diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 0698e3ea..e51aee06 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -61,6 +61,8 @@ on: - xtensa-intel_ace30_ptl_zephyr-elf - xtensa-intel_tgl_adsp_zephyr-elf - xtensa-mtk_mt8195_adsp_zephyr-elf + - xtensa-mtk_mt818x_adsp_zephyr-elf + - xtensa-mtk_mt8196_adsp_zephyr-elf - xtensa-nxp_imx_adsp_zephyr-elf - xtensa-nxp_imx8m_adsp_zephyr-elf - xtensa-nxp_imx8ulp_adsp_zephyr-elf @@ -179,6 +181,8 @@ jobs: xtensa-intel_ace30_ptl_zephyr-elf) build_target_xtensa_intel_ace30_ptl_zephyr_elf="y";; xtensa-intel_tgl_adsp_zephyr-elf) build_target_xtensa_intel_tgl_adsp_zephyr_elf="y";; xtensa-mtk_mt8195_adsp_zephyr-elf) build_target_xtensa_mtk_mt8195_adsp_zephyr_elf="y";; + xtensa-mtk_mt818x_adsp_zephyr-elf) build_target_xtensa_mtk_mt818x_adsp_zephyr_elf="y";; + xtensa-mtk_mt8196_adsp_zephyr-elf) build_target_xtensa_mtk_mt8196_adsp_zephyr_elf="y";; xtensa-nxp_imx_adsp_zephyr-elf) build_target_xtensa_nxp_imx_adsp_zephyr_elf="y";; xtensa-nxp_imx8m_adsp_zephyr-elf) build_target_xtensa_nxp_imx8m_adsp_zephyr_elf="y";; xtensa-nxp_imx8ulp_adsp_zephyr-elf) build_target_xtensa_nxp_imx8ulp_adsp_zephyr_elf="y";; @@ -225,6 +229,8 @@ jobs: build_target_xtensa_intel_ace30_ptl_zephyr_elf="y" build_target_xtensa_intel_tgl_adsp_zephyr_elf="y" build_target_xtensa_mtk_mt8195_adsp_zephyr_elf="y" + build_target_xtensa_mtk_mt818x_adsp_zephyr_elf="y" + build_target_xtensa_mtk_mt8196_adsp_zephyr_elf="y" build_target_xtensa_nxp_imx_adsp_zephyr_elf="y" build_target_xtensa_nxp_imx8m_adsp_zephyr_elf="y" build_target_xtensa_nxp_imx8ulp_adsp_zephyr_elf="y" @@ -311,6 +317,8 @@ jobs: [ "${build_target_xtensa_intel_ace30_ptl_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-intel_ace30_ptl_zephyr-elf",' [ "${build_target_xtensa_intel_tgl_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-intel_tgl_adsp_zephyr-elf",' [ "${build_target_xtensa_mtk_mt8195_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-mtk_mt8195_adsp_zephyr-elf",' + [ "${build_target_xtensa_mtk_mt818x_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-mtk_mt818x_adsp_zephyr-elf",' + [ "${build_target_xtensa_mtk_mt8196_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-mtk_mt8196_adsp_zephyr-elf",' [ "${build_target_xtensa_nxp_imx_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx_adsp_zephyr-elf",' [ "${build_target_xtensa_nxp_imx8m_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx8m_adsp_zephyr-elf",' [ "${build_target_xtensa_nxp_imx8ulp_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx8ulp_adsp_zephyr-elf",' @@ -1582,8 +1590,16 @@ jobs: PLATFORM_ARGS+="-p intel_adsp/cavs25 " ;; xtensa-mtk_mt8195_adsp_zephyr-elf) - # xtensa-mtk_mt8195_adsp_zephyr-elf is untested because no - # upstream user platform is currently available. + # Not merged yet, see Zephyr #81154 + #PLATFORM_ARGS+="-p mt8195/mt8195/adsp" + ;; + xtensa-mtk_mt818x_adsp_zephyr-elf) + # Not merged yet, see Zephyr #81154 + #PLATFORM_ARGS+="-p mt818x/mt818x/adsp" + ;; + xtensa-mtk_mt8196_adsp_zephyr-elf) + # Not merged yet, see Zephyr #81154 + #PLATFORM_ARGS+="-p mt8196/mt8196/adsp" ;; xtensa-nxp_imx_adsp_zephyr-elf) PLATFORM_ARGS+="-p imx8qm_mek/mimx8qm6/adsp " diff --git a/configs/xtensa-mtk_mt818x_adsp_zephyr-elf.config b/configs/xtensa-mtk_mt818x_adsp_zephyr-elf.config new file mode 100644 index 00000000..9f6ffc04 --- /dev/null +++ b/configs/xtensa-mtk_mt818x_adsp_zephyr-elf.config @@ -0,0 +1,10 @@ +CT_CONFIG_VERSION="3" +CT_EXPERIMENTAL=y +CT_OVERLAY_LOCATION="overlays" +CT_OVERLAY_NAME="mtk_mt818x_adsp" +CT_ARCH_XTENSA=y +CT_XTENSA_CUSTOM=y +CT_TARGET_VENDOR="mtk_mt818x_adsp_zephyr" +CT_TARGET_CFLAGS="-ftls-model=local-exec" +CT_CC_GCC_CONFIG_TLS=n +CT_GDB_CROSS_EXTRA_CONFIG_ARRAY="--enable-xtensa-use-target-regnum --disable-xtensa-remote-g-packet" diff --git a/configs/xtensa-mtk_mt8196_adsp_zephyr-elf.config b/configs/xtensa-mtk_mt8196_adsp_zephyr-elf.config new file mode 100644 index 00000000..8807269b --- /dev/null +++ b/configs/xtensa-mtk_mt8196_adsp_zephyr-elf.config @@ -0,0 +1,10 @@ +CT_CONFIG_VERSION="3" +CT_EXPERIMENTAL=y +CT_OVERLAY_LOCATION="overlays" +CT_OVERLAY_NAME="mtk_mt8196_adsp" +CT_ARCH_XTENSA=y +CT_XTENSA_CUSTOM=y +CT_TARGET_VENDOR="mtk_mt8196_adsp_zephyr" +CT_TARGET_CFLAGS="-ftls-model=local-exec" +CT_GDB_CROSS_EXTRA_CONFIG_ARRAY="--enable-xtensa-use-target-regnum --disable-xtensa-remote-g-packet" +CT_CC_GCC_CONFIG_TLS=n diff --git a/overlays/xtensa_mtk_mt818x_adsp/binutils/xtensa-config.h b/overlays/xtensa_mtk_mt818x_adsp/binutils/xtensa-config.h new file mode 100644 index 00000000..84aeb9ea --- /dev/null +++ b/overlays/xtensa_mtk_mt818x_adsp/binutils/xtensa-config.h @@ -0,0 +1,185 @@ +/* Xtensa configuration settings. + Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 + Free Software Foundation, Inc. + Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef XTENSA_CONFIG_H +#define XTENSA_CONFIG_H + +/* The macros defined here match those with the same names in the Xtensa + compile-time HAL (Hardware Abstraction Layer). Please refer to the + Xtensa System Software Reference Manual for documentation of these + macros. */ + +#undef XCHAL_HAVE_BE +#define XCHAL_HAVE_BE 0 + +#undef XCHAL_HAVE_DENSITY +#define XCHAL_HAVE_DENSITY 1 + +#undef XCHAL_HAVE_CONST16 +#define XCHAL_HAVE_CONST16 0 + +#undef XCHAL_HAVE_ABS +#define XCHAL_HAVE_ABS 1 + +#undef XCHAL_HAVE_ADDX +#define XCHAL_HAVE_ADDX 1 + +#undef XCHAL_HAVE_L32R +#define XCHAL_HAVE_L32R 1 + +#undef XSHAL_USE_ABSOLUTE_LITERALS +#define XSHAL_USE_ABSOLUTE_LITERALS 0 + +#undef XSHAL_HAVE_TEXT_SECTION_LITERALS +#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ + +#undef XCHAL_HAVE_MAC16 +#define XCHAL_HAVE_MAC16 0 + +#undef XCHAL_HAVE_MUL16 +#define XCHAL_HAVE_MUL16 1 + +#undef XCHAL_HAVE_MUL32 +#define XCHAL_HAVE_MUL32 1 + +#undef XCHAL_HAVE_MUL32_HIGH +#define XCHAL_HAVE_MUL32_HIGH 0 + +#undef XCHAL_HAVE_DIV32 +#define XCHAL_HAVE_DIV32 1 + +#undef XCHAL_HAVE_NSA +#define XCHAL_HAVE_NSA 1 + +#undef XCHAL_HAVE_MINMAX +#define XCHAL_HAVE_MINMAX 1 + +#undef XCHAL_HAVE_SEXT +#define XCHAL_HAVE_SEXT 1 + +#undef XCHAL_HAVE_LOOPS +#define XCHAL_HAVE_LOOPS 1 + +#undef XCHAL_HAVE_THREADPTR +#define XCHAL_HAVE_THREADPTR 1 + +#undef XCHAL_HAVE_RELEASE_SYNC +#define XCHAL_HAVE_RELEASE_SYNC 1 + +#undef XCHAL_HAVE_S32C1I +#define XCHAL_HAVE_S32C1I 0 + +#undef XCHAL_HAVE_BOOLEANS +#define XCHAL_HAVE_BOOLEANS 1 + +#undef XCHAL_HAVE_FP +#define XCHAL_HAVE_FP 0 + +#undef XCHAL_HAVE_FP_DIV +#define XCHAL_HAVE_FP_DIV 0 + +#undef XCHAL_HAVE_FP_RECIP +#define XCHAL_HAVE_FP_RECIP 0 + +#undef XCHAL_HAVE_FP_SQRT +#define XCHAL_HAVE_FP_SQRT 0 + +#undef XCHAL_HAVE_FP_RSQRT +#define XCHAL_HAVE_FP_RSQRT 0 + +#undef XCHAL_HAVE_DFP_ACCEL +#define XCHAL_HAVE_DFP_ACCEL 0 +/* For backward compatibility */ +#undef XCHAL_HAVE_DFP_accel +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL + +#undef XCHAL_HAVE_WINDOWED +#define XCHAL_HAVE_WINDOWED 1 + +#undef XCHAL_NUM_AREGS +#define XCHAL_NUM_AREGS 64 + +#undef XCHAL_HAVE_WIDE_BRANCHES +#define XCHAL_HAVE_WIDE_BRANCHES 0 + +#undef XCHAL_ICACHE_SIZE +#define XCHAL_ICACHE_SIZE 65536 + +#undef XCHAL_DCACHE_SIZE +#define XCHAL_DCACHE_SIZE 131072 + +#undef XCHAL_ICACHE_LINESIZE +#define XCHAL_ICACHE_LINESIZE 128 + +#undef XCHAL_DCACHE_LINESIZE +#define XCHAL_DCACHE_LINESIZE 128 + +#undef XCHAL_ICACHE_LINEWIDTH +#define XCHAL_ICACHE_LINEWIDTH 7 + +#undef XCHAL_DCACHE_LINEWIDTH +#define XCHAL_DCACHE_LINEWIDTH 7 + +#undef XCHAL_DCACHE_IS_WRITEBACK +#define XCHAL_DCACHE_IS_WRITEBACK 1 + + +#undef XCHAL_HAVE_MMU +#define XCHAL_HAVE_MMU 0 + + +#undef XCHAL_HAVE_DEBUG +#define XCHAL_HAVE_DEBUG 1 + +#undef XCHAL_NUM_IBREAK +#define XCHAL_NUM_IBREAK 2 + +#undef XCHAL_NUM_DBREAK +#define XCHAL_NUM_DBREAK 2 + +#undef XCHAL_DEBUGLEVEL +#define XCHAL_DEBUGLEVEL 5 + + +#undef XCHAL_MAX_INSTRUCTION_SIZE +#define XCHAL_MAX_INSTRUCTION_SIZE 16 + +#undef XCHAL_INST_FETCH_WIDTH +#define XCHAL_INST_FETCH_WIDTH 16 + + +#undef XSHAL_ABI +#undef XTHAL_ABI_WINDOWED +#undef XTHAL_ABI_CALL0 +#define XSHAL_ABI XTHAL_ABI_WINDOWED +#define XTHAL_ABI_WINDOWED 0 +#define XTHAL_ABI_CALL0 1 + + +#undef XCHAL_M_STAGE +#define XCHAL_M_STAGE 3 + +#undef XTENSA_MARCH_LATEST +#define XTENSA_MARCH_LATEST 281050 + +#undef XTENSA_MARCH_EARLIEST +#define XTENSA_MARCH_EARLIEST 281050 + + +#endif /* !XTENSA_CONFIG_H */ diff --git a/overlays/xtensa_mtk_mt818x_adsp/binutils/xtensa-modules.c b/overlays/xtensa_mtk_mt818x_adsp/binutils/xtensa-modules.c new file mode 100644 index 00000000..733bb4b6 --- /dev/null +++ b/overlays/xtensa_mtk_mt818x_adsp/binutils/xtensa-modules.c @@ -0,0 +1,243798 @@ +/* Xtensa configuration-specific ISA information. + + Copyright (c) 2003-2024 Cadence Design Systems, Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "ansidecl.h" +#include +#include "xtensa-isa-internal.h" + + +/* Sysregs. */ + +static xtensa_sysreg_internal sysregs[] = { + { "LBEG", 0, 0 }, + { "LEND", 1, 0 }, + { "LCOUNT", 2, 0 }, + { "BR", 4, 0 }, + { "MMID", 89, 0 }, + { "DDR", 104, 0 }, + { "CONFIGID0", 176, 0 }, + { "CONFIGID1", 208, 0 }, + { "INTERRUPT", 226, 0 }, + { "INTCLEAR", 227, 0 }, + { "CCOUNT", 234, 0 }, + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, + { "CCOMPARE1", 241, 0 }, + { "CCOMPARE2", 242, 0 }, + { "VECBASE", 231, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EPC3", 179, 0 }, + { "EPC4", 180, 0 }, + { "EPC5", 181, 0 }, + { "EPC6", 182, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EXCSAVE3", 211, 0 }, + { "EXCSAVE4", 212, 0 }, + { "EXCSAVE5", 213, 0 }, + { "EXCSAVE6", 214, 0 }, + { "EPS2", 194, 0 }, + { "EPS3", 195, 0 }, + { "EPS4", 196, 0 }, + { "EPS5", 197, 0 }, + { "EPS6", 198, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, + { "WINDOWBASE", 72, 0 }, + { "WINDOWSTART", 73, 0 }, + { "MEMCTL", 97, 0 }, + { "SAR", 3, 0 }, + { "PS", 230, 0 }, + { "MISC0", 244, 0 }, + { "MISC1", 245, 0 }, + { "MISC2", 246, 0 }, + { "MISC3", 247, 0 }, + { "MPUCFG", 92, 0 }, + { "OPMODE", 119, 0 }, + { "INTENABLE", 228, 0 }, + { "DBREAKA0", 144, 0 }, + { "DBREAKC0", 160, 0 }, + { "DBREAKA1", 145, 0 }, + { "DBREAKC1", 161, 0 }, + { "IBREAKA0", 128, 0 }, + { "IBREAKA1", 129, 0 }, + { "IBREAKENABLE", 96, 0 }, + { "ICOUNTLEVEL", 237, 0 }, + { "DEBUGCAUSE", 233, 0 }, + { "PREFCTL", 40, 0 }, + { "CACHEADRDIS", 98, 0 }, + { "MPUENB", 90, 0 }, + { "CPENABLE", 224, 0 }, + { "ATOMCTL", 99, 0 }, + { "ERACCESS", 95, 0 }, + { "THREADPTR", 231, 1 }, + { "AE_OVF_SAR", 240, 1 }, + { "AE_BITHEAD", 241, 1 }, + { "AE_TS_FTS_BU_BP", 242, 1 }, + { "AE_CW_SD_NO", 243, 1 }, + { "AE_CBEGIN0", 246, 1 }, + { "AE_CEND0", 247, 1 }, + { "AE_CBEGIN1", 248, 1 }, + { "AE_CEND1", 249, 1 }, + { "AE_CBEGIN2", 250, 1 }, + { "AE_CEND2", 251, 1 }, + { "AE_ZBIASV8C", -1, 1 }, + { "FCR_FSR", -1, 1 }, + { "EXPSTATE", 230, 1 } +}; + +#define NUM_SYSREGS 78 +#define MAX_SPECIAL_REG 247 +#define MAX_USER_REG 251 + + +/* Processor states. */ + +static xtensa_state_internal states[] = { + { "LCOUNT", 32, 0 }, + { "PC", 32, 0 }, + { "DDR", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "INTERRUPT", 32, 0 }, + { "CCOUNT", 32, 0 }, + { "XTSYNC", 1, 0 }, + { "VECBASE", 22, 0 }, + { "VECBASELOCK", 1, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EPC3", 32, 0 }, + { "EPC4", 32, 0 }, + { "EPC5", 32, 0 }, + { "EPC6", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EXCSAVE3", 32, 0 }, + { "EXCSAVE4", 32, 0 }, + { "EXCSAVE5", 32, 0 }, + { "EXCSAVE6", 32, 0 }, + { "EPS2", 15, 0 }, + { "EPS3", 15, 0 }, + { "EPS4", 15, 0 }, + { "EPS5", 15, 0 }, + { "EPS6", 15, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, + { "PSWOE", 1, 0 }, + { "PSRING", 2, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, + { "WindowBase", 4, 0 }, + { "WindowStart", 16, 0 }, + { "PSCALLINC", 2, 0 }, + { "PSOWB", 4, 0 }, + { "LBEG", 32, 0 }, + { "LEND", 32, 0 }, + { "MEMCTL", 24, 0 }, + { "SAR", 6, 0 }, + { "THREADPTR", 32, 0 }, + { "MISC0", 32, 0 }, + { "MISC1", 32, 0 }, + { "MISC2", 32, 0 }, + { "MISC3", 32, 0 }, + { "MPUNUMENTRIES", 6, 0 }, + { "OPMODEECCFENCE", 2, 0 }, + { "InOCDMode", 1, 0 }, + { "INTENABLE", 32, 0 }, + { "DBREAKA0", 32, 0 }, + { "DBREAKC0", 8, 0 }, + { "DBREAKA1", 32, 0 }, + { "DBREAKC1", 8, 0 }, + { "IBREAKA0", 32, 0 }, + { "IBREAKA1", 32, 0 }, + { "IBREAKENABLE", 2, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, + { "CCOMPARE0", 32, 0 }, + { "CCOMPARE1", 32, 0 }, + { "CCOMPARE2", 32, 0 }, + { "PREFCTL", 13, 0 }, + { "CACHEADRDIS", 8, 0 }, + { "MPUENB", 32, 0 }, + { "CPENABLE", 2, 0 }, + { "ATOMCTL", 9, 0 }, + { "ERI_RAW_INTERLOCK", 1, 0 }, + { "ERACCESS", 16, 0 }, + { "AE_OVERFLOW", 1, XTENSA_STATE_IS_SHARED_OR }, + { "AE_CBEGIN0", 32, 0 }, + { "AE_CEND0", 32, 0 }, + { "AE_CBEGIN1", 32, 0 }, + { "AE_CEND1", 32, 0 }, + { "AE_CBEGIN2", 32, 0 }, + { "AE_CEND2", 32, 0 }, + { "AE_SAR", 14, 0 }, + { "AE_CWRAP", 1, 0 }, + { "AE_BITHEAD", 32, 0 }, + { "AE_BITPTR", 4, 0 }, + { "AE_BITSUSED", 4, 0 }, + { "AE_TABLESIZE", 4, 0 }, + { "AE_FIRST_TS", 4, 0 }, + { "AE_NEXTOFFSET", 27, 0 }, + { "AE_SEARCHDONE", 1, 0 }, + { "AE_ZBIASV8", 8, 0 }, + { "AE_ZBIASC8", 8, 0 }, + { "RoundMode", 2, 0 }, + { "InvalidFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "DivZeroFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "OverflowFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "UnderflowFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "InexactFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } +}; + +#define NUM_STATES 96 + +enum xtensa_state_id { + STATE_LCOUNT, + STATE_PC, + STATE_DDR, + STATE_ICOUNT, + STATE_INTERRUPT, + STATE_CCOUNT, + STATE_XTSYNC, + STATE_VECBASE, + STATE_VECBASELOCK, + STATE_EPC1, + STATE_EPC2, + STATE_EPC3, + STATE_EPC4, + STATE_EPC5, + STATE_EPC6, + STATE_EXCSAVE1, + STATE_EXCSAVE2, + STATE_EXCSAVE3, + STATE_EXCSAVE4, + STATE_EXCSAVE5, + STATE_EXCSAVE6, + STATE_EPS2, + STATE_EPS3, + STATE_EPS4, + STATE_EPS5, + STATE_EPS6, + STATE_EXCCAUSE, + STATE_PSINTLEVEL, + STATE_PSUM, + STATE_PSWOE, + STATE_PSRING, + STATE_PSEXCM, + STATE_DEPC, + STATE_EXCVADDR, + STATE_WindowBase, + STATE_WindowStart, + STATE_PSCALLINC, + STATE_PSOWB, + STATE_LBEG, + STATE_LEND, + STATE_MEMCTL, + STATE_SAR, + STATE_THREADPTR, + STATE_MISC0, + STATE_MISC1, + STATE_MISC2, + STATE_MISC3, + STATE_MPUNUMENTRIES, + STATE_OPMODEECCFENCE, + STATE_InOCDMode, + STATE_INTENABLE, + STATE_DBREAKA0, + STATE_DBREAKC0, + STATE_DBREAKA1, + STATE_DBREAKC1, + STATE_IBREAKA0, + STATE_IBREAKA1, + STATE_IBREAKENABLE, + STATE_ICOUNTLEVEL, + STATE_DEBUGCAUSE, + STATE_DBNUM, + STATE_CCOMPARE0, + STATE_CCOMPARE1, + STATE_CCOMPARE2, + STATE_PREFCTL, + STATE_CACHEADRDIS, + STATE_MPUENB, + STATE_CPENABLE, + STATE_ATOMCTL, + STATE_ERI_RAW_INTERLOCK, + STATE_ERACCESS, + STATE_AE_OVERFLOW, + STATE_AE_CBEGIN0, + STATE_AE_CEND0, + STATE_AE_CBEGIN1, + STATE_AE_CEND1, + STATE_AE_CBEGIN2, + STATE_AE_CEND2, + STATE_AE_SAR, + STATE_AE_CWRAP, + STATE_AE_BITHEAD, + STATE_AE_BITPTR, + STATE_AE_BITSUSED, + STATE_AE_TABLESIZE, + STATE_AE_FIRST_TS, + STATE_AE_NEXTOFFSET, + STATE_AE_SEARCHDONE, + STATE_AE_ZBIASV8, + STATE_AE_ZBIASC8, + STATE_RoundMode, + STATE_InvalidFlag, + STATE_DivZeroFlag, + STATE_OverflowFlag, + STATE_UnderflowFlag, + STATE_InexactFlag, + STATE_EXPSTATE +}; + + +/* Field definitions. */ + +static unsigned +Field_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_n_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_m_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_inst_15_12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_inst_15_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_inst_11_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_inst_11_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_inst16b_15_13_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_ae_fld_inst16b_15_13_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_ae_fld_inst16b_12_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_ae_fld_inst16b_12_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 3) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_19_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 3) >> 18); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x1fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_3_2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_17_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 3) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_22_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 11) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 3) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_21_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe00000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_19_19_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_18_16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_3_3_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 3) >> 15); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_3_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_28_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 3) >> 7); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_28_14_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 3) >> 17); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_14_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 3) >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 3) >> 13); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x1ffffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot0_8_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_8_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_28_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 3) >> 11); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x1fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_1_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_3_1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_9_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_12_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_12_10_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot0_17_10_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 14) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot0_12_6_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_6_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 3) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_27_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000000) | (tie_t << 27); +} + +static unsigned +Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 8) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot0_23_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_18_13_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 3) >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_17_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_9_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_11_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae_slot0_5_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_5_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_4_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_4_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_18_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_19_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot0_19_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_18_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 13) >> 21); + return tie_t; +} + +static void +Field_fld_ae_slot0_18_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_5_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_4_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_19_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_19_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_19_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_23_19_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_14_13_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_17_13_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_13_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_23_22_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_28_24_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 3) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_24_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_14_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_slot0_28_26_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 3) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_26_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c000000) | (tie_t << 26); +} + +static unsigned +Field_fld_ae_slot0_23_17_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot0_23_17_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot0_9_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_9_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_9_9_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_slot0_7_3_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_3_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae_slot0_12_9_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 19) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_9_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_slot0_14_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_14_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 6) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_16_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 6) >> 18); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 6) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_17_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot1_7_4_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot1_25_1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 6) >> 7); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_slot1_0_0_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot1_0_0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot1_3_0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot1_25_9_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 6) >> 15); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_9_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 6) >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x3ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot1_3_3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae_slot1_3_2_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot1_3_2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 6) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_18_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 6) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot1_17_8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot1_17_13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot1_12_8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot1_12_8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot1_17_17_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot1_17_17_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot1_25_22_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 6) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_22_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae_slot1_25_23_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 6) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_23_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae_slot2_28_4_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 3) >> 7); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_4_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot2_3_0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot2_3_0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 3) >> 18); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_15_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x1fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_5_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 3) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_20_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_7_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_fld_ae_slot2_9_1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 22) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot2_9_2_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_2_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot2_28_19_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 3) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_19_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot2_14_0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 17) >> 17); + return tie_t; +} + +static void +Field_fld_ae_slot2_14_0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot2_28_17_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 3) >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_17_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot2_14_5_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot2_14_5_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_slot2_16_15_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot2_16_15_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 3) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_25_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_slot2_14_10_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot2_14_10_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot2_19_15_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot2_28_5_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 3) >> 8); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_5_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0x1fffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_slot2_9_6_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_6_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae_slot2_9_8_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_8_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot2_14_14_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot2_14_14_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_slot3_36_12_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 20) | (insn[0] >> 12); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_12_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 20); +} + +static unsigned +Field_fld_ae_slot3_11_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot3_11_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_30_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 12) >> 12); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot3_9_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 17) >> 17); + return tie_t; +} + +static void +Field_fld_ae_slot3_14_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_25_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae_slot3_19_19_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_19_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_14_10_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_4_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_ae_slot3_24_10_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot3_36_16_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 16) | (insn[0] >> 16); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_16_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 16); +} + +static unsigned +Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_10_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_24_20_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_20_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_9_5_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot3_16_13_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot3_24_19_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 7) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot3_24_19_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x1f80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 10) | (insn[0] >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_22_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xffc00000) | (tie_t << 22); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 10); +} + +static unsigned +Field_fld_ae_slot3_19_17_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_17_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot3_14_13_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot3_14_13_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_15_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot3_14_12_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot3_14_12_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot3_9_1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 22) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot3_9_1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_slot3_9_3_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 22) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot3_9_3_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae_slot3_36_19_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 13) | (insn[0] >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_19_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xfff80000) | (tie_t << 19); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 13); +} + +static unsigned +Field_fld_ae_slot3_19_18_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_18_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 16) | (insn[0] >> 16); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 16); +} + +static unsigned +Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 13) | (insn[0] >> 19); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xfff80000) | (tie_t << 19); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 13); +} + +static unsigned +Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 15) | (insn[0] >> 17); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xfffe0000) | (tie_t << 17); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 15); +} + +static unsigned +Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 11) | (insn[0] >> 21); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffe00000) | (tie_t << 21); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 11); +} + +static unsigned +Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_15_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 5) | (insn[0] >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 5); +} + +static unsigned +Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 14); +} + +static unsigned +Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae2_slot0_12_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_ae2_slot0_12_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_12_2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_ae2_slot0_12_2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae2_slot0_14_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_fld_ae2_slot0_14_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 8) | (insn[0] >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xff000000) | (tie_t << 24); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 8); +} + +static unsigned +Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_15_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae2_slot0_40_26_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 6) | (insn[0] >> 26); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_26_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 6); +} + +static unsigned +Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + return tie_t; +} + +static void +Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae2_slot0_18_17_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_18_17_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 9) | (insn[0] >> 23); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xff800000) | (tie_t << 23); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 9); +} + +static unsigned +Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 20) | (insn[0] >> 12); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 20); +} + +static unsigned +Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot1_11_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot1_11_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 16) | (insn[0] >> 16); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 16); +} + +static unsigned +Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot1_36_17_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 15) | (insn[0] >> 17); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_17_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffe0000) | (tie_t << 17); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 15); +} + +static unsigned +Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot1_3_3_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot1_3_3_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 18); +} + +static unsigned +Field_fld_ae2_slot1_3_2_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot1_3_2_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot1_36_18_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_18_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 14); +} + +static unsigned +Field_fld_ae2_slot1_36_22_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 10) | (insn[0] >> 22); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_22_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xffc00000) | (tie_t << 22); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 10); +} + +static unsigned +Field_fld_ae2_slot1_36_23_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 9) | (insn[0] >> 23); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_23_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xff800000) | (tie_t << 23); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 9); +} + +static unsigned +Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 14); +} + +static unsigned +Field_fld_ae2_slot2_17_0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_fld_ae2_slot2_17_0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 7) >> 12); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0x1ffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 7) >> 22); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 14) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + return tie_t; +} + +static void +Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot2_42_26_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 6) | (insn[0] >> 26); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_26_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 6); +} + +static unsigned +Field_fld_ae2_slot2_42_28_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 4) | (insn[0] >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_28_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xf0000000) | (tie_t << 28); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 4); +} + +static unsigned +Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 7) >> 16); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x1fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 12) >> 21); + return tie_t; +} + +static void +Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 15) | (insn[0] >> 17); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xfffe0000) | (tie_t << 17); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 15); +} + +static unsigned +Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 20) | (insn[0] >> 12); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 20); +} + +static unsigned +Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 14); +} + +static unsigned +Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 24) | (insn[0] >> 8); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff00) | (tie_t << 8); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 24); +} + +static unsigned +Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae3_slot0_32_16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 16) | (insn[0] >> 16); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 16); +} + +static unsigned +Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 21) | (insn[0] >> 11); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xfffff800) | (tie_t << 11); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 21); +} + +static unsigned +Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 19) | (insn[0] >> 13); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffffe000) | (tie_t << 13); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 19); +} + +static unsigned +Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 5) | (insn[0] >> 27); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 5); +} + +static unsigned +Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae3_slot0_7_2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_ae3_slot0_7_2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 18); +} + +static unsigned +Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_9_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ae3_slot0_9_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae3_slot1_23_17_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_17_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot1_23_0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot1_23_11_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 8) >> 19); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_11_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 8) >> 21); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 8) >> 23); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae3_slot1_23_19_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_19_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae3_slot1_3_1_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae3_slot1_3_1_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae3_slot1_23_9_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_9_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 2) >> 18); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 2) >> 14); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 2) >> 20); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 2) >> 7); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae5_slot0_29_17_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 2) >> 19); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_17_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x3ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 2) >> 10); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x3fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 2) >> 15); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 2) >> 29); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000000) | (tie_t << 27); +} + +static unsigned +Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 2) >> 17); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x3fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2) | (tie_t << 1); +} + +static unsigned +Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae5_slot0_29_6_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 2) >> 8); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_6_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0x3fffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 19) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae5_slot0_29_19_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 2) >> 21); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_19_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x3ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae5_slot0_7_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae5_slot0_7_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae5_slot0_12_6_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_fld_ae5_slot0_12_6_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae5_slot1_1_0_Slot_ae5_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot1_1_0_Slot_ae5_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot2_24_0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 7) >> 7); + return tie_t; +} + +static void +Field_fld_ae5_slot2_24_0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae5_slot2_14_5_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_ae5_slot2_14_5_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae5_slot2_9_7_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_fld_ae5_slot2_9_7_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 7) >> 24); + return tie_t; +} + +static void +Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 7) >> 22); + return tie_t; +} + +static void +Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot0_29_5_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 2) >> 7); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_5_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 2) >> 17); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x3fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 2) >> 20); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae6_slot0_7_4_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae6_slot0_7_4_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 2) >> 12); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0x3ffffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 2) >> 15); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 2) >> 16); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x3fffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 4) >> 16); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae6_slot1_27_3_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 4) >> 7); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_3_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae6_slot1_2_0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae6_slot1_2_0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 4) >> 19); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 4) >> 24); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 4) >> 10); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xfffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae6_slot1_9_5_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot1_9_5_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae6_slot1_27_21_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 4) >> 25); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_21_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe00000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae6_slot2_24_0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 7) >> 7); + return tie_t; +} + +static void +Field_fld_ae6_slot2_24_0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 7) >> 22); + return tie_t; +} + +static void +Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 7) >> 21); + return tie_t; +} + +static void +Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot2_24_10_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_ae6_slot2_24_10_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_fld_ae6_slot2_24_20_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot2_24_20_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae6_slot3_37_13_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | (insn[1] & 0x3f); + tie_t = (tie_t << 19) | (insn[0] >> 13); + return tie_t; +} + +static void +Field_fld_ae6_slot3_37_13_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffe000) | (tie_t << 13); + insn[1] = (insn[1] & ~0x3f) | (tie_t >> 19); +} + +static unsigned +Field_fld_ae6_slot3_12_0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_ae6_slot3_12_0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | (insn[1] & 0x3f); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x3f) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | (insn[1] & 0x3f); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x3f) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae6_slot3_24_20_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot3_24_20_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae6_slot3_14_0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 17) >> 17); + return tie_t; +} + +static void +Field_fld_ae6_slot3_14_0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | (insn[1] & 0x3f); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x3f) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_ae7_slot0_23_0_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_ae7_slot0_23_0_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 8) >> 21); + return tie_t; +} + +static void +Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + return tie_t; +} + +static void +Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot0_12_6_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot0_12_6_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot1_23_0_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_ae7_slot1_23_0_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 8) >> 21); + return tie_t; +} + +static void +Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + return tie_t; +} + +static void +Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot1_12_6_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot1_12_6_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot2_36_12_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 20) | (insn[0] >> 12); + return tie_t; +} + +static void +Field_fld_ae7_slot2_36_12_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 20); +} + +static unsigned +Field_fld_ae7_slot2_11_0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); + return tie_t; +} + +static void +Field_fld_ae7_slot2_11_0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae7_slot2_14_10_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae7_slot2_14_10_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae7_slot3_35_11_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | (insn[1] & 0xf); + tie_t = (tie_t << 21) | (insn[0] >> 11); + return tie_t; +} + +static void +Field_fld_ae7_slot3_35_11_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffff800) | (tie_t << 11); + insn[1] = (insn[1] & ~0xf) | (tie_t >> 21); +} + +static unsigned +Field_fld_ae7_slot3_10_0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 21) >> 21); + return tie_t; +} + +static void +Field_fld_ae7_slot3_10_0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | (insn[1] & 0xf); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0xf) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae7_slot3_24_10_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_ae7_slot3_24_10_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae7_slot3_4_0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae7_slot3_4_0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | (insn[1] & 0xf); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0xf) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | (insn[1] & 0xf); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0xf) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 0) >> 18); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 0) >> 12); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 0) >> 8); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot0_13_13_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_fld_ae8_slot0_13_13_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 0) >> 20); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae8_slot0_31_7_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 0) >> 7); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_7_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae8_slot0_6_0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ae8_slot0_6_0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot0_31_9_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 0) >> 9); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_9_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xfffffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 0) >> 15); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae8_slot0_7_5_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ae8_slot0_7_5_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 18) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 14) >> 18); + return tie_t; +} + +static void +Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 0) >> 19); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae8_slot0_8_0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_ae8_slot0_8_0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot0_17_8_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot0_17_8_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae8_slot0_31_21_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 0) >> 21); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_21_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe00000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae8_slot0_31_22_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 0) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_22_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae8_slot0_31_23_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 0) >> 23); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_23_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + return tie_t; +} + +static void +Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 2) >> 14); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae8_slot1_17_15_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae8_slot1_17_15_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae8_slot1_29_5_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 2) >> 7); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_5_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae8_slot1_4_0_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae8_slot1_4_0_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 2) >> 10); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x3fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot1_29_9_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 2) >> 11); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_9_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x3ffffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 2) >> 15); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 2) >> 20); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae8_slot1_29_22_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 2) >> 24); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_22_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae8_slot1_29_23_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 2) >> 25); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_23_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[1] << 5) >> 7); + return tie_t; +} + +static void +Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[1] = (insn[1] & ~0x7fffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae8_slot2_33_9_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 23) | (insn[0] >> 9); + return tie_t; +} + +static void +Field_fld_ae8_slot2_33_9_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffffe00) | (tie_t << 9); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 23); +} + +static unsigned +Field_fld_ae8_slot2_8_0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_ae8_slot2_8_0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot2_33_25_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae8_slot2_33_25_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae8_slot2_19_15_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae8_slot2_19_15_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[1] << 5) >> 23); + return tie_t; +} + +static void +Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[1] = (insn[1] & ~0x7fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[1] << 5) >> 13); + return tie_t; +} + +static void +Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[1] = (insn[1] & ~0x7ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[1] << 5) >> 8); + return tie_t; +} + +static void +Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[1] = (insn[1] & ~0x7fffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[1] << 19) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[1] = (insn[1] & ~0x1ff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 4) >> 20); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 4) >> 16); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 4) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 4) >> 12); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot0_27_17_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 4) >> 21); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_17_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 4) >> 24); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae9_slot0_27_3_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 4) >> 7); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_3_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae9_slot0_2_0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae9_slot0_2_0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 4) >> 14); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 4) >> 17); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae9_slot0_7_6_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae9_slot0_7_6_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 14) >> 18); + return tie_t; +} + +static void +Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae9_slot0_27_19_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 4) >> 23); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_19_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 19) >> 24); + return tie_t; +} + +static void +Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 23) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae9_slot0_27_22_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 4) >> 26); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_22_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 4) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 5) >> 21); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae9_slot1_26_17_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 5) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_17_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae9_slot1_26_2_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 5) >> 7); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_2_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae9_slot1_1_0_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae9_slot1_1_0_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 5) >> 13); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x7ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot1_26_9_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 5) >> 14); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_9_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x7fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 5) >> 18); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x7ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae9_slot1_3_2_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae9_slot1_3_2_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 5) >> 23); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae9_slot1_26_22_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 5) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_22_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae9_slot1_26_23_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_23_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae9_slot2_33_9_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 23) | (insn[0] >> 9); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_9_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffffe00) | (tie_t << 9); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 23); +} + +static unsigned +Field_fld_ae9_slot2_8_0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_ae9_slot2_8_0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 6) | (insn[0] >> 26); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 6); +} + +static unsigned +Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 4) | (insn[0] >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xf0000000) | (tie_t << 28); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 4); +} + +static unsigned +Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 18); +} + +static unsigned +Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 7) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 7) >> 21); + return tie_t; +} + +static void +Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae9_slot3_31_7_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 0) >> 7); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_7_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae9_slot3_6_0_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ae9_slot3_6_0_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 0) >> 25); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae9_slot3_4_4_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot3_4_4_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 0) >> 15); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 0) >> 20); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 0) >> 26); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); +} + +static unsigned +Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 0) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000000) | (tie_t << 28); +} + +static unsigned +Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 0) >> 14); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); +} + +static unsigned +Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 7) >> 23); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 7) >> 19); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 7) >> 25); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 7) >> 15); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot0_24_17_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 7) >> 24); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_17_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae10_slot0_24_0_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 7) >> 7); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_0_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 7) >> 20); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae10_slot0_7_6_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot0_7_6_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 14) >> 18); + return tie_t; +} + +static void +Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae10_slot0_17_8_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot0_17_8_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 6) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 6) >> 18); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae10_slot1_25_17_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 6) >> 23); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_17_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae10_slot1_25_1_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 6) >> 7); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_1_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae10_slot1_0_0_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot1_0_0_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot1_25_9_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 6) >> 15); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_9_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 6) >> 19); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x3ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae10_slot1_3_2_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot1_3_2_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 6) >> 24); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 6) >> 26); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae10_slot1_25_22_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 6) >> 28); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_22_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae10_slot1_25_23_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 6) >> 29); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_23_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae10_slot2_34_10_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 22) | (insn[0] >> 10); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_10_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffffc00) | (tie_t << 10); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 22); +} + +static unsigned +Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 1) | (insn[0] >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x80000000) | (tie_t << 31); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 1); +} + +static unsigned +Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[1] << 29) >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[1] = (insn[1] & ~0x6) | (tie_t << 1); +} + +static unsigned +Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 18); +} + +static unsigned +Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae10_slot3_34_10_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 22) | (insn[0] >> 10); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_10_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffffc00) | (tie_t << 10); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 22); +} + +static unsigned +Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae10_slot3_4_4_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot3_4_4_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 1) | (insn[0] >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x80000000) | (tie_t << 31); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 1); +} + +static unsigned +Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[1] << 29) >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[1] = (insn[1] & ~0x6) | (tie_t << 1); +} + +static unsigned +Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 18); +} + +static unsigned +Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); +} + +static unsigned +Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 9) >> 21); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 9) >> 17); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot0_22_17_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 9) >> 26); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_17_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae4_slot0_22_20_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_20_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae4_slot0_22_0_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 9) >> 9); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_0_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot0_3_1_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot0_3_1_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 9) >> 22); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 9) >> 15); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x7fffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 9) >> 21); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae4_slot1_22_17_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 9) >> 26); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_17_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae4_slot1_22_0_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 9) >> 9); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_0_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 9) >> 17); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot1_3_1_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot1_3_1_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 9) >> 22); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae4_slot2_23_0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_ae4_slot2_23_0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 8) >> 23); + return tie_t; +} + +static void +Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae4_slot2_23_17_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_ae4_slot2_23_17_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae4_slot2_4_0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot2_4_0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae4_slot3_27_3_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 4) >> 7); + return tie_t; +} + +static void +Field_fld_ae4_slot3_27_3_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae4_slot3_2_0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot3_2_0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae4_slot3_19_19_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_fld_ae4_slot3_19_19_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae4_slot3_19_5_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 12) >> 17); + return tie_t; +} + +static void +Field_fld_ae4_slot3_19_5_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae4_slot3_27_20_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 4) >> 24); + return tie_t; +} + +static void +Field_fld_ae4_slot3_27_20_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae4_slot3_14_10_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot3_14_10_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae4_slot4_22_0_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 9) >> 9); + return tie_t; +} + +static void +Field_fld_ae4_slot4_22_0_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 9) >> 24); + return tie_t; +} + +static void +Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_t_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_t_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 23) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e0) | (tie_t << 5); +} + +static unsigned +Field_t_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bbi_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_bbi_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_bbi_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 24) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_imm8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_imm8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_imm8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29); + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_imm8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); + tie_t = (val << 24) >> 29; + insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14); +} + +static unsigned +Field_imm8_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_imm8_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_imm8_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_imm8_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_imm8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_s_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_s8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_s8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_s8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_s8_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_s8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_s8_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_s8_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_imms8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_imms8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 22) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); + tie_t = (val << 21) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 20) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_imm12b_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_imm12b_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 20) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_imm12b_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_imm12b_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 10) | ((insn[0] << 18) >> 22); + return tie_t; +} + +static void +Field_imm12b_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0) | (tie_t << 4); + tie_t = (val << 20) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_imm12b_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 11) | ((insn[0] << 13) >> 21); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 17) >> 21; + insn[0] = (insn[0] & ~0x7ff00) | (tie_t << 8); + tie_t = (val << 16) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_imm16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 14) | ((insn[0] << 14) >> 18); + return tie_t; +} + +static void +Field_imm16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0) | (tie_t << 4); + tie_t = (val << 16) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_imm16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_imm16_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_imm16_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_imm16_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_offset_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 17) | ((insn[0] << 15) >> 15); + return tie_t; +} + +static void +Field_offset_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff) | (tie_t << 0); + tie_t = (val << 14) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_offset_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 17) | ((insn[0] << 15) >> 15); + return tie_t; +} + +static void +Field_offset_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff) | (tie_t << 0); + tie_t = (val << 14) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_offset_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_op2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_op2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_op2_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_op2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_op2_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_op2_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_op2_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_op2_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_r_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_disp_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_r_disp_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_r_3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r_3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_sae_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_sae_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_sae_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sae_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_sae_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_sal_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_sal_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_sal_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sal_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_sargt_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_sargt_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sargt_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_sargt_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_sas_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sas_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_sas_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_sas_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_sas_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_sas_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_sas_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_sas_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_sas_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_sas_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_sas_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_t2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_t2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_t2_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_t2_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); +} + +static unsigned +Field_s2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_r2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_r2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_r2_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_r2_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_t4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_t4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_t4_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_t4_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); +} + +static unsigned +Field_s4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_s4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_s4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_s4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_s4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_s4_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_s4_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_s4_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_s4_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_s4_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_r4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_r4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_r4_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_r4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_r4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_r4_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_r4_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_r4_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_t8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_r8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_xt_wbr15_imm_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_xt_wbr15_imm_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_xt_wbr15_imm_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae_sem_arithmetic_art_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_art_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_art_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_art_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 6) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 6) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 16) >> 26); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_br4t_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_br4t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpcnv_arr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_arr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_hpcnv_arr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_arr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_hpcnv_art_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_art_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_hpcnv_art_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_art_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 23) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_vu_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_vu_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_vu_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_vu_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_vu_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_vu_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_vu_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_vu_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_rng_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_rng_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_a_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_a_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_shift_a0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_a0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_a0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_shift_a0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_a0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_shift_d1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_d1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_da_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_da_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_da_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_da_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_shift_da_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_da_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_i32_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_shift_i32_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i32_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_i32_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 7) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i32_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_shift_i32_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i32_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_shift_i32_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i32_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_shift_i64_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i64_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_i64_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i64_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_sem_shift_i64_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i64_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_shift_i64_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i64_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_shift_i64_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i64_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_shift_imm32_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_imm32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_imm32_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_imm32_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_imm8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_imm8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_sd_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_sd_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_sd_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_sd_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_sd_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_sd_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_shift_sd_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_sd_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_shift_sd_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_sd_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_arr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_arr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_arr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_arr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_arr_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_arr_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_art_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_art_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_art_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_art_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_art_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_art_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vr_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vr_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vt_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vt_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_slot0_1_1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_1_1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 23) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_ds_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_ds_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_ds_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_ds_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_ds_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_ds_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 1) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000000) | (tie_t << 30); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 1) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000000) | (tie_t << 30); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_imm_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_imm_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_multiply_d1_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d1_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_d1_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d1_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_multiply_d1_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d1_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_multiply_d1_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d1_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d3_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d3_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_multiply_d3_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d3_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d3_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d3_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_multiply_d3_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d3_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_rng_d_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_d_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_shift_e_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_e_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_i8_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i8_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vp_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vp_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vp_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vp_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vp_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vp_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vq_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vq_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vq_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vq_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vq_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vq_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_sb_loads_stores_iba2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sb_loads_stores_iba2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_ardecnorm16_ar_u_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_ardecnorm16_ar_u_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_lb_db_ops_ar_u_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_db_ops_ar_u_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_lb_db_ops_iba_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_db_ops_iba_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_rng_a_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_a_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_rng_art_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_art_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_rng_i2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_i2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_rng_imm2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_imm2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae_sem_mul_nn_c0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_c0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_mul_nn_c1_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_c1_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae_sem_mul_nn_c2_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_c2_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_mul_nn_c3_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_c3_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_nn_q0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_q0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_mul_nn_q1_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_q1_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_nn_q2_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_q2_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_mul_nn_q3_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_q3_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_mul_nn_v0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_v0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_mul_nn_v1_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_v1_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae_sem_mul_nn_v2_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_v2_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_mul_nn_v3_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_v3_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_hpfma_vp_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vp_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vu_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vu_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_vu_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vu_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vu_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vu_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vu_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vu_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vu_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vu_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vq_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vq_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_vq_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vq_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_inst_12_12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_inst_12_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_inst_12_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_inst_12_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_inst_13_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_fld_inst_13_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); +} + +static unsigned +Field_fld_inst_19_17_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_fld_inst_19_17_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_inst_19_18_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_inst_19_18_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_inst_23_12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_fld_inst_23_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_fld_inst_23_16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_fld_inst_23_16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_inst_4_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_inst_4_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_inst_5_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_inst_5_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_inst_7_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_inst_7_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_inst_7_6_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_inst_7_6_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_inst_7_7_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_inst_7_7_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_inst_9_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_inst_9_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) +{ + /* Do nothing. */ +} + +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 4; +} + +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 8; +} + +static unsigned +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 12; +} + +static unsigned +Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +enum xtensa_field_id { + FIELD_t, + FIELD_bbi4, + FIELD_bbi, + FIELD_imm12, + FIELD_imm8, + FIELD_s, + FIELD_s8, + FIELD_imms8, + FIELD_imm12b, + FIELD_imm16, + FIELD_m, + FIELD_n, + FIELD_offset, + FIELD_op0, + FIELD_op1, + FIELD_op2, + FIELD_r, + FIELD_r_disp, + FIELD_r_3, + FIELD_sa4, + FIELD_sae4, + FIELD_sae, + FIELD_sal, + FIELD_sargt, + FIELD_sas4, + FIELD_sas, + FIELD_sr, + FIELD_st, + FIELD_thi3, + FIELD_imm4, + FIELD_mn, + FIELD_i, + FIELD_imm6lo, + FIELD_imm6hi, + FIELD_imm7lo, + FIELD_imm7hi, + FIELD_z, + FIELD_imm6, + FIELD_imm7, + FIELD_t2, + FIELD_s2, + FIELD_r2, + FIELD_t4, + FIELD_s4, + FIELD_r4, + FIELD_t8, + FIELD_r8, + FIELD_xt_wbr15_imm, + FIELD_xt_wbr18_imm, + FIELD_ae_fld_Inst16b_12, + FIELD_ae_fld_Inst16b_15_13, + FIELD_fld_ae_sem_arithmetic_art, + FIELD_fld_ae_sem_arithmetic_ds, + FIELD_fld_ae_sem_arithmetic_v, + FIELD_fld_ae_sem_arithmetic_v0, + FIELD_fld_ae_sem_arithmetic_v1, + FIELD_fld_ae_sem_arithmetic_va, + FIELD_fld_ae_sem_arithmetic_vs, + FIELD_fld_ae_sem_dr_to_ar_a, + FIELD_fld_ae_sem_dr_to_ar_ab, + FIELD_fld_ae_sem_dr_to_ar_ai, + FIELD_fld_ae_sem_dr_to_ar_aoe, + FIELD_fld_ae_sem_dr_to_ar_d, + FIELD_fld_ae_sem_dr_to_ar_d0, + FIELD_fld_ae_sem_dr_to_ar_d1, + FIELD_fld_ae_sem_dr_to_ar_imm8, + FIELD_fld_ae_sem_dr_to_ar_v0, + FIELD_fld_ae_sem_dr_to_ar_vr, + FIELD_fld_ae_sem_dr_to_dr_arr, + FIELD_fld_ae_sem_dr_to_dr_bt, + FIELD_fld_ae_sem_dr_to_dr_ds, + FIELD_fld_ae_sem_dr_to_dr_imm2, + FIELD_fld_ae_sem_dr_to_dr_immed, + FIELD_fld_ae_sem_dr_to_dr_movi_imm, + FIELD_fld_ae_sem_dr_to_dr_v, + FIELD_fld_ae_sem_dr_to_dr_v0, + FIELD_fld_ae_sem_dr_to_dr_v1, + FIELD_fld_ae_sem_hpcmp_br4t, + FIELD_fld_ae_sem_hpcmp_vr, + FIELD_fld_ae_sem_hpcmp_vs, + FIELD_fld_ae_sem_hpcnv_arr, + FIELD_fld_ae_sem_hpcnv_art, + FIELD_fld_ae_sem_hpcnv_i_imm4, + FIELD_fld_ae_sem_hpcnv_vr, + FIELD_fld_ae_sem_hpcnv_vt, + FIELD_fld_ae_sem_hprminmaxnum_vr, + FIELD_fld_ae_sem_hprminmaxnum_vt, + FIELD_fld_ae_sem_lb_ops_iba, + FIELD_fld_ae_sem_loads_stores_a, + FIELD_fld_ae_sem_loads_stores_a_0, + FIELD_fld_ae_sem_loads_stores_av, + FIELD_fld_ae_sem_loads_stores_av1, + FIELD_fld_ae_sem_loads_stores_end, + FIELD_fld_ae_sem_loads_stores_i128, + FIELD_fld_ae_sem_loads_stores_i16, + FIELD_fld_ae_sem_loads_stores_i3, + FIELD_fld_ae_sem_loads_stores_i32, + FIELD_fld_ae_sem_loads_stores_i32pos, + FIELD_fld_ae_sem_loads_stores_i64, + FIELD_fld_ae_sem_loads_stores_i64half, + FIELD_fld_ae_sem_loads_stores_i64neg, + FIELD_fld_ae_sem_loads_stores_i64pos, + FIELD_fld_ae_sem_loads_stores_i64x2, + FIELD_fld_ae_sem_loads_stores_i8, + FIELD_fld_ae_sem_loads_stores_imm2, + FIELD_fld_ae_sem_loads_stores_su, + FIELD_fld_ae_sem_loads_stores_uu, + FIELD_fld_ae_sem_loads_stores_v, + FIELD_fld_ae_sem_loads_stores_v1, + FIELD_fld_ae_sem_loads_stores_vu, + FIELD_fld_ae_sem_loads_stores_x, + FIELD_fld_ae_sem_pks_d, + FIELD_fld_ae_sem_pks_pos, + FIELD_fld_ae_sem_pks_s, + FIELD_fld_ae_sem_rng_v0, + FIELD_fld_ae_sem_rng_v1, + FIELD_fld_ae_sem_sb_loads_stores_iba, + FIELD_fld_ae_sem_shift_a, + FIELD_fld_ae_sem_shift_a0, + FIELD_fld_ae_sem_shift_d, + FIELD_fld_ae_sem_shift_d0, + FIELD_fld_ae_sem_shift_d1, + FIELD_fld_ae_sem_shift_da, + FIELD_fld_ae_sem_shift_i16, + FIELD_fld_ae_sem_shift_i32, + FIELD_fld_ae_sem_shift_i64, + FIELD_fld_ae_sem_shift_imm32, + FIELD_fld_ae_sem_shift_imm8, + FIELD_fld_ae_sem_shift_sd, + FIELD_fld_ae_sem_sp32cvt_arr, + FIELD_fld_ae_sem_sp32cvt_art, + FIELD_fld_ae_sem_sp32cvt_i_imm5, + FIELD_fld_ae_sem_sp32cvt_vr, + FIELD_fld_ae_sem_sp32cvt_vt, + FIELD_fld_ae_sem_spmisc_brt, + FIELD_fld_ae_sem_spmisc_vr, + FIELD_fld_ae_sem_spmisc_vs, + FIELD_fld_ae_slot0_11_10, + FIELD_fld_ae_slot0_11_11, + FIELD_fld_ae_slot0_11_8, + FIELD_fld_ae_slot0_11_9, + FIELD_fld_ae_slot0_12_0, + FIELD_fld_ae_slot0_12_10, + FIELD_fld_ae_slot0_12_12, + FIELD_fld_ae_slot0_12_2, + FIELD_fld_ae_slot0_12_6, + FIELD_fld_ae_slot0_12_8, + FIELD_fld_ae_slot0_12_9, + FIELD_fld_ae_slot0_14_12, + FIELD_fld_ae_slot0_14_13, + FIELD_fld_ae_slot0_17_10, + FIELD_fld_ae_slot0_17_12, + FIELD_fld_ae_slot0_17_13, + FIELD_fld_ae_slot0_17_14, + FIELD_fld_ae_slot0_17_15, + FIELD_fld_ae_slot0_17_16, + FIELD_fld_ae_slot0_17_17, + FIELD_fld_ae_slot0_17_8, + FIELD_fld_ae_slot0_18_13, + FIELD_fld_ae_slot0_18_15, + FIELD_fld_ae_slot0_18_16, + FIELD_fld_ae_slot0_18_8, + FIELD_fld_ae_slot0_19_12, + FIELD_fld_ae_slot0_19_15, + FIELD_fld_ae_slot0_19_19, + FIELD_fld_ae_slot0_19_8, + FIELD_fld_ae_slot0_1_0, + FIELD_fld_ae_slot0_1_1, + FIELD_fld_ae_slot0_20_16, + FIELD_fld_ae_slot0_20_20, + FIELD_fld_ae_slot0_23_15, + FIELD_fld_ae_slot0_23_17, + FIELD_fld_ae_slot0_23_19, + FIELD_fld_ae_slot0_23_22, + FIELD_fld_ae_slot0_28_10, + FIELD_fld_ae_slot0_28_12, + FIELD_fld_ae_slot0_28_14, + FIELD_fld_ae_slot0_28_15, + FIELD_fld_ae_slot0_28_16, + FIELD_fld_ae_slot0_28_17, + FIELD_fld_ae_slot0_28_19, + FIELD_fld_ae_slot0_28_21, + FIELD_fld_ae_slot0_28_22, + FIELD_fld_ae_slot0_28_24, + FIELD_fld_ae_slot0_28_26, + FIELD_fld_ae_slot0_28_27, + FIELD_fld_ae_slot0_28_4, + FIELD_fld_ae_slot0_28_8, + FIELD_fld_ae_slot0_3_0, + FIELD_fld_ae_slot0_3_1, + FIELD_fld_ae_slot0_3_2, + FIELD_fld_ae_slot0_3_3, + FIELD_fld_ae_slot0_4_0, + FIELD_fld_ae_slot0_4_4, + FIELD_fld_ae_slot0_5_0, + FIELD_fld_ae_slot0_5_4, + FIELD_fld_ae_slot0_7_0, + FIELD_fld_ae_slot0_7_2, + FIELD_fld_ae_slot0_7_3, + FIELD_fld_ae_slot0_7_4, + FIELD_fld_ae_slot0_8_8, + FIELD_fld_ae_slot0_9_4, + FIELD_fld_ae_slot0_9_8, + FIELD_fld_ae_slot0_9_9, + FIELD_fld_ae_slot1_0_0, + FIELD_fld_ae_slot1_12_8, + FIELD_fld_ae_slot1_17_13, + FIELD_fld_ae_slot1_17_17, + FIELD_fld_ae_slot1_17_8, + FIELD_fld_ae_slot1_25_1, + FIELD_fld_ae_slot1_25_12, + FIELD_fld_ae_slot1_25_13, + FIELD_fld_ae_slot1_25_16, + FIELD_fld_ae_slot1_25_17, + FIELD_fld_ae_slot1_25_18, + FIELD_fld_ae_slot1_25_20, + FIELD_fld_ae_slot1_25_22, + FIELD_fld_ae_slot1_25_23, + FIELD_fld_ae_slot1_25_8, + FIELD_fld_ae_slot1_25_9, + FIELD_fld_ae_slot1_3_0, + FIELD_fld_ae_slot1_3_2, + FIELD_fld_ae_slot1_3_3, + FIELD_fld_ae_slot1_7_4, + FIELD_fld_ae_sem_arithmetic_e, + FIELD_fld_ae_sem_arithmetic_ep, + FIELD_fld_ae_sem_arithmetic_ep1, + FIELD_fld_ae_sem_dr_to_ar_ei, + FIELD_fld_ae_sem_dr_to_ar_eo, + FIELD_fld_ae_sem_dr_to_dr_immed_N, + FIELD_fld_ae_sem_fpmov_i_imm4, + FIELD_fld_ae_sem_fpmov_vr, + FIELD_fld_ae_sem_fpmov_vs, + FIELD_fld_ae_sem_fpmov_vt, + FIELD_fld_ae_sem_fpmov_vu, + FIELD_fld_ae_sem_hpcmp_vt, + FIELD_fld_ae_sem_hpcnv_vs, + FIELD_fld_ae_sem_hpfma_vr, + FIELD_fld_ae_sem_hpfma_vs, + FIELD_fld_ae_sem_hpfma_vt, + FIELD_fld_ae_sem_movfpstate_v, + FIELD_fld_ae_sem_multiply_acc_ep, + FIELD_fld_ae_sem_multiply_d0, + FIELD_fld_ae_sem_multiply_d2, + FIELD_fld_ae_sem_multiply_q0, + FIELD_fld_ae_sem_multiply_q1, + FIELD_fld_ae_sem_reduction_sort_ds, + FIELD_fld_ae_sem_reduction_sort_v, + FIELD_fld_ae_sem_reduction_sort_v0, + FIELD_fld_ae_sem_select_isel, + FIELD_fld_ae_sem_select_ss, + FIELD_fld_ae_sem_select_vr, + FIELD_fld_ae_sem_select_vs, + FIELD_fld_ae_sem_select_vt, + FIELD_fld_ae_sem_select_vu, + FIELD_fld_ae_sem_spaddsub_vr, + FIELD_fld_ae_sem_spaddsub_vs, + FIELD_fld_ae_sem_spaddsub_vt, + FIELD_fld_ae_sem_spaddsub_vu, + FIELD_fld_ae_sem_spfma_i_imm1, + FIELD_fld_ae_sem_spfma_i_imm3, + FIELD_fld_ae_sem_spfma_vp, + FIELD_fld_ae_sem_spfma_vr, + FIELD_fld_ae_sem_spfma_vs, + FIELD_fld_ae_sem_spfma_vt, + FIELD_fld_ae_sem_spmisc_vsM, + FIELD_fld_ae_sem_spmisc_vt, + FIELD_fld_ae_sem_spmisc_vtM, + FIELD_fld_ae_slot2_14_0, + FIELD_fld_ae_slot2_14_10, + FIELD_fld_ae_slot2_14_14, + FIELD_fld_ae_slot2_14_5, + FIELD_fld_ae_slot2_16_15, + FIELD_fld_ae_slot2_19_15, + FIELD_fld_ae_slot2_28_15, + FIELD_fld_ae_slot2_28_17, + FIELD_fld_ae_slot2_28_19, + FIELD_fld_ae_slot2_28_20, + FIELD_fld_ae_slot2_28_25, + FIELD_fld_ae_slot2_28_4, + FIELD_fld_ae_slot2_28_5, + FIELD_fld_ae_slot2_3_0, + FIELD_fld_ae_slot2_9_0, + FIELD_fld_ae_slot2_9_1, + FIELD_fld_ae_slot2_9_2, + FIELD_fld_ae_slot2_9_5, + FIELD_fld_ae_slot2_9_6, + FIELD_fld_ae_slot2_9_7, + FIELD_fld_ae_slot2_9_8, + FIELD_fld_ae_sem_dr_to_dr_imm, + FIELD_fld_ae_sem_multiply_d1, + FIELD_fld_ae_sem_multiply_d3, + FIELD_fld_ae_sem_rng_d, + FIELD_fld_ae_sem_shift_e, + FIELD_fld_ae_sem_shift_i8, + FIELD_fld_ae_slot3_11_0, + FIELD_fld_ae_slot3_14_0, + FIELD_fld_ae_slot3_14_10, + FIELD_fld_ae_slot3_14_12, + FIELD_fld_ae_slot3_14_13, + FIELD_fld_ae_slot3_16_13, + FIELD_fld_ae_slot3_19_0, + FIELD_fld_ae_slot3_19_10, + FIELD_fld_ae_slot3_19_15, + FIELD_fld_ae_slot3_19_17, + FIELD_fld_ae_slot3_19_18, + FIELD_fld_ae_slot3_19_19, + FIELD_fld_ae_slot3_24_10, + FIELD_fld_ae_slot3_24_19, + FIELD_fld_ae_slot3_24_20, + FIELD_fld_ae_slot3_36_12, + FIELD_fld_ae_slot3_36_16, + FIELD_fld_ae_slot3_36_19, + FIELD_fld_ae_slot3_36_20, + FIELD_fld_ae_slot3_36_22, + FIELD_fld_ae_slot3_36_25, + FIELD_fld_ae_slot3_36_30, + FIELD_fld_ae_slot3_4_0, + FIELD_fld_ae_slot3_9_0, + FIELD_fld_ae_slot3_9_1, + FIELD_fld_ae_slot3_9_3, + FIELD_fld_ae_slot3_9_5, + FIELD_fld_ae2_slot0_0_0, + FIELD_fld_ae2_slot0_11_4, + FIELD_fld_ae2_slot0_11_8, + FIELD_fld_ae2_slot0_11_9, + FIELD_fld_ae2_slot0_12_0, + FIELD_fld_ae2_slot0_12_2, + FIELD_fld_ae2_slot0_12_4, + FIELD_fld_ae2_slot0_12_8, + FIELD_fld_ae2_slot0_14_13, + FIELD_fld_ae2_slot0_14_8, + FIELD_fld_ae2_slot0_15_0, + FIELD_fld_ae2_slot0_15_12, + FIELD_fld_ae2_slot0_15_13, + FIELD_fld_ae2_slot0_15_15, + FIELD_fld_ae2_slot0_15_4, + FIELD_fld_ae2_slot0_15_8, + FIELD_fld_ae2_slot0_17_13, + FIELD_fld_ae2_slot0_17_17, + FIELD_fld_ae2_slot0_18_15, + FIELD_fld_ae2_slot0_18_17, + FIELD_fld_ae2_slot0_18_18, + FIELD_fld_ae2_slot0_1_0, + FIELD_fld_ae2_slot0_23_18, + FIELD_fld_ae2_slot0_23_19, + FIELD_fld_ae2_slot0_3_0, + FIELD_fld_ae2_slot0_40_16, + FIELD_fld_ae2_slot0_40_17, + FIELD_fld_ae2_slot0_40_18, + FIELD_fld_ae2_slot0_40_19, + FIELD_fld_ae2_slot0_40_21, + FIELD_fld_ae2_slot0_40_23, + FIELD_fld_ae2_slot0_40_24, + FIELD_fld_ae2_slot0_40_25, + FIELD_fld_ae2_slot0_40_26, + FIELD_fld_ae2_slot0_40_27, + FIELD_fld_ae2_slot0_7_0, + FIELD_fld_ae2_slot0_7_4, + FIELD_fld_ae2_slot0_7_6, + FIELD_fld_ae2_slot0_7_7, + FIELD_fld_ae2_slot0_8_8, + FIELD_fld_ae2_slot0_9_8, + FIELD_fld_ae2_slot1_0_0, + FIELD_fld_ae2_slot1_11_0, + FIELD_fld_ae2_slot1_11_10, + FIELD_fld_ae2_slot1_11_8, + FIELD_fld_ae2_slot1_14_10, + FIELD_fld_ae2_slot1_14_11, + FIELD_fld_ae2_slot1_14_12, + FIELD_fld_ae2_slot1_14_14, + FIELD_fld_ae2_slot1_14_8, + FIELD_fld_ae2_slot1_36_12, + FIELD_fld_ae2_slot1_36_14, + FIELD_fld_ae2_slot1_36_15, + FIELD_fld_ae2_slot1_36_16, + FIELD_fld_ae2_slot1_36_17, + FIELD_fld_ae2_slot1_36_18, + FIELD_fld_ae2_slot1_36_20, + FIELD_fld_ae2_slot1_36_22, + FIELD_fld_ae2_slot1_36_23, + FIELD_fld_ae2_slot1_3_0, + FIELD_fld_ae2_slot1_3_1, + FIELD_fld_ae2_slot1_3_2, + FIELD_fld_ae2_slot1_3_3, + FIELD_fld_ae2_slot1_7_4, + FIELD_fld_ae2_slot1_9_8, + FIELD_fld_ae2_slot1_9_9, + FIELD_fld_ae2_slot2_14_10, + FIELD_fld_ae2_slot2_17_0, + FIELD_fld_ae2_slot2_17_10, + FIELD_fld_ae2_slot2_17_15, + FIELD_fld_ae2_slot2_17_17, + FIELD_fld_ae2_slot2_19_10, + FIELD_fld_ae2_slot2_19_15, + FIELD_fld_ae2_slot2_19_18, + FIELD_fld_ae2_slot2_19_9, + FIELD_fld_ae2_slot2_24_10, + FIELD_fld_ae2_slot2_24_15, + FIELD_fld_ae2_slot2_24_20, + FIELD_fld_ae2_slot2_24_5, + FIELD_fld_ae2_slot2_24_9, + FIELD_fld_ae2_slot2_42_18, + FIELD_fld_ae2_slot2_42_20, + FIELD_fld_ae2_slot2_42_25, + FIELD_fld_ae2_slot2_42_26, + FIELD_fld_ae2_slot2_42_28, + FIELD_fld_ae2_slot2_42_30, + FIELD_fld_ae2_slot2_4_0, + FIELD_fld_ae2_slot2_9_5, + FIELD_fld_ae_sem_spaddsub_vp, + FIELD_fld_ae_sem_spaddsub_vq, + FIELD_fld_ae3_slot0_11_11, + FIELD_fld_ae3_slot0_11_4, + FIELD_fld_ae3_slot0_11_8, + FIELD_fld_ae3_slot0_12_12, + FIELD_fld_ae3_slot0_12_8, + FIELD_fld_ae3_slot0_13_13, + FIELD_fld_ae3_slot0_13_8, + FIELD_fld_ae3_slot0_1_0, + FIELD_fld_ae3_slot0_32_11, + FIELD_fld_ae3_slot0_32_12, + FIELD_fld_ae3_slot0_32_13, + FIELD_fld_ae3_slot0_32_14, + FIELD_fld_ae3_slot0_32_15, + FIELD_fld_ae3_slot0_32_16, + FIELD_fld_ae3_slot0_32_17, + FIELD_fld_ae3_slot0_32_18, + FIELD_fld_ae3_slot0_32_20, + FIELD_fld_ae3_slot0_32_27, + FIELD_fld_ae3_slot0_32_8, + FIELD_fld_ae3_slot0_3_0, + FIELD_fld_ae3_slot0_3_2, + FIELD_fld_ae3_slot0_3_3, + FIELD_fld_ae3_slot0_4_0, + FIELD_fld_ae3_slot0_4_4, + FIELD_fld_ae3_slot0_5_0, + FIELD_fld_ae3_slot0_5_4, + FIELD_fld_ae3_slot0_7_0, + FIELD_fld_ae3_slot0_7_2, + FIELD_fld_ae3_slot0_7_4, + FIELD_fld_ae3_slot0_7_6, + FIELD_fld_ae3_slot0_8_8, + FIELD_fld_ae3_slot0_9_4, + FIELD_fld_ae3_slot0_9_8, + FIELD_fld_ae_sem_dr_to_ar_ar_s, + FIELD_fld_ae_sem_sb_loads_stores_iba2, + FIELD_fld_ae3_slot1_23_0, + FIELD_fld_ae3_slot1_23_11, + FIELD_fld_ae3_slot1_23_12, + FIELD_fld_ae3_slot1_23_13, + FIELD_fld_ae3_slot1_23_15, + FIELD_fld_ae3_slot1_23_16, + FIELD_fld_ae3_slot1_23_17, + FIELD_fld_ae3_slot1_23_19, + FIELD_fld_ae3_slot1_23_6, + FIELD_fld_ae3_slot1_23_8, + FIELD_fld_ae3_slot1_23_9, + FIELD_fld_ae3_slot1_3_0, + FIELD_fld_ae3_slot1_3_1, + FIELD_fld_ae3_slot1_3_2, + FIELD_fld_ae3_slot1_3_3, + FIELD_fld_ae3_slot1_7_4, + FIELD_fld_ae3_slot1_9_8, + FIELD_fld_AE_ARDECNORM16_ar_u, + FIELD_fld_ae5_slot0_11_10, + FIELD_fld_ae5_slot0_11_4, + FIELD_fld_ae5_slot0_11_8, + FIELD_fld_ae5_slot0_11_9, + FIELD_fld_ae5_slot0_12_10, + FIELD_fld_ae5_slot0_12_4, + FIELD_fld_ae5_slot0_12_6, + FIELD_fld_ae5_slot0_12_8, + FIELD_fld_ae5_slot0_12_9, + FIELD_fld_ae5_slot0_1_0, + FIELD_fld_ae5_slot0_1_1, + FIELD_fld_ae5_slot0_29_12, + FIELD_fld_ae5_slot0_29_13, + FIELD_fld_ae5_slot0_29_15, + FIELD_fld_ae5_slot0_29_16, + FIELD_fld_ae5_slot0_29_17, + FIELD_fld_ae5_slot0_29_18, + FIELD_fld_ae5_slot0_29_19, + FIELD_fld_ae5_slot0_29_20, + FIELD_fld_ae5_slot0_29_27, + FIELD_fld_ae5_slot0_29_5, + FIELD_fld_ae5_slot0_29_6, + FIELD_fld_ae5_slot0_29_8, + FIELD_fld_ae5_slot0_2_0, + FIELD_fld_ae5_slot0_3_0, + FIELD_fld_ae5_slot0_3_2, + FIELD_fld_ae5_slot0_4_0, + FIELD_fld_ae5_slot0_4_4, + FIELD_fld_ae5_slot0_7_0, + FIELD_fld_ae5_slot0_7_4, + FIELD_fld_ae5_slot0_7_7, + FIELD_fld_ae5_slot0_8_8, + FIELD_fld_ae_sem_lb_db_ops_ar_u, + FIELD_fld_ae_sem_lb_db_ops_iba, + FIELD_fld_ae_sem_rng_a, + FIELD_fld_ae_sem_rng_art, + FIELD_fld_ae_sem_rng_i2, + FIELD_fld_ae_sem_rng_imm2, + FIELD_fld_ae5_slot1_1_0, + FIELD_fld_ae5_slot2_14_10, + FIELD_fld_ae5_slot2_14_14, + FIELD_fld_ae5_slot2_14_5, + FIELD_fld_ae5_slot2_24_0, + FIELD_fld_ae5_slot2_24_15, + FIELD_fld_ae5_slot2_24_17, + FIELD_fld_ae5_slot2_24_20, + FIELD_fld_ae5_slot2_4_0, + FIELD_fld_ae5_slot2_9_0, + FIELD_fld_ae5_slot2_9_5, + FIELD_fld_ae5_slot2_9_7, + FIELD_fld_ae6_slot0_10_10, + FIELD_fld_ae6_slot0_15_15, + FIELD_fld_ae6_slot0_29_10, + FIELD_fld_ae6_slot0_29_13, + FIELD_fld_ae6_slot0_29_14, + FIELD_fld_ae6_slot0_29_15, + FIELD_fld_ae6_slot0_29_18, + FIELD_fld_ae6_slot0_29_20, + FIELD_fld_ae6_slot0_29_5, + FIELD_fld_ae6_slot0_4_0, + FIELD_fld_ae6_slot0_4_4, + FIELD_fld_ae6_slot0_7_4, + FIELD_fld_ae6_slot0_7_7, + FIELD_fld_ae6_slot0_9_8, + FIELD_fld_ae6_slot0_9_9, + FIELD_fld_ae6_slot1_14_14, + FIELD_fld_ae6_slot1_27_12, + FIELD_fld_ae6_slot1_27_15, + FIELD_fld_ae6_slot1_27_20, + FIELD_fld_ae6_slot1_27_21, + FIELD_fld_ae6_slot1_27_3, + FIELD_fld_ae6_slot1_27_6, + FIELD_fld_ae6_slot1_2_0, + FIELD_fld_ae6_slot1_9_5, + FIELD_fld_ae6_slot1_9_6, + FIELD_fld_ae6_slot1_9_7, + FIELD_fld_ae6_slot1_9_8, + FIELD_fld_ae6_slot1_9_9, + FIELD_fld_ae6_slot2_10_10, + FIELD_fld_ae6_slot2_11_10, + FIELD_fld_ae6_slot2_24_0, + FIELD_fld_ae6_slot2_24_10, + FIELD_fld_ae6_slot2_24_14, + FIELD_fld_ae6_slot2_24_15, + FIELD_fld_ae6_slot2_24_20, + FIELD_fld_ae6_slot2_4_2, + FIELD_fld_ae6_slot2_9_5, + FIELD_fld_ae6_slot3_10_10, + FIELD_fld_ae6_slot3_12_0, + FIELD_fld_ae6_slot3_14_0, + FIELD_fld_ae6_slot3_14_10, + FIELD_fld_ae6_slot3_14_13, + FIELD_fld_ae6_slot3_14_5, + FIELD_fld_ae6_slot3_24_20, + FIELD_fld_ae6_slot3_37_13, + FIELD_fld_ae6_slot3_37_15, + FIELD_fld_ae6_slot3_37_20, + FIELD_fld_ae6_slot3_37_30, + FIELD_fld_ae6_slot3_9_5, + FIELD_fld_ae7_slot0_12_6, + FIELD_fld_ae7_slot0_23_0, + FIELD_fld_ae7_slot0_23_13, + FIELD_fld_ae7_slot0_23_17, + FIELD_fld_ae7_slot0_23_18, + FIELD_fld_ae7_slot0_23_6, + FIELD_fld_ae7_slot0_7_4, + FIELD_fld_ae7_slot0_7_6, + FIELD_fld_ae7_slot0_7_7, + FIELD_fld_ae7_slot1_12_6, + FIELD_fld_ae7_slot1_23_0, + FIELD_fld_ae7_slot1_23_13, + FIELD_fld_ae7_slot1_23_17, + FIELD_fld_ae7_slot1_23_18, + FIELD_fld_ae7_slot1_23_6, + FIELD_fld_ae7_slot1_7_4, + FIELD_fld_ae7_slot1_7_6, + FIELD_fld_ae7_slot1_7_7, + FIELD_fld_ae7_slot2_11_0, + FIELD_fld_ae7_slot2_14_10, + FIELD_fld_ae7_slot2_14_5, + FIELD_fld_ae7_slot2_36_12, + FIELD_fld_ae7_slot2_36_15, + FIELD_fld_ae7_slot2_36_20, + FIELD_fld_ae7_slot2_36_25, + FIELD_fld_ae7_slot2_36_30, + FIELD_fld_ae7_slot2_9_5, + FIELD_fld_ae7_slot3_10_0, + FIELD_fld_ae7_slot3_14_10, + FIELD_fld_ae7_slot3_14_5, + FIELD_fld_ae7_slot3_24_10, + FIELD_fld_ae7_slot3_35_11, + FIELD_fld_ae7_slot3_35_20, + FIELD_fld_ae7_slot3_35_25, + FIELD_fld_ae7_slot3_35_30, + FIELD_fld_ae7_slot3_4_0, + FIELD_fld_ae7_slot3_9_5, + FIELD_fld_ae8_slot0_13_12, + FIELD_fld_ae8_slot0_13_13, + FIELD_fld_ae8_slot0_13_4, + FIELD_fld_ae8_slot0_13_9, + FIELD_fld_ae8_slot0_17_4, + FIELD_fld_ae8_slot0_17_8, + FIELD_fld_ae8_slot0_31_12, + FIELD_fld_ae8_slot0_31_15, + FIELD_fld_ae8_slot0_31_18, + FIELD_fld_ae8_slot0_31_19, + FIELD_fld_ae8_slot0_31_20, + FIELD_fld_ae8_slot0_31_21, + FIELD_fld_ae8_slot0_31_22, + FIELD_fld_ae8_slot0_31_23, + FIELD_fld_ae8_slot0_31_7, + FIELD_fld_ae8_slot0_31_8, + FIELD_fld_ae8_slot0_31_9, + FIELD_fld_ae8_slot0_3_0, + FIELD_fld_ae8_slot0_6_0, + FIELD_fld_ae8_slot0_7_4, + FIELD_fld_ae8_slot0_7_5, + FIELD_fld_ae8_slot0_7_7, + FIELD_fld_ae8_slot0_8_0, + FIELD_fld_ae8_slot1_17_13, + FIELD_fld_ae8_slot1_17_14, + FIELD_fld_ae8_slot1_17_15, + FIELD_fld_ae8_slot1_17_8, + FIELD_fld_ae8_slot1_29_12, + FIELD_fld_ae8_slot1_29_13, + FIELD_fld_ae8_slot1_29_18, + FIELD_fld_ae8_slot1_29_20, + FIELD_fld_ae8_slot1_29_22, + FIELD_fld_ae8_slot1_29_23, + FIELD_fld_ae8_slot1_29_5, + FIELD_fld_ae8_slot1_29_8, + FIELD_fld_ae8_slot1_29_9, + FIELD_fld_ae8_slot1_3_0, + FIELD_fld_ae8_slot1_3_3, + FIELD_fld_ae8_slot1_4_0, + FIELD_fld_ae8_slot1_7_4, + FIELD_fld_ae8_slot2_19_10, + FIELD_fld_ae8_slot2_19_15, + FIELD_fld_ae8_slot2_33_15, + FIELD_fld_ae8_slot2_33_25, + FIELD_fld_ae8_slot2_33_9, + FIELD_fld_ae8_slot2_34_30, + FIELD_fld_ae8_slot2_39_35, + FIELD_fld_ae8_slot2_44_35, + FIELD_fld_ae8_slot2_58_34, + FIELD_fld_ae8_slot2_58_35, + FIELD_fld_ae8_slot2_58_40, + FIELD_fld_ae8_slot2_58_50, + FIELD_fld_ae8_slot2_8_0, + FIELD_fld_ae8_slot2_9_0, + FIELD_fld_ae_sem_mul_nn_c0, + FIELD_fld_ae_sem_mul_nn_c1, + FIELD_fld_ae_sem_mul_nn_c2, + FIELD_fld_ae_sem_mul_nn_c3, + FIELD_fld_ae_sem_mul_nn_q0, + FIELD_fld_ae_sem_mul_nn_q1, + FIELD_fld_ae_sem_mul_nn_q2, + FIELD_fld_ae_sem_mul_nn_q3, + FIELD_fld_ae_sem_mul_nn_v0, + FIELD_fld_ae_sem_mul_nn_v1, + FIELD_fld_ae_sem_mul_nn_v2, + FIELD_fld_ae_sem_mul_nn_v3, + FIELD_fld_ae9_slot0_0_0, + FIELD_fld_ae9_slot0_12_12, + FIELD_fld_ae9_slot0_12_5, + FIELD_fld_ae9_slot0_12_8, + FIELD_fld_ae9_slot0_17_13, + FIELD_fld_ae9_slot0_17_4, + FIELD_fld_ae9_slot0_17_8, + FIELD_fld_ae9_slot0_27_10, + FIELD_fld_ae9_slot0_27_12, + FIELD_fld_ae9_slot0_27_13, + FIELD_fld_ae9_slot0_27_16, + FIELD_fld_ae9_slot0_27_17, + FIELD_fld_ae9_slot0_27_18, + FIELD_fld_ae9_slot0_27_19, + FIELD_fld_ae9_slot0_27_20, + FIELD_fld_ae9_slot0_27_22, + FIELD_fld_ae9_slot0_27_23, + FIELD_fld_ae9_slot0_27_3, + FIELD_fld_ae9_slot0_27_8, + FIELD_fld_ae9_slot0_2_0, + FIELD_fld_ae9_slot0_3_0, + FIELD_fld_ae9_slot0_7_0, + FIELD_fld_ae9_slot0_7_4, + FIELD_fld_ae9_slot0_7_5, + FIELD_fld_ae9_slot0_7_6, + FIELD_fld_ae9_slot0_7_7, + FIELD_fld_ae9_slot0_8_4, + FIELD_fld_ae9_slot0_8_5, + FIELD_fld_ae9_slot0_9_5, + FIELD_fld_ae9_slot1_17_13, + FIELD_fld_ae9_slot1_17_8, + FIELD_fld_ae9_slot1_1_0, + FIELD_fld_ae9_slot1_26_12, + FIELD_fld_ae9_slot1_26_13, + FIELD_fld_ae9_slot1_26_16, + FIELD_fld_ae9_slot1_26_17, + FIELD_fld_ae9_slot1_26_18, + FIELD_fld_ae9_slot1_26_2, + FIELD_fld_ae9_slot1_26_20, + FIELD_fld_ae9_slot1_26_22, + FIELD_fld_ae9_slot1_26_23, + FIELD_fld_ae9_slot1_26_8, + FIELD_fld_ae9_slot1_26_9, + FIELD_fld_ae9_slot1_3_0, + FIELD_fld_ae9_slot1_3_2, + FIELD_fld_ae9_slot1_3_3, + FIELD_fld_ae9_slot1_7_4, + FIELD_fld_ae9_slot2_24_14, + FIELD_fld_ae9_slot2_24_15, + FIELD_fld_ae9_slot2_24_20, + FIELD_fld_ae9_slot2_33_14, + FIELD_fld_ae9_slot2_33_15, + FIELD_fld_ae9_slot2_33_20, + FIELD_fld_ae9_slot2_33_25, + FIELD_fld_ae9_slot2_33_26, + FIELD_fld_ae9_slot2_33_28, + FIELD_fld_ae9_slot2_33_30, + FIELD_fld_ae9_slot2_33_9, + FIELD_fld_ae9_slot2_4_0, + FIELD_fld_ae9_slot2_5_0, + FIELD_fld_ae9_slot2_6_0, + FIELD_fld_ae9_slot2_8_0, + FIELD_fld_ae9_slot2_9_0, + FIELD_fld_ae9_slot2_9_5, + FIELD_fld_ae9_slot2_9_9, + FIELD_fld_ae_sem_hpfma_vp, + FIELD_fld_ae_sem_hpfma_vu, + FIELD_fld_ae_sem_spfma_vu, + FIELD_fld_ae9_slot3_19_15, + FIELD_fld_ae9_slot3_24_20, + FIELD_fld_ae9_slot3_31_14, + FIELD_fld_ae9_slot3_31_15, + FIELD_fld_ae9_slot3_31_20, + FIELD_fld_ae9_slot3_31_25, + FIELD_fld_ae9_slot3_31_26, + FIELD_fld_ae9_slot3_31_28, + FIELD_fld_ae9_slot3_31_7, + FIELD_fld_ae9_slot3_4_0, + FIELD_fld_ae9_slot3_4_3, + FIELD_fld_ae9_slot3_4_4, + FIELD_fld_ae9_slot3_6_0, + FIELD_fld_ae9_slot3_9_0, + FIELD_fld_ae9_slot3_9_5, + FIELD_fld_ae10_slot0_17_13, + FIELD_fld_ae10_slot0_17_4, + FIELD_fld_ae10_slot0_17_8, + FIELD_fld_ae10_slot0_24_0, + FIELD_fld_ae10_slot0_24_10, + FIELD_fld_ae10_slot0_24_12, + FIELD_fld_ae10_slot0_24_13, + FIELD_fld_ae10_slot0_24_16, + FIELD_fld_ae10_slot0_24_17, + FIELD_fld_ae10_slot0_24_18, + FIELD_fld_ae10_slot0_24_20, + FIELD_fld_ae10_slot0_24_8, + FIELD_fld_ae10_slot0_3_0, + FIELD_fld_ae10_slot0_7_4, + FIELD_fld_ae10_slot0_7_6, + FIELD_fld_ae10_slot0_7_7, + FIELD_fld_ae10_slot0_8_4, + FIELD_fld_ae10_slot1_0_0, + FIELD_fld_ae10_slot1_17_13, + FIELD_fld_ae10_slot1_17_8, + FIELD_fld_ae10_slot1_25_1, + FIELD_fld_ae10_slot1_25_12, + FIELD_fld_ae10_slot1_25_13, + FIELD_fld_ae10_slot1_25_16, + FIELD_fld_ae10_slot1_25_17, + FIELD_fld_ae10_slot1_25_18, + FIELD_fld_ae10_slot1_25_20, + FIELD_fld_ae10_slot1_25_22, + FIELD_fld_ae10_slot1_25_23, + FIELD_fld_ae10_slot1_25_8, + FIELD_fld_ae10_slot1_25_9, + FIELD_fld_ae10_slot1_3_0, + FIELD_fld_ae10_slot1_3_2, + FIELD_fld_ae10_slot1_3_3, + FIELD_fld_ae10_slot1_7_4, + FIELD_fld_ae10_slot2_24_20, + FIELD_fld_ae10_slot2_29_20, + FIELD_fld_ae10_slot2_29_25, + FIELD_fld_ae10_slot2_34_10, + FIELD_fld_ae10_slot2_34_14, + FIELD_fld_ae10_slot2_34_15, + FIELD_fld_ae10_slot2_34_20, + FIELD_fld_ae10_slot2_34_25, + FIELD_fld_ae10_slot2_34_30, + FIELD_fld_ae10_slot2_34_31, + FIELD_fld_ae10_slot2_34_33, + FIELD_fld_ae10_slot2_4_0, + FIELD_fld_ae10_slot2_9_0, + FIELD_fld_ae10_slot2_9_5, + FIELD_fld_ae_sem_hpfma_vq, + FIELD_fld_ae_sem_spfma_vq, + FIELD_fld_ae10_slot3_19_15, + FIELD_fld_ae10_slot3_29_20, + FIELD_fld_ae10_slot3_29_25, + FIELD_fld_ae10_slot3_34_10, + FIELD_fld_ae10_slot3_34_14, + FIELD_fld_ae10_slot3_34_15, + FIELD_fld_ae10_slot3_34_20, + FIELD_fld_ae10_slot3_34_25, + FIELD_fld_ae10_slot3_34_30, + FIELD_fld_ae10_slot3_34_31, + FIELD_fld_ae10_slot3_34_33, + FIELD_fld_ae10_slot3_4_0, + FIELD_fld_ae10_slot3_4_3, + FIELD_fld_ae10_slot3_4_4, + FIELD_fld_ae10_slot3_9_0, + FIELD_fld_ae10_slot3_9_5, + FIELD_fld_ae4_slot0_22_0, + FIELD_fld_ae4_slot0_22_12, + FIELD_fld_ae4_slot0_22_13, + FIELD_fld_ae4_slot0_22_16, + FIELD_fld_ae4_slot0_22_17, + FIELD_fld_ae4_slot0_22_18, + FIELD_fld_ae4_slot0_22_20, + FIELD_fld_ae4_slot0_22_6, + FIELD_fld_ae4_slot0_22_8, + FIELD_fld_ae4_slot0_3_0, + FIELD_fld_ae4_slot0_3_1, + FIELD_fld_ae4_slot0_4_4, + FIELD_fld_ae4_slot0_7_4, + FIELD_fld_ae4_slot1_22_0, + FIELD_fld_ae4_slot1_22_12, + FIELD_fld_ae4_slot1_22_13, + FIELD_fld_ae4_slot1_22_16, + FIELD_fld_ae4_slot1_22_17, + FIELD_fld_ae4_slot1_22_18, + FIELD_fld_ae4_slot1_22_8, + FIELD_fld_ae4_slot1_3_0, + FIELD_fld_ae4_slot1_3_1, + FIELD_fld_ae4_slot1_7_4, + FIELD_fld_ae4_slot2_23_0, + FIELD_fld_ae4_slot2_23_12, + FIELD_fld_ae4_slot2_23_15, + FIELD_fld_ae4_slot2_23_17, + FIELD_fld_ae4_slot2_23_20, + FIELD_fld_ae4_slot2_4_0, + FIELD_fld_ae4_slot2_9_5, + FIELD_fld_ae4_slot3_14_10, + FIELD_fld_ae4_slot3_19_15, + FIELD_fld_ae4_slot3_19_19, + FIELD_fld_ae4_slot3_19_5, + FIELD_fld_ae4_slot3_27_20, + FIELD_fld_ae4_slot3_27_25, + FIELD_fld_ae4_slot3_27_3, + FIELD_fld_ae4_slot3_2_0, + FIELD_fld_ae4_slot3_9_0, + FIELD_fld_ae4_slot3_9_5, + FIELD_fld_ae4_slot4_22_0, + FIELD_fld_ae4_slot4_22_15, + FIELD_fld_ae4_slot4_22_20, + FIELD_fld_ae4_slot4_9_5, + FIELD_fld_Inst_11_8, + FIELD_fld_Inst_12_12, + FIELD_fld_Inst_12_8, + FIELD_fld_Inst_13_8, + FIELD_fld_Inst_15_12, + FIELD_fld_Inst_19_17, + FIELD_fld_Inst_19_18, + FIELD_fld_Inst_23_12, + FIELD_fld_Inst_23_16, + FIELD_fld_Inst_4_4, + FIELD_fld_Inst_5_4, + FIELD_fld_Inst_7_4, + FIELD_fld_Inst_7_6, + FIELD_fld_Inst_7_7, + FIELD_fld_Inst_9_8, + FIELD_bitindex, + FIELD_s3to1, + FIELD__ar0, + FIELD__ar4, + FIELD__ar8, + FIELD__ar12, + FIELD__bt16, + FIELD__bs16, + FIELD__br16, + FIELD__brall +}; + + +/* Functional units. */ + +static xtensa_funcUnit_internal funcUnits[] = { + {"XT_LOADSTORE_UNIT", 2}, + { "mul_function", 1 }, + { "mul_S2_function", 1 }, + { "ae_add32x27", 1 }, + { "ae_shift32x4", 1 }, + { "ae_shift32x5", 1 }, + { "ae_leftshift32x5", 2 } +}; + +enum xtensa_funcUnit_id { + FUNCUNIT_XT_LOADSTORE_UNIT, + FUNCUNIT_mul_function, + FUNCUNIT_mul_S2_function, + FUNCUNIT_ae_add32x27, + FUNCUNIT_ae_shift32x4, + FUNCUNIT_ae_shift32x5, + FUNCUNIT_ae_leftshift32x5 +}; + + +/* Register files. */ + +enum xtensa_regfile_id { + REGFILE_AR, + REGFILE_BR, + REGFILE_AE_DR, + REGFILE_AE_VALIGN, + REGFILE_AE_EP, + REGFILE_BR2, + REGFILE_BR4, + REGFILE_BR8, + REGFILE_BR16 +}; + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", REGFILE_AR, 32, 64 }, + { "BR", "b", REGFILE_BR, 1, 16 }, + { "AE_DR", "aed", REGFILE_AE_DR, 64, 32 }, + { "AE_VALIGN", "u", REGFILE_AE_VALIGN, 128, 4 }, + { "AE_EP", "aep", REGFILE_AE_EP, 8, 4 }, + { "BR2", "b", REGFILE_BR, 2, 8 }, + { "BR4", "b", REGFILE_BR, 4, 4 }, + { "BR8", "b", REGFILE_BR, 8, 2 }, + { "BR16", "b", REGFILE_BR, 16, 1 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + { "ERI_RD_Out", 14, 0, 0, 'o' }, + { "ERI_RD_In", 32, 0, 1, 'i' }, + { "ERI_RD_Rdy", 1, 0, 0, 'i' }, + { "ERI_WR_Out", 46, 0, 2, 'o' }, + { "ERI_WR_In", 1, 0, 3, 'i' }, + { "IMPWIRE", 32, 0, 4, 'i' } +}; + +enum xtensa_interface_id { + INTERFACE_ERI_RD_Out, + INTERFACE_ERI_RD_In, + INTERFACE_ERI_RD_Rdy, + INTERFACE_ERI_WR_Out, + INTERFACE_ERI_WR_In, + INTERFACE_IMPWIRE +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table bitmask8 */ +static const unsigned CONST_TBL_bitmask8_0[] = { + 0 & 0xff, + 0x1 & 0xff, + 0x3 & 0xff, + 0x7 & 0xff, + 0xf & 0xff, + 0x1f & 0xff, + 0x3f & 0xff, + 0x7f & 0xff, + 0 +}; + +/* constant table bitmask16 */ +static const unsigned CONST_TBL_bitmask16_0[] = { + 0 & 0xffff, + 0x1 & 0xffff, + 0x3 & 0xffff, + 0x7 & 0xffff, + 0xf & 0xffff, + 0x1f & 0xffff, + 0x3f & 0xffff, + 0x7f & 0xffff, + 0xff & 0xffff, + 0x1ff & 0xffff, + 0x3ff & 0xffff, + 0x7ff & 0xffff, + 0xfff & 0xffff, + 0x1fff & 0xffff, + 0x3fff & 0xffff, + 0x7fff & 0xffff, + 0 +}; + +/* constant table ae_ltr4_table */ +static const unsigned CONST_TBL_ae_ltr4_table_0[] = { + 0 & 0xf, + 0x8 & 0xf, + 0xc & 0xf, + 0xe & 0xf, + 0 +}; + +/* constant table ae_ltr8_table */ +static const unsigned CONST_TBL_ae_ltr8_table_0[] = { + 0 & 0xff, + 0x80 & 0xff, + 0xc0 & 0xff, + 0xe0 & 0xff, + 0xf0 & 0xff, + 0xf8 & 0xff, + 0xfc & 0xff, + 0xfe & 0xff, + 0 +}; + +/* constant table ae_immls64neg */ +static const unsigned CONST_TBL_ae_immls64neg_0[] = { + 0xffffffe0, + 0xffffffe8, + 0xfffffff0, + 0xfffffff8, + 0 +}; + +/* constant table ae_slai72table */ +static const unsigned CONST_TBL_ae_slai72table_0[] = { + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0 +}; + +/* constant table ae_seliencode */ +static const unsigned CONST_TBL_ae_seliencode_0[] = { + 0x4e5 & 0xfff, + 0x65 & 0xfff, + 0x77 & 0xfff, + 0x4f7 & 0xfff, + 0x72e & 0xfff, + 0x29c & 0xfff, + 0xaf & 0xfff, + 0xa6 & 0xfff, + 0x2ef & 0xfff, + 0x10d & 0xfff, + 0x599 & 0xfff, + 0x59f & 0xfff, + 0xb3e & 0xfff, + 0x18f & 0xfff, + 0x51d & 0xfff, + 0xa6 & 0xfff, + 0 +}; + +/* constant table ae_ohba */ +static const unsigned CONST_TBL_ae_ohba_0[] = { + 0x1 & 0x1f, + 0x2 & 0x1f, + 0x3 & 0x1f, + 0x4 & 0x1f, + 0x5 & 0x1f, + 0x6 & 0x1f, + 0x7 & 0x1f, + 0x8 & 0x1f, + 0x9 & 0x1f, + 0xa & 0x1f, + 0xb & 0x1f, + 0xc & 0x1f, + 0xd & 0x1f, + 0xe & 0x1f, + 0xf & 0x1f, + 0x10 & 0x1f, + 0 +}; + +/* constant table ae_ohba2 */ +static const unsigned CONST_TBL_ae_ohba2_0[] = { + 0x1 & 0x1f, + 0x2 & 0x1f, + 0x3 & 0x1f, + 0x4 & 0x1f, + 0x5 & 0x1f, + 0x6 & 0x1f, + 0x7 & 0x1f, + 0x8 & 0x1f, + 0x9 & 0x1f, + 0xa & 0x1f, + 0xb & 0x1f, + 0xc & 0x1f, + 0xd & 0x1f, + 0xe & 0x1f, + 0xf & 0x1f, + 0x10 & 0x1f, + 0 +}; + +/* constant table ae_opnd_tp7 */ +static const unsigned CONST_TBL_ae_opnd_tp7_0[] = { + 0x7 & 0x1f, + 0x8 & 0x1f, + 0x9 & 0x1f, + 0xa & 0x1f, + 0xb & 0x1f, + 0xc & 0x1f, + 0xd & 0x1f, + 0xe & 0x1f, + 0xf & 0x1f, + 0x10 & 0x1f, + 0x11 & 0x1f, + 0x12 & 0x1f, + 0x13 & 0x1f, + 0x14 & 0x1f, + 0x15 & 0x1f, + 0x16 & 0x1f, + 0 +}; + +/* constant table xd_seli_8x8_table0 */ +static const unsigned CONST_TBL_xd_seli_8x8_table0_0[] = { + 0xba987654, + 0xfedc7654, + 0xfedc3210, + 0xba983210, + 0x98765432, + 0xdcba9876, + 0xfeba5410, + 0xfeba7632, + 0xdc985410, + 0xfe76dc54, + 0xba3298dc, + 0xba329810, + 0x54761032, + 0xfe32dc10, + 0xba769854, + 0xfeba7632, + 0xedcba987, + 0xcba98765, + 0xa9876543, + 0x87654321, + 0xf7e6d5c4, + 0xb3a29180, + 0xf3e2d1c0, + 0xb7a69584, + 0xfe76ba32, + 0xeca86420, + 0xfdb97531, + 0xeca87531, + 0xfdb96420, + 0xdc987632, + 0xefcdab89, + 0x32107654, + 0 +}; + +/* constant table xd_seli_8x8_table0_be */ +static const unsigned CONST_TBL_xd_seli_8x8_table0_be_0[] = { + 0x456789ab, + 0x12389ab, + 0x123cdef, + 0x4567cdef, + 0x6789abcd, + 0x23456789, + 0x145abef, + 0x14589cd, + 0x2367abef, + 0x18923ab, + 0x45cd6723, + 0x45cd67ef, + 0xab89efcd, + 0x1cd23ef, + 0x458967ab, + 0x14589cd, + 0x12345678, + 0x3456789a, + 0x56789abc, + 0x789abcde, + 0x8192a3b, + 0x4c5d6e7f, + 0xc1d2e3f, + 0x48596a7b, + 0x18945cd, + 0x13579bdf, + 0x2468ace, + 0x13578ace, + 0x2469bdf, + 0x236789cd, + 0x10325476, + 0xcdef89ab, + 0 +}; + +/* constant table tab_lavunqz_8x8 */ +static const unsigned CONST_TBL_tab_lavunqz_8x8_0[] = { + 0, + 0x7, + 0x70, + 0x76, + 0x700, + 0x706, + 0x760, + 0x765, + 0x7000, + 0x7006, + 0x7060, + 0x7065, + 0x7600, + 0x7605, + 0x7650, + 0x7654, + 0x70000, + 0x70006, + 0x70060, + 0x70065, + 0x70600, + 0x70605, + 0x70650, + 0x70654, + 0x76000, + 0x76005, + 0x76050, + 0x76054, + 0x76500, + 0x76504, + 0x76540, + 0x76543, + 0x700000, + 0x700006, + 0x700060, + 0x700065, + 0x700600, + 0x700605, + 0x700650, + 0x700654, + 0x706000, + 0x706005, + 0x706050, + 0x706054, + 0x706500, + 0x706504, + 0x706540, + 0x706543, + 0x760000, + 0x760005, + 0x760050, + 0x760054, + 0x760500, + 0x760504, + 0x760540, + 0x760543, + 0x765000, + 0x765004, + 0x765040, + 0x765043, + 0x765400, + 0x765403, + 0x765430, + 0x765432, + 0x7000000, + 0x7000006, + 0x7000060, + 0x7000065, + 0x7000600, + 0x7000605, + 0x7000650, + 0x7000654, + 0x7006000, + 0x7006005, + 0x7006050, + 0x7006054, + 0x7006500, + 0x7006504, + 0x7006540, + 0x7006543, + 0x7060000, + 0x7060005, + 0x7060050, + 0x7060054, + 0x7060500, + 0x7060504, + 0x7060540, + 0x7060543, + 0x7065000, + 0x7065004, + 0x7065040, + 0x7065043, + 0x7065400, + 0x7065403, + 0x7065430, + 0x7065432, + 0x7600000, + 0x7600005, + 0x7600050, + 0x7600054, + 0x7600500, + 0x7600504, + 0x7600540, + 0x7600543, + 0x7605000, + 0x7605004, + 0x7605040, + 0x7605043, + 0x7605400, + 0x7605403, + 0x7605430, + 0x7605432, + 0x7650000, + 0x7650004, + 0x7650040, + 0x7650043, + 0x7650400, + 0x7650403, + 0x7650430, + 0x7650432, + 0x7654000, + 0x7654003, + 0x7654030, + 0x7654032, + 0x7654300, + 0x7654302, + 0x7654320, + 0x7654321, + 0x70000000, + 0x70000006, + 0x70000060, + 0x70000065, + 0x70000600, + 0x70000605, + 0x70000650, + 0x70000654, + 0x70006000, + 0x70006005, + 0x70006050, + 0x70006054, + 0x70006500, + 0x70006504, + 0x70006540, + 0x70006543, + 0x70060000, + 0x70060005, + 0x70060050, + 0x70060054, + 0x70060500, + 0x70060504, + 0x70060540, + 0x70060543, + 0x70065000, + 0x70065004, + 0x70065040, + 0x70065043, + 0x70065400, + 0x70065403, + 0x70065430, + 0x70065432, + 0x70600000, + 0x70600005, + 0x70600050, + 0x70600054, + 0x70600500, + 0x70600504, + 0x70600540, + 0x70600543, + 0x70605000, + 0x70605004, + 0x70605040, + 0x70605043, + 0x70605400, + 0x70605403, + 0x70605430, + 0x70605432, + 0x70650000, + 0x70650004, + 0x70650040, + 0x70650043, + 0x70650400, + 0x70650403, + 0x70650430, + 0x70650432, + 0x70654000, + 0x70654003, + 0x70654030, + 0x70654032, + 0x70654300, + 0x70654302, + 0x70654320, + 0x70654321, + 0x76000000, + 0x76000005, + 0x76000050, + 0x76000054, + 0x76000500, + 0x76000504, + 0x76000540, + 0x76000543, + 0x76005000, + 0x76005004, + 0x76005040, + 0x76005043, + 0x76005400, + 0x76005403, + 0x76005430, + 0x76005432, + 0x76050000, + 0x76050004, + 0x76050040, + 0x76050043, + 0x76050400, + 0x76050403, + 0x76050430, + 0x76050432, + 0x76054000, + 0x76054003, + 0x76054030, + 0x76054032, + 0x76054300, + 0x76054302, + 0x76054320, + 0x76054321, + 0x76500000, + 0x76500004, + 0x76500040, + 0x76500043, + 0x76500400, + 0x76500403, + 0x76500430, + 0x76500432, + 0x76504000, + 0x76504003, + 0x76504030, + 0x76504032, + 0x76504300, + 0x76504302, + 0x76504320, + 0x76504321, + 0x76540000, + 0x76540003, + 0x76540030, + 0x76540032, + 0x76540300, + 0x76540302, + 0x76540320, + 0x76540321, + 0x76543000, + 0x76543002, + 0x76543020, + 0x76543021, + 0x76543200, + 0x76543201, + 0x76543210, + 0x76543210, + 0 +}; + +/* constant table tab_lavunqz_16x4 */ +static const unsigned CONST_TBL_tab_lavunqz_16x4_0[] = { + 0 & 0xff, + 0x3 & 0xff, + 0xc & 0xff, + 0xe & 0xff, + 0x30 & 0xff, + 0x32 & 0xff, + 0x38 & 0xff, + 0x39 & 0xff, + 0xc0 & 0xff, + 0xc2 & 0xff, + 0xc8 & 0xff, + 0xc9 & 0xff, + 0xe0 & 0xff, + 0xe1 & 0xff, + 0xe4 & 0xff, + 0xe4 & 0xff, + 0 +}; + +/* constant table xd_recip0_table128_8 */ +static const unsigned CONST_TBL_xd_recip0_table128_8_0[] = { + 0xff & 0xff, + 0xfd & 0xff, + 0xfb & 0xff, + 0xf9 & 0xff, + 0xf7 & 0xff, + 0xf5 & 0xff, + 0xf4 & 0xff, + 0xf2 & 0xff, + 0xf0 & 0xff, + 0xee & 0xff, + 0xed & 0xff, + 0xeb & 0xff, + 0xe9 & 0xff, + 0xe8 & 0xff, + 0xe6 & 0xff, + 0xe4 & 0xff, + 0xe3 & 0xff, + 0xe1 & 0xff, + 0xe0 & 0xff, + 0xde & 0xff, + 0xdd & 0xff, + 0xdb & 0xff, + 0xda & 0xff, + 0xd8 & 0xff, + 0xd7 & 0xff, + 0xd5 & 0xff, + 0xd4 & 0xff, + 0xd3 & 0xff, + 0xd1 & 0xff, + 0xd0 & 0xff, + 0xcf & 0xff, + 0xcd & 0xff, + 0xcc & 0xff, + 0xcb & 0xff, + 0xca & 0xff, + 0xc8 & 0xff, + 0xc7 & 0xff, + 0xc6 & 0xff, + 0xc5 & 0xff, + 0xc4 & 0xff, + 0xc2 & 0xff, + 0xc1 & 0xff, + 0xc0 & 0xff, + 0xbf & 0xff, + 0xbe & 0xff, + 0xbd & 0xff, + 0xbc & 0xff, + 0xbb & 0xff, + 0xba & 0xff, + 0xb9 & 0xff, + 0xb8 & 0xff, + 0xb7 & 0xff, + 0xb6 & 0xff, + 0xb5 & 0xff, + 0xb4 & 0xff, + 0xb3 & 0xff, + 0xb2 & 0xff, + 0xb1 & 0xff, + 0xb0 & 0xff, + 0xaf & 0xff, + 0xae & 0xff, + 0xad & 0xff, + 0xac & 0xff, + 0xab & 0xff, + 0xaa & 0xff, + 0xa9 & 0xff, + 0xa8 & 0xff, + 0xa8 & 0xff, + 0xa7 & 0xff, + 0xa6 & 0xff, + 0xa5 & 0xff, + 0xa4 & 0xff, + 0xa3 & 0xff, + 0xa3 & 0xff, + 0xa2 & 0xff, + 0xa1 & 0xff, + 0xa0 & 0xff, + 0x9f & 0xff, + 0x9f & 0xff, + 0x9e & 0xff, + 0x9d & 0xff, + 0x9c & 0xff, + 0x9c & 0xff, + 0x9b & 0xff, + 0x9a & 0xff, + 0x99 & 0xff, + 0x99 & 0xff, + 0x98 & 0xff, + 0x97 & 0xff, + 0x97 & 0xff, + 0x96 & 0xff, + 0x95 & 0xff, + 0x95 & 0xff, + 0x94 & 0xff, + 0x93 & 0xff, + 0x93 & 0xff, + 0x92 & 0xff, + 0x91 & 0xff, + 0x91 & 0xff, + 0x90 & 0xff, + 0x8f & 0xff, + 0x8f & 0xff, + 0x8e & 0xff, + 0x8e & 0xff, + 0x8d & 0xff, + 0x8c & 0xff, + 0x8c & 0xff, + 0x8b & 0xff, + 0x8b & 0xff, + 0x8a & 0xff, + 0x89 & 0xff, + 0x89 & 0xff, + 0x88 & 0xff, + 0x88 & 0xff, + 0x87 & 0xff, + 0x87 & 0xff, + 0x86 & 0xff, + 0x85 & 0xff, + 0x85 & 0xff, + 0x84 & 0xff, + 0x84 & 0xff, + 0x83 & 0xff, + 0x83 & 0xff, + 0x82 & 0xff, + 0x82 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0 +}; + +/* constant table xd_rsqrt0_table128_8 */ +static const unsigned CONST_TBL_xd_rsqrt0_table128_8_0[] = { + 0xb4 & 0xff, + 0xb3 & 0xff, + 0xb2 & 0xff, + 0xb0 & 0xff, + 0xaf & 0xff, + 0xae & 0xff, + 0xac & 0xff, + 0xab & 0xff, + 0xaa & 0xff, + 0xa9 & 0xff, + 0xa8 & 0xff, + 0xa7 & 0xff, + 0xa6 & 0xff, + 0xa5 & 0xff, + 0xa3 & 0xff, + 0xa2 & 0xff, + 0xa1 & 0xff, + 0xa0 & 0xff, + 0x9f & 0xff, + 0x9e & 0xff, + 0x9e & 0xff, + 0x9d & 0xff, + 0x9c & 0xff, + 0x9b & 0xff, + 0x9a & 0xff, + 0x99 & 0xff, + 0x98 & 0xff, + 0x97 & 0xff, + 0x97 & 0xff, + 0x96 & 0xff, + 0x95 & 0xff, + 0x94 & 0xff, + 0x93 & 0xff, + 0x93 & 0xff, + 0x92 & 0xff, + 0x91 & 0xff, + 0x90 & 0xff, + 0x90 & 0xff, + 0x8f & 0xff, + 0x8e & 0xff, + 0x8e & 0xff, + 0x8d & 0xff, + 0x8c & 0xff, + 0x8c & 0xff, + 0x8b & 0xff, + 0x8a & 0xff, + 0x8a & 0xff, + 0x89 & 0xff, + 0x89 & 0xff, + 0x88 & 0xff, + 0x87 & 0xff, + 0x87 & 0xff, + 0x86 & 0xff, + 0x86 & 0xff, + 0x85 & 0xff, + 0x84 & 0xff, + 0x84 & 0xff, + 0x83 & 0xff, + 0x83 & 0xff, + 0x82 & 0xff, + 0x82 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0x80 & 0xff, + 0xff & 0xff, + 0xfd & 0xff, + 0xfb & 0xff, + 0xf9 & 0xff, + 0xf7 & 0xff, + 0xf6 & 0xff, + 0xf4 & 0xff, + 0xf2 & 0xff, + 0xf1 & 0xff, + 0xef & 0xff, + 0xed & 0xff, + 0xec & 0xff, + 0xea & 0xff, + 0xe9 & 0xff, + 0xe7 & 0xff, + 0xe6 & 0xff, + 0xe4 & 0xff, + 0xe3 & 0xff, + 0xe1 & 0xff, + 0xe0 & 0xff, + 0xdf & 0xff, + 0xdd & 0xff, + 0xdc & 0xff, + 0xdb & 0xff, + 0xda & 0xff, + 0xd8 & 0xff, + 0xd7 & 0xff, + 0xd6 & 0xff, + 0xd5 & 0xff, + 0xd4 & 0xff, + 0xd3 & 0xff, + 0xd2 & 0xff, + 0xd0 & 0xff, + 0xcf & 0xff, + 0xce & 0xff, + 0xcd & 0xff, + 0xcc & 0xff, + 0xcb & 0xff, + 0xca & 0xff, + 0xc9 & 0xff, + 0xc8 & 0xff, + 0xc7 & 0xff, + 0xc6 & 0xff, + 0xc6 & 0xff, + 0xc5 & 0xff, + 0xc4 & 0xff, + 0xc3 & 0xff, + 0xc2 & 0xff, + 0xc1 & 0xff, + 0xc0 & 0xff, + 0xbf & 0xff, + 0xbf & 0xff, + 0xbe & 0xff, + 0xbd & 0xff, + 0xbc & 0xff, + 0xbb & 0xff, + 0xbb & 0xff, + 0xba & 0xff, + 0xb9 & 0xff, + 0xb8 & 0xff, + 0xb8 & 0xff, + 0xb7 & 0xff, + 0xb6 & 0xff, + 0xb5 & 0xff, + 0 +}; + +/* constant table vfpu2_table_mulmux */ +static const unsigned CONST_TBL_vfpu2_table_mulmux_0[] = { + 0xe & 0x3f, + 0x1e & 0x3f, + 0 +}; + +/* constant table vfpu2_table_maddmux */ +static const unsigned CONST_TBL_vfpu2_table_maddmux_0[] = { + 0xe & 0x3f, + 0x21 & 0x3f, + 0x3e & 0x3f, + 0x11 & 0x3f, + 0x1e & 0x3f, + 0x1 & 0x3f, + 0x2e & 0x3f, + 0x31 & 0x3f, + 0 +}; + +/* constant table xdsem_tab_la_default */ +static const unsigned CONST_TBL_xdsem_tab_la_default_0[] = { + 0xffff & 0xffff, + 0xfffe & 0xffff, + 0xfffc & 0xffff, + 0xfff8 & 0xffff, + 0xfff0 & 0xffff, + 0xffe0 & 0xffff, + 0xffc0 & 0xffff, + 0xff80 & 0xffff, + 0xff00 & 0xffff, + 0xfe00 & 0xffff, + 0xfc00 & 0xffff, + 0xf800 & 0xffff, + 0xf000 & 0xffff, + 0xe000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_lahr */ +static const unsigned CONST_TBL_xdsem_tab_lahr_0[] = { + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0 +}; + +/* constant table xdsem_tab_lahs */ +static const unsigned CONST_TBL_xdsem_tab_lahs_0[] = { + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev8_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev8_m64_0[] = { + 0x100 & 0xffff, + 0x200 & 0xffff, + 0x400 & 0xffff, + 0x800 & 0xffff, + 0x1000 & 0xffff, + 0x2000 & 0xffff, + 0x4000 & 0xffff, + 0x8000 & 0xffff, + 0x1 & 0xffff, + 0x2 & 0xffff, + 0x4 & 0xffff, + 0x8 & 0xffff, + 0x10 & 0xffff, + 0x20 & 0xffff, + 0x40 & 0xffff, + 0x80 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev8_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev8_m32_0[] = { + 0x1010 & 0xffff, + 0x2020 & 0xffff, + 0x4040 & 0xffff, + 0x8080 & 0xffff, + 0x101 & 0xffff, + 0x202 & 0xffff, + 0x404 & 0xffff, + 0x808 & 0xffff, + 0x1010 & 0xffff, + 0x2020 & 0xffff, + 0x4040 & 0xffff, + 0x8080 & 0xffff, + 0x101 & 0xffff, + 0x202 & 0xffff, + 0x404 & 0xffff, + 0x808 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev8_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev8_m16_0[] = { + 0x4444 & 0xffff, + 0x8888 & 0xffff, + 0x1111 & 0xffff, + 0x2222 & 0xffff, + 0x4444 & 0xffff, + 0x8888 & 0xffff, + 0x1111 & 0xffff, + 0x2222 & 0xffff, + 0x4444 & 0xffff, + 0x8888 & 0xffff, + 0x1111 & 0xffff, + 0x2222 & 0xffff, + 0x4444 & 0xffff, + 0x8888 & 0xffff, + 0x1111 & 0xffff, + 0x2222 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev8_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev8_m8_0[] = { + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev16_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev16_m64_0[] = { + 0 & 0xffff, + 0 & 0xffff, + 0x3 & 0xffff, + 0x3 & 0xffff, + 0xf & 0xffff, + 0xf & 0xffff, + 0x3f & 0xffff, + 0x3f & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xfc & 0xffff, + 0xfc & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0xc0 & 0xffff, + 0xc0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev16_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev16_m32_0[] = { + 0xff & 0xffff, + 0xff & 0xffff, + 0xcc & 0xffff, + 0xcc & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0x33 & 0xffff, + 0x33 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xcc & 0xffff, + 0xcc & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev16_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev16_m16_0[] = { + 0xff & 0xffff, + 0xff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev16_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev16_m8_0[] = { + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_128rev16_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_128rev16_m32_0[] = { + 0xffff & 0xffff, + 0xffff & 0xffff, + 0xcccc & 0xffff, + 0xcccc & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0x33 & 0xffff, + 0x33 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xcc & 0xffff, + 0xcc & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_128rev16_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_128rev16_m16_0[] = { + 0xffff & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xf0ff & 0xffff, + 0xf0ff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev32_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev32_m64_0[] = { + 0xf00 & 0xffff, + 0xf00 & 0xffff, + 0xf00 & 0xffff, + 0xf00 & 0xffff, + 0xf000 & 0xffff, + 0xf000 & 0xffff, + 0xf000 & 0xffff, + 0xf000 & 0xffff, + 0xf & 0xffff, + 0xf & 0xffff, + 0xf & 0xffff, + 0xf & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev32_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev32_m32_0[] = { + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev64_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev64_m64_0[] = { + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_r16_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_r16_m64_0[] = { + 0x300 & 0xffff, + 0x300 & 0xffff, + 0xc00 & 0xffff, + 0xc00 & 0xffff, + 0x3000 & 0xffff, + 0x3000 & 0xffff, + 0xc000 & 0xffff, + 0xc000 & 0xffff, + 0x3 & 0xffff, + 0x3 & 0xffff, + 0xc & 0xffff, + 0xc & 0xffff, + 0x30 & 0xffff, + 0x30 & 0xffff, + 0xc0 & 0xffff, + 0xc0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_r16_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_r16_m32_0[] = { + 0x3030 & 0xffff, + 0x3030 & 0xffff, + 0xc0c0 & 0xffff, + 0xc0c0 & 0xffff, + 0x303 & 0xffff, + 0x303 & 0xffff, + 0xc0c & 0xffff, + 0xc0c & 0xffff, + 0x3030 & 0xffff, + 0x3030 & 0xffff, + 0xc0c0 & 0xffff, + 0xc0c0 & 0xffff, + 0x303 & 0xffff, + 0x303 & 0xffff, + 0xc0c & 0xffff, + 0xc0c & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_r16_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_r16_m16_0[] = { + 0xcccc & 0xffff, + 0xcccc & 0xffff, + 0x3333 & 0xffff, + 0x3333 & 0xffff, + 0xcccc & 0xffff, + 0xcccc & 0xffff, + 0x3333 & 0xffff, + 0x3333 & 0xffff, + 0xcccc & 0xffff, + 0xcccc & 0xffff, + 0x3333 & 0xffff, + 0x3333 & 0xffff, + 0xcccc & 0xffff, + 0xcccc & 0xffff, + 0x3333 & 0xffff, + 0x3333 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_shiftrot_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_shiftrot_m64_0[] = { + 0 & 0xffff, + 0x101 & 0xffff, + 0x303 & 0xffff, + 0x707 & 0xffff, + 0xf0f & 0xffff, + 0x1f1f & 0xffff, + 0x3f3f & 0xffff, + 0x7f7f & 0xffff, + 0xffff & 0xffff, + 0xfefe & 0xffff, + 0xfcfc & 0xffff, + 0xf8f8 & 0xffff, + 0xf0f0 & 0xffff, + 0xe0e0 & 0xffff, + 0xc0c0 & 0xffff, + 0x8080 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_shiftrot_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_shiftrot_m32_0[] = { + 0 & 0xffff, + 0x1111 & 0xffff, + 0x3333 & 0xffff, + 0x7777 & 0xffff, + 0xffff & 0xffff, + 0xeeee & 0xffff, + 0xcccc & 0xffff, + 0x8888 & 0xffff, + 0 & 0xffff, + 0x1111 & 0xffff, + 0x3333 & 0xffff, + 0x7777 & 0xffff, + 0xffff & 0xffff, + 0xeeee & 0xffff, + 0xcccc & 0xffff, + 0x8888 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_shiftrot_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_shiftrot_m16_0[] = { + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_shiftrot_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_shiftrot_m8_0[] = { + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to16_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to16_m64_0[] = { + 0xf000 & 0xffff, + 0xe000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 & 0xffff, + 0x1 & 0xffff, + 0x3 & 0xffff, + 0x7 & 0xffff, + 0xf & 0xffff, + 0x11e & 0xffff, + 0x33c & 0xffff, + 0x778 & 0xffff, + 0xff0 & 0xffff, + 0x1ee0 & 0xffff, + 0x3cc0 & 0xffff, + 0x7880 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to16_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to16_m32_0[] = { + 0x3c0 & 0xffff, + 0x1680 & 0xffff, + 0x3c00 & 0xffff, + 0x6801 & 0xffff, + 0xc003 & 0xffff, + 0x8016 & 0xffff, + 0x3c & 0xffff, + 0x168 & 0xffff, + 0x3c0 & 0xffff, + 0x1680 & 0xffff, + 0x3c00 & 0xffff, + 0x6801 & 0xffff, + 0xc003 & 0xffff, + 0x8016 & 0xffff, + 0x3c & 0xffff, + 0x168 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to16_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to16_m16_0[] = { + 0x1818 & 0xffff, + 0x6060 & 0xffff, + 0x8181 & 0xffff, + 0x606 & 0xffff, + 0x1818 & 0xffff, + 0x6060 & 0xffff, + 0x8181 & 0xffff, + 0x606 & 0xffff, + 0x1818 & 0xffff, + 0x6060 & 0xffff, + 0x8181 & 0xffff, + 0x606 & 0xffff, + 0x1818 & 0xffff, + 0x6060 & 0xffff, + 0x8181 & 0xffff, + 0x606 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to16_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to16_m8_0[] = { + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp16to32_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp16to32_m16_0[] = { + 0x3838 & 0xffff, + 0x6161 & 0xffff, + 0x8383 & 0xffff, + 0x1616 & 0xffff, + 0x3838 & 0xffff, + 0x6161 & 0xffff, + 0x8383 & 0xffff, + 0x1616 & 0xffff, + 0x3838 & 0xffff, + 0x6161 & 0xffff, + 0x8383 & 0xffff, + 0x1616 & 0xffff, + 0x3838 & 0xffff, + 0x6161 & 0xffff, + 0x8383 & 0xffff, + 0x1616 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp16to32_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp16to32_m8_0[] = { + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to32_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to32_m64_0[] = { + 0xc00 & 0xffff, + 0x1800 & 0xffff, + 0x3000 & 0xffff, + 0x6000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 & 0xffff, + 0x1 & 0xffff, + 0x3 & 0xffff, + 0x6 & 0xffff, + 0xc & 0xffff, + 0x18 & 0xffff, + 0x30 & 0xffff, + 0x160 & 0xffff, + 0x3c0 & 0xffff, + 0x680 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to32_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to32_m32_0[] = { + 0x8020 & 0xffff, + 0x40 & 0xffff, + 0x180 & 0xffff, + 0x200 & 0xffff, + 0x401 & 0xffff, + 0x1802 & 0xffff, + 0x2004 & 0xffff, + 0x4018 & 0xffff, + 0x8020 & 0xffff, + 0x40 & 0xffff, + 0x180 & 0xffff, + 0x200 & 0xffff, + 0x401 & 0xffff, + 0x1802 & 0xffff, + 0x2004 & 0xffff, + 0x4018 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to32_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to32_m16_0[] = { + 0x2184 & 0xffff, + 0x4218 & 0xffff, + 0x8421 & 0xffff, + 0x1842 & 0xffff, + 0x2184 & 0xffff, + 0x4218 & 0xffff, + 0x8421 & 0xffff, + 0x1842 & 0xffff, + 0x2184 & 0xffff, + 0x4218 & 0xffff, + 0x8421 & 0xffff, + 0x1842 & 0xffff, + 0x2184 & 0xffff, + 0x4218 & 0xffff, + 0x8421 & 0xffff, + 0x1842 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to32_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to32_m8_0[] = { + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp16to32h_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp16to32h_m16_0[] = { + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr16to8_m8 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr16to8_m8_0[] = { + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr16to8_m16 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr16to8_m16_0[] = { + 0x4242 & 0xffff, + 0x9090 & 0xffff, + 0x2424 & 0xffff, + 0x909 & 0xffff, + 0x4242 & 0xffff, + 0x9090 & 0xffff, + 0x2424 & 0xffff, + 0x909 & 0xffff, + 0x4242 & 0xffff, + 0x9090 & 0xffff, + 0x2424 & 0xffff, + 0x909 & 0xffff, + 0x4242 & 0xffff, + 0x9090 & 0xffff, + 0x2424 & 0xffff, + 0x909 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr16to8_m32 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr16to8_m32_0[] = { + 0x300c & 0xffff, + 0x6108 & 0xffff, + 0xc300 & 0xffff, + 0x8610 & 0xffff, + 0xc30 & 0xffff, + 0x861 & 0xffff, + 0xc3 & 0xffff, + 0x1086 & 0xffff, + 0x300c & 0xffff, + 0x6108 & 0xffff, + 0xc300 & 0xffff, + 0x8610 & 0xffff, + 0xc30 & 0xffff, + 0x861 & 0xffff, + 0xc3 & 0xffff, + 0x1086 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr16to8_m64 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr16to8_m64_0[] = { + 0xf0 & 0xffff, + 0xe0 & 0xffff, + 0xc0 & 0xffff, + 0x80 & 0xffff, + 0 & 0xffff, + 0x100 & 0xffff, + 0x300 & 0xffff, + 0x700 & 0xffff, + 0xf00 & 0xffff, + 0x1e01 & 0xffff, + 0x3c03 & 0xffff, + 0x7807 & 0xffff, + 0xf00f & 0xffff, + 0xe01e & 0xffff, + 0xc03c & 0xffff, + 0x8078 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to8_m8 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to8_m8_0[] = { + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to8_m16 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to8_m16_0[] = { + 0x8400 & 0xffff, + 0x840 & 0xffff, + 0x84 & 0xffff, + 0x4008 & 0xffff, + 0x8400 & 0xffff, + 0x840 & 0xffff, + 0x84 & 0xffff, + 0x4008 & 0xffff, + 0x8400 & 0xffff, + 0x840 & 0xffff, + 0x84 & 0xffff, + 0x4008 & 0xffff, + 0x8400 & 0xffff, + 0x840 & 0xffff, + 0x84 & 0xffff, + 0x4008 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to8_m32 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to8_m32_0[] = { + 0x802 & 0xffff, + 0x4 & 0xffff, + 0x1008 & 0xffff, + 0x2000 & 0xffff, + 0x4010 & 0xffff, + 0x8120 & 0xffff, + 0x240 & 0xffff, + 0x481 & 0xffff, + 0x802 & 0xffff, + 0x4 & 0xffff, + 0x1008 & 0xffff, + 0x2000 & 0xffff, + 0x4010 & 0xffff, + 0x8120 & 0xffff, + 0x240 & 0xffff, + 0x481 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to8_m64 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to8_m64_0[] = { + 0xc & 0xffff, + 0x18 & 0xffff, + 0x30 & 0xffff, + 0x60 & 0xffff, + 0xc0 & 0xffff, + 0x80 & 0xffff, + 0 & 0xffff, + 0x100 & 0xffff, + 0x300 & 0xffff, + 0x600 & 0xffff, + 0xc00 & 0xffff, + 0x1800 & 0xffff, + 0x3000 & 0xffff, + 0x6001 & 0xffff, + 0xc003 & 0xffff, + 0x8006 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to16_m8 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to16_m8_0[] = { + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to16_m16 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to16_m16_0[] = { + 0xc0c0 & 0xffff, + 0x8484 & 0xffff, + 0xc0c & 0xffff, + 0x4848 & 0xffff, + 0xc0c0 & 0xffff, + 0x8484 & 0xffff, + 0xc0c & 0xffff, + 0x4848 & 0xffff, + 0xc0c0 & 0xffff, + 0x8484 & 0xffff, + 0xc0c & 0xffff, + 0x4848 & 0xffff, + 0xc0c0 & 0xffff, + 0x8484 & 0xffff, + 0xc0c & 0xffff, + 0x4848 & 0xffff, + 0 +}; + +/* constant table bitmask16rev */ +static const unsigned CONST_TBL_bitmask16rev_0[] = { + 0xffff & 0xffff, + 0xfffe & 0xffff, + 0xfffc & 0xffff, + 0xfff8 & 0xffff, + 0xfff0 & 0xffff, + 0xffe0 & 0xffff, + 0xffc0 & 0xffff, + 0xff80 & 0xffff, + 0xff00 & 0xffff, + 0xfe00 & 0xffff, + 0xfc00 & 0xffff, + 0xf800 & 0xffff, + 0xf000 & 0xffff, + 0xe000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 +}; + +/* constant table bitmask16sbe */ +static const unsigned CONST_TBL_bitmask16sbe_0[] = { + 0xfffe & 0xffff, + 0xfffc & 0xffff, + 0xfff8 & 0xffff, + 0xfff0 & 0xffff, + 0xffe0 & 0xffff, + 0xffc0 & 0xffff, + 0xff80 & 0xffff, + 0xff00 & 0xffff, + 0xfe00 & 0xffff, + 0xfc00 & 0xffff, + 0xf800 & 0xffff, + 0xf000 & 0xffff, + 0xe000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table bitmask16rxp */ +static const unsigned CONST_TBL_bitmask16rxp_0[] = { + 0 & 0xffff, + 0x8000 & 0xffff, + 0xc000 & 0xffff, + 0xe000 & 0xffff, + 0xf000 & 0xffff, + 0xf800 & 0xffff, + 0xfc00 & 0xffff, + 0xfe00 & 0xffff, + 0xff00 & 0xffff, + 0xff80 & 0xffff, + 0xffc0 & 0xffff, + 0xffe0 & 0xffff, + 0xfff0 & 0xffff, + 0xfff8 & 0xffff, + 0xfffc & 0xffff, + 0xfffe & 0xffff, + 0 +}; + + +/* Instruction operands. */ + +static int +OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) +{ + unsigned soffsetx4_out_0; + unsigned soffsetx4_in_0; + soffsetx4_in_0 = *valp & 0x3ffff; + soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); + *valp = soffsetx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) +{ + unsigned soffsetx4_in_0; + unsigned soffsetx4_out_0; + soffsetx4_out_0 = *valp; + soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; + *valp = soffsetx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_immr_decode (uint32 *valp) +{ + unsigned immr_out_0; + unsigned immr_in_0; + immr_in_0 = *valp & 0xf; + immr_out_0 = immr_in_0; + *valp = immr_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immr_encode (uint32 *valp) +{ + unsigned immr_in_0; + unsigned immr_out_0; + immr_out_0 = *valp; + immr_in_0 = (immr_out_0 & 0xf); + *valp = immr_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) +{ + unsigned uimm12x8_out_0; + unsigned uimm12x8_in_0; + uimm12x8_in_0 = *valp & 0xfff; + uimm12x8_out_0 = uimm12x8_in_0 << 3; + *valp = uimm12x8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) +{ + unsigned uimm12x8_in_0; + unsigned uimm12x8_out_0; + uimm12x8_out_0 = *valp; + uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); + *valp = uimm12x8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_decode (uint32 *valp) +{ + unsigned simm4_out_0; + unsigned simm4_in_0; + simm4_in_0 = *valp & 0xf; + simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; + *valp = simm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_encode (uint32 *valp) +{ + unsigned simm4_in_0; + unsigned simm4_out_0; + simm4_out_0 = *valp; + simm4_in_0 = (simm4_out_0 & 0xf); + *valp = simm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_0_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_4_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_8_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_8_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_12_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_12_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_entry_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_immrx4_decode (uint32 *valp) +{ + unsigned immrx4_out_0; + unsigned immrx4_in_0; + immrx4_in_0 = *valp & 0xf; + immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; + *valp = immrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immrx4_encode (uint32 *valp) +{ + unsigned immrx4_in_0; + unsigned immrx4_out_0; + immrx4_out_0 = *valp; + immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); + *valp = immrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) +{ + unsigned lsi4x4_out_0; + unsigned lsi4x4_in_0; + lsi4x4_in_0 = *valp & 0xf; + lsi4x4_out_0 = lsi4x4_in_0 << 2; + *valp = lsi4x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) +{ + unsigned lsi4x4_in_0; + unsigned lsi4x4_out_0; + lsi4x4_out_0 = *valp; + lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); + *valp = lsi4x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_decode (uint32 *valp) +{ + unsigned simm7_out_0; + unsigned simm7_in_0; + simm7_in_0 = *valp & 0x7f; + simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; + *valp = simm7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_encode (uint32 *valp) +{ + unsigned simm7_in_0; + unsigned simm7_out_0; + simm7_out_0 = *valp; + simm7_in_0 = (simm7_out_0 & 0x7f); + *valp = simm7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_decode (uint32 *valp) +{ + unsigned uimm6_out_0; + unsigned uimm6_in_0; + uimm6_in_0 = *valp & 0x3f; + uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); + *valp = uimm6_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_encode (uint32 *valp) +{ + unsigned uimm6_in_0; + unsigned uimm6_out_0; + uimm6_out_0 = *valp; + uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; + *valp = uimm6_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_decode (uint32 *valp) +{ + unsigned ai4const_out_0; + unsigned ai4const_in_0; + ai4const_in_0 = *valp & 0xf; + ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; + *valp = ai4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_encode (uint32 *valp) +{ + unsigned ai4const_in_0; + unsigned ai4const_out_0; + ai4const_out_0 = *valp; + switch (ai4const_out_0) + { + case 0xffffffff: ai4const_in_0 = 0; break; + case 0x1: ai4const_in_0 = 0x1; break; + case 0x2: ai4const_in_0 = 0x2; break; + case 0x3: ai4const_in_0 = 0x3; break; + case 0x4: ai4const_in_0 = 0x4; break; + case 0x5: ai4const_in_0 = 0x5; break; + case 0x6: ai4const_in_0 = 0x6; break; + case 0x7: ai4const_in_0 = 0x7; break; + case 0x8: ai4const_in_0 = 0x8; break; + case 0x9: ai4const_in_0 = 0x9; break; + case 0xa: ai4const_in_0 = 0xa; break; + case 0xb: ai4const_in_0 = 0xb; break; + case 0xc: ai4const_in_0 = 0xc; break; + case 0xd: ai4const_in_0 = 0xd; break; + case 0xe: ai4const_in_0 = 0xe; break; + default: ai4const_in_0 = 0xf; break; + } + *valp = ai4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_decode (uint32 *valp) +{ + unsigned b4const_out_0; + unsigned b4const_in_0; + b4const_in_0 = *valp & 0xf; + b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; + *valp = b4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_encode (uint32 *valp) +{ + unsigned b4const_in_0; + unsigned b4const_out_0; + b4const_out_0 = *valp; + switch (b4const_out_0) + { + case 0xffffffff: b4const_in_0 = 0; break; + case 0x1: b4const_in_0 = 0x1; break; + case 0x2: b4const_in_0 = 0x2; break; + case 0x3: b4const_in_0 = 0x3; break; + case 0x4: b4const_in_0 = 0x4; break; + case 0x5: b4const_in_0 = 0x5; break; + case 0x6: b4const_in_0 = 0x6; break; + case 0x7: b4const_in_0 = 0x7; break; + case 0x8: b4const_in_0 = 0x8; break; + case 0xa: b4const_in_0 = 0x9; break; + case 0xc: b4const_in_0 = 0xa; break; + case 0x10: b4const_in_0 = 0xb; break; + case 0x20: b4const_in_0 = 0xc; break; + case 0x40: b4const_in_0 = 0xd; break; + case 0x80: b4const_in_0 = 0xe; break; + default: b4const_in_0 = 0xf; break; + } + *valp = b4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_decode (uint32 *valp) +{ + unsigned b4constu_out_0; + unsigned b4constu_in_0; + b4constu_in_0 = *valp & 0xf; + b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; + *valp = b4constu_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_encode (uint32 *valp) +{ + unsigned b4constu_in_0; + unsigned b4constu_out_0; + b4constu_out_0 = *valp; + switch (b4constu_out_0) + { + case 0x8000: b4constu_in_0 = 0; break; + case 0x10000: b4constu_in_0 = 0x1; break; + case 0x2: b4constu_in_0 = 0x2; break; + case 0x3: b4constu_in_0 = 0x3; break; + case 0x4: b4constu_in_0 = 0x4; break; + case 0x5: b4constu_in_0 = 0x5; break; + case 0x6: b4constu_in_0 = 0x6; break; + case 0x7: b4constu_in_0 = 0x7; break; + case 0x8: b4constu_in_0 = 0x8; break; + case 0xa: b4constu_in_0 = 0x9; break; + case 0xc: b4constu_in_0 = 0xa; break; + case 0x10: b4constu_in_0 = 0xb; break; + case 0x20: b4constu_in_0 = 0xc; break; + case 0x40: b4constu_in_0 = 0xd; break; + case 0x80: b4constu_in_0 = 0xe; break; + default: b4constu_in_0 = 0xf; break; + } + *valp = b4constu_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_decode (uint32 *valp) +{ + unsigned immt_out_0; + unsigned immt_in_0; + immt_in_0 = *valp & 0xf; + immt_out_0 = immt_in_0; + *valp = immt_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_encode (uint32 *valp) +{ + unsigned immt_in_0; + unsigned immt_out_0; + immt_out_0 = *valp; + immt_in_0 = immt_out_0 & 0xf; + *valp = immt_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimms8_decode (uint32 *valp) +{ + unsigned uimms8_out_0; + unsigned uimms8_in_0; + uimms8_in_0 = *valp & 0x7; + uimms8_out_0 = uimms8_in_0; + *valp = uimms8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimms8_encode (uint32 *valp) +{ + unsigned uimms8_in_0; + unsigned uimms8_out_0; + uimms8_out_0 = *valp; + uimms8_in_0 = uimms8_out_0 & 0x7; + *valp = uimms8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_decode (uint32 *valp) +{ + unsigned uimm8_out_0; + unsigned uimm8_in_0; + uimm8_in_0 = *valp & 0xff; + uimm8_out_0 = uimm8_in_0; + *valp = uimm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_encode (uint32 *valp) +{ + unsigned uimm8_in_0; + unsigned uimm8_out_0; + uimm8_out_0 = *valp; + uimm8_in_0 = (uimm8_out_0 & 0xff); + *valp = uimm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) +{ + unsigned uimm8x2_out_0; + unsigned uimm8x2_in_0; + uimm8x2_in_0 = *valp & 0xff; + uimm8x2_out_0 = uimm8x2_in_0 << 1; + *valp = uimm8x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) +{ + unsigned uimm8x2_in_0; + unsigned uimm8x2_out_0; + uimm8x2_out_0 = *valp; + uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); + *valp = uimm8x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) +{ + unsigned uimm8x4_out_0; + unsigned uimm8x4_in_0; + uimm8x4_in_0 = *valp & 0xff; + uimm8x4_out_0 = uimm8x4_in_0 << 2; + *valp = uimm8x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) +{ + unsigned uimm8x4_in_0; + unsigned uimm8x4_out_0; + uimm8x4_out_0 = *valp; + uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); + *valp = uimm8x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) +{ + unsigned uimm4x16_out_0; + unsigned uimm4x16_in_0; + uimm4x16_in_0 = *valp & 0xf; + uimm4x16_out_0 = ((0 << 4) | uimm4x16_in_0) << 4; + *valp = uimm4x16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) +{ + unsigned uimm4x16_in_0; + unsigned uimm4x16_out_0; + uimm4x16_out_0 = *valp; + uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); + *valp = uimm4x16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp) +{ + unsigned uimmrx4_out_0; + unsigned uimmrx4_in_0; + uimmrx4_in_0 = *valp & 0xf; + uimmrx4_out_0 = ((0 << 4) | uimmrx4_in_0) << 2; + *valp = uimmrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp) +{ + unsigned uimmrx4_in_0; + unsigned uimmrx4_out_0; + uimmrx4_out_0 = *valp; + uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf); + *valp = uimmrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_decode (uint32 *valp) +{ + unsigned simm8_out_0; + unsigned simm8_in_0; + simm8_in_0 = *valp & 0xff; + simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; + *valp = simm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_encode (uint32 *valp) +{ + unsigned simm8_in_0; + unsigned simm8_out_0; + simm8_out_0 = *valp; + simm8_in_0 = (simm8_out_0 & 0xff); + *valp = simm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) +{ + unsigned simm8x256_out_0; + unsigned simm8x256_in_0; + simm8x256_in_0 = *valp & 0xff; + simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; + *valp = simm8x256_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) +{ + unsigned simm8x256_in_0; + unsigned simm8x256_out_0; + simm8x256_out_0 = *valp; + simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); + *valp = simm8x256_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_decode (uint32 *valp) +{ + unsigned simm12b_out_0; + unsigned simm12b_in_0; + simm12b_in_0 = *valp & 0xfff; + simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; + *valp = simm12b_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_encode (uint32 *valp) +{ + unsigned simm12b_in_0; + unsigned simm12b_out_0; + simm12b_out_0 = *valp; + simm12b_in_0 = (simm12b_out_0 & 0xfff); + *valp = simm12b_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_decode (uint32 *valp) +{ + unsigned msalp32_out_0; + unsigned msalp32_in_0; + msalp32_in_0 = *valp & 0x1f; + msalp32_out_0 = 0x20 - msalp32_in_0; + *valp = msalp32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_encode (uint32 *valp) +{ + unsigned msalp32_in_0; + unsigned msalp32_out_0; + msalp32_out_0 = *valp; + msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; + *valp = msalp32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_out_0; + unsigned op2p1_in_0; + op2p1_in_0 = *valp & 0xf; + op2p1_out_0 = op2p1_in_0 + 0x1; + *valp = op2p1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_encode (uint32 *valp) +{ + unsigned op2p1_in_0; + unsigned op2p1_out_0; + op2p1_out_0 = *valp; + op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; + *valp = op2p1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_decode (uint32 *valp) +{ + unsigned label8_out_0; + unsigned label8_in_0; + label8_in_0 = *valp & 0xff; + label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); + *valp = label8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_encode (uint32 *valp) +{ + unsigned label8_in_0; + unsigned label8_out_0; + label8_out_0 = *valp; + label8_in_0 = (label8_out_0 - 0x4) & 0xff; + *valp = label8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_decode (uint32 *valp) +{ + unsigned ulabel8_out_0; + unsigned ulabel8_in_0; + ulabel8_in_0 = *valp & 0xff; + ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0); + *valp = ulabel8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_encode (uint32 *valp) +{ + unsigned ulabel8_in_0; + unsigned ulabel8_out_0; + ulabel8_out_0 = *valp; + ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff; + *valp = ulabel8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_decode (uint32 *valp) +{ + unsigned label12_out_0; + unsigned label12_in_0; + label12_in_0 = *valp & 0xfff; + label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); + *valp = label12_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_encode (uint32 *valp) +{ + unsigned label12_in_0; + unsigned label12_out_0; + label12_out_0 = *valp; + label12_in_0 = (label12_out_0 - 0x4) & 0xfff; + *valp = label12_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_decode (uint32 *valp) +{ + unsigned soffset_out_0; + unsigned soffset_in_0; + soffset_in_0 = *valp & 0x3ffff; + soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); + *valp = soffset_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_encode (uint32 *valp) +{ + unsigned soffset_in_0; + unsigned soffset_out_0; + soffset_out_0 = *valp; + soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; + *valp = soffset_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) +{ + unsigned uimm16x4_out_0; + unsigned uimm16x4_in_0; + uimm16x4_in_0 = *valp & 0xffff; + uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; + *valp = uimm16x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) +{ + unsigned uimm16x4_in_0; + unsigned uimm16x4_out_0; + uimm16x4_out_0 = *valp; + uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; + *valp = uimm16x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_decode (uint32 *valp) +{ + unsigned bbi_out_0; + unsigned bbi_in_0; + bbi_in_0 = *valp & 0x1f; + bbi_out_0 = (0 << 5) | bbi_in_0; + *valp = bbi_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_encode (uint32 *valp) +{ + unsigned bbi_in_0; + unsigned bbi_out_0; + bbi_out_0 = *valp; + bbi_in_0 = (bbi_out_0 & 0x1f); + *valp = bbi_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_decode (uint32 *valp) +{ + unsigned s_out_0; + unsigned s_in_0; + s_in_0 = *valp & 0xf; + s_out_0 = (0 << 4) | s_in_0; + *valp = s_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_encode (uint32 *valp) +{ + unsigned s_in_0; + unsigned s_out_0; + s_out_0 = *valp; + s_in_0 = (s_out_0 & 0xf); + *valp = s_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_imms_decode (uint32 *valp) +{ + unsigned imms_out_0; + unsigned imms_in_0; + imms_in_0 = *valp & 0xf; + imms_out_0 = imms_in_0; + *valp = imms_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_imms_encode (uint32 *valp) +{ + unsigned imms_in_0; + unsigned imms_out_0; + imms_out_0 = *valp; + imms_in_0 = imms_out_0 & 0xf; + *valp = imms_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_BR_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16); + return error; +} + +static int +OperandSem_opnd_sem_BR2_decode (uint32 *valp) +{ + *valp = *valp << 1; + return 0; +} + +static int +OperandSem_opnd_sem_BR2_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 1) != 0); + *valp = *valp >> 1; + return error; +} + +static int +OperandSem_opnd_sem_BR4_decode (uint32 *valp) +{ + *valp = *valp << 2; + return 0; +} + +static int +OperandSem_opnd_sem_BR4_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 3) != 0); + *valp = *valp >> 2; + return error; +} + +static int +OperandSem_opnd_sem_BR8_decode (uint32 *valp) +{ + *valp = *valp << 3; + return 0; +} + +static int +OperandSem_opnd_sem_BR8_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 7) != 0); + *valp = *valp >> 3; + return error; +} + +static int +OperandSem_opnd_sem_BR16_decode (uint32 *valp) +{ + *valp = *valp << 4; + return 0; +} + +static int +OperandSem_opnd_sem_BR16_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 15) != 0); + *valp = *valp >> 4; + return error; +} + +static int +OperandSem_opnd_sem_tp7_decode (uint32 *valp) +{ + unsigned tp7_out_0; + unsigned tp7_in_0; + tp7_in_0 = *valp & 0xf; + tp7_out_0 = tp7_in_0 + 0x7; + *valp = tp7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_tp7_encode (uint32 *valp) +{ + unsigned tp7_in_0; + unsigned tp7_out_0; + tp7_out_0 = *valp; + tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; + *valp = tp7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) +{ + unsigned xt_wbr15_label_out_0; + unsigned xt_wbr15_label_in_0; + xt_wbr15_label_in_0 = *valp & 0x7fff; + xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); + *valp = xt_wbr15_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) +{ + unsigned xt_wbr15_label_in_0; + unsigned xt_wbr15_label_out_0; + xt_wbr15_label_out_0 = *valp; + xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; + *valp = xt_wbr15_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp) +{ + unsigned xt_wbr18_label_out_0; + unsigned xt_wbr18_label_in_0; + xt_wbr18_label_in_0 = *valp & 0x3ffff; + xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14); + *valp = xt_wbr18_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp) +{ + unsigned xt_wbr18_label_in_0; + unsigned xt_wbr18_label_out_0; + xt_wbr18_label_out_0 = *valp; + xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff; + *valp = xt_wbr18_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_uimm2x2_decode (uint32 *valp) +{ + unsigned ae_uimm2x2_out_0; + unsigned ae_uimm2x2_in_0; + ae_uimm2x2_in_0 = *valp & 0x1; + ae_uimm2x2_out_0 = (0 << 2) | (ae_uimm2x2_in_0 << 1) | 0; + *valp = ae_uimm2x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_uimm2x2_encode (uint32 *valp) +{ + unsigned ae_uimm2x2_in_0; + unsigned ae_uimm2x2_out_0; + ae_uimm2x2_out_0 = *valp; + ae_uimm2x2_in_0 = (((ae_uimm2x2_out_0 >> 1) & 1)) & 0x1; + *valp = ae_uimm2x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AE_DR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_DR_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64_out_0; + unsigned opnd_ae_sem_loads_stores_i64_in_0; + opnd_ae_sem_loads_stores_i64_in_0 = *valp & 0xf; + opnd_ae_sem_loads_stores_i64_out_0 = (((int) opnd_ae_sem_loads_stores_i64_in_0 << 28) >> 28) << 3; + *valp = opnd_ae_sem_loads_stores_i64_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64_in_0; + unsigned opnd_ae_sem_loads_stores_i64_out_0; + opnd_ae_sem_loads_stores_i64_out_0 = *valp; + opnd_ae_sem_loads_stores_i64_in_0 = ((opnd_ae_sem_loads_stores_i64_out_0 >> 3) & 0xf); + *valp = opnd_ae_sem_loads_stores_i64_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_sb_loads_stores_iba_out_0; + unsigned opnd_ae_sem_sb_loads_stores_iba_in_0; + opnd_ae_sem_sb_loads_stores_iba_in_0 = *valp & 0xf; + opnd_ae_sem_sb_loads_stores_iba_out_0 = CONST_TBL_ae_ohba_0[opnd_ae_sem_sb_loads_stores_iba_in_0 & 0xf]; + *valp = opnd_ae_sem_sb_loads_stores_iba_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_sb_loads_stores_iba_in_0; + unsigned opnd_ae_sem_sb_loads_stores_iba_out_0; + opnd_ae_sem_sb_loads_stores_iba_out_0 = *valp; + switch (opnd_ae_sem_sb_loads_stores_iba_out_0) + { + case 0x1: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0; break; + case 0x2: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x1; break; + case 0x3: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x2; break; + case 0x4: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x3; break; + case 0x5: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x4; break; + case 0x6: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x5; break; + case 0x7: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x6; break; + case 0x8: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x7; break; + case 0x9: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x8; break; + case 0xa: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x9; break; + case 0xb: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xa; break; + case 0xc: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xb; break; + case 0xd: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xc; break; + case 0xe: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xd; break; + case 0xf: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xe; break; + default: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xf; break; + } + *valp = opnd_ae_sem_sb_loads_stores_iba_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_imm2_out_0; + unsigned opnd_ae_sem_loads_stores_imm2_in_0; + opnd_ae_sem_loads_stores_imm2_in_0 = *valp & 0x3; + opnd_ae_sem_loads_stores_imm2_out_0 = (0 << 2) | opnd_ae_sem_loads_stores_imm2_in_0; + *valp = opnd_ae_sem_loads_stores_imm2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_imm2_in_0; + unsigned opnd_ae_sem_loads_stores_imm2_out_0; + opnd_ae_sem_loads_stores_imm2_out_0 = *valp; + opnd_ae_sem_loads_stores_imm2_in_0 = (opnd_ae_sem_loads_stores_imm2_out_0 & 0x3); + *valp = opnd_ae_sem_loads_stores_imm2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_movi_imm_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_dr_to_dr_movi_imm_out_0; + unsigned opnd_ae_sem_dr_to_dr_movi_imm_in_0; + opnd_ae_sem_dr_to_dr_movi_imm_in_0 = *valp & 0x3f; + opnd_ae_sem_dr_to_dr_movi_imm_out_0 = (((-(( ( ((((opnd_ae_sem_dr_to_dr_movi_imm_in_0 >> 4) & 0x3)) | 0xfffffffc)) == 0xffffffff))) & 0x3ffffff) << 6) | opnd_ae_sem_dr_to_dr_movi_imm_in_0; + *valp = opnd_ae_sem_dr_to_dr_movi_imm_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_movi_imm_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_dr_to_dr_movi_imm_in_0; + unsigned opnd_ae_sem_dr_to_dr_movi_imm_out_0; + opnd_ae_sem_dr_to_dr_movi_imm_out_0 = *valp; + opnd_ae_sem_dr_to_dr_movi_imm_in_0 = (opnd_ae_sem_dr_to_dr_movi_imm_out_0 & 0x3f); + *valp = opnd_ae_sem_dr_to_dr_movi_imm_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_spfma_i_imm3_out_0; + unsigned opnd_ae_sem_spfma_i_imm3_in_0; + opnd_ae_sem_spfma_i_imm3_in_0 = *valp & 0x7; + opnd_ae_sem_spfma_i_imm3_out_0 = (0 << 3) | opnd_ae_sem_spfma_i_imm3_in_0; + *valp = opnd_ae_sem_spfma_i_imm3_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_spfma_i_imm3_in_0; + unsigned opnd_ae_sem_spfma_i_imm3_out_0; + opnd_ae_sem_spfma_i_imm3_out_0 = *valp; + opnd_ae_sem_spfma_i_imm3_in_0 = (opnd_ae_sem_spfma_i_imm3_out_0 & 0x7); + *valp = opnd_ae_sem_spfma_i_imm3_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AE_VALIGN_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_VALIGN_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i32_out_0; + unsigned opnd_ae_sem_loads_stores_i32_in_0; + opnd_ae_sem_loads_stores_i32_in_0 = *valp & 0xf; + opnd_ae_sem_loads_stores_i32_out_0 = (((int) opnd_ae_sem_loads_stores_i32_in_0 << 28) >> 28) << 2; + *valp = opnd_ae_sem_loads_stores_i32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i32_in_0; + unsigned opnd_ae_sem_loads_stores_i32_out_0; + opnd_ae_sem_loads_stores_i32_out_0 = *valp; + opnd_ae_sem_loads_stores_i32_in_0 = ((opnd_ae_sem_loads_stores_i32_out_0 >> 2) & 0xf); + *valp = opnd_ae_sem_loads_stores_i32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i16_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i16_out_0; + unsigned opnd_ae_sem_loads_stores_i16_in_0; + opnd_ae_sem_loads_stores_i16_in_0 = *valp & 0xf; + opnd_ae_sem_loads_stores_i16_out_0 = (((int) opnd_ae_sem_loads_stores_i16_in_0 << 28) >> 28) << 1; + *valp = opnd_ae_sem_loads_stores_i16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i16_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i16_in_0; + unsigned opnd_ae_sem_loads_stores_i16_out_0; + opnd_ae_sem_loads_stores_i16_out_0 = *valp; + opnd_ae_sem_loads_stores_i16_in_0 = ((opnd_ae_sem_loads_stores_i16_out_0 >> 1) & 0xf); + *valp = opnd_ae_sem_loads_stores_i16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i8_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i8_out_0; + unsigned opnd_ae_sem_loads_stores_i8_in_0; + opnd_ae_sem_loads_stores_i8_in_0 = *valp & 0xf; + opnd_ae_sem_loads_stores_i8_out_0 = ((int) opnd_ae_sem_loads_stores_i8_in_0 << 28) >> 28; + *valp = opnd_ae_sem_loads_stores_i8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i8_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i8_in_0; + unsigned opnd_ae_sem_loads_stores_i8_out_0; + opnd_ae_sem_loads_stores_i8_out_0 = *valp; + opnd_ae_sem_loads_stores_i8_in_0 = (opnd_ae_sem_loads_stores_i8_out_0 & 0xf); + *valp = opnd_ae_sem_loads_stores_i8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64pos_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64pos_out_0; + unsigned opnd_ae_sem_loads_stores_i64pos_in_0; + opnd_ae_sem_loads_stores_i64pos_in_0 = *valp & 0x7; + opnd_ae_sem_loads_stores_i64pos_out_0 = ((0 << 3) | opnd_ae_sem_loads_stores_i64pos_in_0) << 3; + *valp = opnd_ae_sem_loads_stores_i64pos_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64pos_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64pos_in_0; + unsigned opnd_ae_sem_loads_stores_i64pos_out_0; + opnd_ae_sem_loads_stores_i64pos_out_0 = *valp; + opnd_ae_sem_loads_stores_i64pos_in_0 = ((opnd_ae_sem_loads_stores_i64pos_out_0 >> 3) & 0x7); + *valp = opnd_ae_sem_loads_stores_i64pos_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64neg_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64neg_out_0; + unsigned opnd_ae_sem_loads_stores_i64neg_in_0; + opnd_ae_sem_loads_stores_i64neg_in_0 = *valp & 0x3; + opnd_ae_sem_loads_stores_i64neg_out_0 = CONST_TBL_ae_immls64neg_0[opnd_ae_sem_loads_stores_i64neg_in_0 & 0x3]; + *valp = opnd_ae_sem_loads_stores_i64neg_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64neg_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64neg_in_0; + unsigned opnd_ae_sem_loads_stores_i64neg_out_0; + opnd_ae_sem_loads_stores_i64neg_out_0 = *valp; + opnd_ae_sem_loads_stores_i64neg_in_0 = (((opnd_ae_sem_loads_stores_i64neg_out_0 == (CONST_TBL_ae_immls64neg_0[0]))) ? 0 : (((opnd_ae_sem_loads_stores_i64neg_out_0 == (CONST_TBL_ae_immls64neg_0[1]))) ? 0x1 : (((opnd_ae_sem_loads_stores_i64neg_out_0 == (CONST_TBL_ae_immls64neg_0[2]))) ? 0x2 : 0x3))) & 0x3; + *valp = opnd_ae_sem_loads_stores_i64neg_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64half_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64half_out_0; + unsigned opnd_ae_sem_loads_stores_i64half_in_0; + opnd_ae_sem_loads_stores_i64half_in_0 = *valp & 0x7; + opnd_ae_sem_loads_stores_i64half_out_0 = (((int) opnd_ae_sem_loads_stores_i64half_in_0 << 29) >> 29) << 3; + *valp = opnd_ae_sem_loads_stores_i64half_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64half_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64half_in_0; + unsigned opnd_ae_sem_loads_stores_i64half_out_0; + opnd_ae_sem_loads_stores_i64half_out_0 = *valp; + opnd_ae_sem_loads_stores_i64half_in_0 = ((opnd_ae_sem_loads_stores_i64half_out_0 >> 3) & 0x7); + *valp = opnd_ae_sem_loads_stores_i64half_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_hpcnv_i_imm4_out_0; + unsigned opnd_ae_sem_hpcnv_i_imm4_in_0; + opnd_ae_sem_hpcnv_i_imm4_in_0 = *valp & 0xf; + opnd_ae_sem_hpcnv_i_imm4_out_0 = (0 << 4) | opnd_ae_sem_hpcnv_i_imm4_in_0; + *valp = opnd_ae_sem_hpcnv_i_imm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_hpcnv_i_imm4_in_0; + unsigned opnd_ae_sem_hpcnv_i_imm4_out_0; + opnd_ae_sem_hpcnv_i_imm4_out_0 = *valp; + opnd_ae_sem_hpcnv_i_imm4_in_0 = (opnd_ae_sem_hpcnv_i_imm4_out_0 & 0xf); + *valp = opnd_ae_sem_hpcnv_i_imm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_sp32cvt_i_imm5_out_0; + unsigned opnd_ae_sem_sp32cvt_i_imm5_in_0; + opnd_ae_sem_sp32cvt_i_imm5_in_0 = *valp & 0x1f; + opnd_ae_sem_sp32cvt_i_imm5_out_0 = (0 << 5) | opnd_ae_sem_sp32cvt_i_imm5_in_0; + *valp = opnd_ae_sem_sp32cvt_i_imm5_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_sp32cvt_i_imm5_in_0; + unsigned opnd_ae_sem_sp32cvt_i_imm5_out_0; + opnd_ae_sem_sp32cvt_i_imm5_out_0 = *valp; + opnd_ae_sem_sp32cvt_i_imm5_in_0 = (opnd_ae_sem_sp32cvt_i_imm5_out_0 & 0x1f); + *valp = opnd_ae_sem_sp32cvt_i_imm5_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_shift_i64_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_shift_i64_out_0; + unsigned opnd_ae_sem_shift_i64_in_0; + opnd_ae_sem_shift_i64_in_0 = *valp & 0x3f; + opnd_ae_sem_shift_i64_out_0 = (0 << 6) | opnd_ae_sem_shift_i64_in_0; + *valp = opnd_ae_sem_shift_i64_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_shift_i64_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_shift_i64_in_0; + unsigned opnd_ae_sem_shift_i64_out_0; + opnd_ae_sem_shift_i64_out_0 = *valp; + opnd_ae_sem_shift_i64_in_0 = (opnd_ae_sem_shift_i64_out_0 & 0x3f); + *valp = opnd_ae_sem_shift_i64_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i128_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i128_out_0; + unsigned opnd_ae_sem_loads_stores_i128_in_0; + opnd_ae_sem_loads_stores_i128_in_0 = *valp & 0xf; + opnd_ae_sem_loads_stores_i128_out_0 = (((int) opnd_ae_sem_loads_stores_i128_in_0 << 28) >> 28) << 4; + *valp = opnd_ae_sem_loads_stores_i128_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i128_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i128_in_0; + unsigned opnd_ae_sem_loads_stores_i128_out_0; + opnd_ae_sem_loads_stores_i128_out_0 = *valp; + opnd_ae_sem_loads_stores_i128_in_0 = ((opnd_ae_sem_loads_stores_i128_out_0 >> 4) & 0xf); + *valp = opnd_ae_sem_loads_stores_i128_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AE_EP_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_EP_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_shift_i8_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_shift_i8_out_0; + unsigned opnd_ae_sem_shift_i8_in_0; + opnd_ae_sem_shift_i8_in_0 = *valp & 0x7; + opnd_ae_sem_shift_i8_out_0 = CONST_TBL_ae_slai72table_0[opnd_ae_sem_shift_i8_in_0 & 0x7]; + *valp = opnd_ae_sem_shift_i8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_shift_i8_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_shift_i8_in_0; + unsigned opnd_ae_sem_shift_i8_out_0; + opnd_ae_sem_shift_i8_out_0 = *valp; + switch (opnd_ae_sem_shift_i8_out_0) + { + case 0x1: opnd_ae_sem_shift_i8_in_0 = 0; break; + case 0x2: opnd_ae_sem_shift_i8_in_0 = 0x1; break; + case 0x3: opnd_ae_sem_shift_i8_in_0 = 0x2; break; + case 0x4: opnd_ae_sem_shift_i8_in_0 = 0x3; break; + case 0x5: opnd_ae_sem_shift_i8_in_0 = 0x4; break; + case 0x6: opnd_ae_sem_shift_i8_in_0 = 0x5; break; + case 0x7: opnd_ae_sem_shift_i8_in_0 = 0x6; break; + default: opnd_ae_sem_shift_i8_in_0 = 0x7; break; + } + *valp = opnd_ae_sem_shift_i8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_imm_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_dr_to_dr_imm_out_0; + unsigned opnd_ae_sem_dr_to_dr_imm_in_0; + opnd_ae_sem_dr_to_dr_imm_in_0 = *valp & 0xf; + opnd_ae_sem_dr_to_dr_imm_out_0 = CONST_TBL_ae_opnd_tp7_0[opnd_ae_sem_dr_to_dr_imm_in_0 & 0xf]; + *valp = opnd_ae_sem_dr_to_dr_imm_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_imm_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_dr_to_dr_imm_in_0; + unsigned opnd_ae_sem_dr_to_dr_imm_out_0; + opnd_ae_sem_dr_to_dr_imm_out_0 = *valp; + switch (opnd_ae_sem_dr_to_dr_imm_out_0) + { + case 0x7: opnd_ae_sem_dr_to_dr_imm_in_0 = 0; break; + case 0x8: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x1; break; + case 0x9: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x2; break; + case 0xa: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x3; break; + case 0xb: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x4; break; + case 0xc: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x5; break; + case 0xd: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x6; break; + case 0xe: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x7; break; + case 0xf: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x8; break; + case 0x10: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x9; break; + case 0x11: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xa; break; + case 0x12: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xb; break; + case 0x13: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xc; break; + case 0x14: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xd; break; + case 0x15: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xe; break; + default: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xf; break; + } + *valp = opnd_ae_sem_dr_to_dr_imm_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba2_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_sb_loads_stores_iba2_out_0; + unsigned opnd_ae_sem_sb_loads_stores_iba2_in_0; + opnd_ae_sem_sb_loads_stores_iba2_in_0 = *valp & 0xf; + opnd_ae_sem_sb_loads_stores_iba2_out_0 = CONST_TBL_ae_ohba2_0[opnd_ae_sem_sb_loads_stores_iba2_in_0 & 0xf]; + *valp = opnd_ae_sem_sb_loads_stores_iba2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba2_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_sb_loads_stores_iba2_in_0; + unsigned opnd_ae_sem_sb_loads_stores_iba2_out_0; + opnd_ae_sem_sb_loads_stores_iba2_out_0 = *valp; + switch (opnd_ae_sem_sb_loads_stores_iba2_out_0) + { + case 0x1: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0; break; + case 0x2: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x1; break; + case 0x3: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x2; break; + case 0x4: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x3; break; + case 0x5: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x4; break; + case 0x6: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x5; break; + case 0x7: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x6; break; + case 0x8: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x7; break; + case 0x9: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x8; break; + case 0xa: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x9; break; + case 0xb: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xa; break; + case 0xc: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xb; break; + case 0xd: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xc; break; + case 0xe: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xd; break; + case 0xf: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xe; break; + default: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xf; break; + } + *valp = opnd_ae_sem_sb_loads_stores_iba2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm1_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_spfma_i_imm1_out_0; + unsigned opnd_ae_sem_spfma_i_imm1_in_0; + opnd_ae_sem_spfma_i_imm1_in_0 = *valp & 0x1; + opnd_ae_sem_spfma_i_imm1_out_0 = (0 << 1) | opnd_ae_sem_spfma_i_imm1_in_0; + *valp = opnd_ae_sem_spfma_i_imm1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm1_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_spfma_i_imm1_in_0; + unsigned opnd_ae_sem_spfma_i_imm1_out_0; + opnd_ae_sem_spfma_i_imm1_out_0 = *valp; + opnd_ae_sem_spfma_i_imm1_in_0 = (((opnd_ae_sem_spfma_i_imm1_out_0 >> 0) & 1)) & 0x1; + *valp = opnd_ae_sem_spfma_i_imm1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bitindex_decode (uint32 *valp) +{ + unsigned bitindex_out_0; + unsigned bitindex_in_0; + bitindex_in_0 = *valp & 0x1f; + bitindex_out_0 = (0 << 5) | bitindex_in_0; + *valp = bitindex_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bitindex_encode (uint32 *valp) +{ + unsigned bitindex_in_0; + unsigned bitindex_out_0; + bitindex_out_0 = *valp; + bitindex_in_0 = (bitindex_out_0 & 0x1f); + *valp = bitindex_in_0; + return 0; +} + +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +{ + *valp -= (pc & ~0x3); + return 0; +} + +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += (pc & ~0x3); + return 0; +} + +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ulabel8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label12_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +{ + *valp -= ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static xtensa_operand_internal operands[] = { + { "soffsetx4", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa, + -1, 0 }, + { "immr", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_immr_encode, OperandSem_opnd_sem_immr_decode, + 0, 0, + -1, 0 }, + { "uimm12x8", FIELD_imm12, -1, 0, + 0, + OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, + 0, 0, + -1, 0 }, + { "simm4", FIELD_mn, -1, 0, + 0, + OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, + 0, 0, + -1, 0 }, + { "arr", FIELD_r, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "ars", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "*ars_invisible", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "art", FIELD_t, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "ar0", FIELD__ar0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, + 0, 0, + 0, 63 }, + { "ar4", FIELD__ar4, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, + 0, 0, + 0, 63 }, + { "ar8", FIELD__ar8, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_8_encode, OperandSem_opnd_sem_AR_8_decode, + 0, 0, + 0, 63 }, + { "ar12", FIELD__ar12, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_12_encode, OperandSem_opnd_sem_AR_12_decode, + 0, 0, + 0, 63 }, + { "ars_entry", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_entry_encode, OperandSem_opnd_sem_AR_entry_decode, + 0, 0, + 0, 63 }, + { "immrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, + 0, 0, + -1, 0 }, + { "lsi4x4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, + 0, 0, + -1, 0 }, + { "simm7", FIELD_imm7, -1, 0, + 0, + OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, + 0, 0, + -1, 0 }, + { "uimm6", FIELD_imm6, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa, + -1, 0 }, + { "ai4const", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, + 0, 0, + -1, 0 }, + { "b4const", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, + 0, 0, + -1, 0 }, + { "b4constu", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, + 0, 0, + -1, 0 }, + { "immt", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, + 0, 0, + -1, 0 }, + { "uimms8", FIELD_imms8, -1, 0, + 0, + OperandSem_opnd_sem_uimms8_encode, OperandSem_opnd_sem_uimms8_decode, + 0, 0, + -1, 0 }, + { "uimm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, + 0, 0, + -1, 0 }, + { "uimm8x2", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, + 0, 0, + -1, 0 }, + { "uimm8x4", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, + 0, 0, + -1, 0 }, + { "uimm4x16", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, + 0, 0, + -1, 0 }, + { "uimmrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode, + 0, 0, + -1, 0 }, + { "simm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, + 0, 0, + -1, 0 }, + { "simm8x256", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, + 0, 0, + -1, 0 }, + { "simm12b", FIELD_imm12b, -1, 0, + 0, + OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, + 0, 0, + -1, 0 }, + { "msalp32", FIELD_sal, -1, 0, + 0, + OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, + 0, 0, + -1, 0 }, + { "op2p1", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, + 0, 0, + -1, 0 }, + { "label8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, + Operand_label8_ator, Operand_label8_rtoa, + -1, 0 }, + { "ulabel8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode, + Operand_ulabel8_ator, Operand_ulabel8_rtoa, + -1, 0 }, + { "label12", FIELD_imm12, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, + Operand_label12_ator, Operand_label12_rtoa, + -1, 0 }, + { "soffset", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa, + -1, 0 }, + { "uimm16x4", FIELD_imm16, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa, + -1, 0 }, + { "bbi", FIELD_bbi, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "sae", FIELD_sae, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "sas", FIELD_sas, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "sargt", FIELD_sargt, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "s", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, + 0, 0, + -1, 0 }, + { "imms", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_imms_encode, OperandSem_opnd_sem_imms_decode, + 0, 0, + -1, 0 }, + { "imms1", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_imms_encode, OperandSem_opnd_sem_imms_decode, + 0, 0, + -1, 0 }, + { "bt", FIELD_t, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "bs", FIELD_s, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "br", FIELD_r, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "bt2", FIELD_t2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "bs2", FIELD_s2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "br2", FIELD_r2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "bt4", FIELD_t4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "bs4", FIELD_s4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "br4", FIELD_r4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "bt8", FIELD_t8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0, + 0, 15 }, + { "bs8", FIELD_s8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0, + 0, 15 }, + { "br8", FIELD_r8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0, + 0, 15 }, + { "bt16", FIELD__bt16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "bs16", FIELD__bs16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "br16", FIELD__br16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "brall", FIELD__brall, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "tp7", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, + 0, 0, + -1, 0 }, + { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa, + -1, 0 }, + { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode, + Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa, + -1, 0 }, + { "ae_uimm2x2", FIELD_ae_fld_Inst16b_12, -1, 0, + 0, + OperandSem_opnd_sem_ae_uimm2x2_encode, OperandSem_opnd_sem_ae_uimm2x2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_dr_v", FIELD_fld_ae_sem_dr_to_dr_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_arithmetic_v", FIELD_fld_ae_sem_arithmetic_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_arithmetic_v0", FIELD_fld_ae_sem_arithmetic_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_arithmetic_v1", FIELD_fld_ae_sem_arithmetic_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_a.0", FIELD_fld_ae_sem_loads_stores_a_0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_loads_stores_x", FIELD_fld_ae_sem_loads_stores_x, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_loads_stores_end", FIELD_fld_ae_sem_loads_stores_end, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_loads_stores_i64", FIELD_fld_ae_sem_loads_stores_i64, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_lb_ops_iba", FIELD_fld_ae_sem_lb_ops_iba, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_encode, OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_sb_loads_stores_iba", FIELD_fld_ae_sem_sb_loads_stores_iba, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_encode, OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_pks_d", FIELD_fld_ae_sem_pks_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_pks_pos", FIELD_fld_ae_sem_pks_pos, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_pks_s", FIELD_fld_ae_sem_pks_s, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_a", FIELD_fld_ae_sem_dr_to_ar_a, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_dr_to_ar_v0", FIELD_fld_ae_sem_dr_to_ar_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_v0", FIELD_fld_ae_sem_dr_to_dr_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_ab", FIELD_fld_ae_sem_dr_to_ar_ab, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_dr_to_ar_ai", FIELD_fld_ae_sem_dr_to_ar_ai, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_dr_to_ar_aoe", FIELD_fld_ae_sem_dr_to_ar_aoe, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_dr_to_dr_movi_imm", FIELD_fld_ae_sem_dr_to_dr_movi_imm, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_movi_imm_encode, OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_movi_imm_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_dr_ds", FIELD_fld_ae_sem_dr_to_dr_ds, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_v1", FIELD_fld_ae_sem_dr_to_dr_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_imm8", FIELD_fld_ae_sem_dr_to_ar_imm8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_encode, OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_a0", FIELD_fld_ae_sem_shift_a0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_shift_d", FIELD_fld_ae_sem_shift_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_shift_d0", FIELD_fld_ae_sem_shift_d0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_d", FIELD_fld_ae_sem_dr_to_ar_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_d0", FIELD_fld_ae_sem_dr_to_ar_d0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_d1", FIELD_fld_ae_sem_dr_to_ar_d1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_imm2", FIELD_fld_ae_sem_dr_to_dr_imm2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_arithmetic_ds", FIELD_fld_ae_sem_arithmetic_ds, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_uu", FIELD_fld_ae_sem_loads_stores_uu, REGFILE_AE_VALIGN, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_VALIGN_encode, OperandSem_opnd_sem_AE_VALIGN_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_loads_stores_vu", FIELD_fld_ae_sem_loads_stores_vu, REGFILE_AE_VALIGN, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_VALIGN_encode, OperandSem_opnd_sem_AE_VALIGN_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_loads_stores_i32", FIELD_fld_ae_sem_loads_stores_i32, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_v", FIELD_fld_ae_sem_loads_stores_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_i16", FIELD_fld_ae_sem_loads_stores_i16, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i16_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i16_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i8", FIELD_fld_ae_sem_loads_stores_i8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i8_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i8_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i64pos", FIELD_fld_ae_sem_loads_stores_i64pos, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64pos_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64pos_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i64neg", FIELD_fld_ae_sem_loads_stores_i64neg, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64neg_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64neg_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i64half", FIELD_fld_ae_sem_loads_stores_i64half, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64half_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64half_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_su", FIELD_fld_ae_sem_loads_stores_su, REGFILE_AE_VALIGN, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_VALIGN_encode, OperandSem_opnd_sem_AE_VALIGN_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_loads_stores_v1", FIELD_fld_ae_sem_loads_stores_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_av", FIELD_fld_ae_sem_loads_stores_av, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_shift_i16", FIELD_fld_ae_sem_shift_i16, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_encode, OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_i32", FIELD_fld_ae_sem_shift_i32, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_encode, OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_d1", FIELD_fld_ae_sem_shift_d1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_shift_da", FIELD_fld_ae_sem_shift_da, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_shift_imm32", FIELD_fld_ae_sem_shift_imm32, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_encode, OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_a", FIELD_fld_ae_sem_shift_a, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_shift_sd", FIELD_fld_ae_sem_shift_sd, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_shift_i64", FIELD_fld_ae_sem_shift_i64, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_shift_i64_encode, OperandSem_opnd_sem_opnd_ae_sem_shift_i64_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_imm8", FIELD_fld_ae_sem_shift_imm8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_encode, OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_dr_immed", FIELD_fld_ae_sem_dr_to_dr_immed, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_encode, OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_arithmetic_art", FIELD_fld_ae_sem_arithmetic_art, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_arithmetic_va", FIELD_fld_ae_sem_arithmetic_va, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_arithmetic_vs", FIELD_fld_ae_sem_arithmetic_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_i128", FIELD_fld_ae_sem_loads_stores_i128, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i128_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i128_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_av1", FIELD_fld_ae_sem_loads_stores_av1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_imm2", FIELD_fld_ae_sem_loads_stores_imm2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i3", FIELD_fld_ae_sem_loads_stores_i3, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_encode, OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_rng_v0", FIELD_fld_ae_sem_rng_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_rng_v1", FIELD_fld_ae_sem_rng_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_reduction_sort_v", FIELD_fld_ae_sem_reduction_sort_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_reduction_sort_v0", FIELD_fld_ae_sem_reduction_sort_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_reduction_sort_ds", FIELD_fld_ae_sem_reduction_sort_ds, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_multiply_d0", FIELD_fld_ae_sem_multiply_d0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_multiply_d2", FIELD_fld_ae_sem_multiply_d2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_multiply_q0", FIELD_fld_ae_sem_multiply_q0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_multiply_q1", FIELD_fld_ae_sem_multiply_q1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_immed.N", FIELD_fld_ae_sem_dr_to_dr_immed_N, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_ar_ei", FIELD_fld_ae_sem_dr_to_ar_ei, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_dr_to_ar_eo", FIELD_fld_ae_sem_dr_to_ar_eo, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_multiply_acc_ep", FIELD_fld_ae_sem_multiply_acc_ep, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_arithmetic_e", FIELD_fld_ae_sem_arithmetic_e, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_arithmetic_ep", FIELD_fld_ae_sem_arithmetic_ep, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_arithmetic_ep1", FIELD_fld_ae_sem_arithmetic_ep1, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_select_ss", FIELD_fld_ae_sem_select_ss, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_select_vr", FIELD_fld_ae_sem_select_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_select_vs", FIELD_fld_ae_sem_select_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_select_vt", FIELD_fld_ae_sem_select_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_select_vu", FIELD_fld_ae_sem_select_vu, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_select_isel", FIELD_fld_ae_sem_select_isel, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_encode, OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_e", FIELD_fld_ae_sem_shift_e, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_shift_i8", FIELD_fld_ae_sem_shift_i8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_shift_i8_encode, OperandSem_opnd_sem_opnd_ae_sem_shift_i8_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_multiply_d1", FIELD_fld_ae_sem_multiply_d1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_multiply_d3", FIELD_fld_ae_sem_multiply_d3, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_imm", FIELD_fld_ae_sem_dr_to_dr_imm, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_imm_encode, OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_imm_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_rng_d", FIELD_fld_ae_sem_rng_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_sb_loads_stores_iba2", FIELD_fld_ae_sem_sb_loads_stores_iba2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba2_encode, OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_ar_ar_s", FIELD_fld_ae_sem_dr_to_ar_ar_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_AE_ARDECNORM16_ar_u", FIELD_fld_AE_ARDECNORM16_ar_u, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_rng_a", FIELD_fld_ae_sem_rng_a, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_rng_art", FIELD_fld_ae_sem_rng_art, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_rng_i2", FIELD_fld_ae_sem_rng_i2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_rng_imm2", FIELD_fld_ae_sem_rng_imm2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_lb_db_ops_ar_u", FIELD_fld_ae_sem_lb_db_ops_ar_u, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_lb_db_ops_iba", FIELD_fld_ae_sem_lb_db_ops_iba, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_encode, OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_ar_vr", FIELD_fld_ae_sem_dr_to_ar_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spmisc_brt", FIELD_fld_ae_sem_spmisc_brt, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_spmisc_vr", FIELD_fld_ae_sem_spmisc_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spmisc_vs", FIELD_fld_ae_sem_spmisc_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_arr", FIELD_fld_ae_sem_dr_to_dr_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_dr_to_dr_bt", FIELD_fld_ae_sem_dr_to_dr_bt, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_sp32cvt_art", FIELD_fld_ae_sem_sp32cvt_art, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_sp32cvt_i_imm5", FIELD_fld_ae_sem_sp32cvt_i_imm5, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_encode, OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_sp32cvt_vr", FIELD_fld_ae_sem_sp32cvt_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_sp32cvt_vt", FIELD_fld_ae_sem_sp32cvt_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_sp32cvt_arr", FIELD_fld_ae_sem_sp32cvt_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_movfpstate_v", FIELD_fld_ae_sem_movfpstate_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_fpmov_vr", FIELD_fld_ae_sem_fpmov_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_fpmov_vt", FIELD_fld_ae_sem_fpmov_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_fpmov_i_imm4", FIELD_fld_ae_sem_fpmov_i_imm4, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_encode, OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_fpmov_vs", FIELD_fld_ae_sem_fpmov_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_fpmov_vu", FIELD_fld_ae_sem_fpmov_vu, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spmisc_vsM", FIELD_fld_ae_sem_spmisc_vsM, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spmisc_vtM", FIELD_fld_ae_sem_spmisc_vtM, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spmisc_vt", FIELD_fld_ae_sem_spmisc_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spaddsub_vr", FIELD_fld_ae_sem_spaddsub_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spaddsub_vs", FIELD_fld_ae_sem_spaddsub_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spaddsub_vt", FIELD_fld_ae_sem_spaddsub_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spaddsub_vu", FIELD_fld_ae_sem_spaddsub_vu, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vr", FIELD_fld_ae_sem_spfma_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vs", FIELD_fld_ae_sem_spfma_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vt", FIELD_fld_ae_sem_spfma_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vp", FIELD_fld_ae_sem_spfma_vp, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_i_imm1", FIELD_fld_ae_sem_spfma_i_imm1, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm1_encode, OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm1_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_spfma_i_imm3", FIELD_fld_ae_sem_spfma_i_imm3, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_encode, OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_spaddsub_vp", FIELD_fld_ae_sem_spaddsub_vp, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spaddsub_vq", FIELD_fld_ae_sem_spaddsub_vq, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vu", FIELD_fld_ae_sem_spfma_vu, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vq", FIELD_fld_ae_sem_spfma_vq, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hprminmaxnum_vr", FIELD_fld_ae_sem_hprminmaxnum_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hprminmaxnum_vt", FIELD_fld_ae_sem_hprminmaxnum_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcmp_br4t", FIELD_fld_ae_sem_hpcmp_br4t, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_hpcmp_vr", FIELD_fld_ae_sem_hpcmp_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcmp_vs", FIELD_fld_ae_sem_hpcmp_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcnv_art", FIELD_fld_ae_sem_hpcnv_art, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_hpcnv_i_imm4", FIELD_fld_ae_sem_hpcnv_i_imm4, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_encode, OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_hpcnv_vr", FIELD_fld_ae_sem_hpcnv_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcnv_arr", FIELD_fld_ae_sem_hpcnv_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_hpcnv_vt", FIELD_fld_ae_sem_hpcnv_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcmp_vt", FIELD_fld_ae_sem_hpcmp_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcnv_vs", FIELD_fld_ae_sem_hpcnv_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vr", FIELD_fld_ae_sem_hpfma_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vs", FIELD_fld_ae_sem_hpfma_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vt", FIELD_fld_ae_sem_hpfma_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vp", FIELD_fld_ae_sem_hpfma_vp, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vu", FIELD_fld_ae_sem_hpfma_vu, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vq", FIELD_fld_ae_sem_hpfma_vq, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_c0", FIELD_fld_ae_sem_mul_nn_c0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_c1", FIELD_fld_ae_sem_mul_nn_c1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_c2", FIELD_fld_ae_sem_mul_nn_c2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_c3", FIELD_fld_ae_sem_mul_nn_c3, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_q0", FIELD_fld_ae_sem_mul_nn_q0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_q1", FIELD_fld_ae_sem_mul_nn_q1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_v0", FIELD_fld_ae_sem_mul_nn_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_v1", FIELD_fld_ae_sem_mul_nn_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_q2", FIELD_fld_ae_sem_mul_nn_q2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_q3", FIELD_fld_ae_sem_mul_nn_q3, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_v2", FIELD_fld_ae_sem_mul_nn_v2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_v3", FIELD_fld_ae_sem_mul_nn_v3, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "bitindex", FIELD_bitindex, -1, 0, + 0, + OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode, + 0, 0, + -1, 0 }, + { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 }, + { "imms8", FIELD_imms8, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, + { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, + { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, + { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, + { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, + { "r_disp", FIELD_r_disp, -1, 0, 0, 0, 0, 0, 0 }, + { "r_3", FIELD_r_3, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, + { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, + { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, + { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, + { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 }, + { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 }, + { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 }, + { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 }, + { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 }, + { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 }, + { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 }, + { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_Inst16b_12", FIELD_ae_fld_Inst16b_12, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_Inst16b_15_13", FIELD_ae_fld_Inst16b_15_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_art", FIELD_fld_ae_sem_arithmetic_art, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_ds", FIELD_fld_ae_sem_arithmetic_ds, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_v", FIELD_fld_ae_sem_arithmetic_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_v0", FIELD_fld_ae_sem_arithmetic_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_v1", FIELD_fld_ae_sem_arithmetic_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_va", FIELD_fld_ae_sem_arithmetic_va, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_vs", FIELD_fld_ae_sem_arithmetic_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_a", FIELD_fld_ae_sem_dr_to_ar_a, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_ab", FIELD_fld_ae_sem_dr_to_ar_ab, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_ai", FIELD_fld_ae_sem_dr_to_ar_ai, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_aoe", FIELD_fld_ae_sem_dr_to_ar_aoe, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_d", FIELD_fld_ae_sem_dr_to_ar_d, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_d0", FIELD_fld_ae_sem_dr_to_ar_d0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_d1", FIELD_fld_ae_sem_dr_to_ar_d1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_imm8", FIELD_fld_ae_sem_dr_to_ar_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_v0", FIELD_fld_ae_sem_dr_to_ar_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_vr", FIELD_fld_ae_sem_dr_to_ar_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_arr", FIELD_fld_ae_sem_dr_to_dr_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_bt", FIELD_fld_ae_sem_dr_to_dr_bt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_ds", FIELD_fld_ae_sem_dr_to_dr_ds, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_imm2", FIELD_fld_ae_sem_dr_to_dr_imm2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_immed", FIELD_fld_ae_sem_dr_to_dr_immed, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_movi_imm", FIELD_fld_ae_sem_dr_to_dr_movi_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_v", FIELD_fld_ae_sem_dr_to_dr_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_v0", FIELD_fld_ae_sem_dr_to_dr_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_v1", FIELD_fld_ae_sem_dr_to_dr_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcmp_br4t", FIELD_fld_ae_sem_hpcmp_br4t, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcmp_vr", FIELD_fld_ae_sem_hpcmp_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcmp_vs", FIELD_fld_ae_sem_hpcmp_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_arr", FIELD_fld_ae_sem_hpcnv_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_art", FIELD_fld_ae_sem_hpcnv_art, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_i_imm4", FIELD_fld_ae_sem_hpcnv_i_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_vr", FIELD_fld_ae_sem_hpcnv_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_vt", FIELD_fld_ae_sem_hpcnv_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hprminmaxnum_vr", FIELD_fld_ae_sem_hprminmaxnum_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hprminmaxnum_vt", FIELD_fld_ae_sem_hprminmaxnum_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_lb_ops_iba", FIELD_fld_ae_sem_lb_ops_iba, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_a", FIELD_fld_ae_sem_loads_stores_a, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_a.0", FIELD_fld_ae_sem_loads_stores_a_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_av", FIELD_fld_ae_sem_loads_stores_av, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_av1", FIELD_fld_ae_sem_loads_stores_av1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_end", FIELD_fld_ae_sem_loads_stores_end, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i128", FIELD_fld_ae_sem_loads_stores_i128, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i16", FIELD_fld_ae_sem_loads_stores_i16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i3", FIELD_fld_ae_sem_loads_stores_i3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i32", FIELD_fld_ae_sem_loads_stores_i32, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i32pos", FIELD_fld_ae_sem_loads_stores_i32pos, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i64", FIELD_fld_ae_sem_loads_stores_i64, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i64half", FIELD_fld_ae_sem_loads_stores_i64half, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i64neg", FIELD_fld_ae_sem_loads_stores_i64neg, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i64pos", FIELD_fld_ae_sem_loads_stores_i64pos, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i64x2", FIELD_fld_ae_sem_loads_stores_i64x2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i8", FIELD_fld_ae_sem_loads_stores_i8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_imm2", FIELD_fld_ae_sem_loads_stores_imm2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_su", FIELD_fld_ae_sem_loads_stores_su, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_uu", FIELD_fld_ae_sem_loads_stores_uu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_v", FIELD_fld_ae_sem_loads_stores_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_v1", FIELD_fld_ae_sem_loads_stores_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_vu", FIELD_fld_ae_sem_loads_stores_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_x", FIELD_fld_ae_sem_loads_stores_x, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_pks_d", FIELD_fld_ae_sem_pks_d, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_pks_pos", FIELD_fld_ae_sem_pks_pos, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_pks_s", FIELD_fld_ae_sem_pks_s, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_v0", FIELD_fld_ae_sem_rng_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_v1", FIELD_fld_ae_sem_rng_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sb_loads_stores_iba", FIELD_fld_ae_sem_sb_loads_stores_iba, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_a", FIELD_fld_ae_sem_shift_a, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_a0", FIELD_fld_ae_sem_shift_a0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_d", FIELD_fld_ae_sem_shift_d, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_d0", FIELD_fld_ae_sem_shift_d0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_d1", FIELD_fld_ae_sem_shift_d1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_da", FIELD_fld_ae_sem_shift_da, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_i16", FIELD_fld_ae_sem_shift_i16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_i32", FIELD_fld_ae_sem_shift_i32, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_i64", FIELD_fld_ae_sem_shift_i64, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_imm32", FIELD_fld_ae_sem_shift_imm32, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_imm8", FIELD_fld_ae_sem_shift_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_sd", FIELD_fld_ae_sem_shift_sd, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sp32cvt_arr", FIELD_fld_ae_sem_sp32cvt_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sp32cvt_art", FIELD_fld_ae_sem_sp32cvt_art, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sp32cvt_i_imm5", FIELD_fld_ae_sem_sp32cvt_i_imm5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sp32cvt_vr", FIELD_fld_ae_sem_sp32cvt_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sp32cvt_vt", FIELD_fld_ae_sem_sp32cvt_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_brt", FIELD_fld_ae_sem_spmisc_brt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_vr", FIELD_fld_ae_sem_spmisc_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_vs", FIELD_fld_ae_sem_spmisc_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_10", FIELD_fld_ae_slot0_11_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_11", FIELD_fld_ae_slot0_11_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_8", FIELD_fld_ae_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_9", FIELD_fld_ae_slot0_11_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_0", FIELD_fld_ae_slot0_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_10", FIELD_fld_ae_slot0_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_12", FIELD_fld_ae_slot0_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_2", FIELD_fld_ae_slot0_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_6", FIELD_fld_ae_slot0_12_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_8", FIELD_fld_ae_slot0_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_9", FIELD_fld_ae_slot0_12_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_14_12", FIELD_fld_ae_slot0_14_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_14_13", FIELD_fld_ae_slot0_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_10", FIELD_fld_ae_slot0_17_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_12", FIELD_fld_ae_slot0_17_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_13", FIELD_fld_ae_slot0_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_14", FIELD_fld_ae_slot0_17_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_15", FIELD_fld_ae_slot0_17_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_16", FIELD_fld_ae_slot0_17_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_17", FIELD_fld_ae_slot0_17_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_8", FIELD_fld_ae_slot0_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_18_13", FIELD_fld_ae_slot0_18_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_18_15", FIELD_fld_ae_slot0_18_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_18_16", FIELD_fld_ae_slot0_18_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_18_8", FIELD_fld_ae_slot0_18_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_19_12", FIELD_fld_ae_slot0_19_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_19_15", FIELD_fld_ae_slot0_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_19_19", FIELD_fld_ae_slot0_19_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_19_8", FIELD_fld_ae_slot0_19_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_1_0", FIELD_fld_ae_slot0_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_1_1", FIELD_fld_ae_slot0_1_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_16", FIELD_fld_ae_slot0_20_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_20", FIELD_fld_ae_slot0_20_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_23_15", FIELD_fld_ae_slot0_23_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_23_17", FIELD_fld_ae_slot0_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_23_19", FIELD_fld_ae_slot0_23_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_23_22", FIELD_fld_ae_slot0_23_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_10", FIELD_fld_ae_slot0_28_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_12", FIELD_fld_ae_slot0_28_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_14", FIELD_fld_ae_slot0_28_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_15", FIELD_fld_ae_slot0_28_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_16", FIELD_fld_ae_slot0_28_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_17", FIELD_fld_ae_slot0_28_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_19", FIELD_fld_ae_slot0_28_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_21", FIELD_fld_ae_slot0_28_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_22", FIELD_fld_ae_slot0_28_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_24", FIELD_fld_ae_slot0_28_24, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_26", FIELD_fld_ae_slot0_28_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_27", FIELD_fld_ae_slot0_28_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_4", FIELD_fld_ae_slot0_28_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_8", FIELD_fld_ae_slot0_28_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_3_0", FIELD_fld_ae_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_3_1", FIELD_fld_ae_slot0_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_3_2", FIELD_fld_ae_slot0_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_3_3", FIELD_fld_ae_slot0_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_4_0", FIELD_fld_ae_slot0_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_4_4", FIELD_fld_ae_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_5_0", FIELD_fld_ae_slot0_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_5_4", FIELD_fld_ae_slot0_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_0", FIELD_fld_ae_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_2", FIELD_fld_ae_slot0_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_3", FIELD_fld_ae_slot0_7_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_4", FIELD_fld_ae_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_8_8", FIELD_fld_ae_slot0_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_9_4", FIELD_fld_ae_slot0_9_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_9_8", FIELD_fld_ae_slot0_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_9_9", FIELD_fld_ae_slot0_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_0_0", FIELD_fld_ae_slot1_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_12_8", FIELD_fld_ae_slot1_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_17_13", FIELD_fld_ae_slot1_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_17_17", FIELD_fld_ae_slot1_17_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_17_8", FIELD_fld_ae_slot1_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_1", FIELD_fld_ae_slot1_25_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_12", FIELD_fld_ae_slot1_25_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_13", FIELD_fld_ae_slot1_25_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_16", FIELD_fld_ae_slot1_25_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_17", FIELD_fld_ae_slot1_25_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_18", FIELD_fld_ae_slot1_25_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_20", FIELD_fld_ae_slot1_25_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_22", FIELD_fld_ae_slot1_25_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_23", FIELD_fld_ae_slot1_25_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_8", FIELD_fld_ae_slot1_25_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_9", FIELD_fld_ae_slot1_25_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_3_0", FIELD_fld_ae_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_3_2", FIELD_fld_ae_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_3_3", FIELD_fld_ae_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_7_4", FIELD_fld_ae_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_e", FIELD_fld_ae_sem_arithmetic_e, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_ep", FIELD_fld_ae_sem_arithmetic_ep, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_ep1", FIELD_fld_ae_sem_arithmetic_ep1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_ei", FIELD_fld_ae_sem_dr_to_ar_ei, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_eo", FIELD_fld_ae_sem_dr_to_ar_eo, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_immed.N", FIELD_fld_ae_sem_dr_to_dr_immed_N, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_fpmov_i_imm4", FIELD_fld_ae_sem_fpmov_i_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_fpmov_vr", FIELD_fld_ae_sem_fpmov_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_fpmov_vs", FIELD_fld_ae_sem_fpmov_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_fpmov_vt", FIELD_fld_ae_sem_fpmov_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_fpmov_vu", FIELD_fld_ae_sem_fpmov_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcmp_vt", FIELD_fld_ae_sem_hpcmp_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_vs", FIELD_fld_ae_sem_hpcnv_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vr", FIELD_fld_ae_sem_hpfma_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vs", FIELD_fld_ae_sem_hpfma_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vt", FIELD_fld_ae_sem_hpfma_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_movfpstate_v", FIELD_fld_ae_sem_movfpstate_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_acc_ep", FIELD_fld_ae_sem_multiply_acc_ep, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_d0", FIELD_fld_ae_sem_multiply_d0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_d2", FIELD_fld_ae_sem_multiply_d2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_q0", FIELD_fld_ae_sem_multiply_q0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_q1", FIELD_fld_ae_sem_multiply_q1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_reduction_sort_ds", FIELD_fld_ae_sem_reduction_sort_ds, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_reduction_sort_v", FIELD_fld_ae_sem_reduction_sort_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_reduction_sort_v0", FIELD_fld_ae_sem_reduction_sort_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_isel", FIELD_fld_ae_sem_select_isel, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_ss", FIELD_fld_ae_sem_select_ss, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_vr", FIELD_fld_ae_sem_select_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_vs", FIELD_fld_ae_sem_select_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_vt", FIELD_fld_ae_sem_select_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_vu", FIELD_fld_ae_sem_select_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vr", FIELD_fld_ae_sem_spaddsub_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vs", FIELD_fld_ae_sem_spaddsub_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vt", FIELD_fld_ae_sem_spaddsub_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vu", FIELD_fld_ae_sem_spaddsub_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_i_imm1", FIELD_fld_ae_sem_spfma_i_imm1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_i_imm3", FIELD_fld_ae_sem_spfma_i_imm3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vp", FIELD_fld_ae_sem_spfma_vp, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vr", FIELD_fld_ae_sem_spfma_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vs", FIELD_fld_ae_sem_spfma_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vt", FIELD_fld_ae_sem_spfma_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_vsM", FIELD_fld_ae_sem_spmisc_vsM, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_vt", FIELD_fld_ae_sem_spmisc_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_vtM", FIELD_fld_ae_sem_spmisc_vtM, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_14_0", FIELD_fld_ae_slot2_14_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_14_10", FIELD_fld_ae_slot2_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_14_14", FIELD_fld_ae_slot2_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_14_5", FIELD_fld_ae_slot2_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_16_15", FIELD_fld_ae_slot2_16_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_19_15", FIELD_fld_ae_slot2_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_15", FIELD_fld_ae_slot2_28_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_17", FIELD_fld_ae_slot2_28_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_19", FIELD_fld_ae_slot2_28_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_20", FIELD_fld_ae_slot2_28_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_25", FIELD_fld_ae_slot2_28_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_4", FIELD_fld_ae_slot2_28_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_5", FIELD_fld_ae_slot2_28_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_3_0", FIELD_fld_ae_slot2_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_0", FIELD_fld_ae_slot2_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_1", FIELD_fld_ae_slot2_9_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_2", FIELD_fld_ae_slot2_9_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_5", FIELD_fld_ae_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_6", FIELD_fld_ae_slot2_9_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_7", FIELD_fld_ae_slot2_9_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_8", FIELD_fld_ae_slot2_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_imm", FIELD_fld_ae_sem_dr_to_dr_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_d1", FIELD_fld_ae_sem_multiply_d1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_d3", FIELD_fld_ae_sem_multiply_d3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_d", FIELD_fld_ae_sem_rng_d, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_e", FIELD_fld_ae_sem_shift_e, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_i8", FIELD_fld_ae_sem_shift_i8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_11_0", FIELD_fld_ae_slot3_11_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_14_0", FIELD_fld_ae_slot3_14_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_14_10", FIELD_fld_ae_slot3_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_14_12", FIELD_fld_ae_slot3_14_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_14_13", FIELD_fld_ae_slot3_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_16_13", FIELD_fld_ae_slot3_16_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_0", FIELD_fld_ae_slot3_19_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_10", FIELD_fld_ae_slot3_19_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_15", FIELD_fld_ae_slot3_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_17", FIELD_fld_ae_slot3_19_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_18", FIELD_fld_ae_slot3_19_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_19", FIELD_fld_ae_slot3_19_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_24_10", FIELD_fld_ae_slot3_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_24_19", FIELD_fld_ae_slot3_24_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_24_20", FIELD_fld_ae_slot3_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_12", FIELD_fld_ae_slot3_36_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_16", FIELD_fld_ae_slot3_36_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_19", FIELD_fld_ae_slot3_36_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_20", FIELD_fld_ae_slot3_36_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_22", FIELD_fld_ae_slot3_36_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_25", FIELD_fld_ae_slot3_36_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_30", FIELD_fld_ae_slot3_36_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_4_0", FIELD_fld_ae_slot3_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_9_0", FIELD_fld_ae_slot3_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_9_1", FIELD_fld_ae_slot3_9_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_9_3", FIELD_fld_ae_slot3_9_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_9_5", FIELD_fld_ae_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_0_0", FIELD_fld_ae2_slot0_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_11_4", FIELD_fld_ae2_slot0_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_11_8", FIELD_fld_ae2_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_11_9", FIELD_fld_ae2_slot0_11_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_12_0", FIELD_fld_ae2_slot0_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_12_2", FIELD_fld_ae2_slot0_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_12_4", FIELD_fld_ae2_slot0_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_12_8", FIELD_fld_ae2_slot0_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_14_13", FIELD_fld_ae2_slot0_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_14_8", FIELD_fld_ae2_slot0_14_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_0", FIELD_fld_ae2_slot0_15_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_12", FIELD_fld_ae2_slot0_15_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_13", FIELD_fld_ae2_slot0_15_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_15", FIELD_fld_ae2_slot0_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_4", FIELD_fld_ae2_slot0_15_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_8", FIELD_fld_ae2_slot0_15_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_17_13", FIELD_fld_ae2_slot0_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_17_17", FIELD_fld_ae2_slot0_17_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_18_15", FIELD_fld_ae2_slot0_18_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_18_17", FIELD_fld_ae2_slot0_18_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_18_18", FIELD_fld_ae2_slot0_18_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_1_0", FIELD_fld_ae2_slot0_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_23_18", FIELD_fld_ae2_slot0_23_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_23_19", FIELD_fld_ae2_slot0_23_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_3_0", FIELD_fld_ae2_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_16", FIELD_fld_ae2_slot0_40_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_17", FIELD_fld_ae2_slot0_40_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_18", FIELD_fld_ae2_slot0_40_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_19", FIELD_fld_ae2_slot0_40_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_21", FIELD_fld_ae2_slot0_40_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_23", FIELD_fld_ae2_slot0_40_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_24", FIELD_fld_ae2_slot0_40_24, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_25", FIELD_fld_ae2_slot0_40_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_26", FIELD_fld_ae2_slot0_40_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_27", FIELD_fld_ae2_slot0_40_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_0", FIELD_fld_ae2_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_4", FIELD_fld_ae2_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_6", FIELD_fld_ae2_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_7", FIELD_fld_ae2_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_8_8", FIELD_fld_ae2_slot0_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_9_8", FIELD_fld_ae2_slot0_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_0_0", FIELD_fld_ae2_slot1_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_11_0", FIELD_fld_ae2_slot1_11_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_11_10", FIELD_fld_ae2_slot1_11_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_11_8", FIELD_fld_ae2_slot1_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_14_10", FIELD_fld_ae2_slot1_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_14_11", FIELD_fld_ae2_slot1_14_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_14_12", FIELD_fld_ae2_slot1_14_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_14_14", FIELD_fld_ae2_slot1_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_14_8", FIELD_fld_ae2_slot1_14_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_12", FIELD_fld_ae2_slot1_36_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_14", FIELD_fld_ae2_slot1_36_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_15", FIELD_fld_ae2_slot1_36_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_16", FIELD_fld_ae2_slot1_36_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_17", FIELD_fld_ae2_slot1_36_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_18", FIELD_fld_ae2_slot1_36_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_20", FIELD_fld_ae2_slot1_36_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_22", FIELD_fld_ae2_slot1_36_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_23", FIELD_fld_ae2_slot1_36_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_3_0", FIELD_fld_ae2_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_3_1", FIELD_fld_ae2_slot1_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_3_2", FIELD_fld_ae2_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_3_3", FIELD_fld_ae2_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_7_4", FIELD_fld_ae2_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_9_8", FIELD_fld_ae2_slot1_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_9_9", FIELD_fld_ae2_slot1_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_14_10", FIELD_fld_ae2_slot2_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_17_0", FIELD_fld_ae2_slot2_17_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_17_10", FIELD_fld_ae2_slot2_17_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_17_15", FIELD_fld_ae2_slot2_17_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_17_17", FIELD_fld_ae2_slot2_17_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_19_10", FIELD_fld_ae2_slot2_19_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_19_15", FIELD_fld_ae2_slot2_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_19_18", FIELD_fld_ae2_slot2_19_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_19_9", FIELD_fld_ae2_slot2_19_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_10", FIELD_fld_ae2_slot2_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_15", FIELD_fld_ae2_slot2_24_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_20", FIELD_fld_ae2_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_5", FIELD_fld_ae2_slot2_24_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_9", FIELD_fld_ae2_slot2_24_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_18", FIELD_fld_ae2_slot2_42_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_20", FIELD_fld_ae2_slot2_42_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_25", FIELD_fld_ae2_slot2_42_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_26", FIELD_fld_ae2_slot2_42_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_28", FIELD_fld_ae2_slot2_42_28, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_30", FIELD_fld_ae2_slot2_42_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_4_0", FIELD_fld_ae2_slot2_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_9_5", FIELD_fld_ae2_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vp", FIELD_fld_ae_sem_spaddsub_vp, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vq", FIELD_fld_ae_sem_spaddsub_vq, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_11_11", FIELD_fld_ae3_slot0_11_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_11_4", FIELD_fld_ae3_slot0_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_11_8", FIELD_fld_ae3_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_12_12", FIELD_fld_ae3_slot0_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_12_8", FIELD_fld_ae3_slot0_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_13_13", FIELD_fld_ae3_slot0_13_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_13_8", FIELD_fld_ae3_slot0_13_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_1_0", FIELD_fld_ae3_slot0_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_11", FIELD_fld_ae3_slot0_32_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_12", FIELD_fld_ae3_slot0_32_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_13", FIELD_fld_ae3_slot0_32_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_14", FIELD_fld_ae3_slot0_32_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_15", FIELD_fld_ae3_slot0_32_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_16", FIELD_fld_ae3_slot0_32_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_17", FIELD_fld_ae3_slot0_32_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_18", FIELD_fld_ae3_slot0_32_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_20", FIELD_fld_ae3_slot0_32_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_27", FIELD_fld_ae3_slot0_32_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_8", FIELD_fld_ae3_slot0_32_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_3_0", FIELD_fld_ae3_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_3_2", FIELD_fld_ae3_slot0_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_3_3", FIELD_fld_ae3_slot0_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_4_0", FIELD_fld_ae3_slot0_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_4_4", FIELD_fld_ae3_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_5_0", FIELD_fld_ae3_slot0_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_5_4", FIELD_fld_ae3_slot0_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_7_0", FIELD_fld_ae3_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_7_2", FIELD_fld_ae3_slot0_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_7_4", FIELD_fld_ae3_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_7_6", FIELD_fld_ae3_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_8_8", FIELD_fld_ae3_slot0_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_9_4", FIELD_fld_ae3_slot0_9_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_9_8", FIELD_fld_ae3_slot0_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_ar_s", FIELD_fld_ae_sem_dr_to_ar_ar_s, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sb_loads_stores_iba2", FIELD_fld_ae_sem_sb_loads_stores_iba2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_0", FIELD_fld_ae3_slot1_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_11", FIELD_fld_ae3_slot1_23_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_12", FIELD_fld_ae3_slot1_23_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_13", FIELD_fld_ae3_slot1_23_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_15", FIELD_fld_ae3_slot1_23_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_16", FIELD_fld_ae3_slot1_23_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_17", FIELD_fld_ae3_slot1_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_19", FIELD_fld_ae3_slot1_23_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_6", FIELD_fld_ae3_slot1_23_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_8", FIELD_fld_ae3_slot1_23_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_9", FIELD_fld_ae3_slot1_23_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_3_0", FIELD_fld_ae3_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_3_1", FIELD_fld_ae3_slot1_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_3_2", FIELD_fld_ae3_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_3_3", FIELD_fld_ae3_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_7_4", FIELD_fld_ae3_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_9_8", FIELD_fld_ae3_slot1_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_AE_ARDECNORM16_ar_u", FIELD_fld_AE_ARDECNORM16_ar_u, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_11_10", FIELD_fld_ae5_slot0_11_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_11_4", FIELD_fld_ae5_slot0_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_11_8", FIELD_fld_ae5_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_11_9", FIELD_fld_ae5_slot0_11_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_12_10", FIELD_fld_ae5_slot0_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_12_4", FIELD_fld_ae5_slot0_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_12_6", FIELD_fld_ae5_slot0_12_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_12_8", FIELD_fld_ae5_slot0_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_12_9", FIELD_fld_ae5_slot0_12_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_1_0", FIELD_fld_ae5_slot0_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_1_1", FIELD_fld_ae5_slot0_1_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_12", FIELD_fld_ae5_slot0_29_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_13", FIELD_fld_ae5_slot0_29_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_15", FIELD_fld_ae5_slot0_29_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_16", FIELD_fld_ae5_slot0_29_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_17", FIELD_fld_ae5_slot0_29_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_18", FIELD_fld_ae5_slot0_29_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_19", FIELD_fld_ae5_slot0_29_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_20", FIELD_fld_ae5_slot0_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_27", FIELD_fld_ae5_slot0_29_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_5", FIELD_fld_ae5_slot0_29_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_6", FIELD_fld_ae5_slot0_29_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_8", FIELD_fld_ae5_slot0_29_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_2_0", FIELD_fld_ae5_slot0_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_3_0", FIELD_fld_ae5_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_3_2", FIELD_fld_ae5_slot0_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_4_0", FIELD_fld_ae5_slot0_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_4_4", FIELD_fld_ae5_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_7_0", FIELD_fld_ae5_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_7_4", FIELD_fld_ae5_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_7_7", FIELD_fld_ae5_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_8_8", FIELD_fld_ae5_slot0_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_lb_db_ops_ar_u", FIELD_fld_ae_sem_lb_db_ops_ar_u, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_lb_db_ops_iba", FIELD_fld_ae_sem_lb_db_ops_iba, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_a", FIELD_fld_ae_sem_rng_a, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_art", FIELD_fld_ae_sem_rng_art, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_i2", FIELD_fld_ae_sem_rng_i2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_imm2", FIELD_fld_ae_sem_rng_imm2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot1_1_0", FIELD_fld_ae5_slot1_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_14_10", FIELD_fld_ae5_slot2_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_14_14", FIELD_fld_ae5_slot2_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_14_5", FIELD_fld_ae5_slot2_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_24_0", FIELD_fld_ae5_slot2_24_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_24_15", FIELD_fld_ae5_slot2_24_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_24_17", FIELD_fld_ae5_slot2_24_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_24_20", FIELD_fld_ae5_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_4_0", FIELD_fld_ae5_slot2_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_9_0", FIELD_fld_ae5_slot2_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_9_5", FIELD_fld_ae5_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_9_7", FIELD_fld_ae5_slot2_9_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_10_10", FIELD_fld_ae6_slot0_10_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_15_15", FIELD_fld_ae6_slot0_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_10", FIELD_fld_ae6_slot0_29_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_13", FIELD_fld_ae6_slot0_29_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_14", FIELD_fld_ae6_slot0_29_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_15", FIELD_fld_ae6_slot0_29_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_18", FIELD_fld_ae6_slot0_29_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_20", FIELD_fld_ae6_slot0_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_5", FIELD_fld_ae6_slot0_29_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_4_0", FIELD_fld_ae6_slot0_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_4_4", FIELD_fld_ae6_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_7_4", FIELD_fld_ae6_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_7_7", FIELD_fld_ae6_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_9_8", FIELD_fld_ae6_slot0_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_9_9", FIELD_fld_ae6_slot0_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_14_14", FIELD_fld_ae6_slot1_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_12", FIELD_fld_ae6_slot1_27_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_15", FIELD_fld_ae6_slot1_27_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_20", FIELD_fld_ae6_slot1_27_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_21", FIELD_fld_ae6_slot1_27_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_3", FIELD_fld_ae6_slot1_27_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_6", FIELD_fld_ae6_slot1_27_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_2_0", FIELD_fld_ae6_slot1_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_9_5", FIELD_fld_ae6_slot1_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_9_6", FIELD_fld_ae6_slot1_9_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_9_7", FIELD_fld_ae6_slot1_9_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_9_8", FIELD_fld_ae6_slot1_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_9_9", FIELD_fld_ae6_slot1_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_10_10", FIELD_fld_ae6_slot2_10_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_11_10", FIELD_fld_ae6_slot2_11_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_24_0", FIELD_fld_ae6_slot2_24_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_24_10", FIELD_fld_ae6_slot2_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_24_14", FIELD_fld_ae6_slot2_24_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_24_15", FIELD_fld_ae6_slot2_24_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_24_20", FIELD_fld_ae6_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_4_2", FIELD_fld_ae6_slot2_4_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_9_5", FIELD_fld_ae6_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_10_10", FIELD_fld_ae6_slot3_10_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_12_0", FIELD_fld_ae6_slot3_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_14_0", FIELD_fld_ae6_slot3_14_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_14_10", FIELD_fld_ae6_slot3_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_14_13", FIELD_fld_ae6_slot3_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_14_5", FIELD_fld_ae6_slot3_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_24_20", FIELD_fld_ae6_slot3_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_37_13", FIELD_fld_ae6_slot3_37_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_37_15", FIELD_fld_ae6_slot3_37_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_37_20", FIELD_fld_ae6_slot3_37_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_37_30", FIELD_fld_ae6_slot3_37_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_9_5", FIELD_fld_ae6_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_12_6", FIELD_fld_ae7_slot0_12_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_23_0", FIELD_fld_ae7_slot0_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_23_13", FIELD_fld_ae7_slot0_23_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_23_17", FIELD_fld_ae7_slot0_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_23_18", FIELD_fld_ae7_slot0_23_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_23_6", FIELD_fld_ae7_slot0_23_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_7_4", FIELD_fld_ae7_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_7_6", FIELD_fld_ae7_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_7_7", FIELD_fld_ae7_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_12_6", FIELD_fld_ae7_slot1_12_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_23_0", FIELD_fld_ae7_slot1_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_23_13", FIELD_fld_ae7_slot1_23_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_23_17", FIELD_fld_ae7_slot1_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_23_18", FIELD_fld_ae7_slot1_23_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_23_6", FIELD_fld_ae7_slot1_23_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_7_4", FIELD_fld_ae7_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_7_6", FIELD_fld_ae7_slot1_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_7_7", FIELD_fld_ae7_slot1_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_11_0", FIELD_fld_ae7_slot2_11_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_14_10", FIELD_fld_ae7_slot2_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_14_5", FIELD_fld_ae7_slot2_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_36_12", FIELD_fld_ae7_slot2_36_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_36_15", FIELD_fld_ae7_slot2_36_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_36_20", FIELD_fld_ae7_slot2_36_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_36_25", FIELD_fld_ae7_slot2_36_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_36_30", FIELD_fld_ae7_slot2_36_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_9_5", FIELD_fld_ae7_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_10_0", FIELD_fld_ae7_slot3_10_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_14_10", FIELD_fld_ae7_slot3_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_14_5", FIELD_fld_ae7_slot3_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_24_10", FIELD_fld_ae7_slot3_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_35_11", FIELD_fld_ae7_slot3_35_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_35_20", FIELD_fld_ae7_slot3_35_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_35_25", FIELD_fld_ae7_slot3_35_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_35_30", FIELD_fld_ae7_slot3_35_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_4_0", FIELD_fld_ae7_slot3_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_9_5", FIELD_fld_ae7_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_13_12", FIELD_fld_ae8_slot0_13_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_13_13", FIELD_fld_ae8_slot0_13_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_13_4", FIELD_fld_ae8_slot0_13_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_13_9", FIELD_fld_ae8_slot0_13_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_17_4", FIELD_fld_ae8_slot0_17_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_17_8", FIELD_fld_ae8_slot0_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_12", FIELD_fld_ae8_slot0_31_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_15", FIELD_fld_ae8_slot0_31_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_18", FIELD_fld_ae8_slot0_31_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_19", FIELD_fld_ae8_slot0_31_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_20", FIELD_fld_ae8_slot0_31_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_21", FIELD_fld_ae8_slot0_31_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_22", FIELD_fld_ae8_slot0_31_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_23", FIELD_fld_ae8_slot0_31_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_7", FIELD_fld_ae8_slot0_31_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_8", FIELD_fld_ae8_slot0_31_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_9", FIELD_fld_ae8_slot0_31_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_3_0", FIELD_fld_ae8_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_6_0", FIELD_fld_ae8_slot0_6_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_7_4", FIELD_fld_ae8_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_7_5", FIELD_fld_ae8_slot0_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_7_7", FIELD_fld_ae8_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_8_0", FIELD_fld_ae8_slot0_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_17_13", FIELD_fld_ae8_slot1_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_17_14", FIELD_fld_ae8_slot1_17_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_17_15", FIELD_fld_ae8_slot1_17_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_17_8", FIELD_fld_ae8_slot1_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_12", FIELD_fld_ae8_slot1_29_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_13", FIELD_fld_ae8_slot1_29_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_18", FIELD_fld_ae8_slot1_29_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_20", FIELD_fld_ae8_slot1_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_22", FIELD_fld_ae8_slot1_29_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_23", FIELD_fld_ae8_slot1_29_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_5", FIELD_fld_ae8_slot1_29_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_8", FIELD_fld_ae8_slot1_29_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_9", FIELD_fld_ae8_slot1_29_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_3_0", FIELD_fld_ae8_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_3_3", FIELD_fld_ae8_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_4_0", FIELD_fld_ae8_slot1_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_7_4", FIELD_fld_ae8_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_19_10", FIELD_fld_ae8_slot2_19_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_19_15", FIELD_fld_ae8_slot2_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_33_15", FIELD_fld_ae8_slot2_33_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_33_25", FIELD_fld_ae8_slot2_33_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_33_9", FIELD_fld_ae8_slot2_33_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_34_30", FIELD_fld_ae8_slot2_34_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_39_35", FIELD_fld_ae8_slot2_39_35, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_44_35", FIELD_fld_ae8_slot2_44_35, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_58_34", FIELD_fld_ae8_slot2_58_34, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_58_35", FIELD_fld_ae8_slot2_58_35, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_58_40", FIELD_fld_ae8_slot2_58_40, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_58_50", FIELD_fld_ae8_slot2_58_50, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_8_0", FIELD_fld_ae8_slot2_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_9_0", FIELD_fld_ae8_slot2_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_c0", FIELD_fld_ae_sem_mul_nn_c0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_c1", FIELD_fld_ae_sem_mul_nn_c1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_c2", FIELD_fld_ae_sem_mul_nn_c2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_c3", FIELD_fld_ae_sem_mul_nn_c3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_q0", FIELD_fld_ae_sem_mul_nn_q0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_q1", FIELD_fld_ae_sem_mul_nn_q1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_q2", FIELD_fld_ae_sem_mul_nn_q2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_q3", FIELD_fld_ae_sem_mul_nn_q3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_v0", FIELD_fld_ae_sem_mul_nn_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_v1", FIELD_fld_ae_sem_mul_nn_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_v2", FIELD_fld_ae_sem_mul_nn_v2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_v3", FIELD_fld_ae_sem_mul_nn_v3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_0_0", FIELD_fld_ae9_slot0_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_12_12", FIELD_fld_ae9_slot0_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_12_5", FIELD_fld_ae9_slot0_12_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_12_8", FIELD_fld_ae9_slot0_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_17_13", FIELD_fld_ae9_slot0_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_17_4", FIELD_fld_ae9_slot0_17_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_17_8", FIELD_fld_ae9_slot0_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_10", FIELD_fld_ae9_slot0_27_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_12", FIELD_fld_ae9_slot0_27_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_13", FIELD_fld_ae9_slot0_27_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_16", FIELD_fld_ae9_slot0_27_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_17", FIELD_fld_ae9_slot0_27_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_18", FIELD_fld_ae9_slot0_27_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_19", FIELD_fld_ae9_slot0_27_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_20", FIELD_fld_ae9_slot0_27_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_22", FIELD_fld_ae9_slot0_27_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_23", FIELD_fld_ae9_slot0_27_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_3", FIELD_fld_ae9_slot0_27_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_8", FIELD_fld_ae9_slot0_27_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_2_0", FIELD_fld_ae9_slot0_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_3_0", FIELD_fld_ae9_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_7_0", FIELD_fld_ae9_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_7_4", FIELD_fld_ae9_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_7_5", FIELD_fld_ae9_slot0_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_7_6", FIELD_fld_ae9_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_7_7", FIELD_fld_ae9_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_8_4", FIELD_fld_ae9_slot0_8_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_8_5", FIELD_fld_ae9_slot0_8_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_9_5", FIELD_fld_ae9_slot0_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_17_13", FIELD_fld_ae9_slot1_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_17_8", FIELD_fld_ae9_slot1_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_1_0", FIELD_fld_ae9_slot1_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_12", FIELD_fld_ae9_slot1_26_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_13", FIELD_fld_ae9_slot1_26_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_16", FIELD_fld_ae9_slot1_26_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_17", FIELD_fld_ae9_slot1_26_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_18", FIELD_fld_ae9_slot1_26_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_2", FIELD_fld_ae9_slot1_26_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_20", FIELD_fld_ae9_slot1_26_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_22", FIELD_fld_ae9_slot1_26_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_23", FIELD_fld_ae9_slot1_26_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_8", FIELD_fld_ae9_slot1_26_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_9", FIELD_fld_ae9_slot1_26_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_3_0", FIELD_fld_ae9_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_3_2", FIELD_fld_ae9_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_3_3", FIELD_fld_ae9_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_7_4", FIELD_fld_ae9_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_24_14", FIELD_fld_ae9_slot2_24_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_24_15", FIELD_fld_ae9_slot2_24_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_24_20", FIELD_fld_ae9_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_14", FIELD_fld_ae9_slot2_33_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_15", FIELD_fld_ae9_slot2_33_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_20", FIELD_fld_ae9_slot2_33_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_25", FIELD_fld_ae9_slot2_33_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_26", FIELD_fld_ae9_slot2_33_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_28", FIELD_fld_ae9_slot2_33_28, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_30", FIELD_fld_ae9_slot2_33_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_9", FIELD_fld_ae9_slot2_33_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_4_0", FIELD_fld_ae9_slot2_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_5_0", FIELD_fld_ae9_slot2_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_6_0", FIELD_fld_ae9_slot2_6_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_8_0", FIELD_fld_ae9_slot2_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_9_0", FIELD_fld_ae9_slot2_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_9_5", FIELD_fld_ae9_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_9_9", FIELD_fld_ae9_slot2_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vp", FIELD_fld_ae_sem_hpfma_vp, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vu", FIELD_fld_ae_sem_hpfma_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vu", FIELD_fld_ae_sem_spfma_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_19_15", FIELD_fld_ae9_slot3_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_24_20", FIELD_fld_ae9_slot3_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_14", FIELD_fld_ae9_slot3_31_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_15", FIELD_fld_ae9_slot3_31_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_20", FIELD_fld_ae9_slot3_31_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_25", FIELD_fld_ae9_slot3_31_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_26", FIELD_fld_ae9_slot3_31_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_28", FIELD_fld_ae9_slot3_31_28, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_7", FIELD_fld_ae9_slot3_31_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_4_0", FIELD_fld_ae9_slot3_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_4_3", FIELD_fld_ae9_slot3_4_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_4_4", FIELD_fld_ae9_slot3_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_6_0", FIELD_fld_ae9_slot3_6_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_9_0", FIELD_fld_ae9_slot3_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_9_5", FIELD_fld_ae9_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_17_13", FIELD_fld_ae10_slot0_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_17_4", FIELD_fld_ae10_slot0_17_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_17_8", FIELD_fld_ae10_slot0_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_0", FIELD_fld_ae10_slot0_24_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_10", FIELD_fld_ae10_slot0_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_12", FIELD_fld_ae10_slot0_24_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_13", FIELD_fld_ae10_slot0_24_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_16", FIELD_fld_ae10_slot0_24_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_17", FIELD_fld_ae10_slot0_24_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_18", FIELD_fld_ae10_slot0_24_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_20", FIELD_fld_ae10_slot0_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_8", FIELD_fld_ae10_slot0_24_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_3_0", FIELD_fld_ae10_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_7_4", FIELD_fld_ae10_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_7_6", FIELD_fld_ae10_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_7_7", FIELD_fld_ae10_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_8_4", FIELD_fld_ae10_slot0_8_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_0_0", FIELD_fld_ae10_slot1_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_17_13", FIELD_fld_ae10_slot1_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_17_8", FIELD_fld_ae10_slot1_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_1", FIELD_fld_ae10_slot1_25_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_12", FIELD_fld_ae10_slot1_25_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_13", FIELD_fld_ae10_slot1_25_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_16", FIELD_fld_ae10_slot1_25_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_17", FIELD_fld_ae10_slot1_25_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_18", FIELD_fld_ae10_slot1_25_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_20", FIELD_fld_ae10_slot1_25_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_22", FIELD_fld_ae10_slot1_25_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_23", FIELD_fld_ae10_slot1_25_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_8", FIELD_fld_ae10_slot1_25_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_9", FIELD_fld_ae10_slot1_25_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_3_0", FIELD_fld_ae10_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_3_2", FIELD_fld_ae10_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_3_3", FIELD_fld_ae10_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_7_4", FIELD_fld_ae10_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_24_20", FIELD_fld_ae10_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_29_20", FIELD_fld_ae10_slot2_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_29_25", FIELD_fld_ae10_slot2_29_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_10", FIELD_fld_ae10_slot2_34_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_14", FIELD_fld_ae10_slot2_34_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_15", FIELD_fld_ae10_slot2_34_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_20", FIELD_fld_ae10_slot2_34_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_25", FIELD_fld_ae10_slot2_34_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_30", FIELD_fld_ae10_slot2_34_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_31", FIELD_fld_ae10_slot2_34_31, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_33", FIELD_fld_ae10_slot2_34_33, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_4_0", FIELD_fld_ae10_slot2_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_9_0", FIELD_fld_ae10_slot2_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_9_5", FIELD_fld_ae10_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vq", FIELD_fld_ae_sem_hpfma_vq, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vq", FIELD_fld_ae_sem_spfma_vq, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_19_15", FIELD_fld_ae10_slot3_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_29_20", FIELD_fld_ae10_slot3_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_29_25", FIELD_fld_ae10_slot3_29_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_10", FIELD_fld_ae10_slot3_34_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_14", FIELD_fld_ae10_slot3_34_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_15", FIELD_fld_ae10_slot3_34_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_20", FIELD_fld_ae10_slot3_34_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_25", FIELD_fld_ae10_slot3_34_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_30", FIELD_fld_ae10_slot3_34_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_31", FIELD_fld_ae10_slot3_34_31, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_33", FIELD_fld_ae10_slot3_34_33, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_4_0", FIELD_fld_ae10_slot3_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_4_3", FIELD_fld_ae10_slot3_4_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_4_4", FIELD_fld_ae10_slot3_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_9_0", FIELD_fld_ae10_slot3_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_9_5", FIELD_fld_ae10_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_0", FIELD_fld_ae4_slot0_22_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_12", FIELD_fld_ae4_slot0_22_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_13", FIELD_fld_ae4_slot0_22_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_16", FIELD_fld_ae4_slot0_22_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_17", FIELD_fld_ae4_slot0_22_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_18", FIELD_fld_ae4_slot0_22_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_20", FIELD_fld_ae4_slot0_22_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_6", FIELD_fld_ae4_slot0_22_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_8", FIELD_fld_ae4_slot0_22_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_3_0", FIELD_fld_ae4_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_3_1", FIELD_fld_ae4_slot0_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_4_4", FIELD_fld_ae4_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_7_4", FIELD_fld_ae4_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_0", FIELD_fld_ae4_slot1_22_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_12", FIELD_fld_ae4_slot1_22_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_13", FIELD_fld_ae4_slot1_22_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_16", FIELD_fld_ae4_slot1_22_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_17", FIELD_fld_ae4_slot1_22_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_18", FIELD_fld_ae4_slot1_22_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_8", FIELD_fld_ae4_slot1_22_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_3_0", FIELD_fld_ae4_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_3_1", FIELD_fld_ae4_slot1_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_7_4", FIELD_fld_ae4_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_23_0", FIELD_fld_ae4_slot2_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_23_12", FIELD_fld_ae4_slot2_23_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_23_15", FIELD_fld_ae4_slot2_23_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_23_17", FIELD_fld_ae4_slot2_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_23_20", FIELD_fld_ae4_slot2_23_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_4_0", FIELD_fld_ae4_slot2_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_9_5", FIELD_fld_ae4_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_14_10", FIELD_fld_ae4_slot3_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_19_15", FIELD_fld_ae4_slot3_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_19_19", FIELD_fld_ae4_slot3_19_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_19_5", FIELD_fld_ae4_slot3_19_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_27_20", FIELD_fld_ae4_slot3_27_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_27_25", FIELD_fld_ae4_slot3_27_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_27_3", FIELD_fld_ae4_slot3_27_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_2_0", FIELD_fld_ae4_slot3_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_9_0", FIELD_fld_ae4_slot3_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_9_5", FIELD_fld_ae4_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot4_22_0", FIELD_fld_ae4_slot4_22_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot4_22_15", FIELD_fld_ae4_slot4_22_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot4_22_20", FIELD_fld_ae4_slot4_22_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot4_9_5", FIELD_fld_ae4_slot4_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_11_8", FIELD_fld_Inst_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_12_12", FIELD_fld_Inst_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_12_8", FIELD_fld_Inst_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_13_8", FIELD_fld_Inst_13_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_15_12", FIELD_fld_Inst_15_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_19_17", FIELD_fld_Inst_19_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_19_18", FIELD_fld_Inst_19_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_23_12", FIELD_fld_Inst_23_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_23_16", FIELD_fld_Inst_23_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_4_4", FIELD_fld_Inst_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_5_4", FIELD_fld_Inst_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_7_4", FIELD_fld_Inst_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_7_6", FIELD_fld_Inst_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_7_7", FIELD_fld_Inst_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_9_8", FIELD_fld_Inst_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 } +}; + +enum xtensa_operand_id { + OPERAND_soffsetx4, + OPERAND_immr, + OPERAND_uimm12x8, + OPERAND_simm4, + OPERAND_arr, + OPERAND_ars, + OPERAND__ars_invisible, + OPERAND_art, + OPERAND_ar0, + OPERAND_ar4, + OPERAND_ar8, + OPERAND_ar12, + OPERAND_ars_entry, + OPERAND_immrx4, + OPERAND_lsi4x4, + OPERAND_simm7, + OPERAND_uimm6, + OPERAND_ai4const, + OPERAND_b4const, + OPERAND_b4constu, + OPERAND_immt, + OPERAND_uimms8, + OPERAND_uimm8, + OPERAND_uimm8x2, + OPERAND_uimm8x4, + OPERAND_uimm4x16, + OPERAND_uimmrx4, + OPERAND_simm8, + OPERAND_simm8x256, + OPERAND_simm12b, + OPERAND_msalp32, + OPERAND_op2p1, + OPERAND_label8, + OPERAND_ulabel8, + OPERAND_label12, + OPERAND_soffset, + OPERAND_uimm16x4, + OPERAND_bbi, + OPERAND_sae, + OPERAND_sas, + OPERAND_sargt, + OPERAND_s, + OPERAND_imms, + OPERAND_imms1, + OPERAND_bt, + OPERAND_bs, + OPERAND_br, + OPERAND_bt2, + OPERAND_bs2, + OPERAND_br2, + OPERAND_bt4, + OPERAND_bs4, + OPERAND_br4, + OPERAND_bt8, + OPERAND_bs8, + OPERAND_br8, + OPERAND_bt16, + OPERAND_bs16, + OPERAND_br16, + OPERAND_brall, + OPERAND_tp7, + OPERAND_xt_wbr15_label, + OPERAND_xt_wbr18_label, + OPERAND_ae_uimm2x2, + OPERAND_opnd_ae_sem_dr_to_dr_v, + OPERAND_opnd_ae_sem_arithmetic_v, + OPERAND_opnd_ae_sem_arithmetic_v0, + OPERAND_opnd_ae_sem_arithmetic_v1, + OPERAND_opnd_ae_sem_loads_stores_a_0, + OPERAND_opnd_ae_sem_loads_stores_x, + OPERAND_opnd_ae_sem_loads_stores_end, + OPERAND_opnd_ae_sem_loads_stores_i64, + OPERAND_opnd_ae_sem_lb_ops_iba, + OPERAND_opnd_ae_sem_sb_loads_stores_iba, + OPERAND_opnd_ae_sem_pks_d, + OPERAND_opnd_ae_sem_pks_pos, + OPERAND_opnd_ae_sem_pks_s, + OPERAND_opnd_ae_sem_dr_to_ar_a, + OPERAND_opnd_ae_sem_dr_to_ar_v0, + OPERAND_opnd_ae_sem_dr_to_dr_v0, + OPERAND_opnd_ae_sem_dr_to_ar_ab, + OPERAND_opnd_ae_sem_dr_to_ar_ai, + OPERAND_opnd_ae_sem_dr_to_ar_aoe, + OPERAND_opnd_ae_sem_dr_to_dr_movi_imm, + OPERAND_opnd_ae_sem_dr_to_dr_ds, + OPERAND_opnd_ae_sem_dr_to_dr_v1, + OPERAND_opnd_ae_sem_dr_to_ar_imm8, + OPERAND_opnd_ae_sem_shift_a0, + OPERAND_opnd_ae_sem_shift_d, + OPERAND_opnd_ae_sem_shift_d0, + OPERAND_opnd_ae_sem_dr_to_ar_d, + OPERAND_opnd_ae_sem_dr_to_ar_d0, + OPERAND_opnd_ae_sem_dr_to_ar_d1, + OPERAND_opnd_ae_sem_dr_to_dr_imm2, + OPERAND_opnd_ae_sem_arithmetic_ds, + OPERAND_opnd_ae_sem_loads_stores_uu, + OPERAND_opnd_ae_sem_loads_stores_vu, + OPERAND_opnd_ae_sem_loads_stores_i32, + OPERAND_opnd_ae_sem_loads_stores_v, + OPERAND_opnd_ae_sem_loads_stores_i16, + OPERAND_opnd_ae_sem_loads_stores_i8, + OPERAND_opnd_ae_sem_loads_stores_i64pos, + OPERAND_opnd_ae_sem_loads_stores_i64neg, + OPERAND_opnd_ae_sem_loads_stores_i64half, + OPERAND_opnd_ae_sem_loads_stores_su, + OPERAND_opnd_ae_sem_loads_stores_v1, + OPERAND_opnd_ae_sem_loads_stores_av, + OPERAND_opnd_ae_sem_shift_i16, + OPERAND_opnd_ae_sem_shift_i32, + OPERAND_opnd_ae_sem_shift_d1, + OPERAND_opnd_ae_sem_shift_da, + OPERAND_opnd_ae_sem_shift_imm32, + OPERAND_opnd_ae_sem_shift_a, + OPERAND_opnd_ae_sem_shift_sd, + OPERAND_opnd_ae_sem_shift_i64, + OPERAND_opnd_ae_sem_shift_imm8, + OPERAND_opnd_ae_sem_dr_to_dr_immed, + OPERAND_opnd_ae_sem_arithmetic_art, + OPERAND_opnd_ae_sem_arithmetic_va, + OPERAND_opnd_ae_sem_arithmetic_vs, + OPERAND_opnd_ae_sem_loads_stores_i128, + OPERAND_opnd_ae_sem_loads_stores_av1, + OPERAND_opnd_ae_sem_loads_stores_imm2, + OPERAND_opnd_ae_sem_loads_stores_i3, + OPERAND_opnd_ae_sem_rng_v0, + OPERAND_opnd_ae_sem_rng_v1, + OPERAND_opnd_ae_sem_reduction_sort_v, + OPERAND_opnd_ae_sem_reduction_sort_v0, + OPERAND_opnd_ae_sem_reduction_sort_ds, + OPERAND_opnd_ae_sem_multiply_d0, + OPERAND_opnd_ae_sem_multiply_d2, + OPERAND_opnd_ae_sem_multiply_q0, + OPERAND_opnd_ae_sem_multiply_q1, + OPERAND_opnd_ae_sem_dr_to_dr_immed_N, + OPERAND_opnd_ae_sem_dr_to_ar_ei, + OPERAND_opnd_ae_sem_dr_to_ar_eo, + OPERAND_opnd_ae_sem_multiply_acc_ep, + OPERAND_opnd_ae_sem_arithmetic_e, + OPERAND_opnd_ae_sem_arithmetic_ep, + OPERAND_opnd_ae_sem_arithmetic_ep1, + OPERAND_opnd_ae_sem_select_ss, + OPERAND_opnd_ae_sem_select_vr, + OPERAND_opnd_ae_sem_select_vs, + OPERAND_opnd_ae_sem_select_vt, + OPERAND_opnd_ae_sem_select_vu, + OPERAND_opnd_ae_sem_select_isel, + OPERAND_opnd_ae_sem_shift_e, + OPERAND_opnd_ae_sem_shift_i8, + OPERAND_opnd_ae_sem_multiply_d1, + OPERAND_opnd_ae_sem_multiply_d3, + OPERAND_opnd_ae_sem_dr_to_dr_imm, + OPERAND_opnd_ae_sem_rng_d, + OPERAND_opnd_ae_sem_sb_loads_stores_iba2, + OPERAND_opnd_ae_sem_dr_to_ar_ar_s, + OPERAND_opnd_AE_ARDECNORM16_ar_u, + OPERAND_opnd_ae_sem_rng_a, + OPERAND_opnd_ae_sem_rng_art, + OPERAND_opnd_ae_sem_rng_i2, + OPERAND_opnd_ae_sem_rng_imm2, + OPERAND_opnd_ae_sem_lb_db_ops_ar_u, + OPERAND_opnd_ae_sem_lb_db_ops_iba, + OPERAND_opnd_ae_sem_dr_to_ar_vr, + OPERAND_opnd_ae_sem_spmisc_brt, + OPERAND_opnd_ae_sem_spmisc_vr, + OPERAND_opnd_ae_sem_spmisc_vs, + OPERAND_opnd_ae_sem_dr_to_dr_arr, + OPERAND_opnd_ae_sem_dr_to_dr_bt, + OPERAND_opnd_ae_sem_sp32cvt_art, + OPERAND_opnd_ae_sem_sp32cvt_i_imm5, + OPERAND_opnd_ae_sem_sp32cvt_vr, + OPERAND_opnd_ae_sem_sp32cvt_vt, + OPERAND_opnd_ae_sem_sp32cvt_arr, + OPERAND_opnd_ae_sem_movfpstate_v, + OPERAND_opnd_ae_sem_fpmov_vr, + OPERAND_opnd_ae_sem_fpmov_vt, + OPERAND_opnd_ae_sem_fpmov_i_imm4, + OPERAND_opnd_ae_sem_fpmov_vs, + OPERAND_opnd_ae_sem_fpmov_vu, + OPERAND_opnd_ae_sem_spmisc_vsM, + OPERAND_opnd_ae_sem_spmisc_vtM, + OPERAND_opnd_ae_sem_spmisc_vt, + OPERAND_opnd_ae_sem_spaddsub_vr, + OPERAND_opnd_ae_sem_spaddsub_vs, + OPERAND_opnd_ae_sem_spaddsub_vt, + OPERAND_opnd_ae_sem_spaddsub_vu, + OPERAND_opnd_ae_sem_spfma_vr, + OPERAND_opnd_ae_sem_spfma_vs, + OPERAND_opnd_ae_sem_spfma_vt, + OPERAND_opnd_ae_sem_spfma_vp, + OPERAND_opnd_ae_sem_spfma_i_imm1, + OPERAND_opnd_ae_sem_spfma_i_imm3, + OPERAND_opnd_ae_sem_spaddsub_vp, + OPERAND_opnd_ae_sem_spaddsub_vq, + OPERAND_opnd_ae_sem_spfma_vu, + OPERAND_opnd_ae_sem_spfma_vq, + OPERAND_opnd_ae_sem_hprminmaxnum_vr, + OPERAND_opnd_ae_sem_hprminmaxnum_vt, + OPERAND_opnd_ae_sem_hpcmp_br4t, + OPERAND_opnd_ae_sem_hpcmp_vr, + OPERAND_opnd_ae_sem_hpcmp_vs, + OPERAND_opnd_ae_sem_hpcnv_art, + OPERAND_opnd_ae_sem_hpcnv_i_imm4, + OPERAND_opnd_ae_sem_hpcnv_vr, + OPERAND_opnd_ae_sem_hpcnv_arr, + OPERAND_opnd_ae_sem_hpcnv_vt, + OPERAND_opnd_ae_sem_hpcmp_vt, + OPERAND_opnd_ae_sem_hpcnv_vs, + OPERAND_opnd_ae_sem_hpfma_vr, + OPERAND_opnd_ae_sem_hpfma_vs, + OPERAND_opnd_ae_sem_hpfma_vt, + OPERAND_opnd_ae_sem_hpfma_vp, + OPERAND_opnd_ae_sem_hpfma_vu, + OPERAND_opnd_ae_sem_hpfma_vq, + OPERAND_opnd_ae_sem_mul_nn_c0, + OPERAND_opnd_ae_sem_mul_nn_c1, + OPERAND_opnd_ae_sem_mul_nn_c2, + OPERAND_opnd_ae_sem_mul_nn_c3, + OPERAND_opnd_ae_sem_mul_nn_q0, + OPERAND_opnd_ae_sem_mul_nn_q1, + OPERAND_opnd_ae_sem_mul_nn_v0, + OPERAND_opnd_ae_sem_mul_nn_v1, + OPERAND_opnd_ae_sem_mul_nn_q2, + OPERAND_opnd_ae_sem_mul_nn_q3, + OPERAND_opnd_ae_sem_mul_nn_v2, + OPERAND_opnd_ae_sem_mul_nn_v3, + OPERAND_bitindex, + OPERAND_t, + OPERAND_bbi4, + OPERAND_imm12, + OPERAND_imm8, + OPERAND_s8, + OPERAND_imms8, + OPERAND_imm12b, + OPERAND_imm16, + OPERAND_m, + OPERAND_n, + OPERAND_offset, + OPERAND_op0, + OPERAND_op1, + OPERAND_op2, + OPERAND_r, + OPERAND_r_disp, + OPERAND_r_3, + OPERAND_sa4, + OPERAND_sae4, + OPERAND_sal, + OPERAND_sas4, + OPERAND_sr, + OPERAND_st, + OPERAND_thi3, + OPERAND_imm4, + OPERAND_mn, + OPERAND_i, + OPERAND_imm6lo, + OPERAND_imm6hi, + OPERAND_imm7lo, + OPERAND_imm7hi, + OPERAND_z, + OPERAND_imm6, + OPERAND_imm7, + OPERAND_t2, + OPERAND_s2, + OPERAND_r2, + OPERAND_t4, + OPERAND_s4, + OPERAND_r4, + OPERAND_t8, + OPERAND_r8, + OPERAND_xt_wbr15_imm, + OPERAND_xt_wbr18_imm, + OPERAND_ae_fld_Inst16b_12, + OPERAND_ae_fld_Inst16b_15_13, + OPERAND_fld_ae_sem_arithmetic_art, + OPERAND_fld_ae_sem_arithmetic_ds, + OPERAND_fld_ae_sem_arithmetic_v, + OPERAND_fld_ae_sem_arithmetic_v0, + OPERAND_fld_ae_sem_arithmetic_v1, + OPERAND_fld_ae_sem_arithmetic_va, + OPERAND_fld_ae_sem_arithmetic_vs, + OPERAND_fld_ae_sem_dr_to_ar_a, + OPERAND_fld_ae_sem_dr_to_ar_ab, + OPERAND_fld_ae_sem_dr_to_ar_ai, + OPERAND_fld_ae_sem_dr_to_ar_aoe, + OPERAND_fld_ae_sem_dr_to_ar_d, + OPERAND_fld_ae_sem_dr_to_ar_d0, + OPERAND_fld_ae_sem_dr_to_ar_d1, + OPERAND_fld_ae_sem_dr_to_ar_imm8, + OPERAND_fld_ae_sem_dr_to_ar_v0, + OPERAND_fld_ae_sem_dr_to_ar_vr, + OPERAND_fld_ae_sem_dr_to_dr_arr, + OPERAND_fld_ae_sem_dr_to_dr_bt, + OPERAND_fld_ae_sem_dr_to_dr_ds, + OPERAND_fld_ae_sem_dr_to_dr_imm2, + OPERAND_fld_ae_sem_dr_to_dr_immed, + OPERAND_fld_ae_sem_dr_to_dr_movi_imm, + OPERAND_fld_ae_sem_dr_to_dr_v, + OPERAND_fld_ae_sem_dr_to_dr_v0, + OPERAND_fld_ae_sem_dr_to_dr_v1, + OPERAND_fld_ae_sem_hpcmp_br4t, + OPERAND_fld_ae_sem_hpcmp_vr, + OPERAND_fld_ae_sem_hpcmp_vs, + OPERAND_fld_ae_sem_hpcnv_arr, + OPERAND_fld_ae_sem_hpcnv_art, + OPERAND_fld_ae_sem_hpcnv_i_imm4, + OPERAND_fld_ae_sem_hpcnv_vr, + OPERAND_fld_ae_sem_hpcnv_vt, + OPERAND_fld_ae_sem_hprminmaxnum_vr, + OPERAND_fld_ae_sem_hprminmaxnum_vt, + OPERAND_fld_ae_sem_lb_ops_iba, + OPERAND_fld_ae_sem_loads_stores_a, + OPERAND_fld_ae_sem_loads_stores_a_0, + OPERAND_fld_ae_sem_loads_stores_av, + OPERAND_fld_ae_sem_loads_stores_av1, + OPERAND_fld_ae_sem_loads_stores_end, + OPERAND_fld_ae_sem_loads_stores_i128, + OPERAND_fld_ae_sem_loads_stores_i16, + OPERAND_fld_ae_sem_loads_stores_i3, + OPERAND_fld_ae_sem_loads_stores_i32, + OPERAND_fld_ae_sem_loads_stores_i32pos, + OPERAND_fld_ae_sem_loads_stores_i64, + OPERAND_fld_ae_sem_loads_stores_i64half, + OPERAND_fld_ae_sem_loads_stores_i64neg, + OPERAND_fld_ae_sem_loads_stores_i64pos, + OPERAND_fld_ae_sem_loads_stores_i64x2, + OPERAND_fld_ae_sem_loads_stores_i8, + OPERAND_fld_ae_sem_loads_stores_imm2, + OPERAND_fld_ae_sem_loads_stores_su, + OPERAND_fld_ae_sem_loads_stores_uu, + OPERAND_fld_ae_sem_loads_stores_v, + OPERAND_fld_ae_sem_loads_stores_v1, + OPERAND_fld_ae_sem_loads_stores_vu, + OPERAND_fld_ae_sem_loads_stores_x, + OPERAND_fld_ae_sem_pks_d, + OPERAND_fld_ae_sem_pks_pos, + OPERAND_fld_ae_sem_pks_s, + OPERAND_fld_ae_sem_rng_v0, + OPERAND_fld_ae_sem_rng_v1, + OPERAND_fld_ae_sem_sb_loads_stores_iba, + OPERAND_fld_ae_sem_shift_a, + OPERAND_fld_ae_sem_shift_a0, + OPERAND_fld_ae_sem_shift_d, + OPERAND_fld_ae_sem_shift_d0, + OPERAND_fld_ae_sem_shift_d1, + OPERAND_fld_ae_sem_shift_da, + OPERAND_fld_ae_sem_shift_i16, + OPERAND_fld_ae_sem_shift_i32, + OPERAND_fld_ae_sem_shift_i64, + OPERAND_fld_ae_sem_shift_imm32, + OPERAND_fld_ae_sem_shift_imm8, + OPERAND_fld_ae_sem_shift_sd, + OPERAND_fld_ae_sem_sp32cvt_arr, + OPERAND_fld_ae_sem_sp32cvt_art, + OPERAND_fld_ae_sem_sp32cvt_i_imm5, + OPERAND_fld_ae_sem_sp32cvt_vr, + OPERAND_fld_ae_sem_sp32cvt_vt, + OPERAND_fld_ae_sem_spmisc_brt, + OPERAND_fld_ae_sem_spmisc_vr, + OPERAND_fld_ae_sem_spmisc_vs, + OPERAND_fld_ae_slot0_11_10, + OPERAND_fld_ae_slot0_11_11, + OPERAND_fld_ae_slot0_11_8, + OPERAND_fld_ae_slot0_11_9, + OPERAND_fld_ae_slot0_12_0, + OPERAND_fld_ae_slot0_12_10, + OPERAND_fld_ae_slot0_12_12, + OPERAND_fld_ae_slot0_12_2, + OPERAND_fld_ae_slot0_12_6, + OPERAND_fld_ae_slot0_12_8, + OPERAND_fld_ae_slot0_12_9, + OPERAND_fld_ae_slot0_14_12, + OPERAND_fld_ae_slot0_14_13, + OPERAND_fld_ae_slot0_17_10, + OPERAND_fld_ae_slot0_17_12, + OPERAND_fld_ae_slot0_17_13, + OPERAND_fld_ae_slot0_17_14, + OPERAND_fld_ae_slot0_17_15, + OPERAND_fld_ae_slot0_17_16, + OPERAND_fld_ae_slot0_17_17, + OPERAND_fld_ae_slot0_17_8, + OPERAND_fld_ae_slot0_18_13, + OPERAND_fld_ae_slot0_18_15, + OPERAND_fld_ae_slot0_18_16, + OPERAND_fld_ae_slot0_18_8, + OPERAND_fld_ae_slot0_19_12, + OPERAND_fld_ae_slot0_19_15, + OPERAND_fld_ae_slot0_19_19, + OPERAND_fld_ae_slot0_19_8, + OPERAND_fld_ae_slot0_1_0, + OPERAND_fld_ae_slot0_1_1, + OPERAND_fld_ae_slot0_20_16, + OPERAND_fld_ae_slot0_20_20, + OPERAND_fld_ae_slot0_23_15, + OPERAND_fld_ae_slot0_23_17, + OPERAND_fld_ae_slot0_23_19, + OPERAND_fld_ae_slot0_23_22, + OPERAND_fld_ae_slot0_28_10, + OPERAND_fld_ae_slot0_28_12, + OPERAND_fld_ae_slot0_28_14, + OPERAND_fld_ae_slot0_28_15, + OPERAND_fld_ae_slot0_28_16, + OPERAND_fld_ae_slot0_28_17, + OPERAND_fld_ae_slot0_28_19, + OPERAND_fld_ae_slot0_28_21, + OPERAND_fld_ae_slot0_28_22, + OPERAND_fld_ae_slot0_28_24, + OPERAND_fld_ae_slot0_28_26, + OPERAND_fld_ae_slot0_28_27, + OPERAND_fld_ae_slot0_28_4, + OPERAND_fld_ae_slot0_28_8, + OPERAND_fld_ae_slot0_3_0, + OPERAND_fld_ae_slot0_3_1, + OPERAND_fld_ae_slot0_3_2, + OPERAND_fld_ae_slot0_3_3, + OPERAND_fld_ae_slot0_4_0, + OPERAND_fld_ae_slot0_4_4, + OPERAND_fld_ae_slot0_5_0, + OPERAND_fld_ae_slot0_5_4, + OPERAND_fld_ae_slot0_7_0, + OPERAND_fld_ae_slot0_7_2, + OPERAND_fld_ae_slot0_7_3, + OPERAND_fld_ae_slot0_7_4, + OPERAND_fld_ae_slot0_8_8, + OPERAND_fld_ae_slot0_9_4, + OPERAND_fld_ae_slot0_9_8, + OPERAND_fld_ae_slot0_9_9, + OPERAND_fld_ae_slot1_0_0, + OPERAND_fld_ae_slot1_12_8, + OPERAND_fld_ae_slot1_17_13, + OPERAND_fld_ae_slot1_17_17, + OPERAND_fld_ae_slot1_17_8, + OPERAND_fld_ae_slot1_25_1, + OPERAND_fld_ae_slot1_25_12, + OPERAND_fld_ae_slot1_25_13, + OPERAND_fld_ae_slot1_25_16, + OPERAND_fld_ae_slot1_25_17, + OPERAND_fld_ae_slot1_25_18, + OPERAND_fld_ae_slot1_25_20, + OPERAND_fld_ae_slot1_25_22, + OPERAND_fld_ae_slot1_25_23, + OPERAND_fld_ae_slot1_25_8, + OPERAND_fld_ae_slot1_25_9, + OPERAND_fld_ae_slot1_3_0, + OPERAND_fld_ae_slot1_3_2, + OPERAND_fld_ae_slot1_3_3, + OPERAND_fld_ae_slot1_7_4, + OPERAND_fld_ae_sem_arithmetic_e, + OPERAND_fld_ae_sem_arithmetic_ep, + OPERAND_fld_ae_sem_arithmetic_ep1, + OPERAND_fld_ae_sem_dr_to_ar_ei, + OPERAND_fld_ae_sem_dr_to_ar_eo, + OPERAND_fld_ae_sem_dr_to_dr_immed_N, + OPERAND_fld_ae_sem_fpmov_i_imm4, + OPERAND_fld_ae_sem_fpmov_vr, + OPERAND_fld_ae_sem_fpmov_vs, + OPERAND_fld_ae_sem_fpmov_vt, + OPERAND_fld_ae_sem_fpmov_vu, + OPERAND_fld_ae_sem_hpcmp_vt, + OPERAND_fld_ae_sem_hpcnv_vs, + OPERAND_fld_ae_sem_hpfma_vr, + OPERAND_fld_ae_sem_hpfma_vs, + OPERAND_fld_ae_sem_hpfma_vt, + OPERAND_fld_ae_sem_movfpstate_v, + OPERAND_fld_ae_sem_multiply_acc_ep, + OPERAND_fld_ae_sem_multiply_d0, + OPERAND_fld_ae_sem_multiply_d2, + OPERAND_fld_ae_sem_multiply_q0, + OPERAND_fld_ae_sem_multiply_q1, + OPERAND_fld_ae_sem_reduction_sort_ds, + OPERAND_fld_ae_sem_reduction_sort_v, + OPERAND_fld_ae_sem_reduction_sort_v0, + OPERAND_fld_ae_sem_select_isel, + OPERAND_fld_ae_sem_select_ss, + OPERAND_fld_ae_sem_select_vr, + OPERAND_fld_ae_sem_select_vs, + OPERAND_fld_ae_sem_select_vt, + OPERAND_fld_ae_sem_select_vu, + OPERAND_fld_ae_sem_spaddsub_vr, + OPERAND_fld_ae_sem_spaddsub_vs, + OPERAND_fld_ae_sem_spaddsub_vt, + OPERAND_fld_ae_sem_spaddsub_vu, + OPERAND_fld_ae_sem_spfma_i_imm1, + OPERAND_fld_ae_sem_spfma_i_imm3, + OPERAND_fld_ae_sem_spfma_vp, + OPERAND_fld_ae_sem_spfma_vr, + OPERAND_fld_ae_sem_spfma_vs, + OPERAND_fld_ae_sem_spfma_vt, + OPERAND_fld_ae_sem_spmisc_vsM, + OPERAND_fld_ae_sem_spmisc_vt, + OPERAND_fld_ae_sem_spmisc_vtM, + OPERAND_fld_ae_slot2_14_0, + OPERAND_fld_ae_slot2_14_10, + OPERAND_fld_ae_slot2_14_14, + OPERAND_fld_ae_slot2_14_5, + OPERAND_fld_ae_slot2_16_15, + OPERAND_fld_ae_slot2_19_15, + OPERAND_fld_ae_slot2_28_15, + OPERAND_fld_ae_slot2_28_17, + OPERAND_fld_ae_slot2_28_19, + OPERAND_fld_ae_slot2_28_20, + OPERAND_fld_ae_slot2_28_25, + OPERAND_fld_ae_slot2_28_4, + OPERAND_fld_ae_slot2_28_5, + OPERAND_fld_ae_slot2_3_0, + OPERAND_fld_ae_slot2_9_0, + OPERAND_fld_ae_slot2_9_1, + OPERAND_fld_ae_slot2_9_2, + OPERAND_fld_ae_slot2_9_5, + OPERAND_fld_ae_slot2_9_6, + OPERAND_fld_ae_slot2_9_7, + OPERAND_fld_ae_slot2_9_8, + OPERAND_fld_ae_sem_dr_to_dr_imm, + OPERAND_fld_ae_sem_multiply_d1, + OPERAND_fld_ae_sem_multiply_d3, + OPERAND_fld_ae_sem_rng_d, + OPERAND_fld_ae_sem_shift_e, + OPERAND_fld_ae_sem_shift_i8, + OPERAND_fld_ae_slot3_11_0, + OPERAND_fld_ae_slot3_14_0, + OPERAND_fld_ae_slot3_14_10, + OPERAND_fld_ae_slot3_14_12, + OPERAND_fld_ae_slot3_14_13, + OPERAND_fld_ae_slot3_16_13, + OPERAND_fld_ae_slot3_19_0, + OPERAND_fld_ae_slot3_19_10, + OPERAND_fld_ae_slot3_19_15, + OPERAND_fld_ae_slot3_19_17, + OPERAND_fld_ae_slot3_19_18, + OPERAND_fld_ae_slot3_19_19, + OPERAND_fld_ae_slot3_24_10, + OPERAND_fld_ae_slot3_24_19, + OPERAND_fld_ae_slot3_24_20, + OPERAND_fld_ae_slot3_36_12, + OPERAND_fld_ae_slot3_36_16, + OPERAND_fld_ae_slot3_36_19, + OPERAND_fld_ae_slot3_36_20, + OPERAND_fld_ae_slot3_36_22, + OPERAND_fld_ae_slot3_36_25, + OPERAND_fld_ae_slot3_36_30, + OPERAND_fld_ae_slot3_4_0, + OPERAND_fld_ae_slot3_9_0, + OPERAND_fld_ae_slot3_9_1, + OPERAND_fld_ae_slot3_9_3, + OPERAND_fld_ae_slot3_9_5, + OPERAND_fld_ae2_slot0_0_0, + OPERAND_fld_ae2_slot0_11_4, + OPERAND_fld_ae2_slot0_11_8, + OPERAND_fld_ae2_slot0_11_9, + OPERAND_fld_ae2_slot0_12_0, + OPERAND_fld_ae2_slot0_12_2, + OPERAND_fld_ae2_slot0_12_4, + OPERAND_fld_ae2_slot0_12_8, + OPERAND_fld_ae2_slot0_14_13, + OPERAND_fld_ae2_slot0_14_8, + OPERAND_fld_ae2_slot0_15_0, + OPERAND_fld_ae2_slot0_15_12, + OPERAND_fld_ae2_slot0_15_13, + OPERAND_fld_ae2_slot0_15_15, + OPERAND_fld_ae2_slot0_15_4, + OPERAND_fld_ae2_slot0_15_8, + OPERAND_fld_ae2_slot0_17_13, + OPERAND_fld_ae2_slot0_17_17, + OPERAND_fld_ae2_slot0_18_15, + OPERAND_fld_ae2_slot0_18_17, + OPERAND_fld_ae2_slot0_18_18, + OPERAND_fld_ae2_slot0_1_0, + OPERAND_fld_ae2_slot0_23_18, + OPERAND_fld_ae2_slot0_23_19, + OPERAND_fld_ae2_slot0_3_0, + OPERAND_fld_ae2_slot0_40_16, + OPERAND_fld_ae2_slot0_40_17, + OPERAND_fld_ae2_slot0_40_18, + OPERAND_fld_ae2_slot0_40_19, + OPERAND_fld_ae2_slot0_40_21, + OPERAND_fld_ae2_slot0_40_23, + OPERAND_fld_ae2_slot0_40_24, + OPERAND_fld_ae2_slot0_40_25, + OPERAND_fld_ae2_slot0_40_26, + OPERAND_fld_ae2_slot0_40_27, + OPERAND_fld_ae2_slot0_7_0, + OPERAND_fld_ae2_slot0_7_4, + OPERAND_fld_ae2_slot0_7_6, + OPERAND_fld_ae2_slot0_7_7, + OPERAND_fld_ae2_slot0_8_8, + OPERAND_fld_ae2_slot0_9_8, + OPERAND_fld_ae2_slot1_0_0, + OPERAND_fld_ae2_slot1_11_0, + OPERAND_fld_ae2_slot1_11_10, + OPERAND_fld_ae2_slot1_11_8, + OPERAND_fld_ae2_slot1_14_10, + OPERAND_fld_ae2_slot1_14_11, + OPERAND_fld_ae2_slot1_14_12, + OPERAND_fld_ae2_slot1_14_14, + OPERAND_fld_ae2_slot1_14_8, + OPERAND_fld_ae2_slot1_36_12, + OPERAND_fld_ae2_slot1_36_14, + OPERAND_fld_ae2_slot1_36_15, + OPERAND_fld_ae2_slot1_36_16, + OPERAND_fld_ae2_slot1_36_17, + OPERAND_fld_ae2_slot1_36_18, + OPERAND_fld_ae2_slot1_36_20, + OPERAND_fld_ae2_slot1_36_22, + OPERAND_fld_ae2_slot1_36_23, + OPERAND_fld_ae2_slot1_3_0, + OPERAND_fld_ae2_slot1_3_1, + OPERAND_fld_ae2_slot1_3_2, + OPERAND_fld_ae2_slot1_3_3, + OPERAND_fld_ae2_slot1_7_4, + OPERAND_fld_ae2_slot1_9_8, + OPERAND_fld_ae2_slot1_9_9, + OPERAND_fld_ae2_slot2_14_10, + OPERAND_fld_ae2_slot2_17_0, + OPERAND_fld_ae2_slot2_17_10, + OPERAND_fld_ae2_slot2_17_15, + OPERAND_fld_ae2_slot2_17_17, + OPERAND_fld_ae2_slot2_19_10, + OPERAND_fld_ae2_slot2_19_15, + OPERAND_fld_ae2_slot2_19_18, + OPERAND_fld_ae2_slot2_19_9, + OPERAND_fld_ae2_slot2_24_10, + OPERAND_fld_ae2_slot2_24_15, + OPERAND_fld_ae2_slot2_24_20, + OPERAND_fld_ae2_slot2_24_5, + OPERAND_fld_ae2_slot2_24_9, + OPERAND_fld_ae2_slot2_42_18, + OPERAND_fld_ae2_slot2_42_20, + OPERAND_fld_ae2_slot2_42_25, + OPERAND_fld_ae2_slot2_42_26, + OPERAND_fld_ae2_slot2_42_28, + OPERAND_fld_ae2_slot2_42_30, + OPERAND_fld_ae2_slot2_4_0, + OPERAND_fld_ae2_slot2_9_5, + OPERAND_fld_ae_sem_spaddsub_vp, + OPERAND_fld_ae_sem_spaddsub_vq, + OPERAND_fld_ae3_slot0_11_11, + OPERAND_fld_ae3_slot0_11_4, + OPERAND_fld_ae3_slot0_11_8, + OPERAND_fld_ae3_slot0_12_12, + OPERAND_fld_ae3_slot0_12_8, + OPERAND_fld_ae3_slot0_13_13, + OPERAND_fld_ae3_slot0_13_8, + OPERAND_fld_ae3_slot0_1_0, + OPERAND_fld_ae3_slot0_32_11, + OPERAND_fld_ae3_slot0_32_12, + OPERAND_fld_ae3_slot0_32_13, + OPERAND_fld_ae3_slot0_32_14, + OPERAND_fld_ae3_slot0_32_15, + OPERAND_fld_ae3_slot0_32_16, + OPERAND_fld_ae3_slot0_32_17, + OPERAND_fld_ae3_slot0_32_18, + OPERAND_fld_ae3_slot0_32_20, + OPERAND_fld_ae3_slot0_32_27, + OPERAND_fld_ae3_slot0_32_8, + OPERAND_fld_ae3_slot0_3_0, + OPERAND_fld_ae3_slot0_3_2, + OPERAND_fld_ae3_slot0_3_3, + OPERAND_fld_ae3_slot0_4_0, + OPERAND_fld_ae3_slot0_4_4, + OPERAND_fld_ae3_slot0_5_0, + OPERAND_fld_ae3_slot0_5_4, + OPERAND_fld_ae3_slot0_7_0, + OPERAND_fld_ae3_slot0_7_2, + OPERAND_fld_ae3_slot0_7_4, + OPERAND_fld_ae3_slot0_7_6, + OPERAND_fld_ae3_slot0_8_8, + OPERAND_fld_ae3_slot0_9_4, + OPERAND_fld_ae3_slot0_9_8, + OPERAND_fld_ae_sem_dr_to_ar_ar_s, + OPERAND_fld_ae_sem_sb_loads_stores_iba2, + OPERAND_fld_ae3_slot1_23_0, + OPERAND_fld_ae3_slot1_23_11, + OPERAND_fld_ae3_slot1_23_12, + OPERAND_fld_ae3_slot1_23_13, + OPERAND_fld_ae3_slot1_23_15, + OPERAND_fld_ae3_slot1_23_16, + OPERAND_fld_ae3_slot1_23_17, + OPERAND_fld_ae3_slot1_23_19, + OPERAND_fld_ae3_slot1_23_6, + OPERAND_fld_ae3_slot1_23_8, + OPERAND_fld_ae3_slot1_23_9, + OPERAND_fld_ae3_slot1_3_0, + OPERAND_fld_ae3_slot1_3_1, + OPERAND_fld_ae3_slot1_3_2, + OPERAND_fld_ae3_slot1_3_3, + OPERAND_fld_ae3_slot1_7_4, + OPERAND_fld_ae3_slot1_9_8, + OPERAND_fld_AE_ARDECNORM16_ar_u, + OPERAND_fld_ae5_slot0_11_10, + OPERAND_fld_ae5_slot0_11_4, + OPERAND_fld_ae5_slot0_11_8, + OPERAND_fld_ae5_slot0_11_9, + OPERAND_fld_ae5_slot0_12_10, + OPERAND_fld_ae5_slot0_12_4, + OPERAND_fld_ae5_slot0_12_6, + OPERAND_fld_ae5_slot0_12_8, + OPERAND_fld_ae5_slot0_12_9, + OPERAND_fld_ae5_slot0_1_0, + OPERAND_fld_ae5_slot0_1_1, + OPERAND_fld_ae5_slot0_29_12, + OPERAND_fld_ae5_slot0_29_13, + OPERAND_fld_ae5_slot0_29_15, + OPERAND_fld_ae5_slot0_29_16, + OPERAND_fld_ae5_slot0_29_17, + OPERAND_fld_ae5_slot0_29_18, + OPERAND_fld_ae5_slot0_29_19, + OPERAND_fld_ae5_slot0_29_20, + OPERAND_fld_ae5_slot0_29_27, + OPERAND_fld_ae5_slot0_29_5, + OPERAND_fld_ae5_slot0_29_6, + OPERAND_fld_ae5_slot0_29_8, + OPERAND_fld_ae5_slot0_2_0, + OPERAND_fld_ae5_slot0_3_0, + OPERAND_fld_ae5_slot0_3_2, + OPERAND_fld_ae5_slot0_4_0, + OPERAND_fld_ae5_slot0_4_4, + OPERAND_fld_ae5_slot0_7_0, + OPERAND_fld_ae5_slot0_7_4, + OPERAND_fld_ae5_slot0_7_7, + OPERAND_fld_ae5_slot0_8_8, + OPERAND_fld_ae_sem_lb_db_ops_ar_u, + OPERAND_fld_ae_sem_lb_db_ops_iba, + OPERAND_fld_ae_sem_rng_a, + OPERAND_fld_ae_sem_rng_art, + OPERAND_fld_ae_sem_rng_i2, + OPERAND_fld_ae_sem_rng_imm2, + OPERAND_fld_ae5_slot1_1_0, + OPERAND_fld_ae5_slot2_14_10, + OPERAND_fld_ae5_slot2_14_14, + OPERAND_fld_ae5_slot2_14_5, + OPERAND_fld_ae5_slot2_24_0, + OPERAND_fld_ae5_slot2_24_15, + OPERAND_fld_ae5_slot2_24_17, + OPERAND_fld_ae5_slot2_24_20, + OPERAND_fld_ae5_slot2_4_0, + OPERAND_fld_ae5_slot2_9_0, + OPERAND_fld_ae5_slot2_9_5, + OPERAND_fld_ae5_slot2_9_7, + OPERAND_fld_ae6_slot0_10_10, + OPERAND_fld_ae6_slot0_15_15, + OPERAND_fld_ae6_slot0_29_10, + OPERAND_fld_ae6_slot0_29_13, + OPERAND_fld_ae6_slot0_29_14, + OPERAND_fld_ae6_slot0_29_15, + OPERAND_fld_ae6_slot0_29_18, + OPERAND_fld_ae6_slot0_29_20, + OPERAND_fld_ae6_slot0_29_5, + OPERAND_fld_ae6_slot0_4_0, + OPERAND_fld_ae6_slot0_4_4, + OPERAND_fld_ae6_slot0_7_4, + OPERAND_fld_ae6_slot0_7_7, + OPERAND_fld_ae6_slot0_9_8, + OPERAND_fld_ae6_slot0_9_9, + OPERAND_fld_ae6_slot1_14_14, + OPERAND_fld_ae6_slot1_27_12, + OPERAND_fld_ae6_slot1_27_15, + OPERAND_fld_ae6_slot1_27_20, + OPERAND_fld_ae6_slot1_27_21, + OPERAND_fld_ae6_slot1_27_3, + OPERAND_fld_ae6_slot1_27_6, + OPERAND_fld_ae6_slot1_2_0, + OPERAND_fld_ae6_slot1_9_5, + OPERAND_fld_ae6_slot1_9_6, + OPERAND_fld_ae6_slot1_9_7, + OPERAND_fld_ae6_slot1_9_8, + OPERAND_fld_ae6_slot1_9_9, + OPERAND_fld_ae6_slot2_10_10, + OPERAND_fld_ae6_slot2_11_10, + OPERAND_fld_ae6_slot2_24_0, + OPERAND_fld_ae6_slot2_24_10, + OPERAND_fld_ae6_slot2_24_14, + OPERAND_fld_ae6_slot2_24_15, + OPERAND_fld_ae6_slot2_24_20, + OPERAND_fld_ae6_slot2_4_2, + OPERAND_fld_ae6_slot2_9_5, + OPERAND_fld_ae6_slot3_10_10, + OPERAND_fld_ae6_slot3_12_0, + OPERAND_fld_ae6_slot3_14_0, + OPERAND_fld_ae6_slot3_14_10, + OPERAND_fld_ae6_slot3_14_13, + OPERAND_fld_ae6_slot3_14_5, + OPERAND_fld_ae6_slot3_24_20, + OPERAND_fld_ae6_slot3_37_13, + OPERAND_fld_ae6_slot3_37_15, + OPERAND_fld_ae6_slot3_37_20, + OPERAND_fld_ae6_slot3_37_30, + OPERAND_fld_ae6_slot3_9_5, + OPERAND_fld_ae7_slot0_12_6, + OPERAND_fld_ae7_slot0_23_0, + OPERAND_fld_ae7_slot0_23_13, + OPERAND_fld_ae7_slot0_23_17, + OPERAND_fld_ae7_slot0_23_18, + OPERAND_fld_ae7_slot0_23_6, + OPERAND_fld_ae7_slot0_7_4, + OPERAND_fld_ae7_slot0_7_6, + OPERAND_fld_ae7_slot0_7_7, + OPERAND_fld_ae7_slot1_12_6, + OPERAND_fld_ae7_slot1_23_0, + OPERAND_fld_ae7_slot1_23_13, + OPERAND_fld_ae7_slot1_23_17, + OPERAND_fld_ae7_slot1_23_18, + OPERAND_fld_ae7_slot1_23_6, + OPERAND_fld_ae7_slot1_7_4, + OPERAND_fld_ae7_slot1_7_6, + OPERAND_fld_ae7_slot1_7_7, + OPERAND_fld_ae7_slot2_11_0, + OPERAND_fld_ae7_slot2_14_10, + OPERAND_fld_ae7_slot2_14_5, + OPERAND_fld_ae7_slot2_36_12, + OPERAND_fld_ae7_slot2_36_15, + OPERAND_fld_ae7_slot2_36_20, + OPERAND_fld_ae7_slot2_36_25, + OPERAND_fld_ae7_slot2_36_30, + OPERAND_fld_ae7_slot2_9_5, + OPERAND_fld_ae7_slot3_10_0, + OPERAND_fld_ae7_slot3_14_10, + OPERAND_fld_ae7_slot3_14_5, + OPERAND_fld_ae7_slot3_24_10, + OPERAND_fld_ae7_slot3_35_11, + OPERAND_fld_ae7_slot3_35_20, + OPERAND_fld_ae7_slot3_35_25, + OPERAND_fld_ae7_slot3_35_30, + OPERAND_fld_ae7_slot3_4_0, + OPERAND_fld_ae7_slot3_9_5, + OPERAND_fld_ae8_slot0_13_12, + OPERAND_fld_ae8_slot0_13_13, + OPERAND_fld_ae8_slot0_13_4, + OPERAND_fld_ae8_slot0_13_9, + OPERAND_fld_ae8_slot0_17_4, + OPERAND_fld_ae8_slot0_17_8, + OPERAND_fld_ae8_slot0_31_12, + OPERAND_fld_ae8_slot0_31_15, + OPERAND_fld_ae8_slot0_31_18, + OPERAND_fld_ae8_slot0_31_19, + OPERAND_fld_ae8_slot0_31_20, + OPERAND_fld_ae8_slot0_31_21, + OPERAND_fld_ae8_slot0_31_22, + OPERAND_fld_ae8_slot0_31_23, + OPERAND_fld_ae8_slot0_31_7, + OPERAND_fld_ae8_slot0_31_8, + OPERAND_fld_ae8_slot0_31_9, + OPERAND_fld_ae8_slot0_3_0, + OPERAND_fld_ae8_slot0_6_0, + OPERAND_fld_ae8_slot0_7_4, + OPERAND_fld_ae8_slot0_7_5, + OPERAND_fld_ae8_slot0_7_7, + OPERAND_fld_ae8_slot0_8_0, + OPERAND_fld_ae8_slot1_17_13, + OPERAND_fld_ae8_slot1_17_14, + OPERAND_fld_ae8_slot1_17_15, + OPERAND_fld_ae8_slot1_17_8, + OPERAND_fld_ae8_slot1_29_12, + OPERAND_fld_ae8_slot1_29_13, + OPERAND_fld_ae8_slot1_29_18, + OPERAND_fld_ae8_slot1_29_20, + OPERAND_fld_ae8_slot1_29_22, + OPERAND_fld_ae8_slot1_29_23, + OPERAND_fld_ae8_slot1_29_5, + OPERAND_fld_ae8_slot1_29_8, + OPERAND_fld_ae8_slot1_29_9, + OPERAND_fld_ae8_slot1_3_0, + OPERAND_fld_ae8_slot1_3_3, + OPERAND_fld_ae8_slot1_4_0, + OPERAND_fld_ae8_slot1_7_4, + OPERAND_fld_ae8_slot2_19_10, + OPERAND_fld_ae8_slot2_19_15, + OPERAND_fld_ae8_slot2_33_15, + OPERAND_fld_ae8_slot2_33_25, + OPERAND_fld_ae8_slot2_33_9, + OPERAND_fld_ae8_slot2_34_30, + OPERAND_fld_ae8_slot2_39_35, + OPERAND_fld_ae8_slot2_44_35, + OPERAND_fld_ae8_slot2_58_34, + OPERAND_fld_ae8_slot2_58_35, + OPERAND_fld_ae8_slot2_58_40, + OPERAND_fld_ae8_slot2_58_50, + OPERAND_fld_ae8_slot2_8_0, + OPERAND_fld_ae8_slot2_9_0, + OPERAND_fld_ae_sem_mul_nn_c0, + OPERAND_fld_ae_sem_mul_nn_c1, + OPERAND_fld_ae_sem_mul_nn_c2, + OPERAND_fld_ae_sem_mul_nn_c3, + OPERAND_fld_ae_sem_mul_nn_q0, + OPERAND_fld_ae_sem_mul_nn_q1, + OPERAND_fld_ae_sem_mul_nn_q2, + OPERAND_fld_ae_sem_mul_nn_q3, + OPERAND_fld_ae_sem_mul_nn_v0, + OPERAND_fld_ae_sem_mul_nn_v1, + OPERAND_fld_ae_sem_mul_nn_v2, + OPERAND_fld_ae_sem_mul_nn_v3, + OPERAND_fld_ae9_slot0_0_0, + OPERAND_fld_ae9_slot0_12_12, + OPERAND_fld_ae9_slot0_12_5, + OPERAND_fld_ae9_slot0_12_8, + OPERAND_fld_ae9_slot0_17_13, + OPERAND_fld_ae9_slot0_17_4, + OPERAND_fld_ae9_slot0_17_8, + OPERAND_fld_ae9_slot0_27_10, + OPERAND_fld_ae9_slot0_27_12, + OPERAND_fld_ae9_slot0_27_13, + OPERAND_fld_ae9_slot0_27_16, + OPERAND_fld_ae9_slot0_27_17, + OPERAND_fld_ae9_slot0_27_18, + OPERAND_fld_ae9_slot0_27_19, + OPERAND_fld_ae9_slot0_27_20, + OPERAND_fld_ae9_slot0_27_22, + OPERAND_fld_ae9_slot0_27_23, + OPERAND_fld_ae9_slot0_27_3, + OPERAND_fld_ae9_slot0_27_8, + OPERAND_fld_ae9_slot0_2_0, + OPERAND_fld_ae9_slot0_3_0, + OPERAND_fld_ae9_slot0_7_0, + OPERAND_fld_ae9_slot0_7_4, + OPERAND_fld_ae9_slot0_7_5, + OPERAND_fld_ae9_slot0_7_6, + OPERAND_fld_ae9_slot0_7_7, + OPERAND_fld_ae9_slot0_8_4, + OPERAND_fld_ae9_slot0_8_5, + OPERAND_fld_ae9_slot0_9_5, + OPERAND_fld_ae9_slot1_17_13, + OPERAND_fld_ae9_slot1_17_8, + OPERAND_fld_ae9_slot1_1_0, + OPERAND_fld_ae9_slot1_26_12, + OPERAND_fld_ae9_slot1_26_13, + OPERAND_fld_ae9_slot1_26_16, + OPERAND_fld_ae9_slot1_26_17, + OPERAND_fld_ae9_slot1_26_18, + OPERAND_fld_ae9_slot1_26_2, + OPERAND_fld_ae9_slot1_26_20, + OPERAND_fld_ae9_slot1_26_22, + OPERAND_fld_ae9_slot1_26_23, + OPERAND_fld_ae9_slot1_26_8, + OPERAND_fld_ae9_slot1_26_9, + OPERAND_fld_ae9_slot1_3_0, + OPERAND_fld_ae9_slot1_3_2, + OPERAND_fld_ae9_slot1_3_3, + OPERAND_fld_ae9_slot1_7_4, + OPERAND_fld_ae9_slot2_24_14, + OPERAND_fld_ae9_slot2_24_15, + OPERAND_fld_ae9_slot2_24_20, + OPERAND_fld_ae9_slot2_33_14, + OPERAND_fld_ae9_slot2_33_15, + OPERAND_fld_ae9_slot2_33_20, + OPERAND_fld_ae9_slot2_33_25, + OPERAND_fld_ae9_slot2_33_26, + OPERAND_fld_ae9_slot2_33_28, + OPERAND_fld_ae9_slot2_33_30, + OPERAND_fld_ae9_slot2_33_9, + OPERAND_fld_ae9_slot2_4_0, + OPERAND_fld_ae9_slot2_5_0, + OPERAND_fld_ae9_slot2_6_0, + OPERAND_fld_ae9_slot2_8_0, + OPERAND_fld_ae9_slot2_9_0, + OPERAND_fld_ae9_slot2_9_5, + OPERAND_fld_ae9_slot2_9_9, + OPERAND_fld_ae_sem_hpfma_vp, + OPERAND_fld_ae_sem_hpfma_vu, + OPERAND_fld_ae_sem_spfma_vu, + OPERAND_fld_ae9_slot3_19_15, + OPERAND_fld_ae9_slot3_24_20, + OPERAND_fld_ae9_slot3_31_14, + OPERAND_fld_ae9_slot3_31_15, + OPERAND_fld_ae9_slot3_31_20, + OPERAND_fld_ae9_slot3_31_25, + OPERAND_fld_ae9_slot3_31_26, + OPERAND_fld_ae9_slot3_31_28, + OPERAND_fld_ae9_slot3_31_7, + OPERAND_fld_ae9_slot3_4_0, + OPERAND_fld_ae9_slot3_4_3, + OPERAND_fld_ae9_slot3_4_4, + OPERAND_fld_ae9_slot3_6_0, + OPERAND_fld_ae9_slot3_9_0, + OPERAND_fld_ae9_slot3_9_5, + OPERAND_fld_ae10_slot0_17_13, + OPERAND_fld_ae10_slot0_17_4, + OPERAND_fld_ae10_slot0_17_8, + OPERAND_fld_ae10_slot0_24_0, + OPERAND_fld_ae10_slot0_24_10, + OPERAND_fld_ae10_slot0_24_12, + OPERAND_fld_ae10_slot0_24_13, + OPERAND_fld_ae10_slot0_24_16, + OPERAND_fld_ae10_slot0_24_17, + OPERAND_fld_ae10_slot0_24_18, + OPERAND_fld_ae10_slot0_24_20, + OPERAND_fld_ae10_slot0_24_8, + OPERAND_fld_ae10_slot0_3_0, + OPERAND_fld_ae10_slot0_7_4, + OPERAND_fld_ae10_slot0_7_6, + OPERAND_fld_ae10_slot0_7_7, + OPERAND_fld_ae10_slot0_8_4, + OPERAND_fld_ae10_slot1_0_0, + OPERAND_fld_ae10_slot1_17_13, + OPERAND_fld_ae10_slot1_17_8, + OPERAND_fld_ae10_slot1_25_1, + OPERAND_fld_ae10_slot1_25_12, + OPERAND_fld_ae10_slot1_25_13, + OPERAND_fld_ae10_slot1_25_16, + OPERAND_fld_ae10_slot1_25_17, + OPERAND_fld_ae10_slot1_25_18, + OPERAND_fld_ae10_slot1_25_20, + OPERAND_fld_ae10_slot1_25_22, + OPERAND_fld_ae10_slot1_25_23, + OPERAND_fld_ae10_slot1_25_8, + OPERAND_fld_ae10_slot1_25_9, + OPERAND_fld_ae10_slot1_3_0, + OPERAND_fld_ae10_slot1_3_2, + OPERAND_fld_ae10_slot1_3_3, + OPERAND_fld_ae10_slot1_7_4, + OPERAND_fld_ae10_slot2_24_20, + OPERAND_fld_ae10_slot2_29_20, + OPERAND_fld_ae10_slot2_29_25, + OPERAND_fld_ae10_slot2_34_10, + OPERAND_fld_ae10_slot2_34_14, + OPERAND_fld_ae10_slot2_34_15, + OPERAND_fld_ae10_slot2_34_20, + OPERAND_fld_ae10_slot2_34_25, + OPERAND_fld_ae10_slot2_34_30, + OPERAND_fld_ae10_slot2_34_31, + OPERAND_fld_ae10_slot2_34_33, + OPERAND_fld_ae10_slot2_4_0, + OPERAND_fld_ae10_slot2_9_0, + OPERAND_fld_ae10_slot2_9_5, + OPERAND_fld_ae_sem_hpfma_vq, + OPERAND_fld_ae_sem_spfma_vq, + OPERAND_fld_ae10_slot3_19_15, + OPERAND_fld_ae10_slot3_29_20, + OPERAND_fld_ae10_slot3_29_25, + OPERAND_fld_ae10_slot3_34_10, + OPERAND_fld_ae10_slot3_34_14, + OPERAND_fld_ae10_slot3_34_15, + OPERAND_fld_ae10_slot3_34_20, + OPERAND_fld_ae10_slot3_34_25, + OPERAND_fld_ae10_slot3_34_30, + OPERAND_fld_ae10_slot3_34_31, + OPERAND_fld_ae10_slot3_34_33, + OPERAND_fld_ae10_slot3_4_0, + OPERAND_fld_ae10_slot3_4_3, + OPERAND_fld_ae10_slot3_4_4, + OPERAND_fld_ae10_slot3_9_0, + OPERAND_fld_ae10_slot3_9_5, + OPERAND_fld_ae4_slot0_22_0, + OPERAND_fld_ae4_slot0_22_12, + OPERAND_fld_ae4_slot0_22_13, + OPERAND_fld_ae4_slot0_22_16, + OPERAND_fld_ae4_slot0_22_17, + OPERAND_fld_ae4_slot0_22_18, + OPERAND_fld_ae4_slot0_22_20, + OPERAND_fld_ae4_slot0_22_6, + OPERAND_fld_ae4_slot0_22_8, + OPERAND_fld_ae4_slot0_3_0, + OPERAND_fld_ae4_slot0_3_1, + OPERAND_fld_ae4_slot0_4_4, + OPERAND_fld_ae4_slot0_7_4, + OPERAND_fld_ae4_slot1_22_0, + OPERAND_fld_ae4_slot1_22_12, + OPERAND_fld_ae4_slot1_22_13, + OPERAND_fld_ae4_slot1_22_16, + OPERAND_fld_ae4_slot1_22_17, + OPERAND_fld_ae4_slot1_22_18, + OPERAND_fld_ae4_slot1_22_8, + OPERAND_fld_ae4_slot1_3_0, + OPERAND_fld_ae4_slot1_3_1, + OPERAND_fld_ae4_slot1_7_4, + OPERAND_fld_ae4_slot2_23_0, + OPERAND_fld_ae4_slot2_23_12, + OPERAND_fld_ae4_slot2_23_15, + OPERAND_fld_ae4_slot2_23_17, + OPERAND_fld_ae4_slot2_23_20, + OPERAND_fld_ae4_slot2_4_0, + OPERAND_fld_ae4_slot2_9_5, + OPERAND_fld_ae4_slot3_14_10, + OPERAND_fld_ae4_slot3_19_15, + OPERAND_fld_ae4_slot3_19_19, + OPERAND_fld_ae4_slot3_19_5, + OPERAND_fld_ae4_slot3_27_20, + OPERAND_fld_ae4_slot3_27_25, + OPERAND_fld_ae4_slot3_27_3, + OPERAND_fld_ae4_slot3_2_0, + OPERAND_fld_ae4_slot3_9_0, + OPERAND_fld_ae4_slot3_9_5, + OPERAND_fld_ae4_slot4_22_0, + OPERAND_fld_ae4_slot4_22_15, + OPERAND_fld_ae4_slot4_22_20, + OPERAND_fld_ae4_slot4_9_5, + OPERAND_fld_Inst_11_8, + OPERAND_fld_Inst_12_12, + OPERAND_fld_Inst_12_8, + OPERAND_fld_Inst_13_8, + OPERAND_fld_Inst_15_12, + OPERAND_fld_Inst_19_17, + OPERAND_fld_Inst_19_18, + OPERAND_fld_Inst_23_12, + OPERAND_fld_Inst_23_16, + OPERAND_fld_Inst_4_4, + OPERAND_fld_Inst_5_4, + OPERAND_fld_Inst_7_4, + OPERAND_fld_Inst_7_6, + OPERAND_fld_Inst_7_7, + OPERAND_fld_Inst_9_8, + OPERAND_s3to1 +}; + + +/* Iclass table. */ + +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSRING }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { OPERAND_ars_entry }, 's' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm12x8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { OPERAND_simm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ai4const }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_simm7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8x256 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_label12 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sae }, 'i' }, + { { OPERAND_op2p1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { OPERAND_soffset }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_uimm16x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_simm12b }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ex_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ex_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_getex_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_getex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clrex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_simcall_args[] = { + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimmrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { OPERAND_sas }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_msalp32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sargt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { + { { STATE_LEND }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { + { { STATE_LEND }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { + { { STATE_LEND }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { + { { STATE_LCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MEMCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MEMCTL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MEMCTL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'i' }, + { { STATE_VECBASELOCK }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'm' }, + { { STATE_VECBASELOCK }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'm' }, + { { STATE_VECBASELOCK }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpucfg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpucfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUNUMENTRIES }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpucfg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpucfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUNUMENTRIES }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_salt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_opmode_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_opmode_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_OPMODEECCFENCE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_opmode_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_opmode_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_OPMODEECCFENCE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_opmode_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_opmode_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_OPMODEECCFENCE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_mul16_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_EPC5 }, 'i' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_EPS3 }, 'i' }, + { { STATE_EPS4 }, 'i' }, + { { STATE_EPS5 }, 'i' }, + { { STATE_EPS6 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTERRUPT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { OPERAND_imms }, 'i' }, + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC5 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_VECBASE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_bs }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { + { { OPERAND_bs }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_brall }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_brall }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_brall }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpfb_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpdngrd_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdcw_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdcw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldcw_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldcw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_stateArgs[] = { + { { STATE_PREFCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_stateArgs[] = { + { { STATE_PREFCTL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_stateArgs[] = { + { { STATE_PREFCTL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cacheadrdis_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cacheadrdis_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CACHEADRDIS }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cacheadrdis_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cacheadrdis_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CACHEADRDIS }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cacheadrdis_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cacheadrdis_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CACHEADRDIS }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb0_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wptlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wptlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpuenb_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpuenb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpuenb_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpuenb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_mpuenb_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_mpuenb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ERACCESS }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ERACCESS }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ERACCESS }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { + { { STATE_ERACCESS }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_ERI_RAW_INTERLOCK }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = { + INTERFACE_ERI_RD_In, + INTERFACE_ERI_RD_Out +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { + { { STATE_ERACCESS }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_ERI_RAW_INTERLOCK }, 'o' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = { + INTERFACE_ERI_WR_In, + INTERFACE_ERI_WR_Out +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_1_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_2_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_3_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'i' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'o' }, + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = { + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = { + { { STATE_AE_BITHEAD }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_TABLESIZE }, 'i' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = { + { { STATE_AE_BITPTR }, 'o' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cw_sd_no_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cw_sd_no_stateArgs[] = { + { { STATE_AE_CWRAP }, 'i' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cw_sd_no_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cw_sd_no_stateArgs[] = { + { { STATE_AE_CWRAP }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin0_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin0_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend0_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend0_stateArgs[] = { + { { STATE_AE_CEND0 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin1_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend1_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin2_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend2_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_sext16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_zext16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_zext8_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_clamps16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_fcr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fcr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = { + { { STATE_RoundMode }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_fsr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = { + { { STATE_InvalidFlag }, 'i' }, + { { STATE_DivZeroFlag }, 'i' }, + { { STATE_OverflowFlag }, 'i' }, + { { STATE_UnderflowFlag }, 'i' }, + { { STATE_InexactFlag }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fsr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = { + { { STATE_InvalidFlag }, 'o' }, + { { STATE_DivZeroFlag }, 'o' }, + { { STATE_OverflowFlag }, 'o' }, + { { STATE_UnderflowFlag }, 'o' }, + { { STATE_InexactFlag }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { + INTERFACE_IMPWIRE +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_OVERFLOW_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_OVERFLOW_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_OVERFLOW_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_OVERFLOW_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SAR_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SAR_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SAR_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SAR_stateArgs[] = { + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITPTR_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITPTR_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITPTR_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITPTR_stateArgs[] = { + { { STATE_AE_BITPTR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITSUSED_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITSUSED_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITSUSED_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITSUSED_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_TABLESIZE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_TABLESIZE_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_TABLESIZE_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_TABLESIZE_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_FIRST_TS_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_FIRST_TS_stateArgs[] = { + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_FIRST_TS_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_FIRST_TS_stateArgs[] = { + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_NEXTOFFSET_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_NEXTOFFSET_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_NEXTOFFSET_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_NEXTOFFSET_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SEARCHDONE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SEARCHDONE_stateArgs[] = { + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SEARCHDONE_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SEARCHDONE_stateArgs[] = { + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_CWRAP_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_CWRAP_stateArgs[] = { + { { STATE_AE_CWRAP }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_CWRAP_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_CWRAP_stateArgs[] = { + { { STATE_AE_CWRAP }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64neg }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RI_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64half }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_I_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_IP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_X_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_XP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_I_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_IP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_X_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_XP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_I_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_IP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_X_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_XP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_I_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_IP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_X_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_XP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ZALIGN64_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_ZALIGN64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LALIGN64_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LALIGN64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SALIGN64_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SALIGN64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVALIGN_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_vu }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVALIGN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA64_PP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA64_PP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8NEG_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8NEG_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64POS_FP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64POS_FP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64NEG_FP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64NEG_FP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDICIRC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_end }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_I_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_X_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_I_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_X_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RA64S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24X2RA64S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S24X2RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RA32S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RA32S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDBRBA32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_aoe }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ab }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ai }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_L_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BITSWAP_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_aoe }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ab }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32JS_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32JS_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32JS_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32JS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_H_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_H_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_L_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDRNG32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBRNG32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RNG32X2_args[] = { + { { OPERAND_opnd_ae_sem_rng_d }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RNG32X2_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_immed }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_N_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_immed_N }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_N_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHORTSWAP_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHORTSWAP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAB4_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAB2_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAB_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA1X2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVB2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVB4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT16X4_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF16X4_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT32X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF32X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARA7X2_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARA7X2_stateArgs[] = { + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARD7_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARD7_stateArgs[] = { + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVASAR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_MOVASAR_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVI_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_movi_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24A32X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24A32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT16X4_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT16X4_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_10_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_10_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_10_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_10_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LL_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LH_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HL_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HH_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24Q48X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24Q48X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32X2F64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32X2F64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32X2F64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32X2F64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32F64S_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32F64S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32F64S_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32F64S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP16_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SSYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SSYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SSYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SSYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2SYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2SYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2ASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2ASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24SYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24SYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24ASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24ASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOV_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT64_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF64_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56A32S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56A32S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48A32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48A32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64A32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64A32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64F32_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64F32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT48S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT48S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATQ56S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT24S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCQ32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCQ32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48SYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48SYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48ASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48ASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32Q48_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32Q48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_3_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_1_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_0_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRA64_32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRA64_32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR32_args[] = { + { { OPERAND_opnd_ae_sem_pks_d }, 'm' }, + { { OPERAND_opnd_ae_sem_pks_s }, 'i' }, + { { OPERAND_opnd_ae_sem_pks_pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR24_args[] = { + { { OPERAND_opnd_ae_sem_pks_d }, 'm' }, + { { OPERAND_opnd_ae_sem_pks_s }, 'i' }, + { { OPERAND_opnd_ae_sem_pks_pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR24_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSRF32_args[] = { + { { OPERAND_opnd_ae_sem_pks_d }, 'm' }, + { { OPERAND_opnd_ae_sem_pks_s }, 'i' }, + { { OPERAND_opnd_ae_sem_pks_pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSRF32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR16_args[] = { + { { OPERAND_opnd_ae_sem_pks_d }, 'm' }, + { { OPERAND_opnd_ae_sem_pks_s }, 'i' }, + { { OPERAND_opnd_ae_sem_pks_pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR16_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD24S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB24S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG24S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS24S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG16S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS16S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16JS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16JS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16JS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16JS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16JS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16JS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16JS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16JS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT16_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE16_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ16_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINMAX32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINMAX32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINMAX16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINMAX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSQ56S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBSQ56S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEGSQ56S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEGSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABSSQ56S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABSSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_AND_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_AND_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NAND_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NAND_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_OR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_OR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_XOR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_XOR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16R_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32R_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI16S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA16S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16RS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32RS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASQ56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLSQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLSQ56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRASQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRASQ56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAAQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAAQ56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLAQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLAQ56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAAQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAAQ56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS64_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS64_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAISQ56S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAISQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASSQ56S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAASQ56S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAASQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT64_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE64_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ64_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA64_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ16_0_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ16_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ32_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32U_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32U_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32U_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32U_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32U_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32U_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_33_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_33_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_21_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_21_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_31_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_31_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_30_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_30_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_10_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_10_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_20_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_20_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_11_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_11_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_33_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_33_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_21_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_21_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_31_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_31_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_30_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_30_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_10_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_10_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_20_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_20_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_11_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_11_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_33_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_33_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_21_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_21_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_31_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_31_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_30_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_30_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_10_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_10_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_20_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_20_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_11_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_11_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16S_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16S_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16S_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16S_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16S_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16S_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2R_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2R_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2R_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2TS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2TS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2TS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2TS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2TS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2TS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC24RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC24RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC24RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC24RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16X4SS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16X4SS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16X4SS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16X4SS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16X4SS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16X4SS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC16RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC16RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC16RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC16RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16JS_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16JS_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG16RAS_S1_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_vs }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG16RAS_S1_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG16RAS_S2_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_vs }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG16RAS_S2_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CONJ16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CONJ16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAFQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAFQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAFQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAFQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16_00_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16_00_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_H_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHA32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_aoe }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ai }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL32T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL32T_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16T_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IP_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IP_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC1_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDSHT_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDSHT_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_opnd_ae_sem_lb_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ae_sem_lb_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBS_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBS_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBSI_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_opnd_ae_sem_lb_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBSI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ARDECNORM16_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_opnd_AE_ARDECNORM16_ar_u }, 'm' }, + { { OPERAND_arr }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL32T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL32T_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL16T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL16T_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC1_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC1_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IP_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IP_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IP_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAE_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ei }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAE_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEA_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_eo }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ar_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEEP_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_eo }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ei }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEEP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT72_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ep1 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ep1 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72X64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72X64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72X64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72X64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32EP_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32EP_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32EP_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32EP_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32EP_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32EP_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32USEP_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32USEP_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32USEP_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32USEP_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI72_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_e }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI72_args[] = { + { { OPERAND_opnd_ae_sem_shift_e }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_e }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16SI_N_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_uimm2x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16UI_N_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_uimm2x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16I_N_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_uimm2x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LALIGN128_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LALIGN128_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SALIGN128_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SALIGN128_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA128_PP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA128_PP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA128POS_FP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA128POS_FP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X4S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X4S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X4U_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X4U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS8S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG8S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD8S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB8S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_art }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_art }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_art }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU16X4_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU16X4_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT32X2_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT32X2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU32X2_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU32X2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT8X8X16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT8X8X16_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU8X8X16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU8X8X16_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT8X4X32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT8X4X32_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU8X4X32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU8X4X32_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X8F16SSYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X8F16SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X8F16SASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X8F16SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X4F32SSYM_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X4F32SSYM_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X4F32SASYM_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X4F32SASYM_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA8_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD8_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDX2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDX2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32J_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32J_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW8U_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW8U_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW8U_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_HL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_HL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_HL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_HL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_HL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_HL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2R_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2R_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2R_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2R_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2R_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2R_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2R_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2R_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2R_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2R_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2R_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2R_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2P32X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2P32X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS2P32X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS2P32X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2P32X4T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2P32X4T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS2P32X4T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS2P32X4T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA32X2_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA32X2_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS32X2_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS32X2_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA32X2_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA32X2_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32X2_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32X2_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULCJ32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULCJ32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULACJ32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULACJ32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULADDF32RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULADDF32RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULADDF32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULADDF32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSUBF32RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSUBF32RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSUBF32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSUBF32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULCJ32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULCJ32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULACJ32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULACJ32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2D32X2WS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2D32X2WS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2C16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2C16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2C16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2C16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ16RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ16RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ16RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ16RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD16X16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD16X16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA2D16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA2D16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA2D16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA2D16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS2D16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS2D16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS2D16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS2D16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA2D16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA2D16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA2D16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA2D16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS2D16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS2D16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS2D16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS2D16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD16X16X4WS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD16X16X4WS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q16X8_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q16X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q16X8_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q16X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q8_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q8_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULPC32X16X2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULPC32X16X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAPC32X16X2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAPC32X16X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFPC32X16X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFPC32X16X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFPC32X16X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFPC32X16X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFPCJ32X16X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFPCJ32X16X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFPCJ32X16X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFPCJ32X16X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2Q32X16_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2Q32X16_FIR_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2Q32X16_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2Q32X16_FIR_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2Q32X16_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2Q32X16_FIR_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2Q32X16_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2Q32X16_FIR_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI8_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI8R_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI8R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI8_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI8_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI8S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA8_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA8_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA8S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA8RS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA8RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA8S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI16_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI16_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA16_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA16_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16SYM_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16SYM_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16SYMS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16SYMS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32SYM_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32SYM_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32SYMS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32SYMS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAV16RS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAV16RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAV32RS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAV32RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8S_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8S_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8S_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8S_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8U_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8U_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8U_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8US_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8US_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8US_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8US_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8U_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8U_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8U_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8US_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8US_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8US_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8US_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16S_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16S_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16U_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16US_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16US_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16U_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16US_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16US_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8S_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8S_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8U_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8US_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8US_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8U_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8US_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8US_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL8X8_args[] = { + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHFL8X8_args[] = { + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHFL8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16X4_args[] = { + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHFL16X4_args[] = { + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHFL16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DSEL8X8_args[] = { + { { OPERAND_opnd_ae_sem_select_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DSEL8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DSEL16X4_args[] = { + { { OPERAND_opnd_ae_sem_select_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DSEL16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL8X8I_args[] = { + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_isel }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL8X8I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMAX8X8_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMAX8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMIN8X8_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMIN8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMAX16X4_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMAX16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMIN16X4_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMIN16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SORT16X4_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SORT16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD8X8_H_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD8X8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA8X8_H_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'm' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA8X8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD8X8_L_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD8X8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA8X8_L_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'm' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA8X8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD16X4_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA16X4_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'm' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX8X8_H_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX8X8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX8X8_L_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX8X8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN8X8_H_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN8X8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN8X8_L_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN8X8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX16X4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN16X4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX32X2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN32X2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDINV16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDINV16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDINV32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDINV32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT16X8_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT16X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT8X16_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT8X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT8X16_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT8X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBD1X4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBD1X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBD1X2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBD1X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVNEG32S_T_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVNEG32S_T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDEXT_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDEXT_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVADEXT_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_a }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVADEXT_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVADEXT_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_a }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVADEXT_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA16X4_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_d }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ32X4_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_d }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ32X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA32X4_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_d }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA32X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI16X4F32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI16X4F32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI16X4F64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI16X4F64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16X4F32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16X4F32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16X4F64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16X4F64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDC32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDC32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBC32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBC32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDC32U_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDC32U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBC32U_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBC32U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPADD16_H_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPADD16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPSUB16_H_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPSUB16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPADD16_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPADD16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPSUB16_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPSUB16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCEXP32_H_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCEXP32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCEXP32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCEXP32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG16_args[] = { + { { OPERAND_opnd_ae_sem_rng_a }, 'o' }, + { { OPERAND_opnd_ae_sem_rng_art }, 'o' }, + { { OPERAND_opnd_ae_sem_rng_i2 }, 'i' }, + { { OPERAND_opnd_ae_sem_rng_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG16_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG32_args[] = { + { { OPERAND_opnd_ae_sem_rng_a }, 'o' }, + { { OPERAND_opnd_ae_sem_rng_art }, 'o' }, + { { OPERAND_opnd_ae_sem_rng_i2 }, 'i' }, + { { OPERAND_opnd_ae_sem_rng_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RNG32X4_args[] = { + { { OPERAND_opnd_ae_sem_rng_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_rng_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RNG32X4_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAV8X8X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAV8X8X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAV16X4X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAV16X4X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAV8X8X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAV8X8X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAV16X4X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAV16X4X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVZBVCDR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVZBVCDR_stateArgs[] = { + { { STATE_AE_ZBIASV8 }, 'o' }, + { { STATE_AE_ZBIASC8 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDRZBVC_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDRZBVC_stateArgs[] = { + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAVUNSQZ8X8_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAVUNSQZ8X8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAVUNSQZ16X4_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAVUNSQZ16X4_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_HL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_HL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_HL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_HL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_L_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_L_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_H_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_L_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_L_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_H_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVFCRFSRV_args[] = { + { { OPERAND_opnd_ae_sem_movfpstate_v }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVFCRFSRV_stateArgs[] = { + { { STATE_RoundMode }, 'o' }, + { { STATE_InvalidFlag }, 'o' }, + { { STATE_DivZeroFlag }, 'o' }, + { { STATE_OverflowFlag }, 'o' }, + { { STATE_UnderflowFlag }, 'o' }, + { { STATE_InexactFlag }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVVFCRFSR_args[] = { + { { OPERAND_opnd_ae_sem_movfpstate_v }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_MOVVFCRFSR_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_InvalidFlag }, 'i' }, + { { STATE_DivZeroFlag }, 'i' }, + { { STATE_OverflowFlag }, 'i' }, + { { STATE_UnderflowFlag }, 'i' }, + { { STATE_InexactFlag }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVT_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVT_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVF_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVF_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVEQZ_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVEQZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVNEZ_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVNEZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVGEZ_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVGEZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVLTZ_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVLTZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RFR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RFR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WFR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_WFR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBN_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBN_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_S_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_S_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'm' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_S_stateArgs[] = { + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vsM }, 'm' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vsM }, 'm' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MIN_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MIN_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAX_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAX_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUX_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUX_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUX_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUX_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_art }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_art }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_SX2_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_SX2_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_SX2_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_SX2_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FICEIL_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FICEIL_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIFLOOR_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIFLOOR_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIRINT_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIRINT_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIROUND_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIROUND_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FITRUNC_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FITRUNC_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_SX2_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_SX2_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_SX2_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_SX2_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_S_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_S_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_S_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_S_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_S_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CLSFY_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CLSFY_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUM_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUM_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUM_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUM_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDANDSUB_S_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDANDSUB_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDANDSUBJC_S_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDANDSUBJC_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_HL_LH_S_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_HL_LH_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDA_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDA_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FREXP_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vsM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FREXP_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOATEXP_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOATEXP_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUMABS_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUMABS_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUMABS_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUMABS_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUXQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUXQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUXQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUXQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMAXNUM_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMAXNUM_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMINNUM_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMINNUM_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMAXNUMABS_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMAXNUMABS_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMINNUMABS_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMINNUMABS_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_SX2X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_SX2X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_SX2X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_SX2X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_SX2X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUX_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUX_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUX_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUX_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'm' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'm' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CLSFY_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CLSFY_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_H_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_H_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MIN_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MIN_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAX_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAX_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUM_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUM_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUM_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUM_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_H_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FICEIL_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FICEIL_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIFLOOR_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIFLOOR_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIRINT_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIRINT_H_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIROUND_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIROUND_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FITRUNC_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FITRUNC_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vs }, 'm' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP0_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP0_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT16_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT16_H_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT16_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT16_H_stateArgs[] = { + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC16_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_art }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC16_H_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC16_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_art }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC16_H_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT16_HX4_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT16_HX4_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT16_HX4_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT16_HX4_stateArgs[] = { + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC16_HX4_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC16_HX4_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC16_HX4_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC16_HX4_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBN_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBN_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_H_stateArgs[] = { + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RMINNUM_H_args[] = { + { { OPERAND_opnd_ae_sem_hprminmaxnum_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hprminmaxnum_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RMINNUM_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RMAXNUM_H_args[] = { + { { OPERAND_opnd_ae_sem_hprminmaxnum_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hprminmaxnum_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RMAXNUM_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_HX4X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_HX4X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_HX4X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_HX4X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_HX4X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULQ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULQ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDQ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDQ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULCNVH_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULCNVH_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULACNVH_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULACNVH_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULCNVL_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULCNVL_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULACNVL_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULACNVL_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_iclass_internal iclasses[] = { + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_threadptr_args, + 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, + { 1, Iclass_wur_threadptr_args, + 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_loop_args, + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_loopz_args, + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32ex_args, + 1, Iclass_xt_iclass_l32ex_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_s32ex_args, + 1, Iclass_xt_iclass_s32ex_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_getex_args, + 1, Iclass_xt_iclass_getex_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_clrex */, + 1, Iclass_xt_iclass_clrex_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_simcall_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32nb_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lend_args, + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lend_args, + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lend_args, + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lcount_args, + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lcount_args, + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lcount_args, + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lbeg_args, + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lbeg_args, + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lbeg_args, + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_memctl_args, + 3, Iclass_xt_iclass_rsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_memctl_args, + 3, Iclass_xt_iclass_wsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_memctl_args, + 3, Iclass_xt_iclass_xsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid0_args, + 2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_configid0_args, + 2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid1_args, + 2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc3_args, + 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc3_args, + 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc3_args, + 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave3_args, + 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave3_args, + 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave3_args, + 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc4_args, + 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc4_args, + 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc4_args, + 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave4_args, + 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave4_args, + 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave4_args, + 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc5_args, + 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc5_args, + 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc5_args, + 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave5_args, + 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave5_args, + 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave5_args, + 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc6_args, + 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc6_args, + 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc6_args, + 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave6_args, + 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave6_args, + 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave6_args, + 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps3_args, + 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps3_args, + 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps3_args, + 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps4_args, + 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps4_args, + 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps4_args, + 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps5_args, + 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps5_args, + 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps5_args, + 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps6_args, + 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps6_args, + 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps6_args, + 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc0_args, + 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc0_args, + 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc0_args, + 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc1_args, + 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc1_args, + 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc1_args, + 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc2_args, + 3, Iclass_xt_iclass_rsr_misc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc2_args, + 3, Iclass_xt_iclass_wsr_misc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc2_args, + 3, Iclass_xt_iclass_xsr_misc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc3_args, + 3, Iclass_xt_iclass_rsr_misc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc3_args, + 3, Iclass_xt_iclass_wsr_misc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc3_args, + 3, Iclass_xt_iclass_xsr_misc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_vecbase_args, + 4, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_vecbase_args, + 4, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_vecbase_args, + 4, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_mpucfg_args, + 3, Iclass_xt_iclass_rsr_mpucfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mpucfg_args, + 3, Iclass_xt_iclass_wsr_mpucfg_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_salt_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_opmode_args, + 3, Iclass_xt_iclass_rsr_opmode_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_opmode_args, + 3, Iclass_xt_iclass_wsr_opmode_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_opmode_args, + 3, Iclass_xt_iclass_xsr_opmode_stateArgs, 0, 0 }, + { 3, Iclass_xt_mul16_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 19, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka0_args, + 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka0_args, + 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka0_args, + 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc0_args, + 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc0_args, + 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc0_args, + 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka1_args, + 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka1_args, + 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka1_args, + 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc1_args, + 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc1_args, + 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc1_args, + 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka0_args, + 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka0_args, + 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka0_args, + 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka1_args, + 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka1_args, + 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka1_args, + 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreakenable_args, + 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreakenable_args, + 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreakenable_args, + 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_lddr32_p_args, + 5, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sddr32_p_args, + 4, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfdo_args, + 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 2, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mmid_args, + 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_bbool1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbranch_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bmove_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_RSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_WSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_XSR_BR_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare1_args, + 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare1_args, + 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare1_args, + 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare2_args, + 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare2_args, + 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare2_args, + 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_lock_args, + 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_inv_args, + 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_licx_args, + 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sicx_args, + 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_dcache_dyn_args, + 2, Iclass_xt_iclass_dcache_dyn_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_ind_args, + 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_inv_args, + 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dpf_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dpfb_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_bpfnxt */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dpdngrd_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_bpfctl */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_lock_args, + 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sdct_args, + 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ldct_args, + 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sdcw_args, + 2, Iclass_xt_iclass_sdcw_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ldcw_args, + 2, Iclass_xt_iclass_ldcw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prefctl_args, + 1, Iclass_xt_iclass_rsr_prefctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_prefctl_args, + 1, Iclass_xt_iclass_wsr_prefctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_prefctl_args, + 1, Iclass_xt_iclass_xsr_prefctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cacheadrdis_args, + 4, Iclass_xt_iclass_wsr_cacheadrdis_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cacheadrdis_args, + 3, Iclass_xt_iclass_rsr_cacheadrdis_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cacheadrdis_args, + 4, Iclass_xt_iclass_xsr_cacheadrdis_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rptlb0_args, + 3, Iclass_xt_iclass_rptlb0_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rptlb_args, + 2, Iclass_xt_iclass_rptlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_wptlb_args, + 4, Iclass_xt_iclass_wptlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_mpuenb_args, + 3, Iclass_xt_iclass_rsr_mpuenb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mpuenb_args, + 4, Iclass_xt_iclass_wsr_mpuenb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_mpuenb_args, + 4, Iclass_xt_iclass_xsr_mpuenb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cpenable_args, + 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cpenable_args, + 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cpenable_args, + 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_clamp_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_minmax_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_sx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32ai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32ri_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_atomctl_args, + 4, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_atomctl_args, + 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_atomctl_args, + 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_div_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eraccess_args, + 3, Iclass_xt_iclass_rsr_eraccess_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eraccess_args, + 3, Iclass_xt_iclass_wsr_eraccess_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eraccess_args, + 3, Iclass_xt_iclass_xsr_eraccess_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rer_args, + 4, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs }, + { 2, Iclass_xt_iclass_wer_args, + 4, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs }, + { 2, Iclass_xt_iclass_wb15_0_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_1_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_2_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_3_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_ae_ovf_sar_args, + 3, Iclass_rur_ae_ovf_sar_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_ovf_sar_args, + 3, Iclass_wur_ae_ovf_sar_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_bithead_args, + 2, Iclass_rur_ae_bithead_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_bithead_args, + 2, Iclass_wur_ae_bithead_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_ts_fts_bu_bp_args, + 5, Iclass_rur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_ts_fts_bu_bp_args, + 5, Iclass_wur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cw_sd_no_args, + 4, Iclass_rur_ae_cw_sd_no_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cw_sd_no_args, + 4, Iclass_wur_ae_cw_sd_no_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cbegin0_args, + 2, Iclass_rur_ae_cbegin0_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cbegin0_args, + 2, Iclass_wur_ae_cbegin0_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cend0_args, + 2, Iclass_rur_ae_cend0_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cend0_args, + 2, Iclass_wur_ae_cend0_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cbegin1_args, + 2, Iclass_rur_ae_cbegin1_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cbegin1_args, + 2, Iclass_wur_ae_cbegin1_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cend1_args, + 2, Iclass_rur_ae_cend1_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cend1_args, + 2, Iclass_wur_ae_cend1_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cbegin2_args, + 2, Iclass_rur_ae_cbegin2_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cbegin2_args, + 2, Iclass_wur_ae_cbegin2_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cend2_args, + 2, Iclass_rur_ae_cend2_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cend2_args, + 2, Iclass_wur_ae_cend2_stateArgs, 0, 0 }, + { 2, Iclass_ic_sext16_args, + 0, 0, 0, 0 }, + { 2, Iclass_ic_zext16_args, + 0, 0, 0, 0 }, + { 2, Iclass_ic_zext8_args, + 0, 0, 0, 0 }, + { 2, Iclass_ic_clamps16_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_fcr_args, + 2, Iclass_rur_fcr_stateArgs, 0, 0 }, + { 1, Iclass_wur_fcr_args, + 2, Iclass_wur_fcr_stateArgs, 0, 0 }, + { 1, Iclass_rur_fsr_args, + 6, Iclass_rur_fsr_stateArgs, 0, 0 }, + { 1, Iclass_wur_fsr_args, + 6, Iclass_wur_fsr_stateArgs, 0, 0 }, + { 1, Iclass_rur_expstate_args, + 1, Iclass_rur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_wur_expstate_args, + 1, Iclass_wur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_iclass_READ_IMPWIRE_args, + 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, + { 1, Iclass_iclass_SETB_EXPSTATE_args, + 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, + { 1, Iclass_iclass_CLRB_EXPSTATE_args, + 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, + { 2, Iclass_iclass_WRMSK_EXPSTATE_args, + 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_OVERFLOW_args, + 2, Iclass_RUR_AE_OVERFLOW_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_OVERFLOW_args, + 2, Iclass_WUR_AE_OVERFLOW_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_SAR_args, + 2, Iclass_RUR_AE_SAR_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_SAR_args, + 2, Iclass_WUR_AE_SAR_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_BITPTR_args, + 2, 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Iclass_AE_S16X4X2RNG_I_args, + 2, Iclass_AE_S16X4X2RNG_I_stateArgs, 0, 0 }, + { 4, Iclass_AE_S16X4X2RNG_IP_args, + 2, Iclass_AE_S16X4X2RNG_IP_stateArgs, 0, 0 }, + { 4, Iclass_AE_S16X4X2RNG_X_args, + 2, Iclass_AE_S16X4X2RNG_X_stateArgs, 0, 0 }, + { 4, Iclass_AE_S16X4X2RNG_XP_args, + 2, Iclass_AE_S16X4X2RNG_XP_stateArgs, 0, 0 }, + { 1, Iclass_AE_ZALIGN64_args, + 1, Iclass_AE_ZALIGN64_stateArgs, 0, 0 }, + { 3, Iclass_AE_LALIGN64_I_args, + 1, Iclass_AE_LALIGN64_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_SALIGN64_I_args, + 1, Iclass_AE_SALIGN64_I_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVALIGN_args, + 1, Iclass_AE_MOVALIGN_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA64_PP_args, + 1, Iclass_AE_LA64_PP_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24POS_PC_args, + 3, Iclass_AE_LA24POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24NEG_PC_args, + 3, Iclass_AE_LA24NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24POS_PC1_args, + 3, Iclass_AE_LA24POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24NEG_PC1_args, + 3, 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Iclass_AE_LA16X4X2POS_PC1_args, + 3, Iclass_AE_LA16X4X2POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4X2POS_PC2_args, + 3, Iclass_AE_LA16X4X2POS_PC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8X2POS_PC_args, + 3, Iclass_AE_LA8X8X2POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8X2POS_PC1_args, + 3, Iclass_AE_LA8X8X2POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8X2POS_PC2_args, + 3, Iclass_AE_LA8X8X2POS_PC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_SA64POS_FP_args, + 1, Iclass_AE_SA64POS_FP_stateArgs, 0, 0 }, + { 2, Iclass_AE_SA64NEG_FP_args, + 1, Iclass_AE_SA64NEG_FP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IC_args, + 3, Iclass_AE_LA32X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IC1_args, + 3, Iclass_AE_LA32X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IC2_args, + 3, Iclass_AE_LA32X2_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IP_args, + 1, Iclass_AE_LA32X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_RIP_args, + 1, Iclass_AE_LA32X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_RIC_args, + 3, Iclass_AE_LA32X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_RIC1_args, + 3, Iclass_AE_LA32X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IC_args, + 3, Iclass_AE_LA16X4_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IC1_args, + 3, Iclass_AE_LA16X4_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IC2_args, + 3, Iclass_AE_LA16X4_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IP_args, + 1, Iclass_AE_LA16X4_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_RIP_args, + 1, Iclass_AE_LA16X4_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_RIC_args, + 3, Iclass_AE_LA16X4_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_RIC1_args, + 3, Iclass_AE_LA16X4_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_IC_args, + 3, Iclass_AE_LA8X8_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_IC1_args, + 3, Iclass_AE_LA8X8_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_IC2_args, + 3, Iclass_AE_LA8X8_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_IP_args, + 1, Iclass_AE_LA8X8_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_RIP_args, + 1, Iclass_AE_LA8X8_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_RIC_args, + 3, Iclass_AE_LA8X8_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_RIC1_args, + 3, Iclass_AE_LA8X8_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_IC_args, + 3, Iclass_AE_LA32X2F24_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_IC1_args, + 3, Iclass_AE_LA32X2F24_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_IP_args, + 1, Iclass_AE_LA32X2F24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_RIP_args, + 1, Iclass_AE_LA32X2F24_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_RIC_args, + 3, Iclass_AE_LA32X2F24_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_RIC1_args, + 3, Iclass_AE_LA32X2F24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_IC_args, + 3, Iclass_AE_LA24_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_IC1_args, + 3, Iclass_AE_LA24_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_IP_args, + 1, Iclass_AE_LA24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_RIP_args, + 1, Iclass_AE_LA24_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_RIC_args, + 3, Iclass_AE_LA24_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_RIC1_args, + 3, Iclass_AE_LA24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_IC_args, + 3, Iclass_AE_LA24X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_IC1_args, + 3, Iclass_AE_LA24X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_IP_args, + 1, Iclass_AE_LA24X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_RIP_args, + 1, Iclass_AE_LA24X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_RIC_args, + 3, Iclass_AE_LA24X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_RIC1_args, + 3, Iclass_AE_LA24X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IC_args, + 3, Iclass_AE_SA32X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IC1_args, + 3, Iclass_AE_SA32X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IC2_args, + 3, Iclass_AE_SA32X2_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IP_args, + 1, Iclass_AE_SA32X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_RIP_args, + 1, Iclass_AE_SA32X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_RIC_args, + 3, Iclass_AE_SA32X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_RIC1_args, + 3, Iclass_AE_SA32X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IC_args, + 3, Iclass_AE_SA16X4_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IC1_args, + 3, Iclass_AE_SA16X4_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IC2_args, + 3, Iclass_AE_SA16X4_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IP_args, + 1, Iclass_AE_SA16X4_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_RIP_args, + 1, Iclass_AE_SA16X4_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_RIC_args, + 3, Iclass_AE_SA16X4_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_RIC1_args, + 3, Iclass_AE_SA16X4_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_IC_args, + 3, Iclass_AE_SA8X8_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_IC1_args, + 3, Iclass_AE_SA8X8_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_IC2_args, + 3, Iclass_AE_SA8X8_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_IP_args, + 1, Iclass_AE_SA8X8_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_RIP_args, + 1, Iclass_AE_SA8X8_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_RIC_args, + 3, Iclass_AE_SA8X8_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_RIC1_args, + 3, Iclass_AE_SA8X8_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_IC_args, + 3, Iclass_AE_SA32X2F24_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_IC1_args, + 3, Iclass_AE_SA32X2F24_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_IP_args, + 1, Iclass_AE_SA32X2F24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_RIP_args, + 1, Iclass_AE_SA32X2F24_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_RIC_args, + 3, Iclass_AE_SA32X2F24_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_RIC1_args, + 3, Iclass_AE_SA32X2F24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_IC_args, + 3, Iclass_AE_SA24_L_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_IC1_args, + 3, Iclass_AE_SA24_L_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_IP_args, + 1, Iclass_AE_SA24_L_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_RIP_args, + 1, Iclass_AE_SA24_L_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_RIC_args, + 3, Iclass_AE_SA24_L_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_RIC1_args, + 3, Iclass_AE_SA24_L_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_IC_args, + 3, Iclass_AE_SA24X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_IC1_args, + 3, Iclass_AE_SA24X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_IP_args, + 1, Iclass_AE_SA24X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_RIP_args, + 1, Iclass_AE_SA24X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_RIC_args, + 3, Iclass_AE_SA24X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_RIC1_args, + 3, Iclass_AE_SA24X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDICIRC_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_ADDCIRC_XC2_args, + 3, Iclass_AE_ADDCIRC_XC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_ADDCIRC_XC1_args, + 3, Iclass_AE_ADDCIRC_XC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_ADDCIRC_XC_args, + 3, Iclass_AE_ADDCIRC_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_I_args, + 2, Iclass_AE_S32RA64S_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_IP_args, + 2, Iclass_AE_S32RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_X_args, + 2, Iclass_AE_S32RA64S_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_XP_args, + 2, Iclass_AE_S32RA64S_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_XC_args, + 4, Iclass_AE_S32RA64S_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_XC1_args, + 4, Iclass_AE_S32RA64S_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_I_args, + 2, Iclass_AE_S24RA64S_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_IP_args, + 2, Iclass_AE_S24RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_X_args, + 2, Iclass_AE_S24RA64S_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_XP_args, + 2, Iclass_AE_S24RA64S_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_XC_args, + 4, Iclass_AE_S24RA64S_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_XC1_args, + 4, Iclass_AE_S24RA64S_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2RA64S_IP_args, + 2, Iclass_AE_S32X2RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24X2RA64S_IP_args, + 2, Iclass_AE_S24X2RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4RA32S_IP_args, + 2, Iclass_AE_S16X4RA32S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDBRBA32_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_S32X2_L_IP_args, + 1, Iclass_AE_S32X2_L_IP_stateArgs, 0, 0 }, + { 2, Iclass_AE_BITSWAP_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MUL32JS_args, + 1, Iclass_AE_MUL32JS_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUB32S_args, + 2, Iclass_AE_ADDANDSUB32S_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUB32JS_args, + 2, Iclass_AE_ADDANDSUB32JS_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUBRNG32_args, + 2, Iclass_AE_ADDANDSUBRNG32_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUBRNG32_H_args, + 2, Iclass_AE_ADDANDSUBRNG32_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUBRNG32_L_args, + 2, Iclass_AE_ADDANDSUBRNG32_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDRNG32_args, + 2, Iclass_AE_ADDRNG32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUBRNG32_args, + 2, Iclass_AE_SUBRNG32_stateArgs, 0, 0 }, + { 1, Iclass_AE_RNG32X2_args, + 2, Iclass_AE_RNG32X2_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL16I_args, + 1, Iclass_AE_SEL16I_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL16I_N_args, + 1, Iclass_AE_SEL16I_N_stateArgs, 0, 0 }, + { 2, Iclass_AE_SHORTSWAP_args, + 1, Iclass_AE_SHORTSWAP_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAB4_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVAB2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVAB_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVBA_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_MOVBA1X2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVBA4_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVBA2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVB2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVB4_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_MOVT16X4_args, + 1, Iclass_AE_MOVT16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVF16X4_args, + 1, Iclass_AE_MOVF16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVT32X2_args, + 1, Iclass_AE_MOVT32X2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVF32X2_args, + 1, Iclass_AE_MOVF32X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVSARA7X2_args, + 2, Iclass_AE_MOVSARA7X2_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVSARD7_args, + 2, Iclass_AE_MOVSARD7_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVASAR_args, + 2, Iclass_AE_MOVASAR_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVDA32X2_args, + 1, Iclass_AE_MOVDA32X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVDA32_args, + 1, Iclass_AE_MOVDA32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVDA16X2_args, + 1, Iclass_AE_MOVDA16X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVDA16_args, + 1, Iclass_AE_MOVDA16_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVI_args, + 1, Iclass_AE_MOVI_stateArgs, 0, 0 }, + { 3, Iclass_AE_TRUNCP24A32X2_args, + 1, Iclass_AE_TRUNCP24A32X2_stateArgs, 0, 0 }, + { 3, Iclass_AE_SAT16X4_args, + 2, Iclass_AE_SAT16X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT32X2F16_32_args, + 1, Iclass_AE_CVT32X2F16_32_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT32X2F16_10_args, + 1, Iclass_AE_CVT32X2F16_10_stateArgs, 0, 0 }, + { 2, Iclass_AE_SEXT32X2D16_32_args, + 1, Iclass_AE_SEXT32X2D16_32_stateArgs, 0, 0 }, + { 2, Iclass_AE_SEXT32X2D16_10_args, + 1, Iclass_AE_SEXT32X2D16_10_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTA32F24S_L_args, + 1, Iclass_AE_CVTA32F24S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTA32F24S_H_args, + 1, Iclass_AE_CVTA32F24S_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_LL_args, + 1, Iclass_AE_CVTP24A16X2_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_LH_args, + 1, Iclass_AE_CVTP24A16X2_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_HL_args, + 1, Iclass_AE_CVTP24A16X2_HL_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_HH_args, + 1, Iclass_AE_CVTP24A16X2_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_TRUNCP24Q48X2_args, + 1, Iclass_AE_TRUNCP24Q48X2_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCA32X2F64S_args, + 2, Iclass_AE_TRUNCA32X2F64S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCI32X2F64S_args, + 2, Iclass_AE_TRUNCI32X2F64S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCA32F64S_L_args, + 2, Iclass_AE_TRUNCA32F64S_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCI32F64S_L_args, + 2, Iclass_AE_TRUNCI32F64S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCP16_args, + 1, Iclass_AE_TRUNCP16_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F64SSYM_args, + 2, Iclass_AE_ROUND32X2F64SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F64SASYM_args, + 2, Iclass_AE_ROUND32X2F64SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F48SSYM_args, + 2, Iclass_AE_ROUND32X2F48SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F48SASYM_args, + 2, Iclass_AE_ROUND32X2F48SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND16X4F32SSYM_args, + 2, Iclass_AE_ROUND16X4F32SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND16X4F32SASYM_args, + 2, Iclass_AE_ROUND16X4F32SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND24X2F48SSYM_args, + 2, Iclass_AE_ROUND24X2F48SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND24X2F48SASYM_args, + 2, Iclass_AE_ROUND24X2F48SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUNDSP16Q48X2SYM_args, + 2, Iclass_AE_ROUNDSP16Q48X2SYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUNDSP16Q48X2ASYM_args, + 2, Iclass_AE_ROUNDSP16Q48X2ASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_MINABS32S_args, + 2, Iclass_AE_MINABS32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAXABS32S_args, + 2, Iclass_AE_MAXABS32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSP16F24SYM_args, + 2, Iclass_AE_ROUNDSP16F24SYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSP16F24ASYM_args, + 2, Iclass_AE_ROUNDSP16F24ASYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOV_args, + 1, Iclass_AE_MOV_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVT64_args, + 1, Iclass_AE_MOVT64_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVF64_args, + 1, Iclass_AE_MOVF64_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTQ56A32S_args, + 1, Iclass_AE_CVTQ56A32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT48A32_args, + 1, Iclass_AE_CVT48A32_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT64A32_args, + 1, Iclass_AE_CVT64A32_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTQ56P32S_L_args, + 1, Iclass_AE_CVTQ56P32S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTQ56P32S_H_args, + 1, Iclass_AE_CVTQ56P32S_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT64F32_H_args, + 1, Iclass_AE_CVT64F32_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT48F32_L_args, + 1, Iclass_AE_CVT48F32_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT48F32_H_args, + 1, Iclass_AE_CVT48F32_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_SAT48S_args, + 2, Iclass_AE_SAT48S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SATQ56S_args, + 2, Iclass_AE_SATQ56S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SAT24S_args, + 2, Iclass_AE_SAT24S_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCQ32_args, + 1, Iclass_AE_TRUNCQ32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MINABS64S_args, + 2, Iclass_AE_MINABS64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAXABS64S_args, + 2, Iclass_AE_MAXABS64S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSQ32F48SYM_args, + 2, Iclass_AE_ROUNDSQ32F48SYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSQ32F48ASYM_args, + 2, Iclass_AE_ROUNDSQ32F48ASYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCA32Q48_args, + 1, Iclass_AE_TRUNCA32Q48_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD32_L_args, + 1, Iclass_AE_MOVAD32_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD32_H_args, + 1, Iclass_AE_MOVAD32_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_3_args, + 1, Iclass_AE_MOVAD16_3_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_2_args, + 1, Iclass_AE_MOVAD16_2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_1_args, + 1, Iclass_AE_MOVAD16_1_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_0_args, + 1, Iclass_AE_MOVAD16_0_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRA64_32_args, + 1, Iclass_AE_SRA64_32_stateArgs, 0, 0 }, + { 3, Iclass_AE_PKSR32_args, + 2, Iclass_AE_PKSR32_stateArgs, 0, 0 }, + { 3, Iclass_AE_PKSR24_args, + 2, Iclass_AE_PKSR24_stateArgs, 0, 0 }, + { 3, Iclass_AE_PKSRF32_args, + 2, Iclass_AE_PKSRF32_stateArgs, 0, 0 }, + { 3, Iclass_AE_PKSR16_args, + 2, Iclass_AE_PKSR16_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCA16P24S_L_args, + 1, Iclass_AE_TRUNCA16P24S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCA16P24S_H_args, + 1, Iclass_AE_TRUNCA16P24S_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD32_args, + 1, Iclass_AE_ADD32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB32_args, + 1, Iclass_AE_SUB32_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDSUB32_args, + 1, Iclass_AE_ADDSUB32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUBADD32_args, + 1, Iclass_AE_SUBADD32_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD16_args, + 1, Iclass_AE_ADD16_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB16_args, + 1, Iclass_AE_SUB16_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD32_HL_LH_args, + 1, Iclass_AE_ADD32_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDSUB32_HL_LH_args, + 1, Iclass_AE_ADDSUB32_HL_LH_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG32_args, + 1, Iclass_AE_NEG32_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS32_args, + 1, Iclass_AE_ABS32_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG32_L_args, + 1, Iclass_AE_NEG32_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD24S_args, + 2, Iclass_AE_ADD24S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB24S_args, + 2, Iclass_AE_SUB24S_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD32S_args, + 2, Iclass_AE_ADD32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB32S_args, + 2, Iclass_AE_SUB32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDSUB32S_args, + 2, Iclass_AE_ADDSUB32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUBADD32S_args, + 2, Iclass_AE_SUBADD32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD16S_args, + 2, Iclass_AE_ADD16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB16S_args, + 2, Iclass_AE_SUB16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD32S_HL_LH_args, + 2, Iclass_AE_ADD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDSUB32S_HL_LH_args, + 2, Iclass_AE_ADDSUB32S_HL_LH_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG24S_args, + 2, Iclass_AE_NEG24S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS24S_args, + 2, Iclass_AE_ABS24S_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG32S_args, + 1, Iclass_AE_NEG32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS32S_args, + 1, Iclass_AE_ABS32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG16S_args, + 1, Iclass_AE_NEG16S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS16S_args, + 1, Iclass_AE_ABS16S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS16_args, + 1, Iclass_AE_ABS16_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULC16JS_H_args, + 2, Iclass_AE_MULC16JS_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULC16JS_L_args, + 2, Iclass_AE_MULC16JS_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAC16JS_H_args, + 2, Iclass_AE_MULAC16JS_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAC16JS_L_args, + 2, Iclass_AE_MULAC16JS_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_LT16_args, + 1, Iclass_AE_LT16_stateArgs, 0, 0 }, + { 3, Iclass_AE_LE16_args, + 1, Iclass_AE_LE16_stateArgs, 0, 0 }, + { 3, Iclass_AE_EQ16_args, + 1, Iclass_AE_EQ16_stateArgs, 0, 0 }, + { 3, Iclass_AE_LT32_args, + 1, Iclass_AE_LT32_stateArgs, 0, 0 }, + { 3, Iclass_AE_LE32_args, + 1, Iclass_AE_LE32_stateArgs, 0, 0 }, + { 3, Iclass_AE_EQ32_args, + 1, Iclass_AE_EQ32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MIN32_args, + 1, Iclass_AE_MIN32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAX32_args, + 1, Iclass_AE_MAX32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MINMAX32_args, + 1, Iclass_AE_MINMAX32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MINMAX16_args, + 1, Iclass_AE_MINMAX16_stateArgs, 0, 0 }, + { 3, Iclass_AE_MIN16_args, + 1, Iclass_AE_MIN16_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAX16_args, + 1, Iclass_AE_MAX16_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD64_args, + 1, Iclass_AE_ADD64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB64_args, + 1, Iclass_AE_SUB64_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG64_args, + 1, Iclass_AE_NEG64_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS64_args, + 1, Iclass_AE_ABS64_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDSQ56S_args, + 2, Iclass_AE_ADDSQ56S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUBSQ56S_args, + 2, Iclass_AE_SUBSQ56S_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD64S_args, + 2, Iclass_AE_ADD64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB64S_args, + 2, Iclass_AE_SUB64S_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEGSQ56S_args, + 2, Iclass_AE_NEGSQ56S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABSSQ56S_args, + 2, Iclass_AE_ABSSQ56S_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG64S_args, + 2, Iclass_AE_NEG64S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS64S_args, + 2, Iclass_AE_ABS64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_AND_args, + 1, Iclass_AE_AND_stateArgs, 0, 0 }, + { 3, Iclass_AE_NAND_args, + 1, Iclass_AE_NAND_stateArgs, 0, 0 }, + { 3, Iclass_AE_OR_args, + 1, Iclass_AE_OR_stateArgs, 0, 0 }, + { 3, Iclass_AE_XOR_args, + 1, Iclass_AE_XOR_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI24_args, + 1, Iclass_AE_SLAI24_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLI24_args, + 1, Iclass_AE_SRLI24_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI24_args, + 1, Iclass_AE_SRAI24_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS24_args, + 2, Iclass_AE_SLAS24_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRLS24_args, + 2, Iclass_AE_SRLS24_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRAS24_args, + 2, Iclass_AE_SRAS24_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI16_args, + 1, Iclass_AE_SRAI16_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI16R_args, + 1, Iclass_AE_SRAI16R_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI32_args, + 1, Iclass_AE_SLAI32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLI32_args, + 1, Iclass_AE_SRLI32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI32_args, + 1, Iclass_AE_SRAI32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI32R_args, + 1, Iclass_AE_SRAI32R_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS32_args, + 2, Iclass_AE_SLAS32_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRLS32_args, + 2, Iclass_AE_SRLS32_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRAS32_args, + 2, Iclass_AE_SRAS32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA32_args, + 1, Iclass_AE_SLAA32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLA32_args, + 1, Iclass_AE_SRLA32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA32_args, + 1, Iclass_AE_SRAA32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI16S_args, + 2, Iclass_AE_SLAI16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA16S_args, + 2, Iclass_AE_SLAA16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA16S_args, + 2, Iclass_AE_SRAA16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA16RS_args, + 2, Iclass_AE_SRAA16RS_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI24S_args, + 2, Iclass_AE_SLAI24S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS24S_args, + 3, Iclass_AE_SLAS24S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI32S_args, + 2, Iclass_AE_SLAI32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS32S_args, + 3, Iclass_AE_SLAS32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA32S_args, + 2, Iclass_AE_SLAA32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA32S_args, + 2, Iclass_AE_SRAA32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA32RS_args, + 2, Iclass_AE_SRAA32RS_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLASQ56_args, + 2, Iclass_AE_SLASQ56_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRLSQ56_args, + 2, Iclass_AE_SRLSQ56_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRASQ56_args, + 2, Iclass_AE_SRASQ56_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAAQ56_args, + 1, Iclass_AE_SLAAQ56_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLAQ56_args, + 1, Iclass_AE_SRLAQ56_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAAQ56_args, + 1, Iclass_AE_SRAAQ56_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI64_args, + 1, Iclass_AE_SLAI64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLI64_args, + 1, Iclass_AE_SRLI64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI64_args, + 1, Iclass_AE_SRAI64_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS64_args, + 2, Iclass_AE_SLAS64_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRLS64_args, + 2, Iclass_AE_SRLS64_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRAS64_args, + 2, Iclass_AE_SRAS64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA64_args, + 1, Iclass_AE_SLAA64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLA64_args, + 1, Iclass_AE_SRLA64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA64_args, + 1, Iclass_AE_SRAA64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAISQ56S_args, + 2, Iclass_AE_SLAISQ56S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLASSQ56S_args, + 3, Iclass_AE_SLASSQ56S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAASQ56S_args, + 2, Iclass_AE_SLAASQ56S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI64S_args, + 2, Iclass_AE_SLAI64S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS64S_args, + 3, Iclass_AE_SLAS64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA64S_args, + 2, Iclass_AE_SLAA64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_LT64_args, + 1, Iclass_AE_LT64_stateArgs, 0, 0 }, + { 3, Iclass_AE_LE64_args, + 1, Iclass_AE_LE64_stateArgs, 0, 0 }, + { 3, Iclass_AE_EQ64_args, + 1, Iclass_AE_EQ64_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAX64_args, + 1, Iclass_AE_MAX64_stateArgs, 0, 0 }, + { 3, Iclass_AE_MIN64_args, + 1, Iclass_AE_MIN64_stateArgs, 0, 0 }, + { 2, Iclass_AE_NSA64_args, + 1, Iclass_AE_NSA64_stateArgs, 0, 0 }, + { 2, Iclass_AE_NSAZ16_0_args, + 1, Iclass_AE_NSAZ16_0_stateArgs, 0, 0 }, + { 2, Iclass_AE_NSAZ32_L_args, + 1, Iclass_AE_NSAZ32_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32F48P16S_LL_args, + 2, Iclass_AE_MULS32F48P16S_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32S_LL_args, + 2, Iclass_AE_MULF32S_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32_LL_args, + 1, Iclass_AE_MUL32_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32R_LL_args, + 1, Iclass_AE_MULF32R_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32RA_LL_args, + 1, Iclass_AE_MULF32RA_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32F48P16S_LH_args, + 2, Iclass_AE_MULS32F48P16S_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32S_LH_args, + 2, Iclass_AE_MULF32S_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32_LH_args, + 1, Iclass_AE_MUL32_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32R_LH_args, + 1, Iclass_AE_MULF32R_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32RA_LH_args, + 1, Iclass_AE_MULF32RA_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32F48P16S_HH_args, + 2, Iclass_AE_MULS32F48P16S_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32S_HH_args, + 2, Iclass_AE_MULF32S_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32_HH_args, + 1, Iclass_AE_MUL32_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32R_HH_args, + 1, Iclass_AE_MULF32R_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32RA_HH_args, + 1, Iclass_AE_MULF32RA_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAS32F48P16S_LL_args, + 2, Iclass_AE_MULAS32F48P16S_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAF32S_LL_args, + 2, Iclass_AE_MULAF32S_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA32_LL_args, + 1, Iclass_AE_MULA32_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAF32R_LL_args, + 1, Iclass_AE_MULAF32R_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAF32RA_LL_args, + 1, Iclass_AE_MULAF32RA_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAS32F48P16S_LH_args, + 2, Iclass_AE_MULAS32F48P16S_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAF32S_LH_args, + 2, Iclass_AE_MULAF32S_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA32_LH_args, + 1, Iclass_AE_MULA32_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAF32R_LH_args, + 1, Iclass_AE_MULAF32R_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAF32RA_LH_args, + 1, Iclass_AE_MULAF32RA_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAS32F48P16S_HH_args, + 2, Iclass_AE_MULAS32F48P16S_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAF32S_HH_args, + 2, Iclass_AE_MULAF32S_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA32_HH_args, + 1, Iclass_AE_MULA32_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAF32R_HH_args, + 1, Iclass_AE_MULAF32R_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAF32RA_HH_args, + 1, Iclass_AE_MULAF32RA_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSS32F48P16S_LL_args, + 2, Iclass_AE_MULSS32F48P16S_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSF32S_LL_args, + 2, Iclass_AE_MULSF32S_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32_LL_args, + 1, Iclass_AE_MULS32_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSF32R_LL_args, + 1, Iclass_AE_MULSF32R_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSF32RA_LL_args, + 1, Iclass_AE_MULSF32RA_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSS32F48P16S_LH_args, + 2, Iclass_AE_MULSS32F48P16S_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSF32S_LH_args, + 2, Iclass_AE_MULSF32S_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32_LH_args, + 1, Iclass_AE_MULS32_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSF32R_LH_args, + 1, Iclass_AE_MULSF32R_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSF32RA_LH_args, + 1, Iclass_AE_MULSF32RA_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSS32F48P16S_HH_args, + 2, Iclass_AE_MULSS32F48P16S_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSF32S_HH_args, + 2, Iclass_AE_MULSF32S_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32_HH_args, + 1, Iclass_AE_MULS32_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSF32R_HH_args, + 1, Iclass_AE_MULSF32R_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSF32RA_HH_args, + 1, Iclass_AE_MULSF32RA_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32U_LL_args, + 1, Iclass_AE_MUL32U_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA32U_LL_args, + 1, Iclass_AE_MULA32U_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32U_LL_args, + 1, Iclass_AE_MULS32U_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF16SS_33_args, + 2, Iclass_AE_MULF16SS_33_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF16SS_22_args, + 2, Iclass_AE_MULF16SS_22_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF16SS_32_args, + 2, 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}, + { 5, Iclass_AE_MULFQ16X2_FIR_0_args, + 1, Iclass_AE_MULFQ16X2_FIR_0_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFQ16X2_FIR_3_args, + 1, Iclass_AE_MULAFQ16X2_FIR_3_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFQ16X2_FIR_2_args, + 1, Iclass_AE_MULAFQ16X2_FIR_2_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFQ16X2_FIR_1_args, + 1, Iclass_AE_MULAFQ16X2_FIR_1_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFQ16X2_FIR_0_args, + 1, Iclass_AE_MULAFQ16X2_FIR_0_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAAAAFQ32X16_args, + 1, Iclass_AE_MULZAAAAFQ32X16_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAAAFQ32X16_args, + 1, Iclass_AE_MULAAAAFQ32X16_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAAAAQ32X16_args, + 1, Iclass_AE_MULZAAAAQ32X16_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAAAQ32X16_args, + 1, Iclass_AE_MULAAAAQ32X16_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL16_00_args, + 1, Iclass_AE_MUL16_00_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA16_00_args, + 1, Iclass_AE_MULA16_00_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZAAAAQ16_args, + 1, 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Iclass_AE_LBKI_DBI_IP_stateArgs, 0, 0 }, + { 4, Iclass_AE_LBKI_DBI_args, + 3, Iclass_AE_LBKI_DBI_stateArgs, 0, 0 }, + { 3, Iclass_AE_LBI_DBI_IC_args, + 6, Iclass_AE_LBI_DBI_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LBI_DBI_IP_args, + 3, Iclass_AE_LBI_DBI_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LBI_DBI_args, + 3, Iclass_AE_LBI_DBI_stateArgs, 0, 0 }, + { 4, Iclass_AE_LBK_DB_IC_args, + 6, Iclass_AE_LBK_DB_IC_stateArgs, 0, 0 }, + { 4, Iclass_AE_LBK_DB_IP_args, + 3, Iclass_AE_LBK_DB_IP_stateArgs, 0, 0 }, + { 4, Iclass_AE_LBK_DB_args, + 3, Iclass_AE_LBK_DB_stateArgs, 0, 0 }, + { 3, Iclass_AE_LB_DB_IC_args, + 6, Iclass_AE_LB_DB_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LB_DB_IP_args, + 3, Iclass_AE_LB_DB_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LB_DB_args, + 3, Iclass_AE_LB_DB_stateArgs, 0, 0 }, + { 3, Iclass_AE_VLEL32T_args, + 3, Iclass_AE_VLEL32T_stateArgs, 0, 0 }, + { 3, Iclass_AE_VLEL16T_args, + 3, Iclass_AE_VLEL16T_stateArgs, 0, 0 }, + { 2, Iclass_AE_SB_args, + 4, Iclass_AE_SB_stateArgs, 0, 0 }, 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Iclass_AE_MULZAAD32EP_HH_LL_args, + 1, Iclass_AE_MULZAAD32EP_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZSSD32EP_HH_LL_args, + 1, Iclass_AE_MULZSSD32EP_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAD32EP_HH_LL_args, + 1, Iclass_AE_MULAAD32EP_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSSD32EP_HH_LL_args, + 1, Iclass_AE_MULSSD32EP_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAD32USEP_HL_LH_args, + 1, Iclass_AE_MULAAD32USEP_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAAD32USEP_HL_LH_args, + 1, Iclass_AE_MULZAAD32USEP_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MUL32USEP_LH_args, + 1, Iclass_AE_MUL32USEP_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULA32USEP_LH_args, + 1, Iclass_AE_MULA32USEP_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MUL32USEP_LL_args, + 1, Iclass_AE_MUL32USEP_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULA32USEP_LL_args, + 1, Iclass_AE_MULA32USEP_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_SRAI72_args, + 1, Iclass_AE_SRAI72_stateArgs, 0, 0 }, + { 4, Iclass_AE_SLAI72_args, + 1, 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2, Iclass_AE_SATU8X4X32_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND8X8F16SSYM_args, + 2, Iclass_AE_ROUND8X8F16SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND8X8F16SASYM_args, + 2, Iclass_AE_ROUND8X8F16SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND8X4F32SSYM_L_args, + 2, Iclass_AE_ROUND8X4F32SSYM_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND8X4F32SASYM_L_args, + 2, Iclass_AE_ROUND8X4F32SASYM_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVDA8_args, + 1, Iclass_AE_MOVDA8_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVAD8_args, + 1, Iclass_AE_MOVAD8_stateArgs, 0, 0 }, + { 4, Iclass_AE_MOVDX2_args, + 1, Iclass_AE_MOVDX2_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUB32J_args, + 1, Iclass_AE_ADDANDSUB32J_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDW8_args, + 1, Iclass_AE_ADDW8_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDW16_args, + 1, Iclass_AE_ADDW16_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDW32_args, + 1, Iclass_AE_ADDW32_stateArgs, 0, 0 }, + { 4, Iclass_AE_SUBW8_args, + 1, Iclass_AE_SUBW8_stateArgs, 0, 0 }, + { 4, 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Iclass_AE_MULAFP32X2S_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSFP32X2S_HL_LH_args, + 2, Iclass_AE_MULSFP32X2S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZAAF2D32S_HH_LL_args, + 2, Iclass_AE_MULZAAF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZASF2D32S_HH_LL_args, + 2, Iclass_AE_MULZASF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSAF2D32S_HH_LL_args, + 2, Iclass_AE_MULZSAF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSSF2D32S_HH_LL_args, + 2, Iclass_AE_MULZSSF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAAF2D32S_HH_LL_args, + 2, Iclass_AE_MULAAF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULASF2D32S_HH_LL_args, + 2, Iclass_AE_MULASF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSAF2D32S_HH_LL_args, + 2, Iclass_AE_MULSAF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSSF2D32S_HH_LL_args, + 2, Iclass_AE_MULSSF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZAAF2D32S_HL_LH_args, + 2, Iclass_AE_MULZAAF2D32S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZASF2D32S_HL_LH_args, + 2, Iclass_AE_MULZASF2D32S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSAF2D32S_HL_LH_args, + 2, Iclass_AE_MULZSAF2D32S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSSF2D32S_HL_LH_args, + 2, Iclass_AE_MULZSSF2D32S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAAF2D32S_HL_LH_args, + 2, Iclass_AE_MULAAF2D32S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULASF2D32S_HL_LH_args, + 2, Iclass_AE_MULASF2D32S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSAF2D32S_HL_LH_args, + 2, Iclass_AE_MULSAF2D32S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSSF2D32S_HL_LH_args, + 2, Iclass_AE_MULSSF2D32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32S_HH_args, + 2, Iclass_AE_MUL32S_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA32S_HH_args, + 2, Iclass_AE_MULA32S_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32S_HH_args, + 2, Iclass_AE_MULS32S_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32S_LL_args, + 2, Iclass_AE_MUL32S_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA32S_LL_args, + 2, Iclass_AE_MULA32S_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32S_LL_args, + 2, Iclass_AE_MULS32S_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32S_HL_args, + 2, Iclass_AE_MUL32S_HL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA32S_HL_args, + 2, Iclass_AE_MULA32S_HL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32S_HL_args, + 2, Iclass_AE_MULS32S_HL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32S_LH_args, + 2, Iclass_AE_MUL32S_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA32S_LH_args, + 2, Iclass_AE_MULA32S_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32S_LH_args, + 2, Iclass_AE_MULS32S_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MUL32X2S_HH_LL_args, + 2, Iclass_AE_MUL32X2S_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULA32X2S_HH_LL_args, + 2, Iclass_AE_MULA32X2S_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULS32X2S_HH_LL_args, + 2, Iclass_AE_MULS32X2S_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MUL32X2S_HL_LH_args, + 2, Iclass_AE_MUL32X2S_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULA32X2S_HL_LH_args, + 2, Iclass_AE_MULA32X2S_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULS32X2S_HL_LH_args, + 2, Iclass_AE_MULS32X2S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZAAD32S_HH_LL_args, + 2, Iclass_AE_MULZAAD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZASD32S_HH_LL_args, + 2, Iclass_AE_MULZASD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZSAD32S_HH_LL_args, + 2, Iclass_AE_MULZSAD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZSSD32S_HH_LL_args, + 2, Iclass_AE_MULZSSD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAAD32S_HH_LL_args, + 2, Iclass_AE_MULAAD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULASD32S_HH_LL_args, + 2, Iclass_AE_MULASD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSAD32S_HH_LL_args, + 2, Iclass_AE_MULSAD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSSD32S_HH_LL_args, + 2, Iclass_AE_MULSSD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZAAD32S_HL_LH_args, + 2, Iclass_AE_MULZAAD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZASD32S_HL_LH_args, + 2, Iclass_AE_MULZASD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZSAD32S_HL_LH_args, + 2, Iclass_AE_MULZSAD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZSSD32S_HL_LH_args, + 2, Iclass_AE_MULZSSD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAAD32S_HL_LH_args, + 2, Iclass_AE_MULAAD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULASD32S_HL_LH_args, + 2, Iclass_AE_MULASD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSAD32S_HL_LH_args, + 2, Iclass_AE_MULSAD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSSD32S_HL_LH_args, + 2, Iclass_AE_MULSSD32S_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULF32X2RA_HH_LL_args, + 1, Iclass_AE_MULF32X2RA_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAF32X2RA_HH_LL_args, + 1, Iclass_AE_MULAF32X2RA_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSF32X2RA_HH_LL_args, + 1, Iclass_AE_MULSF32X2RA_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULF32X2RA_HL_LH_args, + 1, Iclass_AE_MULF32X2RA_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAF32X2RA_HL_LH_args, + 1, Iclass_AE_MULAF32X2RA_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSF32X2RA_HL_LH_args, + 1, Iclass_AE_MULSF32X2RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZAAF2D32RA_HH_LL_args, + 1, Iclass_AE_MULZAAF2D32RA_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZASF2D32RA_HH_LL_args, + 1, Iclass_AE_MULZASF2D32RA_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSAF2D32RA_HH_LL_args, + 1, Iclass_AE_MULZSAF2D32RA_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSSF2D32RA_HH_LL_args, + 1, Iclass_AE_MULZSSF2D32RA_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAAF2D32RA_HH_LL_args, + 1, Iclass_AE_MULAAF2D32RA_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULASF2D32RA_HH_LL_args, + 1, Iclass_AE_MULASF2D32RA_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSAF2D32RA_HH_LL_args, + 1, Iclass_AE_MULSAF2D32RA_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSSF2D32RA_HH_LL_args, + 1, Iclass_AE_MULSSF2D32RA_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZAAF2D32RA_HL_LH_args, + 1, Iclass_AE_MULZAAF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZASF2D32RA_HL_LH_args, + 1, Iclass_AE_MULZASF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSAF2D32RA_HL_LH_args, + 1, Iclass_AE_MULZSAF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSSF2D32RA_HL_LH_args, + 1, Iclass_AE_MULZSSF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAAF2D32RA_HL_LH_args, + 1, Iclass_AE_MULAAF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULASF2D32RA_HL_LH_args, + 1, Iclass_AE_MULASF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSAF2D32RA_HL_LH_args, + 1, Iclass_AE_MULSAF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSSF2D32RA_HL_LH_args, + 1, Iclass_AE_MULSSF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULF32X2R_HH_LL_args, + 1, Iclass_AE_MULF32X2R_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAF32X2R_HH_LL_args, + 1, Iclass_AE_MULAF32X2R_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSF32X2R_HH_LL_args, + 1, Iclass_AE_MULSF32X2R_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULF32X2R_HL_LH_args, + 1, Iclass_AE_MULF32X2R_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAF32X2R_HL_LH_args, + 1, Iclass_AE_MULAF32X2R_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSF32X2R_HL_LH_args, + 1, Iclass_AE_MULSF32X2R_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULFC32W_args, + 1, Iclass_AE_MULFC32W_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAFC32W_args, + 1, Iclass_AE_MULAFC32W_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULFCJ32W_args, + 1, Iclass_AE_MULFCJ32W_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAFCJ32W_args, + 1, Iclass_AE_MULAFCJ32W_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULFCJ32RAS_args, + 2, Iclass_AE_MULFCJ32RAS_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAFCJ32RAS_args, + 2, Iclass_AE_MULAFCJ32RAS_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULF2P32X4RS_args, + 2, Iclass_AE_MULF2P32X4RS_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAF2P32X4RS_args, + 2, Iclass_AE_MULAF2P32X4RS_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSF2P32X4RS_args, + 2, Iclass_AE_MULSF2P32X4RS_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULF2P32X4RAS_args, + 2, Iclass_AE_MULF2P32X4RAS_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAF2P32X4RAS_args, + 2, Iclass_AE_MULAF2P32X4RAS_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSF2P32X4RAS_args, + 2, Iclass_AE_MULSF2P32X4RAS_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULP32X2S_args, + 2, Iclass_AE_MULP32X2S_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL2P32X4S_args, + 2, Iclass_AE_MUL2P32X4S_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL2P32X4_args, + 1, Iclass_AE_MUL2P32X4_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA2P32X4_args, + 1, Iclass_AE_MULA2P32X4_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULS2P32X4_args, + 1, Iclass_AE_MULS2P32X4_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL2P32X4T_args, + 1, Iclass_AE_MUL2P32X4T_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA2P32X4T_args, + 1, Iclass_AE_MULA2P32X4T_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULS2P32X4T_args, + 1, Iclass_AE_MULS2P32X4T_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAA32X2_HH_LL_args, + 1, Iclass_AE_MULZAA32X2_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZSS32X2_HH_LL_args, + 1, Iclass_AE_MULZSS32X2_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAA32X2_HH_LL_args, + 1, Iclass_AE_MULAA32X2_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSS32X2_HH_LL_args, + 1, Iclass_AE_MULSS32X2_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULCJ32_args, + 1, Iclass_AE_MULCJ32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULACJ32_args, + 1, Iclass_AE_MULACJ32_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULADDF32RS_args, + 2, Iclass_AE_MULADDF32RS_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULADDF32RAS_args, + 2, Iclass_AE_MULADDF32RAS_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSUBF32RS_args, + 2, Iclass_AE_MULSUBF32RS_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSUBF32RAS_args, + 2, Iclass_AE_MULSUBF32RAS_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULFC32RA_args, + 1, Iclass_AE_MULFC32RA_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAFC32RA_args, + 1, Iclass_AE_MULAFC32RA_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULCJ32W_args, + 1, Iclass_AE_MULCJ32W_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULACJ32W_args, + 1, Iclass_AE_MULACJ32W_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULC32W_args, + 1, Iclass_AE_MULC32W_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAC32W_args, + 1, Iclass_AE_MULAC32W_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULF2D32X2WS_args, + 2, Iclass_AE_MULF2D32X2WS_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZAAAA2Q16_args, + 1, Iclass_AE_MULZAAAA2Q16_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAAAA2Q16_args, + 1, Iclass_AE_MULAAAA2Q16_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULP16S_H_args, + 2, Iclass_AE_MULP16S_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAP16S_H_args, + 2, Iclass_AE_MULAP16S_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSP16S_H_args, + 2, Iclass_AE_MULSP16S_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULP16S_L_args, + 2, Iclass_AE_MULP16S_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAP16S_L_args, + 2, Iclass_AE_MULAP16S_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSP16S_L_args, + 2, Iclass_AE_MULSP16S_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULC16W_H_args, + 1, Iclass_AE_MULC16W_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAC16W_H_args, + 1, Iclass_AE_MULAC16W_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULC16W_L_args, + 1, Iclass_AE_MULC16W_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAC16W_L_args, + 1, Iclass_AE_MULAC16W_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_MUL2C16S_args, + 2, Iclass_AE_MUL2C16S_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULA2C16S_args, + 2, Iclass_AE_MULA2C16S_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULFC16S_args, + 2, Iclass_AE_MULFC16S_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAFC16S_args, + 2, Iclass_AE_MULAFC16S_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULFCJ16S_args, + 2, Iclass_AE_MULFCJ16S_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAFCJ16S_args, + 2, Iclass_AE_MULAFCJ16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULFCJ16RAS_args, + 2, Iclass_AE_MULFCJ16RAS_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAFCJ16RAS_args, + 2, Iclass_AE_MULAFCJ16RAS_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULC16S_args, + 2, Iclass_AE_MULC16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAC16S_args, + 2, Iclass_AE_MULAC16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULFP16X4RS_args, + 2, Iclass_AE_MULFP16X4RS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFD16X16X4RAS_args, + 2, Iclass_AE_MULFD16X16X4RAS_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULP16X16X4S_args, + 2, Iclass_AE_MULP16X16X4S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAP16X16X4S_args, + 2, Iclass_AE_MULAP16X16X4S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSP16X16X4S_args, + 2, Iclass_AE_MULSP16X16X4S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZAA2D16SS_HH_LL_args, + 2, Iclass_AE_MULZAA2D16SS_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZAA2D16SS_HL_LH_args, + 2, Iclass_AE_MULZAA2D16SS_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZSS2D16SS_HH_LL_args, + 2, Iclass_AE_MULZSS2D16SS_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZSS2D16SS_HL_LH_args, + 2, Iclass_AE_MULZSS2D16SS_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAA2D16SS_HH_LL_args, + 2, Iclass_AE_MULAA2D16SS_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAA2D16SS_HL_LH_args, + 2, Iclass_AE_MULAA2D16SS_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSS2D16SS_HH_LL_args, + 2, Iclass_AE_MULSS2D16SS_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSS2D16SS_HL_LH_args, + 2, Iclass_AE_MULSS2D16SS_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZAAFD16SS_HH_LL_args, + 2, Iclass_AE_MULZAAFD16SS_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZAAFD16SS_HL_LH_args, + 2, Iclass_AE_MULZAAFD16SS_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZSSFD16SS_HH_LL_args, + 2, Iclass_AE_MULZSSFD16SS_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZSSFD16SS_HL_LH_args, + 2, Iclass_AE_MULZSSFD16SS_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAAFD16SS_HH_LL_args, + 2, Iclass_AE_MULAAFD16SS_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAAFD16SS_HL_LH_args, + 2, Iclass_AE_MULAAFD16SS_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSSFD16SS_HH_LL_args, + 2, Iclass_AE_MULSSFD16SS_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSSFD16SS_HL_LH_args, + 2, Iclass_AE_MULSSFD16SS_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULFD16X16X4WS_args, + 2, Iclass_AE_MULFD16X16X4WS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULZAAAA2Q16X8_args, + 1, Iclass_AE_MULZAAAA2Q16X8_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAAAA2Q16X8_args, + 1, Iclass_AE_MULAAAA2Q16X8_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAAAA2Q8_args, + 1, Iclass_AE_MULZAAAA2Q8_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAAA2Q8_args, + 1, Iclass_AE_MULAAAA2Q8_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULC32X16W_H_args, + 1, Iclass_AE_MULC32X16W_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAC32X16W_H_args, + 1, Iclass_AE_MULAC32X16W_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULC32X16W_L_args, + 1, Iclass_AE_MULC32X16W_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAC32X16W_L_args, + 1, Iclass_AE_MULAC32X16W_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULPC32X16X2_args, + 1, Iclass_AE_MULPC32X16X2_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAPC32X16X2_args, + 1, Iclass_AE_MULAPC32X16X2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULFP32X16_H_args, + 1, Iclass_AE_MULFP32X16_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAFP32X16_H_args, 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Iclass_AE_MULAFCJ32X16W_L_args, + 1, Iclass_AE_MULAFCJ32X16W_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULF2P32X16X4RAS_args, + 2, Iclass_AE_MULF2P32X16X4RAS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAF2P32X16X4RAS_args, + 2, Iclass_AE_MULAF2P32X16X4RAS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULSF2P32X16X4RAS_args, + 2, Iclass_AE_MULSF2P32X16X4RAS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULF2P32X16X4RS_args, + 2, Iclass_AE_MULF2P32X16X4RS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAF2P32X16X4RS_args, + 2, Iclass_AE_MULAF2P32X16X4RS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULSF2P32X16X4RS_args, + 2, Iclass_AE_MULSF2P32X16X4RS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULF2P32X16X4S_args, + 2, Iclass_AE_MULF2P32X16X4S_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAF2P32X16X4S_args, + 2, Iclass_AE_MULAF2P32X16X4S_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULSF2P32X16X4S_args, + 2, Iclass_AE_MULSF2P32X16X4S_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFPC32X16X2RAS_args, + 2, Iclass_AE_MULFPC32X16X2RAS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFPC32X16X2RAS_args, + 2, Iclass_AE_MULAFPC32X16X2RAS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFPCJ32X16X2RAS_args, + 2, Iclass_AE_MULFPCJ32X16X2RAS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFPCJ32X16X2RAS_args, + 2, Iclass_AE_MULAFPCJ32X16X2RAS_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZAAAA2Q32X16_args, + 1, Iclass_AE_MULZAAAA2Q32X16_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAAAA2Q32X16_args, + 1, Iclass_AE_MULAAAA2Q32X16_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL2Q32X16_FIR_H_args, + 1, Iclass_AE_MUL2Q32X16_FIR_H_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA2Q32X16_FIR_H_args, + 1, Iclass_AE_MULA2Q32X16_FIR_H_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL2Q32X16_FIR_L_args, + 1, Iclass_AE_MUL2Q32X16_FIR_L_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA2Q32X16_FIR_L_args, + 1, Iclass_AE_MULA2Q32X16_FIR_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI8_args, + 1, Iclass_AE_SRAI8_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI8R_args, + 1, Iclass_AE_SRAI8R_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLI8_args, + 1, Iclass_AE_SRLI8_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI8_args, + 1, Iclass_AE_SLAI8_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI8S_args, + 2, Iclass_AE_SLAI8S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA8_args, + 1, Iclass_AE_SLAA8_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLA8_args, + 1, Iclass_AE_SRLA8_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA8S_args, + 2, Iclass_AE_SLAA8S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA8RS_args, + 2, Iclass_AE_SRAA8RS_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA8S_args, + 2, Iclass_AE_SRAA8S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLI16_args, + 1, Iclass_AE_SRLI16_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI16_args, + 1, Iclass_AE_SLAI16_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA16_args, + 1, Iclass_AE_SLAA16_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLA16_args, + 1, Iclass_AE_SRLA16_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI16SYM_args, + 1, Iclass_AE_SRAI16SYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA16SYMS_args, + 2, Iclass_AE_SRAA16SYMS_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI32SYM_args, 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Iclass_AE_CVTI32X4F8U_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTI32X4F8U_L_args, + 1, Iclass_AE_CVTI32X4F8U_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTI32X4F8US_H_args, + 2, Iclass_AE_CVTI32X4F8US_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTI32X4F8US_L_args, + 2, Iclass_AE_CVTI32X4F8US_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA32X4F8U_H_args, + 1, Iclass_AE_CVTA32X4F8U_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA32X4F8U_L_args, + 1, Iclass_AE_CVTA32X4F8U_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA32X4F8US_H_args, + 2, Iclass_AE_CVTA32X4F8US_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA32X4F8US_L_args, + 2, Iclass_AE_CVTA32X4F8US_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTI32X4F16_args, + 1, Iclass_AE_CVTI32X4F16_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTI32X4F16S_args, + 2, Iclass_AE_CVTI32X4F16S_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA32X4F16_args, + 1, Iclass_AE_CVTA32X4F16_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA32X4F16S_args, + 2, Iclass_AE_CVTA32X4F16S_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTI32X4F16U_args, + 1, Iclass_AE_CVTI32X4F16U_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTI32X4F16US_args, + 2, Iclass_AE_CVTI32X4F16US_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA32X4F16U_args, + 1, Iclass_AE_CVTA32X4F16U_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA32X4F16US_args, + 2, Iclass_AE_CVTA32X4F16US_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTI16X4X2F8_args, + 1, Iclass_AE_CVTI16X4X2F8_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTI16X4X2F8S_args, + 2, Iclass_AE_CVTI16X4X2F8S_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA16X4X2F8_args, + 1, Iclass_AE_CVTA16X4X2F8_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA16X4X2F8S_args, + 2, Iclass_AE_CVTA16X4X2F8S_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTI16X4X2F8U_args, + 1, Iclass_AE_CVTI16X4X2F8U_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTI16X4X2F8US_args, + 2, Iclass_AE_CVTI16X4X2F8US_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA16X4X2F8U_args, + 1, Iclass_AE_CVTA16X4X2F8U_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA16X4X2F8US_args, + 2, Iclass_AE_CVTA16X4X2F8US_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL8X8_args, + 1, Iclass_AE_SEL8X8_stateArgs, 0, 0 }, + { 3, Iclass_AE_SHFL8X8_args, + 1, Iclass_AE_SHFL8X8_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL16X4_args, + 1, Iclass_AE_SEL16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_SHFL16X4_args, + 1, Iclass_AE_SHFL16X4_stateArgs, 0, 0 }, + { 5, Iclass_AE_DSEL8X8_args, + 1, Iclass_AE_DSEL8X8_stateArgs, 0, 0 }, + { 5, Iclass_AE_DSEL16X4_args, + 1, Iclass_AE_DSEL16X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL8X8I_args, + 1, Iclass_AE_SEL8X8I_stateArgs, 0, 0 }, + { 2, Iclass_AE_RMAX8X8_args, + 1, Iclass_AE_RMAX8X8_stateArgs, 0, 0 }, + { 2, Iclass_AE_RMIN8X8_args, + 1, Iclass_AE_RMIN8X8_stateArgs, 0, 0 }, + { 2, Iclass_AE_RMAX16X4_args, + 1, Iclass_AE_RMAX16X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_RMIN16X4_args, + 1, Iclass_AE_RMIN16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_SORT16X4_args, + 1, Iclass_AE_SORT16X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADD8X8_H_args, + 1, Iclass_AE_RADD8X8_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADDA8X8_H_args, + 1, Iclass_AE_RADDA8X8_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADD8X8_L_args, + 1, Iclass_AE_RADD8X8_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADDA8X8_L_args, + 1, Iclass_AE_RADDA8X8_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADD16X4_args, + 1, Iclass_AE_RADD16X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADDA16X4_args, + 1, Iclass_AE_RADDA16X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMAX8X8_H_args, + 1, Iclass_AE_BMAX8X8_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMAX8X8_L_args, + 1, Iclass_AE_BMAX8X8_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMIN8X8_H_args, + 1, Iclass_AE_BMIN8X8_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMIN8X8_L_args, + 1, Iclass_AE_BMIN8X8_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMAX16X4_args, + 1, Iclass_AE_BMAX16X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMIN16X4_args, + 1, Iclass_AE_BMIN16X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMAX32X2_args, + 1, Iclass_AE_BMAX32X2_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMIN32X2_args, + 1, Iclass_AE_BMIN32X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_ADDINV16S_args, + 2, Iclass_AE_ADDINV16S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ADDINV32S_args, + 2, Iclass_AE_ADDINV32S_stateArgs, 0, 0 }, + { 6, Iclass_AE_MOVT16X8_args, + 1, Iclass_AE_MOVT16X8_stateArgs, 0, 0 }, + { 5, Iclass_AE_MOVT8X16_H_args, + 1, Iclass_AE_MOVT8X16_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MOVT8X16_L_args, + 1, Iclass_AE_MOVT8X16_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVBD1X4_args, + 1, Iclass_AE_MOVBD1X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVBD1X2_args, + 1, Iclass_AE_MOVBD1X2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVNEG32S_T_args, + 1, Iclass_AE_MOVNEG32S_T_stateArgs, 0, 0 }, + { 4, Iclass_AE_MOVDEXT_args, + 1, Iclass_AE_MOVDEXT_stateArgs, 0, 0 }, + { 4, Iclass_AE_MOVADEXT_H_args, + 1, Iclass_AE_MOVADEXT_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_MOVADEXT_L_args, + 1, Iclass_AE_MOVADEXT_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_NSA16X4_args, + 1, Iclass_AE_NSA16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_NSAZ32X4_args, + 1, Iclass_AE_NSAZ32X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_NSA32X4_args, + 1, Iclass_AE_NSA32X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCI16X4F32S_args, + 2, Iclass_AE_TRUNCI16X4F32S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCI16X4F64S_args, + 2, Iclass_AE_TRUNCI16X4F64S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCA16X4F32S_args, + 2, Iclass_AE_TRUNCA16X4F32S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCA16X4F64S_args, + 2, Iclass_AE_TRUNCA16X4F64S_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDC32_args, + 1, Iclass_AE_ADDC32_stateArgs, 0, 0 }, + { 4, Iclass_AE_SUBC32_args, + 1, Iclass_AE_SUBC32_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDC32U_args, + 1, Iclass_AE_ADDC32U_stateArgs, 0, 0 }, + { 4, Iclass_AE_SUBC32U_args, + 1, Iclass_AE_SUBC32U_stateArgs, 0, 0 }, + { 3, Iclass_AE_EXPADD16_H_args, + 1, Iclass_AE_EXPADD16_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_EXPSUB16_H_args, + 1, Iclass_AE_EXPSUB16_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_EXPADD16_L_args, + 1, Iclass_AE_EXPADD16_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_EXPSUB16_L_args, + 1, Iclass_AE_EXPSUB16_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDCEXP32_H_args, + 1, Iclass_AE_ADDCEXP32_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDCEXP32_L_args, + 1, Iclass_AE_ADDCEXP32_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_CALCRNG16_args, + 2, Iclass_AE_CALCRNG16_stateArgs, 0, 0 }, + { 4, Iclass_AE_CALCRNG32_args, + 2, Iclass_AE_CALCRNG32_stateArgs, 0, 0 }, + { 2, Iclass_AE_RNG32X4_args, + 2, Iclass_AE_RNG32X4_stateArgs, 0, 0 }, + { 5, Iclass_AE_LAV8X8X2_XP_args, + 1, Iclass_AE_LAV8X8X2_XP_stateArgs, 0, 0 }, + { 5, Iclass_AE_LAV16X4X2_XP_args, + 1, Iclass_AE_LAV16X4X2_XP_stateArgs, 0, 0 }, + { 5, Iclass_AE_SAV8X8X2_XP_args, + 1, Iclass_AE_SAV8X8X2_XP_stateArgs, 0, 0 }, + { 5, Iclass_AE_SAV16X4X2_XP_args, + 1, Iclass_AE_SAV16X4X2_XP_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVZBVCDR_args, + 3, Iclass_AE_MOVZBVCDR_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVDRZBVC_args, + 3, Iclass_AE_MOVDRZBVC_stateArgs, 0, 0 }, + { 6, Iclass_AE_LAVUNSQZ8X8_XP_args, + 1, Iclass_AE_LAVUNSQZ8X8_XP_stateArgs, 0, 0 }, + { 6, Iclass_AE_LAVUNSQZ16X4_XP_args, + 1, Iclass_AE_LAVUNSQZ16X4_XP_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL8Q8X8_args, + 1, Iclass_AE_MUL8Q8X8_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA8Q8X8_args, + 1, Iclass_AE_MULA8Q8X8_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL8Q4X16_args, + 1, Iclass_AE_MUL8Q4X16_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA8Q4X16_args, + 1, Iclass_AE_MULA8Q4X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL8Q8X16_args, + 1, Iclass_AE_MUL8Q8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA8Q8X16_args, + 1, Iclass_AE_MULA8Q8X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MUL8QW8X16_args, + 1, Iclass_AE_MUL8QW8X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MULA8QW8X16_args, + 1, Iclass_AE_MULA8QW8X16_stateArgs, 0, 0 }, + { 9, Iclass_AE_MUL4O8X8_args, + 1, Iclass_AE_MUL4O8X8_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULA4O8X8_args, + 1, Iclass_AE_MULA4O8X8_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O4X16_args, + 1, Iclass_AE_MUL4O4X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O4X16_args, + 1, Iclass_AE_MULA4O4X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MUL4O8X16_args, + 1, Iclass_AE_MUL4O8X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MULA4O8X16_args, + 1, Iclass_AE_MULA4O8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4QW8X16_args, + 1, Iclass_AE_MUL4QW8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4QW8X16_args, + 1, Iclass_AE_MULA4QW8X16_stateArgs, 0, 0 }, + { 5, Iclass_AE_MUL8Q8X8CNV_L_args, + 1, Iclass_AE_MUL8Q8X8CNV_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MUL8Q8X8CNV_H_args, + 1, Iclass_AE_MUL8Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULA8Q8X8CNV_L_args, + 1, Iclass_AE_MULA8Q8X8CNV_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULA8Q8X8CNV_H_args, + 1, Iclass_AE_MULA8Q8X8CNV_H_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL8Q8X16CNV_args, + 1, Iclass_AE_MUL8Q8X16CNV_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA8Q8X16CNV_args, + 1, Iclass_AE_MULA8Q8X16CNV_stateArgs, 0, 0 }, + { 5, Iclass_AE_MUL2X4Q8X8CNV_H_args, + 1, Iclass_AE_MUL2X4Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULA2X4Q8X8CNV_H_args, + 1, Iclass_AE_MULA2X4Q8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL2X4Q8X8CNV_L_args, + 1, Iclass_AE_MUL2X4Q8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA2X4Q8X8CNV_L_args, + 1, Iclass_AE_MULA2X4Q8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL2X4Q8X16CNV_args, + 1, Iclass_AE_MUL2X4Q8X16CNV_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA2X4Q8X16CNV_args, + 1, Iclass_AE_MULA2X4Q8X16CNV_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULQQ8X16CNV_args, + 1, Iclass_AE_MULQQ8X16CNV_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAQQ8X16CNV_args, + 1, Iclass_AE_MULAQQ8X16CNV_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL4O8X8CNV_H_args, + 1, Iclass_AE_MUL4O8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA4O8X8CNV_H_args, + 1, Iclass_AE_MULA4O8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL4O8X8CNV_L_args, + 1, Iclass_AE_MUL4O8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA4O8X8CNV_L_args, + 1, Iclass_AE_MULA4O8X8CNV_L_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O8X16CNV_H_args, + 1, Iclass_AE_MUL4O8X16CNV_H_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O8X16CNV_H_args, + 1, Iclass_AE_MULA4O8X16CNV_H_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O8X16CNV_L_args, + 1, Iclass_AE_MUL4O8X16CNV_L_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O8X16CNV_L_args, + 1, Iclass_AE_MULA4O8X16CNV_L_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL8Q4X16CNV_H_args, + 1, Iclass_AE_MUL8Q4X16CNV_H_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA8Q4X16CNV_H_args, + 1, Iclass_AE_MULA8Q4X16CNV_H_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL8Q4X16CNV_L_args, + 1, Iclass_AE_MUL8Q4X16CNV_L_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA8Q4X16CNV_L_args, + 1, Iclass_AE_MULA8Q4X16CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL2X4Q4X16CNV_H_args, + 1, Iclass_AE_MUL2X4Q4X16CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA2X4Q4X16CNV_H_args, + 1, Iclass_AE_MULA2X4Q4X16CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL2X4Q4X16CNV_L_args, + 1, Iclass_AE_MUL2X4Q4X16CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA2X4Q4X16CNV_L_args, + 1, Iclass_AE_MULA2X4Q4X16CNV_L_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULQQ4X16CNV_H_args, + 1, Iclass_AE_MULQQ4X16CNV_H_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAQQ4X16CNV_H_args, + 1, Iclass_AE_MULAQQ4X16CNV_H_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULQQ4X16CNV_L_args, + 1, Iclass_AE_MULQQ4X16CNV_L_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAQQ4X16CNV_L_args, + 1, Iclass_AE_MULAQQ4X16CNV_L_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O4X16CNV_HH_args, + 1, Iclass_AE_MUL4O4X16CNV_HH_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O4X16CNV_HL_args, + 1, Iclass_AE_MUL4O4X16CNV_HL_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O4X16CNV_LH_args, + 1, Iclass_AE_MUL4O4X16CNV_LH_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O4X16CNV_LL_args, + 1, Iclass_AE_MUL4O4X16CNV_LL_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O4X16CNV_HH_args, + 1, Iclass_AE_MULA4O4X16CNV_HH_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O4X16CNV_HL_args, + 1, Iclass_AE_MULA4O4X16CNV_HL_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O4X16CNV_LH_args, + 1, Iclass_AE_MULA4O4X16CNV_LH_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O4X16CNV_LL_args, + 1, Iclass_AE_MULA4O4X16CNV_LL_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUU8Q8X8_args, + 1, Iclass_AE_MULUU8Q8X8_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUU8Q8X8_args, + 1, Iclass_AE_MULAUU8Q8X8_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULUU4O8X8_args, + 1, Iclass_AE_MULUU4O8X8_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAUU4O8X8_args, + 1, Iclass_AE_MULAUU4O8X8_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULUU8Q8X8CNV_L_args, + 1, Iclass_AE_MULUU8Q8X8CNV_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAUU8Q8X8CNV_L_args, + 1, Iclass_AE_MULAUU8Q8X8CNV_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULUU8Q8X8CNV_H_args, + 1, Iclass_AE_MULUU8Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAUU8Q8X8CNV_H_args, + 1, Iclass_AE_MULAUU8Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULUU2X4Q8X8CNV_H_args, + 1, Iclass_AE_MULUU2X4Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAUU2X4Q8X8CNV_H_args, + 1, Iclass_AE_MULAUU2X4Q8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUU2X4Q8X8CNV_L_args, + 1, Iclass_AE_MULUU2X4Q8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUU2X4Q8X8CNV_L_args, + 1, Iclass_AE_MULAUU2X4Q8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUU4O8X8CNV_H_args, + 1, Iclass_AE_MULUU4O8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUU4O8X8CNV_H_args, + 1, Iclass_AE_MULAUU4O8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUU4O8X8CNV_L_args, + 1, Iclass_AE_MULUU4O8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUU4O8X8CNV_L_args, + 1, Iclass_AE_MULAUU4O8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUS8Q8X8_args, + 1, Iclass_AE_MULUS8Q8X8_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUS8Q8X8_args, + 1, Iclass_AE_MULAUS8Q8X8_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULUS8Q4X16_args, + 1, Iclass_AE_MULUS8Q4X16_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAUS8Q4X16_args, + 1, Iclass_AE_MULAUS8Q4X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULUS8Q8X16_args, + 1, Iclass_AE_MULUS8Q8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULAUS8Q8X16_args, + 1, Iclass_AE_MULAUS8Q8X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MULUS8QW8X16_args, + 1, Iclass_AE_MULUS8QW8X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MULAUS8QW8X16_args, + 1, Iclass_AE_MULAUS8QW8X16_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULUS4O8X8_args, + 1, Iclass_AE_MULUS4O8X8_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAUS4O8X8_args, + 1, Iclass_AE_MULAUS4O8X8_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULUS4O4X16_args, + 1, Iclass_AE_MULUS4O4X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULAUS4O4X16_args, + 1, Iclass_AE_MULAUS4O4X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MULUS4O8X16_args, + 1, Iclass_AE_MULUS4O8X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MULAUS4O8X16_args, + 1, Iclass_AE_MULAUS4O8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULUS4QW8X16_args, + 1, Iclass_AE_MULUS4QW8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULAUS4QW8X16_args, + 1, Iclass_AE_MULAUS4QW8X16_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULUS8Q8X8CNV_L_args, + 1, Iclass_AE_MULUS8Q8X8CNV_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAUS8Q8X8CNV_L_args, + 1, Iclass_AE_MULAUS8Q8X8CNV_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULUS8Q8X8CNV_H_args, + 1, Iclass_AE_MULUS8Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAUS8Q8X8CNV_H_args, + 1, Iclass_AE_MULAUS8Q8X8CNV_H_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULUS8Q8X16CNV_args, + 1, Iclass_AE_MULUS8Q8X16CNV_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAUS8Q8X16CNV_args, + 1, Iclass_AE_MULAUS8Q8X16CNV_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULUS2X4Q8X8CNV_H_args, + 1, Iclass_AE_MULUS2X4Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAUS2X4Q8X8CNV_H_args, + 1, Iclass_AE_MULAUS2X4Q8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUS2X4Q8X8CNV_L_args, + 1, Iclass_AE_MULUS2X4Q8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUS2X4Q8X8CNV_L_args, + 1, Iclass_AE_MULAUS2X4Q8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUS2X4Q8X16CNV_args, + 1, Iclass_AE_MULUS2X4Q8X16CNV_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUS2X4Q8X16CNV_args, + 1, Iclass_AE_MULAUS2X4Q8X16CNV_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULUSQQ8X16CNV_args, + 1, Iclass_AE_MULUSQQ8X16CNV_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAUSQQ8X16CNV_args, + 1, Iclass_AE_MULAUSQQ8X16CNV_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUS4O8X8CNV_H_args, + 1, Iclass_AE_MULUS4O8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUS4O8X8CNV_H_args, + 1, Iclass_AE_MULAUS4O8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUS4O8X8CNV_L_args, + 1, Iclass_AE_MULUS4O8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUS4O8X8CNV_L_args, + 1, Iclass_AE_MULAUS4O8X8CNV_L_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULUS4O8X16CNV_H_args, + 1, Iclass_AE_MULUS4O8X16CNV_H_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULAUS4O8X16CNV_H_args, + 1, Iclass_AE_MULAUS4O8X16CNV_H_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULUS4O8X16CNV_L_args, + 1, Iclass_AE_MULUS4O8X16CNV_L_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULAUS4O8X16CNV_L_args, + 1, Iclass_AE_MULAUS4O8X16CNV_L_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULUS8Q4X16CNV_H_args, + 1, Iclass_AE_MULUS8Q4X16CNV_H_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAUS8Q4X16CNV_H_args, + 1, Iclass_AE_MULAUS8Q4X16CNV_H_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULUS8Q4X16CNV_L_args, + 1, Iclass_AE_MULUS8Q4X16CNV_L_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAUS8Q4X16CNV_L_args, + 1, Iclass_AE_MULAUS8Q4X16CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUS2X4Q4X16CNV_H_args, + 1, Iclass_AE_MULUS2X4Q4X16CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUS2X4Q4X16CNV_H_args, + 1, Iclass_AE_MULAUS2X4Q4X16CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUS2X4Q4X16CNV_L_args, + 1, Iclass_AE_MULUS2X4Q4X16CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUS2X4Q4X16CNV_L_args, + 1, Iclass_AE_MULAUS2X4Q4X16CNV_L_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULUSQQ4X16CNV_H_args, + 1, Iclass_AE_MULUSQQ4X16CNV_H_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAUSQQ4X16CNV_H_args, + 1, Iclass_AE_MULAUSQQ4X16CNV_H_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULUSQQ4X16CNV_L_args, + 1, Iclass_AE_MULUSQQ4X16CNV_L_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAUSQQ4X16CNV_L_args, + 1, Iclass_AE_MULAUSQQ4X16CNV_L_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULUS4O4X16CNV_HH_args, + 1, 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}, + { 2, Iclass_FITRUNC_S_args, + 2, Iclass_FITRUNC_S_stateArgs, 0, 0 }, + { 3, Iclass_FLOAT_S_args, + 3, Iclass_FLOAT_S_stateArgs, 0, 0 }, + { 3, Iclass_UFLOAT_S_args, + 3, Iclass_UFLOAT_S_stateArgs, 0, 0 }, + { 3, Iclass_FLOAT_SX2_args, + 3, Iclass_FLOAT_SX2_stateArgs, 0, 0 }, + { 3, Iclass_UFLOAT_SX2_args, + 3, Iclass_UFLOAT_SX2_stateArgs, 0, 0 }, + { 2, Iclass_ABS_S_args, + 1, Iclass_ABS_S_stateArgs, 0, 0 }, + { 2, Iclass_NEG_S_args, + 1, Iclass_NEG_S_stateArgs, 0, 0 }, + { 2, Iclass_CONJC_S_args, + 1, Iclass_CONJC_S_stateArgs, 0, 0 }, + { 2, Iclass_MULJC_S_args, + 1, Iclass_MULJC_S_stateArgs, 0, 0 }, + { 2, Iclass_CONST_S_args, + 1, Iclass_CONST_S_stateArgs, 0, 0 }, + { 2, Iclass_CLSFY_S_args, + 1, Iclass_CLSFY_S_stateArgs, 0, 0 }, + { 3, Iclass_MINNUM_S_args, + 2, Iclass_MINNUM_S_stateArgs, 0, 0 }, + { 3, Iclass_MAXNUM_S_args, + 2, Iclass_MAXNUM_S_stateArgs, 0, 0 }, + { 4, Iclass_ADDANDSUB_S_args, + 5, Iclass_ADDANDSUB_S_stateArgs, 0, 0 }, + { 4, Iclass_ADDANDSUBJC_S_args, + 5, Iclass_ADDANDSUBJC_S_stateArgs, 0, 0 }, + { 3, Iclass_ADD_HL_LH_S_args, + 5, Iclass_ADD_HL_LH_S_stateArgs, 0, 0 }, + { 4, Iclass_MADDA_S_args, + 6, Iclass_MADDA_S_stateArgs, 0, 0 }, + { 3, Iclass_FREXP_S_args, + 1, Iclass_FREXP_S_stateArgs, 0, 0 }, + { 2, Iclass_FLOATEXP_S_args, + 1, Iclass_FLOATEXP_S_stateArgs, 0, 0 }, + { 3, Iclass_MINNUMABS_S_args, + 2, Iclass_MINNUMABS_S_stateArgs, 0, 0 }, + { 3, Iclass_MAXNUMABS_S_args, + 2, Iclass_MAXNUMABS_S_stateArgs, 0, 0 }, + { 5, Iclass_MULQ_S_args, + 6, Iclass_MULQ_S_stateArgs, 0, 0 }, + { 5, Iclass_MADDQ_S_args, + 6, Iclass_MADDQ_S_stateArgs, 0, 0 }, + { 5, Iclass_MSUBQ_S_args, + 6, Iclass_MSUBQ_S_stateArgs, 0, 0 }, + { 6, Iclass_MULMUXQ_S_args, + 6, Iclass_MULMUXQ_S_stateArgs, 0, 0 }, + { 6, Iclass_MADDMUXQ_S_args, + 6, Iclass_MADDMUXQ_S_stateArgs, 0, 0 }, + { 4, Iclass_BMAXNUM_S_args, + 2, Iclass_BMAXNUM_S_stateArgs, 0, 0 }, + { 4, Iclass_BMINNUM_S_args, + 2, Iclass_BMINNUM_S_stateArgs, 0, 0 }, + { 4, Iclass_BMAXNUMABS_S_args, + 2, Iclass_BMAXNUMABS_S_stateArgs, 0, 0 }, + { 4, Iclass_BMINNUMABS_S_args, + 2, Iclass_BMINNUMABS_S_stateArgs, 0, 0 }, + { 4, Iclass_ABS_SX2X2_args, + 1, Iclass_ABS_SX2X2_stateArgs, 0, 0 }, + { 4, Iclass_NEG_SX2X2_args, + 1, Iclass_NEG_SX2X2_stateArgs, 0, 0 }, + { 4, Iclass_CONJC_SX2X2_args, + 1, Iclass_CONJC_SX2X2_stateArgs, 0, 0 }, + { 4, Iclass_MULJC_SX2X2_args, + 1, Iclass_MULJC_SX2X2_stateArgs, 0, 0 }, + { 3, Iclass_CONST_SX2X2_args, + 1, Iclass_CONST_SX2X2_stateArgs, 0, 0 }, + { 6, Iclass_ADD_SX2X2_args, + 5, Iclass_ADD_SX2X2_stateArgs, 0, 0 }, + { 6, Iclass_SUB_SX2X2_args, + 5, Iclass_SUB_SX2X2_stateArgs, 0, 0 }, + { 6, Iclass_MUL_SX2X2_args, + 6, Iclass_MUL_SX2X2_stateArgs, 0, 0 }, + { 6, Iclass_MADD_SX2X2_args, + 6, Iclass_MADD_SX2X2_stateArgs, 0, 0 }, + { 6, Iclass_MSUB_SX2X2_args, + 6, Iclass_MSUB_SX2X2_stateArgs, 0, 0 }, + { 7, Iclass_MULMUX_SX2X2_args, + 6, Iclass_MULMUX_SX2X2_stateArgs, 0, 0 }, + { 7, Iclass_MADDMUX_SX2X2_args, + 6, Iclass_MADDMUX_SX2X2_stateArgs, 0, 0 }, + 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Iclass_UEQ_H_args, + 2, Iclass_UEQ_H_stateArgs, 0, 0 }, + { 3, Iclass_ULE_H_args, + 2, Iclass_ULE_H_stateArgs, 0, 0 }, + { 3, Iclass_ULT_H_args, + 2, Iclass_ULT_H_stateArgs, 0, 0 }, + { 3, Iclass_UN_H_args, + 2, Iclass_UN_H_stateArgs, 0, 0 }, + { 2, Iclass_DIV0_H_args, + 1, Iclass_DIV0_H_stateArgs, 0, 0 }, + { 2, Iclass_FICEIL_H_args, + 2, Iclass_FICEIL_H_stateArgs, 0, 0 }, + { 2, Iclass_FIFLOOR_H_args, + 2, Iclass_FIFLOOR_H_stateArgs, 0, 0 }, + { 2, Iclass_FIRINT_H_args, + 4, Iclass_FIRINT_H_stateArgs, 0, 0 }, + { 2, Iclass_FIROUND_H_args, + 2, Iclass_FIROUND_H_stateArgs, 0, 0 }, + { 2, Iclass_FITRUNC_H_args, + 2, Iclass_FITRUNC_H_stateArgs, 0, 0 }, + { 2, Iclass_MKDADJ_H_args, + 3, Iclass_MKDADJ_H_stateArgs, 0, 0 }, + { 2, Iclass_MKSADJ_H_args, + 2, Iclass_MKSADJ_H_stateArgs, 0, 0 }, + { 2, Iclass_NEXP0_H_args, + 1, Iclass_NEXP0_H_stateArgs, 0, 0 }, + { 2, Iclass_NEXP01_H_args, + 1, Iclass_NEXP01_H_stateArgs, 0, 0 }, + { 2, Iclass_RECIP0_H_args, + 3, Iclass_RECIP0_H_stateArgs, 0, 0 }, + { 2, Iclass_RSQRT0_H_args, + 3, Iclass_RSQRT0_H_stateArgs, 0, 0 }, + { 2, Iclass_SQRT0_H_args, + 1, Iclass_SQRT0_H_stateArgs, 0, 0 }, + { 3, Iclass_FLOAT16_H_args, + 3, Iclass_FLOAT16_H_stateArgs, 0, 0 }, + { 3, Iclass_UFLOAT16_H_args, + 4, Iclass_UFLOAT16_H_stateArgs, 0, 0 }, + { 3, Iclass_TRUNC16_H_args, + 3, Iclass_TRUNC16_H_stateArgs, 0, 0 }, + { 3, Iclass_UTRUNC16_H_args, + 3, Iclass_UTRUNC16_H_stateArgs, 0, 0 }, + { 3, Iclass_FLOAT16_HX4_args, + 3, Iclass_FLOAT16_HX4_stateArgs, 0, 0 }, + { 3, Iclass_UFLOAT16_HX4_args, + 4, Iclass_UFLOAT16_HX4_stateArgs, 0, 0 }, + { 3, Iclass_TRUNC16_HX4_args, + 3, Iclass_TRUNC16_HX4_stateArgs, 0, 0 }, + { 3, Iclass_UTRUNC16_HX4_args, + 3, Iclass_UTRUNC16_HX4_stateArgs, 0, 0 }, + { 3, Iclass_ADD_H_args, + 5, Iclass_ADD_H_stateArgs, 0, 0 }, + { 3, Iclass_SUB_H_args, + 5, Iclass_SUB_H_stateArgs, 0, 0 }, + { 3, Iclass_MUL_H_args, + 6, Iclass_MUL_H_stateArgs, 0, 0 }, + { 3, Iclass_MADD_H_args, + 6, Iclass_MADD_H_stateArgs, 0, 0 }, + { 3, Iclass_MSUB_H_args, + 6, Iclass_MSUB_H_stateArgs, 0, 0 }, + { 3, Iclass_MADDN_H_args, + 1, Iclass_MADDN_H_stateArgs, 0, 0 }, + { 3, Iclass_MSUBN_H_args, + 1, Iclass_MSUBN_H_stateArgs, 0, 0 }, + { 3, Iclass_DIVN_H_args, + 5, Iclass_DIVN_H_stateArgs, 0, 0 }, + { 2, Iclass_RMINNUM_H_args, + 2, Iclass_RMINNUM_H_stateArgs, 0, 0 }, + { 2, Iclass_RMAXNUM_H_args, + 2, Iclass_RMAXNUM_H_stateArgs, 0, 0 }, + { 4, Iclass_ABS_HX4X2_args, + 1, Iclass_ABS_HX4X2_stateArgs, 0, 0 }, + { 4, Iclass_NEG_HX4X2_args, + 1, Iclass_NEG_HX4X2_stateArgs, 0, 0 }, + { 4, Iclass_CONJC_HX4X2_args, + 1, Iclass_CONJC_HX4X2_stateArgs, 0, 0 }, + { 3, Iclass_CONST_HX4X2_args, + 1, Iclass_CONST_HX4X2_stateArgs, 0, 0 }, + { 4, Iclass_MULJC_HX4X2_args, + 1, Iclass_MULJC_HX4X2_stateArgs, 0, 0 }, + { 6, Iclass_ADD_HX4X2_args, + 5, Iclass_ADD_HX4X2_stateArgs, 0, 0 }, + { 6, Iclass_SUB_HX4X2_args, + 5, Iclass_SUB_HX4X2_stateArgs, 0, 0 }, + { 6, Iclass_MUL_HX4X2_args, + 6, Iclass_MUL_HX4X2_stateArgs, 0, 0 }, + { 6, Iclass_MADD_HX4X2_args, + 6, Iclass_MADD_HX4X2_stateArgs, 0, 0 }, + { 6, Iclass_MSUB_HX4X2_args, + 6, Iclass_MSUB_HX4X2_stateArgs, 0, 0 }, + { 5, Iclass_MULQ_H_args, + 6, Iclass_MULQ_H_stateArgs, 0, 0 }, + { 5, Iclass_MADDQ_H_args, + 6, Iclass_MADDQ_H_stateArgs, 0, 0 }, + { 5, Iclass_MULCNVH_HX4X2_args, + 6, Iclass_MULCNVH_HX4X2_stateArgs, 0, 0 }, + { 5, Iclass_MULACNVH_HX4X2_args, + 6, Iclass_MULACNVH_HX4X2_stateArgs, 0, 0 }, + { 5, Iclass_MULCNVL_HX4X2_args, + 6, Iclass_MULCNVL_HX4X2_stateArgs, 0, 0 }, + { 5, Iclass_MULACNVL_HX4X2_args, + 6, Iclass_MULACNVL_HX4X2_stateArgs, 0, 0 } +}; + +enum xtensa_iclass_id { + ICLASS_xt_iclass_excw, + ICLASS_xt_iclass_rfe, + ICLASS_xt_iclass_rfde, + ICLASS_xt_iclass_syscall, + ICLASS_xt_iclass_call12, + ICLASS_xt_iclass_call8, + ICLASS_xt_iclass_call4, + ICLASS_xt_iclass_callx12, + ICLASS_xt_iclass_callx8, + ICLASS_xt_iclass_callx4, + ICLASS_xt_iclass_entry, + ICLASS_xt_iclass_movsp, + ICLASS_xt_iclass_rotw, + ICLASS_xt_iclass_retw, + ICLASS_xt_iclass_rfwou, + ICLASS_xt_iclass_l32e, + ICLASS_xt_iclass_s32e, + ICLASS_xt_iclass_rsr_windowbase, + ICLASS_xt_iclass_wsr_windowbase, + ICLASS_xt_iclass_xsr_windowbase, + ICLASS_xt_iclass_rsr_windowstart, + ICLASS_xt_iclass_wsr_windowstart, + ICLASS_xt_iclass_xsr_windowstart, + ICLASS_xt_iclass_add_n, + ICLASS_xt_iclass_addi_n, + ICLASS_xt_iclass_bz6, + ICLASS_xt_iclass_ill_n, + ICLASS_xt_iclass_loadi4, + ICLASS_xt_iclass_mov_n, + ICLASS_xt_iclass_movi_n, + ICLASS_xt_iclass_nopn, + ICLASS_xt_iclass_retn, + ICLASS_xt_iclass_storei4, + ICLASS_rur_threadptr, + ICLASS_wur_threadptr, + ICLASS_xt_iclass_addi, + ICLASS_xt_iclass_addmi, + ICLASS_xt_iclass_addsub, + ICLASS_xt_iclass_bit, + ICLASS_xt_iclass_bsi8, + ICLASS_xt_iclass_bsi8b, + ICLASS_xt_iclass_bsi8u, + ICLASS_xt_iclass_bst8, + ICLASS_xt_iclass_bsz12, + ICLASS_xt_iclass_call0, + ICLASS_xt_iclass_callx0, + ICLASS_xt_iclass_exti, + ICLASS_xt_iclass_ill, + ICLASS_xt_iclass_jump, + ICLASS_xt_iclass_jumpx, + ICLASS_xt_iclass_l16ui, + ICLASS_xt_iclass_l16si, + ICLASS_xt_iclass_l32i, + ICLASS_xt_iclass_l32r, + ICLASS_xt_iclass_l8i, + ICLASS_xt_iclass_loop, + ICLASS_xt_iclass_loopz, + ICLASS_xt_iclass_movi, + ICLASS_xt_iclass_movz, + ICLASS_xt_iclass_neg, + ICLASS_xt_iclass_nop, + ICLASS_xt_iclass_l32ex, + ICLASS_xt_iclass_s32ex, + ICLASS_xt_iclass_getex, + ICLASS_xt_iclass_clrex, + ICLASS_xt_iclass_return, + ICLASS_xt_iclass_simcall, + ICLASS_xt_iclass_s16i, + ICLASS_xt_iclass_s32i, + ICLASS_xt_iclass_s32nb, + ICLASS_xt_iclass_s8i, + ICLASS_xt_iclass_sar, + ICLASS_xt_iclass_sari, + ICLASS_xt_iclass_shifts, + ICLASS_xt_iclass_shiftst, + ICLASS_xt_iclass_shiftt, + ICLASS_xt_iclass_slli, + ICLASS_xt_iclass_srai, + ICLASS_xt_iclass_srli, + ICLASS_xt_iclass_memw, + ICLASS_xt_iclass_extw, + ICLASS_xt_iclass_isync, + ICLASS_xt_iclass_sync, + ICLASS_xt_iclass_rsil, + ICLASS_xt_iclass_rsr_lend, + ICLASS_xt_iclass_wsr_lend, + ICLASS_xt_iclass_xsr_lend, + ICLASS_xt_iclass_rsr_lcount, + ICLASS_xt_iclass_wsr_lcount, + ICLASS_xt_iclass_xsr_lcount, + ICLASS_xt_iclass_rsr_lbeg, + ICLASS_xt_iclass_wsr_lbeg, + ICLASS_xt_iclass_xsr_lbeg, + ICLASS_xt_iclass_rsr_sar, + ICLASS_xt_iclass_wsr_sar, + ICLASS_xt_iclass_xsr_sar, + ICLASS_xt_iclass_rsr_memctl, + ICLASS_xt_iclass_wsr_memctl, + ICLASS_xt_iclass_xsr_memctl, + ICLASS_xt_iclass_rsr_configid0, + ICLASS_xt_iclass_wsr_configid0, + ICLASS_xt_iclass_rsr_configid1, + ICLASS_xt_iclass_rsr_ps, + ICLASS_xt_iclass_wsr_ps, + ICLASS_xt_iclass_xsr_ps, + ICLASS_xt_iclass_rsr_epc1, + ICLASS_xt_iclass_wsr_epc1, + ICLASS_xt_iclass_xsr_epc1, + ICLASS_xt_iclass_rsr_excsave1, + ICLASS_xt_iclass_wsr_excsave1, + ICLASS_xt_iclass_xsr_excsave1, + ICLASS_xt_iclass_rsr_epc2, + ICLASS_xt_iclass_wsr_epc2, + ICLASS_xt_iclass_xsr_epc2, + ICLASS_xt_iclass_rsr_excsave2, + ICLASS_xt_iclass_wsr_excsave2, + ICLASS_xt_iclass_xsr_excsave2, + ICLASS_xt_iclass_rsr_epc3, + ICLASS_xt_iclass_wsr_epc3, + ICLASS_xt_iclass_xsr_epc3, + ICLASS_xt_iclass_rsr_excsave3, + ICLASS_xt_iclass_wsr_excsave3, + ICLASS_xt_iclass_xsr_excsave3, + ICLASS_xt_iclass_rsr_epc4, + ICLASS_xt_iclass_wsr_epc4, + ICLASS_xt_iclass_xsr_epc4, + ICLASS_xt_iclass_rsr_excsave4, + ICLASS_xt_iclass_wsr_excsave4, + ICLASS_xt_iclass_xsr_excsave4, + ICLASS_xt_iclass_rsr_epc5, + ICLASS_xt_iclass_wsr_epc5, + ICLASS_xt_iclass_xsr_epc5, + ICLASS_xt_iclass_rsr_excsave5, + ICLASS_xt_iclass_wsr_excsave5, + ICLASS_xt_iclass_xsr_excsave5, + ICLASS_xt_iclass_rsr_epc6, + ICLASS_xt_iclass_wsr_epc6, + ICLASS_xt_iclass_xsr_epc6, + ICLASS_xt_iclass_rsr_excsave6, + ICLASS_xt_iclass_wsr_excsave6, + ICLASS_xt_iclass_xsr_excsave6, + ICLASS_xt_iclass_rsr_eps2, + ICLASS_xt_iclass_wsr_eps2, + ICLASS_xt_iclass_xsr_eps2, + ICLASS_xt_iclass_rsr_eps3, + ICLASS_xt_iclass_wsr_eps3, + ICLASS_xt_iclass_xsr_eps3, + ICLASS_xt_iclass_rsr_eps4, + ICLASS_xt_iclass_wsr_eps4, + ICLASS_xt_iclass_xsr_eps4, + ICLASS_xt_iclass_rsr_eps5, + ICLASS_xt_iclass_wsr_eps5, + ICLASS_xt_iclass_xsr_eps5, + ICLASS_xt_iclass_rsr_eps6, + ICLASS_xt_iclass_wsr_eps6, + ICLASS_xt_iclass_xsr_eps6, + ICLASS_xt_iclass_rsr_excvaddr, + ICLASS_xt_iclass_wsr_excvaddr, + ICLASS_xt_iclass_xsr_excvaddr, + ICLASS_xt_iclass_rsr_depc, + ICLASS_xt_iclass_wsr_depc, + ICLASS_xt_iclass_xsr_depc, + ICLASS_xt_iclass_rsr_exccause, + ICLASS_xt_iclass_wsr_exccause, + ICLASS_xt_iclass_xsr_exccause, + ICLASS_xt_iclass_rsr_misc0, + ICLASS_xt_iclass_wsr_misc0, + ICLASS_xt_iclass_xsr_misc0, + ICLASS_xt_iclass_rsr_misc1, + ICLASS_xt_iclass_wsr_misc1, + ICLASS_xt_iclass_xsr_misc1, + ICLASS_xt_iclass_rsr_misc2, + ICLASS_xt_iclass_wsr_misc2, + ICLASS_xt_iclass_xsr_misc2, + ICLASS_xt_iclass_rsr_misc3, + ICLASS_xt_iclass_wsr_misc3, + ICLASS_xt_iclass_xsr_misc3, + ICLASS_xt_iclass_rsr_prid, + ICLASS_xt_iclass_rsr_vecbase, + ICLASS_xt_iclass_wsr_vecbase, + ICLASS_xt_iclass_xsr_vecbase, + ICLASS_xt_iclass_rsr_mpucfg, + ICLASS_xt_iclass_wsr_mpucfg, + ICLASS_xt_iclass_salt, + ICLASS_xt_iclass_rsr_opmode, + ICLASS_xt_iclass_wsr_opmode, + ICLASS_xt_iclass_xsr_opmode, + ICLASS_xt_mul16, + ICLASS_xt_mul32, + ICLASS_xt_iclass_rfi, + ICLASS_xt_iclass_wait, + ICLASS_xt_iclass_rsr_interrupt, + ICLASS_xt_iclass_wsr_intset, + ICLASS_xt_iclass_wsr_intclear, + ICLASS_xt_iclass_rsr_intenable, + ICLASS_xt_iclass_wsr_intenable, + ICLASS_xt_iclass_xsr_intenable, + ICLASS_xt_iclass_break, + ICLASS_xt_iclass_break_n, + ICLASS_xt_iclass_rsr_dbreaka0, + ICLASS_xt_iclass_wsr_dbreaka0, + ICLASS_xt_iclass_xsr_dbreaka0, + ICLASS_xt_iclass_rsr_dbreakc0, + ICLASS_xt_iclass_wsr_dbreakc0, + ICLASS_xt_iclass_xsr_dbreakc0, + ICLASS_xt_iclass_rsr_dbreaka1, + ICLASS_xt_iclass_wsr_dbreaka1, + ICLASS_xt_iclass_xsr_dbreaka1, + ICLASS_xt_iclass_rsr_dbreakc1, + ICLASS_xt_iclass_wsr_dbreakc1, + ICLASS_xt_iclass_xsr_dbreakc1, + ICLASS_xt_iclass_rsr_ibreaka0, + ICLASS_xt_iclass_wsr_ibreaka0, + ICLASS_xt_iclass_xsr_ibreaka0, + ICLASS_xt_iclass_rsr_ibreaka1, + ICLASS_xt_iclass_wsr_ibreaka1, + ICLASS_xt_iclass_xsr_ibreaka1, + ICLASS_xt_iclass_rsr_ibreakenable, + ICLASS_xt_iclass_wsr_ibreakenable, + ICLASS_xt_iclass_xsr_ibreakenable, + ICLASS_xt_iclass_rsr_debugcause, + ICLASS_xt_iclass_wsr_debugcause, + ICLASS_xt_iclass_xsr_debugcause, + ICLASS_xt_iclass_rsr_icount, + ICLASS_xt_iclass_wsr_icount, + ICLASS_xt_iclass_xsr_icount, + ICLASS_xt_iclass_rsr_icountlevel, + ICLASS_xt_iclass_wsr_icountlevel, + ICLASS_xt_iclass_xsr_icountlevel, + ICLASS_xt_iclass_rsr_ddr, + ICLASS_xt_iclass_wsr_ddr, + ICLASS_xt_iclass_xsr_ddr, + ICLASS_xt_iclass_lddr32_p, + ICLASS_xt_iclass_sddr32_p, + ICLASS_xt_iclass_rfdo, + ICLASS_xt_iclass_rfdd, + ICLASS_xt_iclass_wsr_mmid, + ICLASS_xt_iclass_bbool1, + ICLASS_xt_iclass_bbool4, + ICLASS_xt_iclass_bbool8, + ICLASS_xt_iclass_bbranch, + ICLASS_xt_iclass_bmove, + ICLASS_xt_iclass_RSR_BR, + ICLASS_xt_iclass_WSR_BR, + ICLASS_xt_iclass_XSR_BR, + ICLASS_xt_iclass_rsr_ccount, + ICLASS_xt_iclass_wsr_ccount, + ICLASS_xt_iclass_xsr_ccount, + ICLASS_xt_iclass_rsr_ccompare0, + ICLASS_xt_iclass_wsr_ccompare0, + ICLASS_xt_iclass_xsr_ccompare0, + ICLASS_xt_iclass_rsr_ccompare1, + ICLASS_xt_iclass_wsr_ccompare1, + ICLASS_xt_iclass_xsr_ccompare1, + ICLASS_xt_iclass_rsr_ccompare2, + ICLASS_xt_iclass_wsr_ccompare2, + ICLASS_xt_iclass_xsr_ccompare2, + ICLASS_xt_iclass_icache, + ICLASS_xt_iclass_icache_lock, + ICLASS_xt_iclass_icache_inv, + ICLASS_xt_iclass_licx, + ICLASS_xt_iclass_sicx, + ICLASS_xt_iclass_dcache, + ICLASS_xt_iclass_dcache_dyn, + ICLASS_xt_iclass_dcache_ind, + ICLASS_xt_iclass_dcache_inv, + ICLASS_xt_iclass_dpf, + ICLASS_xt_iclass_dpfb, + ICLASS_xt_iclass_bpfnxt, + ICLASS_xt_iclass_dpdngrd, + ICLASS_xt_iclass_bpfctl, + ICLASS_xt_iclass_dcache_lock, + ICLASS_xt_iclass_sdct, + ICLASS_xt_iclass_ldct, + ICLASS_xt_iclass_sdcw, + ICLASS_xt_iclass_ldcw, + ICLASS_xt_iclass_rsr_prefctl, + ICLASS_xt_iclass_wsr_prefctl, + ICLASS_xt_iclass_xsr_prefctl, + ICLASS_xt_iclass_wsr_cacheadrdis, + ICLASS_xt_iclass_rsr_cacheadrdis, + ICLASS_xt_iclass_xsr_cacheadrdis, + ICLASS_xt_iclass_rptlb0, + ICLASS_xt_iclass_rptlb, + ICLASS_xt_iclass_wptlb, + ICLASS_xt_iclass_rsr_mpuenb, + ICLASS_xt_iclass_wsr_mpuenb, + ICLASS_xt_iclass_xsr_mpuenb, + ICLASS_xt_iclass_rsr_cpenable, + ICLASS_xt_iclass_wsr_cpenable, + ICLASS_xt_iclass_xsr_cpenable, + ICLASS_xt_iclass_clamp, + ICLASS_xt_iclass_minmax, + ICLASS_xt_iclass_nsa, + ICLASS_xt_iclass_sx, + ICLASS_xt_iclass_l32ai, + ICLASS_xt_iclass_s32ri, + ICLASS_xt_iclass_rsr_atomctl, + ICLASS_xt_iclass_wsr_atomctl, + ICLASS_xt_iclass_xsr_atomctl, + ICLASS_xt_iclass_div, + ICLASS_xt_iclass_rsr_eraccess, + ICLASS_xt_iclass_wsr_eraccess, + ICLASS_xt_iclass_xsr_eraccess, + ICLASS_xt_iclass_rer, + ICLASS_xt_iclass_wer, + ICLASS_xt_iclass_wb15_0, + ICLASS_xt_iclass_wb15_1, + ICLASS_xt_iclass_wb15_2, + ICLASS_xt_iclass_wb15_3, + ICLASS_xt_iclass_wb15_4, + ICLASS_rur_ae_ovf_sar, + ICLASS_wur_ae_ovf_sar, + ICLASS_rur_ae_bithead, + ICLASS_wur_ae_bithead, + ICLASS_rur_ae_ts_fts_bu_bp, + ICLASS_wur_ae_ts_fts_bu_bp, + ICLASS_rur_ae_cw_sd_no, + ICLASS_wur_ae_cw_sd_no, + ICLASS_rur_ae_cbegin0, + ICLASS_wur_ae_cbegin0, + ICLASS_rur_ae_cend0, + ICLASS_wur_ae_cend0, + ICLASS_rur_ae_cbegin1, + ICLASS_wur_ae_cbegin1, + ICLASS_rur_ae_cend1, + ICLASS_wur_ae_cend1, + ICLASS_rur_ae_cbegin2, + ICLASS_wur_ae_cbegin2, + ICLASS_rur_ae_cend2, + ICLASS_wur_ae_cend2, + ICLASS_ic_sext16, + ICLASS_ic_zext16, + ICLASS_ic_zext8, + ICLASS_ic_clamps16, + ICLASS_rur_fcr, + ICLASS_wur_fcr, + ICLASS_rur_fsr, + ICLASS_wur_fsr, + ICLASS_rur_expstate, + ICLASS_wur_expstate, + ICLASS_iclass_READ_IMPWIRE, + ICLASS_iclass_SETB_EXPSTATE, + ICLASS_iclass_CLRB_EXPSTATE, + ICLASS_iclass_WRMSK_EXPSTATE, + ICLASS_RUR_AE_OVERFLOW, + ICLASS_WUR_AE_OVERFLOW, + ICLASS_RUR_AE_SAR, + ICLASS_WUR_AE_SAR, + ICLASS_RUR_AE_BITPTR, + ICLASS_WUR_AE_BITPTR, + ICLASS_RUR_AE_BITSUSED, + ICLASS_WUR_AE_BITSUSED, + ICLASS_RUR_AE_TABLESIZE, + ICLASS_WUR_AE_TABLESIZE, + ICLASS_RUR_AE_FIRST_TS, + ICLASS_WUR_AE_FIRST_TS, + ICLASS_RUR_AE_NEXTOFFSET, + ICLASS_WUR_AE_NEXTOFFSET, + ICLASS_RUR_AE_SEARCHDONE, + ICLASS_WUR_AE_SEARCHDONE, + ICLASS_RUR_AE_CWRAP, + ICLASS_WUR_AE_CWRAP, + ICLASS_AE_L8X4F_I, + ICLASS_AE_L8X4F_IP, + ICLASS_AE_L8X4F_X, + ICLASS_AE_L8X4F_XP, + ICLASS_AE_L8X4S_I, + ICLASS_AE_L8X4S_IP, + ICLASS_AE_L8X4S_X, + ICLASS_AE_L8X4S_XP, + ICLASS_AE_L8X4U_I, + ICLASS_AE_L8X4U_IP, + ICLASS_AE_L8X4U_X, + ICLASS_AE_L8X4U_XP, + ICLASS_AE_L16M_XC, + ICLASS_AE_L16M_XC1, + ICLASS_AE_L16M_I, + ICLASS_AE_L16M_IU, + ICLASS_AE_L16M_X, + ICLASS_AE_L16M_XU, + ICLASS_AE_L16_XC, + ICLASS_AE_L16_XC1, + ICLASS_AE_L16_I, + ICLASS_AE_L16_IP, + ICLASS_AE_L16_X, + ICLASS_AE_L16_XP, + ICLASS_AE_L8_XC, + ICLASS_AE_L8_XC1, + ICLASS_AE_L8_I, + ICLASS_AE_L8_IP, + ICLASS_AE_L8_X, + ICLASS_AE_L8_XP, + ICLASS_AE_L32F24_XC, + ICLASS_AE_L32F24_XC1, + ICLASS_AE_L32F24_I, + ICLASS_AE_L32F24_IP, + ICLASS_AE_L32F24_X, + ICLASS_AE_L32F24_XP, + ICLASS_AE_L32_XC, + ICLASS_AE_L32_XC1, + ICLASS_AE_L32_I, + ICLASS_AE_L32_IP, + ICLASS_AE_L32_X, + ICLASS_AE_L32_XP, + ICLASS_AE_L32M_XC, + ICLASS_AE_L32M_I, + ICLASS_AE_L32M_IU, + ICLASS_AE_L32M_X, + ICLASS_AE_L32M_XU, + ICLASS_AE_L16X2M_XC, + ICLASS_AE_L16X2M_XC1, + ICLASS_AE_L16X2M_I, + ICLASS_AE_L16X2M_IU, + ICLASS_AE_L16X2M_X, + ICLASS_AE_L16X2M_XU, + ICLASS_AE_L32X2F24_XC, + ICLASS_AE_L32X2F24_XC1, + ICLASS_AE_L32X2F24_I, + ICLASS_AE_L32X2F24_IP, + ICLASS_AE_L32X2F24_RIP, + ICLASS_AE_L32X2F24_RI, + ICLASS_AE_L32X2F24_RIC, + ICLASS_AE_L32X2F24_RIC1, + ICLASS_AE_L32X2F24_X, + ICLASS_AE_L32X2F24_XP, + ICLASS_AE_L32X2_XC, + ICLASS_AE_L32X2_XC1, + ICLASS_AE_L32X2_I, + ICLASS_AE_L32X2_IP, + ICLASS_AE_L32X2_RIC, + ICLASS_AE_L32X2_RIC1, + ICLASS_AE_L32X2_X, + ICLASS_AE_L32X2_XP, + ICLASS_AE_L16X4_XC, + ICLASS_AE_L16X4_XC1, + ICLASS_AE_L16X4_I, + ICLASS_AE_L16X4_IP, + ICLASS_AE_L16X4_X, + ICLASS_AE_L16X4_XP, + ICLASS_AE_L8X8_XC, + ICLASS_AE_L8X8_XC1, + ICLASS_AE_L8X8_I, + ICLASS_AE_L8X8_IP, + ICLASS_AE_L8X8_X, + ICLASS_AE_L8X8_XP, + ICLASS_AE_L64_XC, + ICLASS_AE_L64_XC1, + ICLASS_AE_L64_I, + ICLASS_AE_L64_IP, + ICLASS_AE_L64_X, + ICLASS_AE_L64_XP, + ICLASS_AE_S16X2M_XC, + ICLASS_AE_S16X2M_XC1, + ICLASS_AE_S16X2M_I, + ICLASS_AE_S16X2M_IU, + ICLASS_AE_S16X2M_X, + ICLASS_AE_S16X2M_XU, + ICLASS_AE_S32X2F24_XC, + ICLASS_AE_S32X2F24_XC1, + ICLASS_AE_S32X2F24_I, + ICLASS_AE_S32X2F24_IP, + ICLASS_AE_S32X2F24_RIP, + ICLASS_AE_S32X2F24_RIC, + ICLASS_AE_S32X2F24_RIC1, + ICLASS_AE_S32X2F24_X, + ICLASS_AE_S32X2F24_XP, + ICLASS_AE_S32X2_XC, + ICLASS_AE_S32X2_XC1, + ICLASS_AE_S32X2_I, + ICLASS_AE_S32X2_IP, + ICLASS_AE_S32X2_RIC, + ICLASS_AE_S32X2_RIC1, + ICLASS_AE_S32X2_X, + ICLASS_AE_S32X2_XP, + ICLASS_AE_S32X2RNG_I, + ICLASS_AE_S32X2RNG_IP, + ICLASS_AE_S32X2RNG_X, + ICLASS_AE_S32X2RNG_XP, + ICLASS_AE_S16X4_XC, + ICLASS_AE_S16X4_XC1, + ICLASS_AE_S16X4_I, + ICLASS_AE_S16X4_IP, + ICLASS_AE_S16X4_X, + ICLASS_AE_S16X4_XP, + ICLASS_AE_S8X8_XC, + ICLASS_AE_S8X8_XC1, + ICLASS_AE_S8X8_I, + ICLASS_AE_S8X8_IP, + ICLASS_AE_S8X8_X, + ICLASS_AE_S8X8_XP, + ICLASS_AE_S16M_L_XC, + ICLASS_AE_S16M_L_XC1, + ICLASS_AE_S16M_L_I, + ICLASS_AE_S16M_L_IU, + ICLASS_AE_S16M_L_X, + ICLASS_AE_S16M_L_XU, + ICLASS_AE_S32F24_L_XC, + ICLASS_AE_S32F24_L_XC1, + ICLASS_AE_S32F24_L_I, + ICLASS_AE_S32F24_L_IP, + ICLASS_AE_S32F24_L_X, + ICLASS_AE_S32F24_L_XP, + ICLASS_AE_S32_L_XC, + ICLASS_AE_S32_L_XC1, + ICLASS_AE_S32_L_I, + ICLASS_AE_S32_L_IP, + ICLASS_AE_S32_L_X, + ICLASS_AE_S32_L_XP, + ICLASS_AE_S32_H_XC, + ICLASS_AE_S32_H_XC1, + ICLASS_AE_S32_H_I, + ICLASS_AE_S32_H_IP, + ICLASS_AE_S32_H_X, + ICLASS_AE_S32_H_XP, + ICLASS_AE_S16_0_XC, + ICLASS_AE_S16_0_XC1, + ICLASS_AE_S16_0_I, + ICLASS_AE_S16_0_IP, + ICLASS_AE_S16_0_X, + ICLASS_AE_S16_0_XP, + ICLASS_AE_S8_0_XC, + ICLASS_AE_S8_0_XC1, + ICLASS_AE_S8_0_I, + ICLASS_AE_S8_0_IP, + ICLASS_AE_S8_0_X, + ICLASS_AE_S8_0_XP, + ICLASS_AE_S64_XC, + ICLASS_AE_S64_XC1, + ICLASS_AE_S64_I, + ICLASS_AE_S64_IP, + ICLASS_AE_S64_X, + ICLASS_AE_S64_XP, + ICLASS_AE_S32M_XC, + ICLASS_AE_S32M_I, + ICLASS_AE_S32M_IU, + ICLASS_AE_S32M_X, + ICLASS_AE_S32M_XU, + ICLASS_AE_L32X2_XC2, + ICLASS_AE_L16X4_XC2, + ICLASS_AE_L8X8_XC2, + ICLASS_AE_L64_XC2, + ICLASS_AE_S32X2_XC2, + ICLASS_AE_S16X4_XC2, + ICLASS_AE_S8X8_XC2, + ICLASS_AE_S64_XC2, + ICLASS_AE_S16X4RNG_I, + ICLASS_AE_S16X4RNG_IP, + ICLASS_AE_S16X4RNG_X, + ICLASS_AE_S16X4RNG_XP, + ICLASS_AE_L32X2X2_XC, + ICLASS_AE_L32X2X2_XC1, + ICLASS_AE_L32X2X2_I, + ICLASS_AE_L32X2X2_IP, + ICLASS_AE_L32X2X2_X, + ICLASS_AE_L32X2X2_XP, + ICLASS_AE_L16X4X2_XC, + ICLASS_AE_L16X4X2_XC1, + ICLASS_AE_L16X4X2_I, + ICLASS_AE_L16X4X2_IP, + ICLASS_AE_L16X4X2_X, + ICLASS_AE_L16X4X2_XP, + ICLASS_AE_L8X8X2_XC, + ICLASS_AE_L8X8X2_XC1, + ICLASS_AE_L8X8X2_I, + ICLASS_AE_L8X8X2_IP, + ICLASS_AE_L8X8X2_X, + ICLASS_AE_L8X8X2_XP, + ICLASS_AE_L64X2_XC, + ICLASS_AE_L64X2_XC1, + ICLASS_AE_L64X2_I, + ICLASS_AE_L64X2_IP, + ICLASS_AE_L64X2_X, + ICLASS_AE_L64X2_XP, + ICLASS_AE_S32X2X2_XC, + ICLASS_AE_S32X2X2_XC1, + ICLASS_AE_S32X2X2_I, + ICLASS_AE_S32X2X2_IP, + ICLASS_AE_S32X2X2_X, + ICLASS_AE_S32X2X2_XP, + ICLASS_AE_S32X2X2RNG_I, + ICLASS_AE_S32X2X2RNG_IP, + ICLASS_AE_S32X2X2RNG_X, + ICLASS_AE_S32X2X2RNG_XP, + ICLASS_AE_S16X4X2_XC, + ICLASS_AE_S16X4X2_XC1, + ICLASS_AE_S16X4X2_I, + ICLASS_AE_S16X4X2_IP, + ICLASS_AE_S16X4X2_X, + ICLASS_AE_S16X4X2_XP, + ICLASS_AE_S8X8X2_XC, + ICLASS_AE_S8X8X2_XC1, + ICLASS_AE_S8X8X2_I, + ICLASS_AE_S8X8X2_IP, + ICLASS_AE_S8X8X2_X, + ICLASS_AE_S8X8X2_XP, + ICLASS_AE_S64X2_XC, + ICLASS_AE_S64X2_XC1, + ICLASS_AE_S64X2_I, + ICLASS_AE_S64X2_IP, + ICLASS_AE_S64X2_X, + ICLASS_AE_S64X2_XP, + ICLASS_AE_L32X2X2_XC2, + ICLASS_AE_L16X4X2_XC2, + ICLASS_AE_L8X8X2_XC2, + ICLASS_AE_L64X2_XC2, + ICLASS_AE_S32X2X2_XC2, + ICLASS_AE_S16X4X2_XC2, + ICLASS_AE_S8X8X2_XC2, + ICLASS_AE_S64X2_XC2, + ICLASS_AE_S16X4X2RNG_I, + ICLASS_AE_S16X4X2RNG_IP, + ICLASS_AE_S16X4X2RNG_X, + ICLASS_AE_S16X4X2RNG_XP, + ICLASS_AE_ZALIGN64, + ICLASS_AE_LALIGN64_I, + ICLASS_AE_SALIGN64_I, + ICLASS_AE_MOVALIGN, + ICLASS_AE_LA64_PP, + ICLASS_AE_LA24POS_PC, + ICLASS_AE_LA24NEG_PC, + ICLASS_AE_LA24POS_PC1, + ICLASS_AE_LA24NEG_PC1, + ICLASS_AE_LA24X2POS_PC, + ICLASS_AE_LA24X2NEG_PC, + ICLASS_AE_LA24X2POS_PC1, + ICLASS_AE_LA24X2NEG_PC1, + ICLASS_AE_LA32X2POS_PC, + ICLASS_AE_LA32X2NEG_PC, + ICLASS_AE_LA32X2POS_PC1, + ICLASS_AE_LA32X2NEG_PC1, + ICLASS_AE_LA32X2POS_PC2, + ICLASS_AE_LA16X4POS_PC, + ICLASS_AE_LA16X4NEG_PC, + ICLASS_AE_LA16X4POS_PC1, + ICLASS_AE_LA16X4NEG_PC1, + ICLASS_AE_LA16X4POS_PC2, + ICLASS_AE_LA8X8POS_PC, + ICLASS_AE_LA8X8NEG_PC, + ICLASS_AE_LA8X8POS_PC1, + ICLASS_AE_LA8X8NEG_PC1, + ICLASS_AE_LA8X8POS_PC2, + ICLASS_AE_LA32X2X2POS_PC, + ICLASS_AE_LA32X2X2POS_PC1, + ICLASS_AE_LA32X2X2POS_PC2, + ICLASS_AE_LA16X4X2POS_PC, + ICLASS_AE_LA16X4X2POS_PC1, + ICLASS_AE_LA16X4X2POS_PC2, + ICLASS_AE_LA8X8X2POS_PC, + ICLASS_AE_LA8X8X2POS_PC1, + ICLASS_AE_LA8X8X2POS_PC2, + ICLASS_AE_SA64POS_FP, + ICLASS_AE_SA64NEG_FP, + ICLASS_AE_LA32X2_IC, + ICLASS_AE_LA32X2_IC1, + ICLASS_AE_LA32X2_IC2, + ICLASS_AE_LA32X2_IP, + ICLASS_AE_LA32X2_RIP, + ICLASS_AE_LA32X2_RIC, + ICLASS_AE_LA32X2_RIC1, + ICLASS_AE_LA16X4_IC, + ICLASS_AE_LA16X4_IC1, + ICLASS_AE_LA16X4_IC2, + ICLASS_AE_LA16X4_IP, + ICLASS_AE_LA16X4_RIP, + ICLASS_AE_LA16X4_RIC, + ICLASS_AE_LA16X4_RIC1, + ICLASS_AE_LA8X8_IC, + ICLASS_AE_LA8X8_IC1, + ICLASS_AE_LA8X8_IC2, + ICLASS_AE_LA8X8_IP, + ICLASS_AE_LA8X8_RIP, + ICLASS_AE_LA8X8_RIC, + ICLASS_AE_LA8X8_RIC1, + ICLASS_AE_LA32X2F24_IC, + ICLASS_AE_LA32X2F24_IC1, + ICLASS_AE_LA32X2F24_IP, + ICLASS_AE_LA32X2F24_RIP, + ICLASS_AE_LA32X2F24_RIC, + ICLASS_AE_LA32X2F24_RIC1, + ICLASS_AE_LA24_IC, + ICLASS_AE_LA24_IC1, + ICLASS_AE_LA24_IP, + ICLASS_AE_LA24_RIP, + ICLASS_AE_LA24_RIC, + ICLASS_AE_LA24_RIC1, + ICLASS_AE_LA24X2_IC, + ICLASS_AE_LA24X2_IC1, + ICLASS_AE_LA24X2_IP, + ICLASS_AE_LA24X2_RIP, + ICLASS_AE_LA24X2_RIC, + ICLASS_AE_LA24X2_RIC1, + ICLASS_AE_SA32X2_IC, + ICLASS_AE_SA32X2_IC1, + ICLASS_AE_SA32X2_IC2, + ICLASS_AE_SA32X2_IP, + ICLASS_AE_SA32X2_RIP, + ICLASS_AE_SA32X2_RIC, + ICLASS_AE_SA32X2_RIC1, + ICLASS_AE_SA16X4_IC, + ICLASS_AE_SA16X4_IC1, + ICLASS_AE_SA16X4_IC2, + ICLASS_AE_SA16X4_IP, + ICLASS_AE_SA16X4_RIP, + ICLASS_AE_SA16X4_RIC, + ICLASS_AE_SA16X4_RIC1, + ICLASS_AE_SA8X8_IC, + ICLASS_AE_SA8X8_IC1, + ICLASS_AE_SA8X8_IC2, + ICLASS_AE_SA8X8_IP, + ICLASS_AE_SA8X8_RIP, + ICLASS_AE_SA8X8_RIC, + ICLASS_AE_SA8X8_RIC1, + ICLASS_AE_SA32X2F24_IC, + ICLASS_AE_SA32X2F24_IC1, + ICLASS_AE_SA32X2F24_IP, + ICLASS_AE_SA32X2F24_RIP, + ICLASS_AE_SA32X2F24_RIC, + ICLASS_AE_SA32X2F24_RIC1, + ICLASS_AE_SA24_L_IC, + ICLASS_AE_SA24_L_IC1, + ICLASS_AE_SA24_L_IP, + ICLASS_AE_SA24_L_RIP, + ICLASS_AE_SA24_L_RIC, + ICLASS_AE_SA24_L_RIC1, + ICLASS_AE_SA24X2_IC, + ICLASS_AE_SA24X2_IC1, + ICLASS_AE_SA24X2_IP, + ICLASS_AE_SA24X2_RIP, + ICLASS_AE_SA24X2_RIC, + ICLASS_AE_SA24X2_RIC1, + ICLASS_AE_ADDICIRC, + ICLASS_AE_ADDCIRC_XC2, + ICLASS_AE_ADDCIRC_XC1, + ICLASS_AE_ADDCIRC_XC, + ICLASS_AE_S32RA64S_I, + ICLASS_AE_S32RA64S_IP, + ICLASS_AE_S32RA64S_X, + ICLASS_AE_S32RA64S_XP, + ICLASS_AE_S32RA64S_XC, + ICLASS_AE_S32RA64S_XC1, + ICLASS_AE_S24RA64S_I, + ICLASS_AE_S24RA64S_IP, + ICLASS_AE_S24RA64S_X, + ICLASS_AE_S24RA64S_XP, + ICLASS_AE_S24RA64S_XC, + ICLASS_AE_S24RA64S_XC1, + ICLASS_AE_S32X2RA64S_IP, + ICLASS_AE_S24X2RA64S_IP, + ICLASS_AE_S16X4RA32S_IP, + ICLASS_AE_ADDBRBA32, + ICLASS_AE_S32X2_L_IP, + ICLASS_AE_BITSWAP, + ICLASS_AE_MUL32JS, + ICLASS_AE_ADDANDSUB32S, + ICLASS_AE_ADDANDSUB32JS, + ICLASS_AE_ADDANDSUBRNG32, + ICLASS_AE_ADDANDSUBRNG32_H, + ICLASS_AE_ADDANDSUBRNG32_L, + ICLASS_AE_ADDRNG32, + ICLASS_AE_SUBRNG32, + ICLASS_AE_RNG32X2, + ICLASS_AE_SEL16I, + ICLASS_AE_SEL16I_N, + ICLASS_AE_SHORTSWAP, + ICLASS_AE_MOVAB4, + ICLASS_AE_MOVAB2, + ICLASS_AE_MOVAB, + ICLASS_AE_MOVBA, + ICLASS_AE_MOVBA1X2, + ICLASS_AE_MOVBA4, + ICLASS_AE_MOVBA2, + ICLASS_AE_MOVB2, + ICLASS_AE_MOVB4, + ICLASS_AE_MOVT16X4, + ICLASS_AE_MOVF16X4, + ICLASS_AE_MOVT32X2, + ICLASS_AE_MOVF32X2, + ICLASS_AE_MOVSARA7X2, + ICLASS_AE_MOVSARD7, + ICLASS_AE_MOVASAR, + ICLASS_AE_MOVDA32X2, + ICLASS_AE_MOVDA32, + ICLASS_AE_MOVDA16X2, + ICLASS_AE_MOVDA16, + ICLASS_AE_MOVI, + ICLASS_AE_TRUNCP24A32X2, + ICLASS_AE_SAT16X4, + ICLASS_AE_CVT32X2F16_32, + ICLASS_AE_CVT32X2F16_10, + ICLASS_AE_SEXT32X2D16_32, + ICLASS_AE_SEXT32X2D16_10, + ICLASS_AE_CVTA32F24S_L, + ICLASS_AE_CVTA32F24S_H, + ICLASS_AE_CVTP24A16X2_LL, + ICLASS_AE_CVTP24A16X2_LH, + ICLASS_AE_CVTP24A16X2_HL, + ICLASS_AE_CVTP24A16X2_HH, + ICLASS_AE_TRUNCP24Q48X2, + ICLASS_AE_TRUNCA32X2F64S, + ICLASS_AE_TRUNCI32X2F64S, + ICLASS_AE_TRUNCA32F64S_L, + ICLASS_AE_TRUNCI32F64S_L, + ICLASS_AE_TRUNCP16, + ICLASS_AE_ROUND32X2F64SSYM, + ICLASS_AE_ROUND32X2F64SASYM, + ICLASS_AE_ROUND32X2F48SSYM, + ICLASS_AE_ROUND32X2F48SASYM, + ICLASS_AE_ROUND16X4F32SSYM, + ICLASS_AE_ROUND16X4F32SASYM, + ICLASS_AE_ROUND24X2F48SSYM, + ICLASS_AE_ROUND24X2F48SASYM, + ICLASS_AE_ROUNDSP16Q48X2SYM, + ICLASS_AE_ROUNDSP16Q48X2ASYM, + ICLASS_AE_MINABS32S, + ICLASS_AE_MAXABS32S, + ICLASS_AE_ROUNDSP16F24SYM, + ICLASS_AE_ROUNDSP16F24ASYM, + ICLASS_AE_MOV, + ICLASS_AE_MOVT64, + ICLASS_AE_MOVF64, + ICLASS_AE_CVTQ56A32S, + ICLASS_AE_CVT48A32, + ICLASS_AE_CVT64A32, + ICLASS_AE_CVTQ56P32S_L, + ICLASS_AE_CVTQ56P32S_H, + ICLASS_AE_CVT64F32_H, + ICLASS_AE_CVT48F32_L, + ICLASS_AE_CVT48F32_H, + ICLASS_AE_SAT48S, + ICLASS_AE_SATQ56S, + ICLASS_AE_SAT24S, + ICLASS_AE_TRUNCQ32, + ICLASS_AE_MINABS64S, + ICLASS_AE_MAXABS64S, + ICLASS_AE_ROUNDSQ32F48SYM, + ICLASS_AE_ROUNDSQ32F48ASYM, + ICLASS_AE_TRUNCA32Q48, + ICLASS_AE_MOVAD32_L, + ICLASS_AE_MOVAD32_H, + ICLASS_AE_MOVAD16_3, + ICLASS_AE_MOVAD16_2, + ICLASS_AE_MOVAD16_1, + ICLASS_AE_MOVAD16_0, + ICLASS_AE_SRA64_32, + ICLASS_AE_PKSR32, + ICLASS_AE_PKSR24, + ICLASS_AE_PKSRF32, + ICLASS_AE_PKSR16, + ICLASS_AE_TRUNCA16P24S_L, + ICLASS_AE_TRUNCA16P24S_H, + ICLASS_AE_ADD32, + ICLASS_AE_SUB32, + ICLASS_AE_ADDSUB32, + ICLASS_AE_SUBADD32, + ICLASS_AE_ADD16, + ICLASS_AE_SUB16, + ICLASS_AE_ADD32_HL_LH, + ICLASS_AE_ADDSUB32_HL_LH, + ICLASS_AE_NEG32, + ICLASS_AE_ABS32, + ICLASS_AE_NEG32_L, + ICLASS_AE_ADD24S, + ICLASS_AE_SUB24S, + ICLASS_AE_ADD32S, + ICLASS_AE_SUB32S, + ICLASS_AE_ADDSUB32S, + ICLASS_AE_SUBADD32S, + ICLASS_AE_ADD16S, + ICLASS_AE_SUB16S, + ICLASS_AE_ADD32S_HL_LH, + ICLASS_AE_ADDSUB32S_HL_LH, + ICLASS_AE_NEG24S, + ICLASS_AE_ABS24S, + ICLASS_AE_NEG32S, + ICLASS_AE_ABS32S, + ICLASS_AE_NEG16S, + ICLASS_AE_ABS16S, + ICLASS_AE_ABS16, + ICLASS_AE_MULC16JS_H, + ICLASS_AE_MULC16JS_L, + ICLASS_AE_MULAC16JS_H, + ICLASS_AE_MULAC16JS_L, + ICLASS_AE_LT16, + ICLASS_AE_LE16, + ICLASS_AE_EQ16, + ICLASS_AE_LT32, + ICLASS_AE_LE32, + ICLASS_AE_EQ32, + ICLASS_AE_MIN32, + ICLASS_AE_MAX32, + ICLASS_AE_MINMAX32, + ICLASS_AE_MINMAX16, + ICLASS_AE_MIN16, + ICLASS_AE_MAX16, + ICLASS_AE_ADD64, + ICLASS_AE_SUB64, + ICLASS_AE_NEG64, + ICLASS_AE_ABS64, + ICLASS_AE_ADDSQ56S, + ICLASS_AE_SUBSQ56S, + ICLASS_AE_ADD64S, + ICLASS_AE_SUB64S, + ICLASS_AE_NEGSQ56S, + ICLASS_AE_ABSSQ56S, + ICLASS_AE_NEG64S, + ICLASS_AE_ABS64S, + ICLASS_AE_AND, + ICLASS_AE_NAND, + ICLASS_AE_OR, + ICLASS_AE_XOR, + ICLASS_AE_SLAI24, + ICLASS_AE_SRLI24, + ICLASS_AE_SRAI24, + ICLASS_AE_SLAS24, + ICLASS_AE_SRLS24, + ICLASS_AE_SRAS24, + ICLASS_AE_SRAI16, + ICLASS_AE_SRAI16R, + ICLASS_AE_SLAI32, + ICLASS_AE_SRLI32, + ICLASS_AE_SRAI32, + ICLASS_AE_SRAI32R, + ICLASS_AE_SLAS32, + ICLASS_AE_SRLS32, + ICLASS_AE_SRAS32, + ICLASS_AE_SLAA32, + ICLASS_AE_SRLA32, + ICLASS_AE_SRAA32, + ICLASS_AE_SLAI16S, + ICLASS_AE_SLAA16S, + ICLASS_AE_SRAA16S, + ICLASS_AE_SRAA16RS, + ICLASS_AE_SLAI24S, + ICLASS_AE_SLAS24S, + ICLASS_AE_SLAI32S, + ICLASS_AE_SLAS32S, + ICLASS_AE_SLAA32S, + ICLASS_AE_SRAA32S, + ICLASS_AE_SRAA32RS, + ICLASS_AE_SLASQ56, + ICLASS_AE_SRLSQ56, + ICLASS_AE_SRASQ56, + ICLASS_AE_SLAAQ56, + ICLASS_AE_SRLAQ56, + ICLASS_AE_SRAAQ56, + ICLASS_AE_SLAI64, + ICLASS_AE_SRLI64, + ICLASS_AE_SRAI64, + ICLASS_AE_SLAS64, + ICLASS_AE_SRLS64, + ICLASS_AE_SRAS64, + ICLASS_AE_SLAA64, + ICLASS_AE_SRLA64, + ICLASS_AE_SRAA64, + ICLASS_AE_SLAISQ56S, + ICLASS_AE_SLASSQ56S, + ICLASS_AE_SLAASQ56S, + ICLASS_AE_SLAI64S, + ICLASS_AE_SLAS64S, + ICLASS_AE_SLAA64S, + ICLASS_AE_LT64, + ICLASS_AE_LE64, + ICLASS_AE_EQ64, + ICLASS_AE_MAX64, + ICLASS_AE_MIN64, + ICLASS_AE_NSA64, + ICLASS_AE_NSAZ16_0, + ICLASS_AE_NSAZ32_L, + ICLASS_AE_MULS32F48P16S_LL, + ICLASS_AE_MULF32S_LL, + ICLASS_AE_MUL32_LL, + ICLASS_AE_MULF32R_LL, + ICLASS_AE_MULF32RA_LL, + ICLASS_AE_MULS32F48P16S_LH, + ICLASS_AE_MULF32S_LH, + ICLASS_AE_MUL32_LH, + ICLASS_AE_MULF32R_LH, + ICLASS_AE_MULF32RA_LH, + ICLASS_AE_MULS32F48P16S_HH, + ICLASS_AE_MULF32S_HH, + ICLASS_AE_MUL32_HH, + ICLASS_AE_MULF32R_HH, + ICLASS_AE_MULF32RA_HH, + ICLASS_AE_MULAS32F48P16S_LL, + ICLASS_AE_MULAF32S_LL, + ICLASS_AE_MULA32_LL, + ICLASS_AE_MULAF32R_LL, + ICLASS_AE_MULAF32RA_LL, + ICLASS_AE_MULAS32F48P16S_LH, + ICLASS_AE_MULAF32S_LH, + ICLASS_AE_MULA32_LH, + ICLASS_AE_MULAF32R_LH, + ICLASS_AE_MULAF32RA_LH, + ICLASS_AE_MULAS32F48P16S_HH, + ICLASS_AE_MULAF32S_HH, + ICLASS_AE_MULA32_HH, + ICLASS_AE_MULAF32R_HH, + ICLASS_AE_MULAF32RA_HH, + ICLASS_AE_MULSS32F48P16S_LL, + ICLASS_AE_MULSF32S_LL, + ICLASS_AE_MULS32_LL, + ICLASS_AE_MULSF32R_LL, + ICLASS_AE_MULSF32RA_LL, + ICLASS_AE_MULSS32F48P16S_LH, + ICLASS_AE_MULSF32S_LH, + ICLASS_AE_MULS32_LH, + ICLASS_AE_MULSF32R_LH, + ICLASS_AE_MULSF32RA_LH, + ICLASS_AE_MULSS32F48P16S_HH, + ICLASS_AE_MULSF32S_HH, + ICLASS_AE_MULS32_HH, + ICLASS_AE_MULSF32R_HH, + ICLASS_AE_MULSF32RA_HH, + ICLASS_AE_MUL32U_LL, + ICLASS_AE_MULA32U_LL, + ICLASS_AE_MULS32U_LL, + ICLASS_AE_MULF16SS_33, + ICLASS_AE_MULF16SS_22, + ICLASS_AE_MULF16SS_32, + ICLASS_AE_MULF16SS_21, + ICLASS_AE_MULF16SS_31, + ICLASS_AE_MULF16SS_30, + ICLASS_AE_MULF16SS_10, + ICLASS_AE_MULF16SS_20, + ICLASS_AE_MULF16SS_11, + ICLASS_AE_MULF16SS_00, + ICLASS_AE_MULSF16SS_33, + ICLASS_AE_MULSF16SS_22, + ICLASS_AE_MULSF16SS_32, + ICLASS_AE_MULSF16SS_21, + ICLASS_AE_MULSF16SS_31, + ICLASS_AE_MULSF16SS_30, + ICLASS_AE_MULSF16SS_10, + ICLASS_AE_MULSF16SS_20, + ICLASS_AE_MULSF16SS_11, + ICLASS_AE_MULSF16SS_00, + ICLASS_AE_MULAF16SS_33, + ICLASS_AE_MULAF16SS_22, + ICLASS_AE_MULAF16SS_32, + ICLASS_AE_MULAF16SS_21, + ICLASS_AE_MULAF16SS_31, + ICLASS_AE_MULAF16SS_30, + ICLASS_AE_MULAF16SS_10, + ICLASS_AE_MULAF16SS_20, + ICLASS_AE_MULAF16SS_11, + ICLASS_AE_MULAF16SS_00, + ICLASS_AE_MUL16S_00, + ICLASS_AE_MULA16S_00, + ICLASS_AE_MULS16S_00, + ICLASS_AE_MULAAFD16SS_33_22, + ICLASS_AE_MULAAFD16SS_13_02, + ICLASS_AE_MULAAFD16SS_11_00, + ICLASS_AE_MULSSFD16SS_33_22, + ICLASS_AE_MULSSFD16SS_13_02, + ICLASS_AE_MULSSFD16SS_11_00, + ICLASS_AE_MULZAAFD16SS_33_22, + ICLASS_AE_MULZAAFD16SS_13_02, + ICLASS_AE_MULZAAFD16SS_11_00, + ICLASS_AE_MULZSSFD16SS_33_22, + ICLASS_AE_MULZSSFD16SS_13_02, + ICLASS_AE_MULZSSFD16SS_11_00, + ICLASS_AE_MULF48Q32SP16S_L, + ICLASS_AE_MULF48Q32SP16U_L, + ICLASS_AE_MULQ32SP16S_L, + ICLASS_AE_MULQ32SP16U_L, + ICLASS_AE_MULAF48Q32SP16S_L, + ICLASS_AE_MULAF48Q32SP16U_L, + ICLASS_AE_MULAQ32SP16S_L, + ICLASS_AE_MULAQ32SP16U_L, + ICLASS_AE_MULSF48Q32SP16S_L, + ICLASS_AE_MULSF48Q32SP16U_L, + ICLASS_AE_MULSQ32SP16S_L, + ICLASS_AE_MULSQ32SP16U_L, + ICLASS_AE_MULFP24X2RA, + ICLASS_AE_MULFP24X2R, + ICLASS_AE_MULAFP24X2RA, + ICLASS_AE_MULAFP24X2R, + ICLASS_AE_MULSFP24X2RA, + ICLASS_AE_MULSFP24X2R, + ICLASS_AE_MULZAAFD32S_HH_LL, + ICLASS_AE_MULZAAFD32RA_HH_LL, + ICLASS_AE_MULZAAD32_HH_LL, + ICLASS_AE_MULZAAFD32S_HL_LH, + ICLASS_AE_MULZAAFD32RA_HL_LH, + ICLASS_AE_MULZAAD32_HL_LH, + ICLASS_AE_MULZASFD32S_HH_LL, + ICLASS_AE_MULZASFD32RA_HH_LL, + ICLASS_AE_MULZASD32_HH_LL, + ICLASS_AE_MULZASFD32S_HL_LH, + ICLASS_AE_MULZASFD32RA_HL_LH, + ICLASS_AE_MULZASD32_HL_LH, + ICLASS_AE_MULZSAFD32S_HH_LL, + ICLASS_AE_MULZSAFD32RA_HH_LL, + ICLASS_AE_MULZSAD32_HH_LL, + ICLASS_AE_MULZSSFD32S_HH_LL, + ICLASS_AE_MULZSSFD32RA_HH_LL, + ICLASS_AE_MULZSSD32_HH_LL, + ICLASS_AE_MULZSSFD32S_HL_LH, + ICLASS_AE_MULZSSFD32RA_HL_LH, + ICLASS_AE_MULZSSD32_HL_LH, + ICLASS_AE_MULAAFD32S_HH_LL, + ICLASS_AE_MULAAFD32RA_HH_LL, + ICLASS_AE_MULAAD32_HH_LL, + ICLASS_AE_MULAAFD32S_HL_LH, + ICLASS_AE_MULAAFD32RA_HL_LH, + ICLASS_AE_MULAAD32_HL_LH, + ICLASS_AE_MULASFD32S_HH_LL, + ICLASS_AE_MULASFD32RA_HH_LL, + ICLASS_AE_MULASD32_HH_LL, + ICLASS_AE_MULASFD32S_HL_LH, + ICLASS_AE_MULASFD32RA_HL_LH, + ICLASS_AE_MULASD32_HL_LH, + ICLASS_AE_MULSAFD32S_HH_LL, + ICLASS_AE_MULSAFD32RA_HH_LL, + ICLASS_AE_MULSAD32_HH_LL, + ICLASS_AE_MULSSFD32S_HH_LL, + ICLASS_AE_MULSSFD32RA_HH_LL, + ICLASS_AE_MULSSD32_HH_LL, + ICLASS_AE_MULSSFD32S_HL_LH, + ICLASS_AE_MULSSFD32RA_HL_LH, + ICLASS_AE_MULSSD32_HL_LH, + ICLASS_AE_MULF32X16_L0, + ICLASS_AE_MUL32X16_L0, + ICLASS_AE_MULF32X16_L1, + ICLASS_AE_MUL32X16_L1, + ICLASS_AE_MULF32X16_L2, + ICLASS_AE_MUL32X16_L2, + ICLASS_AE_MULF32X16_L3, + ICLASS_AE_MUL32X16_L3, + ICLASS_AE_MULF32X16_H0, + ICLASS_AE_MUL32X16_H0, + ICLASS_AE_MULF32X16_H1, + ICLASS_AE_MUL32X16_H1, + ICLASS_AE_MULF32X16_H2, + ICLASS_AE_MUL32X16_H2, + ICLASS_AE_MULF32X16_H3, + ICLASS_AE_MUL32X16_H3, + ICLASS_AE_MULAF32X16_L0, + ICLASS_AE_MULA32X16_L0, + ICLASS_AE_MULAF32X16_L1, + ICLASS_AE_MULA32X16_L1, + ICLASS_AE_MULAF32X16_L2, + ICLASS_AE_MULA32X16_L2, + ICLASS_AE_MULAF32X16_L3, + ICLASS_AE_MULA32X16_L3, + ICLASS_AE_MULAF32X16_H0, + ICLASS_AE_MULA32X16_H0, + ICLASS_AE_MULAF32X16_H1, + ICLASS_AE_MULA32X16_H1, + ICLASS_AE_MULAF32X16_H2, + ICLASS_AE_MULA32X16_H2, + ICLASS_AE_MULAF32X16_H3, + ICLASS_AE_MULA32X16_H3, + ICLASS_AE_MULSF32X16_L0, + ICLASS_AE_MULS32X16_L0, + ICLASS_AE_MULSF32X16_L1, + ICLASS_AE_MULS32X16_L1, + ICLASS_AE_MULSF32X16_L2, + ICLASS_AE_MULS32X16_L2, + ICLASS_AE_MULSF32X16_L3, + ICLASS_AE_MULS32X16_L3, + ICLASS_AE_MULSF32X16_H0, + ICLASS_AE_MULS32X16_H0, + ICLASS_AE_MULSF32X16_H1, + ICLASS_AE_MULS32X16_H1, + ICLASS_AE_MULSF32X16_H2, + ICLASS_AE_MULS32X16_H2, + ICLASS_AE_MULSF32X16_H3, + ICLASS_AE_MULS32X16_H3, + ICLASS_AE_MULAAFD32X16_H3_L2, + ICLASS_AE_MULAAD32X16_H3_L2, + ICLASS_AE_MULAAFD32X16_H1_L0, + ICLASS_AE_MULAAD32X16_H1_L0, + ICLASS_AE_MULASFD32X16_H3_L2, + ICLASS_AE_MULASD32X16_H3_L2, + ICLASS_AE_MULASFD32X16_H1_L0, + ICLASS_AE_MULASD32X16_H1_L0, + ICLASS_AE_MULSAFD32X16_H3_L2, + ICLASS_AE_MULSAD32X16_H3_L2, + ICLASS_AE_MULSAFD32X16_H1_L0, + ICLASS_AE_MULSAD32X16_H1_L0, + ICLASS_AE_MULSSFD32X16_H3_L2, + ICLASS_AE_MULSSD32X16_H3_L2, + ICLASS_AE_MULSSFD32X16_H1_L0, + ICLASS_AE_MULSSD32X16_H1_L0, + ICLASS_AE_MULZAAFD32X16_H3_L2, + ICLASS_AE_MULZAAD32X16_H3_L2, + ICLASS_AE_MULZAAFD32X16_H1_L0, + ICLASS_AE_MULZAAD32X16_H1_L0, + ICLASS_AE_MULZASFD32X16_H3_L2, + ICLASS_AE_MULZASD32X16_H3_L2, + ICLASS_AE_MULZASFD32X16_H1_L0, + ICLASS_AE_MULZASD32X16_H1_L0, + ICLASS_AE_MULZSAFD32X16_H3_L2, + ICLASS_AE_MULZSAD32X16_H3_L2, + ICLASS_AE_MULZSAFD32X16_H1_L0, + ICLASS_AE_MULZSAD32X16_H1_L0, + ICLASS_AE_MULZSSFD32X16_H3_L2, + ICLASS_AE_MULZSSD32X16_H3_L2, + ICLASS_AE_MULZSSFD32X16_H1_L0, + ICLASS_AE_MULZSSD32X16_H1_L0, + ICLASS_AE_MULZAAFD32X16_H2_L3, + ICLASS_AE_MULZAAFD32X16_H0_L1, + ICLASS_AE_MULAAFD32X16_H2_L3, + ICLASS_AE_MULAAFD32X16_H0_L1, + ICLASS_AE_MULZAAD32X16_H2_L3, + ICLASS_AE_MULZAAD32X16_H0_L1, + ICLASS_AE_MULAAD32X16_H2_L3, + ICLASS_AE_MULAAD32X16_H0_L1, + ICLASS_AE_MULP32X16X2_H, + ICLASS_AE_MULFP32X16X2RS_H, + ICLASS_AE_MULFP32X16X2RAS_H, + ICLASS_AE_MULFP32X16X2S_H, + ICLASS_AE_MULP32X16X2_L, + ICLASS_AE_MULFP32X16X2RS_L, + ICLASS_AE_MULFP32X16X2RAS_L, + ICLASS_AE_MULFP32X16X2S_L, + ICLASS_AE_MULAP32X16X2_H, + ICLASS_AE_MULAFP32X16X2RS_H, + ICLASS_AE_MULAFP32X16X2RAS_H, + ICLASS_AE_MULAFP32X16X2S_H, + ICLASS_AE_MULAP32X16X2_L, + ICLASS_AE_MULAFP32X16X2RS_L, + ICLASS_AE_MULAFP32X16X2RAS_L, + ICLASS_AE_MULAFP32X16X2S_L, + ICLASS_AE_MULSP32X16X2_H, + ICLASS_AE_MULSFP32X16X2RS_H, + ICLASS_AE_MULSFP32X16X2RAS_H, + ICLASS_AE_MULSFP32X16X2S_H, + ICLASS_AE_MULSP32X16X2_L, + ICLASS_AE_MULSFP32X16X2RS_L, + ICLASS_AE_MULSFP32X16X2RAS_L, + ICLASS_AE_MULSFP32X16X2S_L, + ICLASS_AE_MULP32X2, + ICLASS_AE_MULFP32X2RS, + ICLASS_AE_MULFP32X2RAS, + ICLASS_AE_MULFP32X2TS, + ICLASS_AE_MULP32X2T, + ICLASS_AE_MULAP32X2, + ICLASS_AE_MULAFP32X2RS, + ICLASS_AE_MULAFP32X2RAS, + ICLASS_AE_MULAFP32X2TS, + ICLASS_AE_MULAP32X2T, + ICLASS_AE_MULSP32X2, + ICLASS_AE_MULSFP32X2RS, + ICLASS_AE_MULSFP32X2RAS, + ICLASS_AE_MULSFP32X2TS, + ICLASS_AE_MULSP32X2T, + ICLASS_AE_MULFP16X4S, + ICLASS_AE_MULFP16X4RAS, + ICLASS_AE_MULC32, + ICLASS_AE_MULFC24RA, + ICLASS_AE_MULFC32RAS, + ICLASS_AE_MULC32X16_L, + ICLASS_AE_MULFC32X16RAS_L, + ICLASS_AE_MULC32X16_H, + ICLASS_AE_MULFC32X16RAS_H, + ICLASS_AE_MULAC32, + ICLASS_AE_MULAFC24RA, + ICLASS_AE_MULAFC32RAS, + ICLASS_AE_MULAC32X16_L, + ICLASS_AE_MULAFC32X16RAS_L, + ICLASS_AE_MULAC32X16_H, + ICLASS_AE_MULAFC32X16RAS_H, + ICLASS_AE_MULF16X4SS, + ICLASS_AE_MULAF16X4SS, + ICLASS_AE_MULSF16X4SS, + ICLASS_AE_MUL16X4S, + ICLASS_AE_MULA16X4S, + ICLASS_AE_MULS16X4S, + ICLASS_AE_MUL16X4, + ICLASS_AE_MULA16X4, + ICLASS_AE_MULS16X4, + ICLASS_AE_MULFD32X2S_FIR_H, + ICLASS_AE_MULFD32X2RA_FIR_H, + ICLASS_AE_MULFD32X2S_FIR_L, + ICLASS_AE_MULFD32X2RA_FIR_L, + ICLASS_AE_MULFD32X16X2_FIR_HH, + ICLASS_AE_MULFD32X16X2_FIR_HL, + ICLASS_AE_MULFD32X16X2_FIR_LH, + ICLASS_AE_MULFD32X16X2_FIR_LL, + ICLASS_AE_MULAFD32X2S_FIR_H, + ICLASS_AE_MULAFD32X2RA_FIR_H, + ICLASS_AE_MULAFD32X2S_FIR_L, + ICLASS_AE_MULAFD32X2RA_FIR_L, + ICLASS_AE_MULAFD32X16X2_FIR_HH, + ICLASS_AE_MULAFD32X16X2_FIR_HL, + ICLASS_AE_MULAFD32X16X2_FIR_LH, + ICLASS_AE_MULAFD32X16X2_FIR_LL, + ICLASS_AE_MULC16S_H, + ICLASS_AE_MULC16S_L, + ICLASS_AE_MULAC16S_H, + ICLASS_AE_MULAC16S_L, + ICLASS_AE_MULFC16RAS, + ICLASS_AE_MULAFC16RAS, + ICLASS_AE_MUL16JS, + ICLASS_AE_ADDANDSUBRNG16RAS_S1, + ICLASS_AE_ADDANDSUBRNG16RAS_S2, + ICLASS_AE_CONJ16S, + ICLASS_AE_MULFQ16X2_FIR_3, + ICLASS_AE_MULFQ16X2_FIR_2, + ICLASS_AE_MULFQ16X2_FIR_1, + ICLASS_AE_MULFQ16X2_FIR_0, + ICLASS_AE_MULAFQ16X2_FIR_3, + ICLASS_AE_MULAFQ16X2_FIR_2, + ICLASS_AE_MULAFQ16X2_FIR_1, + ICLASS_AE_MULAFQ16X2_FIR_0, + ICLASS_AE_MULZAAAAFQ32X16, + ICLASS_AE_MULAAAAFQ32X16, + ICLASS_AE_MULZAAAAQ32X16, + ICLASS_AE_MULAAAAQ32X16, + ICLASS_AE_MUL16_00, + ICLASS_AE_MULA16_00, + ICLASS_AE_MULZAAAAQ16, + ICLASS_AE_MULAAAAQ16, + ICLASS_AE_DIV64D32_H, + ICLASS_AE_DIV64D32_L, + ICLASS_AE_SHA32, + ICLASS_AE_VLDL32T, + ICLASS_AE_VLDL16T, + ICLASS_AE_VLDL16C, + ICLASS_AE_VLDL16C_IP, + ICLASS_AE_VLDL16C_IC, + ICLASS_AE_VLDL16C_IC1, + ICLASS_AE_VLDSHT, + ICLASS_AE_LB, + ICLASS_AE_LBI, + ICLASS_AE_LBK, + ICLASS_AE_LBKI, + ICLASS_AE_LBS, + ICLASS_AE_LBSI, + ICLASS_AE_DB, + ICLASS_AE_DBI, + ICLASS_AE_DB_IC, + ICLASS_AE_DBI_IC, + ICLASS_AE_DB_IC1, + ICLASS_AE_DBI_IC1, + ICLASS_AE_DB_IP, + ICLASS_AE_DBI_IP, + ICLASS_AE_ARDECNORM16, + ICLASS_AE_LBKI_DBI_IC, + ICLASS_AE_LBKI_DBI_IP, + ICLASS_AE_LBKI_DBI, + ICLASS_AE_LBI_DBI_IC, + ICLASS_AE_LBI_DBI_IP, + ICLASS_AE_LBI_DBI, + ICLASS_AE_LBK_DB_IC, + ICLASS_AE_LBK_DB_IP, + ICLASS_AE_LBK_DB, + ICLASS_AE_LB_DB_IC, + ICLASS_AE_LB_DB_IP, + ICLASS_AE_LB_DB, + ICLASS_AE_VLEL32T, + ICLASS_AE_VLEL16T, + ICLASS_AE_SB, + ICLASS_AE_SBI, + ICLASS_AE_VLES16C, + ICLASS_AE_SBF, + ICLASS_AE_SB_IC, + ICLASS_AE_SBI_IC, + ICLASS_AE_VLES16C_IC, + ICLASS_AE_SBF_IC, + ICLASS_AE_SB_IC1, + ICLASS_AE_SBI_IC1, + ICLASS_AE_VLES16C_IC1, + ICLASS_AE_SBF_IC1, + ICLASS_AE_SB_IP, + ICLASS_AE_SBI_IP, + ICLASS_AE_VLES16C_IP, + ICLASS_AE_SBF_IP, + ICLASS_AE_SEXT32, + ICLASS_AE_MOVAE, + ICLASS_AE_MOVEA, + ICLASS_AE_MOVEEP, + ICLASS_AE_SEXT72, + ICLASS_AE_ADD72, + ICLASS_AE_SUB72, + ICLASS_AE_ADD72X64, + ICLASS_AE_SUB72X64, + ICLASS_AE_MUL32EP_HH, + ICLASS_AE_MULA32EP_HH, + ICLASS_AE_MULS32EP_HH, + ICLASS_AE_MULZAAD32EP_HH_LL, + ICLASS_AE_MULZSSD32EP_HH_LL, + ICLASS_AE_MULAAD32EP_HH_LL, + ICLASS_AE_MULSSD32EP_HH_LL, + ICLASS_AE_MULAAD32USEP_HL_LH, + ICLASS_AE_MULZAAD32USEP_HL_LH, + ICLASS_AE_MUL32USEP_LH, + ICLASS_AE_MULA32USEP_LH, + ICLASS_AE_MUL32USEP_LL, + ICLASS_AE_MULA32USEP_LL, + ICLASS_AE_SRAI72, + ICLASS_AE_SLAI72, + ICLASS_AE_SAT64S, + ICLASS_AE_L16SI_N, + ICLASS_AE_L16UI_N, + ICLASS_AE_S16I_N, + ICLASS_AE_LALIGN128_I, + ICLASS_AE_SALIGN128_I, + ICLASS_AE_LA128_PP, + ICLASS_AE_SA128POS_FP, + ICLASS_AE_LA8X4S_IP, + ICLASS_AE_LA8X4U_IP, + ICLASS_AE_LA8X8X2_IP, + ICLASS_AE_LA16X4X2_IP, + ICLASS_AE_LA32X2X2_IP, + ICLASS_AE_LA8X8X2_IC, + ICLASS_AE_LA16X4X2_IC, + ICLASS_AE_LA32X2X2_IC, + ICLASS_AE_LA8X8X2_IC1, + ICLASS_AE_LA16X4X2_IC1, + ICLASS_AE_LA32X2X2_IC1, + ICLASS_AE_LA8X8X2_IC2, + ICLASS_AE_LA16X4X2_IC2, + ICLASS_AE_LA32X2X2_IC2, + ICLASS_AE_SA8X8X2_IP, + ICLASS_AE_SA16X4X2_IP, + ICLASS_AE_SA32X2X2_IP, + ICLASS_AE_SA8X8X2_IC, + ICLASS_AE_SA16X4X2_IC, + ICLASS_AE_SA32X2X2_IC, + ICLASS_AE_SA8X8X2_IC1, + ICLASS_AE_SA16X4X2_IC1, + ICLASS_AE_SA32X2X2_IC1, + ICLASS_AE_SA8X8X2_IC2, + ICLASS_AE_SA16X4X2_IC2, + ICLASS_AE_SA32X2X2_IC2, + ICLASS_AE_ABS8, + ICLASS_AE_ABS8S, + ICLASS_AE_NEG8S, + ICLASS_AE_ADD8, + ICLASS_AE_SUB8, + ICLASS_AE_MAX8, + ICLASS_AE_MIN8, + ICLASS_AE_ADD8S, + ICLASS_AE_SUB8S, + ICLASS_AE_LE8, + ICLASS_AE_LT8, + ICLASS_AE_EQ8, + ICLASS_AE_SATU16X4, + ICLASS_AE_SAT32X2, + ICLASS_AE_SATU32X2, + ICLASS_AE_SAT8X8X16, + ICLASS_AE_SATU8X8X16, + ICLASS_AE_SAT8X4X32_L, + ICLASS_AE_SATU8X4X32_L, + ICLASS_AE_ROUND8X8F16SSYM, + ICLASS_AE_ROUND8X8F16SASYM, + ICLASS_AE_ROUND8X4F32SSYM_L, + ICLASS_AE_ROUND8X4F32SASYM_L, + ICLASS_AE_MOVDA8, + ICLASS_AE_MOVAD8, + ICLASS_AE_MOVDX2, + ICLASS_AE_ADDANDSUB32J, + ICLASS_AE_ADDW8, + ICLASS_AE_ADDW16, + ICLASS_AE_ADDW32, + ICLASS_AE_SUBW8, + ICLASS_AE_SUBW16, + ICLASS_AE_SUBW32, + ICLASS_AE_ACCW8, + ICLASS_AE_ACCW16, + ICLASS_AE_ACCW32, + ICLASS_AE_ADDW8U, + ICLASS_AE_SUBW8U, + ICLASS_AE_ACCW8U, + ICLASS_AE_MULFP32X2S_HH_LL, + ICLASS_AE_MULAFP32X2S_HH_LL, + ICLASS_AE_MULSFP32X2S_HH_LL, + ICLASS_AE_MULFP32X2S_HL_LH, + ICLASS_AE_MULAFP32X2S_HL_LH, + ICLASS_AE_MULSFP32X2S_HL_LH, + ICLASS_AE_MULZAAF2D32S_HH_LL, + ICLASS_AE_MULZASF2D32S_HH_LL, + ICLASS_AE_MULZSAF2D32S_HH_LL, + ICLASS_AE_MULZSSF2D32S_HH_LL, + ICLASS_AE_MULAAF2D32S_HH_LL, + ICLASS_AE_MULASF2D32S_HH_LL, + ICLASS_AE_MULSAF2D32S_HH_LL, + ICLASS_AE_MULSSF2D32S_HH_LL, + ICLASS_AE_MULZAAF2D32S_HL_LH, + ICLASS_AE_MULZASF2D32S_HL_LH, + ICLASS_AE_MULZSAF2D32S_HL_LH, + ICLASS_AE_MULZSSF2D32S_HL_LH, + ICLASS_AE_MULAAF2D32S_HL_LH, + ICLASS_AE_MULASF2D32S_HL_LH, + ICLASS_AE_MULSAF2D32S_HL_LH, + ICLASS_AE_MULSSF2D32S_HL_LH, + ICLASS_AE_MUL32S_HH, + ICLASS_AE_MULA32S_HH, + ICLASS_AE_MULS32S_HH, + ICLASS_AE_MUL32S_LL, + ICLASS_AE_MULA32S_LL, + ICLASS_AE_MULS32S_LL, + ICLASS_AE_MUL32S_HL, + ICLASS_AE_MULA32S_HL, + ICLASS_AE_MULS32S_HL, + ICLASS_AE_MUL32S_LH, + ICLASS_AE_MULA32S_LH, + ICLASS_AE_MULS32S_LH, + ICLASS_AE_MUL32X2S_HH_LL, + ICLASS_AE_MULA32X2S_HH_LL, + ICLASS_AE_MULS32X2S_HH_LL, + ICLASS_AE_MUL32X2S_HL_LH, + ICLASS_AE_MULA32X2S_HL_LH, + ICLASS_AE_MULS32X2S_HL_LH, + ICLASS_AE_MULZAAD32S_HH_LL, + ICLASS_AE_MULZASD32S_HH_LL, + ICLASS_AE_MULZSAD32S_HH_LL, + ICLASS_AE_MULZSSD32S_HH_LL, + ICLASS_AE_MULAAD32S_HH_LL, + ICLASS_AE_MULASD32S_HH_LL, + ICLASS_AE_MULSAD32S_HH_LL, + ICLASS_AE_MULSSD32S_HH_LL, + ICLASS_AE_MULZAAD32S_HL_LH, + ICLASS_AE_MULZASD32S_HL_LH, + ICLASS_AE_MULZSAD32S_HL_LH, + ICLASS_AE_MULZSSD32S_HL_LH, + ICLASS_AE_MULAAD32S_HL_LH, + ICLASS_AE_MULASD32S_HL_LH, + ICLASS_AE_MULSAD32S_HL_LH, + ICLASS_AE_MULSSD32S_HL_LH, + ICLASS_AE_MULF32X2RA_HH_LL, + ICLASS_AE_MULAF32X2RA_HH_LL, + ICLASS_AE_MULSF32X2RA_HH_LL, + ICLASS_AE_MULF32X2RA_HL_LH, + ICLASS_AE_MULAF32X2RA_HL_LH, + ICLASS_AE_MULSF32X2RA_HL_LH, + ICLASS_AE_MULZAAF2D32RA_HH_LL, + ICLASS_AE_MULZASF2D32RA_HH_LL, + ICLASS_AE_MULZSAF2D32RA_HH_LL, + ICLASS_AE_MULZSSF2D32RA_HH_LL, + ICLASS_AE_MULAAF2D32RA_HH_LL, + ICLASS_AE_MULASF2D32RA_HH_LL, + ICLASS_AE_MULSAF2D32RA_HH_LL, + ICLASS_AE_MULSSF2D32RA_HH_LL, + ICLASS_AE_MULZAAF2D32RA_HL_LH, + ICLASS_AE_MULZASF2D32RA_HL_LH, + ICLASS_AE_MULZSAF2D32RA_HL_LH, + ICLASS_AE_MULZSSF2D32RA_HL_LH, + ICLASS_AE_MULAAF2D32RA_HL_LH, + ICLASS_AE_MULASF2D32RA_HL_LH, + ICLASS_AE_MULSAF2D32RA_HL_LH, + ICLASS_AE_MULSSF2D32RA_HL_LH, + ICLASS_AE_MULF32X2R_HH_LL, + ICLASS_AE_MULAF32X2R_HH_LL, + ICLASS_AE_MULSF32X2R_HH_LL, + ICLASS_AE_MULF32X2R_HL_LH, + ICLASS_AE_MULAF32X2R_HL_LH, + ICLASS_AE_MULSF32X2R_HL_LH, + ICLASS_AE_MULFC32W, + ICLASS_AE_MULAFC32W, + ICLASS_AE_MULFCJ32W, + ICLASS_AE_MULAFCJ32W, + ICLASS_AE_MULFCJ32RAS, + ICLASS_AE_MULAFCJ32RAS, + ICLASS_AE_MULF2P32X4RS, + ICLASS_AE_MULAF2P32X4RS, + ICLASS_AE_MULSF2P32X4RS, + ICLASS_AE_MULF2P32X4RAS, + ICLASS_AE_MULAF2P32X4RAS, + ICLASS_AE_MULSF2P32X4RAS, + ICLASS_AE_MULP32X2S, + ICLASS_AE_MUL2P32X4S, + ICLASS_AE_MUL2P32X4, + ICLASS_AE_MULA2P32X4, + ICLASS_AE_MULS2P32X4, + ICLASS_AE_MUL2P32X4T, + ICLASS_AE_MULA2P32X4T, + ICLASS_AE_MULS2P32X4T, + ICLASS_AE_MULZAA32X2_HH_LL, + ICLASS_AE_MULZSS32X2_HH_LL, + ICLASS_AE_MULAA32X2_HH_LL, + ICLASS_AE_MULSS32X2_HH_LL, + ICLASS_AE_MULCJ32, + ICLASS_AE_MULACJ32, + ICLASS_AE_MULADDF32RS, + ICLASS_AE_MULADDF32RAS, + ICLASS_AE_MULSUBF32RS, + ICLASS_AE_MULSUBF32RAS, + ICLASS_AE_MULFC32RA, + ICLASS_AE_MULAFC32RA, + ICLASS_AE_MULCJ32W, + ICLASS_AE_MULACJ32W, + ICLASS_AE_MULC32W, + ICLASS_AE_MULAC32W, + ICLASS_AE_MULF2D32X2WS, + ICLASS_AE_MULZAAAA2Q16, + ICLASS_AE_MULAAAA2Q16, + ICLASS_AE_MULP16S_H, + ICLASS_AE_MULAP16S_H, + ICLASS_AE_MULSP16S_H, + ICLASS_AE_MULP16S_L, + ICLASS_AE_MULAP16S_L, + ICLASS_AE_MULSP16S_L, + ICLASS_AE_MULC16W_H, + ICLASS_AE_MULAC16W_H, + ICLASS_AE_MULC16W_L, + ICLASS_AE_MULAC16W_L, + ICLASS_AE_MUL2C16S, + ICLASS_AE_MULA2C16S, + ICLASS_AE_MULFC16S, + ICLASS_AE_MULAFC16S, + ICLASS_AE_MULFCJ16S, + ICLASS_AE_MULAFCJ16S, + ICLASS_AE_MULFCJ16RAS, + ICLASS_AE_MULAFCJ16RAS, + ICLASS_AE_MULC16S, + ICLASS_AE_MULAC16S, + ICLASS_AE_MULFP16X4RS, + ICLASS_AE_MULFD16X16X4RAS, + ICLASS_AE_MULP16X16X4S, + ICLASS_AE_MULAP16X16X4S, + ICLASS_AE_MULSP16X16X4S, + ICLASS_AE_MULZAA2D16SS_HH_LL, + ICLASS_AE_MULZAA2D16SS_HL_LH, + ICLASS_AE_MULZSS2D16SS_HH_LL, + ICLASS_AE_MULZSS2D16SS_HL_LH, + ICLASS_AE_MULAA2D16SS_HH_LL, + ICLASS_AE_MULAA2D16SS_HL_LH, + ICLASS_AE_MULSS2D16SS_HH_LL, + ICLASS_AE_MULSS2D16SS_HL_LH, + ICLASS_AE_MULZAAFD16SS_HH_LL, + ICLASS_AE_MULZAAFD16SS_HL_LH, + ICLASS_AE_MULZSSFD16SS_HH_LL, + ICLASS_AE_MULZSSFD16SS_HL_LH, + ICLASS_AE_MULAAFD16SS_HH_LL, + ICLASS_AE_MULAAFD16SS_HL_LH, + ICLASS_AE_MULSSFD16SS_HH_LL, + ICLASS_AE_MULSSFD16SS_HL_LH, + ICLASS_AE_MULFD16X16X4WS, + ICLASS_AE_MULZAAAA2Q16X8, + ICLASS_AE_MULAAAA2Q16X8, + ICLASS_AE_MULZAAAA2Q8, + ICLASS_AE_MULAAAA2Q8, + ICLASS_AE_MULC32X16W_H, + ICLASS_AE_MULAC32X16W_H, + ICLASS_AE_MULC32X16W_L, + ICLASS_AE_MULAC32X16W_L, + ICLASS_AE_MULPC32X16X2, + ICLASS_AE_MULAPC32X16X2, + ICLASS_AE_MULFP32X16_H, + ICLASS_AE_MULAFP32X16_H, + ICLASS_AE_MULSFP32X16_H, + ICLASS_AE_MULFP32X16_L, + ICLASS_AE_MULAFP32X16_L, + ICLASS_AE_MULSFP32X16_L, + ICLASS_AE_MULFC32X16W_H, + ICLASS_AE_MULAFC32X16W_H, + ICLASS_AE_MULFC32X16W_L, + ICLASS_AE_MULAFC32X16W_L, + ICLASS_AE_MULFCJ32X16W_H, + ICLASS_AE_MULAFCJ32X16W_H, + ICLASS_AE_MULFCJ32X16W_L, + ICLASS_AE_MULAFCJ32X16W_L, + ICLASS_AE_MULF2P32X16X4RAS, + ICLASS_AE_MULAF2P32X16X4RAS, + ICLASS_AE_MULSF2P32X16X4RAS, + ICLASS_AE_MULF2P32X16X4RS, + ICLASS_AE_MULAF2P32X16X4RS, + ICLASS_AE_MULSF2P32X16X4RS, + ICLASS_AE_MULF2P32X16X4S, + ICLASS_AE_MULAF2P32X16X4S, + ICLASS_AE_MULSF2P32X16X4S, + ICLASS_AE_MULFPC32X16X2RAS, + ICLASS_AE_MULAFPC32X16X2RAS, + ICLASS_AE_MULFPCJ32X16X2RAS, + ICLASS_AE_MULAFPCJ32X16X2RAS, + ICLASS_AE_MULZAAAA2Q32X16, + ICLASS_AE_MULAAAA2Q32X16, + ICLASS_AE_MUL2Q32X16_FIR_H, + ICLASS_AE_MULA2Q32X16_FIR_H, + ICLASS_AE_MUL2Q32X16_FIR_L, + ICLASS_AE_MULA2Q32X16_FIR_L, + ICLASS_AE_SRAI8, + ICLASS_AE_SRAI8R, + ICLASS_AE_SRLI8, + ICLASS_AE_SLAI8, + ICLASS_AE_SLAI8S, + ICLASS_AE_SLAA8, + ICLASS_AE_SRLA8, + ICLASS_AE_SLAA8S, + ICLASS_AE_SRAA8RS, + ICLASS_AE_SRAA8S, + ICLASS_AE_SRLI16, + ICLASS_AE_SLAI16, + ICLASS_AE_SLAA16, + ICLASS_AE_SRLA16, + ICLASS_AE_SRAI16SYM, + ICLASS_AE_SRAA16SYMS, + ICLASS_AE_SRAI32SYM, + ICLASS_AE_SRAA32SYMS, + ICLASS_AE_SRAV16RS, + ICLASS_AE_SRAV32RS, + ICLASS_AE_CVTI32X4F8_H, + ICLASS_AE_CVTI32X4F8_L, + ICLASS_AE_CVTI32X4F8S_H, + ICLASS_AE_CVTI32X4F8S_L, + ICLASS_AE_CVTA32X4F8_H, + ICLASS_AE_CVTA32X4F8_L, + ICLASS_AE_CVTA32X4F8S_H, + ICLASS_AE_CVTA32X4F8S_L, + ICLASS_AE_CVTI32X4F8U_H, + ICLASS_AE_CVTI32X4F8U_L, + ICLASS_AE_CVTI32X4F8US_H, + ICLASS_AE_CVTI32X4F8US_L, + ICLASS_AE_CVTA32X4F8U_H, + ICLASS_AE_CVTA32X4F8U_L, + ICLASS_AE_CVTA32X4F8US_H, + ICLASS_AE_CVTA32X4F8US_L, + ICLASS_AE_CVTI32X4F16, + ICLASS_AE_CVTI32X4F16S, + ICLASS_AE_CVTA32X4F16, + ICLASS_AE_CVTA32X4F16S, + ICLASS_AE_CVTI32X4F16U, + ICLASS_AE_CVTI32X4F16US, + ICLASS_AE_CVTA32X4F16U, + ICLASS_AE_CVTA32X4F16US, + ICLASS_AE_CVTI16X4X2F8, + ICLASS_AE_CVTI16X4X2F8S, + ICLASS_AE_CVTA16X4X2F8, + ICLASS_AE_CVTA16X4X2F8S, + ICLASS_AE_CVTI16X4X2F8U, + ICLASS_AE_CVTI16X4X2F8US, + ICLASS_AE_CVTA16X4X2F8U, + ICLASS_AE_CVTA16X4X2F8US, + ICLASS_AE_SEL8X8, + ICLASS_AE_SHFL8X8, + ICLASS_AE_SEL16X4, + ICLASS_AE_SHFL16X4, + ICLASS_AE_DSEL8X8, + ICLASS_AE_DSEL16X4, + ICLASS_AE_SEL8X8I, + ICLASS_AE_RMAX8X8, + ICLASS_AE_RMIN8X8, + ICLASS_AE_RMAX16X4, + ICLASS_AE_RMIN16X4, + ICLASS_AE_SORT16X4, + ICLASS_AE_RADD8X8_H, + ICLASS_AE_RADDA8X8_H, + ICLASS_AE_RADD8X8_L, + ICLASS_AE_RADDA8X8_L, + ICLASS_AE_RADD16X4, + ICLASS_AE_RADDA16X4, + ICLASS_AE_BMAX8X8_H, + ICLASS_AE_BMAX8X8_L, + ICLASS_AE_BMIN8X8_H, + ICLASS_AE_BMIN8X8_L, + ICLASS_AE_BMAX16X4, + ICLASS_AE_BMIN16X4, + ICLASS_AE_BMAX32X2, + ICLASS_AE_BMIN32X2, + ICLASS_AE_ADDINV16S, + ICLASS_AE_ADDINV32S, + ICLASS_AE_MOVT16X8, + ICLASS_AE_MOVT8X16_H, + ICLASS_AE_MOVT8X16_L, + ICLASS_AE_MOVBD1X4, + ICLASS_AE_MOVBD1X2, + ICLASS_AE_MOVNEG32S_T, + ICLASS_AE_MOVDEXT, + ICLASS_AE_MOVADEXT_H, + ICLASS_AE_MOVADEXT_L, + ICLASS_AE_NSA16X4, + ICLASS_AE_NSAZ32X4, + ICLASS_AE_NSA32X4, + ICLASS_AE_TRUNCI16X4F32S, + ICLASS_AE_TRUNCI16X4F64S, + ICLASS_AE_TRUNCA16X4F32S, + ICLASS_AE_TRUNCA16X4F64S, + ICLASS_AE_ADDC32, + ICLASS_AE_SUBC32, + ICLASS_AE_ADDC32U, + ICLASS_AE_SUBC32U, + ICLASS_AE_EXPADD16_H, + ICLASS_AE_EXPSUB16_H, + ICLASS_AE_EXPADD16_L, + ICLASS_AE_EXPSUB16_L, + ICLASS_AE_ADDCEXP32_H, + ICLASS_AE_ADDCEXP32_L, + ICLASS_AE_CALCRNG16, + ICLASS_AE_CALCRNG32, + ICLASS_AE_RNG32X4, + ICLASS_AE_LAV8X8X2_XP, + ICLASS_AE_LAV16X4X2_XP, + ICLASS_AE_SAV8X8X2_XP, + ICLASS_AE_SAV16X4X2_XP, + ICLASS_AE_MOVZBVCDR, + ICLASS_AE_MOVDRZBVC, + ICLASS_AE_LAVUNSQZ8X8_XP, + ICLASS_AE_LAVUNSQZ16X4_XP, + ICLASS_AE_MUL8Q8X8, + ICLASS_AE_MULA8Q8X8, + ICLASS_AE_MUL8Q4X16, + ICLASS_AE_MULA8Q4X16, + ICLASS_AE_MUL8Q8X16, + ICLASS_AE_MULA8Q8X16, + ICLASS_AE_MUL8QW8X16, + ICLASS_AE_MULA8QW8X16, + ICLASS_AE_MUL4O8X8, + ICLASS_AE_MULA4O8X8, + ICLASS_AE_MUL4O4X16, + ICLASS_AE_MULA4O4X16, + ICLASS_AE_MUL4O8X16, + ICLASS_AE_MULA4O8X16, + ICLASS_AE_MUL4QW8X16, + ICLASS_AE_MULA4QW8X16, + ICLASS_AE_MUL8Q8X8CNV_L, + ICLASS_AE_MUL8Q8X8CNV_H, + ICLASS_AE_MULA8Q8X8CNV_L, + ICLASS_AE_MULA8Q8X8CNV_H, + ICLASS_AE_MUL8Q8X16CNV, + ICLASS_AE_MULA8Q8X16CNV, + ICLASS_AE_MUL2X4Q8X8CNV_H, + ICLASS_AE_MULA2X4Q8X8CNV_H, + ICLASS_AE_MUL2X4Q8X8CNV_L, + ICLASS_AE_MULA2X4Q8X8CNV_L, + ICLASS_AE_MUL2X4Q8X16CNV, + ICLASS_AE_MULA2X4Q8X16CNV, + ICLASS_AE_MULQQ8X16CNV, + ICLASS_AE_MULAQQ8X16CNV, + ICLASS_AE_MUL4O8X8CNV_H, + ICLASS_AE_MULA4O8X8CNV_H, + ICLASS_AE_MUL4O8X8CNV_L, + ICLASS_AE_MULA4O8X8CNV_L, + ICLASS_AE_MUL4O8X16CNV_H, + ICLASS_AE_MULA4O8X16CNV_H, + ICLASS_AE_MUL4O8X16CNV_L, + ICLASS_AE_MULA4O8X16CNV_L, + ICLASS_AE_MUL8Q4X16CNV_H, + ICLASS_AE_MULA8Q4X16CNV_H, + ICLASS_AE_MUL8Q4X16CNV_L, + ICLASS_AE_MULA8Q4X16CNV_L, + ICLASS_AE_MUL2X4Q4X16CNV_H, + ICLASS_AE_MULA2X4Q4X16CNV_H, + ICLASS_AE_MUL2X4Q4X16CNV_L, + ICLASS_AE_MULA2X4Q4X16CNV_L, + ICLASS_AE_MULQQ4X16CNV_H, + ICLASS_AE_MULAQQ4X16CNV_H, + ICLASS_AE_MULQQ4X16CNV_L, + ICLASS_AE_MULAQQ4X16CNV_L, + ICLASS_AE_MUL4O4X16CNV_HH, + ICLASS_AE_MUL4O4X16CNV_HL, + ICLASS_AE_MUL4O4X16CNV_LH, + ICLASS_AE_MUL4O4X16CNV_LL, + ICLASS_AE_MULA4O4X16CNV_HH, + ICLASS_AE_MULA4O4X16CNV_HL, + ICLASS_AE_MULA4O4X16CNV_LH, + ICLASS_AE_MULA4O4X16CNV_LL, + ICLASS_AE_MULUU8Q8X8, + ICLASS_AE_MULAUU8Q8X8, + ICLASS_AE_MULUU4O8X8, + ICLASS_AE_MULAUU4O8X8, + ICLASS_AE_MULUU8Q8X8CNV_L, + ICLASS_AE_MULAUU8Q8X8CNV_L, + ICLASS_AE_MULUU8Q8X8CNV_H, + ICLASS_AE_MULAUU8Q8X8CNV_H, + ICLASS_AE_MULUU2X4Q8X8CNV_H, + ICLASS_AE_MULAUU2X4Q8X8CNV_H, + ICLASS_AE_MULUU2X4Q8X8CNV_L, + ICLASS_AE_MULAUU2X4Q8X8CNV_L, + ICLASS_AE_MULUU4O8X8CNV_H, + ICLASS_AE_MULAUU4O8X8CNV_H, + ICLASS_AE_MULUU4O8X8CNV_L, + ICLASS_AE_MULAUU4O8X8CNV_L, + ICLASS_AE_MULUS8Q8X8, + ICLASS_AE_MULAUS8Q8X8, + ICLASS_AE_MULUS8Q4X16, + ICLASS_AE_MULAUS8Q4X16, + ICLASS_AE_MULUS8Q8X16, + ICLASS_AE_MULAUS8Q8X16, + ICLASS_AE_MULUS8QW8X16, + ICLASS_AE_MULAUS8QW8X16, + ICLASS_AE_MULUS4O8X8, + ICLASS_AE_MULAUS4O8X8, + ICLASS_AE_MULUS4O4X16, + ICLASS_AE_MULAUS4O4X16, + ICLASS_AE_MULUS4O8X16, + ICLASS_AE_MULAUS4O8X16, + ICLASS_AE_MULUS4QW8X16, + ICLASS_AE_MULAUS4QW8X16, + ICLASS_AE_MULUS8Q8X8CNV_L, + ICLASS_AE_MULAUS8Q8X8CNV_L, + ICLASS_AE_MULUS8Q8X8CNV_H, + ICLASS_AE_MULAUS8Q8X8CNV_H, + ICLASS_AE_MULUS8Q8X16CNV, + ICLASS_AE_MULAUS8Q8X16CNV, + ICLASS_AE_MULUS2X4Q8X8CNV_H, + ICLASS_AE_MULAUS2X4Q8X8CNV_H, + ICLASS_AE_MULUS2X4Q8X8CNV_L, + ICLASS_AE_MULAUS2X4Q8X8CNV_L, + ICLASS_AE_MULUS2X4Q8X16CNV, + ICLASS_AE_MULAUS2X4Q8X16CNV, + ICLASS_AE_MULUSQQ8X16CNV, + ICLASS_AE_MULAUSQQ8X16CNV, + ICLASS_AE_MULUS4O8X8CNV_H, + ICLASS_AE_MULAUS4O8X8CNV_H, + ICLASS_AE_MULUS4O8X8CNV_L, + ICLASS_AE_MULAUS4O8X8CNV_L, + ICLASS_AE_MULUS4O8X16CNV_H, + ICLASS_AE_MULAUS4O8X16CNV_H, + ICLASS_AE_MULUS4O8X16CNV_L, + ICLASS_AE_MULAUS4O8X16CNV_L, + ICLASS_AE_MULUS8Q4X16CNV_H, + ICLASS_AE_MULAUS8Q4X16CNV_H, + ICLASS_AE_MULUS8Q4X16CNV_L, + ICLASS_AE_MULAUS8Q4X16CNV_L, + ICLASS_AE_MULUS2X4Q4X16CNV_H, + ICLASS_AE_MULAUS2X4Q4X16CNV_H, + ICLASS_AE_MULUS2X4Q4X16CNV_L, + ICLASS_AE_MULAUS2X4Q4X16CNV_L, + ICLASS_AE_MULUSQQ4X16CNV_H, + ICLASS_AE_MULAUSQQ4X16CNV_H, + ICLASS_AE_MULUSQQ4X16CNV_L, + ICLASS_AE_MULAUSQQ4X16CNV_L, + ICLASS_AE_MULUS4O4X16CNV_HH, + ICLASS_AE_MULUS4O4X16CNV_HL, + ICLASS_AE_MULUS4O4X16CNV_LH, + ICLASS_AE_MULUS4O4X16CNV_LL, + ICLASS_AE_MULAUS4O4X16CNV_HH, + ICLASS_AE_MULAUS4O4X16CNV_HL, + ICLASS_AE_MULAUS4O4X16CNV_LH, + ICLASS_AE_MULAUS4O4X16CNV_LL, + ICLASS_AE_MULSU8Q8X8, + ICLASS_AE_MULASU8Q8X8, + ICLASS_AE_MULSU4O8X8, + ICLASS_AE_MULASU4O8X8, + ICLASS_AE_MULSU8Q8X8CNV_L, + ICLASS_AE_MULASU8Q8X8CNV_L, + ICLASS_AE_MULSU8Q8X8CNV_H, + ICLASS_AE_MULASU8Q8X8CNV_H, + ICLASS_AE_MULSU2X4Q8X8CNV_H, + ICLASS_AE_MULASU2X4Q8X8CNV_H, + ICLASS_AE_MULSU2X4Q8X8CNV_L, + ICLASS_AE_MULASU2X4Q8X8CNV_L, + ICLASS_AE_MULSU4O8X8CNV_H, + ICLASS_AE_MULASU4O8X8CNV_H, + ICLASS_AE_MULSU4O8X8CNV_L, + ICLASS_AE_MULASU4O8X8CNV_L, + ICLASS_AE_MULUUZB8Q8X8, + ICLASS_AE_MULAUUZB8Q8X8, + ICLASS_AE_MULUUZB4O8X8, + ICLASS_AE_MULAUUZB4O8X8, + ICLASS_AE_MULUUZB8Q8X8CNV_L, + ICLASS_AE_MULAUUZB8Q8X8CNV_L, + ICLASS_AE_MULUUZB8Q8X8CNV_H, + ICLASS_AE_MULAUUZB8Q8X8CNV_H, + ICLASS_AE_MULUUZB2X4Q8X8CNV_H, + ICLASS_AE_MULAUUZB2X4Q8X8CNV_H, + ICLASS_AE_MULUUZB2X4Q8X8CNV_L, + ICLASS_AE_MULAUUZB2X4Q8X8CNV_L, + ICLASS_AE_MULUUZB4O8X8CNV_H, + ICLASS_AE_MULAUUZB4O8X8CNV_H, + ICLASS_AE_MULUUZB4O8X8CNV_L, + ICLASS_AE_MULAUUZB4O8X8CNV_L, + ICLASS_CVTSF16_L, + ICLASS_CVTSF16_H, + ICLASS_CVTF16S_L, + ICLASS_CVTF16S_H, + ICLASS_AE_MOVFCRFSRV, + ICLASS_AE_MOVVFCRFSR, + ICLASS_MOVT_S, + ICLASS_MOVF_S, + ICLASS_MOVEQZ_S, + ICLASS_MOVNEZ_S, + ICLASS_MOVGEZ_S, + ICLASS_MOVLTZ_S, + ICLASS_RFR, + ICLASS_WFR, + ICLASS_MUL_S, + ICLASS_MADD_S, + ICLASS_MSUB_S, + ICLASS_MSUBN_S, + ICLASS_MADDN_S, + ICLASS_ADD_S, + ICLASS_SUB_S, + ICLASS_OLE_S, + ICLASS_OLT_S, + ICLASS_OEQ_S, + ICLASS_UN_S, + ICLASS_ULE_S, + ICLASS_ULT_S, + ICLASS_UEQ_S, + ICLASS_NEXP01_S, + ICLASS_MKSADJ_S, + ICLASS_MKDADJ_S, + ICLASS_DIV0_S, + ICLASS_SQRT0_S, + ICLASS_RECIP0_S, + ICLASS_RSQRT0_S, + ICLASS_DIVN_S, + ICLASS_ADDEXP_S, + ICLASS_ADDEXPM_S, + ICLASS_MIN_S, + ICLASS_MAX_S, + ICLASS_MULMUX_S, + ICLASS_MADDMUX_S, + ICLASS_TRUNC_S, + ICLASS_UTRUNC_S, + ICLASS_TRUNC_SX2, + ICLASS_UTRUNC_SX2, + ICLASS_FICEIL_S, + ICLASS_FIFLOOR_S, + ICLASS_FIRINT_S, + ICLASS_FIROUND_S, + ICLASS_FITRUNC_S, + ICLASS_FLOAT_S, + ICLASS_UFLOAT_S, + ICLASS_FLOAT_SX2, + ICLASS_UFLOAT_SX2, + ICLASS_ABS_S, + ICLASS_NEG_S, + ICLASS_CONJC_S, + ICLASS_MULJC_S, + ICLASS_CONST_S, + ICLASS_CLSFY_S, + ICLASS_MINNUM_S, + ICLASS_MAXNUM_S, + ICLASS_ADDANDSUB_S, + ICLASS_ADDANDSUBJC_S, + ICLASS_ADD_HL_LH_S, + ICLASS_MADDA_S, + ICLASS_FREXP_S, + ICLASS_FLOATEXP_S, + ICLASS_MINNUMABS_S, + ICLASS_MAXNUMABS_S, + ICLASS_MULQ_S, + ICLASS_MADDQ_S, + ICLASS_MSUBQ_S, + ICLASS_MULMUXQ_S, + ICLASS_MADDMUXQ_S, + ICLASS_BMAXNUM_S, + ICLASS_BMINNUM_S, + ICLASS_BMAXNUMABS_S, + ICLASS_BMINNUMABS_S, + ICLASS_ABS_SX2X2, + ICLASS_NEG_SX2X2, + ICLASS_CONJC_SX2X2, + ICLASS_MULJC_SX2X2, + ICLASS_CONST_SX2X2, + ICLASS_ADD_SX2X2, + ICLASS_SUB_SX2X2, + ICLASS_MUL_SX2X2, + ICLASS_MADD_SX2X2, + ICLASS_MSUB_SX2X2, + ICLASS_MULMUX_SX2X2, + ICLASS_MADDMUX_SX2X2, + ICLASS_ABS_H, + ICLASS_ADDEXP_H, + ICLASS_ADDEXPM_H, + ICLASS_CLSFY_H, + ICLASS_CONJC_H, + ICLASS_CONST_H, + ICLASS_MIN_H, + ICLASS_MAX_H, + ICLASS_MINNUM_H, + ICLASS_MAXNUM_H, + ICLASS_MULJC_H, + ICLASS_NEG_H, + ICLASS_OEQ_H, + ICLASS_OLE_H, + ICLASS_OLT_H, + ICLASS_UEQ_H, + ICLASS_ULE_H, + ICLASS_ULT_H, + ICLASS_UN_H, + ICLASS_DIV0_H, + ICLASS_FICEIL_H, + ICLASS_FIFLOOR_H, + ICLASS_FIRINT_H, + ICLASS_FIROUND_H, + ICLASS_FITRUNC_H, + ICLASS_MKDADJ_H, + ICLASS_MKSADJ_H, + ICLASS_NEXP0_H, + ICLASS_NEXP01_H, + ICLASS_RECIP0_H, + ICLASS_RSQRT0_H, + ICLASS_SQRT0_H, + ICLASS_FLOAT16_H, + ICLASS_UFLOAT16_H, + ICLASS_TRUNC16_H, + ICLASS_UTRUNC16_H, + ICLASS_FLOAT16_HX4, + ICLASS_UFLOAT16_HX4, + ICLASS_TRUNC16_HX4, + ICLASS_UTRUNC16_HX4, + ICLASS_ADD_H, + ICLASS_SUB_H, + ICLASS_MUL_H, + ICLASS_MADD_H, + ICLASS_MSUB_H, + ICLASS_MADDN_H, + ICLASS_MSUBN_H, + ICLASS_DIVN_H, + ICLASS_RMINNUM_H, + ICLASS_RMAXNUM_H, + ICLASS_ABS_HX4X2, + ICLASS_NEG_HX4X2, + ICLASS_CONJC_HX4X2, + ICLASS_CONST_HX4X2, + ICLASS_MULJC_HX4X2, + ICLASS_ADD_HX4X2, + ICLASS_SUB_HX4X2, + ICLASS_MUL_HX4X2, + ICLASS_MADD_HX4X2, + ICLASS_MSUB_HX4X2, + ICLASS_MULQ_H, + ICLASS_MADDQ_H, + ICLASS_MULCNVH_HX4X2, + ICLASS_MULACNVH_HX4X2, + ICLASS_MULCNVL_HX4X2, + ICLASS_MULACNVL_HX4X2 +}; + + +/* Opcode encodings. */ + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408000; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf01d; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3400; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3500; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34800; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134800; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614800; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34900; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134900; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614900; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf06d; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03d; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00d; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e70; +} + +static void +Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e700; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_addi_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e0000; +} + +static void +Opcode_addi_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_addi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6e0000; + slotbuf[1] = 0; +} + +static void +Opcode_addi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01000; + slotbuf[1] = 0; +} + +static void +Opcode_addi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103e0000; + slotbuf[1] = 0; +} + +static void +Opcode_addi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_addi_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000; +} + +static void +Opcode_addi_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_addi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10360000; +} + +static void +Opcode_addi_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2642000; +} + +static void +Opcode_addi_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308000; +} + +static void +Opcode_addi_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2360000; +} + +static void +Opcode_addi_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340000; +} + +static void +Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb900000; +} + +static void +Opcode_addi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340000; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002; +} + +static void +Opcode_addmi_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f0000; +} + +static void +Opcode_addmi_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1250000; +} + +static void +Opcode_addmi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6f0000; + slotbuf[1] = 0; +} + +static void +Opcode_addmi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01200; + slotbuf[1] = 0; +} + +static void +Opcode_addmi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103e2000; + slotbuf[1] = 0; +} + +static void +Opcode_addmi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_addmi_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000; +} + +static void +Opcode_addmi_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_addmi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10370000; +} + +static void +Opcode_addmi_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2643000; +} + +static void +Opcode_addmi_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130c000; +} + +static void +Opcode_addmi_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2370000; +} + +static void +Opcode_addmi_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1350000; +} + +static void +Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb901000; +} + +static void +Opcode_addmi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1350000; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_add_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc48000; +} + +static void +Opcode_add_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144c000; +} + +static void +Opcode_add_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ba000; + slotbuf[1] = 0; +} + +static void +Opcode_add_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e12000; + slotbuf[1] = 0; +} + +static void +Opcode_add_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10724000; + slotbuf[1] = 0; +} + +static void +Opcode_add_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4000; +} + +static void +Opcode_add_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c4000; +} + +static void +Opcode_add_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c000; +} + +static void +Opcode_add_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10614000; +} + +static void +Opcode_add_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a09000; +} + +static void +Opcode_add_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1588000; +} + +static void +Opcode_add_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2750000; +} + +static void +Opcode_add_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154e000; +} + +static void +Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a79004; +} + +static void +Opcode_add_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154c000; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addx2_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc49000; +} + +static void +Opcode_addx2_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144d000; +} + +static void +Opcode_addx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74bb000; + slotbuf[1] = 0; +} + +static void +Opcode_addx2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1a000; + slotbuf[1] = 0; +} + +static void +Opcode_addx2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10725000; + slotbuf[1] = 0; +} + +static void +Opcode_addx2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a5000; +} + +static void +Opcode_addx2_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c5000; +} + +static void +Opcode_addx2_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29d000; +} + +static void +Opcode_addx2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10615000; +} + +static void +Opcode_addx2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0d000; +} + +static void +Opcode_addx2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c8000; +} + +static void +Opcode_addx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2751000; +} + +static void +Opcode_addx2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f000; +} + +static void +Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b79004; +} + +static void +Opcode_addx2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154d000; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_addx4_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc88000; +} + +static void +Opcode_addx4_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148c000; +} + +static void +Opcode_addx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74bc000; + slotbuf[1] = 0; +} + +static void +Opcode_addx4_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e42000; + slotbuf[1] = 0; +} + +static void +Opcode_addx4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10726000; + slotbuf[1] = 0; +} + +static void +Opcode_addx4_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6000; +} + +static void +Opcode_addx4_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c6000; +} + +static void +Opcode_addx4_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29e000; +} + +static void +Opcode_addx4_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10616000; +} + +static void +Opcode_addx4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a11000; +} + +static void +Opcode_addx4_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1589000; +} + +static void +Opcode_addx4_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2752000; +} + +static void +Opcode_addx4_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158e000; +} + +static void +Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9928000; +} + +static void +Opcode_addx4_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158c000; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_addx8_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc89000; +} + +static void +Opcode_addx8_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148d000; +} + +static void +Opcode_addx8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74bd000; + slotbuf[1] = 0; +} + +static void +Opcode_addx8_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e4a000; + slotbuf[1] = 0; +} + +static void +Opcode_addx8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10727000; + slotbuf[1] = 0; +} + +static void +Opcode_addx8_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a7000; +} + +static void +Opcode_addx8_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c7000; +} + +static void +Opcode_addx8_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29f000; +} + +static void +Opcode_addx8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10617000; +} + +static void +Opcode_addx8_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a15000; +} + +static void +Opcode_addx8_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c9000; +} + +static void +Opcode_addx8_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2753000; +} + +static void +Opcode_addx8_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158f000; +} + +static void +Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9968000; +} + +static void +Opcode_addx8_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158d000; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_sub_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4d000; +} + +static void +Opcode_sub_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1451000; +} + +static void +Opcode_sub_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74eb000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eba000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072a000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6000; +} + +static void +Opcode_sub_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d5000; +} + +static void +Opcode_sub_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ad000; +} + +static void +Opcode_sub_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064b000; +} + +static void +Opcode_sub_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a4d000; +} + +static void +Opcode_sub_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154d000; +} + +static void +Opcode_sub_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2761000; +} + +static void +Opcode_sub_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1553000; +} + +static void +Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a7900c; +} + +static void +Opcode_sub_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1551000; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_subx2_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8c000; +} + +static void +Opcode_subx2_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1490000; +} + +static void +Opcode_subx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ec000; + slotbuf[1] = 0; +} + +static void +Opcode_subx2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec2000; + slotbuf[1] = 0; +} + +static void +Opcode_subx2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072b000; + slotbuf[1] = 0; +} + +static void +Opcode_subx2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7000; +} + +static void +Opcode_subx2_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d6000; +} + +static void +Opcode_subx2_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ae000; +} + +static void +Opcode_subx2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064d000; +} + +static void +Opcode_subx2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a51000; +} + +static void +Opcode_subx2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158d000; +} + +static void +Opcode_subx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2762000; +} + +static void +Opcode_subx2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1592000; +} + +static void +Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b7100c; +} + +static void +Opcode_subx2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1590000; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_subx4_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8d000; +} + +static void +Opcode_subx4_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1491000; +} + +static void +Opcode_subx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ed000; + slotbuf[1] = 0; +} + +static void +Opcode_subx4_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eca000; + slotbuf[1] = 0; +} + +static void +Opcode_subx4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072c000; + slotbuf[1] = 0; +} + +static void +Opcode_subx4_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8000; +} + +static void +Opcode_subx4_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d7000; +} + +static void +Opcode_subx4_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2af000; +} + +static void +Opcode_subx4_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064f000; +} + +static void +Opcode_subx4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a55000; +} + +static void +Opcode_subx4_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cd000; +} + +static void +Opcode_subx4_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2763000; +} + +static void +Opcode_subx4_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1593000; +} + +static void +Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b7900c; +} + +static void +Opcode_subx4_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1591000; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_subx8_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xccc000; +} + +static void +Opcode_subx8_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d0000; +} + +static void +Opcode_subx8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ee000; + slotbuf[1] = 0; +} + +static void +Opcode_subx8_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ed2000; + slotbuf[1] = 0; +} + +static void +Opcode_subx8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072d000; + slotbuf[1] = 0; +} + +static void +Opcode_subx8_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b9000; +} + +static void +Opcode_subx8_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d8000; +} + +static void +Opcode_subx8_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0000; +} + +static void +Opcode_subx8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10651000; +} + +static void +Opcode_subx8_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a59000; +} + +static void +Opcode_subx8_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150e000; +} + +static void +Opcode_subx8_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2764000; +} + +static void +Opcode_subx8_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d2000; +} + +static void +Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9920008; +} + +static void +Opcode_subx8_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d0000; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_and_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc8000; +} + +static void +Opcode_and_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14cc000; +} + +static void +Opcode_and_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74be000; + slotbuf[1] = 0; +} + +static void +Opcode_and_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e52000; + slotbuf[1] = 0; +} + +static void +Opcode_and_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054b000; + slotbuf[1] = 0; +} + +static void +Opcode_and_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9000; +} + +static void +Opcode_and_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c8000; +} + +static void +Opcode_and_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0000; +} + +static void +Opcode_and_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10638000; +} + +static void +Opcode_and_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a19000; +} + +static void +Opcode_and_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150a000; +} + +static void +Opcode_and_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2754000; +} + +static void +Opcode_and_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ce000; +} + +static void +Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9920004; +} + +static void +Opcode_and_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cc000; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_or_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xccb000; +} + +static void +Opcode_or_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14cf000; +} + +static void +Opcode_or_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e7000; + slotbuf[1] = 0; +} + +static void +Opcode_or_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e9a000; + slotbuf[1] = 0; +} + +static void +Opcode_or_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1075d000; + slotbuf[1] = 0; +} + +static void +Opcode_or_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2000; +} + +static void +Opcode_or_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d1000; +} + +static void +Opcode_or_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a9000; +} + +static void +Opcode_or_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10643000; +} + +static void +Opcode_or_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_or_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a3d000; +} + +static void +Opcode_or_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154c000; +} + +static void +Opcode_or_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275d000; +} + +static void +Opcode_or_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d1000; +} + +static void +Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a79008; +} + +static void +Opcode_or_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cf000; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_xor_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xccd000; +} + +static void +Opcode_xor_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d1000; +} + +static void +Opcode_xor_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ef000; + slotbuf[1] = 0; +} + +static void +Opcode_xor_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eda000; + slotbuf[1] = 0; +} + +static void +Opcode_xor_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072e000; + slotbuf[1] = 0; +} + +static void +Opcode_xor_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba000; +} + +static void +Opcode_xor_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d9000; +} + +static void +Opcode_xor_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b1000; +} + +static void +Opcode_xor_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10653000; +} + +static void +Opcode_xor_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa01000; +} + +static void +Opcode_xor_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a5d000; +} + +static void +Opcode_xor_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154e000; +} + +static void +Opcode_xor_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2765000; +} + +static void +Opcode_xor_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d3000; +} + +static void +Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9960008; +} + +static void +Opcode_xor_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d1000; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6007; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe007; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4007; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5007; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd007; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1007; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa007; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb007; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2007; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3007; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc007; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9007; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_call0_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940000; +} + +static void +Opcode_call0_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d620000; + slotbuf[1] = 0; +} + +static void +Opcode_call0_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340000; + slotbuf[1] = 0; +} + +static void +Opcode_call0_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_call0_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0000; +} + +static void +Opcode_call0_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c0000; +} + +static void +Opcode_call0_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22c0000; +} + +static void +Opcode_call0_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7300000; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_callx0_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21003; +} + +static void +Opcode_callx0_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520205; + slotbuf[1] = 0; +} + +static void +Opcode_callx0_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10587bc0; + slotbuf[1] = 0; +} + +static void +Opcode_callx0_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6402; +} + +static void +Opcode_callx0_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d230; +} + +static void +Opcode_callx0_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d001; +} + +static void +Opcode_callx0_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781003; +} + +static void +Opcode_callx0_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e10e0; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_extui_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0000; +} + +static void +Opcode_extui_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_extui_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6a0000; + slotbuf[1] = 0; +} + +static void +Opcode_extui_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00000; + slotbuf[1] = 0; +} + +static void +Opcode_extui_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103c0000; + slotbuf[1] = 0; +} + +static void +Opcode_extui_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_extui_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_extui_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_extui_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340000; +} + +static void +Opcode_extui_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2640000; +} + +static void +Opcode_extui_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_extui_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2340000; +} + +static void +Opcode_extui_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_extui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa900000; +} + +static void +Opcode_extui_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_j_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_j_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d600000; + slotbuf[1] = 0; +} + +static void +Opcode_j_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300000; + slotbuf[1] = 0; +} + +static void +Opcode_j_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_j_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280000; +} + +static void +Opcode_j_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2580000; +} + +static void +Opcode_j_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2280000; +} + +static void +Opcode_j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7200000; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; +} + +static void +Opcode_jx_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21203; +} + +static void +Opcode_jx_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520a05; + slotbuf[1] = 0; +} + +static void +Opcode_jx_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef00; + slotbuf[1] = 0; +} + +static void +Opcode_jx_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6404; +} + +static void +Opcode_jx_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d430; +} + +static void +Opcode_jx_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d201; +} + +static void +Opcode_jx_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781203; +} + +static void +Opcode_jx_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e12e0; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1002; +} + +static void +Opcode_l16ui_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa40000; +} + +static void +Opcode_l16ui_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_l16ui_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7c0000; + slotbuf[1] = 0; +} + +static void +Opcode_l16ui_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c02200; + slotbuf[1] = 0; +} + +static void +Opcode_l16ui_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10402000; + slotbuf[1] = 0; +} + +static void +Opcode_l16ui_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_l16ui_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x350000; +} + +static void +Opcode_l16ui_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250000; +} + +static void +Opcode_l16ui_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103c0000; +} + +static void +Opcode_l16ui_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c0000; +} + +static void +Opcode_l16ui_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1314000; +} + +static void +Opcode_l16ui_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2390000; +} + +static void +Opcode_l16ui_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c0000; +} + +static void +Opcode_l16ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb01000; +} + +static void +Opcode_l16ui_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c0000; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9002; +} + +static void +Opcode_l16si_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_l16si_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_l16si_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d780000; + slotbuf[1] = 0; +} + +static void +Opcode_l16si_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c02000; + slotbuf[1] = 0; +} + +static void +Opcode_l16si_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10400000; + slotbuf[1] = 0; +} + +static void +Opcode_l16si_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_l16si_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_l16si_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_l16si_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103b0000; +} + +static void +Opcode_l16si_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2680000; +} + +static void +Opcode_l16si_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1310000; +} + +static void +Opcode_l16si_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2380000; +} + +static void +Opcode_l16si_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380000; +} + +static void +Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb00000; +} + +static void +Opcode_l16si_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380000; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2002; +} + +static void +Opcode_l32i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa80000; +} + +static void +Opcode_l32i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1290000; +} + +static void +Opcode_l32i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d790000; + slotbuf[1] = 0; +} + +static void +Opcode_l32i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c03000; + slotbuf[1] = 0; +} + +static void +Opcode_l32i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10420000; + slotbuf[1] = 0; +} + +static void +Opcode_l32i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_l32i_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360000; +} + +static void +Opcode_l32i_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260000; +} + +static void +Opcode_l32i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103d0000; +} + +static void +Opcode_l32i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2681000; +} + +static void +Opcode_l32i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318000; +} + +static void +Opcode_l32i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23a0000; +} + +static void +Opcode_l32i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1390000; +} + +static void +Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7320000; +} + +static void +Opcode_l32i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1390000; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_l32r_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_l32r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7200000; + slotbuf[1] = 0; +} + +static void +Opcode_l32r_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0; +} + +static void +Opcode_l32r_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_l32r_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; +} + +static void +Opcode_l32r_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_l32r_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_l32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000000; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_l8ui_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac0000; +} + +static void +Opcode_l8ui_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12d0000; +} + +static void +Opcode_l8ui_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7d0000; + slotbuf[1] = 0; +} + +static void +Opcode_l8ui_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c03200; + slotbuf[1] = 0; +} + +static void +Opcode_l8ui_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10422000; + slotbuf[1] = 0; +} + +static void +Opcode_l8ui_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_l8ui_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370000; +} + +static void +Opcode_l8ui_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270000; +} + +static void +Opcode_l8ui_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103e0000; +} + +static void +Opcode_l8ui_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c1000; +} + +static void +Opcode_l8ui_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131c000; +} + +static void +Opcode_l8ui_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23b0000; +} + +static void +Opcode_l8ui_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d0000; +} + +static void +Opcode_l8ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7321000; +} + +static void +Opcode_l8ui_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d0000; +} + +static void +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8076; +} + +static void +Opcode_loop_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_loop_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520000; + slotbuf[1] = 0; +} + +static void +Opcode_loop_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10582000; + slotbuf[1] = 0; +} + +static void +Opcode_loop_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0000; +} + +static void +Opcode_loop_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690000; +} + +static void +Opcode_loop_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac1000; +} + +static void +Opcode_loop_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2780000; +} + +static void +Opcode_loop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b20000; +} + +static void +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa076; +} + +static void +Opcode_loopgtz_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20001; +} + +static void +Opcode_loopgtz_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520001; + slotbuf[1] = 0; +} + +static void +Opcode_loopgtz_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10582040; + slotbuf[1] = 0; +} + +static void +Opcode_loopgtz_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0001; +} + +static void +Opcode_loopgtz_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690010; +} + +static void +Opcode_loopgtz_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac1001; +} + +static void +Opcode_loopgtz_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2780001; +} + +static void +Opcode_loopgtz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b20040; +} + +static void +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9076; +} + +static void +Opcode_loopnez_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20002; +} + +static void +Opcode_loopnez_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520002; + slotbuf[1] = 0; +} + +static void +Opcode_loopnez_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10582080; + slotbuf[1] = 0; +} + +static void +Opcode_loopnez_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0002; +} + +static void +Opcode_loopnez_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690020; +} + +static void +Opcode_loopnez_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac1002; +} + +static void +Opcode_loopnez_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2780002; +} + +static void +Opcode_loopnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b20080; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa002; +} + +static void +Opcode_movi_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad0000; +} + +static void +Opcode_movi_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1220000; +} + +static void +Opcode_movi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7f0000; + slotbuf[1] = 0; +} + +static void +Opcode_movi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04000; + slotbuf[1] = 0; +} + +static void +Opcode_movi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480000; + slotbuf[1] = 0; +} + +static void +Opcode_movi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_movi_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0000; +} + +static void +Opcode_movi_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_movi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10450000; +} + +static void +Opcode_movi_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c3000; +} + +static void +Opcode_movi_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1320000; +} + +static void +Opcode_movi_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23f0000; +} + +static void +Opcode_movi_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1320000; +} + +static void +Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9820000; +} + +static void +Opcode_movi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1320000; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830000; +} + +static void +Opcode_moveqz_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4b000; +} + +static void +Opcode_moveqz_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144f000; +} + +static void +Opcode_moveqz_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e3000; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e7a000; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10755000; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae000; +} + +static void +Opcode_moveqz_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3cd000; +} + +static void +Opcode_moveqz_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a5000; +} + +static void +Opcode_moveqz_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063d000; +} + +static void +Opcode_moveqz_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a2d000; +} + +static void +Opcode_moveqz_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154b000; +} + +static void +Opcode_moveqz_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2759000; +} + +static void +Opcode_moveqz_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1551000; +} + +static void +Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9978008; +} + +static void +Opcode_moveqz_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f000; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30000; +} + +static void +Opcode_movgez_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8a000; +} + +static void +Opcode_movgez_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148e000; +} + +static void +Opcode_movgez_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e4000; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e82000; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10757000; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1af000; +} + +static void +Opcode_movgez_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ce000; +} + +static void +Opcode_movgez_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a6000; +} + +static void +Opcode_movgez_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063e000; +} + +static void +Opcode_movgez_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a31000; +} + +static void +Opcode_movgez_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158b000; +} + +static void +Opcode_movgez_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275a000; +} + +static void +Opcode_movgez_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1590000; +} + +static void +Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x997000c; +} + +static void +Opcode_movgez_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158e000; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_movltz_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8b000; +} + +static void +Opcode_movltz_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148f000; +} + +static void +Opcode_movltz_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e5000; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e8a000; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10759000; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_movltz_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3cf000; +} + +static void +Opcode_movltz_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a7000; +} + +static void +Opcode_movltz_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063f000; +} + +static void +Opcode_movltz_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a35000; +} + +static void +Opcode_movltz_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cb000; +} + +static void +Opcode_movltz_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275b000; +} + +static void +Opcode_movltz_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1591000; +} + +static void +Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x997800c; +} + +static void +Opcode_movltz_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158f000; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_movnez_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcca000; +} + +static void +Opcode_movnez_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14ce000; +} + +static void +Opcode_movnez_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e6000; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e92000; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1075b000; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1000; +} + +static void +Opcode_movnez_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d0000; +} + +static void +Opcode_movnez_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8000; +} + +static void +Opcode_movnez_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10641000; +} + +static void +Opcode_movnez_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a39000; +} + +static void +Opcode_movnez_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150c000; +} + +static void +Opcode_movnez_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275c000; +} + +static void +Opcode_movnez_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d0000; +} + +static void +Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a71008; +} + +static void +Opcode_movnez_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ce000; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600100; +} + +static void +Opcode_abs_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc12020; +} + +static void +Opcode_abs_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1453000; +} + +static void +Opcode_abs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191f6030; + slotbuf[1] = 0; +} + +static void +Opcode_abs_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e14000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a00e; + slotbuf[1] = 0; +} + +static void +Opcode_abs_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8000; +} + +static void +Opcode_abs_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e5000; +} + +static void +Opcode_abs_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6000; +} + +static void +Opcode_abs_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a200b; +} + +static void +Opcode_abs_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a89000; +} + +static void +Opcode_abs_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f000; +} + +static void +Opcode_abs_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c6010; +} + +static void +Opcode_abs_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1555000; +} + +static void +Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a3000; +} + +static void +Opcode_abs_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1521000; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_neg_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc12030; +} + +static void +Opcode_neg_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1453010; +} + +static void +Opcode_neg_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191f7030; + slotbuf[1] = 0; +} + +static void +Opcode_neg_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e14010; + slotbuf[1] = 0; +} + +static void +Opcode_neg_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071b00f; + slotbuf[1] = 0; +} + +static void +Opcode_neg_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8020; +} + +static void +Opcode_neg_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e5020; +} + +static void +Opcode_neg_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6010; +} + +static void +Opcode_neg_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a300b; +} + +static void +Opcode_neg_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a89010; +} + +static void +Opcode_neg_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f010; +} + +static void +Opcode_neg_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c7010; +} + +static void +Opcode_neg_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1555010; +} + +static void +Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a3002; +} + +static void +Opcode_neg_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1521020; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f0; +} + +static void +Opcode_nop_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21903; +} + +static void +Opcode_nop_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1496109; +} + +static void +Opcode_nop_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000065; + slotbuf[1] = 0x6; +} + +static void +Opcode_nop_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82164012; + slotbuf[1] = 0x5; +} + +static void +Opcode_nop_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b48fb5; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c702; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63f8c00; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef74; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9603; +} + +static void +Opcode_nop_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e640b; +} + +static void +Opcode_nop_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7306; +} + +static void +Opcode_nop_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x568001; +} + +static void +Opcode_nop_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40b84a0; +} + +static void +Opcode_nop_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x510040; +} + +static void +Opcode_nop_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069db31; +} + +static void +Opcode_nop_Slot_ae5_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_nop_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700212; +} + +static void +Opcode_nop_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133b800; +} + +static void +Opcode_nop_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08940; +} + +static void +Opcode_nop_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130060; +} + +static void +Opcode_nop_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000021; + slotbuf[1] = 0x2; +} + +static void +Opcode_nop_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x692180; +} + +static void +Opcode_nop_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x692180; +} + +static void +Opcode_nop_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00560; + slotbuf[1] = 0xe; +} + +static void +Opcode_nop_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000801; + slotbuf[1] = 0xe; +} + +static void +Opcode_nop_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d901; +} + +static void +Opcode_nop_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d260f; +} + +static void +Opcode_nop_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200001; + slotbuf[1] = 0x229860; +} + +static void +Opcode_nop_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781903; +} + +static void +Opcode_nop_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159690b; +} + +static void +Opcode_nop_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c10041; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d35801d; +} + +static void +Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab20055; +} + +static void +Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14b610c; +} + +static void +Opcode_nop_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00427; +} + +static void +Opcode_nop_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80426862; + slotbuf[1] = 0xe; +} + +static void +Opcode_l32ex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf14000; +} + +static void +Opcode_s32ex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf15000; +} + +static void +Opcode_getex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40a000; +} + +static void +Opcode_clrex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3120; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_ret_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21303; +} + +static void +Opcode_ret_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520e05; + slotbuf[1] = 0; +} + +static void +Opcode_ret_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef10; + slotbuf[1] = 0; +} + +static void +Opcode_ret_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6405; +} + +static void +Opcode_ret_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d530; +} + +static void +Opcode_ret_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d301; +} + +static void +Opcode_ret_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781303; +} + +static void +Opcode_ret_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e13e0; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5002; +} + +static void +Opcode_s16i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_s16i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7a0000; + slotbuf[1] = 0; +} + +static void +Opcode_s16i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10440000; + slotbuf[1] = 0; +} + +static void +Opcode_s16i_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_s16i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103f0000; +} + +static void +Opcode_s16i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2682000; +} + +static void +Opcode_s16i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23c0000; +} + +static void +Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7330000; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002; +} + +static void +Opcode_s32i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa50000; +} + +static void +Opcode_s32i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7e0000; + slotbuf[1] = 0; +} + +static void +Opcode_s32i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10442000; + slotbuf[1] = 0; +} + +static void +Opcode_s32i_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x390000; +} + +static void +Opcode_s32i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10400000; +} + +static void +Opcode_s32i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c2000; +} + +static void +Opcode_s32i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23d0000; +} + +static void +Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7331000; +} + +static void +Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590000; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_s8i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa90000; +} + +static void +Opcode_s8i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7b0000; + slotbuf[1] = 0; +} + +static void +Opcode_s8i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10460000; + slotbuf[1] = 0; +} + +static void +Opcode_s8i_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0000; +} + +static void +Opcode_s8i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10410000; +} + +static void +Opcode_s8i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2683000; +} + +static void +Opcode_s8i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23e0000; +} + +static void +Opcode_s8i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa980000; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403000; +} + +static void +Opcode_ssa8b_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21503; +} + +static void +Opcode_ssa8b_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145420a; +} + +static void +Opcode_ssa8b_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7521605; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8b_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00c03; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8b_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef30; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8b_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9103; +} + +static void +Opcode_ssa8b_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6407; +} + +static void +Opcode_ssa8b_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7302; +} + +static void +Opcode_ssa8b_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d730; +} + +static void +Opcode_ssa8b_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d501; +} + +static void +Opcode_ssa8b_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d220f; +} + +static void +Opcode_ssa8b_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781503; +} + +static void +Opcode_ssa8b_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556a0b; +} + +static void +Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e15e0; +} + +static void +Opcode_ssa8b_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d7204; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402000; +} + +static void +Opcode_ssa8l_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21603; +} + +static void +Opcode_ssa8l_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145430a; +} + +static void +Opcode_ssa8l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7521a05; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f08c03; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef40; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8l_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9503; +} + +static void +Opcode_ssa8l_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6408; +} + +static void +Opcode_ssa8l_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7303; +} + +static void +Opcode_ssa8l_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d830; +} + +static void +Opcode_ssa8l_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d601; +} + +static void +Opcode_ssa8l_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d230f; +} + +static void +Opcode_ssa8l_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781603; +} + +static void +Opcode_ssa8l_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556b0b; +} + +static void +Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e16e0; +} + +static void +Opcode_ssa8l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d7304; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401000; +} + +static void +Opcode_ssl_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21703; +} + +static void +Opcode_ssl_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416109; +} + +static void +Opcode_ssl_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7521e05; + slotbuf[1] = 0; +} + +static void +Opcode_ssl_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c402; + slotbuf[1] = 0; +} + +static void +Opcode_ssl_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef50; + slotbuf[1] = 0; +} + +static void +Opcode_ssl_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9203; +} + +static void +Opcode_ssl_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6409; +} + +static void +Opcode_ssl_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7304; +} + +static void +Opcode_ssl_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d930; +} + +static void +Opcode_ssl_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d701; +} + +static void +Opcode_ssl_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d240f; +} + +static void +Opcode_ssl_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781703; +} + +static void +Opcode_ssl_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151690b; +} + +static void +Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e17e0; +} + +static void +Opcode_ssl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143610c; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ssr_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21803; +} + +static void +Opcode_ssr_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1456109; +} + +static void +Opcode_ssr_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a4af00; + slotbuf[1] = 0; +} + +static void +Opcode_ssr_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c502; + slotbuf[1] = 0; +} + +static void +Opcode_ssr_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef60; + slotbuf[1] = 0; +} + +static void +Opcode_ssr_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9303; +} + +static void +Opcode_ssr_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e640a; +} + +static void +Opcode_ssr_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7305; +} + +static void +Opcode_ssr_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069da30; +} + +static void +Opcode_ssr_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d801; +} + +static void +Opcode_ssr_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d250f; +} + +static void +Opcode_ssr_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781803; +} + +static void +Opcode_ssr_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x155690b; +} + +static void +Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e18e0; +} + +static void +Opcode_ssr_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x147610c; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404000; +} + +static void +Opcode_ssai_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc92520; +} + +static void +Opcode_ssai_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145400a; +} + +static void +Opcode_ssai_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19034310; + slotbuf[1] = 0; +} + +static void +Opcode_ssai_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00c01; + slotbuf[1] = 0; +} + +static void +Opcode_ssai_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afa0a; + slotbuf[1] = 0; +} + +static void +Opcode_ssai_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9003; +} + +static void +Opcode_ssai_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6400; +} + +static void +Opcode_ssai_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7300; +} + +static void +Opcode_ssai_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687701; +} + +static void +Opcode_ssai_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a88640; +} + +static void +Opcode_ssai_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d200f; +} + +static void +Opcode_ssai_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b520; +} + +static void +Opcode_ssai_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516a0b; +} + +static void +Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa60005; +} + +static void +Opcode_ssai_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d7004; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_sll_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20003; +} + +static void +Opcode_sll_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x141400a; +} + +static void +Opcode_sll_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x752c003; + slotbuf[1] = 0; +} + +static void +Opcode_sll_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0c002; + slotbuf[1] = 0; +} + +static void +Opcode_sll_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105860c0; + slotbuf[1] = 0; +} + +static void +Opcode_sll_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9000; +} + +static void +Opcode_sll_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0003; +} + +static void +Opcode_sll_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b8000; +} + +static void +Opcode_sll_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069c030; +} + +static void +Opcode_sll_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d000; +} + +static void +Opcode_sll_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159200f; +} + +static void +Opcode_sll_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2780003; +} + +static void +Opcode_sll_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151600a; +} + +static void +Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e10e0; +} + +static void +Opcode_sll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1596004; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_src_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4c000; +} + +static void +Opcode_src_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1450000; +} + +static void +Opcode_src_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ea000; + slotbuf[1] = 0; +} + +static void +Opcode_src_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eb2000; + slotbuf[1] = 0; +} + +static void +Opcode_src_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10729000; + slotbuf[1] = 0; +} + +static void +Opcode_src_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b5000; +} + +static void +Opcode_src_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d4000; +} + +static void +Opcode_src_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac000; +} + +static void +Opcode_src_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10649000; +} + +static void +Opcode_src_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a49000; +} + +static void +Opcode_src_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150d000; +} + +static void +Opcode_src_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2760000; +} + +static void +Opcode_src_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1552000; +} + +static void +Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a7100c; +} + +static void +Opcode_src_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1550000; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10000; +} + +static void +Opcode_sra_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc52020; +} + +static void +Opcode_sra_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1453020; +} + +static void +Opcode_sra_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191fc030; + slotbuf[1] = 0; +} + +static void +Opcode_sra_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e14020; + slotbuf[1] = 0; +} + +static void +Opcode_sra_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af000; + slotbuf[1] = 0; +} + +static void +Opcode_sra_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8030; +} + +static void +Opcode_sra_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e5010; +} + +static void +Opcode_sra_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6020; +} + +static void +Opcode_sra_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2007; +} + +static void +Opcode_sra_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a89020; +} + +static void +Opcode_sra_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f020; +} + +static void +Opcode_sra_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b000; +} + +static void +Opcode_sra_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1555020; +} + +static void +Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a3003; +} + +static void +Opcode_sra_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1521030; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_srl_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc52030; +} + +static void +Opcode_srl_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1453030; +} + +static void +Opcode_srl_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191fe030; + slotbuf[1] = 0; +} + +static void +Opcode_srl_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e14030; + slotbuf[1] = 0; +} + +static void +Opcode_srl_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af001; + slotbuf[1] = 0; +} + +static void +Opcode_srl_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8040; +} + +static void +Opcode_srl_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e5030; +} + +static void +Opcode_srl_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6030; +} + +static void +Opcode_srl_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a200f; +} + +static void +Opcode_srl_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a89030; +} + +static void +Opcode_srl_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f030; +} + +static void +Opcode_srl_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b010; +} + +static void +Opcode_srl_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1555030; +} + +static void +Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a3000; +} + +static void +Opcode_srl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1521040; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_slli_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc6000; +} + +static void +Opcode_slli_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14ca000; +} + +static void +Opcode_slli_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74b6000; + slotbuf[1] = 0; +} + +static void +Opcode_slli_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e22000; + slotbuf[1] = 0; +} + +static void +Opcode_slli_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10542000; + slotbuf[1] = 0; +} + +static void +Opcode_slli_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_slli_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_slli_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290000; +} + +static void +Opcode_slli_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10610000; +} + +static void +Opcode_slli_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a01000; +} + +static void +Opcode_slli_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1508000; +} + +static void +Opcode_slli_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x274c000; +} + +static void +Opcode_slli_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cc000; +} + +static void +Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9920000; +} + +static void +Opcode_slli_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ca000; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_srai_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc08000; +} + +static void +Opcode_srai_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140c000; +} + +static void +Opcode_srai_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74b8000; + slotbuf[1] = 0; +} + +static void +Opcode_srai_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e02000; + slotbuf[1] = 0; +} + +static void +Opcode_srai_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10546000; + slotbuf[1] = 0; +} + +static void +Opcode_srai_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2000; +} + +static void +Opcode_srai_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c2000; +} + +static void +Opcode_srai_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x292000; +} + +static void +Opcode_srai_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10612000; +} + +static void +Opcode_srai_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000e0; +} + +static void +Opcode_srai_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1548000; +} + +static void +Opcode_srai_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x274e000; +} + +static void +Opcode_srai_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150e000; +} + +static void +Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9970004; +} + +static void +Opcode_srai_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150c000; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_srli_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8e000; +} + +static void +Opcode_srli_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1452000; +} + +static void +Opcode_srli_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f4000; + slotbuf[1] = 0; +} + +static void +Opcode_srli_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ef2000; + slotbuf[1] = 0; +} + +static void +Opcode_srli_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056a000; + slotbuf[1] = 0; +} + +static void +Opcode_srli_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bd000; +} + +static void +Opcode_srli_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3de000; +} + +static void +Opcode_srli_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b4000; +} + +static void +Opcode_srli_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065d000; +} + +static void +Opcode_srli_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a71000; +} + +static void +Opcode_srli_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150f000; +} + +static void +Opcode_srli_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276a000; +} + +static void +Opcode_srli_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1554000; +} + +static void +Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x992800c; +} + +static void +Opcode_srli_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1552000; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d0; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2030; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2020; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2010; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30100; +} + +static void +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610100; +} + +static void +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200; +} + +static void +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610200; +} + +static void +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30300; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610300; +} + +static void +Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36100; +} + +static void +Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136100; +} + +static void +Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616100; +} + +static void +Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b000; +} + +static void +Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e600; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e600; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e600; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b100; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b100; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b100; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d100; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d100; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d100; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b200; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b200; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b200; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d200; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d200; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d200; +} + +static void +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b300; +} + +static void +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b300; +} + +static void +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b300; +} + +static void +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d300; +} + +static void +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d300; +} + +static void +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d300; +} + +static void +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b400; +} + +static void +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b400; +} + +static void +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b400; +} + +static void +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d400; +} + +static void +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d400; +} + +static void +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d400; +} + +static void +Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b500; +} + +static void +Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b500; +} + +static void +Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b500; +} + +static void +Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d500; +} + +static void +Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d500; +} + +static void +Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d500; +} + +static void +Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b600; +} + +static void +Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b600; +} + +static void +Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b600; +} + +static void +Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d600; +} + +static void +Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d600; +} + +static void +Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d600; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c200; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c200; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c200; +} + +static void +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c300; +} + +static void +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c300; +} + +static void +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c300; +} + +static void +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400; +} + +static void +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c400; +} + +static void +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c400; +} + +static void +Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c500; +} + +static void +Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c500; +} + +static void +Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c500; +} + +static void +Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c600; +} + +static void +Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c600; +} + +static void +Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c600; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ee00; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee00; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ee00; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c000; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e800; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e800; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e800; +} + +static void +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f400; +} + +static void +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f400; +} + +static void +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f400; +} + +static void +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f500; +} + +static void +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f500; +} + +static void +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f500; +} + +static void +Opcode_rsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f600; +} + +static void +Opcode_wsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f600; +} + +static void +Opcode_xsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f600; +} + +static void +Opcode_rsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f700; +} + +static void +Opcode_wsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f700; +} + +static void +Opcode_xsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f700; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3eb00; +} + +static void +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e700; +} + +static void +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e700; +} + +static void +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e700; +} + +static void +Opcode_rsr_mpucfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35c00; +} + +static void +Opcode_wsr_mpucfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135c00; +} + +static void +Opcode_salt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720000; +} + +static void +Opcode_salt_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c000; +} + +static void +Opcode_salt_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1410000; +} + +static void +Opcode_salt_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e8000; + slotbuf[1] = 0; +} + +static void +Opcode_salt_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea2000; + slotbuf[1] = 0; +} + +static void +Opcode_salt_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1075f000; + slotbuf[1] = 0; +} + +static void +Opcode_salt_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b3000; +} + +static void +Opcode_salt_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d2000; +} + +static void +Opcode_salt_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2aa000; +} + +static void +Opcode_salt_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10645000; +} + +static void +Opcode_salt_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a41000; +} + +static void +Opcode_salt_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158c000; +} + +static void +Opcode_salt_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275e000; +} + +static void +Opcode_salt_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512000; +} + +static void +Opcode_salt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b71008; +} + +static void +Opcode_salt_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510000; +} + +static void +Opcode_saltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x620000; +} + +static void +Opcode_saltu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0d000; +} + +static void +Opcode_saltu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1411000; +} + +static void +Opcode_saltu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e9000; + slotbuf[1] = 0; +} + +static void +Opcode_saltu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eaa000; + slotbuf[1] = 0; +} + +static void +Opcode_saltu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10728000; + slotbuf[1] = 0; +} + +static void +Opcode_saltu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b4000; +} + +static void +Opcode_saltu_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d3000; +} + +static void +Opcode_saltu_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ab000; +} + +static void +Opcode_saltu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10647000; +} + +static void +Opcode_saltu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a45000; +} + +static void +Opcode_saltu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cc000; +} + +static void +Opcode_saltu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275f000; +} + +static void +Opcode_saltu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1513000; +} + +static void +Opcode_saltu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b79008; +} + +static void +Opcode_saltu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1511000; +} + +static void +Opcode_rsr_opmode_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37700; +} + +static void +Opcode_wsr_opmode_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137700; +} + +static void +Opcode_xsr_opmode_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x617700; +} + +static void +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820000; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3010; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e200; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e200; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e300; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e400; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e400; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf02d; +} + +static void +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139000; +} + +static void +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619000; +} + +static void +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a000; +} + +static void +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a000; +} + +static void +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39100; +} + +static void +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139100; +} + +static void +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619100; +} + +static void +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a100; +} + +static void +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a100; +} + +static void +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a100; +} + +static void +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618000; +} + +static void +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38100; +} + +static void +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138100; +} + +static void +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618100; +} + +static void +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000; +} + +static void +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136000; +} + +static void +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616000; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e900; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e900; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e900; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ec00; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec00; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ec00; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ed00; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ed00; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ed00; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36800; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136800; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616800; +} + +static void +Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e0; +} + +static void +Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f0; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e000; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e010; +} + +static void +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135900; +} + +static void +Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_andb_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8f000; +} + +static void +Opcode_andb_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f5000; + slotbuf[1] = 0; +} + +static void +Opcode_andb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056b000; + slotbuf[1] = 0; +} + +static void +Opcode_andb_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3df000; +} + +static void +Opcode_andb_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10661000; +} + +static void +Opcode_andb_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a75000; +} + +static void +Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996800c; +} + +static void +Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_andbc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcce000; +} + +static void +Opcode_andbc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f6000; + slotbuf[1] = 0; +} + +static void +Opcode_andbc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056e000; + slotbuf[1] = 0; +} + +static void +Opcode_andbc_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0000; +} + +static void +Opcode_andbc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10663000; +} + +static void +Opcode_andbc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a79000; +} + +static void +Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9921000; +} + +static void +Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_orb_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xccf000; +} + +static void +Opcode_orb_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f7000; + slotbuf[1] = 0; +} + +static void +Opcode_orb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056f000; + slotbuf[1] = 0; +} + +static void +Opcode_orb_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e1000; +} + +static void +Opcode_orb_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10665000; +} + +static void +Opcode_orb_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a7d000; +} + +static void +Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9961000; +} + +static void +Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000; +} + +static void +Opcode_orbc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_orbc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f8000; + slotbuf[1] = 0; +} + +static void +Opcode_orbc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10572000; + slotbuf[1] = 0; +} + +static void +Opcode_orbc_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e2000; +} + +static void +Opcode_orbc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10667000; +} + +static void +Opcode_orbc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a81000; +} + +static void +Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929000; +} + +static void +Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420000; +} + +static void +Opcode_xorb_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc11000; +} + +static void +Opcode_xorb_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f9000; + slotbuf[1] = 0; +} + +static void +Opcode_xorb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10573000; + slotbuf[1] = 0; +} + +static void +Opcode_xorb_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e3000; +} + +static void +Opcode_xorb_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10669000; +} + +static void +Opcode_xorb_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a85000; +} + +static void +Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9969000; +} + +static void +Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_all4_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc92020; +} + +static void +Opcode_all4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19034010; + slotbuf[1] = 0; +} + +static void +Opcode_all4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af00a; + slotbuf[1] = 0; +} + +static void +Opcode_all4_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6300; +} + +static void +Opcode_all4_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687602; +} + +static void +Opcode_all4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80640; +} + +static void +Opcode_all4_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b020; +} + +static void +Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a7400; +} + +static void +Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_any4_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc92030; +} + +static void +Opcode_any4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19036010; + slotbuf[1] = 0; +} + +static void +Opcode_any4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af00b; + slotbuf[1] = 0; +} + +static void +Opcode_any4_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6340; +} + +static void +Opcode_any4_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687603; +} + +static void +Opcode_any4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80650; +} + +static void +Opcode_any4_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b030; +} + +static void +Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a7401; +} + +static void +Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000; +} + +static void +Opcode_all8_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc92420; +} + +static void +Opcode_all8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19034210; + slotbuf[1] = 0; +} + +static void +Opcode_all8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af80a; + slotbuf[1] = 0; +} + +static void +Opcode_all8_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6380; +} + +static void +Opcode_all8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687700; +} + +static void +Opcode_all8_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80660; +} + +static void +Opcode_all8_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b420; +} + +static void +Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a7402; +} + +static void +Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_any8_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc92430; +} + +static void +Opcode_any8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19036210; + slotbuf[1] = 0; +} + +static void +Opcode_any8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af80b; + slotbuf[1] = 0; +} + +static void +Opcode_any8_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6390; +} + +static void +Opcode_any8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687704; +} + +static void +Opcode_any8_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80670; +} + +static void +Opcode_any8_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b430; +} + +static void +Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a7403; +} + +static void +Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76; +} + +static void +Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1076; +} + +static void +Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc30000; +} + +static void +Opcode_movf_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0e000; +} + +static void +Opcode_movf_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f0000; + slotbuf[1] = 0; +} + +static void +Opcode_movf_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055f000; + slotbuf[1] = 0; +} + +static void +Opcode_movf_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3da000; +} + +static void +Opcode_movf_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10655000; +} + +static void +Opcode_movf_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a61000; +} + +static void +Opcode_movf_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2766000; +} + +static void +Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9928008; +} + +static void +Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30000; +} + +static void +Opcode_movt_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0f000; +} + +static void +Opcode_movt_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f1000; + slotbuf[1] = 0; +} + +static void +Opcode_movt_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10562000; + slotbuf[1] = 0; +} + +static void +Opcode_movt_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3db000; +} + +static void +Opcode_movt_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10657000; +} + +static void +Opcode_movt_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a65000; +} + +static void +Opcode_movt_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2767000; +} + +static void +Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9968008; +} + +static void +Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30400; +} + +static void +Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130400; +} + +static void +Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610400; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ea00; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea00; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ea00; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f000; +} + +static void +Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f100; +} + +static void +Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f100; +} + +static void +Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f100; +} + +static void +Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f200; +} + +static void +Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f200; +} + +static void +Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f200; +} + +static void +Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e2; +} + +static void +Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70c2; +} + +static void +Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270d2; +} + +static void +Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370d2; +} + +static void +Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70d2; +} + +static void +Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f2; +} + +static void +Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10000; +} + +static void +Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf12000; +} + +static void +Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf11000; +} + +static void +Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13000; +} + +static void +Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7042; +} + +static void +Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7052; +} + +static void +Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf7082; +} + +static void +Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x47082; +} + +static void +Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57082; +} + +static void +Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7062; +} + +static void +Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7072; +} + +static void +Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7002; +} + +static void +Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7022; +} + +static void +Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7012; +} + +static void +Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7032; +} + +static void +Opcode_dpfm_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193000; +} + +static void +Opcode_dpfm_b_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a1af00; + slotbuf[1] = 0; +} + +static void +Opcode_dpfm_b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0130c; +} + +static void +Opcode_dpfm_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x197000; +} + +static void +Opcode_dpfm_bf_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a22f00; + slotbuf[1] = 0; +} + +static void +Opcode_dpfm_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0170c; +} + +static void +Opcode_dpfr_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191000; +} + +static void +Opcode_dpfr_b_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a2af00; + slotbuf[1] = 0; +} + +static void +Opcode_dpfr_b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01b0c; +} + +static void +Opcode_dpfr_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x195000; +} + +static void +Opcode_dpfr_bf_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a32f00; + slotbuf[1] = 0; +} + +static void +Opcode_dpfr_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01f0c; +} + +static void +Opcode_dpfw_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192000; +} + +static void +Opcode_dpfw_b_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a3af00; + slotbuf[1] = 0; +} + +static void +Opcode_dpfw_b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0930c; +} + +static void +Opcode_dpfw_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x196000; +} + +static void +Opcode_dpfw_bf_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a42f00; + slotbuf[1] = 0; +} + +static void +Opcode_dpfw_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0970c; +} + +static void +Opcode_pfnxt_f_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3430; +} + +static void +Opcode_dhi_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x199000; +} + +static void +Opcode_dhwbi_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19b000; +} + +static void +Opcode_dhwb_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a000; +} + +static void +Opcode_pfend_a_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3030; +} + +static void +Opcode_pfend_o_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3130; +} + +static void +Opcode_pfwait_a_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3230; +} + +static void +Opcode_pfwait_r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3330; +} + +static void +Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27082; +} + +static void +Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37082; +} + +static void +Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7082; +} + +static void +Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf19000; +} + +static void +Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf18000; +} + +static void +Opcode_sdcw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1b000; +} + +static void +Opcode_ldcw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1a000; +} + +static void +Opcode_rsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32800; +} + +static void +Opcode_wsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132800; +} + +static void +Opcode_xsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612800; +} + +static void +Opcode_wsr_cacheadrdis_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136200; +} + +static void +Opcode_rsr_cacheadrdis_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36200; +} + +static void +Opcode_xsr_cacheadrdis_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616200; +} + +static void +Opcode_rptlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50b000; +} + +static void +Opcode_pptlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50d000; +} + +static void +Opcode_rptlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50f000; +} + +static void +Opcode_wptlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50e000; +} + +static void +Opcode_rsr_mpuenb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35a00; +} + +static void +Opcode_wsr_mpuenb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135a00; +} + +static void +Opcode_xsr_mpuenb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615a00; +} + +static void +Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e000; +} + +static void +Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e000; +} + +static void +Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000; +} + +static void +Opcode_clamps_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4e000; +} + +static void +Opcode_clamps_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1412000; +} + +static void +Opcode_clamps_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f2000; + slotbuf[1] = 0; +} + +static void +Opcode_clamps_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee2000; + slotbuf[1] = 0; +} + +static void +Opcode_clamps_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10566000; + slotbuf[1] = 0; +} + +static void +Opcode_clamps_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb000; +} + +static void +Opcode_clamps_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3dc000; +} + +static void +Opcode_clamps_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b2000; +} + +static void +Opcode_clamps_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10659000; +} + +static void +Opcode_clamps_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a69000; +} + +static void +Opcode_clamps_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158e000; +} + +static void +Opcode_clamps_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2768000; +} + +static void +Opcode_clamps_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514000; +} + +static void +Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x992000c; +} + +static void +Opcode_clamps_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512000; +} + +static void +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_max_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc9000; +} + +static void +Opcode_max_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14cd000; +} + +static void +Opcode_max_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74bf000; + slotbuf[1] = 0; +} + +static void +Opcode_max_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e5a000; + slotbuf[1] = 0; +} + +static void +Opcode_max_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054e000; + slotbuf[1] = 0; +} + +static void +Opcode_max_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa000; +} + +static void +Opcode_max_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c9000; +} + +static void +Opcode_max_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a1000; +} + +static void +Opcode_max_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10639000; +} + +static void +Opcode_max_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a1d000; +} + +static void +Opcode_max_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154a000; +} + +static void +Opcode_max_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2755000; +} + +static void +Opcode_max_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cf000; +} + +static void +Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9960004; +} + +static void +Opcode_max_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cd000; +} + +static void +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_maxu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a000; +} + +static void +Opcode_maxu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140e000; +} + +static void +Opcode_maxu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e0000; + slotbuf[1] = 0; +} + +static void +Opcode_maxu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e62000; + slotbuf[1] = 0; +} + +static void +Opcode_maxu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054f000; + slotbuf[1] = 0; +} + +static void +Opcode_maxu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab000; +} + +static void +Opcode_maxu_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ca000; +} + +static void +Opcode_maxu_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a2000; +} + +static void +Opcode_maxu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063a000; +} + +static void +Opcode_maxu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a21000; +} + +static void +Opcode_maxu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158a000; +} + +static void +Opcode_maxu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2756000; +} + +static void +Opcode_maxu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510000; +} + +static void +Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9928004; +} + +static void +Opcode_maxu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150e000; +} + +static void +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_min_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0b000; +} + +static void +Opcode_min_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140f000; +} + +static void +Opcode_min_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e1000; + slotbuf[1] = 0; +} + +static void +Opcode_min_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6a000; + slotbuf[1] = 0; +} + +static void +Opcode_min_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10751000; + slotbuf[1] = 0; +} + +static void +Opcode_min_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac000; +} + +static void +Opcode_min_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3cb000; +} + +static void +Opcode_min_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a3000; +} + +static void +Opcode_min_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063b000; +} + +static void +Opcode_min_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a25000; +} + +static void +Opcode_min_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ca000; +} + +static void +Opcode_min_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2757000; +} + +static void +Opcode_min_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1511000; +} + +static void +Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9968004; +} + +static void +Opcode_min_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150f000; +} + +static void +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_minu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4a000; +} + +static void +Opcode_minu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144e000; +} + +static void +Opcode_minu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e2000; + slotbuf[1] = 0; +} + +static void +Opcode_minu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e72000; + slotbuf[1] = 0; +} + +static void +Opcode_minu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10753000; + slotbuf[1] = 0; +} + +static void +Opcode_minu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ad000; +} + +static void +Opcode_minu_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3cc000; +} + +static void +Opcode_minu_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a4000; +} + +static void +Opcode_minu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063c000; +} + +static void +Opcode_minu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a29000; +} + +static void +Opcode_minu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150b000; +} + +static void +Opcode_minu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2758000; +} + +static void +Opcode_minu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1550000; +} + +static void +Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9970008; +} + +static void +Opcode_minu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154e000; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40e000; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40f000; +} + +static void +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_sext_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4f000; +} + +static void +Opcode_sext_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1413000; +} + +static void +Opcode_sext_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f3000; + slotbuf[1] = 0; +} + +static void +Opcode_sext_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eea000; + slotbuf[1] = 0; +} + +static void +Opcode_sext_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10567000; + slotbuf[1] = 0; +} + +static void +Opcode_sext_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc000; +} + +static void +Opcode_sext_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3dd000; +} + +static void +Opcode_sext_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b3000; +} + +static void +Opcode_sext_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065b000; +} + +static void +Opcode_sext_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a6d000; +} + +static void +Opcode_sext_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ce000; +} + +static void +Opcode_sext_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2769000; +} + +static void +Opcode_sext_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1515000; +} + +static void +Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996000c; +} + +static void +Opcode_sext_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1513000; +} + +static void +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb002; +} + +static void +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002; +} + +static void +Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36300; +} + +static void +Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136300; +} + +static void +Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616300; +} + +static void +Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20000; +} + +static void +Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf20000; +} + +static void +Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe20000; +} + +static void +Opcode_rsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35f00; +} + +static void +Opcode_wsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135f00; +} + +static void +Opcode_xsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615f00; +} + +static void +Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x406000; +} + +static void +Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x407000; +} + +static void +Opcode_beqz_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000a; + slotbuf[1] = 0; +} + +static void +Opcode_beqz_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000a0; + slotbuf[1] = 0; +} + +static void +Opcode_beqz_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c0; +} + +static void +Opcode_bgez_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000e; + slotbuf[1] = 0; +} + +static void +Opcode_bgez_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000e0; + slotbuf[1] = 0; +} + +static void +Opcode_bgez_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000e0; +} + +static void +Opcode_bltz_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000040a; + slotbuf[1] = 0; +} + +static void +Opcode_bltz_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004a0; + slotbuf[1] = 0; +} + +static void +Opcode_bltz_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001c0; +} + +static void +Opcode_bnez_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000040e; + slotbuf[1] = 0; +} + +static void +Opcode_bnez_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004e0; + slotbuf[1] = 0; +} + +static void +Opcode_bnez_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001e0; +} + +static void +Opcode_beqi_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0; +} + +static void +Opcode_beqi_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0; +} + +static void +Opcode_beqi_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; +} + +static void +Opcode_bgei_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000004; + slotbuf[1] = 0; +} + +static void +Opcode_bgei_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000040; + slotbuf[1] = 0; +} + +static void +Opcode_bgei_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; +} + +static void +Opcode_blti_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000c; + slotbuf[1] = 0; +} + +static void +Opcode_blti_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c0; + slotbuf[1] = 0; +} + +static void +Opcode_blti_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000060; +} + +static void +Opcode_bnei_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000006; + slotbuf[1] = 0; +} + +static void +Opcode_bnei_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000060; + slotbuf[1] = 0; +} + +static void +Opcode_bnei_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000a0; +} + +static void +Opcode_bgeui_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000008; + slotbuf[1] = 0; +} + +static void +Opcode_bgeui_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000080; + slotbuf[1] = 0; +} + +static void +Opcode_bgeui_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000040; +} + +static void +Opcode_bltui_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000002; + slotbuf[1] = 0; +} + +static void +Opcode_bltui_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; + slotbuf[1] = 0; +} + +static void +Opcode_bltui_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000080; +} + +static void +Opcode_bbci_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0; +} + +static void +Opcode_bbci_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_bbci_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_bbsi_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000400; + slotbuf[1] = 0; +} + +static void +Opcode_bbsi_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; + slotbuf[1] = 0; +} + +static void +Opcode_bbsi_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; +} + +static void +Opcode_ball_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000800; + slotbuf[1] = 0; +} + +static void +Opcode_ball_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; + slotbuf[1] = 0; +} + +static void +Opcode_ball_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; +} + +static void +Opcode_bany_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000c00; + slotbuf[1] = 0; +} + +static void +Opcode_bany_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600; + slotbuf[1] = 0; +} + +static void +Opcode_bany_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500; +} + +static void +Opcode_bbc_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000900; + slotbuf[1] = 0; +} + +static void +Opcode_bbc_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00; + slotbuf[1] = 0; +} + +static void +Opcode_bbc_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600; +} + +static void +Opcode_bbs_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000d00; + slotbuf[1] = 0; +} + +static void +Opcode_bbs_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00; + slotbuf[1] = 0; +} + +static void +Opcode_bbs_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700; +} + +static void +Opcode_beq_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000200; + slotbuf[1] = 0; +} + +static void +Opcode_beq_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100; + slotbuf[1] = 0; +} + +static void +Opcode_beq_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; +} + +static void +Opcode_bgeu_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000600; + slotbuf[1] = 0; +} + +static void +Opcode_bgeu_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500; + slotbuf[1] = 0; +} + +static void +Opcode_bgeu_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900; +} + +static void +Opcode_bge_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000a00; + slotbuf[1] = 0; +} + +static void +Opcode_bge_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900; + slotbuf[1] = 0; +} + +static void +Opcode_bge_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00; +} + +static void +Opcode_bltu_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000e00; + slotbuf[1] = 0; +} + +static void +Opcode_bltu_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00; + slotbuf[1] = 0; +} + +static void +Opcode_bltu_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00; +} + +static void +Opcode_blt_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000300; + slotbuf[1] = 0; +} + +static void +Opcode_blt_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300; + slotbuf[1] = 0; +} + +static void +Opcode_blt_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00; +} + +static void +Opcode_bnall_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000700; + slotbuf[1] = 0; +} + +static void +Opcode_bnall_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700; + slotbuf[1] = 0; +} + +static void +Opcode_bnall_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00; +} + +static void +Opcode_bne_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000b00; + slotbuf[1] = 0; +} + +static void +Opcode_bne_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00; + slotbuf[1] = 0; +} + +static void +Opcode_bne_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00; +} + +static void +Opcode_bnone_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000f00; + slotbuf[1] = 0; +} + +static void +Opcode_bnone_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00; + slotbuf[1] = 0; +} + +static void +Opcode_bnone_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00; +} + +static void +Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f00; +} + +static void +Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f000; +} + +static void +Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f10; +} + +static void +Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f100; +} + +static void +Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f20; +} + +static void +Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f200; +} + +static void +Opcode_rur_ae_cw_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f30; +} + +static void +Opcode_wur_ae_cw_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f300; +} + +static void +Opcode_rur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f60; +} + +static void +Opcode_wur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f600; +} + +static void +Opcode_rur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f70; +} + +static void +Opcode_wur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f700; +} + +static void +Opcode_rur_ae_cbegin1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f80; +} + +static void +Opcode_wur_ae_cbegin1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f800; +} + +static void +Opcode_rur_ae_cend1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f90; +} + +static void +Opcode_wur_ae_cend1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f900; +} + +static void +Opcode_rur_ae_cbegin2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30fa0; +} + +static void +Opcode_wur_ae_cbegin2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3fa00; +} + +static void +Opcode_rur_ae_cend2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30fb0; +} + +static void +Opcode_wur_ae_cend2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3fb00; +} + +static void +Opcode_ae_sext16_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800d; +} + +static void +Opcode_ae_zext16_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900d; +} + +static void +Opcode_ae_zext8_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00d; +} + +static void +Opcode_ae_clamps16_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00d; +} + +static void +Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e80; +} + +static void +Opcode_rur_fcr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a7030; +} + +static void +Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e800; +} + +static void +Opcode_wur_fcr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa64005; +} + +static void +Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e90; +} + +static void +Opcode_rur_fsr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a7070; +} + +static void +Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e900; +} + +static void +Opcode_wur_fsr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa66005; +} + +static void +Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e60; +} + +static void +Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e600; +} + +static void +Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1200; +} + +static void +Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static void +Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ea04; +} + +static void +Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67eb04; +} + +static void +Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ec04; +} + +static void +Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ed04; +} + +static void +Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ee04; +} + +static void +Opcode_rur_ae_bitptr_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afe0b; + slotbuf[1] = 0; +} + +static void +Opcode_rur_ae_bitptr_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687705; +} + +static void +Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ef04; +} + +static void +Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f004; +} + +static void +Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f104; +} + +static void +Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f204; +} + +static void +Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f304; +} + +static void +Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f404; +} + +static void +Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f504; +} + +static void +Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f604; +} + +static void +Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f704; +} + +static void +Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f804; +} + +static void +Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f904; +} + +static void +Opcode_rur_ae_cwrap_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67fa04; +} + +static void +Opcode_wur_ae_cwrap_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67fb04; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3c000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7450000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10676000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168300; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054c000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901800; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133c000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2676000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c0000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb980008; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13be000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7c000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1440000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7452000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10678000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054e000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941800; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137c000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2678000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1502000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c0008; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fe000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1480000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7454000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1067a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170100; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10550000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981800; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13bc000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x267a000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1542000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb98000c; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xafc000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c0000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7456000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1067c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170200; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10552000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1800; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fc000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x267c000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1582000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c000c; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1540000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3e000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1402000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7458000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1067e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170300; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10554000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901a00; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133e000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x267e000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c2000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb981000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7e000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1442000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x745a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10556000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941a00; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137e000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2680000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1504000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c1000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c0000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabe000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1482000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x745c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10682000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178100; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10558000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981a00; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13be000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2682000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1544000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb981004; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1502000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xafe000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c2000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x745e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10684000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178200; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055a000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1a00; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fe000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2684000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1584000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c1004; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1542000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1404000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7490000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10686000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178300; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055c000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901c00; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2686000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c4000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb981008; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1582000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1444000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7492000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10688000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055e000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941c00; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1540000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2688000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1506000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c1008; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c2000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1484000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7494000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1068a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180100; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10560000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981c00; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268a000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1546000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb98100c; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1504000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c4000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7496000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1068c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180200; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10562000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1c00; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c0000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268c000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1586000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c100c; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1544000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae0000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1266000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c836000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110300; +} + +static void +Opcode_ae_l16m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10466000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e4000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2606000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1366000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a60004; +} + +static void +Opcode_ae_l16m_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1366000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa22000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1268000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c874000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10468000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900200; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1326000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2608000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1368000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1368000; +} + +static void +Opcode_ae_l16m_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa20000; +} + +static void +Opcode_ae_l16m_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1260000; +} + +static void +Opcode_ae_l16m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c832000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ec000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ae_l16m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10460000; +} + +static void +Opcode_ae_l16m_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900000; +} + +static void +Opcode_ae_l16m_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1324000; +} + +static void +Opcode_ae_l16m_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2600000; +} + +static void +Opcode_ae_l16m_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1360000; +} + +static void +Opcode_ae_l16m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9860000; +} + +static void +Opcode_ae_l16m_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1360000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1262000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c872000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_iu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ee000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_iu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110100; +} + +static void +Opcode_ae_l16m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10462000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1364000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2602000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1362000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9860004; +} + +static void +Opcode_ae_l16m_iu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1362000; +} + +static void +Opcode_ae_l16m_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa0000; +} + +static void +Opcode_ae_l16m_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1264000; +} + +static void +Opcode_ae_l16m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c834000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110200; +} + +static void +Opcode_ae_l16m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10464000; +} + +static void +Opcode_ae_l16m_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980000; +} + +static void +Opcode_ae_l16m_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a4000; +} + +static void +Opcode_ae_l16m_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2604000; +} + +static void +Opcode_ae_l16m_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1364000; +} + +static void +Opcode_ae_l16m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a60000; +} + +static void +Opcode_ae_l16m_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1364000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa62000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x126a000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c876000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1046a000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940200; +} + +static void +Opcode_ae_l16m_xu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1366000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260a000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136a000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e0000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136a000; +} + +static void +Opcode_ae_l16_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2a000; +} + +static void +Opcode_ae_l16_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ac000; +} + +static void +Opcode_ae_l16_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8cc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1047e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_ae_l16_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10508000; +} + +static void +Opcode_ae_l16_xc_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x920300; +} + +static void +Opcode_ae_l16_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940a00; +} + +static void +Opcode_ae_l16_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136e000; +} + +static void +Opcode_ae_l16_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262a000; +} + +static void +Opcode_ae_l16_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec000; +} + +static void +Opcode_ae_l16_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x982000c; +} + +static void +Opcode_ae_l16_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ac000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6a000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ec000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8ce000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050a000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980a00; +} + +static void +Opcode_ae_l16_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ae000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262c000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ae000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x986000c; +} + +static void +Opcode_ae_l16_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec000; +} + +static void +Opcode_ae_l16_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa68000; +} + +static void +Opcode_ae_l16_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e8000; +} + +static void +Opcode_ae_l16_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8c6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10472000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128200; +} + +static void +Opcode_ae_l16_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10502000; +} + +static void +Opcode_ae_l16_i_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x908300; +} + +static void +Opcode_ae_l16_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980800; +} + +static void +Opcode_ae_l16_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ac000; +} + +static void +Opcode_ae_l16_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2624000; +} + +static void +Opcode_ae_l16_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13aa000; +} + +static void +Opcode_ae_l16_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9c100c; +} + +static void +Opcode_ae_l16_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e8000; +} + +static void +Opcode_ae_l16_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa8000; +} + +static void +Opcode_ae_l16_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12aa000; +} + +static void +Opcode_ae_l16_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8c8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10476000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128300; +} + +static void +Opcode_ae_l16_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10504000; +} + +static void +Opcode_ae_l16_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910300; +} + +static void +Opcode_ae_l16_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0800; +} + +static void +Opcode_ae_l16_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec000; +} + +static void +Opcode_ae_l16_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2626000; +} + +static void +Opcode_ae_l16_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea000; +} + +static void +Opcode_ae_l16_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9820008; +} + +static void +Opcode_ae_l16_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13aa000; +} + +static void +Opcode_ae_l16_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae8000; +} + +static void +Opcode_ae_l16_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ea000; +} + +static void +Opcode_ae_l16_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8ca000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1047a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ae_l16_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10506000; +} + +static void +Opcode_ae_l16_x_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x918300; +} + +static void +Opcode_ae_l16_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900a00; +} + +static void +Opcode_ae_l16_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132e000; +} + +static void +Opcode_ae_l16_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2628000; +} + +static void +Opcode_ae_l16_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ac000; +} + +static void +Opcode_ae_l16_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9860008; +} + +static void +Opcode_ae_l16_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea000; +} + +static void +Opcode_ae_l16_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaaa000; +} + +static void +Opcode_ae_l16_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ae000; +} + +static void +Opcode_ae_l16_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_ae_l16_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050c000; +} + +static void +Opcode_ae_l16_xp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x928300; +} + +static void +Opcode_ae_l16_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0a00; +} + +static void +Opcode_ae_l16_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee000; +} + +static void +Opcode_ae_l16_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262e000; +} + +static void +Opcode_ae_l16_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee000; +} + +static void +Opcode_ae_l16_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a20008; +} + +static void +Opcode_ae_l16_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ae000; +} + +static void +Opcode_ae_l8_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc06000; +} + +static void +Opcode_ae_l8_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140a000; +} + +static void +Opcode_ae_l8_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74d8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190200; +} + +static void +Opcode_ae_l8_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10574000; +} + +static void +Opcode_ae_l8_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942200; +} + +static void +Opcode_ae_l8_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1546000; +} + +static void +Opcode_ae_l8_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a0000; +} + +static void +Opcode_ae_l8_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150c000; +} + +static void +Opcode_ae_l8_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab40000; +} + +static void +Opcode_ae_l8_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1588000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc46000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144a000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74da000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10576000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982200; +} + +static void +Opcode_ae_l8_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1586000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a2000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154c000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab40004; +} + +static void +Opcode_ae_l8_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c8000; +} + +static void +Opcode_ae_l8_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc44000; +} + +static void +Opcode_ae_l8_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1448000; +} + +static void +Opcode_ae_l8_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74d2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10696000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188300; +} + +static void +Opcode_ae_l8_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056e000; +} + +static void +Opcode_ae_l8_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982000; +} + +static void +Opcode_ae_l8_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1584000; +} + +static void +Opcode_ae_l8_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269a000; +} + +static void +Opcode_ae_l8_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154a000; +} + +static void +Opcode_ae_l8_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa941004; +} + +static void +Opcode_ae_l8_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c6000; +} + +static void +Opcode_ae_l8_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc84000; +} + +static void +Opcode_ae_l8_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1488000; +} + +static void +Opcode_ae_l8_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74d4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10698000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_ae_l8_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10570000; +} + +static void +Opcode_ae_l8_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2000; +} + +static void +Opcode_ae_l8_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c4000; +} + +static void +Opcode_ae_l8_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269c000; +} + +static void +Opcode_ae_l8_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158a000; +} + +static void +Opcode_ae_l8_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa941008; +} + +static void +Opcode_ae_l8_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1508000; +} + +static void +Opcode_ae_l8_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc4000; +} + +static void +Opcode_ae_l8_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c8000; +} + +static void +Opcode_ae_l8_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74d6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190100; +} + +static void +Opcode_ae_l8_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10572000; +} + +static void +Opcode_ae_l8_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902200; +} + +static void +Opcode_ae_l8_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1506000; +} + +static void +Opcode_ae_l8_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269e000; +} + +static void +Opcode_ae_l8_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ca000; +} + +static void +Opcode_ae_l8_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa94100c; +} + +static void +Opcode_ae_l8_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1548000; +} + +static void +Opcode_ae_l8_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc86000; +} + +static void +Opcode_ae_l8_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148a000; +} + +static void +Opcode_ae_l8_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74dc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190300; +} + +static void +Opcode_ae_l8_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10578000; +} + +static void +Opcode_ae_l8_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2200; +} + +static void +Opcode_ae_l8_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c6000; +} + +static void +Opcode_ae_l8_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a4000; +} + +static void +Opcode_ae_l8_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158c000; +} + +static void +Opcode_ae_l8_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab40008; +} + +static void +Opcode_ae_l8_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150a000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaac000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b0000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8d8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10648000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138200; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10514000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2636000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f0000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a0008; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b0000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaec000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f0000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8da000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10516000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2638000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1332000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e0008; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f0000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaea000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ee000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8d2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10642000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_ae_l32f24_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050e000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2630000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a60008; +} + +static void +Opcode_ae_l32f24_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2c000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1230000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8d4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10644000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10510000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2632000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1370000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a2000c; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6c000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1270000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8d6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10646000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138100; +} + +static void +Opcode_ae_l32f24_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10512000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2634000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b0000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a6000c; +} + +static void +Opcode_ae_l32f24_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1370000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2e000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1232000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8dc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138300; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10518000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263a000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1372000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a000c; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1332000; +} + +static void +Opcode_ae_l32_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf6000; +} + +static void +Opcode_ae_l32_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12fa000; +} + +static void +Opcode_ae_l32_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7410000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1066a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ae_l32_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1053c000; +} + +static void +Opcode_ae_l32_xc_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x960300; +} + +static void +Opcode_ae_l32_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981200; +} + +static void +Opcode_ae_l32_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b6000; +} + +static void +Opcode_ae_l32_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2662000; +} + +static void +Opcode_ae_l32_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137c000; +} + +static void +Opcode_ae_l32_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3a100c; +} + +static void +Opcode_ae_l32_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ba000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa38000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x123c000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7412000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1053e000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1200; +} + +static void +Opcode_ae_l32_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f6000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2664000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13bc000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3e100c; +} + +static void +Opcode_ae_l32_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fa000; +} + +static void +Opcode_ae_l32_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa36000; +} + +static void +Opcode_ae_l32_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x123a000; +} + +static void +Opcode_ae_l32_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8fa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10664000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158100; +} + +static void +Opcode_ae_l32_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10536000; +} + +static void +Opcode_ae_l32_i_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x948300; +} + +static void +Opcode_ae_l32_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1000; +} + +static void +Opcode_ae_l32_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f4000; +} + +static void +Opcode_ae_l32_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x265c000; +} + +static void +Opcode_ae_l32_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ba000; +} + +static void +Opcode_ae_l32_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3e100c; +} + +static void +Opcode_ae_l32_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f8000; +} + +static void +Opcode_ae_l32_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa76000; +} + +static void +Opcode_ae_l32_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x127a000; +} + +static void +Opcode_ae_l32_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8fc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10666000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158200; +} + +static void +Opcode_ae_l32_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10538000; +} + +static void +Opcode_ae_l32_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x950300; +} + +static void +Opcode_ae_l32_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901200; +} + +static void +Opcode_ae_l32_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1336000; +} + +static void +Opcode_ae_l32_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x265e000; +} + +static void +Opcode_ae_l32_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fa000; +} + +static void +Opcode_ae_l32_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3a100c; +} + +static void +Opcode_ae_l32_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a000; +} + +static void +Opcode_ae_l32_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab6000; +} + +static void +Opcode_ae_l32_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ba000; +} + +static void +Opcode_ae_l32_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8fe000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10668000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158300; +} + +static void +Opcode_ae_l32_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1053a000; +} + +static void +Opcode_ae_l32_x_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x958300; +} + +static void +Opcode_ae_l32_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941200; +} + +static void +Opcode_ae_l32_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1376000; +} + +static void +Opcode_ae_l32_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2660000; +} + +static void +Opcode_ae_l32_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133c000; +} + +static void +Opcode_ae_l32_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3e100c; +} + +static void +Opcode_ae_l32_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137a000; +} + +static void +Opcode_ae_l32_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa78000; +} + +static void +Opcode_ae_l32_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x127c000; +} + +static void +Opcode_ae_l32_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7414000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1066c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160100; +} + +static void +Opcode_ae_l32_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10540000; +} + +static void +Opcode_ae_l32_xp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x968300; +} + +static void +Opcode_ae_l32_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901400; +} + +static void +Opcode_ae_l32_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338000; +} + +static void +Opcode_ae_l32_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2666000; +} + +static void +Opcode_ae_l32_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fc000; +} + +static void +Opcode_ae_l32_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3a100c; +} + +static void +Opcode_ae_l32_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133c000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1234000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8e4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10652000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140300; +} + +static void +Opcode_ae_l32m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10520000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0c00; +} + +static void +Opcode_ae_l32m_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f0000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2642000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1374000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa000c; +} + +static void +Opcode_ae_l32m_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1334000; +} + +static void +Opcode_ae_l32m_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6e000; +} + +static void +Opcode_ae_l32m_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1272000; +} + +static void +Opcode_ae_l32m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8de000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_l32m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1051a000; +} + +static void +Opcode_ae_l32m_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900c00; +} + +static void +Opcode_ae_l32m_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330000; +} + +static void +Opcode_ae_l32m_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263c000; +} + +static void +Opcode_ae_l32m_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b2000; +} + +static void +Opcode_ae_l32m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e000c; +} + +static void +Opcode_ae_l32m_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1372000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaae000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b2000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_iu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_iu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140100; +} + +static void +Opcode_ae_l32m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1051c000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940c00; +} + +static void +Opcode_ae_l32m_iu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1370000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263e000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f2000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa0008; +} + +static void +Opcode_ae_l32m_iu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b2000; +} + +static void +Opcode_ae_l32m_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaee000; +} + +static void +Opcode_ae_l32m_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f2000; +} + +static void +Opcode_ae_l32m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8e2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10650000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140200; +} + +static void +Opcode_ae_l32m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1051e000; +} + +static void +Opcode_ae_l32m_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980c00; +} + +static void +Opcode_ae_l32m_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b0000; +} + +static void +Opcode_ae_l32m_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2640000; +} + +static void +Opcode_ae_l32m_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1334000; +} + +static void +Opcode_ae_l32m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae0008; +} + +static void +Opcode_ae_l32m_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f2000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa70000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1274000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8e6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10654000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10522000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900e00; +} + +static void +Opcode_ae_l32m_xu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1332000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2644000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b4000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae000c; +} + +static void +Opcode_ae_l32m_xu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1374000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa64000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e0000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c83e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10472000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940400; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1368000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2612000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e0000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa981000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e0000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa4000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a2000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c878000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10474000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980400; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a8000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2614000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a2000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a2000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa2000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x126c000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c838000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118100; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1046c000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980200; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a6000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260c000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136c000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e0004; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136c000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae2000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x126e000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c83a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118200; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1046e000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0200; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e6000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260e000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136e000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae0000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136e000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa24000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a0000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c83c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118300; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10470000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900400; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1328000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2610000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a0000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae0004; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a0000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae4000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e2000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c87a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fe000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120100; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10476000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0400; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e8000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2616000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e2000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9c1000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e2000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa32000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1236000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8ea000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10658000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148300; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10526000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ca000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ca000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264a000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1376000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83e100c; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f4000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa72000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1276000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8ec000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10528000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6cc000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6cc000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264c000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b6000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x93a100c; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1336000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab0000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b4000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19002030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00202; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148100; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10618008; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680050; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680050; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2646000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f4000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9871001; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000d; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc50080; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d2000; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d86a080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10576008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198300; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c2002; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea000; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea000; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276e000; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d4000; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b70006; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d2000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd0080; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1454000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d834080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1061e004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0100; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fc003; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea080; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea080; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277e000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996100e; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1554000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1492008; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74fc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01e01; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198208; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c4002; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276c080; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1594008; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b7000a; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1592008; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd00c0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1454004; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8340c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c010e; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2001; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6080; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6080; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277e040; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556004; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0303; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516002; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd00d0; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1454005; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8360c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00402; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2009; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6090; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6090; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277e050; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556005; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a0303; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556002; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf0000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f4000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8e8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10656000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148200; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10524000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c8000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c8000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2648000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1336000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a100c; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b4000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab2000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b6000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8ee000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1052a000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ce000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ce000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264e000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f6000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x93e100c; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1376000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa74000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1278000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8f2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150300; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1052e000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d2000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d2000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0e00; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f2000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2654000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b8000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3e100c; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f6000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab4000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b8000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8f4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10530000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d4000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d4000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1334000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2656000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f8000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3a100c; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf2000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f6000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19004030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04203; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150100; +} + +static void +Opcode_ae_l32x2_i_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x298000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10618004; +} + +static void +Opcode_ae_l32x2_i_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930300; +} + +static void +Opcode_ae_l32x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680060; +} + +static void +Opcode_ae_l32x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680060; +} + +static void +Opcode_ae_l32x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940e00; +} + +static void +Opcode_ae_l32x2_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1372000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2650000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9871002; +} + +static void +Opcode_ae_l32x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000e; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90080; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d2008; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74fe000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01f01; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057a008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198308; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c6002; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x970380; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee000; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee000; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac0400; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1550000; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276e080; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d4008; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b7000e; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d2008; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd00e0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1454006; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8340d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00401; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c010f; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2005; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f60a0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f60a0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80600; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200f; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277e060; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556006; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e0303; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1596002; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd00f0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1454007; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8360d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00403; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a200d; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f60b0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f60b0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80610; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x155200f; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277e070; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556007; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e0303; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d6002; +} + +static void +Opcode_ae_l32x2_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa34000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1238000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8f0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150200; +} + +static void +Opcode_ae_l32x2_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1052c000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x938300; +} + +static void +Opcode_ae_l32x2_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980e00; +} + +static void +Opcode_ae_l32x2_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b2000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2652000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1378000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3a100c; +} + +static void +Opcode_ae_l32x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b6000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf4000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f8000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8f8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10662000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29a000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10534000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940300; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d6000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d6000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b4000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x265a000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137a000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3a100c; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b8000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa6000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a6000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c87e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10466000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1047a000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c2000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c2000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980600; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13aa000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261c000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a6000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9c1004; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e4000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae6000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e6000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1047c000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c4000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c4000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0600; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261e000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e6000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa981008; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a6000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa26000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a4000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00203; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120200; +} + +static void +Opcode_ae_l16x4_i_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x294000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10618000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900300; +} + +static void +Opcode_ae_l16x4_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680040; +} + +static void +Opcode_ae_l16x4_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680040; +} + +static void +Opcode_ae_l16x4_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900600; +} + +static void +Opcode_ae_l16x4_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132a000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2618000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a4000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9871000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000c; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc50000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1492000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d82a080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10576000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198200; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0002; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x970300; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e8000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e8000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80400; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276c000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1594000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b70002; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1592000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa66000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e4000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c87c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10462000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120300; +} + +static void +Opcode_ae_l16x4_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10478000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940600; +} + +static void +Opcode_ae_l16x4_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136a000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261a000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e4000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa981004; +} + +static void +Opcode_ae_l16x4_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a4000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa28000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a8000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8c4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1046e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128100; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x296000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c6000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c6000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940800; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136c000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2622000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e8000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa98100c; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a8000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc82000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1486000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x749a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188100; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10566000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e2000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e2000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981e00; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1582000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2692000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1548000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa940004; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c4000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc2000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c6000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x749c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10568000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e4000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e4000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1e00; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c2000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2694000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1588000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa940008; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1506000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc02000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1406000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19082030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0420b; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10708001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180300; +} + +static void +Opcode_ae_l8x8_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10620008; +} + +static void +Opcode_ae_l8x8_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0050; +} + +static void +Opcode_ae_l8x8_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0050; +} + +static void +Opcode_ae_l8x8_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901e00; +} + +static void +Opcode_ae_l8x8_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1502000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268e000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c6000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9971001; +} + +static void +Opcode_ae_l8x8_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144000d; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd0000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1414000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74fc080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c8002; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e8080; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e8080; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80480; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1590000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2770000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9921008; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc42000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1446000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7498000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1068e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10564000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941e00; +} + +static void +Opcode_ae_l8x8_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1542000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2690000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1508000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa940000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1584000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc04000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1408000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10694000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188200; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056c000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e6000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e6000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1544000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2698000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150a000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa941000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1586000; +} + +static void +Opcode_ae_l64_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7a000; +} + +static void +Opcode_ae_l64_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x127e000; +} + +static void +Opcode_ae_l64_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7418000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10670000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168100; +} + +static void +Opcode_ae_l64_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10544000; +} + +static void +Opcode_ae_l64_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6da000; +} + +static void +Opcode_ae_l64_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6da000; +} + +static void +Opcode_ae_l64_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901600; +} + +static void +Opcode_ae_l64_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a000; +} + +static void +Opcode_ae_l64_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x266e000; +} + +static void +Opcode_ae_l64_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fe000; +} + +static void +Opcode_ae_l64_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb980000; +} + +static void +Opcode_ae_l64_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13bc000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaba000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12be000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x741a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10546000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6dc000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6dc000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941600; +} + +static void +Opcode_ae_l64_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137a000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2670000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c0000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fc000; +} + +static void +Opcode_ae_l64_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab8000; +} + +static void +Opcode_ae_l64_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12bc000; +} + +static void +Opcode_ae_l64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19006030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04202; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160200; +} + +static void +Opcode_ae_l64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1061800c; +} + +static void +Opcode_ae_l64_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680070; +} + +static void +Opcode_ae_l64_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680070; +} + +static void +Opcode_ae_l64_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941400; +} + +static void +Opcode_ae_l64_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1378000; +} + +static void +Opcode_ae_l64_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2668000; +} + +static void +Opcode_ae_l64_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133e000; +} + +static void +Opcode_ae_l64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9871003; +} + +static void +Opcode_ae_l64_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000f; +} + +static void +Opcode_ae_l64_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf8000; +} + +static void +Opcode_ae_l64_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12fc000; +} + +static void +Opcode_ae_l64_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19080030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0020b; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10708000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160300; +} + +static void +Opcode_ae_l64_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10620000; +} + +static void +Opcode_ae_l64_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0040; +} + +static void +Opcode_ae_l64_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0040; +} + +static void +Opcode_ae_l64_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981400; +} + +static void +Opcode_ae_l64_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b8000; +} + +static void +Opcode_ae_l64_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x266a000; +} + +static void +Opcode_ae_l64_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137e000; +} + +static void +Opcode_ae_l64_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9971000; +} + +static void +Opcode_ae_l64_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144000c; +} + +static void +Opcode_ae_l64_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3a000; +} + +static void +Opcode_ae_l64_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x123e000; +} + +static void +Opcode_ae_l64_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7416000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1066e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_ae_l64_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10542000; +} + +static void +Opcode_ae_l64_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d8000; +} + +static void +Opcode_ae_l64_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d8000; +} + +static void +Opcode_ae_l64_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1400; +} + +static void +Opcode_ae_l64_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f8000; +} + +static void +Opcode_ae_l64_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x266c000; +} + +static void +Opcode_ae_l64_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13be000; +} + +static void +Opcode_ae_l64_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e100c; +} + +static void +Opcode_ae_l64_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137c000; +} + +static void +Opcode_ae_l64_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xafa000; +} + +static void +Opcode_ae_l64_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12fe000; +} + +static void +Opcode_ae_l64_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x741e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10674000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168200; +} + +static void +Opcode_ae_l64_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054a000; +} + +static void +Opcode_ae_l64_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6de000; +} + +static void +Opcode_ae_l64_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6de000; +} + +static void +Opcode_ae_l64_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1600; +} + +static void +Opcode_ae_l64_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fa000; +} + +static void +Opcode_ae_l64_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2674000; +} + +static void +Opcode_ae_l64_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580000; +} + +static void +Opcode_ae_l64_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c0004; +} + +static void +Opcode_ae_l64_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137e000; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7550000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058c000; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942800; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b8000; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9821008; +} + +static void +Opcode_ae_s16x2m_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7552000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058e000; +} + +static void +Opcode_ae_s16x2m_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982800; +} + +static void +Opcode_ae_s16x2m_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ba000; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x751a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106aa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10586000; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982600; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b2000; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9861000; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x751c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ac000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10588000; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2600; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b4000; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9821004; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x751e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ae000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058a000; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902800; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b6000; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9861004; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7554000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10590000; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2800; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26bc000; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9861008; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7428000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c4000; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f6000; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae100c; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c6000; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f8000; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab80000; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19100030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10710000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10628000; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318000; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f2000; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a70000; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d82e080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10730008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ce002; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380000; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2776000; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996100a; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8340f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718007; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2006; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2984010; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996110f; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8340e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718006; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2002; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2904010; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996100f; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8360e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a200a; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2944010; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996120f; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7426000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106de000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c2000; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f4000; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa100c; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c8000; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26fa000; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc0000; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7434000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ea000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d0000; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3200; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2706000; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc0008; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7436000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d2000; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903400; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2708000; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab8000c; +} + +static void +Opcode_ae_s32x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19104030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10710002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10628004; +} + +static void +Opcode_ae_s32x2_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318010; +} + +static void +Opcode_ae_s32x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943200; +} + +static void +Opcode_ae_s32x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2702000; +} + +static void +Opcode_ae_s32x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a70002; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d86e080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10732008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d2002; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380200; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00600; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277a000; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996100c; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8360f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071800a; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a200e; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80620; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c4010; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996130f; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191a4030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2003; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80630; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2906010; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0120c; +} + +static void +Opcode_ae_s32x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7432000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ce000; +} + +static void +Opcode_ae_s32x2_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308200; +} + +static void +Opcode_ae_s32x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983200; +} + +static void +Opcode_ae_s32x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2704000; +} + +static void +Opcode_ae_s32x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab80008; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x743a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ee000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d6000; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308300; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983400; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270c000; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab81000; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19102030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10710001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10628008; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318200; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26fc000; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a70001; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d86c080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10732000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d0002; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380100; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2778000; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x992100c; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ca000; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308000; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26fe000; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab80004; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7430000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105cc000; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308100; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700000; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc0004; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x755c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ba000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10598000; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982a00; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c8000; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a61000; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x755e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1059a000; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2a00; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ca000; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a21004; +} + +static void +Opcode_ae_s16x4_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19086030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10708003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1062000c; +} + +static void +Opcode_ae_s16x4_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1310210; +} + +static void +Opcode_ae_s16x4_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902a00; +} + +static void +Opcode_ae_s16x4_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c4000; +} + +static void +Opcode_ae_s16x4_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9971003; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d82c080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10730000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104cc002; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318310; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac0480; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2774000; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x992100a; +} + +static void +Opcode_ae_s16x4_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x755a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10596000; +} + +static void +Opcode_ae_s16x4_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330200; +} + +static void +Opcode_ae_s16x4_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942a00; +} + +static void +Opcode_ae_s16x4_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c6000; +} + +static void +Opcode_ae_s16x4_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a21000; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7592000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106be000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1059e000; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330300; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942c00; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ce000; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a21008; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1051e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105fc000; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00000; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2738000; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc1004; +} + +static void +Opcode_ae_s8x8_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74a2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105fe000; +} + +static void +Opcode_ae_s8x8_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a40000; +} + +static void +Opcode_ae_s8x8_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x273a000; +} + +static void +Opcode_ae_s8x8_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb81008; +} + +static void +Opcode_ae_s8x8_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19182030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10630008; +} + +static void +Opcode_ae_s8x8_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983e00; +} + +static void +Opcode_ae_s8x8_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2734000; +} + +static void +Opcode_ae_s8x8_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b70001; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d830080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10734000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d4002; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a40600; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277c000; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x992100e; +} + +static void +Opcode_ae_s8x8_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x747e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1051a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105fa000; +} + +static void +Opcode_ae_s8x8_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3e00; +} + +static void +Opcode_ae_s8x8_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2736000; +} + +static void +Opcode_ae_s8x8_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb81004; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74a6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10526000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10602000; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac0000; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x273e000; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb8100c; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7514000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10580000; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2400; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ac000; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab41008; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7516000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10582000; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902600; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ae000; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab4100c; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74de000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057a000; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902400; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a6000; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab4000c; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7510000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057c000; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942400; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a8000; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab41000; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7512000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057e000; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982400; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26aa000; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab41004; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7518000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10584000; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942600; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b0000; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9821000; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75d6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b2000; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e2000; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a100c; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75d8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b4000; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e4000; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e100c; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ca000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ac000; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26dc000; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e1004; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75d2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106cc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae000; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26de000; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a1008; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75d4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ce000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b0000; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e0000; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e1008; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75da000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b6000; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e6000; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa1000; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x746e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10502000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ea000; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903a00; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2720000; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb80004; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7470000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ec000; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943a00; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2722000; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc0004; +} + +static void +Opcode_ae_s32_l_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7468000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106fa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e4000; +} + +static void +Opcode_ae_s32_l_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943800; +} + +static void +Opcode_ae_s32_l_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x271a000; +} + +static void +Opcode_ae_s32_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc100c; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x746a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106fc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e6000; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983800; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x271c000; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb80000; +} + +static void +Opcode_ae_s32_l_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x746c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106fe000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e8000; +} + +static void +Opcode_ae_s32_l_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3800; +} + +static void +Opcode_ae_s32_l_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x271e000; +} + +static void +Opcode_ae_s32_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc0000; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7472000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10506000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ee000; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983a00; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2724000; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb80008; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7462000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105de000; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983600; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2714000; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab81008; +} + +static void +Opcode_ae_s32_h_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7464000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e0000; +} + +static void +Opcode_ae_s32_h_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3600; +} + +static void +Opcode_ae_s32_h_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2716000; +} + +static void +Opcode_ae_s32_h_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc1008; +} + +static void +Opcode_ae_s32_h_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x743c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d8000; +} + +static void +Opcode_ae_s32_h_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3400; +} + +static void +Opcode_ae_s32_h_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270e000; +} + +static void +Opcode_ae_s32_h_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc1000; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x743e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105da000; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903600; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2710000; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab81004; +} + +static void +Opcode_ae_s32_h_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7460000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105dc000; +} + +static void +Opcode_ae_s32_h_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943600; +} + +static void +Opcode_ae_s32_h_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2712000; +} + +static void +Opcode_ae_s32_h_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc1004; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7466000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e2000; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903800; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2718000; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab8100c; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x759a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a6000; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942e00; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d6000; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a1000; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x759c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a8000; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982e00; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d8000; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e1000; +} + +static void +Opcode_ae_s16_0_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7594000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a0000; +} + +static void +Opcode_ae_s16_0_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982c00; +} + +static void +Opcode_ae_s16_0_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d0000; +} + +static void +Opcode_ae_s16_0_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a61008; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7596000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a2000; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2c00; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d2000; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a2100c; +} + +static void +Opcode_ae_s16_0_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7598000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a4000; +} + +static void +Opcode_ae_s16_0_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902e00; +} + +static void +Opcode_ae_s16_0_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d4000; +} + +static void +Opcode_ae_s16_0_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a6100c; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x759e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa000; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2e00; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26da000; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a1004; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ae000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10536000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060a000; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac0200; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2746000; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9870008; +} + +static void +Opcode_ae_s8_0_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74b0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060c000; +} + +static void +Opcode_ae_s8_0_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00400; +} + +static void +Opcode_ae_s8_0_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2748000; +} + +static void +Opcode_ae_s8_0_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x987000c; +} + +static void +Opcode_ae_s8_0_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74a8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1052a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10604000; +} + +static void +Opcode_ae_s8_0_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00200; +} + +static void +Opcode_ae_s8_0_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2740000; +} + +static void +Opcode_ae_s8_0_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc100c; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74aa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1052e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10606000; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a40200; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2742000; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9870000; +} + +static void +Opcode_ae_s8_0_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ac000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10532000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10608000; +} + +static void +Opcode_ae_s8_0_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80200; +} + +static void +Opcode_ae_s8_0_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2744000; +} + +static void +Opcode_ae_s8_0_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9870004; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74b2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1053a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060e000; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a40400; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x274a000; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9970000; +} + +static void +Opcode_ae_s64_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7476000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f2000; +} + +static void +Opcode_ae_s64_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983c00; +} + +static void +Opcode_ae_s64_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x272c000; +} + +static void +Opcode_ae_s64_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb8000c; +} + +static void +Opcode_ae_s64_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7478000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f4000; +} + +static void +Opcode_ae_s64_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3c00; +} + +static void +Opcode_ae_s64_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x272e000; +} + +static void +Opcode_ae_s64_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc000c; +} + +static void +Opcode_ae_s64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19106030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10710003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1062800c; +} + +static void +Opcode_ae_s64_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3a00; +} + +static void +Opcode_ae_s64_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2726000; +} + +static void +Opcode_ae_s64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a70003; +} + +static void +Opcode_ae_s64_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19180030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10630000; +} + +static void +Opcode_ae_s64_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903c00; +} + +static void +Opcode_ae_s64_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2728000; +} + +static void +Opcode_ae_s64_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b70000; +} + +static void +Opcode_ae_s64_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7474000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0000; +} + +static void +Opcode_ae_s64_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943c00; +} + +static void +Opcode_ae_s64_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x272a000; +} + +static void +Opcode_ae_s64_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc0008; +} + +static void +Opcode_ae_s64_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x747c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10516000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f8000; +} + +static void +Opcode_ae_s64_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943e00; +} + +static void +Opcode_ae_s64_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2732000; +} + +static void +Opcode_ae_s64_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc1000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7422000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106da000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105be000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ee000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa1008; +} + +static void +Opcode_ae_s32m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75dc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b8000; +} + +static void +Opcode_ae_s32m_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903000; +} + +static void +Opcode_ae_s32m_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e8000; +} + +static void +Opcode_ae_s32m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae1000; +} + +static void +Opcode_ae_s32m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75de000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ba000; +} + +static void +Opcode_ae_s32m_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943000; +} + +static void +Opcode_ae_s32m_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ea000; +} + +static void +Opcode_ae_s32m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa1004; +} + +static void +Opcode_ae_s32m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7420000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105bc000; +} + +static void +Opcode_ae_s32m_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983000; +} + +static void +Opcode_ae_s32m_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ec000; +} + +static void +Opcode_ae_s32m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae1004; +} + +static void +Opcode_ae_s32m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7424000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106dc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c0000; +} + +static void +Opcode_ae_s32m_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903200; +} + +static void +Opcode_ae_s32m_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f0000; +} + +static void +Opcode_ae_s32m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae1008; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8f6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10660000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10532000; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941000; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1374000; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2658000; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a000; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3e100c; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1378000; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8c2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1046a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1047e000; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900800; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132c000; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2620000; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a8000; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9c1008; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e6000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x749e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10692000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056a000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1504000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2696000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c8000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa94000c; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1546000; +} + +static void +Opcode_ae_l64_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x741c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10672000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10548000; +} + +static void +Opcode_ae_l64_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981600; +} + +static void +Opcode_ae_l64_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ba000; +} + +static void +Opcode_ae_l64_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2672000; +} + +static void +Opcode_ae_l64_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1540000; +} + +static void +Opcode_ae_l64_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb980004; +} + +static void +Opcode_ae_l64_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133e000; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7438000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ec000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d4000; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943400; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270a000; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc000c; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7590000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106bc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1059c000; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902c00; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26cc000; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a61004; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74a4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10522000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600000; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80000; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x273c000; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc1008; +} + +static void +Opcode_ae_s64_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x747a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10512000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f6000; +} + +static void +Opcode_ae_s64_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903e00; +} + +static void +Opcode_ae_s64_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2730000; +} + +static void +Opcode_ae_s64_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb81000; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19084030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10708002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10620004; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1310010; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26be000; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9971002; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74fe080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057e008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ca002; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318210; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2772000; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9961008; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7556000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10592000; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330000; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c0000; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x982100c; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7558000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10594000; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330100; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c2000; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x986100c; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c500000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe150000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c540000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a40000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1540000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf150000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1940000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1440000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb150000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7340000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900100; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1480000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc150000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19c0000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c0000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd150000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c5c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7840000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1840000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7570000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d480000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1880000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8150000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c380000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1780000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7430000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c3c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c0000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7470000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c480000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7240000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa150000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d380000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d80000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1880000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7830000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc0000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c0000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7870000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc0000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c0000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7860000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900200; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7920000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d340000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d40000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1840000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7960000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c640000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e40000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1940000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7970000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d5c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7850000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d200000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7910000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d500000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7900000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d540000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b40000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1640000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7940000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d580000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b80000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1680000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7810000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d280000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1780000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7820000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_s32x2x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2100000; +} + +static void +Opcode_ae_s32x2x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00000; +} + +static void +Opcode_ae_s32x2x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9800000; +} + +static void +Opcode_ae_s32x2x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2140000; +} + +static void +Opcode_ae_s32x2x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e40000; +} + +static void +Opcode_ae_s32x2x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9840000; +} + +static void +Opcode_ae_s32x2x2_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180000; +} + +static void +Opcode_ae_s32x2x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2040000; +} + +static void +Opcode_ae_s32x2x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d40000; +} + +static void +Opcode_ae_s32x2x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d70000; +} + +static void +Opcode_ae_s32x2x2_ip_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_s32x2x2_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0000; +} + +static void +Opcode_ae_s32x2x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080000; +} + +static void +Opcode_ae_s32x2x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d80000; +} + +static void +Opcode_ae_s32x2x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8800000; +} + +static void +Opcode_ae_s32x2x2_x_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_s32x2x2_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_s32x2x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0000; +} + +static void +Opcode_ae_s32x2x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc0000; +} + +static void +Opcode_ae_s32x2x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8840000; +} + +static void +Opcode_ae_s32x2x2_xp_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_s32x2x2_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_ae_s32x2x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21c0000; +} + +static void +Opcode_ae_s32x2x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec0000; +} + +static void +Opcode_ae_s32x2x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa840000; +} + +static void +Opcode_ae_s32x2x2rng_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c40000; +} + +static void +Opcode_ae_s32x2x2rng_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d60000; +} + +static void +Opcode_ae_s32x2x2rng_ip_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_s32x2x2rng_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80000; +} + +static void +Opcode_ae_s32x2x2rng_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c30000; +} + +static void +Opcode_ae_s32x2x2rng_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc0000; +} + +static void +Opcode_ae_s32x2x2rng_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c70000; +} + +static void +Opcode_ae_s32x2x2rng_xp_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_s32x2x2rng_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00000; +} + +static void +Opcode_ae_s32x2x2rng_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d30000; +} + +static void +Opcode_ae_s16x4x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f40000; +} + +static void +Opcode_ae_s16x4x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b40000; +} + +static void +Opcode_ae_s16x4x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d50000; +} + +static void +Opcode_ae_s16x4x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f80000; +} + +static void +Opcode_ae_s16x4x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b80000; +} + +static void +Opcode_ae_s16x4x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c20000; +} + +static void +Opcode_ae_s16x4x2_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_s16x4x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e80000; +} + +static void +Opcode_ae_s16x4x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a80000; +} + +static void +Opcode_ae_s16x4x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c10000; +} + +static void +Opcode_ae_s16x4x2_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_s16x4x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec0000; +} + +static void +Opcode_ae_s16x4x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac0000; +} + +static void +Opcode_ae_s16x4x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c50000; +} + +static void +Opcode_ae_s16x4x2_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_s16x4x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00000; +} + +static void +Opcode_ae_s16x4x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00000; +} + +static void +Opcode_ae_s16x4x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d10000; +} + +static void +Opcode_ae_s16x4x2_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140000; +} + +static void +Opcode_ae_s16x4x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ae_s16x4x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00000; +} + +static void +Opcode_ae_s16x4x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d20000; +} + +static void +Opcode_ae_s8x8x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2480000; +} + +static void +Opcode_ae_s8x8x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2180000; +} + +static void +Opcode_ae_s8x8x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8900000; +} + +static void +Opcode_ae_s8x8x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24c0000; +} + +static void +Opcode_ae_s8x8x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21c0000; +} + +static void +Opcode_ae_s8x8x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8940000; +} + +static void +Opcode_ae_s8x8x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23c0000; +} + +static void +Opcode_ae_s8x8x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0000; +} + +static void +Opcode_ae_s8x8x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe840000; +} + +static void +Opcode_ae_s8x8x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400000; +} + +static void +Opcode_ae_s8x8x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2100000; +} + +static void +Opcode_ae_s8x8x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf800000; +} + +static void +Opcode_ae_s8x8x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2440000; +} + +static void +Opcode_ae_s8x8x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2140000; +} + +static void +Opcode_ae_s8x8x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf840000; +} + +static void +Opcode_ae_s8x8x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540000; +} + +static void +Opcode_ae_s8x8x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2240000; +} + +static void +Opcode_ae_s8x8x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9940000; +} + +static void +Opcode_ae_s64x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22c0000; +} + +static void +Opcode_ae_s64x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fc0000; +} + +static void +Opcode_ae_s64x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc840000; +} + +static void +Opcode_ae_s64x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300000; +} + +static void +Opcode_ae_s64x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ae_s64x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd800000; +} + +static void +Opcode_ae_s64x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200000; +} + +static void +Opcode_ae_s64x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00000; +} + +static void +Opcode_ae_s64x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb800000; +} + +static void +Opcode_ae_s64x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2240000; +} + +static void +Opcode_ae_s64x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f40000; +} + +static void +Opcode_ae_s64x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb840000; +} + +static void +Opcode_ae_s64x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2280000; +} + +static void +Opcode_ae_s64x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f80000; +} + +static void +Opcode_ae_s64x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc800000; +} + +static void +Opcode_ae_s64x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2380000; +} + +static void +Opcode_ae_s64x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080000; +} + +static void +Opcode_ae_s64x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe800000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c580000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a80000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7800000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d4c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c0000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c0000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9150000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c600000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7930000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d240000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c40000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1740000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7950000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_s32x2x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2180000; +} + +static void +Opcode_ae_s32x2x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e80000; +} + +static void +Opcode_ae_s32x2x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800000; +} + +static void +Opcode_ae_s16x4x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fc0000; +} + +static void +Opcode_ae_s16x4x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc0000; +} + +static void +Opcode_ae_s16x4x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c60000; +} + +static void +Opcode_ae_s8x8x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500000; +} + +static void +Opcode_ae_s8x8x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200000; +} + +static void +Opcode_ae_s8x8x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9900000; +} + +static void +Opcode_ae_s64x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2340000; +} + +static void +Opcode_ae_s64x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2040000; +} + +static void +Opcode_ae_s64x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd840000; +} + +static void +Opcode_ae_s16x4x2rng_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980000; +} + +static void +Opcode_ae_s16x4x2rng_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c00000; +} + +static void +Opcode_ae_s16x4x2rng_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19c0000; +} + +static void +Opcode_ae_s16x4x2rng_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c40000; +} + +static void +Opcode_ae_s16x4x2rng_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00000; +} + +static void +Opcode_ae_s16x4x2rng_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d00000; +} + +static void +Opcode_ae_s16x4x2rng_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a40000; +} + +static void +Opcode_ae_s16x4x2rng_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d40000; +} + +static void +Opcode_ae_zalign64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b48fb4; + slotbuf[1] = 0; +} + +static void +Opcode_ae_zalign64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef70; + slotbuf[1] = 0; +} + +static void +Opcode_ae_zalign64_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069db30; +} + +static void +Opcode_ae_zalign64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab20045; +} + +static void +Opcode_ae_lalign64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f10; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lalign64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10748300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lalign64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680600; +} + +static void +Opcode_ae_lalign64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9839c01; +} + +static void +Opcode_ae_salign64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f20; + slotbuf[1] = 0; +} + +static void +Opcode_ae_salign64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10748700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_salign64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680700; +} + +static void +Opcode_ae_salign64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70ab000; +} + +static void +Opcode_ae_movalign_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b48fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movalign_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef80; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movalign_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687702; +} + +static void +Opcode_ae_movalign_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab20005; +} + +static void +Opcode_ae_la64_pp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b20fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la64_pp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afa0c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la64_pp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf500; +} + +static void +Opcode_ae_la64_pp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685602; +} + +static void +Opcode_ae_la64_pp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08540; +} + +static void +Opcode_ae_la64_pp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09a0e; +} + +static void +Opcode_ae_la64_pp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142e10c; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b50f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af00c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681703; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09a0d; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b40f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074cf0c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681701; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0920d; +} + +static void +Opcode_ae_la24pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b58f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683600; +} + +static void +Opcode_ae_la24pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09e0d; +} + +static void +Opcode_ae_la24neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b48f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681702; +} + +static void +Opcode_ae_la24neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0960d; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b70f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af80c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683603; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0160e; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b60f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af40c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683601; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0120e; +} + +static void +Opcode_ae_la24x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b78f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683700; +} + +static void +Opcode_ae_la24x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0160f; +} + +static void +Opcode_ae_la24x2neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b68f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683602; +} + +static void +Opcode_ae_la24x2neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0120f; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b08fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af20c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683703; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01e0e; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afc0c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683701; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01a0e; +} + +static void +Opcode_ae_la32x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b08fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685600; +} + +static void +Opcode_ae_la32x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01e0f; +} + +static void +Opcode_ae_la32x2neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683702; +} + +static void +Opcode_ae_la32x2neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01a0f; +} + +static void +Opcode_ae_la32x2pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b10fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2pos_pc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af60c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2pos_pc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685601; +} + +static void +Opcode_ae_la32x2pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0920e; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b10f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074cf04; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681602; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09f0e; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074cf00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681600; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09f0c; +} + +static void +Opcode_ae_la16x4pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b18f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681603; +} + +static void +Opcode_ae_la16x4pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09f0f; +} + +static void +Opcode_ae_la16x4neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b08f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681601; +} + +static void +Opcode_ae_la16x4neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09f0d; +} + +static void +Opcode_ae_la16x4pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b20f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4pos_pc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074cf08; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4pos_pc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681700; +} + +static void +Opcode_ae_la16x4pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0120d; +} + +static void +Opcode_ae_la8x8pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b28fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074eb00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685701; +} + +static void +Opcode_ae_la8x8pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09e0f; +} + +static void +Opcode_ae_la8x8neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b20fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afe0c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685603; +} + +static void +Opcode_ae_la8x8neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09a0f; +} + +static void +Opcode_ae_la8x8pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b30fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685702; +} + +static void +Opcode_ae_la8x8pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa820005; +} + +static void +Opcode_ae_la8x8neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b28fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685700; +} + +static void +Opcode_ae_la8x8neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09e0e; +} + +static void +Opcode_ae_la8x8pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b30fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8pos_pc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074eb04; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8pos_pc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685703; +} + +static void +Opcode_ae_la8x8pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa860005; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14230; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416103; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b10fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0ec02; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x686180; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x686180; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f30; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514103; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002430; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151630b; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0920f; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142810c; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14240; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416104; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b18fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0f002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x688180; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x688180; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f40; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514104; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002440; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151640b; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0960e; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142a10c; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14250; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416105; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b18fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0f402; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68a180; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68a180; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f50; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514105; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002450; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151650b; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0960f; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142c10c; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14200; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416100; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b28f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0e002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680180; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680180; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f00; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514100; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002400; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151600b; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0160d; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142210c; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14210; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416101; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b30f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0e402; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x682180; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x682180; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f10; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514101; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002410; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151610b; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01a0d; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142410c; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14220; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416102; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b38f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0e802; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x684180; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x684180; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f20; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514102; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002420; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151620b; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01e0d; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142610c; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14260; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416106; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b38fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0f802; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68c180; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68c180; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f60; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514106; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002460; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151660b; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa920005; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143010c; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14270; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416107; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b38fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0fc02; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68e180; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68e180; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f70; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514107; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002470; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151670b; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa960005; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143210c; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14280; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416108; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b40fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690180; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690180; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f80; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514108; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002480; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151680b; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa20005; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143410c; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b48fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074eb0c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687601; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8a4004; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b40fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074eb08; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687600; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa26004; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193c0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060a004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ee003; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fe000; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fe000; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006f0; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000f; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c40205; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19388030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f0002; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0040; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0040; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00800; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512000; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08205; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193c8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060c004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f0003; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00810; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512001; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48205; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19390030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060e004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0008; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f2002; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08000; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2040; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2040; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00820; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512002; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00305; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400c; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193d8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10612004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f4003; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08040; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f8040; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f8040; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00850; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512005; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48305; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400d; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193d0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10610004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f2003; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4040; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4040; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00830; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512003; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c40305; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19398030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f4002; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6040; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6040; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00840; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512004; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08305; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d838080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10736000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d6002; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea0c0; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea0c0; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00680; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510008; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08208; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d838090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d6003; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec080; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec080; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00690; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510009; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48208; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10736004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d8002; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006a0; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000a; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08209; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10736008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0104; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d8003; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x978300; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee080; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee080; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006b0; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000b; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48209; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514008; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104dc002; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x978340; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0000; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0000; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006e0; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000e; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0820b; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514009; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073600c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104da002; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec0c0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec0c0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006c0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000c; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0820a; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104da003; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee0c0; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee0c0; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006d0; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000d; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c4820a; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193a8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10614004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f6002; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fa040; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fa040; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00880; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512008; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c18201; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193e8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f6003; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fc040; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fc040; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00890; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512009; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c58201; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193b0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10616004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f8002; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008a0; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200a; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c10301; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193f0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10618004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0108; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f8003; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08080; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fe040; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fe040; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008b0; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200b; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c50301; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516000; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1061c004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fc002; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa080c0; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4080; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4080; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008e0; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200e; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c10205; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516001; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193b8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1061a004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fa002; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0080; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0080; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008c0; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200c; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c18301; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193f8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fa003; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2080; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2080; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008d0; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200d; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c58301; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10602004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e8003; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2000; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2000; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48201; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ea002; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4000; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4000; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00301; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10604004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ea003; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x978380; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6000; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6000; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c40301; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400a; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19380030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10608004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ee002; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9783c0; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fc000; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fc000; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00205; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400b; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10606004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ec002; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f8000; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f8000; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08301; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ec003; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fa000; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fa000; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48301; +} + +static void +Opcode_ae_la24_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073e004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e2003; +} + +static void +Opcode_ae_la24_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c4830a; +} + +static void +Opcode_ae_la24_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e4002; +} + +static void +Opcode_ae_la24_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0830b; +} + +static void +Opcode_ae_la24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073e008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e4003; +} + +static void +Opcode_ae_la24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c4830b; +} + +static void +Opcode_ae_la24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e8002; +} + +static void +Opcode_ae_la24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08201; +} + +static void +Opcode_ae_la24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073e00c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e6002; +} + +static void +Opcode_ae_la24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00201; +} + +static void +Opcode_ae_la24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e6003; +} + +static void +Opcode_ae_la24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c40201; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073c004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104dc003; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c4820b; +} + +static void +Opcode_ae_la24x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d870080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104de002; +} + +static void +Opcode_ae_la24x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08308; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d878080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073c008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104de003; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48308; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e2002; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0830a; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d870090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073c00c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e0002; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08309; +} + +static void +Opcode_ae_la24x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d878090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e0003; +} + +static void +Opcode_ae_la24x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48309; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a2004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ee001; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a60; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000d; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f0001; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a70; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000e; +} + +static void +Opcode_ae_sa32x2_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a2008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f2001; +} + +static void +Opcode_ae_sa32x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a80; +} + +static void +Opcode_ae_sa32x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000f; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a200c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f4001; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a90; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010c; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19038010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a6004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fa001; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00ac0; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010f; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f6001; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00aa0; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010d; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f8001; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00ab0; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010e; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10620004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fe002; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008f0; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0000; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fe003; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a00; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0001; +} + +static void +Opcode_ae_sa16x4_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10622004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0001; +} + +static void +Opcode_ae_sa16x4_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a10; +} + +static void +Opcode_ae_sa16x4_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0002; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10624004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c2001; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a20; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0003; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10628004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c8001; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a50; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0102; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10626004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c4001; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a30; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0100; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c6001; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a40; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0101; +} + +static void +Opcode_ae_sa8x8_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19078010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a6008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fc001; +} + +static void +Opcode_ae_sa8x8_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00ad0; +} + +static void +Opcode_ae_sa8x8_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0200; +} + +static void +Opcode_ae_sa8x8_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190b8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fe001; +} + +static void +Opcode_ae_sa8x8_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00ae0; +} + +static void +Opcode_ae_sa8x8_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0201; +} + +static void +Opcode_ae_sa8x8_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190f8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a600c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0000; +} + +static void +Opcode_ae_sa8x8_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00af0; +} + +static void +Opcode_ae_sa8x8_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0202; +} + +static void +Opcode_ae_sa8x8_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19138010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0001; +} + +static void +Opcode_ae_sa8x8_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00c00; +} + +static void +Opcode_ae_sa8x8_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0203; +} + +static void +Opcode_ae_sa8x8_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191f8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2000; +} + +static void +Opcode_ae_sa8x8_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00c30; +} + +static void +Opcode_ae_sa8x8_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0302; +} + +static void +Opcode_ae_sa8x8_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19178010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0002; +} + +static void +Opcode_ae_sa8x8_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00c10; +} + +static void +Opcode_ae_sa8x8_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0300; +} + +static void +Opcode_ae_sa8x8_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191b8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0003; +} + +static void +Opcode_ae_sa8x8_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00c20; +} + +static void +Opcode_ae_sa8x8_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0301; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063a004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e2001; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000b; +} + +static void +Opcode_ae_sa32x2f24_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e4001; +} + +static void +Opcode_ae_sa32x2f24_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0108; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063c004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e6001; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0109; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ec001; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000c; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063e004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e8001; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010a; +} + +static void +Opcode_ae_sa32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ea001; +} + +static void +Opcode_ae_sa32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010b; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530070; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10632004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d6001; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0105; +} + +static void +Opcode_ae_sa24_l_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538070; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d8001; +} + +static void +Opcode_ae_sa24_l_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0106; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10634004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104da001; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0107; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10638004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e0001; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000a; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10636004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104dc001; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0008; +} + +static void +Opcode_ae_sa24_l_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104de001; +} + +static void +Opcode_ae_sa24_l_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0009; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530040; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1062a004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ca001; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0103; +} + +static void +Opcode_ae_sa24x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538040; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104cc001; +} + +static void +Opcode_ae_sa24x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0004; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530050; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1062c004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ce001; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0005; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538060; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10630004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d4001; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0104; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538050; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1062e004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d0001; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0006; +} + +static void +Opcode_ae_sa24x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530060; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d2001; +} + +static void +Opcode_ae_sa24x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0007; +} + +static void +Opcode_ae_addicirc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a00f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addicirc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e04000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addicirc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9838c00; +} + +static void +Opcode_ae_addicirc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1520000; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a12f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6200; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7200; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a5400; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1523200; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a0af00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6100; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7100; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a7000; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1523100; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a02f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6000; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7000; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a5000; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1523000; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18800f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481900; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983c400; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18840f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481b00; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983e400; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18880f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481c00; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9838800; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18940f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481f00; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983e800; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188c0f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481e00; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983a800; +} + +static void +Opcode_ae_s32ra64s_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18900f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481d00; +} + +static void +Opcode_ae_s32ra64s_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983c800; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18780f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481400; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9838000; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18781f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481600; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983a000; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187c0b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481500; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983c000; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187c1f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481a00; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983a400; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187c0f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481700; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983e000; +} + +static void +Opcode_ae_s24ra64s_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187c1b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481800; +} + +static void +Opcode_ae_s24ra64s_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9838400; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0004; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830203; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0008; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830302; +} + +static void +Opcode_ae_s16x4ra32s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4ra32s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4ra32s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0000; +} + +static void +Opcode_ae_s16x4ra32s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830202; +} + +static void +Opcode_ae_addbrba32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74fa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addbrba32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1efa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addbrba32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1be000; +} + +static void +Opcode_ae_addbrba32_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e4000; +} + +static void +Opcode_ae_addbrba32_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b5000; +} + +static void +Opcode_ae_addbrba32_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa02000; +} + +static void +Opcode_ae_addbrba32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9921004; +} + +static void +Opcode_ae_addbrba32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1553000; +} + +static void +Opcode_ae_s32x2_l_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340000; +} + +static void +Opcode_ae_bitswap_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191fd030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bitswap_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0d002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bitswap_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9002; +} + +static void +Opcode_ae_bitswap_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a5000; +} + +static void +Opcode_ae_bitswap_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1597004; +} + +static void +Opcode_ae_mul32js_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32js_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80211420; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32js_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x560020; +} + +static void +Opcode_ae_mul32js_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40b00a1; +} + +static void +Opcode_ae_mul32js_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x510020; +} + +static void +Opcode_ae_mul32js_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c0008; +} + +static void +Opcode_ae_mul32js_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700220; +} + +static void +Opcode_ae_mul32js_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a800; +} + +static void +Opcode_ae_mul32js_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130040; +} + +static void +Opcode_ae_mul32js_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00d0; +} + +static void +Opcode_ae_mul32js_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2c0000; +} + +static void +Opcode_ae_mul32js_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8009e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsub32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsub32s_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000020; +} + +static void +Opcode_ae_addandsub32s_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsub32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9400000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5400000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000026; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsub32js_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsub32js_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_addandsub32js_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; +} + +static void +Opcode_ae_addandsub32js_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_addandsub32js_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_addandsub32js_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsub32js_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8400800; +} + +static void +Opcode_ae_addandsub32js_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5300000; +} + +static void +Opcode_ae_addandsub32js_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000025; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000040; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9400800; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5500000; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000027; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000060; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa400000; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5600000; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000028; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000080; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa400800; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5700000; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000029; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addrng32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007860; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subrng32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rng32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40069c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel16i_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82050000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_sel16i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sel16i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_sel16i_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000a0; +} + +static void +Opcode_ae_sel16i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200000; +} + +static void +Opcode_ae_sel16i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700000; +} + +static void +Opcode_ae_sel16i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_sel16i_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c050000; +} + +static void +Opcode_ae_sel16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7420000; +} + +static void +Opcode_ae_sel16i_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40080002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel16i_n_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_sel16i_n_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_sel16i_n_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00380; +} + +static void +Opcode_ae_shortswap_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401d1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movab4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af007; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movab4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a7010; +} + +static void +Opcode_ae_movab2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af006; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movab2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a7000; +} + +static void +Opcode_ae_movab_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movab_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a3002; +} + +static void +Opcode_ae_movba_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movba_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a3001; +} + +static void +Opcode_ae_movba1x2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movba1x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa820000; +} + +static void +Opcode_ae_movba4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af009; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movba4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa862004; +} + +static void +Opcode_ae_movba2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movba2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa822004; +} + +static void +Opcode_ae_movb2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af016; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movb4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af027; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192c0033; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt16x4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt16x4_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132c400; +} + +static void +Opcode_ae_movt16x4_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x124400; +} + +static void +Opcode_ae_movt16x4_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00221; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9832021; +} + +static void +Opcode_ae_movf16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192c0031; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf16x4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf16x4_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132c000; +} + +static void +Opcode_ae_movf16x4_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x124000; +} + +static void +Opcode_ae_movf16x4_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00201; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830021; +} + +static void +Opcode_ae_movt32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800f1; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt32x2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10720010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt32x2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132a000; +} + +static void +Opcode_ae_movt32x2_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120400; +} + +static void +Opcode_ae_movt32x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00021; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7468011; +} + +static void +Opcode_ae_movf32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf32x2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10720000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf32x2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1328000; +} + +static void +Opcode_ae_movf32x2_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ae_movf32x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7468001; +} + +static void +Opcode_ae_movsara7x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9969e04; +} + +static void +Opcode_ae_movsara7x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1523300; +} + +static void +Opcode_ae_movsard7_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19140026; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movsard7_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c401; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movsard7_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058a0c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movsard7_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069e030; +} + +static void +Opcode_ae_movsard7_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8a6004; +} + +static void +Opcode_ae_movasar_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19036310; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movasar_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c602; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movasar_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e19e0; +} + +static void +Opcode_ae_movda32x2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198000; +} + +static void +Opcode_ae_movda32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a79000; +} + +static void +Opcode_ae_movda32x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154a000; +} + +static void +Opcode_ae_movda32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7528003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00801; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107820e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0300; +} + +static void +Opcode_ae_movda32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640650; +} + +static void +Opcode_ae_movda32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e1080; +} + +static void +Opcode_ae_movda32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516004; +} + +static void +Opcode_ae_movda16x2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640400; +} + +static void +Opcode_ae_movda16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7526003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda16_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0310e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107800e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda16_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0203; +} + +static void +Opcode_ae_movda16_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640640; +} + +static void +Opcode_ae_movda16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e1060; +} + +static void +Opcode_ae_movda16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d6003; +} + +static void +Opcode_ae_movi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d836080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa00c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000c; +} + +static void +Opcode_ae_movi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640600; +} + +static void +Opcode_ae_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a1000; +} + +static void +Opcode_ae_movi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1554004; +} + +static void +Opcode_ae_movi_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa400024; +} + +static void +Opcode_ae_movi_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44100003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74b4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198100; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a71004; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158a000; +} + +static void +Opcode_ae_sat16x4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000a0; +} + +static void +Opcode_ae_sat16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000026; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03904; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98320e0; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40189002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000022; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03804; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107800c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98300e0; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40181002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19080026; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00802; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9836061; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800026; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401c9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19080022; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107800a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9836021; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800025; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401c1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvta32f24s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191ac030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32f24s_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e4b400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32f24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01708; +} + +static void +Opcode_ae_cvta32f24s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191a6030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32f24s_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e43400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32f24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01308; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1053e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640300; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a71000; +} + +static void +Opcode_ae_cvtp24a16x2_lh_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640100; +} + +static void +Opcode_ae_cvtp24a16x2_hl_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640200; +} + +static void +Opcode_ae_cvtp24a16x2_hh_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640000; +} + +static void +Opcode_ae_truncp24q48x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40098c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d180000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580000; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81a0300; +} + +static void +Opcode_ae_trunci32x2f64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c280000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunci32x2f64s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10202000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunci32x2f64s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x804000; +} + +static void +Opcode_ae_trunci32x2f64s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1680000; +} + +static void +Opcode_ae_trunca32f64s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d100000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca32f64s_l_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_trunca32f64s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81a0200; +} + +static void +Opcode_ae_trunci32f64s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c200000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunci32f64s_l_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600000; +} + +static void +Opcode_ae_truncp16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401d9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round32x2f64ssym_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80f0000; +} + +static void +Opcode_ae_round32x2f64ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round32x2f64sasym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280400; +} + +static void +Opcode_ae_round32x2f64sasym_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80e8000; +} + +static void +Opcode_ae_round32x2f64sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round32x2f48ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round32x2f48sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round16x4f32ssym_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800090; +} + +static void +Opcode_ae_round16x4f32ssym_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80e0000; +} + +static void +Opcode_ae_round16x4f32ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round16x4f32sasym_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104b0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_round16x4f32sasym_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800080; +} + +static void +Opcode_ae_round16x4f32sasym_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80d8000; +} + +static void +Opcode_ae_round16x4f32sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round24x2f48ssym_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104b8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_round24x2f48ssym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280000; +} + +static void +Opcode_ae_round24x2f48ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round24x2f48sasym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180e00; +} + +static void +Opcode_ae_round24x2f48sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsp16q48x2sym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsp16q48x2asym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_minabs32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_maxabs32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsp16f24sym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80106862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsp16f24asym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mov_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800f; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mov_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160011; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mov_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1904002e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mov_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03b06; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mov_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80f11801; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mov_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780060; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mov_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c010c; +} + +static void +Opcode_ae_mov_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x568000; +} + +static void +Opcode_ae_mov_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40b80a0; +} + +static void +Opcode_ae_mov_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c0000; +} + +static void +Opcode_ae_mov_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020f; +} + +static void +Opcode_ae_mov_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133ac00; +} + +static void +Opcode_ae_mov_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08100; +} + +static void +Opcode_ae_mov_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x124800; +} + +static void +Opcode_ae_mov_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000020; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mov_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00540; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mov_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000800; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mov_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2880080; +} + +static void +Opcode_ae_mov_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x229860; +} + +static void +Opcode_ae_mov_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25402e0; +} + +static void +Opcode_ae_mov_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00361; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mov_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d15801d; +} + +static void +Opcode_ae_mov_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98340e1; +} + +static void +Opcode_ae_mov_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800024; +} + +static void +Opcode_ae_mov_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401b9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movt64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt64_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1324000; +} + +static void +Opcode_ae_movt64_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c000; +} + +static void +Opcode_ae_movt64_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8b00201; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742a001; +} + +static void +Opcode_ae_movf64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf64_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1320000; +} + +static void +Opcode_ae_movf64_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118000; +} + +static void +Opcode_ae_movf64_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8b00001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7428001; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7524003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0310c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0202; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e1040; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1596003; +} + +static void +Opcode_ae_cvt48a32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48a32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03108; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48a32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0200; +} + +static void +Opcode_ae_cvt48a32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e1000; +} + +static void +Opcode_ae_cvt48a32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516003; +} + +static void +Opcode_ae_cvt64a32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7522003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt64a32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0310a; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt64a32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0201; +} + +static void +Opcode_ae_cvt64a32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e1020; +} + +static void +Opcode_ae_cvt64a32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556003; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1904002a; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03a06; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98340a1; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401b1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19040026; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03906; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9834061; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401a9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19040022; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03806; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9834021; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401a1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900002e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03b04; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98360e0; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40199002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900002a; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03a04; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98340e0; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40191002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat48s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa158000; +} + +static void +Opcode_ae_sat48s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800f6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_satq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800fe462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800ee462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_truncq32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98360a1; +} + +static void +Opcode_ae_truncq32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401e1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_minabs64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_maxabs64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsq32f48sym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80306862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsq32f48asym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80206862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_trunca32q48_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191f4030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca32q48_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0cc01; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929604; +} + +static void +Opcode_ae_movad32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191e4030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e7b400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a006; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_l_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf000; +} + +static void +Opcode_ae_movad32_l_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069a030; +} + +static void +Opcode_ae_movad32_l_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2986010; +} + +static void +Opcode_ae_movad32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09f08; +} + +static void +Opcode_ae_movad32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191be030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e73400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_h_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_h_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10698030; +} + +static void +Opcode_ae_movad32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09b08; +} + +static void +Opcode_ae_movad16_3_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191bc030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_3_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6b400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_3_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_3_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10696030; +} + +static void +Opcode_ae_movad16_3_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09708; +} + +static void +Opcode_ae_movad16_2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191b6030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e63400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071800f; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10694030; +} + +static void +Opcode_ae_movad16_2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09308; +} + +static void +Opcode_ae_movad16_1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191b4030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e5b400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071800e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10692030; +} + +static void +Opcode_ae_movad16_1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01f08; +} + +static void +Opcode_ae_movad16_0_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191ae030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_0_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e53400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_0_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071800b; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_0_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690030; +} + +static void +Opcode_ae_movad16_0_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2946010; +} + +static void +Opcode_ae_movad16_0_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01b08; +} + +static void +Opcode_ae_sra64_32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d818000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sra64_32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1000; +} + +static void +Opcode_ae_pksr32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19340032; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6340c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr32_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x55a000; +} + +static void +Opcode_ae_pksr32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c008c; +} + +static void +Opcode_ae_pksr32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17401e0; +} + +static void +Opcode_ae_pksr32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338000; +} + +static void +Opcode_ae_pksr32_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128008; +} + +static void +Opcode_ae_pksr32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830060; +} + +static void +Opcode_ae_pksr32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa200024; +} + +static void +Opcode_ae_pksr24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19340031; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr24_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6320c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr24_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x559000; +} + +static void +Opcode_ae_pksr24_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c001c; +} + +static void +Opcode_ae_pksr24_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17201e0; +} + +static void +Opcode_ae_pksr24_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132e400; +} + +static void +Opcode_ae_pksr24_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128004; +} + +static void +Opcode_ae_pksr24_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa100024; +} + +static void +Opcode_ae_pksrf32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19340033; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksrf32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6360c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksrf32_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x55b000; +} + +static void +Opcode_ae_pksrf32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c009c; +} + +static void +Opcode_ae_pksrf32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17601e0; +} + +static void +Opcode_ae_pksrf32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338400; +} + +static void +Opcode_ae_pksrf32_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12800c; +} + +static void +Opcode_ae_pksrf32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98300a0; +} + +static void +Opcode_ae_pksrf32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa300024; +} + +static void +Opcode_ae_pksr16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19340030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6300c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr16_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x558000; +} + +static void +Opcode_ae_pksr16_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c000c; +} + +static void +Opcode_ae_pksr16_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17001e0; +} + +static void +Opcode_ae_pksr16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132e000; +} + +static void +Opcode_ae_pksr16_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128000; +} + +static void +Opcode_ae_pksr16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830020; +} + +static void +Opcode_ae_pksr16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000024; +} + +static void +Opcode_ae_trunca16p24s_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a00b; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929204; +} + +static void +Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929c04; +} + +static void +Opcode_ae_add32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480000; +} + +static void +Opcode_ae_add32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89a0c00; +} + +static void +Opcode_ae_add32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8038000; +} + +static void +Opcode_ae_add32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005c60; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18500b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280600; +} + +static void +Opcode_ae_sub32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8110000; +} + +static void +Opcode_ae_sub32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addsub32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18100b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addsub32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080200; +} + +static void +Opcode_ae_addsub32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8070000; +} + +static void +Opcode_ae_addsub32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subadd32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18680b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subadd32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380c00; +} + +static void +Opcode_ae_subadd32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8130000; +} + +static void +Opcode_ae_subadd32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88a0800; +} + +static void +Opcode_ae_add16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8020000; +} + +static void +Opcode_ae_add16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18400f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280800; +} + +static void +Opcode_ae_sub16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80f8000; +} + +static void +Opcode_ae_sub16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ba0800; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8050000; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006860; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addsub32_hl_lh_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18180f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addsub32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8088000; +} + +static void +Opcode_ae_addsub32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f30; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0220; +} + +static void +Opcode_ae_neg32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2d8000; +} + +static void +Opcode_ae_neg32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800b6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f60; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0060; +} + +static void +Opcode_ae_abs32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3e8000; +} + +static void +Opcode_ae_abs32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8003e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg32_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2e8000; +} + +static void +Opcode_ae_neg32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800c6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89a0800; +} + +static void +Opcode_ae_add24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8030000; +} + +static void +Opcode_ae_add24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005860; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18480f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280200; +} + +static void +Opcode_ae_sub24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8108000; +} + +static void +Opcode_ae_sub24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10498000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add32s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480400; +} + +static void +Opcode_ae_add32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002400; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_add32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8aa0800; +} + +static void +Opcode_ae_add32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8040000; +} + +static void +Opcode_ae_add32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18500f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_sub32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280a00; +} + +static void +Opcode_ae_sub32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8118000; +} + +static void +Opcode_ae_sub32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addsub32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18100f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addsub32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080600; +} + +static void +Opcode_ae_addsub32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8078000; +} + +static void +Opcode_ae_addsub32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subadd32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18680f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subadd32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380200; +} + +static void +Opcode_ae_subadd32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8138000; +} + +static void +Opcode_ae_subadd32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004062; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10490000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add16s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_add16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88a0c00; +} + +static void +Opcode_ae_add16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8028000; +} + +static void +Opcode_ae_add16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005460; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18480b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub16s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002c00; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_sub16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280c00; +} + +static void +Opcode_ae_sub16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8100000; +} + +static void +Opcode_ae_sub16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002062; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8aa0c00; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8048000; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006460; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addsub32s_hl_lh_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18180b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addsub32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8080000; +} + +static void +Opcode_ae_addsub32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f20; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg24s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107380f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0200; +} + +static void +Opcode_ae_neg24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2d0000; +} + +static void +Opcode_ae_neg24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800ae462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f50; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs24s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738050; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0040; +} + +static void +Opcode_ae_abs24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3c8000; +} + +static void +Opcode_ae_abs24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80036462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f40; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780040; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003860; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_neg32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0240; +} + +static void +Opcode_ae_neg32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2e0000; +} + +static void +Opcode_ae_neg32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800be462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f70; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107380d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003c00; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_abs32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0080; +} + +static void +Opcode_ae_abs32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa390000; +} + +static void +Opcode_ae_abs32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80046462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f10; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107380b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg16s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003c40; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_neg16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00f0; +} + +static void +Opcode_ae_neg16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2c8000; +} + +static void +Opcode_ae_neg16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800a6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f40; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs16s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80211400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs16s_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x560000; +} + +static void +Opcode_ae_abs16s_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40b00a0; +} + +static void +Opcode_ae_abs16s_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x510000; +} + +static void +Opcode_ae_abs16s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003800; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_abs16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0020; +} + +static void +Opcode_ae_abs16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3a8000; +} + +static void +Opcode_ae_abs16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8002e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f30; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0000; +} + +static void +Opcode_ae_abs16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa388000; +} + +static void +Opcode_ae_abs16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80026462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16js_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc16js_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b001c0; +} + +static void +Opcode_ae_mulc16js_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16js_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc16js_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b001e0; +} + +static void +Opcode_ae_mulc16js_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16js_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac16js_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f003c0; +} + +static void +Opcode_ae_mulac16js_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16js_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac16js_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f003e0; +} + +static void +Opcode_ae_mulac16js_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_lt16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880009; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340014; +} + +static void +Opcode_ae_lt16_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400e0; +} + +static void +Opcode_ae_lt16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2a00; +} + +static void +Opcode_ae_le16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880205; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10749300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1348013; +} + +static void +Opcode_ae_le16_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25403c0; +} + +static void +Opcode_ae_le16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022e00; +} + +static void +Opcode_ae_eq16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880005; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10749100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340013; +} + +static void +Opcode_ae_eq16_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25401c0; +} + +static void +Opcode_ae_eq16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022a00; +} + +static void +Opcode_ae_lt32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10749000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340012; +} + +static void +Opcode_ae_lt32_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400c0; +} + +static void +Opcode_ae_lt32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022800; +} + +static void +Opcode_ae_le32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d88010e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10741100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340011; +} + +static void +Opcode_ae_le32_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25001e0; +} + +static void +Opcode_ae_le32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022400; +} + +static void +Opcode_ae_eq32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d88000e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10741000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340010; +} + +static void +Opcode_ae_eq32_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000e0; +} + +static void +Opcode_ae_eq32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022000; +} + +static void +Opcode_ae_min32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18300f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0110080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104a8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min32_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ae_min32_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40a00a0; +} + +static void +Opcode_ae_min32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180c00; +} + +static void +Opcode_ae_min32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80b0000; +} + +static void +Opcode_ae_min32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_max32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18200f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0110020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max32_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x528000; +} + +static void +Opcode_ae_max32_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40880a0; +} + +static void +Opcode_ae_max32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080e00; +} + +static void +Opcode_ae_max32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8098000; +} + +static void +Opcode_ae_max32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_minmax32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80c8000; +} + +static void +Opcode_ae_minmax32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_minmax16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80c0000; +} + +static void +Opcode_ae_minmax16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_min16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18300b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0110060; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min16_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x538000; +} + +static void +Opcode_ae_min16_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40980a0; +} + +static void +Opcode_ae_min16_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x508000; +} + +static void +Opcode_ae_min16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180800; +} + +static void +Opcode_ae_min16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a8000; +} + +static void +Opcode_ae_min16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_max16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18200b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0110000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max16_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x520000; +} + +static void +Opcode_ae_max16_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40800a0; +} + +static void +Opcode_ae_max16_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_max16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080a00; +} + +static void +Opcode_ae_max16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8090000; +} + +static void +Opcode_ae_max16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ba0c00; +} + +static void +Opcode_ae_add64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8058000; +} + +static void +Opcode_ae_add64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006c60; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18580b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280e00; +} + +static void +Opcode_ae_sub64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8120000; +} + +static void +Opcode_ae_sub64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003062; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f50; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0260; +} + +static void +Opcode_ae_neg64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2f0000; +} + +static void +Opcode_ae_neg64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800ce462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f80; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00a0; +} + +static void +Opcode_ae_abs64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa398000; +} + +static void +Opcode_ae_abs64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8004e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addsq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18080f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addsq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080c00; +} + +static void +Opcode_ae_addsq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8068000; +} + +static void +Opcode_ae_addsq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007c60; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subsq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18700b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subsq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380600; +} + +static void +Opcode_ae_subsq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8140000; +} + +static void +Opcode_ae_subsq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080000; +} + +static void +Opcode_ae_add64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8060000; +} + +static void +Opcode_ae_add64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18580f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380000; +} + +static void +Opcode_ae_sub64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8128000; +} + +static void +Opcode_ae_sub64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_negsq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f80; + slotbuf[1] = 0; +} + +static void +Opcode_ae_negsq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a02c0; +} + +static void +Opcode_ae_negsq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa058000; +} + +static void +Opcode_ae_negsq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800e6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abssq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80fc0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0030; +} + +static void +Opcode_ae_abssq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3b8000; +} + +static void +Opcode_ae_abssq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80066462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f60; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0280; +} + +static void +Opcode_ae_neg64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2f8000; +} + +static void +Opcode_ae_neg64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800d6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00c0; +} + +static void +Opcode_ae_abs64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3b0000; +} + +static void +Opcode_ae_abs64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80056462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_and_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_and_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7428000; +} + +static void +Opcode_ae_and_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40080c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_nand_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nand_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742a000; +} + +static void +Opcode_ae_nand_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40088c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_or_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880040; + slotbuf[1] = 0; +} + +static void +Opcode_ae_or_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742c000; +} + +static void +Opcode_ae_or_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40090c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_xor_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880050; + slotbuf[1] = 0; +} + +static void +Opcode_ae_xor_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742e000; +} + +static void +Opcode_ae_xor_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400a0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slai24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c800000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8424003; +} + +static void +Opcode_ae_slai24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40006003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srli24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c810000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srli24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842400b; +} + +static void +Opcode_ae_srli24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c808000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8424007; +} + +static void +Opcode_ae_srai24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40007403; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19238010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c18205; +} + +static void +Opcode_ae_slas24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42080c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srls24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193b8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srls24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04308; +} + +static void +Opcode_ae_srls24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420e0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sras24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19338010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sras24_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500d01; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sras24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c18305; +} + +static void +Opcode_ae_sras24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420c0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c820000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1204; +} + +static void +Opcode_ae_srai16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42080803; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai16r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c822000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai16r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1304; +} + +static void +Opcode_ae_srai16r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slai32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c804000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842c003; +} + +static void +Opcode_ae_slai32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40006803; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srli32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c812000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srli32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842600b; +} + +static void +Opcode_ae_srli32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000403; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8426007; +} + +static void +Opcode_ae_srai32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40007803; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai32r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842c007; +} + +static void +Opcode_ae_srai32r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40007c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1923c010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1c205; +} + +static void +Opcode_ae_slas32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42090c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srls32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193ba010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srls32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c06308; +} + +static void +Opcode_ae_srls32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420e8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sras32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1933a010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sras32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1a305; +} + +static void +Opcode_ae_sras32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420c8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaa32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d814000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8208; +} + +static void +Opcode_ae_srla32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c828000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1008; +} + +static void +Opcode_ae_sraa32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1200; +} + +static void +Opcode_ae_slai16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c81e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a830c; +} + +static void +Opcode_ae_slai16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000803; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaa16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c816000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8108; +} + +static void +Opcode_ae_sraa16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d81c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9000; +} + +static void +Opcode_ae_sraa16rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d81a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa16rs_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa16rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1100; +} + +static void +Opcode_ae_slai24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c802000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8426003; +} + +static void +Opcode_ae_slai24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40006403; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1923a010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas24s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1a205; +} + +static void +Opcode_ae_slas24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42088c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slai32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c806000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842e003; +} + +static void +Opcode_ae_slai32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40006c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1923e010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1e205; +} + +static void +Opcode_ae_slas32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42098c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaa32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d816000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8308; +} + +static void +Opcode_ae_sraa32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x748c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9200; +} + +static void +Opcode_ae_sraa32rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa32rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1300; +} + +static void +Opcode_ae_slasq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192bc010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c14305; +} + +static void +Opcode_ae_slasq56_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420b0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srlsq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193be010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c06309; +} + +static void +Opcode_ae_srlsq56_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420f8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srasq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1933e010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1e305; +} + +static void +Opcode_ae_srasq56_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420d8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaaq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c818000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaaq56_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a020c; +} + +static void +Opcode_ae_srlaq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c82e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9108; +} + +static void +Opcode_ae_sraaq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x758e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraaq56_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9104; +} + +static void +Opcode_ae_slai64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a0000; +} + +static void +Opcode_ae_slai64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srli64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7408000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srli64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a0008; +} + +static void +Opcode_ae_srli64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40004003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7406000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8004; +} + +static void +Opcode_ae_srai64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4001a003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192b8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c10305; +} + +static void +Opcode_ae_slas64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420a0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srls64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193bc010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srls64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04309; +} + +static void +Opcode_ae_srls64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420f0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sras64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1933c010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sras64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1c305; +} + +static void +Opcode_ae_sras64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420d0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaa64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a000c; +} + +static void +Opcode_ae_srla64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c82a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1108; +} + +static void +Opcode_ae_sraa64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1004; +} + +static void +Opcode_ae_slaisq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7404000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a0004; +} + +static void +Opcode_ae_slaisq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40012003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slassq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192be010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slassq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c16305; +} + +static void +Opcode_ae_slassq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420b8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaasq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c81a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaasq56s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a030c; +} + +static void +Opcode_ae_slai64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7402000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8000; +} + +static void +Opcode_ae_slai64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000a003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192ba010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c12305; +} + +static void +Opcode_ae_slas64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420a8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaa64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x748a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a010c; +} + +static void +Opcode_ae_lt64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt64_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1310000; +} + +static void +Opcode_ae_lt64_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000c0; +} + +static void +Opcode_ae_lt64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6202000; +} + +static void +Opcode_ae_le64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le64_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300010; +} + +static void +Opcode_ae_le64_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000a0; +} + +static void +Opcode_ae_le64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6102000; +} + +static void +Opcode_ae_eq64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq64_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ae_eq64_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500080; +} + +static void +Opcode_ae_eq64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002000; +} + +static void +Opcode_ae_max64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18280b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180000; +} + +static void +Opcode_ae_max64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_min64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18380b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180200; +} + +static void +Opcode_ae_min64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_nsa64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191e6030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsa64_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0c001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsa64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929004; +} + +static void +Opcode_ae_nsaz16_0_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191ec030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz16_0_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0c401; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz16_0_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a007; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz16_0_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929404; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191ee030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0c801; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a00a; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929804; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca004800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200280; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d001a0; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce001c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100140; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72001a0; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002a0; +} + +static void +Opcode_ae_mul32_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00260; +} + +static void +Opcode_ae_mul32_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88d00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8001c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000e0; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71001c0; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32ra_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca001800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32ra_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70001e0; +} + +static void +Opcode_ae_mulf32ra_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8004800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200260; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d00180; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc001c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100120; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7200180; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00280; +} + +static void +Opcode_ae_mul32_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00240; +} + +static void +Opcode_ae_mul32_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ec00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce001800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000c0; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71001a0; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32ra_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8001800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32ra_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70001c0; +} + +static void +Opcode_ae_mulf32ra_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce004400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200240; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c001e0; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca001c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100100; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71001e0; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00260; +} + +static void +Opcode_ae_mul32_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00220; +} + +static void +Opcode_ae_mul32_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8cc00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc001800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000a0; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7100180; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32ra_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce001400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32ra_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70001a0; +} + +static void +Opcode_ae_mulf32ra_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000240; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68001a0; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8bf00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00160; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7900160; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f500040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6003400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000e0; +} + +static void +Opcode_ae_mula32_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f000a0; +} + +static void +Opcode_ae_mula32_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00100; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7600160; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89500040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32ra_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32ra_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7300160; +} + +static void +Opcode_ae_mulaf32ra_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000220; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800180; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89f00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00140; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7800160; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d500040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6003000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000c0; +} + +static void +Opcode_ae_mula32_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00080; +} + +static void +Opcode_ae_mula32_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000e0; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7500160; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32ra_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32ra_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7200160; +} + +static void +Opcode_ae_mulaf32ra_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000200; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67001e0; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8fe00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00120; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7700160; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b500040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6002c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000a0; +} + +static void +Opcode_ae_mula32_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00060; +} + +static void +Opcode_ae_mula32_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000c0; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400160; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32ra_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32ra_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7100160; +} + +static void +Opcode_ae_mulaf32ra_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f300040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14002a0; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400280; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc006800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300240; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200220; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca005800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300080; +} + +static void +Opcode_ae_muls32_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60002a0; +} + +static void +Opcode_ae_muls32_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce006400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13001e0; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61003c0; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32ra_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8006400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32ra_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100360; +} + +static void +Opcode_ae_mulsf32ra_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400280; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400260; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca006800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300220; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200200; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8005800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300060; +} + +static void +Opcode_ae_muls32_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000280; +} + +static void +Opcode_ae_muls32_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc006400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13001c0; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61003a0; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32ra_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32ra_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100340; +} + +static void +Opcode_ae_mulsf32ra_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400260; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400240; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8006800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300200; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61003e0; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce005400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300040; +} + +static void +Opcode_ae_muls32_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000260; +} + +static void +Opcode_ae_muls32_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca006400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13001a0; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100380; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32ra_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32ra_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100320; +} + +static void +Opcode_ae_mulsf32ra_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32u_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32u_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00140; +} + +static void +Opcode_ae_mul32u_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00100; +} + +static void +Opcode_ae_mula32u_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32u_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00380; +} + +static void +Opcode_ae_mula32u_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00340; +} + +static void +Opcode_ae_muls32u_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc004c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32u_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200320; +} + +static void +Opcode_ae_muls32u_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e001c0; +} + +static void +Opcode_ae_mulf16ss_33_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000180; +} + +static void +Opcode_ae_mulf16ss_33_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f00180; +} + +static void +Opcode_ae_mulf16ss_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f001e0; +} + +static void +Opcode_ae_mulf16ss_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_21_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e001e0; +} + +static void +Opcode_ae_mulf16ss_21_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_31_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f001c0; +} + +static void +Opcode_ae_mulf16ss_31_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_30_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f001a0; +} + +static void +Opcode_ae_mulf16ss_30_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e00180; +} + +static void +Opcode_ae_mulf16ss_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_20_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e001c0; +} + +static void +Opcode_ae_mulf16ss_20_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_11_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e001a0; +} + +static void +Opcode_ae_mulf16ss_11_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc001400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100080; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d001e0; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_33_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100300; +} + +static void +Opcode_ae_mulsf16ss_33_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100280; +} + +static void +Opcode_ae_mulsf16ss_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61002e0; +} + +static void +Opcode_ae_mulsf16ss_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_21_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100260; +} + +static void +Opcode_ae_mulsf16ss_21_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_31_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61002c0; +} + +static void +Opcode_ae_mulsf16ss_31_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_30_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61002a0; +} + +static void +Opcode_ae_mulsf16ss_30_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100200; +} + +static void +Opcode_ae_mulsf16ss_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_20_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100240; +} + +static void +Opcode_ae_mulsf16ss_20_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_11_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100220; +} + +static void +Opcode_ae_mulsf16ss_11_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300180; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60003e0; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_33_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000160; +} + +static void +Opcode_ae_mulaf16ss_33_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d300040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c00160; +} + +static void +Opcode_ae_mulaf16ss_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d200040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f00160; +} + +static void +Opcode_ae_mulaf16ss_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b300040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_21_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b00160; +} + +static void +Opcode_ae_mulaf16ss_21_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b200040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_31_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e00160; +} + +static void +Opcode_ae_mulaf16ss_31_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89300040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_30_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d00160; +} + +static void +Opcode_ae_mulaf16ss_30_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f200040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800160; +} + +static void +Opcode_ae_mulaf16ss_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d100040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_20_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a00160; +} + +static void +Opcode_ae_mulaf16ss_20_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89200040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_11_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900160; +} + +static void +Opcode_ae_mulaf16ss_11_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f100040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000a0; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700160; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b100040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul16s_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul16s_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00080; +} + +static void +Opcode_ae_mul16s_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00040; +} + +static void +Opcode_ae_mul16s_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula16s_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula16s_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002c0; +} + +static void +Opcode_ae_mula16s_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00280; +} + +static void +Opcode_ae_mula16s_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ad00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls16s_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc004400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls16s_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200220; +} + +static void +Opcode_ae_muls16s_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c001c0; +} + +static void +Opcode_ae_muls16s_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6006c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002a0; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00260; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6006800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00280; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00240; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6006400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00260; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00220; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14003c0; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64003a0; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14003a0; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400380; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400380; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400360; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500280; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600260; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500260; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600240; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500240; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600220; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600380; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68003a0; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600360; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800380; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600340; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800360; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8002800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100260; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74001c0; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca002800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100280; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74001e0; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8004400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12001e0; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c00180; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca004400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200200; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c001a0; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00280; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60001c0; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002a0; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60001e0; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10001c0; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67001a0; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8be00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10001e0; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67001c0; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8de00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce007000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300360; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200340; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8007400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300380; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200360; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14001e0; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63003c0; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400200; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63003e0; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce003000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11003c0; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77001e0; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc003000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11003a0; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77001c0; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf003a0; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300180; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8da00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00380; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62001e0; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ba00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc007400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13003c0; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62003a0; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca007400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13003a0; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200380; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500320; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600300; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15002e0; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66002c0; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500200; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65003e0; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500340; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600320; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500300; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66002e0; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500220; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600200; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000e0; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67002c0; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000a0; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700280; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600060; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700240; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600100; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67002e0; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000c0; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67002a0; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600080; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700260; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16001e0; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800200; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16001c0; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67003e0; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16001a0; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67003c0; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700020; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900240; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003e0; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900200; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600300; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800320; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700040; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900260; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700000; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900220; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600320; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800340; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00340; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00300; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6007800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00300; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f002c0; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6005c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00220; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f001e0; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00360; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00320; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6007c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00320; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f002e0; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00240; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00200; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000360; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a001c0; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000320; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12600020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a00180; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10002e0; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69001c0; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000380; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a001e0; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000340; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12700020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a001a0; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000300; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69001e0; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc005c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300120; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000380; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca005c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300100; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12600040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000360; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8005c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000e0; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000340; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500060; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500240; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500020; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x169000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12700040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500200; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400340; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400320; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500080; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500260; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500040; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x169000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12600060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500220; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400360; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400340; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8002400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11001e0; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73001c0; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd001e0; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e001a0; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8cb00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca002400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100200; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73001e0; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00200; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e001c0; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8eb00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc002400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100220; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400180; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00220; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e001e0; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88c00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce002400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100240; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74001a0; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00240; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00200; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ac00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100160; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72001c0; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00160; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00120; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100180; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72001e0; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00180; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00140; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11001a0; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7300180; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd001a0; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00160; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ca00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11001c0; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73001a0; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd001c0; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00180; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ea00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00200; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e00160; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89700040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6001c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00020; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e003e0; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ef00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00220; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f00160; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b700040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00040; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00000; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00240; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000180; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d700040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6002400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00060; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00020; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00260; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60001a0; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f700040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6002800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00080; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00040; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00180; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a00160; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89600040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd003a0; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00360; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ee00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf001a0; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b00160; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b600040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6001000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd003c0; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00380; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88f00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf001c0; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c00160; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d600040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6001400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd003e0; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e003a0; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8af00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf001e0; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d00160; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f600040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6001800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e003c0; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8cf00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce006c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13002e0; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62002c0; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce005000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12003c0; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f001e0; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8007000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300300; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62002e0; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8005400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12003e0; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000200; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca007000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300320; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200300; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca005400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000220; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc007000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300340; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200320; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc005400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300020; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000240; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce006800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300260; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200240; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce004c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200340; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e001e0; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8006c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300280; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200260; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8005000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200360; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f00180; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca006c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13002a0; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200280; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca005000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200380; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f001a0; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc006c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13002c0; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62002a0; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc005000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12003a0; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f001c0; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe003e0; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f003a0; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6005800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00200; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f001c0; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe003a0; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00360; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6005000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe001c0; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00180; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10003c0; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b001a0; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10002c0; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69001a0; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10003a0; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b00180; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10002a0; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900180; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300160; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60003c0; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000320; +} + +static void +Opcode_ae_mulsad32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce005c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300140; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60003a0; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000300; +} + +static void +Opcode_ae_mulsad32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000c0; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65002a0; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400320; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400300; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000a0; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500280; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400300; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64002e0; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15003c0; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66003a0; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15001e0; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65003c0; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500380; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600360; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15001a0; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500380; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600140; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700320; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600040; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700220; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600120; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700300; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600020; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700200; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600220; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800240; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67003a0; +} + +static void +Opcode_ae_mulzsad32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600200; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800220; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700380; +} + +static void +Opcode_ae_mulzsad32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700080; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69002a0; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002e0; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800300; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700060; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900280; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002c0; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68002e0; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15003a0; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600380; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500360; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600340; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe003c0; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00380; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00380; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00340; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15001c0; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65003a0; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500180; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500360; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6005400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe001e0; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f001a0; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6004c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe001a0; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00160; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200160; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b00180; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc003400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200020; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78001c0; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8003400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11003e0; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7800180; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8003800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200060; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7900180; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200180; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b001a0; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce003400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200040; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78001e0; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca003400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78001a0; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca003800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200080; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x79001a0; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000140; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66001a0; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8dd00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63001e0; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8bb00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf003c0; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63001a0; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8fa00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000040; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64001a0; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8fb00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000160; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66001c0; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8fd00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000020; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400180; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8db00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf003e0; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63001c0; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89b00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000060; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64001c0; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89c00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400160; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300340; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca007800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400020; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300200; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce007400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13003e0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62003c0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce007800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400060; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300240; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400180; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300360; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc007800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400040; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300220; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8007800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62003e0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8007c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400080; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300260; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulp32x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp32x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12001a0; +} + +static void +Opcode_ae_mulp32x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b001c0; +} + +static void +Opcode_ae_mulp32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce003800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000c0; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x79001e0; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc003800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000a0; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x79001c0; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x2ts_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8003c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x2ts_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000e0; +} + +static void +Opcode_ae_mulfp32x2ts_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a00180; +} + +static void +Opcode_ae_mulp32x2t_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp32x2t_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12001c0; +} + +static void +Opcode_ae_mulp32x2t_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b001e0; +} + +static void +Opcode_ae_mulap32x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap32x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000180; +} + +static void +Opcode_ae_mulap32x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66001e0; +} + +static void +Opcode_ae_mulap32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89e00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000a0; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500180; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8dc00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000080; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64001e0; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8bc00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x2ts_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x2ts_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000c0; +} + +static void +Opcode_ae_mulafp32x2ts_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65001a0; +} + +static void +Opcode_ae_mulap32x2t_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap32x2t_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10001a0; +} + +static void +Opcode_ae_mulap32x2t_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700180; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14001a0; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300380; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc007c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000c0; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63002a0; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca007c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000a0; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300280; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x2ts_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce007c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x2ts_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000e0; +} + +static void +Opcode_ae_mulsfp32x2ts_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63002c0; +} + +static void +Opcode_ae_mulsp32x2t_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp32x2t_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14001c0; +} + +static void +Opcode_ae_mulsp32x2t_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63003a0; +} + +static void +Opcode_ae_mulfp16x4s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100380; +} + +static void +Opcode_ae_mulfp16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77001a0; +} + +static void +Opcode_ae_mulfp16x4ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76001e0; +} + +static void +Opcode_ae_mulc32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc001000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_mulc32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c001e0; +} + +static void +Opcode_ae_mulc32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce002800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11002a0; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75001a0; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8002c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x550000; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11002c0; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75001c0; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc32x16_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8001400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc32x16_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100040; +} + +static void +Opcode_ae_mulc32x16_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d001a0; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc002c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100300; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7600180; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc32x16_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce001000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc32x16_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100020; +} + +static void +Opcode_ae_mulc32x16_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d00180; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca002c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11002e0; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108000; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75001e0; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00020; +} + +static void +Opcode_ae_mulac32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300160; +} + +static void +Opcode_ae_mulac32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002c0; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61001a0; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002e0; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61001c0; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32x16_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac32x16_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00060; +} + +static void +Opcode_ae_mulac32x16_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500160; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00320; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200180; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32x16_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac32x16_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00040; +} + +static void +Opcode_ae_mulac32x16_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400160; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00300; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61001e0; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16x4ss_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16x4ss_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16x4ss_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul16x4s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_mul16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4100000; +} + +static void +Opcode_ae_mul16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4300000; +} + +static void +Opcode_ae_mula16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f00000; +} + +static void +Opcode_ae_muls16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul16x4_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mul16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; +} + +static void +Opcode_ae_mul16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4200000; +} + +static void +Opcode_ae_mula16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e00000; +} + +static void +Opcode_ae_muls16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfd32x2s_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2s_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2s_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2s_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2s_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2s_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulc16s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8001000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc16s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c001a0; +} + +static void +Opcode_ae_mulc16s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca001000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c001c0; +} + +static void +Opcode_ae_mulc16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac16s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100160; +} + +static void +Opcode_ae_mulac16s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200160; +} + +static void +Opcode_ae_mulac16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc16ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc002800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc16ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7500180; +} + +static void +Opcode_ae_mulfc16ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc16ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc16ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100180; +} + +static void +Opcode_ae_mulafc16ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul16js_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80ff0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul16js_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80096462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1910002e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133b000; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98360e1; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa00026; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40069462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19140022; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133b400; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18008000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x746a001; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa00027; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40069862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_conj16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_3_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_3_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_2_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_1_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_1_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_0_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_0_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafq16x2_fir_3_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_3_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_2_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_1_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_1_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_0_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_0_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzaaaafq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaafq32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaafq32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaafq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaafq32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaafq32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaaq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaaq32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaaq32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaaq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaaq32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaaq32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul16_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul16_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd000a0; +} + +static void +Opcode_ae_mul16_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00060; +} + +static void +Opcode_ae_mul16_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula16_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula16_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002e0; +} + +static void +Opcode_ae_mula16_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e002a0; +} + +static void +Opcode_ae_mula16_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8cd00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500120; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500300; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00140; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00100; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_div64d32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0090; +} + +static void +Opcode_ae_div64d32_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3f0000; +} + +static void +Opcode_ae_div64d32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80086462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_div64d32_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738070; + slotbuf[1] = 0; +} + +static void +Opcode_ae_div64d32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00b0; +} + +static void +Opcode_ae_div64d32_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3f8000; +} + +static void +Opcode_ae_div64d32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8008e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sha32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074cb00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl32t_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl16t_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10557000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl16c_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105872c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl16c_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10587ac0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl16c_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105876c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl16c_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d030; +} + +static void +Opcode_ae_vldsht_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afa0b; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a00f; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lb_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8010; +} + +static void +Opcode_ae_lb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a3001; +} + +static void +Opcode_ae_lb_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1521010; +} + +static void +Opcode_ae_lbi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lbi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9001; +} + +static void +Opcode_ae_lbi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a3003; +} + +static void +Opcode_ae_lbi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d6004; +} + +static void +Opcode_ae_lbk_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lbk_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8000; +} + +static void +Opcode_ae_lbki_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10563000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lbs_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071b00e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lbsi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af005; + slotbuf[1] = 0; +} + +static void +Opcode_ae_db_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_db_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929e04; +} + +static void +Opcode_ae_dbi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10748b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dbi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09b0c; +} + +static void +Opcode_ae_db_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dbi_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10748f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_db_ic1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dbi_ic1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ab00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_db_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aed00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dbi_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074af00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_ardecnorm16_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065f000; +} + +static void +Opcode_ae_lbki_dbi_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10430000; +} + +static void +Opcode_ae_lbki_dbi_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10440000; +} + +static void +Opcode_ae_lbki_dbi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10420000; +} + +static void +Opcode_ae_lbi_dbi_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680400; +} + +static void +Opcode_ae_lbi_dbi_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680500; +} + +static void +Opcode_ae_lbi_dbi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680300; +} + +static void +Opcode_ae_lbk_db_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10390000; +} + +static void +Opcode_ae_lbk_db_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103a0000; +} + +static void +Opcode_ae_lbk_db_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10380000; +} + +static void +Opcode_ae_lb_db_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680100; +} + +static void +Opcode_ae_lb_db_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680200; +} + +static void +Opcode_ae_lb_db_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680000; +} + +static void +Opcode_ae_vlel32t_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vlel16t_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055b000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072f000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vles16c_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10587ec0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbf_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105871c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sb_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbi_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10552000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vles16c_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105873c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbf_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105875c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sb_ic1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aeb00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbi_ic1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10553000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vles16c_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d130; +} + +static void +Opcode_ae_sbf_ic1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105879c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sb_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aef00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbi_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10556000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vles16c_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105877c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbf_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10587dc0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40081002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movae_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af209; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movae_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf400; +} + +static void +Opcode_ae_movea_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105870c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movea_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf440; +} + +static void +Opcode_ae_moveep_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00426; +} + +static void +Opcode_ae_moveep_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80406862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sext72_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa480000; +} + +static void +Opcode_ae_add72_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa080000; +} + +static void +Opcode_ae_sub72_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa180000; +} + +static void +Opcode_ae_add72x64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa280000; +} + +static void +Opcode_ae_sub72x64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2a0000; +} + +static void +Opcode_ae_mul32ep_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00100; +} + +static void +Opcode_ae_mul32ep_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32ep_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00280; +} + +static void +Opcode_ae_mula32ep_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32ep_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00100; +} + +static void +Opcode_ae_muls32ep_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00200; +} + +static void +Opcode_ae_mulzaad32ep_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00300; +} + +static void +Opcode_ae_mulzssd32ep_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00000; +} + +static void +Opcode_ae_mulaad32ep_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00180; +} + +static void +Opcode_ae_mulssd32ep_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32usep_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00080; +} + +static void +Opcode_ae_mulaad32usep_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32usep_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00280; +} + +static void +Opcode_ae_mulzaad32usep_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32usep_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00180; +} + +static void +Opcode_ae_mula32usep_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00300; +} + +static void +Opcode_ae_mul32usep_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00200; +} + +static void +Opcode_ae_mula32usep_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00380; +} + +static void +Opcode_ae_srai72_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slai72_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40007003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa380000; +} + +static void +Opcode_ae_sat64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_l16si_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200d; +} + +static void +Opcode_ae_l16ui_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400d; +} + +static void +Opcode_ae_s16i_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600d; +} + +static void +Opcode_ae_lalign128_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14000; +} + +static void +Opcode_ae_lalign128_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416000; +} + +static void +Opcode_ae_lalign128_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lalign128_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lalign128_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680080; +} + +static void +Opcode_ae_lalign128_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680080; +} + +static void +Opcode_ae_lalign128_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00e00; +} + +static void +Opcode_ae_lalign128_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514000; +} + +static void +Opcode_ae_lalign128_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000400; +} + +static void +Opcode_ae_lalign128_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1518000; +} + +static void +Opcode_ae_lalign128_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9839c00; +} + +static void +Opcode_ae_lalign128_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142000c; +} + +static void +Opcode_ae_salign128_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000600; +} + +static void +Opcode_ae_salign128_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a9000; +} + +static void +Opcode_ae_la128_pp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08140; +} + +static void +Opcode_ae_la128_pp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142010c; +} + +static void +Opcode_ae_sa128pos_fp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002490; +} + +static void +Opcode_ae_sa128pos_fp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa826004; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc12000; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1414008; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193a0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00860; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512006; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2804010; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516008; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c10201; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400e; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc12010; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1414009; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193e0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03802; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00870; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512007; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2806010; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516009; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c50201; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400f; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00080; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300008; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19068010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000d; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000b0; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000b; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000b0; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000b; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8818101; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000b; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00020; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300002; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19048010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00007; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600080; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600080; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700030; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400003; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400030; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400003; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810101; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400003; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00050; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300005; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19058010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000f; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640040; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640040; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700070; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400007; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400070; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400007; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810103; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400007; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00060; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300006; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19020010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640080; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640080; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700080; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400008; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400080; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400008; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8818000; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400008; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00030; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300003; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19010010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000c0; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000c0; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700040; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400004; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400040; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400004; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810002; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400004; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00070; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300007; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19028010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00009; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400c0; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400c0; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700090; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400009; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400090; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400009; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8818001; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400009; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00010; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300001; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19008010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00006; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600040; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600040; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700010; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400001; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400010; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400001; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810001; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400001; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00040; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300004; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19018010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700050; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400005; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400050; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400005; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810003; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400005; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19060010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00005; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000a0; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000a; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000a0; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000a; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8818100; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000a; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19040010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700020; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400002; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400020; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400002; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810100; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400002; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19050010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700060; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400006; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400060; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400006; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810102; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400006; +} + +static void +Opcode_ae_sa8x8x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800070; +} + +static void +Opcode_ae_sa8x8x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500070; +} + +static void +Opcode_ae_sa8x8x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830301; +} + +static void +Opcode_ae_sa16x4x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000f0; +} + +static void +Opcode_ae_sa16x4x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000f0; +} + +static void +Opcode_ae_sa16x4x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820301; +} + +static void +Opcode_ae_sa32x2x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800030; +} + +static void +Opcode_ae_sa32x2x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500030; +} + +static void +Opcode_ae_sa32x2x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820303; +} + +static void +Opcode_ae_sa8x8x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800040; +} + +static void +Opcode_ae_sa8x8x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500040; +} + +static void +Opcode_ae_sa8x8x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830200; +} + +static void +Opcode_ae_sa16x4x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000c0; +} + +static void +Opcode_ae_sa16x4x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000c0; +} + +static void +Opcode_ae_sa16x4x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820200; +} + +static void +Opcode_ae_sa32x2x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800000; +} + +static void +Opcode_ae_sa32x2x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500000; +} + +static void +Opcode_ae_sa32x2x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820202; +} + +static void +Opcode_ae_sa8x8x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800050; +} + +static void +Opcode_ae_sa8x8x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500050; +} + +static void +Opcode_ae_sa8x8x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830201; +} + +static void +Opcode_ae_sa16x4x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000d0; +} + +static void +Opcode_ae_sa16x4x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000d0; +} + +static void +Opcode_ae_sa16x4x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820201; +} + +static void +Opcode_ae_sa32x2x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800010; +} + +static void +Opcode_ae_sa32x2x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500010; +} + +static void +Opcode_ae_sa32x2x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820203; +} + +static void +Opcode_ae_sa8x8x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800060; +} + +static void +Opcode_ae_sa8x8x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500060; +} + +static void +Opcode_ae_sa8x8x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830300; +} + +static void +Opcode_ae_sa16x4x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000e0; +} + +static void +Opcode_ae_sa16x4x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000e0; +} + +static void +Opcode_ae_sa16x4x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820300; +} + +static void +Opcode_ae_sa32x2x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800020; +} + +static void +Opcode_ae_sa32x2x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500020; +} + +static void +Opcode_ae_sa32x2x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820302; +} + +static void +Opcode_ae_abs8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00e0; +} + +static void +Opcode_ae_abs8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs8s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003820; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_abs8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0010; +} + +static void +Opcode_ae_abs8s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8005e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f70; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg8s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003c60; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_neg8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a02a0; +} + +static void +Opcode_ae_neg8s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800de462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080400; +} + +static void +Opcode_ae_sub8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18600b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380400; +} + +static void +Opcode_ae_max8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18280f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0110040; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max8_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_ae_max8_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40900a0; +} + +static void +Opcode_ae_max8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180400; +} + +static void +Opcode_ae_max8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a0000; +} + +static void +Opcode_ae_min8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18380f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc01100a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min8_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x548000; +} + +static void +Opcode_ae_min8_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40a80a0; +} + +static void +Opcode_ae_min8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180600; +} + +static void +Opcode_ae_min8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80b8000; +} + +static void +Opcode_ae_add8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18080b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add8s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002800; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_add8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080800; +} + +static void +Opcode_ae_add8s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007460; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18600f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub8s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003400; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_sub8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380800; +} + +static void +Opcode_ae_sub8s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_le8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18740f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380e00; +} + +static void +Opcode_ae_lt8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18780b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380b00; +} + +static void +Opcode_ae_eq8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18700f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380a00; +} + +static void +Opcode_ae_satu16x4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000c0; +} + +static void +Opcode_ae_satu16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000062; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_satu32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001062; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat8x8x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_satu8x8x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat8x4x32_l_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000b0; +} + +static void +Opcode_ae_sat8x4x32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_satu8x4x32_l_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000d0; +} + +static void +Opcode_ae_satu8x4x32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round8x8f16ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round8x8f16sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round8x4f32ssym_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round8x4f32sasym_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movda8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x752a003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda8_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00803; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105820c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda8_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0301; +} + +static void +Opcode_ae_movda8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640660; +} + +static void +Opcode_ae_movda8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e10a0; +} + +static void +Opcode_ae_movda8_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556004; +} + +static void +Opcode_ae_movad8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d832080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad8_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10734008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690080; +} + +static void +Opcode_ae_movad8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01208; +} + +static void +Opcode_ae_movdx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movdx2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movdx2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10100000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movdx2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10100000; +} + +static void +Opcode_ae_movdx2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_movdx2_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_movdx2_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_movdx2_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_movdx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_movdx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; +} + +static void +Opcode_ae_movdx2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000100; +} + +static void +Opcode_ae_movdx2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsub32j_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsub32j_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_addandsub32j_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsub32j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8400000; +} + +static void +Opcode_ae_addandsub32j_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5200000; +} + +static void +Opcode_ae_addandsub32j_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000024; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addw8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addw8_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_addw8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc400000; +} + +static void +Opcode_ae_addw8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002e; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addw16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addw16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_addw16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb400000; +} + +static void +Opcode_ae_addw16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002c; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addw32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addw32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ae_addw32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb400800; +} + +static void +Opcode_ae_addw32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002d; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subw8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subw8_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_subw8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe400000; +} + +static void +Opcode_ae_subw8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000032; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subw16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subw16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_ae_subw16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd400000; +} + +static void +Opcode_ae_subw16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000030; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subw32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subw32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_ae_subw32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd400800; +} + +static void +Opcode_ae_subw32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000031; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_accw8_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_accw8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000022; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_accw16_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_accw16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_accw32_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_accw32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000021; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addw8u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addw8u_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_ae_addw8u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc400800; +} + +static void +Opcode_ae_addw8u_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002f; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subw8u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subw8u_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_subw8u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe400800; +} + +static void +Opcode_ae_subw8u_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000033; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_accw8u_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_accw8u_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000023; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x2s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c00000; +} + +static void +Opcode_ae_mulfp32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x2s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4700000; +} + +static void +Opcode_ae_mulafp32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x2s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000000; +} + +static void +Opcode_ae_mulsfp32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x2s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d00000; +} + +static void +Opcode_ae_mulfp32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x2s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4800000; +} + +static void +Opcode_ae_mulafp32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x2s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100000; +} + +static void +Opcode_ae_mulsfp32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulasf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulssf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulasf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulasf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulasf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulssf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulssf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulssf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mul32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd000c0; +} + +static void +Opcode_ae_mul32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00080; +} + +static void +Opcode_ae_mul32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8aa00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00300; +} + +static void +Opcode_ae_mula32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e002c0; +} + +static void +Opcode_ae_mula32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ed00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc004800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12002a0; +} + +static void +Opcode_ae_muls32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d001c0; +} + +static void +Opcode_ae_muls32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00120; +} + +static void +Opcode_ae_mul32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e000e0; +} + +static void +Opcode_ae_mul32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00360; +} + +static void +Opcode_ae_mula32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00320; +} + +static void +Opcode_ae_mula32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ce00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca004c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200300; +} + +static void +Opcode_ae_muls32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e001a0; +} + +static void +Opcode_ae_muls32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32s_hl_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32s_hl_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd000e0; +} + +static void +Opcode_ae_mul32s_hl_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e000a0; +} + +static void +Opcode_ae_mul32s_hl_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ab00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32s_hl_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32s_hl_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00320; +} + +static void +Opcode_ae_mula32s_hl_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e002e0; +} + +static void +Opcode_ae_mula32s_hl_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88e00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32s_hl_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce004800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32s_hl_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12002c0; +} + +static void +Opcode_ae_muls32s_hl_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d001e0; +} + +static void +Opcode_ae_muls32s_hl_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00100; +} + +static void +Opcode_ae_mul32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e000c0; +} + +static void +Opcode_ae_mul32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00340; +} + +static void +Opcode_ae_mula32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00300; +} + +static void +Opcode_ae_mula32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ae00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8004c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12002e0; +} + +static void +Opcode_ae_muls32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e00180; +} + +static void +Opcode_ae_muls32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500140; +} + +static void +Opcode_ae_mulzaad32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500320; +} + +static void +Opcode_ae_mulzaad32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15003e0; +} + +static void +Opcode_ae_mulzasd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66003c0; +} + +static void +Opcode_ae_mulzasd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsad32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsad32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600160; +} + +static void +Opcode_ae_mulzsad32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700340; +} + +static void +Opcode_ae_mulzsad32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600280; +} + +static void +Opcode_ae_mulzssd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68002a0; +} + +static void +Opcode_ae_mulzssd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6004400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00160; +} + +static void +Opcode_ae_mulaad32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00120; +} + +static void +Opcode_ae_mulaad32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000260; +} + +static void +Opcode_ae_mulasd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68001c0; +} + +static void +Opcode_ae_mulasd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8df00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsad32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc005800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsad32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000a0; +} + +static void +Opcode_ae_mulsad32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60002c0; +} + +static void +Opcode_ae_mulsad32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14002c0; +} + +static void +Opcode_ae_mulssd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64002a0; +} + +static void +Opcode_ae_mulssd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500160; +} + +static void +Opcode_ae_mulzaad32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500340; +} + +static void +Opcode_ae_mulzaad32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600000; +} + +static void +Opcode_ae_mulzasd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66003e0; +} + +static void +Opcode_ae_mulzasd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsad32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsad32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600180; +} + +static void +Opcode_ae_mulzsad32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700360; +} + +static void +Opcode_ae_mulzsad32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002a0; +} + +static void +Opcode_ae_mulzssd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68002c0; +} + +static void +Opcode_ae_mulzssd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6004800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00180; +} + +static void +Opcode_ae_mulaad32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00140; +} + +static void +Opcode_ae_mulaad32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000280; +} + +static void +Opcode_ae_mulasd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68001e0; +} + +static void +Opcode_ae_mulasd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ff00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsad32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce005800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsad32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000c0; +} + +static void +Opcode_ae_mulsad32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60002e0; +} + +static void +Opcode_ae_mulsad32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14002e0; +} + +static void +Opcode_ae_mulssd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64002c0; +} + +static void +Opcode_ae_mulssd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x2ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x2ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x2ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x2ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x2ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x2ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulf32x2r_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x2r_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x2r_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x2r_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x2r_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x2r_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj32ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8003000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfcj32ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100340; +} + +static void +Opcode_ae_mulfcj32ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76001c0; +} + +static void +Opcode_ae_mulfcj32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj32ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafcj32ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00360; +} + +static void +Opcode_ae_mulafcj32ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62001c0; +} + +static void +Opcode_ae_mulafcj32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89a00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf2p32x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2p32x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2p32x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulaf2p32x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulaf2p32x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulaf2p32x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulsf2p32x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulsf2p32x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulsf2p32x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulf2p32x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2p32x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2p32x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulaf2p32x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaf2p32x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaf2p32x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulsf2p32x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsf2p32x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsf2p32x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulp32x2s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul2p32x4s_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4s_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula2p32x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2p32x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2p32x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_muls2p32x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_muls2p32x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_muls2p32x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mul2p32x4t_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4t_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4t_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula2p32x4t_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2p32x4t_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2p32x4t_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_muls2p32x4t_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_muls2p32x4t_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_muls2p32x4t_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulzaa32x2_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzss32x2_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaa32x2_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss32x2_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulcj32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca001400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulcj32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100060; +} + +static void +Opcode_ae_mulcj32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d001c0; +} + +static void +Opcode_ae_mulcj32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulacj32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulacj32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00080; +} + +static void +Opcode_ae_mulacj32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600160; +} + +static void +Opcode_ae_mulacj32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89100040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc32ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc32ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_mulfc32ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4900000; +} + +static void +Opcode_ae_mulfc32ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc32ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc32ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_mulafc32ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4400000; +} + +static void +Opcode_ae_mulafc32ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulcj32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulacj32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf2d32x2ws_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2d32x2ws_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2d32x2ws_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulzaaaa2q16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaaa2q16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaaa2q16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulaaaa2q16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaaa2q16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaaa2q16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulp16s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca003c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp16s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200100; +} + +static void +Opcode_ae_mulp16s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a001a0; +} + +static void +Opcode_ae_mulp16s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulap16s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap16s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000e0; +} + +static void +Opcode_ae_mulap16s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65001c0; +} + +static void +Opcode_ae_mulap16s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8fc00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsp16s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp16s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400100; +} + +static void +Opcode_ae_mulsp16s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63002e0; +} + +static void +Opcode_ae_mulsp16s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc003c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200120; +} + +static void +Opcode_ae_mulp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a001c0; +} + +static void +Opcode_ae_mulp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulap16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000100; +} + +static void +Opcode_ae_mulap16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65001e0; +} + +static void +Opcode_ae_mulap16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89d00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400120; +} + +static void +Opcode_ae_mulsp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300300; +} + +static void +Opcode_ae_mulsp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul2c16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula2c16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj16ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce002c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfcj16ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100320; +} + +static void +Opcode_ae_mulfcj16ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76001a0; +} + +static void +Opcode_ae_mulfcj16ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj16ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafcj16ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00340; +} + +static void +Opcode_ae_mulafcj16ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62001a0; +} + +static void +Opcode_ae_mulafcj16ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc16s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10003e0; +} + +static void +Opcode_ae_mulc16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c00180; +} + +static void +Opcode_ae_mulc16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac16s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_mulac16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000160; +} + +static void +Opcode_ae_mulac16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp16x4rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca003000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp16x4rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100360; +} + +static void +Opcode_ae_mulfp16x4rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7700180; +} + +static void +Opcode_ae_mulfp16x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfd16x16x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfd16x16x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfd16x16x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulp16x16x4s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce003c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp16x16x4s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200140; +} + +static void +Opcode_ae_mulp16x16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a001e0; +} + +static void +Opcode_ae_mulp16x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulap16x16x4s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap16x16x4s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000120; +} + +static void +Opcode_ae_mulap16x16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600180; +} + +static void +Opcode_ae_mulap16x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8bd00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsp16x16x4s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp16x16x4s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400140; +} + +static void +Opcode_ae_mulsp16x16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300320; +} + +static void +Opcode_ae_mulsp16x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000e0; +} + +static void +Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65002c0; +} + +static void +Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500100; +} + +static void +Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65002e0; +} + +static void +Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600240; +} + +static void +Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800260; +} + +static void +Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600260; +} + +static void +Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800280; +} + +static void +Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6003800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00100; +} + +static void +Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f000c0; +} + +static void +Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6003c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00120; +} + +static void +Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f000e0; +} + +static void +Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss2d16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulss2d16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400220; +} + +static void +Opcode_ae_mulss2d16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400200; +} + +static void +Opcode_ae_mulss2d16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss2d16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulss2d16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400240; +} + +static void +Opcode_ae_mulss2d16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400220; +} + +static void +Opcode_ae_mulss2d16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15002a0; +} + +static void +Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600280; +} + +static void +Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15002c0; +} + +static void +Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66002a0; +} + +static void +Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003a0; +} + +static void +Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68003c0; +} + +static void +Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003c0; +} + +static void +Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68003e0; +} + +static void +Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6007000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002c0; +} + +static void +Opcode_ae_mulaafd16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00280; +} + +static void +Opcode_ae_mulaafd16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6007400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002e0; +} + +static void +Opcode_ae_mulaafd16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f002a0; +} + +static void +Opcode_ae_mulaafd16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14003e0; +} + +static void +Opcode_ae_mulssfd16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64003c0; +} + +static void +Opcode_ae_mulssfd16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_mulssfd16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64003e0; +} + +static void +Opcode_ae_mulssfd16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfd16x16x4ws_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulfd16x16x4ws_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulfd16x16x4ws_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulzaaaa2q16x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaa2q16x8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaa2q16x8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaa2q16x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaaaa2q16x8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaaaa2q16x8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzaaaa2q8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaa2q8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaa2q8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaa2q8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaa2q8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaa2q8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulpc32x16x2_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulpc32x16x2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulpc32x16x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulapc32x16x2_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulapc32x16x2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulapc32x16x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfp32x16_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc32x16w_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a00000; +} + +static void +Opcode_ae_mulfc32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc32x16w_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4500000; +} + +static void +Opcode_ae_mulafc32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc32x16w_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b00000; +} + +static void +Opcode_ae_mulfc32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc32x16w_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4600000; +} + +static void +Opcode_ae_mulafc32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf2p32x16x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulsf2p32x16x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf2p32x16x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulsf2p32x16x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf2p32x16x4s_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4s_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4s_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4s_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulsf2p32x16x4s_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4s_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfpc32x16x2ras_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mulfpc32x16x2ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfpc32x16x2ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfpc32x16x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpc32x16x2ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpc32x16x2ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpc32x16x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfpcj32x16x2ras_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ae_mulfpcj32x16x2ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfpcj32x16x2ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfpcj32x16x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpcj32x16x2ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpcj32x16x2ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpcj32x16x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzaaaa2q32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaaa2q32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaaa2q32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulaaaa2q32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaaa2q32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaaa2q32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mul2q32x16_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2q32x16_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2q32x16_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula2q32x16_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2q32x16_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2q32x16_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mul2q32x16_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mul2q32x16_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mul2q32x16_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2q32x16_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mula2q32x16_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mula2q32x16_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_srai8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d824080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00208; +} + +static void +Opcode_ae_srai8r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d826080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai8r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04208; +} + +static void +Opcode_ae_srli8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d828080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srli8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00308; +} + +static void +Opcode_ae_slai8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d820080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9308; +} + +static void +Opcode_ae_slai8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d822080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83ad308; +} + +static void +Opcode_ae_slaa8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a800c; +} + +static void +Opcode_ae_srla8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c82c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9008; +} + +static void +Opcode_ae_slaa8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x758a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a810c; +} + +static void +Opcode_ae_sraa8rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa8rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1104; +} + +static void +Opcode_ae_sraa8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x758c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9004; +} + +static void +Opcode_ae_srli16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c830000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srli16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1208; +} + +static void +Opcode_ae_slai16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c81c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a820c; +} + +static void +Opcode_ae_slaa16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c814000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8008; +} + +static void +Opcode_ae_srla16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c826000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9304; +} + +static void +Opcode_ae_srai16sym_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c824000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai16sym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9204; +} + +static void +Opcode_ae_sraa16syms_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d81e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa16syms_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9100; +} + +static void +Opcode_ae_srai32sym_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai32sym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842e007; +} + +static void +Opcode_ae_sraa32syms_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x748e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa32syms_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9300; +} + +static void +Opcode_ae_srav16rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srav16rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00000; +} + +static void +Opcode_ae_srav32rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srav32rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c02000; +} + +static void +Opcode_ae_cvti32x4f8_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a014000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8424002; +} + +static void +Opcode_ae_cvti32x4f8_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a016000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8426002; +} + +static void +Opcode_ae_cvti32x4f8s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a008000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8420001; +} + +static void +Opcode_ae_cvti32x4f8s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8422001; +} + +static void +Opcode_ae_cvta32x4f8_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a034000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8120200; +} + +static void +Opcode_ae_cvta32x4f8_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a036000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8120300; +} + +static void +Opcode_ae_cvta32x4f8s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a028000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82a0000; +} + +static void +Opcode_ae_cvta32x4f8s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a02a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82a0100; +} + +static void +Opcode_ae_cvti32x4f8u_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a010000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8u_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8420002; +} + +static void +Opcode_ae_cvti32x4f8u_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a012000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8u_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8422002; +} + +static void +Opcode_ae_cvti32x4f8us_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8us_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8424001; +} + +static void +Opcode_ae_cvti32x4f8us_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8us_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8426001; +} + +static void +Opcode_ae_cvta32x4f8u_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a030000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8u_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8120000; +} + +static void +Opcode_ae_cvta32x4f8u_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a032000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8u_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8120100; +} + +static void +Opcode_ae_cvta32x4f8us_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a02c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8us_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82a0200; +} + +static void +Opcode_ae_cvta32x4f8us_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a02e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8us_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82a0300; +} + +static void +Opcode_ae_cvti32x4f16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8420000; +} + +static void +Opcode_ae_cvti32x4f16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8422000; +} + +static void +Opcode_ae_cvta32x4f16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a020000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a0000; +} + +static void +Opcode_ae_cvta32x4f16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a022000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a0100; +} + +static void +Opcode_ae_cvti32x4f16u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f16u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8424000; +} + +static void +Opcode_ae_cvti32x4f16us_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f16us_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8426000; +} + +static void +Opcode_ae_cvta32x4f16u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a024000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f16u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a0200; +} + +static void +Opcode_ae_cvta32x4f16us_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a026000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f16us_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a0300; +} + +static void +Opcode_ae_cvti16x4x2f8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a038000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti16x4x2f8_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500200; +} + +static void +Opcode_ae_cvti16x4x2f8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8320000; +} + +static void +Opcode_ae_cvti16x4x2f8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a03a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti16x4x2f8s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_cvti16x4x2f8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8320100; +} + +static void +Opcode_ae_cvta16x4x2f8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b018000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta16x4x2f8_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_cvta16x4x2f8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220000; +} + +static void +Opcode_ae_cvta16x4x2f8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b01a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta16x4x2f8s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400200; +} + +static void +Opcode_ae_cvta16x4x2f8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220100; +} + +static void +Opcode_ae_cvti16x4x2f8u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a03c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti16x4x2f8u_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600200; +} + +static void +Opcode_ae_cvti16x4x2f8u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8320200; +} + +static void +Opcode_ae_cvti16x4x2f8us_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a03e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti16x4x2f8us_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8320300; +} + +static void +Opcode_ae_cvta16x4x2f8u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b01c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta16x4x2f8u_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_cvta16x4x2f8u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220200; +} + +static void +Opcode_ae_cvta16x4x2f8us_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b01e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta16x4x2f8us_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220300; +} + +static void +Opcode_ae_sel8x8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0108000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sel8x8_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_ae_sel8x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel8x8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000440; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel8x8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a00000; +} + +static void +Opcode_ae_sel8x8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000036; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl8x8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc01100e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_shfl8x8_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900400; +} + +static void +Opcode_ae_shfl8x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a08000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl8x8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000c40; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl8x8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8200400; +} + +static void +Opcode_ae_shfl8x8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000063; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel16x4_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_sel16x4_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000020; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_sel16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0100000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sel16x4_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_ae_sel16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel16x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel16x4_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sel16x4_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000020; +} + +static void +Opcode_ae_sel16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5900000; +} + +static void +Opcode_ae_sel16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000035; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc01100c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_shfl16x4_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900000; +} + +static void +Opcode_ae_shfl16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl16x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c40; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8200000; +} + +static void +Opcode_ae_shfl16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000063; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel8x8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80008000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dsel8x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel8x8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000400; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel8x8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ae_dsel8x8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000001; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel16x4_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_dsel16x4_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_dsel16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dsel16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel16x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel16x4_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dsel16x4_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000000; +} + +static void +Opcode_ae_dsel16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_dsel16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel8x8i_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sel8x8i_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_sel8x8i_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel8x8i_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000840; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel8x8i_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b00000; +} + +static void +Opcode_ae_sel8x8i_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000037; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rmax8x8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63d0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_rmax8x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b004e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rmax8x8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac58000; +} + +static void +Opcode_ae_rmin8x8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63e0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_rmin8x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00520; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rmin8x8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae58000; +} + +static void +Opcode_ae_rmax16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63c8c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_rmax16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b004c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rmax16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab58000; +} + +static void +Opcode_ae_rmin16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63d8c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_rmin16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00500; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rmin16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad58000; +} + +static void +Opcode_ae_sort16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e048000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sort16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sort16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa038000; +} + +static void +Opcode_ae_radd8x8_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63a0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radd8x8_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00420; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radd8x8_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa658000; +} + +static void +Opcode_ae_radda8x8_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63b8c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radda8x8_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00480; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radda8x8_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa958000; +} + +static void +Opcode_ae_radd8x8_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63a8c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radd8x8_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00440; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radd8x8_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa758000; +} + +static void +Opcode_ae_radda8x8_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63c0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radda8x8_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b004a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radda8x8_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa58000; +} + +static void +Opcode_ae_radd16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6398c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radd16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00400; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radd16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa558000; +} + +static void +Opcode_ae_radda16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63b0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radda16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00460; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radda16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa858000; +} + +static void +Opcode_ae_bmax8x8_h_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14004400; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmax8x8_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_bmax8x8_l_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1288000; +} + +static void +Opcode_ae_bmax8x8_l_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14006000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmax8x8_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_bmin8x8_h_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmin8x8_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_bmin8x8_l_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c8000; +} + +static void +Opcode_ae_bmin8x8_l_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000400; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmin8x8_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_bmax16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bmax16x4_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ae_bmax16x4_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14004000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmax16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820800; +} + +static void +Opcode_ae_bmin16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bmin16x4_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ae_bmin16x4_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14006400; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmin16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820c00; +} + +static void +Opcode_ae_bmax32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c700000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bmax32x2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ae_bmax32x2_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmax32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400a00; +} + +static void +Opcode_ae_bmin32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c700100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bmin32x2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ae_bmin32x2_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14002000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmin32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400e00; +} + +static void +Opcode_ae_addinv16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80fd0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addinv16s_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a000; +} + +static void +Opcode_ae_addinv16s_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ae_addinv16s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003c20; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addinv16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0050; +} + +static void +Opcode_ae_addinv16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3d0000; +} + +static void +Opcode_ae_addinv16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8006e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addinv32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80fe0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addinv32s_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a400; +} + +static void +Opcode_ae_addinv32s_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130020; +} + +static void +Opcode_ae_addinv32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003840; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addinv32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0070; +} + +static void +Opcode_ae_addinv32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3d8000; +} + +static void +Opcode_ae_addinv32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80076462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movt16x8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt16x8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_movt8x16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt8x16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; +} + +static void +Opcode_ae_movt8x16_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt8x16_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000000; +} + +static void +Opcode_ae_movbd1x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520005; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movbd1x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa824004; +} + +static void +Opcode_ae_movbd1x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movbd1x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa820004; +} + +static void +Opcode_ae_movneg32s_t_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18400b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movneg32s_t_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180a00; +} + +static void +Opcode_ae_movneg32s_t_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80d0000; +} + +static void +Opcode_ae_movneg32s_t_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movdext_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movdext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8420003; +} + +static void +Opcode_ae_movadext_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c400000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movadext_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400000; +} + +static void +Opcode_ae_movadext_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c440000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movadext_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400400; +} + +static void +Opcode_ae_nsa16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19196030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsa16x4_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03021; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsa16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0220c; +} + +static void +Opcode_ae_nsaz32x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880070; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz32x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c06001; +} + +static void +Opcode_ae_nsa32x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880060; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsa32x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04001; +} + +static void +Opcode_ae_trunci16x4f32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c080000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunci16x4f32s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_trunci16x4f32s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ae_trunci16x4f32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8422003; +} + +static void +Opcode_ae_trunci16x4f64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunci16x4f64s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_trunci16x4f64s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_trunci16x4f64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8020000; +} + +static void +Opcode_ae_trunca16x4f32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c100000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca16x4f32s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ae_trunca16x4f32s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_trunca16x4f32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81a0000; +} + +static void +Opcode_ae_trunca16x4f64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c180000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca16x4f64s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x704000; +} + +static void +Opcode_ae_trunca16x4f64s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1480000; +} + +static void +Opcode_ae_trunca16x4f64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81a0100; +} + +static void +Opcode_ae_addc32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c680000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addc32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_addc32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400800; +} + +static void +Opcode_ae_subc32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c780000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subc32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_subc32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820000; +} + +static void +Opcode_ae_addc32u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c680100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addc32u_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_ae_addc32u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400c00; +} + +static void +Opcode_ae_subc32u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c780100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subc32u_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_subc32u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820400; +} + +static void +Opcode_ae_expadd16_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; +} + +static void +Opcode_ae_expadd16_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_expsub16_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010000; +} + +static void +Opcode_ae_expsub16_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004860; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_expadd16_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8008000; +} + +static void +Opcode_ae_expadd16_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004460; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_expsub16_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8018000; +} + +static void +Opcode_ae_expsub16_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004c60; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addcexp32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002a; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addcexp32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002b; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_calcrng16_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680800; +} + +static void +Opcode_ae_calcrng32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680c00; +} + +static void +Opcode_ae_rng32x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7382f00; +} + +static void +Opcode_ae_lav8x8x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_lav8x8x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a058000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lav8x8x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_lav8x8x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_lav8x8x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8118000; +} + +static void +Opcode_ae_lav16x4x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lav16x4x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a018000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lav16x4x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_lav16x4x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_lav16x4x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8110000; +} + +static void +Opcode_ae_sav8x8x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_sav8x8x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_sav8x8x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf410000; +} + +static void +Opcode_ae_sav16x4x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_sav16x4x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_sav16x4x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf400000; +} + +static void +Opcode_ae_movzbvcdr_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100001; + slotbuf[1] = 0x229860; +} + +static void +Opcode_ae_movzbvcdr_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00027; +} + +static void +Opcode_ae_movdrzbvc_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; + slotbuf[1] = 0x229860; +} + +static void +Opcode_ae_movdrzbvc_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00026; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6040000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mul8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002000; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mul8q4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula8q4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400; + slotbuf[1] = 0x2c0100; +} + +static void +Opcode_ae_mul8q8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula8q8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mul8qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x40000; +} + +static void +Opcode_ae_mula8qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xc0000; +} + +static void +Opcode_ae_mul4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x240000; +} + +static void +Opcode_ae_mula4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x240000; +} + +static void +Opcode_ae_mul4o4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x280000; +} + +static void +Opcode_ae_mula4o4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x284000; +} + +static void +Opcode_ae_mul4o8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula4o8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x80000; +} + +static void +Opcode_ae_mul4qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x282000; +} + +static void +Opcode_ae_mula4qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x286000; +} + +static void +Opcode_ae_mul8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0728; +} + +static void +Opcode_ae_mul8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0628; +} + +static void +Opcode_ae_mula8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c2628; +} + +static void +Opcode_ae_mula8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c2628; +} + +static void +Opcode_ae_mul8q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0128; +} + +static void +Opcode_ae_mula8q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0228; +} + +static void +Opcode_ae_mul2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0628; +} + +static void +Opcode_ae_mula2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0728; +} + +static void +Opcode_ae_mul2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0008; +} + +static void +Opcode_ae_mul2x4q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula2x4q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0008; +} + +static void +Opcode_ae_mulqq8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200040; +} + +static void +Opcode_ae_mulaqq8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200010; +} + +static void +Opcode_ae_mul4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201860; +} + +static void +Opcode_ae_mula4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x205860; +} + +static void +Opcode_ae_mul4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x203860; +} + +static void +Opcode_ae_mula4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x207860; +} + +static void +Opcode_ae_mul4o8x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200460; +} + +static void +Opcode_ae_mula4o8x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200a60; +} + +static void +Opcode_ae_mul4o8x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200560; +} + +static void +Opcode_ae_mula4o8x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200b60; +} + +static void +Opcode_ae_mul8q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0028; +} + +static void +Opcode_ae_mula8q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0128; +} + +static void +Opcode_ae_mul8q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0028; +} + +static void +Opcode_ae_mula8q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0228; +} + +static void +Opcode_ae_mul2x4q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula2x4q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0008; +} + +static void +Opcode_ae_mul2x4q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula2x4q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0008; +} + +static void +Opcode_ae_mulqq4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200030; +} + +static void +Opcode_ae_mulaqq4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200000; +} + +static void +Opcode_ae_mulqq4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200038; +} + +static void +Opcode_ae_mulaqq4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200008; +} + +static void +Opcode_ae_mul4o4x16cnv_hh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200060; +} + +static void +Opcode_ae_mul4o4x16cnv_hl_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200160; +} + +static void +Opcode_ae_mul4o4x16cnv_lh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200260; +} + +static void +Opcode_ae_mul4o4x16cnv_ll_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200360; +} + +static void +Opcode_ae_mula4o4x16cnv_hh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200660; +} + +static void +Opcode_ae_mula4o4x16cnv_hl_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200760; +} + +static void +Opcode_ae_mula4o4x16cnv_lh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200860; +} + +static void +Opcode_ae_mula4o4x16cnv_ll_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200960; +} + +static void +Opcode_ae_muluu8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; + slotbuf[1] = 0x2c0002; +} + +static void +Opcode_ae_mulauu8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; + slotbuf[1] = 0x2c0001; +} + +static void +Opcode_ae_muluu4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x240002; +} + +static void +Opcode_ae_mulauu4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x240001; +} + +static void +Opcode_ae_muluu8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2cc728; +} + +static void +Opcode_ae_mulauu8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c6728; +} + +static void +Opcode_ae_muluu8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2cc628; +} + +static void +Opcode_ae_mulauu8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c6628; +} + +static void +Opcode_ae_muluu2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2cc628; +} + +static void +Opcode_ae_mulauu2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c6628; +} + +static void +Opcode_ae_muluu2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0028; +} + +static void +Opcode_ae_mulauu2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0018; +} + +static void +Opcode_ae_muluu4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x221860; +} + +static void +Opcode_ae_mulauu4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x211860; +} + +static void +Opcode_ae_muluu4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x223860; +} + +static void +Opcode_ae_mulauu4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x213860; +} + +static void +Opcode_ae_mulus8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0002000; + slotbuf[1] = 0x2c0001; +} + +static void +Opcode_ae_mulaus8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0002000; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mulus8q4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400; + slotbuf[1] = 0x2c0300; +} + +static void +Opcode_ae_mulaus8q4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400; + slotbuf[1] = 0x2c0200; +} + +static void +Opcode_ae_mulus8q8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mulaus8q8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mulus8qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x1c0000; +} + +static void +Opcode_ae_mulaus8qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x140000; +} + +static void +Opcode_ae_mulus4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x240001; +} + +static void +Opcode_ae_mulaus4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x240000; +} + +static void +Opcode_ae_mulus4o4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x28c000; +} + +static void +Opcode_ae_mulaus4o4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x288000; +} + +static void +Opcode_ae_mulus4o8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x180000; +} + +static void +Opcode_ae_mulaus4o8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x100000; +} + +static void +Opcode_ae_mulus4qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x28e000; +} + +static void +Opcode_ae_mulaus4qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x28a000; +} + +static void +Opcode_ae_mulus8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2ca728; +} + +static void +Opcode_ae_mulaus8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c4728; +} + +static void +Opcode_ae_mulus8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2ca728; +} + +static void +Opcode_ae_mulaus8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c4728; +} + +static void +Opcode_ae_mulus8q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0528; +} + +static void +Opcode_ae_mulaus8q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0428; +} + +static void +Opcode_ae_mulus2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2ca628; +} + +static void +Opcode_ae_mulaus2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c4628; +} + +static void +Opcode_ae_mulus2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0020; +} + +static void +Opcode_ae_mulaus2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0018; +} + +static void +Opcode_ae_mulus2x4q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0020; +} + +static void +Opcode_ae_mulaus2x4q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0010; +} + +static void +Opcode_ae_mulusqq8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200058; +} + +static void +Opcode_ae_mulausqq8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200028; +} + +static void +Opcode_ae_mulus4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x21d860; +} + +static void +Opcode_ae_mulaus4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x20d860; +} + +static void +Opcode_ae_mulus4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x21f860; +} + +static void +Opcode_ae_mulaus4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x20f860; +} + +static void +Opcode_ae_mulus4o8x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201660; +} + +static void +Opcode_ae_mulaus4o8x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201060; +} + +static void +Opcode_ae_mulus4o8x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201760; +} + +static void +Opcode_ae_mulaus4o8x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201160; +} + +static void +Opcode_ae_mulus8q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0428; +} + +static void +Opcode_ae_mulaus8q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0328; +} + +static void +Opcode_ae_mulus8q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0528; +} + +static void +Opcode_ae_mulaus8q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0328; +} + +static void +Opcode_ae_mulus2x4q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0020; +} + +static void +Opcode_ae_mulaus2x4q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0010; +} + +static void +Opcode_ae_mulus2x4q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0020; +} + +static void +Opcode_ae_mulaus2x4q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0010; +} + +static void +Opcode_ae_mulusqq4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200048; +} + +static void +Opcode_ae_mulausqq4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200018; +} + +static void +Opcode_ae_mulusqq4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200050; +} + +static void +Opcode_ae_mulausqq4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200020; +} + +static void +Opcode_ae_mulus4o4x16cnv_hh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201260; +} + +static void +Opcode_ae_mulus4o4x16cnv_hl_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201360; +} + +static void +Opcode_ae_mulus4o4x16cnv_lh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201460; +} + +static void +Opcode_ae_mulus4o4x16cnv_ll_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201560; +} + +static void +Opcode_ae_mulaus4o4x16cnv_hh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200c60; +} + +static void +Opcode_ae_mulaus4o4x16cnv_hl_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200d60; +} + +static void +Opcode_ae_mulaus4o4x16cnv_lh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200e60; +} + +static void +Opcode_ae_mulaus4o4x16cnv_ll_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200f60; +} + +static void +Opcode_ae_mulsu8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002000; + slotbuf[1] = 0x2c0001; +} + +static void +Opcode_ae_mulasu8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002000; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mulsu4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x240001; +} + +static void +Opcode_ae_mulasu4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x240000; +} + +static void +Opcode_ae_mulsu8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2ca628; +} + +static void +Opcode_ae_mulasu8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c4628; +} + +static void +Opcode_ae_mulsu8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c8728; +} + +static void +Opcode_ae_mulasu8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c2728; +} + +static void +Opcode_ae_mulsu2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c8728; +} + +static void +Opcode_ae_mulasu2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c2728; +} + +static void +Opcode_ae_mulsu2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0018; +} + +static void +Opcode_ae_mulasu2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0010; +} + +static void +Opcode_ae_mulsu4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x219860; +} + +static void +Opcode_ae_mulasu4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x209860; +} + +static void +Opcode_ae_mulsu4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x21b860; +} + +static void +Opcode_ae_mulasu4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x20b860; +} + +static void +Opcode_ae_muluuzb8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002000; + slotbuf[1] = 0x2c0002; +} + +static void +Opcode_ae_mulauuzb8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002000; + slotbuf[1] = 0x2c0001; +} + +static void +Opcode_ae_muluuzb4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x240002; +} + +static void +Opcode_ae_mulauuzb4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x240001; +} + +static void +Opcode_ae_muluuzb8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2ce628; +} + +static void +Opcode_ae_mulauuzb8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c8628; +} + +static void +Opcode_ae_muluuzb8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2ce628; +} + +static void +Opcode_ae_mulauuzb8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c8628; +} + +static void +Opcode_ae_muluuzb2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2cc728; +} + +static void +Opcode_ae_mulauuzb2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c6728; +} + +static void +Opcode_ae_muluuzb2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0028; +} + +static void +Opcode_ae_mulauuzb2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0018; +} + +static void +Opcode_ae_muluuzb4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x225860; +} + +static void +Opcode_ae_mulauuzb4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x215860; +} + +static void +Opcode_ae_muluuzb4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x227860; +} + +static void +Opcode_ae_mulauuzb4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x217860; +} + +static void +Opcode_cvtsf16_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190c0026; + slotbuf[1] = 0; +} + +static void +Opcode_cvtsf16_l_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b7; +} + +static void +Opcode_cvtsf16_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a2f00; +} + +static void +Opcode_cvtsf16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190c0022; + slotbuf[1] = 0; +} + +static void +Opcode_cvtsf16_h_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b5; +} + +static void +Opcode_cvtsf16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a2b00; +} + +static void +Opcode_cvtf16s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1908002e; + slotbuf[1] = 0; +} + +static void +Opcode_cvtf16s_l_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b3; +} + +static void +Opcode_cvtf16s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2f00; +} + +static void +Opcode_cvtf16s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1908002a; + slotbuf[1] = 0; +} + +static void +Opcode_cvtf16s_h_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b1; +} + +static void +Opcode_cvtf16s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2b00; +} + +static void +Opcode_ae_movfcrfsrv_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4a0000; +} + +static void +Opcode_ae_movvfcrfsr_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4a8000; +} + +static void +Opcode_movt_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800e0; + slotbuf[1] = 0; +} + +static void +Opcode_movt_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481200; +} + +static void +Opcode_movt_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742e001; +} + +static void +Opcode_movf_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800d0; + slotbuf[1] = 0; +} + +static void +Opcode_movf_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480a00; +} + +static void +Opcode_movf_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742c001; +} + +static void +Opcode_moveqz_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d88000c; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04200; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480800; +} + +static void +Opcode_moveqz_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830000; +} + +static void +Opcode_movnez_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d88000a; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04b00; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481000; +} + +static void +Opcode_movnez_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98300c0; +} + +static void +Opcode_movgez_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880002; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04300; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480c00; +} + +static void +Opcode_movgez_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830040; +} + +static void +Opcode_movltz_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880006; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04a00; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480e00; +} + +static void +Opcode_movltz_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830080; +} + +static void +Opcode_rfr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929a04; +} + +static void +Opcode_wfr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e10c0; +} + +static void +Opcode_mul_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000020; + slotbuf[1] = 0x7; +} + +static void +Opcode_mul_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000020; + slotbuf[1] = 0x5; +} + +static void +Opcode_mul_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4300c00; + slotbuf[1] = 0; +} + +static void +Opcode_mul_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17001c0; +} + +static void +Opcode_mul_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae000080; + slotbuf[1] = 0; +} + +static void +Opcode_mul_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e000020; +} + +static void +Opcode_mul_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69003e0; +} + +static void +Opcode_mul_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003f; + slotbuf[1] = 0xe; +} + +static void +Opcode_madd_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; + slotbuf[1] = 0x7; +} + +static void +Opcode_madd_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000020; + slotbuf[1] = 0x5; +} + +static void +Opcode_madd_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe300800; + slotbuf[1] = 0; +} + +static void +Opcode_madd_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700160; +} + +static void +Opcode_madd_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8000080; + slotbuf[1] = 0; +} + +static void +Opcode_madd_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000020; +} + +static void +Opcode_madd_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900300; +} + +static void +Opcode_madd_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003c; + slotbuf[1] = 0xe; +} + +static void +Opcode_msub_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000020; + slotbuf[1] = 0x7; +} + +static void +Opcode_msub_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000020; + slotbuf[1] = 0x5; +} + +static void +Opcode_msub_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2300c00; + slotbuf[1] = 0; +} + +static void +Opcode_msub_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17001a0; +} + +static void +Opcode_msub_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac000080; + slotbuf[1] = 0; +} + +static void +Opcode_msub_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c000020; +} + +static void +Opcode_msub_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69003c0; +} + +static void +Opcode_msub_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003e; + slotbuf[1] = 0xe; +} + +static void +Opcode_msubn_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000020; + slotbuf[1] = 0x7; +} + +static void +Opcode_msubn_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44000020; + slotbuf[1] = 0x5; +} + +static void +Opcode_msubn_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0300c00; + slotbuf[1] = 0; +} + +static void +Opcode_msubn_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700180; +} + +static void +Opcode_msubn_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa000080; + slotbuf[1] = 0; +} + +static void +Opcode_msubn_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a000020; +} + +static void +Opcode_msubn_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69003a0; +} + +static void +Opcode_msubn_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003d; + slotbuf[1] = 0xe; +} + +static void +Opcode_maddn_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000020; + slotbuf[1] = 0x6; +} + +static void +Opcode_maddn_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000020; + slotbuf[1] = 0x4; +} + +static void +Opcode_maddn_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc300800; + slotbuf[1] = 0; +} + +static void +Opcode_maddn_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700140; +} + +static void +Opcode_maddn_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6000080; + slotbuf[1] = 0; +} + +static void +Opcode_maddn_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26000020; +} + +static void +Opcode_maddn_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69002e0; +} + +static void +Opcode_maddn_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003b; + slotbuf[1] = 0xe; +} + +static void +Opcode_add_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000022; + slotbuf[1] = 0x5; +} + +static void +Opcode_add_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000a0; + slotbuf[1] = 0x5; +} + +static void +Opcode_add_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a050000; + slotbuf[1] = 0; +} + +static void +Opcode_add_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1848000; +} + +static void +Opcode_add_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00021; + slotbuf[1] = 0; +} + +static void +Opcode_add_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000a0; +} + +static void +Opcode_add_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa048000; +} + +static void +Opcode_add_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068022; + slotbuf[1] = 0xe; +} + +static void +Opcode_sub_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000042; + slotbuf[1] = 0x5; +} + +static void +Opcode_sub_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000c0; + slotbuf[1] = 0x5; +} + +static void +Opcode_sub_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c050000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1870000; +} + +static void +Opcode_sub_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a000a1; + slotbuf[1] = 0; +} + +static void +Opcode_sub_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000c0; +} + +static void +Opcode_sub_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa050000; +} + +static void +Opcode_sub_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068042; + slotbuf[1] = 0xe; +} + +static void +Opcode_ole_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19200031; + slotbuf[1] = 0; +} + +static void +Opcode_ole_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640510; +} + +static void +Opcode_ole_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540081; +} + +static void +Opcode_ole_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022100; +} + +static void +Opcode_olt_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19240030; + slotbuf[1] = 0; +} + +static void +Opcode_olt_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640800; +} + +static void +Opcode_olt_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540090; +} + +static void +Opcode_olt_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022500; +} + +static void +Opcode_oeq_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19200030; + slotbuf[1] = 0; +} + +static void +Opcode_oeq_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640500; +} + +static void +Opcode_oeq_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540080; +} + +static void +Opcode_oeq_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022c00; +} + +static void +Opcode_un_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192c0030; + slotbuf[1] = 0; +} + +static void +Opcode_un_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640c00; +} + +static void +Opcode_un_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b0; +} + +static void +Opcode_un_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022600; +} + +static void +Opcode_ule_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19280030; + slotbuf[1] = 0; +} + +static void +Opcode_ule_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640900; +} + +static void +Opcode_ule_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400a0; +} + +static void +Opcode_ule_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022d00; +} + +static void +Opcode_ult_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19280031; + slotbuf[1] = 0; +} + +static void +Opcode_ult_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640910; +} + +static void +Opcode_ult_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400a1; +} + +static void +Opcode_ult_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022200; +} + +static void +Opcode_ueq_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19240031; + slotbuf[1] = 0; +} + +static void +Opcode_ueq_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640810; +} + +static void +Opcode_ueq_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540091; +} + +static void +Opcode_ueq_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022900; +} + +static void +Opcode_nexp01_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808008; + slotbuf[1] = 0x7; +} + +static void +Opcode_nexp01_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160004; + slotbuf[1] = 0x5; +} + +static void +Opcode_nexp01_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80211801; + slotbuf[1] = 0; +} + +static void +Opcode_nexp01_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700202; +} + +static void +Opcode_nexp01_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0c08001; + slotbuf[1] = 0; +} + +static void +Opcode_nexp01_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c45801d; +} + +static void +Opcode_nexp01_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa600026; +} + +static void +Opcode_nexp01_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40381002; + slotbuf[1] = 0xe; +} + +static void +Opcode_mksadj_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808004; + slotbuf[1] = 0x7; +} + +static void +Opcode_mksadj_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160003; + slotbuf[1] = 0x5; +} + +static void +Opcode_mksadj_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80111801; + slotbuf[1] = 0; +} + +static void +Opcode_mksadj_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700201; +} + +static void +Opcode_mksadj_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8c08001; + slotbuf[1] = 0; +} + +static void +Opcode_mksadj_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c35801d; +} + +static void +Opcode_mksadj_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa500026; +} + +static void +Opcode_mksadj_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40281002; + slotbuf[1] = 0xe; +} + +static void +Opcode_mkdadj_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000062; + slotbuf[1] = 0x6; +} + +static void +Opcode_mkdadj_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000e2; + slotbuf[1] = 0x5; +} + +static void +Opcode_mkdadj_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6390c00; + slotbuf[1] = 0; +} + +static void +Opcode_mkdadj_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17901e0; +} + +static void +Opcode_mkdadj_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab002c1; + slotbuf[1] = 0; +} + +static void +Opcode_mkdadj_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000e2; +} + +static void +Opcode_mkdadj_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa458000; +} + +static void +Opcode_mkdadj_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068862; + slotbuf[1] = 0xe; +} + +static void +Opcode_div0_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808003; + slotbuf[1] = 0x7; +} + +static void +Opcode_div0_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160001; + slotbuf[1] = 0x5; +} + +static void +Opcode_div0_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80011801; + slotbuf[1] = 0; +} + +static void +Opcode_div0_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700200; +} + +static void +Opcode_div0_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6c08001; + slotbuf[1] = 0; +} + +static void +Opcode_div0_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c15801d; +} + +static void +Opcode_div0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa500025; +} + +static void +Opcode_div0_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401f1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_sqrt0_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800b; + slotbuf[1] = 0x7; +} + +static void +Opcode_sqrt0_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160007; + slotbuf[1] = 0x5; +} + +static void +Opcode_sqrt0_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80511801; + slotbuf[1] = 0; +} + +static void +Opcode_sqrt0_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700205; +} + +static void +Opcode_sqrt0_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6c08001; + slotbuf[1] = 0; +} + +static void +Opcode_sqrt0_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c75801d; +} + +static void +Opcode_sqrt0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa700025; +} + +static void +Opcode_sqrt0_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40291002; + slotbuf[1] = 0xe; +} + +static void +Opcode_recip0_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808009; + slotbuf[1] = 0x7; +} + +static void +Opcode_recip0_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160005; + slotbuf[1] = 0x5; +} + +static void +Opcode_recip0_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80311801; + slotbuf[1] = 0; +} + +static void +Opcode_recip0_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700203; +} + +static void +Opcode_recip0_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2c08001; + slotbuf[1] = 0; +} + +static void +Opcode_recip0_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c55801d; +} + +static void +Opcode_recip0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa600027; +} + +static void +Opcode_recip0_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40289002; + slotbuf[1] = 0xe; +} + +static void +Opcode_rsqrt0_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800a; + slotbuf[1] = 0x7; +} + +static void +Opcode_rsqrt0_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160006; + slotbuf[1] = 0x5; +} + +static void +Opcode_rsqrt0_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80411801; + slotbuf[1] = 0; +} + +static void +Opcode_rsqrt0_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700204; +} + +static void +Opcode_rsqrt0_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4c08001; + slotbuf[1] = 0; +} + +static void +Opcode_rsqrt0_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c65801d; +} + +static void +Opcode_rsqrt0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa700024; +} + +static void +Opcode_rsqrt0_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40389002; + slotbuf[1] = 0xe; +} + +static void +Opcode_divn_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000020; + slotbuf[1] = 0x6; +} + +static void +Opcode_divn_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000020; + slotbuf[1] = 0x4; +} + +static void +Opcode_divn_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa300800; + slotbuf[1] = 0; +} + +static void +Opcode_divn_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700120; +} + +static void +Opcode_divn_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4000080; + slotbuf[1] = 0; +} + +static void +Opcode_divn_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000020; +} + +static void +Opcode_divn_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69002c0; +} + +static void +Opcode_divn_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003a; + slotbuf[1] = 0xe; +} + +static void +Opcode_addexp_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000061; + slotbuf[1] = 0x6; +} + +static void +Opcode_addexp_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000e1; + slotbuf[1] = 0x5; +} + +static void +Opcode_addexp_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6388c00; + slotbuf[1] = 0; +} + +static void +Opcode_addexp_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17881e0; +} + +static void +Opcode_addexp_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00261; + slotbuf[1] = 0; +} + +static void +Opcode_addexp_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000e1; +} + +static void +Opcode_addexp_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa358000; +} + +static void +Opcode_addexp_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068462; + slotbuf[1] = 0xe; +} + +static void +Opcode_addexpm_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000060; + slotbuf[1] = 0x6; +} + +static void +Opcode_addexpm_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000e0; + slotbuf[1] = 0x5; +} + +static void +Opcode_addexpm_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6380c00; + slotbuf[1] = 0; +} + +static void +Opcode_addexpm_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17801e0; +} + +static void +Opcode_addexpm_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00241; + slotbuf[1] = 0; +} + +static void +Opcode_addexpm_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000e0; +} + +static void +Opcode_addexpm_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa258000; +} + +static void +Opcode_addexpm_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068062; + slotbuf[1] = 0xe; +} + +static void +Opcode_min_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000040; + slotbuf[1] = 0x6; +} + +static void +Opcode_min_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205001b; + slotbuf[1] = 0x5; +} + +static void +Opcode_min_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c048000; + slotbuf[1] = 0; +} + +static void +Opcode_min_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1830000; +} + +static void +Opcode_min_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00141; + slotbuf[1] = 0; +} + +static void +Opcode_min_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05001b; +} + +static void +Opcode_min_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa030000; +} + +static void +Opcode_min_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400d8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_max_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000060; + slotbuf[1] = 0x6; +} + +static void +Opcode_max_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82058019; + slotbuf[1] = 0x5; +} + +static void +Opcode_max_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e040000; + slotbuf[1] = 0; +} + +static void +Opcode_max_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1818000; +} + +static void +Opcode_max_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00181; + slotbuf[1] = 0; +} + +static void +Opcode_max_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c058019; +} + +static void +Opcode_max_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa018000; +} + +static void +Opcode_max_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_mulmux_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulmux_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000020; + slotbuf[1] = 0x4; +} + +static void +Opcode_mulmux_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0300000; + slotbuf[1] = 0; +} + +static void +Opcode_mulmux_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000080; + slotbuf[1] = 0; +} + +static void +Opcode_mulmux_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000020; +} + +static void +Opcode_mulmux_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00000; +} + +static void +Opcode_mulmux_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80100038; + slotbuf[1] = 0xe; +} + +static void +Opcode_maddmux_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_maddmux_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_maddmux_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0300000; + slotbuf[1] = 0; +} + +static void +Opcode_maddmux_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000000; + slotbuf[1] = 0; +} + +static void +Opcode_maddmux_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000000; +} + +static void +Opcode_maddmux_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00000; +} + +static void +Opcode_maddmux_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000038; + slotbuf[1] = 0xe; +} + +static void +Opcode_trunc_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19030010; + slotbuf[1] = 0; +} + +static void +Opcode_trunc_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800010; +} + +static void +Opcode_trunc_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1308; +} + +static void +Opcode_utrunc_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19032010; + slotbuf[1] = 0; +} + +static void +Opcode_utrunc_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2802010; +} + +static void +Opcode_utrunc_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9208; +} + +static void +Opcode_trunc_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000024; + slotbuf[1] = 0; +} + +static void +Opcode_trunc_sx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800002; +} + +static void +Opcode_trunc_sx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c06000; +} + +static void +Opcode_utrunc_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900002c; + slotbuf[1] = 0; +} + +static void +Opcode_utrunc_sx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800006; +} + +static void +Opcode_utrunc_sx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c02001; +} + +static void +Opcode_ficeil_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190c002a; + slotbuf[1] = 0; +} + +static void +Opcode_ficeil_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b9; +} + +static void +Opcode_ficeil_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62a2b00; +} + +static void +Opcode_fifloor_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190c002e; + slotbuf[1] = 0; +} + +static void +Opcode_fifloor_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400bb; +} + +static void +Opcode_fifloor_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62a2f00; +} + +static void +Opcode_firint_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19100022; + slotbuf[1] = 0; +} + +static void +Opcode_firint_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400bd; +} + +static void +Opcode_firint_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63a2b00; +} + +static void +Opcode_firound_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19100026; + slotbuf[1] = 0; +} + +static void +Opcode_firound_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400bf; +} + +static void +Opcode_firound_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63a2f00; +} + +static void +Opcode_fitrunc_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1910002a; + slotbuf[1] = 0; +} + +static void +Opcode_fitrunc_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800008; +} + +static void +Opcode_fitrunc_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380f00; +} + +static void +Opcode_float_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18800b00; + slotbuf[1] = 0; +} + +static void +Opcode_float_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000000; +} + +static void +Opcode_float_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00100; +} + +static void +Opcode_ufloat_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18800b04; + slotbuf[1] = 0; +} + +static void +Opcode_ufloat_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000002; +} + +static void +Opcode_ufloat_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00140; +} + +static void +Opcode_float_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000020; + slotbuf[1] = 0; +} + +static void +Opcode_float_sx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800000; +} + +static void +Opcode_float_sx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04000; +} + +static void +Opcode_ufloat_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000028; + slotbuf[1] = 0; +} + +static void +Opcode_ufloat_sx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800004; +} + +static void +Opcode_ufloat_sx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00001; +} + +static void +Opcode_abs_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808000; + slotbuf[1] = 0x7; +} + +static void +Opcode_abs_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160008; + slotbuf[1] = 0x5; +} + +static void +Opcode_abs_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000a; + slotbuf[1] = 0; +} + +static void +Opcode_abs_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80611801; + slotbuf[1] = 0; +} + +static void +Opcode_abs_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700206; +} + +static void +Opcode_abs_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c08001; + slotbuf[1] = 0; +} + +static void +Opcode_abs_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c85801d; +} + +static void +Opcode_abs_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa400026; +} + +static void +Opcode_abs_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40391002; + slotbuf[1] = 0xe; +} + +static void +Opcode_neg_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808007; + slotbuf[1] = 0x7; +} + +static void +Opcode_neg_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000d; + slotbuf[1] = 0x5; +} + +static void +Opcode_neg_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2800a; + slotbuf[1] = 0; +} + +static void +Opcode_neg_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80b11801; + slotbuf[1] = 0; +} + +static void +Opcode_neg_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020b; +} + +static void +Opcode_neg_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcec08001; + slotbuf[1] = 0; +} + +static void +Opcode_neg_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cd5801d; +} + +static void +Opcode_neg_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa600025; +} + +static void +Opcode_neg_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402a9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_conjc_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808002; + slotbuf[1] = 0x7; +} + +static void +Opcode_conjc_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000a; + slotbuf[1] = 0x5; +} + +static void +Opcode_conjc_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d1000a; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80811801; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700208; +} + +static void +Opcode_conjc_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4c08001; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca5801d; +} + +static void +Opcode_conjc_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa500024; +} + +static void +Opcode_conjc_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40399002; + slotbuf[1] = 0xe; +} + +static void +Opcode_muljc_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808006; + slotbuf[1] = 0x7; +} + +static void +Opcode_muljc_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000c; + slotbuf[1] = 0x5; +} + +static void +Opcode_muljc_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2000a; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a11801; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020a; +} + +static void +Opcode_muljc_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xccc08001; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc5801d; +} + +static void +Opcode_muljc_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa600024; +} + +static void +Opcode_muljc_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403a1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_const_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808011; + slotbuf[1] = 0x7; +} + +static void +Opcode_const_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160013; + slotbuf[1] = 0x5; +} + +static void +Opcode_const_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3000b; + slotbuf[1] = 0; +} + +static void +Opcode_const_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81011a01; + slotbuf[1] = 0; +} + +static void +Opcode_const_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700211; +} + +static void +Opcode_const_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdec0c001; + slotbuf[1] = 0; +} + +static void +Opcode_const_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d25c01d; +} + +static void +Opcode_const_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00025; +} + +static void +Opcode_const_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44300003; + slotbuf[1] = 0xe; +} + +static void +Opcode_clsfy_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82810000; + slotbuf[1] = 0x7; +} + +static void +Opcode_clsfy_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160000; + slotbuf[1] = 0x5; +} + +static void +Opcode_clsfy_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e050000; + slotbuf[1] = 0; +} + +static void +Opcode_clsfy_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1878000; +} + +static void +Opcode_clsfy_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c10001; + slotbuf[1] = 0; +} + +static void +Opcode_clsfy_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05801d; +} + +static void +Opcode_clsfy_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000021; +} + +static void +Opcode_clsfy_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401e9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_minnum_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000060; + slotbuf[1] = 0x6; +} + +static void +Opcode_minnum_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205801a; + slotbuf[1] = 0x5; +} + +static void +Opcode_minnum_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a048000; + slotbuf[1] = 0; +} + +static void +Opcode_minnum_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1828000; +} + +static void +Opcode_minnum_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a000c1; + slotbuf[1] = 0; +} + +static void +Opcode_minnum_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05801a; +} + +static void +Opcode_minnum_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa028000; +} + +static void +Opcode_minnum_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400d0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_maxnum_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000040; + slotbuf[1] = 0x6; +} + +static void +Opcode_maxnum_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82050019; + slotbuf[1] = 0x5; +} + +static void +Opcode_maxnum_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c040000; + slotbuf[1] = 0; +} + +static void +Opcode_maxnum_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1810000; +} + +static void +Opcode_maxnum_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00101; + slotbuf[1] = 0; +} + +static void +Opcode_maxnum_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c050019; +} + +static void +Opcode_maxnum_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa010000; +} + +static void +Opcode_maxnum_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400b8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_addandsub_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000001; + slotbuf[1] = 0x5; +} + +static void +Opcode_addandsub_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82048000; + slotbuf[1] = 0x5; +} + +static void +Opcode_addandsub_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80019000; + slotbuf[1] = 0; +} + +static void +Opcode_addandsub_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addandsub_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0900001; + slotbuf[1] = 0; +} + +static void +Opcode_addandsub_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c048000; +} + +static void +Opcode_addandsub_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000140; +} + +static void +Opcode_addandsub_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40048002; + slotbuf[1] = 0xe; +} + +static void +Opcode_addandsubjc_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_addandsubjc_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82040000; + slotbuf[1] = 0x5; +} + +static void +Opcode_addandsubjc_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80011000; + slotbuf[1] = 0; +} + +static void +Opcode_addandsubjc_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_addandsubjc_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0800001; + slotbuf[1] = 0; +} + +static void +Opcode_addandsubjc_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c040000; +} + +static void +Opcode_addandsubjc_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000120; +} + +static void +Opcode_addandsubjc_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40060002; + slotbuf[1] = 0xe; +} + +static void +Opcode_add_hl_lh_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000002; + slotbuf[1] = 0x5; +} + +static void +Opcode_add_hl_lh_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000080; + slotbuf[1] = 0x5; +} + +static void +Opcode_add_hl_lh_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88050000; + slotbuf[1] = 0; +} + +static void +Opcode_add_hl_lh_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1840000; +} + +static void +Opcode_add_hl_lh_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a001c1; + slotbuf[1] = 0; +} + +static void +Opcode_add_hl_lh_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000080; +} + +static void +Opcode_add_hl_lh_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa040000; +} + +static void +Opcode_add_hl_lh_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068002; + slotbuf[1] = 0xe; +} + +static void +Opcode_madda_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_madda_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_madda_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000000; + slotbuf[1] = 0; +} + +static void +Opcode_madda_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000000; + slotbuf[1] = 0; +} + +static void +Opcode_madda_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000000; +} + +static void +Opcode_madda_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5800000; +} + +static void +Opcode_madda_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000034; + slotbuf[1] = 0xe; +} + +static void +Opcode_frexp_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000040; + slotbuf[1] = 0x6; +} + +static void +Opcode_frexp_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82050018; + slotbuf[1] = 0x5; +} + +static void +Opcode_frexp_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88040000; + slotbuf[1] = 0; +} + +static void +Opcode_frexp_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; +} + +static void +Opcode_frexp_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00001; + slotbuf[1] = 0; +} + +static void +Opcode_frexp_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c050018; +} + +static void +Opcode_frexp_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; +} + +static void +Opcode_frexp_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400a8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_floatexp_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82810020; + slotbuf[1] = 0x7; +} + +static void +Opcode_floatexp_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160002; + slotbuf[1] = 0x5; +} + +static void +Opcode_floatexp_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e050001; + slotbuf[1] = 0; +} + +static void +Opcode_floatexp_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1878001; +} + +static void +Opcode_floatexp_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c10021; + slotbuf[1] = 0; +} + +static void +Opcode_floatexp_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c25801d; +} + +static void +Opcode_floatexp_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa008021; +} + +static void +Opcode_floatexp_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401f9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_minnumabs_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000040; + slotbuf[1] = 0x6; +} + +static void +Opcode_minnumabs_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205001a; + slotbuf[1] = 0x5; +} + +static void +Opcode_minnumabs_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88048000; + slotbuf[1] = 0; +} + +static void +Opcode_minnumabs_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1820000; +} + +static void +Opcode_minnumabs_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00041; + slotbuf[1] = 0; +} + +static void +Opcode_minnumabs_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05001a; +} + +static void +Opcode_minnumabs_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa020000; +} + +static void +Opcode_minnumabs_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_maxnumabs_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000060; + slotbuf[1] = 0x6; +} + +static void +Opcode_maxnumabs_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82058018; + slotbuf[1] = 0x5; +} + +static void +Opcode_maxnumabs_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a040000; + slotbuf[1] = 0; +} + +static void +Opcode_maxnumabs_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1808000; +} + +static void +Opcode_maxnumabs_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00081; + slotbuf[1] = 0; +} + +static void +Opcode_maxnumabs_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c058018; +} + +static void +Opcode_maxnumabs_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa008000; +} + +static void +Opcode_maxnumabs_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400b0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_mulq_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_mulq_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulq_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98000000; + slotbuf[1] = 0; +} + +static void +Opcode_mulq_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000000; +} + +static void +Opcode_maddq_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_maddq_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_maddq_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94000000; + slotbuf[1] = 0; +} + +static void +Opcode_maddq_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000000; +} + +static void +Opcode_msubq_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_msubq_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_msubq_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96000000; + slotbuf[1] = 0; +} + +static void +Opcode_msubq_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000000; +} + +static void +Opcode_mulmuxq_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulmuxq_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_mulmuxq_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000000; + slotbuf[1] = 0; +} + +static void +Opcode_mulmuxq_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; +} + +static void +Opcode_maddmuxq_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x6; +} + +static void +Opcode_maddmuxq_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4; +} + +static void +Opcode_maddmuxq_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_maddmuxq_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_bmaxnum_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82058008; + slotbuf[1] = 0x5; +} + +static void +Opcode_bmaxnum_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82040000; + slotbuf[1] = 0; +} + +static void +Opcode_bmaxnum_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c058008; +} + +static void +Opcode_bmaxnum_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c0402; + slotbuf[1] = 0xe; +} + +static void +Opcode_bminnum_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82058010; + slotbuf[1] = 0x5; +} + +static void +Opcode_bminnum_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86040000; + slotbuf[1] = 0; +} + +static void +Opcode_bminnum_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c058010; +} + +static void +Opcode_bminnum_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c0802; + slotbuf[1] = 0xe; +} + +static void +Opcode_bmaxnumabs_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82058000; + slotbuf[1] = 0x5; +} + +static void +Opcode_bmaxnumabs_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80040000; + slotbuf[1] = 0; +} + +static void +Opcode_bmaxnumabs_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c058000; +} + +static void +Opcode_bmaxnumabs_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40080402; + slotbuf[1] = 0xe; +} + +static void +Opcode_bminnumabs_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82050010; + slotbuf[1] = 0x5; +} + +static void +Opcode_bminnumabs_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84040000; + slotbuf[1] = 0; +} + +static void +Opcode_bminnumabs_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c050010; +} + +static void +Opcode_bminnumabs_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40080802; + slotbuf[1] = 0xe; +} + +static void +Opcode_abs_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82100000; + slotbuf[1] = 0x7; +} + +static void +Opcode_abs_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82008000; + slotbuf[1] = 0x5; +} + +static void +Opcode_abs_sx2x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80018000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_sx2x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_abs_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0100001; + slotbuf[1] = 0; +} + +static void +Opcode_abs_sx2x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c008000; +} + +static void +Opcode_abs_sx2x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000020; +} + +static void +Opcode_abs_sx2x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40008002; + slotbuf[1] = 0xe; +} + +static void +Opcode_neg_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82700000; + slotbuf[1] = 0x7; +} + +static void +Opcode_neg_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82038000; + slotbuf[1] = 0x5; +} + +static void +Opcode_neg_sx2x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; + slotbuf[1] = 0; +} + +static void +Opcode_neg_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80018c00; + slotbuf[1] = 0; +} + +static void +Opcode_neg_sx2x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_neg_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0700001; + slotbuf[1] = 0; +} + +static void +Opcode_neg_sx2x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c038000; +} + +static void +Opcode_neg_sx2x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000e0; +} + +static void +Opcode_neg_sx2x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40040002; + slotbuf[1] = 0xe; +} + +static void +Opcode_conjc_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82300000; + slotbuf[1] = 0x7; +} + +static void +Opcode_conjc_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82018000; + slotbuf[1] = 0x5; +} + +static void +Opcode_conjc_sx2x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80018400; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_sx2x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_conjc_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0300001; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_sx2x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c018000; +} + +static void +Opcode_conjc_sx2x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000060; +} + +static void +Opcode_conjc_sx2x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40010002; + slotbuf[1] = 0xe; +} + +static void +Opcode_muljc_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82500000; + slotbuf[1] = 0x7; +} + +static void +Opcode_muljc_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82028000; + slotbuf[1] = 0x5; +} + +static void +Opcode_muljc_sx2x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80018800; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_sx2x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_muljc_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0500001; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_sx2x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c028000; +} + +static void +Opcode_muljc_sx2x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000a0; +} + +static void +Opcode_muljc_sx2x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40018002; + slotbuf[1] = 0xe; +} + +static void +Opcode_const_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82804000; + slotbuf[1] = 0x7; +} + +static void +Opcode_const_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82064000; + slotbuf[1] = 0x5; +} + +static void +Opcode_const_sx2x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00003; + slotbuf[1] = 0; +} + +static void +Opcode_const_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80011a00; + slotbuf[1] = 0; +} + +static void +Opcode_const_sx2x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1904001; +} + +static void +Opcode_const_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c04001; + slotbuf[1] = 0; +} + +static void +Opcode_const_sx2x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c064000; +} + +static void +Opcode_const_sx2x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa004020; +} + +static void +Opcode_const_sx2x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46000003; + slotbuf[1] = 0xe; +} + +static void +Opcode_add_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_add_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_add_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_sub_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_sub_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_mul_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x3; +} + +static void +Opcode_mul_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x3; +} + +static void +Opcode_madd_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_madd_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_msub_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_msub_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_mulmux_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_mulmux_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_maddmux_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_maddmux_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_abs_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800c; + slotbuf[1] = 0x7; +} + +static void +Opcode_abs_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000e; + slotbuf[1] = 0x5; +} + +static void +Opcode_abs_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03001; + slotbuf[1] = 0; +} + +static void +Opcode_abs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80c11801; + slotbuf[1] = 0; +} + +static void +Opcode_abs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020c; +} + +static void +Opcode_abs_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8c08001; + slotbuf[1] = 0; +} + +static void +Opcode_abs_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce5801d; +} + +static void +Opcode_abs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf58000; +} + +static void +Opcode_abs_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403a9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_addexp_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000064; + slotbuf[1] = 0x6; +} + +static void +Opcode_addexp_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000e4; + slotbuf[1] = 0x5; +} + +static void +Opcode_addexp_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63f0c00; + slotbuf[1] = 0; +} + +static void +Opcode_addexp_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a01e0; +} + +static void +Opcode_addexp_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00341; + slotbuf[1] = 0; +} + +static void +Opcode_addexp_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000e4; +} + +static void +Opcode_addexp_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa700027; +} + +static void +Opcode_addexp_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40069062; + slotbuf[1] = 0xe; +} + +static void +Opcode_addexpm_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000063; + slotbuf[1] = 0x6; +} + +static void +Opcode_addexpm_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000e3; + slotbuf[1] = 0x5; +} + +static void +Opcode_addexpm_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63e8c00; + slotbuf[1] = 0; +} + +static void +Opcode_addexpm_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17981e0; +} + +static void +Opcode_addexpm_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab002e1; + slotbuf[1] = 0; +} + +static void +Opcode_addexpm_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000e3; +} + +static void +Opcode_addexpm_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa700026; +} + +static void +Opcode_addexpm_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_clsfy_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800d; + slotbuf[1] = 0x7; +} + +static void +Opcode_clsfy_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000f; + slotbuf[1] = 0x5; +} + +static void +Opcode_clsfy_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80d11801; + slotbuf[1] = 0; +} + +static void +Opcode_clsfy_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020d; +} + +static void +Opcode_clsfy_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdac08001; + slotbuf[1] = 0; +} + +static void +Opcode_clsfy_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cf5801d; +} + +static void +Opcode_clsfy_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb058000; +} + +static void +Opcode_clsfy_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402b1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_conjc_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808001; + slotbuf[1] = 0x7; +} + +static void +Opcode_conjc_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160009; + slotbuf[1] = 0x5; +} + +static void +Opcode_conjc_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0800a; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80711801; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700207; +} + +static void +Opcode_conjc_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2c08001; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c95801d; +} + +static void +Opcode_conjc_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa400027; +} + +static void +Opcode_conjc_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40299002; + slotbuf[1] = 0xe; +} + +static void +Opcode_const_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808010; + slotbuf[1] = 0x7; +} + +static void +Opcode_const_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160012; + slotbuf[1] = 0x5; +} + +static void +Opcode_const_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3000a; + slotbuf[1] = 0; +} + +static void +Opcode_const_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81011801; + slotbuf[1] = 0; +} + +static void +Opcode_const_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700210; +} + +static void +Opcode_const_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdec08001; + slotbuf[1] = 0; +} + +static void +Opcode_const_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d25801d; +} + +static void +Opcode_const_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00024; +} + +static void +Opcode_const_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44200003; + slotbuf[1] = 0xe; +} + +static void +Opcode_min_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4100003; + slotbuf[1] = 0x6; +} + +static void +Opcode_min_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205001d; + slotbuf[1] = 0x5; +} + +static void +Opcode_min_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80119400; + slotbuf[1] = 0; +} + +static void +Opcode_min_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700100; +} + +static void +Opcode_min_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6b00001; + slotbuf[1] = 0; +} + +static void +Opcode_min_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05001d; +} + +static void +Opcode_min_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900380; +} + +static void +Opcode_min_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400f8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_max_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000003; + slotbuf[1] = 0x6; +} + +static void +Opcode_max_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205001c; + slotbuf[1] = 0x5; +} + +static void +Opcode_max_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80019400; + slotbuf[1] = 0; +} + +static void +Opcode_max_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000c0; +} + +static void +Opcode_max_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2b00001; + slotbuf[1] = 0; +} + +static void +Opcode_max_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05001c; +} + +static void +Opcode_max_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900340; +} + +static void +Opcode_max_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400e8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_minnum_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4100002; + slotbuf[1] = 0x6; +} + +static void +Opcode_minnum_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205801c; + slotbuf[1] = 0x5; +} + +static void +Opcode_minnum_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80111400; + slotbuf[1] = 0; +} + +static void +Opcode_minnum_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000e0; +} + +static void +Opcode_minnum_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4b00001; + slotbuf[1] = 0; +} + +static void +Opcode_minnum_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05801c; +} + +static void +Opcode_minnum_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900360; +} + +static void +Opcode_minnum_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400f0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_maxnum_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000002; + slotbuf[1] = 0x6; +} + +static void +Opcode_maxnum_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205801b; + slotbuf[1] = 0x5; +} + +static void +Opcode_maxnum_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80011400; + slotbuf[1] = 0; +} + +static void +Opcode_maxnum_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000a0; +} + +static void +Opcode_maxnum_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0b00001; + slotbuf[1] = 0; +} + +static void +Opcode_maxnum_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05801b; +} + +static void +Opcode_maxnum_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900320; +} + +static void +Opcode_maxnum_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400e0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_muljc_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808005; + slotbuf[1] = 0x7; +} + +static void +Opcode_muljc_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000b; + slotbuf[1] = 0x5; +} + +static void +Opcode_muljc_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d1800a; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80911801; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700209; +} + +static void +Opcode_muljc_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcac08001; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cb5801d; +} + +static void +Opcode_muljc_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa500027; +} + +static void +Opcode_muljc_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402a1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_neg_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800e; + slotbuf[1] = 0x7; +} + +static void +Opcode_neg_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160010; + slotbuf[1] = 0x5; +} + +static void +Opcode_neg_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03011; + slotbuf[1] = 0; +} + +static void +Opcode_neg_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80e11801; + slotbuf[1] = 0; +} + +static void +Opcode_neg_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020e; +} + +static void +Opcode_neg_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdcc08001; + slotbuf[1] = 0; +} + +static void +Opcode_neg_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d05801d; +} + +static void +Opcode_neg_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb158000; +} + +static void +Opcode_neg_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403b1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_oeq_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2e00; +} + +static void +Opcode_ole_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022300; +} + +static void +Opcode_olt_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022700; +} + +static void +Opcode_ueq_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022b00; +} + +static void +Opcode_ule_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022f00; +} + +static void +Opcode_ult_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2300; +} + +static void +Opcode_un_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2700; +} + +static void +Opcode_div0_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800027; +} + +static void +Opcode_ficeil_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19184030; + slotbuf[1] = 0; +} + +static void +Opcode_ficeil_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0430a; +} + +static void +Opcode_fifloor_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19186030; + slotbuf[1] = 0; +} + +static void +Opcode_fifloor_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0630a; +} + +static void +Opcode_firint_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1918c030; + slotbuf[1] = 0; +} + +static void +Opcode_firint_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0430b; +} + +static void +Opcode_firound_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1918e030; + slotbuf[1] = 0; +} + +static void +Opcode_firound_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0630b; +} + +static void +Opcode_fitrunc_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19194030; + slotbuf[1] = 0; +} + +static void +Opcode_fitrunc_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0020c; +} + +static void +Opcode_mkdadj_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb258000; +} + +static void +Opcode_mksadj_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa900024; +} + +static void +Opcode_nexp0_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa900026; +} + +static void +Opcode_nexp01_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa900025; +} + +static void +Opcode_recip0_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa900027; +} + +static void +Opcode_rsqrt0_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa00024; +} + +static void +Opcode_sqrt0_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa00025; +} + +static void +Opcode_float16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18980f00; + slotbuf[1] = 0; +} + +static void +Opcode_float16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c01200; +} + +static void +Opcode_ufloat16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x189a0f00; + slotbuf[1] = 0; +} + +static void +Opcode_ufloat16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c01240; +} + +static void +Opcode_trunc16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19300030; + slotbuf[1] = 0; +} + +static void +Opcode_trunc16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c01208; +} + +static void +Opcode_utrunc16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19320030; + slotbuf[1] = 0; +} + +static void +Opcode_utrunc16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c01608; +} + +static void +Opcode_float16_hx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d820000; + slotbuf[1] = 0; +} + +static void +Opcode_float16_hx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00200; +} + +static void +Opcode_ufloat16_hx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d820020; + slotbuf[1] = 0; +} + +static void +Opcode_ufloat16_hx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04200; +} + +static void +Opcode_trunc16_hx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d820010; + slotbuf[1] = 0; +} + +static void +Opcode_trunc16_hx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c02200; +} + +static void +Opcode_utrunc16_hx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d820030; + slotbuf[1] = 0; +} + +static void +Opcode_utrunc16_hx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c06200; +} + +static void +Opcode_add_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000001; + slotbuf[1] = 0x6; +} + +static void +Opcode_add_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000040; + slotbuf[1] = 0x5; +} + +static void +Opcode_add_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0118000; + slotbuf[1] = 0; +} + +static void +Opcode_add_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1838000; +} + +static void +Opcode_add_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000080; + slotbuf[1] = 0; +} + +static void +Opcode_add_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000040; +} + +static void +Opcode_add_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8148000; +} + +static void +Opcode_add_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_sub_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000a1; + slotbuf[1] = 0x6; +} + +static void +Opcode_sub_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000062; + slotbuf[1] = 0x5; +} + +static void +Opcode_sub_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc118000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1868000; +} + +static void +Opcode_sub_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000085; + slotbuf[1] = 0; +} + +static void +Opcode_sub_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000062; +} + +static void +Opcode_sub_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8178000; +} + +static void +Opcode_sub_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006062; + slotbuf[1] = 0xe; +} + +static void +Opcode_mul_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000081; + slotbuf[1] = 0x6; +} + +static void +Opcode_mul_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000042; + slotbuf[1] = 0x5; +} + +static void +Opcode_mul_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca118000; + slotbuf[1] = 0; +} + +static void +Opcode_mul_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1860000; +} + +static void +Opcode_mul_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000084; + slotbuf[1] = 0; +} + +static void +Opcode_mul_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000042; +} + +static void +Opcode_mul_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8170000; +} + +static void +Opcode_mul_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_madd_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000021; + slotbuf[1] = 0x6; +} + +static void +Opcode_madd_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000060; + slotbuf[1] = 0x5; +} + +static void +Opcode_madd_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6118000; + slotbuf[1] = 0; +} + +static void +Opcode_madd_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1850000; +} + +static void +Opcode_madd_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000081; + slotbuf[1] = 0; +} + +static void +Opcode_madd_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000060; +} + +static void +Opcode_madd_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8160000; +} + +static void +Opcode_madd_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005062; + slotbuf[1] = 0xe; +} + +static void +Opcode_msub_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000061; + slotbuf[1] = 0x6; +} + +static void +Opcode_msub_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000061; + slotbuf[1] = 0x5; +} + +static void +Opcode_msub_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8118000; + slotbuf[1] = 0; +} + +static void +Opcode_msub_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1858000; +} + +static void +Opcode_msub_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000083; + slotbuf[1] = 0; +} + +static void +Opcode_msub_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000061; +} + +static void +Opcode_msub_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8168000; +} + +static void +Opcode_msub_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005862; + slotbuf[1] = 0xe; +} + +static void +Opcode_maddn_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4118000; + slotbuf[1] = 0; +} + +static void +Opcode_maddn_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8158000; +} + +static void +Opcode_msubn_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000041; + slotbuf[1] = 0x6; +} + +static void +Opcode_msubn_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000041; + slotbuf[1] = 0x5; +} + +static void +Opcode_msubn_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000082; + slotbuf[1] = 0; +} + +static void +Opcode_msubn_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000041; +} + +static void +Opcode_msubn_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005462; + slotbuf[1] = 0xe; +} + +static void +Opcode_divn_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2118000; + slotbuf[1] = 0; +} + +static void +Opcode_divn_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8150000; +} + +static void +Opcode_rminnum_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1919e030; + slotbuf[1] = 0; +} + +static void +Opcode_rminnum_h_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540ae0; +} + +static void +Opcode_rminnum_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0620c; +} + +static void +Opcode_rmaxnum_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1919c030; + slotbuf[1] = 0; +} + +static void +Opcode_rmaxnum_h_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25406e0; +} + +static void +Opcode_rmaxnum_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0420c; +} + +static void +Opcode_abs_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_abs_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_abs_hx4x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_hx4x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80010000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_hx4x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000001; + slotbuf[1] = 0; +} + +static void +Opcode_abs_hx4x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000000; +} + +static void +Opcode_abs_hx4x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; +} + +static void +Opcode_abs_hx4x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40020002; + slotbuf[1] = 0xe; +} + +static void +Opcode_neg_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82600000; + slotbuf[1] = 0x7; +} + +static void +Opcode_neg_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82030000; + slotbuf[1] = 0x5; +} + +static void +Opcode_neg_hx4x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; + slotbuf[1] = 0; +} + +static void +Opcode_neg_hx4x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80010c00; + slotbuf[1] = 0; +} + +static void +Opcode_neg_hx4x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0600001; + slotbuf[1] = 0; +} + +static void +Opcode_neg_hx4x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c030000; +} + +static void +Opcode_neg_hx4x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000c0; +} + +static void +Opcode_neg_hx4x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40038002; + slotbuf[1] = 0xe; +} + +static void +Opcode_conjc_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82200000; + slotbuf[1] = 0x7; +} + +static void +Opcode_conjc_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82010000; + slotbuf[1] = 0x5; +} + +static void +Opcode_conjc_hx4x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_hx4x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80010400; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_hx4x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200001; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_hx4x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c010000; +} + +static void +Opcode_conjc_hx4x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000040; +} + +static void +Opcode_conjc_hx4x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40028002; + slotbuf[1] = 0xe; +} + +static void +Opcode_const_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82800000; + slotbuf[1] = 0x7; +} + +static void +Opcode_const_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82060000; + slotbuf[1] = 0x5; +} + +static void +Opcode_const_hx4x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00002; + slotbuf[1] = 0; +} + +static void +Opcode_const_hx4x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80011800; + slotbuf[1] = 0; +} + +static void +Opcode_const_hx4x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1904000; +} + +static void +Opcode_const_hx4x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c00001; + slotbuf[1] = 0; +} + +static void +Opcode_const_hx4x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c060000; +} + +static void +Opcode_const_hx4x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000020; +} + +static void +Opcode_const_hx4x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44000003; + slotbuf[1] = 0xe; +} + +static void +Opcode_muljc_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82400000; + slotbuf[1] = 0x7; +} + +static void +Opcode_muljc_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82020000; + slotbuf[1] = 0x5; +} + +static void +Opcode_muljc_hx4x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_hx4x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80010800; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_hx4x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0400001; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_hx4x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c020000; +} + +static void +Opcode_muljc_hx4x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000080; +} + +static void +Opcode_muljc_hx4x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40030002; + slotbuf[1] = 0xe; +} + +static void +Opcode_add_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_sub_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_mul_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4; +} + +static void +Opcode_mul_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_madd_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_madd_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_msub_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_msub_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_mulq_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulq_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulq_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a000000; + slotbuf[1] = 0; +} + +static void +Opcode_maddq_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x5; +} + +static void +Opcode_maddq_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulcnvh_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulcnvh_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulacnvh_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulacnvh_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulcnvl_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulcnvl_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulacnvl_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulacnvl_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40; + slotbuf[1] = 0x6; +} + +static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { + Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { + Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0, Opcode_addi_Slot_ae_slot0_encode, Opcode_addi_Slot_ae_slot1_encode, 0, 0, Opcode_addi_Slot_ae2_slot0_encode, Opcode_addi_Slot_ae2_slot1_encode, 0, Opcode_addi_Slot_ae3_slot0_encode, Opcode_addi_Slot_ae3_slot1_encode, Opcode_addi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addi_Slot_ae8_slot0_encode, Opcode_addi_Slot_ae8_slot1_encode, 0, Opcode_addi_Slot_ae9_slot0_encode, Opcode_addi_Slot_ae9_slot1_encode, 0, 0, Opcode_addi_Slot_ae10_slot0_encode, Opcode_addi_Slot_ae10_slot1_encode, 0, 0, Opcode_addi_Slot_ae4_slot0_encode, Opcode_addi_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0, Opcode_addmi_Slot_ae_slot0_encode, Opcode_addmi_Slot_ae_slot1_encode, 0, 0, Opcode_addmi_Slot_ae2_slot0_encode, Opcode_addmi_Slot_ae2_slot1_encode, 0, Opcode_addmi_Slot_ae3_slot0_encode, Opcode_addmi_Slot_ae3_slot1_encode, Opcode_addmi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addmi_Slot_ae8_slot0_encode, Opcode_addmi_Slot_ae8_slot1_encode, 0, Opcode_addmi_Slot_ae9_slot0_encode, Opcode_addmi_Slot_ae9_slot1_encode, 0, 0, Opcode_addmi_Slot_ae10_slot0_encode, Opcode_addmi_Slot_ae10_slot1_encode, 0, 0, Opcode_addmi_Slot_ae4_slot0_encode, Opcode_addmi_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0, Opcode_add_Slot_ae_slot0_encode, Opcode_add_Slot_ae_slot1_encode, 0, 0, Opcode_add_Slot_ae2_slot0_encode, Opcode_add_Slot_ae2_slot1_encode, 0, Opcode_add_Slot_ae3_slot0_encode, Opcode_add_Slot_ae3_slot1_encode, Opcode_add_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_Slot_ae8_slot0_encode, Opcode_add_Slot_ae8_slot1_encode, 0, Opcode_add_Slot_ae9_slot0_encode, Opcode_add_Slot_ae9_slot1_encode, 0, 0, Opcode_add_Slot_ae10_slot0_encode, Opcode_add_Slot_ae10_slot1_encode, 0, 0, Opcode_add_Slot_ae4_slot0_encode, Opcode_add_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0, Opcode_addx2_Slot_ae_slot0_encode, Opcode_addx2_Slot_ae_slot1_encode, 0, 0, Opcode_addx2_Slot_ae2_slot0_encode, Opcode_addx2_Slot_ae2_slot1_encode, 0, Opcode_addx2_Slot_ae3_slot0_encode, Opcode_addx2_Slot_ae3_slot1_encode, Opcode_addx2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addx2_Slot_ae8_slot0_encode, Opcode_addx2_Slot_ae8_slot1_encode, 0, Opcode_addx2_Slot_ae9_slot0_encode, Opcode_addx2_Slot_ae9_slot1_encode, 0, 0, Opcode_addx2_Slot_ae10_slot0_encode, Opcode_addx2_Slot_ae10_slot1_encode, 0, 0, Opcode_addx2_Slot_ae4_slot0_encode, Opcode_addx2_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0, Opcode_addx4_Slot_ae_slot0_encode, Opcode_addx4_Slot_ae_slot1_encode, 0, 0, Opcode_addx4_Slot_ae2_slot0_encode, Opcode_addx4_Slot_ae2_slot1_encode, 0, Opcode_addx4_Slot_ae3_slot0_encode, Opcode_addx4_Slot_ae3_slot1_encode, Opcode_addx4_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addx4_Slot_ae8_slot0_encode, Opcode_addx4_Slot_ae8_slot1_encode, 0, Opcode_addx4_Slot_ae9_slot0_encode, Opcode_addx4_Slot_ae9_slot1_encode, 0, 0, Opcode_addx4_Slot_ae10_slot0_encode, Opcode_addx4_Slot_ae10_slot1_encode, 0, 0, Opcode_addx4_Slot_ae4_slot0_encode, Opcode_addx4_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0, Opcode_addx8_Slot_ae_slot0_encode, Opcode_addx8_Slot_ae_slot1_encode, 0, 0, Opcode_addx8_Slot_ae2_slot0_encode, Opcode_addx8_Slot_ae2_slot1_encode, 0, Opcode_addx8_Slot_ae3_slot0_encode, Opcode_addx8_Slot_ae3_slot1_encode, Opcode_addx8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addx8_Slot_ae8_slot0_encode, Opcode_addx8_Slot_ae8_slot1_encode, 0, Opcode_addx8_Slot_ae9_slot0_encode, Opcode_addx8_Slot_ae9_slot1_encode, 0, 0, Opcode_addx8_Slot_ae10_slot0_encode, Opcode_addx8_Slot_ae10_slot1_encode, 0, 0, Opcode_addx8_Slot_ae4_slot0_encode, Opcode_addx8_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0, Opcode_sub_Slot_ae_slot0_encode, Opcode_sub_Slot_ae_slot1_encode, 0, 0, Opcode_sub_Slot_ae2_slot0_encode, Opcode_sub_Slot_ae2_slot1_encode, 0, Opcode_sub_Slot_ae3_slot0_encode, Opcode_sub_Slot_ae3_slot1_encode, Opcode_sub_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_Slot_ae8_slot0_encode, Opcode_sub_Slot_ae8_slot1_encode, 0, Opcode_sub_Slot_ae9_slot0_encode, Opcode_sub_Slot_ae9_slot1_encode, 0, 0, Opcode_sub_Slot_ae10_slot0_encode, Opcode_sub_Slot_ae10_slot1_encode, 0, 0, Opcode_sub_Slot_ae4_slot0_encode, Opcode_sub_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0, Opcode_subx2_Slot_ae_slot0_encode, Opcode_subx2_Slot_ae_slot1_encode, 0, 0, Opcode_subx2_Slot_ae2_slot0_encode, Opcode_subx2_Slot_ae2_slot1_encode, 0, Opcode_subx2_Slot_ae3_slot0_encode, Opcode_subx2_Slot_ae3_slot1_encode, Opcode_subx2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_subx2_Slot_ae8_slot0_encode, Opcode_subx2_Slot_ae8_slot1_encode, 0, Opcode_subx2_Slot_ae9_slot0_encode, Opcode_subx2_Slot_ae9_slot1_encode, 0, 0, Opcode_subx2_Slot_ae10_slot0_encode, Opcode_subx2_Slot_ae10_slot1_encode, 0, 0, Opcode_subx2_Slot_ae4_slot0_encode, Opcode_subx2_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0, Opcode_subx4_Slot_ae_slot0_encode, Opcode_subx4_Slot_ae_slot1_encode, 0, 0, Opcode_subx4_Slot_ae2_slot0_encode, Opcode_subx4_Slot_ae2_slot1_encode, 0, Opcode_subx4_Slot_ae3_slot0_encode, Opcode_subx4_Slot_ae3_slot1_encode, Opcode_subx4_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_subx4_Slot_ae8_slot0_encode, Opcode_subx4_Slot_ae8_slot1_encode, 0, Opcode_subx4_Slot_ae9_slot0_encode, Opcode_subx4_Slot_ae9_slot1_encode, 0, 0, Opcode_subx4_Slot_ae10_slot0_encode, Opcode_subx4_Slot_ae10_slot1_encode, 0, 0, Opcode_subx4_Slot_ae4_slot0_encode, Opcode_subx4_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0, Opcode_subx8_Slot_ae_slot0_encode, Opcode_subx8_Slot_ae_slot1_encode, 0, 0, Opcode_subx8_Slot_ae2_slot0_encode, Opcode_subx8_Slot_ae2_slot1_encode, 0, Opcode_subx8_Slot_ae3_slot0_encode, Opcode_subx8_Slot_ae3_slot1_encode, Opcode_subx8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_subx8_Slot_ae8_slot0_encode, Opcode_subx8_Slot_ae8_slot1_encode, 0, Opcode_subx8_Slot_ae9_slot0_encode, Opcode_subx8_Slot_ae9_slot1_encode, 0, 0, Opcode_subx8_Slot_ae10_slot0_encode, Opcode_subx8_Slot_ae10_slot1_encode, 0, 0, Opcode_subx8_Slot_ae4_slot0_encode, Opcode_subx8_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0, Opcode_and_Slot_ae_slot0_encode, Opcode_and_Slot_ae_slot1_encode, 0, 0, Opcode_and_Slot_ae2_slot0_encode, Opcode_and_Slot_ae2_slot1_encode, 0, Opcode_and_Slot_ae3_slot0_encode, Opcode_and_Slot_ae3_slot1_encode, Opcode_and_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_and_Slot_ae8_slot0_encode, Opcode_and_Slot_ae8_slot1_encode, 0, Opcode_and_Slot_ae9_slot0_encode, Opcode_and_Slot_ae9_slot1_encode, 0, 0, Opcode_and_Slot_ae10_slot0_encode, Opcode_and_Slot_ae10_slot1_encode, 0, 0, Opcode_and_Slot_ae4_slot0_encode, Opcode_and_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0, Opcode_or_Slot_ae_slot0_encode, Opcode_or_Slot_ae_slot1_encode, 0, 0, Opcode_or_Slot_ae2_slot0_encode, Opcode_or_Slot_ae2_slot1_encode, 0, Opcode_or_Slot_ae3_slot0_encode, Opcode_or_Slot_ae3_slot1_encode, Opcode_or_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_or_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_or_Slot_ae8_slot0_encode, Opcode_or_Slot_ae8_slot1_encode, 0, Opcode_or_Slot_ae9_slot0_encode, Opcode_or_Slot_ae9_slot1_encode, 0, 0, Opcode_or_Slot_ae10_slot0_encode, Opcode_or_Slot_ae10_slot1_encode, 0, 0, Opcode_or_Slot_ae4_slot0_encode, Opcode_or_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0, Opcode_xor_Slot_ae_slot0_encode, Opcode_xor_Slot_ae_slot1_encode, 0, 0, Opcode_xor_Slot_ae2_slot0_encode, Opcode_xor_Slot_ae2_slot1_encode, 0, Opcode_xor_Slot_ae3_slot0_encode, Opcode_xor_Slot_ae3_slot1_encode, Opcode_xor_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_xor_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_xor_Slot_ae8_slot0_encode, Opcode_xor_Slot_ae8_slot1_encode, 0, Opcode_xor_Slot_ae9_slot0_encode, Opcode_xor_Slot_ae9_slot1_encode, 0, 0, Opcode_xor_Slot_ae10_slot0_encode, Opcode_xor_Slot_ae10_slot1_encode, 0, 0, Opcode_xor_Slot_ae4_slot0_encode, Opcode_xor_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0, Opcode_call0_Slot_ae_slot0_encode, 0, 0, 0, Opcode_call0_Slot_ae2_slot0_encode, 0, 0, Opcode_call0_Slot_ae3_slot0_encode, 0, Opcode_call0_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_call0_Slot_ae8_slot0_encode, 0, 0, Opcode_call0_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_call0_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_call0_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0, Opcode_callx0_Slot_ae_slot0_encode, 0, 0, 0, Opcode_callx0_Slot_ae2_slot0_encode, 0, 0, Opcode_callx0_Slot_ae3_slot0_encode, 0, Opcode_callx0_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_callx0_Slot_ae8_slot0_encode, 0, 0, Opcode_callx0_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_callx0_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_callx0_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0, Opcode_extui_Slot_ae_slot0_encode, Opcode_extui_Slot_ae_slot1_encode, 0, 0, Opcode_extui_Slot_ae2_slot0_encode, Opcode_extui_Slot_ae2_slot1_encode, 0, Opcode_extui_Slot_ae3_slot0_encode, Opcode_extui_Slot_ae3_slot1_encode, Opcode_extui_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_extui_Slot_ae8_slot0_encode, Opcode_extui_Slot_ae8_slot1_encode, 0, Opcode_extui_Slot_ae9_slot0_encode, Opcode_extui_Slot_ae9_slot1_encode, 0, 0, Opcode_extui_Slot_ae10_slot0_encode, Opcode_extui_Slot_ae10_slot1_encode, 0, 0, Opcode_extui_Slot_ae4_slot0_encode, Opcode_extui_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0, Opcode_j_Slot_ae_slot0_encode, 0, 0, 0, Opcode_j_Slot_ae2_slot0_encode, 0, 0, Opcode_j_Slot_ae3_slot0_encode, 0, Opcode_j_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_j_Slot_ae8_slot0_encode, 0, 0, Opcode_j_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_j_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_j_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0, Opcode_jx_Slot_ae_slot0_encode, 0, 0, 0, Opcode_jx_Slot_ae2_slot0_encode, 0, 0, Opcode_jx_Slot_ae3_slot0_encode, 0, Opcode_jx_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_jx_Slot_ae8_slot0_encode, 0, 0, Opcode_jx_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_jx_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_jx_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode, Opcode_l16ui_Slot_ae_slot1_encode, 0, 0, Opcode_l16ui_Slot_ae2_slot0_encode, Opcode_l16ui_Slot_ae2_slot1_encode, 0, Opcode_l16ui_Slot_ae3_slot0_encode, Opcode_l16ui_Slot_ae3_slot1_encode, Opcode_l16ui_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l16ui_Slot_ae8_slot0_encode, Opcode_l16ui_Slot_ae8_slot1_encode, 0, Opcode_l16ui_Slot_ae9_slot0_encode, Opcode_l16ui_Slot_ae9_slot1_encode, 0, 0, Opcode_l16ui_Slot_ae10_slot0_encode, Opcode_l16ui_Slot_ae10_slot1_encode, 0, 0, Opcode_l16ui_Slot_ae4_slot0_encode, Opcode_l16ui_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0, Opcode_l16si_Slot_ae_slot0_encode, Opcode_l16si_Slot_ae_slot1_encode, 0, 0, Opcode_l16si_Slot_ae2_slot0_encode, Opcode_l16si_Slot_ae2_slot1_encode, 0, Opcode_l16si_Slot_ae3_slot0_encode, Opcode_l16si_Slot_ae3_slot1_encode, Opcode_l16si_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l16si_Slot_ae8_slot0_encode, Opcode_l16si_Slot_ae8_slot1_encode, 0, Opcode_l16si_Slot_ae9_slot0_encode, Opcode_l16si_Slot_ae9_slot1_encode, 0, 0, Opcode_l16si_Slot_ae10_slot0_encode, Opcode_l16si_Slot_ae10_slot1_encode, 0, 0, Opcode_l16si_Slot_ae4_slot0_encode, Opcode_l16si_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0, Opcode_l32i_Slot_ae_slot0_encode, Opcode_l32i_Slot_ae_slot1_encode, 0, 0, Opcode_l32i_Slot_ae2_slot0_encode, Opcode_l32i_Slot_ae2_slot1_encode, 0, Opcode_l32i_Slot_ae3_slot0_encode, Opcode_l32i_Slot_ae3_slot1_encode, Opcode_l32i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l32i_Slot_ae8_slot0_encode, Opcode_l32i_Slot_ae8_slot1_encode, 0, Opcode_l32i_Slot_ae9_slot0_encode, Opcode_l32i_Slot_ae9_slot1_encode, 0, 0, Opcode_l32i_Slot_ae10_slot0_encode, Opcode_l32i_Slot_ae10_slot1_encode, 0, 0, Opcode_l32i_Slot_ae4_slot0_encode, Opcode_l32i_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0, Opcode_l32r_Slot_ae_slot0_encode, 0, 0, 0, Opcode_l32r_Slot_ae2_slot0_encode, 0, 0, Opcode_l32r_Slot_ae3_slot0_encode, 0, Opcode_l32r_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l32r_Slot_ae8_slot0_encode, 0, 0, Opcode_l32r_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_l32r_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_l32r_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode, Opcode_l8ui_Slot_ae_slot1_encode, 0, 0, Opcode_l8ui_Slot_ae2_slot0_encode, Opcode_l8ui_Slot_ae2_slot1_encode, 0, Opcode_l8ui_Slot_ae3_slot0_encode, Opcode_l8ui_Slot_ae3_slot1_encode, Opcode_l8ui_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l8ui_Slot_ae8_slot0_encode, Opcode_l8ui_Slot_ae8_slot1_encode, 0, Opcode_l8ui_Slot_ae9_slot0_encode, Opcode_l8ui_Slot_ae9_slot1_encode, 0, 0, Opcode_l8ui_Slot_ae10_slot0_encode, Opcode_l8ui_Slot_ae10_slot1_encode, 0, 0, Opcode_l8ui_Slot_ae4_slot0_encode, Opcode_l8ui_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { + Opcode_loop_Slot_inst_encode, 0, 0, Opcode_loop_Slot_ae_slot0_encode, 0, 0, 0, Opcode_loop_Slot_ae2_slot0_encode, 0, 0, Opcode_loop_Slot_ae3_slot0_encode, 0, Opcode_loop_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_loop_Slot_ae8_slot0_encode, 0, 0, Opcode_loop_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_loop_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_loop_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { + Opcode_loopgtz_Slot_inst_encode, 0, 0, Opcode_loopgtz_Slot_ae_slot0_encode, 0, 0, 0, Opcode_loopgtz_Slot_ae2_slot0_encode, 0, 0, Opcode_loopgtz_Slot_ae3_slot0_encode, 0, Opcode_loopgtz_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_loopgtz_Slot_ae8_slot0_encode, 0, 0, Opcode_loopgtz_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_loopgtz_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_loopgtz_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { + Opcode_loopnez_Slot_inst_encode, 0, 0, Opcode_loopnez_Slot_ae_slot0_encode, 0, 0, 0, Opcode_loopnez_Slot_ae2_slot0_encode, 0, 0, Opcode_loopnez_Slot_ae3_slot0_encode, 0, Opcode_loopnez_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_loopnez_Slot_ae8_slot0_encode, 0, 0, Opcode_loopnez_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_loopnez_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_loopnez_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0, Opcode_movi_Slot_ae_slot0_encode, Opcode_movi_Slot_ae_slot1_encode, 0, 0, Opcode_movi_Slot_ae2_slot0_encode, Opcode_movi_Slot_ae2_slot1_encode, 0, Opcode_movi_Slot_ae3_slot0_encode, Opcode_movi_Slot_ae3_slot1_encode, Opcode_movi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movi_Slot_ae8_slot0_encode, Opcode_movi_Slot_ae8_slot1_encode, 0, Opcode_movi_Slot_ae9_slot0_encode, Opcode_movi_Slot_ae9_slot1_encode, 0, 0, Opcode_movi_Slot_ae10_slot0_encode, Opcode_movi_Slot_ae10_slot1_encode, 0, 0, Opcode_movi_Slot_ae4_slot0_encode, Opcode_movi_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode, Opcode_moveqz_Slot_ae_slot1_encode, 0, 0, Opcode_moveqz_Slot_ae2_slot0_encode, Opcode_moveqz_Slot_ae2_slot1_encode, 0, Opcode_moveqz_Slot_ae3_slot0_encode, Opcode_moveqz_Slot_ae3_slot1_encode, Opcode_moveqz_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_moveqz_Slot_ae8_slot0_encode, Opcode_moveqz_Slot_ae8_slot1_encode, 0, Opcode_moveqz_Slot_ae9_slot0_encode, Opcode_moveqz_Slot_ae9_slot1_encode, 0, 0, Opcode_moveqz_Slot_ae10_slot0_encode, Opcode_moveqz_Slot_ae10_slot1_encode, 0, 0, Opcode_moveqz_Slot_ae4_slot0_encode, Opcode_moveqz_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0, Opcode_movgez_Slot_ae_slot0_encode, Opcode_movgez_Slot_ae_slot1_encode, 0, 0, Opcode_movgez_Slot_ae2_slot0_encode, Opcode_movgez_Slot_ae2_slot1_encode, 0, Opcode_movgez_Slot_ae3_slot0_encode, Opcode_movgez_Slot_ae3_slot1_encode, Opcode_movgez_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movgez_Slot_ae8_slot0_encode, Opcode_movgez_Slot_ae8_slot1_encode, 0, Opcode_movgez_Slot_ae9_slot0_encode, Opcode_movgez_Slot_ae9_slot1_encode, 0, 0, Opcode_movgez_Slot_ae10_slot0_encode, Opcode_movgez_Slot_ae10_slot1_encode, 0, 0, Opcode_movgez_Slot_ae4_slot0_encode, Opcode_movgez_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0, Opcode_movltz_Slot_ae_slot0_encode, Opcode_movltz_Slot_ae_slot1_encode, 0, 0, Opcode_movltz_Slot_ae2_slot0_encode, Opcode_movltz_Slot_ae2_slot1_encode, 0, Opcode_movltz_Slot_ae3_slot0_encode, Opcode_movltz_Slot_ae3_slot1_encode, Opcode_movltz_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movltz_Slot_ae8_slot0_encode, Opcode_movltz_Slot_ae8_slot1_encode, 0, Opcode_movltz_Slot_ae9_slot0_encode, Opcode_movltz_Slot_ae9_slot1_encode, 0, 0, Opcode_movltz_Slot_ae10_slot0_encode, Opcode_movltz_Slot_ae10_slot1_encode, 0, 0, Opcode_movltz_Slot_ae4_slot0_encode, Opcode_movltz_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0, Opcode_movnez_Slot_ae_slot0_encode, Opcode_movnez_Slot_ae_slot1_encode, 0, 0, Opcode_movnez_Slot_ae2_slot0_encode, Opcode_movnez_Slot_ae2_slot1_encode, 0, Opcode_movnez_Slot_ae3_slot0_encode, Opcode_movnez_Slot_ae3_slot1_encode, Opcode_movnez_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movnez_Slot_ae8_slot0_encode, Opcode_movnez_Slot_ae8_slot1_encode, 0, Opcode_movnez_Slot_ae9_slot0_encode, Opcode_movnez_Slot_ae9_slot1_encode, 0, 0, Opcode_movnez_Slot_ae10_slot0_encode, Opcode_movnez_Slot_ae10_slot1_encode, 0, 0, Opcode_movnez_Slot_ae4_slot0_encode, Opcode_movnez_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0, Opcode_abs_Slot_ae_slot0_encode, Opcode_abs_Slot_ae_slot1_encode, 0, 0, Opcode_abs_Slot_ae2_slot0_encode, Opcode_abs_Slot_ae2_slot1_encode, 0, Opcode_abs_Slot_ae3_slot0_encode, Opcode_abs_Slot_ae3_slot1_encode, Opcode_abs_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_abs_Slot_ae8_slot0_encode, Opcode_abs_Slot_ae8_slot1_encode, 0, Opcode_abs_Slot_ae9_slot0_encode, Opcode_abs_Slot_ae9_slot1_encode, 0, 0, Opcode_abs_Slot_ae10_slot0_encode, Opcode_abs_Slot_ae10_slot1_encode, 0, 0, Opcode_abs_Slot_ae4_slot0_encode, Opcode_abs_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0, Opcode_neg_Slot_ae_slot0_encode, Opcode_neg_Slot_ae_slot1_encode, 0, 0, Opcode_neg_Slot_ae2_slot0_encode, Opcode_neg_Slot_ae2_slot1_encode, 0, Opcode_neg_Slot_ae3_slot0_encode, Opcode_neg_Slot_ae3_slot1_encode, Opcode_neg_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_neg_Slot_ae8_slot0_encode, Opcode_neg_Slot_ae8_slot1_encode, 0, Opcode_neg_Slot_ae9_slot0_encode, Opcode_neg_Slot_ae9_slot1_encode, 0, 0, Opcode_neg_Slot_ae10_slot0_encode, Opcode_neg_Slot_ae10_slot1_encode, 0, 0, Opcode_neg_Slot_ae4_slot0_encode, Opcode_neg_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot0_encode, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot2_encode, Opcode_nop_Slot_ae_slot3_encode, Opcode_nop_Slot_ae2_slot0_encode, Opcode_nop_Slot_ae2_slot1_encode, Opcode_nop_Slot_ae2_slot2_encode, Opcode_nop_Slot_ae3_slot0_encode, Opcode_nop_Slot_ae3_slot1_encode, Opcode_nop_Slot_ae5_slot0_encode, Opcode_nop_Slot_ae5_slot1_encode, Opcode_nop_Slot_ae5_slot2_encode, Opcode_nop_Slot_ae6_slot0_encode, Opcode_nop_Slot_ae6_slot1_encode, Opcode_nop_Slot_ae6_slot2_encode, Opcode_nop_Slot_ae6_slot3_encode, Opcode_nop_Slot_ae7_slot0_encode, Opcode_nop_Slot_ae7_slot1_encode, Opcode_nop_Slot_ae7_slot2_encode, Opcode_nop_Slot_ae7_slot3_encode, Opcode_nop_Slot_ae8_slot0_encode, Opcode_nop_Slot_ae8_slot1_encode, Opcode_nop_Slot_ae8_slot2_encode, Opcode_nop_Slot_ae9_slot0_encode, Opcode_nop_Slot_ae9_slot1_encode, Opcode_nop_Slot_ae9_slot2_encode, Opcode_nop_Slot_ae9_slot3_encode, Opcode_nop_Slot_ae10_slot0_encode, Opcode_nop_Slot_ae10_slot1_encode, Opcode_nop_Slot_ae10_slot2_encode, Opcode_nop_Slot_ae10_slot3_encode, Opcode_nop_Slot_ae4_slot0_encode, Opcode_nop_Slot_ae4_slot1_encode, Opcode_nop_Slot_ae4_slot2_encode, Opcode_nop_Slot_ae4_slot3_encode, Opcode_nop_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32ex_encode_fns[] = { + Opcode_l32ex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32ex_encode_fns[] = { + Opcode_s32ex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_getex_encode_fns[] = { + Opcode_getex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clrex_encode_fns[] = { + Opcode_clrex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0, Opcode_ret_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ret_Slot_ae2_slot0_encode, 0, 0, Opcode_ret_Slot_ae3_slot0_encode, 0, Opcode_ret_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ret_Slot_ae8_slot0_encode, 0, 0, Opcode_ret_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_ret_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_ret_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0, Opcode_s16i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_s16i_Slot_ae2_slot0_encode, 0, 0, Opcode_s16i_Slot_ae3_slot0_encode, 0, Opcode_s16i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s16i_Slot_ae8_slot0_encode, 0, 0, Opcode_s16i_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_s16i_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_s16i_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0, Opcode_s32i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_s32i_Slot_ae2_slot0_encode, 0, 0, Opcode_s32i_Slot_ae3_slot0_encode, 0, Opcode_s32i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s32i_Slot_ae8_slot0_encode, 0, 0, Opcode_s32i_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_s32i_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_s32i_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = { + Opcode_s32nb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0, Opcode_s8i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_s8i_Slot_ae2_slot0_encode, 0, 0, Opcode_s8i_Slot_ae3_slot0_encode, 0, Opcode_s8i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s8i_Slot_ae8_slot0_encode, 0, 0, Opcode_s8i_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_s8i_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_s8i_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode, Opcode_ssa8b_Slot_ae_slot1_encode, 0, 0, Opcode_ssa8b_Slot_ae2_slot0_encode, Opcode_ssa8b_Slot_ae2_slot1_encode, 0, Opcode_ssa8b_Slot_ae3_slot0_encode, Opcode_ssa8b_Slot_ae3_slot1_encode, Opcode_ssa8b_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssa8b_Slot_ae8_slot0_encode, Opcode_ssa8b_Slot_ae8_slot1_encode, 0, Opcode_ssa8b_Slot_ae9_slot0_encode, Opcode_ssa8b_Slot_ae9_slot1_encode, 0, 0, Opcode_ssa8b_Slot_ae10_slot0_encode, Opcode_ssa8b_Slot_ae10_slot1_encode, 0, 0, Opcode_ssa8b_Slot_ae4_slot0_encode, Opcode_ssa8b_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode, Opcode_ssa8l_Slot_ae_slot1_encode, 0, 0, Opcode_ssa8l_Slot_ae2_slot0_encode, Opcode_ssa8l_Slot_ae2_slot1_encode, 0, Opcode_ssa8l_Slot_ae3_slot0_encode, Opcode_ssa8l_Slot_ae3_slot1_encode, Opcode_ssa8l_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssa8l_Slot_ae8_slot0_encode, Opcode_ssa8l_Slot_ae8_slot1_encode, 0, Opcode_ssa8l_Slot_ae9_slot0_encode, Opcode_ssa8l_Slot_ae9_slot1_encode, 0, 0, Opcode_ssa8l_Slot_ae10_slot0_encode, Opcode_ssa8l_Slot_ae10_slot1_encode, 0, 0, Opcode_ssa8l_Slot_ae4_slot0_encode, Opcode_ssa8l_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0, Opcode_ssl_Slot_ae_slot0_encode, Opcode_ssl_Slot_ae_slot1_encode, 0, 0, Opcode_ssl_Slot_ae2_slot0_encode, Opcode_ssl_Slot_ae2_slot1_encode, 0, Opcode_ssl_Slot_ae3_slot0_encode, Opcode_ssl_Slot_ae3_slot1_encode, Opcode_ssl_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssl_Slot_ae8_slot0_encode, Opcode_ssl_Slot_ae8_slot1_encode, 0, Opcode_ssl_Slot_ae9_slot0_encode, Opcode_ssl_Slot_ae9_slot1_encode, 0, 0, Opcode_ssl_Slot_ae10_slot0_encode, Opcode_ssl_Slot_ae10_slot1_encode, 0, 0, Opcode_ssl_Slot_ae4_slot0_encode, Opcode_ssl_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0, Opcode_ssr_Slot_ae_slot0_encode, Opcode_ssr_Slot_ae_slot1_encode, 0, 0, Opcode_ssr_Slot_ae2_slot0_encode, Opcode_ssr_Slot_ae2_slot1_encode, 0, Opcode_ssr_Slot_ae3_slot0_encode, Opcode_ssr_Slot_ae3_slot1_encode, Opcode_ssr_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssr_Slot_ae8_slot0_encode, Opcode_ssr_Slot_ae8_slot1_encode, 0, Opcode_ssr_Slot_ae9_slot0_encode, Opcode_ssr_Slot_ae9_slot1_encode, 0, 0, Opcode_ssr_Slot_ae10_slot0_encode, Opcode_ssr_Slot_ae10_slot1_encode, 0, 0, Opcode_ssr_Slot_ae4_slot0_encode, Opcode_ssr_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0, Opcode_ssai_Slot_ae_slot0_encode, Opcode_ssai_Slot_ae_slot1_encode, 0, 0, Opcode_ssai_Slot_ae2_slot0_encode, Opcode_ssai_Slot_ae2_slot1_encode, 0, Opcode_ssai_Slot_ae3_slot0_encode, Opcode_ssai_Slot_ae3_slot1_encode, Opcode_ssai_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssai_Slot_ae8_slot0_encode, Opcode_ssai_Slot_ae8_slot1_encode, 0, Opcode_ssai_Slot_ae9_slot0_encode, Opcode_ssai_Slot_ae9_slot1_encode, 0, 0, Opcode_ssai_Slot_ae10_slot0_encode, Opcode_ssai_Slot_ae10_slot1_encode, 0, 0, Opcode_ssai_Slot_ae4_slot0_encode, Opcode_ssai_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0, Opcode_sll_Slot_ae_slot0_encode, Opcode_sll_Slot_ae_slot1_encode, 0, 0, Opcode_sll_Slot_ae2_slot0_encode, Opcode_sll_Slot_ae2_slot1_encode, 0, Opcode_sll_Slot_ae3_slot0_encode, Opcode_sll_Slot_ae3_slot1_encode, Opcode_sll_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sll_Slot_ae8_slot0_encode, Opcode_sll_Slot_ae8_slot1_encode, 0, Opcode_sll_Slot_ae9_slot0_encode, Opcode_sll_Slot_ae9_slot1_encode, 0, 0, Opcode_sll_Slot_ae10_slot0_encode, Opcode_sll_Slot_ae10_slot1_encode, 0, 0, Opcode_sll_Slot_ae4_slot0_encode, Opcode_sll_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0, Opcode_src_Slot_ae_slot0_encode, Opcode_src_Slot_ae_slot1_encode, 0, 0, Opcode_src_Slot_ae2_slot0_encode, Opcode_src_Slot_ae2_slot1_encode, 0, Opcode_src_Slot_ae3_slot0_encode, Opcode_src_Slot_ae3_slot1_encode, Opcode_src_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_src_Slot_ae8_slot0_encode, Opcode_src_Slot_ae8_slot1_encode, 0, Opcode_src_Slot_ae9_slot0_encode, Opcode_src_Slot_ae9_slot1_encode, 0, 0, Opcode_src_Slot_ae10_slot0_encode, Opcode_src_Slot_ae10_slot1_encode, 0, 0, Opcode_src_Slot_ae4_slot0_encode, Opcode_src_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0, Opcode_sra_Slot_ae_slot0_encode, Opcode_sra_Slot_ae_slot1_encode, 0, 0, Opcode_sra_Slot_ae2_slot0_encode, Opcode_sra_Slot_ae2_slot1_encode, 0, Opcode_sra_Slot_ae3_slot0_encode, Opcode_sra_Slot_ae3_slot1_encode, Opcode_sra_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sra_Slot_ae8_slot0_encode, Opcode_sra_Slot_ae8_slot1_encode, 0, Opcode_sra_Slot_ae9_slot0_encode, Opcode_sra_Slot_ae9_slot1_encode, 0, 0, Opcode_sra_Slot_ae10_slot0_encode, Opcode_sra_Slot_ae10_slot1_encode, 0, 0, Opcode_sra_Slot_ae4_slot0_encode, Opcode_sra_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0, Opcode_srl_Slot_ae_slot0_encode, Opcode_srl_Slot_ae_slot1_encode, 0, 0, Opcode_srl_Slot_ae2_slot0_encode, Opcode_srl_Slot_ae2_slot1_encode, 0, Opcode_srl_Slot_ae3_slot0_encode, Opcode_srl_Slot_ae3_slot1_encode, Opcode_srl_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_srl_Slot_ae8_slot0_encode, Opcode_srl_Slot_ae8_slot1_encode, 0, Opcode_srl_Slot_ae9_slot0_encode, Opcode_srl_Slot_ae9_slot1_encode, 0, 0, Opcode_srl_Slot_ae10_slot0_encode, Opcode_srl_Slot_ae10_slot1_encode, 0, 0, Opcode_srl_Slot_ae4_slot0_encode, Opcode_srl_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0, Opcode_slli_Slot_ae_slot0_encode, Opcode_slli_Slot_ae_slot1_encode, 0, 0, Opcode_slli_Slot_ae2_slot0_encode, Opcode_slli_Slot_ae2_slot1_encode, 0, Opcode_slli_Slot_ae3_slot0_encode, Opcode_slli_Slot_ae3_slot1_encode, Opcode_slli_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_slli_Slot_ae8_slot0_encode, Opcode_slli_Slot_ae8_slot1_encode, 0, Opcode_slli_Slot_ae9_slot0_encode, Opcode_slli_Slot_ae9_slot1_encode, 0, 0, Opcode_slli_Slot_ae10_slot0_encode, Opcode_slli_Slot_ae10_slot1_encode, 0, 0, Opcode_slli_Slot_ae4_slot0_encode, Opcode_slli_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0, Opcode_srai_Slot_ae_slot0_encode, Opcode_srai_Slot_ae_slot1_encode, 0, 0, Opcode_srai_Slot_ae2_slot0_encode, Opcode_srai_Slot_ae2_slot1_encode, 0, Opcode_srai_Slot_ae3_slot0_encode, Opcode_srai_Slot_ae3_slot1_encode, Opcode_srai_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_srai_Slot_ae8_slot0_encode, Opcode_srai_Slot_ae8_slot1_encode, 0, Opcode_srai_Slot_ae9_slot0_encode, Opcode_srai_Slot_ae9_slot1_encode, 0, 0, Opcode_srai_Slot_ae10_slot0_encode, Opcode_srai_Slot_ae10_slot1_encode, 0, 0, Opcode_srai_Slot_ae4_slot0_encode, Opcode_srai_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0, Opcode_srli_Slot_ae_slot0_encode, Opcode_srli_Slot_ae_slot1_encode, 0, 0, Opcode_srli_Slot_ae2_slot0_encode, Opcode_srli_Slot_ae2_slot1_encode, 0, Opcode_srli_Slot_ae3_slot0_encode, Opcode_srli_Slot_ae3_slot1_encode, Opcode_srli_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_srli_Slot_ae8_slot0_encode, Opcode_srli_Slot_ae8_slot1_encode, 0, Opcode_srli_Slot_ae9_slot0_encode, Opcode_srli_Slot_ae9_slot1_encode, 0, 0, Opcode_srli_Slot_ae10_slot0_encode, Opcode_srli_Slot_ae10_slot1_encode, 0, 0, Opcode_srli_Slot_ae4_slot0_encode, Opcode_srli_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { + Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { + Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { + Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { + Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { + Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { + Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = { + Opcode_rsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = { + Opcode_wsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = { + Opcode_xsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { + Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { + Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { + Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { + Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { + Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { + Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { + Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { + Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { + Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { + Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { + Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { + Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { + Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { + Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { + Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { + Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { + Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { + Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { + Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { + Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { + Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { + Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { + Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { + Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { + Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { + Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { + Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { + Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { + Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { + Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { + Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { + Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { + Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { + Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { + Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { + Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { + Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { + Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { + Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc2_encode_fns[] = { + Opcode_rsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc2_encode_fns[] = { + Opcode_wsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc2_encode_fns[] = { + Opcode_xsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc3_encode_fns[] = { + Opcode_rsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc3_encode_fns[] = { + Opcode_wsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc3_encode_fns[] = { + Opcode_xsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_mpucfg_encode_fns[] = { + Opcode_rsr_mpucfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mpucfg_encode_fns[] = { + Opcode_wsr_mpucfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_salt_encode_fns[] = { + Opcode_salt_Slot_inst_encode, 0, 0, Opcode_salt_Slot_ae_slot0_encode, Opcode_salt_Slot_ae_slot1_encode, 0, 0, Opcode_salt_Slot_ae2_slot0_encode, Opcode_salt_Slot_ae2_slot1_encode, 0, Opcode_salt_Slot_ae3_slot0_encode, Opcode_salt_Slot_ae3_slot1_encode, Opcode_salt_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_salt_Slot_ae8_slot0_encode, Opcode_salt_Slot_ae8_slot1_encode, 0, Opcode_salt_Slot_ae9_slot0_encode, Opcode_salt_Slot_ae9_slot1_encode, 0, 0, Opcode_salt_Slot_ae10_slot0_encode, Opcode_salt_Slot_ae10_slot1_encode, 0, 0, Opcode_salt_Slot_ae4_slot0_encode, Opcode_salt_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_saltu_encode_fns[] = { + Opcode_saltu_Slot_inst_encode, 0, 0, Opcode_saltu_Slot_ae_slot0_encode, Opcode_saltu_Slot_ae_slot1_encode, 0, 0, Opcode_saltu_Slot_ae2_slot0_encode, Opcode_saltu_Slot_ae2_slot1_encode, 0, Opcode_saltu_Slot_ae3_slot0_encode, Opcode_saltu_Slot_ae3_slot1_encode, Opcode_saltu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_saltu_Slot_ae8_slot0_encode, Opcode_saltu_Slot_ae8_slot1_encode, 0, Opcode_saltu_Slot_ae9_slot0_encode, Opcode_saltu_Slot_ae9_slot1_encode, 0, 0, Opcode_saltu_Slot_ae10_slot0_encode, Opcode_saltu_Slot_ae10_slot1_encode, 0, 0, Opcode_saltu_Slot_ae4_slot0_encode, Opcode_saltu_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_opmode_encode_fns[] = { + Opcode_rsr_opmode_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_opmode_encode_fns[] = { + Opcode_wsr_opmode_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_opmode_encode_fns[] = { + Opcode_xsr_opmode_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { + Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { + Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { + Opcode_mull_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = { + Opcode_lddr32_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = { + Opcode_sddr32_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { + Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { + Opcode_andb_Slot_inst_encode, 0, 0, Opcode_andb_Slot_ae_slot0_encode, 0, 0, 0, Opcode_andb_Slot_ae2_slot0_encode, 0, 0, Opcode_andb_Slot_ae3_slot0_encode, 0, Opcode_andb_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_andb_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_andb_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_andb_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { + Opcode_andbc_Slot_inst_encode, 0, 0, Opcode_andbc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_andbc_Slot_ae2_slot0_encode, 0, 0, Opcode_andbc_Slot_ae3_slot0_encode, 0, Opcode_andbc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_andbc_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_andbc_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_andbc_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { + Opcode_orb_Slot_inst_encode, 0, 0, Opcode_orb_Slot_ae_slot0_encode, 0, 0, 0, Opcode_orb_Slot_ae2_slot0_encode, 0, 0, Opcode_orb_Slot_ae3_slot0_encode, 0, Opcode_orb_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_orb_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_orb_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_orb_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { + Opcode_orbc_Slot_inst_encode, 0, 0, Opcode_orbc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_orbc_Slot_ae2_slot0_encode, 0, 0, Opcode_orbc_Slot_ae3_slot0_encode, 0, Opcode_orbc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_orbc_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_orbc_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_orbc_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { + Opcode_xorb_Slot_inst_encode, 0, 0, Opcode_xorb_Slot_ae_slot0_encode, 0, 0, 0, Opcode_xorb_Slot_ae2_slot0_encode, 0, 0, Opcode_xorb_Slot_ae3_slot0_encode, 0, Opcode_xorb_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_xorb_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_xorb_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_xorb_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { + Opcode_all4_Slot_inst_encode, 0, 0, Opcode_all4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_all4_Slot_ae2_slot0_encode, 0, 0, Opcode_all4_Slot_ae3_slot0_encode, 0, Opcode_all4_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_all4_Slot_ae8_slot0_encode, 0, 0, Opcode_all4_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_all4_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_all4_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { + Opcode_any4_Slot_inst_encode, 0, 0, Opcode_any4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_any4_Slot_ae2_slot0_encode, 0, 0, Opcode_any4_Slot_ae3_slot0_encode, 0, Opcode_any4_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_any4_Slot_ae8_slot0_encode, 0, 0, Opcode_any4_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_any4_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_any4_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { + Opcode_all8_Slot_inst_encode, 0, 0, Opcode_all8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_all8_Slot_ae2_slot0_encode, 0, 0, Opcode_all8_Slot_ae3_slot0_encode, 0, Opcode_all8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_all8_Slot_ae8_slot0_encode, 0, 0, Opcode_all8_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_all8_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_all8_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { + Opcode_any8_Slot_inst_encode, 0, 0, Opcode_any8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_any8_Slot_ae2_slot0_encode, 0, 0, Opcode_any8_Slot_ae3_slot0_encode, 0, Opcode_any8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_any8_Slot_ae8_slot0_encode, 0, 0, Opcode_any8_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_any8_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_any8_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { + Opcode_bf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { + Opcode_bt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { + Opcode_movf_Slot_inst_encode, 0, 0, Opcode_movf_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movf_Slot_ae2_slot0_encode, 0, 0, Opcode_movf_Slot_ae3_slot0_encode, 0, Opcode_movf_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movf_Slot_ae8_slot0_encode, 0, 0, Opcode_movf_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_movf_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_movf_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { + Opcode_movt_Slot_inst_encode, 0, 0, Opcode_movt_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movt_Slot_ae2_slot0_encode, 0, 0, Opcode_movt_Slot_ae3_slot0_encode, 0, Opcode_movt_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movt_Slot_ae8_slot0_encode, 0, 0, Opcode_movt_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_movt_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_movt_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { + Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { + Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { + Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { + Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { + Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { + Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { + Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { + Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { + Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { + Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { + Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { + Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { + Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { + Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { + Opcode_iii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { + Opcode_lict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { + Opcode_licw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { + Opcode_sict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { + Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { + Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { + Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = { + Opcode_diwbui_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { + Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { + Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { + Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { + Opcode_dii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { + Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { + Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { + Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { + Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfm_b_encode_fns[] = { + Opcode_dpfm_b_Slot_inst_encode, 0, 0, Opcode_dpfm_b_Slot_ae_slot0_encode, 0, 0, 0, Opcode_dpfm_b_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfm_bf_encode_fns[] = { + Opcode_dpfm_bf_Slot_inst_encode, 0, 0, Opcode_dpfm_bf_Slot_ae_slot0_encode, 0, 0, 0, Opcode_dpfm_bf_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_b_encode_fns[] = { + Opcode_dpfr_b_Slot_inst_encode, 0, 0, Opcode_dpfr_b_Slot_ae_slot0_encode, 0, 0, 0, Opcode_dpfr_b_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_bf_encode_fns[] = { + Opcode_dpfr_bf_Slot_inst_encode, 0, 0, Opcode_dpfr_bf_Slot_ae_slot0_encode, 0, 0, 0, Opcode_dpfr_bf_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_b_encode_fns[] = { + Opcode_dpfw_b_Slot_inst_encode, 0, 0, Opcode_dpfw_b_Slot_ae_slot0_encode, 0, 0, 0, Opcode_dpfw_b_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_bf_encode_fns[] = { + Opcode_dpfw_bf_Slot_inst_encode, 0, 0, Opcode_dpfw_bf_Slot_ae_slot0_encode, 0, 0, 0, Opcode_dpfw_bf_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pfnxt_f_encode_fns[] = { + Opcode_pfnxt_f_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhi_b_encode_fns[] = { + Opcode_dhi_b_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwbi_b_encode_fns[] = { + Opcode_dhwbi_b_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwb_b_encode_fns[] = { + Opcode_dhwb_b_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pfend_a_encode_fns[] = { + Opcode_pfend_a_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pfend_o_encode_fns[] = { + Opcode_pfend_o_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pfwait_a_encode_fns[] = { + Opcode_pfwait_a_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pfwait_r_encode_fns[] = { + Opcode_pfwait_r_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { + Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { + Opcode_diu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { + Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { + Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { + Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdcw_encode_fns[] = { + Opcode_sdcw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldcw_encode_fns[] = { + Opcode_ldcw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prefctl_encode_fns[] = { + Opcode_rsr_prefctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_prefctl_encode_fns[] = { + Opcode_wsr_prefctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_prefctl_encode_fns[] = { + Opcode_xsr_prefctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_cacheadrdis_encode_fns[] = { + Opcode_wsr_cacheadrdis_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_cacheadrdis_encode_fns[] = { + Opcode_rsr_cacheadrdis_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_cacheadrdis_encode_fns[] = { + Opcode_xsr_cacheadrdis_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rptlb0_encode_fns[] = { + Opcode_rptlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pptlb_encode_fns[] = { + Opcode_pptlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rptlb1_encode_fns[] = { + Opcode_rptlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wptlb_encode_fns[] = { + Opcode_wptlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_mpuenb_encode_fns[] = { + Opcode_rsr_mpuenb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mpuenb_encode_fns[] = { + Opcode_wsr_mpuenb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_mpuenb_encode_fns[] = { + Opcode_xsr_mpuenb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { + Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { + Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { + Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { + Opcode_clamps_Slot_inst_encode, 0, 0, Opcode_clamps_Slot_ae_slot0_encode, Opcode_clamps_Slot_ae_slot1_encode, 0, 0, Opcode_clamps_Slot_ae2_slot0_encode, Opcode_clamps_Slot_ae2_slot1_encode, 0, Opcode_clamps_Slot_ae3_slot0_encode, Opcode_clamps_Slot_ae3_slot1_encode, Opcode_clamps_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_clamps_Slot_ae8_slot0_encode, Opcode_clamps_Slot_ae8_slot1_encode, 0, Opcode_clamps_Slot_ae9_slot0_encode, Opcode_clamps_Slot_ae9_slot1_encode, 0, 0, Opcode_clamps_Slot_ae10_slot0_encode, Opcode_clamps_Slot_ae10_slot1_encode, 0, 0, Opcode_clamps_Slot_ae4_slot0_encode, Opcode_clamps_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { + Opcode_max_Slot_inst_encode, 0, 0, Opcode_max_Slot_ae_slot0_encode, Opcode_max_Slot_ae_slot1_encode, 0, 0, Opcode_max_Slot_ae2_slot0_encode, Opcode_max_Slot_ae2_slot1_encode, 0, Opcode_max_Slot_ae3_slot0_encode, Opcode_max_Slot_ae3_slot1_encode, Opcode_max_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_max_Slot_ae8_slot0_encode, Opcode_max_Slot_ae8_slot1_encode, 0, Opcode_max_Slot_ae9_slot0_encode, Opcode_max_Slot_ae9_slot1_encode, 0, 0, Opcode_max_Slot_ae10_slot0_encode, Opcode_max_Slot_ae10_slot1_encode, 0, 0, Opcode_max_Slot_ae4_slot0_encode, Opcode_max_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { + Opcode_maxu_Slot_inst_encode, 0, 0, Opcode_maxu_Slot_ae_slot0_encode, Opcode_maxu_Slot_ae_slot1_encode, 0, 0, Opcode_maxu_Slot_ae2_slot0_encode, Opcode_maxu_Slot_ae2_slot1_encode, 0, Opcode_maxu_Slot_ae3_slot0_encode, Opcode_maxu_Slot_ae3_slot1_encode, Opcode_maxu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maxu_Slot_ae8_slot0_encode, Opcode_maxu_Slot_ae8_slot1_encode, 0, Opcode_maxu_Slot_ae9_slot0_encode, Opcode_maxu_Slot_ae9_slot1_encode, 0, 0, Opcode_maxu_Slot_ae10_slot0_encode, Opcode_maxu_Slot_ae10_slot1_encode, 0, 0, Opcode_maxu_Slot_ae4_slot0_encode, Opcode_maxu_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { + Opcode_min_Slot_inst_encode, 0, 0, Opcode_min_Slot_ae_slot0_encode, Opcode_min_Slot_ae_slot1_encode, 0, 0, Opcode_min_Slot_ae2_slot0_encode, Opcode_min_Slot_ae2_slot1_encode, 0, Opcode_min_Slot_ae3_slot0_encode, Opcode_min_Slot_ae3_slot1_encode, Opcode_min_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_min_Slot_ae8_slot0_encode, Opcode_min_Slot_ae8_slot1_encode, 0, Opcode_min_Slot_ae9_slot0_encode, Opcode_min_Slot_ae9_slot1_encode, 0, 0, Opcode_min_Slot_ae10_slot0_encode, Opcode_min_Slot_ae10_slot1_encode, 0, 0, Opcode_min_Slot_ae4_slot0_encode, Opcode_min_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { + Opcode_minu_Slot_inst_encode, 0, 0, Opcode_minu_Slot_ae_slot0_encode, Opcode_minu_Slot_ae_slot1_encode, 0, 0, Opcode_minu_Slot_ae2_slot0_encode, Opcode_minu_Slot_ae2_slot1_encode, 0, Opcode_minu_Slot_ae3_slot0_encode, Opcode_minu_Slot_ae3_slot1_encode, Opcode_minu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_minu_Slot_ae8_slot0_encode, Opcode_minu_Slot_ae8_slot1_encode, 0, Opcode_minu_Slot_ae9_slot0_encode, Opcode_minu_Slot_ae9_slot1_encode, 0, 0, Opcode_minu_Slot_ae10_slot0_encode, Opcode_minu_Slot_ae10_slot1_encode, 0, 0, Opcode_minu_Slot_ae4_slot0_encode, Opcode_minu_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { + Opcode_sext_Slot_inst_encode, 0, 0, Opcode_sext_Slot_ae_slot0_encode, Opcode_sext_Slot_ae_slot1_encode, 0, 0, Opcode_sext_Slot_ae2_slot0_encode, Opcode_sext_Slot_ae2_slot1_encode, 0, Opcode_sext_Slot_ae3_slot0_encode, Opcode_sext_Slot_ae3_slot1_encode, Opcode_sext_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sext_Slot_ae8_slot0_encode, Opcode_sext_Slot_ae8_slot1_encode, 0, Opcode_sext_Slot_ae9_slot0_encode, Opcode_sext_Slot_ae9_slot1_encode, 0, 0, Opcode_sext_Slot_ae10_slot0_encode, Opcode_sext_Slot_ae10_slot1_encode, 0, 0, Opcode_sext_Slot_ae4_slot0_encode, Opcode_sext_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { + Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { + Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { + Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { + Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { + Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { + Opcode_quos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { + Opcode_quou_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { + Opcode_rems_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { + Opcode_remu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eraccess_encode_fns[] = { + Opcode_rsr_eraccess_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eraccess_encode_fns[] = { + Opcode_wsr_eraccess_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eraccess_encode_fns[] = { + Opcode_xsr_eraccess_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { + Opcode_rer_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { + Opcode_wer_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_beqz_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_beqz_w15_Slot_ae3_slot0_encode, 0, Opcode_beqz_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bgez_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bgez_w15_Slot_ae3_slot0_encode, 0, Opcode_bgez_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bltz_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bltz_w15_Slot_ae3_slot0_encode, 0, Opcode_bltz_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bnez_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bnez_w15_Slot_ae3_slot0_encode, 0, Opcode_bnez_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_beqi_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_beqi_w15_Slot_ae3_slot0_encode, 0, Opcode_beqi_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bgei_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bgei_w15_Slot_ae3_slot0_encode, 0, Opcode_bgei_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_blti_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_blti_w15_Slot_ae3_slot0_encode, 0, Opcode_blti_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bnei_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bnei_w15_Slot_ae3_slot0_encode, 0, Opcode_bnei_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bgeui_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bgeui_w15_Slot_ae3_slot0_encode, 0, Opcode_bgeui_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bltui_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bltui_w15_Slot_ae3_slot0_encode, 0, Opcode_bltui_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bbci_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bbci_w15_Slot_ae3_slot0_encode, 0, Opcode_bbci_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bbsi_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bbsi_w15_Slot_ae3_slot0_encode, 0, Opcode_bbsi_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ball_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_ball_w15_Slot_ae3_slot0_encode, 0, Opcode_ball_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bany_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bany_w15_Slot_ae3_slot0_encode, 0, Opcode_bany_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bbc_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bbc_w15_Slot_ae3_slot0_encode, 0, Opcode_bbc_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bbs_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bbs_w15_Slot_ae3_slot0_encode, 0, Opcode_bbs_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_beq_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_beq_w15_Slot_ae3_slot0_encode, 0, Opcode_beq_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bgeu_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bgeu_w15_Slot_ae3_slot0_encode, 0, Opcode_bgeu_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bge_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bge_w15_Slot_ae3_slot0_encode, 0, Opcode_bge_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bltu_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bltu_w15_Slot_ae3_slot0_encode, 0, Opcode_bltu_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_blt_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_blt_w15_Slot_ae3_slot0_encode, 0, Opcode_blt_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bnall_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bnall_w15_Slot_ae3_slot0_encode, 0, Opcode_bnall_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bne_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bne_w15_Slot_ae3_slot0_encode, 0, Opcode_bne_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bnone_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bnone_w15_Slot_ae3_slot0_encode, 0, Opcode_bnone_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = { + Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = { + Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = { + Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = { + Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = { + Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = { + Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cw_sd_no_encode_fns[] = { + Opcode_rur_ae_cw_sd_no_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cw_sd_no_encode_fns[] = { + Opcode_wur_ae_cw_sd_no_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cbegin0_encode_fns[] = { + Opcode_rur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cbegin0_encode_fns[] = { + Opcode_wur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cend0_encode_fns[] = { + Opcode_rur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cend0_encode_fns[] = { + Opcode_wur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cbegin1_encode_fns[] = { + Opcode_rur_ae_cbegin1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cbegin1_encode_fns[] = { + Opcode_wur_ae_cbegin1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cend1_encode_fns[] = { + Opcode_rur_ae_cend1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cend1_encode_fns[] = { + Opcode_wur_ae_cend1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cbegin2_encode_fns[] = { + Opcode_rur_ae_cbegin2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cbegin2_encode_fns[] = { + Opcode_wur_ae_cbegin2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cend2_encode_fns[] = { + Opcode_rur_ae_cend2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cend2_encode_fns[] = { + Opcode_wur_ae_cend2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext16_encode_fns[] = { + 0, 0, Opcode_ae_sext16_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_zext16_encode_fns[] = { + 0, 0, Opcode_ae_zext16_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_zext8_encode_fns[] = { + 0, 0, Opcode_ae_zext8_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_clamps16_encode_fns[] = { + 0, 0, Opcode_ae_clamps16_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = { + Opcode_rur_fcr_Slot_inst_encode, 0, 0, Opcode_rur_fcr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = { + Opcode_wur_fcr_Slot_inst_encode, 0, 0, Opcode_wur_fcr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = { + Opcode_rur_fsr_Slot_inst_encode, 0, 0, Opcode_rur_fsr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = { + Opcode_wur_fsr_Slot_inst_encode, 0, 0, Opcode_wur_fsr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { + Opcode_rur_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { + Opcode_wur_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { + Opcode_read_impwire_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { + Opcode_setb_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { + Opcode_clrb_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { + Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = { + Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = { + Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = { + Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = { + Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = { + Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rur_ae_bitptr_Slot_ae3_slot0_encode, 0, Opcode_rur_ae_bitptr_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = { + Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = { + Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = { + Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = { + Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = { + Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = { + Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = { + Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = { + Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = { + Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = { + Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = { + Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cwrap_encode_fns[] = { + Opcode_rur_ae_cwrap_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cwrap_encode_fns[] = { + Opcode_wur_ae_cwrap_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4f_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4f_i_Slot_ae_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4f_i_Slot_ae2_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4f_i_Slot_ae3_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae3_slot1_encode, Opcode_ae_l8x4f_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4f_i_Slot_ae8_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4f_i_Slot_ae9_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4f_i_Slot_ae10_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4f_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4f_ip_Slot_ae_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4f_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4f_ip_Slot_ae3_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae3_slot1_encode, Opcode_ae_l8x4f_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4f_ip_Slot_ae8_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4f_ip_Slot_ae9_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4f_ip_Slot_ae10_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4f_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4f_x_Slot_ae_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4f_x_Slot_ae2_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4f_x_Slot_ae3_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae3_slot1_encode, Opcode_ae_l8x4f_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4f_x_Slot_ae8_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4f_x_Slot_ae9_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4f_x_Slot_ae10_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4f_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4f_xp_Slot_ae_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4f_xp_Slot_ae2_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4f_xp_Slot_ae3_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae3_slot1_encode, Opcode_ae_l8x4f_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4f_xp_Slot_ae8_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4f_xp_Slot_ae9_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4f_xp_Slot_ae10_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4s_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4s_i_Slot_ae_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4s_i_Slot_ae2_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4s_i_Slot_ae3_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae3_slot1_encode, Opcode_ae_l8x4s_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4s_i_Slot_ae8_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4s_i_Slot_ae9_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4s_i_Slot_ae10_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4s_ip_Slot_ae_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4s_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4s_ip_Slot_ae3_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae3_slot1_encode, Opcode_ae_l8x4s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4s_ip_Slot_ae8_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4s_ip_Slot_ae9_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4s_ip_Slot_ae10_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4s_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4s_x_Slot_ae_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4s_x_Slot_ae2_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4s_x_Slot_ae3_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae3_slot1_encode, Opcode_ae_l8x4s_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4s_x_Slot_ae8_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4s_x_Slot_ae9_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4s_x_Slot_ae10_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4s_xp_Slot_ae_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4s_xp_Slot_ae2_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4s_xp_Slot_ae3_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae3_slot1_encode, Opcode_ae_l8x4s_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4s_xp_Slot_ae8_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4s_xp_Slot_ae9_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4s_xp_Slot_ae10_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4u_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4u_i_Slot_ae_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4u_i_Slot_ae2_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4u_i_Slot_ae3_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae3_slot1_encode, Opcode_ae_l8x4u_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4u_i_Slot_ae8_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4u_i_Slot_ae9_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4u_i_Slot_ae10_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4u_ip_Slot_ae_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4u_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4u_ip_Slot_ae3_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae3_slot1_encode, Opcode_ae_l8x4u_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4u_ip_Slot_ae8_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4u_ip_Slot_ae9_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4u_ip_Slot_ae10_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4u_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4u_x_Slot_ae_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4u_x_Slot_ae2_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4u_x_Slot_ae3_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae3_slot1_encode, Opcode_ae_l8x4u_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4u_x_Slot_ae8_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4u_x_Slot_ae9_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4u_x_Slot_ae10_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4u_xp_Slot_ae_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4u_xp_Slot_ae2_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4u_xp_Slot_ae3_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae3_slot1_encode, Opcode_ae_l8x4u_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4u_xp_Slot_ae8_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4u_xp_Slot_ae9_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4u_xp_Slot_ae10_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16m_xc_Slot_ae_slot0_encode, Opcode_ae_l16m_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_xc_Slot_ae2_slot0_encode, Opcode_ae_l16m_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l16m_xc_Slot_ae3_slot0_encode, Opcode_ae_l16m_xc_Slot_ae3_slot1_encode, Opcode_ae_l16m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_xc_Slot_ae8_slot0_encode, Opcode_ae_l16m_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_xc_Slot_ae9_slot0_encode, Opcode_ae_l16m_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_xc_Slot_ae10_slot0_encode, Opcode_ae_l16m_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_xc1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_l16m_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_xc1_Slot_ae2_slot0_encode, Opcode_ae_l16m_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l16m_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_xc1_Slot_ae8_slot0_encode, Opcode_ae_l16m_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_xc1_Slot_ae9_slot0_encode, Opcode_ae_l16m_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_xc1_Slot_ae10_slot0_encode, Opcode_ae_l16m_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16m_i_Slot_ae_slot0_encode, Opcode_ae_l16m_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_i_Slot_ae2_slot0_encode, Opcode_ae_l16m_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l16m_i_Slot_ae3_slot0_encode, Opcode_ae_l16m_i_Slot_ae3_slot1_encode, Opcode_ae_l16m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_i_Slot_ae8_slot0_encode, Opcode_ae_l16m_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_i_Slot_ae9_slot0_encode, Opcode_ae_l16m_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_i_Slot_ae10_slot0_encode, Opcode_ae_l16m_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16m_iu_Slot_ae_slot0_encode, Opcode_ae_l16m_iu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_iu_Slot_ae2_slot0_encode, Opcode_ae_l16m_iu_Slot_ae2_slot1_encode, 0, Opcode_ae_l16m_iu_Slot_ae3_slot0_encode, Opcode_ae_l16m_iu_Slot_ae3_slot1_encode, Opcode_ae_l16m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_iu_Slot_ae8_slot0_encode, Opcode_ae_l16m_iu_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_iu_Slot_ae9_slot0_encode, Opcode_ae_l16m_iu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_iu_Slot_ae10_slot0_encode, Opcode_ae_l16m_iu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16m_x_Slot_ae_slot0_encode, Opcode_ae_l16m_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_x_Slot_ae2_slot0_encode, Opcode_ae_l16m_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l16m_x_Slot_ae3_slot0_encode, Opcode_ae_l16m_x_Slot_ae3_slot1_encode, Opcode_ae_l16m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_x_Slot_ae8_slot0_encode, Opcode_ae_l16m_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_x_Slot_ae9_slot0_encode, Opcode_ae_l16m_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_x_Slot_ae10_slot0_encode, Opcode_ae_l16m_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16m_xu_Slot_ae_slot0_encode, Opcode_ae_l16m_xu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_xu_Slot_ae2_slot0_encode, Opcode_ae_l16m_xu_Slot_ae2_slot1_encode, 0, Opcode_ae_l16m_xu_Slot_ae3_slot0_encode, Opcode_ae_l16m_xu_Slot_ae3_slot1_encode, Opcode_ae_l16m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_xu_Slot_ae8_slot0_encode, Opcode_ae_l16m_xu_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_xu_Slot_ae9_slot0_encode, Opcode_ae_l16m_xu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_xu_Slot_ae10_slot0_encode, Opcode_ae_l16m_xu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_xc_Slot_ae_slot0_encode, Opcode_ae_l16_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_xc_Slot_ae2_slot0_encode, Opcode_ae_l16_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l16_xc_Slot_ae3_slot0_encode, Opcode_ae_l16_xc_Slot_ae3_slot1_encode, Opcode_ae_l16_xc_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16_xc_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_xc_Slot_ae8_slot0_encode, Opcode_ae_l16_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_xc_Slot_ae9_slot0_encode, Opcode_ae_l16_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_xc_Slot_ae10_slot0_encode, Opcode_ae_l16_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_xc1_Slot_ae_slot0_encode, Opcode_ae_l16_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_xc1_Slot_ae2_slot0_encode, Opcode_ae_l16_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l16_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_xc1_Slot_ae8_slot0_encode, Opcode_ae_l16_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_xc1_Slot_ae9_slot0_encode, Opcode_ae_l16_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_xc1_Slot_ae10_slot0_encode, Opcode_ae_l16_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_i_Slot_ae_slot0_encode, Opcode_ae_l16_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_i_Slot_ae2_slot0_encode, Opcode_ae_l16_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l16_i_Slot_ae3_slot0_encode, Opcode_ae_l16_i_Slot_ae3_slot1_encode, Opcode_ae_l16_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16_i_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_i_Slot_ae8_slot0_encode, Opcode_ae_l16_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_i_Slot_ae9_slot0_encode, Opcode_ae_l16_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_i_Slot_ae10_slot0_encode, Opcode_ae_l16_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_ip_Slot_ae_slot0_encode, Opcode_ae_l16_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_ip_Slot_ae2_slot0_encode, Opcode_ae_l16_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l16_ip_Slot_ae3_slot0_encode, Opcode_ae_l16_ip_Slot_ae3_slot1_encode, Opcode_ae_l16_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16_ip_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_ip_Slot_ae8_slot0_encode, Opcode_ae_l16_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_ip_Slot_ae9_slot0_encode, Opcode_ae_l16_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_ip_Slot_ae10_slot0_encode, Opcode_ae_l16_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_x_Slot_ae_slot0_encode, Opcode_ae_l16_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_x_Slot_ae2_slot0_encode, Opcode_ae_l16_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l16_x_Slot_ae3_slot0_encode, Opcode_ae_l16_x_Slot_ae3_slot1_encode, Opcode_ae_l16_x_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16_x_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_x_Slot_ae8_slot0_encode, Opcode_ae_l16_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_x_Slot_ae9_slot0_encode, Opcode_ae_l16_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_x_Slot_ae10_slot0_encode, Opcode_ae_l16_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_xp_Slot_ae_slot0_encode, Opcode_ae_l16_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_xp_Slot_ae2_slot0_encode, Opcode_ae_l16_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l16_xp_Slot_ae3_slot0_encode, Opcode_ae_l16_xp_Slot_ae3_slot1_encode, Opcode_ae_l16_xp_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16_xp_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_xp_Slot_ae8_slot0_encode, Opcode_ae_l16_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_xp_Slot_ae9_slot0_encode, Opcode_ae_l16_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_xp_Slot_ae10_slot0_encode, Opcode_ae_l16_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_xc_Slot_ae_slot0_encode, Opcode_ae_l8_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_xc_Slot_ae2_slot0_encode, Opcode_ae_l8_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l8_xc_Slot_ae3_slot0_encode, Opcode_ae_l8_xc_Slot_ae3_slot1_encode, Opcode_ae_l8_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_xc_Slot_ae8_slot0_encode, Opcode_ae_l8_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_xc_Slot_ae9_slot0_encode, Opcode_ae_l8_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_xc_Slot_ae10_slot0_encode, Opcode_ae_l8_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_xc1_Slot_ae_slot0_encode, Opcode_ae_l8_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_xc1_Slot_ae2_slot0_encode, Opcode_ae_l8_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l8_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_xc1_Slot_ae8_slot0_encode, Opcode_ae_l8_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_xc1_Slot_ae9_slot0_encode, Opcode_ae_l8_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_xc1_Slot_ae10_slot0_encode, Opcode_ae_l8_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_i_Slot_ae_slot0_encode, Opcode_ae_l8_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_i_Slot_ae2_slot0_encode, Opcode_ae_l8_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l8_i_Slot_ae3_slot0_encode, Opcode_ae_l8_i_Slot_ae3_slot1_encode, Opcode_ae_l8_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_i_Slot_ae8_slot0_encode, Opcode_ae_l8_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_i_Slot_ae9_slot0_encode, Opcode_ae_l8_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_i_Slot_ae10_slot0_encode, Opcode_ae_l8_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_ip_Slot_ae_slot0_encode, Opcode_ae_l8_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_ip_Slot_ae2_slot0_encode, Opcode_ae_l8_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l8_ip_Slot_ae3_slot0_encode, Opcode_ae_l8_ip_Slot_ae3_slot1_encode, Opcode_ae_l8_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_ip_Slot_ae8_slot0_encode, Opcode_ae_l8_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_ip_Slot_ae9_slot0_encode, Opcode_ae_l8_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_ip_Slot_ae10_slot0_encode, Opcode_ae_l8_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_x_Slot_ae_slot0_encode, Opcode_ae_l8_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_x_Slot_ae2_slot0_encode, Opcode_ae_l8_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l8_x_Slot_ae3_slot0_encode, Opcode_ae_l8_x_Slot_ae3_slot1_encode, Opcode_ae_l8_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_x_Slot_ae8_slot0_encode, Opcode_ae_l8_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_x_Slot_ae9_slot0_encode, Opcode_ae_l8_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_x_Slot_ae10_slot0_encode, Opcode_ae_l8_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_xp_Slot_ae_slot0_encode, Opcode_ae_l8_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_xp_Slot_ae2_slot0_encode, Opcode_ae_l8_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l8_xp_Slot_ae3_slot0_encode, Opcode_ae_l8_xp_Slot_ae3_slot1_encode, Opcode_ae_l8_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_xp_Slot_ae8_slot0_encode, Opcode_ae_l8_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_xp_Slot_ae9_slot0_encode, Opcode_ae_l8_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_xp_Slot_ae10_slot0_encode, Opcode_ae_l8_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_xc_Slot_ae_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_xc_Slot_ae2_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l32f24_xc_Slot_ae3_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae3_slot1_encode, Opcode_ae_l32f24_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_xc_Slot_ae9_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_xc_Slot_ae10_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae_slot0_encode, Opcode_ae_l32f24_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae2_slot0_encode, Opcode_ae_l32f24_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae9_slot0_encode, Opcode_ae_l32f24_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae10_slot0_encode, Opcode_ae_l32f24_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_i_Slot_ae_slot0_encode, Opcode_ae_l32f24_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_i_Slot_ae2_slot0_encode, Opcode_ae_l32f24_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l32f24_i_Slot_ae3_slot0_encode, Opcode_ae_l32f24_i_Slot_ae3_slot1_encode, Opcode_ae_l32f24_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_i_Slot_ae9_slot0_encode, Opcode_ae_l32f24_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_i_Slot_ae10_slot0_encode, Opcode_ae_l32f24_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_ip_Slot_ae_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_ip_Slot_ae2_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l32f24_ip_Slot_ae3_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae3_slot1_encode, Opcode_ae_l32f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_ip_Slot_ae9_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_ip_Slot_ae10_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_x_Slot_ae_slot0_encode, Opcode_ae_l32f24_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_x_Slot_ae2_slot0_encode, Opcode_ae_l32f24_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l32f24_x_Slot_ae3_slot0_encode, Opcode_ae_l32f24_x_Slot_ae3_slot1_encode, Opcode_ae_l32f24_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_x_Slot_ae9_slot0_encode, Opcode_ae_l32f24_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_x_Slot_ae10_slot0_encode, Opcode_ae_l32f24_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_xp_Slot_ae_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_xp_Slot_ae2_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l32f24_xp_Slot_ae3_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae3_slot1_encode, Opcode_ae_l32f24_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_xp_Slot_ae9_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_xp_Slot_ae10_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_xc_Slot_ae_slot0_encode, Opcode_ae_l32_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_xc_Slot_ae2_slot0_encode, Opcode_ae_l32_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l32_xc_Slot_ae3_slot0_encode, Opcode_ae_l32_xc_Slot_ae3_slot1_encode, Opcode_ae_l32_xc_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32_xc_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_xc_Slot_ae8_slot0_encode, Opcode_ae_l32_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_xc_Slot_ae9_slot0_encode, Opcode_ae_l32_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_xc_Slot_ae10_slot0_encode, Opcode_ae_l32_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_xc1_Slot_ae_slot0_encode, Opcode_ae_l32_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_xc1_Slot_ae2_slot0_encode, Opcode_ae_l32_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_xc1_Slot_ae8_slot0_encode, Opcode_ae_l32_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_xc1_Slot_ae9_slot0_encode, Opcode_ae_l32_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_xc1_Slot_ae10_slot0_encode, Opcode_ae_l32_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_i_Slot_ae_slot0_encode, Opcode_ae_l32_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_i_Slot_ae2_slot0_encode, Opcode_ae_l32_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l32_i_Slot_ae3_slot0_encode, Opcode_ae_l32_i_Slot_ae3_slot1_encode, Opcode_ae_l32_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32_i_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_i_Slot_ae8_slot0_encode, Opcode_ae_l32_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_i_Slot_ae9_slot0_encode, Opcode_ae_l32_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_i_Slot_ae10_slot0_encode, Opcode_ae_l32_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_ip_Slot_ae_slot0_encode, Opcode_ae_l32_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_ip_Slot_ae2_slot0_encode, Opcode_ae_l32_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l32_ip_Slot_ae3_slot0_encode, Opcode_ae_l32_ip_Slot_ae3_slot1_encode, Opcode_ae_l32_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32_ip_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_ip_Slot_ae8_slot0_encode, Opcode_ae_l32_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_ip_Slot_ae9_slot0_encode, Opcode_ae_l32_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_ip_Slot_ae10_slot0_encode, Opcode_ae_l32_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_x_Slot_ae_slot0_encode, Opcode_ae_l32_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_x_Slot_ae2_slot0_encode, Opcode_ae_l32_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l32_x_Slot_ae3_slot0_encode, Opcode_ae_l32_x_Slot_ae3_slot1_encode, Opcode_ae_l32_x_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32_x_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_x_Slot_ae8_slot0_encode, Opcode_ae_l32_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_x_Slot_ae9_slot0_encode, Opcode_ae_l32_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_x_Slot_ae10_slot0_encode, Opcode_ae_l32_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_xp_Slot_ae_slot0_encode, Opcode_ae_l32_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_xp_Slot_ae2_slot0_encode, Opcode_ae_l32_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l32_xp_Slot_ae3_slot0_encode, Opcode_ae_l32_xp_Slot_ae3_slot1_encode, Opcode_ae_l32_xp_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32_xp_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_xp_Slot_ae8_slot0_encode, Opcode_ae_l32_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_xp_Slot_ae9_slot0_encode, Opcode_ae_l32_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_xp_Slot_ae10_slot0_encode, Opcode_ae_l32_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32m_xc_Slot_ae_slot0_encode, Opcode_ae_l32m_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32m_xc_Slot_ae2_slot0_encode, Opcode_ae_l32m_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l32m_xc_Slot_ae3_slot0_encode, Opcode_ae_l32m_xc_Slot_ae3_slot1_encode, Opcode_ae_l32m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32m_xc_Slot_ae8_slot0_encode, Opcode_ae_l32m_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l32m_xc_Slot_ae9_slot0_encode, Opcode_ae_l32m_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32m_xc_Slot_ae10_slot0_encode, Opcode_ae_l32m_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32m_i_Slot_ae_slot0_encode, Opcode_ae_l32m_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32m_i_Slot_ae2_slot0_encode, Opcode_ae_l32m_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l32m_i_Slot_ae3_slot0_encode, Opcode_ae_l32m_i_Slot_ae3_slot1_encode, Opcode_ae_l32m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32m_i_Slot_ae8_slot0_encode, Opcode_ae_l32m_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l32m_i_Slot_ae9_slot0_encode, Opcode_ae_l32m_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32m_i_Slot_ae10_slot0_encode, Opcode_ae_l32m_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32m_iu_Slot_ae_slot0_encode, Opcode_ae_l32m_iu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32m_iu_Slot_ae2_slot0_encode, Opcode_ae_l32m_iu_Slot_ae2_slot1_encode, 0, Opcode_ae_l32m_iu_Slot_ae3_slot0_encode, Opcode_ae_l32m_iu_Slot_ae3_slot1_encode, Opcode_ae_l32m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32m_iu_Slot_ae8_slot0_encode, Opcode_ae_l32m_iu_Slot_ae8_slot1_encode, 0, Opcode_ae_l32m_iu_Slot_ae9_slot0_encode, Opcode_ae_l32m_iu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32m_iu_Slot_ae10_slot0_encode, Opcode_ae_l32m_iu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32m_x_Slot_ae_slot0_encode, Opcode_ae_l32m_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32m_x_Slot_ae2_slot0_encode, Opcode_ae_l32m_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l32m_x_Slot_ae3_slot0_encode, Opcode_ae_l32m_x_Slot_ae3_slot1_encode, Opcode_ae_l32m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32m_x_Slot_ae8_slot0_encode, Opcode_ae_l32m_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l32m_x_Slot_ae9_slot0_encode, Opcode_ae_l32m_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32m_x_Slot_ae10_slot0_encode, Opcode_ae_l32m_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32m_xu_Slot_ae_slot0_encode, Opcode_ae_l32m_xu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32m_xu_Slot_ae2_slot0_encode, Opcode_ae_l32m_xu_Slot_ae2_slot1_encode, 0, Opcode_ae_l32m_xu_Slot_ae3_slot0_encode, Opcode_ae_l32m_xu_Slot_ae3_slot1_encode, Opcode_ae_l32m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32m_xu_Slot_ae8_slot0_encode, Opcode_ae_l32m_xu_Slot_ae8_slot1_encode, 0, Opcode_ae_l32m_xu_Slot_ae9_slot0_encode, Opcode_ae_l32m_xu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32m_xu_Slot_ae10_slot0_encode, Opcode_ae_l32m_xu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x2m_xc_Slot_ae_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_xc_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x2m_xc_Slot_ae3_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_xc_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_xc_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_xc_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_xc1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_xc1_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x2m_i_Slot_ae_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_i_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x2m_i_Slot_ae3_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_i_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_i_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_i_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x2m_iu_Slot_ae_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_iu_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x2m_iu_Slot_ae3_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_iu_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_iu_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_iu_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x2m_x_Slot_ae_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_x_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x2m_x_Slot_ae3_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_x_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_x_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_x_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x2m_xu_Slot_ae_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_xu_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x2m_xu_Slot_ae3_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_xu_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_xu_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_xu_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_xc_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_xc1_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_i_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_ip_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_rip_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ri_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_ri_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_ri_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_ric_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_ric1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ric1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_ric1_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_ric1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_ric1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_x_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_xp_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_xc_Slot_ae_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_xc_Slot_ae3_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae3_slot1_encode, Opcode_ae_l32x2_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_xc_Slot_ae7_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_xc_Slot_ae8_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_xc_Slot_ae9_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_xc_Slot_ae10_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae2_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae7_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae8_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_xc1_Slot_ae9_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae10_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_i_Slot_ae_slot0_encode, Opcode_ae_l32x2_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_i_Slot_ae2_slot0_encode, Opcode_ae_l32x2_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_i_Slot_ae3_slot0_encode, Opcode_ae_l32x2_i_Slot_ae3_slot1_encode, Opcode_ae_l32x2_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32x2_i_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l32x2_i_Slot_ae7_slot0_encode, Opcode_ae_l32x2_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_i_Slot_ae8_slot0_encode, Opcode_ae_l32x2_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_i_Slot_ae9_slot0_encode, Opcode_ae_l32x2_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_i_Slot_ae10_slot0_encode, Opcode_ae_l32x2_i_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2_i_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_ip_Slot_ae_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_ip_Slot_ae3_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae3_slot1_encode, Opcode_ae_l32x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32x2_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l32x2_ip_Slot_ae7_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_ip_Slot_ae8_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_ip_Slot_ae9_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_ip_Slot_ae10_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_ric_Slot_ae_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_ric_Slot_ae2_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_ric_Slot_ae3_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae3_slot1_encode, Opcode_ae_l32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_ric_Slot_ae7_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_ric_Slot_ae8_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_ric_Slot_ae9_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_ric_Slot_ae10_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae2_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae7_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae8_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_ric1_Slot_ae9_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae10_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_x_Slot_ae_slot0_encode, Opcode_ae_l32x2_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_x_Slot_ae2_slot0_encode, Opcode_ae_l32x2_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_x_Slot_ae3_slot0_encode, Opcode_ae_l32x2_x_Slot_ae3_slot1_encode, Opcode_ae_l32x2_x_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32x2_x_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l32x2_x_Slot_ae7_slot0_encode, Opcode_ae_l32x2_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_x_Slot_ae8_slot0_encode, Opcode_ae_l32x2_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_x_Slot_ae9_slot0_encode, Opcode_ae_l32x2_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_x_Slot_ae10_slot0_encode, Opcode_ae_l32x2_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_xp_Slot_ae_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_xp_Slot_ae3_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae3_slot1_encode, Opcode_ae_l32x2_xp_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32x2_xp_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l32x2_xp_Slot_ae7_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_xp_Slot_ae8_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_xp_Slot_ae9_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_xp_Slot_ae10_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2_xp_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_xc_Slot_ae_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_xc_Slot_ae2_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_xc_Slot_ae3_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae3_slot1_encode, Opcode_ae_l16x4_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc_Slot_ae7_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_xc_Slot_ae8_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_xc_Slot_ae9_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_xc_Slot_ae10_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae2_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae7_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae8_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_xc1_Slot_ae9_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae10_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_i_Slot_ae_slot0_encode, Opcode_ae_l16x4_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_i_Slot_ae2_slot0_encode, Opcode_ae_l16x4_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_i_Slot_ae3_slot0_encode, Opcode_ae_l16x4_i_Slot_ae3_slot1_encode, Opcode_ae_l16x4_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16x4_i_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l16x4_i_Slot_ae7_slot0_encode, Opcode_ae_l16x4_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_i_Slot_ae8_slot0_encode, Opcode_ae_l16x4_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_i_Slot_ae9_slot0_encode, Opcode_ae_l16x4_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_i_Slot_ae10_slot0_encode, Opcode_ae_l16x4_i_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4_i_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_ip_Slot_ae_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_ip_Slot_ae2_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_ip_Slot_ae3_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae3_slot1_encode, Opcode_ae_l16x4_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16x4_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l16x4_ip_Slot_ae7_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_ip_Slot_ae8_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_ip_Slot_ae9_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_ip_Slot_ae10_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_x_Slot_ae_slot0_encode, Opcode_ae_l16x4_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_x_Slot_ae2_slot0_encode, Opcode_ae_l16x4_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_x_Slot_ae3_slot0_encode, Opcode_ae_l16x4_x_Slot_ae3_slot1_encode, Opcode_ae_l16x4_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_x_Slot_ae7_slot0_encode, Opcode_ae_l16x4_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_x_Slot_ae8_slot0_encode, Opcode_ae_l16x4_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_x_Slot_ae9_slot0_encode, Opcode_ae_l16x4_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_x_Slot_ae10_slot0_encode, Opcode_ae_l16x4_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_xp_Slot_ae_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_xp_Slot_ae2_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_xp_Slot_ae3_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae3_slot1_encode, Opcode_ae_l16x4_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xp_Slot_ae7_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_xp_Slot_ae8_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_xp_Slot_ae9_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_xp_Slot_ae10_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4_xp_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_xc_Slot_ae_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_xc_Slot_ae2_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_xc_Slot_ae3_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae3_slot1_encode, Opcode_ae_l8x8_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_xc_Slot_ae7_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_xc_Slot_ae8_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_xc_Slot_ae9_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_xc_Slot_ae10_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae2_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae7_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae8_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_xc1_Slot_ae9_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae10_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_i_Slot_ae_slot0_encode, Opcode_ae_l8x8_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_i_Slot_ae2_slot0_encode, Opcode_ae_l8x8_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_i_Slot_ae3_slot0_encode, Opcode_ae_l8x8_i_Slot_ae3_slot1_encode, Opcode_ae_l8x8_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_i_Slot_ae7_slot0_encode, Opcode_ae_l8x8_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_i_Slot_ae8_slot0_encode, Opcode_ae_l8x8_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_i_Slot_ae9_slot0_encode, Opcode_ae_l8x8_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_i_Slot_ae10_slot0_encode, Opcode_ae_l8x8_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_ip_Slot_ae_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_ip_Slot_ae3_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae3_slot1_encode, Opcode_ae_l8x8_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_ip_Slot_ae7_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_ip_Slot_ae8_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_ip_Slot_ae9_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_ip_Slot_ae10_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_x_Slot_ae_slot0_encode, Opcode_ae_l8x8_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_x_Slot_ae2_slot0_encode, Opcode_ae_l8x8_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_x_Slot_ae3_slot0_encode, Opcode_ae_l8x8_x_Slot_ae3_slot1_encode, Opcode_ae_l8x8_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_x_Slot_ae7_slot0_encode, Opcode_ae_l8x8_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_x_Slot_ae8_slot0_encode, Opcode_ae_l8x8_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_x_Slot_ae9_slot0_encode, Opcode_ae_l8x8_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_x_Slot_ae10_slot0_encode, Opcode_ae_l8x8_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_xp_Slot_ae_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_xp_Slot_ae2_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_xp_Slot_ae3_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae3_slot1_encode, Opcode_ae_l8x8_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_xp_Slot_ae7_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_xp_Slot_ae8_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_xp_Slot_ae9_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_xp_Slot_ae10_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_xc_Slot_ae_slot0_encode, Opcode_ae_l64_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_xc_Slot_ae2_slot0_encode, Opcode_ae_l64_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_xc_Slot_ae3_slot0_encode, Opcode_ae_l64_xc_Slot_ae3_slot1_encode, Opcode_ae_l64_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_xc_Slot_ae7_slot0_encode, Opcode_ae_l64_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_xc_Slot_ae8_slot0_encode, Opcode_ae_l64_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_xc_Slot_ae9_slot0_encode, Opcode_ae_l64_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_xc_Slot_ae10_slot0_encode, Opcode_ae_l64_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_xc1_Slot_ae_slot0_encode, Opcode_ae_l64_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_xc1_Slot_ae2_slot0_encode, Opcode_ae_l64_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l64_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_xc1_Slot_ae7_slot0_encode, Opcode_ae_l64_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_xc1_Slot_ae8_slot0_encode, Opcode_ae_l64_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_xc1_Slot_ae9_slot0_encode, Opcode_ae_l64_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_xc1_Slot_ae10_slot0_encode, Opcode_ae_l64_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_i_Slot_ae_slot0_encode, Opcode_ae_l64_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_i_Slot_ae2_slot0_encode, Opcode_ae_l64_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_i_Slot_ae3_slot0_encode, Opcode_ae_l64_i_Slot_ae3_slot1_encode, Opcode_ae_l64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_i_Slot_ae7_slot0_encode, Opcode_ae_l64_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_i_Slot_ae8_slot0_encode, Opcode_ae_l64_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_i_Slot_ae9_slot0_encode, Opcode_ae_l64_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_i_Slot_ae10_slot0_encode, Opcode_ae_l64_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_ip_Slot_ae_slot0_encode, Opcode_ae_l64_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_ip_Slot_ae2_slot0_encode, Opcode_ae_l64_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_ip_Slot_ae3_slot0_encode, Opcode_ae_l64_ip_Slot_ae3_slot1_encode, Opcode_ae_l64_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_ip_Slot_ae7_slot0_encode, Opcode_ae_l64_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_ip_Slot_ae8_slot0_encode, Opcode_ae_l64_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_ip_Slot_ae9_slot0_encode, Opcode_ae_l64_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_ip_Slot_ae10_slot0_encode, Opcode_ae_l64_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_x_Slot_ae_slot0_encode, Opcode_ae_l64_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_x_Slot_ae2_slot0_encode, Opcode_ae_l64_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_x_Slot_ae3_slot0_encode, Opcode_ae_l64_x_Slot_ae3_slot1_encode, Opcode_ae_l64_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_x_Slot_ae7_slot0_encode, Opcode_ae_l64_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_x_Slot_ae8_slot0_encode, Opcode_ae_l64_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_x_Slot_ae9_slot0_encode, Opcode_ae_l64_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_x_Slot_ae10_slot0_encode, Opcode_ae_l64_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_xp_Slot_ae_slot0_encode, Opcode_ae_l64_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_xp_Slot_ae2_slot0_encode, Opcode_ae_l64_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_xp_Slot_ae3_slot0_encode, Opcode_ae_l64_xp_Slot_ae3_slot1_encode, Opcode_ae_l64_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_xp_Slot_ae7_slot0_encode, Opcode_ae_l64_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_xp_Slot_ae8_slot0_encode, Opcode_ae_l64_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_xp_Slot_ae9_slot0_encode, Opcode_ae_l64_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_xp_Slot_ae10_slot0_encode, Opcode_ae_l64_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x2m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x2m_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x2m_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x2m_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x2m_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x2m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x2m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x2m_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x2m_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x2m_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x2m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x2m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_ric_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_ric_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_x_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_xp_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2rng_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2rng_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2rng_x_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2rng_xp_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_x_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_xp_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s8x8_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s16m_l_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16m_l_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s16m_l_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae3_slot0_encode, 0, Opcode_ae_s16m_l_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16m_l_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s16m_l_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae3_slot0_encode, 0, Opcode_ae_s16m_l_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32f24_l_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32f24_l_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32f24_l_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32f24_l_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32f24_l_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_l_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_l_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_l_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_l_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_l_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_l_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_l_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_l_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_l_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_l_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_h_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_h_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32_h_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_h_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_h_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_h_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_h_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_h_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_h_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_h_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_h_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16_0_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s16_0_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16_0_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s16_0_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16_0_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s16_0_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16_0_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s16_0_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16_0_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s16_0_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8_0_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s8_0_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s8_0_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8_0_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s8_0_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8_0_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s8_0_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8_0_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s8_0_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8_0_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s8_0_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s64_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32m_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32m_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32m_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32m_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32m_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32m_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32m_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32m_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32m_iu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32m_iu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32m_iu_Slot_ae3_slot0_encode, 0, Opcode_ae_s32m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_iu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32m_iu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32m_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32m_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32m_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32m_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32m_xu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32m_xu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32m_xu_Slot_ae3_slot0_encode, 0, Opcode_ae_s32m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_xu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32m_xu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_xc2_Slot_ae_slot0_encode, Opcode_ae_l32x2_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_xc2_Slot_ae2_slot0_encode, Opcode_ae_l32x2_xc2_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_l32x2_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_xc2_Slot_ae8_slot0_encode, Opcode_ae_l32x2_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_xc2_Slot_ae9_slot0_encode, Opcode_ae_l32x2_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_xc2_Slot_ae_slot0_encode, Opcode_ae_l16x4_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_xc2_Slot_ae2_slot0_encode, Opcode_ae_l16x4_xc2_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_l16x4_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc2_Slot_ae8_slot0_encode, Opcode_ae_l16x4_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_xc2_Slot_ae9_slot0_encode, Opcode_ae_l16x4_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_xc2_Slot_ae_slot0_encode, Opcode_ae_l8x8_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_xc2_Slot_ae2_slot0_encode, Opcode_ae_l8x8_xc2_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_l8x8_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_xc2_Slot_ae8_slot0_encode, Opcode_ae_l8x8_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_xc2_Slot_ae9_slot0_encode, Opcode_ae_l8x8_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_xc2_Slot_ae_slot0_encode, Opcode_ae_l64_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_xc2_Slot_ae2_slot0_encode, Opcode_ae_l64_xc2_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_l64_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_xc2_Slot_ae8_slot0_encode, Opcode_ae_l64_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_xc2_Slot_ae9_slot0_encode, Opcode_ae_l64_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_xc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_xc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_xc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_xc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_xc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_xc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_xc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_xc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4rng_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4rng_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4rng_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4rng_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4rng_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4rng_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4rng_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4rng_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4rng_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4rng_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4rng_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4rng_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4rng_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4rng_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4rng_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4rng_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4rng_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4rng_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4rng_x_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4rng_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4rng_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4rng_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4rng_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4rng_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4rng_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4rng_xp_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4rng_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4rng_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_xc_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_xc1_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_i_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_i_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_i_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_i_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_i_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_i_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_ip_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_x_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_x_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_x_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_x_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_x_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_x_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_xp_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_xc_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_xc1_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_i_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_i_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_i_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_i_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_i_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_i_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_ip_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_x_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_x_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_x_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_x_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_x_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_x_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_xp_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_xc_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_xc_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_xc_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_xc1_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc1_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_xc1_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc1_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_xc1_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc1_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_i_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_i_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_i_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_i_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_i_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_i_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_ip_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_x_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_x_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_x_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_x_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_x_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_x_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_xp_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_xp_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xp_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_xp_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xp_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_xc_Slot_ae_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_xc_Slot_ae7_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_xc_Slot_ae8_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_xc_Slot_ae9_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_xc_Slot_ae10_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_xc1_Slot_ae_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_xc1_Slot_ae2_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_xc1_Slot_ae7_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_xc1_Slot_ae8_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_xc1_Slot_ae9_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_xc1_Slot_ae10_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_i_Slot_ae_slot0_encode, Opcode_ae_l64x2_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_i_Slot_ae2_slot0_encode, Opcode_ae_l64x2_i_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_i_Slot_ae7_slot0_encode, Opcode_ae_l64x2_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_i_Slot_ae8_slot0_encode, Opcode_ae_l64x2_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_i_Slot_ae9_slot0_encode, Opcode_ae_l64x2_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_i_Slot_ae10_slot0_encode, Opcode_ae_l64x2_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_ip_Slot_ae_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_ip_Slot_ae7_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_ip_Slot_ae8_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_ip_Slot_ae9_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_ip_Slot_ae10_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_x_Slot_ae_slot0_encode, Opcode_ae_l64x2_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_x_Slot_ae2_slot0_encode, Opcode_ae_l64x2_x_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_x_Slot_ae7_slot0_encode, Opcode_ae_l64x2_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_x_Slot_ae8_slot0_encode, Opcode_ae_l64x2_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_x_Slot_ae9_slot0_encode, Opcode_ae_l64x2_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_x_Slot_ae10_slot0_encode, Opcode_ae_l64x2_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_xp_Slot_ae_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_xp_Slot_ae7_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_xp_Slot_ae8_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_xp_Slot_ae9_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_xp_Slot_ae10_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_xc_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_xc1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_ip_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_x_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xp_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2rng_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2rng_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2rng_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2rng_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_ip_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2rng_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2rng_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2rng_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2rng_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_xp_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_xc_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_xc1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_xc_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_xc1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_xc_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_xc1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_xc2_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc2_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_xc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_xc2_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_xc2_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_xc2_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc2_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_xc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_xc2_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_xc2_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_xc2_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc2_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_xc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_xc2_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_xc2_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_xc2_Slot_ae_slot0_encode, Opcode_ae_l64x2_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_xc2_Slot_ae2_slot0_encode, Opcode_ae_l64x2_xc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_xc2_Slot_ae8_slot0_encode, Opcode_ae_l64x2_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_xc2_Slot_ae9_slot0_encode, Opcode_ae_l64x2_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_xc2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_xc2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_xc2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_xc2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2rng_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2rng_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2rng_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2rng_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2rng_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2rng_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2rng_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2rng_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2rng_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2rng_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2rng_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2rng_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_zalign64_encode_fns[] = { + 0, 0, 0, Opcode_ae_zalign64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_zalign64_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_zalign64_Slot_ae3_slot0_encode, 0, Opcode_ae_zalign64_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lalign64_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_lalign64_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lalign64_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_lalign64_i_Slot_ae3_slot0_encode, 0, Opcode_ae_lalign64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_salign64_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_salign64_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_salign64_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_salign64_i_Slot_ae3_slot0_encode, 0, Opcode_ae_salign64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movalign_encode_fns[] = { + 0, 0, 0, Opcode_ae_movalign_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movalign_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movalign_Slot_ae3_slot0_encode, 0, Opcode_ae_movalign_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la64_pp_encode_fns[] = { + 0, 0, 0, Opcode_ae_la64_pp_Slot_ae_slot0_encode, Opcode_ae_la64_pp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la64_pp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la64_pp_Slot_ae3_slot0_encode, Opcode_ae_la64_pp_Slot_ae3_slot1_encode, Opcode_ae_la64_pp_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la64_pp_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24pos_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24pos_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24pos_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la24pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24neg_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24neg_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24neg_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24neg_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la24neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24pos_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24neg_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24neg_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2pos_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2pos_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2pos_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2neg_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2neg_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2neg_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2neg_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2pos_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2neg_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2neg_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2pos_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2pos_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2pos_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2neg_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2neg_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2neg_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2neg_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2pos_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2neg_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2neg_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2pos_pc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2pos_pc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2pos_pc2_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2pos_pc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4pos_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4pos_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4pos_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4neg_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4neg_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4neg_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4neg_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4pos_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4neg_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4neg_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4pos_pc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4pos_pc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4pos_pc2_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4pos_pc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8pos_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8pos_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8pos_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8neg_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8neg_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8neg_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8neg_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8pos_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la8x8pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8neg_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8neg_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la8x8neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8pos_pc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8pos_pc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8pos_pc2_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8pos_pc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa64pos_fp_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa64pos_fp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa64pos_fp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa64pos_fp_Slot_ae3_slot0_encode, 0, Opcode_ae_sa64pos_fp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa64neg_fp_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa64neg_fp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa64neg_fp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa64neg_fp_Slot_ae3_slot0_encode, 0, Opcode_ae_sa64neg_fp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic_Slot_ae7_slot0_encode, Opcode_ae_la32x2_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_ic_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ic_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae7_slot0_encode, Opcode_ae_la32x2_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ic1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic2_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ic2_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ip_Slot_ae_slot0_encode, Opcode_ae_la32x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2_ip_Slot_ae3_slot0_encode, Opcode_ae_la32x2_ip_Slot_ae3_slot1_encode, Opcode_ae_la32x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la32x2_ip_Slot_ae7_slot0_encode, Opcode_ae_la32x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_ip_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_rip_Slot_ae_slot0_encode, Opcode_ae_la32x2_rip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_rip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la32x2_rip_Slot_ae7_slot0_encode, Opcode_ae_la32x2_rip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_rip_Slot_ae8_slot0_encode, Opcode_ae_la32x2_rip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ric_Slot_ae7_slot0_encode, Opcode_ae_la32x2_ric_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_ric_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ric_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae7_slot0_encode, Opcode_ae_la32x2_ric1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ric1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic_Slot_ae7_slot0_encode, Opcode_ae_la16x4_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_ic_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ic_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae7_slot0_encode, Opcode_ae_la16x4_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ic1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic2_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ic2_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ip_Slot_ae_slot0_encode, Opcode_ae_la16x4_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4_ip_Slot_ae3_slot0_encode, Opcode_ae_la16x4_ip_Slot_ae3_slot1_encode, Opcode_ae_la16x4_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la16x4_ip_Slot_ae7_slot0_encode, Opcode_ae_la16x4_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_ip_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_rip_Slot_ae_slot0_encode, Opcode_ae_la16x4_rip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4_rip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_rip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la16x4_rip_Slot_ae7_slot0_encode, Opcode_ae_la16x4_rip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_rip_Slot_ae8_slot0_encode, Opcode_ae_la16x4_rip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ric_Slot_ae7_slot0_encode, Opcode_ae_la16x4_ric_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_ric_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ric_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae7_slot0_encode, Opcode_ae_la16x4_ric1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ric1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8_ic_Slot_ae7_slot0_encode, Opcode_ae_la8x8_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_ic_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ic_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la8x8_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8_ic1_Slot_ae7_slot0_encode, Opcode_ae_la8x8_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_ic1_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ic1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8_ic2_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ic2_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ip_Slot_ae_slot0_encode, Opcode_ae_la8x8_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8_ip_Slot_ae3_slot0_encode, Opcode_ae_la8x8_ip_Slot_ae3_slot1_encode, Opcode_ae_la8x8_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la8x8_ip_Slot_ae7_slot0_encode, Opcode_ae_la8x8_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_ip_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_rip_Slot_ae_slot0_encode, Opcode_ae_la8x8_rip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8_rip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_rip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la8x8_rip_Slot_ae7_slot0_encode, Opcode_ae_la8x8_rip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_rip_Slot_ae8_slot0_encode, Opcode_ae_la8x8_rip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8_ric_Slot_ae7_slot0_encode, Opcode_ae_la8x8_ric_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_ric_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ric_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la8x8_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8_ric1_Slot_ae7_slot0_encode, Opcode_ae_la8x8_ric1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_ric1_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ric1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2f24_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_ic_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_ic1_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae_slot0_encode, Opcode_ae_la32x2f24_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_ip_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae_slot0_encode, Opcode_ae_la32x2f24_rip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_rip_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_ric_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_ric1_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la24_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_la24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ic2_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa16x4_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa16x4_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_sa16x4_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ic2_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa16x4_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa16x4_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa16x4_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa8x8_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa8x8_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ic_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa8x8_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ic1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa8x8_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_sa8x8_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ic2_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa8x8_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa8x8_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa8x8_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa8x8_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_rip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa8x8_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa8x8_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ric_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa8x8_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ric1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2f24_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24_l_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24_l_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24_l_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24_l_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24_l_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24_l_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24_l_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24_l_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24_l_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24_l_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24x2_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24x2_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24x2_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24x2_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addicirc_encode_fns[] = { + 0, 0, 0, Opcode_ae_addicirc_Slot_ae_slot0_encode, Opcode_ae_addicirc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_addicirc_Slot_ae2_slot0_encode, Opcode_ae_addicirc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcirc_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_addcirc_xc2_Slot_ae_slot0_encode, Opcode_ae_addcirc_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_addcirc_xc2_Slot_ae2_slot0_encode, Opcode_ae_addcirc_xc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addcirc_xc2_Slot_ae4_slot0_encode, Opcode_ae_addcirc_xc2_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcirc_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_addcirc_xc1_Slot_ae_slot0_encode, Opcode_ae_addcirc_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_addcirc_xc1_Slot_ae2_slot0_encode, Opcode_ae_addcirc_xc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addcirc_xc1_Slot_ae4_slot0_encode, Opcode_ae_addcirc_xc1_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcirc_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_addcirc_xc_Slot_ae_slot0_encode, Opcode_ae_addcirc_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_addcirc_xc_Slot_ae2_slot0_encode, Opcode_ae_addcirc_xc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addcirc_xc_Slot_ae4_slot0_encode, Opcode_ae_addcirc_xc_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32ra64s_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32ra64s_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32ra64s_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32ra64s_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32ra64s_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32ra64s_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32ra64s_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32ra64s_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32ra64s_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32ra64s_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24ra64s_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s24ra64s_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24ra64s_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s24ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24ra64s_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s24ra64s_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24ra64s_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s24ra64s_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24ra64s_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s24ra64s_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s24ra64s_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2ra64s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24x2ra64s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4ra32s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4ra32s_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4ra32s_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4ra32s_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4ra32s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addbrba32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addbrba32_Slot_ae_slot0_encode, Opcode_ae_addbrba32_Slot_ae_slot1_encode, 0, 0, Opcode_ae_addbrba32_Slot_ae2_slot0_encode, Opcode_ae_addbrba32_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_addbrba32_Slot_ae3_slot1_encode, 0, 0, 0, 0, Opcode_ae_addbrba32_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addbrba32_Slot_ae4_slot0_encode, Opcode_ae_addbrba32_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_l_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_l_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bitswap_encode_fns[] = { + 0, 0, 0, Opcode_ae_bitswap_Slot_ae_slot0_encode, Opcode_ae_bitswap_Slot_ae_slot1_encode, 0, 0, Opcode_ae_bitswap_Slot_ae2_slot0_encode, Opcode_ae_bitswap_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_bitswap_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32js_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32js_Slot_ae_slot0_encode, 0, Opcode_ae_mul32js_Slot_ae_slot2_encode, Opcode_ae_mul32js_Slot_ae_slot3_encode, Opcode_ae_mul32js_Slot_ae2_slot0_encode, 0, Opcode_ae_mul32js_Slot_ae2_slot2_encode, 0, 0, Opcode_ae_mul32js_Slot_ae5_slot0_encode, 0, Opcode_ae_mul32js_Slot_ae5_slot2_encode, Opcode_ae_mul32js_Slot_ae6_slot0_encode, 0, Opcode_ae_mul32js_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32js_Slot_ae4_slot2_encode, Opcode_ae_mul32js_Slot_ae4_slot3_encode, Opcode_ae_mul32js_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsub32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsub32s_Slot_ae_slot0_encode, 0, Opcode_ae_addandsub32s_Slot_ae_slot2_encode, Opcode_ae_addandsub32s_Slot_ae_slot3_encode, Opcode_ae_addandsub32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32s_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsub32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32s_Slot_ae4_slot2_encode, Opcode_ae_addandsub32s_Slot_ae4_slot3_encode, Opcode_ae_addandsub32s_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsub32js_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsub32js_Slot_ae_slot0_encode, 0, Opcode_ae_addandsub32js_Slot_ae_slot2_encode, Opcode_ae_addandsub32js_Slot_ae_slot3_encode, Opcode_ae_addandsub32js_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32js_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsub32js_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32js_Slot_ae4_slot2_encode, Opcode_ae_addandsub32js_Slot_ae4_slot3_encode, Opcode_ae_addandsub32js_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsubrng32_Slot_ae_slot0_encode, 0, Opcode_ae_addandsubrng32_Slot_ae_slot2_encode, Opcode_ae_addandsubrng32_Slot_ae_slot3_encode, Opcode_ae_addandsubrng32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsubrng32_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_Slot_ae4_slot2_encode, Opcode_ae_addandsubrng32_Slot_ae4_slot3_encode, Opcode_ae_addandsubrng32_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsubrng32_h_Slot_ae_slot0_encode, 0, Opcode_ae_addandsubrng32_h_Slot_ae_slot2_encode, Opcode_ae_addandsubrng32_h_Slot_ae_slot3_encode, Opcode_ae_addandsubrng32_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_h_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsubrng32_h_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_h_Slot_ae4_slot2_encode, Opcode_ae_addandsubrng32_h_Slot_ae4_slot3_encode, Opcode_ae_addandsubrng32_h_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsubrng32_l_Slot_ae_slot0_encode, 0, Opcode_ae_addandsubrng32_l_Slot_ae_slot2_encode, Opcode_ae_addandsubrng32_l_Slot_ae_slot3_encode, Opcode_ae_addandsubrng32_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_l_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsubrng32_l_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_l_Slot_ae4_slot2_encode, Opcode_ae_addandsubrng32_l_Slot_ae4_slot3_encode, Opcode_ae_addandsubrng32_l_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addrng32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_addrng32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subrng32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_subrng32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rng32x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_rng32x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel16i_encode_fns[] = { + 0, 0, 0, Opcode_ae_sel16i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sel16i_Slot_ae_slot3_encode, Opcode_ae_sel16i_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_ae_sel16i_Slot_ae3_slot1_encode, Opcode_ae_sel16i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sel16i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sel16i_Slot_ae9_slot0_encode, 0, 0, Opcode_ae_sel16i_Slot_ae9_slot3_encode, 0, 0, 0, Opcode_ae_sel16i_Slot_ae10_slot3_encode, 0, 0, 0, Opcode_ae_sel16i_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel16i_n_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sel16i_n_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sel16i_n_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sel16i_n_Slot_ae4_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_shortswap_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_shortswap_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movab4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movab4_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movab4_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movab2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movab2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movab2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movab_encode_fns[] = { + 0, 0, 0, Opcode_ae_movab_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movab_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba_encode_fns[] = { + 0, 0, 0, Opcode_ae_movba_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movba_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba1x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movba1x2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movba1x2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movba4_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movba4_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movba2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movba2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movb2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movb2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movb4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movb4_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt16x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt16x4_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movt16x4_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movt16x4_Slot_ae6_slot0_encode, 0, Opcode_ae_movt16x4_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movt16x4_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movf16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movf16x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movf16x4_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movf16x4_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movf16x4_Slot_ae6_slot0_encode, 0, Opcode_ae_movf16x4_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movf16x4_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt32x2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt32x2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movt32x2_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movt32x2_Slot_ae6_slot0_encode, 0, Opcode_ae_movt32x2_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movt32x2_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movf32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movf32x2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movf32x2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movf32x2_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movf32x2_Slot_ae6_slot0_encode, 0, Opcode_ae_movf32x2_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movf32x2_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movsara7x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movsara7x2_Slot_ae_slot0_encode, Opcode_ae_movsara7x2_Slot_ae_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movsard7_encode_fns[] = { + 0, 0, 0, Opcode_ae_movsard7_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movsard7_Slot_ae2_slot0_encode, Opcode_ae_movsard7_Slot_ae2_slot1_encode, 0, Opcode_ae_movsard7_Slot_ae3_slot0_encode, 0, Opcode_ae_movsard7_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movasar_encode_fns[] = { + 0, 0, 0, Opcode_ae_movasar_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movasar_Slot_ae2_slot0_encode, Opcode_ae_movasar_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movda32x2_Slot_ae_slot0_encode, Opcode_ae_movda32x2_Slot_ae_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movda32x2_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda32_encode_fns[] = { + 0, 0, 0, Opcode_ae_movda32_Slot_ae_slot0_encode, Opcode_ae_movda32_Slot_ae_slot1_encode, 0, 0, Opcode_ae_movda32_Slot_ae2_slot0_encode, Opcode_ae_movda32_Slot_ae2_slot1_encode, 0, Opcode_ae_movda32_Slot_ae3_slot0_encode, Opcode_ae_movda32_Slot_ae3_slot1_encode, Opcode_ae_movda32_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda16x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movda16x2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda16_encode_fns[] = { + 0, 0, 0, Opcode_ae_movda16_Slot_ae_slot0_encode, Opcode_ae_movda16_Slot_ae_slot1_encode, 0, 0, Opcode_ae_movda16_Slot_ae2_slot0_encode, Opcode_ae_movda16_Slot_ae2_slot1_encode, 0, Opcode_ae_movda16_Slot_ae3_slot0_encode, Opcode_ae_movda16_Slot_ae3_slot1_encode, Opcode_ae_movda16_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movi_encode_fns[] = { + 0, 0, 0, Opcode_ae_movi_Slot_ae_slot0_encode, Opcode_ae_movi_Slot_ae_slot1_encode, Opcode_ae_movi_Slot_ae_slot2_encode, Opcode_ae_movi_Slot_ae_slot3_encode, Opcode_ae_movi_Slot_ae2_slot0_encode, Opcode_ae_movi_Slot_ae2_slot1_encode, 0, Opcode_ae_movi_Slot_ae3_slot0_encode, Opcode_ae_movi_Slot_ae3_slot1_encode, Opcode_ae_movi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode, Opcode_ae_truncp24a32x2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae2_slot0_encode, Opcode_ae_truncp24a32x2_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat16x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sat16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sat16x4_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt32x2f16_32_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt32x2f16_32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvt32x2f16_32_Slot_ae_slot3_encode, Opcode_ae_cvt32x2f16_32_Slot_ae2_slot0_encode, Opcode_ae_cvt32x2f16_32_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt32x2f16_10_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt32x2f16_10_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvt32x2f16_10_Slot_ae_slot3_encode, Opcode_ae_cvt32x2f16_10_Slot_ae2_slot0_encode, Opcode_ae_cvt32x2f16_10_Slot_ae2_slot1_encode, 0, Opcode_ae_cvt32x2f16_10_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext32x2d16_32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sext32x2d16_32_Slot_ae_slot0_encode, 0, Opcode_ae_sext32x2d16_32_Slot_ae_slot2_encode, Opcode_ae_sext32x2d16_32_Slot_ae_slot3_encode, Opcode_ae_sext32x2d16_32_Slot_ae2_slot0_encode, Opcode_ae_sext32x2d16_32_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext32x2d16_10_encode_fns[] = { + 0, 0, 0, Opcode_ae_sext32x2d16_10_Slot_ae_slot0_encode, 0, Opcode_ae_sext32x2d16_10_Slot_ae_slot2_encode, Opcode_ae_sext32x2d16_10_Slot_ae_slot3_encode, Opcode_ae_sext32x2d16_10_Slot_ae2_slot0_encode, Opcode_ae_sext32x2d16_10_Slot_ae2_slot1_encode, 0, Opcode_ae_sext32x2d16_10_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32f24s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32f24s_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32f24s_l_Slot_ae2_slot0_encode, Opcode_ae_cvta32f24s_l_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32f24s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32f24s_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32f24s_h_Slot_ae2_slot0_encode, Opcode_ae_cvta32f24s_h_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae3_slot0_encode, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca32x2f64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunci32x2f64s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci32x2f64s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_trunci32x2f64s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, Opcode_ae_trunci32x2f64s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci32x2f64s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca32f64s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca32f64s_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunca32f64s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca32f64s_l_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunci32f64s_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci32f64s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci32f64s_l_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f64ssym_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_round32x2f64ssym_Slot_ae_slot2_encode, Opcode_ae_round32x2f64ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f64sasym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round32x2f64sasym_Slot_ae_slot0_encode, 0, Opcode_ae_round32x2f64sasym_Slot_ae_slot2_encode, Opcode_ae_round32x2f64sasym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f48ssym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round32x2f48ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f48sasym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round32x2f48sasym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round16x4f32ssym_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_round16x4f32ssym_Slot_ae_slot2_encode, Opcode_ae_round16x4f32ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_round16x4f32ssym_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round16x4f32sasym_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_round16x4f32sasym_Slot_ae_slot2_encode, Opcode_ae_round16x4f32sasym_Slot_ae_slot3_encode, 0, 0, 0, Opcode_ae_round16x4f32sasym_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_round16x4f32sasym_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round24x2f48ssym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round24x2f48ssym_Slot_ae_slot0_encode, 0, 0, Opcode_ae_round24x2f48ssym_Slot_ae_slot3_encode, 0, 0, 0, Opcode_ae_round24x2f48ssym_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round24x2f48sasym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round24x2f48sasym_Slot_ae_slot0_encode, 0, 0, Opcode_ae_round24x2f48sasym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48x2sym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsp16q48x2sym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48x2asym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsp16q48x2asym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minabs32s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_minabs32s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxabs32s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_maxabs32s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16f24sym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsp16f24sym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16f24asym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsp16f24asym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mov_encode_fns[] = { + 0, 0, 0, Opcode_ae_mov_Slot_ae_slot0_encode, 0, Opcode_ae_mov_Slot_ae_slot2_encode, Opcode_ae_mov_Slot_ae_slot3_encode, Opcode_ae_mov_Slot_ae2_slot0_encode, Opcode_ae_mov_Slot_ae2_slot1_encode, Opcode_ae_mov_Slot_ae2_slot2_encode, Opcode_ae_mov_Slot_ae3_slot0_encode, Opcode_ae_mov_Slot_ae3_slot1_encode, Opcode_ae_mov_Slot_ae5_slot0_encode, 0, Opcode_ae_mov_Slot_ae5_slot2_encode, Opcode_ae_mov_Slot_ae6_slot0_encode, Opcode_ae_mov_Slot_ae6_slot1_encode, Opcode_ae_mov_Slot_ae6_slot2_encode, Opcode_ae_mov_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mov_Slot_ae7_slot2_encode, Opcode_ae_mov_Slot_ae7_slot3_encode, Opcode_ae_mov_Slot_ae8_slot0_encode, 0, Opcode_ae_mov_Slot_ae8_slot2_encode, Opcode_ae_mov_Slot_ae9_slot0_encode, 0, Opcode_ae_mov_Slot_ae9_slot2_encode, Opcode_ae_mov_Slot_ae9_slot3_encode, 0, 0, Opcode_ae_mov_Slot_ae10_slot2_encode, Opcode_ae_mov_Slot_ae10_slot3_encode, 0, 0, Opcode_ae_mov_Slot_ae4_slot2_encode, Opcode_ae_mov_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt64_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt64_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movt64_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movt64_Slot_ae6_slot0_encode, 0, Opcode_ae_movt64_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movt64_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movf64_encode_fns[] = { + 0, 0, 0, Opcode_ae_movf64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movf64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movf64_Slot_ae6_slot0_encode, 0, Opcode_ae_movf64_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movf64_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq56a32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvtq56a32s_Slot_ae_slot0_encode, Opcode_ae_cvtq56a32s_Slot_ae_slot1_encode, 0, 0, Opcode_ae_cvtq56a32s_Slot_ae2_slot0_encode, Opcode_ae_cvtq56a32s_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_cvtq56a32s_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt48a32_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt48a32_Slot_ae_slot0_encode, Opcode_ae_cvt48a32_Slot_ae_slot1_encode, 0, 0, Opcode_ae_cvt48a32_Slot_ae2_slot0_encode, Opcode_ae_cvt48a32_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_cvt48a32_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt64a32_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt64a32_Slot_ae_slot0_encode, Opcode_ae_cvt64a32_Slot_ae_slot1_encode, 0, 0, Opcode_ae_cvt64a32_Slot_ae2_slot0_encode, Opcode_ae_cvt64a32_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_cvt64a32_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq56p32s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvtq56p32s_l_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvtq56p32s_l_Slot_ae_slot3_encode, Opcode_ae_cvtq56p32s_l_Slot_ae2_slot0_encode, Opcode_ae_cvtq56p32s_l_Slot_ae2_slot1_encode, 0, Opcode_ae_cvtq56p32s_l_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq56p32s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvtq56p32s_h_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvtq56p32s_h_Slot_ae_slot3_encode, Opcode_ae_cvtq56p32s_h_Slot_ae2_slot0_encode, Opcode_ae_cvtq56p32s_h_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt64f32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt64f32_h_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvt64f32_h_Slot_ae_slot3_encode, Opcode_ae_cvt64f32_h_Slot_ae2_slot0_encode, Opcode_ae_cvt64f32_h_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt48f32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt48f32_l_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvt48f32_l_Slot_ae_slot3_encode, Opcode_ae_cvt48f32_l_Slot_ae2_slot0_encode, Opcode_ae_cvt48f32_l_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt48f32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt48f32_h_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvt48f32_h_Slot_ae_slot3_encode, Opcode_ae_cvt48f32_h_Slot_ae2_slot0_encode, Opcode_ae_cvt48f32_h_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat48s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sat48s_Slot_ae_slot2_encode, Opcode_ae_sat48s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satq56s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_satq56s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat24s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sat24s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = { + 0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_truncq32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minabs64s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_minabs64s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxabs64s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_maxabs64s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsq32f48sym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsq32f48sym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsq32f48asym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsq32f48asym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae2_slot0_encode, Opcode_ae_trunca32q48_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad32_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad32_l_Slot_ae2_slot0_encode, Opcode_ae_movad32_l_Slot_ae2_slot1_encode, 0, Opcode_ae_movad32_l_Slot_ae3_slot0_encode, Opcode_ae_movad32_l_Slot_ae3_slot1_encode, Opcode_ae_movad32_l_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movad32_l_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad32_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad32_h_Slot_ae2_slot0_encode, Opcode_ae_movad32_h_Slot_ae2_slot1_encode, 0, Opcode_ae_movad32_h_Slot_ae3_slot0_encode, 0, Opcode_ae_movad32_h_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_3_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad16_3_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad16_3_Slot_ae2_slot0_encode, Opcode_ae_movad16_3_Slot_ae2_slot1_encode, 0, Opcode_ae_movad16_3_Slot_ae3_slot0_encode, 0, Opcode_ae_movad16_3_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad16_2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad16_2_Slot_ae2_slot0_encode, Opcode_ae_movad16_2_Slot_ae2_slot1_encode, 0, Opcode_ae_movad16_2_Slot_ae3_slot0_encode, 0, Opcode_ae_movad16_2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_1_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad16_1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad16_1_Slot_ae2_slot0_encode, Opcode_ae_movad16_1_Slot_ae2_slot1_encode, 0, Opcode_ae_movad16_1_Slot_ae3_slot0_encode, 0, Opcode_ae_movad16_1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_0_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad16_0_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad16_0_Slot_ae2_slot0_encode, Opcode_ae_movad16_0_Slot_ae2_slot1_encode, 0, Opcode_ae_movad16_0_Slot_ae3_slot0_encode, 0, Opcode_ae_movad16_0_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movad16_0_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sra64_32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sra64_32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sra64_32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksr32_encode_fns[] = { + 0, 0, 0, Opcode_ae_pksr32_Slot_ae_slot0_encode, 0, Opcode_ae_pksr32_Slot_ae_slot2_encode, 0, Opcode_ae_pksr32_Slot_ae2_slot0_encode, 0, Opcode_ae_pksr32_Slot_ae2_slot2_encode, 0, 0, Opcode_ae_pksr32_Slot_ae5_slot0_encode, 0, Opcode_ae_pksr32_Slot_ae5_slot2_encode, Opcode_ae_pksr32_Slot_ae6_slot0_encode, 0, Opcode_ae_pksr32_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_pksr32_Slot_ae4_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksr24_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_pksr24_Slot_ae_slot2_encode, 0, Opcode_ae_pksr24_Slot_ae2_slot0_encode, 0, Opcode_ae_pksr24_Slot_ae2_slot2_encode, 0, 0, Opcode_ae_pksr24_Slot_ae5_slot0_encode, 0, Opcode_ae_pksr24_Slot_ae5_slot2_encode, Opcode_ae_pksr24_Slot_ae6_slot0_encode, 0, Opcode_ae_pksr24_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_pksr24_Slot_ae4_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksrf32_encode_fns[] = { + 0, 0, 0, Opcode_ae_pksrf32_Slot_ae_slot0_encode, 0, Opcode_ae_pksrf32_Slot_ae_slot2_encode, 0, Opcode_ae_pksrf32_Slot_ae2_slot0_encode, 0, Opcode_ae_pksrf32_Slot_ae2_slot2_encode, 0, 0, Opcode_ae_pksrf32_Slot_ae5_slot0_encode, 0, Opcode_ae_pksrf32_Slot_ae5_slot2_encode, Opcode_ae_pksrf32_Slot_ae6_slot0_encode, 0, Opcode_ae_pksrf32_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_pksrf32_Slot_ae4_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksr16_encode_fns[] = { + 0, 0, 0, Opcode_ae_pksr16_Slot_ae_slot0_encode, 0, Opcode_ae_pksr16_Slot_ae_slot2_encode, 0, Opcode_ae_pksr16_Slot_ae2_slot0_encode, 0, Opcode_ae_pksr16_Slot_ae2_slot2_encode, 0, 0, Opcode_ae_pksr16_Slot_ae5_slot0_encode, 0, Opcode_ae_pksr16_Slot_ae5_slot2_encode, Opcode_ae_pksr16_Slot_ae6_slot0_encode, 0, Opcode_ae_pksr16_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_pksr16_Slot_ae4_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32_encode_fns[] = { + 0, 0, 0, Opcode_ae_add32_Slot_ae_slot0_encode, 0, Opcode_ae_add32_Slot_ae_slot2_encode, Opcode_ae_add32_Slot_ae_slot3_encode, Opcode_ae_add32_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_add32_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub32_Slot_ae_slot0_encode, 0, Opcode_ae_sub32_Slot_ae_slot2_encode, Opcode_ae_sub32_Slot_ae_slot3_encode, Opcode_ae_sub32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsub32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsub32_Slot_ae_slot0_encode, 0, Opcode_ae_addsub32_Slot_ae_slot2_encode, Opcode_ae_addsub32_Slot_ae_slot3_encode, Opcode_ae_addsub32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subadd32_encode_fns[] = { + 0, 0, 0, Opcode_ae_subadd32_Slot_ae_slot0_encode, 0, Opcode_ae_subadd32_Slot_ae_slot2_encode, Opcode_ae_subadd32_Slot_ae_slot3_encode, Opcode_ae_subadd32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add16_encode_fns[] = { + 0, 0, 0, Opcode_ae_add16_Slot_ae_slot0_encode, 0, Opcode_ae_add16_Slot_ae_slot2_encode, Opcode_ae_add16_Slot_ae_slot3_encode, Opcode_ae_add16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub16_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub16_Slot_ae_slot0_encode, 0, Opcode_ae_sub16_Slot_ae_slot2_encode, Opcode_ae_sub16_Slot_ae_slot3_encode, Opcode_ae_sub16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_add32_hl_lh_Slot_ae_slot0_encode, 0, Opcode_ae_add32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_add32_hl_lh_Slot_ae_slot3_encode, Opcode_ae_add32_hl_lh_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsub32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_addsub32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_addsub32_hl_lh_Slot_ae_slot3_encode, Opcode_ae_addsub32_hl_lh_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg32_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg32_Slot_ae_slot0_encode, 0, Opcode_ae_neg32_Slot_ae_slot2_encode, Opcode_ae_neg32_Slot_ae_slot3_encode, Opcode_ae_neg32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_neg32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs32_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs32_Slot_ae_slot0_encode, 0, Opcode_ae_abs32_Slot_ae_slot2_encode, Opcode_ae_abs32_Slot_ae_slot3_encode, Opcode_ae_abs32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_abs32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg32_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_neg32_l_Slot_ae_slot2_encode, Opcode_ae_neg32_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add24s_Slot_ae_slot0_encode, 0, Opcode_ae_add24s_Slot_ae_slot2_encode, Opcode_ae_add24s_Slot_ae_slot3_encode, Opcode_ae_add24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub24s_Slot_ae_slot0_encode, 0, Opcode_ae_sub24s_Slot_ae_slot2_encode, Opcode_ae_sub24s_Slot_ae_slot3_encode, Opcode_ae_sub24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add32s_Slot_ae_slot0_encode, 0, Opcode_ae_add32s_Slot_ae_slot2_encode, Opcode_ae_add32s_Slot_ae_slot3_encode, Opcode_ae_add32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_add32s_Slot_ae3_slot0_encode, 0, Opcode_ae_add32s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, Opcode_ae_add32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub32s_Slot_ae_slot0_encode, 0, Opcode_ae_sub32s_Slot_ae_slot2_encode, Opcode_ae_sub32s_Slot_ae_slot3_encode, Opcode_ae_sub32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sub32s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sub32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsub32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsub32s_Slot_ae_slot0_encode, 0, Opcode_ae_addsub32s_Slot_ae_slot2_encode, Opcode_ae_addsub32s_Slot_ae_slot3_encode, Opcode_ae_addsub32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subadd32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_subadd32s_Slot_ae_slot0_encode, 0, Opcode_ae_subadd32s_Slot_ae_slot2_encode, Opcode_ae_subadd32s_Slot_ae_slot3_encode, Opcode_ae_subadd32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add16s_Slot_ae_slot0_encode, 0, Opcode_ae_add16s_Slot_ae_slot2_encode, Opcode_ae_add16s_Slot_ae_slot3_encode, Opcode_ae_add16s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_add16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_add16s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub16s_Slot_ae_slot0_encode, 0, Opcode_ae_sub16s_Slot_ae_slot2_encode, Opcode_ae_sub16s_Slot_ae_slot3_encode, Opcode_ae_sub16s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sub16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sub16s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_add32s_hl_lh_Slot_ae_slot0_encode, 0, Opcode_ae_add32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_add32s_hl_lh_Slot_ae_slot3_encode, Opcode_ae_add32s_hl_lh_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsub32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_addsub32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_addsub32s_hl_lh_Slot_ae_slot3_encode, Opcode_ae_addsub32s_hl_lh_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg24s_Slot_ae_slot0_encode, 0, Opcode_ae_neg24s_Slot_ae_slot2_encode, Opcode_ae_neg24s_Slot_ae_slot3_encode, Opcode_ae_neg24s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_neg24s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs24s_Slot_ae_slot0_encode, 0, Opcode_ae_abs24s_Slot_ae_slot2_encode, Opcode_ae_abs24s_Slot_ae_slot3_encode, Opcode_ae_abs24s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_abs24s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg32s_Slot_ae_slot0_encode, 0, Opcode_ae_neg32s_Slot_ae_slot2_encode, Opcode_ae_neg32s_Slot_ae_slot3_encode, Opcode_ae_neg32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_neg32s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_neg32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs32s_Slot_ae_slot0_encode, 0, Opcode_ae_abs32s_Slot_ae_slot2_encode, Opcode_ae_abs32s_Slot_ae_slot3_encode, Opcode_ae_abs32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_abs32s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_abs32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg16s_Slot_ae_slot0_encode, 0, Opcode_ae_neg16s_Slot_ae_slot2_encode, Opcode_ae_neg16s_Slot_ae_slot3_encode, Opcode_ae_neg16s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_neg16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_neg16s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs16s_Slot_ae_slot0_encode, 0, Opcode_ae_abs16s_Slot_ae_slot2_encode, Opcode_ae_abs16s_Slot_ae_slot3_encode, Opcode_ae_abs16s_Slot_ae2_slot0_encode, 0, Opcode_ae_abs16s_Slot_ae2_slot2_encode, Opcode_ae_abs16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_abs16s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_abs16s_Slot_ae4_slot2_encode, Opcode_ae_abs16s_Slot_ae4_slot3_encode, Opcode_ae_abs16s_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs16_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs16_Slot_ae_slot0_encode, 0, Opcode_ae_abs16_Slot_ae_slot2_encode, Opcode_ae_abs16_Slot_ae_slot3_encode, Opcode_ae_abs16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16js_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc16js_h_Slot_ae_slot2_encode, Opcode_ae_mulc16js_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc16js_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16js_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc16js_l_Slot_ae_slot2_encode, Opcode_ae_mulc16js_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc16js_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16js_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac16js_h_Slot_ae_slot2_encode, Opcode_ae_mulac16js_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac16js_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16js_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac16js_l_Slot_ae_slot2_encode, Opcode_ae_mulac16js_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac16js_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt16_encode_fns[] = { + 0, 0, 0, Opcode_ae_lt16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lt16_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_lt16_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_lt16_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lt16_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le16_encode_fns[] = { + 0, 0, 0, Opcode_ae_le16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_le16_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_le16_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_le16_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_le16_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq16_encode_fns[] = { + 0, 0, 0, Opcode_ae_eq16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_eq16_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_eq16_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_eq16_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_eq16_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt32_encode_fns[] = { + 0, 0, 0, Opcode_ae_lt32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lt32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_lt32_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_lt32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lt32_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le32_encode_fns[] = { + 0, 0, 0, Opcode_ae_le32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_le32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_le32_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_le32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_le32_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq32_encode_fns[] = { + 0, 0, 0, Opcode_ae_eq32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_eq32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_eq32_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_eq32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_eq32_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_min32_encode_fns[] = { + 0, 0, 0, Opcode_ae_min32_Slot_ae_slot0_encode, 0, Opcode_ae_min32_Slot_ae_slot2_encode, Opcode_ae_min32_Slot_ae_slot3_encode, Opcode_ae_min32_Slot_ae2_slot0_encode, 0, Opcode_ae_min32_Slot_ae2_slot2_encode, Opcode_ae_min32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_min32_Slot_ae4_slot2_encode, Opcode_ae_min32_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_max32_encode_fns[] = { + 0, 0, 0, Opcode_ae_max32_Slot_ae_slot0_encode, 0, Opcode_ae_max32_Slot_ae_slot2_encode, Opcode_ae_max32_Slot_ae_slot3_encode, Opcode_ae_max32_Slot_ae2_slot0_encode, 0, Opcode_ae_max32_Slot_ae2_slot2_encode, Opcode_ae_max32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_max32_Slot_ae4_slot2_encode, Opcode_ae_max32_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minmax32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_minmax32_Slot_ae_slot2_encode, Opcode_ae_minmax32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minmax16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_minmax16_Slot_ae_slot2_encode, Opcode_ae_minmax16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_min16_encode_fns[] = { + 0, 0, 0, Opcode_ae_min16_Slot_ae_slot0_encode, 0, Opcode_ae_min16_Slot_ae_slot2_encode, Opcode_ae_min16_Slot_ae_slot3_encode, Opcode_ae_min16_Slot_ae2_slot0_encode, 0, Opcode_ae_min16_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_min16_Slot_ae4_slot2_encode, Opcode_ae_min16_Slot_ae4_slot3_encode, Opcode_ae_min16_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_max16_encode_fns[] = { + 0, 0, 0, Opcode_ae_max16_Slot_ae_slot0_encode, 0, Opcode_ae_max16_Slot_ae_slot2_encode, Opcode_ae_max16_Slot_ae_slot3_encode, Opcode_ae_max16_Slot_ae2_slot0_encode, 0, Opcode_ae_max16_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_max16_Slot_ae4_slot2_encode, Opcode_ae_max16_Slot_ae4_slot3_encode, Opcode_ae_max16_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_add64_encode_fns[] = { + 0, 0, 0, Opcode_ae_add64_Slot_ae_slot0_encode, 0, Opcode_ae_add64_Slot_ae_slot2_encode, Opcode_ae_add64_Slot_ae_slot3_encode, Opcode_ae_add64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub64_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub64_Slot_ae_slot0_encode, 0, Opcode_ae_sub64_Slot_ae_slot2_encode, Opcode_ae_sub64_Slot_ae_slot3_encode, Opcode_ae_sub64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg64_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg64_Slot_ae_slot0_encode, 0, Opcode_ae_neg64_Slot_ae_slot2_encode, Opcode_ae_neg64_Slot_ae_slot3_encode, Opcode_ae_neg64_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_neg64_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs64_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs64_Slot_ae_slot0_encode, 0, Opcode_ae_abs64_Slot_ae_slot2_encode, Opcode_ae_abs64_Slot_ae_slot3_encode, Opcode_ae_abs64_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_abs64_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot0_encode, 0, Opcode_ae_addsq56s_Slot_ae_slot2_encode, Opcode_ae_addsq56s_Slot_ae_slot3_encode, Opcode_ae_addsq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot0_encode, 0, Opcode_ae_subsq56s_Slot_ae_slot2_encode, Opcode_ae_subsq56s_Slot_ae_slot3_encode, Opcode_ae_subsq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add64s_Slot_ae_slot0_encode, 0, Opcode_ae_add64s_Slot_ae_slot2_encode, Opcode_ae_add64s_Slot_ae_slot3_encode, Opcode_ae_add64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub64s_Slot_ae_slot0_encode, 0, Opcode_ae_sub64s_Slot_ae_slot2_encode, Opcode_ae_sub64s_Slot_ae_slot3_encode, Opcode_ae_sub64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot0_encode, 0, Opcode_ae_negsq56s_Slot_ae_slot2_encode, Opcode_ae_negsq56s_Slot_ae_slot3_encode, Opcode_ae_negsq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot0_encode, 0, Opcode_ae_abssq56s_Slot_ae_slot2_encode, Opcode_ae_abssq56s_Slot_ae_slot3_encode, Opcode_ae_abssq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg64s_Slot_ae_slot0_encode, 0, Opcode_ae_neg64s_Slot_ae_slot2_encode, Opcode_ae_neg64s_Slot_ae_slot3_encode, Opcode_ae_neg64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs64s_Slot_ae_slot0_encode, 0, Opcode_ae_abs64s_Slot_ae_slot2_encode, Opcode_ae_abs64s_Slot_ae_slot3_encode, Opcode_ae_abs64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_and_encode_fns[] = { + 0, 0, 0, Opcode_ae_and_Slot_ae_slot0_encode, 0, 0, Opcode_ae_and_Slot_ae_slot3_encode, Opcode_ae_and_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_and_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nand_encode_fns[] = { + 0, 0, 0, Opcode_ae_nand_Slot_ae_slot0_encode, 0, 0, Opcode_ae_nand_Slot_ae_slot3_encode, Opcode_ae_nand_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_or_encode_fns[] = { + 0, 0, 0, Opcode_ae_or_Slot_ae_slot0_encode, 0, 0, Opcode_ae_or_Slot_ae_slot3_encode, Opcode_ae_or_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_or_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_xor_encode_fns[] = { + 0, 0, 0, Opcode_ae_xor_Slot_ae_slot0_encode, 0, 0, Opcode_ae_xor_Slot_ae_slot3_encode, Opcode_ae_xor_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_xor_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai24_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai24_Slot_ae_slot3_encode, Opcode_ae_slai24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srli24_Slot_ae_slot3_encode, Opcode_ae_srli24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai24_Slot_ae_slot3_encode, Opcode_ae_srai24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas24_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas24_Slot_ae_slot3_encode, Opcode_ae_slas24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srls24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srls24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srls24_Slot_ae_slot3_encode, Opcode_ae_srls24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sras24_encode_fns[] = { + 0, 0, 0, Opcode_ae_sras24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sras24_Slot_ae_slot3_encode, Opcode_ae_sras24_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sras24_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai16_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai16_Slot_ae_slot3_encode, Opcode_ae_srai16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai16r_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai16r_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai16r_Slot_ae_slot3_encode, Opcode_ae_srai16r_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai32_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai32_Slot_ae_slot3_encode, Opcode_ae_slai32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli32_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srli32_Slot_ae_slot3_encode, Opcode_ae_srli32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai32_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai32_Slot_ae_slot3_encode, Opcode_ae_srai32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai32r_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai32r_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai32r_Slot_ae_slot3_encode, Opcode_ae_srai32r_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas32_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas32_Slot_ae_slot3_encode, Opcode_ae_slas32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srls32_encode_fns[] = { + 0, 0, 0, Opcode_ae_srls32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srls32_Slot_ae_slot3_encode, Opcode_ae_srls32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sras32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sras32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sras32_Slot_ae_slot3_encode, Opcode_ae_sras32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa32_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srla32_encode_fns[] = { + 0, 0, 0, Opcode_ae_srla32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srla32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_srla32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai16s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai16s_Slot_ae_slot3_encode, Opcode_ae_slai16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa16s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa16s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slaa16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa16s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa16s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sraa16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa16rs_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa16rs_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa16rs_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sraa16rs_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai24s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai24s_Slot_ae_slot3_encode, Opcode_ae_slai24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas24s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas24s_Slot_ae_slot3_encode, Opcode_ae_slas24s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slas24s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai32s_Slot_ae_slot3_encode, Opcode_ae_slai32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas32s_Slot_ae_slot3_encode, Opcode_ae_slas32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa32s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slaa32s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa32s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sraa32s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32rs_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa32rs_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa32rs_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slasq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_slasq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slasq56_Slot_ae_slot3_encode, Opcode_ae_slasq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot3_encode, Opcode_ae_srlsq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srasq56_Slot_ae_slot3_encode, Opcode_ae_srasq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaaq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaaq56_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaaq56_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slaaq56_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sraaq56_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai64_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai64_Slot_ae_slot3_encode, Opcode_ae_slai64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli64_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srli64_Slot_ae_slot3_encode, Opcode_ae_srli64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai64_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai64_Slot_ae_slot3_encode, Opcode_ae_srai64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas64_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas64_Slot_ae_slot3_encode, Opcode_ae_slas64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srls64_encode_fns[] = { + 0, 0, 0, Opcode_ae_srls64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srls64_Slot_ae_slot3_encode, Opcode_ae_srls64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sras64_encode_fns[] = { + 0, 0, 0, Opcode_ae_sras64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sras64_Slot_ae_slot3_encode, Opcode_ae_sras64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa64_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa64_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slaa64_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srla64_encode_fns[] = { + 0, 0, 0, Opcode_ae_srla64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srla64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa64_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaisq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaisq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slaisq56s_Slot_ae_slot3_encode, Opcode_ae_slaisq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slassq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slassq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slassq56s_Slot_ae_slot3_encode, Opcode_ae_slassq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaasq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaasq56s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaasq56s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slaasq56s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai64s_Slot_ae_slot3_encode, Opcode_ae_slai64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas64s_Slot_ae_slot3_encode, Opcode_ae_slas64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa64s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt64_encode_fns[] = { + 0, 0, 0, Opcode_ae_lt64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lt64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lt64_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lt64_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le64_encode_fns[] = { + 0, 0, 0, Opcode_ae_le64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_le64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_le64_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_le64_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq64_encode_fns[] = { + 0, 0, 0, Opcode_ae_eq64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_eq64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_eq64_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_eq64_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_max64_encode_fns[] = { + 0, 0, 0, Opcode_ae_max64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_max64_Slot_ae_slot3_encode, Opcode_ae_max64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_min64_encode_fns[] = { + 0, 0, 0, Opcode_ae_min64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_min64_Slot_ae_slot3_encode, Opcode_ae_min64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsa64_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsa64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsa64_Slot_ae2_slot0_encode, Opcode_ae_nsa64_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsaz16_0_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsaz16_0_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsaz16_0_Slot_ae2_slot0_encode, Opcode_ae_nsaz16_0_Slot_ae2_slot1_encode, 0, Opcode_ae_nsaz16_0_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsaz32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsaz32_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsaz32_l_Slot_ae2_slot0_encode, Opcode_ae_nsaz32_l_Slot_ae2_slot1_encode, 0, Opcode_ae_nsaz32_l_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_ll_Slot_ae_slot2_encode, Opcode_ae_muls32f48p16s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32f48p16s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32s_ll_Slot_ae_slot2_encode, Opcode_ae_mulf32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32_ll_Slot_ae_slot2_encode, Opcode_ae_mul32_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32r_ll_Slot_ae_slot2_encode, Opcode_ae_mulf32r_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32r_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32r_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32ra_ll_Slot_ae_slot2_encode, Opcode_ae_mulf32ra_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32ra_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_lh_Slot_ae_slot2_encode, Opcode_ae_muls32f48p16s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32f48p16s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32s_lh_Slot_ae_slot2_encode, Opcode_ae_mulf32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32_lh_Slot_ae_slot2_encode, Opcode_ae_mul32_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32r_lh_Slot_ae_slot2_encode, Opcode_ae_mulf32r_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32r_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32r_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32ra_lh_Slot_ae_slot2_encode, Opcode_ae_mulf32ra_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32ra_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_hh_Slot_ae_slot2_encode, Opcode_ae_muls32f48p16s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32f48p16s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32s_hh_Slot_ae_slot2_encode, Opcode_ae_mulf32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32_hh_Slot_ae_slot2_encode, Opcode_ae_mul32_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32r_hh_Slot_ae_slot2_encode, Opcode_ae_mulf32r_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32r_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32r_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32ra_hh_Slot_ae_slot2_encode, Opcode_ae_mulf32ra_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32ra_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_ll_Slot_ae_slot2_encode, Opcode_ae_mulas32f48p16s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulas32f48p16s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32s_ll_Slot_ae_slot2_encode, Opcode_ae_mulaf32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32_ll_Slot_ae_slot2_encode, Opcode_ae_mula32_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32r_ll_Slot_ae_slot2_encode, Opcode_ae_mulaf32r_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32r_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32r_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32ra_ll_Slot_ae_slot2_encode, Opcode_ae_mulaf32ra_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32ra_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_lh_Slot_ae_slot2_encode, Opcode_ae_mulas32f48p16s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulas32f48p16s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32s_lh_Slot_ae_slot2_encode, Opcode_ae_mulaf32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32_lh_Slot_ae_slot2_encode, Opcode_ae_mula32_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32r_lh_Slot_ae_slot2_encode, Opcode_ae_mulaf32r_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32r_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32r_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32ra_lh_Slot_ae_slot2_encode, Opcode_ae_mulaf32ra_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32ra_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_hh_Slot_ae_slot2_encode, Opcode_ae_mulas32f48p16s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulas32f48p16s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32s_hh_Slot_ae_slot2_encode, Opcode_ae_mulaf32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32_hh_Slot_ae_slot2_encode, Opcode_ae_mula32_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32r_hh_Slot_ae_slot2_encode, Opcode_ae_mulaf32r_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32r_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32r_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32ra_hh_Slot_ae_slot2_encode, Opcode_ae_mulaf32ra_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32ra_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_ll_Slot_ae_slot2_encode, Opcode_ae_mulss32f48p16s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulss32f48p16s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32s_ll_Slot_ae_slot2_encode, Opcode_ae_mulsf32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32_ll_Slot_ae_slot2_encode, Opcode_ae_muls32_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32r_ll_Slot_ae_slot2_encode, Opcode_ae_mulsf32r_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32r_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32r_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32ra_ll_Slot_ae_slot2_encode, Opcode_ae_mulsf32ra_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32ra_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_lh_Slot_ae_slot2_encode, Opcode_ae_mulss32f48p16s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulss32f48p16s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32s_lh_Slot_ae_slot2_encode, Opcode_ae_mulsf32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32_lh_Slot_ae_slot2_encode, Opcode_ae_muls32_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32r_lh_Slot_ae_slot2_encode, Opcode_ae_mulsf32r_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32r_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32r_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32ra_lh_Slot_ae_slot2_encode, Opcode_ae_mulsf32ra_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32ra_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_hh_Slot_ae_slot2_encode, Opcode_ae_mulss32f48p16s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulss32f48p16s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32s_hh_Slot_ae_slot2_encode, Opcode_ae_mulsf32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32_hh_Slot_ae_slot2_encode, Opcode_ae_muls32_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32r_hh_Slot_ae_slot2_encode, Opcode_ae_mulsf32r_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32r_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32r_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32ra_hh_Slot_ae_slot2_encode, Opcode_ae_mulsf32ra_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32ra_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32u_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32u_ll_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mul32u_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32u_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32u_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32u_ll_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mula32u_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32u_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32u_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32u_ll_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_muls32u_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32u_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_33_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_33_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_33_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_22_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_22_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_32_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_21_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_21_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_21_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_31_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_31_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_31_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_30_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_30_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_30_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_10_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_10_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_10_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_20_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_20_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_20_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_11_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_11_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_11_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_00_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf16ss_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf16ss_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_33_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_33_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_33_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_22_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_22_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_32_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_21_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_21_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_21_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_31_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_31_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_31_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_30_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_30_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_30_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_10_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_10_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_10_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_20_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_20_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_20_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_11_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_11_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_11_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_00_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf16ss_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf16ss_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_33_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_33_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_33_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_22_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_22_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_32_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_21_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_21_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_21_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_31_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_31_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_31_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_30_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_30_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_30_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_10_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_10_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_10_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_20_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_20_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_20_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_11_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_11_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_11_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_00_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf16ss_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf16ss_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16s_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul16s_00_Slot_ae_slot2_encode, Opcode_ae_mul16s_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul16s_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul16s_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16s_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula16s_00_Slot_ae_slot2_encode, Opcode_ae_mula16s_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula16s_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula16s_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls16s_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls16s_00_Slot_ae_slot2_encode, Opcode_ae_muls16s_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls16s_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls16s_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_33_22_Slot_ae_slot2_encode, Opcode_ae_mulaafd16ss_33_22_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_13_02_Slot_ae_slot2_encode, Opcode_ae_mulaafd16ss_13_02_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_11_00_Slot_ae_slot2_encode, Opcode_ae_mulaafd16ss_11_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_33_22_Slot_ae_slot2_encode, Opcode_ae_mulssfd16ss_33_22_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_13_02_Slot_ae_slot2_encode, Opcode_ae_mulssfd16ss_13_02_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_11_00_Slot_ae_slot2_encode, Opcode_ae_mulssfd16ss_11_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_33_22_Slot_ae_slot2_encode, Opcode_ae_mulzaafd16ss_33_22_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_13_02_Slot_ae_slot2_encode, Opcode_ae_mulzaafd16ss_13_02_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_11_00_Slot_ae_slot2_encode, Opcode_ae_mulzaafd16ss_11_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_33_22_Slot_ae_slot2_encode, Opcode_ae_mulzssfd16ss_33_22_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_13_02_Slot_ae_slot2_encode, Opcode_ae_mulzssfd16ss_13_02_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_11_00_Slot_ae_slot2_encode, Opcode_ae_mulzssfd16ss_11_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf48q32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf48q32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulf48q32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf48q32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf48q32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf48q32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf48q32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulf48q32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf48q32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf48q32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulq32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulq32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf48q32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulaf48q32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf48q32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf48q32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulaf48q32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf48q32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf48q32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulsf48q32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf48q32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf48q32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulsf48q32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf48q32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24x2ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp24x2ra_Slot_ae_slot2_encode, Opcode_ae_mulfp24x2ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp24x2ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp24x2ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24x2r_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp24x2r_Slot_ae_slot2_encode, Opcode_ae_mulfp24x2r_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp24x2r_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp24x2r_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24x2ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp24x2ra_Slot_ae_slot2_encode, Opcode_ae_mulafp24x2ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp24x2ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp24x2ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24x2r_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp24x2r_Slot_ae_slot2_encode, Opcode_ae_mulafp24x2r_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp24x2r_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp24x2r_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24x2ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp24x2ra_Slot_ae_slot2_encode, Opcode_ae_mulsfp24x2ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp24x2ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp24x2ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24x2r_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp24x2r_Slot_ae_slot2_encode, Opcode_ae_mulsfp24x2r_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp24x2r_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp24x2r_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaad32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaad32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzasd32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzasd32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsad32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzsad32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssd32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzssd32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaafd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaad32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaafd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaad32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulasfd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulasd32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulasfd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulasd32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsafd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulsafd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsad32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulsad32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssfd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssd32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulssfd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulssd32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l0_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l0_Slot_ae_slot2_encode, Opcode_ae_mul32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l1_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l1_Slot_ae_slot2_encode, Opcode_ae_mul32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l2_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l2_Slot_ae_slot2_encode, Opcode_ae_mul32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l3_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l3_Slot_ae_slot2_encode, Opcode_ae_mul32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h0_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h0_Slot_ae_slot2_encode, Opcode_ae_mul32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h1_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h1_Slot_ae_slot2_encode, Opcode_ae_mul32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h2_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h2_Slot_ae_slot2_encode, Opcode_ae_mul32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h3_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h3_Slot_ae_slot2_encode, Opcode_ae_mul32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l0_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l0_Slot_ae_slot2_encode, Opcode_ae_mula32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l1_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l1_Slot_ae_slot2_encode, Opcode_ae_mula32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l2_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l2_Slot_ae_slot2_encode, Opcode_ae_mula32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l3_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l3_Slot_ae_slot2_encode, Opcode_ae_mula32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h0_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h0_Slot_ae_slot2_encode, Opcode_ae_mula32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h1_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h1_Slot_ae_slot2_encode, Opcode_ae_mula32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h2_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h2_Slot_ae_slot2_encode, Opcode_ae_mula32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h3_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h3_Slot_ae_slot2_encode, Opcode_ae_mula32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l0_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l0_Slot_ae_slot2_encode, Opcode_ae_muls32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l1_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l1_Slot_ae_slot2_encode, Opcode_ae_muls32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l2_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l2_Slot_ae_slot2_encode, Opcode_ae_muls32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l3_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l3_Slot_ae_slot2_encode, Opcode_ae_muls32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h0_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h0_Slot_ae_slot2_encode, Opcode_ae_muls32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h1_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h1_Slot_ae_slot2_encode, Opcode_ae_muls32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h2_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h2_Slot_ae_slot2_encode, Opcode_ae_muls32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h3_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h3_Slot_ae_slot2_encode, Opcode_ae_muls32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulaad32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulaad32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulasd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulasd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsad32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulsad32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsad32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulsad32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulssd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulssd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsad32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzsad32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsad32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzsad32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae_slot2_encode, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae_slot2_encode, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae_slot2_encode, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae_slot2_encode, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h2_l3_Slot_ae_slot2_encode, Opcode_ae_mulaad32x16_h2_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h0_l1_Slot_ae_slot2_encode, Opcode_ae_mulaad32x16_h0_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x16x2_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp32x16x2_h_Slot_ae_slot2_encode, Opcode_ae_mulp32x16x2_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp32x16x2_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp32x16x2_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2rs_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_h_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2rs_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2rs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2ras_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_h_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2ras_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_h_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x16x2_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp32x16x2_l_Slot_ae_slot2_encode, Opcode_ae_mulp32x16x2_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp32x16x2_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp32x16x2_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2rs_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_l_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2rs_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2rs_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2ras_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_l_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2ras_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_l_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x16x2_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap32x16x2_h_Slot_ae_slot2_encode, Opcode_ae_mulap32x16x2_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap32x16x2_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap32x16x2_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2rs_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_h_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2rs_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2rs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2ras_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_h_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2ras_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_h_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x16x2_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap32x16x2_l_Slot_ae_slot2_encode, Opcode_ae_mulap32x16x2_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap32x16x2_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap32x16x2_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2rs_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_l_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2rs_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2rs_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2ras_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_l_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2ras_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_l_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x16x2_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_h_Slot_ae_slot2_encode, Opcode_ae_mulsp32x16x2_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp32x16x2_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2rs_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2ras_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_h_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x16x2_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_l_Slot_ae_slot2_encode, Opcode_ae_mulsp32x16x2_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp32x16x2_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2rs_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2ras_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_l_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp32x2_Slot_ae_slot2_encode, Opcode_ae_mulp32x2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp32x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp32x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2rs_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2rs_Slot_ae_slot2_encode, Opcode_ae_mulfp32x2rs_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x2rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x2rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2ras_Slot_ae_slot2_encode, Opcode_ae_mulfp32x2ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x2ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x2ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2ts_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2ts_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulfp32x2ts_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x2ts_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x2t_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp32x2t_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulp32x2t_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp32x2t_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap32x2_Slot_ae_slot2_encode, Opcode_ae_mulap32x2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap32x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap32x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2rs_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2rs_Slot_ae_slot2_encode, Opcode_ae_mulafp32x2rs_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x2rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x2rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2ras_Slot_ae_slot2_encode, Opcode_ae_mulafp32x2ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x2ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x2ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2ts_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2ts_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulafp32x2ts_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x2ts_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x2t_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap32x2t_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulap32x2t_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap32x2t_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp32x2_Slot_ae_slot2_encode, Opcode_ae_mulsp32x2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp32x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp32x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2rs_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2rs_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x2rs_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x2rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x2rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2ras_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x2ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x2ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x2ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2ts_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2ts_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulsfp32x2ts_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x2ts_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x2t_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp32x2t_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulsp32x2t_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp32x2t_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp16x4s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp16x4s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp16x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp16x4ras_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc32_Slot_ae_slot2_encode, Opcode_ae_mulc32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc32_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulc32_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc24ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc24ra_Slot_ae_slot2_encode, Opcode_ae_mulfc24ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc24ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfc24ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32ras_Slot_ae_slot2_encode, Opcode_ae_mulfc32ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc32ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfc32ras_Slot_ae5_slot2_encode, 0, 0, Opcode_ae_mulfc32ras_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfc32ras_Slot_ae4_slot2_encode, Opcode_ae_mulfc32ras_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32x16_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc32x16_l_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulc32x16_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulc32x16_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32x16ras_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae_slot2_encode, Opcode_ae_mulfc32x16ras_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae5_slot2_encode, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32x16_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc32x16_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulc32x16_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulc32x16_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32x16ras_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae_slot2_encode, Opcode_ae_mulfc32x16ras_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae5_slot2_encode, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac32_Slot_ae_slot2_encode, Opcode_ae_mulac32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac32_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulac32_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc24ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc24ra_Slot_ae_slot2_encode, Opcode_ae_mulafc24ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc24ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafc24ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32ras_Slot_ae_slot2_encode, Opcode_ae_mulafc32ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc32ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafc32ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32x16_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac32x16_l_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulac32x16_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulac32x16_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32x16ras_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_l_Slot_ae_slot2_encode, Opcode_ae_mulafc32x16ras_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc32x16ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32x16_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac32x16_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulac32x16_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulac32x16_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32x16ras_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_h_Slot_ae_slot2_encode, Opcode_ae_mulafc32x16ras_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc32x16ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16x4ss_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf16x4ss_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16x4ss_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf16x4ss_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16x4ss_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf16x4ss_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul16x4s_Slot_ae_slot2_encode, Opcode_ae_mul16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul16x4s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula16x4s_Slot_ae_slot2_encode, Opcode_ae_mula16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls16x4s_Slot_ae_slot2_encode, Opcode_ae_muls16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul16x4_Slot_ae_slot2_encode, Opcode_ae_mul16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul16x4_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula16x4_Slot_ae_slot2_encode, Opcode_ae_mula16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls16x4_Slot_ae_slot2_encode, Opcode_ae_muls16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2s_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2s_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2s_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x2s_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2ra_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2ra_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2ra_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x2ra_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2s_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2s_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2s_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x2s_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2ra_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2ra_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2ra_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x2ra_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2s_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2s_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2s_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x2s_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2ra_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2ra_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2ra_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x2ra_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2s_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2s_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2s_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x2s_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2ra_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2ra_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2ra_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x2ra_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc16s_h_Slot_ae_slot2_encode, Opcode_ae_mulc16s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc16s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc16s_l_Slot_ae_slot2_encode, Opcode_ae_mulc16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac16s_h_Slot_ae_slot2_encode, Opcode_ae_mulac16s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac16s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac16s_l_Slot_ae_slot2_encode, Opcode_ae_mulac16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc16ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc16ras_Slot_ae_slot2_encode, Opcode_ae_mulfc16ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc16ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc16ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc16ras_Slot_ae_slot2_encode, Opcode_ae_mulafc16ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc16ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16js_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul16js_Slot_ae_slot3_encode, Opcode_ae_mul16js_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng16ras_s1_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot0_encode, 0, Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot2_encode, Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot3_encode, Opcode_ae_addandsubrng16ras_s1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng16ras_s1_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsubrng16ras_s1_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng16ras_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot0_encode, 0, Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot2_encode, Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot3_encode, Opcode_ae_addandsubrng16ras_s2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng16ras_s2_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsubrng16ras_s2_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_conj16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_conj16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq16x2_fir_3_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_3_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_3_Slot_ae7_slot2_encode, Opcode_ae_mulfq16x2_fir_3_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq16x2_fir_2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_2_Slot_ae7_slot2_encode, Opcode_ae_mulfq16x2_fir_2_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq16x2_fir_1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_1_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_1_Slot_ae7_slot2_encode, Opcode_ae_mulfq16x2_fir_1_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq16x2_fir_0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_0_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_0_Slot_ae7_slot2_encode, Opcode_ae_mulfq16x2_fir_0_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq16x2_fir_3_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_3_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_3_Slot_ae7_slot2_encode, Opcode_ae_mulafq16x2_fir_3_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq16x2_fir_2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_2_Slot_ae7_slot2_encode, Opcode_ae_mulafq16x2_fir_2_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq16x2_fir_1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_1_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_1_Slot_ae7_slot2_encode, Opcode_ae_mulafq16x2_fir_1_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq16x2_fir_0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_0_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_0_Slot_ae7_slot2_encode, Opcode_ae_mulafq16x2_fir_0_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaafq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaafq32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaafq32x16_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaafq32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaafq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaafq32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaafq32x16_Slot_ae7_slot2_encode, Opcode_ae_mulaaaafq32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaaq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaaq32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaaq32x16_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaaq32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaaq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaaq32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaaq32x16_Slot_ae7_slot2_encode, Opcode_ae_mulaaaaq32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul16_00_Slot_ae_slot2_encode, Opcode_ae_mul16_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul16_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul16_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula16_00_Slot_ae_slot2_encode, Opcode_ae_mula16_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula16_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula16_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaaq16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaaaaq16_Slot_ae_slot2_encode, Opcode_ae_mulzaaaaq16_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaaaaq16_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaaaaq16_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaaq16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaaaaq16_Slot_ae_slot2_encode, Opcode_ae_mulaaaaq16_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaaaaq16_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaaaaq16_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_div64d32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_div64d32_h_Slot_ae_slot0_encode, 0, Opcode_ae_div64d32_h_Slot_ae_slot2_encode, Opcode_ae_div64d32_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_div64d32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_div64d32_l_Slot_ae_slot0_encode, 0, Opcode_ae_div64d32_l_Slot_ae_slot2_encode, Opcode_ae_div64d32_l_Slot_ae_slot3_encode, 0, 0, 0, Opcode_ae_div64d32_l_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sha32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl32t_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16t_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16c_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16c_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16c_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16c_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldsht_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = { + 0, 0, 0, Opcode_ae_lb_Slot_ae_slot0_encode, Opcode_ae_lb_Slot_ae_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_lb_Slot_ae3_slot0_encode, Opcode_ae_lb_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = { + 0, 0, 0, Opcode_ae_lbi_Slot_ae_slot0_encode, Opcode_ae_lbi_Slot_ae_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_lbi_Slot_ae3_slot0_encode, Opcode_ae_lbi_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbk_Slot_ae3_slot0_encode, Opcode_ae_lbk_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbki_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbs_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbsi_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbsi_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = { + 0, 0, 0, Opcode_ae_db_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_db_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = { + 0, 0, 0, Opcode_ae_dbi_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_dbi_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_db_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_dbi_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_db_ic1_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_dbi_ic1_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_db_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_dbi_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_ardecnorm16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_ardecnorm16_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbki_dbi_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbki_dbi_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbki_dbi_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbki_dbi_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbki_dbi_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbki_dbi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbi_dbi_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbi_dbi_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbi_dbi_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbi_dbi_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbi_dbi_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbi_dbi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbk_db_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbk_db_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbk_db_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbk_db_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbk_db_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbk_db_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lb_db_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lb_db_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lb_db_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lb_db_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lb_db_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lb_db_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vlel32t_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vlel16t_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sb_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbi_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vles16c_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbf_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sb_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbi_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vles16c_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbf_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sb_ic1_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbi_ic1_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vles16c_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbf_ic1_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sb_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbi_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vles16c_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbf_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sext32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movae_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movae_Slot_ae3_slot0_encode, Opcode_ae_movae_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movea_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movea_Slot_ae3_slot0_encode, Opcode_ae_movea_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_moveep_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_moveep_Slot_ae_slot2_encode, Opcode_ae_moveep_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext72_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sext72_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add72_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_add72_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub72_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sub72_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add72x64_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_add72x64_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub72x64_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sub72x64_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32ep_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32ep_hh_Slot_ae_slot2_encode, Opcode_ae_mul32ep_hh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32ep_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32ep_hh_Slot_ae_slot2_encode, Opcode_ae_mula32ep_hh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32ep_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32ep_hh_Slot_ae_slot2_encode, Opcode_ae_muls32ep_hh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32ep_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaad32ep_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32ep_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssd32ep_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32ep_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaad32ep_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32ep_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssd32ep_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32usep_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32usep_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaad32usep_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32usep_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32usep_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaad32usep_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32usep_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32usep_lh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32usep_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32usep_lh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32usep_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32usep_ll_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32usep_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32usep_ll_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai72_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_srai72_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai72_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_slai72_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat64s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sat64s_Slot_ae_slot2_encode, Opcode_ae_sat64s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16si_n_encode_fns[] = { + 0, 0, Opcode_ae_l16si_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16ui_n_encode_fns[] = { + 0, 0, Opcode_ae_l16ui_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16i_n_encode_fns[] = { + 0, 0, Opcode_ae_s16i_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lalign128_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_lalign128_i_Slot_ae_slot0_encode, Opcode_ae_lalign128_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_lalign128_i_Slot_ae2_slot0_encode, Opcode_ae_lalign128_i_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lalign128_i_Slot_ae7_slot0_encode, Opcode_ae_lalign128_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_lalign128_i_Slot_ae8_slot0_encode, Opcode_ae_lalign128_i_Slot_ae8_slot1_encode, 0, Opcode_ae_lalign128_i_Slot_ae9_slot0_encode, Opcode_ae_lalign128_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_lalign128_i_Slot_ae10_slot0_encode, Opcode_ae_lalign128_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_salign128_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_salign128_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_salign128_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la128_pp_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_la128_pp_Slot_ae_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la128_pp_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa128pos_fp_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa128pos_fp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa128pos_fp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x4s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x4s_ip_Slot_ae_slot0_encode, Opcode_ae_la8x4s_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x4s_ip_Slot_ae2_slot0_encode, Opcode_ae_la8x4s_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x4s_ip_Slot_ae8_slot0_encode, Opcode_ae_la8x4s_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x4s_ip_Slot_ae9_slot0_encode, Opcode_ae_la8x4s_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x4s_ip_Slot_ae10_slot0_encode, Opcode_ae_la8x4s_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x4u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x4u_ip_Slot_ae_slot0_encode, Opcode_ae_la8x4u_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x4u_ip_Slot_ae2_slot0_encode, Opcode_ae_la8x4u_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x4u_ip_Slot_ae8_slot0_encode, Opcode_ae_la8x4u_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x4u_ip_Slot_ae9_slot0_encode, Opcode_ae_la8x4u_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x4u_ip_Slot_ae10_slot0_encode, Opcode_ae_la8x4u_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2_ip_Slot_ae_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ip_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2_ip_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ip_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2_ip_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ip_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2_ip_Slot_ae_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ip_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2_ip_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ip_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2_ip_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ip_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2_ip_Slot_ae_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ip_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2_ip_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ip_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2_ip_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ip_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2_ic_Slot_ae_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2_ic_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2_ic_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2_ic_Slot_ae_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2_ic_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2_ic_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2_ic_Slot_ae_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2_ic_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2_ic_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2_ic1_Slot_ae_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic1_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2_ic1_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic1_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2_ic1_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic1_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2_ic1_Slot_ae_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic1_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2_ic1_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic1_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2_ic1_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic1_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2_ic1_Slot_ae_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic1_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2_ic1_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic1_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2_ic1_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic1_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2_ic2_Slot_ae_slot0_encode, Opcode_ae_la8x8x2_ic2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic2_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2_ic2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2_ic2_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2_ic2_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2_ic2_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2_ic2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2_ic2_Slot_ae_slot0_encode, Opcode_ae_la16x4x2_ic2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic2_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2_ic2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2_ic2_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2_ic2_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2_ic2_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2_ic2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2_ic2_Slot_ae_slot0_encode, Opcode_ae_la32x2x2_ic2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic2_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2_ic2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2_ic2_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2_ic2_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2_ic2_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2_ic2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa8x8x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa16x4x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa32x2x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8x2_ic_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8x2_ic_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa8x8x2_ic_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4x2_ic_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4x2_ic_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa16x4x2_ic_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2x2_ic_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2x2_ic_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa32x2x2_ic_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8x2_ic1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa8x8x2_ic1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4x2_ic1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa16x4x2_ic1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2x2_ic1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa32x2x2_ic1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8x2_ic2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8x2_ic2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa8x8x2_ic2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4x2_ic2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4x2_ic2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa16x4x2_ic2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2x2_ic2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2x2_ic2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa32x2x2_ic2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs8_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_abs8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs8s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_abs8s_Slot_ae_slot3_encode, Opcode_ae_abs8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_abs8s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg8s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_neg8s_Slot_ae_slot3_encode, Opcode_ae_neg8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_neg8s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add8_encode_fns[] = { + 0, 0, 0, Opcode_ae_add8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_add8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub8_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sub8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_max8_encode_fns[] = { + 0, 0, 0, Opcode_ae_max8_Slot_ae_slot0_encode, 0, Opcode_ae_max8_Slot_ae_slot2_encode, 0, Opcode_ae_max8_Slot_ae2_slot0_encode, 0, Opcode_ae_max8_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_max8_Slot_ae4_slot2_encode, Opcode_ae_max8_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_min8_encode_fns[] = { + 0, 0, 0, Opcode_ae_min8_Slot_ae_slot0_encode, 0, Opcode_ae_min8_Slot_ae_slot2_encode, 0, Opcode_ae_min8_Slot_ae2_slot0_encode, 0, Opcode_ae_min8_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_min8_Slot_ae4_slot2_encode, Opcode_ae_min8_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add8s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add8s_Slot_ae_slot3_encode, Opcode_ae_add8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_add8s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub8s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sub8s_Slot_ae_slot3_encode, Opcode_ae_sub8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sub8s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le8_encode_fns[] = { + 0, 0, 0, Opcode_ae_le8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_le8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt8_encode_fns[] = { + 0, 0, 0, Opcode_ae_lt8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lt8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq8_encode_fns[] = { + 0, 0, 0, Opcode_ae_eq8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_eq8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satu16x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_satu16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_satu16x4_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat32x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sat32x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satu32x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_satu32x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat8x8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sat8x8x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satu8x8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_satu8x8x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat8x4x32_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sat8x4x32_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sat8x4x32_l_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satu8x4x32_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_satu8x4x32_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_satu8x4x32_l_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round8x8f16ssym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round8x8f16ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round8x8f16sasym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round8x8f16sasym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round8x4f32ssym_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round8x4f32ssym_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round8x4f32sasym_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round8x4f32sasym_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda8_encode_fns[] = { + 0, 0, 0, Opcode_ae_movda8_Slot_ae_slot0_encode, Opcode_ae_movda8_Slot_ae_slot1_encode, 0, 0, Opcode_ae_movda8_Slot_ae2_slot0_encode, Opcode_ae_movda8_Slot_ae2_slot1_encode, 0, Opcode_ae_movda8_Slot_ae3_slot0_encode, Opcode_ae_movda8_Slot_ae3_slot1_encode, Opcode_ae_movda8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad8_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad8_Slot_ae2_slot0_encode, Opcode_ae_movad8_Slot_ae2_slot1_encode, 0, Opcode_ae_movad8_Slot_ae3_slot0_encode, 0, Opcode_ae_movad8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movdx2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movdx2_Slot_ae_slot0_encode, 0, Opcode_ae_movdx2_Slot_ae_slot2_encode, Opcode_ae_movdx2_Slot_ae_slot3_encode, Opcode_ae_movdx2_Slot_ae2_slot0_encode, Opcode_ae_movdx2_Slot_ae2_slot1_encode, 0, Opcode_ae_movdx2_Slot_ae3_slot0_encode, 0, Opcode_ae_movdx2_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_movdx2_Slot_ae6_slot0_encode, Opcode_ae_movdx2_Slot_ae6_slot1_encode, Opcode_ae_movdx2_Slot_ae6_slot2_encode, Opcode_ae_movdx2_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movdx2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsub32j_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsub32j_Slot_ae_slot0_encode, 0, Opcode_ae_addandsub32j_Slot_ae_slot2_encode, Opcode_ae_addandsub32j_Slot_ae_slot3_encode, Opcode_ae_addandsub32j_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32j_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsub32j_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addw8_encode_fns[] = { + 0, 0, 0, Opcode_ae_addw8_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addw8_Slot_ae_slot3_encode, Opcode_ae_addw8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addw8_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addw16_encode_fns[] = { + 0, 0, 0, Opcode_ae_addw16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addw16_Slot_ae_slot3_encode, Opcode_ae_addw16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addw16_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addw32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addw32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addw32_Slot_ae_slot3_encode, Opcode_ae_addw32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addw32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subw8_encode_fns[] = { + 0, 0, 0, Opcode_ae_subw8_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subw8_Slot_ae_slot3_encode, Opcode_ae_subw8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subw8_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subw16_encode_fns[] = { + 0, 0, 0, Opcode_ae_subw16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subw16_Slot_ae_slot3_encode, Opcode_ae_subw16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subw16_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subw32_encode_fns[] = { + 0, 0, 0, Opcode_ae_subw32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subw32_Slot_ae_slot3_encode, Opcode_ae_subw32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subw32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_accw8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_accw8_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_accw8_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_accw16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_accw16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_accw16_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_accw32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_accw32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_accw32_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addw8u_encode_fns[] = { + 0, 0, 0, Opcode_ae_addw8u_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addw8u_Slot_ae_slot3_encode, Opcode_ae_addw8u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addw8u_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subw8u_encode_fns[] = { + 0, 0, 0, Opcode_ae_subw8u_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subw8u_Slot_ae_slot3_encode, Opcode_ae_subw8u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subw8u_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_accw8u_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_accw8u_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_accw8u_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulfp32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulafp32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulfp32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulafp32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulasf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsaf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulssf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulasf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsaf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulssf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32s_hh_Slot_ae_slot2_encode, Opcode_ae_mul32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32s_hh_Slot_ae_slot2_encode, Opcode_ae_mula32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32s_hh_Slot_ae_slot2_encode, Opcode_ae_muls32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32s_ll_Slot_ae_slot2_encode, Opcode_ae_mul32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32s_ll_Slot_ae_slot2_encode, Opcode_ae_mula32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32s_ll_Slot_ae_slot2_encode, Opcode_ae_muls32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32s_hl_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32s_hl_Slot_ae_slot2_encode, Opcode_ae_mul32s_hl_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32s_hl_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32s_hl_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32s_hl_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32s_hl_Slot_ae_slot2_encode, Opcode_ae_mula32s_hl_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32s_hl_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32s_hl_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32s_hl_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32s_hl_Slot_ae_slot2_encode, Opcode_ae_muls32s_hl_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32s_hl_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32s_hl_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32s_lh_Slot_ae_slot2_encode, Opcode_ae_mul32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32s_lh_Slot_ae_slot2_encode, Opcode_ae_mula32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32s_lh_Slot_ae_slot2_encode, Opcode_ae_muls32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaad32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzasd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsad32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzsad32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsad32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsad32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaad32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulasd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsad32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulsad32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsad32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsad32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaad32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzasd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsad32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzsad32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsad32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsad32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzssd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaad32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulasd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsad32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulsad32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsad32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsad32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulssd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x2ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x2ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x2ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x2ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x2ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x2ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x2ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x2ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x2ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x2ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x2ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x2ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsaf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsaf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x2r_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x2r_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x2r_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x2r_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x2r_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x2r_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x2r_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x2r_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x2r_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x2r_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x2r_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x2r_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfc32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafc32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfcj32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafcj32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj32ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfcj32ras_Slot_ae_slot2_encode, Opcode_ae_mulfcj32ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfcj32ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfcj32ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj32ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafcj32ras_Slot_ae_slot2_encode, Opcode_ae_mulafcj32ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafcj32ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafcj32ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2p32x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulf2p32x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf2p32x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulaf2p32x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf2p32x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulsf2p32x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2p32x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulf2p32x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf2p32x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulaf2p32x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf2p32x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulsf2p32x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x2s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulp32x2s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2p32x4s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4s_Slot_ae7_slot2_encode, Opcode_ae_mul2p32x4s_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2p32x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4_Slot_ae7_slot2_encode, Opcode_ae_mul2p32x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2p32x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula2p32x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2p32x4_Slot_ae7_slot2_encode, Opcode_ae_mula2p32x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls2p32x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muls2p32x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muls2p32x4_Slot_ae7_slot2_encode, Opcode_ae_muls2p32x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2p32x4t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4t_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4t_Slot_ae7_slot2_encode, Opcode_ae_mul2p32x4t_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2p32x4t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula2p32x4t_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2p32x4t_Slot_ae7_slot2_encode, Opcode_ae_mula2p32x4t_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls2p32x4t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muls2p32x4t_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muls2p32x4t_Slot_ae7_slot2_encode, Opcode_ae_muls2p32x4t_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaa32x2_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaa32x2_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzss32x2_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzss32x2_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaa32x2_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaa32x2_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32x2_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulss32x2_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulcj32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulcj32_Slot_ae_slot2_encode, Opcode_ae_mulcj32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulcj32_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulcj32_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulacj32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulacj32_Slot_ae_slot2_encode, Opcode_ae_mulacj32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulacj32_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulacj32_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muladdf32rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muladdf32rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muladdf32rs_Slot_ae7_slot2_encode, Opcode_ae_muladdf32rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muladdf32ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muladdf32ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muladdf32ras_Slot_ae7_slot2_encode, Opcode_ae_muladdf32ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsubf32rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsubf32rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsubf32rs_Slot_ae7_slot2_encode, Opcode_ae_mulsubf32rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsubf32ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsubf32ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsubf32ras_Slot_ae7_slot2_encode, Opcode_ae_mulsubf32ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32ra_Slot_ae_slot2_encode, Opcode_ae_mulfc32ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc32ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfc32ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32ra_Slot_ae_slot2_encode, Opcode_ae_mulafc32ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc32ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafc32ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulcj32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulcj32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulacj32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulacj32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulc32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulac32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2d32x2ws_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2d32x2ws_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2d32x2ws_Slot_ae7_slot2_encode, Opcode_ae_mulf2d32x2ws_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaa2q16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q16_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaa2q16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaa2q16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q16_Slot_ae7_slot2_encode, Opcode_ae_mulaaaa2q16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp16s_h_Slot_ae_slot2_encode, Opcode_ae_mulp16s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp16s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp16s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap16s_h_Slot_ae_slot2_encode, Opcode_ae_mulap16s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap16s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap16s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp16s_h_Slot_ae_slot2_encode, Opcode_ae_mulsp16s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp16s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp16s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap16s_l_Slot_ae_slot2_encode, Opcode_ae_mulap16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulsp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulc16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulac16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulc16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulac16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2c16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2c16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2c16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula2c16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfc16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafc16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfcj16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafcj16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj16ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfcj16ras_Slot_ae_slot2_encode, Opcode_ae_mulfcj16ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfcj16ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfcj16ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj16ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafcj16ras_Slot_ae_slot2_encode, Opcode_ae_mulafcj16ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafcj16ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafcj16ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc16s_Slot_ae_slot2_encode, Opcode_ae_mulc16s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc16s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulc16s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac16s_Slot_ae_slot2_encode, Opcode_ae_mulac16s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac16s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulac16s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp16x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp16x4rs_Slot_ae_slot2_encode, Opcode_ae_mulfp16x4rs_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp16x4rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp16x4rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd16x16x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd16x16x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd16x16x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulfd16x16x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp16x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp16x16x4s_Slot_ae_slot2_encode, Opcode_ae_mulp16x16x4s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp16x16x4s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp16x16x4s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap16x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap16x16x4s_Slot_ae_slot2_encode, Opcode_ae_mulap16x16x4s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap16x16x4s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap16x16x4s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp16x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp16x16x4s_Slot_ae_slot2_encode, Opcode_ae_mulsp16x16x4s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp16x16x4s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp16x16x4s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaa2d16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaa2d16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzss2d16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzss2d16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaa2d16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaa2d16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss2d16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulss2d16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulss2d16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulss2d16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulss2d16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss2d16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulss2d16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulss2d16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulss2d16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulss2d16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaafd16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaafd16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssfd16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulssfd16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd16x16x4ws_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd16x16x4ws_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd16x16x4ws_Slot_ae7_slot2_encode, Opcode_ae_mulfd16x16x4ws_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaa2q16x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q16x8_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q16x8_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaa2q16x8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaa2q16x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q16x8_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q16x8_Slot_ae7_slot2_encode, Opcode_ae_mulaaaa2q16x8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaa2q8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q8_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q8_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaa2q8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaa2q8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q8_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q8_Slot_ae7_slot2_encode, Opcode_ae_mulaaaa2q8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulc32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulac32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulc32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulac32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulpc32x16x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulpc32x16x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulpc32x16x2_Slot_ae7_slot2_encode, Opcode_ae_mulpc32x16x2_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulapc32x16x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulapc32x16x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulapc32x16x2_Slot_ae7_slot2_encode, Opcode_ae_mulapc32x16x2_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32x16w_h_Slot_ae_slot2_encode, Opcode_ae_mulfc32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32x16w_h_Slot_ae_slot2_encode, Opcode_ae_mulafc32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32x16w_l_Slot_ae_slot2_encode, Opcode_ae_mulfc32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32x16w_l_Slot_ae_slot2_encode, Opcode_ae_mulafc32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfcj32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafcj32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfcj32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafcj32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2p32x16x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulf2p32x16x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf2p32x16x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulaf2p32x16x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf2p32x16x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulsf2p32x16x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2p32x16x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulf2p32x16x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf2p32x16x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulaf2p32x16x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf2p32x16x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulsf2p32x16x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2p32x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4s_Slot_ae7_slot2_encode, Opcode_ae_mulf2p32x16x4s_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf2p32x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4s_Slot_ae7_slot2_encode, Opcode_ae_mulaf2p32x16x4s_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf2p32x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4s_Slot_ae7_slot2_encode, Opcode_ae_mulsf2p32x16x4s_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfpc32x16x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpc32x16x2ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpc32x16x2ras_Slot_ae7_slot2_encode, Opcode_ae_mulfpc32x16x2ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpc32x16x2ras_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafpc32x16x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafpc32x16x2ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafpc32x16x2ras_Slot_ae7_slot2_encode, Opcode_ae_mulafpc32x16x2ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfpcj32x16x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpcj32x16x2ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpcj32x16x2ras_Slot_ae7_slot2_encode, Opcode_ae_mulfpcj32x16x2ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpcj32x16x2ras_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafpcj32x16x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafpcj32x16x2ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafpcj32x16x2ras_Slot_ae7_slot2_encode, Opcode_ae_mulafpcj32x16x2ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaa2q32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q32x16_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaa2q32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaa2q32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q32x16_Slot_ae7_slot2_encode, Opcode_ae_mulaaaa2q32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2q32x16_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2q32x16_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2q32x16_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mul2q32x16_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2q32x16_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula2q32x16_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2q32x16_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mula2q32x16_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2q32x16_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2q32x16_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2q32x16_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mul2q32x16_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2q32x16_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula2q32x16_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2q32x16_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mula2q32x16_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai8_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srai8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai8r_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai8r_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srai8r_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli8_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srli8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai8_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slai8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai8s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slai8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa8_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srla8_encode_fns[] = { + 0, 0, 0, Opcode_ae_srla8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srla8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa8s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa8rs_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa8rs_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa8rs_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa8s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli16_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srli16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai16_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slai16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa16_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srla16_encode_fns[] = { + 0, 0, 0, Opcode_ae_srla16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srla16_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_srla16_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai16sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai16sym_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srai16sym_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa16syms_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa16syms_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa16syms_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai32sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai32sym_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srai32sym_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32syms_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa32syms_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa32syms_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srav16rs_encode_fns[] = { + 0, 0, 0, Opcode_ae_srav16rs_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srav16rs_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srav32rs_encode_fns[] = { + 0, 0, 0, Opcode_ae_srav32rs_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srav32rs_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8s_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8s_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8s_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8s_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8s_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8s_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8u_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8u_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8u_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8u_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8u_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8u_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8us_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8us_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8us_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8us_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8us_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8us_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8u_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8u_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8u_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8u_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8u_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8u_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8us_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8us_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8us_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8us_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8us_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8us_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f16_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f16s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f16_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f16s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f16u_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f16u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f16u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f16us_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f16us_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f16us_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f16u_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f16u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f16u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f16us_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f16us_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f16us_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti16x4x2f8_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti16x4x2f8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti16x4x2f8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvti16x4x2f8_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti16x4x2f8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti16x4x2f8s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti16x4x2f8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvti16x4x2f8s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta16x4x2f8_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta16x4x2f8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta16x4x2f8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvta16x4x2f8_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta16x4x2f8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta16x4x2f8s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta16x4x2f8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvta16x4x2f8s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti16x4x2f8u_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti16x4x2f8u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti16x4x2f8u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvti16x4x2f8u_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti16x4x2f8us_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti16x4x2f8us_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti16x4x2f8us_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta16x4x2f8u_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta16x4x2f8u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta16x4x2f8u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvta16x4x2f8u_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta16x4x2f8us_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta16x4x2f8us_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta16x4x2f8us_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel8x8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sel8x8_Slot_ae_slot2_encode, Opcode_ae_sel8x8_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sel8x8_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_sel8x8_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sel8x8_Slot_ae7_slot2_encode, Opcode_ae_sel8x8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_shfl8x8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_shfl8x8_Slot_ae_slot2_encode, Opcode_ae_shfl8x8_Slot_ae_slot3_encode, 0, 0, Opcode_ae_shfl8x8_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_shfl8x8_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_shfl8x8_Slot_ae7_slot2_encode, Opcode_ae_shfl8x8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sel16x4_Slot_ae_slot2_encode, Opcode_ae_sel16x4_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sel16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_sel16x4_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sel16x4_Slot_ae7_slot2_encode, Opcode_ae_sel16x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, Opcode_ae_sel16x4_Slot_ae9_slot2_encode, Opcode_ae_sel16x4_Slot_ae9_slot3_encode, 0, 0, Opcode_ae_sel16x4_Slot_ae10_slot2_encode, Opcode_ae_sel16x4_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_shfl16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_shfl16x4_Slot_ae_slot2_encode, Opcode_ae_shfl16x4_Slot_ae_slot3_encode, 0, 0, Opcode_ae_shfl16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_shfl16x4_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_shfl16x4_Slot_ae7_slot2_encode, Opcode_ae_shfl16x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dsel8x8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_dsel8x8_Slot_ae_slot2_encode, Opcode_ae_dsel8x8_Slot_ae_slot3_encode, 0, 0, Opcode_ae_dsel8x8_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_dsel8x8_Slot_ae7_slot2_encode, Opcode_ae_dsel8x8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dsel16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_dsel16x4_Slot_ae_slot2_encode, Opcode_ae_dsel16x4_Slot_ae_slot3_encode, 0, 0, Opcode_ae_dsel16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_dsel16x4_Slot_ae7_slot2_encode, Opcode_ae_dsel16x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, Opcode_ae_dsel16x4_Slot_ae9_slot2_encode, Opcode_ae_dsel16x4_Slot_ae9_slot3_encode, 0, 0, Opcode_ae_dsel16x4_Slot_ae10_slot2_encode, Opcode_ae_dsel16x4_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel8x8i_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sel8x8i_Slot_ae_slot2_encode, Opcode_ae_sel8x8i_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sel8x8i_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_sel8x8i_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sel8x8i_Slot_ae7_slot2_encode, Opcode_ae_sel8x8i_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rmax8x8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_rmax8x8_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_rmax8x8_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_rmax8x8_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rmin8x8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_rmin8x8_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_rmin8x8_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_rmin8x8_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rmax16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_rmax16x4_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_rmax16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_rmax16x4_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rmin16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_rmin16x4_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_rmin16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_rmin16x4_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sort16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sort16x4_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_sort16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sort16x4_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radd8x8_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radd8x8_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radd8x8_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radd8x8_h_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radda8x8_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radda8x8_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radda8x8_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radda8x8_h_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radd8x8_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radd8x8_l_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radd8x8_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radd8x8_l_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radda8x8_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radda8x8_l_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radda8x8_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radda8x8_l_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radd16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radd16x4_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radd16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radd16x4_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radda16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radda16x4_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radda16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radda16x4_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmax8x8_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_bmax8x8_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmax8x8_h_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmax8x8_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_bmax8x8_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmax8x8_l_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmax8x8_l_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmin8x8_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_bmin8x8_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmin8x8_h_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmin8x8_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_bmin8x8_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmin8x8_l_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmin8x8_l_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmax16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_bmax16x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_bmax16x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmax16x4_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmax16x4_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmin16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_bmin16x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_bmin16x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmin16x4_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmin16x4_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmax32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_bmax32x2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_bmax32x2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmax32x2_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmax32x2_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmin32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_bmin32x2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_bmin32x2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmin32x2_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmin32x2_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addinv16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addinv16s_Slot_ae_slot0_encode, 0, Opcode_ae_addinv16s_Slot_ae_slot2_encode, Opcode_ae_addinv16s_Slot_ae_slot3_encode, Opcode_ae_addinv16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addinv16s_Slot_ae6_slot0_encode, 0, Opcode_ae_addinv16s_Slot_ae6_slot2_encode, Opcode_ae_addinv16s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addinv32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addinv32s_Slot_ae_slot0_encode, 0, Opcode_ae_addinv32s_Slot_ae_slot2_encode, Opcode_ae_addinv32s_Slot_ae_slot3_encode, Opcode_ae_addinv32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addinv32s_Slot_ae6_slot0_encode, 0, Opcode_ae_addinv32s_Slot_ae6_slot2_encode, Opcode_ae_addinv32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt16x8_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt16x8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt16x8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt8x16_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt8x16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt8x16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt8x16_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt8x16_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt8x16_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movbd1x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movbd1x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movbd1x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movbd1x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movbd1x2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movbd1x2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movneg32s_t_encode_fns[] = { + 0, 0, 0, Opcode_ae_movneg32s_t_Slot_ae_slot0_encode, 0, Opcode_ae_movneg32s_t_Slot_ae_slot2_encode, Opcode_ae_movneg32s_t_Slot_ae_slot3_encode, Opcode_ae_movneg32s_t_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movdext_encode_fns[] = { + 0, 0, 0, Opcode_ae_movdext_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movdext_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movadext_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_movadext_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movadext_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movadext_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_movadext_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movadext_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsa16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsa16x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsa16x4_Slot_ae2_slot0_encode, Opcode_ae_nsa16x4_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsaz32x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsaz32x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsaz32x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsa32x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsa32x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsa32x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunci16x4f32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunci16x4f32s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunci16x4f32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci16x4f32s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci16x4f32s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunci16x4f64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunci16x4f64s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunci16x4f64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci16x4f64s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci16x4f64s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16x4f32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca16x4f32s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunca16x4f32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca16x4f32s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca16x4f32s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16x4f64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca16x4f64s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunca16x4f64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca16x4f64s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca16x4f64s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addc32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addc32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_addc32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addc32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subc32_encode_fns[] = { + 0, 0, 0, Opcode_ae_subc32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_subc32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subc32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addc32u_encode_fns[] = { + 0, 0, 0, Opcode_ae_addc32u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_addc32u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addc32u_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subc32u_encode_fns[] = { + 0, 0, 0, Opcode_ae_subc32u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_subc32u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subc32u_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_expadd16_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_expadd16_h_Slot_ae_slot2_encode, Opcode_ae_expadd16_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_expsub16_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_expsub16_h_Slot_ae_slot2_encode, Opcode_ae_expsub16_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_expadd16_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_expadd16_l_Slot_ae_slot2_encode, Opcode_ae_expadd16_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_expsub16_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_expsub16_l_Slot_ae_slot2_encode, Opcode_ae_expsub16_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcexp32_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_addcexp32_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcexp32_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_addcexp32_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_calcrng16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_calcrng16_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_calcrng32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_calcrng32_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rng32x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_rng32x4_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lav8x8x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_lav8x8x2_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lav8x8x2_xp_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lav8x8x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_lav8x8x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_ae_lav8x8x2_xp_Slot_ae10_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lav16x4x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_lav16x4x2_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lav16x4x2_xp_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lav16x4x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_lav16x4x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_ae_lav16x4x2_xp_Slot_ae10_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sav8x8x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_sav8x8x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sav8x8x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sav8x8x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sav16x4x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_sav16x4x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sav16x4x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sav16x4x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movzbvcdr_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_movzbvcdr_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movzbvcdr_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movdrzbvc_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_movdrzbvc_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movdrzbvc_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lavunsqz8x8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_lavunsqz8x8_xp_Slot_ae_slot0_encode, Opcode_ae_lavunsqz8x8_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_lavunsqz8x8_xp_Slot_ae2_slot0_encode, Opcode_ae_lavunsqz8x8_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lavunsqz8x8_xp_Slot_ae8_slot0_encode, Opcode_ae_lavunsqz8x8_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_lavunsqz8x8_xp_Slot_ae9_slot0_encode, Opcode_ae_lavunsqz8x8_xp_Slot_ae9_slot1_encode, 0, 0, 0, Opcode_ae_lavunsqz8x8_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lavunsqz16x4_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_lavunsqz16x4_xp_Slot_ae_slot0_encode, Opcode_ae_lavunsqz16x4_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_lavunsqz16x4_xp_Slot_ae2_slot0_encode, Opcode_ae_lavunsqz16x4_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lavunsqz16x4_xp_Slot_ae8_slot0_encode, Opcode_ae_lavunsqz16x4_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_lavunsqz16x4_xp_Slot_ae9_slot0_encode, Opcode_ae_lavunsqz16x4_xp_Slot_ae9_slot1_encode, 0, 0, 0, Opcode_ae_lavunsqz16x4_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2x4q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2x4q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2x4q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2x4q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulqq8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulqq8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaqq8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaqq8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2x4q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2x4q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2x4q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2x4q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2x4q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2x4q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2x4q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2x4q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulqq4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulqq4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaqq4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaqq4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulqq4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulqq4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaqq4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaqq4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o4x16cnv_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o4x16cnv_hh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o4x16cnv_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o4x16cnv_hl_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o4x16cnv_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o4x16cnv_lh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o4x16cnv_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o4x16cnv_ll_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o4x16cnv_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o4x16cnv_hh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o4x16cnv_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o4x16cnv_hl_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o4x16cnv_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o4x16cnv_lh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o4x16cnv_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o4x16cnv_ll_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus2x4q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus2x4q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus2x4q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus2x4q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulusqq8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulusqq8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulausqq8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulausqq8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus2x4q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus2x4q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus2x4q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus2x4q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus2x4q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus2x4q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus2x4q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus2x4q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulusqq4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulusqq4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulausqq4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulausqq4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulusqq4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulusqq4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulausqq4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulausqq4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o4x16cnv_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o4x16cnv_hh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o4x16cnv_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o4x16cnv_hl_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o4x16cnv_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o4x16cnv_lh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o4x16cnv_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o4x16cnv_ll_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o4x16cnv_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o4x16cnv_hh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o4x16cnv_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o4x16cnv_hl_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o4x16cnv_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o4x16cnv_lh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o4x16cnv_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o4x16cnv_ll_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtsf16_l_encode_fns[] = { + 0, 0, 0, Opcode_cvtsf16_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_cvtsf16_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtsf16_l_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtsf16_h_encode_fns[] = { + 0, 0, 0, Opcode_cvtsf16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_cvtsf16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtsf16_h_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtf16s_l_encode_fns[] = { + 0, 0, 0, Opcode_cvtf16s_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_cvtf16s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtf16s_l_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtf16s_h_encode_fns[] = { + 0, 0, 0, Opcode_cvtf16s_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_cvtf16s_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtf16s_h_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movfcrfsrv_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_movfcrfsrv_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movvfcrfsr_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_movvfcrfsr_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = { + 0, 0, 0, Opcode_movt_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movt_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_movt_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = { + 0, 0, 0, Opcode_movf_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movf_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_movf_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = { + 0, 0, 0, Opcode_moveqz_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_moveqz_s_Slot_ae2_slot0_encode, Opcode_moveqz_s_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_moveqz_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = { + 0, 0, 0, Opcode_movnez_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movnez_s_Slot_ae2_slot0_encode, Opcode_movnez_s_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_movnez_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = { + 0, 0, 0, Opcode_movgez_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movgez_s_Slot_ae2_slot0_encode, Opcode_movgez_s_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_movgez_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = { + 0, 0, 0, Opcode_movltz_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movltz_s_Slot_ae2_slot0_encode, Opcode_movltz_s_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_movltz_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = { + 0, 0, 0, Opcode_rfr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = { + 0, 0, 0, Opcode_wfr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mul_s_Slot_ae_slot2_encode, Opcode_mul_s_Slot_ae_slot3_encode, 0, 0, Opcode_mul_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_mul_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mul_s_Slot_ae9_slot2_encode, Opcode_mul_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mul_s_Slot_ae10_slot2_encode, Opcode_mul_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_madd_s_Slot_ae_slot2_encode, Opcode_madd_s_Slot_ae_slot3_encode, 0, 0, Opcode_madd_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_madd_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_madd_s_Slot_ae9_slot2_encode, Opcode_madd_s_Slot_ae9_slot3_encode, 0, 0, Opcode_madd_s_Slot_ae10_slot2_encode, Opcode_madd_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_msub_s_Slot_ae_slot2_encode, Opcode_msub_s_Slot_ae_slot3_encode, 0, 0, Opcode_msub_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_msub_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msub_s_Slot_ae9_slot2_encode, Opcode_msub_s_Slot_ae9_slot3_encode, 0, 0, Opcode_msub_s_Slot_ae10_slot2_encode, Opcode_msub_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msubn_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_msubn_s_Slot_ae_slot2_encode, Opcode_msubn_s_Slot_ae_slot3_encode, 0, 0, Opcode_msubn_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_msubn_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msubn_s_Slot_ae9_slot2_encode, Opcode_msubn_s_Slot_ae9_slot3_encode, 0, 0, Opcode_msubn_s_Slot_ae10_slot2_encode, Opcode_msubn_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddn_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maddn_s_Slot_ae_slot2_encode, Opcode_maddn_s_Slot_ae_slot3_encode, 0, 0, Opcode_maddn_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_maddn_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddn_s_Slot_ae9_slot2_encode, Opcode_maddn_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maddn_s_Slot_ae10_slot2_encode, Opcode_maddn_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_add_s_Slot_ae_slot2_encode, Opcode_add_s_Slot_ae_slot3_encode, 0, 0, Opcode_add_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_add_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_s_Slot_ae9_slot2_encode, Opcode_add_s_Slot_ae9_slot3_encode, 0, 0, Opcode_add_s_Slot_ae10_slot2_encode, Opcode_add_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_sub_s_Slot_ae_slot2_encode, Opcode_sub_s_Slot_ae_slot3_encode, 0, 0, Opcode_sub_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_sub_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_s_Slot_ae9_slot2_encode, Opcode_sub_s_Slot_ae9_slot3_encode, 0, 0, Opcode_sub_s_Slot_ae10_slot2_encode, Opcode_sub_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = { + 0, 0, 0, Opcode_ole_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ole_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ole_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ole_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = { + 0, 0, 0, Opcode_olt_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_olt_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_olt_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_olt_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = { + 0, 0, 0, Opcode_oeq_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_oeq_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_oeq_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_oeq_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = { + 0, 0, 0, Opcode_un_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_un_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_un_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_un_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = { + 0, 0, 0, Opcode_ule_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ule_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ule_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ule_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = { + 0, 0, 0, Opcode_ult_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ult_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ult_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ult_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = { + 0, 0, 0, Opcode_ueq_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ueq_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ueq_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ueq_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nexp01_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_nexp01_s_Slot_ae_slot2_encode, Opcode_nexp01_s_Slot_ae_slot3_encode, 0, 0, Opcode_nexp01_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_nexp01_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_nexp01_s_Slot_ae9_slot2_encode, Opcode_nexp01_s_Slot_ae9_slot3_encode, 0, 0, Opcode_nexp01_s_Slot_ae10_slot2_encode, Opcode_nexp01_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mksadj_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mksadj_s_Slot_ae_slot2_encode, Opcode_mksadj_s_Slot_ae_slot3_encode, 0, 0, Opcode_mksadj_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_mksadj_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mksadj_s_Slot_ae9_slot2_encode, Opcode_mksadj_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mksadj_s_Slot_ae10_slot2_encode, Opcode_mksadj_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mkdadj_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mkdadj_s_Slot_ae_slot2_encode, Opcode_mkdadj_s_Slot_ae_slot3_encode, 0, 0, Opcode_mkdadj_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_mkdadj_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mkdadj_s_Slot_ae9_slot2_encode, Opcode_mkdadj_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mkdadj_s_Slot_ae10_slot2_encode, Opcode_mkdadj_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_div0_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_div0_s_Slot_ae_slot2_encode, Opcode_div0_s_Slot_ae_slot3_encode, 0, 0, Opcode_div0_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_div0_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_div0_s_Slot_ae9_slot2_encode, Opcode_div0_s_Slot_ae9_slot3_encode, 0, 0, Opcode_div0_s_Slot_ae10_slot2_encode, Opcode_div0_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sqrt0_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_sqrt0_s_Slot_ae_slot2_encode, Opcode_sqrt0_s_Slot_ae_slot3_encode, 0, 0, Opcode_sqrt0_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_sqrt0_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sqrt0_s_Slot_ae9_slot2_encode, Opcode_sqrt0_s_Slot_ae9_slot3_encode, 0, 0, Opcode_sqrt0_s_Slot_ae10_slot2_encode, Opcode_sqrt0_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_recip0_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_recip0_s_Slot_ae_slot2_encode, Opcode_recip0_s_Slot_ae_slot3_encode, 0, 0, Opcode_recip0_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_recip0_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_recip0_s_Slot_ae9_slot2_encode, Opcode_recip0_s_Slot_ae9_slot3_encode, 0, 0, Opcode_recip0_s_Slot_ae10_slot2_encode, Opcode_recip0_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsqrt0_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_rsqrt0_s_Slot_ae_slot2_encode, Opcode_rsqrt0_s_Slot_ae_slot3_encode, 0, 0, Opcode_rsqrt0_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_rsqrt0_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rsqrt0_s_Slot_ae9_slot2_encode, Opcode_rsqrt0_s_Slot_ae9_slot3_encode, 0, 0, Opcode_rsqrt0_s_Slot_ae10_slot2_encode, Opcode_rsqrt0_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_divn_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_divn_s_Slot_ae_slot2_encode, Opcode_divn_s_Slot_ae_slot3_encode, 0, 0, Opcode_divn_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_divn_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_divn_s_Slot_ae9_slot2_encode, Opcode_divn_s_Slot_ae9_slot3_encode, 0, 0, Opcode_divn_s_Slot_ae10_slot2_encode, Opcode_divn_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexp_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addexp_s_Slot_ae_slot2_encode, Opcode_addexp_s_Slot_ae_slot3_encode, 0, 0, Opcode_addexp_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addexp_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addexp_s_Slot_ae9_slot2_encode, Opcode_addexp_s_Slot_ae9_slot3_encode, 0, 0, Opcode_addexp_s_Slot_ae10_slot2_encode, Opcode_addexp_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexpm_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addexpm_s_Slot_ae_slot2_encode, Opcode_addexpm_s_Slot_ae_slot3_encode, 0, 0, Opcode_addexpm_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addexpm_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addexpm_s_Slot_ae9_slot2_encode, Opcode_addexpm_s_Slot_ae9_slot3_encode, 0, 0, Opcode_addexpm_s_Slot_ae10_slot2_encode, Opcode_addexpm_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_min_s_Slot_ae_slot2_encode, Opcode_min_s_Slot_ae_slot3_encode, 0, 0, Opcode_min_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_min_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_min_s_Slot_ae9_slot2_encode, Opcode_min_s_Slot_ae9_slot3_encode, 0, 0, Opcode_min_s_Slot_ae10_slot2_encode, Opcode_min_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_max_s_Slot_ae_slot2_encode, Opcode_max_s_Slot_ae_slot3_encode, 0, 0, Opcode_max_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_max_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_max_s_Slot_ae9_slot2_encode, Opcode_max_s_Slot_ae9_slot3_encode, 0, 0, Opcode_max_s_Slot_ae10_slot2_encode, Opcode_max_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulmux_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mulmux_s_Slot_ae_slot2_encode, Opcode_mulmux_s_Slot_ae_slot3_encode, 0, 0, Opcode_mulmux_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulmux_s_Slot_ae9_slot2_encode, Opcode_mulmux_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mulmux_s_Slot_ae10_slot2_encode, Opcode_mulmux_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddmux_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maddmux_s_Slot_ae_slot2_encode, Opcode_maddmux_s_Slot_ae_slot3_encode, 0, 0, Opcode_maddmux_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddmux_s_Slot_ae9_slot2_encode, Opcode_maddmux_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maddmux_s_Slot_ae10_slot2_encode, Opcode_maddmux_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = { + 0, 0, 0, Opcode_trunc_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_trunc_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_trunc_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = { + 0, 0, 0, Opcode_utrunc_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_utrunc_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_utrunc_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc_sx2_encode_fns[] = { + 0, 0, 0, Opcode_trunc_sx2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_trunc_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_trunc_sx2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc_sx2_encode_fns[] = { + 0, 0, 0, Opcode_utrunc_sx2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_utrunc_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_utrunc_sx2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ficeil_s_encode_fns[] = { + 0, 0, 0, Opcode_ficeil_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ficeil_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ficeil_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_fifloor_s_encode_fns[] = { + 0, 0, 0, Opcode_fifloor_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_fifloor_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_fifloor_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_firint_s_encode_fns[] = { + 0, 0, 0, Opcode_firint_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_firint_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_firint_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_firound_s_encode_fns[] = { + 0, 0, 0, Opcode_firound_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_firound_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_firound_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_fitrunc_s_encode_fns[] = { + 0, 0, 0, Opcode_fitrunc_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_fitrunc_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_fitrunc_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = { + 0, 0, 0, Opcode_float_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_float_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_float_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = { + 0, 0, 0, Opcode_ufloat_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ufloat_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ufloat_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float_sx2_encode_fns[] = { + 0, 0, 0, Opcode_float_sx2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_float_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_float_sx2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat_sx2_encode_fns[] = { + 0, 0, 0, Opcode_ufloat_sx2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ufloat_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ufloat_sx2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_abs_s_Slot_ae_slot2_encode, Opcode_abs_s_Slot_ae_slot3_encode, 0, Opcode_abs_s_Slot_ae2_slot1_encode, Opcode_abs_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_abs_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_abs_s_Slot_ae9_slot2_encode, Opcode_abs_s_Slot_ae9_slot3_encode, 0, 0, Opcode_abs_s_Slot_ae10_slot2_encode, Opcode_abs_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_neg_s_Slot_ae_slot2_encode, Opcode_neg_s_Slot_ae_slot3_encode, 0, Opcode_neg_s_Slot_ae2_slot1_encode, Opcode_neg_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_neg_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_neg_s_Slot_ae9_slot2_encode, Opcode_neg_s_Slot_ae9_slot3_encode, 0, 0, Opcode_neg_s_Slot_ae10_slot2_encode, Opcode_neg_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_conjc_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_conjc_s_Slot_ae_slot2_encode, Opcode_conjc_s_Slot_ae_slot3_encode, 0, Opcode_conjc_s_Slot_ae2_slot1_encode, Opcode_conjc_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_conjc_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_conjc_s_Slot_ae9_slot2_encode, Opcode_conjc_s_Slot_ae9_slot3_encode, 0, 0, Opcode_conjc_s_Slot_ae10_slot2_encode, Opcode_conjc_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muljc_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_muljc_s_Slot_ae_slot2_encode, Opcode_muljc_s_Slot_ae_slot3_encode, 0, Opcode_muljc_s_Slot_ae2_slot1_encode, Opcode_muljc_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_muljc_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_muljc_s_Slot_ae9_slot2_encode, Opcode_muljc_s_Slot_ae9_slot3_encode, 0, 0, Opcode_muljc_s_Slot_ae10_slot2_encode, Opcode_muljc_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_const_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_const_s_Slot_ae_slot2_encode, Opcode_const_s_Slot_ae_slot3_encode, 0, Opcode_const_s_Slot_ae2_slot1_encode, Opcode_const_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_const_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_const_s_Slot_ae9_slot2_encode, Opcode_const_s_Slot_ae9_slot3_encode, 0, 0, Opcode_const_s_Slot_ae10_slot2_encode, Opcode_const_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clsfy_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_clsfy_s_Slot_ae_slot2_encode, Opcode_clsfy_s_Slot_ae_slot3_encode, 0, 0, Opcode_clsfy_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_clsfy_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_clsfy_s_Slot_ae9_slot2_encode, Opcode_clsfy_s_Slot_ae9_slot3_encode, 0, 0, Opcode_clsfy_s_Slot_ae10_slot2_encode, Opcode_clsfy_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minnum_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_minnum_s_Slot_ae_slot2_encode, Opcode_minnum_s_Slot_ae_slot3_encode, 0, 0, Opcode_minnum_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_minnum_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_minnum_s_Slot_ae9_slot2_encode, Opcode_minnum_s_Slot_ae9_slot3_encode, 0, 0, Opcode_minnum_s_Slot_ae10_slot2_encode, Opcode_minnum_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxnum_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maxnum_s_Slot_ae_slot2_encode, Opcode_maxnum_s_Slot_ae_slot3_encode, 0, 0, Opcode_maxnum_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_maxnum_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maxnum_s_Slot_ae9_slot2_encode, Opcode_maxnum_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maxnum_s_Slot_ae10_slot2_encode, Opcode_maxnum_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addandsub_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addandsub_s_Slot_ae_slot2_encode, Opcode_addandsub_s_Slot_ae_slot3_encode, 0, 0, Opcode_addandsub_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addandsub_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addandsub_s_Slot_ae9_slot2_encode, Opcode_addandsub_s_Slot_ae9_slot3_encode, 0, 0, Opcode_addandsub_s_Slot_ae10_slot2_encode, Opcode_addandsub_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addandsubjc_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addandsubjc_s_Slot_ae_slot2_encode, Opcode_addandsubjc_s_Slot_ae_slot3_encode, 0, 0, Opcode_addandsubjc_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addandsubjc_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addandsubjc_s_Slot_ae9_slot2_encode, Opcode_addandsubjc_s_Slot_ae9_slot3_encode, 0, 0, Opcode_addandsubjc_s_Slot_ae10_slot2_encode, Opcode_addandsubjc_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_hl_lh_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_add_hl_lh_s_Slot_ae_slot2_encode, Opcode_add_hl_lh_s_Slot_ae_slot3_encode, 0, 0, Opcode_add_hl_lh_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_add_hl_lh_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_hl_lh_s_Slot_ae9_slot2_encode, Opcode_add_hl_lh_s_Slot_ae9_slot3_encode, 0, 0, Opcode_add_hl_lh_s_Slot_ae10_slot2_encode, Opcode_add_hl_lh_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madda_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_madda_s_Slot_ae_slot2_encode, Opcode_madda_s_Slot_ae_slot3_encode, 0, 0, Opcode_madda_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_madda_s_Slot_ae9_slot2_encode, Opcode_madda_s_Slot_ae9_slot3_encode, 0, 0, Opcode_madda_s_Slot_ae10_slot2_encode, Opcode_madda_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_frexp_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_frexp_s_Slot_ae_slot2_encode, Opcode_frexp_s_Slot_ae_slot3_encode, 0, 0, Opcode_frexp_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_frexp_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_frexp_s_Slot_ae9_slot2_encode, Opcode_frexp_s_Slot_ae9_slot3_encode, 0, 0, Opcode_frexp_s_Slot_ae10_slot2_encode, Opcode_frexp_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_floatexp_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_floatexp_s_Slot_ae_slot2_encode, Opcode_floatexp_s_Slot_ae_slot3_encode, 0, 0, Opcode_floatexp_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_floatexp_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_floatexp_s_Slot_ae9_slot2_encode, Opcode_floatexp_s_Slot_ae9_slot3_encode, 0, 0, Opcode_floatexp_s_Slot_ae10_slot2_encode, Opcode_floatexp_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minnumabs_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_minnumabs_s_Slot_ae_slot2_encode, Opcode_minnumabs_s_Slot_ae_slot3_encode, 0, 0, Opcode_minnumabs_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_minnumabs_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_minnumabs_s_Slot_ae9_slot2_encode, Opcode_minnumabs_s_Slot_ae9_slot3_encode, 0, 0, Opcode_minnumabs_s_Slot_ae10_slot2_encode, Opcode_minnumabs_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxnumabs_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maxnumabs_s_Slot_ae_slot2_encode, Opcode_maxnumabs_s_Slot_ae_slot3_encode, 0, 0, Opcode_maxnumabs_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_maxnumabs_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maxnumabs_s_Slot_ae9_slot2_encode, Opcode_maxnumabs_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maxnumabs_s_Slot_ae10_slot2_encode, Opcode_maxnumabs_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulq_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulq_s_Slot_ae9_slot2_encode, Opcode_mulq_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mulq_s_Slot_ae10_slot2_encode, Opcode_mulq_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddq_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddq_s_Slot_ae9_slot2_encode, Opcode_maddq_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maddq_s_Slot_ae10_slot2_encode, Opcode_maddq_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msubq_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msubq_s_Slot_ae9_slot2_encode, Opcode_msubq_s_Slot_ae9_slot3_encode, 0, 0, Opcode_msubq_s_Slot_ae10_slot2_encode, Opcode_msubq_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulmuxq_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulmuxq_s_Slot_ae9_slot2_encode, Opcode_mulmuxq_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mulmuxq_s_Slot_ae10_slot2_encode, Opcode_mulmuxq_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddmuxq_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddmuxq_s_Slot_ae9_slot2_encode, Opcode_maddmuxq_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maddmuxq_s_Slot_ae10_slot2_encode, Opcode_maddmuxq_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bmaxnum_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_bmaxnum_s_Slot_ae_slot3_encode, 0, 0, Opcode_bmaxnum_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bmaxnum_s_Slot_ae9_slot3_encode, 0, 0, 0, Opcode_bmaxnum_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bminnum_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_bminnum_s_Slot_ae_slot3_encode, 0, 0, Opcode_bminnum_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bminnum_s_Slot_ae9_slot3_encode, 0, 0, 0, Opcode_bminnum_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bmaxnumabs_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_bmaxnumabs_s_Slot_ae_slot3_encode, 0, 0, Opcode_bmaxnumabs_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bmaxnumabs_s_Slot_ae9_slot3_encode, 0, 0, 0, Opcode_bmaxnumabs_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bminnumabs_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_bminnumabs_s_Slot_ae_slot3_encode, 0, 0, Opcode_bminnumabs_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bminnumabs_s_Slot_ae9_slot3_encode, 0, 0, 0, Opcode_bminnumabs_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_abs_sx2x2_Slot_ae_slot2_encode, Opcode_abs_sx2x2_Slot_ae_slot3_encode, 0, Opcode_abs_sx2x2_Slot_ae2_slot1_encode, Opcode_abs_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_abs_sx2x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_abs_sx2x2_Slot_ae9_slot2_encode, Opcode_abs_sx2x2_Slot_ae9_slot3_encode, 0, 0, Opcode_abs_sx2x2_Slot_ae10_slot2_encode, Opcode_abs_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_neg_sx2x2_Slot_ae_slot2_encode, Opcode_neg_sx2x2_Slot_ae_slot3_encode, 0, Opcode_neg_sx2x2_Slot_ae2_slot1_encode, Opcode_neg_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_neg_sx2x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_neg_sx2x2_Slot_ae9_slot2_encode, Opcode_neg_sx2x2_Slot_ae9_slot3_encode, 0, 0, Opcode_neg_sx2x2_Slot_ae10_slot2_encode, Opcode_neg_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_conjc_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_conjc_sx2x2_Slot_ae_slot2_encode, Opcode_conjc_sx2x2_Slot_ae_slot3_encode, 0, Opcode_conjc_sx2x2_Slot_ae2_slot1_encode, Opcode_conjc_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_conjc_sx2x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_conjc_sx2x2_Slot_ae9_slot2_encode, Opcode_conjc_sx2x2_Slot_ae9_slot3_encode, 0, 0, Opcode_conjc_sx2x2_Slot_ae10_slot2_encode, Opcode_conjc_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muljc_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_muljc_sx2x2_Slot_ae_slot2_encode, Opcode_muljc_sx2x2_Slot_ae_slot3_encode, 0, Opcode_muljc_sx2x2_Slot_ae2_slot1_encode, Opcode_muljc_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_muljc_sx2x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_muljc_sx2x2_Slot_ae9_slot2_encode, Opcode_muljc_sx2x2_Slot_ae9_slot3_encode, 0, 0, Opcode_muljc_sx2x2_Slot_ae10_slot2_encode, Opcode_muljc_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_const_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_const_sx2x2_Slot_ae_slot2_encode, Opcode_const_sx2x2_Slot_ae_slot3_encode, 0, Opcode_const_sx2x2_Slot_ae2_slot1_encode, Opcode_const_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_const_sx2x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_const_sx2x2_Slot_ae9_slot2_encode, Opcode_const_sx2x2_Slot_ae9_slot3_encode, 0, 0, Opcode_const_sx2x2_Slot_ae10_slot2_encode, Opcode_const_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_sx2x2_Slot_ae9_slot2_encode, 0, 0, 0, Opcode_add_sx2x2_Slot_ae10_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_sx2x2_Slot_ae9_slot2_encode, 0, 0, 0, Opcode_sub_sx2x2_Slot_ae10_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mul_sx2x2_Slot_ae10_slot2_encode, Opcode_mul_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madd_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_madd_sx2x2_Slot_ae10_slot2_encode, Opcode_madd_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msub_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msub_sx2x2_Slot_ae10_slot2_encode, Opcode_msub_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulmux_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulmux_sx2x2_Slot_ae10_slot2_encode, Opcode_mulmux_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddmux_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddmux_sx2x2_Slot_ae10_slot2_encode, Opcode_maddmux_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_abs_h_Slot_ae_slot2_encode, Opcode_abs_h_Slot_ae_slot3_encode, 0, Opcode_abs_h_Slot_ae2_slot1_encode, Opcode_abs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_abs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_abs_h_Slot_ae9_slot2_encode, Opcode_abs_h_Slot_ae9_slot3_encode, 0, 0, Opcode_abs_h_Slot_ae10_slot2_encode, Opcode_abs_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexp_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addexp_h_Slot_ae_slot2_encode, Opcode_addexp_h_Slot_ae_slot3_encode, 0, 0, Opcode_addexp_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addexp_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addexp_h_Slot_ae9_slot2_encode, Opcode_addexp_h_Slot_ae9_slot3_encode, 0, 0, Opcode_addexp_h_Slot_ae10_slot2_encode, Opcode_addexp_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexpm_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addexpm_h_Slot_ae_slot2_encode, Opcode_addexpm_h_Slot_ae_slot3_encode, 0, 0, Opcode_addexpm_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addexpm_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addexpm_h_Slot_ae9_slot2_encode, Opcode_addexpm_h_Slot_ae9_slot3_encode, 0, 0, Opcode_addexpm_h_Slot_ae10_slot2_encode, Opcode_addexpm_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clsfy_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_clsfy_h_Slot_ae_slot2_encode, Opcode_clsfy_h_Slot_ae_slot3_encode, 0, 0, Opcode_clsfy_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_clsfy_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_clsfy_h_Slot_ae9_slot2_encode, Opcode_clsfy_h_Slot_ae9_slot3_encode, 0, 0, Opcode_clsfy_h_Slot_ae10_slot2_encode, Opcode_clsfy_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_conjc_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_conjc_h_Slot_ae_slot2_encode, Opcode_conjc_h_Slot_ae_slot3_encode, 0, Opcode_conjc_h_Slot_ae2_slot1_encode, Opcode_conjc_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_conjc_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_conjc_h_Slot_ae9_slot2_encode, Opcode_conjc_h_Slot_ae9_slot3_encode, 0, 0, Opcode_conjc_h_Slot_ae10_slot2_encode, Opcode_conjc_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_const_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_const_h_Slot_ae_slot2_encode, Opcode_const_h_Slot_ae_slot3_encode, 0, Opcode_const_h_Slot_ae2_slot1_encode, Opcode_const_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_const_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_const_h_Slot_ae9_slot2_encode, Opcode_const_h_Slot_ae9_slot3_encode, 0, 0, Opcode_const_h_Slot_ae10_slot2_encode, Opcode_const_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_min_h_Slot_ae_slot2_encode, Opcode_min_h_Slot_ae_slot3_encode, 0, 0, Opcode_min_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_min_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_min_h_Slot_ae9_slot2_encode, Opcode_min_h_Slot_ae9_slot3_encode, 0, 0, Opcode_min_h_Slot_ae10_slot2_encode, Opcode_min_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_max_h_Slot_ae_slot2_encode, Opcode_max_h_Slot_ae_slot3_encode, 0, 0, Opcode_max_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_max_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_max_h_Slot_ae9_slot2_encode, Opcode_max_h_Slot_ae9_slot3_encode, 0, 0, Opcode_max_h_Slot_ae10_slot2_encode, Opcode_max_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minnum_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_minnum_h_Slot_ae_slot2_encode, Opcode_minnum_h_Slot_ae_slot3_encode, 0, 0, Opcode_minnum_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_minnum_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_minnum_h_Slot_ae9_slot2_encode, Opcode_minnum_h_Slot_ae9_slot3_encode, 0, 0, Opcode_minnum_h_Slot_ae10_slot2_encode, Opcode_minnum_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxnum_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maxnum_h_Slot_ae_slot2_encode, Opcode_maxnum_h_Slot_ae_slot3_encode, 0, 0, Opcode_maxnum_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_maxnum_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maxnum_h_Slot_ae9_slot2_encode, Opcode_maxnum_h_Slot_ae9_slot3_encode, 0, 0, Opcode_maxnum_h_Slot_ae10_slot2_encode, Opcode_maxnum_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muljc_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_muljc_h_Slot_ae_slot2_encode, Opcode_muljc_h_Slot_ae_slot3_encode, 0, Opcode_muljc_h_Slot_ae2_slot1_encode, Opcode_muljc_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_muljc_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_muljc_h_Slot_ae9_slot2_encode, Opcode_muljc_h_Slot_ae9_slot3_encode, 0, 0, Opcode_muljc_h_Slot_ae10_slot2_encode, Opcode_muljc_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_neg_h_Slot_ae_slot2_encode, Opcode_neg_h_Slot_ae_slot3_encode, 0, Opcode_neg_h_Slot_ae2_slot1_encode, Opcode_neg_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_neg_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_neg_h_Slot_ae9_slot2_encode, Opcode_neg_h_Slot_ae9_slot3_encode, 0, 0, Opcode_neg_h_Slot_ae10_slot2_encode, Opcode_neg_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_oeq_h_encode_fns[] = { + 0, 0, 0, Opcode_oeq_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ole_h_encode_fns[] = { + 0, 0, 0, Opcode_ole_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_olt_h_encode_fns[] = { + 0, 0, 0, Opcode_olt_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ueq_h_encode_fns[] = { + 0, 0, 0, Opcode_ueq_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ule_h_encode_fns[] = { + 0, 0, 0, Opcode_ule_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ult_h_encode_fns[] = { + 0, 0, 0, Opcode_ult_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_un_h_encode_fns[] = { + 0, 0, 0, Opcode_un_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_div0_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_div0_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ficeil_h_encode_fns[] = { + 0, 0, 0, Opcode_ficeil_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ficeil_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_fifloor_h_encode_fns[] = { + 0, 0, 0, Opcode_fifloor_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_fifloor_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_firint_h_encode_fns[] = { + 0, 0, 0, Opcode_firint_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_firint_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_firound_h_encode_fns[] = { + 0, 0, 0, Opcode_firound_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_firound_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_fitrunc_h_encode_fns[] = { + 0, 0, 0, Opcode_fitrunc_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_fitrunc_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mkdadj_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mkdadj_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mksadj_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mksadj_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nexp0_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_nexp0_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nexp01_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_nexp01_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_recip0_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_recip0_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsqrt0_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_rsqrt0_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sqrt0_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_sqrt0_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float16_h_encode_fns[] = { + 0, 0, 0, Opcode_float16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_float16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat16_h_encode_fns[] = { + 0, 0, 0, Opcode_ufloat16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ufloat16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc16_h_encode_fns[] = { + 0, 0, 0, Opcode_trunc16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_trunc16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc16_h_encode_fns[] = { + 0, 0, 0, Opcode_utrunc16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_utrunc16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float16_hx4_encode_fns[] = { + 0, 0, 0, Opcode_float16_hx4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_float16_hx4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat16_hx4_encode_fns[] = { + 0, 0, 0, Opcode_ufloat16_hx4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ufloat16_hx4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc16_hx4_encode_fns[] = { + 0, 0, 0, Opcode_trunc16_hx4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_trunc16_hx4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc16_hx4_encode_fns[] = { + 0, 0, 0, Opcode_utrunc16_hx4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_utrunc16_hx4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_add_h_Slot_ae_slot2_encode, Opcode_add_h_Slot_ae_slot3_encode, 0, 0, Opcode_add_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_add_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_h_Slot_ae9_slot2_encode, Opcode_add_h_Slot_ae9_slot3_encode, 0, 0, Opcode_add_h_Slot_ae10_slot2_encode, Opcode_add_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_sub_h_Slot_ae_slot2_encode, Opcode_sub_h_Slot_ae_slot3_encode, 0, 0, Opcode_sub_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_sub_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_h_Slot_ae9_slot2_encode, Opcode_sub_h_Slot_ae9_slot3_encode, 0, 0, Opcode_sub_h_Slot_ae10_slot2_encode, Opcode_sub_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mul_h_Slot_ae_slot2_encode, Opcode_mul_h_Slot_ae_slot3_encode, 0, 0, Opcode_mul_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_mul_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mul_h_Slot_ae9_slot2_encode, Opcode_mul_h_Slot_ae9_slot3_encode, 0, 0, Opcode_mul_h_Slot_ae10_slot2_encode, Opcode_mul_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madd_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_madd_h_Slot_ae_slot2_encode, Opcode_madd_h_Slot_ae_slot3_encode, 0, 0, Opcode_madd_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_madd_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_madd_h_Slot_ae9_slot2_encode, Opcode_madd_h_Slot_ae9_slot3_encode, 0, 0, Opcode_madd_h_Slot_ae10_slot2_encode, Opcode_madd_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msub_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_msub_h_Slot_ae_slot2_encode, Opcode_msub_h_Slot_ae_slot3_encode, 0, 0, Opcode_msub_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_msub_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msub_h_Slot_ae9_slot2_encode, Opcode_msub_h_Slot_ae9_slot3_encode, 0, 0, Opcode_msub_h_Slot_ae10_slot2_encode, Opcode_msub_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddn_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maddn_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_maddn_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msubn_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_msubn_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msubn_h_Slot_ae9_slot2_encode, Opcode_msubn_h_Slot_ae9_slot3_encode, 0, 0, Opcode_msubn_h_Slot_ae10_slot2_encode, Opcode_msubn_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_divn_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_divn_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_divn_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rminnum_h_encode_fns[] = { + 0, 0, 0, Opcode_rminnum_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_rminnum_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rminnum_h_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rmaxnum_h_encode_fns[] = { + 0, 0, 0, Opcode_rmaxnum_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_rmaxnum_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rmaxnum_h_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_abs_hx4x2_Slot_ae_slot2_encode, Opcode_abs_hx4x2_Slot_ae_slot3_encode, 0, Opcode_abs_hx4x2_Slot_ae2_slot1_encode, Opcode_abs_hx4x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_abs_hx4x2_Slot_ae9_slot2_encode, Opcode_abs_hx4x2_Slot_ae9_slot3_encode, 0, 0, Opcode_abs_hx4x2_Slot_ae10_slot2_encode, Opcode_abs_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_neg_hx4x2_Slot_ae_slot2_encode, Opcode_neg_hx4x2_Slot_ae_slot3_encode, 0, Opcode_neg_hx4x2_Slot_ae2_slot1_encode, Opcode_neg_hx4x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_neg_hx4x2_Slot_ae9_slot2_encode, Opcode_neg_hx4x2_Slot_ae9_slot3_encode, 0, 0, Opcode_neg_hx4x2_Slot_ae10_slot2_encode, Opcode_neg_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_conjc_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_conjc_hx4x2_Slot_ae_slot2_encode, Opcode_conjc_hx4x2_Slot_ae_slot3_encode, 0, Opcode_conjc_hx4x2_Slot_ae2_slot1_encode, Opcode_conjc_hx4x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_conjc_hx4x2_Slot_ae9_slot2_encode, Opcode_conjc_hx4x2_Slot_ae9_slot3_encode, 0, 0, Opcode_conjc_hx4x2_Slot_ae10_slot2_encode, Opcode_conjc_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_const_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_const_hx4x2_Slot_ae_slot2_encode, Opcode_const_hx4x2_Slot_ae_slot3_encode, 0, Opcode_const_hx4x2_Slot_ae2_slot1_encode, Opcode_const_hx4x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_const_hx4x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_const_hx4x2_Slot_ae9_slot2_encode, Opcode_const_hx4x2_Slot_ae9_slot3_encode, 0, 0, Opcode_const_hx4x2_Slot_ae10_slot2_encode, Opcode_const_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muljc_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_muljc_hx4x2_Slot_ae_slot2_encode, Opcode_muljc_hx4x2_Slot_ae_slot3_encode, 0, Opcode_muljc_hx4x2_Slot_ae2_slot1_encode, Opcode_muljc_hx4x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_muljc_hx4x2_Slot_ae9_slot2_encode, Opcode_muljc_hx4x2_Slot_ae9_slot3_encode, 0, 0, Opcode_muljc_hx4x2_Slot_ae10_slot2_encode, Opcode_muljc_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_hx4x2_Slot_ae10_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_hx4x2_Slot_ae10_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mul_hx4x2_Slot_ae10_slot2_encode, Opcode_mul_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madd_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_madd_hx4x2_Slot_ae10_slot2_encode, Opcode_madd_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msub_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msub_hx4x2_Slot_ae10_slot2_encode, Opcode_msub_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulq_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulq_h_Slot_ae9_slot2_encode, 0, 0, 0, Opcode_mulq_h_Slot_ae10_slot2_encode, Opcode_mulq_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddq_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddq_h_Slot_ae10_slot2_encode, Opcode_maddq_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulcnvh_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulcnvh_hx4x2_Slot_ae10_slot2_encode, Opcode_mulcnvh_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulacnvh_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulacnvh_hx4x2_Slot_ae10_slot2_encode, Opcode_mulacnvh_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulcnvl_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulcnvl_hx4x2_Slot_ae10_slot2_encode, Opcode_mulcnvl_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulacnvl_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulacnvl_hx4x2_Slot_ae10_slot2_encode, Opcode_mulacnvl_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +int num_bypass_groups() { + return 0; +} + +int num_bypass_group_chunks() { + return 0; +} + +uint32 *bypass_entry(int i) { + return 0; +} + + +/* Opcode table. */ + +static xtensa_funcUnit_use Opcode_l32e_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32e_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32i_n_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32i_n_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l16ui_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l16si_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32r_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l8ui_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32ex_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32ex_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s16i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32nb_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s8i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_lddr32_p_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sddr32_p_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_lict_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_licw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sict_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sicw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sdct_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ldct_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sdcw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ldcw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32ai_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32ri_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4f_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4f_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4f_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4f_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4s_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4s_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4s_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4u_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4u_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4u_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4u_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ri_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4rng_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4rng_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4rng_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4rng_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2rng_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2rng_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2rng_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2rng_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2rng_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2rng_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2rng_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2rng_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lalign64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_salign64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la64_pp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa64pos_fp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa64neg_fp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24x2ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4ra32s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 } +}; + +static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbs_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbsi_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbki_dbi_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbki_dbi_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbki_dbi_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbi_dbi_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbi_dbi_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbi_dbi_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbk_db_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbk_db_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbk_db_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lb_db_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lb_db_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lb_db_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16si_n_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16ui_n_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16i_n_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lalign128_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_salign128_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la128_pp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa128pos_fp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x4s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x4u_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lav8x8x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lav16x4x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sav8x8x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sav16x4x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lavunsqz8x8_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lavunsqz16x4_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_opcode_internal opcodes[] = { + { "excw", ICLASS_xt_iclass_excw, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", ICLASS_xt_iclass_rfe, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", ICLASS_xt_iclass_rfde, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", ICLASS_xt_iclass_syscall, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "call12", ICLASS_xt_iclass_call12, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", ICLASS_xt_iclass_call8, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", ICLASS_xt_iclass_call4, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", ICLASS_xt_iclass_callx12, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", ICLASS_xt_iclass_callx8, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", ICLASS_xt_iclass_callx4, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", ICLASS_xt_iclass_entry, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", ICLASS_xt_iclass_movsp, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", ICLASS_xt_iclass_rotw, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", ICLASS_xt_iclass_l32e, + 0, + Opcode_l32e_encode_fns, 1, Opcode_l32e_funcUnit_uses }, + { "s32e", ICLASS_xt_iclass_s32e, + 0, + Opcode_s32e_encode_fns, 1, Opcode_s32e_funcUnit_uses }, + { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", ICLASS_xt_iclass_add_n, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", ICLASS_xt_iclass_addi_n, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", ICLASS_xt_iclass_ill_n, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", ICLASS_xt_iclass_loadi4, + 0, + Opcode_l32i_n_encode_fns, 1, Opcode_l32i_n_funcUnit_uses }, + { "mov.n", ICLASS_xt_iclass_mov_n, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", ICLASS_xt_iclass_movi_n, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", ICLASS_xt_iclass_nopn, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", ICLASS_xt_iclass_retn, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", ICLASS_xt_iclass_storei4, + 0, + Opcode_s32i_n_encode_fns, 1, Opcode_s32i_n_funcUnit_uses }, + { "rur.threadptr", ICLASS_rur_threadptr, + 0, + Opcode_rur_threadptr_encode_fns, 0, 0 }, + { "wur.threadptr", ICLASS_wur_threadptr, + 0, + Opcode_wur_threadptr_encode_fns, 0, 0 }, + { "addi", ICLASS_xt_iclass_addi, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", ICLASS_xt_iclass_addmi, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", ICLASS_xt_iclass_addsub, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "addx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "sub", ICLASS_xt_iclass_addsub, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "subx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", ICLASS_xt_iclass_bit, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", ICLASS_xt_iclass_bit, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", ICLASS_xt_iclass_bit, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bgei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bnei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bbci", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "ball", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bany", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bbc", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beq", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bge", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "bgeu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "blt", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bltu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bnall", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bne", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bnone", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "beqz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bgez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "bnez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "call0", ICLASS_xt_iclass_call0, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", ICLASS_xt_iclass_callx0, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "extui", ICLASS_xt_iclass_exti, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", ICLASS_xt_iclass_ill, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", ICLASS_xt_iclass_jump, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", ICLASS_xt_iclass_jumpx, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", ICLASS_xt_iclass_l16ui, + 0, + Opcode_l16ui_encode_fns, 1, Opcode_l16ui_funcUnit_uses }, + { "l16si", ICLASS_xt_iclass_l16si, + 0, + Opcode_l16si_encode_fns, 1, Opcode_l16si_funcUnit_uses }, + { "l32i", ICLASS_xt_iclass_l32i, + 0, + Opcode_l32i_encode_fns, 1, Opcode_l32i_funcUnit_uses }, + { "l32r", ICLASS_xt_iclass_l32r, + 0, + Opcode_l32r_encode_fns, 1, Opcode_l32r_funcUnit_uses }, + { "l8ui", ICLASS_xt_iclass_l8i, + 0, + Opcode_l8ui_encode_fns, 1, Opcode_l8ui_funcUnit_uses }, + { "loop", ICLASS_xt_iclass_loop, + XTENSA_OPCODE_IS_LOOP, + Opcode_loop_encode_fns, 0, 0 }, + { "loopgtz", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopgtz_encode_fns, 0, 0 }, + { "loopnez", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopnez_encode_fns, 0, 0 }, + { "movi", ICLASS_xt_iclass_movi, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", ICLASS_xt_iclass_movz, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movgez", ICLASS_xt_iclass_movz, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "movltz", ICLASS_xt_iclass_movz, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movnez", ICLASS_xt_iclass_movz, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "abs", ICLASS_xt_iclass_neg, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "neg", ICLASS_xt_iclass_neg, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "nop", ICLASS_xt_iclass_nop, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "l32ex", ICLASS_xt_iclass_l32ex, + 0, + Opcode_l32ex_encode_fns, 1, Opcode_l32ex_funcUnit_uses }, + { "s32ex", ICLASS_xt_iclass_s32ex, + 0, + Opcode_s32ex_encode_fns, 1, Opcode_s32ex_funcUnit_uses }, + { "getex", ICLASS_xt_iclass_getex, + 0, + Opcode_getex_encode_fns, 0, 0 }, + { "clrex", ICLASS_xt_iclass_clrex, + 0, + Opcode_clrex_encode_fns, 0, 0 }, + { "ret", ICLASS_xt_iclass_return, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "simcall", ICLASS_xt_iclass_simcall, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "s16i", ICLASS_xt_iclass_s16i, + 0, + Opcode_s16i_encode_fns, 1, Opcode_s16i_funcUnit_uses }, + { "s32i", ICLASS_xt_iclass_s32i, + 0, + Opcode_s32i_encode_fns, 1, Opcode_s32i_funcUnit_uses }, + { "s32nb", ICLASS_xt_iclass_s32nb, + 0, + Opcode_s32nb_encode_fns, 1, Opcode_s32nb_funcUnit_uses }, + { "s8i", ICLASS_xt_iclass_s8i, + 0, + Opcode_s8i_encode_fns, 1, Opcode_s8i_funcUnit_uses }, + { "ssa8b", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssa8l", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssl", ICLASS_xt_iclass_sar, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssr", ICLASS_xt_iclass_sar, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssai", ICLASS_xt_iclass_sari, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", ICLASS_xt_iclass_shifts, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", ICLASS_xt_iclass_shiftst, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "sra", ICLASS_xt_iclass_shiftt, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "srl", ICLASS_xt_iclass_shiftt, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "slli", ICLASS_xt_iclass_slli, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", ICLASS_xt_iclass_srai, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", ICLASS_xt_iclass_srli, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", ICLASS_xt_iclass_memw, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", ICLASS_xt_iclass_extw, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", ICLASS_xt_iclass_isync, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "dsync", ICLASS_xt_iclass_sync, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "esync", ICLASS_xt_iclass_sync, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "rsync", ICLASS_xt_iclass_sync, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "rsil", ICLASS_xt_iclass_rsil, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.lend", ICLASS_xt_iclass_rsr_lend, + 0, + Opcode_rsr_lend_encode_fns, 0, 0 }, + { "wsr.lend", ICLASS_xt_iclass_wsr_lend, + 0, + Opcode_wsr_lend_encode_fns, 0, 0 }, + { "xsr.lend", ICLASS_xt_iclass_xsr_lend, + 0, + Opcode_xsr_lend_encode_fns, 0, 0 }, + { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, + 0, + Opcode_rsr_lcount_encode_fns, 0, 0 }, + { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, + 0, + Opcode_wsr_lcount_encode_fns, 0, 0 }, + { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, + 0, + Opcode_xsr_lcount_encode_fns, 0, 0 }, + { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, + 0, + Opcode_rsr_lbeg_encode_fns, 0, 0 }, + { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, + 0, + Opcode_wsr_lbeg_encode_fns, 0, 0 }, + { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, + 0, + Opcode_xsr_lbeg_encode_fns, 0, 0 }, + { "rsr.sar", ICLASS_xt_iclass_rsr_sar, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", ICLASS_xt_iclass_wsr_sar, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", ICLASS_xt_iclass_xsr_sar, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl, + 0, + Opcode_rsr_memctl_encode_fns, 0, 0 }, + { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl, + 0, + Opcode_wsr_memctl_encode_fns, 0, 0 }, + { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl, + 0, + Opcode_xsr_memctl_encode_fns, 0, 0 }, + { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, + 0, + Opcode_rsr_configid0_encode_fns, 0, 0 }, + { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, + 0, + Opcode_wsr_configid0_encode_fns, 0, 0 }, + { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, + 0, + Opcode_rsr_configid1_encode_fns, 0, 0 }, + { "rsr.ps", ICLASS_xt_iclass_rsr_ps, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", ICLASS_xt_iclass_wsr_ps, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", ICLASS_xt_iclass_xsr_ps, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, + 0, + Opcode_rsr_epc3_encode_fns, 0, 0 }, + { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, + 0, + Opcode_wsr_epc3_encode_fns, 0, 0 }, + { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, + 0, + Opcode_xsr_epc3_encode_fns, 0, 0 }, + { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, + 0, + Opcode_rsr_excsave3_encode_fns, 0, 0 }, + { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, + 0, + Opcode_wsr_excsave3_encode_fns, 0, 0 }, + { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, + 0, + Opcode_xsr_excsave3_encode_fns, 0, 0 }, + { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, + 0, + Opcode_rsr_epc4_encode_fns, 0, 0 }, + { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, + 0, + Opcode_wsr_epc4_encode_fns, 0, 0 }, + { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, + 0, + Opcode_xsr_epc4_encode_fns, 0, 0 }, + { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, + 0, + Opcode_rsr_excsave4_encode_fns, 0, 0 }, + { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, + 0, + Opcode_wsr_excsave4_encode_fns, 0, 0 }, + { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, + 0, + Opcode_xsr_excsave4_encode_fns, 0, 0 }, + { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, + 0, + Opcode_rsr_epc5_encode_fns, 0, 0 }, + { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, + 0, + Opcode_wsr_epc5_encode_fns, 0, 0 }, + { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, + 0, + Opcode_xsr_epc5_encode_fns, 0, 0 }, + { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, + 0, + Opcode_rsr_excsave5_encode_fns, 0, 0 }, + { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, + 0, + Opcode_wsr_excsave5_encode_fns, 0, 0 }, + { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, + 0, + Opcode_xsr_excsave5_encode_fns, 0, 0 }, + { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, + 0, + Opcode_rsr_epc6_encode_fns, 0, 0 }, + { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, + 0, + Opcode_wsr_epc6_encode_fns, 0, 0 }, + { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, + 0, + Opcode_xsr_epc6_encode_fns, 0, 0 }, + { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, + 0, + Opcode_rsr_excsave6_encode_fns, 0, 0 }, + { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, + 0, + Opcode_wsr_excsave6_encode_fns, 0, 0 }, + { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, + 0, + Opcode_xsr_excsave6_encode_fns, 0, 0 }, + { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, + 0, + Opcode_rsr_eps3_encode_fns, 0, 0 }, + { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, + 0, + Opcode_wsr_eps3_encode_fns, 0, 0 }, + { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, + 0, + Opcode_xsr_eps3_encode_fns, 0, 0 }, + { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, + 0, + Opcode_rsr_eps4_encode_fns, 0, 0 }, + { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, + 0, + Opcode_wsr_eps4_encode_fns, 0, 0 }, + { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, + 0, + Opcode_xsr_eps4_encode_fns, 0, 0 }, + { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, + 0, + Opcode_rsr_eps5_encode_fns, 0, 0 }, + { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, + 0, + Opcode_wsr_eps5_encode_fns, 0, 0 }, + { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, + 0, + Opcode_xsr_eps5_encode_fns, 0, 0 }, + { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, + 0, + Opcode_rsr_eps6_encode_fns, 0, 0 }, + { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, + 0, + Opcode_wsr_eps6_encode_fns, 0, 0 }, + { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, + 0, + Opcode_xsr_eps6_encode_fns, 0, 0 }, + { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", ICLASS_xt_iclass_rsr_depc, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", ICLASS_xt_iclass_wsr_depc, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", ICLASS_xt_iclass_xsr_depc, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, + 0, + Opcode_rsr_misc0_encode_fns, 0, 0 }, + { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, + 0, + Opcode_wsr_misc0_encode_fns, 0, 0 }, + { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, + 0, + Opcode_xsr_misc0_encode_fns, 0, 0 }, + { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, + 0, + Opcode_rsr_misc1_encode_fns, 0, 0 }, + { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, + 0, + Opcode_wsr_misc1_encode_fns, 0, 0 }, + { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, + 0, + Opcode_xsr_misc1_encode_fns, 0, 0 }, + { "rsr.misc2", ICLASS_xt_iclass_rsr_misc2, + 0, + Opcode_rsr_misc2_encode_fns, 0, 0 }, + { "wsr.misc2", ICLASS_xt_iclass_wsr_misc2, + 0, + Opcode_wsr_misc2_encode_fns, 0, 0 }, + { "xsr.misc2", ICLASS_xt_iclass_xsr_misc2, + 0, + Opcode_xsr_misc2_encode_fns, 0, 0 }, + { "rsr.misc3", ICLASS_xt_iclass_rsr_misc3, + 0, + Opcode_rsr_misc3_encode_fns, 0, 0 }, + { "wsr.misc3", ICLASS_xt_iclass_wsr_misc3, + 0, + Opcode_wsr_misc3_encode_fns, 0, 0 }, + { "xsr.misc3", ICLASS_xt_iclass_xsr_misc3, + 0, + Opcode_xsr_misc3_encode_fns, 0, 0 }, + { "rsr.prid", ICLASS_xt_iclass_rsr_prid, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, + 0, + Opcode_rsr_vecbase_encode_fns, 0, 0 }, + { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, + 0, + Opcode_wsr_vecbase_encode_fns, 0, 0 }, + { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, + 0, + Opcode_xsr_vecbase_encode_fns, 0, 0 }, + { "rsr.mpucfg", ICLASS_xt_iclass_rsr_mpucfg, + 0, + Opcode_rsr_mpucfg_encode_fns, 0, 0 }, + { "wsr.mpucfg", ICLASS_xt_iclass_wsr_mpucfg, + 0, + Opcode_wsr_mpucfg_encode_fns, 0, 0 }, + { "salt", ICLASS_xt_iclass_salt, + 0, + Opcode_salt_encode_fns, 0, 0 }, + { "saltu", ICLASS_xt_iclass_salt, + 0, + Opcode_saltu_encode_fns, 0, 0 }, + { "rsr.opmode", ICLASS_xt_iclass_rsr_opmode, + 0, + Opcode_rsr_opmode_encode_fns, 0, 0 }, + { "wsr.opmode", ICLASS_xt_iclass_wsr_opmode, + 0, + Opcode_wsr_opmode_encode_fns, 0, 0 }, + { "xsr.opmode", ICLASS_xt_iclass_xsr_opmode, + 0, + Opcode_xsr_opmode_encode_fns, 0, 0 }, + { "mul16s", ICLASS_xt_mul16, + 0, + Opcode_mul16s_encode_fns, 0, 0 }, + { "mul16u", ICLASS_xt_mul16, + 0, + Opcode_mul16u_encode_fns, 0, 0 }, + { "mull", ICLASS_xt_mul32, + 0, + Opcode_mull_encode_fns, 0, 0 }, + { "rfi", ICLASS_xt_iclass_rfi, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", ICLASS_xt_iclass_wait, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", ICLASS_xt_iclass_wsr_intset, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", ICLASS_xt_iclass_break, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", ICLASS_xt_iclass_break_n, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, + 0, + Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, + { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, + 0, + Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, + { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, + 0, + Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, + { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, + 0, + Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, + { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, + 0, + Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, + { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, + 0, + Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, + { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, + 0, + Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, + { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, + 0, + Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, + { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, + 0, + Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, + { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, + 0, + Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, + { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, + 0, + Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, + { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, + 0, + Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, + { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, + 0, + Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, + { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, + 0, + Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, + { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, + 0, + Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, + { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, + 0, + Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, + { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, + 0, + Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, + { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, + 0, + Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, + { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, + 0, + Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, + { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, + 0, + Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, + { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, + 0, + Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, + { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", ICLASS_xt_iclass_rsr_icount, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", ICLASS_xt_iclass_wsr_icount, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", ICLASS_xt_iclass_xsr_icount, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "lddr32.p", ICLASS_xt_iclass_lddr32_p, + 0, + Opcode_lddr32_p_encode_fns, 1, Opcode_lddr32_p_funcUnit_uses }, + { "sddr32.p", ICLASS_xt_iclass_sddr32_p, + 0, + Opcode_sddr32_p_encode_fns, 1, Opcode_sddr32_p_funcUnit_uses }, + { "rfdo", ICLASS_xt_iclass_rfdo, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", ICLASS_xt_iclass_rfdd, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, + 0, + Opcode_wsr_mmid_encode_fns, 0, 0 }, + { "andb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andb_encode_fns, 0, 0 }, + { "andbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andbc_encode_fns, 0, 0 }, + { "orb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orb_encode_fns, 0, 0 }, + { "orbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orbc_encode_fns, 0, 0 }, + { "xorb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_xorb_encode_fns, 0, 0 }, + { "all4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_all4_encode_fns, 0, 0 }, + { "any4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_any4_encode_fns, 0, 0 }, + { "all8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_all8_encode_fns, 0, 0 }, + { "any8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_any8_encode_fns, 0, 0 }, + { "bf", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bf_encode_fns, 0, 0 }, + { "bt", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bt_encode_fns, 0, 0 }, + { "movf", ICLASS_xt_iclass_bmove, + 0, + Opcode_movf_encode_fns, 0, 0 }, + { "movt", ICLASS_xt_iclass_bmove, + 0, + Opcode_movt_encode_fns, 0, 0 }, + { "rsr.br", ICLASS_xt_iclass_RSR_BR, + 0, + Opcode_rsr_br_encode_fns, 0, 0 }, + { "wsr.br", ICLASS_xt_iclass_WSR_BR, + 0, + Opcode_wsr_br_encode_fns, 0, 0 }, + { "xsr.br", ICLASS_xt_iclass_XSR_BR, + 0, + Opcode_xsr_br_encode_fns, 0, 0 }, + { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, + 0, + Opcode_rsr_ccompare1_encode_fns, 0, 0 }, + { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, + 0, + Opcode_wsr_ccompare1_encode_fns, 0, 0 }, + { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, + 0, + Opcode_xsr_ccompare1_encode_fns, 0, 0 }, + { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, + 0, + Opcode_rsr_ccompare2_encode_fns, 0, 0 }, + { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, + 0, + Opcode_wsr_ccompare2_encode_fns, 0, 0 }, + { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, + 0, + Opcode_xsr_ccompare2_encode_fns, 0, 0 }, + { "ihi", ICLASS_xt_iclass_icache, + 0, + Opcode_ihi_encode_fns, 0, 0 }, + { "ipf", ICLASS_xt_iclass_icache, + 0, + Opcode_ipf_encode_fns, 0, 0 }, + { "ihu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ihu_encode_fns, 0, 0 }, + { "iiu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_iiu_encode_fns, 0, 0 }, + { "ipfl", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ipfl_encode_fns, 0, 0 }, + { "iii", ICLASS_xt_iclass_icache_inv, + 0, + Opcode_iii_encode_fns, 0, 0 }, + { "lict", ICLASS_xt_iclass_licx, + 0, + Opcode_lict_encode_fns, 1, Opcode_lict_funcUnit_uses }, + { "licw", ICLASS_xt_iclass_licx, + 0, + Opcode_licw_encode_fns, 1, Opcode_licw_funcUnit_uses }, + { "sict", ICLASS_xt_iclass_sicx, + 0, + Opcode_sict_encode_fns, 1, Opcode_sict_funcUnit_uses }, + { "sicw", ICLASS_xt_iclass_sicx, + 0, + Opcode_sicw_encode_fns, 1, Opcode_sicw_funcUnit_uses }, + { "dhwb", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwb_encode_fns, 0, 0 }, + { "dhwbi", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwbi_encode_fns, 0, 0 }, + { "diwbui.p", ICLASS_xt_iclass_dcache_dyn, + 0, + Opcode_diwbui_p_encode_fns, 0, 0 }, + { "diwb", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwb_encode_fns, 0, 0 }, + { "diwbi", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwbi_encode_fns, 0, 0 }, + { "dhi", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dhi_encode_fns, 0, 0 }, + { "dii", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dii_encode_fns, 0, 0 }, + { "dpfr", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfr_encode_fns, 0, 0 }, + { "dpfro", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfro_encode_fns, 0, 0 }, + { "dpfw", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfw_encode_fns, 0, 0 }, + { "dpfwo", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfwo_encode_fns, 0, 0 }, + { "dpfm.b", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfm_b_encode_fns, 0, 0 }, + { "dpfm.bf", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfm_bf_encode_fns, 0, 0 }, + { "dpfr.b", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfr_b_encode_fns, 0, 0 }, + { "dpfr.bf", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfr_bf_encode_fns, 0, 0 }, + { "dpfw.b", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfw_b_encode_fns, 0, 0 }, + { "dpfw.bf", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfw_bf_encode_fns, 0, 0 }, + { "pfnxt.f", ICLASS_xt_iclass_bpfnxt, + 0, + Opcode_pfnxt_f_encode_fns, 0, 0 }, + { "dhi.b", ICLASS_xt_iclass_dpdngrd, + 0, + Opcode_dhi_b_encode_fns, 0, 0 }, + { "dhwbi.b", ICLASS_xt_iclass_dpdngrd, + 0, + Opcode_dhwbi_b_encode_fns, 0, 0 }, + { "dhwb.b", ICLASS_xt_iclass_dpdngrd, + 0, + Opcode_dhwb_b_encode_fns, 0, 0 }, + { "pfend.a", ICLASS_xt_iclass_bpfctl, + 0, + Opcode_pfend_a_encode_fns, 0, 0 }, + { "pfend.o", ICLASS_xt_iclass_bpfctl, + 0, + Opcode_pfend_o_encode_fns, 0, 0 }, + { "pfwait.a", ICLASS_xt_iclass_bpfctl, + 0, + Opcode_pfwait_a_encode_fns, 0, 0 }, + { "pfwait.r", ICLASS_xt_iclass_bpfctl, + 0, + Opcode_pfwait_r_encode_fns, 0, 0 }, + { "dhu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dhu_encode_fns, 0, 0 }, + { "diu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_diu_encode_fns, 0, 0 }, + { "dpfl", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dpfl_encode_fns, 0, 0 }, + { "sdct", ICLASS_xt_iclass_sdct, + 0, + Opcode_sdct_encode_fns, 1, Opcode_sdct_funcUnit_uses }, + { "ldct", ICLASS_xt_iclass_ldct, + 0, + Opcode_ldct_encode_fns, 1, Opcode_ldct_funcUnit_uses }, + { "sdcw", ICLASS_xt_iclass_sdcw, + 0, + Opcode_sdcw_encode_fns, 1, Opcode_sdcw_funcUnit_uses }, + { "ldcw", ICLASS_xt_iclass_ldcw, + 0, + Opcode_ldcw_encode_fns, 1, Opcode_ldcw_funcUnit_uses }, + { "rsr.prefctl", ICLASS_xt_iclass_rsr_prefctl, + 0, + Opcode_rsr_prefctl_encode_fns, 0, 0 }, + { "wsr.prefctl", ICLASS_xt_iclass_wsr_prefctl, + 0, + Opcode_wsr_prefctl_encode_fns, 0, 0 }, + { "xsr.prefctl", ICLASS_xt_iclass_xsr_prefctl, + 0, + Opcode_xsr_prefctl_encode_fns, 0, 0 }, + { "wsr.cacheadrdis", ICLASS_xt_iclass_wsr_cacheadrdis, + 0, + Opcode_wsr_cacheadrdis_encode_fns, 0, 0 }, + { "rsr.cacheadrdis", ICLASS_xt_iclass_rsr_cacheadrdis, + 0, + Opcode_rsr_cacheadrdis_encode_fns, 0, 0 }, + { "xsr.cacheadrdis", ICLASS_xt_iclass_xsr_cacheadrdis, + 0, + Opcode_xsr_cacheadrdis_encode_fns, 0, 0 }, + { "rptlb0", ICLASS_xt_iclass_rptlb0, + 0, + Opcode_rptlb0_encode_fns, 0, 0 }, + { "pptlb", ICLASS_xt_iclass_rptlb, + 0, + Opcode_pptlb_encode_fns, 0, 0 }, + { "rptlb1", ICLASS_xt_iclass_rptlb, + 0, + Opcode_rptlb1_encode_fns, 0, 0 }, + { "wptlb", ICLASS_xt_iclass_wptlb, + 0, + Opcode_wptlb_encode_fns, 0, 0 }, + { "rsr.mpuenb", ICLASS_xt_iclass_rsr_mpuenb, + 0, + Opcode_rsr_mpuenb_encode_fns, 0, 0 }, + { "wsr.mpuenb", ICLASS_xt_iclass_wsr_mpuenb, + 0, + Opcode_wsr_mpuenb_encode_fns, 0, 0 }, + { "xsr.mpuenb", ICLASS_xt_iclass_xsr_mpuenb, + 0, + Opcode_xsr_mpuenb_encode_fns, 0, 0 }, + { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, + 0, + Opcode_rsr_cpenable_encode_fns, 0, 0 }, + { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, + 0, + Opcode_wsr_cpenable_encode_fns, 0, 0 }, + { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, + 0, + Opcode_xsr_cpenable_encode_fns, 0, 0 }, + { "clamps", ICLASS_xt_iclass_clamp, + 0, + Opcode_clamps_encode_fns, 0, 0 }, + { "max", ICLASS_xt_iclass_minmax, + 0, + Opcode_max_encode_fns, 0, 0 }, + { "maxu", ICLASS_xt_iclass_minmax, + 0, + Opcode_maxu_encode_fns, 0, 0 }, + { "min", ICLASS_xt_iclass_minmax, + 0, + Opcode_min_encode_fns, 0, 0 }, + { "minu", ICLASS_xt_iclass_minmax, + 0, + Opcode_minu_encode_fns, 0, 0 }, + { "nsa", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsau_encode_fns, 0, 0 }, + { "sext", ICLASS_xt_iclass_sx, + 0, + Opcode_sext_encode_fns, 0, 0 }, + { "l32ai", ICLASS_xt_iclass_l32ai, + 0, + Opcode_l32ai_encode_fns, 1, Opcode_l32ai_funcUnit_uses }, + { "s32ri", ICLASS_xt_iclass_s32ri, + 0, + Opcode_s32ri_encode_fns, 1, Opcode_s32ri_funcUnit_uses }, + { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, + 0, + Opcode_rsr_atomctl_encode_fns, 0, 0 }, + { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, + 0, + Opcode_wsr_atomctl_encode_fns, 0, 0 }, + { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, + 0, + Opcode_xsr_atomctl_encode_fns, 0, 0 }, + { "quos", ICLASS_xt_iclass_div, + 0, + Opcode_quos_encode_fns, 0, 0 }, + { "quou", ICLASS_xt_iclass_div, + 0, + Opcode_quou_encode_fns, 0, 0 }, + { "rems", ICLASS_xt_iclass_div, + 0, + Opcode_rems_encode_fns, 0, 0 }, + { "remu", ICLASS_xt_iclass_div, + 0, + Opcode_remu_encode_fns, 0, 0 }, + { "rsr.eraccess", ICLASS_xt_iclass_rsr_eraccess, + 0, + Opcode_rsr_eraccess_encode_fns, 0, 0 }, + { "wsr.eraccess", ICLASS_xt_iclass_wsr_eraccess, + 0, + Opcode_wsr_eraccess_encode_fns, 0, 0 }, + { "xsr.eraccess", ICLASS_xt_iclass_xsr_eraccess, + 0, + Opcode_xsr_eraccess_encode_fns, 0, 0 }, + { "rer", ICLASS_xt_iclass_rer, + 0, + Opcode_rer_encode_fns, 0, 0 }, + { "wer", ICLASS_xt_iclass_wer, + 0, + Opcode_wer_encode_fns, 0, 0 }, + { "beqz.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_w15_encode_fns, 0, 0 }, + { "bgez.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_w15_encode_fns, 0, 0 }, + { "bltz.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_w15_encode_fns, 0, 0 }, + { "bnez.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_w15_encode_fns, 0, 0 }, + { "beqi.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_w15_encode_fns, 0, 0 }, + { "bgei.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_w15_encode_fns, 0, 0 }, + { "blti.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_w15_encode_fns, 0, 0 }, + { "bnei.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_w15_encode_fns, 0, 0 }, + { "bgeui.w15", ICLASS_xt_iclass_wb15_2, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_w15_encode_fns, 0, 0 }, + { "bltui.w15", ICLASS_xt_iclass_wb15_2, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_w15_encode_fns, 0, 0 }, + { "bbci.w15", ICLASS_xt_iclass_wb15_3, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_w15_encode_fns, 0, 0 }, + { "bbsi.w15", ICLASS_xt_iclass_wb15_3, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_w15_encode_fns, 0, 0 }, + { "ball.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_w15_encode_fns, 0, 0 }, + { "bany.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_w15_encode_fns, 0, 0 }, + { "bbc.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_w15_encode_fns, 0, 0 }, + { "bbs.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_w15_encode_fns, 0, 0 }, + { "beq.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_w15_encode_fns, 0, 0 }, + { "bgeu.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_w15_encode_fns, 0, 0 }, + { "bge.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_w15_encode_fns, 0, 0 }, + { "bltu.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_w15_encode_fns, 0, 0 }, + { "blt.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_w15_encode_fns, 0, 0 }, + { "bnall.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_w15_encode_fns, 0, 0 }, + { "bne.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_w15_encode_fns, 0, 0 }, + { "bnone.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_w15_encode_fns, 0, 0 }, + { "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar, + 0, + Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 }, + { "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar, + 0, + Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 }, + { "rur.ae_bithead", ICLASS_rur_ae_bithead, + 0, + Opcode_rur_ae_bithead_encode_fns, 0, 0 }, + { "wur.ae_bithead", ICLASS_wur_ae_bithead, + 0, + Opcode_wur_ae_bithead_encode_fns, 0, 0 }, + { "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp, + 0, + Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, + { "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp, + 0, + Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, + { "rur.ae_cw_sd_no", ICLASS_rur_ae_cw_sd_no, + 0, + Opcode_rur_ae_cw_sd_no_encode_fns, 0, 0 }, + { "wur.ae_cw_sd_no", ICLASS_wur_ae_cw_sd_no, + 0, + Opcode_wur_ae_cw_sd_no_encode_fns, 0, 0 }, + { "rur.ae_cbegin0", ICLASS_rur_ae_cbegin0, + 0, + Opcode_rur_ae_cbegin0_encode_fns, 0, 0 }, + { "wur.ae_cbegin0", ICLASS_wur_ae_cbegin0, + 0, + Opcode_wur_ae_cbegin0_encode_fns, 0, 0 }, + { "rur.ae_cend0", ICLASS_rur_ae_cend0, + 0, + Opcode_rur_ae_cend0_encode_fns, 0, 0 }, + { "wur.ae_cend0", ICLASS_wur_ae_cend0, + 0, + Opcode_wur_ae_cend0_encode_fns, 0, 0 }, + { "rur.ae_cbegin1", ICLASS_rur_ae_cbegin1, + 0, + Opcode_rur_ae_cbegin1_encode_fns, 0, 0 }, + { "wur.ae_cbegin1", ICLASS_wur_ae_cbegin1, + 0, + Opcode_wur_ae_cbegin1_encode_fns, 0, 0 }, + { "rur.ae_cend1", ICLASS_rur_ae_cend1, + 0, + Opcode_rur_ae_cend1_encode_fns, 0, 0 }, + { "wur.ae_cend1", ICLASS_wur_ae_cend1, + 0, + Opcode_wur_ae_cend1_encode_fns, 0, 0 }, + { "rur.ae_cbegin2", ICLASS_rur_ae_cbegin2, + 0, + Opcode_rur_ae_cbegin2_encode_fns, 0, 0 }, + { "wur.ae_cbegin2", ICLASS_wur_ae_cbegin2, + 0, + Opcode_wur_ae_cbegin2_encode_fns, 0, 0 }, + { "rur.ae_cend2", ICLASS_rur_ae_cend2, + 0, + Opcode_rur_ae_cend2_encode_fns, 0, 0 }, + { "wur.ae_cend2", ICLASS_wur_ae_cend2, + 0, + Opcode_wur_ae_cend2_encode_fns, 0, 0 }, + { "ae_sext16", ICLASS_ic_sext16, + 0, + Opcode_ae_sext16_encode_fns, 0, 0 }, + { "ae_zext16", ICLASS_ic_zext16, + 0, + Opcode_ae_zext16_encode_fns, 0, 0 }, + { "ae_zext8", ICLASS_ic_zext8, + 0, + Opcode_ae_zext8_encode_fns, 0, 0 }, + { "ae_clamps16", ICLASS_ic_clamps16, + 0, + Opcode_ae_clamps16_encode_fns, 0, 0 }, + { "rur.fcr", ICLASS_rur_fcr, + 0, + Opcode_rur_fcr_encode_fns, 0, 0 }, + { "wur.fcr", ICLASS_wur_fcr, + 0, + Opcode_wur_fcr_encode_fns, 0, 0 }, + { "rur.fsr", ICLASS_rur_fsr, + 0, + Opcode_rur_fsr_encode_fns, 0, 0 }, + { "wur.fsr", ICLASS_wur_fsr, + 0, + Opcode_wur_fsr_encode_fns, 0, 0 }, + { "rur.expstate", ICLASS_rur_expstate, + 0, + Opcode_rur_expstate_encode_fns, 0, 0 }, + { "wur.expstate", ICLASS_wur_expstate, + 0, + Opcode_wur_expstate_encode_fns, 0, 0 }, + { "read_impwire", ICLASS_iclass_READ_IMPWIRE, + 0, + Opcode_read_impwire_encode_fns, 0, 0 }, + { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, + 0, + Opcode_setb_expstate_encode_fns, 0, 0 }, + { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, + 0, + Opcode_clrb_expstate_encode_fns, 0, 0 }, + { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, + 0, + Opcode_wrmsk_expstate_encode_fns, 0, 0 }, + { "rur.ae_overflow", ICLASS_RUR_AE_OVERFLOW, + 0, + Opcode_rur_ae_overflow_encode_fns, 0, 0 }, + { "wur.ae_overflow", ICLASS_WUR_AE_OVERFLOW, + 0, + Opcode_wur_ae_overflow_encode_fns, 0, 0 }, + { "rur.ae_sar", ICLASS_RUR_AE_SAR, + 0, + Opcode_rur_ae_sar_encode_fns, 0, 0 }, + { "wur.ae_sar", ICLASS_WUR_AE_SAR, + 0, + Opcode_wur_ae_sar_encode_fns, 0, 0 }, + { "rur.ae_bitptr", ICLASS_RUR_AE_BITPTR, + 0, + Opcode_rur_ae_bitptr_encode_fns, 0, 0 }, + { "wur.ae_bitptr", ICLASS_WUR_AE_BITPTR, + 0, + Opcode_wur_ae_bitptr_encode_fns, 0, 0 }, + { "rur.ae_bitsused", ICLASS_RUR_AE_BITSUSED, + 0, + Opcode_rur_ae_bitsused_encode_fns, 0, 0 }, + { "wur.ae_bitsused", ICLASS_WUR_AE_BITSUSED, + 0, + Opcode_wur_ae_bitsused_encode_fns, 0, 0 }, + { "rur.ae_tablesize", ICLASS_RUR_AE_TABLESIZE, + 0, + Opcode_rur_ae_tablesize_encode_fns, 0, 0 }, + { "wur.ae_tablesize", ICLASS_WUR_AE_TABLESIZE, + 0, + Opcode_wur_ae_tablesize_encode_fns, 0, 0 }, + { "rur.ae_first_ts", ICLASS_RUR_AE_FIRST_TS, + 0, + Opcode_rur_ae_first_ts_encode_fns, 0, 0 }, + { "wur.ae_first_ts", ICLASS_WUR_AE_FIRST_TS, + 0, + Opcode_wur_ae_first_ts_encode_fns, 0, 0 }, + { "rur.ae_nextoffset", ICLASS_RUR_AE_NEXTOFFSET, + 0, + Opcode_rur_ae_nextoffset_encode_fns, 0, 0 }, + { "wur.ae_nextoffset", ICLASS_WUR_AE_NEXTOFFSET, + 0, + Opcode_wur_ae_nextoffset_encode_fns, 0, 0 }, + { "rur.ae_searchdone", ICLASS_RUR_AE_SEARCHDONE, + 0, + Opcode_rur_ae_searchdone_encode_fns, 0, 0 }, + { "wur.ae_searchdone", ICLASS_WUR_AE_SEARCHDONE, + 0, + Opcode_wur_ae_searchdone_encode_fns, 0, 0 }, + { "rur.ae_cwrap", ICLASS_RUR_AE_CWRAP, + 0, + Opcode_rur_ae_cwrap_encode_fns, 0, 0 }, + { "wur.ae_cwrap", ICLASS_WUR_AE_CWRAP, + 0, + Opcode_wur_ae_cwrap_encode_fns, 0, 0 }, + { "ae_l8x4f.i", ICLASS_AE_L8X4F_I, + 0, + Opcode_ae_l8x4f_i_encode_fns, 1, Opcode_ae_l8x4f_i_funcUnit_uses }, + { "ae_l8x4f.ip", ICLASS_AE_L8X4F_IP, + 0, + Opcode_ae_l8x4f_ip_encode_fns, 1, Opcode_ae_l8x4f_ip_funcUnit_uses }, + { "ae_l8x4f.x", ICLASS_AE_L8X4F_X, + 0, + Opcode_ae_l8x4f_x_encode_fns, 1, Opcode_ae_l8x4f_x_funcUnit_uses }, + { "ae_l8x4f.xp", ICLASS_AE_L8X4F_XP, + 0, + Opcode_ae_l8x4f_xp_encode_fns, 1, Opcode_ae_l8x4f_xp_funcUnit_uses }, + { "ae_l8x4s.i", ICLASS_AE_L8X4S_I, + 0, + Opcode_ae_l8x4s_i_encode_fns, 1, Opcode_ae_l8x4s_i_funcUnit_uses }, + { "ae_l8x4s.ip", ICLASS_AE_L8X4S_IP, + 0, + Opcode_ae_l8x4s_ip_encode_fns, 1, Opcode_ae_l8x4s_ip_funcUnit_uses }, + { "ae_l8x4s.x", ICLASS_AE_L8X4S_X, + 0, + Opcode_ae_l8x4s_x_encode_fns, 1, Opcode_ae_l8x4s_x_funcUnit_uses }, + { "ae_l8x4s.xp", ICLASS_AE_L8X4S_XP, + 0, + Opcode_ae_l8x4s_xp_encode_fns, 1, Opcode_ae_l8x4s_xp_funcUnit_uses }, + { "ae_l8x4u.i", ICLASS_AE_L8X4U_I, + 0, + Opcode_ae_l8x4u_i_encode_fns, 1, Opcode_ae_l8x4u_i_funcUnit_uses }, + { "ae_l8x4u.ip", ICLASS_AE_L8X4U_IP, + 0, + Opcode_ae_l8x4u_ip_encode_fns, 1, Opcode_ae_l8x4u_ip_funcUnit_uses }, + { "ae_l8x4u.x", ICLASS_AE_L8X4U_X, + 0, + Opcode_ae_l8x4u_x_encode_fns, 1, Opcode_ae_l8x4u_x_funcUnit_uses }, + { "ae_l8x4u.xp", ICLASS_AE_L8X4U_XP, + 0, + Opcode_ae_l8x4u_xp_encode_fns, 1, Opcode_ae_l8x4u_xp_funcUnit_uses }, + { "ae_l16m.xc", ICLASS_AE_L16M_XC, + 0, + Opcode_ae_l16m_xc_encode_fns, 1, Opcode_ae_l16m_xc_funcUnit_uses }, + { "ae_l16m.xc1", ICLASS_AE_L16M_XC1, + 0, + Opcode_ae_l16m_xc1_encode_fns, 1, Opcode_ae_l16m_xc1_funcUnit_uses }, + { "ae_l16m.i", ICLASS_AE_L16M_I, + 0, + Opcode_ae_l16m_i_encode_fns, 1, Opcode_ae_l16m_i_funcUnit_uses }, + { "ae_l16m.iu", ICLASS_AE_L16M_IU, + 0, + Opcode_ae_l16m_iu_encode_fns, 1, Opcode_ae_l16m_iu_funcUnit_uses }, + { "ae_l16m.x", ICLASS_AE_L16M_X, + 0, + Opcode_ae_l16m_x_encode_fns, 1, Opcode_ae_l16m_x_funcUnit_uses }, + { "ae_l16m.xu", ICLASS_AE_L16M_XU, + 0, + Opcode_ae_l16m_xu_encode_fns, 1, Opcode_ae_l16m_xu_funcUnit_uses }, + { "ae_l16.xc", ICLASS_AE_L16_XC, + 0, + Opcode_ae_l16_xc_encode_fns, 1, Opcode_ae_l16_xc_funcUnit_uses }, + { "ae_l16.xc1", ICLASS_AE_L16_XC1, + 0, + Opcode_ae_l16_xc1_encode_fns, 1, Opcode_ae_l16_xc1_funcUnit_uses }, + { "ae_l16.i", ICLASS_AE_L16_I, + 0, + Opcode_ae_l16_i_encode_fns, 1, Opcode_ae_l16_i_funcUnit_uses }, + { "ae_l16.ip", ICLASS_AE_L16_IP, + 0, + Opcode_ae_l16_ip_encode_fns, 1, Opcode_ae_l16_ip_funcUnit_uses }, + { "ae_l16.x", ICLASS_AE_L16_X, + 0, + Opcode_ae_l16_x_encode_fns, 1, Opcode_ae_l16_x_funcUnit_uses }, + { "ae_l16.xp", ICLASS_AE_L16_XP, + 0, + Opcode_ae_l16_xp_encode_fns, 1, Opcode_ae_l16_xp_funcUnit_uses }, + { "ae_l8.xc", ICLASS_AE_L8_XC, + 0, + Opcode_ae_l8_xc_encode_fns, 1, Opcode_ae_l8_xc_funcUnit_uses }, + { "ae_l8.xc1", ICLASS_AE_L8_XC1, + 0, + Opcode_ae_l8_xc1_encode_fns, 1, Opcode_ae_l8_xc1_funcUnit_uses }, + { "ae_l8.i", ICLASS_AE_L8_I, + 0, + Opcode_ae_l8_i_encode_fns, 1, Opcode_ae_l8_i_funcUnit_uses }, + { "ae_l8.ip", ICLASS_AE_L8_IP, + 0, + Opcode_ae_l8_ip_encode_fns, 1, Opcode_ae_l8_ip_funcUnit_uses }, + { "ae_l8.x", ICLASS_AE_L8_X, + 0, + Opcode_ae_l8_x_encode_fns, 1, Opcode_ae_l8_x_funcUnit_uses }, + { "ae_l8.xp", ICLASS_AE_L8_XP, + 0, + Opcode_ae_l8_xp_encode_fns, 1, Opcode_ae_l8_xp_funcUnit_uses }, + { "ae_l32f24.xc", ICLASS_AE_L32F24_XC, + 0, + Opcode_ae_l32f24_xc_encode_fns, 1, Opcode_ae_l32f24_xc_funcUnit_uses }, + { "ae_l32f24.xc1", ICLASS_AE_L32F24_XC1, + 0, + Opcode_ae_l32f24_xc1_encode_fns, 1, Opcode_ae_l32f24_xc1_funcUnit_uses }, + { "ae_l32f24.i", ICLASS_AE_L32F24_I, + 0, + Opcode_ae_l32f24_i_encode_fns, 1, Opcode_ae_l32f24_i_funcUnit_uses }, + { "ae_l32f24.ip", ICLASS_AE_L32F24_IP, + 0, + Opcode_ae_l32f24_ip_encode_fns, 1, Opcode_ae_l32f24_ip_funcUnit_uses }, + { "ae_l32f24.x", ICLASS_AE_L32F24_X, + 0, + Opcode_ae_l32f24_x_encode_fns, 1, Opcode_ae_l32f24_x_funcUnit_uses }, + { "ae_l32f24.xp", ICLASS_AE_L32F24_XP, + 0, + Opcode_ae_l32f24_xp_encode_fns, 1, Opcode_ae_l32f24_xp_funcUnit_uses }, + { "ae_l32.xc", ICLASS_AE_L32_XC, + 0, + Opcode_ae_l32_xc_encode_fns, 1, Opcode_ae_l32_xc_funcUnit_uses }, + { "ae_l32.xc1", ICLASS_AE_L32_XC1, + 0, + Opcode_ae_l32_xc1_encode_fns, 1, Opcode_ae_l32_xc1_funcUnit_uses }, + { "ae_l32.i", ICLASS_AE_L32_I, + 0, + Opcode_ae_l32_i_encode_fns, 1, Opcode_ae_l32_i_funcUnit_uses }, + { "ae_l32.ip", ICLASS_AE_L32_IP, + 0, + Opcode_ae_l32_ip_encode_fns, 1, Opcode_ae_l32_ip_funcUnit_uses }, + { "ae_l32.x", ICLASS_AE_L32_X, + 0, + Opcode_ae_l32_x_encode_fns, 1, Opcode_ae_l32_x_funcUnit_uses }, + { "ae_l32.xp", ICLASS_AE_L32_XP, + 0, + Opcode_ae_l32_xp_encode_fns, 1, Opcode_ae_l32_xp_funcUnit_uses }, + { "ae_l32m.xc", ICLASS_AE_L32M_XC, + 0, + Opcode_ae_l32m_xc_encode_fns, 1, Opcode_ae_l32m_xc_funcUnit_uses }, + { "ae_l32m.i", ICLASS_AE_L32M_I, + 0, + Opcode_ae_l32m_i_encode_fns, 1, Opcode_ae_l32m_i_funcUnit_uses }, + { "ae_l32m.iu", ICLASS_AE_L32M_IU, + 0, + Opcode_ae_l32m_iu_encode_fns, 1, Opcode_ae_l32m_iu_funcUnit_uses }, + { "ae_l32m.x", ICLASS_AE_L32M_X, + 0, + Opcode_ae_l32m_x_encode_fns, 1, Opcode_ae_l32m_x_funcUnit_uses }, + { "ae_l32m.xu", ICLASS_AE_L32M_XU, + 0, + Opcode_ae_l32m_xu_encode_fns, 1, Opcode_ae_l32m_xu_funcUnit_uses }, + { "ae_l16x2m.xc", ICLASS_AE_L16X2M_XC, + 0, + Opcode_ae_l16x2m_xc_encode_fns, 1, Opcode_ae_l16x2m_xc_funcUnit_uses }, + { "ae_l16x2m.xc1", ICLASS_AE_L16X2M_XC1, + 0, + Opcode_ae_l16x2m_xc1_encode_fns, 1, Opcode_ae_l16x2m_xc1_funcUnit_uses }, + { "ae_l16x2m.i", ICLASS_AE_L16X2M_I, + 0, + Opcode_ae_l16x2m_i_encode_fns, 1, Opcode_ae_l16x2m_i_funcUnit_uses }, + { "ae_l16x2m.iu", ICLASS_AE_L16X2M_IU, + 0, + Opcode_ae_l16x2m_iu_encode_fns, 1, Opcode_ae_l16x2m_iu_funcUnit_uses }, + { "ae_l16x2m.x", ICLASS_AE_L16X2M_X, + 0, + Opcode_ae_l16x2m_x_encode_fns, 1, Opcode_ae_l16x2m_x_funcUnit_uses }, + { "ae_l16x2m.xu", ICLASS_AE_L16X2M_XU, + 0, + Opcode_ae_l16x2m_xu_encode_fns, 1, Opcode_ae_l16x2m_xu_funcUnit_uses }, + { "ae_l32x2f24.xc", ICLASS_AE_L32X2F24_XC, + 0, + Opcode_ae_l32x2f24_xc_encode_fns, 1, Opcode_ae_l32x2f24_xc_funcUnit_uses }, + { "ae_l32x2f24.xc1", ICLASS_AE_L32X2F24_XC1, + 0, + Opcode_ae_l32x2f24_xc1_encode_fns, 1, Opcode_ae_l32x2f24_xc1_funcUnit_uses }, + { "ae_l32x2f24.i", ICLASS_AE_L32X2F24_I, + 0, + Opcode_ae_l32x2f24_i_encode_fns, 1, Opcode_ae_l32x2f24_i_funcUnit_uses }, + { "ae_l32x2f24.ip", ICLASS_AE_L32X2F24_IP, + 0, + Opcode_ae_l32x2f24_ip_encode_fns, 1, Opcode_ae_l32x2f24_ip_funcUnit_uses }, + { "ae_l32x2f24.rip", ICLASS_AE_L32X2F24_RIP, + 0, + Opcode_ae_l32x2f24_rip_encode_fns, 1, Opcode_ae_l32x2f24_rip_funcUnit_uses }, + { "ae_l32x2f24.ri", ICLASS_AE_L32X2F24_RI, + 0, + Opcode_ae_l32x2f24_ri_encode_fns, 1, Opcode_ae_l32x2f24_ri_funcUnit_uses }, + { "ae_l32x2f24.ric", ICLASS_AE_L32X2F24_RIC, + 0, + Opcode_ae_l32x2f24_ric_encode_fns, 1, Opcode_ae_l32x2f24_ric_funcUnit_uses }, + { "ae_l32x2f24.ric1", ICLASS_AE_L32X2F24_RIC1, + 0, + Opcode_ae_l32x2f24_ric1_encode_fns, 1, Opcode_ae_l32x2f24_ric1_funcUnit_uses }, + { "ae_l32x2f24.x", ICLASS_AE_L32X2F24_X, + 0, + Opcode_ae_l32x2f24_x_encode_fns, 1, Opcode_ae_l32x2f24_x_funcUnit_uses }, + { "ae_l32x2f24.xp", ICLASS_AE_L32X2F24_XP, + 0, + Opcode_ae_l32x2f24_xp_encode_fns, 1, Opcode_ae_l32x2f24_xp_funcUnit_uses }, + { "ae_l32x2.xc", ICLASS_AE_L32X2_XC, + 0, + Opcode_ae_l32x2_xc_encode_fns, 1, Opcode_ae_l32x2_xc_funcUnit_uses }, + { "ae_l32x2.xc1", ICLASS_AE_L32X2_XC1, + 0, + Opcode_ae_l32x2_xc1_encode_fns, 1, Opcode_ae_l32x2_xc1_funcUnit_uses }, + { "ae_l32x2.i", ICLASS_AE_L32X2_I, + 0, + Opcode_ae_l32x2_i_encode_fns, 1, Opcode_ae_l32x2_i_funcUnit_uses }, + { "ae_l32x2.ip", ICLASS_AE_L32X2_IP, + 0, + Opcode_ae_l32x2_ip_encode_fns, 1, Opcode_ae_l32x2_ip_funcUnit_uses }, + { "ae_l32x2.ric", ICLASS_AE_L32X2_RIC, + 0, + Opcode_ae_l32x2_ric_encode_fns, 1, Opcode_ae_l32x2_ric_funcUnit_uses }, + { "ae_l32x2.ric1", ICLASS_AE_L32X2_RIC1, + 0, + Opcode_ae_l32x2_ric1_encode_fns, 1, Opcode_ae_l32x2_ric1_funcUnit_uses }, + { "ae_l32x2.x", ICLASS_AE_L32X2_X, + 0, + Opcode_ae_l32x2_x_encode_fns, 1, Opcode_ae_l32x2_x_funcUnit_uses }, + { "ae_l32x2.xp", ICLASS_AE_L32X2_XP, + 0, + Opcode_ae_l32x2_xp_encode_fns, 1, Opcode_ae_l32x2_xp_funcUnit_uses }, + { "ae_l16x4.xc", ICLASS_AE_L16X4_XC, + 0, + Opcode_ae_l16x4_xc_encode_fns, 1, Opcode_ae_l16x4_xc_funcUnit_uses }, + { "ae_l16x4.xc1", ICLASS_AE_L16X4_XC1, + 0, + Opcode_ae_l16x4_xc1_encode_fns, 1, Opcode_ae_l16x4_xc1_funcUnit_uses }, + { "ae_l16x4.i", ICLASS_AE_L16X4_I, + 0, + Opcode_ae_l16x4_i_encode_fns, 1, Opcode_ae_l16x4_i_funcUnit_uses }, + { "ae_l16x4.ip", ICLASS_AE_L16X4_IP, + 0, + Opcode_ae_l16x4_ip_encode_fns, 1, Opcode_ae_l16x4_ip_funcUnit_uses }, + { "ae_l16x4.x", ICLASS_AE_L16X4_X, + 0, + Opcode_ae_l16x4_x_encode_fns, 1, Opcode_ae_l16x4_x_funcUnit_uses }, + { "ae_l16x4.xp", ICLASS_AE_L16X4_XP, + 0, + Opcode_ae_l16x4_xp_encode_fns, 1, Opcode_ae_l16x4_xp_funcUnit_uses }, + { "ae_l8x8.xc", ICLASS_AE_L8X8_XC, + 0, + Opcode_ae_l8x8_xc_encode_fns, 1, Opcode_ae_l8x8_xc_funcUnit_uses }, + { "ae_l8x8.xc1", ICLASS_AE_L8X8_XC1, + 0, + Opcode_ae_l8x8_xc1_encode_fns, 1, Opcode_ae_l8x8_xc1_funcUnit_uses }, + { "ae_l8x8.i", ICLASS_AE_L8X8_I, + 0, + Opcode_ae_l8x8_i_encode_fns, 1, Opcode_ae_l8x8_i_funcUnit_uses }, + { "ae_l8x8.ip", ICLASS_AE_L8X8_IP, + 0, + Opcode_ae_l8x8_ip_encode_fns, 1, Opcode_ae_l8x8_ip_funcUnit_uses }, + { "ae_l8x8.x", ICLASS_AE_L8X8_X, + 0, + Opcode_ae_l8x8_x_encode_fns, 1, Opcode_ae_l8x8_x_funcUnit_uses }, + { "ae_l8x8.xp", ICLASS_AE_L8X8_XP, + 0, + Opcode_ae_l8x8_xp_encode_fns, 1, Opcode_ae_l8x8_xp_funcUnit_uses }, + { "ae_l64.xc", ICLASS_AE_L64_XC, + 0, + Opcode_ae_l64_xc_encode_fns, 1, Opcode_ae_l64_xc_funcUnit_uses }, + { "ae_l64.xc1", ICLASS_AE_L64_XC1, + 0, + Opcode_ae_l64_xc1_encode_fns, 1, Opcode_ae_l64_xc1_funcUnit_uses }, + { "ae_l64.i", ICLASS_AE_L64_I, + 0, + Opcode_ae_l64_i_encode_fns, 1, Opcode_ae_l64_i_funcUnit_uses }, + { "ae_l64.ip", ICLASS_AE_L64_IP, + 0, + Opcode_ae_l64_ip_encode_fns, 1, Opcode_ae_l64_ip_funcUnit_uses }, + { "ae_l64.x", ICLASS_AE_L64_X, + 0, + Opcode_ae_l64_x_encode_fns, 1, Opcode_ae_l64_x_funcUnit_uses }, + { "ae_l64.xp", ICLASS_AE_L64_XP, + 0, + Opcode_ae_l64_xp_encode_fns, 1, Opcode_ae_l64_xp_funcUnit_uses }, + { "ae_s16x2m.xc", ICLASS_AE_S16X2M_XC, + 0, + Opcode_ae_s16x2m_xc_encode_fns, 1, Opcode_ae_s16x2m_xc_funcUnit_uses }, + { "ae_s16x2m.xc1", ICLASS_AE_S16X2M_XC1, + 0, + Opcode_ae_s16x2m_xc1_encode_fns, 1, Opcode_ae_s16x2m_xc1_funcUnit_uses }, + { "ae_s16x2m.i", ICLASS_AE_S16X2M_I, + 0, + Opcode_ae_s16x2m_i_encode_fns, 1, Opcode_ae_s16x2m_i_funcUnit_uses }, + { "ae_s16x2m.iu", ICLASS_AE_S16X2M_IU, + 0, + Opcode_ae_s16x2m_iu_encode_fns, 1, Opcode_ae_s16x2m_iu_funcUnit_uses }, + { "ae_s16x2m.x", ICLASS_AE_S16X2M_X, + 0, + Opcode_ae_s16x2m_x_encode_fns, 1, Opcode_ae_s16x2m_x_funcUnit_uses }, + { "ae_s16x2m.xu", ICLASS_AE_S16X2M_XU, + 0, + Opcode_ae_s16x2m_xu_encode_fns, 1, Opcode_ae_s16x2m_xu_funcUnit_uses }, + { "ae_s32x2f24.xc", ICLASS_AE_S32X2F24_XC, + 0, + Opcode_ae_s32x2f24_xc_encode_fns, 1, Opcode_ae_s32x2f24_xc_funcUnit_uses }, + { "ae_s32x2f24.xc1", ICLASS_AE_S32X2F24_XC1, + 0, + Opcode_ae_s32x2f24_xc1_encode_fns, 1, Opcode_ae_s32x2f24_xc1_funcUnit_uses }, + { "ae_s32x2f24.i", ICLASS_AE_S32X2F24_I, + 0, + Opcode_ae_s32x2f24_i_encode_fns, 1, Opcode_ae_s32x2f24_i_funcUnit_uses }, + { "ae_s32x2f24.ip", ICLASS_AE_S32X2F24_IP, + 0, + Opcode_ae_s32x2f24_ip_encode_fns, 1, Opcode_ae_s32x2f24_ip_funcUnit_uses }, + { "ae_s32x2f24.rip", ICLASS_AE_S32X2F24_RIP, + 0, + Opcode_ae_s32x2f24_rip_encode_fns, 1, Opcode_ae_s32x2f24_rip_funcUnit_uses }, + { "ae_s32x2f24.ric", ICLASS_AE_S32X2F24_RIC, + 0, + Opcode_ae_s32x2f24_ric_encode_fns, 1, Opcode_ae_s32x2f24_ric_funcUnit_uses }, + { "ae_s32x2f24.ric1", ICLASS_AE_S32X2F24_RIC1, + 0, + Opcode_ae_s32x2f24_ric1_encode_fns, 1, Opcode_ae_s32x2f24_ric1_funcUnit_uses }, + { "ae_s32x2f24.x", ICLASS_AE_S32X2F24_X, + 0, + Opcode_ae_s32x2f24_x_encode_fns, 1, Opcode_ae_s32x2f24_x_funcUnit_uses }, + { "ae_s32x2f24.xp", ICLASS_AE_S32X2F24_XP, + 0, + Opcode_ae_s32x2f24_xp_encode_fns, 1, Opcode_ae_s32x2f24_xp_funcUnit_uses }, + { "ae_s32x2.xc", ICLASS_AE_S32X2_XC, + 0, + Opcode_ae_s32x2_xc_encode_fns, 1, Opcode_ae_s32x2_xc_funcUnit_uses }, + { "ae_s32x2.xc1", ICLASS_AE_S32X2_XC1, + 0, + Opcode_ae_s32x2_xc1_encode_fns, 1, Opcode_ae_s32x2_xc1_funcUnit_uses }, + { "ae_s32x2.i", ICLASS_AE_S32X2_I, + 0, + Opcode_ae_s32x2_i_encode_fns, 1, Opcode_ae_s32x2_i_funcUnit_uses }, + { "ae_s32x2.ip", ICLASS_AE_S32X2_IP, + 0, + Opcode_ae_s32x2_ip_encode_fns, 1, Opcode_ae_s32x2_ip_funcUnit_uses }, + { "ae_s32x2.ric", ICLASS_AE_S32X2_RIC, + 0, + Opcode_ae_s32x2_ric_encode_fns, 1, Opcode_ae_s32x2_ric_funcUnit_uses }, + { "ae_s32x2.ric1", ICLASS_AE_S32X2_RIC1, + 0, + Opcode_ae_s32x2_ric1_encode_fns, 1, Opcode_ae_s32x2_ric1_funcUnit_uses }, + { "ae_s32x2.x", ICLASS_AE_S32X2_X, + 0, + Opcode_ae_s32x2_x_encode_fns, 1, Opcode_ae_s32x2_x_funcUnit_uses }, + { "ae_s32x2.xp", ICLASS_AE_S32X2_XP, + 0, + Opcode_ae_s32x2_xp_encode_fns, 1, Opcode_ae_s32x2_xp_funcUnit_uses }, + { "ae_s32x2rng.i", ICLASS_AE_S32X2RNG_I, + 0, + Opcode_ae_s32x2rng_i_encode_fns, 1, Opcode_ae_s32x2rng_i_funcUnit_uses }, + { "ae_s32x2rng.ip", ICLASS_AE_S32X2RNG_IP, + 0, + Opcode_ae_s32x2rng_ip_encode_fns, 1, Opcode_ae_s32x2rng_ip_funcUnit_uses }, + { "ae_s32x2rng.x", ICLASS_AE_S32X2RNG_X, + 0, + Opcode_ae_s32x2rng_x_encode_fns, 1, Opcode_ae_s32x2rng_x_funcUnit_uses }, + { "ae_s32x2rng.xp", ICLASS_AE_S32X2RNG_XP, + 0, + Opcode_ae_s32x2rng_xp_encode_fns, 1, Opcode_ae_s32x2rng_xp_funcUnit_uses }, + { "ae_s16x4.xc", ICLASS_AE_S16X4_XC, + 0, + Opcode_ae_s16x4_xc_encode_fns, 1, Opcode_ae_s16x4_xc_funcUnit_uses }, + { "ae_s16x4.xc1", ICLASS_AE_S16X4_XC1, + 0, + Opcode_ae_s16x4_xc1_encode_fns, 1, Opcode_ae_s16x4_xc1_funcUnit_uses }, + { "ae_s16x4.i", ICLASS_AE_S16X4_I, + 0, + Opcode_ae_s16x4_i_encode_fns, 1, Opcode_ae_s16x4_i_funcUnit_uses }, + { "ae_s16x4.ip", ICLASS_AE_S16X4_IP, + 0, + Opcode_ae_s16x4_ip_encode_fns, 1, Opcode_ae_s16x4_ip_funcUnit_uses }, + { "ae_s16x4.x", ICLASS_AE_S16X4_X, + 0, + Opcode_ae_s16x4_x_encode_fns, 1, Opcode_ae_s16x4_x_funcUnit_uses }, + { "ae_s16x4.xp", ICLASS_AE_S16X4_XP, + 0, + Opcode_ae_s16x4_xp_encode_fns, 1, Opcode_ae_s16x4_xp_funcUnit_uses }, + { "ae_s8x8.xc", ICLASS_AE_S8X8_XC, + 0, + Opcode_ae_s8x8_xc_encode_fns, 1, Opcode_ae_s8x8_xc_funcUnit_uses }, + { "ae_s8x8.xc1", ICLASS_AE_S8X8_XC1, + 0, + Opcode_ae_s8x8_xc1_encode_fns, 1, Opcode_ae_s8x8_xc1_funcUnit_uses }, + { "ae_s8x8.i", ICLASS_AE_S8X8_I, + 0, + Opcode_ae_s8x8_i_encode_fns, 1, Opcode_ae_s8x8_i_funcUnit_uses }, + { "ae_s8x8.ip", ICLASS_AE_S8X8_IP, + 0, + Opcode_ae_s8x8_ip_encode_fns, 1, Opcode_ae_s8x8_ip_funcUnit_uses }, + { "ae_s8x8.x", ICLASS_AE_S8X8_X, + 0, + Opcode_ae_s8x8_x_encode_fns, 1, Opcode_ae_s8x8_x_funcUnit_uses }, + { "ae_s8x8.xp", ICLASS_AE_S8X8_XP, + 0, + Opcode_ae_s8x8_xp_encode_fns, 1, Opcode_ae_s8x8_xp_funcUnit_uses }, + { "ae_s16m.l.xc", ICLASS_AE_S16M_L_XC, + 0, + Opcode_ae_s16m_l_xc_encode_fns, 1, Opcode_ae_s16m_l_xc_funcUnit_uses }, + { "ae_s16m.l.xc1", ICLASS_AE_S16M_L_XC1, + 0, + Opcode_ae_s16m_l_xc1_encode_fns, 1, Opcode_ae_s16m_l_xc1_funcUnit_uses }, + { "ae_s16m.l.i", ICLASS_AE_S16M_L_I, + 0, + Opcode_ae_s16m_l_i_encode_fns, 1, Opcode_ae_s16m_l_i_funcUnit_uses }, + { "ae_s16m.l.iu", ICLASS_AE_S16M_L_IU, + 0, + Opcode_ae_s16m_l_iu_encode_fns, 1, Opcode_ae_s16m_l_iu_funcUnit_uses }, + { "ae_s16m.l.x", ICLASS_AE_S16M_L_X, + 0, + Opcode_ae_s16m_l_x_encode_fns, 1, Opcode_ae_s16m_l_x_funcUnit_uses }, + { "ae_s16m.l.xu", ICLASS_AE_S16M_L_XU, + 0, + Opcode_ae_s16m_l_xu_encode_fns, 1, Opcode_ae_s16m_l_xu_funcUnit_uses }, + { "ae_s32f24.l.xc", ICLASS_AE_S32F24_L_XC, + 0, + Opcode_ae_s32f24_l_xc_encode_fns, 1, Opcode_ae_s32f24_l_xc_funcUnit_uses }, + { "ae_s32f24.l.xc1", ICLASS_AE_S32F24_L_XC1, + 0, + Opcode_ae_s32f24_l_xc1_encode_fns, 1, Opcode_ae_s32f24_l_xc1_funcUnit_uses }, + { "ae_s32f24.l.i", ICLASS_AE_S32F24_L_I, + 0, + Opcode_ae_s32f24_l_i_encode_fns, 1, Opcode_ae_s32f24_l_i_funcUnit_uses }, + { "ae_s32f24.l.ip", ICLASS_AE_S32F24_L_IP, + 0, + Opcode_ae_s32f24_l_ip_encode_fns, 1, Opcode_ae_s32f24_l_ip_funcUnit_uses }, + { "ae_s32f24.l.x", ICLASS_AE_S32F24_L_X, + 0, + Opcode_ae_s32f24_l_x_encode_fns, 1, Opcode_ae_s32f24_l_x_funcUnit_uses }, + { "ae_s32f24.l.xp", ICLASS_AE_S32F24_L_XP, + 0, + Opcode_ae_s32f24_l_xp_encode_fns, 1, Opcode_ae_s32f24_l_xp_funcUnit_uses }, + { "ae_s32.l.xc", ICLASS_AE_S32_L_XC, + 0, + Opcode_ae_s32_l_xc_encode_fns, 1, Opcode_ae_s32_l_xc_funcUnit_uses }, + { "ae_s32.l.xc1", ICLASS_AE_S32_L_XC1, + 0, + Opcode_ae_s32_l_xc1_encode_fns, 1, Opcode_ae_s32_l_xc1_funcUnit_uses }, + { "ae_s32.l.i", ICLASS_AE_S32_L_I, + 0, + Opcode_ae_s32_l_i_encode_fns, 1, Opcode_ae_s32_l_i_funcUnit_uses }, + { "ae_s32.l.ip", ICLASS_AE_S32_L_IP, + 0, + Opcode_ae_s32_l_ip_encode_fns, 1, Opcode_ae_s32_l_ip_funcUnit_uses }, + { "ae_s32.l.x", ICLASS_AE_S32_L_X, + 0, + Opcode_ae_s32_l_x_encode_fns, 1, Opcode_ae_s32_l_x_funcUnit_uses }, + { "ae_s32.l.xp", ICLASS_AE_S32_L_XP, + 0, + Opcode_ae_s32_l_xp_encode_fns, 1, Opcode_ae_s32_l_xp_funcUnit_uses }, + { "ae_s32.h.xc", ICLASS_AE_S32_H_XC, + 0, + Opcode_ae_s32_h_xc_encode_fns, 1, Opcode_ae_s32_h_xc_funcUnit_uses }, + { "ae_s32.h.xc1", ICLASS_AE_S32_H_XC1, + 0, + Opcode_ae_s32_h_xc1_encode_fns, 1, Opcode_ae_s32_h_xc1_funcUnit_uses }, + { "ae_s32.h.i", ICLASS_AE_S32_H_I, + 0, + Opcode_ae_s32_h_i_encode_fns, 1, Opcode_ae_s32_h_i_funcUnit_uses }, + { "ae_s32.h.ip", ICLASS_AE_S32_H_IP, + 0, + Opcode_ae_s32_h_ip_encode_fns, 1, Opcode_ae_s32_h_ip_funcUnit_uses }, + { "ae_s32.h.x", ICLASS_AE_S32_H_X, + 0, + Opcode_ae_s32_h_x_encode_fns, 1, Opcode_ae_s32_h_x_funcUnit_uses }, + { "ae_s32.h.xp", ICLASS_AE_S32_H_XP, + 0, + Opcode_ae_s32_h_xp_encode_fns, 1, Opcode_ae_s32_h_xp_funcUnit_uses }, + { "ae_s16.0.xc", ICLASS_AE_S16_0_XC, + 0, + Opcode_ae_s16_0_xc_encode_fns, 1, Opcode_ae_s16_0_xc_funcUnit_uses }, + { "ae_s16.0.xc1", ICLASS_AE_S16_0_XC1, + 0, + Opcode_ae_s16_0_xc1_encode_fns, 1, Opcode_ae_s16_0_xc1_funcUnit_uses }, + { "ae_s16.0.i", ICLASS_AE_S16_0_I, + 0, + Opcode_ae_s16_0_i_encode_fns, 1, Opcode_ae_s16_0_i_funcUnit_uses }, + { "ae_s16.0.ip", ICLASS_AE_S16_0_IP, + 0, + Opcode_ae_s16_0_ip_encode_fns, 1, Opcode_ae_s16_0_ip_funcUnit_uses }, + { "ae_s16.0.x", ICLASS_AE_S16_0_X, + 0, + Opcode_ae_s16_0_x_encode_fns, 1, Opcode_ae_s16_0_x_funcUnit_uses }, + { "ae_s16.0.xp", ICLASS_AE_S16_0_XP, + 0, + Opcode_ae_s16_0_xp_encode_fns, 1, Opcode_ae_s16_0_xp_funcUnit_uses }, + { "ae_s8.0.xc", ICLASS_AE_S8_0_XC, + 0, + Opcode_ae_s8_0_xc_encode_fns, 1, Opcode_ae_s8_0_xc_funcUnit_uses }, + { "ae_s8.0.xc1", ICLASS_AE_S8_0_XC1, + 0, + Opcode_ae_s8_0_xc1_encode_fns, 1, Opcode_ae_s8_0_xc1_funcUnit_uses }, + { "ae_s8.0.i", ICLASS_AE_S8_0_I, + 0, + Opcode_ae_s8_0_i_encode_fns, 1, Opcode_ae_s8_0_i_funcUnit_uses }, + { "ae_s8.0.ip", ICLASS_AE_S8_0_IP, + 0, + Opcode_ae_s8_0_ip_encode_fns, 1, Opcode_ae_s8_0_ip_funcUnit_uses }, + { "ae_s8.0.x", ICLASS_AE_S8_0_X, + 0, + Opcode_ae_s8_0_x_encode_fns, 1, Opcode_ae_s8_0_x_funcUnit_uses }, + { "ae_s8.0.xp", ICLASS_AE_S8_0_XP, + 0, + Opcode_ae_s8_0_xp_encode_fns, 1, Opcode_ae_s8_0_xp_funcUnit_uses }, + { "ae_s64.xc", ICLASS_AE_S64_XC, + 0, + Opcode_ae_s64_xc_encode_fns, 1, Opcode_ae_s64_xc_funcUnit_uses }, + { "ae_s64.xc1", ICLASS_AE_S64_XC1, + 0, + Opcode_ae_s64_xc1_encode_fns, 1, Opcode_ae_s64_xc1_funcUnit_uses }, + { "ae_s64.i", ICLASS_AE_S64_I, + 0, + Opcode_ae_s64_i_encode_fns, 1, Opcode_ae_s64_i_funcUnit_uses }, + { "ae_s64.ip", ICLASS_AE_S64_IP, + 0, + Opcode_ae_s64_ip_encode_fns, 1, Opcode_ae_s64_ip_funcUnit_uses }, + { "ae_s64.x", ICLASS_AE_S64_X, + 0, + Opcode_ae_s64_x_encode_fns, 1, Opcode_ae_s64_x_funcUnit_uses }, + { "ae_s64.xp", ICLASS_AE_S64_XP, + 0, + Opcode_ae_s64_xp_encode_fns, 1, Opcode_ae_s64_xp_funcUnit_uses }, + { "ae_s32m.xc", ICLASS_AE_S32M_XC, + 0, + Opcode_ae_s32m_xc_encode_fns, 1, Opcode_ae_s32m_xc_funcUnit_uses }, + { "ae_s32m.i", ICLASS_AE_S32M_I, + 0, + Opcode_ae_s32m_i_encode_fns, 1, Opcode_ae_s32m_i_funcUnit_uses }, + { "ae_s32m.iu", ICLASS_AE_S32M_IU, + 0, + Opcode_ae_s32m_iu_encode_fns, 1, Opcode_ae_s32m_iu_funcUnit_uses }, + { "ae_s32m.x", ICLASS_AE_S32M_X, + 0, + Opcode_ae_s32m_x_encode_fns, 1, Opcode_ae_s32m_x_funcUnit_uses }, + { "ae_s32m.xu", ICLASS_AE_S32M_XU, + 0, + Opcode_ae_s32m_xu_encode_fns, 1, Opcode_ae_s32m_xu_funcUnit_uses }, + { "ae_l32x2.xc2", ICLASS_AE_L32X2_XC2, + 0, + Opcode_ae_l32x2_xc2_encode_fns, 1, Opcode_ae_l32x2_xc2_funcUnit_uses }, + { "ae_l16x4.xc2", ICLASS_AE_L16X4_XC2, + 0, + Opcode_ae_l16x4_xc2_encode_fns, 1, Opcode_ae_l16x4_xc2_funcUnit_uses }, + { "ae_l8x8.xc2", ICLASS_AE_L8X8_XC2, + 0, + Opcode_ae_l8x8_xc2_encode_fns, 1, Opcode_ae_l8x8_xc2_funcUnit_uses }, + { "ae_l64.xc2", ICLASS_AE_L64_XC2, + 0, + Opcode_ae_l64_xc2_encode_fns, 1, Opcode_ae_l64_xc2_funcUnit_uses }, + { "ae_s32x2.xc2", ICLASS_AE_S32X2_XC2, + 0, + Opcode_ae_s32x2_xc2_encode_fns, 1, Opcode_ae_s32x2_xc2_funcUnit_uses }, + { "ae_s16x4.xc2", ICLASS_AE_S16X4_XC2, + 0, + Opcode_ae_s16x4_xc2_encode_fns, 1, Opcode_ae_s16x4_xc2_funcUnit_uses }, + { "ae_s8x8.xc2", ICLASS_AE_S8X8_XC2, + 0, + Opcode_ae_s8x8_xc2_encode_fns, 1, Opcode_ae_s8x8_xc2_funcUnit_uses }, + { "ae_s64.xc2", ICLASS_AE_S64_XC2, + 0, + Opcode_ae_s64_xc2_encode_fns, 1, Opcode_ae_s64_xc2_funcUnit_uses }, + { "ae_s16x4rng.i", ICLASS_AE_S16X4RNG_I, + 0, + Opcode_ae_s16x4rng_i_encode_fns, 1, Opcode_ae_s16x4rng_i_funcUnit_uses }, + { "ae_s16x4rng.ip", ICLASS_AE_S16X4RNG_IP, + 0, + Opcode_ae_s16x4rng_ip_encode_fns, 1, Opcode_ae_s16x4rng_ip_funcUnit_uses }, + { "ae_s16x4rng.x", ICLASS_AE_S16X4RNG_X, + 0, + Opcode_ae_s16x4rng_x_encode_fns, 1, Opcode_ae_s16x4rng_x_funcUnit_uses }, + { "ae_s16x4rng.xp", ICLASS_AE_S16X4RNG_XP, + 0, + Opcode_ae_s16x4rng_xp_encode_fns, 1, Opcode_ae_s16x4rng_xp_funcUnit_uses }, + { "ae_l32x2x2.xc", ICLASS_AE_L32X2X2_XC, + 0, + Opcode_ae_l32x2x2_xc_encode_fns, 1, Opcode_ae_l32x2x2_xc_funcUnit_uses }, + { "ae_l32x2x2.xc1", ICLASS_AE_L32X2X2_XC1, + 0, + Opcode_ae_l32x2x2_xc1_encode_fns, 1, Opcode_ae_l32x2x2_xc1_funcUnit_uses }, + { "ae_l32x2x2.i", ICLASS_AE_L32X2X2_I, + 0, + Opcode_ae_l32x2x2_i_encode_fns, 1, Opcode_ae_l32x2x2_i_funcUnit_uses }, + { "ae_l32x2x2.ip", ICLASS_AE_L32X2X2_IP, + 0, + Opcode_ae_l32x2x2_ip_encode_fns, 1, Opcode_ae_l32x2x2_ip_funcUnit_uses }, + { "ae_l32x2x2.x", ICLASS_AE_L32X2X2_X, + 0, + Opcode_ae_l32x2x2_x_encode_fns, 1, Opcode_ae_l32x2x2_x_funcUnit_uses }, + { "ae_l32x2x2.xp", ICLASS_AE_L32X2X2_XP, + 0, + Opcode_ae_l32x2x2_xp_encode_fns, 1, Opcode_ae_l32x2x2_xp_funcUnit_uses }, + { "ae_l16x4x2.xc", ICLASS_AE_L16X4X2_XC, + 0, + Opcode_ae_l16x4x2_xc_encode_fns, 1, Opcode_ae_l16x4x2_xc_funcUnit_uses }, + { "ae_l16x4x2.xc1", ICLASS_AE_L16X4X2_XC1, + 0, + Opcode_ae_l16x4x2_xc1_encode_fns, 1, Opcode_ae_l16x4x2_xc1_funcUnit_uses }, + { "ae_l16x4x2.i", ICLASS_AE_L16X4X2_I, + 0, + Opcode_ae_l16x4x2_i_encode_fns, 1, Opcode_ae_l16x4x2_i_funcUnit_uses }, + { "ae_l16x4x2.ip", ICLASS_AE_L16X4X2_IP, + 0, + Opcode_ae_l16x4x2_ip_encode_fns, 1, Opcode_ae_l16x4x2_ip_funcUnit_uses }, + { "ae_l16x4x2.x", ICLASS_AE_L16X4X2_X, + 0, + Opcode_ae_l16x4x2_x_encode_fns, 1, Opcode_ae_l16x4x2_x_funcUnit_uses }, + { "ae_l16x4x2.xp", ICLASS_AE_L16X4X2_XP, + 0, + Opcode_ae_l16x4x2_xp_encode_fns, 1, Opcode_ae_l16x4x2_xp_funcUnit_uses }, + { "ae_l8x8x2.xc", ICLASS_AE_L8X8X2_XC, + 0, + Opcode_ae_l8x8x2_xc_encode_fns, 1, Opcode_ae_l8x8x2_xc_funcUnit_uses }, + { "ae_l8x8x2.xc1", ICLASS_AE_L8X8X2_XC1, + 0, + Opcode_ae_l8x8x2_xc1_encode_fns, 1, Opcode_ae_l8x8x2_xc1_funcUnit_uses }, + { "ae_l8x8x2.i", ICLASS_AE_L8X8X2_I, + 0, + Opcode_ae_l8x8x2_i_encode_fns, 1, Opcode_ae_l8x8x2_i_funcUnit_uses }, + { "ae_l8x8x2.ip", ICLASS_AE_L8X8X2_IP, + 0, + Opcode_ae_l8x8x2_ip_encode_fns, 1, Opcode_ae_l8x8x2_ip_funcUnit_uses }, + { "ae_l8x8x2.x", ICLASS_AE_L8X8X2_X, + 0, + Opcode_ae_l8x8x2_x_encode_fns, 1, Opcode_ae_l8x8x2_x_funcUnit_uses }, + { "ae_l8x8x2.xp", ICLASS_AE_L8X8X2_XP, + 0, + Opcode_ae_l8x8x2_xp_encode_fns, 1, Opcode_ae_l8x8x2_xp_funcUnit_uses }, + { "ae_l64x2.xc", ICLASS_AE_L64X2_XC, + 0, + Opcode_ae_l64x2_xc_encode_fns, 1, Opcode_ae_l64x2_xc_funcUnit_uses }, + { "ae_l64x2.xc1", ICLASS_AE_L64X2_XC1, + 0, + Opcode_ae_l64x2_xc1_encode_fns, 1, Opcode_ae_l64x2_xc1_funcUnit_uses }, + { "ae_l64x2.i", ICLASS_AE_L64X2_I, + 0, + Opcode_ae_l64x2_i_encode_fns, 1, Opcode_ae_l64x2_i_funcUnit_uses }, + { "ae_l64x2.ip", ICLASS_AE_L64X2_IP, + 0, + Opcode_ae_l64x2_ip_encode_fns, 1, Opcode_ae_l64x2_ip_funcUnit_uses }, + { "ae_l64x2.x", ICLASS_AE_L64X2_X, + 0, + Opcode_ae_l64x2_x_encode_fns, 1, Opcode_ae_l64x2_x_funcUnit_uses }, + { "ae_l64x2.xp", ICLASS_AE_L64X2_XP, + 0, + Opcode_ae_l64x2_xp_encode_fns, 1, Opcode_ae_l64x2_xp_funcUnit_uses }, + { "ae_s32x2x2.xc", ICLASS_AE_S32X2X2_XC, + 0, + Opcode_ae_s32x2x2_xc_encode_fns, 1, Opcode_ae_s32x2x2_xc_funcUnit_uses }, + { "ae_s32x2x2.xc1", ICLASS_AE_S32X2X2_XC1, + 0, + Opcode_ae_s32x2x2_xc1_encode_fns, 1, Opcode_ae_s32x2x2_xc1_funcUnit_uses }, + { "ae_s32x2x2.i", ICLASS_AE_S32X2X2_I, + 0, + Opcode_ae_s32x2x2_i_encode_fns, 1, Opcode_ae_s32x2x2_i_funcUnit_uses }, + { "ae_s32x2x2.ip", ICLASS_AE_S32X2X2_IP, + 0, + Opcode_ae_s32x2x2_ip_encode_fns, 1, Opcode_ae_s32x2x2_ip_funcUnit_uses }, + { "ae_s32x2x2.x", ICLASS_AE_S32X2X2_X, + 0, + Opcode_ae_s32x2x2_x_encode_fns, 1, Opcode_ae_s32x2x2_x_funcUnit_uses }, + { "ae_s32x2x2.xp", ICLASS_AE_S32X2X2_XP, + 0, + Opcode_ae_s32x2x2_xp_encode_fns, 1, Opcode_ae_s32x2x2_xp_funcUnit_uses }, + { "ae_s32x2x2rng.i", ICLASS_AE_S32X2X2RNG_I, + 0, + Opcode_ae_s32x2x2rng_i_encode_fns, 1, Opcode_ae_s32x2x2rng_i_funcUnit_uses }, + { "ae_s32x2x2rng.ip", ICLASS_AE_S32X2X2RNG_IP, + 0, + Opcode_ae_s32x2x2rng_ip_encode_fns, 1, Opcode_ae_s32x2x2rng_ip_funcUnit_uses }, + { "ae_s32x2x2rng.x", ICLASS_AE_S32X2X2RNG_X, + 0, + Opcode_ae_s32x2x2rng_x_encode_fns, 1, Opcode_ae_s32x2x2rng_x_funcUnit_uses }, + { "ae_s32x2x2rng.xp", ICLASS_AE_S32X2X2RNG_XP, + 0, + Opcode_ae_s32x2x2rng_xp_encode_fns, 1, Opcode_ae_s32x2x2rng_xp_funcUnit_uses }, + { "ae_s16x4x2.xc", ICLASS_AE_S16X4X2_XC, + 0, + Opcode_ae_s16x4x2_xc_encode_fns, 1, Opcode_ae_s16x4x2_xc_funcUnit_uses }, + { "ae_s16x4x2.xc1", ICLASS_AE_S16X4X2_XC1, + 0, + Opcode_ae_s16x4x2_xc1_encode_fns, 1, Opcode_ae_s16x4x2_xc1_funcUnit_uses }, + { "ae_s16x4x2.i", ICLASS_AE_S16X4X2_I, + 0, + Opcode_ae_s16x4x2_i_encode_fns, 1, Opcode_ae_s16x4x2_i_funcUnit_uses }, + { "ae_s16x4x2.ip", ICLASS_AE_S16X4X2_IP, + 0, + Opcode_ae_s16x4x2_ip_encode_fns, 1, Opcode_ae_s16x4x2_ip_funcUnit_uses }, + { "ae_s16x4x2.x", ICLASS_AE_S16X4X2_X, + 0, + Opcode_ae_s16x4x2_x_encode_fns, 1, Opcode_ae_s16x4x2_x_funcUnit_uses }, + { "ae_s16x4x2.xp", ICLASS_AE_S16X4X2_XP, + 0, + Opcode_ae_s16x4x2_xp_encode_fns, 1, Opcode_ae_s16x4x2_xp_funcUnit_uses }, + { "ae_s8x8x2.xc", ICLASS_AE_S8X8X2_XC, + 0, + Opcode_ae_s8x8x2_xc_encode_fns, 1, Opcode_ae_s8x8x2_xc_funcUnit_uses }, + { "ae_s8x8x2.xc1", ICLASS_AE_S8X8X2_XC1, + 0, + Opcode_ae_s8x8x2_xc1_encode_fns, 1, Opcode_ae_s8x8x2_xc1_funcUnit_uses }, + { "ae_s8x8x2.i", ICLASS_AE_S8X8X2_I, + 0, + Opcode_ae_s8x8x2_i_encode_fns, 1, Opcode_ae_s8x8x2_i_funcUnit_uses }, + { "ae_s8x8x2.ip", ICLASS_AE_S8X8X2_IP, + 0, + Opcode_ae_s8x8x2_ip_encode_fns, 1, Opcode_ae_s8x8x2_ip_funcUnit_uses }, + { "ae_s8x8x2.x", ICLASS_AE_S8X8X2_X, + 0, + Opcode_ae_s8x8x2_x_encode_fns, 1, Opcode_ae_s8x8x2_x_funcUnit_uses }, + { "ae_s8x8x2.xp", ICLASS_AE_S8X8X2_XP, + 0, + Opcode_ae_s8x8x2_xp_encode_fns, 1, Opcode_ae_s8x8x2_xp_funcUnit_uses }, + { "ae_s64x2.xc", ICLASS_AE_S64X2_XC, + 0, + Opcode_ae_s64x2_xc_encode_fns, 1, Opcode_ae_s64x2_xc_funcUnit_uses }, + { "ae_s64x2.xc1", ICLASS_AE_S64X2_XC1, + 0, + Opcode_ae_s64x2_xc1_encode_fns, 1, Opcode_ae_s64x2_xc1_funcUnit_uses }, + { "ae_s64x2.i", ICLASS_AE_S64X2_I, + 0, + Opcode_ae_s64x2_i_encode_fns, 1, Opcode_ae_s64x2_i_funcUnit_uses }, + { "ae_s64x2.ip", ICLASS_AE_S64X2_IP, + 0, + Opcode_ae_s64x2_ip_encode_fns, 1, Opcode_ae_s64x2_ip_funcUnit_uses }, + { "ae_s64x2.x", ICLASS_AE_S64X2_X, + 0, + Opcode_ae_s64x2_x_encode_fns, 1, Opcode_ae_s64x2_x_funcUnit_uses }, + { "ae_s64x2.xp", ICLASS_AE_S64X2_XP, + 0, + Opcode_ae_s64x2_xp_encode_fns, 1, Opcode_ae_s64x2_xp_funcUnit_uses }, + { "ae_l32x2x2.xc2", ICLASS_AE_L32X2X2_XC2, + 0, + Opcode_ae_l32x2x2_xc2_encode_fns, 1, Opcode_ae_l32x2x2_xc2_funcUnit_uses }, + { "ae_l16x4x2.xc2", ICLASS_AE_L16X4X2_XC2, + 0, + Opcode_ae_l16x4x2_xc2_encode_fns, 1, Opcode_ae_l16x4x2_xc2_funcUnit_uses }, + { "ae_l8x8x2.xc2", ICLASS_AE_L8X8X2_XC2, + 0, + Opcode_ae_l8x8x2_xc2_encode_fns, 1, Opcode_ae_l8x8x2_xc2_funcUnit_uses }, + { "ae_l64x2.xc2", ICLASS_AE_L64X2_XC2, + 0, + Opcode_ae_l64x2_xc2_encode_fns, 1, Opcode_ae_l64x2_xc2_funcUnit_uses }, + { "ae_s32x2x2.xc2", ICLASS_AE_S32X2X2_XC2, + 0, + Opcode_ae_s32x2x2_xc2_encode_fns, 1, Opcode_ae_s32x2x2_xc2_funcUnit_uses }, + { "ae_s16x4x2.xc2", ICLASS_AE_S16X4X2_XC2, + 0, + Opcode_ae_s16x4x2_xc2_encode_fns, 1, Opcode_ae_s16x4x2_xc2_funcUnit_uses }, + { "ae_s8x8x2.xc2", ICLASS_AE_S8X8X2_XC2, + 0, + Opcode_ae_s8x8x2_xc2_encode_fns, 1, Opcode_ae_s8x8x2_xc2_funcUnit_uses }, + { "ae_s64x2.xc2", ICLASS_AE_S64X2_XC2, + 0, + Opcode_ae_s64x2_xc2_encode_fns, 1, Opcode_ae_s64x2_xc2_funcUnit_uses }, + { "ae_s16x4x2rng.i", ICLASS_AE_S16X4X2RNG_I, + 0, + Opcode_ae_s16x4x2rng_i_encode_fns, 1, Opcode_ae_s16x4x2rng_i_funcUnit_uses }, + { "ae_s16x4x2rng.ip", ICLASS_AE_S16X4X2RNG_IP, + 0, + Opcode_ae_s16x4x2rng_ip_encode_fns, 1, Opcode_ae_s16x4x2rng_ip_funcUnit_uses }, + { "ae_s16x4x2rng.x", ICLASS_AE_S16X4X2RNG_X, + 0, + Opcode_ae_s16x4x2rng_x_encode_fns, 1, Opcode_ae_s16x4x2rng_x_funcUnit_uses }, + { "ae_s16x4x2rng.xp", ICLASS_AE_S16X4X2RNG_XP, + 0, + Opcode_ae_s16x4x2rng_xp_encode_fns, 1, Opcode_ae_s16x4x2rng_xp_funcUnit_uses }, + { "ae_zalign64", ICLASS_AE_ZALIGN64, + 0, + Opcode_ae_zalign64_encode_fns, 0, 0 }, + { "ae_lalign64.i", ICLASS_AE_LALIGN64_I, + 0, + Opcode_ae_lalign64_i_encode_fns, 1, Opcode_ae_lalign64_i_funcUnit_uses }, + { "ae_salign64.i", ICLASS_AE_SALIGN64_I, + 0, + Opcode_ae_salign64_i_encode_fns, 1, Opcode_ae_salign64_i_funcUnit_uses }, + { "ae_movalign", ICLASS_AE_MOVALIGN, + 0, + Opcode_ae_movalign_encode_fns, 0, 0 }, + { "ae_la64.pp", ICLASS_AE_LA64_PP, + 0, + Opcode_ae_la64_pp_encode_fns, 1, Opcode_ae_la64_pp_funcUnit_uses }, + { "ae_la24pos.pc", ICLASS_AE_LA24POS_PC, + 0, + Opcode_ae_la24pos_pc_encode_fns, 1, Opcode_ae_la24pos_pc_funcUnit_uses }, + { "ae_la24neg.pc", ICLASS_AE_LA24NEG_PC, + 0, + Opcode_ae_la24neg_pc_encode_fns, 1, Opcode_ae_la24neg_pc_funcUnit_uses }, + { "ae_la24pos.pc1", ICLASS_AE_LA24POS_PC1, + 0, + Opcode_ae_la24pos_pc1_encode_fns, 1, Opcode_ae_la24pos_pc1_funcUnit_uses }, + { "ae_la24neg.pc1", ICLASS_AE_LA24NEG_PC1, + 0, + Opcode_ae_la24neg_pc1_encode_fns, 1, Opcode_ae_la24neg_pc1_funcUnit_uses }, + { "ae_la24x2pos.pc", ICLASS_AE_LA24X2POS_PC, + 0, + Opcode_ae_la24x2pos_pc_encode_fns, 1, Opcode_ae_la24x2pos_pc_funcUnit_uses }, + { "ae_la24x2neg.pc", ICLASS_AE_LA24X2NEG_PC, + 0, + Opcode_ae_la24x2neg_pc_encode_fns, 1, Opcode_ae_la24x2neg_pc_funcUnit_uses }, + { "ae_la24x2pos.pc1", ICLASS_AE_LA24X2POS_PC1, + 0, + Opcode_ae_la24x2pos_pc1_encode_fns, 1, Opcode_ae_la24x2pos_pc1_funcUnit_uses }, + { "ae_la24x2neg.pc1", ICLASS_AE_LA24X2NEG_PC1, + 0, + Opcode_ae_la24x2neg_pc1_encode_fns, 1, Opcode_ae_la24x2neg_pc1_funcUnit_uses }, + { "ae_la32x2pos.pc", ICLASS_AE_LA32X2POS_PC, + 0, + Opcode_ae_la32x2pos_pc_encode_fns, 1, Opcode_ae_la32x2pos_pc_funcUnit_uses }, + { "ae_la32x2neg.pc", ICLASS_AE_LA32X2NEG_PC, + 0, + Opcode_ae_la32x2neg_pc_encode_fns, 1, Opcode_ae_la32x2neg_pc_funcUnit_uses }, + { "ae_la32x2pos.pc1", ICLASS_AE_LA32X2POS_PC1, + 0, + Opcode_ae_la32x2pos_pc1_encode_fns, 1, Opcode_ae_la32x2pos_pc1_funcUnit_uses }, + { "ae_la32x2neg.pc1", ICLASS_AE_LA32X2NEG_PC1, + 0, + Opcode_ae_la32x2neg_pc1_encode_fns, 1, Opcode_ae_la32x2neg_pc1_funcUnit_uses }, + { "ae_la32x2pos.pc2", ICLASS_AE_LA32X2POS_PC2, + 0, + Opcode_ae_la32x2pos_pc2_encode_fns, 1, Opcode_ae_la32x2pos_pc2_funcUnit_uses }, + { "ae_la16x4pos.pc", ICLASS_AE_LA16X4POS_PC, + 0, + Opcode_ae_la16x4pos_pc_encode_fns, 1, Opcode_ae_la16x4pos_pc_funcUnit_uses }, + { "ae_la16x4neg.pc", ICLASS_AE_LA16X4NEG_PC, + 0, + Opcode_ae_la16x4neg_pc_encode_fns, 1, Opcode_ae_la16x4neg_pc_funcUnit_uses }, + { "ae_la16x4pos.pc1", ICLASS_AE_LA16X4POS_PC1, + 0, + Opcode_ae_la16x4pos_pc1_encode_fns, 1, Opcode_ae_la16x4pos_pc1_funcUnit_uses }, + { "ae_la16x4neg.pc1", ICLASS_AE_LA16X4NEG_PC1, + 0, + Opcode_ae_la16x4neg_pc1_encode_fns, 1, Opcode_ae_la16x4neg_pc1_funcUnit_uses }, + { "ae_la16x4pos.pc2", ICLASS_AE_LA16X4POS_PC2, + 0, + Opcode_ae_la16x4pos_pc2_encode_fns, 1, Opcode_ae_la16x4pos_pc2_funcUnit_uses }, + { "ae_la8x8pos.pc", ICLASS_AE_LA8X8POS_PC, + 0, + Opcode_ae_la8x8pos_pc_encode_fns, 1, Opcode_ae_la8x8pos_pc_funcUnit_uses }, + { "ae_la8x8neg.pc", ICLASS_AE_LA8X8NEG_PC, + 0, + Opcode_ae_la8x8neg_pc_encode_fns, 1, Opcode_ae_la8x8neg_pc_funcUnit_uses }, + { "ae_la8x8pos.pc1", ICLASS_AE_LA8X8POS_PC1, + 0, + Opcode_ae_la8x8pos_pc1_encode_fns, 1, Opcode_ae_la8x8pos_pc1_funcUnit_uses }, + { "ae_la8x8neg.pc1", ICLASS_AE_LA8X8NEG_PC1, + 0, + Opcode_ae_la8x8neg_pc1_encode_fns, 1, Opcode_ae_la8x8neg_pc1_funcUnit_uses }, + { "ae_la8x8pos.pc2", ICLASS_AE_LA8X8POS_PC2, + 0, + Opcode_ae_la8x8pos_pc2_encode_fns, 1, Opcode_ae_la8x8pos_pc2_funcUnit_uses }, + { "ae_la32x2x2pos.pc", ICLASS_AE_LA32X2X2POS_PC, + 0, + Opcode_ae_la32x2x2pos_pc_encode_fns, 1, Opcode_ae_la32x2x2pos_pc_funcUnit_uses }, + { "ae_la32x2x2pos.pc1", ICLASS_AE_LA32X2X2POS_PC1, + 0, + Opcode_ae_la32x2x2pos_pc1_encode_fns, 1, Opcode_ae_la32x2x2pos_pc1_funcUnit_uses }, + { "ae_la32x2x2pos.pc2", ICLASS_AE_LA32X2X2POS_PC2, + 0, + Opcode_ae_la32x2x2pos_pc2_encode_fns, 1, Opcode_ae_la32x2x2pos_pc2_funcUnit_uses }, + { "ae_la16x4x2pos.pc", ICLASS_AE_LA16X4X2POS_PC, + 0, + Opcode_ae_la16x4x2pos_pc_encode_fns, 1, Opcode_ae_la16x4x2pos_pc_funcUnit_uses }, + { "ae_la16x4x2pos.pc1", ICLASS_AE_LA16X4X2POS_PC1, + 0, + Opcode_ae_la16x4x2pos_pc1_encode_fns, 1, Opcode_ae_la16x4x2pos_pc1_funcUnit_uses }, + { "ae_la16x4x2pos.pc2", ICLASS_AE_LA16X4X2POS_PC2, + 0, + Opcode_ae_la16x4x2pos_pc2_encode_fns, 1, Opcode_ae_la16x4x2pos_pc2_funcUnit_uses }, + { "ae_la8x8x2pos.pc", ICLASS_AE_LA8X8X2POS_PC, + 0, + Opcode_ae_la8x8x2pos_pc_encode_fns, 1, Opcode_ae_la8x8x2pos_pc_funcUnit_uses }, + { "ae_la8x8x2pos.pc1", ICLASS_AE_LA8X8X2POS_PC1, + 0, + Opcode_ae_la8x8x2pos_pc1_encode_fns, 1, Opcode_ae_la8x8x2pos_pc1_funcUnit_uses }, + { "ae_la8x8x2pos.pc2", ICLASS_AE_LA8X8X2POS_PC2, + 0, + Opcode_ae_la8x8x2pos_pc2_encode_fns, 1, Opcode_ae_la8x8x2pos_pc2_funcUnit_uses }, + { "ae_sa64pos.fp", ICLASS_AE_SA64POS_FP, + 0, + Opcode_ae_sa64pos_fp_encode_fns, 1, Opcode_ae_sa64pos_fp_funcUnit_uses }, + { "ae_sa64neg.fp", ICLASS_AE_SA64NEG_FP, + 0, + Opcode_ae_sa64neg_fp_encode_fns, 1, Opcode_ae_sa64neg_fp_funcUnit_uses }, + { "ae_la32x2.ic", ICLASS_AE_LA32X2_IC, + 0, + Opcode_ae_la32x2_ic_encode_fns, 1, Opcode_ae_la32x2_ic_funcUnit_uses }, + { "ae_la32x2.ic1", ICLASS_AE_LA32X2_IC1, + 0, + Opcode_ae_la32x2_ic1_encode_fns, 1, Opcode_ae_la32x2_ic1_funcUnit_uses }, + { "ae_la32x2.ic2", ICLASS_AE_LA32X2_IC2, + 0, + Opcode_ae_la32x2_ic2_encode_fns, 1, Opcode_ae_la32x2_ic2_funcUnit_uses }, + { "ae_la32x2.ip", ICLASS_AE_LA32X2_IP, + 0, + Opcode_ae_la32x2_ip_encode_fns, 1, Opcode_ae_la32x2_ip_funcUnit_uses }, + { "ae_la32x2.rip", ICLASS_AE_LA32X2_RIP, + 0, + Opcode_ae_la32x2_rip_encode_fns, 1, Opcode_ae_la32x2_rip_funcUnit_uses }, + { "ae_la32x2.ric", ICLASS_AE_LA32X2_RIC, + 0, + Opcode_ae_la32x2_ric_encode_fns, 1, Opcode_ae_la32x2_ric_funcUnit_uses }, + { "ae_la32x2.ric1", ICLASS_AE_LA32X2_RIC1, + 0, + Opcode_ae_la32x2_ric1_encode_fns, 1, Opcode_ae_la32x2_ric1_funcUnit_uses }, + { "ae_la16x4.ic", ICLASS_AE_LA16X4_IC, + 0, + Opcode_ae_la16x4_ic_encode_fns, 1, Opcode_ae_la16x4_ic_funcUnit_uses }, + { "ae_la16x4.ic1", ICLASS_AE_LA16X4_IC1, + 0, + Opcode_ae_la16x4_ic1_encode_fns, 1, Opcode_ae_la16x4_ic1_funcUnit_uses }, + { "ae_la16x4.ic2", ICLASS_AE_LA16X4_IC2, + 0, + Opcode_ae_la16x4_ic2_encode_fns, 1, Opcode_ae_la16x4_ic2_funcUnit_uses }, + { "ae_la16x4.ip", ICLASS_AE_LA16X4_IP, + 0, + Opcode_ae_la16x4_ip_encode_fns, 1, Opcode_ae_la16x4_ip_funcUnit_uses }, + { "ae_la16x4.rip", ICLASS_AE_LA16X4_RIP, + 0, + Opcode_ae_la16x4_rip_encode_fns, 1, Opcode_ae_la16x4_rip_funcUnit_uses }, + { "ae_la16x4.ric", ICLASS_AE_LA16X4_RIC, + 0, + Opcode_ae_la16x4_ric_encode_fns, 1, Opcode_ae_la16x4_ric_funcUnit_uses }, + { "ae_la16x4.ric1", ICLASS_AE_LA16X4_RIC1, + 0, + Opcode_ae_la16x4_ric1_encode_fns, 1, Opcode_ae_la16x4_ric1_funcUnit_uses }, + { "ae_la8x8.ic", ICLASS_AE_LA8X8_IC, + 0, + Opcode_ae_la8x8_ic_encode_fns, 1, Opcode_ae_la8x8_ic_funcUnit_uses }, + { "ae_la8x8.ic1", ICLASS_AE_LA8X8_IC1, + 0, + Opcode_ae_la8x8_ic1_encode_fns, 1, Opcode_ae_la8x8_ic1_funcUnit_uses }, + { "ae_la8x8.ic2", ICLASS_AE_LA8X8_IC2, + 0, + Opcode_ae_la8x8_ic2_encode_fns, 1, Opcode_ae_la8x8_ic2_funcUnit_uses }, + { "ae_la8x8.ip", ICLASS_AE_LA8X8_IP, + 0, + Opcode_ae_la8x8_ip_encode_fns, 1, Opcode_ae_la8x8_ip_funcUnit_uses }, + { "ae_la8x8.rip", ICLASS_AE_LA8X8_RIP, + 0, + Opcode_ae_la8x8_rip_encode_fns, 1, Opcode_ae_la8x8_rip_funcUnit_uses }, + { "ae_la8x8.ric", ICLASS_AE_LA8X8_RIC, + 0, + Opcode_ae_la8x8_ric_encode_fns, 1, Opcode_ae_la8x8_ric_funcUnit_uses }, + { "ae_la8x8.ric1", ICLASS_AE_LA8X8_RIC1, + 0, + Opcode_ae_la8x8_ric1_encode_fns, 1, Opcode_ae_la8x8_ric1_funcUnit_uses }, + { "ae_la32x2f24.ic", ICLASS_AE_LA32X2F24_IC, + 0, + Opcode_ae_la32x2f24_ic_encode_fns, 1, Opcode_ae_la32x2f24_ic_funcUnit_uses }, + { "ae_la32x2f24.ic1", ICLASS_AE_LA32X2F24_IC1, + 0, + Opcode_ae_la32x2f24_ic1_encode_fns, 1, Opcode_ae_la32x2f24_ic1_funcUnit_uses }, + { "ae_la32x2f24.ip", ICLASS_AE_LA32X2F24_IP, + 0, + Opcode_ae_la32x2f24_ip_encode_fns, 1, Opcode_ae_la32x2f24_ip_funcUnit_uses }, + { "ae_la32x2f24.rip", ICLASS_AE_LA32X2F24_RIP, + 0, + Opcode_ae_la32x2f24_rip_encode_fns, 1, Opcode_ae_la32x2f24_rip_funcUnit_uses }, + { "ae_la32x2f24.ric", ICLASS_AE_LA32X2F24_RIC, + 0, + Opcode_ae_la32x2f24_ric_encode_fns, 1, Opcode_ae_la32x2f24_ric_funcUnit_uses }, + { "ae_la32x2f24.ric1", ICLASS_AE_LA32X2F24_RIC1, + 0, + Opcode_ae_la32x2f24_ric1_encode_fns, 1, Opcode_ae_la32x2f24_ric1_funcUnit_uses }, + { "ae_la24.ic", ICLASS_AE_LA24_IC, + 0, + Opcode_ae_la24_ic_encode_fns, 1, Opcode_ae_la24_ic_funcUnit_uses }, + { "ae_la24.ic1", ICLASS_AE_LA24_IC1, + 0, + Opcode_ae_la24_ic1_encode_fns, 1, Opcode_ae_la24_ic1_funcUnit_uses }, + { "ae_la24.ip", ICLASS_AE_LA24_IP, + 0, + Opcode_ae_la24_ip_encode_fns, 1, Opcode_ae_la24_ip_funcUnit_uses }, + { "ae_la24.rip", ICLASS_AE_LA24_RIP, + 0, + Opcode_ae_la24_rip_encode_fns, 1, Opcode_ae_la24_rip_funcUnit_uses }, + { "ae_la24.ric", ICLASS_AE_LA24_RIC, + 0, + Opcode_ae_la24_ric_encode_fns, 1, Opcode_ae_la24_ric_funcUnit_uses }, + { "ae_la24.ric1", ICLASS_AE_LA24_RIC1, + 0, + Opcode_ae_la24_ric1_encode_fns, 1, Opcode_ae_la24_ric1_funcUnit_uses }, + { "ae_la24x2.ic", ICLASS_AE_LA24X2_IC, + 0, + Opcode_ae_la24x2_ic_encode_fns, 1, Opcode_ae_la24x2_ic_funcUnit_uses }, + { "ae_la24x2.ic1", ICLASS_AE_LA24X2_IC1, + 0, + Opcode_ae_la24x2_ic1_encode_fns, 1, Opcode_ae_la24x2_ic1_funcUnit_uses }, + { "ae_la24x2.ip", ICLASS_AE_LA24X2_IP, + 0, + Opcode_ae_la24x2_ip_encode_fns, 1, Opcode_ae_la24x2_ip_funcUnit_uses }, + { "ae_la24x2.rip", ICLASS_AE_LA24X2_RIP, + 0, + Opcode_ae_la24x2_rip_encode_fns, 1, Opcode_ae_la24x2_rip_funcUnit_uses }, + { "ae_la24x2.ric", ICLASS_AE_LA24X2_RIC, + 0, + Opcode_ae_la24x2_ric_encode_fns, 1, Opcode_ae_la24x2_ric_funcUnit_uses }, + { "ae_la24x2.ric1", ICLASS_AE_LA24X2_RIC1, + 0, + Opcode_ae_la24x2_ric1_encode_fns, 1, Opcode_ae_la24x2_ric1_funcUnit_uses }, + { "ae_sa32x2.ic", ICLASS_AE_SA32X2_IC, + 0, + Opcode_ae_sa32x2_ic_encode_fns, 1, Opcode_ae_sa32x2_ic_funcUnit_uses }, + { "ae_sa32x2.ic1", ICLASS_AE_SA32X2_IC1, + 0, + Opcode_ae_sa32x2_ic1_encode_fns, 1, Opcode_ae_sa32x2_ic1_funcUnit_uses }, + { "ae_sa32x2.ic2", ICLASS_AE_SA32X2_IC2, + 0, + Opcode_ae_sa32x2_ic2_encode_fns, 1, Opcode_ae_sa32x2_ic2_funcUnit_uses }, + { "ae_sa32x2.ip", ICLASS_AE_SA32X2_IP, + 0, + Opcode_ae_sa32x2_ip_encode_fns, 1, Opcode_ae_sa32x2_ip_funcUnit_uses }, + { "ae_sa32x2.rip", ICLASS_AE_SA32X2_RIP, + 0, + Opcode_ae_sa32x2_rip_encode_fns, 1, Opcode_ae_sa32x2_rip_funcUnit_uses }, + { "ae_sa32x2.ric", ICLASS_AE_SA32X2_RIC, + 0, + Opcode_ae_sa32x2_ric_encode_fns, 1, Opcode_ae_sa32x2_ric_funcUnit_uses }, + { "ae_sa32x2.ric1", ICLASS_AE_SA32X2_RIC1, + 0, + Opcode_ae_sa32x2_ric1_encode_fns, 1, Opcode_ae_sa32x2_ric1_funcUnit_uses }, + { "ae_sa16x4.ic", ICLASS_AE_SA16X4_IC, + 0, + Opcode_ae_sa16x4_ic_encode_fns, 1, Opcode_ae_sa16x4_ic_funcUnit_uses }, + { "ae_sa16x4.ic1", ICLASS_AE_SA16X4_IC1, + 0, + Opcode_ae_sa16x4_ic1_encode_fns, 1, Opcode_ae_sa16x4_ic1_funcUnit_uses }, + { "ae_sa16x4.ic2", ICLASS_AE_SA16X4_IC2, + 0, + Opcode_ae_sa16x4_ic2_encode_fns, 1, Opcode_ae_sa16x4_ic2_funcUnit_uses }, + { "ae_sa16x4.ip", ICLASS_AE_SA16X4_IP, + 0, + Opcode_ae_sa16x4_ip_encode_fns, 1, Opcode_ae_sa16x4_ip_funcUnit_uses }, + { "ae_sa16x4.rip", ICLASS_AE_SA16X4_RIP, + 0, + Opcode_ae_sa16x4_rip_encode_fns, 1, Opcode_ae_sa16x4_rip_funcUnit_uses }, + { "ae_sa16x4.ric", ICLASS_AE_SA16X4_RIC, + 0, + Opcode_ae_sa16x4_ric_encode_fns, 1, Opcode_ae_sa16x4_ric_funcUnit_uses }, + { "ae_sa16x4.ric1", ICLASS_AE_SA16X4_RIC1, + 0, + Opcode_ae_sa16x4_ric1_encode_fns, 1, Opcode_ae_sa16x4_ric1_funcUnit_uses }, + { "ae_sa8x8.ic", ICLASS_AE_SA8X8_IC, + 0, + Opcode_ae_sa8x8_ic_encode_fns, 1, Opcode_ae_sa8x8_ic_funcUnit_uses }, + { "ae_sa8x8.ic1", ICLASS_AE_SA8X8_IC1, + 0, + Opcode_ae_sa8x8_ic1_encode_fns, 1, Opcode_ae_sa8x8_ic1_funcUnit_uses }, + { "ae_sa8x8.ic2", ICLASS_AE_SA8X8_IC2, + 0, + Opcode_ae_sa8x8_ic2_encode_fns, 1, Opcode_ae_sa8x8_ic2_funcUnit_uses }, + { "ae_sa8x8.ip", ICLASS_AE_SA8X8_IP, + 0, + Opcode_ae_sa8x8_ip_encode_fns, 1, Opcode_ae_sa8x8_ip_funcUnit_uses }, + { "ae_sa8x8.rip", ICLASS_AE_SA8X8_RIP, + 0, + Opcode_ae_sa8x8_rip_encode_fns, 1, Opcode_ae_sa8x8_rip_funcUnit_uses }, + { "ae_sa8x8.ric", ICLASS_AE_SA8X8_RIC, + 0, + Opcode_ae_sa8x8_ric_encode_fns, 1, Opcode_ae_sa8x8_ric_funcUnit_uses }, + { "ae_sa8x8.ric1", ICLASS_AE_SA8X8_RIC1, + 0, + Opcode_ae_sa8x8_ric1_encode_fns, 1, Opcode_ae_sa8x8_ric1_funcUnit_uses }, + { "ae_sa32x2f24.ic", ICLASS_AE_SA32X2F24_IC, + 0, + Opcode_ae_sa32x2f24_ic_encode_fns, 1, Opcode_ae_sa32x2f24_ic_funcUnit_uses }, + { "ae_sa32x2f24.ic1", ICLASS_AE_SA32X2F24_IC1, + 0, + Opcode_ae_sa32x2f24_ic1_encode_fns, 1, Opcode_ae_sa32x2f24_ic1_funcUnit_uses }, + { "ae_sa32x2f24.ip", ICLASS_AE_SA32X2F24_IP, + 0, + Opcode_ae_sa32x2f24_ip_encode_fns, 1, Opcode_ae_sa32x2f24_ip_funcUnit_uses }, + { "ae_sa32x2f24.rip", ICLASS_AE_SA32X2F24_RIP, + 0, + Opcode_ae_sa32x2f24_rip_encode_fns, 1, Opcode_ae_sa32x2f24_rip_funcUnit_uses }, + { "ae_sa32x2f24.ric", ICLASS_AE_SA32X2F24_RIC, + 0, + Opcode_ae_sa32x2f24_ric_encode_fns, 1, Opcode_ae_sa32x2f24_ric_funcUnit_uses }, + { "ae_sa32x2f24.ric1", ICLASS_AE_SA32X2F24_RIC1, + 0, + Opcode_ae_sa32x2f24_ric1_encode_fns, 1, Opcode_ae_sa32x2f24_ric1_funcUnit_uses }, + { "ae_sa24.l.ic", ICLASS_AE_SA24_L_IC, + 0, + Opcode_ae_sa24_l_ic_encode_fns, 1, Opcode_ae_sa24_l_ic_funcUnit_uses }, + { "ae_sa24.l.ic1", ICLASS_AE_SA24_L_IC1, + 0, + Opcode_ae_sa24_l_ic1_encode_fns, 1, Opcode_ae_sa24_l_ic1_funcUnit_uses }, + { "ae_sa24.l.ip", ICLASS_AE_SA24_L_IP, + 0, + Opcode_ae_sa24_l_ip_encode_fns, 1, Opcode_ae_sa24_l_ip_funcUnit_uses }, + { "ae_sa24.l.rip", ICLASS_AE_SA24_L_RIP, + 0, + Opcode_ae_sa24_l_rip_encode_fns, 1, Opcode_ae_sa24_l_rip_funcUnit_uses }, + { "ae_sa24.l.ric", ICLASS_AE_SA24_L_RIC, + 0, + Opcode_ae_sa24_l_ric_encode_fns, 1, Opcode_ae_sa24_l_ric_funcUnit_uses }, + { "ae_sa24.l.ric1", ICLASS_AE_SA24_L_RIC1, + 0, + Opcode_ae_sa24_l_ric1_encode_fns, 1, Opcode_ae_sa24_l_ric1_funcUnit_uses }, + { "ae_sa24x2.ic", ICLASS_AE_SA24X2_IC, + 0, + Opcode_ae_sa24x2_ic_encode_fns, 1, Opcode_ae_sa24x2_ic_funcUnit_uses }, + { "ae_sa24x2.ic1", ICLASS_AE_SA24X2_IC1, + 0, + Opcode_ae_sa24x2_ic1_encode_fns, 1, Opcode_ae_sa24x2_ic1_funcUnit_uses }, + { "ae_sa24x2.ip", ICLASS_AE_SA24X2_IP, + 0, + Opcode_ae_sa24x2_ip_encode_fns, 1, Opcode_ae_sa24x2_ip_funcUnit_uses }, + { "ae_sa24x2.rip", ICLASS_AE_SA24X2_RIP, + 0, + Opcode_ae_sa24x2_rip_encode_fns, 1, Opcode_ae_sa24x2_rip_funcUnit_uses }, + { "ae_sa24x2.ric", ICLASS_AE_SA24X2_RIC, + 0, + Opcode_ae_sa24x2_ric_encode_fns, 1, Opcode_ae_sa24x2_ric_funcUnit_uses }, + { "ae_sa24x2.ric1", ICLASS_AE_SA24X2_RIC1, + 0, + Opcode_ae_sa24x2_ric1_encode_fns, 1, Opcode_ae_sa24x2_ric1_funcUnit_uses }, + { "ae_addicirc", ICLASS_AE_ADDICIRC, + 0, + Opcode_ae_addicirc_encode_fns, 0, 0 }, + { "ae_addcirc.xc2", ICLASS_AE_ADDCIRC_XC2, + 0, + Opcode_ae_addcirc_xc2_encode_fns, 0, 0 }, + { "ae_addcirc.xc1", ICLASS_AE_ADDCIRC_XC1, + 0, + Opcode_ae_addcirc_xc1_encode_fns, 0, 0 }, + { "ae_addcirc.xc", ICLASS_AE_ADDCIRC_XC, + 0, + Opcode_ae_addcirc_xc_encode_fns, 0, 0 }, + { "ae_s32ra64s.i", ICLASS_AE_S32RA64S_I, + 0, + Opcode_ae_s32ra64s_i_encode_fns, 1, Opcode_ae_s32ra64s_i_funcUnit_uses }, + { "ae_s32ra64s.ip", ICLASS_AE_S32RA64S_IP, + 0, + Opcode_ae_s32ra64s_ip_encode_fns, 1, Opcode_ae_s32ra64s_ip_funcUnit_uses }, + { "ae_s32ra64s.x", ICLASS_AE_S32RA64S_X, + 0, + Opcode_ae_s32ra64s_x_encode_fns, 1, Opcode_ae_s32ra64s_x_funcUnit_uses }, + { "ae_s32ra64s.xp", ICLASS_AE_S32RA64S_XP, + 0, + Opcode_ae_s32ra64s_xp_encode_fns, 1, Opcode_ae_s32ra64s_xp_funcUnit_uses }, + { "ae_s32ra64s.xc", ICLASS_AE_S32RA64S_XC, + 0, + Opcode_ae_s32ra64s_xc_encode_fns, 1, Opcode_ae_s32ra64s_xc_funcUnit_uses }, + { "ae_s32ra64s.xc1", ICLASS_AE_S32RA64S_XC1, + 0, + Opcode_ae_s32ra64s_xc1_encode_fns, 1, Opcode_ae_s32ra64s_xc1_funcUnit_uses }, + { "ae_s24ra64s.i", ICLASS_AE_S24RA64S_I, + 0, + Opcode_ae_s24ra64s_i_encode_fns, 1, Opcode_ae_s24ra64s_i_funcUnit_uses }, + { "ae_s24ra64s.ip", ICLASS_AE_S24RA64S_IP, + 0, + Opcode_ae_s24ra64s_ip_encode_fns, 1, Opcode_ae_s24ra64s_ip_funcUnit_uses }, + { "ae_s24ra64s.x", ICLASS_AE_S24RA64S_X, + 0, + Opcode_ae_s24ra64s_x_encode_fns, 1, Opcode_ae_s24ra64s_x_funcUnit_uses }, + { "ae_s24ra64s.xp", ICLASS_AE_S24RA64S_XP, + 0, + Opcode_ae_s24ra64s_xp_encode_fns, 1, Opcode_ae_s24ra64s_xp_funcUnit_uses }, + { "ae_s24ra64s.xc", ICLASS_AE_S24RA64S_XC, + 0, + Opcode_ae_s24ra64s_xc_encode_fns, 1, Opcode_ae_s24ra64s_xc_funcUnit_uses }, + { "ae_s24ra64s.xc1", ICLASS_AE_S24RA64S_XC1, + 0, + Opcode_ae_s24ra64s_xc1_encode_fns, 1, Opcode_ae_s24ra64s_xc1_funcUnit_uses }, + { "ae_s32x2ra64s.ip", ICLASS_AE_S32X2RA64S_IP, + 0, + Opcode_ae_s32x2ra64s_ip_encode_fns, 1, Opcode_ae_s32x2ra64s_ip_funcUnit_uses }, + { "ae_s24x2ra64s.ip", ICLASS_AE_S24X2RA64S_IP, + 0, + Opcode_ae_s24x2ra64s_ip_encode_fns, 1, Opcode_ae_s24x2ra64s_ip_funcUnit_uses }, + { "ae_s16x4ra32s.ip", ICLASS_AE_S16X4RA32S_IP, + 0, + Opcode_ae_s16x4ra32s_ip_encode_fns, 1, Opcode_ae_s16x4ra32s_ip_funcUnit_uses }, + { "ae_addbrba32", ICLASS_AE_ADDBRBA32, + 0, + Opcode_ae_addbrba32_encode_fns, 0, 0 }, + { "ae_s32x2.l.ip", ICLASS_AE_S32X2_L_IP, + 0, + Opcode_ae_s32x2_l_ip_encode_fns, 1, Opcode_ae_s32x2_l_ip_funcUnit_uses }, + { "ae_bitswap", ICLASS_AE_BITSWAP, + 0, + Opcode_ae_bitswap_encode_fns, 0, 0 }, + { "ae_mul32js", ICLASS_AE_MUL32JS, + 0, + Opcode_ae_mul32js_encode_fns, 0, 0 }, + { "ae_addandsub32s", ICLASS_AE_ADDANDSUB32S, + 0, + Opcode_ae_addandsub32s_encode_fns, 0, 0 }, + { "ae_addandsub32js", ICLASS_AE_ADDANDSUB32JS, + 0, + Opcode_ae_addandsub32js_encode_fns, 0, 0 }, + { "ae_addandsubrng32", ICLASS_AE_ADDANDSUBRNG32, + 0, + Opcode_ae_addandsubrng32_encode_fns, 0, 0 }, + { "ae_addandsubrng32.h", ICLASS_AE_ADDANDSUBRNG32_H, + 0, + Opcode_ae_addandsubrng32_h_encode_fns, 0, 0 }, + { "ae_addandsubrng32.l", ICLASS_AE_ADDANDSUBRNG32_L, + 0, + Opcode_ae_addandsubrng32_l_encode_fns, 0, 0 }, + { "ae_addrng32", ICLASS_AE_ADDRNG32, + 0, + Opcode_ae_addrng32_encode_fns, 0, 0 }, + { "ae_subrng32", ICLASS_AE_SUBRNG32, + 0, + Opcode_ae_subrng32_encode_fns, 0, 0 }, + { "ae_rng32x2", ICLASS_AE_RNG32X2, + 0, + Opcode_ae_rng32x2_encode_fns, 0, 0 }, + { "ae_sel16i", ICLASS_AE_SEL16I, + 0, + Opcode_ae_sel16i_encode_fns, 0, 0 }, + { "ae_sel16i.n", ICLASS_AE_SEL16I_N, + 0, + Opcode_ae_sel16i_n_encode_fns, 0, 0 }, + { "ae_shortswap", ICLASS_AE_SHORTSWAP, + 0, + Opcode_ae_shortswap_encode_fns, 0, 0 }, + { "ae_movab4", ICLASS_AE_MOVAB4, + 0, + Opcode_ae_movab4_encode_fns, 0, 0 }, + { "ae_movab2", ICLASS_AE_MOVAB2, + 0, + Opcode_ae_movab2_encode_fns, 0, 0 }, + { "ae_movab", ICLASS_AE_MOVAB, + 0, + Opcode_ae_movab_encode_fns, 0, 0 }, + { "ae_movba", ICLASS_AE_MOVBA, + 0, + Opcode_ae_movba_encode_fns, 0, 0 }, + { "ae_movba1x2", ICLASS_AE_MOVBA1X2, + 0, + Opcode_ae_movba1x2_encode_fns, 0, 0 }, + { "ae_movba4", ICLASS_AE_MOVBA4, + 0, + Opcode_ae_movba4_encode_fns, 0, 0 }, + { "ae_movba2", ICLASS_AE_MOVBA2, + 0, + Opcode_ae_movba2_encode_fns, 0, 0 }, + { "ae_movb2", ICLASS_AE_MOVB2, + 0, + Opcode_ae_movb2_encode_fns, 0, 0 }, + { "ae_movb4", ICLASS_AE_MOVB4, + 0, + Opcode_ae_movb4_encode_fns, 0, 0 }, + { "ae_movt16x4", ICLASS_AE_MOVT16X4, + 0, + Opcode_ae_movt16x4_encode_fns, 0, 0 }, + { "ae_movf16x4", ICLASS_AE_MOVF16X4, + 0, + Opcode_ae_movf16x4_encode_fns, 0, 0 }, + { "ae_movt32x2", ICLASS_AE_MOVT32X2, + 0, + Opcode_ae_movt32x2_encode_fns, 0, 0 }, + { "ae_movf32x2", ICLASS_AE_MOVF32X2, + 0, + Opcode_ae_movf32x2_encode_fns, 0, 0 }, + { "ae_movsara7x2", ICLASS_AE_MOVSARA7X2, + 0, + Opcode_ae_movsara7x2_encode_fns, 0, 0 }, + { "ae_movsard7", ICLASS_AE_MOVSARD7, + 0, + Opcode_ae_movsard7_encode_fns, 0, 0 }, + { "ae_movasar", ICLASS_AE_MOVASAR, + 0, + Opcode_ae_movasar_encode_fns, 0, 0 }, + { "ae_movda32x2", ICLASS_AE_MOVDA32X2, + 0, + Opcode_ae_movda32x2_encode_fns, 0, 0 }, + { "ae_movda32", ICLASS_AE_MOVDA32, + 0, + Opcode_ae_movda32_encode_fns, 0, 0 }, + { "ae_movda16x2", ICLASS_AE_MOVDA16X2, + 0, + Opcode_ae_movda16x2_encode_fns, 0, 0 }, + { "ae_movda16", ICLASS_AE_MOVDA16, + 0, + Opcode_ae_movda16_encode_fns, 0, 0 }, + { "ae_movi", ICLASS_AE_MOVI, + 0, + Opcode_ae_movi_encode_fns, 0, 0 }, + { "ae_truncp24a32x2", ICLASS_AE_TRUNCP24A32X2, + 0, + Opcode_ae_truncp24a32x2_encode_fns, 0, 0 }, + { "ae_sat16x4", ICLASS_AE_SAT16X4, + 0, + Opcode_ae_sat16x4_encode_fns, 0, 0 }, + { "ae_cvt32x2f16.32", ICLASS_AE_CVT32X2F16_32, + 0, + Opcode_ae_cvt32x2f16_32_encode_fns, 0, 0 }, + { "ae_cvt32x2f16.10", ICLASS_AE_CVT32X2F16_10, + 0, + Opcode_ae_cvt32x2f16_10_encode_fns, 0, 0 }, + { "ae_sext32x2d16.32", ICLASS_AE_SEXT32X2D16_32, + 0, + Opcode_ae_sext32x2d16_32_encode_fns, 0, 0 }, + { "ae_sext32x2d16.10", ICLASS_AE_SEXT32X2D16_10, + 0, + Opcode_ae_sext32x2d16_10_encode_fns, 0, 0 }, + { "ae_cvta32f24s.l", ICLASS_AE_CVTA32F24S_L, + 0, + Opcode_ae_cvta32f24s_l_encode_fns, 0, 0 }, + { "ae_cvta32f24s.h", ICLASS_AE_CVTA32F24S_H, + 0, + Opcode_ae_cvta32f24s_h_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.ll", ICLASS_AE_CVTP24A16X2_LL, + 0, + Opcode_ae_cvtp24a16x2_ll_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.lh", ICLASS_AE_CVTP24A16X2_LH, + 0, + Opcode_ae_cvtp24a16x2_lh_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.hl", ICLASS_AE_CVTP24A16X2_HL, + 0, + Opcode_ae_cvtp24a16x2_hl_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.hh", ICLASS_AE_CVTP24A16X2_HH, + 0, + Opcode_ae_cvtp24a16x2_hh_encode_fns, 0, 0 }, + { "ae_truncp24q48x2", ICLASS_AE_TRUNCP24Q48X2, + 0, + Opcode_ae_truncp24q48x2_encode_fns, 0, 0 }, + { "ae_trunca32x2f64s", ICLASS_AE_TRUNCA32X2F64S, + 0, + Opcode_ae_trunca32x2f64s_encode_fns, 0, 0 }, + { "ae_trunci32x2f64s", ICLASS_AE_TRUNCI32X2F64S, + 0, + Opcode_ae_trunci32x2f64s_encode_fns, 0, 0 }, + { "ae_trunca32f64s.l", ICLASS_AE_TRUNCA32F64S_L, + 0, + Opcode_ae_trunca32f64s_l_encode_fns, 0, 0 }, + { "ae_trunci32f64s.l", ICLASS_AE_TRUNCI32F64S_L, + 0, + Opcode_ae_trunci32f64s_l_encode_fns, 0, 0 }, + { "ae_truncp16", ICLASS_AE_TRUNCP16, + 0, + Opcode_ae_truncp16_encode_fns, 0, 0 }, + { "ae_round32x2f64ssym", ICLASS_AE_ROUND32X2F64SSYM, + 0, + Opcode_ae_round32x2f64ssym_encode_fns, 0, 0 }, + { "ae_round32x2f64sasym", ICLASS_AE_ROUND32X2F64SASYM, + 0, + Opcode_ae_round32x2f64sasym_encode_fns, 0, 0 }, + { "ae_round32x2f48ssym", ICLASS_AE_ROUND32X2F48SSYM, + 0, + Opcode_ae_round32x2f48ssym_encode_fns, 0, 0 }, + { "ae_round32x2f48sasym", ICLASS_AE_ROUND32X2F48SASYM, + 0, + Opcode_ae_round32x2f48sasym_encode_fns, 0, 0 }, + { "ae_round16x4f32ssym", ICLASS_AE_ROUND16X4F32SSYM, + 0, + Opcode_ae_round16x4f32ssym_encode_fns, 0, 0 }, + { "ae_round16x4f32sasym", ICLASS_AE_ROUND16X4F32SASYM, + 0, + Opcode_ae_round16x4f32sasym_encode_fns, 0, 0 }, + { "ae_round24x2f48ssym", ICLASS_AE_ROUND24X2F48SSYM, + 0, + Opcode_ae_round24x2f48ssym_encode_fns, 0, 0 }, + { "ae_round24x2f48sasym", ICLASS_AE_ROUND24X2F48SASYM, + 0, + Opcode_ae_round24x2f48sasym_encode_fns, 0, 0 }, + { "ae_roundsp16q48x2sym", ICLASS_AE_ROUNDSP16Q48X2SYM, + 0, + Opcode_ae_roundsp16q48x2sym_encode_fns, 0, 0 }, + { "ae_roundsp16q48x2asym", ICLASS_AE_ROUNDSP16Q48X2ASYM, + 0, + Opcode_ae_roundsp16q48x2asym_encode_fns, 0, 0 }, + { "ae_minabs32s", ICLASS_AE_MINABS32S, + 0, + Opcode_ae_minabs32s_encode_fns, 0, 0 }, + { "ae_maxabs32s", ICLASS_AE_MAXABS32S, + 0, + Opcode_ae_maxabs32s_encode_fns, 0, 0 }, + { "ae_roundsp16f24sym", ICLASS_AE_ROUNDSP16F24SYM, + 0, + Opcode_ae_roundsp16f24sym_encode_fns, 0, 0 }, + { "ae_roundsp16f24asym", ICLASS_AE_ROUNDSP16F24ASYM, + 0, + Opcode_ae_roundsp16f24asym_encode_fns, 0, 0 }, + { "ae_mov", ICLASS_AE_MOV, + 0, + Opcode_ae_mov_encode_fns, 0, 0 }, + { "ae_movt64", ICLASS_AE_MOVT64, + 0, + Opcode_ae_movt64_encode_fns, 0, 0 }, + { "ae_movf64", ICLASS_AE_MOVF64, + 0, + Opcode_ae_movf64_encode_fns, 0, 0 }, + { "ae_cvtq56a32s", ICLASS_AE_CVTQ56A32S, + 0, + Opcode_ae_cvtq56a32s_encode_fns, 0, 0 }, + { "ae_cvt48a32", ICLASS_AE_CVT48A32, + 0, + Opcode_ae_cvt48a32_encode_fns, 0, 0 }, + { "ae_cvt64a32", ICLASS_AE_CVT64A32, + 0, + Opcode_ae_cvt64a32_encode_fns, 0, 0 }, + { "ae_cvtq56p32s.l", ICLASS_AE_CVTQ56P32S_L, + 0, + Opcode_ae_cvtq56p32s_l_encode_fns, 0, 0 }, + { "ae_cvtq56p32s.h", ICLASS_AE_CVTQ56P32S_H, + 0, + Opcode_ae_cvtq56p32s_h_encode_fns, 0, 0 }, + { "ae_cvt64f32.h", ICLASS_AE_CVT64F32_H, + 0, + Opcode_ae_cvt64f32_h_encode_fns, 0, 0 }, + { "ae_cvt48f32.l", ICLASS_AE_CVT48F32_L, + 0, + Opcode_ae_cvt48f32_l_encode_fns, 0, 0 }, + { "ae_cvt48f32.h", ICLASS_AE_CVT48F32_H, + 0, + Opcode_ae_cvt48f32_h_encode_fns, 0, 0 }, + { "ae_sat48s", ICLASS_AE_SAT48S, + 0, + Opcode_ae_sat48s_encode_fns, 0, 0 }, + { "ae_satq56s", ICLASS_AE_SATQ56S, + 0, + Opcode_ae_satq56s_encode_fns, 0, 0 }, + { "ae_sat24s", ICLASS_AE_SAT24S, + 0, + Opcode_ae_sat24s_encode_fns, 0, 0 }, + { "ae_truncq32", ICLASS_AE_TRUNCQ32, + 0, + Opcode_ae_truncq32_encode_fns, 0, 0 }, + { "ae_minabs64s", ICLASS_AE_MINABS64S, + 0, + Opcode_ae_minabs64s_encode_fns, 0, 0 }, + { "ae_maxabs64s", ICLASS_AE_MAXABS64S, + 0, + Opcode_ae_maxabs64s_encode_fns, 0, 0 }, + { "ae_roundsq32f48sym", ICLASS_AE_ROUNDSQ32F48SYM, + 0, + Opcode_ae_roundsq32f48sym_encode_fns, 0, 0 }, + { "ae_roundsq32f48asym", ICLASS_AE_ROUNDSQ32F48ASYM, + 0, + Opcode_ae_roundsq32f48asym_encode_fns, 0, 0 }, + { "ae_trunca32q48", ICLASS_AE_TRUNCA32Q48, + 0, + Opcode_ae_trunca32q48_encode_fns, 0, 0 }, + { "ae_movad32.l", ICLASS_AE_MOVAD32_L, + 0, + Opcode_ae_movad32_l_encode_fns, 0, 0 }, + { "ae_movad32.h", ICLASS_AE_MOVAD32_H, + 0, + Opcode_ae_movad32_h_encode_fns, 0, 0 }, + { "ae_movad16.3", ICLASS_AE_MOVAD16_3, + 0, + Opcode_ae_movad16_3_encode_fns, 0, 0 }, + { "ae_movad16.2", ICLASS_AE_MOVAD16_2, + 0, + Opcode_ae_movad16_2_encode_fns, 0, 0 }, + { "ae_movad16.1", ICLASS_AE_MOVAD16_1, + 0, + Opcode_ae_movad16_1_encode_fns, 0, 0 }, + { "ae_movad16.0", ICLASS_AE_MOVAD16_0, + 0, + Opcode_ae_movad16_0_encode_fns, 0, 0 }, + { "ae_sra64_32", ICLASS_AE_SRA64_32, + 0, + Opcode_ae_sra64_32_encode_fns, 0, 0 }, + { "ae_pksr32", ICLASS_AE_PKSR32, + 0, + Opcode_ae_pksr32_encode_fns, 0, 0 }, + { "ae_pksr24", ICLASS_AE_PKSR24, + 0, + Opcode_ae_pksr24_encode_fns, 0, 0 }, + { "ae_pksrf32", ICLASS_AE_PKSRF32, + 0, + Opcode_ae_pksrf32_encode_fns, 0, 0 }, + { "ae_pksr16", ICLASS_AE_PKSR16, + 0, + Opcode_ae_pksr16_encode_fns, 0, 0 }, + { "ae_trunca16p24s.l", ICLASS_AE_TRUNCA16P24S_L, + 0, + Opcode_ae_trunca16p24s_l_encode_fns, 0, 0 }, + { "ae_trunca16p24s.h", ICLASS_AE_TRUNCA16P24S_H, + 0, + Opcode_ae_trunca16p24s_h_encode_fns, 0, 0 }, + { "ae_add32", ICLASS_AE_ADD32, + 0, + Opcode_ae_add32_encode_fns, 0, 0 }, + { "ae_sub32", ICLASS_AE_SUB32, + 0, + Opcode_ae_sub32_encode_fns, 0, 0 }, + { "ae_addsub32", ICLASS_AE_ADDSUB32, + 0, + Opcode_ae_addsub32_encode_fns, 0, 0 }, + { "ae_subadd32", ICLASS_AE_SUBADD32, + 0, + Opcode_ae_subadd32_encode_fns, 0, 0 }, + { "ae_add16", ICLASS_AE_ADD16, + 0, + Opcode_ae_add16_encode_fns, 0, 0 }, + { "ae_sub16", ICLASS_AE_SUB16, + 0, + Opcode_ae_sub16_encode_fns, 0, 0 }, + { "ae_add32_hl_lh", ICLASS_AE_ADD32_HL_LH, + 0, + Opcode_ae_add32_hl_lh_encode_fns, 0, 0 }, + { "ae_addsub32_hl_lh", ICLASS_AE_ADDSUB32_HL_LH, + 0, + Opcode_ae_addsub32_hl_lh_encode_fns, 0, 0 }, + { "ae_neg32", ICLASS_AE_NEG32, + 0, + Opcode_ae_neg32_encode_fns, 0, 0 }, + { "ae_abs32", ICLASS_AE_ABS32, + 0, + Opcode_ae_abs32_encode_fns, 0, 0 }, + { "ae_neg32_l", ICLASS_AE_NEG32_L, + 0, + Opcode_ae_neg32_l_encode_fns, 0, 0 }, + { "ae_add24s", ICLASS_AE_ADD24S, + 0, + Opcode_ae_add24s_encode_fns, 0, 0 }, + { "ae_sub24s", ICLASS_AE_SUB24S, + 0, + Opcode_ae_sub24s_encode_fns, 0, 0 }, + { "ae_add32s", ICLASS_AE_ADD32S, + 0, + Opcode_ae_add32s_encode_fns, 0, 0 }, + { "ae_sub32s", ICLASS_AE_SUB32S, + 0, + Opcode_ae_sub32s_encode_fns, 0, 0 }, + { "ae_addsub32s", ICLASS_AE_ADDSUB32S, + 0, + Opcode_ae_addsub32s_encode_fns, 0, 0 }, + { "ae_subadd32s", ICLASS_AE_SUBADD32S, + 0, + Opcode_ae_subadd32s_encode_fns, 0, 0 }, + { "ae_add16s", ICLASS_AE_ADD16S, + 0, + Opcode_ae_add16s_encode_fns, 0, 0 }, + { "ae_sub16s", ICLASS_AE_SUB16S, + 0, + Opcode_ae_sub16s_encode_fns, 0, 0 }, + { "ae_add32s_hl_lh", ICLASS_AE_ADD32S_HL_LH, + 0, + Opcode_ae_add32s_hl_lh_encode_fns, 0, 0 }, + { "ae_addsub32s_hl_lh", ICLASS_AE_ADDSUB32S_HL_LH, + 0, + Opcode_ae_addsub32s_hl_lh_encode_fns, 0, 0 }, + { "ae_neg24s", ICLASS_AE_NEG24S, + 0, + Opcode_ae_neg24s_encode_fns, 0, 0 }, + { "ae_abs24s", ICLASS_AE_ABS24S, + 0, + Opcode_ae_abs24s_encode_fns, 0, 0 }, + { "ae_neg32s", ICLASS_AE_NEG32S, + 0, + Opcode_ae_neg32s_encode_fns, 0, 0 }, + { "ae_abs32s", ICLASS_AE_ABS32S, + 0, + Opcode_ae_abs32s_encode_fns, 0, 0 }, + { "ae_neg16s", ICLASS_AE_NEG16S, + 0, + Opcode_ae_neg16s_encode_fns, 0, 0 }, + { "ae_abs16s", ICLASS_AE_ABS16S, + 0, + Opcode_ae_abs16s_encode_fns, 0, 0 }, + { "ae_abs16", ICLASS_AE_ABS16, + 0, + Opcode_ae_abs16_encode_fns, 0, 0 }, + { "ae_mulc16js.h", ICLASS_AE_MULC16JS_H, + 0, + Opcode_ae_mulc16js_h_encode_fns, 0, 0 }, + { "ae_mulc16js.l", ICLASS_AE_MULC16JS_L, + 0, + Opcode_ae_mulc16js_l_encode_fns, 0, 0 }, + { "ae_mulac16js.h", ICLASS_AE_MULAC16JS_H, + 0, + Opcode_ae_mulac16js_h_encode_fns, 0, 0 }, + { "ae_mulac16js.l", ICLASS_AE_MULAC16JS_L, + 0, + Opcode_ae_mulac16js_l_encode_fns, 0, 0 }, + { "ae_lt16", ICLASS_AE_LT16, + 0, + Opcode_ae_lt16_encode_fns, 0, 0 }, + { "ae_le16", ICLASS_AE_LE16, + 0, + Opcode_ae_le16_encode_fns, 0, 0 }, + { "ae_eq16", ICLASS_AE_EQ16, + 0, + Opcode_ae_eq16_encode_fns, 0, 0 }, + { "ae_lt32", ICLASS_AE_LT32, + 0, + Opcode_ae_lt32_encode_fns, 0, 0 }, + { "ae_le32", ICLASS_AE_LE32, + 0, + Opcode_ae_le32_encode_fns, 0, 0 }, + { "ae_eq32", ICLASS_AE_EQ32, + 0, + Opcode_ae_eq32_encode_fns, 0, 0 }, + { "ae_min32", ICLASS_AE_MIN32, + 0, + Opcode_ae_min32_encode_fns, 0, 0 }, + { "ae_max32", ICLASS_AE_MAX32, + 0, + Opcode_ae_max32_encode_fns, 0, 0 }, + { "ae_minmax32", ICLASS_AE_MINMAX32, + 0, + Opcode_ae_minmax32_encode_fns, 0, 0 }, + { "ae_minmax16", ICLASS_AE_MINMAX16, + 0, + Opcode_ae_minmax16_encode_fns, 0, 0 }, + { "ae_min16", ICLASS_AE_MIN16, + 0, + Opcode_ae_min16_encode_fns, 0, 0 }, + { "ae_max16", ICLASS_AE_MAX16, + 0, + Opcode_ae_max16_encode_fns, 0, 0 }, + { "ae_add64", ICLASS_AE_ADD64, + 0, + Opcode_ae_add64_encode_fns, 0, 0 }, + { "ae_sub64", ICLASS_AE_SUB64, + 0, + Opcode_ae_sub64_encode_fns, 0, 0 }, + { "ae_neg64", ICLASS_AE_NEG64, + 0, + Opcode_ae_neg64_encode_fns, 0, 0 }, + { "ae_abs64", ICLASS_AE_ABS64, + 0, + Opcode_ae_abs64_encode_fns, 0, 0 }, + { "ae_addsq56s", ICLASS_AE_ADDSQ56S, + 0, + Opcode_ae_addsq56s_encode_fns, 0, 0 }, + { "ae_subsq56s", ICLASS_AE_SUBSQ56S, + 0, + Opcode_ae_subsq56s_encode_fns, 0, 0 }, + { "ae_add64s", ICLASS_AE_ADD64S, + 0, + Opcode_ae_add64s_encode_fns, 0, 0 }, + { "ae_sub64s", ICLASS_AE_SUB64S, + 0, + Opcode_ae_sub64s_encode_fns, 0, 0 }, + { "ae_negsq56s", ICLASS_AE_NEGSQ56S, + 0, + Opcode_ae_negsq56s_encode_fns, 0, 0 }, + { "ae_abssq56s", ICLASS_AE_ABSSQ56S, + 0, + Opcode_ae_abssq56s_encode_fns, 0, 0 }, + { "ae_neg64s", ICLASS_AE_NEG64S, + 0, + Opcode_ae_neg64s_encode_fns, 0, 0 }, + { "ae_abs64s", ICLASS_AE_ABS64S, + 0, + Opcode_ae_abs64s_encode_fns, 0, 0 }, + { "ae_and", ICLASS_AE_AND, + 0, + Opcode_ae_and_encode_fns, 0, 0 }, + { "ae_nand", ICLASS_AE_NAND, + 0, + Opcode_ae_nand_encode_fns, 0, 0 }, + { "ae_or", ICLASS_AE_OR, + 0, + Opcode_ae_or_encode_fns, 0, 0 }, + { "ae_xor", ICLASS_AE_XOR, + 0, + Opcode_ae_xor_encode_fns, 0, 0 }, + { "ae_slai24", ICLASS_AE_SLAI24, + 0, + Opcode_ae_slai24_encode_fns, 0, 0 }, + { "ae_srli24", ICLASS_AE_SRLI24, + 0, + Opcode_ae_srli24_encode_fns, 0, 0 }, + { "ae_srai24", ICLASS_AE_SRAI24, + 0, + Opcode_ae_srai24_encode_fns, 0, 0 }, + { "ae_slas24", ICLASS_AE_SLAS24, + 0, + Opcode_ae_slas24_encode_fns, 0, 0 }, + { "ae_srls24", ICLASS_AE_SRLS24, + 0, + Opcode_ae_srls24_encode_fns, 0, 0 }, + { "ae_sras24", ICLASS_AE_SRAS24, + 0, + Opcode_ae_sras24_encode_fns, 0, 0 }, + { "ae_srai16", ICLASS_AE_SRAI16, + 0, + Opcode_ae_srai16_encode_fns, 0, 0 }, + { "ae_srai16r", ICLASS_AE_SRAI16R, + 0, + Opcode_ae_srai16r_encode_fns, 0, 0 }, + { "ae_slai32", ICLASS_AE_SLAI32, + 0, + Opcode_ae_slai32_encode_fns, 0, 0 }, + { "ae_srli32", ICLASS_AE_SRLI32, + 0, + Opcode_ae_srli32_encode_fns, 0, 0 }, + { "ae_srai32", ICLASS_AE_SRAI32, + 0, + Opcode_ae_srai32_encode_fns, 0, 0 }, + { "ae_srai32r", ICLASS_AE_SRAI32R, + 0, + Opcode_ae_srai32r_encode_fns, 0, 0 }, + { "ae_slas32", ICLASS_AE_SLAS32, + 0, + Opcode_ae_slas32_encode_fns, 0, 0 }, + { "ae_srls32", ICLASS_AE_SRLS32, + 0, + Opcode_ae_srls32_encode_fns, 0, 0 }, + { "ae_sras32", ICLASS_AE_SRAS32, + 0, + Opcode_ae_sras32_encode_fns, 0, 0 }, + { "ae_slaa32", ICLASS_AE_SLAA32, + 0, + Opcode_ae_slaa32_encode_fns, 0, 0 }, + { "ae_srla32", ICLASS_AE_SRLA32, + 0, + Opcode_ae_srla32_encode_fns, 0, 0 }, + { "ae_sraa32", ICLASS_AE_SRAA32, + 0, + Opcode_ae_sraa32_encode_fns, 0, 0 }, + { "ae_slai16s", ICLASS_AE_SLAI16S, + 0, + Opcode_ae_slai16s_encode_fns, 0, 0 }, + { "ae_slaa16s", ICLASS_AE_SLAA16S, + 0, + Opcode_ae_slaa16s_encode_fns, 0, 0 }, + { "ae_sraa16s", ICLASS_AE_SRAA16S, + 0, + Opcode_ae_sraa16s_encode_fns, 0, 0 }, + { "ae_sraa16rs", ICLASS_AE_SRAA16RS, + 0, + Opcode_ae_sraa16rs_encode_fns, 0, 0 }, + { "ae_slai24s", ICLASS_AE_SLAI24S, + 0, + Opcode_ae_slai24s_encode_fns, 0, 0 }, + { "ae_slas24s", ICLASS_AE_SLAS24S, + 0, + Opcode_ae_slas24s_encode_fns, 0, 0 }, + { "ae_slai32s", ICLASS_AE_SLAI32S, + 0, + Opcode_ae_slai32s_encode_fns, 0, 0 }, + { "ae_slas32s", ICLASS_AE_SLAS32S, + 0, + Opcode_ae_slas32s_encode_fns, 0, 0 }, + { "ae_slaa32s", ICLASS_AE_SLAA32S, + 0, + Opcode_ae_slaa32s_encode_fns, 0, 0 }, + { "ae_sraa32s", ICLASS_AE_SRAA32S, + 0, + Opcode_ae_sraa32s_encode_fns, 0, 0 }, + { "ae_sraa32rs", ICLASS_AE_SRAA32RS, + 0, + Opcode_ae_sraa32rs_encode_fns, 0, 0 }, + { "ae_slasq56", ICLASS_AE_SLASQ56, + 0, + Opcode_ae_slasq56_encode_fns, 0, 0 }, + { "ae_srlsq56", ICLASS_AE_SRLSQ56, + 0, + Opcode_ae_srlsq56_encode_fns, 0, 0 }, + { "ae_srasq56", ICLASS_AE_SRASQ56, + 0, + Opcode_ae_srasq56_encode_fns, 0, 0 }, + { "ae_slaaq56", ICLASS_AE_SLAAQ56, + 0, + Opcode_ae_slaaq56_encode_fns, 0, 0 }, + { "ae_srlaq56", ICLASS_AE_SRLAQ56, + 0, + Opcode_ae_srlaq56_encode_fns, 0, 0 }, + { "ae_sraaq56", ICLASS_AE_SRAAQ56, + 0, + Opcode_ae_sraaq56_encode_fns, 0, 0 }, + { "ae_slai64", ICLASS_AE_SLAI64, + 0, + Opcode_ae_slai64_encode_fns, 0, 0 }, + { "ae_srli64", ICLASS_AE_SRLI64, + 0, + Opcode_ae_srli64_encode_fns, 0, 0 }, + { "ae_srai64", ICLASS_AE_SRAI64, + 0, + Opcode_ae_srai64_encode_fns, 0, 0 }, + { "ae_slas64", ICLASS_AE_SLAS64, + 0, + Opcode_ae_slas64_encode_fns, 0, 0 }, + { "ae_srls64", ICLASS_AE_SRLS64, + 0, + Opcode_ae_srls64_encode_fns, 0, 0 }, + { "ae_sras64", ICLASS_AE_SRAS64, + 0, + Opcode_ae_sras64_encode_fns, 0, 0 }, + { "ae_slaa64", ICLASS_AE_SLAA64, + 0, + Opcode_ae_slaa64_encode_fns, 0, 0 }, + { "ae_srla64", ICLASS_AE_SRLA64, + 0, + Opcode_ae_srla64_encode_fns, 0, 0 }, + { "ae_sraa64", ICLASS_AE_SRAA64, + 0, + Opcode_ae_sraa64_encode_fns, 0, 0 }, + { "ae_slaisq56s", ICLASS_AE_SLAISQ56S, + 0, + Opcode_ae_slaisq56s_encode_fns, 0, 0 }, + { "ae_slassq56s", ICLASS_AE_SLASSQ56S, + 0, + Opcode_ae_slassq56s_encode_fns, 0, 0 }, + { "ae_slaasq56s", ICLASS_AE_SLAASQ56S, + 0, + Opcode_ae_slaasq56s_encode_fns, 0, 0 }, + { "ae_slai64s", ICLASS_AE_SLAI64S, + 0, + Opcode_ae_slai64s_encode_fns, 0, 0 }, + { "ae_slas64s", ICLASS_AE_SLAS64S, + 0, + Opcode_ae_slas64s_encode_fns, 0, 0 }, + { "ae_slaa64s", ICLASS_AE_SLAA64S, + 0, + Opcode_ae_slaa64s_encode_fns, 0, 0 }, + { "ae_lt64", ICLASS_AE_LT64, + 0, + Opcode_ae_lt64_encode_fns, 0, 0 }, + { "ae_le64", ICLASS_AE_LE64, + 0, + Opcode_ae_le64_encode_fns, 0, 0 }, + { "ae_eq64", ICLASS_AE_EQ64, + 0, + Opcode_ae_eq64_encode_fns, 0, 0 }, + { "ae_max64", ICLASS_AE_MAX64, + 0, + Opcode_ae_max64_encode_fns, 0, 0 }, + { "ae_min64", ICLASS_AE_MIN64, + 0, + Opcode_ae_min64_encode_fns, 0, 0 }, + { "ae_nsa64", ICLASS_AE_NSA64, + 0, + Opcode_ae_nsa64_encode_fns, 0, 0 }, + { "ae_nsaz16.0", ICLASS_AE_NSAZ16_0, + 0, + Opcode_ae_nsaz16_0_encode_fns, 0, 0 }, + { "ae_nsaz32.l", ICLASS_AE_NSAZ32_L, + 0, + Opcode_ae_nsaz32_l_encode_fns, 0, 0 }, + { "ae_muls32f48p16s.ll", ICLASS_AE_MULS32F48P16S_LL, + 0, + Opcode_ae_muls32f48p16s_ll_encode_fns, 0, 0 }, + { "ae_mulf32s.ll", ICLASS_AE_MULF32S_LL, + 0, + Opcode_ae_mulf32s_ll_encode_fns, 0, 0 }, + { "ae_mul32.ll", ICLASS_AE_MUL32_LL, + 0, + Opcode_ae_mul32_ll_encode_fns, 0, 0 }, + { "ae_mulf32r.ll", ICLASS_AE_MULF32R_LL, + 0, + Opcode_ae_mulf32r_ll_encode_fns, 0, 0 }, + { "ae_mulf32ra.ll", ICLASS_AE_MULF32RA_LL, + 0, + Opcode_ae_mulf32ra_ll_encode_fns, 0, 0 }, + { "ae_muls32f48p16s.lh", ICLASS_AE_MULS32F48P16S_LH, + 0, + Opcode_ae_muls32f48p16s_lh_encode_fns, 0, 0 }, + { "ae_mulf32s.lh", ICLASS_AE_MULF32S_LH, + 0, + Opcode_ae_mulf32s_lh_encode_fns, 0, 0 }, + { "ae_mul32.lh", ICLASS_AE_MUL32_LH, + 0, + Opcode_ae_mul32_lh_encode_fns, 0, 0 }, + { "ae_mulf32r.lh", ICLASS_AE_MULF32R_LH, + 0, + Opcode_ae_mulf32r_lh_encode_fns, 0, 0 }, + { "ae_mulf32ra.lh", ICLASS_AE_MULF32RA_LH, + 0, + Opcode_ae_mulf32ra_lh_encode_fns, 0, 0 }, + { "ae_muls32f48p16s.hh", ICLASS_AE_MULS32F48P16S_HH, + 0, + Opcode_ae_muls32f48p16s_hh_encode_fns, 0, 0 }, + { "ae_mulf32s.hh", ICLASS_AE_MULF32S_HH, + 0, + Opcode_ae_mulf32s_hh_encode_fns, 0, 0 }, + { "ae_mul32.hh", ICLASS_AE_MUL32_HH, + 0, + Opcode_ae_mul32_hh_encode_fns, 0, 0 }, + { "ae_mulf32r.hh", ICLASS_AE_MULF32R_HH, + 0, + Opcode_ae_mulf32r_hh_encode_fns, 0, 0 }, + { "ae_mulf32ra.hh", ICLASS_AE_MULF32RA_HH, + 0, + Opcode_ae_mulf32ra_hh_encode_fns, 0, 0 }, + { "ae_mulas32f48p16s.ll", ICLASS_AE_MULAS32F48P16S_LL, + 0, + Opcode_ae_mulas32f48p16s_ll_encode_fns, 0, 0 }, + { "ae_mulaf32s.ll", ICLASS_AE_MULAF32S_LL, + 0, + Opcode_ae_mulaf32s_ll_encode_fns, 0, 0 }, + { "ae_mula32.ll", ICLASS_AE_MULA32_LL, + 0, + Opcode_ae_mula32_ll_encode_fns, 0, 0 }, + { "ae_mulaf32r.ll", ICLASS_AE_MULAF32R_LL, + 0, + Opcode_ae_mulaf32r_ll_encode_fns, 0, 0 }, + { "ae_mulaf32ra.ll", ICLASS_AE_MULAF32RA_LL, + 0, + Opcode_ae_mulaf32ra_ll_encode_fns, 0, 0 }, + { "ae_mulas32f48p16s.lh", ICLASS_AE_MULAS32F48P16S_LH, + 0, + Opcode_ae_mulas32f48p16s_lh_encode_fns, 0, 0 }, + { "ae_mulaf32s.lh", ICLASS_AE_MULAF32S_LH, + 0, + Opcode_ae_mulaf32s_lh_encode_fns, 0, 0 }, + { "ae_mula32.lh", ICLASS_AE_MULA32_LH, + 0, + Opcode_ae_mula32_lh_encode_fns, 0, 0 }, + { "ae_mulaf32r.lh", ICLASS_AE_MULAF32R_LH, + 0, + Opcode_ae_mulaf32r_lh_encode_fns, 0, 0 }, + { "ae_mulaf32ra.lh", ICLASS_AE_MULAF32RA_LH, + 0, + Opcode_ae_mulaf32ra_lh_encode_fns, 0, 0 }, + { "ae_mulas32f48p16s.hh", ICLASS_AE_MULAS32F48P16S_HH, + 0, + Opcode_ae_mulas32f48p16s_hh_encode_fns, 0, 0 }, + { "ae_mulaf32s.hh", ICLASS_AE_MULAF32S_HH, + 0, + Opcode_ae_mulaf32s_hh_encode_fns, 0, 0 }, + { "ae_mula32.hh", ICLASS_AE_MULA32_HH, + 0, + Opcode_ae_mula32_hh_encode_fns, 0, 0 }, + { "ae_mulaf32r.hh", ICLASS_AE_MULAF32R_HH, + 0, + Opcode_ae_mulaf32r_hh_encode_fns, 0, 0 }, + { "ae_mulaf32ra.hh", ICLASS_AE_MULAF32RA_HH, + 0, + Opcode_ae_mulaf32ra_hh_encode_fns, 0, 0 }, + { "ae_mulss32f48p16s.ll", ICLASS_AE_MULSS32F48P16S_LL, + 0, + Opcode_ae_mulss32f48p16s_ll_encode_fns, 0, 0 }, + { "ae_mulsf32s.ll", ICLASS_AE_MULSF32S_LL, + 0, + Opcode_ae_mulsf32s_ll_encode_fns, 0, 0 }, + { "ae_muls32.ll", ICLASS_AE_MULS32_LL, + 0, + Opcode_ae_muls32_ll_encode_fns, 0, 0 }, + { "ae_mulsf32r.ll", ICLASS_AE_MULSF32R_LL, + 0, + Opcode_ae_mulsf32r_ll_encode_fns, 0, 0 }, + { "ae_mulsf32ra.ll", ICLASS_AE_MULSF32RA_LL, + 0, + Opcode_ae_mulsf32ra_ll_encode_fns, 0, 0 }, + { "ae_mulss32f48p16s.lh", ICLASS_AE_MULSS32F48P16S_LH, + 0, + Opcode_ae_mulss32f48p16s_lh_encode_fns, 0, 0 }, + { "ae_mulsf32s.lh", ICLASS_AE_MULSF32S_LH, + 0, + Opcode_ae_mulsf32s_lh_encode_fns, 0, 0 }, + { "ae_muls32.lh", ICLASS_AE_MULS32_LH, + 0, + Opcode_ae_muls32_lh_encode_fns, 0, 0 }, + { "ae_mulsf32r.lh", ICLASS_AE_MULSF32R_LH, + 0, + Opcode_ae_mulsf32r_lh_encode_fns, 0, 0 }, + { "ae_mulsf32ra.lh", ICLASS_AE_MULSF32RA_LH, + 0, + Opcode_ae_mulsf32ra_lh_encode_fns, 0, 0 }, + { "ae_mulss32f48p16s.hh", ICLASS_AE_MULSS32F48P16S_HH, + 0, + Opcode_ae_mulss32f48p16s_hh_encode_fns, 0, 0 }, + { "ae_mulsf32s.hh", ICLASS_AE_MULSF32S_HH, + 0, + Opcode_ae_mulsf32s_hh_encode_fns, 0, 0 }, + { "ae_muls32.hh", ICLASS_AE_MULS32_HH, + 0, + Opcode_ae_muls32_hh_encode_fns, 0, 0 }, + { "ae_mulsf32r.hh", ICLASS_AE_MULSF32R_HH, + 0, + Opcode_ae_mulsf32r_hh_encode_fns, 0, 0 }, + { "ae_mulsf32ra.hh", ICLASS_AE_MULSF32RA_HH, + 0, + Opcode_ae_mulsf32ra_hh_encode_fns, 0, 0 }, + { "ae_mul32u.ll", ICLASS_AE_MUL32U_LL, + 0, + Opcode_ae_mul32u_ll_encode_fns, 0, 0 }, + { "ae_mula32u.ll", ICLASS_AE_MULA32U_LL, + 0, + Opcode_ae_mula32u_ll_encode_fns, 0, 0 }, + { "ae_muls32u.ll", ICLASS_AE_MULS32U_LL, + 0, + Opcode_ae_muls32u_ll_encode_fns, 0, 0 }, + { "ae_mulf16ss.33", ICLASS_AE_MULF16SS_33, + 0, + Opcode_ae_mulf16ss_33_encode_fns, 0, 0 }, + { "ae_mulf16ss.22", ICLASS_AE_MULF16SS_22, + 0, + Opcode_ae_mulf16ss_22_encode_fns, 0, 0 }, + { "ae_mulf16ss.32", ICLASS_AE_MULF16SS_32, + 0, + Opcode_ae_mulf16ss_32_encode_fns, 0, 0 }, + { "ae_mulf16ss.21", ICLASS_AE_MULF16SS_21, + 0, + Opcode_ae_mulf16ss_21_encode_fns, 0, 0 }, + { "ae_mulf16ss.31", ICLASS_AE_MULF16SS_31, + 0, + Opcode_ae_mulf16ss_31_encode_fns, 0, 0 }, + { "ae_mulf16ss.30", ICLASS_AE_MULF16SS_30, + 0, + Opcode_ae_mulf16ss_30_encode_fns, 0, 0 }, + { "ae_mulf16ss.10", ICLASS_AE_MULF16SS_10, + 0, + Opcode_ae_mulf16ss_10_encode_fns, 0, 0 }, + { "ae_mulf16ss.20", ICLASS_AE_MULF16SS_20, + 0, + Opcode_ae_mulf16ss_20_encode_fns, 0, 0 }, + { "ae_mulf16ss.11", ICLASS_AE_MULF16SS_11, + 0, + Opcode_ae_mulf16ss_11_encode_fns, 0, 0 }, + { "ae_mulf16ss.00", ICLASS_AE_MULF16SS_00, + 0, + Opcode_ae_mulf16ss_00_encode_fns, 0, 0 }, + { "ae_mulsf16ss.33", ICLASS_AE_MULSF16SS_33, + 0, + Opcode_ae_mulsf16ss_33_encode_fns, 0, 0 }, + { "ae_mulsf16ss.22", ICLASS_AE_MULSF16SS_22, + 0, + Opcode_ae_mulsf16ss_22_encode_fns, 0, 0 }, + { "ae_mulsf16ss.32", ICLASS_AE_MULSF16SS_32, + 0, + Opcode_ae_mulsf16ss_32_encode_fns, 0, 0 }, + { "ae_mulsf16ss.21", ICLASS_AE_MULSF16SS_21, + 0, + Opcode_ae_mulsf16ss_21_encode_fns, 0, 0 }, + { "ae_mulsf16ss.31", ICLASS_AE_MULSF16SS_31, + 0, + Opcode_ae_mulsf16ss_31_encode_fns, 0, 0 }, + { "ae_mulsf16ss.30", ICLASS_AE_MULSF16SS_30, + 0, + Opcode_ae_mulsf16ss_30_encode_fns, 0, 0 }, + { "ae_mulsf16ss.10", ICLASS_AE_MULSF16SS_10, + 0, + Opcode_ae_mulsf16ss_10_encode_fns, 0, 0 }, + { "ae_mulsf16ss.20", ICLASS_AE_MULSF16SS_20, + 0, + Opcode_ae_mulsf16ss_20_encode_fns, 0, 0 }, + { "ae_mulsf16ss.11", ICLASS_AE_MULSF16SS_11, + 0, + Opcode_ae_mulsf16ss_11_encode_fns, 0, 0 }, + { "ae_mulsf16ss.00", ICLASS_AE_MULSF16SS_00, + 0, + Opcode_ae_mulsf16ss_00_encode_fns, 0, 0 }, + { "ae_mulaf16ss.33", ICLASS_AE_MULAF16SS_33, + 0, + Opcode_ae_mulaf16ss_33_encode_fns, 0, 0 }, + { "ae_mulaf16ss.22", ICLASS_AE_MULAF16SS_22, + 0, + Opcode_ae_mulaf16ss_22_encode_fns, 0, 0 }, + { "ae_mulaf16ss.32", ICLASS_AE_MULAF16SS_32, + 0, + Opcode_ae_mulaf16ss_32_encode_fns, 0, 0 }, + { "ae_mulaf16ss.21", ICLASS_AE_MULAF16SS_21, + 0, + Opcode_ae_mulaf16ss_21_encode_fns, 0, 0 }, + { "ae_mulaf16ss.31", ICLASS_AE_MULAF16SS_31, + 0, + Opcode_ae_mulaf16ss_31_encode_fns, 0, 0 }, + { "ae_mulaf16ss.30", ICLASS_AE_MULAF16SS_30, + 0, + Opcode_ae_mulaf16ss_30_encode_fns, 0, 0 }, + { "ae_mulaf16ss.10", ICLASS_AE_MULAF16SS_10, + 0, + Opcode_ae_mulaf16ss_10_encode_fns, 0, 0 }, + { "ae_mulaf16ss.20", ICLASS_AE_MULAF16SS_20, + 0, + Opcode_ae_mulaf16ss_20_encode_fns, 0, 0 }, + { "ae_mulaf16ss.11", ICLASS_AE_MULAF16SS_11, + 0, + Opcode_ae_mulaf16ss_11_encode_fns, 0, 0 }, + { "ae_mulaf16ss.00", ICLASS_AE_MULAF16SS_00, + 0, + Opcode_ae_mulaf16ss_00_encode_fns, 0, 0 }, + { "ae_mul16s.00", ICLASS_AE_MUL16S_00, + 0, + Opcode_ae_mul16s_00_encode_fns, 0, 0 }, + { "ae_mula16s.00", ICLASS_AE_MULA16S_00, + 0, + Opcode_ae_mula16s_00_encode_fns, 0, 0 }, + { "ae_muls16s.00", ICLASS_AE_MULS16S_00, + 0, + Opcode_ae_muls16s_00_encode_fns, 0, 0 }, + { "ae_mulaafd16ss.33_22", ICLASS_AE_MULAAFD16SS_33_22, + 0, + Opcode_ae_mulaafd16ss_33_22_encode_fns, 0, 0 }, + { "ae_mulaafd16ss.13_02", ICLASS_AE_MULAAFD16SS_13_02, + 0, + Opcode_ae_mulaafd16ss_13_02_encode_fns, 0, 0 }, + { "ae_mulaafd16ss.11_00", ICLASS_AE_MULAAFD16SS_11_00, + 0, + Opcode_ae_mulaafd16ss_11_00_encode_fns, 0, 0 }, + { "ae_mulssfd16ss.33_22", ICLASS_AE_MULSSFD16SS_33_22, + 0, + Opcode_ae_mulssfd16ss_33_22_encode_fns, 0, 0 }, + { "ae_mulssfd16ss.13_02", ICLASS_AE_MULSSFD16SS_13_02, + 0, + Opcode_ae_mulssfd16ss_13_02_encode_fns, 0, 0 }, + { "ae_mulssfd16ss.11_00", ICLASS_AE_MULSSFD16SS_11_00, + 0, + Opcode_ae_mulssfd16ss_11_00_encode_fns, 0, 0 }, + { "ae_mulzaafd16ss.33_22", ICLASS_AE_MULZAAFD16SS_33_22, + 0, + Opcode_ae_mulzaafd16ss_33_22_encode_fns, 0, 0 }, + { "ae_mulzaafd16ss.13_02", ICLASS_AE_MULZAAFD16SS_13_02, + 0, + Opcode_ae_mulzaafd16ss_13_02_encode_fns, 0, 0 }, + { "ae_mulzaafd16ss.11_00", ICLASS_AE_MULZAAFD16SS_11_00, + 0, + Opcode_ae_mulzaafd16ss_11_00_encode_fns, 0, 0 }, + { "ae_mulzssfd16ss.33_22", ICLASS_AE_MULZSSFD16SS_33_22, + 0, + Opcode_ae_mulzssfd16ss_33_22_encode_fns, 0, 0 }, + { "ae_mulzssfd16ss.13_02", ICLASS_AE_MULZSSFD16SS_13_02, + 0, + Opcode_ae_mulzssfd16ss_13_02_encode_fns, 0, 0 }, + { "ae_mulzssfd16ss.11_00", ICLASS_AE_MULZSSFD16SS_11_00, + 0, + Opcode_ae_mulzssfd16ss_11_00_encode_fns, 0, 0 }, + { "ae_mulf48q32sp16s.l", ICLASS_AE_MULF48Q32SP16S_L, + 0, + Opcode_ae_mulf48q32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulf48q32sp16u.l", ICLASS_AE_MULF48Q32SP16U_L, + 0, + Opcode_ae_mulf48q32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulq32sp16s.l", ICLASS_AE_MULQ32SP16S_L, + 0, + Opcode_ae_mulq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulq32sp16u.l", ICLASS_AE_MULQ32SP16U_L, + 0, + Opcode_ae_mulq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulaf48q32sp16s.l", ICLASS_AE_MULAF48Q32SP16S_L, + 0, + Opcode_ae_mulaf48q32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulaf48q32sp16u.l", ICLASS_AE_MULAF48Q32SP16U_L, + 0, + Opcode_ae_mulaf48q32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulaq32sp16s.l", ICLASS_AE_MULAQ32SP16S_L, + 0, + Opcode_ae_mulaq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulaq32sp16u.l", ICLASS_AE_MULAQ32SP16U_L, + 0, + Opcode_ae_mulaq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulsf48q32sp16s.l", ICLASS_AE_MULSF48Q32SP16S_L, + 0, + Opcode_ae_mulsf48q32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulsf48q32sp16u.l", ICLASS_AE_MULSF48Q32SP16U_L, + 0, + Opcode_ae_mulsf48q32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulsq32sp16s.l", ICLASS_AE_MULSQ32SP16S_L, + 0, + Opcode_ae_mulsq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulsq32sp16u.l", ICLASS_AE_MULSQ32SP16U_L, + 0, + Opcode_ae_mulsq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulfp24x2ra", ICLASS_AE_MULFP24X2RA, + 0, + Opcode_ae_mulfp24x2ra_encode_fns, 0, 0 }, + { "ae_mulfp24x2r", ICLASS_AE_MULFP24X2R, + 0, + Opcode_ae_mulfp24x2r_encode_fns, 0, 0 }, + { "ae_mulafp24x2ra", ICLASS_AE_MULAFP24X2RA, + 0, + Opcode_ae_mulafp24x2ra_encode_fns, 0, 0 }, + { "ae_mulafp24x2r", ICLASS_AE_MULAFP24X2R, + 0, + Opcode_ae_mulafp24x2r_encode_fns, 0, 0 }, + { "ae_mulsfp24x2ra", ICLASS_AE_MULSFP24X2RA, + 0, + Opcode_ae_mulsfp24x2ra_encode_fns, 0, 0 }, + { "ae_mulsfp24x2r", ICLASS_AE_MULSFP24X2R, + 0, + Opcode_ae_mulsfp24x2r_encode_fns, 0, 0 }, + { "ae_mulzaafd32s.hh.ll", ICLASS_AE_MULZAAFD32S_HH_LL, + 0, + Opcode_ae_mulzaafd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaafd32ra.hh.ll", ICLASS_AE_MULZAAFD32RA_HH_LL, + 0, + Opcode_ae_mulzaafd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaad32.hh.ll", ICLASS_AE_MULZAAD32_HH_LL, + 0, + Opcode_ae_mulzaad32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaafd32s.hl.lh", ICLASS_AE_MULZAAFD32S_HL_LH, + 0, + Opcode_ae_mulzaafd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaafd32ra.hl.lh", ICLASS_AE_MULZAAFD32RA_HL_LH, + 0, + Opcode_ae_mulzaafd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaad32.hl.lh", ICLASS_AE_MULZAAD32_HL_LH, + 0, + Opcode_ae_mulzaad32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasfd32s.hh.ll", ICLASS_AE_MULZASFD32S_HH_LL, + 0, + Opcode_ae_mulzasfd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasfd32ra.hh.ll", ICLASS_AE_MULZASFD32RA_HH_LL, + 0, + Opcode_ae_mulzasfd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasd32.hh.ll", ICLASS_AE_MULZASD32_HH_LL, + 0, + Opcode_ae_mulzasd32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasfd32s.hl.lh", ICLASS_AE_MULZASFD32S_HL_LH, + 0, + Opcode_ae_mulzasfd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasfd32ra.hl.lh", ICLASS_AE_MULZASFD32RA_HL_LH, + 0, + Opcode_ae_mulzasfd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasd32.hl.lh", ICLASS_AE_MULZASD32_HL_LH, + 0, + Opcode_ae_mulzasd32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzsafd32s.hh.ll", ICLASS_AE_MULZSAFD32S_HH_LL, + 0, + Opcode_ae_mulzsafd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsafd32ra.hh.ll", ICLASS_AE_MULZSAFD32RA_HH_LL, + 0, + Opcode_ae_mulzsafd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsad32.hh.ll", ICLASS_AE_MULZSAD32_HH_LL, + 0, + Opcode_ae_mulzsad32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssfd32s.hh.ll", ICLASS_AE_MULZSSFD32S_HH_LL, + 0, + Opcode_ae_mulzssfd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssfd32ra.hh.ll", ICLASS_AE_MULZSSFD32RA_HH_LL, + 0, + Opcode_ae_mulzssfd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssd32.hh.ll", ICLASS_AE_MULZSSD32_HH_LL, + 0, + Opcode_ae_mulzssd32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssfd32s.hl.lh", ICLASS_AE_MULZSSFD32S_HL_LH, + 0, + Opcode_ae_mulzssfd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssfd32ra.hl.lh", ICLASS_AE_MULZSSFD32RA_HL_LH, + 0, + Opcode_ae_mulzssfd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssd32.hl.lh", ICLASS_AE_MULZSSD32_HL_LH, + 0, + Opcode_ae_mulzssd32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaafd32s.hh.ll", ICLASS_AE_MULAAFD32S_HH_LL, + 0, + Opcode_ae_mulaafd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaafd32ra.hh.ll", ICLASS_AE_MULAAFD32RA_HH_LL, + 0, + Opcode_ae_mulaafd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaad32.hh.ll", ICLASS_AE_MULAAD32_HH_LL, + 0, + Opcode_ae_mulaad32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaafd32s.hl.lh", ICLASS_AE_MULAAFD32S_HL_LH, + 0, + Opcode_ae_mulaafd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaafd32ra.hl.lh", ICLASS_AE_MULAAFD32RA_HL_LH, + 0, + Opcode_ae_mulaafd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaad32.hl.lh", ICLASS_AE_MULAAD32_HL_LH, + 0, + Opcode_ae_mulaad32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasfd32s.hh.ll", ICLASS_AE_MULASFD32S_HH_LL, + 0, + Opcode_ae_mulasfd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasfd32ra.hh.ll", ICLASS_AE_MULASFD32RA_HH_LL, + 0, + Opcode_ae_mulasfd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasd32.hh.ll", ICLASS_AE_MULASD32_HH_LL, + 0, + Opcode_ae_mulasd32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasfd32s.hl.lh", ICLASS_AE_MULASFD32S_HL_LH, + 0, + Opcode_ae_mulasfd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasfd32ra.hl.lh", ICLASS_AE_MULASFD32RA_HL_LH, + 0, + Opcode_ae_mulasfd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasd32.hl.lh", ICLASS_AE_MULASD32_HL_LH, + 0, + Opcode_ae_mulasd32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsafd32s.hh.ll", ICLASS_AE_MULSAFD32S_HH_LL, + 0, + Opcode_ae_mulsafd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsafd32ra.hh.ll", ICLASS_AE_MULSAFD32RA_HH_LL, + 0, + Opcode_ae_mulsafd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsad32.hh.ll", ICLASS_AE_MULSAD32_HH_LL, + 0, + Opcode_ae_mulsad32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssfd32s.hh.ll", ICLASS_AE_MULSSFD32S_HH_LL, + 0, + Opcode_ae_mulssfd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssfd32ra.hh.ll", ICLASS_AE_MULSSFD32RA_HH_LL, + 0, + Opcode_ae_mulssfd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssd32.hh.ll", ICLASS_AE_MULSSD32_HH_LL, + 0, + Opcode_ae_mulssd32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssfd32s.hl.lh", ICLASS_AE_MULSSFD32S_HL_LH, + 0, + Opcode_ae_mulssfd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssfd32ra.hl.lh", ICLASS_AE_MULSSFD32RA_HL_LH, + 0, + Opcode_ae_mulssfd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssd32.hl.lh", ICLASS_AE_MULSSD32_HL_LH, + 0, + Opcode_ae_mulssd32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulf32x16.l0", ICLASS_AE_MULF32X16_L0, + 0, + Opcode_ae_mulf32x16_l0_encode_fns, 0, 0 }, + { "ae_mul32x16.l0", ICLASS_AE_MUL32X16_L0, + 0, + Opcode_ae_mul32x16_l0_encode_fns, 0, 0 }, + { "ae_mulf32x16.l1", ICLASS_AE_MULF32X16_L1, + 0, + Opcode_ae_mulf32x16_l1_encode_fns, 0, 0 }, + { "ae_mul32x16.l1", ICLASS_AE_MUL32X16_L1, + 0, + Opcode_ae_mul32x16_l1_encode_fns, 0, 0 }, + { "ae_mulf32x16.l2", ICLASS_AE_MULF32X16_L2, + 0, + Opcode_ae_mulf32x16_l2_encode_fns, 0, 0 }, + { "ae_mul32x16.l2", ICLASS_AE_MUL32X16_L2, + 0, + Opcode_ae_mul32x16_l2_encode_fns, 0, 0 }, + { "ae_mulf32x16.l3", ICLASS_AE_MULF32X16_L3, + 0, + Opcode_ae_mulf32x16_l3_encode_fns, 0, 0 }, + { "ae_mul32x16.l3", ICLASS_AE_MUL32X16_L3, + 0, + Opcode_ae_mul32x16_l3_encode_fns, 0, 0 }, + { "ae_mulf32x16.h0", ICLASS_AE_MULF32X16_H0, + 0, + Opcode_ae_mulf32x16_h0_encode_fns, 0, 0 }, + { "ae_mul32x16.h0", ICLASS_AE_MUL32X16_H0, + 0, + Opcode_ae_mul32x16_h0_encode_fns, 0, 0 }, + { "ae_mulf32x16.h1", ICLASS_AE_MULF32X16_H1, + 0, + Opcode_ae_mulf32x16_h1_encode_fns, 0, 0 }, + { "ae_mul32x16.h1", ICLASS_AE_MUL32X16_H1, + 0, + Opcode_ae_mul32x16_h1_encode_fns, 0, 0 }, + { "ae_mulf32x16.h2", ICLASS_AE_MULF32X16_H2, + 0, + Opcode_ae_mulf32x16_h2_encode_fns, 0, 0 }, + { "ae_mul32x16.h2", ICLASS_AE_MUL32X16_H2, + 0, + Opcode_ae_mul32x16_h2_encode_fns, 0, 0 }, + { "ae_mulf32x16.h3", ICLASS_AE_MULF32X16_H3, + 0, + Opcode_ae_mulf32x16_h3_encode_fns, 0, 0 }, + { "ae_mul32x16.h3", ICLASS_AE_MUL32X16_H3, + 0, + Opcode_ae_mul32x16_h3_encode_fns, 0, 0 }, + { "ae_mulaf32x16.l0", ICLASS_AE_MULAF32X16_L0, + 0, + Opcode_ae_mulaf32x16_l0_encode_fns, 0, 0 }, + { "ae_mula32x16.l0", ICLASS_AE_MULA32X16_L0, + 0, + Opcode_ae_mula32x16_l0_encode_fns, 0, 0 }, + { "ae_mulaf32x16.l1", ICLASS_AE_MULAF32X16_L1, + 0, + Opcode_ae_mulaf32x16_l1_encode_fns, 0, 0 }, + { "ae_mula32x16.l1", ICLASS_AE_MULA32X16_L1, + 0, + Opcode_ae_mula32x16_l1_encode_fns, 0, 0 }, + { "ae_mulaf32x16.l2", ICLASS_AE_MULAF32X16_L2, + 0, + Opcode_ae_mulaf32x16_l2_encode_fns, 0, 0 }, + { "ae_mula32x16.l2", ICLASS_AE_MULA32X16_L2, + 0, + Opcode_ae_mula32x16_l2_encode_fns, 0, 0 }, + { "ae_mulaf32x16.l3", ICLASS_AE_MULAF32X16_L3, + 0, + Opcode_ae_mulaf32x16_l3_encode_fns, 0, 0 }, + { "ae_mula32x16.l3", ICLASS_AE_MULA32X16_L3, + 0, + Opcode_ae_mula32x16_l3_encode_fns, 0, 0 }, + { "ae_mulaf32x16.h0", ICLASS_AE_MULAF32X16_H0, + 0, + Opcode_ae_mulaf32x16_h0_encode_fns, 0, 0 }, + { "ae_mula32x16.h0", ICLASS_AE_MULA32X16_H0, + 0, + Opcode_ae_mula32x16_h0_encode_fns, 0, 0 }, + { "ae_mulaf32x16.h1", ICLASS_AE_MULAF32X16_H1, + 0, + Opcode_ae_mulaf32x16_h1_encode_fns, 0, 0 }, + { "ae_mula32x16.h1", ICLASS_AE_MULA32X16_H1, + 0, + Opcode_ae_mula32x16_h1_encode_fns, 0, 0 }, + { "ae_mulaf32x16.h2", ICLASS_AE_MULAF32X16_H2, + 0, + Opcode_ae_mulaf32x16_h2_encode_fns, 0, 0 }, + { "ae_mula32x16.h2", ICLASS_AE_MULA32X16_H2, + 0, + Opcode_ae_mula32x16_h2_encode_fns, 0, 0 }, + { "ae_mulaf32x16.h3", ICLASS_AE_MULAF32X16_H3, + 0, + Opcode_ae_mulaf32x16_h3_encode_fns, 0, 0 }, + { "ae_mula32x16.h3", ICLASS_AE_MULA32X16_H3, + 0, + Opcode_ae_mula32x16_h3_encode_fns, 0, 0 }, + { "ae_mulsf32x16.l0", ICLASS_AE_MULSF32X16_L0, + 0, + Opcode_ae_mulsf32x16_l0_encode_fns, 0, 0 }, + { "ae_muls32x16.l0", ICLASS_AE_MULS32X16_L0, + 0, + Opcode_ae_muls32x16_l0_encode_fns, 0, 0 }, + { "ae_mulsf32x16.l1", ICLASS_AE_MULSF32X16_L1, + 0, + Opcode_ae_mulsf32x16_l1_encode_fns, 0, 0 }, + { "ae_muls32x16.l1", ICLASS_AE_MULS32X16_L1, + 0, + Opcode_ae_muls32x16_l1_encode_fns, 0, 0 }, + { "ae_mulsf32x16.l2", ICLASS_AE_MULSF32X16_L2, + 0, + Opcode_ae_mulsf32x16_l2_encode_fns, 0, 0 }, + { "ae_muls32x16.l2", ICLASS_AE_MULS32X16_L2, + 0, + Opcode_ae_muls32x16_l2_encode_fns, 0, 0 }, + { "ae_mulsf32x16.l3", ICLASS_AE_MULSF32X16_L3, + 0, + Opcode_ae_mulsf32x16_l3_encode_fns, 0, 0 }, + { "ae_muls32x16.l3", ICLASS_AE_MULS32X16_L3, + 0, + Opcode_ae_muls32x16_l3_encode_fns, 0, 0 }, + { "ae_mulsf32x16.h0", ICLASS_AE_MULSF32X16_H0, + 0, + Opcode_ae_mulsf32x16_h0_encode_fns, 0, 0 }, + { "ae_muls32x16.h0", ICLASS_AE_MULS32X16_H0, + 0, + Opcode_ae_muls32x16_h0_encode_fns, 0, 0 }, + { "ae_mulsf32x16.h1", ICLASS_AE_MULSF32X16_H1, + 0, + Opcode_ae_mulsf32x16_h1_encode_fns, 0, 0 }, + { "ae_muls32x16.h1", ICLASS_AE_MULS32X16_H1, + 0, + Opcode_ae_muls32x16_h1_encode_fns, 0, 0 }, + { "ae_mulsf32x16.h2", ICLASS_AE_MULSF32X16_H2, + 0, + Opcode_ae_mulsf32x16_h2_encode_fns, 0, 0 }, + { "ae_muls32x16.h2", ICLASS_AE_MULS32X16_H2, + 0, + Opcode_ae_muls32x16_h2_encode_fns, 0, 0 }, + { "ae_mulsf32x16.h3", ICLASS_AE_MULSF32X16_H3, + 0, + Opcode_ae_mulsf32x16_h3_encode_fns, 0, 0 }, + { "ae_muls32x16.h3", ICLASS_AE_MULS32X16_H3, + 0, + Opcode_ae_muls32x16_h3_encode_fns, 0, 0 }, + { "ae_mulaafd32x16.h3.l2", ICLASS_AE_MULAAFD32X16_H3_L2, + 0, + Opcode_ae_mulaafd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulaad32x16.h3.l2", ICLASS_AE_MULAAD32X16_H3_L2, + 0, + Opcode_ae_mulaad32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulaafd32x16.h1.l0", ICLASS_AE_MULAAFD32X16_H1_L0, + 0, + Opcode_ae_mulaafd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulaad32x16.h1.l0", ICLASS_AE_MULAAD32X16_H1_L0, + 0, + Opcode_ae_mulaad32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulasfd32x16.h3.l2", ICLASS_AE_MULASFD32X16_H3_L2, + 0, + Opcode_ae_mulasfd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulasd32x16.h3.l2", ICLASS_AE_MULASD32X16_H3_L2, + 0, + Opcode_ae_mulasd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulasfd32x16.h1.l0", ICLASS_AE_MULASFD32X16_H1_L0, + 0, + Opcode_ae_mulasfd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulasd32x16.h1.l0", ICLASS_AE_MULASD32X16_H1_L0, + 0, + Opcode_ae_mulasd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulsafd32x16.h3.l2", ICLASS_AE_MULSAFD32X16_H3_L2, + 0, + Opcode_ae_mulsafd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulsad32x16.h3.l2", ICLASS_AE_MULSAD32X16_H3_L2, + 0, + Opcode_ae_mulsad32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulsafd32x16.h1.l0", ICLASS_AE_MULSAFD32X16_H1_L0, + 0, + Opcode_ae_mulsafd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulsad32x16.h1.l0", ICLASS_AE_MULSAD32X16_H1_L0, + 0, + Opcode_ae_mulsad32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulssfd32x16.h3.l2", ICLASS_AE_MULSSFD32X16_H3_L2, + 0, + Opcode_ae_mulssfd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulssd32x16.h3.l2", ICLASS_AE_MULSSD32X16_H3_L2, + 0, + Opcode_ae_mulssd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulssfd32x16.h1.l0", ICLASS_AE_MULSSFD32X16_H1_L0, + 0, + Opcode_ae_mulssfd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulssd32x16.h1.l0", ICLASS_AE_MULSSD32X16_H1_L0, + 0, + Opcode_ae_mulssd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzaafd32x16.h3.l2", ICLASS_AE_MULZAAFD32X16_H3_L2, + 0, + Opcode_ae_mulzaafd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzaad32x16.h3.l2", ICLASS_AE_MULZAAD32X16_H3_L2, + 0, + Opcode_ae_mulzaad32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzaafd32x16.h1.l0", ICLASS_AE_MULZAAFD32X16_H1_L0, + 0, + Opcode_ae_mulzaafd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzaad32x16.h1.l0", ICLASS_AE_MULZAAD32X16_H1_L0, + 0, + Opcode_ae_mulzaad32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzasfd32x16.h3.l2", ICLASS_AE_MULZASFD32X16_H3_L2, + 0, + Opcode_ae_mulzasfd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzasd32x16.h3.l2", ICLASS_AE_MULZASD32X16_H3_L2, + 0, + Opcode_ae_mulzasd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzasfd32x16.h1.l0", ICLASS_AE_MULZASFD32X16_H1_L0, + 0, + Opcode_ae_mulzasfd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzasd32x16.h1.l0", ICLASS_AE_MULZASD32X16_H1_L0, + 0, + Opcode_ae_mulzasd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzsafd32x16.h3.l2", ICLASS_AE_MULZSAFD32X16_H3_L2, + 0, + Opcode_ae_mulzsafd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzsad32x16.h3.l2", ICLASS_AE_MULZSAD32X16_H3_L2, + 0, + Opcode_ae_mulzsad32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzsafd32x16.h1.l0", ICLASS_AE_MULZSAFD32X16_H1_L0, + 0, + Opcode_ae_mulzsafd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzsad32x16.h1.l0", ICLASS_AE_MULZSAD32X16_H1_L0, + 0, + Opcode_ae_mulzsad32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzssfd32x16.h3.l2", ICLASS_AE_MULZSSFD32X16_H3_L2, + 0, + Opcode_ae_mulzssfd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzssd32x16.h3.l2", ICLASS_AE_MULZSSD32X16_H3_L2, + 0, + Opcode_ae_mulzssd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzssfd32x16.h1.l0", ICLASS_AE_MULZSSFD32X16_H1_L0, + 0, + Opcode_ae_mulzssfd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzssd32x16.h1.l0", ICLASS_AE_MULZSSD32X16_H1_L0, + 0, + Opcode_ae_mulzssd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzaafd32x16.h2.l3", ICLASS_AE_MULZAAFD32X16_H2_L3, + 0, + Opcode_ae_mulzaafd32x16_h2_l3_encode_fns, 0, 0 }, + { "ae_mulzaafd32x16.h0.l1", ICLASS_AE_MULZAAFD32X16_H0_L1, + 0, + Opcode_ae_mulzaafd32x16_h0_l1_encode_fns, 0, 0 }, + { "ae_mulaafd32x16.h2.l3", ICLASS_AE_MULAAFD32X16_H2_L3, + 0, + Opcode_ae_mulaafd32x16_h2_l3_encode_fns, 0, 0 }, + { "ae_mulaafd32x16.h0.l1", ICLASS_AE_MULAAFD32X16_H0_L1, + 0, + Opcode_ae_mulaafd32x16_h0_l1_encode_fns, 0, 0 }, + { "ae_mulzaad32x16.h2.l3", ICLASS_AE_MULZAAD32X16_H2_L3, + 0, + Opcode_ae_mulzaad32x16_h2_l3_encode_fns, 0, 0 }, + { "ae_mulzaad32x16.h0.l1", ICLASS_AE_MULZAAD32X16_H0_L1, + 0, + Opcode_ae_mulzaad32x16_h0_l1_encode_fns, 0, 0 }, + { "ae_mulaad32x16.h2.l3", ICLASS_AE_MULAAD32X16_H2_L3, + 0, + Opcode_ae_mulaad32x16_h2_l3_encode_fns, 0, 0 }, + { "ae_mulaad32x16.h0.l1", ICLASS_AE_MULAAD32X16_H0_L1, + 0, + Opcode_ae_mulaad32x16_h0_l1_encode_fns, 0, 0 }, + { "ae_mulp32x16x2.h", ICLASS_AE_MULP32X16X2_H, + 0, + Opcode_ae_mulp32x16x2_h_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2rs.h", ICLASS_AE_MULFP32X16X2RS_H, + 0, + Opcode_ae_mulfp32x16x2rs_h_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2ras.h", ICLASS_AE_MULFP32X16X2RAS_H, + 0, + Opcode_ae_mulfp32x16x2ras_h_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2s.h", ICLASS_AE_MULFP32X16X2S_H, + 0, + Opcode_ae_mulfp32x16x2s_h_encode_fns, 0, 0 }, + { "ae_mulp32x16x2.l", ICLASS_AE_MULP32X16X2_L, + 0, + Opcode_ae_mulp32x16x2_l_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2rs.l", ICLASS_AE_MULFP32X16X2RS_L, + 0, + Opcode_ae_mulfp32x16x2rs_l_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2ras.l", ICLASS_AE_MULFP32X16X2RAS_L, + 0, + Opcode_ae_mulfp32x16x2ras_l_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2s.l", ICLASS_AE_MULFP32X16X2S_L, + 0, + Opcode_ae_mulfp32x16x2s_l_encode_fns, 0, 0 }, + { "ae_mulap32x16x2.h", ICLASS_AE_MULAP32X16X2_H, + 0, + Opcode_ae_mulap32x16x2_h_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2rs.h", ICLASS_AE_MULAFP32X16X2RS_H, + 0, + Opcode_ae_mulafp32x16x2rs_h_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2ras.h", ICLASS_AE_MULAFP32X16X2RAS_H, + 0, + Opcode_ae_mulafp32x16x2ras_h_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2s.h", ICLASS_AE_MULAFP32X16X2S_H, + 0, + Opcode_ae_mulafp32x16x2s_h_encode_fns, 0, 0 }, + { "ae_mulap32x16x2.l", ICLASS_AE_MULAP32X16X2_L, + 0, + Opcode_ae_mulap32x16x2_l_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2rs.l", ICLASS_AE_MULAFP32X16X2RS_L, + 0, + Opcode_ae_mulafp32x16x2rs_l_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2ras.l", ICLASS_AE_MULAFP32X16X2RAS_L, + 0, + Opcode_ae_mulafp32x16x2ras_l_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2s.l", ICLASS_AE_MULAFP32X16X2S_L, + 0, + Opcode_ae_mulafp32x16x2s_l_encode_fns, 0, 0 }, + { "ae_mulsp32x16x2.h", ICLASS_AE_MULSP32X16X2_H, + 0, + Opcode_ae_mulsp32x16x2_h_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2rs.h", ICLASS_AE_MULSFP32X16X2RS_H, + 0, + Opcode_ae_mulsfp32x16x2rs_h_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2ras.h", ICLASS_AE_MULSFP32X16X2RAS_H, + 0, + Opcode_ae_mulsfp32x16x2ras_h_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2s.h", ICLASS_AE_MULSFP32X16X2S_H, + 0, + Opcode_ae_mulsfp32x16x2s_h_encode_fns, 0, 0 }, + { "ae_mulsp32x16x2.l", ICLASS_AE_MULSP32X16X2_L, + 0, + Opcode_ae_mulsp32x16x2_l_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2rs.l", ICLASS_AE_MULSFP32X16X2RS_L, + 0, + Opcode_ae_mulsfp32x16x2rs_l_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2ras.l", ICLASS_AE_MULSFP32X16X2RAS_L, + 0, + Opcode_ae_mulsfp32x16x2ras_l_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2s.l", ICLASS_AE_MULSFP32X16X2S_L, + 0, + Opcode_ae_mulsfp32x16x2s_l_encode_fns, 0, 0 }, + { "ae_mulp32x2", ICLASS_AE_MULP32X2, + 0, + Opcode_ae_mulp32x2_encode_fns, 0, 0 }, + { "ae_mulfp32x2rs", ICLASS_AE_MULFP32X2RS, + 0, + Opcode_ae_mulfp32x2rs_encode_fns, 0, 0 }, + { "ae_mulfp32x2ras", ICLASS_AE_MULFP32X2RAS, + 0, + Opcode_ae_mulfp32x2ras_encode_fns, 0, 0 }, + { "ae_mulfp32x2ts", ICLASS_AE_MULFP32X2TS, + 0, + Opcode_ae_mulfp32x2ts_encode_fns, 0, 0 }, + { "ae_mulp32x2t", ICLASS_AE_MULP32X2T, + 0, + Opcode_ae_mulp32x2t_encode_fns, 0, 0 }, + { "ae_mulap32x2", ICLASS_AE_MULAP32X2, + 0, + Opcode_ae_mulap32x2_encode_fns, 0, 0 }, + { "ae_mulafp32x2rs", ICLASS_AE_MULAFP32X2RS, + 0, + Opcode_ae_mulafp32x2rs_encode_fns, 0, 0 }, + { "ae_mulafp32x2ras", ICLASS_AE_MULAFP32X2RAS, + 0, + Opcode_ae_mulafp32x2ras_encode_fns, 0, 0 }, + { "ae_mulafp32x2ts", ICLASS_AE_MULAFP32X2TS, + 0, + Opcode_ae_mulafp32x2ts_encode_fns, 0, 0 }, + { "ae_mulap32x2t", ICLASS_AE_MULAP32X2T, + 0, + Opcode_ae_mulap32x2t_encode_fns, 0, 0 }, + { "ae_mulsp32x2", ICLASS_AE_MULSP32X2, + 0, + Opcode_ae_mulsp32x2_encode_fns, 0, 0 }, + { "ae_mulsfp32x2rs", ICLASS_AE_MULSFP32X2RS, + 0, + Opcode_ae_mulsfp32x2rs_encode_fns, 0, 0 }, + { "ae_mulsfp32x2ras", ICLASS_AE_MULSFP32X2RAS, + 0, + Opcode_ae_mulsfp32x2ras_encode_fns, 0, 0 }, + { "ae_mulsfp32x2ts", ICLASS_AE_MULSFP32X2TS, + 0, + Opcode_ae_mulsfp32x2ts_encode_fns, 0, 0 }, + { "ae_mulsp32x2t", ICLASS_AE_MULSP32X2T, + 0, + Opcode_ae_mulsp32x2t_encode_fns, 0, 0 }, + { "ae_mulfp16x4s", ICLASS_AE_MULFP16X4S, + 0, + Opcode_ae_mulfp16x4s_encode_fns, 0, 0 }, + { "ae_mulfp16x4ras", ICLASS_AE_MULFP16X4RAS, + 0, + Opcode_ae_mulfp16x4ras_encode_fns, 0, 0 }, + { "ae_mulc32", ICLASS_AE_MULC32, + 0, + Opcode_ae_mulc32_encode_fns, 0, 0 }, + { "ae_mulfc24ra", ICLASS_AE_MULFC24RA, + 0, + Opcode_ae_mulfc24ra_encode_fns, 0, 0 }, + { "ae_mulfc32ras", ICLASS_AE_MULFC32RAS, + 0, + Opcode_ae_mulfc32ras_encode_fns, 0, 0 }, + { "ae_mulc32x16.l", ICLASS_AE_MULC32X16_L, + 0, + Opcode_ae_mulc32x16_l_encode_fns, 0, 0 }, + { "ae_mulfc32x16ras.l", ICLASS_AE_MULFC32X16RAS_L, + 0, + Opcode_ae_mulfc32x16ras_l_encode_fns, 0, 0 }, + { "ae_mulc32x16.h", ICLASS_AE_MULC32X16_H, + 0, + Opcode_ae_mulc32x16_h_encode_fns, 0, 0 }, + { "ae_mulfc32x16ras.h", ICLASS_AE_MULFC32X16RAS_H, + 0, + Opcode_ae_mulfc32x16ras_h_encode_fns, 0, 0 }, + { "ae_mulac32", ICLASS_AE_MULAC32, + 0, + Opcode_ae_mulac32_encode_fns, 0, 0 }, + { "ae_mulafc24ra", ICLASS_AE_MULAFC24RA, + 0, + Opcode_ae_mulafc24ra_encode_fns, 0, 0 }, + { "ae_mulafc32ras", ICLASS_AE_MULAFC32RAS, + 0, + Opcode_ae_mulafc32ras_encode_fns, 0, 0 }, + { "ae_mulac32x16.l", ICLASS_AE_MULAC32X16_L, + 0, + Opcode_ae_mulac32x16_l_encode_fns, 0, 0 }, + { "ae_mulafc32x16ras.l", ICLASS_AE_MULAFC32X16RAS_L, + 0, + Opcode_ae_mulafc32x16ras_l_encode_fns, 0, 0 }, + { "ae_mulac32x16.h", ICLASS_AE_MULAC32X16_H, + 0, + Opcode_ae_mulac32x16_h_encode_fns, 0, 0 }, + { "ae_mulafc32x16ras.h", ICLASS_AE_MULAFC32X16RAS_H, + 0, + Opcode_ae_mulafc32x16ras_h_encode_fns, 0, 0 }, + { "ae_mulf16x4ss", ICLASS_AE_MULF16X4SS, + 0, + Opcode_ae_mulf16x4ss_encode_fns, 0, 0 }, + { "ae_mulaf16x4ss", ICLASS_AE_MULAF16X4SS, + 0, + Opcode_ae_mulaf16x4ss_encode_fns, 0, 0 }, + { "ae_mulsf16x4ss", ICLASS_AE_MULSF16X4SS, + 0, + Opcode_ae_mulsf16x4ss_encode_fns, 0, 0 }, + { "ae_mul16x4s", ICLASS_AE_MUL16X4S, + 0, + Opcode_ae_mul16x4s_encode_fns, 0, 0 }, + { "ae_mula16x4s", ICLASS_AE_MULA16X4S, + 0, + Opcode_ae_mula16x4s_encode_fns, 0, 0 }, + { "ae_muls16x4s", ICLASS_AE_MULS16X4S, + 0, + Opcode_ae_muls16x4s_encode_fns, 0, 0 }, + { "ae_mul16x4", ICLASS_AE_MUL16X4, + 0, + Opcode_ae_mul16x4_encode_fns, 0, 0 }, + { "ae_mula16x4", ICLASS_AE_MULA16X4, + 0, + Opcode_ae_mula16x4_encode_fns, 0, 0 }, + { "ae_muls16x4", ICLASS_AE_MULS16X4, + 0, + Opcode_ae_muls16x4_encode_fns, 0, 0 }, + { "ae_mulfd32x2s.fir.h", ICLASS_AE_MULFD32X2S_FIR_H, + 0, + Opcode_ae_mulfd32x2s_fir_h_encode_fns, 0, 0 }, + { "ae_mulfd32x2ra.fir.h", ICLASS_AE_MULFD32X2RA_FIR_H, + 0, + Opcode_ae_mulfd32x2ra_fir_h_encode_fns, 0, 0 }, + { "ae_mulfd32x2s.fir.l", ICLASS_AE_MULFD32X2S_FIR_L, + 0, + Opcode_ae_mulfd32x2s_fir_l_encode_fns, 0, 0 }, + { "ae_mulfd32x2ra.fir.l", ICLASS_AE_MULFD32X2RA_FIR_L, + 0, + Opcode_ae_mulfd32x2ra_fir_l_encode_fns, 0, 0 }, + { "ae_mulfd32x16x2.fir.hh", ICLASS_AE_MULFD32X16X2_FIR_HH, + 0, + Opcode_ae_mulfd32x16x2_fir_hh_encode_fns, 0, 0 }, + { "ae_mulfd32x16x2.fir.hl", ICLASS_AE_MULFD32X16X2_FIR_HL, + 0, + Opcode_ae_mulfd32x16x2_fir_hl_encode_fns, 0, 0 }, + { "ae_mulfd32x16x2.fir.lh", ICLASS_AE_MULFD32X16X2_FIR_LH, + 0, + Opcode_ae_mulfd32x16x2_fir_lh_encode_fns, 0, 0 }, + { "ae_mulfd32x16x2.fir.ll", ICLASS_AE_MULFD32X16X2_FIR_LL, + 0, + Opcode_ae_mulfd32x16x2_fir_ll_encode_fns, 0, 0 }, + { "ae_mulafd32x2s.fir.h", ICLASS_AE_MULAFD32X2S_FIR_H, + 0, + Opcode_ae_mulafd32x2s_fir_h_encode_fns, 0, 0 }, + { "ae_mulafd32x2ra.fir.h", ICLASS_AE_MULAFD32X2RA_FIR_H, + 0, + Opcode_ae_mulafd32x2ra_fir_h_encode_fns, 0, 0 }, + { "ae_mulafd32x2s.fir.l", ICLASS_AE_MULAFD32X2S_FIR_L, + 0, + Opcode_ae_mulafd32x2s_fir_l_encode_fns, 0, 0 }, + { "ae_mulafd32x2ra.fir.l", ICLASS_AE_MULAFD32X2RA_FIR_L, + 0, + Opcode_ae_mulafd32x2ra_fir_l_encode_fns, 0, 0 }, + { "ae_mulafd32x16x2.fir.hh", ICLASS_AE_MULAFD32X16X2_FIR_HH, + 0, + Opcode_ae_mulafd32x16x2_fir_hh_encode_fns, 0, 0 }, + { "ae_mulafd32x16x2.fir.hl", ICLASS_AE_MULAFD32X16X2_FIR_HL, + 0, + Opcode_ae_mulafd32x16x2_fir_hl_encode_fns, 0, 0 }, + { "ae_mulafd32x16x2.fir.lh", ICLASS_AE_MULAFD32X16X2_FIR_LH, + 0, + Opcode_ae_mulafd32x16x2_fir_lh_encode_fns, 0, 0 }, + { "ae_mulafd32x16x2.fir.ll", ICLASS_AE_MULAFD32X16X2_FIR_LL, + 0, + Opcode_ae_mulafd32x16x2_fir_ll_encode_fns, 0, 0 }, + { "ae_mulc16s.h", ICLASS_AE_MULC16S_H, + 0, + Opcode_ae_mulc16s_h_encode_fns, 0, 0 }, + { "ae_mulc16s.l", ICLASS_AE_MULC16S_L, + 0, + Opcode_ae_mulc16s_l_encode_fns, 0, 0 }, + { "ae_mulac16s.h", ICLASS_AE_MULAC16S_H, + 0, + Opcode_ae_mulac16s_h_encode_fns, 0, 0 }, + { "ae_mulac16s.l", ICLASS_AE_MULAC16S_L, + 0, + Opcode_ae_mulac16s_l_encode_fns, 0, 0 }, + { "ae_mulfc16ras", ICLASS_AE_MULFC16RAS, + 0, + Opcode_ae_mulfc16ras_encode_fns, 0, 0 }, + { "ae_mulafc16ras", ICLASS_AE_MULAFC16RAS, + 0, + Opcode_ae_mulafc16ras_encode_fns, 0, 0 }, + { "ae_mul16js", ICLASS_AE_MUL16JS, + 0, + Opcode_ae_mul16js_encode_fns, 0, 0 }, + { "ae_addandsubrng16ras_s1", ICLASS_AE_ADDANDSUBRNG16RAS_S1, + 0, + Opcode_ae_addandsubrng16ras_s1_encode_fns, 0, 0 }, + { "ae_addandsubrng16ras_s2", ICLASS_AE_ADDANDSUBRNG16RAS_S2, + 0, + Opcode_ae_addandsubrng16ras_s2_encode_fns, 0, 0 }, + { "ae_conj16s", ICLASS_AE_CONJ16S, + 0, + Opcode_ae_conj16s_encode_fns, 0, 0 }, + { "ae_mulfq16x2.fir.3", ICLASS_AE_MULFQ16X2_FIR_3, + 0, + Opcode_ae_mulfq16x2_fir_3_encode_fns, 0, 0 }, + { "ae_mulfq16x2.fir.2", ICLASS_AE_MULFQ16X2_FIR_2, + 0, + Opcode_ae_mulfq16x2_fir_2_encode_fns, 0, 0 }, + { "ae_mulfq16x2.fir.1", ICLASS_AE_MULFQ16X2_FIR_1, + 0, + Opcode_ae_mulfq16x2_fir_1_encode_fns, 0, 0 }, + { "ae_mulfq16x2.fir.0", ICLASS_AE_MULFQ16X2_FIR_0, + 0, + Opcode_ae_mulfq16x2_fir_0_encode_fns, 0, 0 }, + { "ae_mulafq16x2.fir.3", ICLASS_AE_MULAFQ16X2_FIR_3, + 0, + Opcode_ae_mulafq16x2_fir_3_encode_fns, 0, 0 }, + { "ae_mulafq16x2.fir.2", ICLASS_AE_MULAFQ16X2_FIR_2, + 0, + Opcode_ae_mulafq16x2_fir_2_encode_fns, 0, 0 }, + { "ae_mulafq16x2.fir.1", ICLASS_AE_MULAFQ16X2_FIR_1, + 0, + Opcode_ae_mulafq16x2_fir_1_encode_fns, 0, 0 }, + { "ae_mulafq16x2.fir.0", ICLASS_AE_MULAFQ16X2_FIR_0, + 0, + Opcode_ae_mulafq16x2_fir_0_encode_fns, 0, 0 }, + { "ae_mulzaaaafq32x16", ICLASS_AE_MULZAAAAFQ32X16, + 0, + Opcode_ae_mulzaaaafq32x16_encode_fns, 0, 0 }, + { "ae_mulaaaafq32x16", ICLASS_AE_MULAAAAFQ32X16, + 0, + Opcode_ae_mulaaaafq32x16_encode_fns, 0, 0 }, + { "ae_mulzaaaaq32x16", ICLASS_AE_MULZAAAAQ32X16, + 0, + Opcode_ae_mulzaaaaq32x16_encode_fns, 0, 0 }, + { "ae_mulaaaaq32x16", ICLASS_AE_MULAAAAQ32X16, + 0, + Opcode_ae_mulaaaaq32x16_encode_fns, 0, 0 }, + { "ae_mul16.00", ICLASS_AE_MUL16_00, + 0, + Opcode_ae_mul16_00_encode_fns, 0, 0 }, + { "ae_mula16.00", ICLASS_AE_MULA16_00, + 0, + Opcode_ae_mula16_00_encode_fns, 0, 0 }, + { "ae_mulzaaaaq16", ICLASS_AE_MULZAAAAQ16, + 0, + Opcode_ae_mulzaaaaq16_encode_fns, 0, 0 }, + { "ae_mulaaaaq16", ICLASS_AE_MULAAAAQ16, + 0, + Opcode_ae_mulaaaaq16_encode_fns, 0, 0 }, + { "ae_div64d32.h", ICLASS_AE_DIV64D32_H, + 0, + Opcode_ae_div64d32_h_encode_fns, 0, 0 }, + { "ae_div64d32.l", ICLASS_AE_DIV64D32_L, + 0, + Opcode_ae_div64d32_l_encode_fns, 0, 0 }, + { "ae_sha32", ICLASS_AE_SHA32, + 0, + Opcode_ae_sha32_encode_fns, 0, 0 }, + { "ae_vldl32t", ICLASS_AE_VLDL32T, + 0, + Opcode_ae_vldl32t_encode_fns, 2, Opcode_ae_vldl32t_funcUnit_uses }, + { "ae_vldl16t", ICLASS_AE_VLDL16T, + 0, + Opcode_ae_vldl16t_encode_fns, 2, Opcode_ae_vldl16t_funcUnit_uses }, + { "ae_vldl16c", ICLASS_AE_VLDL16C, + 0, + Opcode_ae_vldl16c_encode_fns, 4, Opcode_ae_vldl16c_funcUnit_uses }, + { "ae_vldl16c.ip", ICLASS_AE_VLDL16C_IP, + 0, + Opcode_ae_vldl16c_ip_encode_fns, 4, Opcode_ae_vldl16c_ip_funcUnit_uses }, + { "ae_vldl16c.ic", ICLASS_AE_VLDL16C_IC, + 0, + Opcode_ae_vldl16c_ic_encode_fns, 4, Opcode_ae_vldl16c_ic_funcUnit_uses }, + { "ae_vldl16c.ic1", ICLASS_AE_VLDL16C_IC1, + 0, + Opcode_ae_vldl16c_ic1_encode_fns, 4, Opcode_ae_vldl16c_ic1_funcUnit_uses }, + { "ae_vldsht", ICLASS_AE_VLDSHT, + 0, + Opcode_ae_vldsht_encode_fns, 3, Opcode_ae_vldsht_funcUnit_uses }, + { "ae_lb", ICLASS_AE_LB, + 0, + Opcode_ae_lb_encode_fns, 1, Opcode_ae_lb_funcUnit_uses }, + { "ae_lbi", ICLASS_AE_LBI, + 0, + Opcode_ae_lbi_encode_fns, 1, Opcode_ae_lbi_funcUnit_uses }, + { "ae_lbk", ICLASS_AE_LBK, + 0, + Opcode_ae_lbk_encode_fns, 1, Opcode_ae_lbk_funcUnit_uses }, + { "ae_lbki", ICLASS_AE_LBKI, + 0, + Opcode_ae_lbki_encode_fns, 1, Opcode_ae_lbki_funcUnit_uses }, + { "ae_lbs", ICLASS_AE_LBS, + 0, + Opcode_ae_lbs_encode_fns, 1, Opcode_ae_lbs_funcUnit_uses }, + { "ae_lbsi", ICLASS_AE_LBSI, + 0, + Opcode_ae_lbsi_encode_fns, 1, Opcode_ae_lbsi_funcUnit_uses }, + { "ae_db", ICLASS_AE_DB, + 0, + Opcode_ae_db_encode_fns, 3, Opcode_ae_db_funcUnit_uses }, + { "ae_dbi", ICLASS_AE_DBI, + 0, + Opcode_ae_dbi_encode_fns, 3, Opcode_ae_dbi_funcUnit_uses }, + { "ae_db.ic", ICLASS_AE_DB_IC, + 0, + Opcode_ae_db_ic_encode_fns, 3, Opcode_ae_db_ic_funcUnit_uses }, + { "ae_dbi.ic", ICLASS_AE_DBI_IC, + 0, + Opcode_ae_dbi_ic_encode_fns, 3, Opcode_ae_dbi_ic_funcUnit_uses }, + { "ae_db.ic1", ICLASS_AE_DB_IC1, + 0, + Opcode_ae_db_ic1_encode_fns, 3, Opcode_ae_db_ic1_funcUnit_uses }, + { "ae_dbi.ic1", ICLASS_AE_DBI_IC1, + 0, + Opcode_ae_dbi_ic1_encode_fns, 3, Opcode_ae_dbi_ic1_funcUnit_uses }, + { "ae_db.ip", ICLASS_AE_DB_IP, + 0, + Opcode_ae_db_ip_encode_fns, 3, Opcode_ae_db_ip_funcUnit_uses }, + { "ae_dbi.ip", ICLASS_AE_DBI_IP, + 0, + Opcode_ae_dbi_ip_encode_fns, 3, Opcode_ae_dbi_ip_funcUnit_uses }, + { "ae_ardecnorm16", ICLASS_AE_ARDECNORM16, + 0, + Opcode_ae_ardecnorm16_encode_fns, 0, 0 }, + { "ae_lbki_dbi.ic", ICLASS_AE_LBKI_DBI_IC, + 0, + Opcode_ae_lbki_dbi_ic_encode_fns, 1, Opcode_ae_lbki_dbi_ic_funcUnit_uses }, + { "ae_lbki_dbi.ip", ICLASS_AE_LBKI_DBI_IP, + 0, + Opcode_ae_lbki_dbi_ip_encode_fns, 1, Opcode_ae_lbki_dbi_ip_funcUnit_uses }, + { "ae_lbki_dbi", ICLASS_AE_LBKI_DBI, + 0, + Opcode_ae_lbki_dbi_encode_fns, 1, Opcode_ae_lbki_dbi_funcUnit_uses }, + { "ae_lbi_dbi.ic", ICLASS_AE_LBI_DBI_IC, + 0, + Opcode_ae_lbi_dbi_ic_encode_fns, 1, Opcode_ae_lbi_dbi_ic_funcUnit_uses }, + { "ae_lbi_dbi.ip", ICLASS_AE_LBI_DBI_IP, + 0, + Opcode_ae_lbi_dbi_ip_encode_fns, 1, Opcode_ae_lbi_dbi_ip_funcUnit_uses }, + { "ae_lbi_dbi", ICLASS_AE_LBI_DBI, + 0, + Opcode_ae_lbi_dbi_encode_fns, 1, Opcode_ae_lbi_dbi_funcUnit_uses }, + { "ae_lbk_db.ic", ICLASS_AE_LBK_DB_IC, + 0, + Opcode_ae_lbk_db_ic_encode_fns, 1, Opcode_ae_lbk_db_ic_funcUnit_uses }, + { "ae_lbk_db.ip", ICLASS_AE_LBK_DB_IP, + 0, + Opcode_ae_lbk_db_ip_encode_fns, 1, Opcode_ae_lbk_db_ip_funcUnit_uses }, + { "ae_lbk_db", ICLASS_AE_LBK_DB, + 0, + Opcode_ae_lbk_db_encode_fns, 1, Opcode_ae_lbk_db_funcUnit_uses }, + { "ae_lb_db.ic", ICLASS_AE_LB_DB_IC, + 0, + Opcode_ae_lb_db_ic_encode_fns, 1, Opcode_ae_lb_db_ic_funcUnit_uses }, + { "ae_lb_db.ip", ICLASS_AE_LB_DB_IP, + 0, + Opcode_ae_lb_db_ip_encode_fns, 1, Opcode_ae_lb_db_ip_funcUnit_uses }, + { "ae_lb_db", ICLASS_AE_LB_DB, + 0, + Opcode_ae_lb_db_encode_fns, 1, Opcode_ae_lb_db_funcUnit_uses }, + { "ae_vlel32t", ICLASS_AE_VLEL32T, + 0, + Opcode_ae_vlel32t_encode_fns, 2, Opcode_ae_vlel32t_funcUnit_uses }, + { "ae_vlel16t", ICLASS_AE_VLEL16T, + 0, + Opcode_ae_vlel16t_encode_fns, 2, Opcode_ae_vlel16t_funcUnit_uses }, + { "ae_sb", ICLASS_AE_SB, + 0, + Opcode_ae_sb_encode_fns, 3, Opcode_ae_sb_funcUnit_uses }, + { "ae_sbi", ICLASS_AE_SBI, + 0, + Opcode_ae_sbi_encode_fns, 3, Opcode_ae_sbi_funcUnit_uses }, + { "ae_vles16c", ICLASS_AE_VLES16C, + 0, + Opcode_ae_vles16c_encode_fns, 3, Opcode_ae_vles16c_funcUnit_uses }, + { "ae_sbf", ICLASS_AE_SBF, + 0, + Opcode_ae_sbf_encode_fns, 3, Opcode_ae_sbf_funcUnit_uses }, + { "ae_sb.ic", ICLASS_AE_SB_IC, + 0, + Opcode_ae_sb_ic_encode_fns, 3, Opcode_ae_sb_ic_funcUnit_uses }, + { "ae_sbi.ic", ICLASS_AE_SBI_IC, + 0, + Opcode_ae_sbi_ic_encode_fns, 3, Opcode_ae_sbi_ic_funcUnit_uses }, + { "ae_vles16c.ic", ICLASS_AE_VLES16C_IC, + 0, + Opcode_ae_vles16c_ic_encode_fns, 3, Opcode_ae_vles16c_ic_funcUnit_uses }, + { "ae_sbf.ic", ICLASS_AE_SBF_IC, + 0, + Opcode_ae_sbf_ic_encode_fns, 3, Opcode_ae_sbf_ic_funcUnit_uses }, + { "ae_sb.ic1", ICLASS_AE_SB_IC1, + 0, + Opcode_ae_sb_ic1_encode_fns, 3, Opcode_ae_sb_ic1_funcUnit_uses }, + { "ae_sbi.ic1", ICLASS_AE_SBI_IC1, + 0, + Opcode_ae_sbi_ic1_encode_fns, 3, Opcode_ae_sbi_ic1_funcUnit_uses }, + { "ae_vles16c.ic1", ICLASS_AE_VLES16C_IC1, + 0, + Opcode_ae_vles16c_ic1_encode_fns, 3, Opcode_ae_vles16c_ic1_funcUnit_uses }, + { "ae_sbf.ic1", ICLASS_AE_SBF_IC1, + 0, + Opcode_ae_sbf_ic1_encode_fns, 3, Opcode_ae_sbf_ic1_funcUnit_uses }, + { "ae_sb.ip", ICLASS_AE_SB_IP, + 0, + Opcode_ae_sb_ip_encode_fns, 3, Opcode_ae_sb_ip_funcUnit_uses }, + { "ae_sbi.ip", ICLASS_AE_SBI_IP, + 0, + Opcode_ae_sbi_ip_encode_fns, 3, Opcode_ae_sbi_ip_funcUnit_uses }, + { "ae_vles16c.ip", ICLASS_AE_VLES16C_IP, + 0, + Opcode_ae_vles16c_ip_encode_fns, 3, Opcode_ae_vles16c_ip_funcUnit_uses }, + { "ae_sbf.ip", ICLASS_AE_SBF_IP, + 0, + Opcode_ae_sbf_ip_encode_fns, 3, Opcode_ae_sbf_ip_funcUnit_uses }, + { "ae_sext32", ICLASS_AE_SEXT32, + 0, + Opcode_ae_sext32_encode_fns, 0, 0 }, + { "ae_movae", ICLASS_AE_MOVAE, + 0, + Opcode_ae_movae_encode_fns, 0, 0 }, + { "ae_movea", ICLASS_AE_MOVEA, + 0, + Opcode_ae_movea_encode_fns, 0, 0 }, + { "ae_moveep", ICLASS_AE_MOVEEP, + 0, + Opcode_ae_moveep_encode_fns, 0, 0 }, + { "ae_sext72", ICLASS_AE_SEXT72, + 0, + Opcode_ae_sext72_encode_fns, 0, 0 }, + { "ae_add72", ICLASS_AE_ADD72, + 0, + Opcode_ae_add72_encode_fns, 0, 0 }, + { "ae_sub72", ICLASS_AE_SUB72, + 0, + Opcode_ae_sub72_encode_fns, 0, 0 }, + { "ae_add72x64", ICLASS_AE_ADD72X64, + 0, + Opcode_ae_add72x64_encode_fns, 0, 0 }, + { "ae_sub72x64", ICLASS_AE_SUB72X64, + 0, + Opcode_ae_sub72x64_encode_fns, 0, 0 }, + { "ae_mul32ep.hh", ICLASS_AE_MUL32EP_HH, + 0, + Opcode_ae_mul32ep_hh_encode_fns, 0, 0 }, + { "ae_mula32ep.hh", ICLASS_AE_MULA32EP_HH, + 0, + Opcode_ae_mula32ep_hh_encode_fns, 0, 0 }, + { "ae_muls32ep.hh", ICLASS_AE_MULS32EP_HH, + 0, + Opcode_ae_muls32ep_hh_encode_fns, 0, 0 }, + { "ae_mulzaad32ep.hh.ll", ICLASS_AE_MULZAAD32EP_HH_LL, + 0, + Opcode_ae_mulzaad32ep_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssd32ep.hh.ll", ICLASS_AE_MULZSSD32EP_HH_LL, + 0, + Opcode_ae_mulzssd32ep_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaad32ep.hh.ll", ICLASS_AE_MULAAD32EP_HH_LL, + 0, + Opcode_ae_mulaad32ep_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssd32ep.hh.ll", ICLASS_AE_MULSSD32EP_HH_LL, + 0, + Opcode_ae_mulssd32ep_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaad32usep.hl.lh", ICLASS_AE_MULAAD32USEP_HL_LH, + 0, + Opcode_ae_mulaad32usep_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaad32usep.hl.lh", ICLASS_AE_MULZAAD32USEP_HL_LH, + 0, + Opcode_ae_mulzaad32usep_hl_lh_encode_fns, 0, 0 }, + { "ae_mul32usep.lh", ICLASS_AE_MUL32USEP_LH, + 0, + Opcode_ae_mul32usep_lh_encode_fns, 0, 0 }, + { "ae_mula32usep.lh", ICLASS_AE_MULA32USEP_LH, + 0, + Opcode_ae_mula32usep_lh_encode_fns, 0, 0 }, + { "ae_mul32usep.ll", ICLASS_AE_MUL32USEP_LL, + 0, + Opcode_ae_mul32usep_ll_encode_fns, 0, 0 }, + { "ae_mula32usep.ll", ICLASS_AE_MULA32USEP_LL, + 0, + Opcode_ae_mula32usep_ll_encode_fns, 0, 0 }, + { "ae_srai72", ICLASS_AE_SRAI72, + 0, + Opcode_ae_srai72_encode_fns, 0, 0 }, + { "ae_slai72", ICLASS_AE_SLAI72, + 0, + Opcode_ae_slai72_encode_fns, 0, 0 }, + { "ae_sat64s", ICLASS_AE_SAT64S, + 0, + Opcode_ae_sat64s_encode_fns, 0, 0 }, + { "ae_l16si.n", ICLASS_AE_L16SI_N, + 0, + Opcode_ae_l16si_n_encode_fns, 2, Opcode_ae_l16si_n_funcUnit_uses }, + { "ae_l16ui.n", ICLASS_AE_L16UI_N, + 0, + Opcode_ae_l16ui_n_encode_fns, 2, Opcode_ae_l16ui_n_funcUnit_uses }, + { "ae_s16i.n", ICLASS_AE_S16I_N, + 0, + Opcode_ae_s16i_n_encode_fns, 2, Opcode_ae_s16i_n_funcUnit_uses }, + { "ae_lalign128.i", ICLASS_AE_LALIGN128_I, + 0, + Opcode_ae_lalign128_i_encode_fns, 1, Opcode_ae_lalign128_i_funcUnit_uses }, + { "ae_salign128.i", ICLASS_AE_SALIGN128_I, + 0, + Opcode_ae_salign128_i_encode_fns, 1, Opcode_ae_salign128_i_funcUnit_uses }, + { "ae_la128.pp", ICLASS_AE_LA128_PP, + 0, + Opcode_ae_la128_pp_encode_fns, 1, Opcode_ae_la128_pp_funcUnit_uses }, + { "ae_sa128pos.fp", ICLASS_AE_SA128POS_FP, + 0, + Opcode_ae_sa128pos_fp_encode_fns, 1, Opcode_ae_sa128pos_fp_funcUnit_uses }, + { "ae_la8x4s_ip", ICLASS_AE_LA8X4S_IP, + 0, + Opcode_ae_la8x4s_ip_encode_fns, 1, Opcode_ae_la8x4s_ip_funcUnit_uses }, + { "ae_la8x4u_ip", ICLASS_AE_LA8X4U_IP, + 0, + Opcode_ae_la8x4u_ip_encode_fns, 1, Opcode_ae_la8x4u_ip_funcUnit_uses }, + { "ae_la8x8x2_ip", ICLASS_AE_LA8X8X2_IP, + 0, + Opcode_ae_la8x8x2_ip_encode_fns, 1, Opcode_ae_la8x8x2_ip_funcUnit_uses }, + { "ae_la16x4x2_ip", ICLASS_AE_LA16X4X2_IP, + 0, + Opcode_ae_la16x4x2_ip_encode_fns, 1, Opcode_ae_la16x4x2_ip_funcUnit_uses }, + { "ae_la32x2x2_ip", ICLASS_AE_LA32X2X2_IP, + 0, + Opcode_ae_la32x2x2_ip_encode_fns, 1, Opcode_ae_la32x2x2_ip_funcUnit_uses }, + { "ae_la8x8x2_ic", ICLASS_AE_LA8X8X2_IC, + 0, + Opcode_ae_la8x8x2_ic_encode_fns, 1, Opcode_ae_la8x8x2_ic_funcUnit_uses }, + { "ae_la16x4x2_ic", ICLASS_AE_LA16X4X2_IC, + 0, + Opcode_ae_la16x4x2_ic_encode_fns, 1, Opcode_ae_la16x4x2_ic_funcUnit_uses }, + { "ae_la32x2x2_ic", ICLASS_AE_LA32X2X2_IC, + 0, + Opcode_ae_la32x2x2_ic_encode_fns, 1, Opcode_ae_la32x2x2_ic_funcUnit_uses }, + { "ae_la8x8x2_ic1", ICLASS_AE_LA8X8X2_IC1, + 0, + Opcode_ae_la8x8x2_ic1_encode_fns, 1, Opcode_ae_la8x8x2_ic1_funcUnit_uses }, + { "ae_la16x4x2_ic1", ICLASS_AE_LA16X4X2_IC1, + 0, + Opcode_ae_la16x4x2_ic1_encode_fns, 1, Opcode_ae_la16x4x2_ic1_funcUnit_uses }, + { "ae_la32x2x2_ic1", ICLASS_AE_LA32X2X2_IC1, + 0, + Opcode_ae_la32x2x2_ic1_encode_fns, 1, Opcode_ae_la32x2x2_ic1_funcUnit_uses }, + { "ae_la8x8x2_ic2", ICLASS_AE_LA8X8X2_IC2, + 0, + Opcode_ae_la8x8x2_ic2_encode_fns, 1, Opcode_ae_la8x8x2_ic2_funcUnit_uses }, + { "ae_la16x4x2_ic2", ICLASS_AE_LA16X4X2_IC2, + 0, + Opcode_ae_la16x4x2_ic2_encode_fns, 1, Opcode_ae_la16x4x2_ic2_funcUnit_uses }, + { "ae_la32x2x2_ic2", ICLASS_AE_LA32X2X2_IC2, + 0, + Opcode_ae_la32x2x2_ic2_encode_fns, 1, Opcode_ae_la32x2x2_ic2_funcUnit_uses }, + { "ae_sa8x8x2_ip", ICLASS_AE_SA8X8X2_IP, + 0, + Opcode_ae_sa8x8x2_ip_encode_fns, 1, Opcode_ae_sa8x8x2_ip_funcUnit_uses }, + { "ae_sa16x4x2_ip", ICLASS_AE_SA16X4X2_IP, + 0, + Opcode_ae_sa16x4x2_ip_encode_fns, 1, Opcode_ae_sa16x4x2_ip_funcUnit_uses }, + { "ae_sa32x2x2_ip", ICLASS_AE_SA32X2X2_IP, + 0, + Opcode_ae_sa32x2x2_ip_encode_fns, 1, Opcode_ae_sa32x2x2_ip_funcUnit_uses }, + { "ae_sa8x8x2_ic", ICLASS_AE_SA8X8X2_IC, + 0, + Opcode_ae_sa8x8x2_ic_encode_fns, 1, Opcode_ae_sa8x8x2_ic_funcUnit_uses }, + { "ae_sa16x4x2_ic", ICLASS_AE_SA16X4X2_IC, + 0, + Opcode_ae_sa16x4x2_ic_encode_fns, 1, Opcode_ae_sa16x4x2_ic_funcUnit_uses }, + { "ae_sa32x2x2_ic", ICLASS_AE_SA32X2X2_IC, + 0, + Opcode_ae_sa32x2x2_ic_encode_fns, 1, Opcode_ae_sa32x2x2_ic_funcUnit_uses }, + { "ae_sa8x8x2_ic1", ICLASS_AE_SA8X8X2_IC1, + 0, + Opcode_ae_sa8x8x2_ic1_encode_fns, 1, Opcode_ae_sa8x8x2_ic1_funcUnit_uses }, + { "ae_sa16x4x2_ic1", ICLASS_AE_SA16X4X2_IC1, + 0, + Opcode_ae_sa16x4x2_ic1_encode_fns, 1, Opcode_ae_sa16x4x2_ic1_funcUnit_uses }, + { "ae_sa32x2x2_ic1", ICLASS_AE_SA32X2X2_IC1, + 0, + Opcode_ae_sa32x2x2_ic1_encode_fns, 1, Opcode_ae_sa32x2x2_ic1_funcUnit_uses }, + { "ae_sa8x8x2_ic2", ICLASS_AE_SA8X8X2_IC2, + 0, + Opcode_ae_sa8x8x2_ic2_encode_fns, 1, Opcode_ae_sa8x8x2_ic2_funcUnit_uses }, + { "ae_sa16x4x2_ic2", ICLASS_AE_SA16X4X2_IC2, + 0, + Opcode_ae_sa16x4x2_ic2_encode_fns, 1, Opcode_ae_sa16x4x2_ic2_funcUnit_uses }, + { "ae_sa32x2x2_ic2", ICLASS_AE_SA32X2X2_IC2, + 0, + Opcode_ae_sa32x2x2_ic2_encode_fns, 1, Opcode_ae_sa32x2x2_ic2_funcUnit_uses }, + { "ae_abs8", ICLASS_AE_ABS8, + 0, + Opcode_ae_abs8_encode_fns, 0, 0 }, + { "ae_abs8s", ICLASS_AE_ABS8S, + 0, + Opcode_ae_abs8s_encode_fns, 0, 0 }, + { "ae_neg8s", ICLASS_AE_NEG8S, + 0, + Opcode_ae_neg8s_encode_fns, 0, 0 }, + { "ae_add8", ICLASS_AE_ADD8, + 0, + Opcode_ae_add8_encode_fns, 0, 0 }, + { "ae_sub8", ICLASS_AE_SUB8, + 0, + Opcode_ae_sub8_encode_fns, 0, 0 }, + { "ae_max8", ICLASS_AE_MAX8, + 0, + Opcode_ae_max8_encode_fns, 0, 0 }, + { "ae_min8", ICLASS_AE_MIN8, + 0, + Opcode_ae_min8_encode_fns, 0, 0 }, + { "ae_add8s", ICLASS_AE_ADD8S, + 0, + Opcode_ae_add8s_encode_fns, 0, 0 }, + { "ae_sub8s", ICLASS_AE_SUB8S, + 0, + Opcode_ae_sub8s_encode_fns, 0, 0 }, + { "ae_le8", ICLASS_AE_LE8, + 0, + Opcode_ae_le8_encode_fns, 0, 0 }, + { "ae_lt8", ICLASS_AE_LT8, + 0, + Opcode_ae_lt8_encode_fns, 0, 0 }, + { "ae_eq8", ICLASS_AE_EQ8, + 0, + Opcode_ae_eq8_encode_fns, 0, 0 }, + { "ae_satu16x4", ICLASS_AE_SATU16X4, + 0, + Opcode_ae_satu16x4_encode_fns, 0, 0 }, + { "ae_sat32x2", ICLASS_AE_SAT32X2, + 0, + Opcode_ae_sat32x2_encode_fns, 0, 0 }, + { "ae_satu32x2", ICLASS_AE_SATU32X2, + 0, + Opcode_ae_satu32x2_encode_fns, 0, 0 }, + { "ae_sat8x8x16", ICLASS_AE_SAT8X8X16, + 0, + Opcode_ae_sat8x8x16_encode_fns, 0, 0 }, + { "ae_satu8x8x16", ICLASS_AE_SATU8X8X16, + 0, + Opcode_ae_satu8x8x16_encode_fns, 0, 0 }, + { "ae_sat8x4x32_l", ICLASS_AE_SAT8X4X32_L, + 0, + Opcode_ae_sat8x4x32_l_encode_fns, 0, 0 }, + { "ae_satu8x4x32_l", ICLASS_AE_SATU8X4X32_L, + 0, + Opcode_ae_satu8x4x32_l_encode_fns, 0, 0 }, + { "ae_round8x8f16ssym", ICLASS_AE_ROUND8X8F16SSYM, + 0, + Opcode_ae_round8x8f16ssym_encode_fns, 0, 0 }, + { "ae_round8x8f16sasym", ICLASS_AE_ROUND8X8F16SASYM, + 0, + Opcode_ae_round8x8f16sasym_encode_fns, 0, 0 }, + { "ae_round8x4f32ssym_l", ICLASS_AE_ROUND8X4F32SSYM_L, + 0, + Opcode_ae_round8x4f32ssym_l_encode_fns, 0, 0 }, + { "ae_round8x4f32sasym_l", ICLASS_AE_ROUND8X4F32SASYM_L, + 0, + Opcode_ae_round8x4f32sasym_l_encode_fns, 0, 0 }, + { "ae_movda8", ICLASS_AE_MOVDA8, + 0, + Opcode_ae_movda8_encode_fns, 0, 0 }, + { "ae_movad8", ICLASS_AE_MOVAD8, + 0, + Opcode_ae_movad8_encode_fns, 0, 0 }, + { "ae_movdx2", ICLASS_AE_MOVDX2, + 0, + Opcode_ae_movdx2_encode_fns, 0, 0 }, + { "ae_addandsub32j", ICLASS_AE_ADDANDSUB32J, + 0, + Opcode_ae_addandsub32j_encode_fns, 0, 0 }, + { "ae_addw8", ICLASS_AE_ADDW8, + 0, + Opcode_ae_addw8_encode_fns, 0, 0 }, + { "ae_addw16", ICLASS_AE_ADDW16, + 0, + Opcode_ae_addw16_encode_fns, 0, 0 }, + { "ae_addw32", ICLASS_AE_ADDW32, + 0, + Opcode_ae_addw32_encode_fns, 0, 0 }, + { "ae_subw8", ICLASS_AE_SUBW8, + 0, + Opcode_ae_subw8_encode_fns, 0, 0 }, + { "ae_subw16", ICLASS_AE_SUBW16, + 0, + Opcode_ae_subw16_encode_fns, 0, 0 }, + { "ae_subw32", ICLASS_AE_SUBW32, + 0, + Opcode_ae_subw32_encode_fns, 0, 0 }, + { "ae_accw8", ICLASS_AE_ACCW8, + 0, + Opcode_ae_accw8_encode_fns, 0, 0 }, + { "ae_accw16", ICLASS_AE_ACCW16, + 0, + Opcode_ae_accw16_encode_fns, 0, 0 }, + { "ae_accw32", ICLASS_AE_ACCW32, + 0, + Opcode_ae_accw32_encode_fns, 0, 0 }, + { "ae_addw8u", ICLASS_AE_ADDW8U, + 0, + Opcode_ae_addw8u_encode_fns, 0, 0 }, + { "ae_subw8u", ICLASS_AE_SUBW8U, + 0, + Opcode_ae_subw8u_encode_fns, 0, 0 }, + { "ae_accw8u", ICLASS_AE_ACCW8U, + 0, + Opcode_ae_accw8u_encode_fns, 0, 0 }, + { "ae_mulfp32x2s.hh.ll", ICLASS_AE_MULFP32X2S_HH_LL, + 0, + Opcode_ae_mulfp32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulafp32x2s.hh.ll", ICLASS_AE_MULAFP32X2S_HH_LL, + 0, + Opcode_ae_mulafp32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsfp32x2s.hh.ll", ICLASS_AE_MULSFP32X2S_HH_LL, + 0, + Opcode_ae_mulsfp32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulfp32x2s.hl.lh", ICLASS_AE_MULFP32X2S_HL_LH, + 0, + Opcode_ae_mulfp32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulafp32x2s.hl.lh", ICLASS_AE_MULAFP32X2S_HL_LH, + 0, + Opcode_ae_mulafp32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsfp32x2s.hl.lh", ICLASS_AE_MULSFP32X2S_HL_LH, + 0, + Opcode_ae_mulsfp32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaaf2d32s.hh.ll", ICLASS_AE_MULZAAF2D32S_HH_LL, + 0, + Opcode_ae_mulzaaf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasf2d32s.hh.ll", ICLASS_AE_MULZASF2D32S_HH_LL, + 0, + Opcode_ae_mulzasf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsaf2d32s.hh.ll", ICLASS_AE_MULZSAF2D32S_HH_LL, + 0, + Opcode_ae_mulzsaf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssf2d32s.hh.ll", ICLASS_AE_MULZSSF2D32S_HH_LL, + 0, + Opcode_ae_mulzssf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaaf2d32s.hh.ll", ICLASS_AE_MULAAF2D32S_HH_LL, + 0, + Opcode_ae_mulaaf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasf2d32s.hh.ll", ICLASS_AE_MULASF2D32S_HH_LL, + 0, + Opcode_ae_mulasf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsaf2d32s.hh.ll", ICLASS_AE_MULSAF2D32S_HH_LL, + 0, + Opcode_ae_mulsaf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssf2d32s.hh.ll", ICLASS_AE_MULSSF2D32S_HH_LL, + 0, + Opcode_ae_mulssf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaaf2d32s.hl.lh", ICLASS_AE_MULZAAF2D32S_HL_LH, + 0, + Opcode_ae_mulzaaf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasf2d32s.hl.lh", ICLASS_AE_MULZASF2D32S_HL_LH, + 0, + Opcode_ae_mulzasf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzsaf2d32s.hl.lh", ICLASS_AE_MULZSAF2D32S_HL_LH, + 0, + Opcode_ae_mulzsaf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssf2d32s.hl.lh", ICLASS_AE_MULZSSF2D32S_HL_LH, + 0, + Opcode_ae_mulzssf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaaf2d32s.hl.lh", ICLASS_AE_MULAAF2D32S_HL_LH, + 0, + Opcode_ae_mulaaf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasf2d32s.hl.lh", ICLASS_AE_MULASF2D32S_HL_LH, + 0, + Opcode_ae_mulasf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsaf2d32s.hl.lh", ICLASS_AE_MULSAF2D32S_HL_LH, + 0, + Opcode_ae_mulsaf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssf2d32s.hl.lh", ICLASS_AE_MULSSF2D32S_HL_LH, + 0, + Opcode_ae_mulssf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mul32s.hh", ICLASS_AE_MUL32S_HH, + 0, + Opcode_ae_mul32s_hh_encode_fns, 0, 0 }, + { "ae_mula32s.hh", ICLASS_AE_MULA32S_HH, + 0, + Opcode_ae_mula32s_hh_encode_fns, 0, 0 }, + { "ae_muls32s.hh", ICLASS_AE_MULS32S_HH, + 0, + Opcode_ae_muls32s_hh_encode_fns, 0, 0 }, + { "ae_mul32s.ll", ICLASS_AE_MUL32S_LL, + 0, + Opcode_ae_mul32s_ll_encode_fns, 0, 0 }, + { "ae_mula32s.ll", ICLASS_AE_MULA32S_LL, + 0, + Opcode_ae_mula32s_ll_encode_fns, 0, 0 }, + { "ae_muls32s.ll", ICLASS_AE_MULS32S_LL, + 0, + Opcode_ae_muls32s_ll_encode_fns, 0, 0 }, + { "ae_mul32s.hl", ICLASS_AE_MUL32S_HL, + 0, + Opcode_ae_mul32s_hl_encode_fns, 0, 0 }, + { "ae_mula32s.hl", ICLASS_AE_MULA32S_HL, + 0, + Opcode_ae_mula32s_hl_encode_fns, 0, 0 }, + { "ae_muls32s.hl", ICLASS_AE_MULS32S_HL, + 0, + Opcode_ae_muls32s_hl_encode_fns, 0, 0 }, + { "ae_mul32s.lh", ICLASS_AE_MUL32S_LH, + 0, + Opcode_ae_mul32s_lh_encode_fns, 0, 0 }, + { "ae_mula32s.lh", ICLASS_AE_MULA32S_LH, + 0, + Opcode_ae_mula32s_lh_encode_fns, 0, 0 }, + { "ae_muls32s.lh", ICLASS_AE_MULS32S_LH, + 0, + Opcode_ae_muls32s_lh_encode_fns, 0, 0 }, + { "ae_mul32x2s.hh.ll", ICLASS_AE_MUL32X2S_HH_LL, + 0, + Opcode_ae_mul32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_mula32x2s.hh.ll", ICLASS_AE_MULA32X2S_HH_LL, + 0, + Opcode_ae_mula32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_muls32x2s.hh.ll", ICLASS_AE_MULS32X2S_HH_LL, + 0, + Opcode_ae_muls32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_mul32x2s.hl.lh", ICLASS_AE_MUL32X2S_HL_LH, + 0, + Opcode_ae_mul32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_mula32x2s.hl.lh", ICLASS_AE_MULA32X2S_HL_LH, + 0, + Opcode_ae_mula32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_muls32x2s.hl.lh", ICLASS_AE_MULS32X2S_HL_LH, + 0, + Opcode_ae_muls32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaad32s.hh.ll", ICLASS_AE_MULZAAD32S_HH_LL, + 0, + Opcode_ae_mulzaad32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasd32s.hh.ll", ICLASS_AE_MULZASD32S_HH_LL, + 0, + Opcode_ae_mulzasd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsad32s.hh.ll", ICLASS_AE_MULZSAD32S_HH_LL, + 0, + Opcode_ae_mulzsad32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssd32s.hh.ll", ICLASS_AE_MULZSSD32S_HH_LL, + 0, + Opcode_ae_mulzssd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaad32s.hh.ll", ICLASS_AE_MULAAD32S_HH_LL, + 0, + Opcode_ae_mulaad32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasd32s.hh.ll", ICLASS_AE_MULASD32S_HH_LL, + 0, + Opcode_ae_mulasd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsad32s.hh.ll", ICLASS_AE_MULSAD32S_HH_LL, + 0, + Opcode_ae_mulsad32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssd32s.hh.ll", ICLASS_AE_MULSSD32S_HH_LL, + 0, + Opcode_ae_mulssd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaad32s.hl.lh", ICLASS_AE_MULZAAD32S_HL_LH, + 0, + Opcode_ae_mulzaad32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasd32s.hl.lh", ICLASS_AE_MULZASD32S_HL_LH, + 0, + Opcode_ae_mulzasd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzsad32s.hl.lh", ICLASS_AE_MULZSAD32S_HL_LH, + 0, + Opcode_ae_mulzsad32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssd32s.hl.lh", ICLASS_AE_MULZSSD32S_HL_LH, + 0, + Opcode_ae_mulzssd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaad32s.hl.lh", ICLASS_AE_MULAAD32S_HL_LH, + 0, + Opcode_ae_mulaad32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasd32s.hl.lh", ICLASS_AE_MULASD32S_HL_LH, + 0, + Opcode_ae_mulasd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsad32s.hl.lh", ICLASS_AE_MULSAD32S_HL_LH, + 0, + Opcode_ae_mulsad32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssd32s.hl.lh", ICLASS_AE_MULSSD32S_HL_LH, + 0, + Opcode_ae_mulssd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulf32x2ra.hh.ll", ICLASS_AE_MULF32X2RA_HH_LL, + 0, + Opcode_ae_mulf32x2ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaf32x2ra.hh.ll", ICLASS_AE_MULAF32X2RA_HH_LL, + 0, + Opcode_ae_mulaf32x2ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsf32x2ra.hh.ll", ICLASS_AE_MULSF32X2RA_HH_LL, + 0, + Opcode_ae_mulsf32x2ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulf32x2ra.hl.lh", ICLASS_AE_MULF32X2RA_HL_LH, + 0, + Opcode_ae_mulf32x2ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaf32x2ra.hl.lh", ICLASS_AE_MULAF32X2RA_HL_LH, + 0, + Opcode_ae_mulaf32x2ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsf32x2ra.hl.lh", ICLASS_AE_MULSF32X2RA_HL_LH, + 0, + Opcode_ae_mulsf32x2ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaaf2d32ra.hh.ll", ICLASS_AE_MULZAAF2D32RA_HH_LL, + 0, + Opcode_ae_mulzaaf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasf2d32ra.hh.ll", ICLASS_AE_MULZASF2D32RA_HH_LL, + 0, + Opcode_ae_mulzasf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsaf2d32ra.hh.ll", ICLASS_AE_MULZSAF2D32RA_HH_LL, + 0, + Opcode_ae_mulzsaf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssf2d32ra.hh.ll", ICLASS_AE_MULZSSF2D32RA_HH_LL, + 0, + Opcode_ae_mulzssf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaaf2d32ra.hh.ll", ICLASS_AE_MULAAF2D32RA_HH_LL, + 0, + Opcode_ae_mulaaf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasf2d32ra.hh.ll", ICLASS_AE_MULASF2D32RA_HH_LL, + 0, + Opcode_ae_mulasf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsaf2d32ra.hh.ll", ICLASS_AE_MULSAF2D32RA_HH_LL, + 0, + Opcode_ae_mulsaf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssf2d32ra.hh.ll", ICLASS_AE_MULSSF2D32RA_HH_LL, + 0, + Opcode_ae_mulssf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaaf2d32ra.hl.lh", ICLASS_AE_MULZAAF2D32RA_HL_LH, + 0, + Opcode_ae_mulzaaf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasf2d32ra.hl.lh", ICLASS_AE_MULZASF2D32RA_HL_LH, + 0, + Opcode_ae_mulzasf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzsaf2d32ra.hl.lh", ICLASS_AE_MULZSAF2D32RA_HL_LH, + 0, + Opcode_ae_mulzsaf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssf2d32ra.hl.lh", ICLASS_AE_MULZSSF2D32RA_HL_LH, + 0, + Opcode_ae_mulzssf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaaf2d32ra.hl.lh", ICLASS_AE_MULAAF2D32RA_HL_LH, + 0, + Opcode_ae_mulaaf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasf2d32ra.hl.lh", ICLASS_AE_MULASF2D32RA_HL_LH, + 0, + Opcode_ae_mulasf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsaf2d32ra.hl.lh", ICLASS_AE_MULSAF2D32RA_HL_LH, + 0, + Opcode_ae_mulsaf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssf2d32ra.hl.lh", ICLASS_AE_MULSSF2D32RA_HL_LH, + 0, + Opcode_ae_mulssf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulf32x2r.hh.ll", ICLASS_AE_MULF32X2R_HH_LL, + 0, + Opcode_ae_mulf32x2r_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaf32x2r.hh.ll", ICLASS_AE_MULAF32X2R_HH_LL, + 0, + Opcode_ae_mulaf32x2r_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsf32x2r.hh.ll", ICLASS_AE_MULSF32X2R_HH_LL, + 0, + Opcode_ae_mulsf32x2r_hh_ll_encode_fns, 0, 0 }, + { "ae_mulf32x2r.hl.lh", ICLASS_AE_MULF32X2R_HL_LH, + 0, + Opcode_ae_mulf32x2r_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaf32x2r.hl.lh", ICLASS_AE_MULAF32X2R_HL_LH, + 0, + Opcode_ae_mulaf32x2r_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsf32x2r.hl.lh", ICLASS_AE_MULSF32X2R_HL_LH, + 0, + Opcode_ae_mulsf32x2r_hl_lh_encode_fns, 0, 0 }, + { "ae_mulfc32w", ICLASS_AE_MULFC32W, + 0, + Opcode_ae_mulfc32w_encode_fns, 0, 0 }, + { "ae_mulafc32w", ICLASS_AE_MULAFC32W, + 0, + Opcode_ae_mulafc32w_encode_fns, 0, 0 }, + { "ae_mulfcj32w", ICLASS_AE_MULFCJ32W, + 0, + Opcode_ae_mulfcj32w_encode_fns, 0, 0 }, + { "ae_mulafcj32w", ICLASS_AE_MULAFCJ32W, + 0, + Opcode_ae_mulafcj32w_encode_fns, 0, 0 }, + { "ae_mulfcj32ras", ICLASS_AE_MULFCJ32RAS, + 0, + Opcode_ae_mulfcj32ras_encode_fns, 0, 0 }, + { "ae_mulafcj32ras", ICLASS_AE_MULAFCJ32RAS, + 0, + Opcode_ae_mulafcj32ras_encode_fns, 0, 0 }, + { "ae_mulf2p32x4rs", ICLASS_AE_MULF2P32X4RS, + 0, + Opcode_ae_mulf2p32x4rs_encode_fns, 0, 0 }, + { "ae_mulaf2p32x4rs", ICLASS_AE_MULAF2P32X4RS, + 0, + Opcode_ae_mulaf2p32x4rs_encode_fns, 0, 0 }, + { "ae_mulsf2p32x4rs", ICLASS_AE_MULSF2P32X4RS, + 0, + Opcode_ae_mulsf2p32x4rs_encode_fns, 0, 0 }, + { "ae_mulf2p32x4ras", ICLASS_AE_MULF2P32X4RAS, + 0, + Opcode_ae_mulf2p32x4ras_encode_fns, 0, 0 }, + { "ae_mulaf2p32x4ras", ICLASS_AE_MULAF2P32X4RAS, + 0, + Opcode_ae_mulaf2p32x4ras_encode_fns, 0, 0 }, + { "ae_mulsf2p32x4ras", ICLASS_AE_MULSF2P32X4RAS, + 0, + Opcode_ae_mulsf2p32x4ras_encode_fns, 0, 0 }, + { "ae_mulp32x2s", ICLASS_AE_MULP32X2S, + 0, + Opcode_ae_mulp32x2s_encode_fns, 0, 0 }, + { "ae_mul2p32x4s", ICLASS_AE_MUL2P32X4S, + 0, + Opcode_ae_mul2p32x4s_encode_fns, 0, 0 }, + { "ae_mul2p32x4", ICLASS_AE_MUL2P32X4, + 0, + Opcode_ae_mul2p32x4_encode_fns, 0, 0 }, + { "ae_mula2p32x4", ICLASS_AE_MULA2P32X4, + 0, + Opcode_ae_mula2p32x4_encode_fns, 0, 0 }, + { "ae_muls2p32x4", ICLASS_AE_MULS2P32X4, + 0, + Opcode_ae_muls2p32x4_encode_fns, 0, 0 }, + { "ae_mul2p32x4t", ICLASS_AE_MUL2P32X4T, + 0, + Opcode_ae_mul2p32x4t_encode_fns, 0, 0 }, + { "ae_mula2p32x4t", ICLASS_AE_MULA2P32X4T, + 0, + Opcode_ae_mula2p32x4t_encode_fns, 0, 0 }, + { "ae_muls2p32x4t", ICLASS_AE_MULS2P32X4T, + 0, + Opcode_ae_muls2p32x4t_encode_fns, 0, 0 }, + { "ae_mulzaa32x2.hh.ll", ICLASS_AE_MULZAA32X2_HH_LL, + 0, + Opcode_ae_mulzaa32x2_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzss32x2.hh.ll", ICLASS_AE_MULZSS32X2_HH_LL, + 0, + Opcode_ae_mulzss32x2_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaa32x2.hh.ll", ICLASS_AE_MULAA32X2_HH_LL, + 0, + Opcode_ae_mulaa32x2_hh_ll_encode_fns, 0, 0 }, + { "ae_mulss32x2.hh.ll", ICLASS_AE_MULSS32X2_HH_LL, + 0, + Opcode_ae_mulss32x2_hh_ll_encode_fns, 0, 0 }, + { "ae_mulcj32", ICLASS_AE_MULCJ32, + 0, + Opcode_ae_mulcj32_encode_fns, 0, 0 }, + { "ae_mulacj32", ICLASS_AE_MULACJ32, + 0, + Opcode_ae_mulacj32_encode_fns, 0, 0 }, + { "ae_muladdf32rs", ICLASS_AE_MULADDF32RS, + 0, + Opcode_ae_muladdf32rs_encode_fns, 0, 0 }, + { "ae_muladdf32ras", ICLASS_AE_MULADDF32RAS, + 0, + Opcode_ae_muladdf32ras_encode_fns, 0, 0 }, + { "ae_mulsubf32rs", ICLASS_AE_MULSUBF32RS, + 0, + Opcode_ae_mulsubf32rs_encode_fns, 0, 0 }, + { "ae_mulsubf32ras", ICLASS_AE_MULSUBF32RAS, + 0, + Opcode_ae_mulsubf32ras_encode_fns, 0, 0 }, + { "ae_mulfc32ra", ICLASS_AE_MULFC32RA, + 0, + Opcode_ae_mulfc32ra_encode_fns, 0, 0 }, + { "ae_mulafc32ra", ICLASS_AE_MULAFC32RA, + 0, + Opcode_ae_mulafc32ra_encode_fns, 0, 0 }, + { "ae_mulcj32w", ICLASS_AE_MULCJ32W, + 0, + Opcode_ae_mulcj32w_encode_fns, 0, 0 }, + { "ae_mulacj32w", ICLASS_AE_MULACJ32W, + 0, + Opcode_ae_mulacj32w_encode_fns, 0, 0 }, + { "ae_mulc32w", ICLASS_AE_MULC32W, + 0, + Opcode_ae_mulc32w_encode_fns, 0, 0 }, + { "ae_mulac32w", ICLASS_AE_MULAC32W, + 0, + Opcode_ae_mulac32w_encode_fns, 0, 0 }, + { "ae_mulf2d32x2ws", ICLASS_AE_MULF2D32X2WS, + 0, + Opcode_ae_mulf2d32x2ws_encode_fns, 0, 0 }, + { "ae_mulzaaaa2q16", ICLASS_AE_MULZAAAA2Q16, + 0, + Opcode_ae_mulzaaaa2q16_encode_fns, 0, 0 }, + { "ae_mulaaaa2q16", ICLASS_AE_MULAAAA2Q16, + 0, + Opcode_ae_mulaaaa2q16_encode_fns, 0, 0 }, + { "ae_mulp16s.h", ICLASS_AE_MULP16S_H, + 0, + Opcode_ae_mulp16s_h_encode_fns, 0, 0 }, + { "ae_mulap16s.h", ICLASS_AE_MULAP16S_H, + 0, + Opcode_ae_mulap16s_h_encode_fns, 0, 0 }, + { "ae_mulsp16s.h", ICLASS_AE_MULSP16S_H, + 0, + Opcode_ae_mulsp16s_h_encode_fns, 0, 0 }, + { "ae_mulp16s.l", ICLASS_AE_MULP16S_L, + 0, + Opcode_ae_mulp16s_l_encode_fns, 0, 0 }, + { "ae_mulap16s.l", ICLASS_AE_MULAP16S_L, + 0, + Opcode_ae_mulap16s_l_encode_fns, 0, 0 }, + { "ae_mulsp16s.l", ICLASS_AE_MULSP16S_L, + 0, + Opcode_ae_mulsp16s_l_encode_fns, 0, 0 }, + { "ae_mulc16w.h", ICLASS_AE_MULC16W_H, + 0, + Opcode_ae_mulc16w_h_encode_fns, 0, 0 }, + { "ae_mulac16w.h", ICLASS_AE_MULAC16W_H, + 0, + Opcode_ae_mulac16w_h_encode_fns, 0, 0 }, + { "ae_mulc16w.l", ICLASS_AE_MULC16W_L, + 0, + Opcode_ae_mulc16w_l_encode_fns, 0, 0 }, + { "ae_mulac16w.l", ICLASS_AE_MULAC16W_L, + 0, + Opcode_ae_mulac16w_l_encode_fns, 0, 0 }, + { "ae_mul2c16s", ICLASS_AE_MUL2C16S, + 0, + Opcode_ae_mul2c16s_encode_fns, 0, 0 }, + { "ae_mula2c16s", ICLASS_AE_MULA2C16S, + 0, + Opcode_ae_mula2c16s_encode_fns, 0, 0 }, + { "ae_mulfc16s", ICLASS_AE_MULFC16S, + 0, + Opcode_ae_mulfc16s_encode_fns, 0, 0 }, + { "ae_mulafc16s", ICLASS_AE_MULAFC16S, + 0, + Opcode_ae_mulafc16s_encode_fns, 0, 0 }, + { "ae_mulfcj16s", ICLASS_AE_MULFCJ16S, + 0, + Opcode_ae_mulfcj16s_encode_fns, 0, 0 }, + { "ae_mulafcj16s", ICLASS_AE_MULAFCJ16S, + 0, + Opcode_ae_mulafcj16s_encode_fns, 0, 0 }, + { "ae_mulfcj16ras", ICLASS_AE_MULFCJ16RAS, + 0, + Opcode_ae_mulfcj16ras_encode_fns, 0, 0 }, + { "ae_mulafcj16ras", ICLASS_AE_MULAFCJ16RAS, + 0, + Opcode_ae_mulafcj16ras_encode_fns, 0, 0 }, + { "ae_mulc16s", ICLASS_AE_MULC16S, + 0, + Opcode_ae_mulc16s_encode_fns, 0, 0 }, + { "ae_mulac16s", ICLASS_AE_MULAC16S, + 0, + Opcode_ae_mulac16s_encode_fns, 0, 0 }, + { "ae_mulfp16x4rs", ICLASS_AE_MULFP16X4RS, + 0, + Opcode_ae_mulfp16x4rs_encode_fns, 0, 0 }, + { "ae_mulfd16x16x4ras", ICLASS_AE_MULFD16X16X4RAS, + 0, + Opcode_ae_mulfd16x16x4ras_encode_fns, 0, 0 }, + { "ae_mulp16x16x4s", ICLASS_AE_MULP16X16X4S, + 0, + Opcode_ae_mulp16x16x4s_encode_fns, 0, 0 }, + { "ae_mulap16x16x4s", ICLASS_AE_MULAP16X16X4S, + 0, + Opcode_ae_mulap16x16x4s_encode_fns, 0, 0 }, + { "ae_mulsp16x16x4s", ICLASS_AE_MULSP16X16X4S, + 0, + Opcode_ae_mulsp16x16x4s_encode_fns, 0, 0 }, + { "ae_mulzaa2d16ss.hh_ll", ICLASS_AE_MULZAA2D16SS_HH_LL, + 0, + Opcode_ae_mulzaa2d16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaa2d16ss.hl_lh", ICLASS_AE_MULZAA2D16SS_HL_LH, + 0, + Opcode_ae_mulzaa2d16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzss2d16ss.hh_ll", ICLASS_AE_MULZSS2D16SS_HH_LL, + 0, + Opcode_ae_mulzss2d16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzss2d16ss.hl_lh", ICLASS_AE_MULZSS2D16SS_HL_LH, + 0, + Opcode_ae_mulzss2d16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaa2d16ss.hh_ll", ICLASS_AE_MULAA2D16SS_HH_LL, + 0, + Opcode_ae_mulaa2d16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaa2d16ss.hl_lh", ICLASS_AE_MULAA2D16SS_HL_LH, + 0, + Opcode_ae_mulaa2d16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulss2d16ss.hh_ll", ICLASS_AE_MULSS2D16SS_HH_LL, + 0, + Opcode_ae_mulss2d16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulss2d16ss.hl_lh", ICLASS_AE_MULSS2D16SS_HL_LH, + 0, + Opcode_ae_mulss2d16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaafd16ss.hh_ll", ICLASS_AE_MULZAAFD16SS_HH_LL, + 0, + Opcode_ae_mulzaafd16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaafd16ss.hl_lh", ICLASS_AE_MULZAAFD16SS_HL_LH, + 0, + Opcode_ae_mulzaafd16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssfd16ss.hh_ll", ICLASS_AE_MULZSSFD16SS_HH_LL, + 0, + Opcode_ae_mulzssfd16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssfd16ss.hl_lh", ICLASS_AE_MULZSSFD16SS_HL_LH, + 0, + Opcode_ae_mulzssfd16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaafd16ss.hh_ll", ICLASS_AE_MULAAFD16SS_HH_LL, + 0, + Opcode_ae_mulaafd16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaafd16ss.hl_lh", ICLASS_AE_MULAAFD16SS_HL_LH, + 0, + Opcode_ae_mulaafd16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssfd16ss.hh_ll", ICLASS_AE_MULSSFD16SS_HH_LL, + 0, + Opcode_ae_mulssfd16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssfd16ss.hl_lh", ICLASS_AE_MULSSFD16SS_HL_LH, + 0, + Opcode_ae_mulssfd16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulfd16x16x4ws", ICLASS_AE_MULFD16X16X4WS, + 0, + Opcode_ae_mulfd16x16x4ws_encode_fns, 0, 0 }, + { "ae_mulzaaaa2q16x8", ICLASS_AE_MULZAAAA2Q16X8, + 0, + Opcode_ae_mulzaaaa2q16x8_encode_fns, 0, 0 }, + { "ae_mulaaaa2q16x8", ICLASS_AE_MULAAAA2Q16X8, + 0, + Opcode_ae_mulaaaa2q16x8_encode_fns, 0, 0 }, + { "ae_mulzaaaa2q8", ICLASS_AE_MULZAAAA2Q8, + 0, + Opcode_ae_mulzaaaa2q8_encode_fns, 0, 0 }, + { "ae_mulaaaa2q8", ICLASS_AE_MULAAAA2Q8, + 0, + Opcode_ae_mulaaaa2q8_encode_fns, 0, 0 }, + { "ae_mulc32x16w.h", ICLASS_AE_MULC32X16W_H, + 0, + Opcode_ae_mulc32x16w_h_encode_fns, 0, 0 }, + { "ae_mulac32x16w.h", ICLASS_AE_MULAC32X16W_H, + 0, + Opcode_ae_mulac32x16w_h_encode_fns, 0, 0 }, + { "ae_mulc32x16w.l", ICLASS_AE_MULC32X16W_L, + 0, + Opcode_ae_mulc32x16w_l_encode_fns, 0, 0 }, + { "ae_mulac32x16w.l", ICLASS_AE_MULAC32X16W_L, + 0, + Opcode_ae_mulac32x16w_l_encode_fns, 0, 0 }, + { "ae_mulpc32x16x2", ICLASS_AE_MULPC32X16X2, + 0, + Opcode_ae_mulpc32x16x2_encode_fns, 0, 0 }, + { "ae_mulapc32x16x2", ICLASS_AE_MULAPC32X16X2, + 0, + Opcode_ae_mulapc32x16x2_encode_fns, 0, 0 }, + { "ae_mulfp32x16.h", ICLASS_AE_MULFP32X16_H, + 0, + Opcode_ae_mulfp32x16_h_encode_fns, 0, 0 }, + { "ae_mulafp32x16.h", ICLASS_AE_MULAFP32X16_H, + 0, + Opcode_ae_mulafp32x16_h_encode_fns, 0, 0 }, + { "ae_mulsfp32x16.h", ICLASS_AE_MULSFP32X16_H, + 0, + Opcode_ae_mulsfp32x16_h_encode_fns, 0, 0 }, + { "ae_mulfp32x16.l", ICLASS_AE_MULFP32X16_L, + 0, + Opcode_ae_mulfp32x16_l_encode_fns, 0, 0 }, + { "ae_mulafp32x16.l", ICLASS_AE_MULAFP32X16_L, + 0, + Opcode_ae_mulafp32x16_l_encode_fns, 0, 0 }, + { "ae_mulsfp32x16.l", ICLASS_AE_MULSFP32X16_L, + 0, + Opcode_ae_mulsfp32x16_l_encode_fns, 0, 0 }, + { "ae_mulfc32x16w.h", ICLASS_AE_MULFC32X16W_H, + 0, + Opcode_ae_mulfc32x16w_h_encode_fns, 0, 0 }, + { "ae_mulafc32x16w.h", ICLASS_AE_MULAFC32X16W_H, + 0, + Opcode_ae_mulafc32x16w_h_encode_fns, 0, 0 }, + { "ae_mulfc32x16w.l", ICLASS_AE_MULFC32X16W_L, + 0, + Opcode_ae_mulfc32x16w_l_encode_fns, 0, 0 }, + { "ae_mulafc32x16w.l", ICLASS_AE_MULAFC32X16W_L, + 0, + Opcode_ae_mulafc32x16w_l_encode_fns, 0, 0 }, + { "ae_mulfcj32x16w.h", ICLASS_AE_MULFCJ32X16W_H, + 0, + Opcode_ae_mulfcj32x16w_h_encode_fns, 0, 0 }, + { "ae_mulafcj32x16w.h", ICLASS_AE_MULAFCJ32X16W_H, + 0, + Opcode_ae_mulafcj32x16w_h_encode_fns, 0, 0 }, + { "ae_mulfcj32x16w.l", ICLASS_AE_MULFCJ32X16W_L, + 0, + Opcode_ae_mulfcj32x16w_l_encode_fns, 0, 0 }, + { "ae_mulafcj32x16w.l", ICLASS_AE_MULAFCJ32X16W_L, + 0, + Opcode_ae_mulafcj32x16w_l_encode_fns, 0, 0 }, + { "ae_mulf2p32x16x4ras", ICLASS_AE_MULF2P32X16X4RAS, + 0, + Opcode_ae_mulf2p32x16x4ras_encode_fns, 0, 0 }, + { "ae_mulaf2p32x16x4ras", ICLASS_AE_MULAF2P32X16X4RAS, + 0, + Opcode_ae_mulaf2p32x16x4ras_encode_fns, 0, 0 }, + { "ae_mulsf2p32x16x4ras", ICLASS_AE_MULSF2P32X16X4RAS, + 0, + Opcode_ae_mulsf2p32x16x4ras_encode_fns, 0, 0 }, + { "ae_mulf2p32x16x4rs", ICLASS_AE_MULF2P32X16X4RS, + 0, + Opcode_ae_mulf2p32x16x4rs_encode_fns, 0, 0 }, + { "ae_mulaf2p32x16x4rs", ICLASS_AE_MULAF2P32X16X4RS, + 0, + Opcode_ae_mulaf2p32x16x4rs_encode_fns, 0, 0 }, + { "ae_mulsf2p32x16x4rs", ICLASS_AE_MULSF2P32X16X4RS, + 0, + Opcode_ae_mulsf2p32x16x4rs_encode_fns, 0, 0 }, + { "ae_mulf2p32x16x4s", ICLASS_AE_MULF2P32X16X4S, + 0, + Opcode_ae_mulf2p32x16x4s_encode_fns, 0, 0 }, + { "ae_mulaf2p32x16x4s", ICLASS_AE_MULAF2P32X16X4S, + 0, + Opcode_ae_mulaf2p32x16x4s_encode_fns, 0, 0 }, + { "ae_mulsf2p32x16x4s", ICLASS_AE_MULSF2P32X16X4S, + 0, + Opcode_ae_mulsf2p32x16x4s_encode_fns, 0, 0 }, + { "ae_mulfpc32x16x2ras", ICLASS_AE_MULFPC32X16X2RAS, + 0, + Opcode_ae_mulfpc32x16x2ras_encode_fns, 0, 0 }, + { "ae_mulafpc32x16x2ras", ICLASS_AE_MULAFPC32X16X2RAS, + 0, + Opcode_ae_mulafpc32x16x2ras_encode_fns, 0, 0 }, + { "ae_mulfpcj32x16x2ras", ICLASS_AE_MULFPCJ32X16X2RAS, + 0, + Opcode_ae_mulfpcj32x16x2ras_encode_fns, 0, 0 }, + { "ae_mulafpcj32x16x2ras", ICLASS_AE_MULAFPCJ32X16X2RAS, + 0, + Opcode_ae_mulafpcj32x16x2ras_encode_fns, 0, 0 }, + { "ae_mulzaaaa2q32x16", ICLASS_AE_MULZAAAA2Q32X16, + 0, + Opcode_ae_mulzaaaa2q32x16_encode_fns, 0, 0 }, + { "ae_mulaaaa2q32x16", ICLASS_AE_MULAAAA2Q32X16, + 0, + Opcode_ae_mulaaaa2q32x16_encode_fns, 0, 0 }, + { "ae_mul2q32x16.fir.h", ICLASS_AE_MUL2Q32X16_FIR_H, + 0, + Opcode_ae_mul2q32x16_fir_h_encode_fns, 0, 0 }, + { "ae_mula2q32x16.fir.h", ICLASS_AE_MULA2Q32X16_FIR_H, + 0, + Opcode_ae_mula2q32x16_fir_h_encode_fns, 0, 0 }, + { "ae_mul2q32x16.fir.l", ICLASS_AE_MUL2Q32X16_FIR_L, + 0, + Opcode_ae_mul2q32x16_fir_l_encode_fns, 0, 0 }, + { "ae_mula2q32x16.fir.l", ICLASS_AE_MULA2Q32X16_FIR_L, + 0, + Opcode_ae_mula2q32x16_fir_l_encode_fns, 0, 0 }, + { "ae_srai8", ICLASS_AE_SRAI8, + 0, + Opcode_ae_srai8_encode_fns, 0, 0 }, + { "ae_srai8r", ICLASS_AE_SRAI8R, + 0, + Opcode_ae_srai8r_encode_fns, 0, 0 }, + { "ae_srli8", ICLASS_AE_SRLI8, + 0, + Opcode_ae_srli8_encode_fns, 0, 0 }, + { "ae_slai8", ICLASS_AE_SLAI8, + 0, + Opcode_ae_slai8_encode_fns, 0, 0 }, + { "ae_slai8s", ICLASS_AE_SLAI8S, + 0, + Opcode_ae_slai8s_encode_fns, 0, 0 }, + { "ae_slaa8", ICLASS_AE_SLAA8, + 0, + Opcode_ae_slaa8_encode_fns, 0, 0 }, + { "ae_srla8", ICLASS_AE_SRLA8, + 0, + Opcode_ae_srla8_encode_fns, 0, 0 }, + { "ae_slaa8s", ICLASS_AE_SLAA8S, + 0, + Opcode_ae_slaa8s_encode_fns, 0, 0 }, + { "ae_sraa8rs", ICLASS_AE_SRAA8RS, + 0, + Opcode_ae_sraa8rs_encode_fns, 0, 0 }, + { "ae_sraa8s", ICLASS_AE_SRAA8S, + 0, + Opcode_ae_sraa8s_encode_fns, 0, 0 }, + { "ae_srli16", ICLASS_AE_SRLI16, + 0, + Opcode_ae_srli16_encode_fns, 0, 0 }, + { "ae_slai16", ICLASS_AE_SLAI16, + 0, + Opcode_ae_slai16_encode_fns, 0, 0 }, + { "ae_slaa16", ICLASS_AE_SLAA16, + 0, + Opcode_ae_slaa16_encode_fns, 0, 0 }, + { "ae_srla16", ICLASS_AE_SRLA16, + 0, + Opcode_ae_srla16_encode_fns, 0, 0 }, + { "ae_srai16sym", ICLASS_AE_SRAI16SYM, + 0, + Opcode_ae_srai16sym_encode_fns, 0, 0 }, + { "ae_sraa16syms", ICLASS_AE_SRAA16SYMS, + 0, + Opcode_ae_sraa16syms_encode_fns, 0, 0 }, + { "ae_srai32sym", ICLASS_AE_SRAI32SYM, + 0, + Opcode_ae_srai32sym_encode_fns, 0, 0 }, + { "ae_sraa32syms", ICLASS_AE_SRAA32SYMS, + 0, + Opcode_ae_sraa32syms_encode_fns, 0, 0 }, + { "ae_srav16rs", ICLASS_AE_SRAV16RS, + 0, + Opcode_ae_srav16rs_encode_fns, 0, 0 }, + { "ae_srav32rs", ICLASS_AE_SRAV32RS, + 0, + Opcode_ae_srav32rs_encode_fns, 0, 0 }, + { "ae_cvti32x4f8.h", ICLASS_AE_CVTI32X4F8_H, + 0, + Opcode_ae_cvti32x4f8_h_encode_fns, 0, 0 }, + { "ae_cvti32x4f8.l", ICLASS_AE_CVTI32X4F8_L, + 0, + Opcode_ae_cvti32x4f8_l_encode_fns, 0, 0 }, + { "ae_cvti32x4f8s.h", ICLASS_AE_CVTI32X4F8S_H, + 0, + Opcode_ae_cvti32x4f8s_h_encode_fns, 0, 0 }, + { "ae_cvti32x4f8s.l", ICLASS_AE_CVTI32X4F8S_L, + 0, + Opcode_ae_cvti32x4f8s_l_encode_fns, 0, 0 }, + { "ae_cvta32x4f8.h", ICLASS_AE_CVTA32X4F8_H, + 0, + Opcode_ae_cvta32x4f8_h_encode_fns, 0, 0 }, + { "ae_cvta32x4f8.l", ICLASS_AE_CVTA32X4F8_L, + 0, + Opcode_ae_cvta32x4f8_l_encode_fns, 0, 0 }, + { "ae_cvta32x4f8s.h", ICLASS_AE_CVTA32X4F8S_H, + 0, + Opcode_ae_cvta32x4f8s_h_encode_fns, 0, 0 }, + { "ae_cvta32x4f8s.l", ICLASS_AE_CVTA32X4F8S_L, + 0, + Opcode_ae_cvta32x4f8s_l_encode_fns, 0, 0 }, + { "ae_cvti32x4f8u.h", ICLASS_AE_CVTI32X4F8U_H, + 0, + Opcode_ae_cvti32x4f8u_h_encode_fns, 0, 0 }, + { "ae_cvti32x4f8u.l", ICLASS_AE_CVTI32X4F8U_L, + 0, + Opcode_ae_cvti32x4f8u_l_encode_fns, 0, 0 }, + { "ae_cvti32x4f8us.h", ICLASS_AE_CVTI32X4F8US_H, + 0, + Opcode_ae_cvti32x4f8us_h_encode_fns, 0, 0 }, + { "ae_cvti32x4f8us.l", ICLASS_AE_CVTI32X4F8US_L, + 0, + Opcode_ae_cvti32x4f8us_l_encode_fns, 0, 0 }, + { "ae_cvta32x4f8u.h", ICLASS_AE_CVTA32X4F8U_H, + 0, + Opcode_ae_cvta32x4f8u_h_encode_fns, 0, 0 }, + { "ae_cvta32x4f8u.l", ICLASS_AE_CVTA32X4F8U_L, + 0, + Opcode_ae_cvta32x4f8u_l_encode_fns, 0, 0 }, + { "ae_cvta32x4f8us.h", ICLASS_AE_CVTA32X4F8US_H, + 0, + Opcode_ae_cvta32x4f8us_h_encode_fns, 0, 0 }, + { "ae_cvta32x4f8us.l", ICLASS_AE_CVTA32X4F8US_L, + 0, + Opcode_ae_cvta32x4f8us_l_encode_fns, 0, 0 }, + { "ae_cvti32x4f16", ICLASS_AE_CVTI32X4F16, + 0, + Opcode_ae_cvti32x4f16_encode_fns, 0, 0 }, + { "ae_cvti32x4f16s", ICLASS_AE_CVTI32X4F16S, + 0, + Opcode_ae_cvti32x4f16s_encode_fns, 0, 0 }, + { "ae_cvta32x4f16", ICLASS_AE_CVTA32X4F16, + 0, + Opcode_ae_cvta32x4f16_encode_fns, 0, 0 }, + { "ae_cvta32x4f16s", ICLASS_AE_CVTA32X4F16S, + 0, + Opcode_ae_cvta32x4f16s_encode_fns, 0, 0 }, + { "ae_cvti32x4f16u", ICLASS_AE_CVTI32X4F16U, + 0, + Opcode_ae_cvti32x4f16u_encode_fns, 0, 0 }, + { "ae_cvti32x4f16us", ICLASS_AE_CVTI32X4F16US, + 0, + Opcode_ae_cvti32x4f16us_encode_fns, 0, 0 }, + { "ae_cvta32x4f16u", ICLASS_AE_CVTA32X4F16U, + 0, + Opcode_ae_cvta32x4f16u_encode_fns, 0, 0 }, + { "ae_cvta32x4f16us", ICLASS_AE_CVTA32X4F16US, + 0, + Opcode_ae_cvta32x4f16us_encode_fns, 0, 0 }, + { "ae_cvti16x4x2f8", ICLASS_AE_CVTI16X4X2F8, + 0, + Opcode_ae_cvti16x4x2f8_encode_fns, 0, 0 }, + { "ae_cvti16x4x2f8s", ICLASS_AE_CVTI16X4X2F8S, + 0, + Opcode_ae_cvti16x4x2f8s_encode_fns, 0, 0 }, + { "ae_cvta16x4x2f8", ICLASS_AE_CVTA16X4X2F8, + 0, + Opcode_ae_cvta16x4x2f8_encode_fns, 0, 0 }, + { "ae_cvta16x4x2f8s", ICLASS_AE_CVTA16X4X2F8S, + 0, + Opcode_ae_cvta16x4x2f8s_encode_fns, 0, 0 }, + { "ae_cvti16x4x2f8u", ICLASS_AE_CVTI16X4X2F8U, + 0, + Opcode_ae_cvti16x4x2f8u_encode_fns, 0, 0 }, + { "ae_cvti16x4x2f8us", ICLASS_AE_CVTI16X4X2F8US, + 0, + Opcode_ae_cvti16x4x2f8us_encode_fns, 0, 0 }, + { "ae_cvta16x4x2f8u", ICLASS_AE_CVTA16X4X2F8U, + 0, + Opcode_ae_cvta16x4x2f8u_encode_fns, 0, 0 }, + { "ae_cvta16x4x2f8us", ICLASS_AE_CVTA16X4X2F8US, + 0, + Opcode_ae_cvta16x4x2f8us_encode_fns, 0, 0 }, + { "ae_sel8x8", ICLASS_AE_SEL8X8, + 0, + Opcode_ae_sel8x8_encode_fns, 0, 0 }, + { "ae_shfl8x8", ICLASS_AE_SHFL8X8, + 0, + Opcode_ae_shfl8x8_encode_fns, 0, 0 }, + { "ae_sel16x4", ICLASS_AE_SEL16X4, + 0, + Opcode_ae_sel16x4_encode_fns, 0, 0 }, + { "ae_shfl16x4", ICLASS_AE_SHFL16X4, + 0, + Opcode_ae_shfl16x4_encode_fns, 0, 0 }, + { "ae_dsel8x8", ICLASS_AE_DSEL8X8, + 0, + Opcode_ae_dsel8x8_encode_fns, 0, 0 }, + { "ae_dsel16x4", ICLASS_AE_DSEL16X4, + 0, + Opcode_ae_dsel16x4_encode_fns, 0, 0 }, + { "ae_sel8x8i", ICLASS_AE_SEL8X8I, + 0, + Opcode_ae_sel8x8i_encode_fns, 0, 0 }, + { "ae_rmax8x8", ICLASS_AE_RMAX8X8, + 0, + Opcode_ae_rmax8x8_encode_fns, 0, 0 }, + { "ae_rmin8x8", ICLASS_AE_RMIN8X8, + 0, + Opcode_ae_rmin8x8_encode_fns, 0, 0 }, + { "ae_rmax16x4", ICLASS_AE_RMAX16X4, + 0, + Opcode_ae_rmax16x4_encode_fns, 0, 0 }, + { "ae_rmin16x4", ICLASS_AE_RMIN16X4, + 0, + Opcode_ae_rmin16x4_encode_fns, 0, 0 }, + { "ae_sort16x4", ICLASS_AE_SORT16X4, + 0, + Opcode_ae_sort16x4_encode_fns, 0, 0 }, + { "ae_radd8x8.h", ICLASS_AE_RADD8X8_H, + 0, + Opcode_ae_radd8x8_h_encode_fns, 0, 0 }, + { "ae_radda8x8.h", ICLASS_AE_RADDA8X8_H, + 0, + Opcode_ae_radda8x8_h_encode_fns, 0, 0 }, + { "ae_radd8x8.l", ICLASS_AE_RADD8X8_L, + 0, + Opcode_ae_radd8x8_l_encode_fns, 0, 0 }, + { "ae_radda8x8.l", ICLASS_AE_RADDA8X8_L, + 0, + Opcode_ae_radda8x8_l_encode_fns, 0, 0 }, + { "ae_radd16x4", ICLASS_AE_RADD16X4, + 0, + Opcode_ae_radd16x4_encode_fns, 0, 0 }, + { "ae_radda16x4", ICLASS_AE_RADDA16X4, + 0, + Opcode_ae_radda16x4_encode_fns, 0, 0 }, + { "ae_bmax8x8.h", ICLASS_AE_BMAX8X8_H, + 0, + Opcode_ae_bmax8x8_h_encode_fns, 0, 0 }, + { "ae_bmax8x8.l", ICLASS_AE_BMAX8X8_L, + 0, + Opcode_ae_bmax8x8_l_encode_fns, 0, 0 }, + { "ae_bmin8x8.h", ICLASS_AE_BMIN8X8_H, + 0, + Opcode_ae_bmin8x8_h_encode_fns, 0, 0 }, + { "ae_bmin8x8.l", ICLASS_AE_BMIN8X8_L, + 0, + Opcode_ae_bmin8x8_l_encode_fns, 0, 0 }, + { "ae_bmax16x4", ICLASS_AE_BMAX16X4, + 0, + Opcode_ae_bmax16x4_encode_fns, 0, 0 }, + { "ae_bmin16x4", ICLASS_AE_BMIN16X4, + 0, + Opcode_ae_bmin16x4_encode_fns, 0, 0 }, + { "ae_bmax32x2", ICLASS_AE_BMAX32X2, + 0, + Opcode_ae_bmax32x2_encode_fns, 0, 0 }, + { "ae_bmin32x2", ICLASS_AE_BMIN32X2, + 0, + Opcode_ae_bmin32x2_encode_fns, 0, 0 }, + { "ae_addinv16s", ICLASS_AE_ADDINV16S, + 0, + Opcode_ae_addinv16s_encode_fns, 0, 0 }, + { "ae_addinv32s", ICLASS_AE_ADDINV32S, + 0, + Opcode_ae_addinv32s_encode_fns, 0, 0 }, + { "ae_movt16x8", ICLASS_AE_MOVT16X8, + 0, + Opcode_ae_movt16x8_encode_fns, 0, 0 }, + { "ae_movt8x16.h", ICLASS_AE_MOVT8X16_H, + 0, + Opcode_ae_movt8x16_h_encode_fns, 0, 0 }, + { "ae_movt8x16.l", ICLASS_AE_MOVT8X16_L, + 0, + Opcode_ae_movt8x16_l_encode_fns, 0, 0 }, + { "ae_movbd1x4", ICLASS_AE_MOVBD1X4, + 0, + Opcode_ae_movbd1x4_encode_fns, 0, 0 }, + { "ae_movbd1x2", ICLASS_AE_MOVBD1X2, + 0, + Opcode_ae_movbd1x2_encode_fns, 0, 0 }, + { "ae_movneg32s_t", ICLASS_AE_MOVNEG32S_T, + 0, + Opcode_ae_movneg32s_t_encode_fns, 0, 0 }, + { "ae_movdext", ICLASS_AE_MOVDEXT, + 0, + Opcode_ae_movdext_encode_fns, 0, 0 }, + { "ae_movadext.h", ICLASS_AE_MOVADEXT_H, + 0, + Opcode_ae_movadext_h_encode_fns, 0, 0 }, + { "ae_movadext.l", ICLASS_AE_MOVADEXT_L, + 0, + Opcode_ae_movadext_l_encode_fns, 0, 0 }, + { "ae_nsa16x4", ICLASS_AE_NSA16X4, + 0, + Opcode_ae_nsa16x4_encode_fns, 0, 0 }, + { "ae_nsaz32x4", ICLASS_AE_NSAZ32X4, + 0, + Opcode_ae_nsaz32x4_encode_fns, 0, 0 }, + { "ae_nsa32x4", ICLASS_AE_NSA32X4, + 0, + Opcode_ae_nsa32x4_encode_fns, 0, 0 }, + { "ae_trunci16x4f32s", ICLASS_AE_TRUNCI16X4F32S, + 0, + Opcode_ae_trunci16x4f32s_encode_fns, 0, 0 }, + { "ae_trunci16x4f64s", ICLASS_AE_TRUNCI16X4F64S, + 0, + Opcode_ae_trunci16x4f64s_encode_fns, 0, 0 }, + { "ae_trunca16x4f32s", ICLASS_AE_TRUNCA16X4F32S, + 0, + Opcode_ae_trunca16x4f32s_encode_fns, 0, 0 }, + { "ae_trunca16x4f64s", ICLASS_AE_TRUNCA16X4F64S, + 0, + Opcode_ae_trunca16x4f64s_encode_fns, 0, 0 }, + { "ae_addc32", ICLASS_AE_ADDC32, + 0, + Opcode_ae_addc32_encode_fns, 0, 0 }, + { "ae_subc32", ICLASS_AE_SUBC32, + 0, + Opcode_ae_subc32_encode_fns, 0, 0 }, + { "ae_addc32u", ICLASS_AE_ADDC32U, + 0, + Opcode_ae_addc32u_encode_fns, 0, 0 }, + { "ae_subc32u", ICLASS_AE_SUBC32U, + 0, + Opcode_ae_subc32u_encode_fns, 0, 0 }, + { "ae_expadd16.h", ICLASS_AE_EXPADD16_H, + 0, + Opcode_ae_expadd16_h_encode_fns, 0, 0 }, + { "ae_expsub16.h", ICLASS_AE_EXPSUB16_H, + 0, + Opcode_ae_expsub16_h_encode_fns, 0, 0 }, + { "ae_expadd16.l", ICLASS_AE_EXPADD16_L, + 0, + Opcode_ae_expadd16_l_encode_fns, 0, 0 }, + { "ae_expsub16.l", ICLASS_AE_EXPSUB16_L, + 0, + Opcode_ae_expsub16_l_encode_fns, 0, 0 }, + { "ae_addcexp32.h", ICLASS_AE_ADDCEXP32_H, + 0, + Opcode_ae_addcexp32_h_encode_fns, 0, 0 }, + { "ae_addcexp32.l", ICLASS_AE_ADDCEXP32_L, + 0, + Opcode_ae_addcexp32_l_encode_fns, 0, 0 }, + { "ae_calcrng16", ICLASS_AE_CALCRNG16, + 0, + Opcode_ae_calcrng16_encode_fns, 0, 0 }, + { "ae_calcrng32", ICLASS_AE_CALCRNG32, + 0, + Opcode_ae_calcrng32_encode_fns, 0, 0 }, + { "ae_rng32x4", ICLASS_AE_RNG32X4, + 0, + Opcode_ae_rng32x4_encode_fns, 0, 0 }, + { "ae_lav8x8x2_xp", ICLASS_AE_LAV8X8X2_XP, + 0, + Opcode_ae_lav8x8x2_xp_encode_fns, 1, Opcode_ae_lav8x8x2_xp_funcUnit_uses }, + { "ae_lav16x4x2_xp", ICLASS_AE_LAV16X4X2_XP, + 0, + Opcode_ae_lav16x4x2_xp_encode_fns, 1, Opcode_ae_lav16x4x2_xp_funcUnit_uses }, + { "ae_sav8x8x2_xp", ICLASS_AE_SAV8X8X2_XP, + 0, + Opcode_ae_sav8x8x2_xp_encode_fns, 1, Opcode_ae_sav8x8x2_xp_funcUnit_uses }, + { "ae_sav16x4x2_xp", ICLASS_AE_SAV16X4X2_XP, + 0, + Opcode_ae_sav16x4x2_xp_encode_fns, 1, Opcode_ae_sav16x4x2_xp_funcUnit_uses }, + { "ae_movzbvcdr", ICLASS_AE_MOVZBVCDR, + 0, + Opcode_ae_movzbvcdr_encode_fns, 0, 0 }, + { "ae_movdrzbvc", ICLASS_AE_MOVDRZBVC, + 0, + Opcode_ae_movdrzbvc_encode_fns, 0, 0 }, + { "ae_lavunsqz8x8_xp", ICLASS_AE_LAVUNSQZ8X8_XP, + 0, + Opcode_ae_lavunsqz8x8_xp_encode_fns, 1, Opcode_ae_lavunsqz8x8_xp_funcUnit_uses }, + { "ae_lavunsqz16x4_xp", ICLASS_AE_LAVUNSQZ16X4_XP, + 0, + Opcode_ae_lavunsqz16x4_xp_encode_fns, 1, Opcode_ae_lavunsqz16x4_xp_funcUnit_uses }, + { "ae_mul8q8x8", ICLASS_AE_MUL8Q8X8, + 0, + Opcode_ae_mul8q8x8_encode_fns, 0, 0 }, + { "ae_mula8q8x8", ICLASS_AE_MULA8Q8X8, + 0, + Opcode_ae_mula8q8x8_encode_fns, 0, 0 }, + { "ae_mul8q4x16", ICLASS_AE_MUL8Q4X16, + 0, + Opcode_ae_mul8q4x16_encode_fns, 0, 0 }, + { "ae_mula8q4x16", ICLASS_AE_MULA8Q4X16, + 0, + Opcode_ae_mula8q4x16_encode_fns, 0, 0 }, + { "ae_mul8q8x16", ICLASS_AE_MUL8Q8X16, + 0, + Opcode_ae_mul8q8x16_encode_fns, 0, 0 }, + { "ae_mula8q8x16", ICLASS_AE_MULA8Q8X16, + 0, + Opcode_ae_mula8q8x16_encode_fns, 0, 0 }, + { "ae_mul8qw8x16", ICLASS_AE_MUL8QW8X16, + 0, + Opcode_ae_mul8qw8x16_encode_fns, 0, 0 }, + { "ae_mula8qw8x16", ICLASS_AE_MULA8QW8X16, + 0, + Opcode_ae_mula8qw8x16_encode_fns, 0, 0 }, + { "ae_mul4o8x8", ICLASS_AE_MUL4O8X8, + 0, + Opcode_ae_mul4o8x8_encode_fns, 0, 0 }, + { "ae_mula4o8x8", ICLASS_AE_MULA4O8X8, + 0, + Opcode_ae_mula4o8x8_encode_fns, 0, 0 }, + { "ae_mul4o4x16", ICLASS_AE_MUL4O4X16, + 0, + Opcode_ae_mul4o4x16_encode_fns, 0, 0 }, + { "ae_mula4o4x16", ICLASS_AE_MULA4O4X16, + 0, + Opcode_ae_mula4o4x16_encode_fns, 0, 0 }, + { "ae_mul4o8x16", ICLASS_AE_MUL4O8X16, + 0, + Opcode_ae_mul4o8x16_encode_fns, 0, 0 }, + { "ae_mula4o8x16", ICLASS_AE_MULA4O8X16, + 0, + Opcode_ae_mula4o8x16_encode_fns, 0, 0 }, + { "ae_mul4qw8x16", ICLASS_AE_MUL4QW8X16, + 0, + Opcode_ae_mul4qw8x16_encode_fns, 0, 0 }, + { "ae_mula4qw8x16", ICLASS_AE_MULA4QW8X16, + 0, + Opcode_ae_mula4qw8x16_encode_fns, 0, 0 }, + { "ae_mul8q8x8cnv_l", ICLASS_AE_MUL8Q8X8CNV_L, + 0, + Opcode_ae_mul8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mul8q8x8cnv_h", ICLASS_AE_MUL8Q8X8CNV_H, + 0, + Opcode_ae_mul8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mula8q8x8cnv_l", ICLASS_AE_MULA8Q8X8CNV_L, + 0, + Opcode_ae_mula8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mula8q8x8cnv_h", ICLASS_AE_MULA8Q8X8CNV_H, + 0, + Opcode_ae_mula8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mul8q8x16cnv", ICLASS_AE_MUL8Q8X16CNV, + 0, + Opcode_ae_mul8q8x16cnv_encode_fns, 0, 0 }, + { "ae_mula8q8x16cnv", ICLASS_AE_MULA8Q8X16CNV, + 0, + Opcode_ae_mula8q8x16cnv_encode_fns, 0, 0 }, + { "ae_mul2x4q8x8cnv_h", ICLASS_AE_MUL2X4Q8X8CNV_H, + 0, + Opcode_ae_mul2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mula2x4q8x8cnv_h", ICLASS_AE_MULA2X4Q8X8CNV_H, + 0, + Opcode_ae_mula2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mul2x4q8x8cnv_l", ICLASS_AE_MUL2X4Q8X8CNV_L, + 0, + Opcode_ae_mul2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mula2x4q8x8cnv_l", ICLASS_AE_MULA2X4Q8X8CNV_L, + 0, + Opcode_ae_mula2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mul2x4q8x16cnv", ICLASS_AE_MUL2X4Q8X16CNV, + 0, + Opcode_ae_mul2x4q8x16cnv_encode_fns, 0, 0 }, + { "ae_mula2x4q8x16cnv", ICLASS_AE_MULA2X4Q8X16CNV, + 0, + Opcode_ae_mula2x4q8x16cnv_encode_fns, 0, 0 }, + { "ae_mulqq8x16cnv", ICLASS_AE_MULQQ8X16CNV, + 0, + Opcode_ae_mulqq8x16cnv_encode_fns, 0, 0 }, + { "ae_mulaqq8x16cnv", ICLASS_AE_MULAQQ8X16CNV, + 0, + Opcode_ae_mulaqq8x16cnv_encode_fns, 0, 0 }, + { "ae_mul4o8x8cnv_h", ICLASS_AE_MUL4O8X8CNV_H, + 0, + Opcode_ae_mul4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mula4o8x8cnv_h", ICLASS_AE_MULA4O8X8CNV_H, + 0, + Opcode_ae_mula4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mul4o8x8cnv_l", ICLASS_AE_MUL4O8X8CNV_L, + 0, + Opcode_ae_mul4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mula4o8x8cnv_l", ICLASS_AE_MULA4O8X8CNV_L, + 0, + Opcode_ae_mula4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mul4o8x16cnv_h", ICLASS_AE_MUL4O8X16CNV_H, + 0, + Opcode_ae_mul4o8x16cnv_h_encode_fns, 0, 0 }, + { "ae_mula4o8x16cnv_h", ICLASS_AE_MULA4O8X16CNV_H, + 0, + Opcode_ae_mula4o8x16cnv_h_encode_fns, 0, 0 }, + { "ae_mul4o8x16cnv_l", ICLASS_AE_MUL4O8X16CNV_L, + 0, + Opcode_ae_mul4o8x16cnv_l_encode_fns, 0, 0 }, + { "ae_mula4o8x16cnv_l", ICLASS_AE_MULA4O8X16CNV_L, + 0, + Opcode_ae_mula4o8x16cnv_l_encode_fns, 0, 0 }, + { "ae_mul8q4x16cnv_h", ICLASS_AE_MUL8Q4X16CNV_H, + 0, + Opcode_ae_mul8q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mula8q4x16cnv_h", ICLASS_AE_MULA8Q4X16CNV_H, + 0, + Opcode_ae_mula8q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mul8q4x16cnv_l", ICLASS_AE_MUL8Q4X16CNV_L, + 0, + Opcode_ae_mul8q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mula8q4x16cnv_l", ICLASS_AE_MULA8Q4X16CNV_L, + 0, + Opcode_ae_mula8q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mul2x4q4x16cnv_h", ICLASS_AE_MUL2X4Q4X16CNV_H, + 0, + Opcode_ae_mul2x4q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mula2x4q4x16cnv_h", ICLASS_AE_MULA2X4Q4X16CNV_H, + 0, + Opcode_ae_mula2x4q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mul2x4q4x16cnv_l", ICLASS_AE_MUL2X4Q4X16CNV_L, + 0, + Opcode_ae_mul2x4q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mula2x4q4x16cnv_l", ICLASS_AE_MULA2X4Q4X16CNV_L, + 0, + Opcode_ae_mula2x4q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulqq4x16cnv_h", ICLASS_AE_MULQQ4X16CNV_H, + 0, + Opcode_ae_mulqq4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulaqq4x16cnv_h", ICLASS_AE_MULAQQ4X16CNV_H, + 0, + Opcode_ae_mulaqq4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulqq4x16cnv_l", ICLASS_AE_MULQQ4X16CNV_L, + 0, + Opcode_ae_mulqq4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulaqq4x16cnv_l", ICLASS_AE_MULAQQ4X16CNV_L, + 0, + Opcode_ae_mulaqq4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mul4o4x16cnv_hh", ICLASS_AE_MUL4O4X16CNV_HH, + 0, + Opcode_ae_mul4o4x16cnv_hh_encode_fns, 0, 0 }, + { "ae_mul4o4x16cnv_hl", ICLASS_AE_MUL4O4X16CNV_HL, + 0, + Opcode_ae_mul4o4x16cnv_hl_encode_fns, 0, 0 }, + { "ae_mul4o4x16cnv_lh", ICLASS_AE_MUL4O4X16CNV_LH, + 0, + Opcode_ae_mul4o4x16cnv_lh_encode_fns, 0, 0 }, + { "ae_mul4o4x16cnv_ll", ICLASS_AE_MUL4O4X16CNV_LL, + 0, + Opcode_ae_mul4o4x16cnv_ll_encode_fns, 0, 0 }, + { "ae_mula4o4x16cnv_hh", ICLASS_AE_MULA4O4X16CNV_HH, + 0, + Opcode_ae_mula4o4x16cnv_hh_encode_fns, 0, 0 }, + { "ae_mula4o4x16cnv_hl", ICLASS_AE_MULA4O4X16CNV_HL, + 0, + Opcode_ae_mula4o4x16cnv_hl_encode_fns, 0, 0 }, + { "ae_mula4o4x16cnv_lh", ICLASS_AE_MULA4O4X16CNV_LH, + 0, + Opcode_ae_mula4o4x16cnv_lh_encode_fns, 0, 0 }, + { "ae_mula4o4x16cnv_ll", ICLASS_AE_MULA4O4X16CNV_LL, + 0, + Opcode_ae_mula4o4x16cnv_ll_encode_fns, 0, 0 }, + { "ae_muluu8q8x8", ICLASS_AE_MULUU8Q8X8, + 0, + Opcode_ae_muluu8q8x8_encode_fns, 0, 0 }, + { "ae_mulauu8q8x8", ICLASS_AE_MULAUU8Q8X8, + 0, + Opcode_ae_mulauu8q8x8_encode_fns, 0, 0 }, + { "ae_muluu4o8x8", ICLASS_AE_MULUU4O8X8, + 0, + Opcode_ae_muluu4o8x8_encode_fns, 0, 0 }, + { "ae_mulauu4o8x8", ICLASS_AE_MULAUU4O8X8, + 0, + Opcode_ae_mulauu4o8x8_encode_fns, 0, 0 }, + { "ae_muluu8q8x8cnv_l", ICLASS_AE_MULUU8Q8X8CNV_L, + 0, + Opcode_ae_muluu8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauu8q8x8cnv_l", ICLASS_AE_MULAUU8Q8X8CNV_L, + 0, + Opcode_ae_mulauu8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluu8q8x8cnv_h", ICLASS_AE_MULUU8Q8X8CNV_H, + 0, + Opcode_ae_muluu8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauu8q8x8cnv_h", ICLASS_AE_MULAUU8Q8X8CNV_H, + 0, + Opcode_ae_mulauu8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluu2x4q8x8cnv_h", ICLASS_AE_MULUU2X4Q8X8CNV_H, + 0, + Opcode_ae_muluu2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauu2x4q8x8cnv_h", ICLASS_AE_MULAUU2X4Q8X8CNV_H, + 0, + Opcode_ae_mulauu2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluu2x4q8x8cnv_l", ICLASS_AE_MULUU2X4Q8X8CNV_L, + 0, + Opcode_ae_muluu2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauu2x4q8x8cnv_l", ICLASS_AE_MULAUU2X4Q8X8CNV_L, + 0, + Opcode_ae_mulauu2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluu4o8x8cnv_h", ICLASS_AE_MULUU4O8X8CNV_H, + 0, + Opcode_ae_muluu4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauu4o8x8cnv_h", ICLASS_AE_MULAUU4O8X8CNV_H, + 0, + Opcode_ae_mulauu4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluu4o8x8cnv_l", ICLASS_AE_MULUU4O8X8CNV_L, + 0, + Opcode_ae_muluu4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauu4o8x8cnv_l", ICLASS_AE_MULAUU4O8X8CNV_L, + 0, + Opcode_ae_mulauu4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulus8q8x8", ICLASS_AE_MULUS8Q8X8, + 0, + Opcode_ae_mulus8q8x8_encode_fns, 0, 0 }, + { "ae_mulaus8q8x8", ICLASS_AE_MULAUS8Q8X8, + 0, + Opcode_ae_mulaus8q8x8_encode_fns, 0, 0 }, + { "ae_mulus8q4x16", ICLASS_AE_MULUS8Q4X16, + 0, + Opcode_ae_mulus8q4x16_encode_fns, 0, 0 }, + { "ae_mulaus8q4x16", ICLASS_AE_MULAUS8Q4X16, + 0, + Opcode_ae_mulaus8q4x16_encode_fns, 0, 0 }, + { "ae_mulus8q8x16", ICLASS_AE_MULUS8Q8X16, + 0, + Opcode_ae_mulus8q8x16_encode_fns, 0, 0 }, + { "ae_mulaus8q8x16", ICLASS_AE_MULAUS8Q8X16, + 0, + Opcode_ae_mulaus8q8x16_encode_fns, 0, 0 }, + { "ae_mulus8qw8x16", ICLASS_AE_MULUS8QW8X16, + 0, + Opcode_ae_mulus8qw8x16_encode_fns, 0, 0 }, + { "ae_mulaus8qw8x16", ICLASS_AE_MULAUS8QW8X16, + 0, + Opcode_ae_mulaus8qw8x16_encode_fns, 0, 0 }, + { "ae_mulus4o8x8", ICLASS_AE_MULUS4O8X8, + 0, + Opcode_ae_mulus4o8x8_encode_fns, 0, 0 }, + { "ae_mulaus4o8x8", ICLASS_AE_MULAUS4O8X8, + 0, + Opcode_ae_mulaus4o8x8_encode_fns, 0, 0 }, + { "ae_mulus4o4x16", ICLASS_AE_MULUS4O4X16, + 0, + Opcode_ae_mulus4o4x16_encode_fns, 0, 0 }, + { "ae_mulaus4o4x16", ICLASS_AE_MULAUS4O4X16, + 0, + Opcode_ae_mulaus4o4x16_encode_fns, 0, 0 }, + { "ae_mulus4o8x16", ICLASS_AE_MULUS4O8X16, + 0, + Opcode_ae_mulus4o8x16_encode_fns, 0, 0 }, + { "ae_mulaus4o8x16", ICLASS_AE_MULAUS4O8X16, + 0, + Opcode_ae_mulaus4o8x16_encode_fns, 0, 0 }, + { "ae_mulus4qw8x16", ICLASS_AE_MULUS4QW8X16, + 0, + Opcode_ae_mulus4qw8x16_encode_fns, 0, 0 }, + { "ae_mulaus4qw8x16", ICLASS_AE_MULAUS4QW8X16, + 0, + Opcode_ae_mulaus4qw8x16_encode_fns, 0, 0 }, + { "ae_mulus8q8x8cnv_l", ICLASS_AE_MULUS8Q8X8CNV_L, + 0, + Opcode_ae_mulus8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulaus8q8x8cnv_l", ICLASS_AE_MULAUS8Q8X8CNV_L, + 0, + Opcode_ae_mulaus8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulus8q8x8cnv_h", ICLASS_AE_MULUS8Q8X8CNV_H, + 0, + Opcode_ae_mulus8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulaus8q8x8cnv_h", ICLASS_AE_MULAUS8Q8X8CNV_H, + 0, + Opcode_ae_mulaus8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulus8q8x16cnv", ICLASS_AE_MULUS8Q8X16CNV, + 0, + Opcode_ae_mulus8q8x16cnv_encode_fns, 0, 0 }, + { "ae_mulaus8q8x16cnv", ICLASS_AE_MULAUS8Q8X16CNV, + 0, + Opcode_ae_mulaus8q8x16cnv_encode_fns, 0, 0 }, + { "ae_mulus2x4q8x8cnv_h", ICLASS_AE_MULUS2X4Q8X8CNV_H, + 0, + Opcode_ae_mulus2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulaus2x4q8x8cnv_h", ICLASS_AE_MULAUS2X4Q8X8CNV_H, + 0, + Opcode_ae_mulaus2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulus2x4q8x8cnv_l", ICLASS_AE_MULUS2X4Q8X8CNV_L, + 0, + Opcode_ae_mulus2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulaus2x4q8x8cnv_l", ICLASS_AE_MULAUS2X4Q8X8CNV_L, + 0, + Opcode_ae_mulaus2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulus2x4q8x16cnv", ICLASS_AE_MULUS2X4Q8X16CNV, + 0, + Opcode_ae_mulus2x4q8x16cnv_encode_fns, 0, 0 }, + { "ae_mulaus2x4q8x16cnv", ICLASS_AE_MULAUS2X4Q8X16CNV, + 0, + Opcode_ae_mulaus2x4q8x16cnv_encode_fns, 0, 0 }, + { "ae_mulusqq8x16cnv", ICLASS_AE_MULUSQQ8X16CNV, + 0, + Opcode_ae_mulusqq8x16cnv_encode_fns, 0, 0 }, + { "ae_mulausqq8x16cnv", ICLASS_AE_MULAUSQQ8X16CNV, + 0, + Opcode_ae_mulausqq8x16cnv_encode_fns, 0, 0 }, + { "ae_mulus4o8x8cnv_h", ICLASS_AE_MULUS4O8X8CNV_H, + 0, + Opcode_ae_mulus4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulaus4o8x8cnv_h", ICLASS_AE_MULAUS4O8X8CNV_H, + 0, + Opcode_ae_mulaus4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulus4o8x8cnv_l", ICLASS_AE_MULUS4O8X8CNV_L, + 0, + Opcode_ae_mulus4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulaus4o8x8cnv_l", ICLASS_AE_MULAUS4O8X8CNV_L, + 0, + Opcode_ae_mulaus4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulus4o8x16cnv_h", ICLASS_AE_MULUS4O8X16CNV_H, + 0, + Opcode_ae_mulus4o8x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulaus4o8x16cnv_h", ICLASS_AE_MULAUS4O8X16CNV_H, + 0, + Opcode_ae_mulaus4o8x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulus4o8x16cnv_l", ICLASS_AE_MULUS4O8X16CNV_L, + 0, + Opcode_ae_mulus4o8x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulaus4o8x16cnv_l", ICLASS_AE_MULAUS4O8X16CNV_L, + 0, + Opcode_ae_mulaus4o8x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulus8q4x16cnv_h", ICLASS_AE_MULUS8Q4X16CNV_H, + 0, + Opcode_ae_mulus8q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulaus8q4x16cnv_h", ICLASS_AE_MULAUS8Q4X16CNV_H, + 0, + Opcode_ae_mulaus8q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulus8q4x16cnv_l", ICLASS_AE_MULUS8Q4X16CNV_L, + 0, + Opcode_ae_mulus8q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulaus8q4x16cnv_l", ICLASS_AE_MULAUS8Q4X16CNV_L, + 0, + Opcode_ae_mulaus8q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulus2x4q4x16cnv_h", ICLASS_AE_MULUS2X4Q4X16CNV_H, + 0, + Opcode_ae_mulus2x4q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulaus2x4q4x16cnv_h", ICLASS_AE_MULAUS2X4Q4X16CNV_H, + 0, + Opcode_ae_mulaus2x4q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulus2x4q4x16cnv_l", ICLASS_AE_MULUS2X4Q4X16CNV_L, + 0, + Opcode_ae_mulus2x4q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulaus2x4q4x16cnv_l", ICLASS_AE_MULAUS2X4Q4X16CNV_L, + 0, + Opcode_ae_mulaus2x4q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulusqq4x16cnv_h", ICLASS_AE_MULUSQQ4X16CNV_H, + 0, + Opcode_ae_mulusqq4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulausqq4x16cnv_h", ICLASS_AE_MULAUSQQ4X16CNV_H, + 0, + Opcode_ae_mulausqq4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulusqq4x16cnv_l", ICLASS_AE_MULUSQQ4X16CNV_L, + 0, + Opcode_ae_mulusqq4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulausqq4x16cnv_l", ICLASS_AE_MULAUSQQ4X16CNV_L, + 0, + Opcode_ae_mulausqq4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulus4o4x16cnv_hh", ICLASS_AE_MULUS4O4X16CNV_HH, + 0, + Opcode_ae_mulus4o4x16cnv_hh_encode_fns, 0, 0 }, + { "ae_mulus4o4x16cnv_hl", ICLASS_AE_MULUS4O4X16CNV_HL, + 0, + Opcode_ae_mulus4o4x16cnv_hl_encode_fns, 0, 0 }, + { "ae_mulus4o4x16cnv_lh", ICLASS_AE_MULUS4O4X16CNV_LH, + 0, + Opcode_ae_mulus4o4x16cnv_lh_encode_fns, 0, 0 }, + { "ae_mulus4o4x16cnv_ll", ICLASS_AE_MULUS4O4X16CNV_LL, + 0, + Opcode_ae_mulus4o4x16cnv_ll_encode_fns, 0, 0 }, + { "ae_mulaus4o4x16cnv_hh", ICLASS_AE_MULAUS4O4X16CNV_HH, + 0, + Opcode_ae_mulaus4o4x16cnv_hh_encode_fns, 0, 0 }, + { "ae_mulaus4o4x16cnv_hl", ICLASS_AE_MULAUS4O4X16CNV_HL, + 0, + Opcode_ae_mulaus4o4x16cnv_hl_encode_fns, 0, 0 }, + { "ae_mulaus4o4x16cnv_lh", ICLASS_AE_MULAUS4O4X16CNV_LH, + 0, + Opcode_ae_mulaus4o4x16cnv_lh_encode_fns, 0, 0 }, + { "ae_mulaus4o4x16cnv_ll", ICLASS_AE_MULAUS4O4X16CNV_LL, + 0, + Opcode_ae_mulaus4o4x16cnv_ll_encode_fns, 0, 0 }, + { "ae_mulsu8q8x8", ICLASS_AE_MULSU8Q8X8, + 0, + Opcode_ae_mulsu8q8x8_encode_fns, 0, 0 }, + { "ae_mulasu8q8x8", ICLASS_AE_MULASU8Q8X8, + 0, + Opcode_ae_mulasu8q8x8_encode_fns, 0, 0 }, + { "ae_mulsu4o8x8", ICLASS_AE_MULSU4O8X8, + 0, + Opcode_ae_mulsu4o8x8_encode_fns, 0, 0 }, + { "ae_mulasu4o8x8", ICLASS_AE_MULASU4O8X8, + 0, + Opcode_ae_mulasu4o8x8_encode_fns, 0, 0 }, + { "ae_mulsu8q8x8cnv_l", ICLASS_AE_MULSU8Q8X8CNV_L, + 0, + Opcode_ae_mulsu8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulasu8q8x8cnv_l", ICLASS_AE_MULASU8Q8X8CNV_L, + 0, + Opcode_ae_mulasu8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulsu8q8x8cnv_h", ICLASS_AE_MULSU8Q8X8CNV_H, + 0, + Opcode_ae_mulsu8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulasu8q8x8cnv_h", ICLASS_AE_MULASU8Q8X8CNV_H, + 0, + Opcode_ae_mulasu8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulsu2x4q8x8cnv_h", ICLASS_AE_MULSU2X4Q8X8CNV_H, + 0, + Opcode_ae_mulsu2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulasu2x4q8x8cnv_h", ICLASS_AE_MULASU2X4Q8X8CNV_H, + 0, + Opcode_ae_mulasu2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulsu2x4q8x8cnv_l", ICLASS_AE_MULSU2X4Q8X8CNV_L, + 0, + Opcode_ae_mulsu2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulasu2x4q8x8cnv_l", ICLASS_AE_MULASU2X4Q8X8CNV_L, + 0, + Opcode_ae_mulasu2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulsu4o8x8cnv_h", ICLASS_AE_MULSU4O8X8CNV_H, + 0, + Opcode_ae_mulsu4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulasu4o8x8cnv_h", ICLASS_AE_MULASU4O8X8CNV_H, + 0, + Opcode_ae_mulasu4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulsu4o8x8cnv_l", ICLASS_AE_MULSU4O8X8CNV_L, + 0, + Opcode_ae_mulsu4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulasu4o8x8cnv_l", ICLASS_AE_MULASU4O8X8CNV_L, + 0, + Opcode_ae_mulasu4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluuzb8q8x8", ICLASS_AE_MULUUZB8Q8X8, + 0, + Opcode_ae_muluuzb8q8x8_encode_fns, 0, 0 }, + { "ae_mulauuzb8q8x8", ICLASS_AE_MULAUUZB8Q8X8, + 0, + Opcode_ae_mulauuzb8q8x8_encode_fns, 0, 0 }, + { "ae_muluuzb4o8x8", ICLASS_AE_MULUUZB4O8X8, + 0, + Opcode_ae_muluuzb4o8x8_encode_fns, 0, 0 }, + { "ae_mulauuzb4o8x8", ICLASS_AE_MULAUUZB4O8X8, + 0, + Opcode_ae_mulauuzb4o8x8_encode_fns, 0, 0 }, + { "ae_muluuzb8q8x8cnv_l", ICLASS_AE_MULUUZB8Q8X8CNV_L, + 0, + Opcode_ae_muluuzb8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauuzb8q8x8cnv_l", ICLASS_AE_MULAUUZB8Q8X8CNV_L, + 0, + Opcode_ae_mulauuzb8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluuzb8q8x8cnv_h", ICLASS_AE_MULUUZB8Q8X8CNV_H, + 0, + Opcode_ae_muluuzb8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauuzb8q8x8cnv_h", ICLASS_AE_MULAUUZB8Q8X8CNV_H, + 0, + Opcode_ae_mulauuzb8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluuzb2x4q8x8cnv_h", ICLASS_AE_MULUUZB2X4Q8X8CNV_H, + 0, + Opcode_ae_muluuzb2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauuzb2x4q8x8cnv_h", ICLASS_AE_MULAUUZB2X4Q8X8CNV_H, + 0, + Opcode_ae_mulauuzb2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluuzb2x4q8x8cnv_l", ICLASS_AE_MULUUZB2X4Q8X8CNV_L, + 0, + Opcode_ae_muluuzb2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauuzb2x4q8x8cnv_l", ICLASS_AE_MULAUUZB2X4Q8X8CNV_L, + 0, + Opcode_ae_mulauuzb2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluuzb4o8x8cnv_h", ICLASS_AE_MULUUZB4O8X8CNV_H, + 0, + Opcode_ae_muluuzb4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauuzb4o8x8cnv_h", ICLASS_AE_MULAUUZB4O8X8CNV_H, + 0, + Opcode_ae_mulauuzb4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluuzb4o8x8cnv_l", ICLASS_AE_MULUUZB4O8X8CNV_L, + 0, + Opcode_ae_muluuzb4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauuzb4o8x8cnv_l", ICLASS_AE_MULAUUZB4O8X8CNV_L, + 0, + Opcode_ae_mulauuzb4o8x8cnv_l_encode_fns, 0, 0 }, + { "cvtsf16.l", ICLASS_CVTSF16_L, + 0, + Opcode_cvtsf16_l_encode_fns, 0, 0 }, + { "cvtsf16.h", ICLASS_CVTSF16_H, + 0, + Opcode_cvtsf16_h_encode_fns, 0, 0 }, + { "cvtf16s.l", ICLASS_CVTF16S_L, + 0, + Opcode_cvtf16s_l_encode_fns, 0, 0 }, + { "cvtf16s.h", ICLASS_CVTF16S_H, + 0, + Opcode_cvtf16s_h_encode_fns, 0, 0 }, + { "ae_movfcrfsrv", ICLASS_AE_MOVFCRFSRV, + 0, + Opcode_ae_movfcrfsrv_encode_fns, 0, 0 }, + { "ae_movvfcrfsr", ICLASS_AE_MOVVFCRFSR, + 0, + Opcode_ae_movvfcrfsr_encode_fns, 0, 0 }, + { "movt.s", ICLASS_MOVT_S, + 0, + Opcode_movt_s_encode_fns, 0, 0 }, + { "movf.s", ICLASS_MOVF_S, + 0, + Opcode_movf_s_encode_fns, 0, 0 }, + { "moveqz.s", ICLASS_MOVEQZ_S, + 0, + Opcode_moveqz_s_encode_fns, 0, 0 }, + { "movnez.s", ICLASS_MOVNEZ_S, + 0, + Opcode_movnez_s_encode_fns, 0, 0 }, + { "movgez.s", ICLASS_MOVGEZ_S, + 0, + Opcode_movgez_s_encode_fns, 0, 0 }, + { "movltz.s", ICLASS_MOVLTZ_S, + 0, + Opcode_movltz_s_encode_fns, 0, 0 }, + { "rfr", ICLASS_RFR, + 0, + Opcode_rfr_encode_fns, 0, 0 }, + { "wfr", ICLASS_WFR, + 0, + Opcode_wfr_encode_fns, 0, 0 }, + { "mul.s", ICLASS_MUL_S, + 0, + Opcode_mul_s_encode_fns, 0, 0 }, + { "madd.s", ICLASS_MADD_S, + 0, + Opcode_madd_s_encode_fns, 0, 0 }, + { "msub.s", ICLASS_MSUB_S, + 0, + Opcode_msub_s_encode_fns, 0, 0 }, + { "msubn.s", ICLASS_MSUBN_S, + 0, + Opcode_msubn_s_encode_fns, 0, 0 }, + { "maddn.s", ICLASS_MADDN_S, + 0, + Opcode_maddn_s_encode_fns, 0, 0 }, + { "add.s", ICLASS_ADD_S, + 0, + Opcode_add_s_encode_fns, 0, 0 }, + { "sub.s", ICLASS_SUB_S, + 0, + Opcode_sub_s_encode_fns, 0, 0 }, + { "ole.s", ICLASS_OLE_S, + 0, + Opcode_ole_s_encode_fns, 0, 0 }, + { "olt.s", ICLASS_OLT_S, + 0, + Opcode_olt_s_encode_fns, 0, 0 }, + { "oeq.s", ICLASS_OEQ_S, + 0, + Opcode_oeq_s_encode_fns, 0, 0 }, + { "un.s", ICLASS_UN_S, + 0, + Opcode_un_s_encode_fns, 0, 0 }, + { "ule.s", ICLASS_ULE_S, + 0, + Opcode_ule_s_encode_fns, 0, 0 }, + { "ult.s", ICLASS_ULT_S, + 0, + Opcode_ult_s_encode_fns, 0, 0 }, + { "ueq.s", ICLASS_UEQ_S, + 0, + Opcode_ueq_s_encode_fns, 0, 0 }, + { "nexp01.s", ICLASS_NEXP01_S, + 0, + Opcode_nexp01_s_encode_fns, 0, 0 }, + { "mksadj.s", ICLASS_MKSADJ_S, + 0, + Opcode_mksadj_s_encode_fns, 0, 0 }, + { "mkdadj.s", ICLASS_MKDADJ_S, + 0, + Opcode_mkdadj_s_encode_fns, 0, 0 }, + { "div0.s", ICLASS_DIV0_S, + 0, + Opcode_div0_s_encode_fns, 0, 0 }, + { "sqrt0.s", ICLASS_SQRT0_S, + 0, + Opcode_sqrt0_s_encode_fns, 0, 0 }, + { "recip0.s", ICLASS_RECIP0_S, + 0, + Opcode_recip0_s_encode_fns, 0, 0 }, + { "rsqrt0.s", ICLASS_RSQRT0_S, + 0, + Opcode_rsqrt0_s_encode_fns, 0, 0 }, + { "divn.s", ICLASS_DIVN_S, + 0, + Opcode_divn_s_encode_fns, 0, 0 }, + { "addexp.s", ICLASS_ADDEXP_S, + 0, + Opcode_addexp_s_encode_fns, 0, 0 }, + { "addexpm.s", ICLASS_ADDEXPM_S, + 0, + Opcode_addexpm_s_encode_fns, 0, 0 }, + { "min.s", ICLASS_MIN_S, + 0, + Opcode_min_s_encode_fns, 0, 0 }, + { "max.s", ICLASS_MAX_S, + 0, + Opcode_max_s_encode_fns, 0, 0 }, + { "mulmux.s", ICLASS_MULMUX_S, + 0, + Opcode_mulmux_s_encode_fns, 0, 0 }, + { "maddmux.s", ICLASS_MADDMUX_S, + 0, + Opcode_maddmux_s_encode_fns, 0, 0 }, + { "trunc.s", ICLASS_TRUNC_S, + 0, + Opcode_trunc_s_encode_fns, 0, 0 }, + { "utrunc.s", ICLASS_UTRUNC_S, + 0, + Opcode_utrunc_s_encode_fns, 0, 0 }, + { "trunc.sx2", ICLASS_TRUNC_SX2, + 0, + Opcode_trunc_sx2_encode_fns, 0, 0 }, + { "utrunc.sx2", ICLASS_UTRUNC_SX2, + 0, + Opcode_utrunc_sx2_encode_fns, 0, 0 }, + { "ficeil.s", ICLASS_FICEIL_S, + 0, + Opcode_ficeil_s_encode_fns, 0, 0 }, + { "fifloor.s", ICLASS_FIFLOOR_S, + 0, + Opcode_fifloor_s_encode_fns, 0, 0 }, + { "firint.s", ICLASS_FIRINT_S, + 0, + Opcode_firint_s_encode_fns, 0, 0 }, + { "firound.s", ICLASS_FIROUND_S, + 0, + Opcode_firound_s_encode_fns, 0, 0 }, + { "fitrunc.s", ICLASS_FITRUNC_S, + 0, + Opcode_fitrunc_s_encode_fns, 0, 0 }, + { "float.s", ICLASS_FLOAT_S, + 0, + Opcode_float_s_encode_fns, 0, 0 }, + { "ufloat.s", ICLASS_UFLOAT_S, + 0, + Opcode_ufloat_s_encode_fns, 0, 0 }, + { "float.sx2", ICLASS_FLOAT_SX2, + 0, + Opcode_float_sx2_encode_fns, 0, 0 }, + { "ufloat.sx2", ICLASS_UFLOAT_SX2, + 0, + Opcode_ufloat_sx2_encode_fns, 0, 0 }, + { "abs.s", ICLASS_ABS_S, + 0, + Opcode_abs_s_encode_fns, 0, 0 }, + { "neg.s", ICLASS_NEG_S, + 0, + Opcode_neg_s_encode_fns, 0, 0 }, + { "conjc.s", ICLASS_CONJC_S, + 0, + Opcode_conjc_s_encode_fns, 0, 0 }, + { "muljc.s", ICLASS_MULJC_S, + 0, + Opcode_muljc_s_encode_fns, 0, 0 }, + { "const.s", ICLASS_CONST_S, + 0, + Opcode_const_s_encode_fns, 0, 0 }, + { "clsfy.s", ICLASS_CLSFY_S, + 0, + Opcode_clsfy_s_encode_fns, 0, 0 }, + { "minnum.s", ICLASS_MINNUM_S, + 0, + Opcode_minnum_s_encode_fns, 0, 0 }, + { "maxnum.s", ICLASS_MAXNUM_S, + 0, + Opcode_maxnum_s_encode_fns, 0, 0 }, + { "addandsub.s", ICLASS_ADDANDSUB_S, + 0, + Opcode_addandsub_s_encode_fns, 0, 0 }, + { "addandsubjc.s", ICLASS_ADDANDSUBJC_S, + 0, + Opcode_addandsubjc_s_encode_fns, 0, 0 }, + { "add_hl_lh.s", ICLASS_ADD_HL_LH_S, + 0, + Opcode_add_hl_lh_s_encode_fns, 0, 0 }, + { "madda.s", ICLASS_MADDA_S, + 0, + Opcode_madda_s_encode_fns, 0, 0 }, + { "frexp.s", ICLASS_FREXP_S, + 0, + Opcode_frexp_s_encode_fns, 0, 0 }, + { "floatexp.s", ICLASS_FLOATEXP_S, + 0, + Opcode_floatexp_s_encode_fns, 0, 0 }, + { "minnumabs.s", ICLASS_MINNUMABS_S, + 0, + Opcode_minnumabs_s_encode_fns, 0, 0 }, + { "maxnumabs.s", ICLASS_MAXNUMABS_S, + 0, + Opcode_maxnumabs_s_encode_fns, 0, 0 }, + { "mulq.s", ICLASS_MULQ_S, + 0, + Opcode_mulq_s_encode_fns, 0, 0 }, + { "maddq.s", ICLASS_MADDQ_S, + 0, + Opcode_maddq_s_encode_fns, 0, 0 }, + { "msubq.s", ICLASS_MSUBQ_S, + 0, + Opcode_msubq_s_encode_fns, 0, 0 }, + { "mulmuxq.s", ICLASS_MULMUXQ_S, + 0, + Opcode_mulmuxq_s_encode_fns, 0, 0 }, + { "maddmuxq.s", ICLASS_MADDMUXQ_S, + 0, + Opcode_maddmuxq_s_encode_fns, 0, 0 }, + { "bmaxnum.s", ICLASS_BMAXNUM_S, + 0, + Opcode_bmaxnum_s_encode_fns, 0, 0 }, + { "bminnum.s", ICLASS_BMINNUM_S, + 0, + Opcode_bminnum_s_encode_fns, 0, 0 }, + { "bmaxnumabs.s", ICLASS_BMAXNUMABS_S, + 0, + Opcode_bmaxnumabs_s_encode_fns, 0, 0 }, + { "bminnumabs.s", ICLASS_BMINNUMABS_S, + 0, + Opcode_bminnumabs_s_encode_fns, 0, 0 }, + { "abs.sx2x2", ICLASS_ABS_SX2X2, + 0, + Opcode_abs_sx2x2_encode_fns, 0, 0 }, + { "neg.sx2x2", ICLASS_NEG_SX2X2, + 0, + Opcode_neg_sx2x2_encode_fns, 0, 0 }, + { "conjc.sx2x2", ICLASS_CONJC_SX2X2, + 0, + Opcode_conjc_sx2x2_encode_fns, 0, 0 }, + { "muljc.sx2x2", ICLASS_MULJC_SX2X2, + 0, + Opcode_muljc_sx2x2_encode_fns, 0, 0 }, + { "const.sx2x2", ICLASS_CONST_SX2X2, + 0, + Opcode_const_sx2x2_encode_fns, 0, 0 }, + { "add.sx2x2", ICLASS_ADD_SX2X2, + 0, + Opcode_add_sx2x2_encode_fns, 0, 0 }, + { "sub.sx2x2", ICLASS_SUB_SX2X2, + 0, + Opcode_sub_sx2x2_encode_fns, 0, 0 }, + { "mul.sx2x2", ICLASS_MUL_SX2X2, + 0, + Opcode_mul_sx2x2_encode_fns, 0, 0 }, + { "madd.sx2x2", ICLASS_MADD_SX2X2, + 0, + Opcode_madd_sx2x2_encode_fns, 0, 0 }, + { "msub.sx2x2", ICLASS_MSUB_SX2X2, + 0, + Opcode_msub_sx2x2_encode_fns, 0, 0 }, + { "mulmux.sx2x2", ICLASS_MULMUX_SX2X2, + 0, + Opcode_mulmux_sx2x2_encode_fns, 0, 0 }, + { "maddmux.sx2x2", ICLASS_MADDMUX_SX2X2, + 0, + Opcode_maddmux_sx2x2_encode_fns, 0, 0 }, + { "abs.h", ICLASS_ABS_H, + 0, + Opcode_abs_h_encode_fns, 0, 0 }, + { "addexp.h", ICLASS_ADDEXP_H, + 0, + Opcode_addexp_h_encode_fns, 0, 0 }, + { "addexpm.h", ICLASS_ADDEXPM_H, + 0, + Opcode_addexpm_h_encode_fns, 0, 0 }, + { "clsfy.h", ICLASS_CLSFY_H, + 0, + Opcode_clsfy_h_encode_fns, 0, 0 }, + { "conjc.h", ICLASS_CONJC_H, + 0, + Opcode_conjc_h_encode_fns, 0, 0 }, + { "const.h", ICLASS_CONST_H, + 0, + Opcode_const_h_encode_fns, 0, 0 }, + { "min.h", ICLASS_MIN_H, + 0, + Opcode_min_h_encode_fns, 0, 0 }, + { "max.h", ICLASS_MAX_H, + 0, + Opcode_max_h_encode_fns, 0, 0 }, + { "minnum.h", ICLASS_MINNUM_H, + 0, + Opcode_minnum_h_encode_fns, 0, 0 }, + { "maxnum.h", ICLASS_MAXNUM_H, + 0, + Opcode_maxnum_h_encode_fns, 0, 0 }, + { "muljc.h", ICLASS_MULJC_H, + 0, + Opcode_muljc_h_encode_fns, 0, 0 }, + { "neg.h", ICLASS_NEG_H, + 0, + Opcode_neg_h_encode_fns, 0, 0 }, + { "oeq.h", ICLASS_OEQ_H, + 0, + Opcode_oeq_h_encode_fns, 0, 0 }, + { "ole.h", ICLASS_OLE_H, + 0, + Opcode_ole_h_encode_fns, 0, 0 }, + { "olt.h", ICLASS_OLT_H, + 0, + Opcode_olt_h_encode_fns, 0, 0 }, + { "ueq.h", ICLASS_UEQ_H, + 0, + Opcode_ueq_h_encode_fns, 0, 0 }, + { "ule.h", ICLASS_ULE_H, + 0, + Opcode_ule_h_encode_fns, 0, 0 }, + { "ult.h", ICLASS_ULT_H, + 0, + Opcode_ult_h_encode_fns, 0, 0 }, + { "un.h", ICLASS_UN_H, + 0, + Opcode_un_h_encode_fns, 0, 0 }, + { "div0.h", ICLASS_DIV0_H, + 0, + Opcode_div0_h_encode_fns, 0, 0 }, + { "ficeil.h", ICLASS_FICEIL_H, + 0, + Opcode_ficeil_h_encode_fns, 0, 0 }, + { "fifloor.h", ICLASS_FIFLOOR_H, + 0, + Opcode_fifloor_h_encode_fns, 0, 0 }, + { "firint.h", ICLASS_FIRINT_H, + 0, + Opcode_firint_h_encode_fns, 0, 0 }, + { "firound.h", ICLASS_FIROUND_H, + 0, + Opcode_firound_h_encode_fns, 0, 0 }, + { "fitrunc.h", ICLASS_FITRUNC_H, + 0, + Opcode_fitrunc_h_encode_fns, 0, 0 }, + { "mkdadj.h", ICLASS_MKDADJ_H, + 0, + Opcode_mkdadj_h_encode_fns, 0, 0 }, + { "mksadj.h", ICLASS_MKSADJ_H, + 0, + Opcode_mksadj_h_encode_fns, 0, 0 }, + { "nexp0.h", ICLASS_NEXP0_H, + 0, + Opcode_nexp0_h_encode_fns, 0, 0 }, + { "nexp01.h", ICLASS_NEXP01_H, + 0, + Opcode_nexp01_h_encode_fns, 0, 0 }, + { "recip0.h", ICLASS_RECIP0_H, + 0, + Opcode_recip0_h_encode_fns, 0, 0 }, + { "rsqrt0.h", ICLASS_RSQRT0_H, + 0, + Opcode_rsqrt0_h_encode_fns, 0, 0 }, + { "sqrt0.h", ICLASS_SQRT0_H, + 0, + Opcode_sqrt0_h_encode_fns, 0, 0 }, + { "float16.h", ICLASS_FLOAT16_H, + 0, + Opcode_float16_h_encode_fns, 0, 0 }, + { "ufloat16.h", ICLASS_UFLOAT16_H, + 0, + Opcode_ufloat16_h_encode_fns, 0, 0 }, + { "trunc16.h", ICLASS_TRUNC16_H, + 0, + Opcode_trunc16_h_encode_fns, 0, 0 }, + { "utrunc16.h", ICLASS_UTRUNC16_H, + 0, + Opcode_utrunc16_h_encode_fns, 0, 0 }, + { "float16.hx4", ICLASS_FLOAT16_HX4, + 0, + Opcode_float16_hx4_encode_fns, 0, 0 }, + { "ufloat16.hx4", ICLASS_UFLOAT16_HX4, + 0, + Opcode_ufloat16_hx4_encode_fns, 0, 0 }, + { "trunc16.hx4", ICLASS_TRUNC16_HX4, + 0, + Opcode_trunc16_hx4_encode_fns, 0, 0 }, + { "utrunc16.hx4", ICLASS_UTRUNC16_HX4, + 0, + Opcode_utrunc16_hx4_encode_fns, 0, 0 }, + { "add.h", ICLASS_ADD_H, + 0, + Opcode_add_h_encode_fns, 0, 0 }, + { "sub.h", ICLASS_SUB_H, + 0, + Opcode_sub_h_encode_fns, 0, 0 }, + { "mul.h", ICLASS_MUL_H, + 0, + Opcode_mul_h_encode_fns, 0, 0 }, + { "madd.h", ICLASS_MADD_H, + 0, + Opcode_madd_h_encode_fns, 0, 0 }, + { "msub.h", ICLASS_MSUB_H, + 0, + Opcode_msub_h_encode_fns, 0, 0 }, + { "maddn.h", ICLASS_MADDN_H, + 0, + Opcode_maddn_h_encode_fns, 0, 0 }, + { "msubn.h", ICLASS_MSUBN_H, + 0, + Opcode_msubn_h_encode_fns, 0, 0 }, + { "divn.h", ICLASS_DIVN_H, + 0, + Opcode_divn_h_encode_fns, 0, 0 }, + { "rminnum.h", ICLASS_RMINNUM_H, + 0, + Opcode_rminnum_h_encode_fns, 0, 0 }, + { "rmaxnum.h", ICLASS_RMAXNUM_H, + 0, + Opcode_rmaxnum_h_encode_fns, 0, 0 }, + { "abs.hx4x2", ICLASS_ABS_HX4X2, + 0, + Opcode_abs_hx4x2_encode_fns, 0, 0 }, + { "neg.hx4x2", ICLASS_NEG_HX4X2, + 0, + Opcode_neg_hx4x2_encode_fns, 0, 0 }, + { "conjc.hx4x2", ICLASS_CONJC_HX4X2, + 0, + Opcode_conjc_hx4x2_encode_fns, 0, 0 }, + { "const.hx4x2", ICLASS_CONST_HX4X2, + 0, + Opcode_const_hx4x2_encode_fns, 0, 0 }, + { "muljc.hx4x2", ICLASS_MULJC_HX4X2, + 0, + Opcode_muljc_hx4x2_encode_fns, 0, 0 }, + { "add.hx4x2", ICLASS_ADD_HX4X2, + 0, + Opcode_add_hx4x2_encode_fns, 0, 0 }, + { "sub.hx4x2", ICLASS_SUB_HX4X2, + 0, + Opcode_sub_hx4x2_encode_fns, 0, 0 }, + { "mul.hx4x2", ICLASS_MUL_HX4X2, + 0, + Opcode_mul_hx4x2_encode_fns, 0, 0 }, + { "madd.hx4x2", ICLASS_MADD_HX4X2, + 0, + Opcode_madd_hx4x2_encode_fns, 0, 0 }, + { "msub.hx4x2", ICLASS_MSUB_HX4X2, + 0, + Opcode_msub_hx4x2_encode_fns, 0, 0 }, + { "mulq.h", ICLASS_MULQ_H, + 0, + Opcode_mulq_h_encode_fns, 0, 0 }, + { "maddq.h", ICLASS_MADDQ_H, + 0, + Opcode_maddq_h_encode_fns, 0, 0 }, + { "mulcnvh.hx4x2", ICLASS_MULCNVH_HX4X2, + 0, + Opcode_mulcnvh_hx4x2_encode_fns, 0, 0 }, + { "mulacnvh.hx4x2", ICLASS_MULACNVH_HX4X2, + 0, + Opcode_mulacnvh_hx4x2_encode_fns, 0, 0 }, + { "mulcnvl.hx4x2", ICLASS_MULCNVL_HX4X2, + 0, + Opcode_mulcnvl_hx4x2_encode_fns, 0, 0 }, + { "mulacnvl.hx4x2", ICLASS_MULACNVL_HX4X2, + 0, + Opcode_mulacnvl_hx4x2_encode_fns, 0, 0 } +}; + +enum xtensa_opcode_id { + OPCODE_EXCW, + OPCODE_RFE, + OPCODE_RFDE, + OPCODE_SYSCALL, + OPCODE_CALL12, + OPCODE_CALL8, + OPCODE_CALL4, + OPCODE_CALLX12, + OPCODE_CALLX8, + OPCODE_CALLX4, + OPCODE_ENTRY, + OPCODE_MOVSP, + OPCODE_ROTW, + OPCODE_RETW, + OPCODE_RETW_N, + OPCODE_RFWO, + OPCODE_RFWU, + OPCODE_L32E, + OPCODE_S32E, + OPCODE_RSR_WINDOWBASE, + OPCODE_WSR_WINDOWBASE, + OPCODE_XSR_WINDOWBASE, + OPCODE_RSR_WINDOWSTART, + OPCODE_WSR_WINDOWSTART, + OPCODE_XSR_WINDOWSTART, + OPCODE_ADD_N, + OPCODE_ADDI_N, + OPCODE_BEQZ_N, + OPCODE_BNEZ_N, + OPCODE_ILL_N, + OPCODE_L32I_N, + OPCODE_MOV_N, + OPCODE_MOVI_N, + OPCODE_NOP_N, + OPCODE_RET_N, + OPCODE_S32I_N, + OPCODE_RUR_THREADPTR, + OPCODE_WUR_THREADPTR, + OPCODE_ADDI, + OPCODE_ADDMI, + OPCODE_ADD, + OPCODE_ADDX2, + OPCODE_ADDX4, + OPCODE_ADDX8, + OPCODE_SUB, + OPCODE_SUBX2, + OPCODE_SUBX4, + OPCODE_SUBX8, + OPCODE_AND, + OPCODE_OR, + OPCODE_XOR, + OPCODE_BEQI, + OPCODE_BGEI, + OPCODE_BLTI, + OPCODE_BNEI, + OPCODE_BBCI, + OPCODE_BBSI, + OPCODE_BGEUI, + OPCODE_BLTUI, + OPCODE_BALL, + OPCODE_BANY, + OPCODE_BBC, + OPCODE_BBS, + OPCODE_BEQ, + OPCODE_BGE, + OPCODE_BGEU, + OPCODE_BLT, + OPCODE_BLTU, + OPCODE_BNALL, + OPCODE_BNE, + OPCODE_BNONE, + OPCODE_BEQZ, + OPCODE_BGEZ, + OPCODE_BLTZ, + OPCODE_BNEZ, + OPCODE_CALL0, + OPCODE_CALLX0, + OPCODE_EXTUI, + OPCODE_ILL, + OPCODE_J, + OPCODE_JX, + OPCODE_L16UI, + OPCODE_L16SI, + OPCODE_L32I, + OPCODE_L32R, + OPCODE_L8UI, + OPCODE_LOOP, + OPCODE_LOOPGTZ, + OPCODE_LOOPNEZ, + OPCODE_MOVI, + OPCODE_MOVEQZ, + OPCODE_MOVGEZ, + OPCODE_MOVLTZ, + OPCODE_MOVNEZ, + OPCODE_ABS, + OPCODE_NEG, + OPCODE_NOP, + OPCODE_L32EX, + OPCODE_S32EX, + OPCODE_GETEX, + OPCODE_CLREX, + OPCODE_RET, + OPCODE_SIMCALL, + OPCODE_S16I, + OPCODE_S32I, + OPCODE_S32NB, + OPCODE_S8I, + OPCODE_SSA8B, + OPCODE_SSA8L, + OPCODE_SSL, + OPCODE_SSR, + OPCODE_SSAI, + OPCODE_SLL, + OPCODE_SRC, + OPCODE_SRA, + OPCODE_SRL, + OPCODE_SLLI, + OPCODE_SRAI, + OPCODE_SRLI, + OPCODE_MEMW, + OPCODE_EXTW, + OPCODE_ISYNC, + OPCODE_DSYNC, + OPCODE_ESYNC, + OPCODE_RSYNC, + OPCODE_RSIL, + OPCODE_RSR_LEND, + OPCODE_WSR_LEND, + OPCODE_XSR_LEND, + OPCODE_RSR_LCOUNT, + OPCODE_WSR_LCOUNT, + OPCODE_XSR_LCOUNT, + OPCODE_RSR_LBEG, + OPCODE_WSR_LBEG, + OPCODE_XSR_LBEG, + OPCODE_RSR_SAR, + OPCODE_WSR_SAR, + OPCODE_XSR_SAR, + OPCODE_RSR_MEMCTL, + OPCODE_WSR_MEMCTL, + OPCODE_XSR_MEMCTL, + OPCODE_RSR_CONFIGID0, + OPCODE_WSR_CONFIGID0, + OPCODE_RSR_CONFIGID1, + OPCODE_RSR_PS, + OPCODE_WSR_PS, + OPCODE_XSR_PS, + OPCODE_RSR_EPC1, + OPCODE_WSR_EPC1, + OPCODE_XSR_EPC1, + OPCODE_RSR_EXCSAVE1, + OPCODE_WSR_EXCSAVE1, + OPCODE_XSR_EXCSAVE1, + OPCODE_RSR_EPC2, + OPCODE_WSR_EPC2, + OPCODE_XSR_EPC2, + OPCODE_RSR_EXCSAVE2, + OPCODE_WSR_EXCSAVE2, + OPCODE_XSR_EXCSAVE2, + OPCODE_RSR_EPC3, + OPCODE_WSR_EPC3, + OPCODE_XSR_EPC3, + OPCODE_RSR_EXCSAVE3, + OPCODE_WSR_EXCSAVE3, + OPCODE_XSR_EXCSAVE3, + OPCODE_RSR_EPC4, + OPCODE_WSR_EPC4, + OPCODE_XSR_EPC4, + OPCODE_RSR_EXCSAVE4, + OPCODE_WSR_EXCSAVE4, + OPCODE_XSR_EXCSAVE4, + OPCODE_RSR_EPC5, + OPCODE_WSR_EPC5, + OPCODE_XSR_EPC5, + OPCODE_RSR_EXCSAVE5, + OPCODE_WSR_EXCSAVE5, + OPCODE_XSR_EXCSAVE5, + OPCODE_RSR_EPC6, + OPCODE_WSR_EPC6, + OPCODE_XSR_EPC6, + OPCODE_RSR_EXCSAVE6, + OPCODE_WSR_EXCSAVE6, + OPCODE_XSR_EXCSAVE6, + OPCODE_RSR_EPS2, + OPCODE_WSR_EPS2, + OPCODE_XSR_EPS2, + OPCODE_RSR_EPS3, + OPCODE_WSR_EPS3, + OPCODE_XSR_EPS3, + OPCODE_RSR_EPS4, + OPCODE_WSR_EPS4, + OPCODE_XSR_EPS4, + OPCODE_RSR_EPS5, + OPCODE_WSR_EPS5, + OPCODE_XSR_EPS5, + OPCODE_RSR_EPS6, + OPCODE_WSR_EPS6, + OPCODE_XSR_EPS6, + OPCODE_RSR_EXCVADDR, + OPCODE_WSR_EXCVADDR, + OPCODE_XSR_EXCVADDR, + OPCODE_RSR_DEPC, + OPCODE_WSR_DEPC, + OPCODE_XSR_DEPC, + OPCODE_RSR_EXCCAUSE, + OPCODE_WSR_EXCCAUSE, + OPCODE_XSR_EXCCAUSE, + OPCODE_RSR_MISC0, + OPCODE_WSR_MISC0, + OPCODE_XSR_MISC0, + OPCODE_RSR_MISC1, + OPCODE_WSR_MISC1, + OPCODE_XSR_MISC1, + OPCODE_RSR_MISC2, + OPCODE_WSR_MISC2, + OPCODE_XSR_MISC2, + OPCODE_RSR_MISC3, + OPCODE_WSR_MISC3, + OPCODE_XSR_MISC3, + OPCODE_RSR_PRID, + OPCODE_RSR_VECBASE, + OPCODE_WSR_VECBASE, + OPCODE_XSR_VECBASE, + OPCODE_RSR_MPUCFG, + OPCODE_WSR_MPUCFG, + OPCODE_SALT, + OPCODE_SALTU, + OPCODE_RSR_OPMODE, + OPCODE_WSR_OPMODE, + OPCODE_XSR_OPMODE, + OPCODE_MUL16S, + OPCODE_MUL16U, + OPCODE_MULL, + OPCODE_RFI, + OPCODE_WAITI, + OPCODE_RSR_INTERRUPT, + OPCODE_WSR_INTSET, + OPCODE_WSR_INTCLEAR, + OPCODE_RSR_INTENABLE, + OPCODE_WSR_INTENABLE, + OPCODE_XSR_INTENABLE, + OPCODE_BREAK, + OPCODE_BREAK_N, + OPCODE_RSR_DBREAKA0, + OPCODE_WSR_DBREAKA0, + OPCODE_XSR_DBREAKA0, + OPCODE_RSR_DBREAKC0, + OPCODE_WSR_DBREAKC0, + OPCODE_XSR_DBREAKC0, + OPCODE_RSR_DBREAKA1, + OPCODE_WSR_DBREAKA1, + OPCODE_XSR_DBREAKA1, + OPCODE_RSR_DBREAKC1, + OPCODE_WSR_DBREAKC1, + OPCODE_XSR_DBREAKC1, + OPCODE_RSR_IBREAKA0, + OPCODE_WSR_IBREAKA0, + OPCODE_XSR_IBREAKA0, + OPCODE_RSR_IBREAKA1, + OPCODE_WSR_IBREAKA1, + OPCODE_XSR_IBREAKA1, + OPCODE_RSR_IBREAKENABLE, + OPCODE_WSR_IBREAKENABLE, + OPCODE_XSR_IBREAKENABLE, + OPCODE_RSR_DEBUGCAUSE, + OPCODE_WSR_DEBUGCAUSE, + OPCODE_XSR_DEBUGCAUSE, + OPCODE_RSR_ICOUNT, + OPCODE_WSR_ICOUNT, + OPCODE_XSR_ICOUNT, + OPCODE_RSR_ICOUNTLEVEL, + OPCODE_WSR_ICOUNTLEVEL, + OPCODE_XSR_ICOUNTLEVEL, + OPCODE_RSR_DDR, + OPCODE_WSR_DDR, + OPCODE_XSR_DDR, + OPCODE_LDDR32_P, + OPCODE_SDDR32_P, + OPCODE_RFDO, + OPCODE_RFDD, + OPCODE_WSR_MMID, + OPCODE_ANDB, + OPCODE_ANDBC, + OPCODE_ORB, + OPCODE_ORBC, + OPCODE_XORB, + OPCODE_ALL4, + OPCODE_ANY4, + OPCODE_ALL8, + OPCODE_ANY8, + OPCODE_BF, + OPCODE_BT, + OPCODE_MOVF, + OPCODE_MOVT, + OPCODE_RSR_BR, + OPCODE_WSR_BR, + OPCODE_XSR_BR, + OPCODE_RSR_CCOUNT, + OPCODE_WSR_CCOUNT, + OPCODE_XSR_CCOUNT, + OPCODE_RSR_CCOMPARE0, + OPCODE_WSR_CCOMPARE0, + OPCODE_XSR_CCOMPARE0, + OPCODE_RSR_CCOMPARE1, + OPCODE_WSR_CCOMPARE1, + OPCODE_XSR_CCOMPARE1, + OPCODE_RSR_CCOMPARE2, + OPCODE_WSR_CCOMPARE2, + OPCODE_XSR_CCOMPARE2, + OPCODE_IHI, + OPCODE_IPF, + OPCODE_IHU, + OPCODE_IIU, + OPCODE_IPFL, + OPCODE_III, + OPCODE_LICT, + OPCODE_LICW, + OPCODE_SICT, + OPCODE_SICW, + OPCODE_DHWB, + OPCODE_DHWBI, + OPCODE_DIWBUI_P, + OPCODE_DIWB, + OPCODE_DIWBI, + OPCODE_DHI, + OPCODE_DII, + OPCODE_DPFR, + OPCODE_DPFRO, + OPCODE_DPFW, + OPCODE_DPFWO, + OPCODE_DPFM_B, + OPCODE_DPFM_BF, + OPCODE_DPFR_B, + OPCODE_DPFR_BF, + OPCODE_DPFW_B, + OPCODE_DPFW_BF, + OPCODE_PFNXT_F, + OPCODE_DHI_B, + OPCODE_DHWBI_B, + OPCODE_DHWB_B, + OPCODE_PFEND_A, + OPCODE_PFEND_O, + OPCODE_PFWAIT_A, + OPCODE_PFWAIT_R, + OPCODE_DHU, + OPCODE_DIU, + OPCODE_DPFL, + OPCODE_SDCT, + OPCODE_LDCT, + OPCODE_SDCW, + OPCODE_LDCW, + OPCODE_RSR_PREFCTL, + OPCODE_WSR_PREFCTL, + OPCODE_XSR_PREFCTL, + OPCODE_WSR_CACHEADRDIS, + OPCODE_RSR_CACHEADRDIS, + OPCODE_XSR_CACHEADRDIS, + OPCODE_RPTLB0, + OPCODE_PPTLB, + OPCODE_RPTLB1, + OPCODE_WPTLB, + OPCODE_RSR_MPUENB, + OPCODE_WSR_MPUENB, + OPCODE_XSR_MPUENB, + OPCODE_RSR_CPENABLE, + OPCODE_WSR_CPENABLE, + OPCODE_XSR_CPENABLE, + OPCODE_CLAMPS, + OPCODE_MAX, + OPCODE_MAXU, + OPCODE_MIN, + OPCODE_MINU, + OPCODE_NSA, + OPCODE_NSAU, + OPCODE_SEXT, + OPCODE_L32AI, + OPCODE_S32RI, + OPCODE_RSR_ATOMCTL, + OPCODE_WSR_ATOMCTL, + OPCODE_XSR_ATOMCTL, + OPCODE_QUOS, + OPCODE_QUOU, + OPCODE_REMS, + OPCODE_REMU, + OPCODE_RSR_ERACCESS, + OPCODE_WSR_ERACCESS, + OPCODE_XSR_ERACCESS, + OPCODE_RER, + OPCODE_WER, + OPCODE_BEQZ_W15, + OPCODE_BGEZ_W15, + OPCODE_BLTZ_W15, + OPCODE_BNEZ_W15, + OPCODE_BEQI_W15, + OPCODE_BGEI_W15, + OPCODE_BLTI_W15, + OPCODE_BNEI_W15, + OPCODE_BGEUI_W15, + OPCODE_BLTUI_W15, + OPCODE_BBCI_W15, + OPCODE_BBSI_W15, + OPCODE_BALL_W15, + OPCODE_BANY_W15, + OPCODE_BBC_W15, + OPCODE_BBS_W15, + OPCODE_BEQ_W15, + OPCODE_BGEU_W15, + OPCODE_BGE_W15, + OPCODE_BLTU_W15, + OPCODE_BLT_W15, + OPCODE_BNALL_W15, + OPCODE_BNE_W15, + OPCODE_BNONE_W15, + OPCODE_RUR_AE_OVF_SAR, + OPCODE_WUR_AE_OVF_SAR, + OPCODE_RUR_AE_BITHEAD, + OPCODE_WUR_AE_BITHEAD, + OPCODE_RUR_AE_TS_FTS_BU_BP, + OPCODE_WUR_AE_TS_FTS_BU_BP, + OPCODE_RUR_AE_CW_SD_NO, + OPCODE_WUR_AE_CW_SD_NO, + OPCODE_RUR_AE_CBEGIN0, + OPCODE_WUR_AE_CBEGIN0, + OPCODE_RUR_AE_CEND0, + OPCODE_WUR_AE_CEND0, + OPCODE_RUR_AE_CBEGIN1, + OPCODE_WUR_AE_CBEGIN1, + OPCODE_RUR_AE_CEND1, + OPCODE_WUR_AE_CEND1, + OPCODE_RUR_AE_CBEGIN2, + OPCODE_WUR_AE_CBEGIN2, + OPCODE_RUR_AE_CEND2, + OPCODE_WUR_AE_CEND2, + OPCODE_AE_SEXT16, + OPCODE_AE_ZEXT16, + OPCODE_AE_ZEXT8, + OPCODE_AE_CLAMPS16, + OPCODE_RUR_FCR, + OPCODE_WUR_FCR, + OPCODE_RUR_FSR, + OPCODE_WUR_FSR, + OPCODE_RUR_EXPSTATE, + OPCODE_WUR_EXPSTATE, + OPCODE_READ_IMPWIRE, + OPCODE_SETB_EXPSTATE, + OPCODE_CLRB_EXPSTATE, + OPCODE_WRMSK_EXPSTATE, + OPCODE_RUR_AE_OVERFLOW, + OPCODE_WUR_AE_OVERFLOW, + OPCODE_RUR_AE_SAR, + OPCODE_WUR_AE_SAR, + OPCODE_RUR_AE_BITPTR, + OPCODE_WUR_AE_BITPTR, + OPCODE_RUR_AE_BITSUSED, + OPCODE_WUR_AE_BITSUSED, + OPCODE_RUR_AE_TABLESIZE, + OPCODE_WUR_AE_TABLESIZE, + OPCODE_RUR_AE_FIRST_TS, + OPCODE_WUR_AE_FIRST_TS, + OPCODE_RUR_AE_NEXTOFFSET, + OPCODE_WUR_AE_NEXTOFFSET, + OPCODE_RUR_AE_SEARCHDONE, + OPCODE_WUR_AE_SEARCHDONE, + OPCODE_RUR_AE_CWRAP, + OPCODE_WUR_AE_CWRAP, + OPCODE_AE_L8X4F_I, + OPCODE_AE_L8X4F_IP, + OPCODE_AE_L8X4F_X, + OPCODE_AE_L8X4F_XP, + OPCODE_AE_L8X4S_I, + OPCODE_AE_L8X4S_IP, + OPCODE_AE_L8X4S_X, + OPCODE_AE_L8X4S_XP, + OPCODE_AE_L8X4U_I, + OPCODE_AE_L8X4U_IP, + OPCODE_AE_L8X4U_X, + OPCODE_AE_L8X4U_XP, + OPCODE_AE_L16M_XC, + OPCODE_AE_L16M_XC1, + OPCODE_AE_L16M_I, + OPCODE_AE_L16M_IU, + OPCODE_AE_L16M_X, + OPCODE_AE_L16M_XU, + OPCODE_AE_L16_XC, + OPCODE_AE_L16_XC1, + OPCODE_AE_L16_I, + OPCODE_AE_L16_IP, + OPCODE_AE_L16_X, + OPCODE_AE_L16_XP, + OPCODE_AE_L8_XC, + OPCODE_AE_L8_XC1, + OPCODE_AE_L8_I, + OPCODE_AE_L8_IP, + OPCODE_AE_L8_X, + OPCODE_AE_L8_XP, + OPCODE_AE_L32F24_XC, + OPCODE_AE_L32F24_XC1, + OPCODE_AE_L32F24_I, + OPCODE_AE_L32F24_IP, + OPCODE_AE_L32F24_X, + OPCODE_AE_L32F24_XP, + OPCODE_AE_L32_XC, + OPCODE_AE_L32_XC1, + OPCODE_AE_L32_I, + OPCODE_AE_L32_IP, + OPCODE_AE_L32_X, + OPCODE_AE_L32_XP, + OPCODE_AE_L32M_XC, + OPCODE_AE_L32M_I, + OPCODE_AE_L32M_IU, + OPCODE_AE_L32M_X, + OPCODE_AE_L32M_XU, + OPCODE_AE_L16X2M_XC, + OPCODE_AE_L16X2M_XC1, + OPCODE_AE_L16X2M_I, + OPCODE_AE_L16X2M_IU, + OPCODE_AE_L16X2M_X, + OPCODE_AE_L16X2M_XU, + OPCODE_AE_L32X2F24_XC, + OPCODE_AE_L32X2F24_XC1, + OPCODE_AE_L32X2F24_I, + OPCODE_AE_L32X2F24_IP, + OPCODE_AE_L32X2F24_RIP, + OPCODE_AE_L32X2F24_RI, + OPCODE_AE_L32X2F24_RIC, + OPCODE_AE_L32X2F24_RIC1, + OPCODE_AE_L32X2F24_X, + OPCODE_AE_L32X2F24_XP, + OPCODE_AE_L32X2_XC, + OPCODE_AE_L32X2_XC1, + OPCODE_AE_L32X2_I, + OPCODE_AE_L32X2_IP, + OPCODE_AE_L32X2_RIC, + OPCODE_AE_L32X2_RIC1, + OPCODE_AE_L32X2_X, + OPCODE_AE_L32X2_XP, + OPCODE_AE_L16X4_XC, + OPCODE_AE_L16X4_XC1, + OPCODE_AE_L16X4_I, + OPCODE_AE_L16X4_IP, + OPCODE_AE_L16X4_X, + OPCODE_AE_L16X4_XP, + OPCODE_AE_L8X8_XC, + OPCODE_AE_L8X8_XC1, + OPCODE_AE_L8X8_I, + OPCODE_AE_L8X8_IP, + OPCODE_AE_L8X8_X, + OPCODE_AE_L8X8_XP, + OPCODE_AE_L64_XC, + OPCODE_AE_L64_XC1, + OPCODE_AE_L64_I, + OPCODE_AE_L64_IP, + OPCODE_AE_L64_X, + OPCODE_AE_L64_XP, + OPCODE_AE_S16X2M_XC, + OPCODE_AE_S16X2M_XC1, + OPCODE_AE_S16X2M_I, + OPCODE_AE_S16X2M_IU, + OPCODE_AE_S16X2M_X, + OPCODE_AE_S16X2M_XU, + OPCODE_AE_S32X2F24_XC, + OPCODE_AE_S32X2F24_XC1, + OPCODE_AE_S32X2F24_I, + OPCODE_AE_S32X2F24_IP, + OPCODE_AE_S32X2F24_RIP, + OPCODE_AE_S32X2F24_RIC, + OPCODE_AE_S32X2F24_RIC1, + OPCODE_AE_S32X2F24_X, + OPCODE_AE_S32X2F24_XP, + OPCODE_AE_S32X2_XC, + OPCODE_AE_S32X2_XC1, + OPCODE_AE_S32X2_I, + OPCODE_AE_S32X2_IP, + OPCODE_AE_S32X2_RIC, + OPCODE_AE_S32X2_RIC1, + OPCODE_AE_S32X2_X, + OPCODE_AE_S32X2_XP, + OPCODE_AE_S32X2RNG_I, + OPCODE_AE_S32X2RNG_IP, + OPCODE_AE_S32X2RNG_X, + OPCODE_AE_S32X2RNG_XP, + OPCODE_AE_S16X4_XC, + OPCODE_AE_S16X4_XC1, + OPCODE_AE_S16X4_I, + OPCODE_AE_S16X4_IP, + OPCODE_AE_S16X4_X, + OPCODE_AE_S16X4_XP, + OPCODE_AE_S8X8_XC, + OPCODE_AE_S8X8_XC1, + OPCODE_AE_S8X8_I, + OPCODE_AE_S8X8_IP, + OPCODE_AE_S8X8_X, + OPCODE_AE_S8X8_XP, + OPCODE_AE_S16M_L_XC, + OPCODE_AE_S16M_L_XC1, + OPCODE_AE_S16M_L_I, + OPCODE_AE_S16M_L_IU, + OPCODE_AE_S16M_L_X, + OPCODE_AE_S16M_L_XU, + OPCODE_AE_S32F24_L_XC, + OPCODE_AE_S32F24_L_XC1, + OPCODE_AE_S32F24_L_I, + OPCODE_AE_S32F24_L_IP, + OPCODE_AE_S32F24_L_X, + OPCODE_AE_S32F24_L_XP, + OPCODE_AE_S32_L_XC, + OPCODE_AE_S32_L_XC1, + OPCODE_AE_S32_L_I, + OPCODE_AE_S32_L_IP, + OPCODE_AE_S32_L_X, + OPCODE_AE_S32_L_XP, + OPCODE_AE_S32_H_XC, + OPCODE_AE_S32_H_XC1, + OPCODE_AE_S32_H_I, + OPCODE_AE_S32_H_IP, + OPCODE_AE_S32_H_X, + OPCODE_AE_S32_H_XP, + OPCODE_AE_S16_0_XC, + OPCODE_AE_S16_0_XC1, + OPCODE_AE_S16_0_I, + OPCODE_AE_S16_0_IP, + OPCODE_AE_S16_0_X, + OPCODE_AE_S16_0_XP, + OPCODE_AE_S8_0_XC, + OPCODE_AE_S8_0_XC1, + OPCODE_AE_S8_0_I, + OPCODE_AE_S8_0_IP, + OPCODE_AE_S8_0_X, + OPCODE_AE_S8_0_XP, + OPCODE_AE_S64_XC, + OPCODE_AE_S64_XC1, + OPCODE_AE_S64_I, + OPCODE_AE_S64_IP, + OPCODE_AE_S64_X, + OPCODE_AE_S64_XP, + OPCODE_AE_S32M_XC, + OPCODE_AE_S32M_I, + OPCODE_AE_S32M_IU, + OPCODE_AE_S32M_X, + OPCODE_AE_S32M_XU, + OPCODE_AE_L32X2_XC2, + OPCODE_AE_L16X4_XC2, + OPCODE_AE_L8X8_XC2, + OPCODE_AE_L64_XC2, + OPCODE_AE_S32X2_XC2, + OPCODE_AE_S16X4_XC2, + OPCODE_AE_S8X8_XC2, + OPCODE_AE_S64_XC2, + OPCODE_AE_S16X4RNG_I, + OPCODE_AE_S16X4RNG_IP, + OPCODE_AE_S16X4RNG_X, + OPCODE_AE_S16X4RNG_XP, + OPCODE_AE_L32X2X2_XC, + OPCODE_AE_L32X2X2_XC1, + OPCODE_AE_L32X2X2_I, + OPCODE_AE_L32X2X2_IP, + OPCODE_AE_L32X2X2_X, + OPCODE_AE_L32X2X2_XP, + OPCODE_AE_L16X4X2_XC, + OPCODE_AE_L16X4X2_XC1, + OPCODE_AE_L16X4X2_I, + OPCODE_AE_L16X4X2_IP, + OPCODE_AE_L16X4X2_X, + OPCODE_AE_L16X4X2_XP, + OPCODE_AE_L8X8X2_XC, + OPCODE_AE_L8X8X2_XC1, + OPCODE_AE_L8X8X2_I, + OPCODE_AE_L8X8X2_IP, + OPCODE_AE_L8X8X2_X, + OPCODE_AE_L8X8X2_XP, + OPCODE_AE_L64X2_XC, + OPCODE_AE_L64X2_XC1, + OPCODE_AE_L64X2_I, + OPCODE_AE_L64X2_IP, + OPCODE_AE_L64X2_X, + OPCODE_AE_L64X2_XP, + OPCODE_AE_S32X2X2_XC, + OPCODE_AE_S32X2X2_XC1, + OPCODE_AE_S32X2X2_I, + OPCODE_AE_S32X2X2_IP, + OPCODE_AE_S32X2X2_X, + OPCODE_AE_S32X2X2_XP, + OPCODE_AE_S32X2X2RNG_I, + OPCODE_AE_S32X2X2RNG_IP, + OPCODE_AE_S32X2X2RNG_X, + OPCODE_AE_S32X2X2RNG_XP, + OPCODE_AE_S16X4X2_XC, + OPCODE_AE_S16X4X2_XC1, + OPCODE_AE_S16X4X2_I, + OPCODE_AE_S16X4X2_IP, + OPCODE_AE_S16X4X2_X, + OPCODE_AE_S16X4X2_XP, + OPCODE_AE_S8X8X2_XC, + OPCODE_AE_S8X8X2_XC1, + OPCODE_AE_S8X8X2_I, + OPCODE_AE_S8X8X2_IP, + OPCODE_AE_S8X8X2_X, + OPCODE_AE_S8X8X2_XP, + OPCODE_AE_S64X2_XC, + OPCODE_AE_S64X2_XC1, + OPCODE_AE_S64X2_I, + OPCODE_AE_S64X2_IP, + OPCODE_AE_S64X2_X, + OPCODE_AE_S64X2_XP, + OPCODE_AE_L32X2X2_XC2, + OPCODE_AE_L16X4X2_XC2, + OPCODE_AE_L8X8X2_XC2, + OPCODE_AE_L64X2_XC2, + OPCODE_AE_S32X2X2_XC2, + OPCODE_AE_S16X4X2_XC2, + OPCODE_AE_S8X8X2_XC2, + OPCODE_AE_S64X2_XC2, + OPCODE_AE_S16X4X2RNG_I, + OPCODE_AE_S16X4X2RNG_IP, + OPCODE_AE_S16X4X2RNG_X, + OPCODE_AE_S16X4X2RNG_XP, + OPCODE_AE_ZALIGN64, + OPCODE_AE_LALIGN64_I, + OPCODE_AE_SALIGN64_I, + OPCODE_AE_MOVALIGN, + OPCODE_AE_LA64_PP, + OPCODE_AE_LA24POS_PC, + OPCODE_AE_LA24NEG_PC, + OPCODE_AE_LA24POS_PC1, + OPCODE_AE_LA24NEG_PC1, + OPCODE_AE_LA24X2POS_PC, + OPCODE_AE_LA24X2NEG_PC, + OPCODE_AE_LA24X2POS_PC1, + OPCODE_AE_LA24X2NEG_PC1, + OPCODE_AE_LA32X2POS_PC, + OPCODE_AE_LA32X2NEG_PC, + OPCODE_AE_LA32X2POS_PC1, + OPCODE_AE_LA32X2NEG_PC1, + OPCODE_AE_LA32X2POS_PC2, + OPCODE_AE_LA16X4POS_PC, + OPCODE_AE_LA16X4NEG_PC, + OPCODE_AE_LA16X4POS_PC1, + OPCODE_AE_LA16X4NEG_PC1, + OPCODE_AE_LA16X4POS_PC2, + OPCODE_AE_LA8X8POS_PC, + OPCODE_AE_LA8X8NEG_PC, + OPCODE_AE_LA8X8POS_PC1, + OPCODE_AE_LA8X8NEG_PC1, + OPCODE_AE_LA8X8POS_PC2, + OPCODE_AE_LA32X2X2POS_PC, + OPCODE_AE_LA32X2X2POS_PC1, + OPCODE_AE_LA32X2X2POS_PC2, + OPCODE_AE_LA16X4X2POS_PC, + OPCODE_AE_LA16X4X2POS_PC1, + OPCODE_AE_LA16X4X2POS_PC2, + OPCODE_AE_LA8X8X2POS_PC, + OPCODE_AE_LA8X8X2POS_PC1, + OPCODE_AE_LA8X8X2POS_PC2, + OPCODE_AE_SA64POS_FP, + OPCODE_AE_SA64NEG_FP, + OPCODE_AE_LA32X2_IC, + OPCODE_AE_LA32X2_IC1, + OPCODE_AE_LA32X2_IC2, + OPCODE_AE_LA32X2_IP, + OPCODE_AE_LA32X2_RIP, + OPCODE_AE_LA32X2_RIC, + OPCODE_AE_LA32X2_RIC1, + OPCODE_AE_LA16X4_IC, + OPCODE_AE_LA16X4_IC1, + OPCODE_AE_LA16X4_IC2, + OPCODE_AE_LA16X4_IP, + OPCODE_AE_LA16X4_RIP, + OPCODE_AE_LA16X4_RIC, + OPCODE_AE_LA16X4_RIC1, + OPCODE_AE_LA8X8_IC, + OPCODE_AE_LA8X8_IC1, + OPCODE_AE_LA8X8_IC2, + OPCODE_AE_LA8X8_IP, + OPCODE_AE_LA8X8_RIP, + OPCODE_AE_LA8X8_RIC, + OPCODE_AE_LA8X8_RIC1, + OPCODE_AE_LA32X2F24_IC, + OPCODE_AE_LA32X2F24_IC1, + OPCODE_AE_LA32X2F24_IP, + OPCODE_AE_LA32X2F24_RIP, + OPCODE_AE_LA32X2F24_RIC, + OPCODE_AE_LA32X2F24_RIC1, + OPCODE_AE_LA24_IC, + OPCODE_AE_LA24_IC1, + OPCODE_AE_LA24_IP, + OPCODE_AE_LA24_RIP, + OPCODE_AE_LA24_RIC, + OPCODE_AE_LA24_RIC1, + OPCODE_AE_LA24X2_IC, + OPCODE_AE_LA24X2_IC1, + OPCODE_AE_LA24X2_IP, + OPCODE_AE_LA24X2_RIP, + OPCODE_AE_LA24X2_RIC, + OPCODE_AE_LA24X2_RIC1, + OPCODE_AE_SA32X2_IC, + OPCODE_AE_SA32X2_IC1, + OPCODE_AE_SA32X2_IC2, + OPCODE_AE_SA32X2_IP, + OPCODE_AE_SA32X2_RIP, + OPCODE_AE_SA32X2_RIC, + OPCODE_AE_SA32X2_RIC1, + OPCODE_AE_SA16X4_IC, + OPCODE_AE_SA16X4_IC1, + OPCODE_AE_SA16X4_IC2, + OPCODE_AE_SA16X4_IP, + OPCODE_AE_SA16X4_RIP, + OPCODE_AE_SA16X4_RIC, + OPCODE_AE_SA16X4_RIC1, + OPCODE_AE_SA8X8_IC, + OPCODE_AE_SA8X8_IC1, + OPCODE_AE_SA8X8_IC2, + OPCODE_AE_SA8X8_IP, + OPCODE_AE_SA8X8_RIP, + OPCODE_AE_SA8X8_RIC, + OPCODE_AE_SA8X8_RIC1, + OPCODE_AE_SA32X2F24_IC, + OPCODE_AE_SA32X2F24_IC1, + OPCODE_AE_SA32X2F24_IP, + OPCODE_AE_SA32X2F24_RIP, + OPCODE_AE_SA32X2F24_RIC, + OPCODE_AE_SA32X2F24_RIC1, + OPCODE_AE_SA24_L_IC, + OPCODE_AE_SA24_L_IC1, + OPCODE_AE_SA24_L_IP, + OPCODE_AE_SA24_L_RIP, + OPCODE_AE_SA24_L_RIC, + OPCODE_AE_SA24_L_RIC1, + OPCODE_AE_SA24X2_IC, + OPCODE_AE_SA24X2_IC1, + OPCODE_AE_SA24X2_IP, + OPCODE_AE_SA24X2_RIP, + OPCODE_AE_SA24X2_RIC, + OPCODE_AE_SA24X2_RIC1, + OPCODE_AE_ADDICIRC, + OPCODE_AE_ADDCIRC_XC2, + OPCODE_AE_ADDCIRC_XC1, + OPCODE_AE_ADDCIRC_XC, + OPCODE_AE_S32RA64S_I, + OPCODE_AE_S32RA64S_IP, + OPCODE_AE_S32RA64S_X, + OPCODE_AE_S32RA64S_XP, + OPCODE_AE_S32RA64S_XC, + OPCODE_AE_S32RA64S_XC1, + OPCODE_AE_S24RA64S_I, + OPCODE_AE_S24RA64S_IP, + OPCODE_AE_S24RA64S_X, + OPCODE_AE_S24RA64S_XP, + OPCODE_AE_S24RA64S_XC, + OPCODE_AE_S24RA64S_XC1, + OPCODE_AE_S32X2RA64S_IP, + OPCODE_AE_S24X2RA64S_IP, + OPCODE_AE_S16X4RA32S_IP, + OPCODE_AE_ADDBRBA32, + OPCODE_AE_S32X2_L_IP, + OPCODE_AE_BITSWAP, + OPCODE_AE_MUL32JS, + OPCODE_AE_ADDANDSUB32S, + OPCODE_AE_ADDANDSUB32JS, + OPCODE_AE_ADDANDSUBRNG32, + OPCODE_AE_ADDANDSUBRNG32_H, + OPCODE_AE_ADDANDSUBRNG32_L, + OPCODE_AE_ADDRNG32, + OPCODE_AE_SUBRNG32, + OPCODE_AE_RNG32X2, + OPCODE_AE_SEL16I, + OPCODE_AE_SEL16I_N, + OPCODE_AE_SHORTSWAP, + OPCODE_AE_MOVAB4, + OPCODE_AE_MOVAB2, + OPCODE_AE_MOVAB, + OPCODE_AE_MOVBA, + OPCODE_AE_MOVBA1X2, + OPCODE_AE_MOVBA4, + OPCODE_AE_MOVBA2, + OPCODE_AE_MOVB2, + OPCODE_AE_MOVB4, + OPCODE_AE_MOVT16X4, + OPCODE_AE_MOVF16X4, + OPCODE_AE_MOVT32X2, + OPCODE_AE_MOVF32X2, + OPCODE_AE_MOVSARA7X2, + OPCODE_AE_MOVSARD7, + OPCODE_AE_MOVASAR, + OPCODE_AE_MOVDA32X2, + OPCODE_AE_MOVDA32, + OPCODE_AE_MOVDA16X2, + OPCODE_AE_MOVDA16, + OPCODE_AE_MOVI, + OPCODE_AE_TRUNCP24A32X2, + OPCODE_AE_SAT16X4, + OPCODE_AE_CVT32X2F16_32, + OPCODE_AE_CVT32X2F16_10, + OPCODE_AE_SEXT32X2D16_32, + OPCODE_AE_SEXT32X2D16_10, + OPCODE_AE_CVTA32F24S_L, + OPCODE_AE_CVTA32F24S_H, + OPCODE_AE_CVTP24A16X2_LL, + OPCODE_AE_CVTP24A16X2_LH, + OPCODE_AE_CVTP24A16X2_HL, + OPCODE_AE_CVTP24A16X2_HH, + OPCODE_AE_TRUNCP24Q48X2, + OPCODE_AE_TRUNCA32X2F64S, + OPCODE_AE_TRUNCI32X2F64S, + OPCODE_AE_TRUNCA32F64S_L, + OPCODE_AE_TRUNCI32F64S_L, + OPCODE_AE_TRUNCP16, + OPCODE_AE_ROUND32X2F64SSYM, + OPCODE_AE_ROUND32X2F64SASYM, + OPCODE_AE_ROUND32X2F48SSYM, + OPCODE_AE_ROUND32X2F48SASYM, + OPCODE_AE_ROUND16X4F32SSYM, + OPCODE_AE_ROUND16X4F32SASYM, + OPCODE_AE_ROUND24X2F48SSYM, + OPCODE_AE_ROUND24X2F48SASYM, + OPCODE_AE_ROUNDSP16Q48X2SYM, + OPCODE_AE_ROUNDSP16Q48X2ASYM, + OPCODE_AE_MINABS32S, + OPCODE_AE_MAXABS32S, + OPCODE_AE_ROUNDSP16F24SYM, + OPCODE_AE_ROUNDSP16F24ASYM, + OPCODE_AE_MOV, + OPCODE_AE_MOVT64, + OPCODE_AE_MOVF64, + OPCODE_AE_CVTQ56A32S, + OPCODE_AE_CVT48A32, + OPCODE_AE_CVT64A32, + OPCODE_AE_CVTQ56P32S_L, + OPCODE_AE_CVTQ56P32S_H, + OPCODE_AE_CVT64F32_H, + OPCODE_AE_CVT48F32_L, + OPCODE_AE_CVT48F32_H, + OPCODE_AE_SAT48S, + OPCODE_AE_SATQ56S, + OPCODE_AE_SAT24S, + OPCODE_AE_TRUNCQ32, + OPCODE_AE_MINABS64S, + OPCODE_AE_MAXABS64S, + OPCODE_AE_ROUNDSQ32F48SYM, + OPCODE_AE_ROUNDSQ32F48ASYM, + OPCODE_AE_TRUNCA32Q48, + OPCODE_AE_MOVAD32_L, + OPCODE_AE_MOVAD32_H, + OPCODE_AE_MOVAD16_3, + OPCODE_AE_MOVAD16_2, + OPCODE_AE_MOVAD16_1, + OPCODE_AE_MOVAD16_0, + OPCODE_AE_SRA64_32, + OPCODE_AE_PKSR32, + OPCODE_AE_PKSR24, + OPCODE_AE_PKSRF32, + OPCODE_AE_PKSR16, + OPCODE_AE_TRUNCA16P24S_L, + OPCODE_AE_TRUNCA16P24S_H, + OPCODE_AE_ADD32, + OPCODE_AE_SUB32, + OPCODE_AE_ADDSUB32, + OPCODE_AE_SUBADD32, + OPCODE_AE_ADD16, + OPCODE_AE_SUB16, + OPCODE_AE_ADD32_HL_LH, + OPCODE_AE_ADDSUB32_HL_LH, + OPCODE_AE_NEG32, + OPCODE_AE_ABS32, + OPCODE_AE_NEG32_L, + OPCODE_AE_ADD24S, + OPCODE_AE_SUB24S, + OPCODE_AE_ADD32S, + OPCODE_AE_SUB32S, + OPCODE_AE_ADDSUB32S, + OPCODE_AE_SUBADD32S, + OPCODE_AE_ADD16S, + OPCODE_AE_SUB16S, + OPCODE_AE_ADD32S_HL_LH, + OPCODE_AE_ADDSUB32S_HL_LH, + OPCODE_AE_NEG24S, + OPCODE_AE_ABS24S, + OPCODE_AE_NEG32S, + OPCODE_AE_ABS32S, + OPCODE_AE_NEG16S, + OPCODE_AE_ABS16S, + OPCODE_AE_ABS16, + OPCODE_AE_MULC16JS_H, + OPCODE_AE_MULC16JS_L, + OPCODE_AE_MULAC16JS_H, + OPCODE_AE_MULAC16JS_L, + OPCODE_AE_LT16, + OPCODE_AE_LE16, + OPCODE_AE_EQ16, + OPCODE_AE_LT32, + OPCODE_AE_LE32, + OPCODE_AE_EQ32, + OPCODE_AE_MIN32, + OPCODE_AE_MAX32, + OPCODE_AE_MINMAX32, + OPCODE_AE_MINMAX16, + OPCODE_AE_MIN16, + OPCODE_AE_MAX16, + OPCODE_AE_ADD64, + OPCODE_AE_SUB64, + OPCODE_AE_NEG64, + OPCODE_AE_ABS64, + OPCODE_AE_ADDSQ56S, + OPCODE_AE_SUBSQ56S, + OPCODE_AE_ADD64S, + OPCODE_AE_SUB64S, + OPCODE_AE_NEGSQ56S, + OPCODE_AE_ABSSQ56S, + OPCODE_AE_NEG64S, + OPCODE_AE_ABS64S, + OPCODE_AE_AND, + OPCODE_AE_NAND, + OPCODE_AE_OR, + OPCODE_AE_XOR, + OPCODE_AE_SLAI24, + OPCODE_AE_SRLI24, + OPCODE_AE_SRAI24, + OPCODE_AE_SLAS24, + OPCODE_AE_SRLS24, + OPCODE_AE_SRAS24, + OPCODE_AE_SRAI16, + OPCODE_AE_SRAI16R, + OPCODE_AE_SLAI32, + OPCODE_AE_SRLI32, + OPCODE_AE_SRAI32, + OPCODE_AE_SRAI32R, + OPCODE_AE_SLAS32, + OPCODE_AE_SRLS32, + OPCODE_AE_SRAS32, + OPCODE_AE_SLAA32, + OPCODE_AE_SRLA32, + OPCODE_AE_SRAA32, + OPCODE_AE_SLAI16S, + OPCODE_AE_SLAA16S, + OPCODE_AE_SRAA16S, + OPCODE_AE_SRAA16RS, + OPCODE_AE_SLAI24S, + OPCODE_AE_SLAS24S, + OPCODE_AE_SLAI32S, + OPCODE_AE_SLAS32S, + OPCODE_AE_SLAA32S, + OPCODE_AE_SRAA32S, + OPCODE_AE_SRAA32RS, + OPCODE_AE_SLASQ56, + OPCODE_AE_SRLSQ56, + OPCODE_AE_SRASQ56, + OPCODE_AE_SLAAQ56, + OPCODE_AE_SRLAQ56, + OPCODE_AE_SRAAQ56, + OPCODE_AE_SLAI64, + OPCODE_AE_SRLI64, + OPCODE_AE_SRAI64, + OPCODE_AE_SLAS64, + OPCODE_AE_SRLS64, + OPCODE_AE_SRAS64, + OPCODE_AE_SLAA64, + OPCODE_AE_SRLA64, + OPCODE_AE_SRAA64, + OPCODE_AE_SLAISQ56S, + OPCODE_AE_SLASSQ56S, + OPCODE_AE_SLAASQ56S, + OPCODE_AE_SLAI64S, + OPCODE_AE_SLAS64S, + OPCODE_AE_SLAA64S, + OPCODE_AE_LT64, + OPCODE_AE_LE64, + OPCODE_AE_EQ64, + OPCODE_AE_MAX64, + OPCODE_AE_MIN64, + OPCODE_AE_NSA64, + OPCODE_AE_NSAZ16_0, + OPCODE_AE_NSAZ32_L, + OPCODE_AE_MULS32F48P16S_LL, + OPCODE_AE_MULF32S_LL, + OPCODE_AE_MUL32_LL, + OPCODE_AE_MULF32R_LL, + OPCODE_AE_MULF32RA_LL, + OPCODE_AE_MULS32F48P16S_LH, + OPCODE_AE_MULF32S_LH, + OPCODE_AE_MUL32_LH, + OPCODE_AE_MULF32R_LH, + OPCODE_AE_MULF32RA_LH, + OPCODE_AE_MULS32F48P16S_HH, + OPCODE_AE_MULF32S_HH, + OPCODE_AE_MUL32_HH, + OPCODE_AE_MULF32R_HH, + OPCODE_AE_MULF32RA_HH, + OPCODE_AE_MULAS32F48P16S_LL, + OPCODE_AE_MULAF32S_LL, + OPCODE_AE_MULA32_LL, + OPCODE_AE_MULAF32R_LL, + OPCODE_AE_MULAF32RA_LL, + OPCODE_AE_MULAS32F48P16S_LH, + OPCODE_AE_MULAF32S_LH, + OPCODE_AE_MULA32_LH, + OPCODE_AE_MULAF32R_LH, + OPCODE_AE_MULAF32RA_LH, + OPCODE_AE_MULAS32F48P16S_HH, + OPCODE_AE_MULAF32S_HH, + OPCODE_AE_MULA32_HH, + OPCODE_AE_MULAF32R_HH, + OPCODE_AE_MULAF32RA_HH, + OPCODE_AE_MULSS32F48P16S_LL, + OPCODE_AE_MULSF32S_LL, + OPCODE_AE_MULS32_LL, + OPCODE_AE_MULSF32R_LL, + OPCODE_AE_MULSF32RA_LL, + OPCODE_AE_MULSS32F48P16S_LH, + OPCODE_AE_MULSF32S_LH, + OPCODE_AE_MULS32_LH, + OPCODE_AE_MULSF32R_LH, + OPCODE_AE_MULSF32RA_LH, + OPCODE_AE_MULSS32F48P16S_HH, + OPCODE_AE_MULSF32S_HH, + OPCODE_AE_MULS32_HH, + OPCODE_AE_MULSF32R_HH, + OPCODE_AE_MULSF32RA_HH, + OPCODE_AE_MUL32U_LL, + OPCODE_AE_MULA32U_LL, + OPCODE_AE_MULS32U_LL, + OPCODE_AE_MULF16SS_33, + OPCODE_AE_MULF16SS_22, + OPCODE_AE_MULF16SS_32, + OPCODE_AE_MULF16SS_21, + OPCODE_AE_MULF16SS_31, + OPCODE_AE_MULF16SS_30, + OPCODE_AE_MULF16SS_10, + OPCODE_AE_MULF16SS_20, + OPCODE_AE_MULF16SS_11, + OPCODE_AE_MULF16SS_00, + OPCODE_AE_MULSF16SS_33, + OPCODE_AE_MULSF16SS_22, + OPCODE_AE_MULSF16SS_32, + OPCODE_AE_MULSF16SS_21, + OPCODE_AE_MULSF16SS_31, + OPCODE_AE_MULSF16SS_30, + OPCODE_AE_MULSF16SS_10, + OPCODE_AE_MULSF16SS_20, + OPCODE_AE_MULSF16SS_11, + OPCODE_AE_MULSF16SS_00, + OPCODE_AE_MULAF16SS_33, + OPCODE_AE_MULAF16SS_22, + OPCODE_AE_MULAF16SS_32, + OPCODE_AE_MULAF16SS_21, + OPCODE_AE_MULAF16SS_31, + OPCODE_AE_MULAF16SS_30, + OPCODE_AE_MULAF16SS_10, + OPCODE_AE_MULAF16SS_20, + OPCODE_AE_MULAF16SS_11, + OPCODE_AE_MULAF16SS_00, + OPCODE_AE_MUL16S_00, + OPCODE_AE_MULA16S_00, + OPCODE_AE_MULS16S_00, + OPCODE_AE_MULAAFD16SS_33_22, + OPCODE_AE_MULAAFD16SS_13_02, + OPCODE_AE_MULAAFD16SS_11_00, + OPCODE_AE_MULSSFD16SS_33_22, + OPCODE_AE_MULSSFD16SS_13_02, + OPCODE_AE_MULSSFD16SS_11_00, + OPCODE_AE_MULZAAFD16SS_33_22, + OPCODE_AE_MULZAAFD16SS_13_02, + OPCODE_AE_MULZAAFD16SS_11_00, + OPCODE_AE_MULZSSFD16SS_33_22, + OPCODE_AE_MULZSSFD16SS_13_02, + OPCODE_AE_MULZSSFD16SS_11_00, + OPCODE_AE_MULF48Q32SP16S_L, + OPCODE_AE_MULF48Q32SP16U_L, + OPCODE_AE_MULQ32SP16S_L, + OPCODE_AE_MULQ32SP16U_L, + OPCODE_AE_MULAF48Q32SP16S_L, + OPCODE_AE_MULAF48Q32SP16U_L, + OPCODE_AE_MULAQ32SP16S_L, + OPCODE_AE_MULAQ32SP16U_L, + OPCODE_AE_MULSF48Q32SP16S_L, + OPCODE_AE_MULSF48Q32SP16U_L, + OPCODE_AE_MULSQ32SP16S_L, + OPCODE_AE_MULSQ32SP16U_L, + OPCODE_AE_MULFP24X2RA, + OPCODE_AE_MULFP24X2R, + OPCODE_AE_MULAFP24X2RA, + OPCODE_AE_MULAFP24X2R, + OPCODE_AE_MULSFP24X2RA, + OPCODE_AE_MULSFP24X2R, + OPCODE_AE_MULZAAFD32S_HH_LL, + OPCODE_AE_MULZAAFD32RA_HH_LL, + OPCODE_AE_MULZAAD32_HH_LL, + OPCODE_AE_MULZAAFD32S_HL_LH, + OPCODE_AE_MULZAAFD32RA_HL_LH, + OPCODE_AE_MULZAAD32_HL_LH, + OPCODE_AE_MULZASFD32S_HH_LL, + OPCODE_AE_MULZASFD32RA_HH_LL, + OPCODE_AE_MULZASD32_HH_LL, + OPCODE_AE_MULZASFD32S_HL_LH, + OPCODE_AE_MULZASFD32RA_HL_LH, + OPCODE_AE_MULZASD32_HL_LH, + OPCODE_AE_MULZSAFD32S_HH_LL, + OPCODE_AE_MULZSAFD32RA_HH_LL, + OPCODE_AE_MULZSAD32_HH_LL, + OPCODE_AE_MULZSSFD32S_HH_LL, + OPCODE_AE_MULZSSFD32RA_HH_LL, + OPCODE_AE_MULZSSD32_HH_LL, + OPCODE_AE_MULZSSFD32S_HL_LH, + OPCODE_AE_MULZSSFD32RA_HL_LH, + OPCODE_AE_MULZSSD32_HL_LH, + OPCODE_AE_MULAAFD32S_HH_LL, + OPCODE_AE_MULAAFD32RA_HH_LL, + OPCODE_AE_MULAAD32_HH_LL, + OPCODE_AE_MULAAFD32S_HL_LH, + OPCODE_AE_MULAAFD32RA_HL_LH, + OPCODE_AE_MULAAD32_HL_LH, + OPCODE_AE_MULASFD32S_HH_LL, + OPCODE_AE_MULASFD32RA_HH_LL, + OPCODE_AE_MULASD32_HH_LL, + OPCODE_AE_MULASFD32S_HL_LH, + OPCODE_AE_MULASFD32RA_HL_LH, + OPCODE_AE_MULASD32_HL_LH, + OPCODE_AE_MULSAFD32S_HH_LL, + OPCODE_AE_MULSAFD32RA_HH_LL, + OPCODE_AE_MULSAD32_HH_LL, + OPCODE_AE_MULSSFD32S_HH_LL, + OPCODE_AE_MULSSFD32RA_HH_LL, + OPCODE_AE_MULSSD32_HH_LL, + OPCODE_AE_MULSSFD32S_HL_LH, + OPCODE_AE_MULSSFD32RA_HL_LH, + OPCODE_AE_MULSSD32_HL_LH, + OPCODE_AE_MULF32X16_L0, + OPCODE_AE_MUL32X16_L0, + OPCODE_AE_MULF32X16_L1, + OPCODE_AE_MUL32X16_L1, + OPCODE_AE_MULF32X16_L2, + OPCODE_AE_MUL32X16_L2, + OPCODE_AE_MULF32X16_L3, + OPCODE_AE_MUL32X16_L3, + OPCODE_AE_MULF32X16_H0, + OPCODE_AE_MUL32X16_H0, + OPCODE_AE_MULF32X16_H1, + OPCODE_AE_MUL32X16_H1, + OPCODE_AE_MULF32X16_H2, + OPCODE_AE_MUL32X16_H2, + OPCODE_AE_MULF32X16_H3, + OPCODE_AE_MUL32X16_H3, + OPCODE_AE_MULAF32X16_L0, + OPCODE_AE_MULA32X16_L0, + OPCODE_AE_MULAF32X16_L1, + OPCODE_AE_MULA32X16_L1, + OPCODE_AE_MULAF32X16_L2, + OPCODE_AE_MULA32X16_L2, + OPCODE_AE_MULAF32X16_L3, + OPCODE_AE_MULA32X16_L3, + OPCODE_AE_MULAF32X16_H0, + OPCODE_AE_MULA32X16_H0, + OPCODE_AE_MULAF32X16_H1, + OPCODE_AE_MULA32X16_H1, + OPCODE_AE_MULAF32X16_H2, + OPCODE_AE_MULA32X16_H2, + OPCODE_AE_MULAF32X16_H3, + OPCODE_AE_MULA32X16_H3, + OPCODE_AE_MULSF32X16_L0, + OPCODE_AE_MULS32X16_L0, + OPCODE_AE_MULSF32X16_L1, + OPCODE_AE_MULS32X16_L1, + OPCODE_AE_MULSF32X16_L2, + OPCODE_AE_MULS32X16_L2, + OPCODE_AE_MULSF32X16_L3, + OPCODE_AE_MULS32X16_L3, + OPCODE_AE_MULSF32X16_H0, + OPCODE_AE_MULS32X16_H0, + OPCODE_AE_MULSF32X16_H1, + OPCODE_AE_MULS32X16_H1, + OPCODE_AE_MULSF32X16_H2, + OPCODE_AE_MULS32X16_H2, + OPCODE_AE_MULSF32X16_H3, + OPCODE_AE_MULS32X16_H3, + OPCODE_AE_MULAAFD32X16_H3_L2, + OPCODE_AE_MULAAD32X16_H3_L2, + OPCODE_AE_MULAAFD32X16_H1_L0, + OPCODE_AE_MULAAD32X16_H1_L0, + OPCODE_AE_MULASFD32X16_H3_L2, + OPCODE_AE_MULASD32X16_H3_L2, + OPCODE_AE_MULASFD32X16_H1_L0, + OPCODE_AE_MULASD32X16_H1_L0, + OPCODE_AE_MULSAFD32X16_H3_L2, + OPCODE_AE_MULSAD32X16_H3_L2, + OPCODE_AE_MULSAFD32X16_H1_L0, + OPCODE_AE_MULSAD32X16_H1_L0, + OPCODE_AE_MULSSFD32X16_H3_L2, + OPCODE_AE_MULSSD32X16_H3_L2, + OPCODE_AE_MULSSFD32X16_H1_L0, + OPCODE_AE_MULSSD32X16_H1_L0, + OPCODE_AE_MULZAAFD32X16_H3_L2, + OPCODE_AE_MULZAAD32X16_H3_L2, + OPCODE_AE_MULZAAFD32X16_H1_L0, + OPCODE_AE_MULZAAD32X16_H1_L0, + OPCODE_AE_MULZASFD32X16_H3_L2, + OPCODE_AE_MULZASD32X16_H3_L2, + OPCODE_AE_MULZASFD32X16_H1_L0, + OPCODE_AE_MULZASD32X16_H1_L0, + OPCODE_AE_MULZSAFD32X16_H3_L2, + OPCODE_AE_MULZSAD32X16_H3_L2, + OPCODE_AE_MULZSAFD32X16_H1_L0, + OPCODE_AE_MULZSAD32X16_H1_L0, + OPCODE_AE_MULZSSFD32X16_H3_L2, + OPCODE_AE_MULZSSD32X16_H3_L2, + OPCODE_AE_MULZSSFD32X16_H1_L0, + OPCODE_AE_MULZSSD32X16_H1_L0, + OPCODE_AE_MULZAAFD32X16_H2_L3, + OPCODE_AE_MULZAAFD32X16_H0_L1, + OPCODE_AE_MULAAFD32X16_H2_L3, + OPCODE_AE_MULAAFD32X16_H0_L1, + OPCODE_AE_MULZAAD32X16_H2_L3, + OPCODE_AE_MULZAAD32X16_H0_L1, + OPCODE_AE_MULAAD32X16_H2_L3, + OPCODE_AE_MULAAD32X16_H0_L1, + OPCODE_AE_MULP32X16X2_H, + OPCODE_AE_MULFP32X16X2RS_H, + OPCODE_AE_MULFP32X16X2RAS_H, + OPCODE_AE_MULFP32X16X2S_H, + OPCODE_AE_MULP32X16X2_L, + OPCODE_AE_MULFP32X16X2RS_L, + OPCODE_AE_MULFP32X16X2RAS_L, + OPCODE_AE_MULFP32X16X2S_L, + OPCODE_AE_MULAP32X16X2_H, + OPCODE_AE_MULAFP32X16X2RS_H, + OPCODE_AE_MULAFP32X16X2RAS_H, + OPCODE_AE_MULAFP32X16X2S_H, + OPCODE_AE_MULAP32X16X2_L, + OPCODE_AE_MULAFP32X16X2RS_L, + OPCODE_AE_MULAFP32X16X2RAS_L, + OPCODE_AE_MULAFP32X16X2S_L, + OPCODE_AE_MULSP32X16X2_H, + OPCODE_AE_MULSFP32X16X2RS_H, + OPCODE_AE_MULSFP32X16X2RAS_H, + OPCODE_AE_MULSFP32X16X2S_H, + OPCODE_AE_MULSP32X16X2_L, + OPCODE_AE_MULSFP32X16X2RS_L, + OPCODE_AE_MULSFP32X16X2RAS_L, + OPCODE_AE_MULSFP32X16X2S_L, + OPCODE_AE_MULP32X2, + OPCODE_AE_MULFP32X2RS, + OPCODE_AE_MULFP32X2RAS, + OPCODE_AE_MULFP32X2TS, + OPCODE_AE_MULP32X2T, + OPCODE_AE_MULAP32X2, + OPCODE_AE_MULAFP32X2RS, + OPCODE_AE_MULAFP32X2RAS, + OPCODE_AE_MULAFP32X2TS, + OPCODE_AE_MULAP32X2T, + OPCODE_AE_MULSP32X2, + OPCODE_AE_MULSFP32X2RS, + OPCODE_AE_MULSFP32X2RAS, + OPCODE_AE_MULSFP32X2TS, + OPCODE_AE_MULSP32X2T, + OPCODE_AE_MULFP16X4S, + OPCODE_AE_MULFP16X4RAS, + OPCODE_AE_MULC32, + OPCODE_AE_MULFC24RA, + OPCODE_AE_MULFC32RAS, + OPCODE_AE_MULC32X16_L, + OPCODE_AE_MULFC32X16RAS_L, + OPCODE_AE_MULC32X16_H, + OPCODE_AE_MULFC32X16RAS_H, + OPCODE_AE_MULAC32, + OPCODE_AE_MULAFC24RA, + OPCODE_AE_MULAFC32RAS, + OPCODE_AE_MULAC32X16_L, + OPCODE_AE_MULAFC32X16RAS_L, + OPCODE_AE_MULAC32X16_H, + OPCODE_AE_MULAFC32X16RAS_H, + OPCODE_AE_MULF16X4SS, + OPCODE_AE_MULAF16X4SS, + OPCODE_AE_MULSF16X4SS, + OPCODE_AE_MUL16X4S, + OPCODE_AE_MULA16X4S, + OPCODE_AE_MULS16X4S, + OPCODE_AE_MUL16X4, + OPCODE_AE_MULA16X4, + OPCODE_AE_MULS16X4, + OPCODE_AE_MULFD32X2S_FIR_H, + OPCODE_AE_MULFD32X2RA_FIR_H, + OPCODE_AE_MULFD32X2S_FIR_L, + OPCODE_AE_MULFD32X2RA_FIR_L, + OPCODE_AE_MULFD32X16X2_FIR_HH, + OPCODE_AE_MULFD32X16X2_FIR_HL, + OPCODE_AE_MULFD32X16X2_FIR_LH, + OPCODE_AE_MULFD32X16X2_FIR_LL, + OPCODE_AE_MULAFD32X2S_FIR_H, + OPCODE_AE_MULAFD32X2RA_FIR_H, + OPCODE_AE_MULAFD32X2S_FIR_L, + OPCODE_AE_MULAFD32X2RA_FIR_L, + OPCODE_AE_MULAFD32X16X2_FIR_HH, + OPCODE_AE_MULAFD32X16X2_FIR_HL, + OPCODE_AE_MULAFD32X16X2_FIR_LH, + OPCODE_AE_MULAFD32X16X2_FIR_LL, + OPCODE_AE_MULC16S_H, + OPCODE_AE_MULC16S_L, + OPCODE_AE_MULAC16S_H, + OPCODE_AE_MULAC16S_L, + OPCODE_AE_MULFC16RAS, + OPCODE_AE_MULAFC16RAS, + OPCODE_AE_MUL16JS, + OPCODE_AE_ADDANDSUBRNG16RAS_S1, + OPCODE_AE_ADDANDSUBRNG16RAS_S2, + OPCODE_AE_CONJ16S, + OPCODE_AE_MULFQ16X2_FIR_3, + OPCODE_AE_MULFQ16X2_FIR_2, + OPCODE_AE_MULFQ16X2_FIR_1, + OPCODE_AE_MULFQ16X2_FIR_0, + OPCODE_AE_MULAFQ16X2_FIR_3, + OPCODE_AE_MULAFQ16X2_FIR_2, + OPCODE_AE_MULAFQ16X2_FIR_1, + OPCODE_AE_MULAFQ16X2_FIR_0, + OPCODE_AE_MULZAAAAFQ32X16, + OPCODE_AE_MULAAAAFQ32X16, + OPCODE_AE_MULZAAAAQ32X16, + OPCODE_AE_MULAAAAQ32X16, + OPCODE_AE_MUL16_00, + OPCODE_AE_MULA16_00, + OPCODE_AE_MULZAAAAQ16, + OPCODE_AE_MULAAAAQ16, + OPCODE_AE_DIV64D32_H, + OPCODE_AE_DIV64D32_L, + OPCODE_AE_SHA32, + OPCODE_AE_VLDL32T, + OPCODE_AE_VLDL16T, + OPCODE_AE_VLDL16C, + OPCODE_AE_VLDL16C_IP, + OPCODE_AE_VLDL16C_IC, + OPCODE_AE_VLDL16C_IC1, + OPCODE_AE_VLDSHT, + OPCODE_AE_LB, + OPCODE_AE_LBI, + OPCODE_AE_LBK, + OPCODE_AE_LBKI, + OPCODE_AE_LBS, + OPCODE_AE_LBSI, + OPCODE_AE_DB, + OPCODE_AE_DBI, + OPCODE_AE_DB_IC, + OPCODE_AE_DBI_IC, + OPCODE_AE_DB_IC1, + OPCODE_AE_DBI_IC1, + OPCODE_AE_DB_IP, + OPCODE_AE_DBI_IP, + OPCODE_AE_ARDECNORM16, + OPCODE_AE_LBKI_DBI_IC, + OPCODE_AE_LBKI_DBI_IP, + OPCODE_AE_LBKI_DBI, + OPCODE_AE_LBI_DBI_IC, + OPCODE_AE_LBI_DBI_IP, + OPCODE_AE_LBI_DBI, + OPCODE_AE_LBK_DB_IC, + OPCODE_AE_LBK_DB_IP, + OPCODE_AE_LBK_DB, + OPCODE_AE_LB_DB_IC, + OPCODE_AE_LB_DB_IP, + OPCODE_AE_LB_DB, + OPCODE_AE_VLEL32T, + OPCODE_AE_VLEL16T, + OPCODE_AE_SB, + OPCODE_AE_SBI, + OPCODE_AE_VLES16C, + OPCODE_AE_SBF, + OPCODE_AE_SB_IC, + OPCODE_AE_SBI_IC, + OPCODE_AE_VLES16C_IC, + OPCODE_AE_SBF_IC, + OPCODE_AE_SB_IC1, + OPCODE_AE_SBI_IC1, + OPCODE_AE_VLES16C_IC1, + OPCODE_AE_SBF_IC1, + OPCODE_AE_SB_IP, + OPCODE_AE_SBI_IP, + OPCODE_AE_VLES16C_IP, + OPCODE_AE_SBF_IP, + OPCODE_AE_SEXT32, + OPCODE_AE_MOVAE, + OPCODE_AE_MOVEA, + OPCODE_AE_MOVEEP, + OPCODE_AE_SEXT72, + OPCODE_AE_ADD72, + OPCODE_AE_SUB72, + OPCODE_AE_ADD72X64, + OPCODE_AE_SUB72X64, + OPCODE_AE_MUL32EP_HH, + OPCODE_AE_MULA32EP_HH, + OPCODE_AE_MULS32EP_HH, + OPCODE_AE_MULZAAD32EP_HH_LL, + OPCODE_AE_MULZSSD32EP_HH_LL, + OPCODE_AE_MULAAD32EP_HH_LL, + OPCODE_AE_MULSSD32EP_HH_LL, + OPCODE_AE_MULAAD32USEP_HL_LH, + OPCODE_AE_MULZAAD32USEP_HL_LH, + OPCODE_AE_MUL32USEP_LH, + OPCODE_AE_MULA32USEP_LH, + OPCODE_AE_MUL32USEP_LL, + OPCODE_AE_MULA32USEP_LL, + OPCODE_AE_SRAI72, + OPCODE_AE_SLAI72, + OPCODE_AE_SAT64S, + OPCODE_AE_L16SI_N, + OPCODE_AE_L16UI_N, + OPCODE_AE_S16I_N, + OPCODE_AE_LALIGN128_I, + OPCODE_AE_SALIGN128_I, + OPCODE_AE_LA128_PP, + OPCODE_AE_SA128POS_FP, + OPCODE_AE_LA8X4S_IP, + OPCODE_AE_LA8X4U_IP, + OPCODE_AE_LA8X8X2_IP, + OPCODE_AE_LA16X4X2_IP, + OPCODE_AE_LA32X2X2_IP, + OPCODE_AE_LA8X8X2_IC, + OPCODE_AE_LA16X4X2_IC, + OPCODE_AE_LA32X2X2_IC, + OPCODE_AE_LA8X8X2_IC1, + OPCODE_AE_LA16X4X2_IC1, + OPCODE_AE_LA32X2X2_IC1, + OPCODE_AE_LA8X8X2_IC2, + OPCODE_AE_LA16X4X2_IC2, + OPCODE_AE_LA32X2X2_IC2, + OPCODE_AE_SA8X8X2_IP, + OPCODE_AE_SA16X4X2_IP, + OPCODE_AE_SA32X2X2_IP, + OPCODE_AE_SA8X8X2_IC, + OPCODE_AE_SA16X4X2_IC, + OPCODE_AE_SA32X2X2_IC, + OPCODE_AE_SA8X8X2_IC1, + OPCODE_AE_SA16X4X2_IC1, + OPCODE_AE_SA32X2X2_IC1, + OPCODE_AE_SA8X8X2_IC2, + OPCODE_AE_SA16X4X2_IC2, + OPCODE_AE_SA32X2X2_IC2, + OPCODE_AE_ABS8, + OPCODE_AE_ABS8S, + OPCODE_AE_NEG8S, + OPCODE_AE_ADD8, + OPCODE_AE_SUB8, + OPCODE_AE_MAX8, + OPCODE_AE_MIN8, + OPCODE_AE_ADD8S, + OPCODE_AE_SUB8S, + OPCODE_AE_LE8, + OPCODE_AE_LT8, + OPCODE_AE_EQ8, + OPCODE_AE_SATU16X4, + OPCODE_AE_SAT32X2, + OPCODE_AE_SATU32X2, + OPCODE_AE_SAT8X8X16, + OPCODE_AE_SATU8X8X16, + OPCODE_AE_SAT8X4X32_L, + OPCODE_AE_SATU8X4X32_L, + OPCODE_AE_ROUND8X8F16SSYM, + OPCODE_AE_ROUND8X8F16SASYM, + OPCODE_AE_ROUND8X4F32SSYM_L, + OPCODE_AE_ROUND8X4F32SASYM_L, + OPCODE_AE_MOVDA8, + OPCODE_AE_MOVAD8, + OPCODE_AE_MOVDX2, + OPCODE_AE_ADDANDSUB32J, + OPCODE_AE_ADDW8, + OPCODE_AE_ADDW16, + OPCODE_AE_ADDW32, + OPCODE_AE_SUBW8, + OPCODE_AE_SUBW16, + OPCODE_AE_SUBW32, + OPCODE_AE_ACCW8, + OPCODE_AE_ACCW16, + OPCODE_AE_ACCW32, + OPCODE_AE_ADDW8U, + OPCODE_AE_SUBW8U, + OPCODE_AE_ACCW8U, + OPCODE_AE_MULFP32X2S_HH_LL, + OPCODE_AE_MULAFP32X2S_HH_LL, + OPCODE_AE_MULSFP32X2S_HH_LL, + OPCODE_AE_MULFP32X2S_HL_LH, + OPCODE_AE_MULAFP32X2S_HL_LH, + OPCODE_AE_MULSFP32X2S_HL_LH, + OPCODE_AE_MULZAAF2D32S_HH_LL, + OPCODE_AE_MULZASF2D32S_HH_LL, + OPCODE_AE_MULZSAF2D32S_HH_LL, + OPCODE_AE_MULZSSF2D32S_HH_LL, + OPCODE_AE_MULAAF2D32S_HH_LL, + OPCODE_AE_MULASF2D32S_HH_LL, + OPCODE_AE_MULSAF2D32S_HH_LL, + OPCODE_AE_MULSSF2D32S_HH_LL, + OPCODE_AE_MULZAAF2D32S_HL_LH, + OPCODE_AE_MULZASF2D32S_HL_LH, + OPCODE_AE_MULZSAF2D32S_HL_LH, + OPCODE_AE_MULZSSF2D32S_HL_LH, + OPCODE_AE_MULAAF2D32S_HL_LH, + OPCODE_AE_MULASF2D32S_HL_LH, + OPCODE_AE_MULSAF2D32S_HL_LH, + OPCODE_AE_MULSSF2D32S_HL_LH, + OPCODE_AE_MUL32S_HH, + OPCODE_AE_MULA32S_HH, + OPCODE_AE_MULS32S_HH, + OPCODE_AE_MUL32S_LL, + OPCODE_AE_MULA32S_LL, + OPCODE_AE_MULS32S_LL, + OPCODE_AE_MUL32S_HL, + OPCODE_AE_MULA32S_HL, + OPCODE_AE_MULS32S_HL, + OPCODE_AE_MUL32S_LH, + OPCODE_AE_MULA32S_LH, + OPCODE_AE_MULS32S_LH, + OPCODE_AE_MUL32X2S_HH_LL, + OPCODE_AE_MULA32X2S_HH_LL, + OPCODE_AE_MULS32X2S_HH_LL, + OPCODE_AE_MUL32X2S_HL_LH, + OPCODE_AE_MULA32X2S_HL_LH, + OPCODE_AE_MULS32X2S_HL_LH, + OPCODE_AE_MULZAAD32S_HH_LL, + OPCODE_AE_MULZASD32S_HH_LL, + OPCODE_AE_MULZSAD32S_HH_LL, + OPCODE_AE_MULZSSD32S_HH_LL, + OPCODE_AE_MULAAD32S_HH_LL, + OPCODE_AE_MULASD32S_HH_LL, + OPCODE_AE_MULSAD32S_HH_LL, + OPCODE_AE_MULSSD32S_HH_LL, + OPCODE_AE_MULZAAD32S_HL_LH, + OPCODE_AE_MULZASD32S_HL_LH, + OPCODE_AE_MULZSAD32S_HL_LH, + OPCODE_AE_MULZSSD32S_HL_LH, + OPCODE_AE_MULAAD32S_HL_LH, + OPCODE_AE_MULASD32S_HL_LH, + OPCODE_AE_MULSAD32S_HL_LH, + OPCODE_AE_MULSSD32S_HL_LH, + OPCODE_AE_MULF32X2RA_HH_LL, + OPCODE_AE_MULAF32X2RA_HH_LL, + OPCODE_AE_MULSF32X2RA_HH_LL, + OPCODE_AE_MULF32X2RA_HL_LH, + OPCODE_AE_MULAF32X2RA_HL_LH, + OPCODE_AE_MULSF32X2RA_HL_LH, + OPCODE_AE_MULZAAF2D32RA_HH_LL, + OPCODE_AE_MULZASF2D32RA_HH_LL, + OPCODE_AE_MULZSAF2D32RA_HH_LL, + OPCODE_AE_MULZSSF2D32RA_HH_LL, + OPCODE_AE_MULAAF2D32RA_HH_LL, + OPCODE_AE_MULASF2D32RA_HH_LL, + OPCODE_AE_MULSAF2D32RA_HH_LL, + OPCODE_AE_MULSSF2D32RA_HH_LL, + OPCODE_AE_MULZAAF2D32RA_HL_LH, + OPCODE_AE_MULZASF2D32RA_HL_LH, + OPCODE_AE_MULZSAF2D32RA_HL_LH, + OPCODE_AE_MULZSSF2D32RA_HL_LH, + OPCODE_AE_MULAAF2D32RA_HL_LH, + OPCODE_AE_MULASF2D32RA_HL_LH, + OPCODE_AE_MULSAF2D32RA_HL_LH, + OPCODE_AE_MULSSF2D32RA_HL_LH, + OPCODE_AE_MULF32X2R_HH_LL, + OPCODE_AE_MULAF32X2R_HH_LL, + OPCODE_AE_MULSF32X2R_HH_LL, + OPCODE_AE_MULF32X2R_HL_LH, + OPCODE_AE_MULAF32X2R_HL_LH, + OPCODE_AE_MULSF32X2R_HL_LH, + OPCODE_AE_MULFC32W, + OPCODE_AE_MULAFC32W, + OPCODE_AE_MULFCJ32W, + OPCODE_AE_MULAFCJ32W, + OPCODE_AE_MULFCJ32RAS, + OPCODE_AE_MULAFCJ32RAS, + OPCODE_AE_MULF2P32X4RS, + OPCODE_AE_MULAF2P32X4RS, + OPCODE_AE_MULSF2P32X4RS, + OPCODE_AE_MULF2P32X4RAS, + OPCODE_AE_MULAF2P32X4RAS, + OPCODE_AE_MULSF2P32X4RAS, + OPCODE_AE_MULP32X2S, + OPCODE_AE_MUL2P32X4S, + OPCODE_AE_MUL2P32X4, + OPCODE_AE_MULA2P32X4, + OPCODE_AE_MULS2P32X4, + OPCODE_AE_MUL2P32X4T, + OPCODE_AE_MULA2P32X4T, + OPCODE_AE_MULS2P32X4T, + OPCODE_AE_MULZAA32X2_HH_LL, + OPCODE_AE_MULZSS32X2_HH_LL, + OPCODE_AE_MULAA32X2_HH_LL, + OPCODE_AE_MULSS32X2_HH_LL, + OPCODE_AE_MULCJ32, + OPCODE_AE_MULACJ32, + OPCODE_AE_MULADDF32RS, + OPCODE_AE_MULADDF32RAS, + OPCODE_AE_MULSUBF32RS, + OPCODE_AE_MULSUBF32RAS, + OPCODE_AE_MULFC32RA, + OPCODE_AE_MULAFC32RA, + OPCODE_AE_MULCJ32W, + OPCODE_AE_MULACJ32W, + OPCODE_AE_MULC32W, + OPCODE_AE_MULAC32W, + OPCODE_AE_MULF2D32X2WS, + OPCODE_AE_MULZAAAA2Q16, + OPCODE_AE_MULAAAA2Q16, + OPCODE_AE_MULP16S_H, + OPCODE_AE_MULAP16S_H, + OPCODE_AE_MULSP16S_H, + OPCODE_AE_MULP16S_L, + OPCODE_AE_MULAP16S_L, + OPCODE_AE_MULSP16S_L, + OPCODE_AE_MULC16W_H, + OPCODE_AE_MULAC16W_H, + OPCODE_AE_MULC16W_L, + OPCODE_AE_MULAC16W_L, + OPCODE_AE_MUL2C16S, + OPCODE_AE_MULA2C16S, + OPCODE_AE_MULFC16S, + OPCODE_AE_MULAFC16S, + OPCODE_AE_MULFCJ16S, + OPCODE_AE_MULAFCJ16S, + OPCODE_AE_MULFCJ16RAS, + OPCODE_AE_MULAFCJ16RAS, + OPCODE_AE_MULC16S, + OPCODE_AE_MULAC16S, + OPCODE_AE_MULFP16X4RS, + OPCODE_AE_MULFD16X16X4RAS, + OPCODE_AE_MULP16X16X4S, + OPCODE_AE_MULAP16X16X4S, + OPCODE_AE_MULSP16X16X4S, + OPCODE_AE_MULZAA2D16SS_HH_LL, + OPCODE_AE_MULZAA2D16SS_HL_LH, + OPCODE_AE_MULZSS2D16SS_HH_LL, + OPCODE_AE_MULZSS2D16SS_HL_LH, + OPCODE_AE_MULAA2D16SS_HH_LL, + OPCODE_AE_MULAA2D16SS_HL_LH, + OPCODE_AE_MULSS2D16SS_HH_LL, + OPCODE_AE_MULSS2D16SS_HL_LH, + OPCODE_AE_MULZAAFD16SS_HH_LL, + OPCODE_AE_MULZAAFD16SS_HL_LH, + OPCODE_AE_MULZSSFD16SS_HH_LL, + OPCODE_AE_MULZSSFD16SS_HL_LH, + OPCODE_AE_MULAAFD16SS_HH_LL, + OPCODE_AE_MULAAFD16SS_HL_LH, + OPCODE_AE_MULSSFD16SS_HH_LL, + OPCODE_AE_MULSSFD16SS_HL_LH, + OPCODE_AE_MULFD16X16X4WS, + OPCODE_AE_MULZAAAA2Q16X8, + OPCODE_AE_MULAAAA2Q16X8, + OPCODE_AE_MULZAAAA2Q8, + OPCODE_AE_MULAAAA2Q8, + OPCODE_AE_MULC32X16W_H, + OPCODE_AE_MULAC32X16W_H, + OPCODE_AE_MULC32X16W_L, + OPCODE_AE_MULAC32X16W_L, + OPCODE_AE_MULPC32X16X2, + OPCODE_AE_MULAPC32X16X2, + OPCODE_AE_MULFP32X16_H, + OPCODE_AE_MULAFP32X16_H, + OPCODE_AE_MULSFP32X16_H, + OPCODE_AE_MULFP32X16_L, + OPCODE_AE_MULAFP32X16_L, + OPCODE_AE_MULSFP32X16_L, + OPCODE_AE_MULFC32X16W_H, + OPCODE_AE_MULAFC32X16W_H, + OPCODE_AE_MULFC32X16W_L, + OPCODE_AE_MULAFC32X16W_L, + OPCODE_AE_MULFCJ32X16W_H, + OPCODE_AE_MULAFCJ32X16W_H, + OPCODE_AE_MULFCJ32X16W_L, + OPCODE_AE_MULAFCJ32X16W_L, + OPCODE_AE_MULF2P32X16X4RAS, + OPCODE_AE_MULAF2P32X16X4RAS, + OPCODE_AE_MULSF2P32X16X4RAS, + OPCODE_AE_MULF2P32X16X4RS, + OPCODE_AE_MULAF2P32X16X4RS, + OPCODE_AE_MULSF2P32X16X4RS, + OPCODE_AE_MULF2P32X16X4S, + OPCODE_AE_MULAF2P32X16X4S, + OPCODE_AE_MULSF2P32X16X4S, + OPCODE_AE_MULFPC32X16X2RAS, + OPCODE_AE_MULAFPC32X16X2RAS, + OPCODE_AE_MULFPCJ32X16X2RAS, + OPCODE_AE_MULAFPCJ32X16X2RAS, + OPCODE_AE_MULZAAAA2Q32X16, + OPCODE_AE_MULAAAA2Q32X16, + OPCODE_AE_MUL2Q32X16_FIR_H, + OPCODE_AE_MULA2Q32X16_FIR_H, + OPCODE_AE_MUL2Q32X16_FIR_L, + OPCODE_AE_MULA2Q32X16_FIR_L, + OPCODE_AE_SRAI8, + OPCODE_AE_SRAI8R, + OPCODE_AE_SRLI8, + OPCODE_AE_SLAI8, + OPCODE_AE_SLAI8S, + OPCODE_AE_SLAA8, + OPCODE_AE_SRLA8, + OPCODE_AE_SLAA8S, + OPCODE_AE_SRAA8RS, + OPCODE_AE_SRAA8S, + OPCODE_AE_SRLI16, + OPCODE_AE_SLAI16, + OPCODE_AE_SLAA16, + OPCODE_AE_SRLA16, + OPCODE_AE_SRAI16SYM, + OPCODE_AE_SRAA16SYMS, + OPCODE_AE_SRAI32SYM, + OPCODE_AE_SRAA32SYMS, + OPCODE_AE_SRAV16RS, + OPCODE_AE_SRAV32RS, + OPCODE_AE_CVTI32X4F8_H, + OPCODE_AE_CVTI32X4F8_L, + OPCODE_AE_CVTI32X4F8S_H, + OPCODE_AE_CVTI32X4F8S_L, + OPCODE_AE_CVTA32X4F8_H, + OPCODE_AE_CVTA32X4F8_L, + OPCODE_AE_CVTA32X4F8S_H, + OPCODE_AE_CVTA32X4F8S_L, + OPCODE_AE_CVTI32X4F8U_H, + OPCODE_AE_CVTI32X4F8U_L, + OPCODE_AE_CVTI32X4F8US_H, + OPCODE_AE_CVTI32X4F8US_L, + OPCODE_AE_CVTA32X4F8U_H, + OPCODE_AE_CVTA32X4F8U_L, + OPCODE_AE_CVTA32X4F8US_H, + OPCODE_AE_CVTA32X4F8US_L, + OPCODE_AE_CVTI32X4F16, + OPCODE_AE_CVTI32X4F16S, + OPCODE_AE_CVTA32X4F16, + OPCODE_AE_CVTA32X4F16S, + OPCODE_AE_CVTI32X4F16U, + OPCODE_AE_CVTI32X4F16US, + OPCODE_AE_CVTA32X4F16U, + OPCODE_AE_CVTA32X4F16US, + OPCODE_AE_CVTI16X4X2F8, + OPCODE_AE_CVTI16X4X2F8S, + OPCODE_AE_CVTA16X4X2F8, + OPCODE_AE_CVTA16X4X2F8S, + OPCODE_AE_CVTI16X4X2F8U, + OPCODE_AE_CVTI16X4X2F8US, + OPCODE_AE_CVTA16X4X2F8U, + OPCODE_AE_CVTA16X4X2F8US, + OPCODE_AE_SEL8X8, + OPCODE_AE_SHFL8X8, + OPCODE_AE_SEL16X4, + OPCODE_AE_SHFL16X4, + OPCODE_AE_DSEL8X8, + OPCODE_AE_DSEL16X4, + OPCODE_AE_SEL8X8I, + OPCODE_AE_RMAX8X8, + OPCODE_AE_RMIN8X8, + OPCODE_AE_RMAX16X4, + OPCODE_AE_RMIN16X4, + OPCODE_AE_SORT16X4, + OPCODE_AE_RADD8X8_H, + OPCODE_AE_RADDA8X8_H, + OPCODE_AE_RADD8X8_L, + OPCODE_AE_RADDA8X8_L, + OPCODE_AE_RADD16X4, + OPCODE_AE_RADDA16X4, + OPCODE_AE_BMAX8X8_H, + OPCODE_AE_BMAX8X8_L, + OPCODE_AE_BMIN8X8_H, + OPCODE_AE_BMIN8X8_L, + OPCODE_AE_BMAX16X4, + OPCODE_AE_BMIN16X4, + OPCODE_AE_BMAX32X2, + OPCODE_AE_BMIN32X2, + OPCODE_AE_ADDINV16S, + OPCODE_AE_ADDINV32S, + OPCODE_AE_MOVT16X8, + OPCODE_AE_MOVT8X16_H, + OPCODE_AE_MOVT8X16_L, + OPCODE_AE_MOVBD1X4, + OPCODE_AE_MOVBD1X2, + OPCODE_AE_MOVNEG32S_T, + OPCODE_AE_MOVDEXT, + OPCODE_AE_MOVADEXT_H, + OPCODE_AE_MOVADEXT_L, + OPCODE_AE_NSA16X4, + OPCODE_AE_NSAZ32X4, + OPCODE_AE_NSA32X4, + OPCODE_AE_TRUNCI16X4F32S, + OPCODE_AE_TRUNCI16X4F64S, + OPCODE_AE_TRUNCA16X4F32S, + OPCODE_AE_TRUNCA16X4F64S, + OPCODE_AE_ADDC32, + OPCODE_AE_SUBC32, + OPCODE_AE_ADDC32U, + OPCODE_AE_SUBC32U, + OPCODE_AE_EXPADD16_H, + OPCODE_AE_EXPSUB16_H, + OPCODE_AE_EXPADD16_L, + OPCODE_AE_EXPSUB16_L, + OPCODE_AE_ADDCEXP32_H, + OPCODE_AE_ADDCEXP32_L, + OPCODE_AE_CALCRNG16, + OPCODE_AE_CALCRNG32, + OPCODE_AE_RNG32X4, + OPCODE_AE_LAV8X8X2_XP, + OPCODE_AE_LAV16X4X2_XP, + OPCODE_AE_SAV8X8X2_XP, + OPCODE_AE_SAV16X4X2_XP, + OPCODE_AE_MOVZBVCDR, + OPCODE_AE_MOVDRZBVC, + OPCODE_AE_LAVUNSQZ8X8_XP, + OPCODE_AE_LAVUNSQZ16X4_XP, + OPCODE_AE_MUL8Q8X8, + OPCODE_AE_MULA8Q8X8, + OPCODE_AE_MUL8Q4X16, + OPCODE_AE_MULA8Q4X16, + OPCODE_AE_MUL8Q8X16, + OPCODE_AE_MULA8Q8X16, + OPCODE_AE_MUL8QW8X16, + OPCODE_AE_MULA8QW8X16, + OPCODE_AE_MUL4O8X8, + OPCODE_AE_MULA4O8X8, + OPCODE_AE_MUL4O4X16, + OPCODE_AE_MULA4O4X16, + OPCODE_AE_MUL4O8X16, + OPCODE_AE_MULA4O8X16, + OPCODE_AE_MUL4QW8X16, + OPCODE_AE_MULA4QW8X16, + OPCODE_AE_MUL8Q8X8CNV_L, + OPCODE_AE_MUL8Q8X8CNV_H, + OPCODE_AE_MULA8Q8X8CNV_L, + OPCODE_AE_MULA8Q8X8CNV_H, + OPCODE_AE_MUL8Q8X16CNV, + OPCODE_AE_MULA8Q8X16CNV, + OPCODE_AE_MUL2X4Q8X8CNV_H, + OPCODE_AE_MULA2X4Q8X8CNV_H, + OPCODE_AE_MUL2X4Q8X8CNV_L, + OPCODE_AE_MULA2X4Q8X8CNV_L, + OPCODE_AE_MUL2X4Q8X16CNV, + OPCODE_AE_MULA2X4Q8X16CNV, + OPCODE_AE_MULQQ8X16CNV, + OPCODE_AE_MULAQQ8X16CNV, + OPCODE_AE_MUL4O8X8CNV_H, + OPCODE_AE_MULA4O8X8CNV_H, + OPCODE_AE_MUL4O8X8CNV_L, + OPCODE_AE_MULA4O8X8CNV_L, + OPCODE_AE_MUL4O8X16CNV_H, + OPCODE_AE_MULA4O8X16CNV_H, + OPCODE_AE_MUL4O8X16CNV_L, + OPCODE_AE_MULA4O8X16CNV_L, + OPCODE_AE_MUL8Q4X16CNV_H, + OPCODE_AE_MULA8Q4X16CNV_H, + OPCODE_AE_MUL8Q4X16CNV_L, + OPCODE_AE_MULA8Q4X16CNV_L, + OPCODE_AE_MUL2X4Q4X16CNV_H, + OPCODE_AE_MULA2X4Q4X16CNV_H, + OPCODE_AE_MUL2X4Q4X16CNV_L, + OPCODE_AE_MULA2X4Q4X16CNV_L, + OPCODE_AE_MULQQ4X16CNV_H, + OPCODE_AE_MULAQQ4X16CNV_H, + OPCODE_AE_MULQQ4X16CNV_L, + OPCODE_AE_MULAQQ4X16CNV_L, + OPCODE_AE_MUL4O4X16CNV_HH, + OPCODE_AE_MUL4O4X16CNV_HL, + OPCODE_AE_MUL4O4X16CNV_LH, + OPCODE_AE_MUL4O4X16CNV_LL, + OPCODE_AE_MULA4O4X16CNV_HH, + OPCODE_AE_MULA4O4X16CNV_HL, + OPCODE_AE_MULA4O4X16CNV_LH, + OPCODE_AE_MULA4O4X16CNV_LL, + OPCODE_AE_MULUU8Q8X8, + OPCODE_AE_MULAUU8Q8X8, + OPCODE_AE_MULUU4O8X8, + OPCODE_AE_MULAUU4O8X8, + OPCODE_AE_MULUU8Q8X8CNV_L, + OPCODE_AE_MULAUU8Q8X8CNV_L, + OPCODE_AE_MULUU8Q8X8CNV_H, + OPCODE_AE_MULAUU8Q8X8CNV_H, + OPCODE_AE_MULUU2X4Q8X8CNV_H, + OPCODE_AE_MULAUU2X4Q8X8CNV_H, + OPCODE_AE_MULUU2X4Q8X8CNV_L, + OPCODE_AE_MULAUU2X4Q8X8CNV_L, + OPCODE_AE_MULUU4O8X8CNV_H, + OPCODE_AE_MULAUU4O8X8CNV_H, + OPCODE_AE_MULUU4O8X8CNV_L, + OPCODE_AE_MULAUU4O8X8CNV_L, + OPCODE_AE_MULUS8Q8X8, + OPCODE_AE_MULAUS8Q8X8, + OPCODE_AE_MULUS8Q4X16, + OPCODE_AE_MULAUS8Q4X16, + OPCODE_AE_MULUS8Q8X16, + OPCODE_AE_MULAUS8Q8X16, + OPCODE_AE_MULUS8QW8X16, + OPCODE_AE_MULAUS8QW8X16, + OPCODE_AE_MULUS4O8X8, + OPCODE_AE_MULAUS4O8X8, + OPCODE_AE_MULUS4O4X16, + OPCODE_AE_MULAUS4O4X16, + OPCODE_AE_MULUS4O8X16, + OPCODE_AE_MULAUS4O8X16, + OPCODE_AE_MULUS4QW8X16, + OPCODE_AE_MULAUS4QW8X16, + OPCODE_AE_MULUS8Q8X8CNV_L, + OPCODE_AE_MULAUS8Q8X8CNV_L, + OPCODE_AE_MULUS8Q8X8CNV_H, + OPCODE_AE_MULAUS8Q8X8CNV_H, + OPCODE_AE_MULUS8Q8X16CNV, + OPCODE_AE_MULAUS8Q8X16CNV, + OPCODE_AE_MULUS2X4Q8X8CNV_H, + OPCODE_AE_MULAUS2X4Q8X8CNV_H, + OPCODE_AE_MULUS2X4Q8X8CNV_L, + OPCODE_AE_MULAUS2X4Q8X8CNV_L, + OPCODE_AE_MULUS2X4Q8X16CNV, + OPCODE_AE_MULAUS2X4Q8X16CNV, + OPCODE_AE_MULUSQQ8X16CNV, + OPCODE_AE_MULAUSQQ8X16CNV, + OPCODE_AE_MULUS4O8X8CNV_H, + OPCODE_AE_MULAUS4O8X8CNV_H, + OPCODE_AE_MULUS4O8X8CNV_L, + OPCODE_AE_MULAUS4O8X8CNV_L, + OPCODE_AE_MULUS4O8X16CNV_H, + OPCODE_AE_MULAUS4O8X16CNV_H, + OPCODE_AE_MULUS4O8X16CNV_L, + OPCODE_AE_MULAUS4O8X16CNV_L, + OPCODE_AE_MULUS8Q4X16CNV_H, + OPCODE_AE_MULAUS8Q4X16CNV_H, + OPCODE_AE_MULUS8Q4X16CNV_L, + OPCODE_AE_MULAUS8Q4X16CNV_L, + OPCODE_AE_MULUS2X4Q4X16CNV_H, + OPCODE_AE_MULAUS2X4Q4X16CNV_H, + OPCODE_AE_MULUS2X4Q4X16CNV_L, + OPCODE_AE_MULAUS2X4Q4X16CNV_L, + OPCODE_AE_MULUSQQ4X16CNV_H, + OPCODE_AE_MULAUSQQ4X16CNV_H, + OPCODE_AE_MULUSQQ4X16CNV_L, + OPCODE_AE_MULAUSQQ4X16CNV_L, + OPCODE_AE_MULUS4O4X16CNV_HH, + OPCODE_AE_MULUS4O4X16CNV_HL, + OPCODE_AE_MULUS4O4X16CNV_LH, + OPCODE_AE_MULUS4O4X16CNV_LL, + OPCODE_AE_MULAUS4O4X16CNV_HH, + OPCODE_AE_MULAUS4O4X16CNV_HL, + OPCODE_AE_MULAUS4O4X16CNV_LH, + OPCODE_AE_MULAUS4O4X16CNV_LL, + OPCODE_AE_MULSU8Q8X8, + OPCODE_AE_MULASU8Q8X8, + OPCODE_AE_MULSU4O8X8, + OPCODE_AE_MULASU4O8X8, + OPCODE_AE_MULSU8Q8X8CNV_L, + OPCODE_AE_MULASU8Q8X8CNV_L, + OPCODE_AE_MULSU8Q8X8CNV_H, + OPCODE_AE_MULASU8Q8X8CNV_H, + OPCODE_AE_MULSU2X4Q8X8CNV_H, + OPCODE_AE_MULASU2X4Q8X8CNV_H, + OPCODE_AE_MULSU2X4Q8X8CNV_L, + OPCODE_AE_MULASU2X4Q8X8CNV_L, + OPCODE_AE_MULSU4O8X8CNV_H, + OPCODE_AE_MULASU4O8X8CNV_H, + OPCODE_AE_MULSU4O8X8CNV_L, + OPCODE_AE_MULASU4O8X8CNV_L, + OPCODE_AE_MULUUZB8Q8X8, + OPCODE_AE_MULAUUZB8Q8X8, + OPCODE_AE_MULUUZB4O8X8, + OPCODE_AE_MULAUUZB4O8X8, + OPCODE_AE_MULUUZB8Q8X8CNV_L, + OPCODE_AE_MULAUUZB8Q8X8CNV_L, + OPCODE_AE_MULUUZB8Q8X8CNV_H, + OPCODE_AE_MULAUUZB8Q8X8CNV_H, + OPCODE_AE_MULUUZB2X4Q8X8CNV_H, + OPCODE_AE_MULAUUZB2X4Q8X8CNV_H, + OPCODE_AE_MULUUZB2X4Q8X8CNV_L, + OPCODE_AE_MULAUUZB2X4Q8X8CNV_L, + OPCODE_AE_MULUUZB4O8X8CNV_H, + OPCODE_AE_MULAUUZB4O8X8CNV_H, + OPCODE_AE_MULUUZB4O8X8CNV_L, + OPCODE_AE_MULAUUZB4O8X8CNV_L, + OPCODE_CVTSF16_L, + OPCODE_CVTSF16_H, + OPCODE_CVTF16S_L, + OPCODE_CVTF16S_H, + OPCODE_AE_MOVFCRFSRV, + OPCODE_AE_MOVVFCRFSR, + OPCODE_MOVT_S, + OPCODE_MOVF_S, + OPCODE_MOVEQZ_S, + OPCODE_MOVNEZ_S, + OPCODE_MOVGEZ_S, + OPCODE_MOVLTZ_S, + OPCODE_RFR, + OPCODE_WFR, + OPCODE_MUL_S, + OPCODE_MADD_S, + OPCODE_MSUB_S, + OPCODE_MSUBN_S, + OPCODE_MADDN_S, + OPCODE_ADD_S, + OPCODE_SUB_S, + OPCODE_OLE_S, + OPCODE_OLT_S, + OPCODE_OEQ_S, + OPCODE_UN_S, + OPCODE_ULE_S, + OPCODE_ULT_S, + OPCODE_UEQ_S, + OPCODE_NEXP01_S, + OPCODE_MKSADJ_S, + OPCODE_MKDADJ_S, + OPCODE_DIV0_S, + OPCODE_SQRT0_S, + OPCODE_RECIP0_S, + OPCODE_RSQRT0_S, + OPCODE_DIVN_S, + OPCODE_ADDEXP_S, + OPCODE_ADDEXPM_S, + OPCODE_MIN_S, + OPCODE_MAX_S, + OPCODE_MULMUX_S, + OPCODE_MADDMUX_S, + OPCODE_TRUNC_S, + OPCODE_UTRUNC_S, + OPCODE_TRUNC_SX2, + OPCODE_UTRUNC_SX2, + OPCODE_FICEIL_S, + OPCODE_FIFLOOR_S, + OPCODE_FIRINT_S, + OPCODE_FIROUND_S, + OPCODE_FITRUNC_S, + OPCODE_FLOAT_S, + OPCODE_UFLOAT_S, + OPCODE_FLOAT_SX2, + OPCODE_UFLOAT_SX2, + OPCODE_ABS_S, + OPCODE_NEG_S, + OPCODE_CONJC_S, + OPCODE_MULJC_S, + OPCODE_CONST_S, + OPCODE_CLSFY_S, + OPCODE_MINNUM_S, + OPCODE_MAXNUM_S, + OPCODE_ADDANDSUB_S, + OPCODE_ADDANDSUBJC_S, + OPCODE_ADD_HL_LH_S, + OPCODE_MADDA_S, + OPCODE_FREXP_S, + OPCODE_FLOATEXP_S, + OPCODE_MINNUMABS_S, + OPCODE_MAXNUMABS_S, + OPCODE_MULQ_S, + OPCODE_MADDQ_S, + OPCODE_MSUBQ_S, + OPCODE_MULMUXQ_S, + OPCODE_MADDMUXQ_S, + OPCODE_BMAXNUM_S, + OPCODE_BMINNUM_S, + OPCODE_BMAXNUMABS_S, + OPCODE_BMINNUMABS_S, + OPCODE_ABS_SX2X2, + OPCODE_NEG_SX2X2, + OPCODE_CONJC_SX2X2, + OPCODE_MULJC_SX2X2, + OPCODE_CONST_SX2X2, + OPCODE_ADD_SX2X2, + OPCODE_SUB_SX2X2, + OPCODE_MUL_SX2X2, + OPCODE_MADD_SX2X2, + OPCODE_MSUB_SX2X2, + OPCODE_MULMUX_SX2X2, + OPCODE_MADDMUX_SX2X2, + OPCODE_ABS_H, + OPCODE_ADDEXP_H, + OPCODE_ADDEXPM_H, + OPCODE_CLSFY_H, + OPCODE_CONJC_H, + OPCODE_CONST_H, + OPCODE_MIN_H, + OPCODE_MAX_H, + OPCODE_MINNUM_H, + OPCODE_MAXNUM_H, + OPCODE_MULJC_H, + OPCODE_NEG_H, + OPCODE_OEQ_H, + OPCODE_OLE_H, + OPCODE_OLT_H, + OPCODE_UEQ_H, + OPCODE_ULE_H, + OPCODE_ULT_H, + OPCODE_UN_H, + OPCODE_DIV0_H, + OPCODE_FICEIL_H, + OPCODE_FIFLOOR_H, + OPCODE_FIRINT_H, + OPCODE_FIROUND_H, + OPCODE_FITRUNC_H, + OPCODE_MKDADJ_H, + OPCODE_MKSADJ_H, + OPCODE_NEXP0_H, + OPCODE_NEXP01_H, + OPCODE_RECIP0_H, + OPCODE_RSQRT0_H, + OPCODE_SQRT0_H, + OPCODE_FLOAT16_H, + OPCODE_UFLOAT16_H, + OPCODE_TRUNC16_H, + OPCODE_UTRUNC16_H, + OPCODE_FLOAT16_HX4, + OPCODE_UFLOAT16_HX4, + OPCODE_TRUNC16_HX4, + OPCODE_UTRUNC16_HX4, + OPCODE_ADD_H, + OPCODE_SUB_H, + OPCODE_MUL_H, + OPCODE_MADD_H, + OPCODE_MSUB_H, + OPCODE_MADDN_H, + OPCODE_MSUBN_H, + OPCODE_DIVN_H, + OPCODE_RMINNUM_H, + OPCODE_RMAXNUM_H, + OPCODE_ABS_HX4X2, + OPCODE_NEG_HX4X2, + OPCODE_CONJC_HX4X2, + OPCODE_CONST_HX4X2, + OPCODE_MULJC_HX4X2, + OPCODE_ADD_HX4X2, + OPCODE_SUB_HX4X2, + OPCODE_MUL_HX4X2, + OPCODE_MADD_HX4X2, + OPCODE_MSUB_HX4X2, + OPCODE_MULQ_H, + OPCODE_MADDQ_H, + OPCODE_MULCNVH_HX4X2, + OPCODE_MULACNVH_HX4X2, + OPCODE_MULCNVL_HX4X2, + OPCODE_MULACNVL_HX4X2 +}; + + +/* Slot-specific opcode decode functions. */ + +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst_get (insn) == 0) + { + if (Field_op1_Slot_inst_get (insn) == 0) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_r_Slot_inst_get (insn) == 0) + { + if (Field_m_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return OPCODE_ILL; + if (Field_m_Slot_inst_get (insn) == 2) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_RET; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_RETW; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_JX; + } + if (Field_m_Slot_inst_get (insn) == 3) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALLX0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALLX4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALLX8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALLX12; + } + } + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_MOVSP; + if (Field_r_Slot_inst_get (insn) == 2) + { + if (Field_s_Slot_inst_get (insn) == 0) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_ISYNC; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RSYNC; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_ESYNC; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DSYNC; + if (Field_t_Slot_inst_get (insn) == 8) + return OPCODE_EXCW; + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_MEMW; + if (Field_t_Slot_inst_get (insn) == 13) + return OPCODE_EXTW; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_NOP; + } + } + if (Field_r_Slot_inst_get (insn) == 3) + { + if (Field_t_Slot_inst_get (insn) == 0) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_RFE; + if (Field_s_Slot_inst_get (insn) == 2) + return OPCODE_RFDE; + if (Field_s_Slot_inst_get (insn) == 4) + return OPCODE_RFWO; + if (Field_s_Slot_inst_get (insn) == 5) + return OPCODE_RFWU; + } + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFI; + if (Field_t_Slot_inst_get (insn) == 2 && + Field_s_Slot_inst_get (insn) == 1) + return OPCODE_CLREX; + } + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 4 && + Field_t_Slot_inst_get (insn) == 3) + return OPCODE_PFNXT_F; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 3) + return OPCODE_PFEND_A; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 3) + return OPCODE_PFEND_O; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 3) + return OPCODE_PFWAIT_A; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 3) + return OPCODE_PFWAIT_R; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BREAK; + if (Field_r_Slot_inst_get (insn) == 5) + { + if (Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SYSCALL; + if (Field_s_Slot_inst_get (insn) == 1) + return OPCODE_SIMCALL; + } + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RSIL; + if (Field_r_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_WAITI; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_LDDR32_P; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_SDDR32_P; + } + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_ANY4; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_ALL4; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_ANY8; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_ALL8; + } + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_AND; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_OR; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_XOR; + if (Field_op2_Slot_inst_get (insn) == 4) + { + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSR; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSL; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8L; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8B; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_thi3_Slot_inst_get (insn) == 0) + return OPCODE_SSAI; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RER; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_WER; + if (Field_r_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_ROTW; + if (Field_r_Slot_inst_get (insn) == 10 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_GETEX; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_NSA; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_NSAU; + } + if (Field_op2_Slot_inst_get (insn) == 5) + { + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_RPTLB0; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_PPTLB; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_WPTLB; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_RPTLB1; + } + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_NEG; + if (Field_s_Slot_inst_get (insn) == 1) + return OPCODE_ABS; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_ADD; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_ADDX2; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_ADDX4; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_ADDX8; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_SUB; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_SUBX2; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_SUBX4; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_SUBX8; + } + if (Field_op1_Slot_inst_get (insn) == 1) + { + if ((Field_op2_Slot_inst_get (insn) == 0 || + Field_op2_Slot_inst_get (insn) == 1)) + return OPCODE_SLLI; + if ((Field_op2_Slot_inst_get (insn) == 2 || + Field_op2_Slot_inst_get (insn) == 3)) + return OPCODE_SRAI; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_SRLI; + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_XSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_XSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_XSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_XSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_XSR_BR; + if (Field_sr_Slot_inst_get (insn) == 40) + return OPCODE_XSR_PREFCTL; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_XSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_XSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_XSR_MPUENB; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_XSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_XSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_XSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 98) + return OPCODE_XSR_CACHEADRDIS; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_XSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_XSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 119) + return OPCODE_XSR_OPMODE; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_XSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_XSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_XSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_XSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_XSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_XSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_XSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_XSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_XSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_XSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_XSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_XSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_XSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_XSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_XSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_XSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_XSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_XSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_XSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_XSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_XSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_XSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_XSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_XSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_XSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_XSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_XSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_XSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_XSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_XSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_XSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_XSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_XSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_XSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_XSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_XSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_XSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_XSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_XSR_MISC1; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_XSR_MISC2; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_XSR_MISC3; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_SRC; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRL; + if (Field_op2_Slot_inst_get (insn) == 10 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SLL; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRA; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MUL16U; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MUL16S; + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_LICT; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_SICT; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_LICW; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_SICW; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_L32EX; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_S32EX; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LDCT; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_SDCT; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_LDCW; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_SDCW; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_RFDO; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFDD; + } + } + if (Field_op1_Slot_inst_get (insn) == 2) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_ANDB; + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_ANDBC; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_ORB; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_ORBC; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_XORB; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_SALTU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_SALT; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MULL; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_QUOU; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_QUOS; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_REMU; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_REMS; + } + if (Field_op1_Slot_inst_get (insn) == 3) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_RSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_RSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_RSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_RSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_RSR_BR; + if (Field_sr_Slot_inst_get (insn) == 40) + return OPCODE_RSR_PREFCTL; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_RSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_RSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_RSR_MPUENB; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_RSR_MPUCFG; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_RSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_RSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_RSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 98) + return OPCODE_RSR_CACHEADRDIS; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_RSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_RSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 119) + return OPCODE_RSR_OPMODE; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_RSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_RSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_RSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_RSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_RSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_RSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_RSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_RSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_RSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_RSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_RSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_RSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_RSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_RSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_RSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_RSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_RSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_RSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_RSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 208) + return OPCODE_RSR_CONFIGID1; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_RSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_RSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_RSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_RSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_RSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_RSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_RSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_RSR_INTERRUPT; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_RSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_RSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_RSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_RSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_RSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_RSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 235) + return OPCODE_RSR_PRID; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_RSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_RSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_RSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_RSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_RSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_RSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_RSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_RSR_MISC1; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_RSR_MISC2; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_RSR_MISC3; + } + if (Field_op2_Slot_inst_get (insn) == 1) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_WSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_WSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_WSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_WSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_WSR_BR; + if (Field_sr_Slot_inst_get (insn) == 40) + return OPCODE_WSR_PREFCTL; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_WSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_WSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 89) + return OPCODE_WSR_MMID; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_WSR_MPUENB; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_WSR_MPUCFG; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_WSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_WSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_WSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 98) + return OPCODE_WSR_CACHEADRDIS; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_WSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_WSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 119) + return OPCODE_WSR_OPMODE; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_WSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_WSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_WSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_WSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_WSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_WSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_WSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_WSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_WSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_WSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_WSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_WSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_WSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_WSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_WSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_WSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_WSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_WSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_WSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_WSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_WSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_WSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_WSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_WSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_WSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_WSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_WSR_INTSET; + if (Field_sr_Slot_inst_get (insn) == 227) + return OPCODE_WSR_INTCLEAR; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_WSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_WSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_WSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_WSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_WSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_WSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_WSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_WSR_MISC1; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_WSR_MISC2; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_WSR_MISC3; + } + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_SEXT; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_CLAMPS; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_MIN; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_MAX; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_MINU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_MAXU; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MOVEQZ; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_MOVNEZ; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MOVLTZ; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MOVGEZ; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MOVF; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MOVT; + if (Field_op2_Slot_inst_get (insn) == 14) + { + if (Field_st_Slot_inst_get (insn) == 230) + return OPCODE_RUR_EXPSTATE; + if (Field_st_Slot_inst_get (insn) == 231) + return OPCODE_RUR_THREADPTR; + if (Field_st_Slot_inst_get (insn) == 232) + return OPCODE_RUR_FCR; + if (Field_st_Slot_inst_get (insn) == 233) + return OPCODE_RUR_FSR; + if (Field_st_Slot_inst_get (insn) == 240) + return OPCODE_RUR_AE_OVF_SAR; + if (Field_st_Slot_inst_get (insn) == 241) + return OPCODE_RUR_AE_BITHEAD; + if (Field_st_Slot_inst_get (insn) == 242) + return OPCODE_RUR_AE_TS_FTS_BU_BP; + if (Field_st_Slot_inst_get (insn) == 243) + return OPCODE_RUR_AE_CW_SD_NO; + if (Field_st_Slot_inst_get (insn) == 246) + return OPCODE_RUR_AE_CBEGIN0; + if (Field_st_Slot_inst_get (insn) == 247) + return OPCODE_RUR_AE_CEND0; + if (Field_st_Slot_inst_get (insn) == 248) + return OPCODE_RUR_AE_CBEGIN1; + if (Field_st_Slot_inst_get (insn) == 249) + return OPCODE_RUR_AE_CEND1; + if (Field_st_Slot_inst_get (insn) == 250) + return OPCODE_RUR_AE_CBEGIN2; + if (Field_st_Slot_inst_get (insn) == 251) + return OPCODE_RUR_AE_CEND2; + } + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WUR_EXPSTATE; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WUR_THREADPTR; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WUR_FCR; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WUR_FSR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WUR_AE_OVF_SAR; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WUR_AE_BITHEAD; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_WUR_AE_TS_FTS_BU_BP; + if (Field_sr_Slot_inst_get (insn) == 243) + return OPCODE_WUR_AE_CW_SD_NO; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_WUR_AE_CBEGIN0; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_WUR_AE_CEND0; + if (Field_sr_Slot_inst_get (insn) == 248) + return OPCODE_WUR_AE_CBEGIN1; + if (Field_sr_Slot_inst_get (insn) == 249) + return OPCODE_WUR_AE_CEND1; + if (Field_sr_Slot_inst_get (insn) == 250) + return OPCODE_WUR_AE_CBEGIN2; + if (Field_sr_Slot_inst_get (insn) == 251) + return OPCODE_WUR_AE_CEND2; + } + } + if ((Field_op1_Slot_inst_get (insn) == 4 || + Field_op1_Slot_inst_get (insn) == 5)) + return OPCODE_EXTUI; + if (Field_op1_Slot_inst_get (insn) == 9) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_L32E; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 3) + return OPCODE_DPFM_B; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 7) + return OPCODE_DPFM_BF; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 1) + return OPCODE_DPFR_B; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 5) + return OPCODE_DPFR_BF; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 2) + return OPCODE_DPFW_B; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 6) + return OPCODE_DPFW_BF; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 9) + return OPCODE_DHI_B; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 11) + return OPCODE_DHWBI_B; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 10) + return OPCODE_DHWB_B; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_S32E; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_S32NB; + } + if (Field_r_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_READ_IMPWIRE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_SETB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_CLRB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_WRMSK_EXPSTATE; + } + if (Field_op0_Slot_inst_get (insn) == 1) + return OPCODE_L32R; + if (Field_op0_Slot_inst_get (insn) == 2) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_L8UI; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_L16UI; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_L32I; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_S8I; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_S16I; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_S32I; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_DPFR; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_DPFW; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_DPFRO; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DPFWO; + if (Field_t_Slot_inst_get (insn) == 4) + return OPCODE_DHWB; + if (Field_t_Slot_inst_get (insn) == 5) + return OPCODE_DHWBI; + if (Field_t_Slot_inst_get (insn) == 6) + return OPCODE_DHI; + if (Field_t_Slot_inst_get (insn) == 7) + return OPCODE_DII; + if (Field_t_Slot_inst_get (insn) == 8) + { + if (Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_DPFL; + if (Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_DHU; + if (Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_DIU; + if (Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_DIWB; + if (Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_DIWBI; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_DIWBUI_P; + } + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_IPF; + if (Field_t_Slot_inst_get (insn) == 13) + { + if (Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_IPFL; + if (Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_IHU; + if (Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_IIU; + } + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_IHI; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_III; + } + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_L16SI; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_MOVI; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_L32AI; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_ADDI; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_ADDMI; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_S32RI; + } + if (Field_op0_Slot_inst_get (insn) == 4) + { + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 10) + return OPCODE_RUR_AE_OVERFLOW; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 11) + return OPCODE_WUR_AE_OVERFLOW; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_SAR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 13) + return OPCODE_WUR_AE_SAR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 14) + return OPCODE_RUR_AE_BITPTR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 15) + return OPCODE_WUR_AE_BITPTR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 0) + return OPCODE_RUR_AE_BITSUSED; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 1) + return OPCODE_WUR_AE_BITSUSED; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 2) + return OPCODE_RUR_AE_TABLESIZE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 3) + return OPCODE_WUR_AE_TABLESIZE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 4) + return OPCODE_RUR_AE_FIRST_TS; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 5) + return OPCODE_WUR_AE_FIRST_TS; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 6) + return OPCODE_RUR_AE_NEXTOFFSET; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 7) + return OPCODE_WUR_AE_NEXTOFFSET; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 8) + return OPCODE_RUR_AE_SEARCHDONE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 9) + return OPCODE_WUR_AE_SEARCHDONE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 10) + return OPCODE_RUR_AE_CWRAP; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 11) + return OPCODE_WUR_AE_CWRAP; + } + if (Field_op0_Slot_inst_get (insn) == 5) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALL0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALL4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALL8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALL12; + } + if (Field_op0_Slot_inst_get (insn) == 6) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_J; + if (Field_n_Slot_inst_get (insn) == 1) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQZ; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEZ; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTZ; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEZ; + } + if (Field_n_Slot_inst_get (insn) == 2) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQI; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEI; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEI; + } + if (Field_n_Slot_inst_get (insn) == 3) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_ENTRY; + if (Field_m_Slot_inst_get (insn) == 1) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BF; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BT; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LOOP; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_LOOPNEZ; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_LOOPGTZ; + } + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTUI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEUI; + } + } + if (Field_op0_Slot_inst_get (insn) == 7) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BNONE; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BEQ; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_BLT; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_BLTU; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BALL; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_BBC; + if ((Field_r_Slot_inst_get (insn) == 6 || + Field_r_Slot_inst_get (insn) == 7)) + return OPCODE_BBCI; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_BANY; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_BNE; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_BGE; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_BGEU; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_BNALL; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_BBS; + if ((Field_r_Slot_inst_get (insn) == 14 || + Field_r_Slot_inst_get (insn) == 15)) + return OPCODE_BBSI; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16b_get (insn) == 12) + { + if (Field_i_Slot_inst16b_get (insn) == 0) + return OPCODE_MOVI_N; + if (Field_i_Slot_inst16b_get (insn) == 1) + { + if (Field_z_Slot_inst16b_get (insn) == 0) + return OPCODE_BEQZ_N; + if (Field_z_Slot_inst16b_get (insn) == 1) + return OPCODE_BNEZ_N; + } + } + if (Field_op0_Slot_inst16b_get (insn) == 13) + { + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 1) + return OPCODE_AE_L16SI_N; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 2) + return OPCODE_AE_L16UI_N; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 3) + return OPCODE_AE_S16I_N; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 4 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 0) + return OPCODE_AE_SEXT16; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 4 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 1) + return OPCODE_AE_ZEXT16; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 5 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 1) + return OPCODE_AE_ZEXT8; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 5 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 0) + return OPCODE_AE_CLAMPS16; + if (Field_r_Slot_inst16b_get (insn) == 0) + return OPCODE_MOV_N; + if (Field_r_Slot_inst16b_get (insn) == 15) + { + if (Field_t_Slot_inst16b_get (insn) == 0) + return OPCODE_RET_N; + if (Field_t_Slot_inst16b_get (insn) == 1) + return OPCODE_RETW_N; + if (Field_t_Slot_inst16b_get (insn) == 2) + return OPCODE_BREAK_N; + if (Field_t_Slot_inst16b_get (insn) == 3 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_NOP_N; + if (Field_t_Slot_inst16b_get (insn) == 6 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_ILL_N; + } + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16a_get (insn) == 8) + return OPCODE_L32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 9) + return OPCODE_S32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 10) + return OPCODE_ADD_N; + if (Field_op0_Slot_inst16a_get (insn) == 11) + return OPCODE_ADDI_N; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae10_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae10_slot0_24_0_Slot_ae10_slot0_get (insn) == 12720387) + return OPCODE_NOP; + if (Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (insn) == 12872 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_ALL4; + if (Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (insn) == 12872 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_ANY4; + if (Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (insn) == 12873 && + Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_get (insn) == 18) + return OPCODE_SSAI; + if (Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (insn) == 12873 && + Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_ALL8; + if (Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (insn) == 12873 && + Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_ANY8; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3082) + return OPCODE_MAXU; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3083) + return OPCODE_MIN; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3084) + return OPCODE_SALT; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3085) + return OPCODE_SALTU; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3086) + return OPCODE_MOVF; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3087) + return OPCODE_MOVT; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3088) + return OPCODE_ORBC; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3089) + return OPCODE_XORB; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3090 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_ABS; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3090 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_NEG; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3104 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3144) + return OPCODE_ADD; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3145) + return OPCODE_ADDX2; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3146) + return OPCODE_MINU; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3147) + return OPCODE_MOVEQZ; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3148) + return OPCODE_SRC; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3149) + return OPCODE_SUB; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3150) + return OPCODE_CLAMPS; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3151) + return OPCODE_SEXT; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3154 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3154 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3208) + return OPCODE_ADDX4; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3209) + return OPCODE_ADDX8; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3210) + return OPCODE_MOVGEZ; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3211) + return OPCODE_MOVLTZ; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3212) + return OPCODE_SUBX2; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3213) + return OPCODE_SUBX4; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3214) + return OPCODE_SRLI; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3215) + return OPCODE_ANDB; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3272) + return OPCODE_AND; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3273) + return OPCODE_MAX; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3274) + return OPCODE_MOVNEZ; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3275) + return OPCODE_OR; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3276) + return OPCODE_SUBX8; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3277) + return OPCODE_XOR; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3278) + return OPCODE_ANDBC; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3279) + return OPCODE_ORB; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1296) + return OPCODE_AE_L16M_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1297) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1298) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1299) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1300) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1301) + return OPCODE_AE_L16_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1302) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1303) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1304) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1305) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1306) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1307) + return OPCODE_AE_L32_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1308) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1309) + return OPCODE_AE_L64_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1310) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1311) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1328) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1329) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1330) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1331) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1332) + return OPCODE_AE_L16_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1333) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1334) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1335) + return OPCODE_AE_L32M_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1336) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1337) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1338) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1339) + return OPCODE_AE_L32_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1340) + return OPCODE_AE_L32_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1341) + return OPCODE_AE_L64_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1342) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1343) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1360) + return OPCODE_AE_L16M_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1361) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1362) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1363) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1364) + return OPCODE_AE_L16_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1365) + return OPCODE_AE_L16_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1366) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1367) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1368) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1369) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1370) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1371) + return OPCODE_AE_L32_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1372) + return OPCODE_AE_L64_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1373) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1374) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1375) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1392) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1393) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1394) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1395) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1396) + return OPCODE_AE_L16_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1397) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1398) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1399) + return OPCODE_AE_L32M_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1400) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1401) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1402) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1403) + return OPCODE_AE_L32_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1404) + return OPCODE_AE_L64_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1405) + return OPCODE_AE_L64_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1406) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1407) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1536) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1537) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1538) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1539) + return OPCODE_AE_L8_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1540) + return OPCODE_SRAI; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1568) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1569) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1570) + return OPCODE_AE_L8_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1571) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1576 && + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1576 && + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1600) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1601) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1602) + return OPCODE_AE_L8_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1603) + return OPCODE_AE_L8_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1608 && + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1608 && + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1632) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1633) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1634) + return OPCODE_AE_L8_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1635) + return OPCODE_SLLI; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_6_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 12) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 13) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 14) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 15) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 158) + return OPCODE_ADDI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 159) + return OPCODE_ADDMI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 160) + return OPCODE_L16SI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 161) + return OPCODE_S16I; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 164) + return OPCODE_L16UI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 165) + return OPCODE_S32I; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 168) + return OPCODE_L32I; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 169) + return OPCODE_S8I; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 172) + return OPCODE_L8UI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 173) + return OPCODE_MOVI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 194 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 194 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 194 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae10_slot0_24_17_Slot_ae10_slot0_get (insn) == 78) + return OPCODE_EXTUI; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 12) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 13) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 14) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 15) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 16) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 17) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 18) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 19) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 20) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 21) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 22) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 23) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 24) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 25) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 26) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 27) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 28) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 29) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 30) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 31) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 32) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 33) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 34) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 35) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 36) + return OPCODE_J; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 37) + return OPCODE_CALL0; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_LAV16X4X2_XP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_AE_LAV8X8X2_XP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_L32R; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 6) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 7) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5155) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5156) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5157) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5152) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5153) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5154) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5158) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5159) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5160) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_8_Slot_ae10_slot0_get (insn) == 320) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_get (insn) == 9 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_get (insn) == 9 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49680 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_CALLX0; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49682 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_JX; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49683 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_RET; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49685 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SSA8B; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49686 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SSA8L; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49687 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SSL; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49688 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SSR; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae10_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae10_slot1_25_1_Slot_ae10_slot1_get (insn) == 10793092 && + Field_fld_ae10_slot1_0_0_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5134) + return OPCODE_MAXU; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5135) + return OPCODE_MIN; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5136) + return OPCODE_SALT; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5137) + return OPCODE_SALTU; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5138) + return OPCODE_CLAMPS; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5139) + return OPCODE_SEXT; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5140 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 10) + return OPCODE_SLL; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5196) + return OPCODE_ADD; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5197) + return OPCODE_ADDX2; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5198) + return OPCODE_MINU; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5199) + return OPCODE_MOVEQZ; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5200) + return OPCODE_SRC; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5201) + return OPCODE_SUB; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5202) + return OPCODE_SRLI; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5203 && + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5203 && + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5203 && + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5203 && + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5260) + return OPCODE_ADDX4; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5261) + return OPCODE_ADDX8; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5262) + return OPCODE_MOVGEZ; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5263) + return OPCODE_MOVLTZ; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5264) + return OPCODE_SUBX2; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5265) + return OPCODE_SUBX4; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5324) + return OPCODE_AND; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5325) + return OPCODE_MAX; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5326) + return OPCODE_MOVNEZ; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5327) + return OPCODE_OR; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5328) + return OPCODE_SUBX8; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5329) + return OPCODE_XOR; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2328) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2329) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2330) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2331) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2332) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2333) + return OPCODE_AE_L32_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2334) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2335) + return OPCODE_AE_L64_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2352) + return OPCODE_AE_L16M_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2353) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2354) + return OPCODE_AE_L16M_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2355) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2356) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2357) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2358) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2359) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2360) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2361) + return OPCODE_AE_L32M_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2362) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2363) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2364) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2365) + return OPCODE_AE_L32_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2366) + return OPCODE_AE_L32_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2367) + return OPCODE_AE_L64_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2384) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2385) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2386) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2387) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2388) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2389) + return OPCODE_AE_L16_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2390) + return OPCODE_AE_L16_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2391) + return OPCODE_AE_L16_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2392) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2393) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2394) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2395) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2396) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2397) + return OPCODE_AE_L32_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2398) + return OPCODE_AE_L64_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2399) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2416) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2417) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2418) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2419) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2420) + return OPCODE_AE_L16_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2421) + return OPCODE_AE_L16_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2422) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2423) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2424) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2425) + return OPCODE_AE_L32M_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2426) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2427) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2428) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2429) + return OPCODE_AE_L32_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2430) + return OPCODE_AE_L64_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2431) + return OPCODE_AE_L64_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2560) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2561) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2562) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2563) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2564) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2565) + return OPCODE_AE_L8_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2566) + return OPCODE_SRAI; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2570 && + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2592) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2593) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2594) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2595) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2596) + return OPCODE_AE_L8_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2597) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2602 && + Field_fld_ae10_slot1_3_2_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2602 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 4) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2602 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 5) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2602 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 6) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2602 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 7) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2624) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2625) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2626) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2627) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2628) + return OPCODE_AE_L8_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2629) + return OPCODE_AE_L8_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2633 && + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2633 && + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2656) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2657) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2658) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2659) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2660) + return OPCODE_AE_L8_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2661) + return OPCODE_SLLI; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2665 && + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2665 && + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 290) + return OPCODE_MOVI; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 292) + return OPCODE_ADDI; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 293) + return OPCODE_ADDMI; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 296) + return OPCODE_L16SI; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 297) + return OPCODE_L32I; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 300) + return OPCODE_L16UI; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 301) + return OPCODE_L8UI; + if (Field_fld_ae10_slot1_25_17_Slot_ae10_slot1_get (insn) == 144) + return OPCODE_EXTUI; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 48) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 49) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 50) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 51) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 52) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 53) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 54) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 55) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 56) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 57) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 58) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 59) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 60) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 61) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 62) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 63) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 64) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 65) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 66) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 67) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 68) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 69) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 70) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 71) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 6) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 7) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 6) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 7) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 352) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_get (insn) == 10 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 8) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_get (insn) == 10 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 9) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae10_slot1_25_22_Slot_ae10_slot1_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae10_slot1_25_23_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get (insn) == 82273 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 9) + return OPCODE_SSL; + if (Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get (insn) == 83266 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 10) + return OPCODE_SSA8B; + if (Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get (insn) == 83267 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 10) + return OPCODE_SSA8L; + if (Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get (insn) == 83297 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 9) + return OPCODE_SSR; + if (Field_fld_ae10_slot1_25_9_Slot_ae10_slot1_get (insn) == 41632 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 10) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae2_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L64_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L64_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L64_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32M_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S32_H_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S64_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S64_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S64_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_ADD; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_ADDX2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_ADDX4; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_ADDX8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AND; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SLLI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_SRAI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_MAX; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S8_0_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L8_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L8_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L8_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L8_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L8_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_SUB; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_SUBX2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_SUBX4; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_SUBX8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_OR; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_XOR; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_MOVEQZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_MOVGEZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_MOVLTZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_MOVNEZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_SRC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_SALT; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_SALTU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_MAXU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_MIN; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_MINU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_SRLI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_ANDB; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_ANDBC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_ORB; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_ORBC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_XORB; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_MOVF; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_MOVT; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_CLAMPS; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SEXT; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_CALLX0; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 10 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_JX; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_RET; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 22 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_SSA8B; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_SSA8L; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 30 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_SSL; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 12 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_MOVBD1X4; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_MOVBD1X2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_SA32X2_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_SA32X2F24_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_SA32X2F24_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SA24_L_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SA24_L_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_SA24X2_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SA24X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16X2M_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S32M_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6304 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 175) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6304 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 47) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6305 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 175) + return OPCODE_DPFM_B; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6305 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 47) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6306 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 47) + return OPCODE_DPFM_BF; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6306 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 175) + return OPCODE_DPFR_B; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6307 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 47) + return OPCODE_DPFR_BF; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6307 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 175) + return OPCODE_DPFW_B; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6308 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 175 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_SSR; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6308 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 47) + return OPCODE_DPFW_BF; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA32X2POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA32X2NEG_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4NEG_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA32X2POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA8X8POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA8X8NEG_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA8X8NEG_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA8X8POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA8X8POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_0_Slot_ae2_slot0_get (insn) == 36789) + return OPCODE_NOP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_0_Slot_ae2_slot0_get (insn) == 4020) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_2_Slot_ae2_slot0_get (insn) == 1004) + return OPCODE_AE_MOVALIGN; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24NEG_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6325 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6325 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6326 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6326 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24X2NEG_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6327 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6327 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24X2POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 49) + return OPCODE_SSAI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_ALL4; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_ANY4; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 33) + return OPCODE_ALL8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 33) + return OPCODE_ANY8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_4_Slot_ae2_slot0_get (insn) == 1585) + return OPCODE_AE_MOVASAR; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6407 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6411 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6415 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6419 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6420 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6423 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6426 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6426 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVTA32F24S_L; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6426 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVTA32F24S_H; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6426 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6427 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6427 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6427 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6427 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6427 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6430 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6430 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_NSA64; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6430 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_NSAZ16_0; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6430 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_ABS; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_NEG; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 12 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_TRUNCA32Q48; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6456 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6456 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6457 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6457 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6458 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6458 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6459 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6459 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6460 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6460 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6461 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6461 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6462 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6462 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6463 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6463 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16M_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L16M_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7534) + return OPCODE_ADDI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7535) + return OPCODE_ADDMI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7544) + return OPCODE_L16SI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7545) + return OPCODE_L32I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7546) + return OPCODE_S16I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7547) + return OPCODE_S8I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7548) + return OPCODE_L16UI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7549) + return OPCODE_L8UI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7550) + return OPCODE_S32I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7551) + return OPCODE_MOVI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7554 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7554 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7554 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_MOVI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_MOVAD8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7558 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7558 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7558 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_LA24_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_LA24_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_LA24X2_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_LA24X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L16_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L16_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L16_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L16_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L16_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L32M_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32M_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L32_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L32_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L32_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_get (insn) == 3224 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_TRUNC16_H; + if (Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_get (insn) == 3225 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_UTRUNC16_H; + if (Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_get (insn) == 3765) + return OPCODE_EXTUI; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 457) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 459) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 461) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 463) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1564 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_EQ8; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1565 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_LE8; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1566 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1566 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 31) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1566 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_LT8; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1567 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1567 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 31) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1567 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1567 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 27) + return OPCODE_AE_S24RA64S_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1568 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1569 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1570 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1571 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1572 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1573 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1600 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1600 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1600 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1600 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1601 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_AE_MOV; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1601 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1601 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1601 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1602 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1602 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1602 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_CVTF16S_L; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1602 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_CVTF16S_H; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1603 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_CVTSF16_L; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1603 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_CVTSF16_H; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1603 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_FICEIL_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1603 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_FIFLOOR_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1604 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1604 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_FIRINT_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1604 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_FIROUND_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1604 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_FITRUNC_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1605 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1608 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_OLE_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1608 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_OEQ_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1609 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_OLT_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1609 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_UEQ_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1610 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_ULE_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1610 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_ULT_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1611 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1611 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1611 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_UN_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1613 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_PKSR32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1613 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_PKSR24; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1613 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1613 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_PKSR16; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1806) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1807) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1810) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1811) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1812) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1813) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1814) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1815) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1816) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1817) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_S16X4RA32S_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_MOVT64; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MOVF64; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_MOVT_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_MOVF_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1864) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1865) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1866) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1867) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1868) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1869) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1870) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1871) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1874) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1875) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1876) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1877) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1878) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1879) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_LT16; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_LE16; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_EQ16; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LT32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_LE32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_EQ32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_LT64; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_LE64; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_EQ64; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_MOVEQZ_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_MOVNEZ_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_MOVGEZ_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_MOVLTZ_S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 232 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRAA32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 232 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRAA32RS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 232 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SLAA64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 233 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRAA32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 233 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SLAA64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 233 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRAA32SYMS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 234 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRAA64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 234 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SLAA8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 234 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRAA8RS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 235 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRAAQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 235 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SLAA8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 235 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRAA8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 768 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADD64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 768 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADD8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 769 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 769 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADD8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 770 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 770 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 771 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADDSUB32_HL_LH; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 771 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADDSUB32S_HL_LH; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 772 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_MAX32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 772 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MAX16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 773 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MAX64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 773 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_MAX8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 774 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_MIN32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 774 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MIN16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 775 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MIN64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 775 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_MIN8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 776 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUB16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 776 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MOVNEG32S_T; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 777 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUB24S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 777 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUB16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 778 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUB32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 778 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUB32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 779 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUB64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 779 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUB64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 780 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUB8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 780 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUB8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 781 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 781 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 782 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 787 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_FLOAT16_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 787 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_UFLOAT16_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 788 && + Field_fld_ae2_slot0_14_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 241) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 242) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 246) + return OPCODE_AE_ABS32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 245) + return OPCODE_AE_ABS24S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 247) + return OPCODE_AE_ABS32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 244) + return OPCODE_AE_ABS16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 243) + return OPCODE_AE_ABS16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 248) + return OPCODE_AE_ABS64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 252) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_ABS64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 255) + return OPCODE_AE_MUL16JS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 240) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_ABS8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_ABS8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 253) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 254) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 240) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 243) + return OPCODE_AE_NEG32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 242) + return OPCODE_AE_NEG24S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 244) + return OPCODE_AE_NEG32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 241) + return OPCODE_AE_NEG16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 245) + return OPCODE_AE_NEG64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 248) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 246) + return OPCODE_AE_NEG64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 247) + return OPCODE_AE_NEG8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 800 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 800 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 800 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 800 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 801 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 801 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L64_IP; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 801 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 801 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 802 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 802 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 802 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 802 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S64_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S64_IP; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_NSA16X4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FICEIL_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FIFLOOR_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FIRINT_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FIROUND_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 10 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FITRUNC_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 15 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_RMINNUM_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_RMAXNUM_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 804 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 28 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS24; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 804 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 30 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 804 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 29 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 804 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 31 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 805 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 30 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLASQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 805 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 28 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 805 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 31 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLASSQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 805 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 29 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 806 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 28 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAS24; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 806 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 29 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAS32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 806 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 31 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRASQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 806 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 30 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAS64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 807 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 28 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRLS24; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 807 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 29 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRLS32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 807 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 31 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRLSQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 807 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 30 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRLS64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 898) + return OPCODE_AE_TRUNCA16X4F32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 899) + return OPCODE_AE_TRUNCA16X4F64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 900) + return OPCODE_AE_TRUNCI32F64S_L; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 901) + return OPCODE_AE_TRUNCI32X2F64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 902) + return OPCODE_AE_SEL16I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 909 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_ADDC32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 909 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_ADDC32U; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 910 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_BMAX32X2; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 910 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_BMIN32X2; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 911 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SUBC32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 911 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SUBC32U; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 16) + return OPCODE_AE_SRAI16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 17) + return OPCODE_AE_SRAI16R; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 20) + return OPCODE_AE_SRLA32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SLAI16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SLAA16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_SLAAQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 23) + return OPCODE_AE_SRLAQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 21) + return OPCODE_AE_SRLA64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SLAASQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 22) + return OPCODE_AE_SRLA8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 24) + return OPCODE_AE_SRLI16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_SLAI16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_SLAA16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 19) + return OPCODE_AE_SRLA16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 18) + return OPCODE_AE_SRAI16SYM; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_AND; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_NAND; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_OR; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_XOR; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SRAV16RS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAV32RS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_NSAZ32X4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_NSA32X4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 930) + return OPCODE_AE_TRUNCA32F64S_L; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 931) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 940 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_CALL0; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 940 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_J; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_ADD32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_ADD16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_ADD24S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_ADD32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_ADD16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADD64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_BMAX16X4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_BMIN16X4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_SRA64_32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_SLAA32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_SRAA16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SRAA16RS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SLAA32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 18 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAI8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 19 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAI8R; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 20 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRLI8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAI8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 17 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAI8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SRAA16SYMS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_FLOAT16_HX4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_UFLOAT16_HX4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_TRUNC16_HX4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_UTRUNC16_HX4; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 56) + return OPCODE_AE_TRUNCI16X4F64S; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 57 && + Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_L32R; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 58 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SLAI64; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 58 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_SRLI64; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 58 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SRAI64; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 58 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SLAISQ56S; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 58 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAI64S; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 49 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_FLOAT_S; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 49 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_UFLOAT_S; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_TRUNC_S; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_UTRUNC_S; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 36) + return OPCODE_TRUNC_SX2; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 44) + return OPCODE_UTRUNC_SX2; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 32) + return OPCODE_FLOAT_SX2; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 40) + return OPCODE_UFLOAT_SX2; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_MOVT8X16_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_MOVT8X16_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_18_17_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_ADDW8; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_ADDW16; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_ADDW32; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SUBW8; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SUBW16; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SUBW32; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_ADDW8U; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SUBW8U; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 9 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 4 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 12 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 8 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 10 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 26) + return OPCODE_AE_CVTA32X4F8_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 27) + return OPCODE_AE_CVTA32X4F8_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 20) + return OPCODE_AE_CVTA32X4F8S_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 21) + return OPCODE_AE_CVTA32X4F8S_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 24) + return OPCODE_AE_CVTA32X4F8U_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 25) + return OPCODE_AE_CVTA32X4F8U_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 22) + return OPCODE_AE_CVTA32X4F8US_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 23) + return OPCODE_AE_CVTA32X4F8US_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 16) + return OPCODE_AE_CVTA32X4F16; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 17) + return OPCODE_AE_CVTA32X4F16S; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 18) + return OPCODE_AE_CVTA32X4F16U; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 19) + return OPCODE_AE_CVTA32X4F16US; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 28) + return OPCODE_AE_CVTI16X4X2F8; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 29) + return OPCODE_AE_CVTI16X4X2F8S; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 30) + return OPCODE_AE_CVTI16X4X2F8U; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 31) + return OPCODE_AE_CVTI16X4X2F8US; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_LAV8X8X2_XP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LAV16X4X2_XP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 27 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_CVTA16X4X2F8; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 27 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_CVTA16X4X2F8S; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 27 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_CVTA16X4X2F8U; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 27 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_CVTA16X4X2F8US; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_CVTI32X4F8_H; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_CVTI32X4F8_L; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_CVTI32X4F8S_H; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_CVTI32X4F8S_L; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_CVTI32X4F8U_H; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_CVTI32X4F8U_L; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_CVTI32X4F8US_H; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_CVTI32X4F8US_L; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_CVTI32X4F16; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_CVTI32X4F16S; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_CVTI32X4F16U; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVTI32X4F16US; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SLAI24; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_SRLI24; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_SRAI24; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SLAI32; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SRLI32; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SRAI32; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRAI32R; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAI24S; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SLAI32S; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRAI32SYM; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVDEXT; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_get (insn) == 16) + return OPCODE_AE_MOVADEXT_H; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_get (insn) == 17) + return OPCODE_AE_MOVADEXT_L; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCI16X4F32S; + if (Field_fld_ae2_slot0_40_26_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVT16X8; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_BBSI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_BALL_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_BANY_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_BBC_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_BBS_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_BEQ_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_BGEU_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_BGE_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_BLTU_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_BLT_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_BNALL_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_BNE_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_BNONE_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_BEQZ_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_BGEZ_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_BLTZ_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_BNEZ_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_BEQI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_BGEI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_BLTI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_BNEI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_BGEUI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_BLTUI_W15; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae2_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7692 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_SLL; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7692 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_TRUNCA32Q48; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7692 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_NSA64; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7692 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_NSAZ16_0; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7692 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7693 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7694 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7694 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7694 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7694 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7695 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7695 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7695 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7695 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7698) + return OPCODE_ADD; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7700 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7700 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7700 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7700 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7706) + return OPCODE_ADDX2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_0_Slot_ae2_slot1_get (insn) == 1794) + return OPCODE_NOP; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_SSL; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 5 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_SSR; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 6 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_MOVASAR; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7746) + return OPCODE_ADDX4; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7747 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_CVTA32F24S_H; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7754) + return OPCODE_ADDX8; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7755 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_CVTA32F24S_L; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7762) + return OPCODE_AND; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7763 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7770) + return OPCODE_MAX; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7771 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7778) + return OPCODE_MAXU; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7779 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7786) + return OPCODE_MIN; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7787 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7794) + return OPCODE_MINU; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7795 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7802) + return OPCODE_MOVEQZ; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7803 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7810) + return OPCODE_MOVGEZ; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7818) + return OPCODE_MOVLTZ; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7826) + return OPCODE_MOVNEZ; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7834) + return OPCODE_OR; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7842) + return OPCODE_SALT; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7850) + return OPCODE_SALTU; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7858) + return OPCODE_SRC; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7866) + return OPCODE_SUB; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7874) + return OPCODE_SUBX2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7882) + return OPCODE_SUBX4; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7890) + return OPCODE_SUBX8; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7898) + return OPCODE_XOR; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7906) + return OPCODE_CLAMPS; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7914) + return OPCODE_SEXT; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7922) + return OPCODE_SRLI; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7930) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7936 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_SSA8B; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7944 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_SSA8L; + if (Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_get (insn) == 1921 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_get (insn) == 1923 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 928 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_ABS_S; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 929 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_CONJC_H; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 930 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_CONJC_S; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 931 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_MULJC_H; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 932 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_MULJC_S; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 933 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_NEG_S; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 934 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 11) + return OPCODE_CONST_S; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 934 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 10) + return OPCODE_CONST_H; + if (Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_get (insn) == 480 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_SRAI; + if (Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_get (insn) == 496 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_SSAI; + if (Field_fld_ae2_slot1_36_17_Slot_ae2_slot1_get (insn) == 241 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_SLLI; + if (Field_fld_ae2_slot1_36_18_Slot_ae2_slot1_get (insn) == 120 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 13 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD8; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 12) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 13) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 14) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 15) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 16) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 17) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 18) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 19) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 20) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 21 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 21 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 21 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 21 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 22 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 22 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 22 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 22 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 23 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 23 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 23 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 23 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 24 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 24 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 24 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 24 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 25 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 25 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 25 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 25 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 26 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 26 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 26 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 26 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 27 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 27 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 27 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 27 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_ADDI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_ADDMI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_L16UI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_L16SI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_L32I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_L8UI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_MOVI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 83) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 84) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 80) + return OPCODE_AE_L16M_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 81) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 82) + return OPCODE_AE_L16M_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 85) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 100) + return OPCODE_AE_L16_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 101) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 97) + return OPCODE_AE_L16_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 98) + return OPCODE_AE_L16_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 99) + return OPCODE_AE_L16_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 102) + return OPCODE_AE_L16_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 106) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 107) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 103) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 104) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 105) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 108) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 126) + return OPCODE_AE_L32_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 127) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 123) + return OPCODE_AE_L32_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 124) + return OPCODE_AE_L32_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 125) + return OPCODE_AE_L32_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 112) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 109) + return OPCODE_AE_L32M_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 110) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 111) + return OPCODE_AE_L32M_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 113) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 89) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 90) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 86) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 87) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 88) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 91) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 115) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 116) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 114) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 117) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 119) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 120) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 118) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 122) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 93) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 94) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 92) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 96) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 121) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 95) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 8 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_MOVEQZ_S; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 9 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_MOVNEZ_S; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 8 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_MOVGEZ_S; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 9 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_MOVLTZ_S; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 11) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L64_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 11) + return OPCODE_AE_L64_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 13) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 7) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 15) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 8) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 14) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 12) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 7) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 8) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 9) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 10) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 11) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 12) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 13) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 14) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 15) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 16) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 17) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 26) + return OPCODE_AE_L8_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 27) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 23) + return OPCODE_AE_L8_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 24) + return OPCODE_AE_L8_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 25) + return OPCODE_AE_L8_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 28) + return OPCODE_AE_L8_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 49 && + Field_fld_ae2_slot1_3_3_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 19) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 20) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 48 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 18) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 22) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L64_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L64_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_AE_L64_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 21) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 49 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 14) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 29) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_MOV; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 49 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 12) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 49 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 8) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 49 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 10) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 14 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 14 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_NSA16X4; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_ABS_H; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_NEG_H; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 8 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_2_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 8 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae2_slot1_36_22_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae2_slot1_36_23_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae3_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (insn) == 133982 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_ALL4; + if (Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (insn) == 133982 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_ANY4; + if (Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (insn) == 133983 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 2 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_SSAI; + if (Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (insn) == 133983 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_ALL8; + if (Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (insn) == 133983 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_ANY8; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66890) + return OPCODE_AE_LBK; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66891) + return OPCODE_AND; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66894) + return OPCODE_MAX; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66895) + return OPCODE_MAXU; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66898) + return OPCODE_AE_SBI_IC; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66899) + return OPCODE_AE_SBI_IC1; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66902) + return OPCODE_AE_SBI_IP; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66903) + return OPCODE_AE_VLDL16T; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66906) + return OPCODE_AE_VLDL32T; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66907) + return OPCODE_AE_VLEL16T; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66910) + return OPCODE_AE_VLEL32T; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66911) + return OPCODE_MOVF; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66914) + return OPCODE_MOVT; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66915) + return OPCODE_AE_LBKI; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66918) + return OPCODE_CLAMPS; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66919) + return OPCODE_SEXT; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66922) + return OPCODE_SRLI; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66923) + return OPCODE_ANDB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66926) + return OPCODE_ANDBC; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66927) + return OPCODE_ORB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66930) + return OPCODE_ORBC; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66931) + return OPCODE_XORB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66950 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_SLL; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66951 && + Field_fld_ae3_slot0_9_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_MOVEA; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66990 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVBA1X2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_SRA; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_SRL; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_MOVAB4; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_MOVAB2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_MOVAB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_MOVBA; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_MOVBA4; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_AE_MOVBA2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get (insn) == 22) + return OPCODE_AE_MOVB2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get (insn) == 39) + return OPCODE_AE_MOVB4; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_AE_LBI; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_LBSI; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 2 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_MOVAE; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67354 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_ABS; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67354 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_AE_LB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67355 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_NEG; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67355 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_LBS; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67364) + return OPCODE_ADD; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67365) + return OPCODE_ADDX2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67366) + return OPCODE_ADDX4; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67367) + return OPCODE_ADDX8; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67368) + return OPCODE_SALTU; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67369) + return OPCODE_SRC; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67370) + return OPCODE_SUB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67371) + return OPCODE_SUBX2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67372) + return OPCODE_SUBX4; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67373) + return OPCODE_SUBX8; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67374) + return OPCODE_XOR; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67375) + return OPCODE_AE_SBI; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67409) + return OPCODE_MIN; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67411) + return OPCODE_MINU; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67413) + return OPCODE_MOVEQZ; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67415) + return OPCODE_MOVGEZ; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67417) + return OPCODE_MOVLTZ; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67419) + return OPCODE_MOVNEZ; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67421) + return OPCODE_OR; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67423) + return OPCODE_SALT; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33329) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33331) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33333) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33335) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33337) + return OPCODE_AE_L16_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33339) + return OPCODE_AE_L16_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33341) + return OPCODE_AE_L16_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33343) + return OPCODE_AE_L16_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33398) + return OPCODE_AE_L16M_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33399) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33400) + return OPCODE_AE_L16M_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33401) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33402) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33403) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33404) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33405) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33406) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33407) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33409) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33411) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33413) + return OPCODE_AE_S64_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33415) + return OPCODE_AE_S64_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33417) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33419) + return OPCODE_AE_S64_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33421) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33423) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33425) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33427) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33429) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33431) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33433) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33435) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33437) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33439) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33441) + return OPCODE_SLLI; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33443) + return OPCODE_SRAI; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33467 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33467 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33469 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33469 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33471 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33471 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33473 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33477 && + Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_get (insn) == 192) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33489 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33489 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33489 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33489 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33491 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33491 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33491 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33491 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA8X8_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33493 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33493 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33493 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33493 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_MOVI; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33536 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33537 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33538 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33539 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33540 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33541 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33542 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33543 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33544 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33545 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33546 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33547 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33548 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33549 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33550 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33551 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33552 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33553 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33554 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33555 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33556 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33557 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33558 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33559 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33560 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33561 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33562 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33563 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33564 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33565 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33566 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33567 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33568) + return OPCODE_AE_L16_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33569) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33570) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33571) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33572) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33573) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33574) + return OPCODE_AE_L32M_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33575) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33576) + return OPCODE_AE_L32M_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33577) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33578) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33579) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33580) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33581) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33582) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33583) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33584) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33585) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33586) + return OPCODE_AE_L32_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33587) + return OPCODE_AE_L32_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33588) + return OPCODE_AE_L32_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33589) + return OPCODE_AE_L32_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33590) + return OPCODE_AE_L32_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33591) + return OPCODE_AE_L64_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33592) + return OPCODE_AE_L64_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33593) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33594) + return OPCODE_AE_L64_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33595) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33596) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33597) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33598) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33599) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33600) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33601) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33602) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33603) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33604) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33605) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33606) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33607) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33608) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33609) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33610) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33611) + return OPCODE_AE_L8_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33612) + return OPCODE_AE_L8_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33613) + return OPCODE_AE_L8_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33614) + return OPCODE_AE_L8_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33615) + return OPCODE_AE_L8_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33616) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33617) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33618) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33619) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33620) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33621) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33622) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33623) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33624) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33625) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33626) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33627) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33628) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33629) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33630) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33631) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33632) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33633) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33634) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33635) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33636) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33637) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33638) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33639) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33640) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33641) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33642) + return OPCODE_AE_S32M_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33643) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33644) + return OPCODE_AE_S32M_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33645) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33646) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33647) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33648) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33649) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33650) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33651) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33652) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33653) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33654) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33655) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33656) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33657) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33658) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33659) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33660) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33661) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33662) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33663) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_AE_TRUNCA16P24S_L; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_NSAZ16_0; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33688 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33688 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33689 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33689 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33690 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33690 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_MOVAD8; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33691 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33691 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33691 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33691 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33694 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33694 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33694 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33694 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33695 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33695 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33695 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33695 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33728 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33729 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16698) + return OPCODE_AE_MOVT64; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16840 && + Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16840 && + Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_ABS32; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_AE_NEG24S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_ABS24S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 13) + return OPCODE_AE_ABS32S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_AE_NEG16S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_ABS16S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_ABS64; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_MOV; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_NEG32; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_AE_NEG32S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_AE_NEG64; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8338) + return OPCODE_AE_ADD16S; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8339) + return OPCODE_AE_ADD32S; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8340) + return OPCODE_AE_MAX32; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8341) + return OPCODE_AE_MIN32; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8342) + return OPCODE_AE_ROUND16X4F32SASYM; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8343) + return OPCODE_AE_ROUND24X2F48SSYM; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8344) + return OPCODE_AE_SUB16S; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8345) + return OPCODE_AE_SUB32S; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8346) + return OPCODE_AE_AND; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8347) + return OPCODE_AE_OR; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8348) + return OPCODE_AE_XOR; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8416 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8416 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8416 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8416 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8417 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8417 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L64_IP; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8417 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8417 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8418 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8418 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8418 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8418 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_S64_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8419 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8419 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S64_IP; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8424 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LT16; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8424 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LE32; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8424 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_EQ32; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8425 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8425 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8425 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LE16; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8425 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_EQ16; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8425 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LT32; + if (Field_fld_ae3_slot0_32_16_Slot_ae3_slot0_get (insn) == 4168) + return OPCODE_MOVI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2078) + return OPCODE_EXTUI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2079 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_ADDI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2079 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_ADDMI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2080 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_L16UI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2080 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_L16SI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2081 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_L32I; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2081 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_L8UI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2082 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_S16I; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2082 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_S32I; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2083 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_S8I; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2092 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2092 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_LOOPGTZ; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2092 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_LOOPNEZ; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1036) + return OPCODE_J; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1037) + return OPCODE_CALL0; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1048 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1048 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1048 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S16X4RA32S_IP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 256) + return OPCODE_L32R; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 257) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 258 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 258 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCI32X2F64S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 13 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SRAS24; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_SRLA32; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_SLAA16S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_SRAA16S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_SRAA16RS; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 13 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_AE_SLAA32S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_SRAA32S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_SLAAQ56; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SRAAQ56; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_AE_SLAA64; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SLAASQ56S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_SRLA16; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_BBSI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_BALL_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_BANY_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_BBC_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_BBS_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_BEQ_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_BGEU_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_BGE_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 13) + return OPCODE_BLTU_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_BLT_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_BNALL_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_BNE_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_BNONE_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_BEQZ_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_BGEZ_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get (insn) == 74) + return OPCODE_BLTZ_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get (insn) == 78) + return OPCODE_BNEZ_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_BEQI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_BGEI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_BLTI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_BNEI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_BGEUI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_BLTUI_W15; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071217 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_SBF; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071218 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLDL16C; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071219 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLES16C_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071221 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_SBF_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071222 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLDL16C_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071223 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLES16C_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071225 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_SBF_IC1; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071226 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLDL16C_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071227 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_CALLX0; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071229 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_SBF_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071230 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLES16C; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071841) + return OPCODE_AE_DB; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071843) + return OPCODE_AE_SB; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071845) + return OPCODE_AE_DB_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071847) + return OPCODE_AE_SB_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071849) + return OPCODE_AE_DB_IC1; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071851) + return OPCODE_AE_SB_IC1; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071853) + return OPCODE_AE_DB_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071855) + return OPCODE_AE_SB_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071856 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071858 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071860 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071862 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2POS_PC2; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071864 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071866 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071866 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_AE_VLDSHT; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071868 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071870 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_RUR_AE_BITPTR; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071870 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8NEG_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078411) + return OPCODE_AE_DBI; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078415) + return OPCODE_AE_DBI_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078443) + return OPCODE_AE_DBI_IC1; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078447) + return OPCODE_AE_DBI_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078475) + return OPCODE_AE_SHA32; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078479 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078479 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078479 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078479 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4POS_PC2; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078507 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8POS_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078507 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8POS_PC2; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078507 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078507 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_JX; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_get (insn) == 116) + return OPCODE_NOP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_RET; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_SSA8B; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_SSA8L; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_SSL; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_SSR; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_2_Slot_ae3_slot0_get (insn) == 28) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 2 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVALIGN; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae3_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae3_slot1_23_0_Slot_ae3_slot1_get (insn) == 1873411) + return OPCODE_NOP; + if (Field_fld_ae3_slot1_23_11_Slot_ae3_slot1_get (insn) == 914 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSAI; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 420) + return OPCODE_ADD; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 421) + return OPCODE_ADDX2; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 422) + return OPCODE_ADDX4; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 423) + return OPCODE_ADDX8; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 424) + return OPCODE_AE_LBK; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 425) + return OPCODE_AND; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 426) + return OPCODE_MAX; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 427) + return OPCODE_MAXU; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 428) + return OPCODE_MIN; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 429) + return OPCODE_MINU; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 430) + return OPCODE_MOVEQZ; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 431) + return OPCODE_MOVGEZ; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 432) + return OPCODE_MOVLTZ; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 433) + return OPCODE_MOVNEZ; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 434) + return OPCODE_OR; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 435) + return OPCODE_SALT; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 436) + return OPCODE_SALTU; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 437) + return OPCODE_SRC; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 438) + return OPCODE_SUB; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 439) + return OPCODE_SUBX2; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 440) + return OPCODE_SUBX4; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 441) + return OPCODE_SUBX8; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 442) + return OPCODE_XOR; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 443) + return OPCODE_CLAMPS; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 444) + return OPCODE_SEXT; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 445) + return OPCODE_SRLI; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 446) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 456 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 456 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 456 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 456 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 4) + return OPCODE_SRL; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 456 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_LB; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 457 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 457 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 457 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_LBI; + if (Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_get (insn) == 208) + return OPCODE_SLLI; + if (Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_get (insn) == 209) + return OPCODE_SRAI; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 34 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 34 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16M_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 34 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 34 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L16M_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 35 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 35 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 35 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 35 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 36 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 36 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 36 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 36 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 37 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L16_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 37 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L16_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 37 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 37 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 38 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L16_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 38 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 38 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L16_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 38 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 39 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 39 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 39 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 39 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 40 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 40 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32M_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 40 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 40 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L32M_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 41 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 41 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 41 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 41 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 42 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 42 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 42 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 42 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 43 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 43 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L32_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 43 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 43 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 44 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 44 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 44 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L64_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 44 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L64_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 45 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 45 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L64_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 45 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L64_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 45 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L64_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 46 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 46 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 46 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 46 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 47 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 47 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 47 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 47 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 48 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 48 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 48 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 48 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 49 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 49 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 49 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 49 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 50 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L8_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 50 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 50 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L8_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 50 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3 && + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3 && + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_MOVDA32X2; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 14) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 15) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0 && + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_MOVI; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_1_Slot_ae3_slot1_get (insn) == 6) + return OPCODE_AE_MOV; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 10) + return OPCODE_ADDI; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 11) + return OPCODE_ADDMI; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 12) + return OPCODE_L16SI; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 13) + return OPCODE_L16UI; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 14) + return OPCODE_L32I; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 15) + return OPCODE_L8UI; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 16) + return OPCODE_MOVI; + if (Field_fld_ae3_slot1_23_17_Slot_ae3_slot1_get (insn) == 4) + return OPCODE_EXTUI; + if (Field_fld_ae3_slot1_23_19_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_SEL16I; + if (Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_get (insn) == 28624) + return OPCODE_AE_MOVAE; + if (Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_get (insn) == 28625) + return OPCODE_AE_MOVEA; + if (Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (insn) == 7157 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (insn) == 7313 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSA8B; + if (Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (insn) == 7314 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSL; + if (Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (insn) == 7315 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSR; + if (Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (insn) == 7317 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSA8L; + if (Field_fld_ae3_slot1_23_9_Slot_ae3_slot1_get (insn) == 3576) + return OPCODE_AE_MOVAD32_L; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot0_22_0_Slot_ae4_slot0_get (insn) == 4088843) + return OPCODE_NOP; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 964) + return OPCODE_ADD; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 965) + return OPCODE_ADDX2; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 966) + return OPCODE_ADDX4; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 967) + return OPCODE_ADDX8; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 968) + return OPCODE_AND; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 969) + return OPCODE_MAX; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 970) + return OPCODE_MAXU; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 971) + return OPCODE_MIN; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 972) + return OPCODE_MINU; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 973) + return OPCODE_MOVEQZ; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 974) + return OPCODE_MOVGEZ; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 975) + return OPCODE_MOVLTZ; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 976) + return OPCODE_MOVNEZ; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 977) + return OPCODE_OR; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 978) + return OPCODE_SALT; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 979) + return OPCODE_SALTU; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 980) + return OPCODE_SRC; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 981) + return OPCODE_SUB; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 982) + return OPCODE_SUBX2; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 983) + return OPCODE_SUBX4; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 984) + return OPCODE_SUBX8; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 985) + return OPCODE_XOR; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 986) + return OPCODE_MOVF; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 987) + return OPCODE_MOVT; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 988) + return OPCODE_CLAMPS; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 989) + return OPCODE_SEXT; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 990) + return OPCODE_SRLI; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 991) + return OPCODE_ANDB; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 992) + return OPCODE_ANDBC; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 993) + return OPCODE_ORB; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 994) + return OPCODE_ORBC; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 995) + return OPCODE_XORB; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 996) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 997 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 997 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 997 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 1) + return OPCODE_SRA; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 997 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 1008 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_get (insn) == 480) + return OPCODE_SLLI; + if (Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_get (insn) == 481) + return OPCODE_SRAI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 50) + return OPCODE_ADDI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 51) + return OPCODE_ADDMI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 52) + return OPCODE_L16SI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 53) + return OPCODE_L16UI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 54) + return OPCODE_L32I; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 55) + return OPCODE_L8UI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 56) + return OPCODE_S16I; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 57) + return OPCODE_S32I; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 58) + return OPCODE_S8I; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 59) + return OPCODE_MOVI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 63 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 63 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 63 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae4_slot0_22_17_Slot_ae4_slot0_get (insn) == 24) + return OPCODE_EXTUI; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 4) + return OPCODE_AE_S32X2X2RNG_IP; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 5) + return OPCODE_AE_S32X2X2RNG_XP; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 6) + return OPCODE_AE_S32X2X2_IP; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 7) + return OPCODE_AE_S32X2X2_X; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 8) + return OPCODE_AE_S32X2X2_XP; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 9) + return OPCODE_J; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 10) + return OPCODE_CALL0; + if (Field_fld_ae4_slot0_22_20_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_L32R; + if (Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get (insn) == 63884) + return OPCODE_ALL4; + if (Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get (insn) == 63885) + return OPCODE_ANY4; + if (Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get (insn) == 63886 && + Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_ALL8; + if (Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get (insn) == 63886 && + Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_get (insn) == 1) + return OPCODE_ANY8; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15968) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15969) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15970) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 2) + return OPCODE_CALLX0; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 4) + return OPCODE_JX; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 5) + return OPCODE_RET; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 7) + return OPCODE_SSA8B; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 8) + return OPCODE_SSA8L; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 9) + return OPCODE_SSL; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 10) + return OPCODE_SSR; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_1_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot1_22_0_Slot_ae4_slot1_get (insn) == 2847494) + return OPCODE_NOP; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 668) + return OPCODE_ADD; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 669) + return OPCODE_ADDX2; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 670) + return OPCODE_ADDX4; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 671) + return OPCODE_ADDX8; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 672) + return OPCODE_AND; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 673) + return OPCODE_MAX; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 674) + return OPCODE_MAXU; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 675) + return OPCODE_MIN; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 676) + return OPCODE_MINU; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 677) + return OPCODE_MOVEQZ; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 678) + return OPCODE_MOVGEZ; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 679) + return OPCODE_MOVLTZ; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 680) + return OPCODE_MOVNEZ; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 681) + return OPCODE_OR; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 682) + return OPCODE_SALT; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 683) + return OPCODE_SALTU; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 684) + return OPCODE_SRC; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 685) + return OPCODE_SUB; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 686) + return OPCODE_SUBX2; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 687) + return OPCODE_SUBX4; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 688) + return OPCODE_SUBX8; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 689) + return OPCODE_XOR; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 690) + return OPCODE_CLAMPS; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 691) + return OPCODE_SEXT; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 692) + return OPCODE_SRLI; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 693) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 694 && + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 694 && + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 694 && + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 694 && + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 696 && + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 328) + return OPCODE_SLLI; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 329) + return OPCODE_SRAI; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 330) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 331) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 332) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 333) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 34) + return OPCODE_ADDI; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 35) + return OPCODE_ADDMI; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 36) + return OPCODE_L16SI; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 37) + return OPCODE_L16UI; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 38) + return OPCODE_L32I; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 39) + return OPCODE_L8UI; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 40) + return OPCODE_MOVI; + if (Field_fld_ae4_slot1_22_17_Slot_ae4_slot1_get (insn) == 16) + return OPCODE_EXTUI; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 0) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 1) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 2) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 3) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 4) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 5) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 6) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 7) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11120) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11121) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11122) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11123 && + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (insn) == 2) + return OPCODE_SSA8B; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11123 && + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (insn) == 3) + return OPCODE_SSA8L; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11123 && + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (insn) == 4) + return OPCODE_SSL; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11123 && + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (insn) == 5) + return OPCODE_SSR; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11123 && + Field_fld_ae4_slot1_3_1_Slot_ae4_slot1_get (insn) == 0) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae5_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67092) + return OPCODE_ADD; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67093) + return OPCODE_ADDX2; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67094) + return OPCODE_ADDX4; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67095) + return OPCODE_ADDX8; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67128) + return OPCODE_AND; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67129) + return OPCODE_MAX; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67130) + return OPCODE_MAXU; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67131) + return OPCODE_MIN; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67132) + return OPCODE_MINU; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67133) + return OPCODE_MOVEQZ; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67134) + return OPCODE_MOVGEZ; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67135) + return OPCODE_MOVLTZ; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67137) + return OPCODE_MOVNEZ; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67139) + return OPCODE_OR; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67141) + return OPCODE_SALT; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67143) + return OPCODE_SALTU; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67145) + return OPCODE_SRC; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67147) + return OPCODE_SUB; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67149) + return OPCODE_SUBX2; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67151) + return OPCODE_SUBX4; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67153) + return OPCODE_SUBX8; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67155) + return OPCODE_XOR; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67157) + return OPCODE_MOVF; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67159) + return OPCODE_MOVT; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67161) + return OPCODE_CLAMPS; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67163) + return OPCODE_SEXT; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67165) + return OPCODE_SRLI; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67167) + return OPCODE_AE_ARDECNORM16; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67169) + return OPCODE_ANDB; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67171) + return OPCODE_ANDBC; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67173) + return OPCODE_ORB; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67175) + return OPCODE_ORBC; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67177) + return OPCODE_XORB; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67228 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67234 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 11) + return OPCODE_ABS; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67234 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 7) + return OPCODE_SRA; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67234 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 15) + return OPCODE_SRL; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67235 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 11) + return OPCODE_NEG; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33328) + return OPCODE_AE_L16M_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33329) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33330) + return OPCODE_AE_L16M_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33331) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33332) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33333) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33334) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33335) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33336) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33337) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33338) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33339) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33340) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33341) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33342) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33343) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33376 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33376 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33377 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33377 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33378 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33378 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33379 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33379 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33380 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33380 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33381 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33381 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33382 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33382 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33383 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33383 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33384 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33384 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33385 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33385 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33386 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33386 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33387 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33387 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33387 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33388 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33388 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33388 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33389 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33389 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33389 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33390 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33390 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33390 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33391 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33391 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33391 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33392 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33392 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33392 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33393 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33393 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33393 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33394 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33394 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33394 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33395 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33395 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33395 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33396 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33396 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33396 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33397 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33397 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33397 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33398 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33398 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33398 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33399 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33399 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33399 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33400 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33400 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33400 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33401 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33401 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33401 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33402 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33402 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33402 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33403 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33403 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33403 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33404 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33404 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33404 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33405 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33405 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33405 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33406 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33406 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33406 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33407 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33407 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33407 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33408) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33409) + return OPCODE_AE_L16_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33410) + return OPCODE_AE_L16_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33411) + return OPCODE_AE_L16_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33412) + return OPCODE_AE_L16_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33413) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33414) + return OPCODE_AE_L16_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33415) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33416) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33417) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33418) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33419) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33420) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33421) + return OPCODE_AE_L32M_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33422) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33423) + return OPCODE_AE_L32M_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33424) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33425) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33426) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33427) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33428) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33429) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33430) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33431) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33432) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33433) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33434) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33435) + return OPCODE_AE_L32_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33436) + return OPCODE_AE_L32_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33437) + return OPCODE_AE_L32_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33438) + return OPCODE_AE_L32_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33439) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33440) + return OPCODE_AE_L32_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33441) + return OPCODE_AE_L64_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33442) + return OPCODE_AE_L64_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33443) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33444) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33445) + return OPCODE_AE_L64_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33446) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33447) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33448) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33449) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33450) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33451) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33452) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33453) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33454) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33455) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33456) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33457) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33458) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33459) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33460) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33461) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33462) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33463) + return OPCODE_AE_L8_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33464) + return OPCODE_AE_L8_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33465) + return OPCODE_AE_L8_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33466) + return OPCODE_AE_L8_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33467) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33468) + return OPCODE_AE_L8_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33469) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33470) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33471) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33472) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33473) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33474) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33475) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33476) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33477) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33478) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33479) + return OPCODE_AE_S16X2M_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33480) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33481) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33482) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33483) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33484) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33485) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33486) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33487) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33488) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33489) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33490) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33491) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33492) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33493) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33494) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33495) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33496) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33497) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33498) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33499) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33500) + return OPCODE_AE_S32M_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33501) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33502) + return OPCODE_AE_S32M_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33503) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33504) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33505) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33506) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33507) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33508) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33509) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33510) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33511) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33512) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33513) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33514) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33515) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33516) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33517) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33518) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33519) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33520) + return OPCODE_AE_S32_H_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33521) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33522) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33523) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33524) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33525) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33526) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33527) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33528) + return OPCODE_AE_S64_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33529) + return OPCODE_AE_S64_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33530) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33531) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33532) + return OPCODE_AE_S64_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33533) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33534) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33535) + return OPCODE_AE_S8X8_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33536) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33537) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33538) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33539) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33540) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33541) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33542) + return OPCODE_AE_S8_0_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33543) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33544) + return OPCODE_SLLI; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33545) + return OPCODE_SRAI; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33608 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33608 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_MOVAD8; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33609 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33610 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33611 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33612 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33613 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33615 && + Field_fld_ae5_slot0_7_0_Slot_ae5_slot0_get (insn) == 48) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33616 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33616 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33616 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33616 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA8X8_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 9) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 13) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 10) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 14) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_RIP; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8387 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8387 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8387 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8387 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8388 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8388 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_L64_IP; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8388 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8388 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8389 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8389 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8389 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8389 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_S64_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8390 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8390 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_S64_IP; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8400 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8400 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 7) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4150) + return OPCODE_ADDI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4151) + return OPCODE_ADDMI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4152) + return OPCODE_AE_LBK_DB; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4153) + return OPCODE_AE_LBK_DB_IC; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4154) + return OPCODE_AE_LBK_DB_IP; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4155) + return OPCODE_L16SI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4156) + return OPCODE_L16UI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4157) + return OPCODE_L32I; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4158) + return OPCODE_L8UI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4159) + return OPCODE_S16I; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4160) + return OPCODE_S32I; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4161) + return OPCODE_S8I; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4162) + return OPCODE_AE_LBKI_DBI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4163) + return OPCODE_AE_LBKI_DBI_IC; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4164) + return OPCODE_AE_LBKI_DBI_IP; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4165) + return OPCODE_MOVI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_AE_LBI_DBI_IC; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_AE_LBI_DBI_IP; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LBI_DBI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LB_DB_IC; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LB_DB_IP; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LB_DB; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_get (insn) == 2 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_CALCRNG16; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_get (insn) == 3 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_CALCRNG32; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4201 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4201 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4201 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae5_slot0_29_17_Slot_ae5_slot0_get (insn) == 2074) + return OPCODE_EXTUI; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1034) + return OPCODE_J; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1035) + return OPCODE_CALL0; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 25) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 27) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 28) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 31) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 30) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 29) + return OPCODE_AE_S32RA64S_XC1; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 20) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 22) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 21) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 26) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 23) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 24) + return OPCODE_AE_S24RA64S_XC1; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_ADD32; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_ADD32S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 9) + return OPCODE_MOVT_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_MOVF_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_MOVEQZ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_MOVNEZ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_MOVGEZ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 7) + return OPCODE_MOVLTZ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_S16X4RA32S_IP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (insn) == 12) + return OPCODE_AE_PKSR32; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (insn) == 28) + return OPCODE_AE_PKSR24; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (insn) == 28) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (insn) == 12) + return OPCODE_AE_PKSR16; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_get (insn) == 101) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_AE_MOVDA16X2; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_get (insn) == 100) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_6_Slot_ae5_slot0_get (insn) == 24) + return OPCODE_AE_MOVI; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_CVTP24A16X2_LH; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_CVTP24A16X2_HL; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_CVTP24A16X2_HH; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_get (insn) == 102) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_OLE_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 2 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_OLT_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_OEQ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 3 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_UN_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 2 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_ULE_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 2 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_ULT_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 2 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_UEQ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1051 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1051 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_MOV; + if (Field_fld_ae5_slot0_29_19_Slot_ae5_slot0_get (insn) == 516) + return OPCODE_AE_SEL16I; + if (Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_get (insn) == 256) + return OPCODE_L32R; + if (Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_get (insn) == 257) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_BBSI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_BALL_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_BANY_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_BBC_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 7) + return OPCODE_BBS_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_BEQ_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 9) + return OPCODE_BGEU_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 10) + return OPCODE_BGE_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 11) + return OPCODE_BLTU_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 12) + return OPCODE_BLT_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 13) + return OPCODE_BNALL_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 14) + return OPCODE_BNE_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 15) + return OPCODE_BNONE_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get (insn) == 12) + return OPCODE_BEQZ_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get (insn) == 14) + return OPCODE_BGEZ_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get (insn) == 28) + return OPCODE_BLTZ_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get (insn) == 30) + return OPCODE_BNEZ_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_BEQI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_BGEI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_BLTI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 10) + return OPCODE_BNEI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_BGEUI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_BLTUI_W15; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605313 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_VLDL16C_IC1; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605321 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_VLES16C_IC1; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605329 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_CALLX0; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605345 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_JX; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605353 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_RET; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605369 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_SSA8B; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605377 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_SSA8L; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605385 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_SSL; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605393 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_SSR; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605401 && + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (insn) == 17) + return OPCODE_NOP; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605401 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae5_slot0_29_6_Slot_ae5_slot0_get (insn) == 4301276 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_MOVALIGN; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075222 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075222 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075222 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4POS_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075222 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4NEG_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075223 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075223 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075223 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24NEG_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075223 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4POS_PC2; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075254 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA24POS_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075254 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075254 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075254 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2NEG_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075255 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA24X2POS_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075255 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075255 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075255 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2NEG_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075286 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075286 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2POS_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075286 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2POS_PC2; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075286 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8NEG_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075287 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8POS_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075287 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8POS_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075287 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8NEG_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075287 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8POS_PC2; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075318 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_ALL4; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075318 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_ANY4; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075318 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075318 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075319 && + Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_SSAI; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075319 && + Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_ALL8; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075319 && + Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_ANY8; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075319 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_RUR_AE_BITPTR; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae8_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10761) + return OPCODE_ADD; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10765) + return OPCODE_ADDX2; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10769) + return OPCODE_ADDX4; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10773) + return OPCODE_ADDX8; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10777) + return OPCODE_AND; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10781) + return OPCODE_MAX; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10785) + return OPCODE_MAXU; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10789) + return OPCODE_MIN; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10793) + return OPCODE_MINU; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10797) + return OPCODE_MOVEQZ; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10801) + return OPCODE_MOVGEZ; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10805) + return OPCODE_MOVLTZ; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10809) + return OPCODE_MOVNEZ; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10813) + return OPCODE_OR; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10817) + return OPCODE_SALT; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10821) + return OPCODE_SALTU; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10825) + return OPCODE_SRC; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10829) + return OPCODE_SUB; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10833) + return OPCODE_SUBX2; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10837) + return OPCODE_SUBX4; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10841) + return OPCODE_SUBX8; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10845) + return OPCODE_XOR; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10849) + return OPCODE_MOVF; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10853) + return OPCODE_MOVT; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10857) + return OPCODE_CLAMPS; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10861) + return OPCODE_SEXT; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10865) + return OPCODE_SRLI; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10869) + return OPCODE_ANDB; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10873) + return OPCODE_ANDBC; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10877) + return OPCODE_ORB; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10881) + return OPCODE_ORBC; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10885) + return OPCODE_XORB; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10889 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10889 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10889 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10889 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10893 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (insn) == 1344 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_SLLI; + if (Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (insn) == 1360 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_ALL4; + if (Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (insn) == 1360 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_ANY4; + if (Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (insn) == 1360 && + Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_get (insn) == 102) + return OPCODE_ALL8; + if (Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (insn) == 1360 && + Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_get (insn) == 103) + return OPCODE_ANY8; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 94) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 95) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 96) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 97) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 98) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 99) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 100) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 101) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 102) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 103) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 104) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 105) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 106) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 107) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 108) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 109) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 110) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 111) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 112) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 113) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 114) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 115) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 116) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 117) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 118) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 119) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 120) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 121) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 122) + return OPCODE_AE_S16X4X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 123) + return OPCODE_AE_S16X4X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 124) + return OPCODE_AE_S16X4X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 125) + return OPCODE_AE_S16X4X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 126) + return OPCODE_AE_S16X4X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 127) + return OPCODE_AE_S16X4X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 128) + return OPCODE_AE_S16X4X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 129) + return OPCODE_AE_S32X2X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 130) + return OPCODE_AE_S32X2X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 131) + return OPCODE_AE_S32X2X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 132) + return OPCODE_AE_S32X2X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 133) + return OPCODE_AE_S32X2X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 134) + return OPCODE_AE_S32X2X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 135) + return OPCODE_AE_S32X2X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 136) + return OPCODE_AE_S64X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 137) + return OPCODE_AE_S64X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 138) + return OPCODE_AE_S64X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 139) + return OPCODE_AE_S64X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 140) + return OPCODE_AE_S64X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 141) + return OPCODE_AE_S64X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 142) + return OPCODE_AE_S64X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 143) + return OPCODE_AE_S8X8X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 144) + return OPCODE_AE_S8X8X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 145) + return OPCODE_AE_S8X8X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 146) + return OPCODE_AE_S8X8X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 147) + return OPCODE_AE_S8X8X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 148) + return OPCODE_AE_S8X8X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 149) + return OPCODE_AE_S8X8X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 150) + return OPCODE_J; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 151) + return OPCODE_CALL0; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 153 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 153 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 153 && + Field_fld_ae8_slot0_13_13_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 154 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_L16SI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 154 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_L32I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 154 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_S16I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 154 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_S8I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 155 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_L16UI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 155 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_L8UI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 155 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_MOVI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 155 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_S32I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 160 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 0 && + Field_fld_ae8_slot0_7_5_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_SRAI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L16M_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_L16_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 17) + return OPCODE_AE_L8_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_L32_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_L32_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_L32M_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_L64_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 20) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 26) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 21) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 19) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 18) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 29) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 27) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 28) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 23) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 30) + return OPCODE_AE_S64_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 24) + return OPCODE_AE_S32M_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 25) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 16) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 22) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 31) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_L16_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 17) + return OPCODE_AE_L8_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_L32_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 16) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_L64_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 20) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 25) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 21) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 22) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 18) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 19) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 29) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 28) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 27) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 23) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 30) + return OPCODE_AE_S64_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 31) + return OPCODE_AE_S64_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 24) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 26) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L16M_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_L16_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 17) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 16) + return OPCODE_AE_L8_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_L32_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_L32M_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_L64_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 20) + return OPCODE_AE_S16X2M_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 19) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 25) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 26) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 21) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 31) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 18) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 28) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 29) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 27) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 23) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 22) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 30) + return OPCODE_AE_S64_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 24) + return OPCODE_AE_S32M_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_L16_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_L16_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 16) + return OPCODE_AE_L8_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 17) + return OPCODE_AE_L8_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_L32_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_L64_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_L64_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 19) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 20) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 25) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 21) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 31) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 18) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 28) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 27) + return OPCODE_AE_S32_H_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 26) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 22) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 23) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 30) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 29) + return OPCODE_AE_S64_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 24) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 168 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 168 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 168 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_S8_0_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 168 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 169 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 169 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 169 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 169 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 40) + return OPCODE_AE_TRUNCA16X4F32S; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 41) + return OPCODE_AE_TRUNCA16X4F64S; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 42) + return OPCODE_AE_TRUNCA32F64S_L; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 43) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 44) + return OPCODE_AE_TRUNCI32F64S_L; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 45) + return OPCODE_AE_TRUNCI32X2F64S; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 46) + return OPCODE_AE_SEL16I; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_SAT16X4; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_ROUND16X4F32SSYM; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_ROUND16X4F32SASYM; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_SATU16X4; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_SAT8X4X32_L; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_SATU8X4X32_L; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 81 && + Field_fld_ae8_slot0_8_0_Slot_ae8_slot0_get (insn) == 128) + return OPCODE_AE_MOV; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_LAV16X4X2_XP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_LAV8X8X2_XP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 16) + return OPCODE_AE_SAV16X4X2_XP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 17) + return OPCODE_AE_SAV8X8X2_XP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 18) + return OPCODE_L32R; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 19) + return OPCODE_AE_TRUNCI16X4F32S; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_SA16X4X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_SA16X4X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_SA16X4X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_SA16X4X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_SA8X8X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_SA8X8X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_SA8X8X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_SA8X8X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 243) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 244) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 245) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 240) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 241) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 242) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 246) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 247) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 248) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_SA32X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_SA8X8_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_SA8X8_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_SA8X8_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_SA8X8_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_8_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae8_slot0_31_21_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_TRUNCI16X4F64S; + if (Field_fld_ae8_slot0_31_22_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae8_slot0_31_23_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae8_slot0_31_7_Slot_ae8_slot0_get (insn) == 348594 && + Field_fld_ae8_slot0_6_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174288 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_CALLX0; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174290 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_JX; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174291 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_RET; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174293 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_SSA8B; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174294 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_SSA8L; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174295 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_SSL; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174296 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_SSR; + if (Field_fld_ae8_slot0_31_9_Slot_ae8_slot0_get (insn) == 87107 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae8_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5386) + return OPCODE_AND; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5387) + return OPCODE_MINU; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5388) + return OPCODE_MOVNEZ; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5389) + return OPCODE_SRC; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5390) + return OPCODE_SUBX8; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5391) + return OPCODE_SRLI; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5450) + return OPCODE_MAX; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5451) + return OPCODE_MOVEQZ; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5452) + return OPCODE_OR; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5453) + return OPCODE_SUB; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5454) + return OPCODE_XOR; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5455 && + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5455 && + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5455 && + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5455 && + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5512) + return OPCODE_ADD; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5513) + return OPCODE_ADDX4; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5514) + return OPCODE_MAXU; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5515) + return OPCODE_MOVGEZ; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5516) + return OPCODE_SALT; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5517) + return OPCODE_SUBX2; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5518) + return OPCODE_CLAMPS; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5522 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SLL; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5576) + return OPCODE_ADDX2; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5577) + return OPCODE_ADDX8; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5578) + return OPCODE_MIN; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5579) + return OPCODE_MOVLTZ; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5580) + return OPCODE_SALTU; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5581) + return OPCODE_SUBX4; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5582) + return OPCODE_SEXT; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2450) + return OPCODE_AE_L16M_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2451) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2452) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2453) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2454) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2455) + return OPCODE_AE_L16_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2456) + return OPCODE_AE_L32M_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2457) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2458) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2459) + return OPCODE_AE_L32_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2460) + return OPCODE_AE_L32_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2461) + return OPCODE_AE_L64_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2462) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2463) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2482) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2483) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2484) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2485) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2486) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2487) + return OPCODE_AE_L16_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2488) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2489) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2490) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2491) + return OPCODE_AE_L32_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2492) + return OPCODE_AE_L64_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2493) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2494) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2495) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2514) + return OPCODE_AE_L16M_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2515) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2516) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2517) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2518) + return OPCODE_AE_L16_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2519) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2520) + return OPCODE_AE_L32M_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2521) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2522) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2523) + return OPCODE_AE_L32_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2524) + return OPCODE_AE_L64_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2525) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2526) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2527) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2546) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2547) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2548) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2549) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2550) + return OPCODE_AE_L16_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2551) + return OPCODE_AE_L16_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2552) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2553) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2554) + return OPCODE_AE_L32_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2555) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2556) + return OPCODE_AE_L64_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2557) + return OPCODE_AE_L64_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2558) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2559) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2688) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2689) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2690) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2691) + return OPCODE_AE_L8_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2692) + return OPCODE_SLLI; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2696 && + Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2697 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2720) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2721) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2722) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2723) + return OPCODE_AE_L8_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2724) + return OPCODE_SRAI; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2728 && + Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2729 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2752) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2753) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2754) + return OPCODE_AE_L8_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2755) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2760 && + Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2784) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2785) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2786) + return OPCODE_AE_L8_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2787) + return OPCODE_AE_L8_XP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 48) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 49) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 50) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 51) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 52) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 53) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 54) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 55) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 56) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 57) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 58) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 59) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 60) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 61) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 62) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 63) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 64) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 65) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 66) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 67) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 68) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 69) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 70) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 71) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 72) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 73) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 74) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 75) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_15_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 5) + return OPCODE_L16UI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 4) + return OPCODE_L16SI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 6) + return OPCODE_L32I; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 7) + return OPCODE_L8UI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 8) + return OPCODE_MOVI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 7) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 10) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 6) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 6) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 7) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 8) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 9) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 10) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 11) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 14) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 12) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 13) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 9) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 10) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 14) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 12) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 13) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 320) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 6) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 7) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae8_slot1_29_22_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae8_slot1_29_23_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae8_slot1_29_5_Slot_ae8_slot1_get (insn) == 715056 && + Field_fld_ae8_slot1_4_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_NOP; + if (Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get (insn) == 89378 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SSA8B; + if (Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get (insn) == 89379 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SSA8L; + if (Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get (insn) == 89380 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SSL; + if (Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get (insn) == 89381 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SSR; + if (Field_fld_ae8_slot1_29_9_Slot_ae8_slot1_get (insn) == 44688 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae9_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (insn) == 40364 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_ALL4; + if (Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (insn) == 40364 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_ANY4; + if (Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (insn) == 40365 && + Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_get (insn) == 18) + return OPCODE_SSAI; + if (Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (insn) == 40365 && + Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_ALL8; + if (Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (insn) == 40365 && + Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_ANY8; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10064) + return OPCODE_ADD; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10065) + return OPCODE_ADDX2; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10066) + return OPCODE_ADDX4; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10067) + return OPCODE_ADDX8; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10068) + return OPCODE_AND; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10069) + return OPCODE_MAX; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10070) + return OPCODE_MAXU; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10071) + return OPCODE_MIN; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10072) + return OPCODE_MINU; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10073) + return OPCODE_MOVEQZ; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10074) + return OPCODE_MOVGEZ; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10075) + return OPCODE_MOVLTZ; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10076) + return OPCODE_MOVNEZ; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10077) + return OPCODE_OR; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10078) + return OPCODE_SALT; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10079) + return OPCODE_SALTU; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10080) + return OPCODE_SRC; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10081) + return OPCODE_SUB; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10082) + return OPCODE_SUBX2; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10083) + return OPCODE_SUBX4; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10084) + return OPCODE_SUBX8; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10085) + return OPCODE_XOR; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10086) + return OPCODE_MOVF; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10087) + return OPCODE_MOVT; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10088) + return OPCODE_CLAMPS; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10089) + return OPCODE_SEXT; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10090) + return OPCODE_SRLI; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10091 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_SRA; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10091 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_SRL; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10112 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10694 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_ABS; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10695 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4864) + return OPCODE_AE_L16M_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4865) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4866) + return OPCODE_AE_L16M_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4867) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4868) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4869) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4870) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4871) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4872) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4873) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4874) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4875) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4876) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4877) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4878) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4879) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4880) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4881) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4882) + return OPCODE_AE_L16_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4883) + return OPCODE_AE_L16_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4884) + return OPCODE_AE_L16_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4885) + return OPCODE_AE_L16_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4886) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4887) + return OPCODE_AE_L16_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4888) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4889) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4890) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4891) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4892) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4893) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4894) + return OPCODE_AE_L32M_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4895) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4896) + return OPCODE_AE_L32M_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4897) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4898) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4899) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4900) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4901) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4902) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4903) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4904) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4905) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4906) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4907) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4908) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4909) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4910) + return OPCODE_AE_L32_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4911) + return OPCODE_AE_L32_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4912) + return OPCODE_AE_L32_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4913) + return OPCODE_AE_L32_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4914) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4915) + return OPCODE_AE_L32_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4916) + return OPCODE_AE_L64_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4917) + return OPCODE_AE_L64_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4918) + return OPCODE_AE_L64_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4919) + return OPCODE_AE_L64_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4920) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4921) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4922) + return OPCODE_AE_L64_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4923) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4924) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4925) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4926) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4927) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4928) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4929) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4930) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4931) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4932) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4933) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4934) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4935) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4936) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4937) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4938) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4939) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4940) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4941) + return OPCODE_AE_L8_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4942) + return OPCODE_AE_L8_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4943) + return OPCODE_AE_L8_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4944) + return OPCODE_AE_L8_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4945) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4946) + return OPCODE_AE_L8_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4947) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4948) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4949) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4950) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4951) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4952) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4953) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4954) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4955) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4956) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4957) + return OPCODE_AE_S16X2M_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4958) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4959) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4960) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4961) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4962) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4963) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4964) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4965) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4966) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4967) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4968) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4969) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4970) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4971) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4972) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4973) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4974) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4975) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4976) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4977) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4978) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4979) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4980) + return OPCODE_AE_S32M_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4981) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4982) + return OPCODE_AE_S32M_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4983) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4984) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4985) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4986) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4987) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4988) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4989) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4990) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4991) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4992) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4993) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4994) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4995) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4996) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4997) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4998) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4999) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5000) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5001) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5002) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5003) + return OPCODE_AE_S32_H_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5004) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5005) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5006) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5007) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5008) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5009) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5010) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5011) + return OPCODE_AE_S64_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5012) + return OPCODE_AE_S64_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5013) + return OPCODE_AE_S64_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5014) + return OPCODE_AE_S64_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5015) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5016) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5017) + return OPCODE_AE_S64_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5018) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5019) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5020) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5021) + return OPCODE_AE_S8X8_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5022) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5023) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5024) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5025) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5026) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5027) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5028) + return OPCODE_AE_S8_0_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5029) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5030) + return OPCODE_SLLI; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5031) + return OPCODE_SRAI; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5046 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5046 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5047 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5047 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5048 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5049 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5050 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5051 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5052 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5053 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5054 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5055 && + Field_fld_ae9_slot0_7_6_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5055 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5055 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5055 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5055 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5250 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5251 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5282 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5283 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5314 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5315 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5346 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 566) + return OPCODE_ADDI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 567) + return OPCODE_ADDMI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 568) + return OPCODE_L16SI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 569) + return OPCODE_L16UI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 570) + return OPCODE_L32I; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 571) + return OPCODE_L8UI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 572) + return OPCODE_S16I; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 573) + return OPCODE_S32I; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 574) + return OPCODE_S8I; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 575) + return OPCODE_MOVI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 632 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 632 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 632 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae9_slot0_27_17_Slot_ae9_slot0_get (insn) == 282) + return OPCODE_EXTUI; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 74) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 75) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 76) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 77) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 78) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 79) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 80) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 81) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 82) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 83) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 84) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 85) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 86) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 87) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 88) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 89) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 90) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 91) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 92) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 93) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 94) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 95) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 96) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 97) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 98) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 99) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 100) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 101) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 102) + return OPCODE_AE_S16X4X2RNG_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 103) + return OPCODE_AE_S16X4X2RNG_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 104) + return OPCODE_AE_S16X4X2RNG_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 105) + return OPCODE_AE_S16X4X2RNG_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 106) + return OPCODE_AE_S16X4X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 107) + return OPCODE_AE_S16X4X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 108) + return OPCODE_AE_S16X4X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 109) + return OPCODE_AE_S16X4X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 110) + return OPCODE_AE_S16X4X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 111) + return OPCODE_AE_S16X4X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 112) + return OPCODE_AE_S16X4X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 113) + return OPCODE_AE_S32X2X2RNG_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 114) + return OPCODE_AE_S32X2X2RNG_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 115) + return OPCODE_AE_S32X2X2RNG_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 116) + return OPCODE_AE_S32X2X2RNG_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 117) + return OPCODE_AE_S32X2X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 118) + return OPCODE_AE_S32X2X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 119) + return OPCODE_AE_S32X2X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 120) + return OPCODE_AE_S32X2X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 121) + return OPCODE_AE_S32X2X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 122) + return OPCODE_AE_S32X2X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 123) + return OPCODE_AE_S32X2X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 124) + return OPCODE_AE_S64X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 125) + return OPCODE_AE_S64X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 126) + return OPCODE_AE_S64X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 127) + return OPCODE_AE_S64X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 128) + return OPCODE_AE_S64X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 129) + return OPCODE_AE_S64X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 130) + return OPCODE_AE_S64X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 131) + return OPCODE_AE_S8X8X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 132) + return OPCODE_AE_S8X8X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 133) + return OPCODE_AE_S8X8X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 134) + return OPCODE_AE_S8X8X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 135) + return OPCODE_AE_S8X8X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 136) + return OPCODE_AE_S8X8X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 137) + return OPCODE_AE_S8X8X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 138) + return OPCODE_J; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 139) + return OPCODE_CALL0; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 148 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_get (insn) == 15) + return OPCODE_AE_LE32; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 148 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_get (insn) == 7) + return OPCODE_AE_EQ32; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 148 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_LT64; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 148 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_get (insn) == 5) + return OPCODE_AE_LE64; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 148 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_AE_EQ64; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_get (insn) == 23) + return OPCODE_AE_MOV; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_get (insn) == 7) + return OPCODE_AE_LT16; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_get (insn) == 30) + return OPCODE_AE_LE16; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_get (insn) == 14) + return OPCODE_AE_EQ16; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_LT32; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 183) + return OPCODE_CVTSF16_L; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 181) + return OPCODE_CVTSF16_H; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 179) + return OPCODE_CVTF16S_L; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 177) + return OPCODE_CVTF16S_H; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 8 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_OLE_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 9 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_OLT_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 8 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_OEQ_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 11 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_UN_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 10 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_ULE_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 10 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_ULT_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 9 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_UEQ_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 185) + return OPCODE_FICEIL_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 187) + return OPCODE_FIFLOOR_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 189) + return OPCODE_FIRINT_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 191) + return OPCODE_FIROUND_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_get (insn) == 87) + return OPCODE_RMINNUM_H; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_get (insn) == 55) + return OPCODE_RMAXNUM_H; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 160 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 8) + return OPCODE_FITRUNC_S; + if (Field_fld_ae9_slot0_27_19_Slot_ae9_slot0_get (insn) == 36) + return OPCODE_AE_SEL16I; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 12) + return OPCODE_AE_LAV16X4X2_XP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 13) + return OPCODE_AE_LAV8X8X2_XP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 14) + return OPCODE_AE_SAV16X4X2_XP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 15) + return OPCODE_AE_SAV8X8X2_XP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 16) + return OPCODE_L32R; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 17) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 11) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 7) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 10) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 15) + return OPCODE_AE_SA16X4X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 12) + return OPCODE_AE_SA16X4X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 13) + return OPCODE_AE_SA16X4X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 14) + return OPCODE_AE_SA16X4X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 7) + return OPCODE_AE_SA8X8X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_AE_SA8X8X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 5) + return OPCODE_AE_SA8X8X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_SA8X8X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 40 && + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get (insn) == 2 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 40 && + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get (insn) == 3 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 579) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 580) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 581) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 576) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 577) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 578) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 582) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 583) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 584) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_SALIGN128_I; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 585) + return OPCODE_AE_SA128POS_FP; + if (Field_fld_ae9_slot0_27_22_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_TRUNC_S; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get (insn) == 1 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_UTRUNC_S; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_TRUNC_SX2; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_UTRUNC_SX2; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_FLOAT_SX2; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_UFLOAT_SX2; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 6 && + Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_FLOAT_S; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 6 && + Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_UFLOAT_S; + if (Field_fld_ae9_slot0_27_3_Slot_ae9_slot0_get (insn) == 5178144 && + Field_fld_ae9_slot0_2_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_NOP; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161808 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_CALLX0; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161810 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_JX; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161811 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_RET; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161813 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_SSA8B; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161814 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_SSA8L; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161815 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_SSL; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161816 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_SSR; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae9_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5392) + return OPCODE_MAXU; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5393) + return OPCODE_MIN; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5394) + return OPCODE_SALT; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5395) + return OPCODE_SALTU; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5396) + return OPCODE_CLAMPS; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5397) + return OPCODE_SEXT; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5398 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 10) + return OPCODE_SLL; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5454) + return OPCODE_ADD; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5455) + return OPCODE_ADDX2; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5456) + return OPCODE_MINU; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5457) + return OPCODE_MOVEQZ; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5458) + return OPCODE_SRC; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5459) + return OPCODE_SUB; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5460) + return OPCODE_SRLI; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5461 && + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5461 && + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5461 && + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5461 && + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5518) + return OPCODE_ADDX4; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5519) + return OPCODE_ADDX8; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5520) + return OPCODE_MOVGEZ; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5521) + return OPCODE_MOVLTZ; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5522) + return OPCODE_SUBX2; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5523) + return OPCODE_SUBX4; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5582) + return OPCODE_AND; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5583) + return OPCODE_MAX; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5584) + return OPCODE_MOVNEZ; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5585) + return OPCODE_OR; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5586) + return OPCODE_SUBX8; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5587) + return OPCODE_XOR; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2456) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2457) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2458) + return OPCODE_AE_L32M_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2459) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2460) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2461) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2462) + return OPCODE_AE_L32_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2463) + return OPCODE_AE_L64_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2480) + return OPCODE_AE_L16M_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2481) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2482) + return OPCODE_AE_L16M_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2483) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2484) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2485) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2486) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2487) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2488) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2489) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2490) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2491) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2492) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2493) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2494) + return OPCODE_AE_L32_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2495) + return OPCODE_AE_L64_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2512) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2513) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2514) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2515) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2516) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2517) + return OPCODE_AE_L16_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2518) + return OPCODE_AE_L16_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2519) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2520) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2521) + return OPCODE_AE_L32M_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2522) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2523) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2524) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2525) + return OPCODE_AE_L32_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2526) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2527) + return OPCODE_AE_L64_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2544) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2545) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2546) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2547) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2548) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2549) + return OPCODE_AE_L16_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2550) + return OPCODE_AE_L16_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2551) + return OPCODE_AE_L16_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2552) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2553) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2554) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2555) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2556) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2557) + return OPCODE_AE_L32_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2558) + return OPCODE_AE_L32_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2559) + return OPCODE_AE_L64_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2688) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2689) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2690) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2691) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2692) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2693) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2694) + return OPCODE_AE_L8_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2695) + return OPCODE_SRAI; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2699 && + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2720) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2721) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2722) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2723) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2724) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2725) + return OPCODE_AE_L8_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2726) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2731 && + Field_fld_ae9_slot1_3_2_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2731 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 4) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2731 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 5) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2731 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 6) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2731 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 7) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2752) + return OPCODE_AE_L64_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2753) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2754) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2755) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2756) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2757) + return OPCODE_AE_L8_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2758) + return OPCODE_AE_L8_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2762 && + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2762 && + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2784) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2785) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2786) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2787) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2788) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2789) + return OPCODE_AE_L8_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2790) + return OPCODE_SLLI; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2794 && + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2794 && + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 306) + return OPCODE_MOVI; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 308) + return OPCODE_ADDI; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 309) + return OPCODE_ADDMI; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 312) + return OPCODE_L16SI; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 313) + return OPCODE_L32I; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 316) + return OPCODE_L16UI; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 317) + return OPCODE_L8UI; + if (Field_fld_ae9_slot1_26_17_Slot_ae9_slot1_get (insn) == 152) + return OPCODE_EXTUI; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 48) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 49) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 50) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 51) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 52) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 53) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 54) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 55) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 56) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 57) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 58) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 59) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 60) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 61) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 62) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 63) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 64) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 65) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 66) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 67) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 68) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 69) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 70) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 71) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 72) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 73) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 74) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 75) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae9_slot1_26_2_Slot_ae9_slot1_get (insn) == 5659202 && + Field_fld_ae9_slot1_1_0_Slot_ae9_slot1_get (insn) == 3) + return OPCODE_NOP; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 7) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 10) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 6) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 355 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 356 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 357 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 352 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 353 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 354 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 358 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 359 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 360 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 384) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_get (insn) == 11 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 8) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_get (insn) == 11 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 9) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae9_slot1_26_22_Slot_ae9_slot1_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae9_slot1_26_23_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get (insn) == 86377 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_SSL; + if (Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get (insn) == 87401 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_SSR; + if (Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get (insn) == 87402 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_SSA8B; + if (Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get (insn) == 87403 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_SSA8L; + if (Field_fld_ae9_slot1_26_9_Slot_ae9_slot1_get (insn) == 43189 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116372 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116373 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116380 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116381 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ALL4; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116381 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ANY4; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116381 && + Field_fld_ae_slot0_8_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_ALL8; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116381 && + Field_fld_ae_slot0_8_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_ANY8; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28835 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28835 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28835 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28835 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LB; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28837 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28839 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 48) + return OPCODE_RUR_FCR; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28839 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 112) + return OPCODE_RUR_FSR; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28839 && + Field_fld_ae_slot0_5_0_Slot_ae_slot0_get (insn) == 16) + return OPCODE_AE_MOVAB4; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28839 && + Field_fld_ae_slot0_4_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVAB2; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 29091 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_SRL; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 29091 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAB; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 29091 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVBA; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 29091 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LBI; + if (Field_fld_ae_slot0_28_14_Slot_ae_slot0_get (insn) == 10904 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_SSAI; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3612 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 56) + return OPCODE_SLL; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1080) + return OPCODE_CALLX0; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1208) + return OPCODE_JX; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1272) + return OPCODE_RET; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1400) + return OPCODE_SSA8B; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1464) + return OPCODE_SSA8L; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1528) + return OPCODE_SSL; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1592) + return OPCODE_SSR; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1656) + return OPCODE_AE_MOVASAR; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4871 && + Field_fld_ae_slot0_12_10_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4871 && + Field_fld_ae_slot0_12_10_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4871 && + Field_fld_ae_slot0_12_10_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4900 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_SUBX8; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4900 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AND; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4900 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ANDBC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4900 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_CLAMPS; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4900 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ADDX4; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SRLI; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ORBC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_MOVF; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MAXU; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_DB; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4908 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_XOR; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4908 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ORB; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4908 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MAX; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4908 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SEXT; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ADDX8; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_ANDB; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_XORB; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_MOVT; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MIN; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVSARA7X2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4910 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_MOVGEZ; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4910 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_MINU; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4911 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_MOVEQZ; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4911 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_MOVLTZ; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4942 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_MOVNEZ; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4942 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SRC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4943 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADD; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4943 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SUB; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4943 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_OR; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4974 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SUBX2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4974 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_SALT; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4975 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADDX2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4975 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SUBX4; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4975 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_SALTU; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_DPFM_B; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_DPFM_BF; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_DPFR_B; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_DPFR_BF; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA24X2POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA24X2NEG_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2NEG_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_DPFW_B; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_DPFW_BF; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA24POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA24NEG_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA16X4POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4NEG_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA8X8POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA8X8NEG_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA8X8NEG_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_DBI; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5380 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5388 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5412 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5420 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5444 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5476 && + Field_fld_ae_slot0_12_0_Slot_ae_slot0_get (insn) == 69) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5476 && + Field_fld_ae_slot0_12_6_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_MOVALIGN; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 1802 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 1806 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 1818 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 1822 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2106 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2110 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2362 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2366 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16M_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S8_0_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32M_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2450 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2450 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2450 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2450 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SRAI; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L64_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16M_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2471 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2471 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2471 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2471 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S64_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32M_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32M_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32M_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2496 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2618 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2622 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2712 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2712 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2712 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2712 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2716 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2716 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2716 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2716 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L8_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32_H_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2874 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2878 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L64_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L64_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S8X8_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S64_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S64_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3130 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3134 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3386 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3390 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3642 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3646 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3898 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3902 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L64_X; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_NEG32; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ABS32; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_NEG24S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ABS24S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_NEG32S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_ABS32S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_NEG16S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_ABS16S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ABS16; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_NEG64; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_ABS64; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_NEG64S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_ABS64S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_DIV64D32_H; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_ABS8; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ABS8S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_NEG8S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 192 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_EQ64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 193 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_CVTF16S_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 193 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_CVTF16S_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 194 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LE64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 195 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_CVTSF16_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 195 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_CVTSF16_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 196 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LT64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 197 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FICEIL_S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 197 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FIFLOOR_S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 199 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FIRINT_S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 199 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FIROUND_S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_MAX32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_MAX16; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADD64S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_ADD8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADD8S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_ROUND24X2F48SASYM; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_MIN32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MIN16; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MAX64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MIN64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MAX8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_MIN8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_MOVNEG32S_T; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 228 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0) + return OPCODE_J; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_ROUND32X2F64SASYM; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ROUND24X2F48SSYM; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SUB32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SUB16; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SUB24S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SUB32S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_SUB16S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SUB64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 230 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0) + return OPCODE_CALL0; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 230 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0) + return OPCODE_L32I; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 230 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1) + return OPCODE_L8UI; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 230 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0) + return OPCODE_S16I; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 230 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1) + return OPCODE_S32I; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SUB64S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SUB8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SUB8S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LE8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LT8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_EQ8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_RNG32X4; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FITRUNC_S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 273 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADD16; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 273 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADD16S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 275 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADD32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 275 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADD24S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 277 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADD32S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 277 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 279 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 279 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADD64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 280 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_9_Slot_ae_slot0_get (insn) == 9 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 1) + return OPCODE_TRUNC16_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 280 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_9_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 1) + return OPCODE_UTRUNC16_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_SLLI; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCA32Q48; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCA16P24S_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCA16P24S_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSA64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSAZ16_0; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_RFR; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 310 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 310 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_LOOPGTZ; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 310 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 8) + return OPCODE_LOOPNEZ; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32F24S_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32F24S_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 337 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 608 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 339 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0) + return OPCODE_S8I; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 370 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ADDI; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 370 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADDMI; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 374 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1) + return OPCODE_L16UI; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 374 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0) + return OPCODE_L16SI; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0) + return OPCODE_L32R; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_10_Slot_ae_slot0_get (insn) == 172 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_SA32X2_IC2; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IC2; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_IC2; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SA8X8_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_SA32X2F24_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_SA32X2F24_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_SA24_L_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_SA24_L_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SA24X2_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SA24X2_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 32) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 24) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_12_Slot_ae_slot0_get (insn) == 161 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 16) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_10_Slot_ae_slot0_get (insn) == 164 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SALIGN128_I; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 40) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 48) + return OPCODE_WFR; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 77 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVDA32X2; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 77 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 77 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 84 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 576 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 84 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 608 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SA128POS_FP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 85 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 608 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LT16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LE16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_EQ16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LT32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LE32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_EQ32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OLE_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OLT_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OEQ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UN_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ULE_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ULT_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UEQ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OEQ_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OLE_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OLT_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UEQ_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ULE_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ULT_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UN_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SEL16I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 52 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 52 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVT64; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVF64; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_13_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_AND; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_13_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_NAND; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_13_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_OR; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_13_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_XOR; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 53 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_BMAX32X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_BMIN32X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVADEXT_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVADEXT_L; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADDC32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADDC32U; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVT_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVF_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S32X2X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S32X2X2RNG_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2X2RNG_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S32X2X2RNG_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2X2RNG_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S16X4X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X4X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X4X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S16X4X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X4X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X4X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S16X4X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X4X2RNG_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S16X4X2RNG_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X4X2RNG_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S16X4X2RNG_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 32 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 33 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 33 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S32X2X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8X8X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S8X8X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X4RA32S_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8X2_IC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4X2_IC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2X2_IC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8X2_IC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4X2_IC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2X2_IC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8X2_IC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4X2_IC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2X2_IC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_BMAX16X4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_BMIN16X4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SUBC32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SUBC32U; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 36 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 37 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 37 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 0) + return OPCODE_MOVI; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S32X2X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S8X8X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8X8X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S24RA64S_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOV; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCQ32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_PKSR32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_PKSR16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_MOVEQZ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 12) + return OPCODE_MOVNEZ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_MOVGEZ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 8) + return OPCODE_MOVLTZ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 40 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 41 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 41 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16) + return OPCODE_EXTUI; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S32X2X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVBA1X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_19_8_Slot_ae_slot0_get (insn) == 1568 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVBA4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_18_8_Slot_ae_slot0_get (insn) == 544 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVBA2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 576 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVBD1X4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 512 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVBD1X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 44 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 45 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDW16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 45 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDW32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 46 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 46 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S64X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 48 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 49 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDW8; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 49 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDW8U; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 50 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S64X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 50 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 52 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 53 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SUBW16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 53 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SUBW32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 54 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 54 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S64X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 57 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SUBW8; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 57 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SUBW8U; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 58 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S8X8X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 58 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 60 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 61 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SAV8X8X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 61 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SAV16X4X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 62 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8X8X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 62 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S8X8X2_X; + if (Field_fld_ae_slot0_28_24_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVT8X16_H; + if (Field_fld_ae_slot0_28_24_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_MOVT8X16_L; + if (Field_fld_ae_slot0_28_24_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae_slot0_28_26_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVT16X8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 392 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 384 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 392 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 387 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 395 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 386 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 394 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 386 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 387 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 395 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 384 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 392 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 384 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LA24_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 384 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 392 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA24_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_LA24X2_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_LA24X2_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_TRUNCA32F64S_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRA64_32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 36 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 36 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_SRLI24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 36 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SRAI24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_SRLS24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SRAS24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAI16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAI16R; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 44 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_SRLI32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SRAI32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 44 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SRAI32R; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_SRLS32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SRAS32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAA32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLA32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI16S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAA16S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA16S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA16RS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI24S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 46 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAA32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA32RS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLASQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_SRLSQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SRASQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAAQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLAQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAAQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SLAI64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLI64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAI64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_SRLS64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SRAS64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAA64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLA64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAA64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLAISQ56S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLASSQ56S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAASQ56S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SLAI64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAA64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 386 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 394 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRAI8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRAI8R; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLI8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAI8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAI8S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAA8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLA8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAA8S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAA8RS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAA8S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLI16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAA16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRLA16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAI16SYM; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA16SYMS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 46 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SRAI32SYM; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA32SYMS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAV16RS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAV32RS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTI32X4F8_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTI32X4F8_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTI32X4F8S_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTI32X4F8S_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32X4F8_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_CVTA32X4F8_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTA32X4F8S_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTA32X4F8S_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTI32X4F8U_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTI32X4F8U_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTI32X4F8US_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTI32X4F8US_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTA32X4F8U_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTA32X4F8U_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32X4F8US_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_CVTA32X4F8US_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTI32X4F16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTI32X4F16S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTA32X4F16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTA32X4F16S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTI32X4F16U; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTI32X4F16US; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32X4F16U; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_CVTA32X4F16US; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTI16X4X2F8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTI16X4X2F8S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTA16X4X2F8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTA16X4X2F8S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTI16X4X2F8U; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_CVTI16X4X2F8US; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA16X4X2F8U; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_CVTA16X4X2F8US; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_MOVDEXT; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_NSA16X4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSAZ32X4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSA32X4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_TRUNCI16X4F32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCI16X4F64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_TRUNCA16X4F32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCA16X4F64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LAV8X8X2_XP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LAV16X4X2_XP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_TRUNC_S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_UTRUNC_S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_TRUNC_SX2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_UTRUNC_SX2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_17_Slot_ae_slot0_get (insn) == 96 && + Field_fld_ae_slot0_9_4_Slot_ae_slot0_get (insn) == 16) + return OPCODE_FLOAT_S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_17_Slot_ae_slot0_get (insn) == 96 && + Field_fld_ae_slot0_9_4_Slot_ae_slot0_get (insn) == 20) + return OPCODE_UFLOAT_S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FLOAT_SX2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_UFLOAT_SX2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_FICEIL_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_FIFLOOR_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_FIRINT_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_FIROUND_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_FITRUNC_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_17_Slot_ae_slot0_get (insn) == 96 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_3_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FLOAT16_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_17_Slot_ae_slot0_get (insn) == 96 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_3_Slot_ae_slot0_get (insn) == 8) + return OPCODE_UFLOAT16_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FLOAT16_HX4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UFLOAT16_HX4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_12_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_TRUNC16_HX4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UTRUNC16_HX4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_RMINNUM_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_RMAXNUM_H; + if (Field_fld_ae_slot0_28_4_Slot_ae_slot0_get (insn) == 11214853 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_NOP; + if (Field_fld_ae_slot0_28_8_Slot_ae_slot0_get (insn) == 697920 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_WUR_FCR; + if (Field_fld_ae_slot0_28_8_Slot_ae_slot0_get (insn) == 697952 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_WUR_FSR; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot1_25_1_Slot_ae_slot1_get (insn) == 10858630 && + Field_fld_ae_slot1_0_0_Slot_ae_slot1_get (insn) == 0) + return OPCODE_NOP; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5390) + return OPCODE_MAXU; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5391) + return OPCODE_MIN; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5392) + return OPCODE_SALT; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5393) + return OPCODE_SALTU; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5394) + return OPCODE_CLAMPS; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5395) + return OPCODE_SEXT; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5409 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5409 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5409 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5409 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SRL; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5409 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_LB; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5452) + return OPCODE_ADD; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5453) + return OPCODE_ADDX2; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5454) + return OPCODE_MINU; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5455) + return OPCODE_MOVEQZ; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5456) + return OPCODE_SRC; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5457) + return OPCODE_SUB; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5458) + return OPCODE_SRLI; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5459) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5516) + return OPCODE_ADDX4; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5517) + return OPCODE_ADDX8; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5518) + return OPCODE_MOVGEZ; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5519) + return OPCODE_MOVLTZ; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5520) + return OPCODE_SUBX2; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5521) + return OPCODE_SUBX4; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5526 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SLL; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5527 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5580) + return OPCODE_AND; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5581) + return OPCODE_MAX; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5582) + return OPCODE_MOVNEZ; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5583) + return OPCODE_OR; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5584) + return OPCODE_SUBX8; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5585) + return OPCODE_XOR; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5590 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_LBI; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2456) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2457) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2458) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2459) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2460) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2461) + return OPCODE_AE_L32_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2462) + return OPCODE_AE_L32_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2463) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2480) + return OPCODE_AE_L16M_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2481) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2482) + return OPCODE_AE_L16M_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2483) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2484) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2485) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2486) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2487) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2488) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2489) + return OPCODE_AE_L32M_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2490) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2491) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2492) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2493) + return OPCODE_AE_L32_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2494) + return OPCODE_AE_L64_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2495) + return OPCODE_AE_L64_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2512) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2513) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2514) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2515) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2516) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2517) + return OPCODE_AE_L16_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2518) + return OPCODE_AE_L16_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2519) + return OPCODE_AE_L16_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2520) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2521) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2522) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2523) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2524) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2525) + return OPCODE_AE_L32_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2526) + return OPCODE_AE_L64_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2527) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2544) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2545) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2546) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2547) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2548) + return OPCODE_AE_L16_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2549) + return OPCODE_AE_L16_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2550) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2551) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2552) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2553) + return OPCODE_AE_L32M_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2554) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2555) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2556) + return OPCODE_AE_L32_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2557) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2558) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2559) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2688) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2689) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2690) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2691) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2692) + return OPCODE_AE_L8_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2693) + return OPCODE_AE_L8_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2694) + return OPCODE_SRAI; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2698 && + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2699 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2699 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2699 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2720) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2721) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2722) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2723) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2724) + return OPCODE_AE_L8_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2725) + return OPCODE_AE_MOVDA32X2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2730 && + Field_fld_ae_slot1_3_2_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2730 && + Field_fld_ae_slot1_3_2_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2731 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2731 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2731 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2752) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2753) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2754) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2755) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2756) + return OPCODE_AE_L8_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2757) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2761 && + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2761 && + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2763 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2763 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2784) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2785) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2786) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2787) + return OPCODE_AE_L8_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2788) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2789) + return OPCODE_SLLI; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2793 && + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2793 && + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2795 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2795 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 306) + return OPCODE_MOVI; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 308) + return OPCODE_ADDI; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 309) + return OPCODE_ADDMI; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 312) + return OPCODE_L16SI; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 313) + return OPCODE_L32I; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 316) + return OPCODE_L16UI; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 317) + return OPCODE_L8UI; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 152) + return OPCODE_EXTUI; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 160 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 13) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 160 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 14) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 160 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 160 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 15) + return OPCODE_AE_L64_I; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 162 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 13) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 162 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_L64_IP; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 169 && + Field_fld_ae_slot1_12_8_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 48) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 49) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 50) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 51) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 52) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 53) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 54) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 55) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 56) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 57) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 58) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 59) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 60) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 61) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 62) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 63) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 64) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 65) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 66) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 67) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 68) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 69) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 70) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 71) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 72) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 73) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 74) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 75) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 737 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 641 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 673 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 705 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 545 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 577 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 609 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 769 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 801 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 833 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_17_Slot_ae_slot1_get (insn) == 1 && + Field_fld_ae_slot1_12_8_Slot_ae_slot1_get (insn) == 0 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 513 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA128_PP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 7) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 10) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 13) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 8) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 9) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 11 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 11 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 10) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 11) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 14) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 15) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae_slot1_25_22_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae_slot1_25_23_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 82785 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_SSL; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 83809 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_SSR; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 86576) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 86577) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 86578) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 86579) + return OPCODE_AE_MOVSARA7X2; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 89458 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SSA8B; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 89459 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SSA8L; + if (Field_fld_ae_slot1_25_9_Slot_ae_slot1_get (insn) == 44728 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_get (insn) == 2560) + return OPCODE_OR; + if (Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_get (insn) == 2561) + return OPCODE_XOR; + if (Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_get (insn) == 2562) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 288 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 289 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16_I; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 290 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 291 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16_X; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 292 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16_XC; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 293 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16_XP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 294 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 295 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 296 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 297 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32_I; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 298 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 299 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32_X; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 300 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32_XC; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 301 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32_XP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 302 && + Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_get (insn) == 7) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 302 && + Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_get (insn) == 6) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 303 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 12) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 303 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 13) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 303 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 14) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 303 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 15) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 321 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 321 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 321 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 321 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 321 && + Field_fld_ae6_slot1_9_5_Slot_ae6_slot1_get (insn) == 8) + return OPCODE_AE_MOV; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 2) + return OPCODE_AE_TRUNCI16X4F32S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 4 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_CVTA16X4X2F8; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 4 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_CVTA16X4X2F8S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 5 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_CVTI16X4X2F8; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 5 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_CVTA16X4X2F8U; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 6 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_CVTI16X4X2F8S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 6 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_CVTI16X4X2F8U; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 7 && + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_TRUNCA16X4F32S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 7 && + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_TRUNCA16X4F64S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 8 && + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 8 && + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_TRUNCI32X2F64S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 9 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 9 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 9 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 2) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae6_slot1_27_21_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_TRUNCI16X4F64S; + if (Field_fld_ae6_slot1_27_3_Slot_ae6_slot1_get (insn) == 1315112 && + Field_fld_ae6_slot1_2_0_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_NOP; + if (Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_get (insn) == 164357) + return OPCODE_AE_LA128_PP; + if (Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_get (insn) == 164373) + return OPCODE_AE_LA64_PP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae10_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae10_slot2_34_10_Slot_ae10_slot2_get (insn) == 28442624 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 101) + return OPCODE_NOP; + if (Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get (insn) == 1968640) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get (insn) == 1968641) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get (insn) == 1968642 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 17) + return OPCODE_CONST_S; + if (Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get (insn) == 1968642 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 16) + return OPCODE_CONST_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 15) + return OPCODE_AE_MOV; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 8) + return OPCODE_NEXP01_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 4) + return OPCODE_MKSADJ_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_DIV0_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 11) + return OPCODE_SQRT0_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 9) + return OPCODE_RECIP0_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 10) + return OPCODE_RSQRT0_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_ABS_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 7) + return OPCODE_NEG_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_CONJC_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 6) + return OPCODE_MULJC_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 12) + return OPCODE_ABS_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 13) + return OPCODE_CLSFY_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_CONJC_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 5) + return OPCODE_MULJC_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 14) + return OPCODE_NEG_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984322 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_CLSFY_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984322 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24640 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MAX_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24640 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MAXNUM_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24641 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MIN_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24641 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MINNUM_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24704 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_FREXP_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24704 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 25728 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MAX_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 25728 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MAXNUM_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 26752 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_DIVN_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 26752 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MINNUM_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 26752 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MADDN_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 98) + return OPCODE_MKDADJ_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 97) + return OPCODE_ADDEXP_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 96) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MIN_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 100) + return OPCODE_ADDEXP_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 99) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 28800 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MADD_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 29824 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MSUBN_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30752) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30753) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30754) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30755) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30756) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30757) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30758) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30759) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30848 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MSUB_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 31872 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MUL_S; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_ADD_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 161) + return OPCODE_SUB_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 129) + return OPCODE_MUL_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 33) + return OPCODE_MADD_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 97) + return OPCODE_MSUB_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 65) + return OPCODE_MSUBN_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 833) + return OPCODE_MADDQ_S; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 865) + return OPCODE_MSUBQ_S; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 897) + return OPCODE_MULQ_S; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 929) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 993 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_MADDA_S; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 10) + return OPCODE_MADD_SX2X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 11) + return OPCODE_MSUB_SX2X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 12) + return OPCODE_MUL_SX2X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 13) + return OPCODE_ADD_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 14) + return OPCODE_MADD_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 15) + return OPCODE_MSUB_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 16) + return OPCODE_MUL_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 17) + return OPCODE_SUB_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 18) + return OPCODE_ADD_SX2X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 19) + return OPCODE_SUB_SX2X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 5) + return OPCODE_MULQ_H; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_MADDQ_H; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MULCNVH_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MULACNVH_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 4) + return OPCODE_MULCNVL_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MULACNVL_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 21 && + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (insn) == 0 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 34) + return OPCODE_ADD_S; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 21 && + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (insn) == 0 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 66) + return OPCODE_SUB_S; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 21 && + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (insn) == 0 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 21 && + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (insn) == 0 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 21 && + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (insn) == 0 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_get (insn) == 4) + return OPCODE_MULMUX_SX2X2; + if (Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_get (insn) == 12 && + Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_get (insn) == 128 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MULMUX_S; + if (Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_get (insn) == 12 && + Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MULMUXQ_S; + if (Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_MADDMUX_SX2X2; + if (Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_get (insn) == 3 && + Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_get (insn) == 128 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_get (insn) == 3 && + Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_MADDMUXQ_S; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae10_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae10_slot3_34_10_Slot_ae10_slot3_get (insn) == 23102864 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 18) + return OPCODE_NOP; + if (Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get (insn) == 1443864) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get (insn) == 1443865) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get (insn) == 1443928 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 19) + return OPCODE_CONST_S; + if (Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get (insn) == 1443928 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 18) + return OPCODE_CONST_H; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 17) + return OPCODE_AE_MOV; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 4) + return OPCODE_NEXP01_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 3) + return OPCODE_MKSADJ_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_DIV0_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 7) + return OPCODE_SQRT0_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 5) + return OPCODE_RECIP0_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 6) + return OPCODE_RSQRT0_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 8) + return OPCODE_ABS_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 13) + return OPCODE_NEG_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 10) + return OPCODE_CONJC_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 12) + return OPCODE_MULJC_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_CLSFY_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 2) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 14) + return OPCODE_ABS_H; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 15) + return OPCODE_CLSFY_H; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 9) + return OPCODE_CONJC_H; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 11) + return OPCODE_MULJC_H; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 16) + return OPCODE_NEG_H; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 18496 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_DIVN_S; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 19520 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MADDN_S; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 20544 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MADD_S; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 21568 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MSUBN_S; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 22592 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MSUB_S; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 23616 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MUL_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 577) + return OPCODE_MADDQ_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 609) + return OPCODE_MSUBQ_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 641) + return OPCODE_MULQ_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 673) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_4_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_AE_SEL16I; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 27) + return OPCODE_MIN_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 25) + return OPCODE_MAX_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 26) + return OPCODE_MINNUM_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 25) + return OPCODE_MAXNUM_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 9) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 8) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 24) + return OPCODE_FREXP_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 26) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 24) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_BMAXNUM_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get (insn) == 2) + return OPCODE_BMINNUM_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_BMAXNUMABS_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get (insn) == 2) + return OPCODE_BMINNUMABS_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 7) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 3) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 5) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 29) + return OPCODE_MIN_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 28) + return OPCODE_MAX_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 28) + return OPCODE_MINNUM_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 27) + return OPCODE_MAXNUM_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 6) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 2) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 4) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 5) + return OPCODE_ADD_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 6) + return OPCODE_SUB_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 226) + return OPCODE_MKDADJ_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 225) + return OPCODE_ADDEXP_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 224) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 4) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_MADDA_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 228) + return OPCODE_ADDEXP_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 227) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 64) + return OPCODE_ADD_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 98) + return OPCODE_SUB_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 66) + return OPCODE_MUL_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 96) + return OPCODE_MADD_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 97) + return OPCODE_MSUB_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 65) + return OPCODE_MSUBN_H; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 10) + return OPCODE_MADD_SX2X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 11) + return OPCODE_MSUB_SX2X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 12) + return OPCODE_MUL_SX2X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 13) + return OPCODE_MADD_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 14) + return OPCODE_MSUB_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 15) + return OPCODE_MUL_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 5) + return OPCODE_MULQ_H; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_MADDQ_H; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 3) + return OPCODE_MULCNVH_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MULACNVH_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 4) + return OPCODE_MULCNVL_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 2) + return OPCODE_MULACNVL_HX4X2; + if (Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_get (insn) == 4) + return OPCODE_MULMUX_SX2X2; + if (Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_get (insn) == 8 && + Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_get (insn) == 64 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MULMUX_S; + if (Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_get (insn) == 8 && + Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MULMUXQ_S; + if (Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_MADDMUX_SX2X2; + if (Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_get (insn) == 2 && + Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_get (insn) == 64 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_get (insn) == 2 && + Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_MADDMUXQ_S; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae2_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12292 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_ADD_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12420 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_DIVN_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12548 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MADDN_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12676 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MADD_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12684 && + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_PKSR24; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12684 && + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get (insn) == 0 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_PKSR16; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12685 && + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get (insn) == 0 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_PKSR32; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12685 && + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 131) + return OPCODE_AE_RADD8X8_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 227) + return OPCODE_AE_RADDA8X8_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 163) + return OPCODE_AE_RADD8X8_L; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 99) + return OPCODE_AE_RADD16X4; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 195) + return OPCODE_AE_RADDA16X4; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 67) + return OPCODE_MKDADJ_S; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 35) + return OPCODE_ADDEXP_S; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_0_Slot_ae2_slot2_get (insn) == 232448) + return OPCODE_NOP; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 67) + return OPCODE_AE_RMAX8X8; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 131) + return OPCODE_AE_RMIN8X8; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 35) + return OPCODE_AE_RMAX16X4; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 99) + return OPCODE_AE_RMIN16X4; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_RADDA8X8_L; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 195) + return OPCODE_ADDEXP_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 163) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12804 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MSUB_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12932 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MUL_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 13060 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_SUB_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3072) + return OPCODE_AE_MULAFC32RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3074 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3074 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP16S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3074 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAA2D16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3075 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3075 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3075 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MSUBN_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3104) + return OPCODE_AE_MULFC32RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3106 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3106 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3106 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3107 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3107 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3107 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MSUB_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3136) + return OPCODE_MADDA_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3138 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3138 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3138 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP16X16X4S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3139 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3139 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3139 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MUL_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULA32U_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 27) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 26) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 25) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 30) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 23) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 31) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 24) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 22) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 20) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 21) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 19) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 16) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULA32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 17) + return OPCODE_AE_MULAAD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 18) + return OPCODE_AE_MULAAD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULAA2D16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULAA2D16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 28) + return OPCODE_AE_MULAAFD16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 29) + return OPCODE_AE_MULAAFD16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3170 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3170 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3170 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3171 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFC16RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3171 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 18) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULF32RA_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32RA_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 22) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 17) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 29) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 23) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 28) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 21) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 27) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 20) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 24) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 16) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULFP32X2TS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULC32X16_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULC16S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 19) + return OPCODE_AE_MULS32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULFCJ32RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3202 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3202 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3202 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3203 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3203 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULC16JS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 18) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULF32RA_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 22) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 24) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 17) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 29) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 23) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 28) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 21) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 27) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 20) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 16) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULC16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 19) + return OPCODE_AE_MULS32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULASD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULCJ32; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULP16S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULFP16X4RS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3234 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3234 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3234 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3235 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3235 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULC16JS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 24) + return OPCODE_AE_MULSF32RA_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 19) + return OPCODE_AE_MULS32U_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 17) + return OPCODE_AE_MULS16S_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 29) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 23) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 28) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 21) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 27) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 20) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 16) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULC32; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULFC16RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 18) + return OPCODE_AE_MULS32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 22) + return OPCODE_AE_MULSAD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULASD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3266 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC16JS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3266 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3266 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP32X2T; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3267 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3267 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 17) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULF32RA_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 24) + return OPCODE_AE_MULSF32RA_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 21) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 28) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 27) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 20) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 19) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 23) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 29) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 16) + return OPCODE_AE_MULP32X2T; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X2TS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULC32X16_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 18) + return OPCODE_AE_MULS32S_HL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 22) + return OPCODE_AE_MULSAD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULFCJ16RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULC16S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULP16X16X4S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3298 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC16JS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3298 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3298 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3299 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3299 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3330 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3330 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3330 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC16S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3331 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3331 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFCJ16RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3362 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3362 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC16S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3362 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSS2D16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3363 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3363 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFCJ32RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3394 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3394 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3394 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSS2D16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3395 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL16S_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3395 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3395 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSS2D16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3426 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3426 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3426 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC32; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3427 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3427 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3427 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSS2D16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3458 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3458 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3458 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC32X16_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3459 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3459 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3459 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3490 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3490 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC32X16_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3490 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3491 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3491 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32S_HL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3491 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3522 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3522 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULACJ32; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3522 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3523 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3523 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3523 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3554 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3554 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3554 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3555 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3555 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3555 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3586 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32RA_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3586 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3586 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3587 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32U_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3587 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3587 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3618 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32RA_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3618 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3618 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3619 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3619 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3619 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3650 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32RA_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3650 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3650 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3651 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3651 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3651 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3682 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3682 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3682 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3683 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3683 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3683 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3714 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3714 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3714 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3715 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3715 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3715 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X2TS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3746 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3746 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3746 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3747 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3747 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP16S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3747 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3778 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3778 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3778 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3779 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3779 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3779 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3810 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3810 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3810 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3811 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3811 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3811 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP16X16X4S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3842 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3842 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3842 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3843 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3843 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3843 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3874 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3874 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3874 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3875 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3875 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3875 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3906 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3906 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3906 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3907 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3907 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3907 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3938 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3938 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3938 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3939 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3939 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3939 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP32X2T; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3970 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3970 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3970 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3971 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA16S_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3971 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3971 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4002 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4002 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4002 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4003 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4003 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4003 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_DIVN_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4034 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4034 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4034 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4035 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4035 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4035 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_MADDN_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4066 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4066 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4066 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZAA2D16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4067 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4067 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA32S_HL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4067 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_MADD_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 64 && + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_BMAXNUMABS_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 65 && + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_BMAXNUM_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 66 && + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_BMINNUMABS_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 67 && + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_BMINNUM_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 68 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 320) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 68 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 256) + return OPCODE_FREXP_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 68 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 288) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 69 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 320) + return OPCODE_ADD_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 69 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 288) + return OPCODE_MINNUM_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 69 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 256) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 70 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 320) + return OPCODE_SUB_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 70 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 288) + return OPCODE_MIN_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 70 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 256) + return OPCODE_MAXNUM_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 71 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 288) + return OPCODE_AE_SORT16X4; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 71 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 256) + return OPCODE_MAX_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 71 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 320 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_CLSFY_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 71 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 320 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae2_slot2_42_26_Slot_ae2_slot2_get (insn) == 52 && + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_MULMUX_S; + if (Field_fld_ae2_slot2_42_28_Slot_ae2_slot2_get (insn) == 12 && + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_ADD_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_SUB_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_get (insn) == 67745) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 15430 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MOV; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_get (insn) == 67744) + return OPCODE_AE_ABS16S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_DSEL8X8; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 2118 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_NEXP01_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 1094 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_MKSADJ_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 70 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_DIV0_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 5190 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_SQRT0_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 3142 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_RECIP0_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 4166 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_RSQRT0_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 6214 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_ABS_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 11334 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_NEG_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 8262 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_CONJC_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 10310 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_MULJC_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_get (insn) == 32909 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_CONST_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 100) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 68) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 96) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 99) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 97) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 98) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_get (insn) == 141 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 12358 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_ABS_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 13382 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_CLSFY_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 7238 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_CONJC_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_get (insn) == 32908 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_CONST_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 1125) + return OPCODE_MIN_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 101) + return OPCODE_MAX_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 1093) + return OPCODE_MINNUM_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 69) + return OPCODE_MAXNUM_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 9286 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_MULJC_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 14406 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_NEG_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 64) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 67) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 65) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_get (insn) == 140 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 66) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MIN32; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MAX32; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MIN16; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MAX16; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MAX8; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MIN8; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 33) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 32) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_SEL8X8I; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot2_23_0_Slot_ae4_slot2_get (insn) == 5668865) + return OPCODE_NOP; + if (Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get (insn) == 1368) + return OPCODE_AE_PKSR16; + if (Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get (insn) == 1369) + return OPCODE_AE_PKSR24; + if (Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get (insn) == 1370) + return OPCODE_AE_PKSR32; + if (Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get (insn) == 1371) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 164) + return OPCODE_AE_MAX16; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 165) + return OPCODE_AE_MAX32; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 166) + return OPCODE_AE_MAX8; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 167) + return OPCODE_AE_MIN16; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 168) + return OPCODE_AE_MIN32; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 169) + return OPCODE_AE_MIN8; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 170) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 172 && + Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_get (insn) == 1) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 172 && + Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_get (insn) == 0) + return OPCODE_AE_ABS16S; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 173 && + Field_fld_ae4_slot2_4_0_Slot_ae4_slot2_get (insn) == 0) + return OPCODE_AE_MOV; + if (Field_fld_ae4_slot2_23_17_Slot_ae4_slot2_get (insn) == 40) + return OPCODE_AE_SEL16I_N; + if (Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (insn) == 1) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (insn) == 2) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (insn) == 3) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (insn) == 4) + return OPCODE_AE_ADDANDSUBRNG32_L; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot3_27_20_Slot_ae4_slot3_get (insn) == 96 && + Field_fld_ae4_slot3_14_10_Slot_ae4_slot3_get (insn) == 0) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 0) + return OPCODE_AE_MULFPC32X16X2RAS; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 1) + return OPCODE_AE_MULFPCJ32X16X2RAS; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 22 && + Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_get (insn) == 161) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 1) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 2) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 3) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 4) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_19_Slot_ae4_slot3_get (insn) == 0 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_SEL16I; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_5_Slot_ae4_slot3_get (insn) == 23557) + return OPCODE_AE_MOV; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 22 && + Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_get (insn) == 160) + return OPCODE_AE_ABS16S; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 20 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MIN32; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 17 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MAX32; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 19 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MIN16; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 16 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MAX16; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 18 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MAX8; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 21 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MIN8; + if (Field_fld_ae4_slot3_27_3_Slot_ae4_slot3_get (insn) == 8482964 && + Field_fld_ae4_slot3_2_0_Slot_ae4_slot3_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot4_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot4_22_0_Slot_ae4_slot4_get (insn) == 5308480) + return OPCODE_NOP; + if (Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get (insn) == 160) + return OPCODE_AE_MAX16; + if (Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get (insn) == 161) + return OPCODE_AE_MIN16; + if (Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get (insn) == 162 && + Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_get (insn) == 1) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get (insn) == 162 && + Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_get (insn) == 0) + return OPCODE_AE_ABS16S; + if (Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (insn) == 1) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (insn) == 2) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (insn) == 3) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (insn) == 4) + return OPCODE_AE_ADDANDSUBRNG32_L; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae5_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae5_slot1_1_0_Slot_ae5_slot1_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae5_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae5_slot2_24_0_Slot_ae5_slot2_get (insn) == 24117778) + return OPCODE_NOP; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 752 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 753 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_ADDEXP_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 754 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_MKDADJ_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 755 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 756 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_ADDEXP_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 768) + return OPCODE_FREXP_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 769) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 770) + return OPCODE_MAXNUM_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 771) + return OPCODE_MAX_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 772) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 773) + return OPCODE_MINNUM_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 774) + return OPCODE_MIN_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 775) + return OPCODE_ADD_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 776) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 777) + return OPCODE_ADD_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 778) + return OPCODE_MADD_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 779) + return OPCODE_MSUB_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 780) + return OPCODE_MUL_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 781) + return OPCODE_SUB_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 782) + return OPCODE_SUB_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 783 && + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_CLSFY_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 783 && + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get (insn) == 184 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_PKSR16; + if (Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get (insn) == 185 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_PKSR24; + if (Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get (insn) == 186 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_PKSR32; + if (Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get (insn) == 187 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MUL16X4; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MUL16X4S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULAFC32RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULFC32RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_SEL8X8I; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_7_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_SEL16I_N; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MUL32U_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULA32U_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MUL16S_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULA16S_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MUL32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULA32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MUL32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULA32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MUL32S_HL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULA32S_HL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MUL32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULA32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULAAD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULAAD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULAA2D16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULAA2D16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULAAFD16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULAAFD16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULAC32; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULAC32X16_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULAC32X16_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULAFCJ32RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULACJ32; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULAFCJ16RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULAC16S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULAFP32X2TS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULAP32X2T; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULASD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULASD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULAP16S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULAP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULC16S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULAP16X16X4S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULFP16X4S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULC32; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULC32X16_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULC32X16_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULFCJ32RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULCJ32; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULFCJ16RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULFP16X4RS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULS32U_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULS16S_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULFP32X2TS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULP32X2T; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULS32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULS32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULS32S_HL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULS32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULP16S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULP16X16X4S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULSAD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULSAD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULSFP32X2TS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULSP32X2T; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULSSD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULSSD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULSP16S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULSP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULSP16X16X4S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULSS2D16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULSS2D16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULSSFD16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULZAAD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULZASD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULZAAD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULZAA2D16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULZAA2D16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULZAAFD16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULZAAFD16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULSSFD16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULZSAD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULZSSD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULZASD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULZSAD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULZSSD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULZSS2D16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULZSS2D16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULZSSFD16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULZSSFD16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_14_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 527) + return OPCODE_AE_MOV; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_MUL_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_MADD_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_MSUB_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_MSUBN_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_MADDN_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 514) + return OPCODE_NEXP01_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 513) + return OPCODE_MKSADJ_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 512) + return OPCODE_DIV0_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 517) + return OPCODE_SQRT0_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 515) + return OPCODE_RECIP0_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 516) + return OPCODE_RSQRT0_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_DIVN_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 518) + return OPCODE_ABS_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 523) + return OPCODE_NEG_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 520) + return OPCODE_CONJC_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 522) + return OPCODE_MULJC_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get (insn) == 0 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 529) + return OPCODE_CONST_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 524) + return OPCODE_ABS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 525) + return OPCODE_CLSFY_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 519) + return OPCODE_CONJC_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get (insn) == 0 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 528) + return OPCODE_CONST_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_MIN_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_MAX_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_MINNUM_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_MAXNUM_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 521) + return OPCODE_MULJC_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 526) + return OPCODE_NEG_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 25 && + Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 25 && + Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 25 && + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get (insn) == 1 && + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 25 && + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get (insn) == 1 && + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_CONST_HX4X2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19688) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19689) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19690) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19691) + return OPCODE_AE_MOV; + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19692) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19693) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2452) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2453) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2454 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2454 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2455 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_PKSR24; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2455 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_PKSR16; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2460 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_PKSR32; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2460 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_get (insn) == 1224) + return OPCODE_AE_MOVF64; + if (Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_get (insn) == 1225) + return OPCODE_AE_MOVT64; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 608 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_LE64; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 608 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_EQ64; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 609 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 609 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 609 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 609 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 610 && + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (insn) == 1 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 610 && + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 610 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_LT64; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 611 && + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 611 && + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 611 && + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (insn) == 1 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 611 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 3 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 611 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 2 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 614 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 2) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 614 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 3) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 614 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 614 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 624 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 624 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 2 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 624 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 1 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 60) + return OPCODE_AE_ADDC32; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 61) + return OPCODE_AE_ADDC32U; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 62) + return OPCODE_AE_BMAX32X2; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 63) + return OPCODE_AE_BMIN32X2; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 64) + return OPCODE_AE_SUBC32; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 65) + return OPCODE_AE_SUBC32U; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 66) + return OPCODE_AE_S16X4X2_I; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 67) + return OPCODE_AE_S16X4X2_IP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 68) + return OPCODE_AE_S16X4X2_X; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 69) + return OPCODE_AE_S16X4X2_XP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 70) + return OPCODE_AE_S32X2X2_I; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 71) + return OPCODE_AE_S32X2X2_IP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 72) + return OPCODE_AE_S32X2X2_X; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 73) + return OPCODE_AE_S32X2X2_XP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 74 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_BMAX8X8_L; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 74 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_BMAX16X4; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 75 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_BMIN8X8_L; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 75 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_BMIN16X4; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_7_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_L_IP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 20) + return OPCODE_AE_LT16; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 1 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 19) + return OPCODE_AE_LE16; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 19) + return OPCODE_AE_EQ16; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 18) + return OPCODE_AE_LT32; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 17) + return OPCODE_AE_LE32; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 16) + return OPCODE_AE_EQ32; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 2) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 3) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 4) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 5) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 6) + return OPCODE_AE_ADDW16; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 7) + return OPCODE_AE_ADDW32; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 8) + return OPCODE_AE_ADDW8; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 9) + return OPCODE_AE_ADDW8U; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 10) + return OPCODE_AE_SUBW16; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 11) + return OPCODE_AE_SUBW32; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 12) + return OPCODE_AE_SUBW8; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 13) + return OPCODE_AE_SUBW8U; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 14) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae6_slot0_29_5_Slot_ae6_slot0_get (insn) == 630208 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot2_24_0_Slot_ae6_slot2_get (insn) == 1245280) + return OPCODE_NOP; + if (Field_fld_ae6_slot2_24_10_Slot_ae6_slot2_get (insn) == 1170) + return OPCODE_AE_MOV; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 70) + return OPCODE_AE_MOVF64; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 71) + return OPCODE_AE_MOVT64; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 72 && + Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_get (insn) == 1) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 72 && + Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 73 && + Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_get (insn) == 1) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 73 && + Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 32) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 33) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 34) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 37 && + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get (insn) == 2) + return OPCODE_AE_PKSR32; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 37 && + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get (insn) == 1) + return OPCODE_AE_PKSR24; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 37 && + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get (insn) == 3) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 37 && + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_PKSR16; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 38 && + Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_get (insn) == 2) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 38 && + Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 38 && + Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_get (insn) == 1) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae6_slot2_24_20_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_MOVDX2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot3_37_13_Slot_ae6_slot3_get (insn) == 1179648 && + Field_fld_ae6_slot3_12_0_Slot_ae6_slot3_get (insn) == 33) + return OPCODE_NOP; + if (Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_get (insn) == 274432 && + Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_get (insn) == 274433 && + Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8192) + return OPCODE_AE_ACCW16; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8224) + return OPCODE_AE_ACCW32; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8256) + return OPCODE_AE_ACCW8; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8288) + return OPCODE_AE_ACCW8U; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8320) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8352) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8384) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8416) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8448) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8480) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 2 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_BMAX8X8_H; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 3 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_BMAX8X8_L; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 2 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_BMAX16X4; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 3 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_BMIN16X4; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_BMAX32X2; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_BMIN32X2; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 9) + return OPCODE_AE_ADD32S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 12) + return OPCODE_AE_SUB32S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 8) + return OPCODE_AE_ADD16S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 11) + return OPCODE_AE_SUB16S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 451) + return OPCODE_AE_NEG32S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 480) + return OPCODE_AE_ABS32S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 482) + return OPCODE_AE_NEG16S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 448) + return OPCODE_AE_ABS16S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 449) + return OPCODE_AE_ABS8S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 483) + return OPCODE_AE_NEG8S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 10) + return OPCODE_AE_ADD8S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 13) + return OPCODE_AE_SUB8S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 0 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_BMIN8X8_H; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 0 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_BMIN8X8_L; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 481) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 450) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_MULZAAF2D32RA_HH_LL; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_MULZAAF2D32RA_HL_LH; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 2) + return OPCODE_AE_MULZASF2D32RA_HH_LL; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 3) + return OPCODE_AE_MULZASF2D32RA_HL_LH; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 4) + return OPCODE_AE_MULZSAF2D32RA_HH_LL; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 5) + return OPCODE_AE_MULZSAF2D32RA_HL_LH; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 6) + return OPCODE_AE_MULZSSF2D32RA_HH_LL; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 7) + return OPCODE_AE_MULZSSF2D32RA_HL_LH; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 9 && + Field_fld_ae6_slot3_24_20_Slot_ae6_slot3_get (insn) == 0 && + Field_fld_ae6_slot3_14_0_Slot_ae6_slot3_get (insn) == 32) + return OPCODE_AE_MOV; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 9 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_MOVDX2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot0_23_0_Slot_ae7_slot0_get (insn) == 6889856) + return OPCODE_NOP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 864) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 865) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 866) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 867) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 868) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 869) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 870) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 871) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 872) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 873) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 874) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 875) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 876) + return OPCODE_AE_L64_X; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 877) + return OPCODE_AE_L64_XC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 878) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 879) + return OPCODE_AE_L64_XP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 880) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 881) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 882) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 883) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 884 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 884 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 885 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 885 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 885 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 886 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 886 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 886 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 887 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 887 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 887 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 888 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 888 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 888 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 889 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 889 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 889 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 890 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 890 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 890 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 8) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 9) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 10) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 11) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 892 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 892 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 893 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 893 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 894 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 894 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 895 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 895 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 52 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 52 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 6) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 52 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 4) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 52 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 7) + return OPCODE_AE_L64_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 52 && + Field_fld_ae7_slot0_12_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 53 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 5) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 53 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 4) + return OPCODE_AE_L64_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 4) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 5) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 6) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 7) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 8) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 9) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 10) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 11) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 12) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 13) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 14) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 15) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 16) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 17) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 18) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 19) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 20) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 21) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 22) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 23) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 24 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 24 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 24 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 24 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 25 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 25 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 25 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 25 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 26 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 106502) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 106630) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 106758) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 106886) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 107014) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 107142) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 107270) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 107398) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 107526) + return OPCODE_AE_LA8X8X2POS_PC2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot1_23_0_Slot_ae7_slot1_get (insn) == 6889856) + return OPCODE_NOP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 864) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 865) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 866) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 867) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 868) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 869) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 870) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 871) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 872) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 873) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 874) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 875) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 876) + return OPCODE_AE_L64_X; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 877) + return OPCODE_AE_L64_XC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 878) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 879) + return OPCODE_AE_L64_XP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 880) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 881) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 882) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 883) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 884 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 884 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 885 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 885 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 885 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 886 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 886 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 886 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 887 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 887 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 887 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 888 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 888 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 888 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 889 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 889 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 889 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 890 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 890 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 890 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 8) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 9) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 10) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 11) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 892 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 892 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 893 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 893 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 894 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 894 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 895 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 895 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 52 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 5) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 52 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 6) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 52 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 4) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 52 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 7) + return OPCODE_AE_L64_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 52 && + Field_fld_ae7_slot1_12_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 53 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 5) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 53 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 4) + return OPCODE_AE_L64_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 4) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 5) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 6) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 7) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 8) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 9) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 10) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 11) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 12) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 13) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 14) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 15) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 16) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 17) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 18) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 19) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 20) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 21) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 22) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 23) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 24 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 24 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 24 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 24 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 25 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 25 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 25 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 25 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 26 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 106502) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 106630) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 106758) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 106886) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 107014) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 107142) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 107270) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 107398) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 107526) + return OPCODE_AE_LA8X8X2POS_PC2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot2_36_12_Slot_ae7_slot2_get (insn) == 14772992 && + Field_fld_ae7_slot2_11_0_Slot_ae7_slot2_get (insn) == 1376) + return OPCODE_NOP; + if (Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_get (insn) == 1846592) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_get (insn) == 1846593) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57696) + return OPCODE_AE_MULAAAA2Q8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57697) + return OPCODE_AE_MULADDF32RAS; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57698) + return OPCODE_AE_MULADDF32RS; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57699) + return OPCODE_AE_MULSUBF32RAS; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57700) + return OPCODE_AE_MULSUBF32RS; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57701) + return OPCODE_AE_MULZAAAA2Q8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57702) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57703) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57704) + return OPCODE_AE_SEL8X8I; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 0) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 2) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 3) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 4) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 5) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 6) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 42) + return OPCODE_AE_MOV; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 39) + return OPCODE_AE_RMAX8X8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 41) + return OPCODE_AE_RMIN8X8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 38) + return OPCODE_AE_RMAX16X4; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 40) + return OPCODE_AE_RMIN16X4; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_10_Slot_ae7_slot2_get (insn) == 0) + return OPCODE_AE_SORT16X4; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 33) + return OPCODE_AE_RADD8X8_H; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 36) + return OPCODE_AE_RADDA8X8_H; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 34) + return OPCODE_AE_RADD8X8_L; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 37) + return OPCODE_AE_RADDA8X8_L; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 32) + return OPCODE_AE_RADD16X4; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 35) + return OPCODE_AE_RADDA16X4; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1760) + return OPCODE_AE_MULAAAA2Q16X8; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1761) + return OPCODE_AE_MULAF2P32X16X4RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1762) + return OPCODE_AE_MULAF2P32X16X4RS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1763) + return OPCODE_AE_MULAF2P32X16X4S; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1764) + return OPCODE_AE_MULAFD32X16X2_FIR_HH; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1765) + return OPCODE_AE_MULAFD32X16X2_FIR_HL; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1766) + return OPCODE_AE_MULAFD32X16X2_FIR_LH; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1767) + return OPCODE_AE_MULAFD32X16X2_FIR_LL; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1768) + return OPCODE_AE_MULAFD32X2RA_FIR_H; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1769) + return OPCODE_AE_MULAFD32X2RA_FIR_L; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1770) + return OPCODE_AE_MULAFD32X2S_FIR_H; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1771) + return OPCODE_AE_MULAFD32X2S_FIR_L; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1772) + return OPCODE_AE_MULAFPC32X16X2RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1773) + return OPCODE_AE_MULAFPCJ32X16X2RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1774) + return OPCODE_AE_MULAFQ16X2_FIR_0; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1775) + return OPCODE_AE_MULAFQ16X2_FIR_1; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1776) + return OPCODE_AE_MULAFQ16X2_FIR_2; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1777) + return OPCODE_AE_MULAFQ16X2_FIR_3; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1778) + return OPCODE_AE_MULAPC32X16X2; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1779) + return OPCODE_AE_MULF2P32X16X4RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1780) + return OPCODE_AE_MULF2P32X16X4RS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1781) + return OPCODE_AE_MULF2P32X16X4S; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1782) + return OPCODE_AE_MULFD32X16X2_FIR_HH; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1783) + return OPCODE_AE_MULFD32X16X2_FIR_HL; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1784) + return OPCODE_AE_MULFD32X16X2_FIR_LH; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1785) + return OPCODE_AE_MULFD32X16X2_FIR_LL; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1786) + return OPCODE_AE_MULFD32X2RA_FIR_H; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1787) + return OPCODE_AE_MULFD32X2RA_FIR_L; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1788) + return OPCODE_AE_MULFD32X2S_FIR_H; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1789) + return OPCODE_AE_MULFD32X2S_FIR_L; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1790) + return OPCODE_AE_MULFPC32X16X2RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1791) + return OPCODE_AE_MULFPCJ32X16X2RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1792) + return OPCODE_AE_MULFQ16X2_FIR_0; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1793) + return OPCODE_AE_MULFQ16X2_FIR_1; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1794) + return OPCODE_AE_MULFQ16X2_FIR_2; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1795) + return OPCODE_AE_MULFQ16X2_FIR_3; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1796) + return OPCODE_AE_MULPC32X16X2; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1797) + return OPCODE_AE_MULSF2P32X16X4RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1798) + return OPCODE_AE_MULSF2P32X16X4RS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1799) + return OPCODE_AE_MULSF2P32X16X4S; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1800) + return OPCODE_AE_MULZAAAA2Q16X8; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1801) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1802) + return OPCODE_AE_DSEL8X8; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1824 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULAAAAFQ32X16; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1825 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULAAAAQ32X16; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1826 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULZAAAAFQ32X16; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1827 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULZAAAAQ32X16; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 0) + return OPCODE_AE_MUL2P32X4; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MUL2P32X4S; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 2) + return OPCODE_AE_MUL2P32X4T; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 3) + return OPCODE_AE_MUL2Q32X16_FIR_H; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 4) + return OPCODE_AE_MUL2Q32X16_FIR_L; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 5) + return OPCODE_AE_MULA2P32X4; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 6) + return OPCODE_AE_MULA2P32X4T; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 7) + return OPCODE_AE_MULA2Q32X16_FIR_H; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 8) + return OPCODE_AE_MULA2Q32X16_FIR_L; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 9) + return OPCODE_AE_MULAAAA2Q16; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 10) + return OPCODE_AE_MULAAAA2Q32X16; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 11) + return OPCODE_AE_MULAAF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 12) + return OPCODE_AE_MULAAF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 13) + return OPCODE_AE_MULAAF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 14) + return OPCODE_AE_MULAAF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 15) + return OPCODE_AE_MULAF2P32X4RAS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 16) + return OPCODE_AE_MULAF2P32X4RS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 17) + return OPCODE_AE_MULASF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 18) + return OPCODE_AE_MULASF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 19) + return OPCODE_AE_MULASF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 20) + return OPCODE_AE_MULASF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 21) + return OPCODE_AE_MULF2D32X2WS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 22) + return OPCODE_AE_MULF2P32X4RAS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 23) + return OPCODE_AE_MULF2P32X4RS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 24) + return OPCODE_AE_MULFD16X16X4WS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 25) + return OPCODE_AE_MULS2P32X4; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 26) + return OPCODE_AE_MULS2P32X4T; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 27) + return OPCODE_AE_MULSAF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 28) + return OPCODE_AE_MULSAF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 29) + return OPCODE_AE_MULSAF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 30) + return OPCODE_AE_MULSAF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 31) + return OPCODE_AE_MULSF2P32X4RAS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 32) + return OPCODE_AE_MULSF2P32X4RS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 33) + return OPCODE_AE_MULSSF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 34) + return OPCODE_AE_MULSSF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 35) + return OPCODE_AE_MULSSF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 36) + return OPCODE_AE_MULSSF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 37) + return OPCODE_AE_MULZAAAA2Q16; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 38) + return OPCODE_AE_MULZAAAA2Q32X16; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 39) + return OPCODE_AE_MULZAAF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 40) + return OPCODE_AE_MULZAAF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 41) + return OPCODE_AE_MULZAAF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 42) + return OPCODE_AE_MULZAAF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 43) + return OPCODE_AE_MULZASF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 44) + return OPCODE_AE_MULZASF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 45) + return OPCODE_AE_MULZASF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 46) + return OPCODE_AE_MULZASF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 47) + return OPCODE_AE_MULZSAF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 48) + return OPCODE_AE_MULZSAF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 49) + return OPCODE_AE_MULZSAF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 50) + return OPCODE_AE_MULZSAF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 51) + return OPCODE_AE_MULZSSF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 52) + return OPCODE_AE_MULZSSF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 53) + return OPCODE_AE_MULZSSF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 54) + return OPCODE_AE_MULZSSF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 57 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 0) + return OPCODE_AE_MULFD16X16X4RAS; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot3_35_11_Slot_ae7_slot3_get (insn) == 29884417 && + Field_fld_ae7_slot3_10_0_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57632) + return OPCODE_AE_MULAAAA2Q8; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57633) + return OPCODE_AE_MULADDF32RAS; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57634) + return OPCODE_AE_MULADDF32RS; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57635) + return OPCODE_AE_MULSUBF32RAS; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57636) + return OPCODE_AE_MULSUBF32RS; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57637) + return OPCODE_AE_MULZAAAA2Q8; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57638 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57638 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57638 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 2) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57638 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 3) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57639 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57639 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57639 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 2) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1760) + return OPCODE_AE_MULAAAA2Q16X8; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1761) + return OPCODE_AE_MULAF2P32X16X4RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1762) + return OPCODE_AE_MULAF2P32X16X4RS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1763) + return OPCODE_AE_MULAF2P32X16X4S; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1764) + return OPCODE_AE_MULAFD32X16X2_FIR_HH; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1765) + return OPCODE_AE_MULAFD32X16X2_FIR_HL; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1766) + return OPCODE_AE_MULAFD32X16X2_FIR_LH; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1767) + return OPCODE_AE_MULAFD32X16X2_FIR_LL; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1768) + return OPCODE_AE_MULAFD32X2RA_FIR_H; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1769) + return OPCODE_AE_MULAFD32X2RA_FIR_L; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1770) + return OPCODE_AE_MULAFD32X2S_FIR_H; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1771) + return OPCODE_AE_MULAFD32X2S_FIR_L; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1772) + return OPCODE_AE_MULAFPC32X16X2RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1773) + return OPCODE_AE_MULAFPCJ32X16X2RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1774) + return OPCODE_AE_MULAFQ16X2_FIR_0; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1775) + return OPCODE_AE_MULAFQ16X2_FIR_1; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1776) + return OPCODE_AE_MULAFQ16X2_FIR_2; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1777) + return OPCODE_AE_MULAFQ16X2_FIR_3; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1778) + return OPCODE_AE_MULAPC32X16X2; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1779) + return OPCODE_AE_MULF2P32X16X4RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1780) + return OPCODE_AE_MULF2P32X16X4RS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1781) + return OPCODE_AE_MULF2P32X16X4S; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1782) + return OPCODE_AE_MULFD32X16X2_FIR_HH; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1783) + return OPCODE_AE_MULFD32X16X2_FIR_HL; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1784) + return OPCODE_AE_MULFD32X16X2_FIR_LH; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1785) + return OPCODE_AE_MULFD32X16X2_FIR_LL; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1786) + return OPCODE_AE_MULFD32X2RA_FIR_H; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1787) + return OPCODE_AE_MULFD32X2RA_FIR_L; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1788) + return OPCODE_AE_MULFD32X2S_FIR_H; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1789) + return OPCODE_AE_MULFD32X2S_FIR_L; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1790) + return OPCODE_AE_MULFPC32X16X2RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1791) + return OPCODE_AE_MULFPCJ32X16X2RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1792) + return OPCODE_AE_MULFQ16X2_FIR_0; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1793) + return OPCODE_AE_MULFQ16X2_FIR_1; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1794) + return OPCODE_AE_MULFQ16X2_FIR_2; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1795) + return OPCODE_AE_MULFQ16X2_FIR_3; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1796) + return OPCODE_AE_MULPC32X16X2; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1797) + return OPCODE_AE_MULSF2P32X16X4RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1798) + return OPCODE_AE_MULSF2P32X16X4RS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1799) + return OPCODE_AE_MULSF2P32X16X4S; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1800) + return OPCODE_AE_MULZAAAA2Q16X8; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1856 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULAAAAFQ32X16; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1856 && + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (insn) == 98) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1857 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULAAAAQ32X16; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1857 && + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (insn) == 98) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1858 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULZAAAAFQ32X16; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1859 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULZAAAAQ32X16; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MUL2P32X4; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MUL2P32X4S; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 2) + return OPCODE_AE_MUL2P32X4T; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 3) + return OPCODE_AE_MUL2Q32X16_FIR_H; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 4) + return OPCODE_AE_MUL2Q32X16_FIR_L; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 5) + return OPCODE_AE_MULA2P32X4; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 6) + return OPCODE_AE_MULA2P32X4T; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 7) + return OPCODE_AE_MULA2Q32X16_FIR_H; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 8) + return OPCODE_AE_MULA2Q32X16_FIR_L; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 9) + return OPCODE_AE_MULAAAA2Q16; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 10) + return OPCODE_AE_MULAAAA2Q32X16; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 11) + return OPCODE_AE_MULAAF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 12) + return OPCODE_AE_MULAAF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 13) + return OPCODE_AE_MULAAF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 14) + return OPCODE_AE_MULAAF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 15) + return OPCODE_AE_MULAF2P32X4RAS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 16) + return OPCODE_AE_MULAF2P32X4RS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 17) + return OPCODE_AE_MULASF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 18) + return OPCODE_AE_MULASF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 19) + return OPCODE_AE_MULASF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 20) + return OPCODE_AE_MULASF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 21) + return OPCODE_AE_MULF2D32X2WS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 22) + return OPCODE_AE_MULF2P32X4RAS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 23) + return OPCODE_AE_MULF2P32X4RS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 24) + return OPCODE_AE_MULFD16X16X4WS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 25) + return OPCODE_AE_MULS2P32X4; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 26) + return OPCODE_AE_MULS2P32X4T; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 27) + return OPCODE_AE_MULSAF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 28) + return OPCODE_AE_MULSAF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 29) + return OPCODE_AE_MULSAF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 30) + return OPCODE_AE_MULSAF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 31) + return OPCODE_AE_MULSF2P32X4RAS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 32) + return OPCODE_AE_MULSF2P32X4RS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 33) + return OPCODE_AE_MULSSF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 34) + return OPCODE_AE_MULSSF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 35) + return OPCODE_AE_MULSSF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 36) + return OPCODE_AE_MULSSF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 37) + return OPCODE_AE_MULZAAAA2Q16; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 38) + return OPCODE_AE_MULZAAAA2Q32X16; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 39) + return OPCODE_AE_MULZAAF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 40) + return OPCODE_AE_MULZAAF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 41) + return OPCODE_AE_MULZAAF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 42) + return OPCODE_AE_MULZAAF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 43) + return OPCODE_AE_MULZASF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 44) + return OPCODE_AE_MULZASF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 45) + return OPCODE_AE_MULZASF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 46) + return OPCODE_AE_MULZASF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 47) + return OPCODE_AE_MULZSAF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 48) + return OPCODE_AE_MULZSAF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 49) + return OPCODE_AE_MULZSAF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 50) + return OPCODE_AE_MULZSAF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 51) + return OPCODE_AE_MULZSSF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 52) + return OPCODE_AE_MULZSSF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 53) + return OPCODE_AE_MULZSSF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 54) + return OPCODE_AE_MULZSSF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 57 && + Field_fld_ae7_slot3_24_10_Slot_ae7_slot3_get (insn) == 2 && + Field_fld_ae7_slot3_4_0_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MOV; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 57 && + Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_DSEL8X8; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 57 && + Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 58 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MULFD16X16X4RAS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 58 && + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (insn) == 34) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 58 && + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (insn) == 2) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 58 && + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (insn) == 66) + return OPCODE_AE_SEL8X8I; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae8_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get (insn) == 566808 && + Field_fld_ae8_slot2_33_9_Slot_ae8_slot2_get (insn) == 4096 && + Field_fld_ae8_slot2_8_0_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get (insn) == 566808 && + Field_fld_ae8_slot2_33_25_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_15_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_get (insn) == 0) + return OPCODE_AE_MOV; + if (Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get (insn) == 566808 && + Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_get (insn) == 32 && + Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MOVZBVCDR; + if (Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get (insn) == 566808 && + Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MOVDRZBVC; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 262924) + return OPCODE_AE_MUL4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 263948) + return OPCODE_AE_MUL4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 264972) + return OPCODE_AE_MULA4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 265996) + return OPCODE_AE_MULA4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 267020) + return OPCODE_AE_MULASU4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 268044) + return OPCODE_AE_MULASU4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 269068) + return OPCODE_AE_MULAUS4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 270092) + return OPCODE_AE_MULAUS4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 271116) + return OPCODE_AE_MULAUU4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 272140) + return OPCODE_AE_MULAUU4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 273164) + return OPCODE_AE_MULAUUZB4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 274188) + return OPCODE_AE_MULAUUZB4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 275212) + return OPCODE_AE_MULSU4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 276236) + return OPCODE_AE_MULSU4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 277260) + return OPCODE_AE_MULUS4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 278284) + return OPCODE_AE_MULUS4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 279308) + return OPCODE_AE_MULUU4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 280332) + return OPCODE_AE_MULUU4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 281356) + return OPCODE_AE_MULUUZB4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 282380) + return OPCODE_AE_MULUUZB4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 360645 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MUL8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 360645 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MUL2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 360677 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MUL8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 360677 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULA2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 361669 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULA8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 361669 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULA8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 361701 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULASU8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 361701 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULASU2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 362693 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUS2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 362693 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULASU8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 362725 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUS8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 362725 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUS8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 363717 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUU8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 363717 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUU2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 363749 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUU8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 363749 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUUZB2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 364741 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUUZB8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 364741 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUUZB8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 364773 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULSU8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 364773 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULSU2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 365765 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 365765 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULSU8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 365797 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 365797 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUS8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 366789 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUU8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 366789 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUU2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 366821 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUU8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 366821 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUUZB2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 367813 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUUZB8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 367813 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUUZB8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10240) + return OPCODE_AE_MUL4O4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10272) + return OPCODE_AE_MUL4QW8X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10304) + return OPCODE_AE_MULA4O4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10336) + return OPCODE_AE_MULA4QW8X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10368) + return OPCODE_AE_MULAUS4O4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10400) + return OPCODE_AE_MULAUS4QW8X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10432) + return OPCODE_AE_MULUS4O4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10464) + return OPCODE_AE_MULUS4QW8X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 11264 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MUL8Q4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 11265 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MULA8Q4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 11266 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MULAUS8Q4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 11267 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MULUS8Q4X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 0) + return OPCODE_AE_MUL4O8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MUL8QW8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 2) + return OPCODE_AE_MULA4O8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 3) + return OPCODE_AE_MULA8QW8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULAUS4O8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULAUS8QW8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUS4O8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS8QW8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULQQ8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 2) + return OPCODE_AE_MULAQQ8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 140) + return OPCODE_AE_MUL4O8X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 332) + return OPCODE_AE_MULA4O8X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 172) + return OPCODE_AE_MUL4O8X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 364) + return OPCODE_AE_MULA4O8X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULQQ4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 0) + return OPCODE_AE_MULAQQ4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULQQ4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MULAQQ4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 12) + return OPCODE_AE_MUL4O4X16CNV_HH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 44) + return OPCODE_AE_MUL4O4X16CNV_HL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 76) + return OPCODE_AE_MUL4O4X16CNV_LH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 108) + return OPCODE_AE_MUL4O4X16CNV_LL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 204) + return OPCODE_AE_MULA4O4X16CNV_HH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 236) + return OPCODE_AE_MULA4O4X16CNV_HL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 268) + return OPCODE_AE_MULA4O4X16CNV_LH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 300) + return OPCODE_AE_MULA4O4X16CNV_LL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 11) + return OPCODE_AE_MULUSQQ8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULAUSQQ8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 716) + return OPCODE_AE_MULUS4O8X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 524) + return OPCODE_AE_MULAUS4O8X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 748) + return OPCODE_AE_MULUS4O8X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 556) + return OPCODE_AE_MULAUS4O8X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MULUSQQ4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3) + return OPCODE_AE_MULAUSQQ4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 10) + return OPCODE_AE_MULUSQQ4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULAUSQQ4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 588) + return OPCODE_AE_MULUS4O4X16CNV_HH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 620) + return OPCODE_AE_MULUS4O4X16CNV_HL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 652) + return OPCODE_AE_MULUS4O4X16CNV_LH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 684) + return OPCODE_AE_MULUS4O4X16CNV_LL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 396) + return OPCODE_AE_MULAUS4O4X16CNV_HH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 428) + return OPCODE_AE_MULAUS4O4X16CNV_HL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 460) + return OPCODE_AE_MULAUS4O4X16CNV_LH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 492) + return OPCODE_AE_MULAUS4O4X16CNV_LL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 0) + return OPCODE_AE_MUL4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MULA4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULUU4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULAUU4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 3) + return OPCODE_AE_MULAUS4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULSU4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 2) + return OPCODE_AE_MULASU4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MULUUZB4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULAUUZB4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MUL8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 1 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULA8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 0) + return OPCODE_AE_MUL8Q8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MULA8Q8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 37 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MUL8Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 69 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULA8Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MUL2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 1 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULA2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MUL2X4Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 1 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULA2X4Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 5 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MUL8Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 37 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULA8Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 5 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MUL8Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 69 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULA8Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MUL2X4Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 1 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULA2X4Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MUL2X4Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 1 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULA2X4Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULUU8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 4 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULAUU8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 5 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULUU2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULAUU2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 7 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULUS8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULAUS8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 3) + return OPCODE_AE_MULUS8Q8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 2) + return OPCODE_AE_MULAUS8Q8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 165 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS8Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 133 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUS8Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 4 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULAUS2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 4 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUS2X4Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 2 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUS2X4Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 133 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS8Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 101 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUS8Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 165 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUS8Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 101 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUS8Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 4 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULUS2X4Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 2 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULAUS2X4Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 4 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULUS2X4Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 2 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUS2X4Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 6 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULSU8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 2 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULASU8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULSU2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 2 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULASU2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULUUZB8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 5 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULAUUZB8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 5 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULUUZB2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUUZB2X4Q8X8CNV_L; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae9_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_get (insn) == 228098 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONST_H; + if (Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_get (insn) == 228099 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONST_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 98689 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ABS_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 99713 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONJC_H; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 100737 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONJC_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 101761 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_DIV0_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 102785 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MKSADJ_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 103809 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MULJC_H; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 104833 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MULJC_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 105857 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_NEG_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 106881 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_NEXP01_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 107905 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_RECIP0_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 108929 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_RSQRT0_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 109953 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_SQRT0_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 110977 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ABS_H; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 112001 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CLSFY_H; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 113025 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_NEG_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2624 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_DIVN_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2656 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MADDN_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2688 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MADD_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2720 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MSUBN_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2752 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MSUB_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2784 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MUL_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3083 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MAXNUM_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3115 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MAX_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3147 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MINNUM_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3179 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MIN_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3211 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 1 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_AE_MOVT64; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3211 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_AE_MOVF64; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 1 && + Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_get (insn) == 33) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 1 && + Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_get (insn) == 33) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 865) + return OPCODE_AE_MOV; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 705) + return OPCODE_MKDADJ_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 609) + return OPCODE_ADDEXP_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 577) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 833) + return OPCODE_ADDEXP_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 737) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 74) + return OPCODE_MADDQ_S; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 75) + return OPCODE_MSUBQ_S; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 76) + return OPCODE_MULQ_S; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 77) + return OPCODE_MULQ_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 0) + return OPCODE_MADDA_S; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 128) + return OPCODE_ADD_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 133) + return OPCODE_SUB_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 132) + return OPCODE_MUL_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 129) + return OPCODE_MADD_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 131) + return OPCODE_MSUB_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 130) + return OPCODE_MSUBN_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 96 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 2) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_get (insn) == 36) + return OPCODE_MULMUXQ_S; + if (Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_get (insn) == 40 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MULMUX_S; + if (Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_get (insn) == 8) + return OPCODE_MADDMUXQ_S; + if (Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 0) + return OPCODE_ADD_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_SUB_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 0) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 33) + return OPCODE_ADD_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 161) + return OPCODE_SUB_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 321) + return OPCODE_MIN_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 385) + return OPCODE_MAX_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_get (insn) == 386 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CLSFY_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 193) + return OPCODE_MINNUM_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 257) + return OPCODE_MAXNUM_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 9 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 8 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 449) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_FREXP_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_get (insn) == 386 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 33) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 65) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 129) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 1 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 7 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 5 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_get (insn) == 769 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 6 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 2 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_get (insn) == 768 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 4 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae9_slot2_33_9_Slot_ae9_slot2_get (insn) == 6316160 && + Field_fld_ae9_slot2_8_0_Slot_ae9_slot2_get (insn) == 65) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae9_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get (insn) == 28696) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get (insn) == 28697) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get (insn) == 29846 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CONST_H; + if (Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get (insn) == 29847 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CONST_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14347 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CLSFY_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14379 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_DIV0_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14411 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14443 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_MKSADJ_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14475 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_NEXP01_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14507 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_RECIP0_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14539 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_RSQRT0_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14571 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_SQRT0_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14603 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_ABS_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14635 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CONJC_H; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14667 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CONJC_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14699 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_MULJC_H; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14731 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_MULJC_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14763 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_NEG_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14795 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_ABS_H; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14827 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CLSFY_H; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14859 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_NEG_H; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14891 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_AE_MOV; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 576 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_DIVN_S; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 608 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MADDN_S; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 640 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MADD_S; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 672 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MSUBN_S; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 704 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MSUB_S; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 736 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MUL_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 10) + return OPCODE_MADDQ_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 11) + return OPCODE_MSUBQ_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 12) + return OPCODE_MULQ_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 13) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_4_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_AE_SEL16I; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 27) + return OPCODE_MIN_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 25) + return OPCODE_MAX_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 26) + return OPCODE_MINNUM_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 25) + return OPCODE_MAXNUM_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 9) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 8) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 24) + return OPCODE_FREXP_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 26) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 24) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_BMAXNUM_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get (insn) == 2) + return OPCODE_BMINNUM_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_BMAXNUMABS_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get (insn) == 2) + return OPCODE_BMINNUMABS_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 7) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 3) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 5) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_MIN_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 28) + return OPCODE_MAX_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 28) + return OPCODE_MINNUM_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 27) + return OPCODE_MAXNUM_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 6) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 2) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 4) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 5) + return OPCODE_ADD_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 6) + return OPCODE_SUB_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 226) + return OPCODE_MKDADJ_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 225) + return OPCODE_ADDEXP_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 224) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 4) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_MADDA_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 228) + return OPCODE_ADDEXP_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 227) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 64) + return OPCODE_ADD_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 98) + return OPCODE_SUB_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 66) + return OPCODE_MUL_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 96) + return OPCODE_MADD_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 97) + return OPCODE_MSUB_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 65) + return OPCODE_MSUBN_H; + if (Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_get (insn) == 4) + return OPCODE_MULMUXQ_S; + if (Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_get (insn) == 8 && + Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MULMUX_S; + if (Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_MADDMUXQ_S; + if (Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_get (insn) == 2 && + Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae9_slot3_31_7_Slot_ae9_slot3_get (insn) == 3828480 && + Field_fld_ae9_slot3_6_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4096) + return OPCODE_AE_EXPADD16_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4097) + return OPCODE_AE_EXPADD16_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4098) + return OPCODE_AE_EXPSUB16_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4099) + return OPCODE_AE_EXPSUB16_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4100) + return OPCODE_AE_ADD16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4101) + return OPCODE_AE_ADD16S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4102) + return OPCODE_AE_ADD24S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4103) + return OPCODE_AE_ADD32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4104) + return OPCODE_AE_ADD32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4105) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4106) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4107) + return OPCODE_AE_ADD64; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4108) + return OPCODE_AE_ADD64S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4109) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4110) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4111) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4112) + return OPCODE_AE_ADDSUB32S_HL_LH; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4113) + return OPCODE_AE_ADDSUB32_HL_LH; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4114) + return OPCODE_AE_MAX16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4115) + return OPCODE_AE_MAX32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4116) + return OPCODE_AE_MAX8; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4117) + return OPCODE_AE_MIN16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4118) + return OPCODE_AE_MIN32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4119) + return OPCODE_AE_MIN8; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4120) + return OPCODE_AE_MINMAX16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4121) + return OPCODE_AE_MINMAX32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4122) + return OPCODE_AE_MOVNEG32S_T; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4123) + return OPCODE_AE_ROUND16X4F32SASYM; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4124) + return OPCODE_AE_ROUND16X4F32SSYM; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4125) + return OPCODE_AE_ROUND32X2F64SASYM; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4126) + return OPCODE_AE_ROUND32X2F64SSYM; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4127) + return OPCODE_AE_SUB16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4128) + return OPCODE_AE_SUB16S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4129) + return OPCODE_AE_SUB24S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4130) + return OPCODE_AE_SUB32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4131) + return OPCODE_AE_SUB32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4132) + return OPCODE_AE_SUB64; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4133) + return OPCODE_AE_SUB64S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4134) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4135) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4136) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4137) + return OPCODE_ADD_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4138) + return OPCODE_DIVN_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4139) + return OPCODE_MADDN_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4140) + return OPCODE_MADD_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4141) + return OPCODE_MSUB_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4142) + return OPCODE_MUL_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4143) + return OPCODE_SUB_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5131 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5163 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SAT48S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5195 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5208 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5209 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG16S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5210 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG24S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5211 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5212 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5213 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG32_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5214 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG64; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5215 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG64S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5227 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ADDEXP_S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5233 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5234 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5235 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS64; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5237 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS16S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5238 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS64S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5239 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5241 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS24S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5242 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5243 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5245 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5246 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_DIV64D32_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5247 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5259 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MKDADJ_S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5291 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADD16X4; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5323 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADD8X8_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5355 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADD8X8_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5387 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADDA16X4; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5419 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADDA8X8_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5451 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADDA8X8_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5483 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RMAX16X4; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5515 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RMAX8X8; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5547 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RMIN16X4; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5579 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RMIN8X8; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5611 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ABS_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5643 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_CLSFY_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5675 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_NEG_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5707 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MKDADJ_H; + if (Field_fld_ae_slot2_28_17_Slot_ae_slot2_get (insn) == 1300 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ADD72X64; + if (Field_fld_ae_slot2_28_17_Slot_ae_slot2_get (insn) == 1301 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SUB72X64; + if (Field_fld_ae_slot2_28_17_Slot_ae_slot2_get (insn) == 1316 && + Field_fld_ae_slot2_14_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SEXT72; + if (Field_fld_ae_slot2_28_19_Slot_ae_slot2_get (insn) == 321 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ADD72; + if (Field_fld_ae_slot2_28_19_Slot_ae_slot2_get (insn) == 323 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SUB72; + if (Field_fld_ae_slot2_28_19_Slot_ae_slot2_get (insn) == 327 && + Field_fld_ae_slot2_16_15_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SAT64S; + if (Field_fld_ae_slot2_28_19_Slot_ae_slot2_get (insn) == 342 && + Field_fld_ae_slot2_14_0_Slot_ae_slot2_get (insn) == 1062) + return OPCODE_AE_MOVEEP; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 64) + return OPCODE_AE_MUL16X4; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 65) + return OPCODE_AE_MUL16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 66) + return OPCODE_AE_MULA16X4; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 67) + return OPCODE_AE_MULA16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 68) + return OPCODE_AE_MULAFC32RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 69) + return OPCODE_AE_MULAFC32X16W_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 70) + return OPCODE_AE_MULAFC32X16W_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 71) + return OPCODE_AE_MULAFP32X2S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 72) + return OPCODE_AE_MULAFP32X2S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 73) + return OPCODE_AE_MULFC32RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 74) + return OPCODE_AE_MULFC32X16W_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 75) + return OPCODE_AE_MULFC32X16W_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 76) + return OPCODE_AE_MULFP32X2S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 77) + return OPCODE_AE_MULFP32X2S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 78) + return OPCODE_AE_MULS16X4; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 79) + return OPCODE_AE_MULS16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 80) + return OPCODE_AE_MULSFP32X2S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 81) + return OPCODE_AE_MULSFP32X2S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 82) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 83) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 84) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 85) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 86) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 87) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 88) + return OPCODE_MADDA_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 89) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 90) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 91) + return OPCODE_AE_SEL8X8I; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 2) + return OPCODE_AE_MUL32EP_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 5) + return OPCODE_AE_MULA32EP_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 3) + return OPCODE_AE_MUL32USEP_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 6) + return OPCODE_AE_MULA32USEP_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 4) + return OPCODE_AE_MUL32USEP_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 7) + return OPCODE_AE_MULA32USEP_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_8_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 7) + return OPCODE_AE_SEL16I_N; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 2) + return OPCODE_AE_MULS32EP_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 4) + return OPCODE_AE_MULZAAD32EP_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 6) + return OPCODE_AE_MULZSSD32EP_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_MULAAD32EP_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 3) + return OPCODE_AE_MULSSD32EP_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 1) + return OPCODE_AE_MULAAD32USEP_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 5) + return OPCODE_AE_MULZAAD32USEP_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 8) + return OPCODE_AE_MUL32U_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULA32U_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 2) + return OPCODE_AE_MUL16S_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULA16S_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 10) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 3) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 4) + return OPCODE_AE_MUL32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULA32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 7) + return OPCODE_AE_MUL32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULA32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 5) + return OPCODE_AE_MUL32S_HL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULA32S_HL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 6) + return OPCODE_AE_MUL32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULA32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_6_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MULMUX_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULAC16JS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULAC16JS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 5) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 4) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 3) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 1) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 2) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 8) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_MULAAD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 10) + return OPCODE_AE_MULAAD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 6) + return OPCODE_AE_MULAA2D16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 7) + return OPCODE_AE_MULAA2D16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULAAFD16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULAAFD16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULSAD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULSAD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULSAD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULSAD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC16S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULSF32RA_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32RA_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32RA_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULSF16SS_33; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULSF16SS_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULSF16SS_32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULSF16SS_21; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULSF16SS_31; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULSF16SS_30; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULSF16SS_10; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULSF16SS_20; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULSF16SS_11; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC16S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAFC16RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAFCJ32RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAFCJ16RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULSFP32X2TS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULSP32X2T; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULSP16S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULSP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULSP16X16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC32X16_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULSSD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULSSD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULSS2D16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULSS2D16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULSSFD16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULSSFD16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAFP32X2TS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC32X16_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULZAAD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULZAAD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAP16S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULZAA2D16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULZAA2D16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULZASD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULZASD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULACJ32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAP16X16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULZAAFD16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULZAAFD16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULZSAD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULZSAD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAP32X2T; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULZSAD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULZSAD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_10; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULZSSD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULASD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULZSSD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULASD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULZSS2D16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULZSS2D16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULZSSFD16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULZSSFD16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_11; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_MUL_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_MADD_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_MSUB_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_MSUBN_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_MADDN_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_DIVN_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_MIN_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_MAX_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_MINNUM_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_MAXNUM_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 106 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_20; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 106 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 106 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 106 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 106 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 107 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULC16JS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 107 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULC16JS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 107 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_21; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 107 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 107 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 108 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 108 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULC32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 108 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULC16S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 108 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULC16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 108 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULC16S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 109 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 109 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_30; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 109 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULC32X16_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 109 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULC32X16_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 109 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULCJ32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 110 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF16SS_21; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 110 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF16SS_10; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 110 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF16SS_20; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 110 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF16SS_11; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 110 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_31; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 111 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF16SS_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 111 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF16SS_32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 111 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF16SS_31; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 111 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF16SS_30; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 111 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 112 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF32RA_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 112 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF32RA_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 112 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF32RA_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 112 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF16SS_33; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 112 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_33; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 113 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 113 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 113 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 113 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 113 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32RA_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 114 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 114 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 114 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32RA_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 114 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 114 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 115 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32RA_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 115 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 115 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 115 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 115 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 116 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 116 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 116 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 116 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 116 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 117 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 117 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 117 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 117 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 117 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFC16RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 118 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 118 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULFP16X4RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 118 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 118 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULFCJ32RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 118 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULFCJ16RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 119 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 119 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 119 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 119 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULFP16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 119 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFP16X4RS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 120 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 120 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 120 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 120 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 120 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 121 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 121 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 121 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 121 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 121 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 122 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 122 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFP32X2TS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 122 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULP16S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 122 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 122 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULP16X16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 123 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 123 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 123 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 123 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 123 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULP32X2T; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 124 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 124 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULS16S_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 124 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 124 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 124 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 125 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 125 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 125 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 125 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULS32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 125 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULS32S_HL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 126 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULS32U_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 126 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 126 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 126 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULS32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 126 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULS32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 127 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 127 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 127 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 127 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 127 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 130 && + Field_fld_ae_slot2_14_10_Slot_ae_slot2_get (insn) == 1) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 130 && + Field_fld_ae_slot2_14_10_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 160 && + Field_fld_ae_slot2_9_2_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_PKSR16; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 161 && + Field_fld_ae_slot2_9_2_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_PKSR24; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 162 && + Field_fld_ae_slot2_9_2_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_PKSR32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 163 && + Field_fld_ae_slot2_9_2_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 164 && + Field_fld_ae_slot2_9_1_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 164 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_ABS_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 164 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_CONJC_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 165 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_MKSADJ_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 165 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_DIV0_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 165 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_CONJC_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 165 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_MULJC_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 166 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_NEXP01_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 166 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_RECIP0_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 166 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_NEG_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 166 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_MULJC_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 167 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_SQRT0_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 167 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_RSQRT0_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 167 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_ADDEXP_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 167 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 168 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 168 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 168 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_AE_MOV; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 168 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_DIV0_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 169 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_MKSADJ_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 169 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_NEXP0_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 169 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_NEXP01_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 169 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_RECIP0_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 170 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 170 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 170 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_RSQRT0_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 170 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_SQRT0_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 171 && + Field_fld_ae_slot2_14_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_AE_MOVZBVCDR; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 171 && + Field_fld_ae_slot2_14_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_AE_MOVDRZBVC; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 171 && + Field_fld_ae_slot2_14_14_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_CONST_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 171 && + Field_fld_ae_slot2_14_14_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_CONST_H; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 1) + return OPCODE_AE_DSEL8X8; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 8) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 10) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 9) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 1) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 7) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 3) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 5) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 6) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 2) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 4) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 7 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SORT16X4; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 9 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ADD_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 10 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_SUB_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 6 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MIN_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MAX_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 33) + return OPCODE_CLSFY_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MINNUM_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 2 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MAXNUM_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 8 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_FREXP_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 1 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 33) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 4 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 1 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_14_14_Slot_ae_slot2_get (insn) == 1 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 32) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_14_14_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 32) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae_slot2_28_4_Slot_ae_slot2_get (insn) == 11206722 && + Field_fld_ae_slot2_3_0_Slot_ae_slot2_get (insn) == 7) + return OPCODE_NOP; + if (Field_fld_ae_slot2_28_5_Slot_ae_slot2_get (insn) == 5394432) + return OPCODE_AE_MOVFCRFSRV; + if (Field_fld_ae_slot2_28_5_Slot_ae_slot2_get (insn) == 5395456) + return OPCODE_AE_MOVVFCRFSR; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot3_36_12_Slot_ae_slot3_get (insn) == 15205414 && + Field_fld_ae_slot3_11_0_Slot_ae_slot3_get (insn) == 2146) + return OPCODE_NOP; + if (Field_fld_ae_slot3_36_16_Slot_ae_slot3_get (insn) == 934928 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot3_36_19_Slot_ae_slot3_get (insn) == 116864 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae_slot3_36_19_Slot_ae_slot3_get (insn) == 116868 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_CONST_H; + if (Field_fld_ae_slot3_36_19_Slot_ae_slot3_get (insn) == 116870 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_CONST_S; + if (Field_fld_ae_slot3_36_19_Slot_ae_slot3_get (insn) == 116928 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57632) + return OPCODE_AE_MUL16X4; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57633) + return OPCODE_AE_MUL16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57634) + return OPCODE_AE_MUL2C16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57635) + return OPCODE_AE_MUL32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57636) + return OPCODE_AE_MUL32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57637) + return OPCODE_AE_MULA16X4; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57638) + return OPCODE_AE_MULA16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57639) + return OPCODE_AE_MULA2C16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57640) + return OPCODE_AE_MULA32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57641) + return OPCODE_AE_MULA32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57642) + return OPCODE_AE_MULAA32X2_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57643) + return OPCODE_AE_MULAAAA2Q8; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57644) + return OPCODE_AE_MULAC16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57645) + return OPCODE_AE_MULAC16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57646) + return OPCODE_AE_MULAC32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57647) + return OPCODE_AE_MULAC32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57648) + return OPCODE_AE_MULAC32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57649) + return OPCODE_AE_MULACJ32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57650) + return OPCODE_AE_MULADDF32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57651) + return OPCODE_AE_MULADDF32RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57652) + return OPCODE_AE_MULAF16X4SS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57653) + return OPCODE_AE_MULAF32X2RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57654) + return OPCODE_AE_MULAF32X2RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57655) + return OPCODE_AE_MULAF32X2R_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57656) + return OPCODE_AE_MULAF32X2R_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57657) + return OPCODE_AE_MULAFC16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57658) + return OPCODE_AE_MULAFC32RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57659) + return OPCODE_AE_MULAFC32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57660) + return OPCODE_AE_MULAFC32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57661) + return OPCODE_AE_MULAFC32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57662) + return OPCODE_AE_MULAFCJ16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57663) + return OPCODE_AE_MULAFCJ32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57664) + return OPCODE_AE_MULAFCJ32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57665) + return OPCODE_AE_MULAFCJ32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57666) + return OPCODE_AE_MULAFP32X16_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57667) + return OPCODE_AE_MULAFP32X16_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57668) + return OPCODE_AE_MULC32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57669) + return OPCODE_AE_MULC32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57670) + return OPCODE_AE_MULC32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57671) + return OPCODE_AE_MULCJ32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57672) + return OPCODE_AE_MULF32X2R_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57673) + return OPCODE_AE_MULFC16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57674) + return OPCODE_AE_MULFC32RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57675) + return OPCODE_AE_MULFC32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57676) + return OPCODE_AE_MULFCJ32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57677) + return OPCODE_AE_MULFCJ32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57678) + return OPCODE_AE_MULFP32X16_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57679) + return OPCODE_AE_MULFP32X16_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57680) + return OPCODE_AE_MULS32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57681) + return OPCODE_AE_MULS32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57682) + return OPCODE_AE_MULSF16X4SS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57683) + return OPCODE_AE_MULSF32X2RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57684) + return OPCODE_AE_MULSFP32X16_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57685) + return OPCODE_AE_MULSFP32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57686) + return OPCODE_AE_MULSFP32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57687) + return OPCODE_AE_MULSS32X2_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57688) + return OPCODE_AE_MULZSS32X2_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULAC16JS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULAC16JS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULAAD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULAAD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULAA2D16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULAA2D16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULAAFD16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULAAFD16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULC16JS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULF32RA_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULF16SS_33; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULF16SS_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULF16SS_31; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULF16SS_10; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULF16SS_20; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULC16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULFC16RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULFCJ32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULCJ32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULC16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULC16JS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULF32RA_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULF32RA_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULF16SS_32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULF16SS_21; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULF16SS_30; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULF16SS_11; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULC32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULC16S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULFCJ16RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULFP16X4RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSS2D16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57693 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57693 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57693 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57693 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57693 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57694 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57694 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57694 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57694 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57694 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57695 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57695 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57695 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57695 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57695 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZSAD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57696) + return OPCODE_AE_MULAFP32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57697) + return OPCODE_AE_MULAFP32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57698) + return OPCODE_AE_MULC16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57699) + return OPCODE_AE_MULC16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57700) + return OPCODE_AE_MULF16X4SS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57701) + return OPCODE_AE_MULF32X2RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57702) + return OPCODE_AE_MULF32X2RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57703) + return OPCODE_AE_MULF32X2R_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57704) + return OPCODE_AE_MULFC32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57705) + return OPCODE_AE_MULFC32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57706) + return OPCODE_AE_MULFCJ16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57707) + return OPCODE_AE_MULFCJ32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57708) + return OPCODE_AE_MULFP32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57709) + return OPCODE_AE_MULFP32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57710) + return OPCODE_AE_MULS16X4; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57711) + return OPCODE_AE_MULS16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57712) + return OPCODE_AE_MULSF32X2RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57713) + return OPCODE_AE_MULSF32X2R_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57714) + return OPCODE_AE_MULSF32X2R_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57715) + return OPCODE_AE_MULSFP32X16_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57716) + return OPCODE_AE_MULSUBF32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57717) + return OPCODE_AE_MULSUBF32RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57718) + return OPCODE_AE_MULZAA32X2_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57719) + return OPCODE_AE_MULZAAAA2Q8; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULSF32RA_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULSF16SS_31; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULSF16SS_20; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULS32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULSAD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULP16S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULSP16S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULSS2D16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULZAAFD16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULSF32RA_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULSF16SS_32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULSF16SS_21; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULS16S_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULS32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULZAAD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULSSD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULSAD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULSP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULSS2D16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULZAAFD16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULSF16SS_33; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULSF16SS_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULSF16SS_10; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULSAD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULS32S_HL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULZAAD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULSSD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULP32X2S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULP16X16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULSP16X16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULZAA2D16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULSSFD16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULSF32RA_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULSF16SS_30; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULSF16SS_11; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULSAD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULS32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULZAA2D16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULSSFD16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57725 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57725 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57725 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57725 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57725 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57726 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57726 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57726 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57726 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57726 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57727 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57727 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57727 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57727 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZSAD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57727 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSS2D16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59532 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59533 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59534 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32S_HL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59535 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59536 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAC16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59537 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULACJ32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59538 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_20; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59539 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_31; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59540 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32RA_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59541 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59542 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59543 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59544 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59545 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59546 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFCJ32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59547 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59548 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59549 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59550 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59551 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59560 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL16S_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59561 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59562 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59563 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32S_HL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59564 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59565 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA16S_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59566 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59567 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59568 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAC16S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59569 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59570 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_21; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59571 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59572 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32RA_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59573 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59574 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59575 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59576 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59577 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59578 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59579 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59580 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59581 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP16X16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59582 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59583 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59592 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59593 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59594 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59595 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59596 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59597 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59598 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59599 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59600 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAC16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59601 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_10; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59602 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59603 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_33; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59604 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59605 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59606 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59607 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59608 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFC16RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59609 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59610 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59611 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59612 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59613 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59614 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59615 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULASD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59624 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59625 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59626 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59627 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59628 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59629 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59630 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59631 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59632 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAC32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59633 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_11; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59634 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_30; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59635 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32RA_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59636 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59637 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59638 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59639 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59640 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59641 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFCJ16RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59642 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59643 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59644 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP16S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59645 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59646 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59647 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULASD32S_HL_LH; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14849 && + Field_fld_ae_slot3_19_17_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26722) + return OPCODE_AE_MOVEEP; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14880 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32EP_HH; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14881 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULS32EP_HH; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14882 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSSD32EP_HH_LL; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14888 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32EP_HH; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14889 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULSSD32EP_HH_LL; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14896 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAAD32EP_HH_LL; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14897 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZAAD32EP_HH_LL; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14904 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAAD32USEP_HL_LH; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14905 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZAAD32USEP_HL_LH; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1760) + return OPCODE_AE_MULAAAA2Q16X8; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1761) + return OPCODE_AE_MULAF2P32X16X4RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1762) + return OPCODE_AE_MULAF2P32X16X4RS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1763) + return OPCODE_AE_MULAF2P32X16X4S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1764) + return OPCODE_AE_MULAFD32X16X2_FIR_HH; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1765) + return OPCODE_AE_MULAFD32X16X2_FIR_HL; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1766) + return OPCODE_AE_MULAFD32X16X2_FIR_LH; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1767) + return OPCODE_AE_MULAFD32X16X2_FIR_LL; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1768) + return OPCODE_AE_MULAFD32X2RA_FIR_H; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1769) + return OPCODE_AE_MULAFD32X2RA_FIR_L; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1770) + return OPCODE_AE_MULAFD32X2S_FIR_H; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1771) + return OPCODE_AE_MULAFD32X2S_FIR_L; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1772) + return OPCODE_AE_MULAFPC32X16X2RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1773) + return OPCODE_AE_MULAFPCJ32X16X2RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1774) + return OPCODE_AE_MULAFQ16X2_FIR_0; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1775) + return OPCODE_AE_MULAFQ16X2_FIR_1; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1776) + return OPCODE_AE_MULAFQ16X2_FIR_2; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1777) + return OPCODE_AE_MULAFQ16X2_FIR_3; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1778) + return OPCODE_AE_MULAPC32X16X2; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1779) + return OPCODE_AE_MULF2P32X16X4RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1780) + return OPCODE_AE_MULF2P32X16X4RS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1781) + return OPCODE_AE_MULF2P32X16X4S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1782) + return OPCODE_AE_MULFD32X16X2_FIR_HH; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1783) + return OPCODE_AE_MULFD32X16X2_FIR_HL; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1784) + return OPCODE_AE_MULFD32X16X2_FIR_LH; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1785) + return OPCODE_AE_MULFD32X16X2_FIR_LL; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1786) + return OPCODE_AE_MULFD32X2RA_FIR_H; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1787) + return OPCODE_AE_MULFD32X2RA_FIR_L; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1788) + return OPCODE_AE_MULFD32X2S_FIR_H; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1789) + return OPCODE_AE_MULFD32X2S_FIR_L; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1790) + return OPCODE_AE_MULFPC32X16X2RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1791) + return OPCODE_AE_MULFPCJ32X16X2RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1792) + return OPCODE_AE_MULFQ16X2_FIR_0; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1793) + return OPCODE_AE_MULFQ16X2_FIR_1; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1794) + return OPCODE_AE_MULFQ16X2_FIR_2; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1795) + return OPCODE_AE_MULFQ16X2_FIR_3; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1796) + return OPCODE_AE_MULPC32X16X2; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1797) + return OPCODE_AE_MULSF2P32X16X4RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1798) + return OPCODE_AE_MULSF2P32X16X4RS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1799) + return OPCODE_AE_MULSF2P32X16X4S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1800) + return OPCODE_AE_MULZAAAA2Q16X8; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 433250) + return OPCODE_AE_RNG32X2; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 24 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 29 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 26 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 30 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 31 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI32R; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 25 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI24S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 27 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI32S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLI64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (insn) == 13 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (insn) == 9 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAISQ56S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (insn) == 5 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI64S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_13_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI72; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 28 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI72; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLI24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 515 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 899 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLS24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 771 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAS24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_19_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI16; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_19_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI16R; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLI32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 579 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 931 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLS32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 803 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAS32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_19_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI16S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 547 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 611 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS32S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 707 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLASQ56; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 995 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLSQ56; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 867 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRASQ56; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 643 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 963 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLS64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 835 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAS64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 739 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLASSQ56S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 675 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS64S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1856 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAAAAFQ32X16; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1856 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 99) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1857 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAAAAQ32X16; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1857 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 99) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1858 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZAAAAFQ32X16; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1859 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZAAAAQ32X16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MUL2P32X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MUL2P32X4S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL2P32X4T; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MUL2Q32X16_FIR_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MUL2Q32X16_FIR_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULA2P32X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULA2P32X4T; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULA2Q32X16_FIR_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULA2Q32X16_FIR_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULAAAA2Q16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULAAAA2Q32X16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULAAF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULAAF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULAAF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULAAF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULAF2P32X4RAS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULAF2P32X4RS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULASF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULASF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULASF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULASF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULF2D32X2WS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULF2P32X4RAS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULF2P32X4RS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULFD16X16X4WS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULS2P32X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULS2P32X4T; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULSAF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULSAF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULSAF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULSAF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULSF2P32X4RAS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 32) + return OPCODE_AE_MULSF2P32X4RS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 33) + return OPCODE_AE_MULSSF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 34) + return OPCODE_AE_MULSSF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 35) + return OPCODE_AE_MULSSF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 36) + return OPCODE_AE_MULSSF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 37) + return OPCODE_AE_MULZAAAA2Q16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 38) + return OPCODE_AE_MULZAAAA2Q32X16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 39) + return OPCODE_AE_MULZAAF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 40) + return OPCODE_AE_MULZAAF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 41) + return OPCODE_AE_MULZAAF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 42) + return OPCODE_AE_MULZAAF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 43) + return OPCODE_AE_MULZASF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 44) + return OPCODE_AE_MULZASF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 45) + return OPCODE_AE_MULZASF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 46) + return OPCODE_AE_MULZASF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 47) + return OPCODE_AE_MULZSAF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 48) + return OPCODE_AE_MULZSAF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 49) + return OPCODE_AE_MULZSAF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 50) + return OPCODE_AE_MULZSAF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 51) + return OPCODE_AE_MULZSSF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 52) + return OPCODE_AE_MULZSSF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 53) + return OPCODE_AE_MULZSSF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 54) + return OPCODE_AE_MULZSSF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_19_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SEL16I; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1860 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SHORTSWAP; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1572 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1540 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1828 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1796 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 611 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_TRUNCP24Q48X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1892 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_TRUNCP16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1764 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MOV; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1732 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1700 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1668 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1636 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1604 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1924 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_TRUNCQ32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 515 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_AND; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 547 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_NAND; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 579 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_OR; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 643 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_XOR; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 431202) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 432226) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_19_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 4 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SEXT32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_DSEL8X8; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 13 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 34) + return OPCODE_ADD_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 13 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 66) + return OPCODE_SUB_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3588 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_NEXP01_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2564 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MKSADJ_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 428130) + return OPCODE_MKDADJ_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1988 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_DIV0_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2628 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_SQRT0_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2596 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_RECIP0_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3620 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_RSQRT0_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 427106) + return OPCODE_ADDEXP_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 426082) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 867 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MIN_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 771 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MAX_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3652 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ABS_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2724 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_NEG_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3684 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CONJC_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3716 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MULJC_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1956 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CLSFY_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 835 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MINNUM_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 739 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MAXNUM_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 9 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 12 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 13 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 675 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_FREXP_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2020 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 803 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 707 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_18_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_BMAXNUM_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_18_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_BMINNUM_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_18_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_BMAXNUMABS_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_18_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_BMINNUMABS_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 8 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3748 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ABS_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 430178) + return OPCODE_ADDEXP_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 429154) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2756 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CLSFY_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2660 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CONJC_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 995 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MIN_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 931 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MAX_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 963 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MINNUM_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 899 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MAXNUM_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2692 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MULJC_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3780 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_NEG_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 4 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 7 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 5 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 6 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 648290) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 38) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 37) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 39) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 40) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 41) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 30816) + return OPCODE_AE_ADDRNG32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 17506) + return OPCODE_AE_SUBRNG32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 31841) + return OPCODE_AE_SAT16X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 24673) + return OPCODE_AE_ROUND32X2F64SSYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 23649) + return OPCODE_AE_ROUND32X2F64SASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 22625) + return OPCODE_AE_ROUND32X2F48SSYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 21601) + return OPCODE_AE_ROUND32X2F48SASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 18529) + return OPCODE_AE_ROUND16X4F32SSYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 17505) + return OPCODE_AE_ROUND16X4F32SASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 20577) + return OPCODE_AE_ROUND24X2F48SSYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 19553) + return OPCODE_AE_ROUND24X2F48SASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 30817) + return OPCODE_AE_ROUNDSP16Q48X2SYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 29793) + return OPCODE_AE_ROUNDSP16Q48X2ASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 12385) + return OPCODE_AE_MINABS32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 7265) + return OPCODE_AE_MAXABS32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26722) + return OPCODE_AE_ROUNDSP16F24SYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26722) + return OPCODE_AE_ROUNDSP16F24ASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 1008738) + return OPCODE_AE_SAT48S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 1041506) + return OPCODE_AE_SATQ56S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 975970) + return OPCODE_AE_SAT24S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 13409) + return OPCODE_AE_MINABS64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 8289) + return OPCODE_AE_MAXABS64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26722) + return OPCODE_AE_ROUNDSQ32F48SYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26722) + return OPCODE_AE_ROUNDSQ32F48ASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 23648) + return OPCODE_AE_ADD32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 10338) + return OPCODE_AE_SUB32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 97) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 15458) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 20576) + return OPCODE_AE_ADD16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 7266) + return OPCODE_AE_SUB16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26720) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 3169) + return OPCODE_AE_ADDSUB32_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 746594) + return OPCODE_AE_NEG32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 255074) + return OPCODE_AE_ABS32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 812130) + return OPCODE_AE_NEG32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 22624) + return OPCODE_AE_ADD24S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 9314) + return OPCODE_AE_SUB24S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 24672) + return OPCODE_AE_ADD32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 11362) + return OPCODE_AE_SUB32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 1121) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 16482) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 21600) + return OPCODE_AE_ADD16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 8290) + return OPCODE_AE_SUB16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 25696) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 2145) + return OPCODE_AE_ADDSUB32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 713826) + return OPCODE_AE_NEG24S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 222306) + return OPCODE_AE_ABS24S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 779362) + return OPCODE_AE_NEG32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 287842) + return OPCODE_AE_ABS32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 681058) + return OPCODE_AE_NEG16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 189538) + return OPCODE_AE_ABS16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 156770) + return OPCODE_AE_ABS16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 10337) + return OPCODE_AE_MIN32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 5217) + return OPCODE_AE_MAX32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 15457) + return OPCODE_AE_MINMAX32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 14433) + return OPCODE_AE_MINMAX16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 9313) + return OPCODE_AE_MIN16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 4193) + return OPCODE_AE_MAX16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 27744) + return OPCODE_AE_ADD64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 12386) + return OPCODE_AE_SUB64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 844898) + return OPCODE_AE_NEG64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 320610) + return OPCODE_AE_ABS64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 31840) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 18530) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 28768) + return OPCODE_AE_ADD64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 13410) + return OPCODE_AE_SUB64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 943202) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 418914) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 877666) + return OPCODE_AE_NEG64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 353378) + return OPCODE_AE_ABS64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 6241) + return OPCODE_AE_MAX64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 11361) + return OPCODE_AE_MIN64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 615522) + return OPCODE_AE_MUL16JS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 517218) + return OPCODE_AE_CONJ16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 549986) + return OPCODE_AE_DIV64D32_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 582754) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_17_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 25698) + return OPCODE_AE_SAT64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 386146) + return OPCODE_AE_ABS8S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 910434) + return OPCODE_AE_NEG8S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 29792) + return OPCODE_AE_ADD8S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 14434) + return OPCODE_AE_SUB8S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 3170) + return OPCODE_AE_SATU16X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 98) + return OPCODE_AE_SAT32X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 4194) + return OPCODE_AE_SATU32X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 2146) + return OPCODE_AE_SAT8X8X16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 6242) + return OPCODE_AE_SATU8X8X16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 1122) + return OPCODE_AE_SAT8X4X32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 5218) + return OPCODE_AE_SATU8X4X32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 28769) + return OPCODE_AE_ROUND8X8F16SSYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 27745) + return OPCODE_AE_ROUND8X8F16SASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26721) + return OPCODE_AE_ROUND8X4F32SSYM_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 25697) + return OPCODE_AE_ROUND8X4F32SASYM_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 36) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 46) + return OPCODE_AE_ADDW8; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 44) + return OPCODE_AE_ADDW16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 45) + return OPCODE_AE_ADDW32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 50) + return OPCODE_AE_SUBW8; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 48) + return OPCODE_AE_SUBW16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 49) + return OPCODE_AE_SUBW32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 34) + return OPCODE_AE_ACCW8; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 32) + return OPCODE_AE_ACCW16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 33) + return OPCODE_AE_ACCW32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 47) + return OPCODE_AE_ADDW8U; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 51) + return OPCODE_AE_SUBW8U; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 35) + return OPCODE_AE_ACCW8U; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULFD16X16X4RAS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 54) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 53) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 55) + return OPCODE_AE_SEL8X8I; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_12_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 96) + return OPCODE_AE_BMAX8X8_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_12_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 96) + return OPCODE_AE_BMAX8X8_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_12_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 96) + return OPCODE_AE_BMIN8X8_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_12_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 96) + return OPCODE_AE_BMIN8X8_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 451682) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 484450) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 16481) + return OPCODE_AE_MOVNEG32S_T; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 16480) + return OPCODE_AE_EXPADD16_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 18528) + return OPCODE_AE_EXPSUB16_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 17504) + return OPCODE_AE_EXPADD16_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 19552) + return OPCODE_AE_EXPSUB16_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 42) + return OPCODE_AE_ADDCEXP32_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 43) + return OPCODE_AE_ADDCEXP32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 63) + return OPCODE_MUL_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 60) + return OPCODE_MADD_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 62) + return OPCODE_MSUB_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 61) + return OPCODE_MSUBN_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 59) + return OPCODE_MADDN_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 58) + return OPCODE_DIVN_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_1_Slot_ae_slot3_get (insn) == 28) + return OPCODE_MULMUX_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_9_3_Slot_ae_slot3_get (insn) == 7) + return OPCODE_MADDMUX_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 52) + return OPCODE_MADDA_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 19554) + return OPCODE_ADD_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 24674) + return OPCODE_SUB_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 23650) + return OPCODE_MUL_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 20578) + return OPCODE_MADD_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 22626) + return OPCODE_MSUB_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 21602) + return OPCODE_MSUBN_H; + return XTENSA_UNDEFINED; +} + + +/* Instruction slots. */ + +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = (insn[0] & 0xffffff); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_ae_format_Format_ae_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x300) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xc) | (((insn[0] & 0x18000000) >> 27) << 2); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf0) >> 4) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf000) >> 12) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | ((insn[1] & 0x1) << 12); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[0] & 0xc00) >> 10) << 13); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[1] & 0x6) >> 1) << 15); + slotbuf[0] = (slotbuf[0] & ~0x20000) | (((insn[2] & 0x1000000) >> 24) << 17); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x10000) >> 16) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[1] & 0x800000) >> 23) << 19); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[0] & 0x4000000) >> 26) << 20); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[1] & 0x1000000) >> 24) << 21); + slotbuf[0] = (slotbuf[0] & ~0xc00000) | (((insn[2] & 0x6000000) >> 25) << 22); + slotbuf[0] = (slotbuf[0] & ~0x7000000) | (((insn[2] & 0xe00000) >> 21) << 24); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x2000) >> 13) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x10000000) >> 28) << 28); +} + +static void +Slot_ae_format_Format_ae_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x300) | ((slotbuf[0] & 0x3) << 8); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0xc) >> 2) << 27); + insn[0] = (insn[0] & ~0xf0) | (((slotbuf[0] & 0xf0) >> 4) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0xf00) >> 8) << 12); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x1000) >> 12); + insn[0] = (insn[0] & ~0xc00) | (((slotbuf[0] & 0x6000) >> 13) << 10); + insn[1] = (insn[1] & ~0x6) | (((slotbuf[0] & 0x18000) >> 15) << 1); + insn[2] = (insn[2] & ~0x1000000) | (((slotbuf[0] & 0x20000) >> 17) << 24); + insn[2] = (insn[2] & ~0x10000) | (((slotbuf[0] & 0x40000) >> 18) << 16); + insn[1] = (insn[1] & ~0x800000) | (((slotbuf[0] & 0x80000) >> 19) << 23); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x100000) >> 20) << 26); + insn[1] = (insn[1] & ~0x1000000) | (((slotbuf[0] & 0x200000) >> 21) << 24); + insn[2] = (insn[2] & ~0x6000000) | (((slotbuf[0] & 0xc00000) >> 22) << 25); + insn[2] = (insn[2] & ~0xe00000) | (((slotbuf[0] & 0x7000000) >> 24) << 21); + insn[3] = (insn[3] & ~0x2000) | (((slotbuf[0] & 0x8000000) >> 27) << 13); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[0] & 0x10000000) >> 28) << 28); +} + +static void +Slot_ae_format_Format_ae_slot1_72_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[2] & 0xf8000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[2] & 0x60000) >> 17) << 18); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[3] & 0x7c000) >> 14) << 20); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x20000000) >> 29) << 25); +} + +static void +Slot_ae_format_Format_ae_slot1_72_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x1f00) >> 8) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[2] = (insn[2] & ~0x60000) | (((slotbuf[0] & 0xc0000) >> 18) << 17); + insn[3] = (insn[3] & ~0x7c000) | (((slotbuf[0] & 0x1f00000) >> 20) << 14); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x2000000) >> 25) << 29); +} + +static void +Slot_ae_format_Format_ae_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x1ff8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0xffc00) | (((insn[0] & 0x3ff0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[3] & 0x3e0) >> 5) << 20); + slotbuf[0] = (slotbuf[0] & ~0xe000000) | (((insn[3] & 0x380000) >> 19) << 25); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x40000000) >> 30) << 28); +} + +static void +Slot_ae_format_Format_ae_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x1ff8) | ((slotbuf[0] & 0x3ff) << 3); + insn[0] = (insn[0] & ~0x3ff0000) | (((slotbuf[0] & 0xffc00) >> 10) << 16); + insn[3] = (insn[3] & ~0x3e0) | (((slotbuf[0] & 0x1f00000) >> 20) << 5); + insn[3] = (insn[3] & ~0x380000) | (((slotbuf[0] & 0xe000000) >> 25) << 19); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x10000000) >> 28) << 30); +} + +static void +Slot_ae_format_Format_ae_slot3_45_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xfe000000) >> 25); + slotbuf[0] = (slotbuf[0] & ~0x7f80) | ((insn[2] & 0xff) << 7); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x180000) >> 19) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[3] & 0x1c00) >> 10) << 17); + slotbuf[0] = (slotbuf[0] & ~0x3ff00000) | (((insn[1] & 0x7fe000) >> 13) << 20); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0xc00000) >> 22) << 30); + slotbuf[1] = ((insn[3] & 0xf000000) >> 24); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x80000000) >> 31) << 4); +} + +static void +Slot_ae_format_Format_ae_slot3_45_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xfe000000) | ((slotbuf[0] & 0x7f) << 25); + insn[2] = (insn[2] & ~0xff) | ((slotbuf[0] & 0x7f80) >> 7); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x18000) >> 15) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0xe0000) >> 17) << 10); + insn[1] = (insn[1] & ~0x7fe000) | (((slotbuf[0] & 0x3ff00000) >> 20) << 13); + insn[3] = (insn[3] & ~0xc00000) | (((slotbuf[0] & 0xc0000000) >> 30) << 22); + insn[3] = (insn[3] & ~0xf000000) | ((slotbuf[1] & 0xf) << 24); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x10) >> 4) << 31); +} + +static void +Slot_ae_format_2_Format_ae2_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xff0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[0] & 0x18000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1c00) | ((insn[1] & 0x7) << 10); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x1000000) >> 24) << 13); + slotbuf[0] = (slotbuf[0] & ~0x1c000) | (((insn[0] & 0xe000) >> 13) << 14); + slotbuf[0] = (slotbuf[0] & ~0x20000) | (((insn[0] & 0x4000000) >> 26) << 17); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x800000) >> 23) << 18); + slotbuf[0] = (slotbuf[0] & ~0x180000) | (((insn[2] & 0x30000) >> 16) << 19); + slotbuf[0] = (slotbuf[0] & ~0xe00000) | (((insn[2] & 0x7000000) >> 24) << 21); + slotbuf[0] = (slotbuf[0] & ~0x7000000) | (((insn[1] & 0xe00000) >> 21) << 24); + slotbuf[0] = (slotbuf[0] & ~0x18000000) | (((insn[1] & 0x6000000) >> 25) << 27); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[2] & 0x100) >> 8) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[2] & 0x200) >> 9) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[2] & 0x400) >> 10) << 31); + slotbuf[1] = ((insn[2] & 0x800) >> 11); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[2] & 0x1000) >> 12) << 1); + slotbuf[1] = (slotbuf[1] & ~0x4) | (((insn[2] & 0x2000) >> 13) << 2); + slotbuf[1] = (slotbuf[1] & ~0x8) | (((insn[2] & 0x4000) >> 14) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[2] & 0x8000) >> 15) << 4); + slotbuf[1] = (slotbuf[1] & ~0x20) | (((insn[2] & 0x40000) >> 18) << 5); + slotbuf[1] = (slotbuf[1] & ~0x40) | (((insn[2] & 0x80000) >> 19) << 6); + slotbuf[1] = (slotbuf[1] & ~0x80) | (((insn[2] & 0x100000) >> 20) << 7); + slotbuf[1] = (slotbuf[1] & ~0x100) | (((insn[2] & 0x200000) >> 21) << 8); +} + +static void +Slot_ae_format_2_Format_ae2_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff0) | ((slotbuf[0] & 0xff) << 4); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x300) >> 8) << 27); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x1c00) >> 10); + insn[1] = (insn[1] & ~0x1000000) | (((slotbuf[0] & 0x2000) >> 13) << 24); + insn[0] = (insn[0] & ~0xe000) | (((slotbuf[0] & 0x1c000) >> 14) << 13); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x20000) >> 17) << 26); + insn[2] = (insn[2] & ~0x800000) | (((slotbuf[0] & 0x40000) >> 18) << 23); + insn[2] = (insn[2] & ~0x30000) | (((slotbuf[0] & 0x180000) >> 19) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0xe00000) >> 21) << 24); + insn[1] = (insn[1] & ~0xe00000) | (((slotbuf[0] & 0x7000000) >> 24) << 21); + insn[1] = (insn[1] & ~0x6000000) | (((slotbuf[0] & 0x18000000) >> 27) << 25); + insn[2] = (insn[2] & ~0x100) | (((slotbuf[0] & 0x20000000) >> 29) << 8); + insn[2] = (insn[2] & ~0x200) | (((slotbuf[0] & 0x40000000) >> 30) << 9); + insn[2] = (insn[2] & ~0x400) | (((slotbuf[0] & 0x80000000) >> 31) << 10); + insn[2] = (insn[2] & ~0x800) | ((slotbuf[1] & 0x1) << 11); + insn[2] = (insn[2] & ~0x1000) | (((slotbuf[1] & 0x2) >> 1) << 12); + insn[2] = (insn[2] & ~0x2000) | (((slotbuf[1] & 0x4) >> 2) << 13); + insn[2] = (insn[2] & ~0x4000) | (((slotbuf[1] & 0x8) >> 3) << 14); + insn[2] = (insn[2] & ~0x8000) | (((slotbuf[1] & 0x10) >> 4) << 15); + insn[2] = (insn[2] & ~0x40000) | (((slotbuf[1] & 0x20) >> 5) << 18); + insn[2] = (insn[2] & ~0x80000) | (((slotbuf[1] & 0x40) >> 6) << 19); + insn[2] = (insn[2] & ~0x100000) | (((slotbuf[1] & 0x80) >> 7) << 20); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[1] & 0x100) >> 8) << 21); +} + +static void +Slot_ae_format_2_Format_ae2_slot1_12_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x40000000) >> 30); + slotbuf[0] = (slotbuf[0] & ~0x2) | (((insn[1] & 0x20000000) >> 29) << 1); + slotbuf[0] = (slotbuf[0] & ~0xc) | (((insn[2] & 0x18000000) >> 27) << 2); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[1] & 0x80000000) >> 31) << 4); + slotbuf[0] = (slotbuf[0] & ~0xe0) | ((insn[2] & 0x7) << 5); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[2] & 0x60000000) >> 29) << 8); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | ((insn[3] & 0x1f) << 10); + slotbuf[0] = (slotbuf[0] & ~0x8000) | (((insn[0] & 0x1000) >> 12) << 15); + slotbuf[0] = (slotbuf[0] & ~0x70000) | (((insn[1] & 0xe000) >> 13) << 16); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[2] & 0x80000000) >> 31) << 19); + slotbuf[0] = (slotbuf[0] & ~0x300000) | (((insn[1] & 0x18000000) >> 27) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1c00000) | (((insn[2] & 0x38) >> 3) << 22); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[2] & 0x400000) >> 22) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x400) >> 10) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x800) >> 11) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x1000) >> 12) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x2000) >> 13) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x4000) >> 14) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x8000) >> 15) << 31); + slotbuf[1] = ((insn[3] & 0x10000) >> 16); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[3] & 0x20000) >> 17) << 1); + slotbuf[1] = (slotbuf[1] & ~0x4) | (((insn[3] & 0x40000) >> 18) << 2); + slotbuf[1] = (slotbuf[1] & ~0x8) | (((insn[3] & 0x80000) >> 19) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x100000) >> 20) << 4); +} + +static void +Slot_ae_format_2_Format_ae2_slot1_12_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x40000000) | ((slotbuf[0] & 0x1) << 30); + insn[1] = (insn[1] & ~0x20000000) | (((slotbuf[0] & 0x2) >> 1) << 29); + insn[2] = (insn[2] & ~0x18000000) | (((slotbuf[0] & 0xc) >> 2) << 27); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x10) >> 4) << 31); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0xe0) >> 5); + insn[2] = (insn[2] & ~0x60000000) | (((slotbuf[0] & 0x300) >> 8) << 29); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x7c00) >> 10); + insn[0] = (insn[0] & ~0x1000) | (((slotbuf[0] & 0x8000) >> 15) << 12); + insn[1] = (insn[1] & ~0xe000) | (((slotbuf[0] & 0x70000) >> 16) << 13); + insn[2] = (insn[2] & ~0x80000000) | (((slotbuf[0] & 0x80000) >> 19) << 31); + insn[1] = (insn[1] & ~0x18000000) | (((slotbuf[0] & 0x300000) >> 20) << 27); + insn[2] = (insn[2] & ~0x38) | (((slotbuf[0] & 0x1c00000) >> 22) << 3); + insn[2] = (insn[2] & ~0x400000) | (((slotbuf[0] & 0x2000000) >> 25) << 22); + insn[3] = (insn[3] & ~0x400) | (((slotbuf[0] & 0x4000000) >> 26) << 10); + insn[3] = (insn[3] & ~0x800) | (((slotbuf[0] & 0x8000000) >> 27) << 11); + insn[3] = (insn[3] & ~0x1000) | (((slotbuf[0] & 0x10000000) >> 28) << 12); + insn[3] = (insn[3] & ~0x2000) | (((slotbuf[0] & 0x20000000) >> 29) << 13); + insn[3] = (insn[3] & ~0x4000) | (((slotbuf[0] & 0x40000000) >> 30) << 14); + insn[3] = (insn[3] & ~0x8000) | (((slotbuf[0] & 0x80000000) >> 31) << 15); + insn[3] = (insn[3] & ~0x10000) | ((slotbuf[1] & 0x1) << 16); + insn[3] = (insn[3] & ~0x20000) | (((slotbuf[1] & 0x2) >> 1) << 17); + insn[3] = (insn[3] & ~0x40000) | (((slotbuf[1] & 0x4) >> 2) << 18); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[1] & 0x8) >> 3) << 19); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[1] & 0x10) >> 4) << 20); +} + +static void +Slot_ae_format_2_Format_ae2_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xf8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0x3e0) | (((insn[0] & 0x1f0000) >> 16) << 5); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[1] & 0x1f00) >> 8) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[3] & 0x3e0) >> 5) << 15); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[0] & 0x3e00000) >> 21) << 20); + slotbuf[0] = (slotbuf[0] & ~0x3e000000) | (((insn[1] & 0x1f0000) >> 16) << 25); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[2] & 0xc0) >> 6) << 30); + slotbuf[1] = ((insn[3] & 0x200000) >> 21); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[3] & 0x400000) >> 22) << 1); + slotbuf[1] = (slotbuf[1] & ~0x4) | (((insn[3] & 0x800000) >> 23) << 2); + slotbuf[1] = (slotbuf[1] & ~0x8) | (((insn[3] & 0x1000000) >> 24) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x2000000) >> 25) << 4); + slotbuf[1] = (slotbuf[1] & ~0x20) | (((insn[3] & 0x4000000) >> 26) << 5); + slotbuf[1] = (slotbuf[1] & ~0x40) | (((insn[3] & 0x8000000) >> 27) << 6); + slotbuf[1] = (slotbuf[1] & ~0x80) | (((insn[3] & 0x10000000) >> 28) << 7); + slotbuf[1] = (slotbuf[1] & ~0x100) | (((insn[3] & 0x20000000) >> 29) << 8); + slotbuf[1] = (slotbuf[1] & ~0x200) | (((insn[3] & 0x40000000) >> 30) << 9); + slotbuf[1] = (slotbuf[1] & ~0x400) | (((insn[3] & 0x80000000) >> 31) << 10); +} + +static void +Slot_ae_format_2_Format_ae2_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xf8) | ((slotbuf[0] & 0x1f) << 3); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0x3e0) >> 5) << 16); + insn[1] = (insn[1] & ~0x1f00) | (((slotbuf[0] & 0x7c00) >> 10) << 8); + insn[3] = (insn[3] & ~0x3e0) | (((slotbuf[0] & 0xf8000) >> 15) << 5); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x1f00000) >> 20) << 21); + insn[1] = (insn[1] & ~0x1f0000) | (((slotbuf[0] & 0x3e000000) >> 25) << 16); + insn[2] = (insn[2] & ~0xc0) | (((slotbuf[0] & 0xc0000000) >> 30) << 6); + insn[3] = (insn[3] & ~0x200000) | ((slotbuf[1] & 0x1) << 21); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[1] & 0x2) >> 1) << 22); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[1] & 0x4) >> 2) << 23); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[1] & 0x8) >> 3) << 24); + insn[3] = (insn[3] & ~0x2000000) | (((slotbuf[1] & 0x10) >> 4) << 25); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[1] & 0x20) >> 5) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[1] & 0x40) >> 6) << 27); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[1] & 0x80) >> 7) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[1] & 0x100) >> 8) << 29); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[1] & 0x200) >> 9) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x400) >> 10) << 31); +} + +static void +Slot_ae_format_3_Format_ae3_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xf00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf0) >> 4) << 4); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[0] & 0x18000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1c00) | ((insn[1] & 0x7) << 10); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x1000000) >> 24) << 13); + slotbuf[0] = (slotbuf[0] & ~0x1c000) | (((insn[0] & 0xe000) >> 13) << 14); + slotbuf[0] = (slotbuf[0] & ~0x20000) | (((insn[0] & 0x4000000) >> 26) << 17); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[1] & 0x6000) >> 13) << 18); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[0] & 0x3e00000) >> 21) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1e000000) | (((insn[1] & 0x78) >> 3) << 25); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[1] & 0x80000) >> 19) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[1] & 0x100000) >> 20) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[1] & 0x200000) >> 21) << 31); + slotbuf[1] = ((insn[1] & 0x400000) >> 22); +} + +static void +Slot_ae_format_3_Format_ae3_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf00) | ((slotbuf[0] & 0xf) << 8); + insn[0] = (insn[0] & ~0xf0) | (((slotbuf[0] & 0xf0) >> 4) << 4); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x300) >> 8) << 27); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x1c00) >> 10); + insn[1] = (insn[1] & ~0x1000000) | (((slotbuf[0] & 0x2000) >> 13) << 24); + insn[0] = (insn[0] & ~0xe000) | (((slotbuf[0] & 0x1c000) >> 14) << 13); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x20000) >> 17) << 26); + insn[1] = (insn[1] & ~0x6000) | (((slotbuf[0] & 0xc0000) >> 18) << 13); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x1f00000) >> 20) << 21); + insn[1] = (insn[1] & ~0x78) | (((slotbuf[0] & 0x1e000000) >> 25) << 3); + insn[1] = (insn[1] & ~0x80000) | (((slotbuf[0] & 0x20000000) >> 29) << 19); + insn[1] = (insn[1] & ~0x100000) | (((slotbuf[0] & 0x40000000) >> 30) << 20); + insn[1] = (insn[1] & ~0x200000) | (((slotbuf[0] & 0x80000000) >> 31) << 21); + insn[1] = (insn[1] & ~0x400000) | ((slotbuf[1] & 0x1) << 22); +} + +static void +Slot_ae_format_3_Format_ae3_slot1_12_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x1000) >> 12); + slotbuf[0] = (slotbuf[0] & ~0xe) | (((insn[1] & 0xe000000) >> 25) << 1); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[1] & 0xf00) >> 8) << 4); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[1] & 0x30000000) >> 28) << 8); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x1f0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x8000) | (((insn[1] & 0x80) >> 7) << 15); + slotbuf[0] = (slotbuf[0] & ~0x10000) | (((insn[1] & 0x1000) >> 12) << 16); + slotbuf[0] = (slotbuf[0] & ~0x1e0000) | (((insn[1] & 0x78000) >> 15) << 17); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[1] & 0x800000) >> 23) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[1] & 0x40000000) >> 30) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[1] & 0x80000000) >> 31) << 23); +} + +static void +Slot_ae_format_3_Format_ae3_slot1_12_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x1000) | ((slotbuf[0] & 0x1) << 12); + insn[1] = (insn[1] & ~0xe000000) | (((slotbuf[0] & 0xe) >> 1) << 25); + insn[1] = (insn[1] & ~0xf00) | (((slotbuf[0] & 0xf0) >> 4) << 8); + insn[1] = (insn[1] & ~0x30000000) | (((slotbuf[0] & 0x300) >> 8) << 28); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0x7c00) >> 10) << 16); + insn[1] = (insn[1] & ~0x80) | (((slotbuf[0] & 0x8000) >> 15) << 7); + insn[1] = (insn[1] & ~0x1000) | (((slotbuf[0] & 0x10000) >> 16) << 12); + insn[1] = (insn[1] & ~0x78000) | (((slotbuf[0] & 0x1e0000) >> 17) << 15); + insn[1] = (insn[1] & ~0x800000) | (((slotbuf[0] & 0x200000) >> 21) << 23); + insn[1] = (insn[1] & ~0x40000000) | (((slotbuf[0] & 0x400000) >> 22) << 30); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x800000) >> 23) << 31); +} + +static void +Slot_ae_format_5_Format_ae5_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xf00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf0) >> 4) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf000) >> 12) << 8); + slotbuf[0] = (slotbuf[0] & ~0x7000) | (((insn[0] & 0x1c000000) >> 26) << 12); + slotbuf[0] = (slotbuf[0] & ~0x38000) | ((insn[1] & 0x7) << 15); + slotbuf[0] = (slotbuf[0] & ~0x1ffc0000) | (((insn[1] & 0xffe000) >> 13) << 18); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[1] & 0x40000000) >> 30) << 29); +} + +static void +Slot_ae_format_5_Format_ae5_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf00) | ((slotbuf[0] & 0xf) << 8); + insn[0] = (insn[0] & ~0xf0) | (((slotbuf[0] & 0xf0) >> 4) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0xf00) >> 8) << 12); + insn[0] = (insn[0] & ~0x1c000000) | (((slotbuf[0] & 0x7000) >> 12) << 26); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x38000) >> 15); + insn[1] = (insn[1] & ~0xffe000) | (((slotbuf[0] & 0x1ffc0000) >> 18) << 13); + insn[1] = (insn[1] & ~0x40000000) | (((slotbuf[0] & 0x20000000) >> 29) << 30); +} + +static void +Slot_ae_format_5_Format_ae5_slot1_56_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x1000000) >> 24); + slotbuf[0] = (slotbuf[0] & ~0x2) | (((insn[1] & 0x80000000) >> 31) << 1); +} + +static void +Slot_ae_format_5_Format_ae5_slot1_56_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x1000000) | ((slotbuf[0] & 0x1) << 24); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x2) >> 1) << 31); +} + +static void +Slot_ae_format_5_Format_ae5_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x1ff8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0xffc00) | (((insn[0] & 0x3ff0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[1] & 0x3e000000) >> 25) << 20); +} + +static void +Slot_ae_format_5_Format_ae5_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x1ff8) | ((slotbuf[0] & 0x3ff) << 3); + insn[0] = (insn[0] & ~0x3ff0000) | (((slotbuf[0] & 0xffc00) >> 10) << 16); + insn[1] = (insn[1] & ~0x3e000000) | (((slotbuf[0] & 0x1f00000) >> 20) << 25); +} + +static void +Slot_ae_format_6_Format_ae6_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xf0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[2] & 0x800000) >> 23) << 4); + slotbuf[0] = (slotbuf[0] & ~0x60) | (((insn[0] & 0x18000000) >> 27) << 5); + slotbuf[0] = (slotbuf[0] & ~0x380) | ((insn[1] & 0x7) << 7); + slotbuf[0] = (slotbuf[0] & ~0x3c00) | (((insn[0] & 0xf000) >> 12) << 10); + slotbuf[0] = (slotbuf[0] & ~0x4000) | (((insn[0] & 0x4000000) >> 26) << 14); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x30000) >> 16) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[2] & 0x7000000) >> 24) << 17); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[1] & 0x1000) >> 12) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1e00000) | (((insn[2] & 0xf00) >> 8) << 21); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x8000) >> 15) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x10000) >> 16) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x20000) >> 17) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x40000) >> 18) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x80000) >> 19) << 29); +} + +static void +Slot_ae_format_6_Format_ae6_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0) | ((slotbuf[0] & 0xf) << 4); + insn[2] = (insn[2] & ~0x800000) | (((slotbuf[0] & 0x10) >> 4) << 23); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x60) >> 5) << 27); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x380) >> 7); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0x3c00) >> 10) << 12); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x4000) >> 14) << 26); + insn[2] = (insn[2] & ~0x30000) | (((slotbuf[0] & 0x18000) >> 15) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0xe0000) >> 17) << 24); + insn[1] = (insn[1] & ~0x1000) | (((slotbuf[0] & 0x100000) >> 20) << 12); + insn[2] = (insn[2] & ~0xf00) | (((slotbuf[0] & 0x1e00000) >> 21) << 8); + insn[3] = (insn[3] & ~0x8000) | (((slotbuf[0] & 0x2000000) >> 25) << 15); + insn[3] = (insn[3] & ~0x10000) | (((slotbuf[0] & 0x4000000) >> 26) << 16); + insn[3] = (insn[3] & ~0x20000) | (((slotbuf[0] & 0x8000000) >> 27) << 17); + insn[3] = (insn[3] & ~0x40000) | (((slotbuf[0] & 0x10000000) >> 28) << 18); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[0] & 0x20000000) >> 29) << 19); +} + +static void +Slot_ae_format_6_Format_ae6_slot1_57_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xc0000000) >> 30); + slotbuf[0] = (slotbuf[0] & ~0x1c) | ((insn[2] & 0x7) << 2); + slotbuf[0] = (slotbuf[0] & ~0x3e0) | (((insn[1] & 0x3e000000) >> 25) << 5); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[2] & 0xf8000000) >> 27) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | ((insn[3] & 0x1f) << 15); + slotbuf[0] = (slotbuf[0] & ~0xf00000) | (((insn[2] & 0xf000) >> 12) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x100000) >> 20) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x200000) >> 21) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x400000) >> 22) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x800000) >> 23) << 27); +} + +static void +Slot_ae_format_6_Format_ae6_slot1_57_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xc0000000) | ((slotbuf[0] & 0x3) << 30); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0x1c) >> 2); + insn[1] = (insn[1] & ~0x3e000000) | (((slotbuf[0] & 0x3e0) >> 5) << 25); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x7c00) >> 10) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0xf8000) >> 15); + insn[2] = (insn[2] & ~0xf000) | (((slotbuf[0] & 0xf00000) >> 20) << 12); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[0] & 0x1000000) >> 24) << 20); + insn[3] = (insn[3] & ~0x200000) | (((slotbuf[0] & 0x2000000) >> 25) << 21); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[0] & 0x4000000) >> 26) << 22); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[0] & 0x8000000) >> 27) << 23); +} + +static void +Slot_ae_format_6_Format_ae6_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xf8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0x7fe0) | (((insn[0] & 0x3ff0000) >> 16) << 5); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[3] & 0x3e0) >> 5) << 15); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[2] & 0x40000) >> 18) << 20); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x1000000) >> 24) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x2000000) >> 25) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x4000000) >> 26) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x8000000) >> 27) << 24); +} + +static void +Slot_ae_format_6_Format_ae6_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xf8) | ((slotbuf[0] & 0x1f) << 3); + insn[0] = (insn[0] & ~0x3ff0000) | (((slotbuf[0] & 0x7fe0) >> 5) << 16); + insn[3] = (insn[3] & ~0x3e0) | (((slotbuf[0] & 0xf8000) >> 15) << 5); + insn[2] = (insn[2] & ~0x40000) | (((slotbuf[0] & 0x100000) >> 20) << 18); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x200000) >> 21) << 24); + insn[3] = (insn[3] & ~0x2000000) | (((slotbuf[0] & 0x400000) >> 22) << 25); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x800000) >> 23) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x1000000) >> 24) << 27); +} + +static void +Slot_ae_format_6_Format_ae6_slot3_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x3e000) >> 13); + slotbuf[0] = (slotbuf[0] & ~0x60) | (((insn[2] & 0x180000) >> 19) << 5); + slotbuf[0] = (slotbuf[0] & ~0x380) | (((insn[3] & 0x1c00) >> 10) << 7); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[2] & 0xf8) >> 3) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[1] & 0x7c0000) >> 18) << 15); + slotbuf[0] = (slotbuf[0] & ~0x700000) | (((insn[0] & 0x700) >> 8) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1800000) | (((insn[1] & 0x1800000) >> 23) << 23); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[0] & 0x800) >> 11) << 25); + slotbuf[0] = (slotbuf[0] & ~0x3c000000) | (((insn[1] & 0xf00) >> 8) << 26); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[2] & 0x600000) >> 21) << 30); + slotbuf[1] = ((insn[3] & 0x6000) >> 13); + slotbuf[1] = (slotbuf[1] & ~0x4) | (((insn[3] & 0x10000000) >> 28) << 2); + slotbuf[1] = (slotbuf[1] & ~0x8) | (((insn[3] & 0x20000000) >> 29) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x40000000) >> 30) << 4); + slotbuf[1] = (slotbuf[1] & ~0x20) | (((insn[3] & 0x80000000) >> 31) << 5); +} + +static void +Slot_ae_format_6_Format_ae6_slot3_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x3e000) | ((slotbuf[0] & 0x1f) << 13); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x60) >> 5) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0x380) >> 7) << 10); + insn[2] = (insn[2] & ~0xf8) | (((slotbuf[0] & 0x7c00) >> 10) << 3); + insn[1] = (insn[1] & ~0x7c0000) | (((slotbuf[0] & 0xf8000) >> 15) << 18); + insn[0] = (insn[0] & ~0x700) | (((slotbuf[0] & 0x700000) >> 20) << 8); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x1800000) >> 23) << 23); + insn[0] = (insn[0] & ~0x800) | (((slotbuf[0] & 0x2000000) >> 25) << 11); + insn[1] = (insn[1] & ~0xf00) | (((slotbuf[0] & 0x3c000000) >> 26) << 8); + insn[2] = (insn[2] & ~0x600000) | (((slotbuf[0] & 0xc0000000) >> 30) << 21); + insn[3] = (insn[3] & ~0x6000) | ((slotbuf[1] & 0x3) << 13); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[1] & 0x4) >> 2) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[1] & 0x8) >> 3) << 29); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[1] & 0x10) >> 4) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x20) >> 5) << 31); +} + +static void +Slot_ae_format_7_Format_ae7_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x3f0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x3c0) | (((insn[0] & 0xf000) >> 12) << 6); + slotbuf[0] = (slotbuf[0] & ~0x1c00) | (((insn[2] & 0xe00000) >> 21) << 10); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[2] & 0x30000) >> 16) << 13); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[2] & 0x7000000) >> 24) << 15); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[0] & 0xc00) >> 10) << 18); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[0] & 0x4000000) >> 26) << 20); + slotbuf[0] = (slotbuf[0] & ~0x600000) | (((insn[1] & 0x1800000) >> 23) << 21); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x20000000) >> 29) << 23); +} + +static void +Slot_ae_format_7_Format_ae7_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3f0) | ((slotbuf[0] & 0x3f) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0x3c0) >> 6) << 12); + insn[2] = (insn[2] & ~0xe00000) | (((slotbuf[0] & 0x1c00) >> 10) << 21); + insn[2] = (insn[2] & ~0x30000) | (((slotbuf[0] & 0x6000) >> 13) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0x38000) >> 15) << 24); + insn[0] = (insn[0] & ~0xc00) | (((slotbuf[0] & 0xc0000) >> 18) << 10); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x100000) >> 20) << 26); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x600000) >> 21) << 23); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x800000) >> 23) << 29); +} + +static void +Slot_ae_format_7_Format_ae7_slot1_72_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xf000) >> 12); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[2] & 0xf00) >> 8) << 4); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[2] & 0xf8000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x40000) >> 18) << 18); + slotbuf[0] = (slotbuf[0] & ~0x780000) | (((insn[3] & 0x1e000) >> 13) << 19); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x40000000) >> 30) << 23); +} + +static void +Slot_ae_format_7_Format_ae7_slot1_72_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xf000) | ((slotbuf[0] & 0xf) << 12); + insn[2] = (insn[2] & ~0xf00) | (((slotbuf[0] & 0xf0) >> 4) << 8); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x1f00) >> 8) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[2] = (insn[2] & ~0x40000) | (((slotbuf[0] & 0x40000) >> 18) << 18); + insn[3] = (insn[3] & ~0x1e000) | (((slotbuf[0] & 0x780000) >> 19) << 13); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x800000) >> 23) << 30); +} + +static void +Slot_ae_format_7_Format_ae7_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x1ff8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x3e00000) >> 21) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[0] & 0x1f0000) >> 16) << 15); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[3] & 0x3e0) >> 5) << 20); + slotbuf[0] = (slotbuf[0] & ~0x6000000) | (((insn[0] & 0x18000000) >> 27) << 25); + slotbuf[0] = (slotbuf[0] & ~0x38000000) | ((insn[1] & 0x7) << 27); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0x60000) >> 17) << 30); + slotbuf[1] = ((insn[3] & 0x780000) >> 19); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x80000000) >> 31) << 4); +} + +static void +Slot_ae_format_7_Format_ae7_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x1ff8) | ((slotbuf[0] & 0x3ff) << 3); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x7c00) >> 10) << 21); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0xf8000) >> 15) << 16); + insn[3] = (insn[3] & ~0x3e0) | (((slotbuf[0] & 0x1f00000) >> 20) << 5); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x6000000) >> 25) << 27); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x38000000) >> 27); + insn[3] = (insn[3] & ~0x60000) | (((slotbuf[0] & 0xc0000000) >> 30) << 17); + insn[3] = (insn[3] & ~0x780000) | ((slotbuf[1] & 0xf) << 19); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x10) >> 4) << 31); +} + +static void +Slot_ae_format_7_Format_ae7_slot3_45_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xfe000000) >> 25); + slotbuf[0] = (slotbuf[0] & ~0x7f80) | ((insn[2] & 0xff) << 7); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x180000) >> 19) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[3] & 0x1c00) >> 10) << 17); + slotbuf[0] = (slotbuf[0] & ~0x3ff00000) | (((insn[1] & 0x7fe000) >> 13) << 20); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0x1800000) >> 23) << 30); + slotbuf[1] = ((insn[3] & 0x1e000000) >> 25); +} + +static void +Slot_ae_format_7_Format_ae7_slot3_45_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xfe000000) | ((slotbuf[0] & 0x7f) << 25); + insn[2] = (insn[2] & ~0xff) | ((slotbuf[0] & 0x7f80) >> 7); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x18000) >> 15) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0xe0000) >> 17) << 10); + insn[1] = (insn[1] & ~0x7fe000) | (((slotbuf[0] & 0x3ff00000) >> 20) << 13); + insn[3] = (insn[3] & ~0x1800000) | (((slotbuf[0] & 0xc0000000) >> 30) << 23); + insn[3] = (insn[3] & ~0x1e000000) | ((slotbuf[1] & 0xf) << 25); +} + +static void +Slot_ae_format_8_Format_ae8_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xf0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x70) | (((insn[2] & 0x3800000) >> 23) << 4); + slotbuf[0] = (slotbuf[0] & ~0x80) | (((insn[0] & 0x2000) >> 13) << 7); + slotbuf[0] = (slotbuf[0] & ~0x100) | (((insn[0] & 0x100) >> 8) << 8); + slotbuf[0] = (slotbuf[0] & ~0x600) | (((insn[0] & 0x18000000) >> 27) << 9); + slotbuf[0] = (slotbuf[0] & ~0x800) | ((insn[1] & 0x1) << 11); + slotbuf[0] = (slotbuf[0] & ~0x3000) | (((insn[1] & 0x1800000) >> 23) << 12); + slotbuf[0] = (slotbuf[0] & ~0x4000) | (((insn[0] & 0x200) >> 9) << 14); + slotbuf[0] = (slotbuf[0] & ~0x8000) | (((insn[0] & 0x1000) >> 12) << 15); + slotbuf[0] = (slotbuf[0] & ~0x30000) | (((insn[0] & 0xc00) >> 10) << 16); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x10000) >> 16) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[2] & 0x200000) >> 21) << 19); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[1] & 0x1000) >> 12) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1e00000) | (((insn[1] & 0x1e000000) >> 25) << 21); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[2] & 0x400000) >> 22) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x10000) >> 16) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x20000) >> 17) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x40000) >> 18) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x80000) >> 19) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x100000) >> 20) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x200000) >> 21) << 31); +} + +static void +Slot_ae_format_8_Format_ae8_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0) | ((slotbuf[0] & 0xf) << 4); + insn[2] = (insn[2] & ~0x3800000) | (((slotbuf[0] & 0x70) >> 4) << 23); + insn[0] = (insn[0] & ~0x2000) | (((slotbuf[0] & 0x80) >> 7) << 13); + insn[0] = (insn[0] & ~0x100) | (((slotbuf[0] & 0x100) >> 8) << 8); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x600) >> 9) << 27); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x800) >> 11); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x3000) >> 12) << 23); + insn[0] = (insn[0] & ~0x200) | (((slotbuf[0] & 0x4000) >> 14) << 9); + insn[0] = (insn[0] & ~0x1000) | (((slotbuf[0] & 0x8000) >> 15) << 12); + insn[0] = (insn[0] & ~0xc00) | (((slotbuf[0] & 0x30000) >> 16) << 10); + insn[2] = (insn[2] & ~0x10000) | (((slotbuf[0] & 0x40000) >> 18) << 16); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[0] & 0x80000) >> 19) << 21); + insn[1] = (insn[1] & ~0x1000) | (((slotbuf[0] & 0x100000) >> 20) << 12); + insn[1] = (insn[1] & ~0x1e000000) | (((slotbuf[0] & 0x1e00000) >> 21) << 25); + insn[2] = (insn[2] & ~0x400000) | (((slotbuf[0] & 0x2000000) >> 25) << 22); + insn[3] = (insn[3] & ~0x10000) | (((slotbuf[0] & 0x4000000) >> 26) << 16); + insn[3] = (insn[3] & ~0x20000) | (((slotbuf[0] & 0x8000000) >> 27) << 17); + insn[3] = (insn[3] & ~0x40000) | (((slotbuf[0] & 0x10000000) >> 28) << 18); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[0] & 0x20000000) >> 29) << 19); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[0] & 0x40000000) >> 30) << 20); + insn[3] = (insn[3] & ~0x200000) | (((slotbuf[0] & 0x80000000) >> 31) << 21); +} + +static void +Slot_ae_format_8_Format_ae8_slot1_14_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[0] & 0xc000) >> 14) << 8); + slotbuf[0] = (slotbuf[0] & ~0x400) | (((insn[1] & 0x2) >> 1) << 10); + slotbuf[0] = (slotbuf[0] & ~0x800) | (((insn[1] & 0x8) >> 3) << 11); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[2] & 0x80000000) >> 31) << 12); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[2] & 0x60000) >> 17) << 18); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[2] & 0x4000000) >> 26) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1e00000) | (((insn[3] & 0x1e0) >> 5) << 21); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x400000) >> 22) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x800000) >> 23) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x1000000) >> 24) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x2000000) >> 25) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x4000000) >> 26) << 29); +} + +static void +Slot_ae_format_8_Format_ae8_slot1_14_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[0] = (insn[0] & ~0xc000) | (((slotbuf[0] & 0x300) >> 8) << 14); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x400) >> 10) << 1); + insn[1] = (insn[1] & ~0x8) | (((slotbuf[0] & 0x800) >> 11) << 3); + insn[2] = (insn[2] & ~0x80000000) | (((slotbuf[0] & 0x1000) >> 12) << 31); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[2] = (insn[2] & ~0x60000) | (((slotbuf[0] & 0xc0000) >> 18) << 17); + insn[2] = (insn[2] & ~0x4000000) | (((slotbuf[0] & 0x100000) >> 20) << 26); + insn[3] = (insn[3] & ~0x1e0) | (((slotbuf[0] & 0x1e00000) >> 21) << 5); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[0] & 0x2000000) >> 25) << 22); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[0] & 0x4000000) >> 26) << 23); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x8000000) >> 27) << 24); + insn[3] = (insn[3] & ~0x2000000) | (((slotbuf[0] & 0x10000000) >> 28) << 25); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x20000000) >> 29) << 26); +} + +static void +Slot_ae_format_8_Format_ae8_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xc0000000) >> 30); + slotbuf[0] = (slotbuf[0] & ~0x3fc) | ((insn[2] & 0xff) << 2); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x3e00000) >> 21) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[0] & 0x1f0000) >> 16) << 15); + slotbuf[0] = (slotbuf[0] & ~0xf00000) | (((insn[1] & 0xf0) >> 4) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[1] & 0x800) >> 11) << 24); + slotbuf[0] = (slotbuf[0] & ~0x6000000) | (((insn[2] & 0x180000) >> 19) << 25); + slotbuf[0] = (slotbuf[0] & ~0x38000000) | (((insn[3] & 0x1c00) >> 10) << 27); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[1] & 0xc0000) >> 18) << 30); + slotbuf[1] = ((insn[1] & 0x700000) >> 20); + slotbuf[1] = (slotbuf[1] & ~0x8) | (((insn[0] & 0x4000000) >> 26) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[1] & 0x4) >> 2) << 4); + slotbuf[1] = (slotbuf[1] & ~0xe0) | (((insn[1] & 0x700) >> 8) << 5); + slotbuf[1] = (slotbuf[1] & ~0x1f00) | (((insn[1] & 0x3e000) >> 13) << 8); + slotbuf[1] = (slotbuf[1] & ~0x2000) | (((insn[1] & 0x20000000) >> 29) << 13); + slotbuf[1] = (slotbuf[1] & ~0x3c000) | (((insn[2] & 0x78000000) >> 27) << 14); + slotbuf[1] = (slotbuf[1] & ~0x40000) | (((insn[3] & 0x200) >> 9) << 18); + slotbuf[1] = (slotbuf[1] & ~0x380000) | (((insn[3] & 0xe000) >> 13) << 19); + slotbuf[1] = (slotbuf[1] & ~0x400000) | (((insn[3] & 0x8000000) >> 27) << 22); + slotbuf[1] = (slotbuf[1] & ~0x800000) | (((insn[3] & 0x10000000) >> 28) << 23); + slotbuf[1] = (slotbuf[1] & ~0x1000000) | (((insn[3] & 0x20000000) >> 29) << 24); + slotbuf[1] = (slotbuf[1] & ~0x2000000) | (((insn[3] & 0x40000000) >> 30) << 25); + slotbuf[1] = (slotbuf[1] & ~0x4000000) | (((insn[3] & 0x80000000) >> 31) << 26); +} + +static void +Slot_ae_format_8_Format_ae8_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xc0000000) | ((slotbuf[0] & 0x3) << 30); + insn[2] = (insn[2] & ~0xff) | ((slotbuf[0] & 0x3fc) >> 2); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x7c00) >> 10) << 21); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0xf8000) >> 15) << 16); + insn[1] = (insn[1] & ~0xf0) | (((slotbuf[0] & 0xf00000) >> 20) << 4); + insn[1] = (insn[1] & ~0x800) | (((slotbuf[0] & 0x1000000) >> 24) << 11); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x6000000) >> 25) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0x38000000) >> 27) << 10); + insn[1] = (insn[1] & ~0xc0000) | (((slotbuf[0] & 0xc0000000) >> 30) << 18); + insn[1] = (insn[1] & ~0x700000) | ((slotbuf[1] & 0x7) << 20); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[1] & 0x8) >> 3) << 26); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[1] & 0x10) >> 4) << 2); + insn[1] = (insn[1] & ~0x700) | (((slotbuf[1] & 0xe0) >> 5) << 8); + insn[1] = (insn[1] & ~0x3e000) | (((slotbuf[1] & 0x1f00) >> 8) << 13); + insn[1] = (insn[1] & ~0x20000000) | (((slotbuf[1] & 0x2000) >> 13) << 29); + insn[2] = (insn[2] & ~0x78000000) | (((slotbuf[1] & 0x3c000) >> 14) << 27); + insn[3] = (insn[3] & ~0x200) | (((slotbuf[1] & 0x40000) >> 18) << 9); + insn[3] = (insn[3] & ~0xe000) | (((slotbuf[1] & 0x380000) >> 19) << 13); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[1] & 0x400000) >> 22) << 27); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[1] & 0x800000) >> 23) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[1] & 0x1000000) >> 24) << 29); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[1] & 0x2000000) >> 25) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x4000000) >> 26) << 31); +} + +static void +Slot_ae_format_9_Format_ae9_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xfff0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x7000) | (((insn[0] & 0x1c000000) >> 26) << 12); + slotbuf[0] = (slotbuf[0] & ~0x38000) | ((insn[1] & 0x7) << 15); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x10000) >> 16) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[2] & 0x200000) >> 21) << 19); + slotbuf[0] = (slotbuf[0] & ~0x300000) | (((insn[1] & 0x1800000) >> 23) << 20); + slotbuf[0] = (slotbuf[0] & ~0x3c00000) | (((insn[2] & 0x3c00000) >> 22) << 22); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x1000000) >> 24) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x2000000) >> 25) << 27); +} + +static void +Slot_ae_format_9_Format_ae9_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xfff0) | ((slotbuf[0] & 0xfff) << 4); + insn[0] = (insn[0] & ~0x1c000000) | (((slotbuf[0] & 0x7000) >> 12) << 26); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x38000) >> 15); + insn[2] = (insn[2] & ~0x10000) | (((slotbuf[0] & 0x40000) >> 18) << 16); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[0] & 0x80000) >> 19) << 21); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x300000) >> 20) << 23); + insn[2] = (insn[2] & ~0x3c00000) | (((slotbuf[0] & 0x3c00000) >> 22) << 22); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x4000000) >> 26) << 24); + insn[3] = (insn[3] & ~0x2000000) | (((slotbuf[0] & 0x8000000) >> 27) << 25); +} + +static void +Slot_ae_format_9_Format_ae9_slot1_72_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[2] & 0xf8000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[2] & 0x60000) >> 17) << 18); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[2] & 0x4000000) >> 26) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1e00000) | (((insn[3] & 0x1e000) >> 13) << 21); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x4000000) >> 26) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x8000000) >> 27) << 26); +} + +static void +Slot_ae_format_9_Format_ae9_slot1_72_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x1f00) >> 8) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[2] = (insn[2] & ~0x60000) | (((slotbuf[0] & 0xc0000) >> 18) << 17); + insn[2] = (insn[2] & ~0x4000000) | (((slotbuf[0] & 0x100000) >> 20) << 26); + insn[3] = (insn[3] & ~0x1e000) | (((slotbuf[0] & 0x1e00000) >> 21) << 13); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x2000000) >> 25) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x4000000) >> 26) << 27); +} + +static void +Slot_ae_format_9_Format_ae9_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[3] & 0x3e0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x60) | (((insn[1] & 0xc0000000) >> 30) << 5); + slotbuf[0] = (slotbuf[0] & ~0x380) | ((insn[2] & 0x7) << 7); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x1f0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1ff8000) | (((insn[1] & 0x1ff8) >> 3) << 15); + slotbuf[0] = (slotbuf[0] & ~0x3e000000) | (((insn[0] & 0x3e00000) >> 21) << 25); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0x60000) >> 17) << 30); + slotbuf[1] = ((insn[3] & 0x10000000) >> 28); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[3] & 0x20000000) >> 29) << 1); +} + +static void +Slot_ae_format_9_Format_ae9_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[3] = (insn[3] & ~0x3e0) | ((slotbuf[0] & 0x1f) << 5); + insn[1] = (insn[1] & ~0xc0000000) | (((slotbuf[0] & 0x60) >> 5) << 30); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0x380) >> 7); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0x7c00) >> 10) << 16); + insn[1] = (insn[1] & ~0x1ff8) | (((slotbuf[0] & 0x1ff8000) >> 15) << 3); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x3e000000) >> 25) << 21); + insn[3] = (insn[3] & ~0x60000) | (((slotbuf[0] & 0xc0000000) >> 30) << 17); + insn[3] = (insn[3] & ~0x10000000) | ((slotbuf[1] & 0x1) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[1] & 0x2) >> 1) << 29); +} + +static void +Slot_ae_format_9_Format_ae9_slot3_45_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xf8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0x3e0) | (((insn[1] & 0x3e000000) >> 25) << 5); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[1] & 0x7c0000) >> 18) << 10); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x180000) >> 19) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[3] & 0x1c00) >> 10) << 17); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[1] & 0x3e000) >> 13) << 20); + slotbuf[0] = (slotbuf[0] & ~0x3e000000) | (((insn[3] & 0xf80000) >> 19) << 25); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x40000000) >> 30) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x80000000) >> 31) << 31); +} + +static void +Slot_ae_format_9_Format_ae9_slot3_45_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xf8) | ((slotbuf[0] & 0x1f) << 3); + insn[1] = (insn[1] & ~0x3e000000) | (((slotbuf[0] & 0x3e0) >> 5) << 25); + insn[1] = (insn[1] & ~0x7c0000) | (((slotbuf[0] & 0x7c00) >> 10) << 18); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x18000) >> 15) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0xe0000) >> 17) << 10); + insn[1] = (insn[1] & ~0x3e000) | (((slotbuf[0] & 0x1f00000) >> 20) << 13); + insn[3] = (insn[3] & ~0xf80000) | (((slotbuf[0] & 0x3e000000) >> 25) << 19); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x40000000) >> 30) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x80000000) >> 31) << 31); +} + +static void +Slot_ae_format_10_Format_ae10_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x3f0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x3c0) | (((insn[0] & 0xf000) >> 12) << 6); + slotbuf[0] = (slotbuf[0] & ~0xc00) | (((insn[0] & 0xc00) >> 10) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[2] & 0x800000) >> 23) << 12); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[2] & 0x30000) >> 16) << 13); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[2] & 0x7000000) >> 24) << 15); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[1] & 0x2) >> 1) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[0] & 0x4000000) >> 26) << 19); + slotbuf[0] = (slotbuf[0] & ~0x300000) | (((insn[2] & 0x600000) >> 21) << 20); + slotbuf[0] = (slotbuf[0] & ~0xc00000) | (((insn[3] & 0x6000) >> 13) << 22); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x40000000) >> 30) << 24); +} + +static void +Slot_ae_format_10_Format_ae10_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3f0) | ((slotbuf[0] & 0x3f) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0x3c0) >> 6) << 12); + insn[0] = (insn[0] & ~0xc00) | (((slotbuf[0] & 0xc00) >> 10) << 10); + insn[2] = (insn[2] & ~0x800000) | (((slotbuf[0] & 0x1000) >> 12) << 23); + insn[2] = (insn[2] & ~0x30000) | (((slotbuf[0] & 0x6000) >> 13) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0x38000) >> 15) << 24); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x40000) >> 18) << 1); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x80000) >> 19) << 26); + insn[2] = (insn[2] & ~0x600000) | (((slotbuf[0] & 0x300000) >> 20) << 21); + insn[3] = (insn[3] & ~0x6000) | (((slotbuf[0] & 0xc00000) >> 22) << 13); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x1000000) >> 24) << 30); +} + +static void +Slot_ae_format_10_Format_ae10_slot1_34_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[2] & 0xf8000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[1] & 0x4) >> 2) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[2] & 0x40000) >> 18) << 19); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[3] & 0xf8000) >> 15) << 20); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x80000000) >> 31) << 25); +} + +static void +Slot_ae_format_10_Format_ae10_slot1_34_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x1f00) >> 8) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[0] & 0x40000) >> 18) << 2); + insn[2] = (insn[2] & ~0x40000) | (((slotbuf[0] & 0x80000) >> 19) << 18); + insn[3] = (insn[3] & ~0xf8000) | (((slotbuf[0] & 0x1f00000) >> 20) << 15); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x2000000) >> 25) << 31); +} + +static void +Slot_ae_format_10_Format_ae10_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[3] & 0x3e0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x60) | (((insn[1] & 0xc0000000) >> 30) << 5); + slotbuf[0] = (slotbuf[0] & ~0x380) | ((insn[2] & 0x7) << 7); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x1f0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1ff8000) | (((insn[1] & 0x1ff8) >> 3) << 15); + slotbuf[0] = (slotbuf[0] & ~0x3e000000) | (((insn[0] & 0x3e00000) >> 21) << 25); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0x300000) >> 20) << 30); + slotbuf[1] = ((insn[3] & 0x1c00000) >> 22); +} + +static void +Slot_ae_format_10_Format_ae10_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[3] = (insn[3] & ~0x3e0) | ((slotbuf[0] & 0x1f) << 5); + insn[1] = (insn[1] & ~0xc0000000) | (((slotbuf[0] & 0x60) >> 5) << 30); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0x380) >> 7); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0x7c00) >> 10) << 16); + insn[1] = (insn[1] & ~0x1ff8) | (((slotbuf[0] & 0x1ff8000) >> 15) << 3); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x3e000000) >> 25) << 21); + insn[3] = (insn[3] & ~0x300000) | (((slotbuf[0] & 0xc0000000) >> 30) << 20); + insn[3] = (insn[3] & ~0x1c00000) | ((slotbuf[1] & 0x7) << 22); +} + +static void +Slot_ae_format_10_Format_ae10_slot3_27_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xf8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0x3e0) | (((insn[1] & 0x3e000000) >> 25) << 5); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[1] & 0x7c0000) >> 18) << 10); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x180000) >> 19) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[3] & 0x1c00) >> 10) << 17); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[1] & 0x3e000) >> 13) << 20); + slotbuf[0] = (slotbuf[0] & ~0x6000000) | (((insn[0] & 0x18000000) >> 27) << 25); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | ((insn[1] & 0x1) << 27); + slotbuf[0] = (slotbuf[0] & ~0x30000000) | (((insn[1] & 0x1800000) >> 23) << 28); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0x6000000) >> 25) << 30); + slotbuf[1] = ((insn[3] & 0x38000000) >> 27); +} + +static void +Slot_ae_format_10_Format_ae10_slot3_27_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xf8) | ((slotbuf[0] & 0x1f) << 3); + insn[1] = (insn[1] & ~0x3e000000) | (((slotbuf[0] & 0x3e0) >> 5) << 25); + insn[1] = (insn[1] & ~0x7c0000) | (((slotbuf[0] & 0x7c00) >> 10) << 18); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x18000) >> 15) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0xe0000) >> 17) << 10); + insn[1] = (insn[1] & ~0x3e000) | (((slotbuf[0] & 0x1f00000) >> 20) << 13); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x6000000) >> 25) << 27); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x8000000) >> 27); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x30000000) >> 28) << 23); + insn[3] = (insn[3] & ~0x6000000) | (((slotbuf[0] & 0xc0000000) >> 30) << 25); + insn[3] = (insn[3] & ~0x38000000) | ((slotbuf[1] & 0x7) << 27); +} + +static void +Slot_ae_format_4_Format_ae4_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x3f0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x3c0) | (((insn[0] & 0xf000) >> 12) << 6); + slotbuf[0] = (slotbuf[0] & ~0xc00) | (((insn[0] & 0xc00) >> 10) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x2) >> 1) << 12); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[0] & 0x18000000) >> 27) << 13); + slotbuf[0] = (slotbuf[0] & ~0x8000) | ((insn[1] & 0x1) << 15); + slotbuf[0] = (slotbuf[0] & ~0x30000) | (((insn[1] & 0x1800000) >> 23) << 16); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x40000) >> 18) << 18); + slotbuf[0] = (slotbuf[0] & ~0x380000) | (((insn[3] & 0xe000) >> 13) << 19); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x10000000) >> 28) << 22); +} + +static void +Slot_ae_format_4_Format_ae4_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3f0) | ((slotbuf[0] & 0x3f) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0x3c0) >> 6) << 12); + insn[0] = (insn[0] & ~0xc00) | (((slotbuf[0] & 0xc00) >> 10) << 10); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x1000) >> 12) << 1); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x6000) >> 13) << 27); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x8000) >> 15); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x30000) >> 16) << 23); + insn[2] = (insn[2] & ~0x40000) | (((slotbuf[0] & 0x40000) >> 18) << 18); + insn[3] = (insn[3] & ~0xe000) | (((slotbuf[0] & 0x380000) >> 19) << 13); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[0] & 0x400000) >> 22) << 28); +} + +static void +Slot_ae_format_4_Format_ae4_slot1_72_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[2] & 0xf8000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0x3c0000) | (((insn[3] & 0xf0000) >> 16) << 18); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x20000000) >> 29) << 22); +} + +static void +Slot_ae_format_4_Format_ae4_slot1_72_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x1f00) >> 8) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[3] = (insn[3] & ~0xf0000) | (((slotbuf[0] & 0x3c0000) >> 18) << 16); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x400000) >> 22) << 29); +} + +static void +Slot_ae_format_4_Format_ae4_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x3e00000) >> 21); + slotbuf[0] = (slotbuf[0] & ~0x3e0) | (((insn[0] & 0x1f0000) >> 16) << 5); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[1] & 0xf8) >> 3) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[3] & 0x3e0) >> 5) << 15); + slotbuf[0] = (slotbuf[0] & ~0x700000) | (((insn[3] & 0x700000) >> 20) << 20); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x40000000) >> 30) << 23); +} + +static void +Slot_ae_format_4_Format_ae4_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3e00000) | ((slotbuf[0] & 0x1f) << 21); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0x3e0) >> 5) << 16); + insn[1] = (insn[1] & ~0xf8) | (((slotbuf[0] & 0x7c00) >> 10) << 3); + insn[3] = (insn[3] & ~0x3e0) | (((slotbuf[0] & 0xf8000) >> 15) << 5); + insn[3] = (insn[3] & ~0x700000) | (((slotbuf[0] & 0x700000) >> 20) << 20); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x800000) >> 23) << 30); +} + +static void +Slot_ae_format_4_Format_ae4_slot3_26_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0x180000) >> 19); + slotbuf[0] = (slotbuf[0] & ~0x1c) | (((insn[3] & 0x1c00) >> 10) << 2); + slotbuf[0] = (slotbuf[0] & ~0x20) | (((insn[0] & 0x4000000) >> 26) << 5); + slotbuf[0] = (slotbuf[0] & ~0x40) | (((insn[1] & 0x4) >> 2) << 6); + slotbuf[0] = (slotbuf[0] & ~0x380) | (((insn[1] & 0x700) >> 8) << 7); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[1] & 0x3e000) >> 13) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[2] & 0xf8) >> 3) << 15); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[1] & 0x7c0000) >> 18) << 20); + slotbuf[0] = (slotbuf[0] & ~0x6000000) | (((insn[3] & 0x1800000) >> 23) << 25); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x80000000) >> 31) << 27); +} + +static void +Slot_ae_format_4_Format_ae4_slot3_26_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0x180000) | ((slotbuf[0] & 0x3) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0x1c) >> 2) << 10); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x20) >> 5) << 26); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[0] & 0x40) >> 6) << 2); + insn[1] = (insn[1] & ~0x700) | (((slotbuf[0] & 0x380) >> 7) << 8); + insn[1] = (insn[1] & ~0x3e000) | (((slotbuf[0] & 0x7c00) >> 10) << 13); + insn[2] = (insn[2] & ~0xf8) | (((slotbuf[0] & 0xf8000) >> 15) << 3); + insn[1] = (insn[1] & ~0x7c0000) | (((slotbuf[0] & 0x1f00000) >> 20) << 18); + insn[3] = (insn[3] & ~0x1800000) | (((slotbuf[0] & 0x6000000) >> 25) << 23); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x8000000) >> 27) << 31); +} + +static void +Slot_ae_format_4_Format_ae4_slot4_43_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xfe000000) >> 25); + slotbuf[0] = (slotbuf[0] & ~0x380) | ((insn[2] & 0x7) << 7); + slotbuf[0] = (slotbuf[0] & ~0xc00) | (((insn[1] & 0x1800) >> 11) << 10); + slotbuf[0] = (slotbuf[0] & ~0x7000) | (((insn[2] & 0xe00000) >> 21) << 12); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x30000) >> 16) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[2] & 0x7000000) >> 24) << 17); + slotbuf[0] = (slotbuf[0] & ~0x700000) | (((insn[3] & 0xe000000) >> 25) << 20); +} + +static void +Slot_ae_format_4_Format_ae4_slot4_43_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xfe000000) | ((slotbuf[0] & 0x7f) << 25); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0x380) >> 7); + insn[1] = (insn[1] & ~0x1800) | (((slotbuf[0] & 0xc00) >> 10) << 11); + insn[2] = (insn[2] & ~0xe00000) | (((slotbuf[0] & 0x7000) >> 12) << 21); + insn[2] = (insn[2] & ~0x30000) | (((slotbuf[0] & 0x18000) >> 15) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0xe0000) >> 17) << 24); + insn[3] = (insn[3] & ~0xe000000) | (((slotbuf[0] & 0x700000) >> 20) << 25); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_s8_Slot_inst_get, + Field_imms8_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_r_disp_Slot_inst_get, + Field_r_3_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst_get, + Field_s2_Slot_inst_get, + Field_r2_Slot_inst_get, + Field_t4_Slot_inst_get, + Field_s4_Slot_inst_get, + Field_r4_Slot_inst_get, + Field_t8_Slot_inst_get, + Field_r8_Slot_inst_get, + Field_xt_wbr15_imm_Slot_inst_get, + Field_xt_wbr18_imm_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_inst_11_8_Slot_inst_get, + Field_fld_inst_12_12_Slot_inst_get, + Field_fld_inst_12_8_Slot_inst_get, + Field_fld_inst_13_8_Slot_inst_get, + Field_fld_inst_15_12_Slot_inst_get, + Field_fld_inst_19_17_Slot_inst_get, + Field_fld_inst_19_18_Slot_inst_get, + Field_fld_inst_23_12_Slot_inst_get, + Field_fld_inst_23_16_Slot_inst_get, + Field_fld_inst_4_4_Slot_inst_get, + Field_fld_inst_5_4_Slot_inst_get, + Field_fld_inst_7_4_Slot_inst_get, + Field_fld_inst_7_6_Slot_inst_get, + Field_fld_inst_7_7_Slot_inst_get, + Field_fld_inst_9_8_Slot_inst_get, + Field_bitindex_Slot_inst_get, + Field_s3to1_Slot_inst_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_s8_Slot_inst_set, + Field_imms8_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_r_disp_Slot_inst_set, + Field_r_3_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst_set, + Field_s2_Slot_inst_set, + Field_r2_Slot_inst_set, + Field_t4_Slot_inst_set, + Field_s4_Slot_inst_set, + Field_r4_Slot_inst_set, + Field_t8_Slot_inst_set, + Field_r8_Slot_inst_set, + Field_xt_wbr15_imm_Slot_inst_set, + Field_xt_wbr18_imm_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_inst_11_8_Slot_inst_set, + Field_fld_inst_12_12_Slot_inst_set, + Field_fld_inst_12_8_Slot_inst_set, + Field_fld_inst_13_8_Slot_inst_set, + Field_fld_inst_15_12_Slot_inst_set, + Field_fld_inst_19_17_Slot_inst_set, + Field_fld_inst_19_18_Slot_inst_set, + Field_fld_inst_23_12_Slot_inst_set, + Field_fld_inst_23_16_Slot_inst_set, + Field_fld_inst_4_4_Slot_inst_set, + Field_fld_inst_5_4_Slot_inst_set, + Field_fld_inst_7_4_Slot_inst_set, + Field_fld_inst_7_6_Slot_inst_set, + Field_fld_inst_7_7_Slot_inst_set, + Field_fld_inst_9_8_Slot_inst_set, + Field_bitindex_Slot_inst_set, + Field_s3to1_Slot_inst_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_get, + 0, + 0, + Field_r_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_set, + 0, + 0, + Field_r_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, 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+ 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_get, + 0, + 0, + Field_r_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_inst16b_12_Slot_inst16b_get, + Field_ae_fld_inst16b_15_13_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_set, + 0, + 0, + Field_r_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_inst16b_12_Slot_inst16b_set, + Field_ae_fld_inst16b_15_13_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot0_get_field_fns[] = { + Field_t_Slot_ae_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot0_get, + Field_s_Slot_ae_slot0_get, + Field_s8_Slot_ae_slot0_get, + 0, + Field_imm12b_Slot_ae_slot0_get, + Field_imm16_Slot_ae_slot0_get, + 0, + 0, + Field_offset_Slot_ae_slot0_get, + 0, + 0, + Field_op2_Slot_ae_slot0_get, + Field_r_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae_slot0_get, + Field_sal_Slot_ae_slot0_get, + Field_sargt_Slot_ae_slot0_get, + 0, + Field_sas_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae_slot0_get, + 0, + Field_r2_Slot_ae_slot0_get, + Field_t4_Slot_ae_slot0_get, + Field_s4_Slot_ae_slot0_get, + Field_r4_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_art_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_d1_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcmp_br4t_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcnv_arr_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcnv_art_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot0_get, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae_slot0_get, + Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_a_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_su_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_vu_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_x_Slot_ae_slot0_get, + Field_fld_ae_sem_pks_d_Slot_ae_slot0_get, + Field_fld_ae_sem_pks_pos_Slot_ae_slot0_get, + Field_fld_ae_sem_pks_s_Slot_ae_slot0_get, + Field_fld_ae_sem_rng_v0_Slot_ae_slot0_get, + Field_fld_ae_sem_rng_v1_Slot_ae_slot0_get, + Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_a_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_a0_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_d_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_d0_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_d1_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_da_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_i16_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_i32_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_i64_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_imm32_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_imm8_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_sd_Slot_ae_slot0_get, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae_slot0_get, + Field_fld_ae_sem_sp32cvt_art_Slot_ae_slot0_get, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae_slot0_get, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae_slot0_get, + Field_fld_ae_sem_spmisc_brt_Slot_ae_slot0_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot0_get, + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get, + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get, + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_10_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_6_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_9_Slot_ae_slot0_get, + Field_fld_ae_slot0_14_12_Slot_ae_slot0_get, + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_10_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_13_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get, + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get, + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get, + Field_fld_ae_slot0_18_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_19_12_Slot_ae_slot0_get, + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get, + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get, + Field_fld_ae_slot0_19_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_1_1_Slot_ae_slot0_get, + Field_fld_ae_slot0_20_16_Slot_ae_slot0_get, + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get, + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get, + Field_fld_ae_slot0_23_17_Slot_ae_slot0_get, + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get, + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_10_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_12_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_14_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_15_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_16_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_17_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_19_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_21_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_22_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_24_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_26_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_27_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_4_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get, + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get, + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get, + Field_fld_ae_slot0_4_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get, + Field_fld_ae_slot0_5_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get, + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get, + Field_fld_ae_slot0_7_3_Slot_ae_slot0_get, + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get, + Field_fld_ae_slot0_8_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_9_4_Slot_ae_slot0_get, + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot0_set_field_fns[] = { + Field_t_Slot_ae_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot0_set, + Field_s_Slot_ae_slot0_set, + Field_s8_Slot_ae_slot0_set, + 0, + Field_imm12b_Slot_ae_slot0_set, + Field_imm16_Slot_ae_slot0_set, + 0, + 0, + Field_offset_Slot_ae_slot0_set, + 0, + 0, + Field_op2_Slot_ae_slot0_set, + Field_r_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae_slot0_set, + Field_sal_Slot_ae_slot0_set, + Field_sargt_Slot_ae_slot0_set, + 0, + Field_sas_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae_slot0_set, + 0, + Field_r2_Slot_ae_slot0_set, + Field_t4_Slot_ae_slot0_set, + Field_s4_Slot_ae_slot0_set, + Field_r4_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_art_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_d1_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcmp_br4t_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcnv_arr_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcnv_art_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot0_set, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae_slot0_set, + Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_a_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_su_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_vu_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_x_Slot_ae_slot0_set, + Field_fld_ae_sem_pks_d_Slot_ae_slot0_set, + Field_fld_ae_sem_pks_pos_Slot_ae_slot0_set, + Field_fld_ae_sem_pks_s_Slot_ae_slot0_set, + Field_fld_ae_sem_rng_v0_Slot_ae_slot0_set, + Field_fld_ae_sem_rng_v1_Slot_ae_slot0_set, + Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_a_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_a0_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_d_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_d0_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_d1_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_da_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_i16_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_i32_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_i64_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_imm32_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_imm8_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_sd_Slot_ae_slot0_set, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae_slot0_set, + Field_fld_ae_sem_sp32cvt_art_Slot_ae_slot0_set, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae_slot0_set, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae_slot0_set, + Field_fld_ae_sem_spmisc_brt_Slot_ae_slot0_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot0_set, + Field_fld_ae_slot0_11_10_Slot_ae_slot0_set, + Field_fld_ae_slot0_11_11_Slot_ae_slot0_set, + Field_fld_ae_slot0_11_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_11_9_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_10_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_12_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_2_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_6_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_9_Slot_ae_slot0_set, + Field_fld_ae_slot0_14_12_Slot_ae_slot0_set, + Field_fld_ae_slot0_14_13_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_10_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_12_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_13_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_14_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_15_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_16_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_17_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_18_13_Slot_ae_slot0_set, + Field_fld_ae_slot0_18_15_Slot_ae_slot0_set, + Field_fld_ae_slot0_18_16_Slot_ae_slot0_set, + Field_fld_ae_slot0_18_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_19_12_Slot_ae_slot0_set, + Field_fld_ae_slot0_19_15_Slot_ae_slot0_set, + Field_fld_ae_slot0_19_19_Slot_ae_slot0_set, + Field_fld_ae_slot0_19_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_1_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_1_1_Slot_ae_slot0_set, + Field_fld_ae_slot0_20_16_Slot_ae_slot0_set, + Field_fld_ae_slot0_20_20_Slot_ae_slot0_set, + Field_fld_ae_slot0_23_15_Slot_ae_slot0_set, + Field_fld_ae_slot0_23_17_Slot_ae_slot0_set, + Field_fld_ae_slot0_23_19_Slot_ae_slot0_set, + Field_fld_ae_slot0_23_22_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_10_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_12_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_14_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_15_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_16_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_17_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_19_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_21_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_22_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_24_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_26_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_27_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_4_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_3_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_3_1_Slot_ae_slot0_set, + Field_fld_ae_slot0_3_2_Slot_ae_slot0_set, + Field_fld_ae_slot0_3_3_Slot_ae_slot0_set, + Field_fld_ae_slot0_4_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_4_4_Slot_ae_slot0_set, + Field_fld_ae_slot0_5_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_5_4_Slot_ae_slot0_set, + Field_fld_ae_slot0_7_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_7_2_Slot_ae_slot0_set, + Field_fld_ae_slot0_7_3_Slot_ae_slot0_set, + Field_fld_ae_slot0_7_4_Slot_ae_slot0_set, + Field_fld_ae_slot0_8_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_9_4_Slot_ae_slot0_set, + Field_fld_ae_slot0_9_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_9_9_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot1_get_field_fns[] = { + Field_t_Slot_ae_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot1_get, + Field_s_Slot_ae_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae_slot1_get, + Field_r_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae_slot1_get, + Field_sal_Slot_ae_slot1_get, + Field_sargt_Slot_ae_slot1_get, + 0, + Field_sas_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot1_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot1_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot1_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_a_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_0_0_Slot_ae_slot1_get, + Field_fld_ae_slot1_12_8_Slot_ae_slot1_get, + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get, + Field_fld_ae_slot1_17_17_Slot_ae_slot1_get, + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_1_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_12_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_13_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_16_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_17_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_18_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_20_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_22_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_23_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_8_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_9_Slot_ae_slot1_get, + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get, + Field_fld_ae_slot1_3_2_Slot_ae_slot1_get, + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get, + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot1_set_field_fns[] = { + Field_t_Slot_ae_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot1_set, + Field_s_Slot_ae_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae_slot1_set, + Field_r_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae_slot1_set, + Field_sal_Slot_ae_slot1_set, + Field_sargt_Slot_ae_slot1_set, + 0, + Field_sas_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot1_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot1_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot1_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_a_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_0_0_Slot_ae_slot1_set, + Field_fld_ae_slot1_12_8_Slot_ae_slot1_set, + Field_fld_ae_slot1_17_13_Slot_ae_slot1_set, + Field_fld_ae_slot1_17_17_Slot_ae_slot1_set, + Field_fld_ae_slot1_17_8_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_1_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_12_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_13_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_16_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_17_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_18_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_20_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_22_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_23_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_8_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_9_Slot_ae_slot1_set, + Field_fld_ae_slot1_3_0_Slot_ae_slot1_set, + Field_fld_ae_slot1_3_2_Slot_ae_slot1_set, + Field_fld_ae_slot1_3_3_Slot_ae_slot1_set, + Field_fld_ae_slot1_7_4_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot2_get, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot2_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae_slot2_get, + Field_fld_ae_sem_pks_pos_Slot_ae_slot2_get, + Field_fld_ae_sem_pks_s_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae_slot2_get, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot2_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae_slot2_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_hpcnv_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_hpfma_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_get, + Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot2_get, + Field_fld_ae_sem_multiply_d0_Slot_ae_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae_slot2_get, + Field_fld_ae_sem_multiply_q1_Slot_ae_slot2_get, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae_slot2_get, + Field_fld_ae_sem_reduction_sort_v_Slot_ae_slot2_get, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae_slot2_get, + Field_fld_ae_sem_select_isel_Slot_ae_slot2_get, + Field_fld_ae_sem_select_ss_Slot_ae_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_select_vu_Slot_ae_slot2_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_vp_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot2_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot2_get, + Field_fld_ae_slot2_14_0_Slot_ae_slot2_get, + Field_fld_ae_slot2_14_10_Slot_ae_slot2_get, + Field_fld_ae_slot2_14_14_Slot_ae_slot2_get, + Field_fld_ae_slot2_14_5_Slot_ae_slot2_get, + Field_fld_ae_slot2_16_15_Slot_ae_slot2_get, + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_15_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_17_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_19_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_20_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_25_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_4_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_5_Slot_ae_slot2_get, + Field_fld_ae_slot2_3_0_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_1_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_2_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_6_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_8_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot2_set, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot2_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae_slot2_set, + Field_fld_ae_sem_pks_pos_Slot_ae_slot2_set, + Field_fld_ae_sem_pks_s_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae_slot2_set, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot2_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae_slot2_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_hpcnv_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_hpfma_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_set, + Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot2_set, + Field_fld_ae_sem_multiply_d0_Slot_ae_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae_slot2_set, + Field_fld_ae_sem_multiply_q1_Slot_ae_slot2_set, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae_slot2_set, + Field_fld_ae_sem_reduction_sort_v_Slot_ae_slot2_set, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae_slot2_set, + Field_fld_ae_sem_select_isel_Slot_ae_slot2_set, + Field_fld_ae_sem_select_ss_Slot_ae_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_select_vu_Slot_ae_slot2_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_vp_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot2_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot2_set, + Field_fld_ae_slot2_14_0_Slot_ae_slot2_set, + Field_fld_ae_slot2_14_10_Slot_ae_slot2_set, + Field_fld_ae_slot2_14_14_Slot_ae_slot2_set, + Field_fld_ae_slot2_14_5_Slot_ae_slot2_set, + Field_fld_ae_slot2_16_15_Slot_ae_slot2_set, + Field_fld_ae_slot2_19_15_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_15_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_17_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_19_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_20_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_25_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_4_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_5_Slot_ae_slot2_set, + Field_fld_ae_slot2_3_0_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_0_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_1_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_2_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_5_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_6_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_7_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_8_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r4_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot3_get, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot3_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot3_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_d_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_d0_Slot_ae_slot3_get, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_i32_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_i64_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae_slot3_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_get, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot3_get, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot3_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae_slot3_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae_slot3_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae_slot3_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae_slot3_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_d0_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_d2_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_q0_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_q1_Slot_ae_slot3_get, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae_slot3_get, + Field_fld_ae_sem_select_ss_Slot_ae_slot3_get, + Field_fld_ae_sem_select_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_select_vs_Slot_ae_slot3_get, + Field_fld_ae_sem_select_vt_Slot_ae_slot3_get, + Field_fld_ae_sem_select_vu_Slot_ae_slot3_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot3_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot3_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_vp_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_vs_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_vt_Slot_ae_slot3_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot3_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae_slot3_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_imm_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_d1_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_d3_Slot_ae_slot3_get, + Field_fld_ae_sem_rng_d_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_e_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_i8_Slot_ae_slot3_get, + Field_fld_ae_slot3_11_0_Slot_ae_slot3_get, + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get, + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get, + Field_fld_ae_slot3_14_12_Slot_ae_slot3_get, + Field_fld_ae_slot3_14_13_Slot_ae_slot3_get, + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_17_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_18_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_19_Slot_ae_slot3_get, + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get, + Field_fld_ae_slot3_24_19_Slot_ae_slot3_get, + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_12_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_16_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_19_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_20_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_22_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_25_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_30_Slot_ae_slot3_get, + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get, + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get, + Field_fld_ae_slot3_9_1_Slot_ae_slot3_get, + Field_fld_ae_slot3_9_3_Slot_ae_slot3_get, + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r4_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot3_set, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot3_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot3_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_d_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_d0_Slot_ae_slot3_set, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_i32_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_i64_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae_slot3_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_set, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot3_set, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot3_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae_slot3_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae_slot3_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae_slot3_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae_slot3_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_d0_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_d2_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_q0_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_q1_Slot_ae_slot3_set, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae_slot3_set, + Field_fld_ae_sem_select_ss_Slot_ae_slot3_set, + Field_fld_ae_sem_select_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_select_vs_Slot_ae_slot3_set, + Field_fld_ae_sem_select_vt_Slot_ae_slot3_set, + Field_fld_ae_sem_select_vu_Slot_ae_slot3_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot3_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot3_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_vp_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_vs_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_vt_Slot_ae_slot3_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot3_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae_slot3_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_imm_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_d1_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_d3_Slot_ae_slot3_set, + Field_fld_ae_sem_rng_d_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_e_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_i8_Slot_ae_slot3_set, + Field_fld_ae_slot3_11_0_Slot_ae_slot3_set, + Field_fld_ae_slot3_14_0_Slot_ae_slot3_set, + Field_fld_ae_slot3_14_10_Slot_ae_slot3_set, + Field_fld_ae_slot3_14_12_Slot_ae_slot3_set, + Field_fld_ae_slot3_14_13_Slot_ae_slot3_set, + Field_fld_ae_slot3_16_13_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_0_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_10_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_15_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_17_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_18_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_19_Slot_ae_slot3_set, + Field_fld_ae_slot3_24_10_Slot_ae_slot3_set, + Field_fld_ae_slot3_24_19_Slot_ae_slot3_set, + Field_fld_ae_slot3_24_20_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_12_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_16_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_19_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_20_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_22_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_25_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_30_Slot_ae_slot3_set, + Field_fld_ae_slot3_4_0_Slot_ae_slot3_set, + Field_fld_ae_slot3_9_0_Slot_ae_slot3_set, + Field_fld_ae_slot3_9_1_Slot_ae_slot3_set, + Field_fld_ae_slot3_9_3_Slot_ae_slot3_set, + Field_fld_ae_slot3_9_5_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae2_slot0_get_field_fns[] = { + Field_t_Slot_ae2_slot0_get, + 0, + Field_bbi_Slot_ae2_slot0_get, + 0, + Field_imm8_Slot_ae2_slot0_get, + Field_s_Slot_ae2_slot0_get, + Field_s8_Slot_ae2_slot0_get, + 0, + Field_imm12b_Slot_ae2_slot0_get, + Field_imm16_Slot_ae2_slot0_get, + 0, + 0, + Field_offset_Slot_ae2_slot0_get, + 0, + 0, + Field_op2_Slot_ae2_slot0_get, + Field_r_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot0_get, + Field_sal_Slot_ae2_slot0_get, + Field_sargt_Slot_ae2_slot0_get, + 0, + Field_sas_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae2_slot0_get, + 0, + Field_r2_Slot_ae2_slot0_get, + Field_t4_Slot_ae2_slot0_get, + Field_s4_Slot_ae2_slot0_get, + Field_r4_Slot_ae2_slot0_get, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae2_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_art_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_ds_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_d1_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_hpcnv_arr_Slot_ae2_slot0_get, + Field_fld_ae_sem_hpcnv_art_Slot_ae2_slot0_get, + Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae2_slot0_get, + Field_fld_ae_sem_hpcnv_vr_Slot_ae2_slot0_get, + Field_fld_ae_sem_hpcnv_vt_Slot_ae2_slot0_get, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae2_slot0_get, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae2_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_su_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_vu_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot0_get, + Field_fld_ae_sem_pks_d_Slot_ae2_slot0_get, + Field_fld_ae_sem_pks_pos_Slot_ae2_slot0_get, + Field_fld_ae_sem_pks_s_Slot_ae2_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_a0_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_d_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_d0_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_d1_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_da_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_i16_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_i32_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_i64_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_imm32_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_imm8_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_sd_Slot_ae2_slot0_get, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae2_slot0_get, + Field_fld_ae_sem_sp32cvt_art_Slot_ae2_slot0_get, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae2_slot0_get, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae2_slot0_get, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae2_slot0_get, + Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot0_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot0_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_12_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_12_2_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_14_8_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_4_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_18_17_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_26_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae2_slot0_set_field_fns[] = { + Field_t_Slot_ae2_slot0_set, + 0, + Field_bbi_Slot_ae2_slot0_set, + 0, + Field_imm8_Slot_ae2_slot0_set, + Field_s_Slot_ae2_slot0_set, + Field_s8_Slot_ae2_slot0_set, + 0, + Field_imm12b_Slot_ae2_slot0_set, + Field_imm16_Slot_ae2_slot0_set, + 0, + 0, + Field_offset_Slot_ae2_slot0_set, + 0, + 0, + Field_op2_Slot_ae2_slot0_set, + Field_r_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot0_set, + Field_sal_Slot_ae2_slot0_set, + Field_sargt_Slot_ae2_slot0_set, + 0, + Field_sas_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae2_slot0_set, + 0, + Field_r2_Slot_ae2_slot0_set, + Field_t4_Slot_ae2_slot0_set, + Field_s4_Slot_ae2_slot0_set, + Field_r4_Slot_ae2_slot0_set, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae2_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_art_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_ds_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_d1_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_hpcnv_arr_Slot_ae2_slot0_set, + Field_fld_ae_sem_hpcnv_art_Slot_ae2_slot0_set, + Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae2_slot0_set, + Field_fld_ae_sem_hpcnv_vr_Slot_ae2_slot0_set, + Field_fld_ae_sem_hpcnv_vt_Slot_ae2_slot0_set, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae2_slot0_set, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae2_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_su_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_vu_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot0_set, + Field_fld_ae_sem_pks_d_Slot_ae2_slot0_set, + Field_fld_ae_sem_pks_pos_Slot_ae2_slot0_set, + Field_fld_ae_sem_pks_s_Slot_ae2_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_a0_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_d_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_d0_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_d1_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_da_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_i16_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_i32_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_i64_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_imm32_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_imm8_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_sd_Slot_ae2_slot0_set, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae2_slot0_set, + Field_fld_ae_sem_sp32cvt_art_Slot_ae2_slot0_set, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae2_slot0_set, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae2_slot0_set, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae2_slot0_set, + Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot0_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot0_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_12_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_12_2_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_14_8_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_4_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_18_17_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_26_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae2_slot1_get_field_fns[] = { + Field_t_Slot_ae2_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae2_slot1_get, + Field_s_Slot_ae2_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae2_slot1_get, + Field_r_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot1_get, + Field_sal_Slot_ae2_slot1_get, + Field_sargt_Slot_ae2_slot1_get, + 0, + Field_sas_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot1_get, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot1_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot1_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot1_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot1_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot1_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_11_0_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_17_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_18_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_22_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_23_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_3_2_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_3_3_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae2_slot1_set_field_fns[] = { + Field_t_Slot_ae2_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae2_slot1_set, + Field_s_Slot_ae2_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae2_slot1_set, + Field_r_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot1_set, + Field_sal_Slot_ae2_slot1_set, + Field_sargt_Slot_ae2_slot1_set, + 0, + Field_sas_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot1_set, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot1_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot1_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot1_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot1_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot1_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_11_0_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_17_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_18_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_22_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_23_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_3_2_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_3_3_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae2_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot2_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot2_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot2_get, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae2_slot2_get, + Field_fld_ae_sem_pks_pos_Slot_ae2_slot2_get, + Field_fld_ae_sem_pks_s_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot2_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot2_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot2_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot2_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot2_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot2_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae2_slot2_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae2_slot2_get, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae2_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae2_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae2_slot2_get, + Field_fld_ae_sem_multiply_q1_Slot_ae2_slot2_get, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae2_slot2_get, + Field_fld_ae_sem_reduction_sort_v_Slot_ae2_slot2_get, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_isel_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_ss_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_vu_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_vp_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_vs_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_vt_Slot_ae2_slot2_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae2_slot2_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae2_slot2_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_17_0_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_26_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_28_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vp_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vq_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae2_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot2_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot2_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot2_set, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae2_slot2_set, + Field_fld_ae_sem_pks_pos_Slot_ae2_slot2_set, + Field_fld_ae_sem_pks_s_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot2_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot2_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot2_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot2_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot2_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot2_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae2_slot2_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae2_slot2_set, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae2_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae2_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae2_slot2_set, + Field_fld_ae_sem_multiply_q1_Slot_ae2_slot2_set, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae2_slot2_set, + Field_fld_ae_sem_reduction_sort_v_Slot_ae2_slot2_set, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_isel_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_ss_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_vu_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_vp_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_vs_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_vt_Slot_ae2_slot2_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae2_slot2_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae2_slot2_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_17_0_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_26_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_28_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vp_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vq_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae3_slot0_get_field_fns[] = { + Field_t_Slot_ae3_slot0_get, + 0, + Field_bbi_Slot_ae3_slot0_get, + 0, + Field_imm8_Slot_ae3_slot0_get, + Field_s_Slot_ae3_slot0_get, + Field_s8_Slot_ae3_slot0_get, + 0, + Field_imm12b_Slot_ae3_slot0_get, + Field_imm16_Slot_ae3_slot0_get, + 0, + 0, + Field_offset_Slot_ae3_slot0_get, + 0, + 0, + Field_op2_Slot_ae3_slot0_get, + Field_r_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot0_get, + Field_sal_Slot_ae3_slot0_get, + Field_sargt_Slot_ae3_slot0_get, + 0, + Field_sas_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae3_slot0_get, + 0, + Field_r2_Slot_ae3_slot0_get, + Field_t4_Slot_ae3_slot0_get, + Field_s4_Slot_ae3_slot0_get, + Field_r4_Slot_ae3_slot0_get, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae3_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae3_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae3_slot0_get, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae3_slot0_get, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_su_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_vu_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae3_slot0_get, + Field_fld_ae_sem_shift_d_Slot_ae3_slot0_get, + Field_fld_ae_sem_shift_d0_Slot_ae3_slot0_get, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_16_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_7_2_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_9_4_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot0_get, + Field_fld_ae_sem_sb_loads_stores_iba2_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae3_slot0_set_field_fns[] = { + Field_t_Slot_ae3_slot0_set, + 0, + Field_bbi_Slot_ae3_slot0_set, + 0, + Field_imm8_Slot_ae3_slot0_set, + Field_s_Slot_ae3_slot0_set, + Field_s8_Slot_ae3_slot0_set, + 0, + Field_imm12b_Slot_ae3_slot0_set, + Field_imm16_Slot_ae3_slot0_set, + 0, + 0, + Field_offset_Slot_ae3_slot0_set, + 0, + 0, + Field_op2_Slot_ae3_slot0_set, + Field_r_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot0_set, + Field_sal_Slot_ae3_slot0_set, + Field_sargt_Slot_ae3_slot0_set, + 0, + Field_sas_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae3_slot0_set, + 0, + Field_r2_Slot_ae3_slot0_set, + Field_t4_Slot_ae3_slot0_set, + Field_s4_Slot_ae3_slot0_set, + Field_r4_Slot_ae3_slot0_set, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae3_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae3_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae3_slot0_set, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae3_slot0_set, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_su_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_vu_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae3_slot0_set, + Field_fld_ae_sem_shift_d_Slot_ae3_slot0_set, + Field_fld_ae_sem_shift_d0_Slot_ae3_slot0_set, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_16_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_7_2_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_9_4_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot0_set, + Field_fld_ae_sem_sb_loads_stores_iba2_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae3_slot1_get_field_fns[] = { + Field_t_Slot_ae3_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae3_slot1_get, + Field_s_Slot_ae3_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae3_slot1_get, + Field_r_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot1_get, + Field_sal_Slot_ae3_slot1_get, + Field_sargt_Slot_ae3_slot1_get, + 0, + Field_sas_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot1_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot1_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot1_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot1_get, + 0, + Field_fld_ae3_slot1_23_0_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_11_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_17_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_19_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_9_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_3_1_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae3_slot1_set_field_fns[] = { + Field_t_Slot_ae3_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae3_slot1_set, + Field_s_Slot_ae3_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae3_slot1_set, + Field_r_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot1_set, + Field_sal_Slot_ae3_slot1_set, + Field_sargt_Slot_ae3_slot1_set, + 0, + Field_sas_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot1_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot1_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot1_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot1_set, + 0, + Field_fld_ae3_slot1_23_0_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_11_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_17_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_19_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_9_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_3_1_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae5_slot0_get_field_fns[] = { + Field_t_Slot_ae5_slot0_get, + 0, + Field_bbi_Slot_ae5_slot0_get, + 0, + Field_imm8_Slot_ae5_slot0_get, + Field_s_Slot_ae5_slot0_get, + Field_s8_Slot_ae5_slot0_get, + 0, + Field_imm12b_Slot_ae5_slot0_get, + Field_imm16_Slot_ae5_slot0_get, + 0, + 0, + Field_offset_Slot_ae5_slot0_get, + 0, + 0, + Field_op2_Slot_ae5_slot0_get, + Field_r_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae5_slot0_get, + Field_sal_Slot_ae5_slot0_get, + Field_sargt_Slot_ae5_slot0_get, + 0, + Field_sas_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae5_slot0_get, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae5_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot0_get, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae5_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae5_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae5_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae5_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae5_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae5_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_su_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_vu_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_x_Slot_ae5_slot0_get, + Field_fld_ae_sem_pks_d_Slot_ae5_slot0_get, + Field_fld_ae_sem_pks_pos_Slot_ae5_slot0_get, + Field_fld_ae_sem_pks_s_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae5_slot0_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot0_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_ardecnorm16_ar_u_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_12_6_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_17_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_19_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_6_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_7_0_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get, + Field_fld_ae_sem_lb_db_ops_ar_u_Slot_ae5_slot0_get, + Field_fld_ae_sem_lb_db_ops_iba_Slot_ae5_slot0_get, + Field_fld_ae_sem_rng_a_Slot_ae5_slot0_get, + Field_fld_ae_sem_rng_art_Slot_ae5_slot0_get, + Field_fld_ae_sem_rng_i2_Slot_ae5_slot0_get, + Field_fld_ae_sem_rng_imm2_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae5_slot0_set_field_fns[] = { + Field_t_Slot_ae5_slot0_set, + 0, + Field_bbi_Slot_ae5_slot0_set, + 0, + Field_imm8_Slot_ae5_slot0_set, + Field_s_Slot_ae5_slot0_set, + Field_s8_Slot_ae5_slot0_set, + 0, + Field_imm12b_Slot_ae5_slot0_set, + Field_imm16_Slot_ae5_slot0_set, + 0, + 0, + Field_offset_Slot_ae5_slot0_set, + 0, + 0, + Field_op2_Slot_ae5_slot0_set, + Field_r_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae5_slot0_set, + Field_sal_Slot_ae5_slot0_set, + Field_sargt_Slot_ae5_slot0_set, + 0, + Field_sas_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae5_slot0_set, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae5_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot0_set, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae5_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae5_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae5_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae5_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae5_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae5_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_su_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_vu_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_x_Slot_ae5_slot0_set, + Field_fld_ae_sem_pks_d_Slot_ae5_slot0_set, + Field_fld_ae_sem_pks_pos_Slot_ae5_slot0_set, + Field_fld_ae_sem_pks_s_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae5_slot0_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot0_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_ardecnorm16_ar_u_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_12_6_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_17_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_19_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_6_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_7_0_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_set, + Field_fld_ae_sem_lb_db_ops_ar_u_Slot_ae5_slot0_set, + Field_fld_ae_sem_lb_db_ops_iba_Slot_ae5_slot0_set, + Field_fld_ae_sem_rng_a_Slot_ae5_slot0_set, + Field_fld_ae_sem_rng_art_Slot_ae5_slot0_set, + Field_fld_ae_sem_rng_i2_Slot_ae5_slot0_set, + Field_fld_ae_sem_rng_imm2_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae5_slot1_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot1_1_0_Slot_ae5_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae5_slot1_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot1_1_0_Slot_ae5_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae5_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot2_get, + 0, + Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot2_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot2_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae5_slot2_get, + Field_fld_ae_sem_pks_pos_Slot_ae5_slot2_get, + Field_fld_ae_sem_pks_s_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae5_slot2_get, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae5_slot2_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae5_slot2_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae5_slot2_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae5_slot2_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae5_slot2_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae5_slot2_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae5_slot2_get, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae5_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae5_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae5_slot2_get, + Field_fld_ae_sem_multiply_q1_Slot_ae5_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae5_slot2_get, + Field_fld_ae_sem_select_ss_Slot_ae5_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae5_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae5_slot2_get, + 0, + Field_fld_ae_sem_spaddsub_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae5_slot2_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae5_slot2_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae5_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_spfma_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_spfma_vs_Slot_ae5_slot2_get, + Field_fld_ae_sem_spfma_vt_Slot_ae5_slot2_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae5_slot2_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae5_slot2_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_14_5_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_24_0_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_9_7_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae5_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot2_set, + 0, + Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot2_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot2_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae5_slot2_set, + Field_fld_ae_sem_pks_pos_Slot_ae5_slot2_set, + Field_fld_ae_sem_pks_s_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae5_slot2_set, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae5_slot2_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae5_slot2_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae5_slot2_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae5_slot2_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae5_slot2_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae5_slot2_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae5_slot2_set, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae5_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae5_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae5_slot2_set, + Field_fld_ae_sem_multiply_q1_Slot_ae5_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae5_slot2_set, + Field_fld_ae_sem_select_ss_Slot_ae5_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae5_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae5_slot2_set, + 0, + Field_fld_ae_sem_spaddsub_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae5_slot2_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae5_slot2_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae5_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_spfma_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_spfma_vs_Slot_ae5_slot2_set, + Field_fld_ae_sem_spfma_vt_Slot_ae5_slot2_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae5_slot2_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae5_slot2_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_14_5_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_24_0_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_9_7_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot0_get_field_fns[] = { + Field_t_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae6_slot0_get, + 0, + Field_r2_Slot_ae6_slot0_get, + Field_t4_Slot_ae6_slot0_get, + 0, + Field_r4_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot0_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot0_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot0_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot0_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot0_get, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot0_get, + Field_fld_ae_sem_pks_d_Slot_ae6_slot0_get, + Field_fld_ae_sem_pks_pos_Slot_ae6_slot0_get, + Field_fld_ae_sem_pks_s_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_5_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_7_4_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot0_set_field_fns[] = { + Field_t_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae6_slot0_set, + 0, + Field_r2_Slot_ae6_slot0_set, + Field_t4_Slot_ae6_slot0_set, + 0, + Field_r4_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot0_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot0_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot0_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot0_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot0_set, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot0_set, + Field_fld_ae_sem_pks_d_Slot_ae6_slot0_set, + Field_fld_ae_sem_pks_pos_Slot_ae6_slot0_set, + Field_fld_ae_sem_pks_s_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_5_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_7_4_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot1_get_field_fns[] = { + Field_t_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + Field_s_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae6_slot1_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae6_slot1_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot1_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot1_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot1_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae6_slot1_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae6_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae6_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot1_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae6_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae6_slot1_get, + Field_fld_ae_sem_shift_d_Slot_ae6_slot1_get, + Field_fld_ae_sem_shift_d0_Slot_ae6_slot1_get, + 0, + Field_fld_ae_sem_shift_da_Slot_ae6_slot1_get, + Field_fld_ae_sem_shift_i16_Slot_ae6_slot1_get, + Field_fld_ae_sem_shift_i32_Slot_ae6_slot1_get, + Field_fld_ae_sem_shift_i64_Slot_ae6_slot1_get, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_21_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_3_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_2_0_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_9_5_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot1_set_field_fns[] = { + Field_t_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + Field_s_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae6_slot1_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae6_slot1_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot1_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot1_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot1_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae6_slot1_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae6_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae6_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot1_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae6_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae6_slot1_set, + Field_fld_ae_sem_shift_d_Slot_ae6_slot1_set, + Field_fld_ae_sem_shift_d0_Slot_ae6_slot1_set, + 0, + Field_fld_ae_sem_shift_da_Slot_ae6_slot1_set, + Field_fld_ae_sem_shift_i16_Slot_ae6_slot1_set, + Field_fld_ae_sem_shift_i32_Slot_ae6_slot1_set, + Field_fld_ae_sem_shift_i64_Slot_ae6_slot1_set, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_21_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_3_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_2_0_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_9_5_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot2_get_field_fns[] = { + Field_t_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae6_slot2_get, + 0, + 0, + Field_t4_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot2_get, + 0, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot2_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae6_slot2_get, + Field_fld_ae_sem_pks_pos_Slot_ae6_slot2_get, + Field_fld_ae_sem_pks_s_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae6_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae6_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_24_0_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_24_10_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_24_20_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot2_set_field_fns[] = { + Field_t_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae6_slot2_set, + 0, + 0, + Field_t4_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot2_set, + 0, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot2_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae6_slot2_set, + Field_fld_ae_sem_pks_pos_Slot_ae6_slot2_set, + Field_fld_ae_sem_pks_s_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae6_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae6_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_24_0_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_24_10_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_24_20_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r2_Slot_ae6_slot3_get, + 0, + 0, + Field_r4_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot3_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot3_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot3_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot3_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot3_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot3_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae6_slot3_get, + Field_fld_ae_sem_multiply_d2_Slot_ae6_slot3_get, + Field_fld_ae_sem_multiply_q0_Slot_ae6_slot3_get, + Field_fld_ae_sem_multiply_q1_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae6_slot3_get, + Field_fld_ae_sem_multiply_d3_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_12_0_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_14_0_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_24_20_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_37_13_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r2_Slot_ae6_slot3_set, + 0, + 0, + Field_r4_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot3_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot3_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot3_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot3_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot3_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot3_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae6_slot3_set, + Field_fld_ae_sem_multiply_d2_Slot_ae6_slot3_set, + Field_fld_ae_sem_multiply_q0_Slot_ae6_slot3_set, + Field_fld_ae_sem_multiply_q1_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae6_slot3_set, + Field_fld_ae_sem_multiply_d3_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_12_0_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_14_0_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_24_20_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_37_13_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot0_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_12_6_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_23_0_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot0_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_12_6_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_23_0_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot1_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_12_6_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_23_0_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot1_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_12_6_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_23_0_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae7_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae7_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae7_slot2_get, + Field_fld_ae_sem_multiply_q1_Slot_ae7_slot2_get, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae7_slot2_get, + Field_fld_ae_sem_reduction_sort_v_Slot_ae7_slot2_get, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_isel_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_ss_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_vu_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae7_slot2_get, + Field_fld_ae_sem_multiply_d3_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot2_11_0_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_14_10_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_36_12_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae7_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae7_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae7_slot2_set, + Field_fld_ae_sem_multiply_q1_Slot_ae7_slot2_set, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae7_slot2_set, + Field_fld_ae_sem_reduction_sort_v_Slot_ae7_slot2_set, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_isel_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_ss_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_vu_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae7_slot2_set, + Field_fld_ae_sem_multiply_d3_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot2_11_0_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_14_10_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_36_12_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae7_slot3_get, + Field_fld_ae_sem_multiply_d2_Slot_ae7_slot3_get, + Field_fld_ae_sem_multiply_q0_Slot_ae7_slot3_get, + Field_fld_ae_sem_multiply_q1_Slot_ae7_slot3_get, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae7_slot3_get, + Field_fld_ae_sem_select_ss_Slot_ae7_slot3_get, + Field_fld_ae_sem_select_vr_Slot_ae7_slot3_get, + Field_fld_ae_sem_select_vs_Slot_ae7_slot3_get, + Field_fld_ae_sem_select_vt_Slot_ae7_slot3_get, + Field_fld_ae_sem_select_vu_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae7_slot3_get, + Field_fld_ae_sem_multiply_d3_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot3_10_0_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_24_10_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_35_11_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_4_0_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae7_slot3_set, + Field_fld_ae_sem_multiply_d2_Slot_ae7_slot3_set, + Field_fld_ae_sem_multiply_q0_Slot_ae7_slot3_set, + Field_fld_ae_sem_multiply_q1_Slot_ae7_slot3_set, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae7_slot3_set, + Field_fld_ae_sem_select_ss_Slot_ae7_slot3_set, + Field_fld_ae_sem_select_vr_Slot_ae7_slot3_set, + Field_fld_ae_sem_select_vs_Slot_ae7_slot3_set, + Field_fld_ae_sem_select_vt_Slot_ae7_slot3_set, + Field_fld_ae_sem_select_vu_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae7_slot3_set, + Field_fld_ae_sem_multiply_d3_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot3_10_0_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_24_10_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_35_11_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_4_0_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae8_slot0_get_field_fns[] = { + Field_t_Slot_ae8_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae8_slot0_get, + Field_s_Slot_ae8_slot0_get, + Field_s8_Slot_ae8_slot0_get, + 0, + Field_imm12b_Slot_ae8_slot0_get, + Field_imm16_Slot_ae8_slot0_get, + 0, + 0, + Field_offset_Slot_ae8_slot0_get, + 0, + 0, + Field_op2_Slot_ae8_slot0_get, + Field_r_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae8_slot0_get, + Field_sal_Slot_ae8_slot0_get, + Field_sargt_Slot_ae8_slot0_get, + 0, + Field_sas_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae8_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae8_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae8_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot0_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_su_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae8_slot0_get, + Field_fld_ae_sem_shift_d_Slot_ae8_slot0_get, + Field_fld_ae_sem_shift_d0_Slot_ae8_slot0_get, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae8_slot0_get, + Field_fld_ae_sem_shift_i32_Slot_ae8_slot0_get, + Field_fld_ae_sem_shift_i64_Slot_ae8_slot0_get, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_13_13_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_17_8_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_21_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_22_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_23_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_7_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_9_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_6_0_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_7_5_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_8_0_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae8_slot0_set_field_fns[] = { + Field_t_Slot_ae8_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae8_slot0_set, + Field_s_Slot_ae8_slot0_set, + Field_s8_Slot_ae8_slot0_set, + 0, + Field_imm12b_Slot_ae8_slot0_set, + Field_imm16_Slot_ae8_slot0_set, + 0, + 0, + Field_offset_Slot_ae8_slot0_set, + 0, + 0, + Field_op2_Slot_ae8_slot0_set, + Field_r_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae8_slot0_set, + Field_sal_Slot_ae8_slot0_set, + Field_sargt_Slot_ae8_slot0_set, + 0, + Field_sas_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae8_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae8_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae8_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot0_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_su_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae8_slot0_set, + Field_fld_ae_sem_shift_d_Slot_ae8_slot0_set, + Field_fld_ae_sem_shift_d0_Slot_ae8_slot0_set, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae8_slot0_set, + Field_fld_ae_sem_shift_i32_Slot_ae8_slot0_set, + Field_fld_ae_sem_shift_i64_Slot_ae8_slot0_set, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_13_13_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_17_8_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_21_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_22_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_23_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_7_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_9_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_6_0_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_7_5_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_8_0_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae8_slot1_get_field_fns[] = { + Field_t_Slot_ae8_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae8_slot1_get, + Field_s_Slot_ae8_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae8_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae8_slot1_get, + Field_r_Slot_ae8_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae8_slot1_get, + Field_sal_Slot_ae8_slot1_get, + Field_sargt_Slot_ae8_slot1_get, + 0, + Field_sas_Slot_ae8_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot1_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_17_15_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_22_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_23_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_5_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_9_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_4_0_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae8_slot1_set_field_fns[] = { + Field_t_Slot_ae8_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae8_slot1_set, + Field_s_Slot_ae8_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae8_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae8_slot1_set, + Field_r_Slot_ae8_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae8_slot1_set, + Field_sal_Slot_ae8_slot1_set, + Field_sargt_Slot_ae8_slot1_set, + 0, + Field_sas_Slot_ae8_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot1_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_17_15_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_22_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_23_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_5_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_9_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_4_0_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae8_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_19_15_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_33_25_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_33_9_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_8_0_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_c0_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_c1_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_c2_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_c3_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_q0_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_q1_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_q2_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_q3_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_v0_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_v1_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_v2_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_v3_Slot_ae8_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae8_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_19_15_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_33_25_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_33_9_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_8_0_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_c0_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_c1_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_c2_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_c3_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_q0_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_q1_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_q2_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_q3_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_v0_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_v1_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_v2_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_v3_Slot_ae8_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae9_slot0_get_field_fns[] = { + Field_t_Slot_ae9_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae9_slot0_get, + Field_s_Slot_ae9_slot0_get, + Field_s8_Slot_ae9_slot0_get, + 0, + Field_imm12b_Slot_ae9_slot0_get, + Field_imm16_Slot_ae9_slot0_get, + 0, + 0, + Field_offset_Slot_ae9_slot0_get, + 0, + 0, + Field_op2_Slot_ae9_slot0_get, + Field_r_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae9_slot0_get, + Field_sal_Slot_ae9_slot0_get, + Field_sargt_Slot_ae9_slot0_get, + 0, + Field_sas_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r2_Slot_ae9_slot0_get, + 0, + Field_s4_Slot_ae9_slot0_get, + Field_r4_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v0_Slot_ae9_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae9_slot0_get, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae9_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae9_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae9_slot0_get, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae9_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_su_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae9_slot0_get, + Field_fld_ae_sem_sp32cvt_art_Slot_ae9_slot0_get, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae9_slot0_get, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae9_slot0_get, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae9_slot0_get, + Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot0_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot0_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_17_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_19_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_22_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_3_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_2_0_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_7_6_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae9_slot0_set_field_fns[] = { + Field_t_Slot_ae9_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae9_slot0_set, + Field_s_Slot_ae9_slot0_set, + Field_s8_Slot_ae9_slot0_set, + 0, + Field_imm12b_Slot_ae9_slot0_set, + Field_imm16_Slot_ae9_slot0_set, + 0, + 0, + Field_offset_Slot_ae9_slot0_set, + 0, + 0, + Field_op2_Slot_ae9_slot0_set, + Field_r_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae9_slot0_set, + Field_sal_Slot_ae9_slot0_set, + Field_sargt_Slot_ae9_slot0_set, + 0, + Field_sas_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r2_Slot_ae9_slot0_set, + 0, + Field_s4_Slot_ae9_slot0_set, + Field_r4_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v0_Slot_ae9_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae9_slot0_set, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae9_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae9_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae9_slot0_set, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae9_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_su_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae9_slot0_set, + Field_fld_ae_sem_sp32cvt_art_Slot_ae9_slot0_set, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae9_slot0_set, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae9_slot0_set, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae9_slot0_set, + Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot0_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot0_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_17_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_19_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_22_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_3_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_2_0_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_7_6_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae9_slot1_get_field_fns[] = { + Field_t_Slot_ae9_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae9_slot1_get, + Field_s_Slot_ae9_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae9_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae9_slot1_get, + Field_r_Slot_ae9_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae9_slot1_get, + Field_sal_Slot_ae9_slot1_get, + Field_sargt_Slot_ae9_slot1_get, + 0, + Field_sas_Slot_ae9_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_1_0_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_17_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_2_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_22_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_23_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_9_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_3_2_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae9_slot1_set_field_fns[] = { + Field_t_Slot_ae9_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae9_slot1_set, + Field_s_Slot_ae9_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae9_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae9_slot1_set, + Field_r_Slot_ae9_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae9_slot1_set, + Field_sal_Slot_ae9_slot1_set, + Field_sargt_Slot_ae9_slot1_set, + 0, + Field_sas_Slot_ae9_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_1_0_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_17_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_2_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_22_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_23_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_9_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_3_2_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae9_slot2_get_field_fns[] = { + Field_t_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae9_slot2_get, + 0, + 0, + Field_t4_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot2_get, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot2_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot2_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot2_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot2_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae9_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae9_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae9_slot2_get, + Field_fld_ae_sem_select_vu_Slot_ae9_slot2_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot2_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot2_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_vp_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_vs_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_vt_Slot_ae9_slot2_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot2_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot2_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spaddsub_vp_Slot_ae9_slot2_get, + Field_fld_ae_sem_spaddsub_vq_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_9_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_8_0_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpfma_vp_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpfma_vu_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_vu_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae9_slot2_set_field_fns[] = { + Field_t_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae9_slot2_set, + 0, + 0, + Field_t4_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot2_set, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot2_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot2_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot2_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot2_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae9_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae9_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae9_slot2_set, + Field_fld_ae_sem_select_vu_Slot_ae9_slot2_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot2_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot2_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_vp_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_vs_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_vt_Slot_ae9_slot2_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot2_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot2_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spaddsub_vp_Slot_ae9_slot2_set, + Field_fld_ae_sem_spaddsub_vq_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_9_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_8_0_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpfma_vp_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpfma_vu_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_vu_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae9_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot3_get, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot3_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot3_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot3_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot3_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot3_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot3_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot3_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot3_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot3_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae9_slot3_get, + Field_fld_ae_sem_select_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_select_vs_Slot_ae9_slot3_get, + Field_fld_ae_sem_select_vt_Slot_ae9_slot3_get, + Field_fld_ae_sem_select_vu_Slot_ae9_slot3_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot3_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot3_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_vp_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_vs_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_vt_Slot_ae9_slot3_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot3_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot3_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spfma_vu_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_7_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_4_4_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_6_0_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae9_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot3_set, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot3_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot3_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot3_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot3_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot3_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot3_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot3_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot3_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot3_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae9_slot3_set, + Field_fld_ae_sem_select_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_select_vs_Slot_ae9_slot3_set, + Field_fld_ae_sem_select_vt_Slot_ae9_slot3_set, + Field_fld_ae_sem_select_vu_Slot_ae9_slot3_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot3_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot3_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_vp_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_vs_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_vt_Slot_ae9_slot3_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot3_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot3_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spfma_vu_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_7_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_4_4_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_6_0_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae10_slot0_get_field_fns[] = { + Field_t_Slot_ae10_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae10_slot0_get, + Field_s_Slot_ae10_slot0_get, + Field_s8_Slot_ae10_slot0_get, + 0, + Field_imm12b_Slot_ae10_slot0_get, + Field_imm16_Slot_ae10_slot0_get, + 0, + 0, + Field_offset_Slot_ae10_slot0_get, + 0, + 0, + Field_op2_Slot_ae10_slot0_get, + Field_r_Slot_ae10_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae10_slot0_get, + Field_sal_Slot_ae10_slot0_get, + Field_sargt_Slot_ae10_slot0_get, + 0, + Field_sas_Slot_ae10_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae10_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot0_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_17_8_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_0_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_17_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_7_6_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae10_slot0_set_field_fns[] = { + Field_t_Slot_ae10_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae10_slot0_set, + Field_s_Slot_ae10_slot0_set, + Field_s8_Slot_ae10_slot0_set, + 0, + Field_imm12b_Slot_ae10_slot0_set, + Field_imm16_Slot_ae10_slot0_set, + 0, + 0, + Field_offset_Slot_ae10_slot0_set, + 0, + 0, + Field_op2_Slot_ae10_slot0_set, + Field_r_Slot_ae10_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae10_slot0_set, + Field_sal_Slot_ae10_slot0_set, + Field_sargt_Slot_ae10_slot0_set, + 0, + Field_sas_Slot_ae10_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae10_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot0_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_17_8_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_0_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_17_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_7_6_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae10_slot1_get_field_fns[] = { + Field_t_Slot_ae10_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae10_slot1_get, + Field_s_Slot_ae10_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae10_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae10_slot1_get, + Field_r_Slot_ae10_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae10_slot1_get, + Field_sal_Slot_ae10_slot1_get, + Field_sargt_Slot_ae10_slot1_get, + 0, + Field_sas_Slot_ae10_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae10_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot1_0_0_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_1_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_17_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_22_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_23_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_9_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_3_2_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae10_slot1_set_field_fns[] = { + Field_t_Slot_ae10_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae10_slot1_set, + Field_s_Slot_ae10_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae10_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae10_slot1_set, + Field_r_Slot_ae10_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae10_slot1_set, + Field_sal_Slot_ae10_slot1_set, + Field_sargt_Slot_ae10_slot1_set, + 0, + Field_sas_Slot_ae10_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae10_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot1_0_0_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_1_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_17_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_22_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_23_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_9_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_3_2_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae10_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot2_get, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot2_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot2_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot2_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot2_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae10_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae10_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae10_slot2_get, + Field_fld_ae_sem_select_vu_Slot_ae10_slot2_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot2_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot2_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vp_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vs_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vt_Slot_ae10_slot2_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot2_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot2_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spaddsub_vp_Slot_ae10_slot2_get, + Field_fld_ae_sem_spaddsub_vq_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vu_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_10_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vq_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae10_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot2_set, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot2_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot2_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot2_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot2_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae10_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae10_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae10_slot2_set, + Field_fld_ae_sem_select_vu_Slot_ae10_slot2_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot2_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot2_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vp_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vs_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vt_Slot_ae10_slot2_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot2_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot2_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spaddsub_vp_Slot_ae10_slot2_set, + Field_fld_ae_sem_spaddsub_vq_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vu_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_10_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vq_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae10_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae10_slot3_get, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot3_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae10_slot3_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae10_slot3_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot3_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot3_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot3_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot3_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot3_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot3_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae10_slot3_get, + Field_fld_ae_sem_select_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_select_vs_Slot_ae10_slot3_get, + Field_fld_ae_sem_select_vt_Slot_ae10_slot3_get, + Field_fld_ae_sem_select_vu_Slot_ae10_slot3_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot3_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot3_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vp_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vs_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vt_Slot_ae10_slot3_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot3_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot3_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot3_get, + Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vu_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vq_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_10_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_4_4_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae10_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae10_slot3_set, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot3_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae10_slot3_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae10_slot3_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot3_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot3_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot3_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot3_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot3_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot3_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae10_slot3_set, + Field_fld_ae_sem_select_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_select_vs_Slot_ae10_slot3_set, + Field_fld_ae_sem_select_vt_Slot_ae10_slot3_set, + Field_fld_ae_sem_select_vu_Slot_ae10_slot3_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot3_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot3_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vp_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vs_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vt_Slot_ae10_slot3_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot3_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot3_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot3_set, + Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vu_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vq_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_10_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_4_4_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot0_get_field_fns[] = { + Field_t_Slot_ae4_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae4_slot0_get, + Field_s_Slot_ae4_slot0_get, + Field_s8_Slot_ae4_slot0_get, + 0, + Field_imm12b_Slot_ae4_slot0_get, + Field_imm16_Slot_ae4_slot0_get, + 0, + 0, + Field_offset_Slot_ae4_slot0_get, + 0, + 0, + Field_op2_Slot_ae4_slot0_get, + Field_r_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae4_slot0_get, + Field_sal_Slot_ae4_slot0_get, + Field_sargt_Slot_ae4_slot0_get, + 0, + Field_sas_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot0_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot0_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot0_22_0_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_17_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_20_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_3_1_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot0_set_field_fns[] = { + Field_t_Slot_ae4_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae4_slot0_set, + Field_s_Slot_ae4_slot0_set, + Field_s8_Slot_ae4_slot0_set, + 0, + Field_imm12b_Slot_ae4_slot0_set, + Field_imm16_Slot_ae4_slot0_set, + 0, + 0, + Field_offset_Slot_ae4_slot0_set, + 0, + 0, + Field_op2_Slot_ae4_slot0_set, + Field_r_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae4_slot0_set, + Field_sal_Slot_ae4_slot0_set, + Field_sargt_Slot_ae4_slot0_set, + 0, + Field_sas_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot0_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot0_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot0_22_0_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_17_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_20_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_3_1_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot1_get_field_fns[] = { + Field_t_Slot_ae4_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae4_slot1_get, + Field_s_Slot_ae4_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae4_slot1_get, + Field_r_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae4_slot1_get, + Field_sal_Slot_ae4_slot1_get, + Field_sargt_Slot_ae4_slot1_get, + 0, + Field_sas_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot1_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot1_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot1_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot1_22_0_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_17_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_3_1_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot1_set_field_fns[] = { + Field_t_Slot_ae4_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae4_slot1_set, + Field_s_Slot_ae4_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae4_slot1_set, + Field_r_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae4_slot1_set, + Field_sal_Slot_ae4_slot1_set, + Field_sargt_Slot_ae4_slot1_set, + 0, + Field_sas_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot1_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot1_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot1_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot1_22_0_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_17_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_3_1_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot2_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot2_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot2_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot2_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae4_slot2_get, + Field_fld_ae_sem_pks_pos_Slot_ae4_slot2_get, + Field_fld_ae_sem_pks_s_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae4_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae4_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot2_23_0_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_23_17_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_4_0_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot2_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot2_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot2_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot2_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae4_slot2_set, + Field_fld_ae_sem_pks_pos_Slot_ae4_slot2_set, + Field_fld_ae_sem_pks_s_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae4_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae4_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot2_23_0_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_23_17_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_4_0_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot3_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot3_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot3_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae4_slot3_get, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot3_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae4_slot3_get, + Field_fld_ae_sem_multiply_d2_Slot_ae4_slot3_get, + Field_fld_ae_sem_multiply_q0_Slot_ae4_slot3_get, + Field_fld_ae_sem_multiply_q1_Slot_ae4_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae4_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot3_14_10_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_19_19_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_19_5_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_27_20_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_27_3_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_2_0_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot3_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot3_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot3_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae4_slot3_set, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot3_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae4_slot3_set, + Field_fld_ae_sem_multiply_d2_Slot_ae4_slot3_set, + Field_fld_ae_sem_multiply_q0_Slot_ae4_slot3_set, + Field_fld_ae_sem_multiply_q1_Slot_ae4_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae4_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot3_14_10_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_19_19_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_19_5_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_27_20_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_27_3_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_2_0_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot4_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot4_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot4_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot4_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot4_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot4_22_0_Slot_ae4_slot4_get, + Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get, + Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get, + Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot4_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot4_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot4_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot4_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot4_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot4_22_0_Slot_ae4_slot4_set, + Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_set, + Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_set, + Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_slot_internal slots[] = { + { "Inst", "x24", 0, + Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, + Slot_inst_get_field_fns, Slot_inst_set_field_fns, + Slot_inst_decode, "nop" }, + { "Inst16a", "x16a", 0, + Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, + Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, + Slot_inst16a_decode, "" }, + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, + Slot_inst16b_decode, "nop.n" }, + { "ae_slot0", "ae_format", 0, + Slot_ae_format_Format_ae_slot0_4_get, Slot_ae_format_Format_ae_slot0_4_set, + Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns, + Slot_ae_slot0_decode, "nop" }, + { "ae_slot1", "ae_format", 1, + Slot_ae_format_Format_ae_slot1_72_get, Slot_ae_format_Format_ae_slot1_72_set, + Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns, + Slot_ae_slot1_decode, "nop" }, + { "ae_slot2", "ae_format", 2, + Slot_ae_format_Format_ae_slot2_16_get, Slot_ae_format_Format_ae_slot2_16_set, + Slot_ae_slot2_get_field_fns, Slot_ae_slot2_set_field_fns, + Slot_ae_slot2_decode, "nop" }, + { "ae_slot3", "ae_format", 3, + Slot_ae_format_Format_ae_slot3_45_get, Slot_ae_format_Format_ae_slot3_45_set, + Slot_ae_slot3_get_field_fns, Slot_ae_slot3_set_field_fns, + Slot_ae_slot3_decode, "nop" }, + { "ae2_slot0", "ae_format_2", 0, + Slot_ae_format_2_Format_ae2_slot0_4_get, Slot_ae_format_2_Format_ae2_slot0_4_set, + Slot_ae2_slot0_get_field_fns, Slot_ae2_slot0_set_field_fns, + Slot_ae2_slot0_decode, "nop" }, + { "ae2_slot1", "ae_format_2", 1, + Slot_ae_format_2_Format_ae2_slot1_12_get, Slot_ae_format_2_Format_ae2_slot1_12_set, + Slot_ae2_slot1_get_field_fns, Slot_ae2_slot1_set_field_fns, + Slot_ae2_slot1_decode, "nop" }, + { "ae2_slot2", "ae_format_2", 2, + Slot_ae_format_2_Format_ae2_slot2_16_get, Slot_ae_format_2_Format_ae2_slot2_16_set, + Slot_ae2_slot2_get_field_fns, Slot_ae2_slot2_set_field_fns, + Slot_ae2_slot2_decode, "nop" }, + { "ae3_slot0", "ae_format_3", 0, + Slot_ae_format_3_Format_ae3_slot0_4_get, Slot_ae_format_3_Format_ae3_slot0_4_set, + Slot_ae3_slot0_get_field_fns, Slot_ae3_slot0_set_field_fns, + Slot_ae3_slot0_decode, "nop" }, + { "ae3_slot1", "ae_format_3", 1, + Slot_ae_format_3_Format_ae3_slot1_12_get, Slot_ae_format_3_Format_ae3_slot1_12_set, + Slot_ae3_slot1_get_field_fns, Slot_ae3_slot1_set_field_fns, + Slot_ae3_slot1_decode, "nop" }, + { "ae5_slot0", "ae_format_5", 0, + Slot_ae_format_5_Format_ae5_slot0_4_get, Slot_ae_format_5_Format_ae5_slot0_4_set, + Slot_ae5_slot0_get_field_fns, Slot_ae5_slot0_set_field_fns, + Slot_ae5_slot0_decode, "nop" }, + { "ae5_slot1", "ae_format_5", 1, + Slot_ae_format_5_Format_ae5_slot1_56_get, Slot_ae_format_5_Format_ae5_slot1_56_set, + Slot_ae5_slot1_get_field_fns, Slot_ae5_slot1_set_field_fns, + Slot_ae5_slot1_decode, "nop" }, + { "ae5_slot2", "ae_format_5", 2, + Slot_ae_format_5_Format_ae5_slot2_16_get, Slot_ae_format_5_Format_ae5_slot2_16_set, + Slot_ae5_slot2_get_field_fns, Slot_ae5_slot2_set_field_fns, + Slot_ae5_slot2_decode, "nop" }, + { "ae6_slot0", "ae_format_6", 0, + Slot_ae_format_6_Format_ae6_slot0_4_get, Slot_ae_format_6_Format_ae6_slot0_4_set, + Slot_ae6_slot0_get_field_fns, Slot_ae6_slot0_set_field_fns, + Slot_ae6_slot0_decode, "nop" }, + { "ae6_slot1", "ae_format_6", 1, + Slot_ae_format_6_Format_ae6_slot1_57_get, Slot_ae_format_6_Format_ae6_slot1_57_set, + Slot_ae6_slot1_get_field_fns, Slot_ae6_slot1_set_field_fns, + Slot_ae6_slot1_decode, "nop" }, + { "ae6_slot2", "ae_format_6", 2, + Slot_ae_format_6_Format_ae6_slot2_16_get, Slot_ae_format_6_Format_ae6_slot2_16_set, + Slot_ae6_slot2_get_field_fns, Slot_ae6_slot2_set_field_fns, + Slot_ae6_slot2_decode, "nop" }, + { "ae6_slot3", "ae_format_6", 3, + Slot_ae_format_6_Format_ae6_slot3_8_get, Slot_ae_format_6_Format_ae6_slot3_8_set, + Slot_ae6_slot3_get_field_fns, Slot_ae6_slot3_set_field_fns, + Slot_ae6_slot3_decode, "nop" }, + { "ae7_slot0", "ae_format_7", 0, + Slot_ae_format_7_Format_ae7_slot0_4_get, Slot_ae_format_7_Format_ae7_slot0_4_set, + Slot_ae7_slot0_get_field_fns, Slot_ae7_slot0_set_field_fns, + Slot_ae7_slot0_decode, "nop" }, + { "ae7_slot1", "ae_format_7", 1, + Slot_ae_format_7_Format_ae7_slot1_72_get, Slot_ae_format_7_Format_ae7_slot1_72_set, + Slot_ae7_slot1_get_field_fns, Slot_ae7_slot1_set_field_fns, + Slot_ae7_slot1_decode, "nop" }, + { "ae7_slot2", "ae_format_7", 2, + Slot_ae_format_7_Format_ae7_slot2_16_get, Slot_ae_format_7_Format_ae7_slot2_16_set, + Slot_ae7_slot2_get_field_fns, Slot_ae7_slot2_set_field_fns, + Slot_ae7_slot2_decode, "nop" }, + { "ae7_slot3", "ae_format_7", 3, + Slot_ae_format_7_Format_ae7_slot3_45_get, Slot_ae_format_7_Format_ae7_slot3_45_set, + Slot_ae7_slot3_get_field_fns, Slot_ae7_slot3_set_field_fns, + Slot_ae7_slot3_decode, "nop" }, + { "ae8_slot0", "ae_format_8", 0, + Slot_ae_format_8_Format_ae8_slot0_4_get, Slot_ae_format_8_Format_ae8_slot0_4_set, + Slot_ae8_slot0_get_field_fns, Slot_ae8_slot0_set_field_fns, + Slot_ae8_slot0_decode, "nop" }, + { "ae8_slot1", "ae_format_8", 1, + Slot_ae_format_8_Format_ae8_slot1_14_get, Slot_ae_format_8_Format_ae8_slot1_14_set, + Slot_ae8_slot1_get_field_fns, Slot_ae8_slot1_set_field_fns, + Slot_ae8_slot1_decode, "nop" }, + { "ae8_slot2", "ae_format_8", 2, + Slot_ae_format_8_Format_ae8_slot2_16_get, Slot_ae_format_8_Format_ae8_slot2_16_set, + Slot_ae8_slot2_get_field_fns, Slot_ae8_slot2_set_field_fns, + Slot_ae8_slot2_decode, "nop" }, + { "ae9_slot0", "ae_format_9", 0, + Slot_ae_format_9_Format_ae9_slot0_4_get, Slot_ae_format_9_Format_ae9_slot0_4_set, + Slot_ae9_slot0_get_field_fns, Slot_ae9_slot0_set_field_fns, + Slot_ae9_slot0_decode, "nop" }, + { "ae9_slot1", "ae_format_9", 1, + Slot_ae_format_9_Format_ae9_slot1_72_get, Slot_ae_format_9_Format_ae9_slot1_72_set, + Slot_ae9_slot1_get_field_fns, Slot_ae9_slot1_set_field_fns, + Slot_ae9_slot1_decode, "nop" }, + { "ae9_slot2", "ae_format_9", 2, + Slot_ae_format_9_Format_ae9_slot2_16_get, Slot_ae_format_9_Format_ae9_slot2_16_set, + Slot_ae9_slot2_get_field_fns, Slot_ae9_slot2_set_field_fns, + Slot_ae9_slot2_decode, "nop" }, + { "ae9_slot3", "ae_format_9", 3, + Slot_ae_format_9_Format_ae9_slot3_45_get, Slot_ae_format_9_Format_ae9_slot3_45_set, + Slot_ae9_slot3_get_field_fns, Slot_ae9_slot3_set_field_fns, + Slot_ae9_slot3_decode, "nop" }, + { "ae10_slot0", "ae_format_10", 0, + Slot_ae_format_10_Format_ae10_slot0_4_get, Slot_ae_format_10_Format_ae10_slot0_4_set, + Slot_ae10_slot0_get_field_fns, Slot_ae10_slot0_set_field_fns, + Slot_ae10_slot0_decode, "nop" }, + { "ae10_slot1", "ae_format_10", 1, + Slot_ae_format_10_Format_ae10_slot1_34_get, Slot_ae_format_10_Format_ae10_slot1_34_set, + Slot_ae10_slot1_get_field_fns, Slot_ae10_slot1_set_field_fns, + Slot_ae10_slot1_decode, "nop" }, + { "ae10_slot2", "ae_format_10", 2, + Slot_ae_format_10_Format_ae10_slot2_16_get, Slot_ae_format_10_Format_ae10_slot2_16_set, + Slot_ae10_slot2_get_field_fns, Slot_ae10_slot2_set_field_fns, + Slot_ae10_slot2_decode, "nop" }, + { "ae10_slot3", "ae_format_10", 3, + Slot_ae_format_10_Format_ae10_slot3_27_get, Slot_ae_format_10_Format_ae10_slot3_27_set, + Slot_ae10_slot3_get_field_fns, Slot_ae10_slot3_set_field_fns, + Slot_ae10_slot3_decode, "nop" }, + { "ae4_slot0", "ae_format_4", 0, + Slot_ae_format_4_Format_ae4_slot0_4_get, Slot_ae_format_4_Format_ae4_slot0_4_set, + Slot_ae4_slot0_get_field_fns, Slot_ae4_slot0_set_field_fns, + Slot_ae4_slot0_decode, "nop" }, + { "ae4_slot1", "ae_format_4", 1, + Slot_ae_format_4_Format_ae4_slot1_72_get, Slot_ae_format_4_Format_ae4_slot1_72_set, + Slot_ae4_slot1_get_field_fns, Slot_ae4_slot1_set_field_fns, + Slot_ae4_slot1_decode, "nop" }, + { "ae4_slot2", "ae_format_4", 2, + Slot_ae_format_4_Format_ae4_slot2_16_get, Slot_ae_format_4_Format_ae4_slot2_16_set, + Slot_ae4_slot2_get_field_fns, Slot_ae4_slot2_set_field_fns, + Slot_ae4_slot2_decode, "nop" }, + { "ae4_slot3", "ae_format_4", 3, + Slot_ae_format_4_Format_ae4_slot3_26_get, Slot_ae_format_4_Format_ae4_slot3_26_set, + Slot_ae4_slot3_get_field_fns, Slot_ae4_slot3_set_field_fns, + Slot_ae4_slot3_decode, "nop" }, + { "ae4_slot4", "ae_format_4", 4, + Slot_ae_format_4_Format_ae4_slot4_43_get, Slot_ae_format_4_Format_ae4_slot4_43_set, + Slot_ae4_slot4_get_field_fns, Slot_ae4_slot4_set_field_fns, + Slot_ae4_slot4_decode, "nop" } +}; + + +/* Instruction formats. */ + +static void +Format_x24_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_x16a_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_x16b_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xf; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_2_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x2000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_3_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_5_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x2000000e; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_6_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x6000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_7_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_8_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xa000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_9_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_10_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_4_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x4000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static int Format_x24_slots[] = { 0 }; + +static int Format_x16a_slots[] = { 1 }; + +static int Format_x16b_slots[] = { 2 }; + +static int Format_ae_format_slots[] = { 3, 5, 6, 4 }; + +static int Format_ae_format_2_slots[] = { 7, 8, 9 }; + +static int Format_ae_format_3_slots[] = { 10, 11 }; + +static int Format_ae_format_5_slots[] = { 12, 14, 13 }; + +static int Format_ae_format_6_slots[] = { 15, 18, 17, 16 }; + +static int Format_ae_format_7_slots[] = { 19, 21, 22, 20 }; + +static int Format_ae_format_8_slots[] = { 23, 24, 25 }; + +static int Format_ae_format_9_slots[] = { 26, 28, 29, 27 }; + +static int Format_ae_format_10_slots[] = { 30, 32, 33, 31 }; + +static int Format_ae_format_4_slots[] = { 34, 36, 37, 38, 35 }; + +static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }, + { "ae_format", 16, Format_ae_format_encode, 4, Format_ae_format_slots }, + { "ae_format_2", 16, Format_ae_format_2_encode, 3, Format_ae_format_2_slots }, + { "ae_format_3", 8, Format_ae_format_3_encode, 2, Format_ae_format_3_slots }, + { "ae_format_5", 8, Format_ae_format_5_encode, 3, Format_ae_format_5_slots }, + { "ae_format_6", 16, Format_ae_format_6_encode, 4, Format_ae_format_6_slots }, + { "ae_format_7", 16, Format_ae_format_7_encode, 4, Format_ae_format_7_slots }, + { "ae_format_8", 16, Format_ae_format_8_encode, 3, Format_ae_format_8_slots }, + { "ae_format_9", 16, Format_ae_format_9_encode, 4, Format_ae_format_9_slots }, + { "ae_format_10", 16, Format_ae_format_10_encode, 4, Format_ae_format_10_slots }, + { "ae_format_4", 16, Format_ae_format_4_encode, 5, Format_ae_format_4_slots } +}; + + +static int +format_decoder (const xtensa_insnbuf insn) +{ + if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 0; /* x24 */ + if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 1; /* x16a */ + if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 2; /* x16b */ + if ((insn[0] & 0xe000000f) == 0xf && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 3; /* ae_format */ + if ((insn[0] & 0xe000000f) == 0x2000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 4; /* ae_format_2 */ + if ((insn[0] & 0xe000000f) == 0xe && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 5; /* ae_format_3 */ + if ((insn[0] & 0xe000000f) == 0x2000000e && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 6; /* ae_format_5 */ + if ((insn[0] & 0xe000000f) == 0x6000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 7; /* ae_format_6 */ + if ((insn[0] & 0xe000000f) == 0x8000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 8; /* ae_format_7 */ + if ((insn[0] & 0xe000000f) == 0xa000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 9; /* ae_format_8 */ + if ((insn[0] & 0xe000000f) == 0xc000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 10; /* ae_format_9 */ + if ((insn[0] & 0xe000000f) == 0xe000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 11; /* ae_format_10 */ + if ((insn[0] & 0xe000000f) == 0x4000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 12; /* ae_format_4 */ + return -1; +} + +static int length_table[256] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16 +}; + +static int +length_decoder (const unsigned char *insn) +{ + int l = insn[0]; + return length_table[l]; +} + + +/* Top-level ISA structure. */ + +xtensa_isa_internal xtensa_modules = { + 0 /* little-endian */, + 16 /* insn_size */, 0, + 13, formats, format_decoder, length_decoder, + 39, slots, + 886 /* num_fields */, + 1098, operands, + 2115, iclasses, + 2217, opcodes, 0, + 9, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, + 6, interfaces, 0, + 7, funcUnits, 0 +}; diff --git a/overlays/xtensa_mtk_mt818x_adsp/gcc/xtensa-config.h b/overlays/xtensa_mtk_mt818x_adsp/gcc/xtensa-config.h new file mode 100644 index 00000000..84aeb9ea --- /dev/null +++ b/overlays/xtensa_mtk_mt818x_adsp/gcc/xtensa-config.h @@ -0,0 +1,185 @@ +/* Xtensa configuration settings. + Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 + Free Software Foundation, Inc. + Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef XTENSA_CONFIG_H +#define XTENSA_CONFIG_H + +/* The macros defined here match those with the same names in the Xtensa + compile-time HAL (Hardware Abstraction Layer). Please refer to the + Xtensa System Software Reference Manual for documentation of these + macros. */ + +#undef XCHAL_HAVE_BE +#define XCHAL_HAVE_BE 0 + +#undef XCHAL_HAVE_DENSITY +#define XCHAL_HAVE_DENSITY 1 + +#undef XCHAL_HAVE_CONST16 +#define XCHAL_HAVE_CONST16 0 + +#undef XCHAL_HAVE_ABS +#define XCHAL_HAVE_ABS 1 + +#undef XCHAL_HAVE_ADDX +#define XCHAL_HAVE_ADDX 1 + +#undef XCHAL_HAVE_L32R +#define XCHAL_HAVE_L32R 1 + +#undef XSHAL_USE_ABSOLUTE_LITERALS +#define XSHAL_USE_ABSOLUTE_LITERALS 0 + +#undef XSHAL_HAVE_TEXT_SECTION_LITERALS +#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ + +#undef XCHAL_HAVE_MAC16 +#define XCHAL_HAVE_MAC16 0 + +#undef XCHAL_HAVE_MUL16 +#define XCHAL_HAVE_MUL16 1 + +#undef XCHAL_HAVE_MUL32 +#define XCHAL_HAVE_MUL32 1 + +#undef XCHAL_HAVE_MUL32_HIGH +#define XCHAL_HAVE_MUL32_HIGH 0 + +#undef XCHAL_HAVE_DIV32 +#define XCHAL_HAVE_DIV32 1 + +#undef XCHAL_HAVE_NSA +#define XCHAL_HAVE_NSA 1 + +#undef XCHAL_HAVE_MINMAX +#define XCHAL_HAVE_MINMAX 1 + +#undef XCHAL_HAVE_SEXT +#define XCHAL_HAVE_SEXT 1 + +#undef XCHAL_HAVE_LOOPS +#define XCHAL_HAVE_LOOPS 1 + +#undef XCHAL_HAVE_THREADPTR +#define XCHAL_HAVE_THREADPTR 1 + +#undef XCHAL_HAVE_RELEASE_SYNC +#define XCHAL_HAVE_RELEASE_SYNC 1 + +#undef XCHAL_HAVE_S32C1I +#define XCHAL_HAVE_S32C1I 0 + +#undef XCHAL_HAVE_BOOLEANS +#define XCHAL_HAVE_BOOLEANS 1 + +#undef XCHAL_HAVE_FP +#define XCHAL_HAVE_FP 0 + +#undef XCHAL_HAVE_FP_DIV +#define XCHAL_HAVE_FP_DIV 0 + +#undef XCHAL_HAVE_FP_RECIP +#define XCHAL_HAVE_FP_RECIP 0 + +#undef XCHAL_HAVE_FP_SQRT +#define XCHAL_HAVE_FP_SQRT 0 + +#undef XCHAL_HAVE_FP_RSQRT +#define XCHAL_HAVE_FP_RSQRT 0 + +#undef XCHAL_HAVE_DFP_ACCEL +#define XCHAL_HAVE_DFP_ACCEL 0 +/* For backward compatibility */ +#undef XCHAL_HAVE_DFP_accel +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL + +#undef XCHAL_HAVE_WINDOWED +#define XCHAL_HAVE_WINDOWED 1 + +#undef XCHAL_NUM_AREGS +#define XCHAL_NUM_AREGS 64 + +#undef XCHAL_HAVE_WIDE_BRANCHES +#define XCHAL_HAVE_WIDE_BRANCHES 0 + +#undef XCHAL_ICACHE_SIZE +#define XCHAL_ICACHE_SIZE 65536 + +#undef XCHAL_DCACHE_SIZE +#define XCHAL_DCACHE_SIZE 131072 + +#undef XCHAL_ICACHE_LINESIZE +#define XCHAL_ICACHE_LINESIZE 128 + +#undef XCHAL_DCACHE_LINESIZE +#define XCHAL_DCACHE_LINESIZE 128 + +#undef XCHAL_ICACHE_LINEWIDTH +#define XCHAL_ICACHE_LINEWIDTH 7 + +#undef XCHAL_DCACHE_LINEWIDTH +#define XCHAL_DCACHE_LINEWIDTH 7 + +#undef XCHAL_DCACHE_IS_WRITEBACK +#define XCHAL_DCACHE_IS_WRITEBACK 1 + + +#undef XCHAL_HAVE_MMU +#define XCHAL_HAVE_MMU 0 + + +#undef XCHAL_HAVE_DEBUG +#define XCHAL_HAVE_DEBUG 1 + +#undef XCHAL_NUM_IBREAK +#define XCHAL_NUM_IBREAK 2 + +#undef XCHAL_NUM_DBREAK +#define XCHAL_NUM_DBREAK 2 + +#undef XCHAL_DEBUGLEVEL +#define XCHAL_DEBUGLEVEL 5 + + +#undef XCHAL_MAX_INSTRUCTION_SIZE +#define XCHAL_MAX_INSTRUCTION_SIZE 16 + +#undef XCHAL_INST_FETCH_WIDTH +#define XCHAL_INST_FETCH_WIDTH 16 + + +#undef XSHAL_ABI +#undef XTHAL_ABI_WINDOWED +#undef XTHAL_ABI_CALL0 +#define XSHAL_ABI XTHAL_ABI_WINDOWED +#define XTHAL_ABI_WINDOWED 0 +#define XTHAL_ABI_CALL0 1 + + +#undef XCHAL_M_STAGE +#define XCHAL_M_STAGE 3 + +#undef XTENSA_MARCH_LATEST +#define XTENSA_MARCH_LATEST 281050 + +#undef XTENSA_MARCH_EARLIEST +#define XTENSA_MARCH_EARLIEST 281050 + + +#endif /* !XTENSA_CONFIG_H */ diff --git a/overlays/xtensa_mtk_mt818x_adsp/gdb/reg-xtensa.dat b/overlays/xtensa_mtk_mt818x_adsp/gdb/reg-xtensa.dat new file mode 100644 index 00000000..9df36235 --- /dev/null +++ b/overlays/xtensa_mtk_mt818x_adsp/gdb/reg-xtensa.dat @@ -0,0 +1,132 @@ +name:xtensa +expedite:pc,windowbase,windowstart +32:pc +32:ar0 +32:ar1 +32:ar2 +32:ar3 +32:ar4 +32:ar5 +32:ar6 +32:ar7 +32:ar8 +32:ar9 +32:ar10 +32:ar11 +32:ar12 +32:ar13 +32:ar14 +32:ar15 +32:ar16 +32:ar17 +32:ar18 +32:ar19 +32:ar20 +32:ar21 +32:ar22 +32:ar23 +32:ar24 +32:ar25 +32:ar26 +32:ar27 +32:ar28 +32:ar29 +32:ar30 +32:ar31 +32:ar32 +32:ar33 +32:ar34 +32:ar35 +32:ar36 +32:ar37 +32:ar38 +32:ar39 +32:ar40 +32:ar41 +32:ar42 +32:ar43 +32:ar44 +32:ar45 +32:ar46 +32:ar47 +32:ar48 +32:ar49 +32:ar50 +32:ar51 +32:ar52 +32:ar53 +32:ar54 +32:ar55 +32:ar56 +32:ar57 +32:ar58 +32:ar59 +32:ar60 +32:ar61 +32:ar62 +32:ar63 +32:lbeg +32:lend +32:lcount +32:sar +32:prefctl +32:windowbase +32:windowstart +32:configid0 +32:configid1 +32:ps +32:threadptr +32:br +32:expstate +32:ae_ovf_sar +32:ae_bithead +32:ae_ts_fts_bu_bp +32:ae_cw_sd_no +32:ae_cbegin0 +32:ae_cend0 +32:ae_cbegin1 +32:ae_cend1 +32:ae_cbegin2 +32:ae_cend2 +64:aed0 +64:aed1 +64:aed2 +64:aed3 +64:aed4 +64:aed5 +64:aed6 +64:aed7 +64:aed8 +64:aed9 +64:aed10 +64:aed11 +64:aed12 +64:aed13 +64:aed14 +64:aed15 +64:aed16 +64:aed17 +64:aed18 +64:aed19 +64:aed20 +64:aed21 +64:aed22 +64:aed23 +64:aed24 +64:aed25 +64:aed26 +64:aed27 +64:aed28 +64:aed29 +64:aed30 +64:aed31 +128:u0 +128:u1 +128:u2 +128:u3 +8:aep0 +8:aep1 +8:aep2 +8:aep3 +32:ae_zbiasv8c +32:fcr_fsr diff --git a/overlays/xtensa_mtk_mt818x_adsp/gdb/xtensa-config.c b/overlays/xtensa_mtk_mt818x_adsp/gdb/xtensa-config.c new file mode 100644 index 00000000..c8a4aca3 --- /dev/null +++ b/overlays/xtensa_mtk_mt818x_adsp/gdb/xtensa-config.c @@ -0,0 +1,562 @@ +/* Configuration for the Xtensa architecture for GDB, the GNU debugger. + + Copyright (c) 2003-2024 Cadence Design Systems, Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#define XTENSA_CONFIG_VERSION 0x70 + +#include "xtensa-config.h" +#include "xtensa-tdep.h" + + + +/* Masked registers. */ +xtensa_reg_mask_t xtensa_submask0[] = { { 76, 0, 1 } }; +const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 }; +xtensa_reg_mask_t xtensa_submask1[] = { { 76, 1, 1 } }; +const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 }; +xtensa_reg_mask_t xtensa_submask2[] = { { 76, 2, 1 } }; +const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 }; +xtensa_reg_mask_t xtensa_submask3[] = { { 76, 3, 1 } }; +const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 }; +xtensa_reg_mask_t xtensa_submask4[] = { { 76, 4, 1 } }; +const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 }; +xtensa_reg_mask_t xtensa_submask5[] = { { 76, 5, 1 } }; +const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 }; +xtensa_reg_mask_t xtensa_submask6[] = { { 76, 6, 1 } }; +const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 }; +xtensa_reg_mask_t xtensa_submask7[] = { { 76, 7, 1 } }; +const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 }; +xtensa_reg_mask_t xtensa_submask8[] = { { 76, 8, 1 } }; +const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 }; +xtensa_reg_mask_t xtensa_submask9[] = { { 76, 9, 1 } }; +const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 }; +xtensa_reg_mask_t xtensa_submask10[] = { { 76, 10, 1 } }; +const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 }; +xtensa_reg_mask_t xtensa_submask11[] = { { 76, 11, 1 } }; +const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 }; +xtensa_reg_mask_t xtensa_submask12[] = { { 76, 12, 1 } }; +const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 }; +xtensa_reg_mask_t xtensa_submask13[] = { { 76, 13, 1 } }; +const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 }; +xtensa_reg_mask_t xtensa_submask14[] = { { 76, 14, 1 } }; +const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 }; +xtensa_reg_mask_t xtensa_submask15[] = { { 76, 15, 1 } }; +const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 }; +xtensa_reg_mask_t xtensa_submask16[] = { { 169, 0, 1 } }; +const xtensa_mask_t xtensa_mask16 = { 1, xtensa_submask16 }; +xtensa_reg_mask_t xtensa_submask17[] = { { 74, 0, 4 } }; +const xtensa_mask_t xtensa_mask17 = { 1, xtensa_submask17 }; +xtensa_reg_mask_t xtensa_submask18[] = { { 74, 5, 1 } }; +const xtensa_mask_t xtensa_mask18 = { 1, xtensa_submask18 }; +xtensa_reg_mask_t xtensa_submask19[] = { { 74, 18, 1 } }; +const xtensa_mask_t xtensa_mask19 = { 1, xtensa_submask19 }; +xtensa_reg_mask_t xtensa_submask20[] = { { 74, 6, 2 } }; +const xtensa_mask_t xtensa_mask20 = { 1, xtensa_submask20 }; +xtensa_reg_mask_t xtensa_submask21[] = { { 74, 4, 1 } }; +const xtensa_mask_t xtensa_mask21 = { 1, xtensa_submask21 }; +xtensa_reg_mask_t xtensa_submask22[] = { { 74, 16, 2 } }; +const xtensa_mask_t xtensa_mask22 = { 1, xtensa_submask22 }; +xtensa_reg_mask_t xtensa_submask23[] = { { 74, 8, 4 } }; +const xtensa_mask_t xtensa_mask23 = { 1, xtensa_submask23 }; +xtensa_reg_mask_t xtensa_submask24[] = { { 132, 0, 6 } }; +const xtensa_mask_t xtensa_mask24 = { 1, xtensa_submask24 }; +xtensa_reg_mask_t xtensa_submask25[] = { { 139, 0, 2 } }; +const xtensa_mask_t xtensa_mask25 = { 1, xtensa_submask25 }; +xtensa_reg_mask_t xtensa_submask26[] = { { 171, 8, 4 } }; +const xtensa_mask_t xtensa_mask26 = { 1, xtensa_submask26 }; +xtensa_reg_mask_t xtensa_submask27[] = { { 78, 7, 1 } }; +const xtensa_mask_t xtensa_mask27 = { 1, xtensa_submask27 }; +xtensa_reg_mask_t xtensa_submask28[] = { { 78, 0, 7 }, { 78, 8, 7 } }; +const xtensa_mask_t xtensa_mask28 = { 2, xtensa_submask28 }; +xtensa_reg_mask_t xtensa_submask29[] = { { 81, 28, 1 } }; +const xtensa_mask_t xtensa_mask29 = { 1, xtensa_submask29 }; +xtensa_reg_mask_t xtensa_submask30[] = { { 80, 0, 4 } }; +const xtensa_mask_t xtensa_mask30 = { 1, xtensa_submask30 }; +xtensa_reg_mask_t xtensa_submask31[] = { { 80, 4, 4 } }; +const xtensa_mask_t xtensa_mask31 = { 1, xtensa_submask31 }; +xtensa_reg_mask_t xtensa_submask32[] = { { 80, 12, 4 } }; +const xtensa_mask_t xtensa_mask32 = { 1, xtensa_submask32 }; +xtensa_reg_mask_t xtensa_submask33[] = { { 80, 8, 4 } }; +const xtensa_mask_t xtensa_mask33 = { 1, xtensa_submask33 }; +xtensa_reg_mask_t xtensa_submask34[] = { { 81, 0, 27 } }; +const xtensa_mask_t xtensa_mask34 = { 1, xtensa_submask34 }; +xtensa_reg_mask_t xtensa_submask35[] = { { 81, 27, 1 } }; +const xtensa_mask_t xtensa_mask35 = { 1, xtensa_submask35 }; +xtensa_reg_mask_t xtensa_submask36[] = { { 128, 8, 8 } }; +const xtensa_mask_t xtensa_mask36 = { 1, xtensa_submask36 }; +xtensa_reg_mask_t xtensa_submask37[] = { { 128, 0, 8 } }; +const xtensa_mask_t xtensa_mask37 = { 1, xtensa_submask37 }; +xtensa_reg_mask_t xtensa_submask38[] = { { 129, 5, 2 } }; +const xtensa_mask_t xtensa_mask38 = { 1, xtensa_submask38 }; +xtensa_reg_mask_t xtensa_submask39[] = { { 129, 4, 1 } }; +const xtensa_mask_t xtensa_mask39 = { 1, xtensa_submask39 }; +xtensa_reg_mask_t xtensa_submask40[] = { { 129, 3, 1 } }; +const xtensa_mask_t xtensa_mask40 = { 1, xtensa_submask40 }; +xtensa_reg_mask_t xtensa_submask41[] = { { 129, 2, 1 } }; +const xtensa_mask_t xtensa_mask41 = { 1, xtensa_submask41 }; +xtensa_reg_mask_t xtensa_submask42[] = { { 129, 1, 1 } }; +const xtensa_mask_t xtensa_mask42 = { 1, xtensa_submask42 }; +xtensa_reg_mask_t xtensa_submask43[] = { { 129, 0, 1 } }; +const xtensa_mask_t xtensa_mask43 = { 1, xtensa_submask43 }; + + +/* Register map. */ +xtensa_register_t rmap[] = +{ + /* idx ofs bi sz al targno flags cp typ group name */ + XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x2100,pc, 0,0,0,0,0,0) + XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) + XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) + XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0) + XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0) + XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0) + XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0) + XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0) + XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0) + XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0) + XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0) + XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0) + XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0) + XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0) + XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0) + XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0) + XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0) + XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0) + XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0) + XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0) + XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0) + XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0) + XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0) + XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0) + XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0) + XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0) + XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0) + XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0) + XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0) + XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0) + XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0) + XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0) + XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0) + XTREG( 33,132,32, 4, 4,0x0120,0x0006,-2, 1,0x0002,ar32, 0,0,0,0,0,0) + XTREG( 34,136,32, 4, 4,0x0121,0x0006,-2, 1,0x0002,ar33, 0,0,0,0,0,0) + XTREG( 35,140,32, 4, 4,0x0122,0x0006,-2, 1,0x0002,ar34, 0,0,0,0,0,0) + XTREG( 36,144,32, 4, 4,0x0123,0x0006,-2, 1,0x0002,ar35, 0,0,0,0,0,0) + XTREG( 37,148,32, 4, 4,0x0124,0x0006,-2, 1,0x0002,ar36, 0,0,0,0,0,0) + XTREG( 38,152,32, 4, 4,0x0125,0x0006,-2, 1,0x0002,ar37, 0,0,0,0,0,0) + XTREG( 39,156,32, 4, 4,0x0126,0x0006,-2, 1,0x0002,ar38, 0,0,0,0,0,0) + XTREG( 40,160,32, 4, 4,0x0127,0x0006,-2, 1,0x0002,ar39, 0,0,0,0,0,0) + XTREG( 41,164,32, 4, 4,0x0128,0x0006,-2, 1,0x0002,ar40, 0,0,0,0,0,0) + XTREG( 42,168,32, 4, 4,0x0129,0x0006,-2, 1,0x0002,ar41, 0,0,0,0,0,0) + XTREG( 43,172,32, 4, 4,0x012a,0x0006,-2, 1,0x0002,ar42, 0,0,0,0,0,0) + XTREG( 44,176,32, 4, 4,0x012b,0x0006,-2, 1,0x0002,ar43, 0,0,0,0,0,0) + XTREG( 45,180,32, 4, 4,0x012c,0x0006,-2, 1,0x0002,ar44, 0,0,0,0,0,0) + XTREG( 46,184,32, 4, 4,0x012d,0x0006,-2, 1,0x0002,ar45, 0,0,0,0,0,0) + XTREG( 47,188,32, 4, 4,0x012e,0x0006,-2, 1,0x0002,ar46, 0,0,0,0,0,0) + XTREG( 48,192,32, 4, 4,0x012f,0x0006,-2, 1,0x0002,ar47, 0,0,0,0,0,0) + XTREG( 49,196,32, 4, 4,0x0130,0x0006,-2, 1,0x0002,ar48, 0,0,0,0,0,0) + XTREG( 50,200,32, 4, 4,0x0131,0x0006,-2, 1,0x0002,ar49, 0,0,0,0,0,0) + XTREG( 51,204,32, 4, 4,0x0132,0x0006,-2, 1,0x0002,ar50, 0,0,0,0,0,0) + XTREG( 52,208,32, 4, 4,0x0133,0x0006,-2, 1,0x0002,ar51, 0,0,0,0,0,0) + XTREG( 53,212,32, 4, 4,0x0134,0x0006,-2, 1,0x0002,ar52, 0,0,0,0,0,0) + XTREG( 54,216,32, 4, 4,0x0135,0x0006,-2, 1,0x0002,ar53, 0,0,0,0,0,0) + XTREG( 55,220,32, 4, 4,0x0136,0x0006,-2, 1,0x0002,ar54, 0,0,0,0,0,0) + XTREG( 56,224,32, 4, 4,0x0137,0x0006,-2, 1,0x0002,ar55, 0,0,0,0,0,0) + XTREG( 57,228,32, 4, 4,0x0138,0x0006,-2, 1,0x0002,ar56, 0,0,0,0,0,0) + XTREG( 58,232,32, 4, 4,0x0139,0x0006,-2, 1,0x0002,ar57, 0,0,0,0,0,0) + XTREG( 59,236,32, 4, 4,0x013a,0x0006,-2, 1,0x0002,ar58, 0,0,0,0,0,0) + XTREG( 60,240,32, 4, 4,0x013b,0x0006,-2, 1,0x0002,ar59, 0,0,0,0,0,0) + XTREG( 61,244,32, 4, 4,0x013c,0x0006,-2, 1,0x0002,ar60, 0,0,0,0,0,0) + XTREG( 62,248,32, 4, 4,0x013d,0x0006,-2, 1,0x0002,ar61, 0,0,0,0,0,0) + XTREG( 63,252,32, 4, 4,0x013e,0x0006,-2, 1,0x0002,ar62, 0,0,0,0,0,0) + XTREG( 64,256,32, 4, 4,0x013f,0x0006,-2, 1,0x0002,ar63, 0,0,0,0,0,0) + XTREG( 65,260,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0) + XTREG( 66,264,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0) + XTREG( 67,268,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0) + XTREG( 68,272, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0) + XTREG( 69,276,20, 4, 4,0x0228,0x0006,-2, 2,0x1100,prefctl, 0,0,0,0,0,0) + XTREG( 70,280, 4, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) + XTREG( 71,284,16, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) + XTREG( 72,288,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0) + XTREG( 73,292,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0) + XTREG( 74,296,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) + XTREG( 75,300,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0) + XTREG( 76,304,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0) + XTREG( 77,308,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0) + XTREG( 78,312,15, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0) + XTREG( 79,316,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0) + XTREG( 80,320,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0) + XTREG( 81,324,29, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_cw_sd_no, 0,0,0,0,0,0) + XTREG( 82,328,32, 4, 4,0x03f6,0x0006, 1, 3,0x0110,ae_cbegin0, 0,0,0,0,0,0) + XTREG( 83,332,32, 4, 4,0x03f7,0x0006, 1, 3,0x0110,ae_cend0, 0,0,0,0,0,0) + XTREG( 84,336,32, 4, 4,0x03f8,0x0006, 1, 3,0x0110,ae_cbegin1, 0,0,0,0,0,0) + XTREG( 85,340,32, 4, 4,0x03f9,0x0006, 1, 3,0x0110,ae_cend1, 0,0,0,0,0,0) + XTREG( 86,344,32, 4, 4,0x03fa,0x0006, 1, 3,0x0110,ae_cbegin2, 0,0,0,0,0,0) + XTREG( 87,348,32, 4, 4,0x03fb,0x0006, 1, 3,0x0110,ae_cend2, 0,0,0,0,0,0) + XTREG( 88,352,64, 8, 8,0x1000,0x0006, 1, 4,0x0101,aed0, + "10:4f:03:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:03:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 89,360,64, 8, 8,0x1001,0x0006, 1, 4,0x0101,aed1, + "10:4f:43:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:43:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 90,368,64, 8, 8,0x1002,0x0006, 1, 4,0x0101,aed2, + "10:4f:83:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:83:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 91,376,64, 8, 8,0x1003,0x0006, 1, 4,0x0101,aed3, + "10:4f:c3:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:c3:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 92,384,64, 8, 8,0x1004,0x0006, 1, 4,0x0101,aed4, + "10:4f:07:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:07:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 93,392,64, 8, 8,0x1005,0x0006, 1, 4,0x0101,aed5, + "10:4f:47:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:47:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 94,400,64, 8, 8,0x1006,0x0006, 1, 4,0x0101,aed6, + "10:4f:87:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:87:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 95,408,64, 8, 8,0x1007,0x0006, 1, 4,0x0101,aed7, + "10:4f:c7:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:c7:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 96,416,64, 8, 8,0x1008,0x0006, 1, 4,0x0101,aed8, + "10:4f:0b:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:0b:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 97,424,64, 8, 8,0x1009,0x0006, 1, 4,0x0101,aed9, + "10:4f:4b:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:4b:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 98,432,64, 8, 8,0x100a,0x0006, 1, 4,0x0101,aed10, + "10:4f:8b:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:8b:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 99,440,64, 8, 8,0x100b,0x0006, 1, 4,0x0101,aed11, + "10:4f:cb:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:cb:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(100,448,64, 8, 8,0x100c,0x0006, 1, 4,0x0101,aed12, + "10:4f:0f:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:0f:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(101,456,64, 8, 8,0x100d,0x0006, 1, 4,0x0101,aed13, + "10:4f:4f:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:4f:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(102,464,64, 8, 8,0x100e,0x0006, 1, 4,0x0101,aed14, + "10:4f:8f:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:8f:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(103,472,64, 8, 8,0x100f,0x0006, 1, 4,0x0101,aed15, + "10:4f:cf:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:cf:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(104,480,64, 8, 8,0x1010,0x0006, 1, 4,0x0101,aed16, + "10:4f:03:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:03:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(105,488,64, 8, 8,0x1011,0x0006, 1, 4,0x0101,aed17, + "10:4f:43:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:43:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(106,496,64, 8, 8,0x1012,0x0006, 1, 4,0x0101,aed18, + "10:4f:83:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:83:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(107,504,64, 8, 8,0x1013,0x0006, 1, 4,0x0101,aed19, + "10:4f:c3:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:c3:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(108,512,64, 8, 8,0x1014,0x0006, 1, 4,0x0101,aed20, + "10:4f:07:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:07:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(109,520,64, 8, 8,0x1015,0x0006, 1, 4,0x0101,aed21, + "10:4f:47:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:47:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(110,528,64, 8, 8,0x1016,0x0006, 1, 4,0x0101,aed22, + "10:4f:87:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:87:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(111,536,64, 8, 8,0x1017,0x0006, 1, 4,0x0101,aed23, + "10:4f:c7:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:c7:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(112,544,64, 8, 8,0x1018,0x0006, 1, 4,0x0101,aed24, + "10:4f:0b:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:0b:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(113,552,64, 8, 8,0x1019,0x0006, 1, 4,0x0101,aed25, + "10:4f:4b:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:4b:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(114,560,64, 8, 8,0x101a,0x0006, 1, 4,0x0101,aed26, + "10:4f:8b:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:8b:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(115,568,64, 8, 8,0x101b,0x0006, 1, 4,0x0101,aed27, + "10:4f:cb:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:cb:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(116,576,64, 8, 8,0x101c,0x0006, 1, 4,0x0101,aed28, + "10:4f:0f:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:0f:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(117,584,64, 8, 8,0x101d,0x0006, 1, 4,0x0101,aed29, + "10:4f:4f:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:4f:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(118,592,64, 8, 8,0x101e,0x0006, 1, 4,0x0101,aed30, + "10:4f:8f:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:8f:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(119,600,64, 8, 8,0x101f,0x0006, 1, 4,0x0101,aed31, + "10:4f:cf:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:cf:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(120,608,128,16,16,0x1020,0x0006, 1, 4,0x0101,u0, + "10:4f:00:01:00:3b:81:80:c4:d0:0c:e4:09:7b:05:ad:0e","10:4f:c0:01:00:3f:81:00:c4:d0:0c:24:0d:7b:25:ad:0e",0,0,0,0) + XTREG(121,624,128,16,16,0x1021,0x0006, 1, 4,0x0101,u1, + "10:4f:00:01:00:3b:81:80:c4:d0:0c:e5:09:7b:05:ad:0e","10:4f:c4:01:00:3f:81:00:c4:d0:0c:24:0d:7b:25:ad:0e",0,0,0,0) + XTREG(122,640,128,16,16,0x1022,0x0006, 1, 4,0x0101,u2, + "10:4f:00:01:04:3b:81:80:c4:d0:0c:e4:09:7b:05:ad:0e","10:4f:c8:01:00:3f:81:00:c4:d0:0c:24:0d:7b:25:ad:0e",0,0,0,0) + XTREG(123,656,128,16,16,0x1023,0x0006, 1, 4,0x0101,u3, + "10:4f:00:01:04:3b:81:80:c4:d0:0c:e5:09:7b:05:ad:0e","10:4f:cc:01:00:3f:81:00:c4:d0:0c:24:0d:7b:25:ad:0e",0,0,0,0) + XTREG(124,672, 8, 1, 1,0x1024,0x0006, 1, 4,0x0101,aep0, + "03:52:64:01:08:5e:79:a5:14:c4:40:07:23:03:52:44:00:03:52:24:01","03:52:64:01:03:52:04:00:08:ce:35:a5:00:c4:40:07:23:03:52:24:01",0,0,0,0) + XTREG(125,673, 8, 1, 1,0x1025,0x0006, 1, 4,0x0101,aep1, + "03:52:64:01:08:5e:79:a5:14:c5:40:07:23:03:52:44:00:03:52:24:01","03:52:64:01:03:52:04:00:08:ce:35:a5:00:c5:40:07:23:03:52:24:01",0,0,0,0) + XTREG(126,674, 8, 1, 1,0x1026,0x0006, 1, 4,0x0101,aep2, + "03:52:64:01:08:5e:79:a5:14:c6:40:07:23:03:52:44:00:03:52:24:01","03:52:64:01:03:52:04:00:08:ce:35:a5:00:c6:40:07:23:03:52:24:01",0,0,0,0) + XTREG(127,675, 8, 1, 1,0x1027,0x0006, 1, 4,0x0101,aep3, + "03:52:64:01:08:5e:79:a5:14:c7:40:07:23:03:52:44:00:03:52:24:01","03:52:64:01:03:52:04:00:08:ce:35:a5:00:c7:40:07:23:03:52:24:01",0,0,0,0) + XTREG(128,676,16, 4, 4,0x1029,0x0006, 1, 3,0x0200,ae_zbiasv8c, + "10:4f:03:01:08:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e:10:5f:01:00:0c:30:81:00:c5:d0:0c:44:0d:7b:25:ad:0e:10:4f:03:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e:10:4f:03:01:08:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e","10:4f:03:01:08:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e:10:4f:03:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e:10:5f:01:00:0c:38:81:00:c5:d0:0c:44:0d:7b:25:ad:0e:10:4f:03:01:08:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(129,680, 7, 4, 4,0x102a,0x0006, 1, 3,0x0200,fcr_fsr, + "10:4f:03:01:08:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e:10:5f:01:a0:0e:00:80:00:c5:d0:0c:44:0d:9b:24:ad:0e:10:4f:03:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e:10:4f:03:01:08:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e","10:4f:03:01:08:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e:10:4f:03:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e:10:5f:01:80:0e:00:80:00:c5:d0:0c:44:0d:9b:24:ad:0e:10:4f:03:01:08:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(130,684,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0) + XTREG(131,688,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,mpuenb, 0,0,0,0,0,0) + XTREG(132,692, 6, 4, 4,0x025c,0x0007,-2, 2,0x1000,mpucfg, 0,0,0,0,0,0) + XTREG(133,696,16, 4, 4,0x025f,0x0007,-2, 2,0x1000,eraccess, 0,0,0,0,0,0) + XTREG(134,700, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0) + XTREG(135,704,24, 4, 4,0x0261,0x0007,-2, 2,0x1000,memctl, 0,0,0,0,0,0) + XTREG(136,708, 8, 4, 4,0x0262,0x0007,-2, 2,0x1000,cacheadrdis, 0,0,0,0,0,0) + XTREG(137,712, 9, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0) + XTREG(138,716,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0) + XTREG(139,720, 2, 4, 4,0x0277,0x0007,-2, 2,0x1000,opmode, 0,0,0,0,0,0) + XTREG(140,724,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0) + XTREG(141,728,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0) + XTREG(142,732,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0) + XTREG(143,736,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0) + XTREG(144,740,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0) + XTREG(145,744,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0) + XTREG(146,748,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0) + XTREG(147,752,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0) + XTREG(148,756,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0) + XTREG(149,760,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0) + XTREG(150,764,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0) + XTREG(151,768,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0) + XTREG(152,772,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0) + XTREG(153,776,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0) + XTREG(154,780,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0) + XTREG(155,784,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0) + XTREG(156,788,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0) + XTREG(157,792,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0) + XTREG(158,796,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) + XTREG(159,800,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) + XTREG(160,804,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0) + XTREG(161,808,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0) + XTREG(162,812,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0) + XTREG(163,816,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0) + XTREG(164,820, 2, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0) + XTREG(165,824,32, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) + XTREG(166,828,32, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0) + XTREG(167,832,32, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0) + XTREG(168,836,32, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0) + XTREG(169,840,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) + XTREG(170,844, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0) + XTREG(171,848,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) + XTREG(172,852,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0) + XTREG(173,856,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0) + XTREG(174,860,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0) + XTREG(175,864, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) + XTREG(176,868,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) + XTREG(177,872,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) + XTREG(178,876,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0) + XTREG(179,880,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0) + XTREG(180,884,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0) + XTREG(181,888,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0) + XTREG(182,892,32, 4, 4,0x02f6,0x0007,-2, 2,0x1000,misc2, 0,0,0,0,0,0) + XTREG(183,896,32, 4, 4,0x02f7,0x0007,-2, 2,0x1000,misc3, 0,0,0,0,0,0) + XTREG(184,900,32, 4, 4,0x2029,0x000f,-2, 4,0x0101,pwrctl, + "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(185,904,32, 4, 4,0x202a,0x000f,-2, 4,0x0101,pwrstat, + "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(186,908, 1, 4, 4,0x202b,0x000f,-2, 4,0x0101,eristat, + "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(187,912,32, 4, 4,0x202c,0x000f,-2, 4,0x0101,cs_itctrl, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(188,916,16, 4, 4,0x202d,0x000f,-2, 4,0x0101,cs_claimset, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(189,920,16, 4, 4,0x202e,0x000f,-2, 4,0x0101,cs_claimclr, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(190,924,32, 4, 4,0x202f,0x000d,-2, 4,0x0101,cs_lockaccess, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(191,928,32, 4, 4,0x2030,0x000b,-2, 4,0x0101,cs_lockstatus, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(192,932, 1, 4, 4,0x2031,0x000b,-2, 4,0x0101,cs_authstatus, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(193,936,32, 4, 4,0x2040,0x000f,-2, 4,0x0101,fault_info, + "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:30:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:30:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(194,940,32, 4, 4,0x2041,0x0003,-2, 4,0x0101,trax_id, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(195,944,32, 4, 4,0x2042,0x000f,-2, 4,0x0101,trax_control, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(196,948,32, 4, 4,0x2043,0x000b,-2, 4,0x0101,trax_status, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(197,952,32, 4, 4,0x2044,0x000f,-2, 4,0x0101,trax_data, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(198,956,32, 4, 4,0x2045,0x000f,-2, 4,0x0101,trax_address, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(199,960,32, 4, 4,0x2046,0x000f,-2, 4,0x0101,trax_pctrigger, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(200,964,32, 4, 4,0x2047,0x000f,-2, 4,0x0101,trax_pcmatch, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(201,968,32, 4, 4,0x2048,0x000f,-2, 4,0x0101,trax_delay, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(202,972,32, 4, 4,0x2049,0x000f,-2, 4,0x0101,trax_memstart, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(203,976,32, 4, 4,0x204a,0x000f,-2, 4,0x0101,trax_memend, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(204,980,32, 4, 4,0x2058,0x000f,-2, 4,0x0101,pmg, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(205,984,32, 4, 4,0x2059,0x000f,-2, 4,0x0101,pmpc, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(206,988,32, 4, 4,0x205a,0x000f,-2, 4,0x0101,pm0, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(207,992,32, 4, 4,0x205b,0x000f,-2, 4,0x0101,pm1, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(208,996,32, 4, 4,0x205c,0x000f,-2, 4,0x0101,pm2, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(209,1000,32, 4, 4,0x205d,0x000f,-2, 4,0x0101,pm3, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(210,1004,32, 4, 4,0x205e,0x000f,-2, 4,0x0101,pm4, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(211,1008,32, 4, 4,0x205f,0x000f,-2, 4,0x0101,pm5, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(212,1012,32, 4, 4,0x2060,0x000f,-2, 4,0x0101,pm6, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(213,1016,32, 4, 4,0x2061,0x000f,-2, 4,0x0101,pm7, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(214,1020,32, 4, 4,0x2062,0x000f,-2, 4,0x0101,pmctrl0, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(215,1024,32, 4, 4,0x2063,0x000f,-2, 4,0x0101,pmctrl1, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(216,1028,32, 4, 4,0x2064,0x000f,-2, 4,0x0101,pmctrl2, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(217,1032,32, 4, 4,0x2065,0x000f,-2, 4,0x0101,pmctrl3, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(218,1036,32, 4, 4,0x2066,0x000f,-2, 4,0x0101,pmctrl4, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(219,1040,32, 4, 4,0x2067,0x000f,-2, 4,0x0101,pmctrl5, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(220,1044,32, 4, 4,0x2068,0x000f,-2, 4,0x0101,pmctrl6, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(221,1048,32, 4, 4,0x2069,0x000f,-2, 4,0x0101,pmctrl7, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(222,1052,32, 4, 4,0x206a,0x000f,-2, 4,0x0101,pmstat0, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(223,1056,32, 4, 4,0x206b,0x000f,-2, 4,0x0101,pmstat1, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(224,1060,32, 4, 4,0x206c,0x000f,-2, 4,0x0101,pmstat2, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(225,1064,32, 4, 4,0x206d,0x000f,-2, 4,0x0101,pmstat3, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(226,1068,32, 4, 4,0x206e,0x000f,-2, 4,0x0101,pmstat4, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(227,1072,32, 4, 4,0x206f,0x000f,-2, 4,0x0101,pmstat5, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(228,1076,32, 4, 4,0x2070,0x000f,-2, 4,0x0101,pmstat6, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(229,1080,32, 4, 4,0x2071,0x000f,-2, 4,0x0101,pmstat7, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(230,1084,32, 4, 4,0x2072,0x0003,-2, 4,0x0101,ocdid, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(231,1088,32, 4, 4,0x2073,0x000f,-2, 4,0x0101,ocd_dcrclr, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(232,1092,32, 4, 4,0x2074,0x000f,-2, 4,0x0101,ocd_dcrset, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(233,1096,32, 4, 4,0x2075,0x000f,-2, 4,0x0101,ocd_dsr, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(234,1100,32, 4, 4,0x0000,0x0006,-2, 8,0x2100,a0, 0,0,0,0,0,0) + XTREG(235,1104,32, 4, 4,0x0001,0x0006,-2, 8,0x2100,a1, 0,0,0,0,0,0) + XTREG(236,1108,32, 4, 4,0x0002,0x0006,-2, 8,0x2100,a2, 0,0,0,0,0,0) + XTREG(237,1112,32, 4, 4,0x0003,0x0006,-2, 8,0x2100,a3, 0,0,0,0,0,0) + XTREG(238,1116,32, 4, 4,0x0004,0x0006,-2, 8,0x2100,a4, 0,0,0,0,0,0) + XTREG(239,1120,32, 4, 4,0x0005,0x0006,-2, 8,0x2100,a5, 0,0,0,0,0,0) + XTREG(240,1124,32, 4, 4,0x0006,0x0006,-2, 8,0x2100,a6, 0,0,0,0,0,0) + XTREG(241,1128,32, 4, 4,0x0007,0x0006,-2, 8,0x2100,a7, 0,0,0,0,0,0) + XTREG(242,1132,32, 4, 4,0x0008,0x0006,-2, 8,0x2100,a8, 0,0,0,0,0,0) + XTREG(243,1136,32, 4, 4,0x0009,0x0006,-2, 8,0x2100,a9, 0,0,0,0,0,0) + XTREG(244,1140,32, 4, 4,0x000a,0x0006,-2, 8,0x2100,a10, 0,0,0,0,0,0) + XTREG(245,1144,32, 4, 4,0x000b,0x0006,-2, 8,0x2100,a11, 0,0,0,0,0,0) + XTREG(246,1148,32, 4, 4,0x000c,0x0006,-2, 8,0x2100,a12, 0,0,0,0,0,0) + XTREG(247,1152,32, 4, 4,0x000d,0x0006,-2, 8,0x2100,a13, 0,0,0,0,0,0) + XTREG(248,1156,32, 4, 4,0x000e,0x0006,-2, 8,0x2100,a14, 0,0,0,0,0,0) + XTREG(249,1160,32, 4, 4,0x000f,0x0006,-2, 8,0x2100,a15, 0,0,0,0,0,0) + XTREG(250,1164, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0, + 0,0,&xtensa_mask0,0,0,0) + XTREG(251,1165, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1, + 0,0,&xtensa_mask1,0,0,0) + XTREG(252,1166, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2, + 0,0,&xtensa_mask2,0,0,0) + XTREG(253,1167, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3, + 0,0,&xtensa_mask3,0,0,0) + XTREG(254,1168, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4, + 0,0,&xtensa_mask4,0,0,0) + XTREG(255,1169, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5, + 0,0,&xtensa_mask5,0,0,0) + XTREG(256,1170, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6, + 0,0,&xtensa_mask6,0,0,0) + XTREG(257,1171, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7, + 0,0,&xtensa_mask7,0,0,0) + XTREG(258,1172, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8, + 0,0,&xtensa_mask8,0,0,0) + XTREG(259,1173, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9, + 0,0,&xtensa_mask9,0,0,0) + XTREG(260,1174, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10, + 0,0,&xtensa_mask10,0,0,0) + XTREG(261,1175, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11, + 0,0,&xtensa_mask11,0,0,0) + XTREG(262,1176, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12, + 0,0,&xtensa_mask12,0,0,0) + XTREG(263,1177, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13, + 0,0,&xtensa_mask13,0,0,0) + XTREG(264,1178, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14, + 0,0,&xtensa_mask14,0,0,0) + XTREG(265,1179, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15, + 0,0,&xtensa_mask15,0,0,0) + XTREG(266,1180, 1, 4, 4,0x2002,0x0006,-2, 6,0x1010,vecbaselock, + 0,0,&xtensa_mask16,0,0,0) + XTREG(267,1184, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel, + 0,0,&xtensa_mask17,0,0,0) + XTREG(268,1188, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum, + 0,0,&xtensa_mask18,0,0,0) + XTREG(269,1192, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe, + 0,0,&xtensa_mask19,0,0,0) + XTREG(270,1196, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,psring, + 0,0,&xtensa_mask20,0,0,0) + XTREG(271,1200, 1, 4, 4,0x200c,0x0006,-2, 6,0x1010,psexcm, + 0,0,&xtensa_mask21,0,0,0) + XTREG(272,1204, 2, 4, 4,0x200d,0x0006,-2, 6,0x1010,pscallinc, + 0,0,&xtensa_mask22,0,0,0) + XTREG(273,1208, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,psowb, + 0,0,&xtensa_mask23,0,0,0) + XTREG(274,1212, 6, 4, 4,0x200f,0x0006,-2, 6,0x1010,mpunumentries, + 0,0,&xtensa_mask24,0,0,0) + XTREG(275,1216, 2, 4, 4,0x2010,0x0006,-2, 6,0x1010,opmodeeccfence, + 0,0,&xtensa_mask25,0,0,0) + XTREG(276,1220, 4, 4, 4,0x2015,0x0006,-2, 6,0x1010,dbnum, + 0,0,&xtensa_mask26,0,0,0) + XTREG(277,1224, 1, 4, 4,0x2018,0x0006, 1, 6,0x1010,ae_overflow, + 0,0,&xtensa_mask27,0,0,0) + XTREG(278,1228,14, 4, 4,0x2019,0x0006, 1, 6,0x1010,ae_sar, + 0,0,&xtensa_mask28,0,0,0) + XTREG(279,1232, 1, 4, 4,0x201a,0x0006, 1, 6,0x1010,ae_cwrap, + 0,0,&xtensa_mask29,0,0,0) + XTREG(280,1236, 4, 4, 4,0x201b,0x0006, 1, 6,0x1010,ae_bitptr, + 0,0,&xtensa_mask30,0,0,0) + XTREG(281,1240, 4, 4, 4,0x201c,0x0006, 1, 6,0x1010,ae_bitsused, + 0,0,&xtensa_mask31,0,0,0) + XTREG(282,1244, 4, 4, 4,0x201d,0x0006, 1, 6,0x1010,ae_tablesize, + 0,0,&xtensa_mask32,0,0,0) + XTREG(283,1248, 4, 4, 4,0x201e,0x0006, 1, 6,0x1010,ae_first_ts, + 0,0,&xtensa_mask33,0,0,0) + XTREG(284,1252,27, 4, 4,0x201f,0x0006, 1, 6,0x1010,ae_nextoffset, + 0,0,&xtensa_mask34,0,0,0) + XTREG(285,1256, 1, 4, 4,0x2020,0x0006, 1, 6,0x1010,ae_searchdone, + 0,0,&xtensa_mask35,0,0,0) + XTREG(286,1260, 8, 4, 4,0x2021,0x0006, 1, 6,0x1010,ae_zbiasv8, + 0,0,&xtensa_mask36,0,0,0) + XTREG(287,1264, 8, 4, 4,0x2022,0x0006, 1, 6,0x1010,ae_zbiasc8, + 0,0,&xtensa_mask37,0,0,0) + XTREG(288,1268, 2, 4, 4,0x2023,0x0006, 1, 6,0x1010,roundmode, + 0,0,&xtensa_mask38,0,0,0) + XTREG(289,1272, 1, 4, 4,0x2024,0x0006, 1, 6,0x1010,invalidflag, + 0,0,&xtensa_mask39,0,0,0) + XTREG(290,1276, 1, 4, 4,0x2025,0x0006, 1, 6,0x1010,divzeroflag, + 0,0,&xtensa_mask40,0,0,0) + XTREG(291,1280, 1, 4, 4,0x2026,0x0006, 1, 6,0x1010,overflowflag, + 0,0,&xtensa_mask41,0,0,0) + XTREG(292,1284, 1, 4, 4,0x2027,0x0006, 1, 6,0x1010,underflowflag, + 0,0,&xtensa_mask42,0,0,0) + XTREG_END +}; + + + +#ifdef XTENSA_CONFIG_INSTANTIATE +XTENSA_CONFIG_INSTANTIATE(rmap,16) +#endif + diff --git a/overlays/xtensa_mtk_mt818x_adsp/gdb/xtensa-config.h b/overlays/xtensa_mtk_mt818x_adsp/gdb/xtensa-config.h new file mode 100644 index 00000000..84aeb9ea --- /dev/null +++ b/overlays/xtensa_mtk_mt818x_adsp/gdb/xtensa-config.h @@ -0,0 +1,185 @@ +/* Xtensa configuration settings. + Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 + Free Software Foundation, Inc. + Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef XTENSA_CONFIG_H +#define XTENSA_CONFIG_H + +/* The macros defined here match those with the same names in the Xtensa + compile-time HAL (Hardware Abstraction Layer). Please refer to the + Xtensa System Software Reference Manual for documentation of these + macros. */ + +#undef XCHAL_HAVE_BE +#define XCHAL_HAVE_BE 0 + +#undef XCHAL_HAVE_DENSITY +#define XCHAL_HAVE_DENSITY 1 + +#undef XCHAL_HAVE_CONST16 +#define XCHAL_HAVE_CONST16 0 + +#undef XCHAL_HAVE_ABS +#define XCHAL_HAVE_ABS 1 + +#undef XCHAL_HAVE_ADDX +#define XCHAL_HAVE_ADDX 1 + +#undef XCHAL_HAVE_L32R +#define XCHAL_HAVE_L32R 1 + +#undef XSHAL_USE_ABSOLUTE_LITERALS +#define XSHAL_USE_ABSOLUTE_LITERALS 0 + +#undef XSHAL_HAVE_TEXT_SECTION_LITERALS +#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ + +#undef XCHAL_HAVE_MAC16 +#define XCHAL_HAVE_MAC16 0 + +#undef XCHAL_HAVE_MUL16 +#define XCHAL_HAVE_MUL16 1 + +#undef XCHAL_HAVE_MUL32 +#define XCHAL_HAVE_MUL32 1 + +#undef XCHAL_HAVE_MUL32_HIGH +#define XCHAL_HAVE_MUL32_HIGH 0 + +#undef XCHAL_HAVE_DIV32 +#define XCHAL_HAVE_DIV32 1 + +#undef XCHAL_HAVE_NSA +#define XCHAL_HAVE_NSA 1 + +#undef XCHAL_HAVE_MINMAX +#define XCHAL_HAVE_MINMAX 1 + +#undef XCHAL_HAVE_SEXT +#define XCHAL_HAVE_SEXT 1 + +#undef XCHAL_HAVE_LOOPS +#define XCHAL_HAVE_LOOPS 1 + +#undef XCHAL_HAVE_THREADPTR +#define XCHAL_HAVE_THREADPTR 1 + +#undef XCHAL_HAVE_RELEASE_SYNC +#define XCHAL_HAVE_RELEASE_SYNC 1 + +#undef XCHAL_HAVE_S32C1I +#define XCHAL_HAVE_S32C1I 0 + +#undef XCHAL_HAVE_BOOLEANS +#define XCHAL_HAVE_BOOLEANS 1 + +#undef XCHAL_HAVE_FP +#define XCHAL_HAVE_FP 0 + +#undef XCHAL_HAVE_FP_DIV +#define XCHAL_HAVE_FP_DIV 0 + +#undef XCHAL_HAVE_FP_RECIP +#define XCHAL_HAVE_FP_RECIP 0 + +#undef XCHAL_HAVE_FP_SQRT +#define XCHAL_HAVE_FP_SQRT 0 + +#undef XCHAL_HAVE_FP_RSQRT +#define XCHAL_HAVE_FP_RSQRT 0 + +#undef XCHAL_HAVE_DFP_ACCEL +#define XCHAL_HAVE_DFP_ACCEL 0 +/* For backward compatibility */ +#undef XCHAL_HAVE_DFP_accel +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL + +#undef XCHAL_HAVE_WINDOWED +#define XCHAL_HAVE_WINDOWED 1 + +#undef XCHAL_NUM_AREGS +#define XCHAL_NUM_AREGS 64 + +#undef XCHAL_HAVE_WIDE_BRANCHES +#define XCHAL_HAVE_WIDE_BRANCHES 0 + +#undef XCHAL_ICACHE_SIZE +#define XCHAL_ICACHE_SIZE 65536 + +#undef XCHAL_DCACHE_SIZE +#define XCHAL_DCACHE_SIZE 131072 + +#undef XCHAL_ICACHE_LINESIZE +#define XCHAL_ICACHE_LINESIZE 128 + +#undef XCHAL_DCACHE_LINESIZE +#define XCHAL_DCACHE_LINESIZE 128 + +#undef XCHAL_ICACHE_LINEWIDTH +#define XCHAL_ICACHE_LINEWIDTH 7 + +#undef XCHAL_DCACHE_LINEWIDTH +#define XCHAL_DCACHE_LINEWIDTH 7 + +#undef XCHAL_DCACHE_IS_WRITEBACK +#define XCHAL_DCACHE_IS_WRITEBACK 1 + + +#undef XCHAL_HAVE_MMU +#define XCHAL_HAVE_MMU 0 + + +#undef XCHAL_HAVE_DEBUG +#define XCHAL_HAVE_DEBUG 1 + +#undef XCHAL_NUM_IBREAK +#define XCHAL_NUM_IBREAK 2 + +#undef XCHAL_NUM_DBREAK +#define XCHAL_NUM_DBREAK 2 + +#undef XCHAL_DEBUGLEVEL +#define XCHAL_DEBUGLEVEL 5 + + +#undef XCHAL_MAX_INSTRUCTION_SIZE +#define XCHAL_MAX_INSTRUCTION_SIZE 16 + +#undef XCHAL_INST_FETCH_WIDTH +#define XCHAL_INST_FETCH_WIDTH 16 + + +#undef XSHAL_ABI +#undef XTHAL_ABI_WINDOWED +#undef XTHAL_ABI_CALL0 +#define XSHAL_ABI XTHAL_ABI_WINDOWED +#define XTHAL_ABI_WINDOWED 0 +#define XTHAL_ABI_CALL0 1 + + +#undef XCHAL_M_STAGE +#define XCHAL_M_STAGE 3 + +#undef XTENSA_MARCH_LATEST +#define XTENSA_MARCH_LATEST 281050 + +#undef XTENSA_MARCH_EARLIEST +#define XTENSA_MARCH_EARLIEST 281050 + + +#endif /* !XTENSA_CONFIG_H */ diff --git a/overlays/xtensa_mtk_mt818x_adsp/gdb/xtensa-modules.c b/overlays/xtensa_mtk_mt818x_adsp/gdb/xtensa-modules.c new file mode 100644 index 00000000..733bb4b6 --- /dev/null +++ b/overlays/xtensa_mtk_mt818x_adsp/gdb/xtensa-modules.c @@ -0,0 +1,243798 @@ +/* Xtensa configuration-specific ISA information. + + Copyright (c) 2003-2024 Cadence Design Systems, Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "ansidecl.h" +#include +#include "xtensa-isa-internal.h" + + +/* Sysregs. */ + +static xtensa_sysreg_internal sysregs[] = { + { "LBEG", 0, 0 }, + { "LEND", 1, 0 }, + { "LCOUNT", 2, 0 }, + { "BR", 4, 0 }, + { "MMID", 89, 0 }, + { "DDR", 104, 0 }, + { "CONFIGID0", 176, 0 }, + { "CONFIGID1", 208, 0 }, + { "INTERRUPT", 226, 0 }, + { "INTCLEAR", 227, 0 }, + { "CCOUNT", 234, 0 }, + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, + { "CCOMPARE1", 241, 0 }, + { "CCOMPARE2", 242, 0 }, + { "VECBASE", 231, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EPC3", 179, 0 }, + { "EPC4", 180, 0 }, + { "EPC5", 181, 0 }, + { "EPC6", 182, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EXCSAVE3", 211, 0 }, + { "EXCSAVE4", 212, 0 }, + { "EXCSAVE5", 213, 0 }, + { "EXCSAVE6", 214, 0 }, + { "EPS2", 194, 0 }, + { "EPS3", 195, 0 }, + { "EPS4", 196, 0 }, + { "EPS5", 197, 0 }, + { "EPS6", 198, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, + { "WINDOWBASE", 72, 0 }, + { "WINDOWSTART", 73, 0 }, + { "MEMCTL", 97, 0 }, + { "SAR", 3, 0 }, + { "PS", 230, 0 }, + { "MISC0", 244, 0 }, + { "MISC1", 245, 0 }, + { "MISC2", 246, 0 }, + { "MISC3", 247, 0 }, + { "MPUCFG", 92, 0 }, + { "OPMODE", 119, 0 }, + { "INTENABLE", 228, 0 }, + { "DBREAKA0", 144, 0 }, + { "DBREAKC0", 160, 0 }, + { "DBREAKA1", 145, 0 }, + { "DBREAKC1", 161, 0 }, + { "IBREAKA0", 128, 0 }, + { "IBREAKA1", 129, 0 }, + { "IBREAKENABLE", 96, 0 }, + { "ICOUNTLEVEL", 237, 0 }, + { "DEBUGCAUSE", 233, 0 }, + { "PREFCTL", 40, 0 }, + { "CACHEADRDIS", 98, 0 }, + { "MPUENB", 90, 0 }, + { "CPENABLE", 224, 0 }, + { "ATOMCTL", 99, 0 }, + { "ERACCESS", 95, 0 }, + { "THREADPTR", 231, 1 }, + { "AE_OVF_SAR", 240, 1 }, + { "AE_BITHEAD", 241, 1 }, + { "AE_TS_FTS_BU_BP", 242, 1 }, + { "AE_CW_SD_NO", 243, 1 }, + { "AE_CBEGIN0", 246, 1 }, + { "AE_CEND0", 247, 1 }, + { "AE_CBEGIN1", 248, 1 }, + { "AE_CEND1", 249, 1 }, + { "AE_CBEGIN2", 250, 1 }, + { "AE_CEND2", 251, 1 }, + { "AE_ZBIASV8C", -1, 1 }, + { "FCR_FSR", -1, 1 }, + { "EXPSTATE", 230, 1 } +}; + +#define NUM_SYSREGS 78 +#define MAX_SPECIAL_REG 247 +#define MAX_USER_REG 251 + + +/* Processor states. */ + +static xtensa_state_internal states[] = { + { "LCOUNT", 32, 0 }, + { "PC", 32, 0 }, + { "DDR", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "INTERRUPT", 32, 0 }, + { "CCOUNT", 32, 0 }, + { "XTSYNC", 1, 0 }, + { "VECBASE", 22, 0 }, + { "VECBASELOCK", 1, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EPC3", 32, 0 }, + { "EPC4", 32, 0 }, + { "EPC5", 32, 0 }, + { "EPC6", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EXCSAVE3", 32, 0 }, + { "EXCSAVE4", 32, 0 }, + { "EXCSAVE5", 32, 0 }, + { "EXCSAVE6", 32, 0 }, + { "EPS2", 15, 0 }, + { "EPS3", 15, 0 }, + { "EPS4", 15, 0 }, + { "EPS5", 15, 0 }, + { "EPS6", 15, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, + { "PSWOE", 1, 0 }, + { "PSRING", 2, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, + { "WindowBase", 4, 0 }, + { "WindowStart", 16, 0 }, + { "PSCALLINC", 2, 0 }, + { "PSOWB", 4, 0 }, + { "LBEG", 32, 0 }, + { "LEND", 32, 0 }, + { "MEMCTL", 24, 0 }, + { "SAR", 6, 0 }, + { "THREADPTR", 32, 0 }, + { "MISC0", 32, 0 }, + { "MISC1", 32, 0 }, + { "MISC2", 32, 0 }, + { "MISC3", 32, 0 }, + { "MPUNUMENTRIES", 6, 0 }, + { "OPMODEECCFENCE", 2, 0 }, + { "InOCDMode", 1, 0 }, + { "INTENABLE", 32, 0 }, + { "DBREAKA0", 32, 0 }, + { "DBREAKC0", 8, 0 }, + { "DBREAKA1", 32, 0 }, + { "DBREAKC1", 8, 0 }, + { "IBREAKA0", 32, 0 }, + { "IBREAKA1", 32, 0 }, + { "IBREAKENABLE", 2, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, + { "CCOMPARE0", 32, 0 }, + { "CCOMPARE1", 32, 0 }, + { "CCOMPARE2", 32, 0 }, + { "PREFCTL", 13, 0 }, + { "CACHEADRDIS", 8, 0 }, + { "MPUENB", 32, 0 }, + { "CPENABLE", 2, 0 }, + { "ATOMCTL", 9, 0 }, + { "ERI_RAW_INTERLOCK", 1, 0 }, + { "ERACCESS", 16, 0 }, + { "AE_OVERFLOW", 1, XTENSA_STATE_IS_SHARED_OR }, + { "AE_CBEGIN0", 32, 0 }, + { "AE_CEND0", 32, 0 }, + { "AE_CBEGIN1", 32, 0 }, + { "AE_CEND1", 32, 0 }, + { "AE_CBEGIN2", 32, 0 }, + { "AE_CEND2", 32, 0 }, + { "AE_SAR", 14, 0 }, + { "AE_CWRAP", 1, 0 }, + { "AE_BITHEAD", 32, 0 }, + { "AE_BITPTR", 4, 0 }, + { "AE_BITSUSED", 4, 0 }, + { "AE_TABLESIZE", 4, 0 }, + { "AE_FIRST_TS", 4, 0 }, + { "AE_NEXTOFFSET", 27, 0 }, + { "AE_SEARCHDONE", 1, 0 }, + { "AE_ZBIASV8", 8, 0 }, + { "AE_ZBIASC8", 8, 0 }, + { "RoundMode", 2, 0 }, + { "InvalidFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "DivZeroFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "OverflowFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "UnderflowFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "InexactFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } +}; + +#define NUM_STATES 96 + +enum xtensa_state_id { + STATE_LCOUNT, + STATE_PC, + STATE_DDR, + STATE_ICOUNT, + STATE_INTERRUPT, + STATE_CCOUNT, + STATE_XTSYNC, + STATE_VECBASE, + STATE_VECBASELOCK, + STATE_EPC1, + STATE_EPC2, + STATE_EPC3, + STATE_EPC4, + STATE_EPC5, + STATE_EPC6, + STATE_EXCSAVE1, + STATE_EXCSAVE2, + STATE_EXCSAVE3, + STATE_EXCSAVE4, + STATE_EXCSAVE5, + STATE_EXCSAVE6, + STATE_EPS2, + STATE_EPS3, + STATE_EPS4, + STATE_EPS5, + STATE_EPS6, + STATE_EXCCAUSE, + STATE_PSINTLEVEL, + STATE_PSUM, + STATE_PSWOE, + STATE_PSRING, + STATE_PSEXCM, + STATE_DEPC, + STATE_EXCVADDR, + STATE_WindowBase, + STATE_WindowStart, + STATE_PSCALLINC, + STATE_PSOWB, + STATE_LBEG, + STATE_LEND, + STATE_MEMCTL, + STATE_SAR, + STATE_THREADPTR, + STATE_MISC0, + STATE_MISC1, + STATE_MISC2, + STATE_MISC3, + STATE_MPUNUMENTRIES, + STATE_OPMODEECCFENCE, + STATE_InOCDMode, + STATE_INTENABLE, + STATE_DBREAKA0, + STATE_DBREAKC0, + STATE_DBREAKA1, + STATE_DBREAKC1, + STATE_IBREAKA0, + STATE_IBREAKA1, + STATE_IBREAKENABLE, + STATE_ICOUNTLEVEL, + STATE_DEBUGCAUSE, + STATE_DBNUM, + STATE_CCOMPARE0, + STATE_CCOMPARE1, + STATE_CCOMPARE2, + STATE_PREFCTL, + STATE_CACHEADRDIS, + STATE_MPUENB, + STATE_CPENABLE, + STATE_ATOMCTL, + STATE_ERI_RAW_INTERLOCK, + STATE_ERACCESS, + STATE_AE_OVERFLOW, + STATE_AE_CBEGIN0, + STATE_AE_CEND0, + STATE_AE_CBEGIN1, + STATE_AE_CEND1, + STATE_AE_CBEGIN2, + STATE_AE_CEND2, + STATE_AE_SAR, + STATE_AE_CWRAP, + STATE_AE_BITHEAD, + STATE_AE_BITPTR, + STATE_AE_BITSUSED, + STATE_AE_TABLESIZE, + STATE_AE_FIRST_TS, + STATE_AE_NEXTOFFSET, + STATE_AE_SEARCHDONE, + STATE_AE_ZBIASV8, + STATE_AE_ZBIASC8, + STATE_RoundMode, + STATE_InvalidFlag, + STATE_DivZeroFlag, + STATE_OverflowFlag, + STATE_UnderflowFlag, + STATE_InexactFlag, + STATE_EXPSTATE +}; + + +/* Field definitions. */ + +static unsigned +Field_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_n_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_m_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_inst_15_12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_inst_15_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_inst_11_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_inst_11_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_inst16b_15_13_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_ae_fld_inst16b_15_13_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_ae_fld_inst16b_12_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_ae_fld_inst16b_12_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 3) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_19_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 3) >> 18); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x1fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_3_2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_17_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 3) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_22_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 11) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 3) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_21_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe00000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_19_19_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_18_16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_3_3_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 3) >> 15); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_3_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_28_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 3) >> 7); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_28_14_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 3) >> 17); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_14_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 3) >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 3) >> 13); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x1ffffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot0_8_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_8_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_28_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 3) >> 11); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x1fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_1_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_3_1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_9_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_12_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_12_10_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot0_17_10_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 14) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot0_12_6_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_6_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 3) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_27_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000000) | (tie_t << 27); +} + +static unsigned +Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 8) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot0_23_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_18_13_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 3) >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_17_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_9_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_11_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae_slot0_5_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_5_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_4_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_4_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_18_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_19_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot0_19_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_18_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 13) >> 21); + return tie_t; +} + +static void +Field_fld_ae_slot0_18_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_5_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_4_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_19_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_19_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_19_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_23_19_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_14_13_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_17_13_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_13_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_23_22_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_28_24_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 3) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_24_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_14_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_slot0_28_26_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 3) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_26_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c000000) | (tie_t << 26); +} + +static unsigned +Field_fld_ae_slot0_23_17_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot0_23_17_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot0_9_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_9_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_9_9_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_slot0_7_3_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_3_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae_slot0_12_9_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 19) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_9_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_slot0_14_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_14_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 6) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_16_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 6) >> 18); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 6) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_17_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot1_7_4_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot1_25_1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 6) >> 7); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_slot1_0_0_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot1_0_0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot1_3_0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot1_25_9_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 6) >> 15); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_9_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 6) >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x3ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot1_3_3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae_slot1_3_2_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot1_3_2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 6) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_18_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 6) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot1_17_8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot1_17_13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot1_12_8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot1_12_8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot1_17_17_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot1_17_17_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot1_25_22_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 6) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_22_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae_slot1_25_23_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 6) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_23_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae_slot2_28_4_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 3) >> 7); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_4_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot2_3_0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot2_3_0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 3) >> 18); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_15_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x1fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_5_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 3) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_20_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_7_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_fld_ae_slot2_9_1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 22) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot2_9_2_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_2_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot2_28_19_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 3) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_19_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot2_14_0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 17) >> 17); + return tie_t; +} + +static void +Field_fld_ae_slot2_14_0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot2_28_17_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 3) >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_17_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot2_14_5_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot2_14_5_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_slot2_16_15_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot2_16_15_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 3) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_25_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_slot2_14_10_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot2_14_10_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot2_19_15_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot2_28_5_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 3) >> 8); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_5_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0x1fffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_slot2_9_6_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_6_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae_slot2_9_8_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_8_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot2_14_14_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot2_14_14_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_slot3_36_12_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 20) | (insn[0] >> 12); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_12_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 20); +} + +static unsigned +Field_fld_ae_slot3_11_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot3_11_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_30_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 12) >> 12); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot3_9_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 17) >> 17); + return tie_t; +} + +static void +Field_fld_ae_slot3_14_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_25_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae_slot3_19_19_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_19_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_14_10_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_4_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_ae_slot3_24_10_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot3_36_16_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 16) | (insn[0] >> 16); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_16_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 16); +} + +static unsigned +Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_10_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_24_20_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_20_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_9_5_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot3_16_13_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot3_24_19_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 7) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot3_24_19_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x1f80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 10) | (insn[0] >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_22_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xffc00000) | (tie_t << 22); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 10); +} + +static unsigned +Field_fld_ae_slot3_19_17_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_17_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot3_14_13_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot3_14_13_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_15_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot3_14_12_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot3_14_12_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot3_9_1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 22) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot3_9_1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_slot3_9_3_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 22) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot3_9_3_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae_slot3_36_19_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 13) | (insn[0] >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_19_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xfff80000) | (tie_t << 19); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 13); +} + +static unsigned +Field_fld_ae_slot3_19_18_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_18_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 16) | (insn[0] >> 16); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 16); +} + +static unsigned +Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 13) | (insn[0] >> 19); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xfff80000) | (tie_t << 19); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 13); +} + +static unsigned +Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 15) | (insn[0] >> 17); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xfffe0000) | (tie_t << 17); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 15); +} + +static unsigned +Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 11) | (insn[0] >> 21); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffe00000) | (tie_t << 21); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 11); +} + +static unsigned +Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_15_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 5) | (insn[0] >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 5); +} + +static unsigned +Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 14); +} + +static unsigned +Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae2_slot0_12_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_ae2_slot0_12_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_12_2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_ae2_slot0_12_2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae2_slot0_14_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_fld_ae2_slot0_14_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 8) | (insn[0] >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xff000000) | (tie_t << 24); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 8); +} + +static unsigned +Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_15_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae2_slot0_40_26_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 6) | (insn[0] >> 26); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_26_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 6); +} + +static unsigned +Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + return tie_t; +} + +static void +Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae2_slot0_18_17_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_18_17_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 9) | (insn[0] >> 23); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xff800000) | (tie_t << 23); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 9); +} + +static unsigned +Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 20) | (insn[0] >> 12); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 20); +} + +static unsigned +Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot1_11_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot1_11_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 16) | (insn[0] >> 16); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 16); +} + +static unsigned +Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot1_36_17_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 15) | (insn[0] >> 17); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_17_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffe0000) | (tie_t << 17); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 15); +} + +static unsigned +Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot1_3_3_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot1_3_3_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 18); +} + +static unsigned +Field_fld_ae2_slot1_3_2_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot1_3_2_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot1_36_18_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_18_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 14); +} + +static unsigned +Field_fld_ae2_slot1_36_22_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 10) | (insn[0] >> 22); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_22_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xffc00000) | (tie_t << 22); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 10); +} + +static unsigned +Field_fld_ae2_slot1_36_23_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 9) | (insn[0] >> 23); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_23_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xff800000) | (tie_t << 23); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 9); +} + +static unsigned +Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 14); +} + +static unsigned +Field_fld_ae2_slot2_17_0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_fld_ae2_slot2_17_0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 7) >> 12); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0x1ffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 7) >> 22); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 14) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + return tie_t; +} + +static void +Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot2_42_26_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 6) | (insn[0] >> 26); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_26_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 6); +} + +static unsigned +Field_fld_ae2_slot2_42_28_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 4) | (insn[0] >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_28_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xf0000000) | (tie_t << 28); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 4); +} + +static unsigned +Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 7) >> 16); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x1fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 12) >> 21); + return tie_t; +} + +static void +Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 15) | (insn[0] >> 17); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xfffe0000) | (tie_t << 17); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 15); +} + +static unsigned +Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 20) | (insn[0] >> 12); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 20); +} + +static unsigned +Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 14); +} + +static unsigned +Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 24) | (insn[0] >> 8); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff00) | (tie_t << 8); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 24); +} + +static unsigned +Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae3_slot0_32_16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 16) | (insn[0] >> 16); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 16); +} + +static unsigned +Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 21) | (insn[0] >> 11); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xfffff800) | (tie_t << 11); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 21); +} + +static unsigned +Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 19) | (insn[0] >> 13); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffffe000) | (tie_t << 13); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 19); +} + +static unsigned +Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 5) | (insn[0] >> 27); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 5); +} + +static unsigned +Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae3_slot0_7_2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_ae3_slot0_7_2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 18); +} + +static unsigned +Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_9_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ae3_slot0_9_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae3_slot1_23_17_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_17_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot1_23_0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot1_23_11_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 8) >> 19); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_11_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 8) >> 21); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 8) >> 23); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae3_slot1_23_19_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_19_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae3_slot1_3_1_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae3_slot1_3_1_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae3_slot1_23_9_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_9_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 2) >> 18); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 2) >> 14); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 2) >> 20); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 2) >> 7); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae5_slot0_29_17_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 2) >> 19); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_17_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x3ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 2) >> 10); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x3fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 2) >> 15); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 2) >> 29); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000000) | (tie_t << 27); +} + +static unsigned +Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 2) >> 17); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x3fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2) | (tie_t << 1); +} + +static unsigned +Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae5_slot0_29_6_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 2) >> 8); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_6_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0x3fffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 19) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae5_slot0_29_19_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 2) >> 21); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_19_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x3ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae5_slot0_7_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae5_slot0_7_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae5_slot0_12_6_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_fld_ae5_slot0_12_6_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae5_slot1_1_0_Slot_ae5_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot1_1_0_Slot_ae5_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot2_24_0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 7) >> 7); + return tie_t; +} + +static void +Field_fld_ae5_slot2_24_0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae5_slot2_14_5_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_ae5_slot2_14_5_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae5_slot2_9_7_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_fld_ae5_slot2_9_7_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 7) >> 24); + return tie_t; +} + +static void +Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 7) >> 22); + return tie_t; +} + +static void +Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot0_29_5_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 2) >> 7); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_5_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 2) >> 17); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x3fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 2) >> 20); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae6_slot0_7_4_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae6_slot0_7_4_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 2) >> 12); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0x3ffffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 2) >> 15); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 2) >> 16); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x3fffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 4) >> 16); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae6_slot1_27_3_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 4) >> 7); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_3_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae6_slot1_2_0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae6_slot1_2_0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 4) >> 19); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 4) >> 24); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 4) >> 10); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xfffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae6_slot1_9_5_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot1_9_5_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae6_slot1_27_21_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 4) >> 25); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_21_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe00000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae6_slot2_24_0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 7) >> 7); + return tie_t; +} + +static void +Field_fld_ae6_slot2_24_0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 7) >> 22); + return tie_t; +} + +static void +Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 7) >> 21); + return tie_t; +} + +static void +Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot2_24_10_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_ae6_slot2_24_10_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_fld_ae6_slot2_24_20_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot2_24_20_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae6_slot3_37_13_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | (insn[1] & 0x3f); + tie_t = (tie_t << 19) | (insn[0] >> 13); + return tie_t; +} + +static void +Field_fld_ae6_slot3_37_13_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffe000) | (tie_t << 13); + insn[1] = (insn[1] & ~0x3f) | (tie_t >> 19); +} + +static unsigned +Field_fld_ae6_slot3_12_0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_ae6_slot3_12_0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | (insn[1] & 0x3f); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x3f) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | (insn[1] & 0x3f); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x3f) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae6_slot3_24_20_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot3_24_20_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae6_slot3_14_0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 17) >> 17); + return tie_t; +} + +static void +Field_fld_ae6_slot3_14_0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | (insn[1] & 0x3f); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x3f) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_ae7_slot0_23_0_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_ae7_slot0_23_0_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 8) >> 21); + return tie_t; +} + +static void +Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + return tie_t; +} + +static void +Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot0_12_6_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot0_12_6_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot1_23_0_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_ae7_slot1_23_0_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 8) >> 21); + return tie_t; +} + +static void +Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + return tie_t; +} + +static void +Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot1_12_6_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot1_12_6_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot2_36_12_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 20) | (insn[0] >> 12); + return tie_t; +} + +static void +Field_fld_ae7_slot2_36_12_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 20); +} + +static unsigned +Field_fld_ae7_slot2_11_0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); + return tie_t; +} + +static void +Field_fld_ae7_slot2_11_0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae7_slot2_14_10_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae7_slot2_14_10_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae7_slot3_35_11_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | (insn[1] & 0xf); + tie_t = (tie_t << 21) | (insn[0] >> 11); + return tie_t; +} + +static void +Field_fld_ae7_slot3_35_11_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffff800) | (tie_t << 11); + insn[1] = (insn[1] & ~0xf) | (tie_t >> 21); +} + +static unsigned +Field_fld_ae7_slot3_10_0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 21) >> 21); + return tie_t; +} + +static void +Field_fld_ae7_slot3_10_0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | (insn[1] & 0xf); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0xf) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae7_slot3_24_10_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_ae7_slot3_24_10_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae7_slot3_4_0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae7_slot3_4_0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | (insn[1] & 0xf); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0xf) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | (insn[1] & 0xf); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0xf) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 0) >> 18); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 0) >> 12); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 0) >> 8); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot0_13_13_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_fld_ae8_slot0_13_13_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 0) >> 20); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae8_slot0_31_7_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 0) >> 7); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_7_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae8_slot0_6_0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ae8_slot0_6_0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot0_31_9_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 0) >> 9); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_9_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xfffffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 0) >> 15); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae8_slot0_7_5_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ae8_slot0_7_5_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 18) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 14) >> 18); + return tie_t; +} + +static void +Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 0) >> 19); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae8_slot0_8_0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_ae8_slot0_8_0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot0_17_8_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot0_17_8_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae8_slot0_31_21_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 0) >> 21); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_21_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe00000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae8_slot0_31_22_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 0) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_22_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae8_slot0_31_23_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 0) >> 23); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_23_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + return tie_t; +} + +static void +Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 2) >> 14); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae8_slot1_17_15_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae8_slot1_17_15_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae8_slot1_29_5_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 2) >> 7); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_5_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae8_slot1_4_0_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae8_slot1_4_0_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 2) >> 10); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x3fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot1_29_9_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 2) >> 11); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_9_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x3ffffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 2) >> 15); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 2) >> 20); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae8_slot1_29_22_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 2) >> 24); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_22_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae8_slot1_29_23_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 2) >> 25); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_23_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[1] << 5) >> 7); + return tie_t; +} + +static void +Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[1] = (insn[1] & ~0x7fffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae8_slot2_33_9_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 23) | (insn[0] >> 9); + return tie_t; +} + +static void +Field_fld_ae8_slot2_33_9_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffffe00) | (tie_t << 9); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 23); +} + +static unsigned +Field_fld_ae8_slot2_8_0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_ae8_slot2_8_0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot2_33_25_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae8_slot2_33_25_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae8_slot2_19_15_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae8_slot2_19_15_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[1] << 5) >> 23); + return tie_t; +} + +static void +Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[1] = (insn[1] & ~0x7fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[1] << 5) >> 13); + return tie_t; +} + +static void +Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[1] = (insn[1] & ~0x7ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[1] << 5) >> 8); + return tie_t; +} + +static void +Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[1] = (insn[1] & ~0x7fffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[1] << 19) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[1] = (insn[1] & ~0x1ff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 4) >> 20); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 4) >> 16); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 4) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 4) >> 12); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot0_27_17_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 4) >> 21); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_17_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 4) >> 24); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae9_slot0_27_3_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 4) >> 7); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_3_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae9_slot0_2_0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae9_slot0_2_0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 4) >> 14); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 4) >> 17); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae9_slot0_7_6_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae9_slot0_7_6_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 14) >> 18); + return tie_t; +} + +static void +Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae9_slot0_27_19_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 4) >> 23); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_19_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 19) >> 24); + return tie_t; +} + +static void +Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 23) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae9_slot0_27_22_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 4) >> 26); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_22_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 4) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 5) >> 21); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae9_slot1_26_17_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 5) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_17_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae9_slot1_26_2_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 5) >> 7); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_2_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae9_slot1_1_0_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae9_slot1_1_0_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 5) >> 13); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x7ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot1_26_9_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 5) >> 14); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_9_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x7fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 5) >> 18); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x7ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae9_slot1_3_2_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae9_slot1_3_2_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 5) >> 23); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae9_slot1_26_22_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 5) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_22_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae9_slot1_26_23_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_23_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae9_slot2_33_9_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 23) | (insn[0] >> 9); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_9_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffffe00) | (tie_t << 9); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 23); +} + +static unsigned +Field_fld_ae9_slot2_8_0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_ae9_slot2_8_0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 6) | (insn[0] >> 26); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 6); +} + +static unsigned +Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 4) | (insn[0] >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xf0000000) | (tie_t << 28); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 4); +} + +static unsigned +Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 18); +} + +static unsigned +Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 7) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 7) >> 21); + return tie_t; +} + +static void +Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae9_slot3_31_7_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 0) >> 7); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_7_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae9_slot3_6_0_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ae9_slot3_6_0_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 0) >> 25); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae9_slot3_4_4_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot3_4_4_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 0) >> 15); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 0) >> 20); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 0) >> 26); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); +} + +static unsigned +Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 0) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000000) | (tie_t << 28); +} + +static unsigned +Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 0) >> 14); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); +} + +static unsigned +Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 7) >> 23); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 7) >> 19); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 7) >> 25); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 7) >> 15); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot0_24_17_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 7) >> 24); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_17_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae10_slot0_24_0_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 7) >> 7); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_0_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 7) >> 20); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae10_slot0_7_6_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot0_7_6_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 14) >> 18); + return tie_t; +} + +static void +Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae10_slot0_17_8_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot0_17_8_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 6) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 6) >> 18); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae10_slot1_25_17_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 6) >> 23); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_17_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae10_slot1_25_1_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 6) >> 7); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_1_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae10_slot1_0_0_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot1_0_0_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot1_25_9_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 6) >> 15); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_9_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 6) >> 19); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x3ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae10_slot1_3_2_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot1_3_2_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 6) >> 24); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 6) >> 26); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae10_slot1_25_22_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 6) >> 28); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_22_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae10_slot1_25_23_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 6) >> 29); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_23_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae10_slot2_34_10_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 22) | (insn[0] >> 10); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_10_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffffc00) | (tie_t << 10); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 22); +} + +static unsigned +Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 1) | (insn[0] >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x80000000) | (tie_t << 31); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 1); +} + +static unsigned +Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[1] << 29) >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[1] = (insn[1] & ~0x6) | (tie_t << 1); +} + +static unsigned +Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 18); +} + +static unsigned +Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae10_slot3_34_10_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 22) | (insn[0] >> 10); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_10_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffffc00) | (tie_t << 10); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 22); +} + +static unsigned +Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae10_slot3_4_4_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot3_4_4_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 1) | (insn[0] >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x80000000) | (tie_t << 31); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 1); +} + +static unsigned +Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[1] << 29) >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[1] = (insn[1] & ~0x6) | (tie_t << 1); +} + +static unsigned +Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 18); +} + +static unsigned +Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); +} + +static unsigned +Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 9) >> 21); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 9) >> 17); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot0_22_17_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 9) >> 26); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_17_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae4_slot0_22_20_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_20_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae4_slot0_22_0_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 9) >> 9); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_0_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot0_3_1_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot0_3_1_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 9) >> 22); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 9) >> 15); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x7fffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 9) >> 21); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae4_slot1_22_17_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 9) >> 26); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_17_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae4_slot1_22_0_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 9) >> 9); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_0_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 9) >> 17); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot1_3_1_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot1_3_1_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 9) >> 22); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae4_slot2_23_0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_ae4_slot2_23_0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 8) >> 23); + return tie_t; +} + +static void +Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae4_slot2_23_17_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_ae4_slot2_23_17_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae4_slot2_4_0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot2_4_0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae4_slot3_27_3_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 4) >> 7); + return tie_t; +} + +static void +Field_fld_ae4_slot3_27_3_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae4_slot3_2_0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot3_2_0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae4_slot3_19_19_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_fld_ae4_slot3_19_19_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae4_slot3_19_5_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 12) >> 17); + return tie_t; +} + +static void +Field_fld_ae4_slot3_19_5_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae4_slot3_27_20_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 4) >> 24); + return tie_t; +} + +static void +Field_fld_ae4_slot3_27_20_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae4_slot3_14_10_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot3_14_10_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae4_slot4_22_0_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 9) >> 9); + return tie_t; +} + +static void +Field_fld_ae4_slot4_22_0_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 9) >> 24); + return tie_t; +} + +static void +Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_t_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_t_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 23) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e0) | (tie_t << 5); +} + +static unsigned +Field_t_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bbi_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_bbi_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_bbi_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 24) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_imm8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_imm8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_imm8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29); + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_imm8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); + tie_t = (val << 24) >> 29; + insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14); +} + +static unsigned +Field_imm8_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_imm8_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_imm8_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_imm8_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_imm8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_s_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_s8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_s8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_s8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_s8_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_s8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_s8_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_s8_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_imms8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_imms8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 22) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); + tie_t = (val << 21) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 20) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_imm12b_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_imm12b_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 20) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_imm12b_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_imm12b_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 10) | ((insn[0] << 18) >> 22); + return tie_t; +} + +static void +Field_imm12b_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0) | (tie_t << 4); + tie_t = (val << 20) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_imm12b_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 11) | ((insn[0] << 13) >> 21); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 17) >> 21; + insn[0] = (insn[0] & ~0x7ff00) | (tie_t << 8); + tie_t = (val << 16) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_imm16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 14) | ((insn[0] << 14) >> 18); + return tie_t; +} + +static void +Field_imm16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0) | (tie_t << 4); + tie_t = (val << 16) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_imm16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_imm16_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_imm16_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_imm16_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_offset_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 17) | ((insn[0] << 15) >> 15); + return tie_t; +} + +static void +Field_offset_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff) | (tie_t << 0); + tie_t = (val << 14) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_offset_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 17) | ((insn[0] << 15) >> 15); + return tie_t; +} + +static void +Field_offset_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff) | (tie_t << 0); + tie_t = (val << 14) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_offset_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_op2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_op2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_op2_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_op2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_op2_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_op2_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_op2_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_op2_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_r_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_disp_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_r_disp_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_r_3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r_3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_sae_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_sae_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_sae_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sae_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_sae_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_sal_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_sal_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_sal_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sal_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_sargt_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_sargt_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sargt_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_sargt_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_sas_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sas_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_sas_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_sas_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_sas_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_sas_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_sas_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_sas_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_sas_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_sas_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_sas_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_t2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_t2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_t2_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_t2_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); +} + +static unsigned +Field_s2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_r2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_r2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_r2_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_r2_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_t4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_t4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_t4_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_t4_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); +} + +static unsigned +Field_s4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_s4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_s4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_s4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_s4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_s4_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_s4_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_s4_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_s4_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_s4_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_r4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_r4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_r4_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_r4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_r4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_r4_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_r4_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_r4_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_t8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_r8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_xt_wbr15_imm_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_xt_wbr15_imm_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_xt_wbr15_imm_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae_sem_arithmetic_art_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_art_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_art_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_art_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 6) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 6) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 16) >> 26); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_br4t_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_br4t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpcnv_arr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_arr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_hpcnv_arr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_arr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_hpcnv_art_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_art_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_hpcnv_art_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_art_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 23) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_vu_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_vu_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_vu_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_vu_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_vu_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_vu_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_vu_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_vu_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_rng_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_rng_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_a_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_a_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_shift_a0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_a0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_a0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_shift_a0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_a0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_shift_d1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_d1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_da_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_da_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_da_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_da_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_shift_da_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_da_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_i32_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_shift_i32_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i32_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_i32_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 7) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i32_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_shift_i32_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i32_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_shift_i32_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i32_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_shift_i64_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i64_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_i64_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i64_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_sem_shift_i64_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i64_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_shift_i64_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i64_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_shift_i64_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i64_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_shift_imm32_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_imm32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_imm32_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_imm32_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_imm8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_imm8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_sd_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_sd_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_sd_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_sd_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_sd_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_sd_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_shift_sd_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_sd_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_shift_sd_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_sd_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_arr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_arr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_arr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_arr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_arr_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_arr_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_art_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_art_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_art_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_art_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_art_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_art_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vr_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vr_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vt_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vt_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_slot0_1_1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_1_1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 23) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_ds_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_ds_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_ds_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_ds_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_ds_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_ds_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 1) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000000) | (tie_t << 30); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 1) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000000) | (tie_t << 30); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_imm_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_imm_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_multiply_d1_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d1_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_d1_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d1_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_multiply_d1_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d1_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_multiply_d1_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d1_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d3_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d3_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_multiply_d3_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d3_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d3_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d3_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_multiply_d3_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d3_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_rng_d_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_d_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_shift_e_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_e_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_i8_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i8_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vp_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vp_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vp_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vp_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vp_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vp_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vq_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vq_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vq_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vq_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vq_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vq_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_sb_loads_stores_iba2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sb_loads_stores_iba2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_ardecnorm16_ar_u_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_ardecnorm16_ar_u_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_lb_db_ops_ar_u_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_db_ops_ar_u_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_lb_db_ops_iba_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_db_ops_iba_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_rng_a_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_a_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_rng_art_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_art_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_rng_i2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_i2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_rng_imm2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_imm2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae_sem_mul_nn_c0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_c0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_mul_nn_c1_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_c1_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae_sem_mul_nn_c2_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_c2_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_mul_nn_c3_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_c3_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_nn_q0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_q0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_mul_nn_q1_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_q1_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_nn_q2_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_q2_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_mul_nn_q3_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_q3_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_mul_nn_v0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_v0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_mul_nn_v1_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_v1_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae_sem_mul_nn_v2_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_v2_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_mul_nn_v3_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_v3_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_hpfma_vp_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vp_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vu_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vu_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_vu_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vu_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vu_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vu_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vu_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vu_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vu_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vu_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vq_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vq_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_vq_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vq_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_inst_12_12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_inst_12_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_inst_12_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_inst_12_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_inst_13_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_fld_inst_13_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); +} + +static unsigned +Field_fld_inst_19_17_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_fld_inst_19_17_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_inst_19_18_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_inst_19_18_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_inst_23_12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_fld_inst_23_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_fld_inst_23_16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_fld_inst_23_16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_inst_4_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_inst_4_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_inst_5_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_inst_5_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_inst_7_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_inst_7_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_inst_7_6_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_inst_7_6_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_inst_7_7_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_inst_7_7_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_inst_9_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_inst_9_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) +{ + /* Do nothing. */ +} + +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 4; +} + +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 8; +} + +static unsigned +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 12; +} + +static unsigned +Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +enum xtensa_field_id { + FIELD_t, + FIELD_bbi4, + FIELD_bbi, + FIELD_imm12, + FIELD_imm8, + FIELD_s, + FIELD_s8, + FIELD_imms8, + FIELD_imm12b, + FIELD_imm16, + FIELD_m, + FIELD_n, + FIELD_offset, + FIELD_op0, + FIELD_op1, + FIELD_op2, + FIELD_r, + FIELD_r_disp, + FIELD_r_3, + FIELD_sa4, + FIELD_sae4, + FIELD_sae, + FIELD_sal, + FIELD_sargt, + FIELD_sas4, + FIELD_sas, + FIELD_sr, + FIELD_st, + FIELD_thi3, + FIELD_imm4, + FIELD_mn, + FIELD_i, + FIELD_imm6lo, + FIELD_imm6hi, + FIELD_imm7lo, + FIELD_imm7hi, + FIELD_z, + FIELD_imm6, + FIELD_imm7, + FIELD_t2, + FIELD_s2, + FIELD_r2, + FIELD_t4, + FIELD_s4, + FIELD_r4, + FIELD_t8, + FIELD_r8, + FIELD_xt_wbr15_imm, + FIELD_xt_wbr18_imm, + FIELD_ae_fld_Inst16b_12, + FIELD_ae_fld_Inst16b_15_13, + FIELD_fld_ae_sem_arithmetic_art, + FIELD_fld_ae_sem_arithmetic_ds, + FIELD_fld_ae_sem_arithmetic_v, + FIELD_fld_ae_sem_arithmetic_v0, + FIELD_fld_ae_sem_arithmetic_v1, + FIELD_fld_ae_sem_arithmetic_va, + FIELD_fld_ae_sem_arithmetic_vs, + FIELD_fld_ae_sem_dr_to_ar_a, + FIELD_fld_ae_sem_dr_to_ar_ab, + FIELD_fld_ae_sem_dr_to_ar_ai, + FIELD_fld_ae_sem_dr_to_ar_aoe, + FIELD_fld_ae_sem_dr_to_ar_d, + FIELD_fld_ae_sem_dr_to_ar_d0, + FIELD_fld_ae_sem_dr_to_ar_d1, + FIELD_fld_ae_sem_dr_to_ar_imm8, + FIELD_fld_ae_sem_dr_to_ar_v0, + FIELD_fld_ae_sem_dr_to_ar_vr, + FIELD_fld_ae_sem_dr_to_dr_arr, + FIELD_fld_ae_sem_dr_to_dr_bt, + FIELD_fld_ae_sem_dr_to_dr_ds, + FIELD_fld_ae_sem_dr_to_dr_imm2, + FIELD_fld_ae_sem_dr_to_dr_immed, + FIELD_fld_ae_sem_dr_to_dr_movi_imm, + FIELD_fld_ae_sem_dr_to_dr_v, + FIELD_fld_ae_sem_dr_to_dr_v0, + FIELD_fld_ae_sem_dr_to_dr_v1, + FIELD_fld_ae_sem_hpcmp_br4t, + FIELD_fld_ae_sem_hpcmp_vr, + FIELD_fld_ae_sem_hpcmp_vs, + FIELD_fld_ae_sem_hpcnv_arr, + FIELD_fld_ae_sem_hpcnv_art, + FIELD_fld_ae_sem_hpcnv_i_imm4, + FIELD_fld_ae_sem_hpcnv_vr, + FIELD_fld_ae_sem_hpcnv_vt, + FIELD_fld_ae_sem_hprminmaxnum_vr, + FIELD_fld_ae_sem_hprminmaxnum_vt, + FIELD_fld_ae_sem_lb_ops_iba, + FIELD_fld_ae_sem_loads_stores_a, + FIELD_fld_ae_sem_loads_stores_a_0, + FIELD_fld_ae_sem_loads_stores_av, + FIELD_fld_ae_sem_loads_stores_av1, + FIELD_fld_ae_sem_loads_stores_end, + FIELD_fld_ae_sem_loads_stores_i128, + FIELD_fld_ae_sem_loads_stores_i16, + FIELD_fld_ae_sem_loads_stores_i3, + FIELD_fld_ae_sem_loads_stores_i32, + FIELD_fld_ae_sem_loads_stores_i32pos, + FIELD_fld_ae_sem_loads_stores_i64, + FIELD_fld_ae_sem_loads_stores_i64half, + FIELD_fld_ae_sem_loads_stores_i64neg, + FIELD_fld_ae_sem_loads_stores_i64pos, + FIELD_fld_ae_sem_loads_stores_i64x2, + FIELD_fld_ae_sem_loads_stores_i8, + FIELD_fld_ae_sem_loads_stores_imm2, + FIELD_fld_ae_sem_loads_stores_su, + FIELD_fld_ae_sem_loads_stores_uu, + FIELD_fld_ae_sem_loads_stores_v, + FIELD_fld_ae_sem_loads_stores_v1, + FIELD_fld_ae_sem_loads_stores_vu, + FIELD_fld_ae_sem_loads_stores_x, + FIELD_fld_ae_sem_pks_d, + FIELD_fld_ae_sem_pks_pos, + FIELD_fld_ae_sem_pks_s, + FIELD_fld_ae_sem_rng_v0, + FIELD_fld_ae_sem_rng_v1, + FIELD_fld_ae_sem_sb_loads_stores_iba, + FIELD_fld_ae_sem_shift_a, + FIELD_fld_ae_sem_shift_a0, + FIELD_fld_ae_sem_shift_d, + FIELD_fld_ae_sem_shift_d0, + FIELD_fld_ae_sem_shift_d1, + FIELD_fld_ae_sem_shift_da, + FIELD_fld_ae_sem_shift_i16, + FIELD_fld_ae_sem_shift_i32, + FIELD_fld_ae_sem_shift_i64, + FIELD_fld_ae_sem_shift_imm32, + FIELD_fld_ae_sem_shift_imm8, + FIELD_fld_ae_sem_shift_sd, + FIELD_fld_ae_sem_sp32cvt_arr, + FIELD_fld_ae_sem_sp32cvt_art, + FIELD_fld_ae_sem_sp32cvt_i_imm5, + FIELD_fld_ae_sem_sp32cvt_vr, + FIELD_fld_ae_sem_sp32cvt_vt, + FIELD_fld_ae_sem_spmisc_brt, + FIELD_fld_ae_sem_spmisc_vr, + FIELD_fld_ae_sem_spmisc_vs, + FIELD_fld_ae_slot0_11_10, + FIELD_fld_ae_slot0_11_11, + FIELD_fld_ae_slot0_11_8, + FIELD_fld_ae_slot0_11_9, + FIELD_fld_ae_slot0_12_0, + FIELD_fld_ae_slot0_12_10, + FIELD_fld_ae_slot0_12_12, + FIELD_fld_ae_slot0_12_2, + FIELD_fld_ae_slot0_12_6, + FIELD_fld_ae_slot0_12_8, + FIELD_fld_ae_slot0_12_9, + FIELD_fld_ae_slot0_14_12, + FIELD_fld_ae_slot0_14_13, + FIELD_fld_ae_slot0_17_10, + FIELD_fld_ae_slot0_17_12, + FIELD_fld_ae_slot0_17_13, + FIELD_fld_ae_slot0_17_14, + FIELD_fld_ae_slot0_17_15, + FIELD_fld_ae_slot0_17_16, + FIELD_fld_ae_slot0_17_17, + FIELD_fld_ae_slot0_17_8, + FIELD_fld_ae_slot0_18_13, + FIELD_fld_ae_slot0_18_15, + FIELD_fld_ae_slot0_18_16, + FIELD_fld_ae_slot0_18_8, + FIELD_fld_ae_slot0_19_12, + FIELD_fld_ae_slot0_19_15, + FIELD_fld_ae_slot0_19_19, + FIELD_fld_ae_slot0_19_8, + FIELD_fld_ae_slot0_1_0, + FIELD_fld_ae_slot0_1_1, + FIELD_fld_ae_slot0_20_16, + FIELD_fld_ae_slot0_20_20, + FIELD_fld_ae_slot0_23_15, + FIELD_fld_ae_slot0_23_17, + FIELD_fld_ae_slot0_23_19, + FIELD_fld_ae_slot0_23_22, + FIELD_fld_ae_slot0_28_10, + FIELD_fld_ae_slot0_28_12, + FIELD_fld_ae_slot0_28_14, + FIELD_fld_ae_slot0_28_15, + FIELD_fld_ae_slot0_28_16, + FIELD_fld_ae_slot0_28_17, + FIELD_fld_ae_slot0_28_19, + FIELD_fld_ae_slot0_28_21, + FIELD_fld_ae_slot0_28_22, + FIELD_fld_ae_slot0_28_24, + FIELD_fld_ae_slot0_28_26, + FIELD_fld_ae_slot0_28_27, + FIELD_fld_ae_slot0_28_4, + FIELD_fld_ae_slot0_28_8, + FIELD_fld_ae_slot0_3_0, + FIELD_fld_ae_slot0_3_1, + FIELD_fld_ae_slot0_3_2, + FIELD_fld_ae_slot0_3_3, + FIELD_fld_ae_slot0_4_0, + FIELD_fld_ae_slot0_4_4, + FIELD_fld_ae_slot0_5_0, + FIELD_fld_ae_slot0_5_4, + FIELD_fld_ae_slot0_7_0, + FIELD_fld_ae_slot0_7_2, + FIELD_fld_ae_slot0_7_3, + FIELD_fld_ae_slot0_7_4, + FIELD_fld_ae_slot0_8_8, + FIELD_fld_ae_slot0_9_4, + FIELD_fld_ae_slot0_9_8, + FIELD_fld_ae_slot0_9_9, + FIELD_fld_ae_slot1_0_0, + FIELD_fld_ae_slot1_12_8, + FIELD_fld_ae_slot1_17_13, + FIELD_fld_ae_slot1_17_17, + FIELD_fld_ae_slot1_17_8, + FIELD_fld_ae_slot1_25_1, + FIELD_fld_ae_slot1_25_12, + FIELD_fld_ae_slot1_25_13, + FIELD_fld_ae_slot1_25_16, + FIELD_fld_ae_slot1_25_17, + FIELD_fld_ae_slot1_25_18, + FIELD_fld_ae_slot1_25_20, + FIELD_fld_ae_slot1_25_22, + FIELD_fld_ae_slot1_25_23, + FIELD_fld_ae_slot1_25_8, + FIELD_fld_ae_slot1_25_9, + FIELD_fld_ae_slot1_3_0, + FIELD_fld_ae_slot1_3_2, + FIELD_fld_ae_slot1_3_3, + FIELD_fld_ae_slot1_7_4, + FIELD_fld_ae_sem_arithmetic_e, + FIELD_fld_ae_sem_arithmetic_ep, + FIELD_fld_ae_sem_arithmetic_ep1, + FIELD_fld_ae_sem_dr_to_ar_ei, + FIELD_fld_ae_sem_dr_to_ar_eo, + FIELD_fld_ae_sem_dr_to_dr_immed_N, + FIELD_fld_ae_sem_fpmov_i_imm4, + FIELD_fld_ae_sem_fpmov_vr, + FIELD_fld_ae_sem_fpmov_vs, + FIELD_fld_ae_sem_fpmov_vt, + FIELD_fld_ae_sem_fpmov_vu, + FIELD_fld_ae_sem_hpcmp_vt, + FIELD_fld_ae_sem_hpcnv_vs, + FIELD_fld_ae_sem_hpfma_vr, + FIELD_fld_ae_sem_hpfma_vs, + FIELD_fld_ae_sem_hpfma_vt, + FIELD_fld_ae_sem_movfpstate_v, + FIELD_fld_ae_sem_multiply_acc_ep, + FIELD_fld_ae_sem_multiply_d0, + FIELD_fld_ae_sem_multiply_d2, + FIELD_fld_ae_sem_multiply_q0, + FIELD_fld_ae_sem_multiply_q1, + FIELD_fld_ae_sem_reduction_sort_ds, + FIELD_fld_ae_sem_reduction_sort_v, + FIELD_fld_ae_sem_reduction_sort_v0, + FIELD_fld_ae_sem_select_isel, + FIELD_fld_ae_sem_select_ss, + FIELD_fld_ae_sem_select_vr, + FIELD_fld_ae_sem_select_vs, + FIELD_fld_ae_sem_select_vt, + FIELD_fld_ae_sem_select_vu, + FIELD_fld_ae_sem_spaddsub_vr, + FIELD_fld_ae_sem_spaddsub_vs, + FIELD_fld_ae_sem_spaddsub_vt, + FIELD_fld_ae_sem_spaddsub_vu, + FIELD_fld_ae_sem_spfma_i_imm1, + FIELD_fld_ae_sem_spfma_i_imm3, + FIELD_fld_ae_sem_spfma_vp, + FIELD_fld_ae_sem_spfma_vr, + FIELD_fld_ae_sem_spfma_vs, + FIELD_fld_ae_sem_spfma_vt, + FIELD_fld_ae_sem_spmisc_vsM, + FIELD_fld_ae_sem_spmisc_vt, + FIELD_fld_ae_sem_spmisc_vtM, + FIELD_fld_ae_slot2_14_0, + FIELD_fld_ae_slot2_14_10, + FIELD_fld_ae_slot2_14_14, + FIELD_fld_ae_slot2_14_5, + FIELD_fld_ae_slot2_16_15, + FIELD_fld_ae_slot2_19_15, + FIELD_fld_ae_slot2_28_15, + FIELD_fld_ae_slot2_28_17, + FIELD_fld_ae_slot2_28_19, + FIELD_fld_ae_slot2_28_20, + FIELD_fld_ae_slot2_28_25, + FIELD_fld_ae_slot2_28_4, + FIELD_fld_ae_slot2_28_5, + FIELD_fld_ae_slot2_3_0, + FIELD_fld_ae_slot2_9_0, + FIELD_fld_ae_slot2_9_1, + FIELD_fld_ae_slot2_9_2, + FIELD_fld_ae_slot2_9_5, + FIELD_fld_ae_slot2_9_6, + FIELD_fld_ae_slot2_9_7, + FIELD_fld_ae_slot2_9_8, + FIELD_fld_ae_sem_dr_to_dr_imm, + FIELD_fld_ae_sem_multiply_d1, + FIELD_fld_ae_sem_multiply_d3, + FIELD_fld_ae_sem_rng_d, + FIELD_fld_ae_sem_shift_e, + FIELD_fld_ae_sem_shift_i8, + FIELD_fld_ae_slot3_11_0, + FIELD_fld_ae_slot3_14_0, + FIELD_fld_ae_slot3_14_10, + FIELD_fld_ae_slot3_14_12, + FIELD_fld_ae_slot3_14_13, + FIELD_fld_ae_slot3_16_13, + FIELD_fld_ae_slot3_19_0, + FIELD_fld_ae_slot3_19_10, + FIELD_fld_ae_slot3_19_15, + FIELD_fld_ae_slot3_19_17, + FIELD_fld_ae_slot3_19_18, + FIELD_fld_ae_slot3_19_19, + FIELD_fld_ae_slot3_24_10, + FIELD_fld_ae_slot3_24_19, + FIELD_fld_ae_slot3_24_20, + FIELD_fld_ae_slot3_36_12, + FIELD_fld_ae_slot3_36_16, + FIELD_fld_ae_slot3_36_19, + FIELD_fld_ae_slot3_36_20, + FIELD_fld_ae_slot3_36_22, + FIELD_fld_ae_slot3_36_25, + FIELD_fld_ae_slot3_36_30, + FIELD_fld_ae_slot3_4_0, + FIELD_fld_ae_slot3_9_0, + FIELD_fld_ae_slot3_9_1, + FIELD_fld_ae_slot3_9_3, + FIELD_fld_ae_slot3_9_5, + FIELD_fld_ae2_slot0_0_0, + FIELD_fld_ae2_slot0_11_4, + FIELD_fld_ae2_slot0_11_8, + FIELD_fld_ae2_slot0_11_9, + FIELD_fld_ae2_slot0_12_0, + FIELD_fld_ae2_slot0_12_2, + FIELD_fld_ae2_slot0_12_4, + FIELD_fld_ae2_slot0_12_8, + FIELD_fld_ae2_slot0_14_13, + FIELD_fld_ae2_slot0_14_8, + FIELD_fld_ae2_slot0_15_0, + FIELD_fld_ae2_slot0_15_12, + FIELD_fld_ae2_slot0_15_13, + FIELD_fld_ae2_slot0_15_15, + FIELD_fld_ae2_slot0_15_4, + FIELD_fld_ae2_slot0_15_8, + FIELD_fld_ae2_slot0_17_13, + FIELD_fld_ae2_slot0_17_17, + FIELD_fld_ae2_slot0_18_15, + FIELD_fld_ae2_slot0_18_17, + FIELD_fld_ae2_slot0_18_18, + FIELD_fld_ae2_slot0_1_0, + FIELD_fld_ae2_slot0_23_18, + FIELD_fld_ae2_slot0_23_19, + FIELD_fld_ae2_slot0_3_0, + FIELD_fld_ae2_slot0_40_16, + FIELD_fld_ae2_slot0_40_17, + FIELD_fld_ae2_slot0_40_18, + FIELD_fld_ae2_slot0_40_19, + FIELD_fld_ae2_slot0_40_21, + FIELD_fld_ae2_slot0_40_23, + FIELD_fld_ae2_slot0_40_24, + FIELD_fld_ae2_slot0_40_25, + FIELD_fld_ae2_slot0_40_26, + FIELD_fld_ae2_slot0_40_27, + FIELD_fld_ae2_slot0_7_0, + FIELD_fld_ae2_slot0_7_4, + FIELD_fld_ae2_slot0_7_6, + FIELD_fld_ae2_slot0_7_7, + FIELD_fld_ae2_slot0_8_8, + FIELD_fld_ae2_slot0_9_8, + FIELD_fld_ae2_slot1_0_0, + FIELD_fld_ae2_slot1_11_0, + FIELD_fld_ae2_slot1_11_10, + FIELD_fld_ae2_slot1_11_8, + FIELD_fld_ae2_slot1_14_10, + FIELD_fld_ae2_slot1_14_11, + FIELD_fld_ae2_slot1_14_12, + FIELD_fld_ae2_slot1_14_14, + FIELD_fld_ae2_slot1_14_8, + FIELD_fld_ae2_slot1_36_12, + FIELD_fld_ae2_slot1_36_14, + FIELD_fld_ae2_slot1_36_15, + FIELD_fld_ae2_slot1_36_16, + FIELD_fld_ae2_slot1_36_17, + FIELD_fld_ae2_slot1_36_18, + FIELD_fld_ae2_slot1_36_20, + FIELD_fld_ae2_slot1_36_22, + FIELD_fld_ae2_slot1_36_23, + FIELD_fld_ae2_slot1_3_0, + FIELD_fld_ae2_slot1_3_1, + FIELD_fld_ae2_slot1_3_2, + FIELD_fld_ae2_slot1_3_3, + FIELD_fld_ae2_slot1_7_4, + FIELD_fld_ae2_slot1_9_8, + FIELD_fld_ae2_slot1_9_9, + FIELD_fld_ae2_slot2_14_10, + FIELD_fld_ae2_slot2_17_0, + FIELD_fld_ae2_slot2_17_10, + FIELD_fld_ae2_slot2_17_15, + FIELD_fld_ae2_slot2_17_17, + FIELD_fld_ae2_slot2_19_10, + FIELD_fld_ae2_slot2_19_15, + FIELD_fld_ae2_slot2_19_18, + FIELD_fld_ae2_slot2_19_9, + FIELD_fld_ae2_slot2_24_10, + FIELD_fld_ae2_slot2_24_15, + FIELD_fld_ae2_slot2_24_20, + FIELD_fld_ae2_slot2_24_5, + FIELD_fld_ae2_slot2_24_9, + FIELD_fld_ae2_slot2_42_18, + FIELD_fld_ae2_slot2_42_20, + FIELD_fld_ae2_slot2_42_25, + FIELD_fld_ae2_slot2_42_26, + FIELD_fld_ae2_slot2_42_28, + FIELD_fld_ae2_slot2_42_30, + FIELD_fld_ae2_slot2_4_0, + FIELD_fld_ae2_slot2_9_5, + FIELD_fld_ae_sem_spaddsub_vp, + FIELD_fld_ae_sem_spaddsub_vq, + FIELD_fld_ae3_slot0_11_11, + FIELD_fld_ae3_slot0_11_4, + FIELD_fld_ae3_slot0_11_8, + FIELD_fld_ae3_slot0_12_12, + FIELD_fld_ae3_slot0_12_8, + FIELD_fld_ae3_slot0_13_13, + FIELD_fld_ae3_slot0_13_8, + FIELD_fld_ae3_slot0_1_0, + FIELD_fld_ae3_slot0_32_11, + FIELD_fld_ae3_slot0_32_12, + FIELD_fld_ae3_slot0_32_13, + FIELD_fld_ae3_slot0_32_14, + FIELD_fld_ae3_slot0_32_15, + FIELD_fld_ae3_slot0_32_16, + FIELD_fld_ae3_slot0_32_17, + FIELD_fld_ae3_slot0_32_18, + FIELD_fld_ae3_slot0_32_20, + FIELD_fld_ae3_slot0_32_27, + FIELD_fld_ae3_slot0_32_8, + FIELD_fld_ae3_slot0_3_0, + FIELD_fld_ae3_slot0_3_2, + FIELD_fld_ae3_slot0_3_3, + FIELD_fld_ae3_slot0_4_0, + FIELD_fld_ae3_slot0_4_4, + FIELD_fld_ae3_slot0_5_0, + FIELD_fld_ae3_slot0_5_4, + FIELD_fld_ae3_slot0_7_0, + FIELD_fld_ae3_slot0_7_2, + FIELD_fld_ae3_slot0_7_4, + FIELD_fld_ae3_slot0_7_6, + FIELD_fld_ae3_slot0_8_8, + FIELD_fld_ae3_slot0_9_4, + FIELD_fld_ae3_slot0_9_8, + FIELD_fld_ae_sem_dr_to_ar_ar_s, + FIELD_fld_ae_sem_sb_loads_stores_iba2, + FIELD_fld_ae3_slot1_23_0, + FIELD_fld_ae3_slot1_23_11, + FIELD_fld_ae3_slot1_23_12, + FIELD_fld_ae3_slot1_23_13, + FIELD_fld_ae3_slot1_23_15, + FIELD_fld_ae3_slot1_23_16, + FIELD_fld_ae3_slot1_23_17, + FIELD_fld_ae3_slot1_23_19, + FIELD_fld_ae3_slot1_23_6, + FIELD_fld_ae3_slot1_23_8, + FIELD_fld_ae3_slot1_23_9, + FIELD_fld_ae3_slot1_3_0, + FIELD_fld_ae3_slot1_3_1, + FIELD_fld_ae3_slot1_3_2, + FIELD_fld_ae3_slot1_3_3, + FIELD_fld_ae3_slot1_7_4, + FIELD_fld_ae3_slot1_9_8, + FIELD_fld_AE_ARDECNORM16_ar_u, + FIELD_fld_ae5_slot0_11_10, + FIELD_fld_ae5_slot0_11_4, + FIELD_fld_ae5_slot0_11_8, + FIELD_fld_ae5_slot0_11_9, + FIELD_fld_ae5_slot0_12_10, + FIELD_fld_ae5_slot0_12_4, + FIELD_fld_ae5_slot0_12_6, + FIELD_fld_ae5_slot0_12_8, + FIELD_fld_ae5_slot0_12_9, + FIELD_fld_ae5_slot0_1_0, + FIELD_fld_ae5_slot0_1_1, + FIELD_fld_ae5_slot0_29_12, + FIELD_fld_ae5_slot0_29_13, + FIELD_fld_ae5_slot0_29_15, + FIELD_fld_ae5_slot0_29_16, + FIELD_fld_ae5_slot0_29_17, + FIELD_fld_ae5_slot0_29_18, + FIELD_fld_ae5_slot0_29_19, + FIELD_fld_ae5_slot0_29_20, + FIELD_fld_ae5_slot0_29_27, + FIELD_fld_ae5_slot0_29_5, + FIELD_fld_ae5_slot0_29_6, + FIELD_fld_ae5_slot0_29_8, + FIELD_fld_ae5_slot0_2_0, + FIELD_fld_ae5_slot0_3_0, + FIELD_fld_ae5_slot0_3_2, + FIELD_fld_ae5_slot0_4_0, + FIELD_fld_ae5_slot0_4_4, + FIELD_fld_ae5_slot0_7_0, + FIELD_fld_ae5_slot0_7_4, + FIELD_fld_ae5_slot0_7_7, + FIELD_fld_ae5_slot0_8_8, + FIELD_fld_ae_sem_lb_db_ops_ar_u, + FIELD_fld_ae_sem_lb_db_ops_iba, + FIELD_fld_ae_sem_rng_a, + FIELD_fld_ae_sem_rng_art, + FIELD_fld_ae_sem_rng_i2, + FIELD_fld_ae_sem_rng_imm2, + FIELD_fld_ae5_slot1_1_0, + FIELD_fld_ae5_slot2_14_10, + FIELD_fld_ae5_slot2_14_14, + FIELD_fld_ae5_slot2_14_5, + FIELD_fld_ae5_slot2_24_0, + FIELD_fld_ae5_slot2_24_15, + FIELD_fld_ae5_slot2_24_17, + FIELD_fld_ae5_slot2_24_20, + FIELD_fld_ae5_slot2_4_0, + FIELD_fld_ae5_slot2_9_0, + FIELD_fld_ae5_slot2_9_5, + FIELD_fld_ae5_slot2_9_7, + FIELD_fld_ae6_slot0_10_10, + FIELD_fld_ae6_slot0_15_15, + FIELD_fld_ae6_slot0_29_10, + FIELD_fld_ae6_slot0_29_13, + FIELD_fld_ae6_slot0_29_14, + FIELD_fld_ae6_slot0_29_15, + FIELD_fld_ae6_slot0_29_18, + FIELD_fld_ae6_slot0_29_20, + FIELD_fld_ae6_slot0_29_5, + FIELD_fld_ae6_slot0_4_0, + FIELD_fld_ae6_slot0_4_4, + FIELD_fld_ae6_slot0_7_4, + FIELD_fld_ae6_slot0_7_7, + FIELD_fld_ae6_slot0_9_8, + FIELD_fld_ae6_slot0_9_9, + FIELD_fld_ae6_slot1_14_14, + FIELD_fld_ae6_slot1_27_12, + FIELD_fld_ae6_slot1_27_15, + FIELD_fld_ae6_slot1_27_20, + FIELD_fld_ae6_slot1_27_21, + FIELD_fld_ae6_slot1_27_3, + FIELD_fld_ae6_slot1_27_6, + FIELD_fld_ae6_slot1_2_0, + FIELD_fld_ae6_slot1_9_5, + FIELD_fld_ae6_slot1_9_6, + FIELD_fld_ae6_slot1_9_7, + FIELD_fld_ae6_slot1_9_8, + FIELD_fld_ae6_slot1_9_9, + FIELD_fld_ae6_slot2_10_10, + FIELD_fld_ae6_slot2_11_10, + FIELD_fld_ae6_slot2_24_0, + FIELD_fld_ae6_slot2_24_10, + FIELD_fld_ae6_slot2_24_14, + FIELD_fld_ae6_slot2_24_15, + FIELD_fld_ae6_slot2_24_20, + FIELD_fld_ae6_slot2_4_2, + FIELD_fld_ae6_slot2_9_5, + FIELD_fld_ae6_slot3_10_10, + FIELD_fld_ae6_slot3_12_0, + FIELD_fld_ae6_slot3_14_0, + FIELD_fld_ae6_slot3_14_10, + FIELD_fld_ae6_slot3_14_13, + FIELD_fld_ae6_slot3_14_5, + FIELD_fld_ae6_slot3_24_20, + FIELD_fld_ae6_slot3_37_13, + FIELD_fld_ae6_slot3_37_15, + FIELD_fld_ae6_slot3_37_20, + FIELD_fld_ae6_slot3_37_30, + FIELD_fld_ae6_slot3_9_5, + FIELD_fld_ae7_slot0_12_6, + FIELD_fld_ae7_slot0_23_0, + FIELD_fld_ae7_slot0_23_13, + FIELD_fld_ae7_slot0_23_17, + FIELD_fld_ae7_slot0_23_18, + FIELD_fld_ae7_slot0_23_6, + FIELD_fld_ae7_slot0_7_4, + FIELD_fld_ae7_slot0_7_6, + FIELD_fld_ae7_slot0_7_7, + FIELD_fld_ae7_slot1_12_6, + FIELD_fld_ae7_slot1_23_0, + FIELD_fld_ae7_slot1_23_13, + FIELD_fld_ae7_slot1_23_17, + FIELD_fld_ae7_slot1_23_18, + FIELD_fld_ae7_slot1_23_6, + FIELD_fld_ae7_slot1_7_4, + FIELD_fld_ae7_slot1_7_6, + FIELD_fld_ae7_slot1_7_7, + FIELD_fld_ae7_slot2_11_0, + FIELD_fld_ae7_slot2_14_10, + FIELD_fld_ae7_slot2_14_5, + FIELD_fld_ae7_slot2_36_12, + FIELD_fld_ae7_slot2_36_15, + FIELD_fld_ae7_slot2_36_20, + FIELD_fld_ae7_slot2_36_25, + FIELD_fld_ae7_slot2_36_30, + FIELD_fld_ae7_slot2_9_5, + FIELD_fld_ae7_slot3_10_0, + FIELD_fld_ae7_slot3_14_10, + FIELD_fld_ae7_slot3_14_5, + FIELD_fld_ae7_slot3_24_10, + FIELD_fld_ae7_slot3_35_11, + FIELD_fld_ae7_slot3_35_20, + FIELD_fld_ae7_slot3_35_25, + FIELD_fld_ae7_slot3_35_30, + FIELD_fld_ae7_slot3_4_0, + FIELD_fld_ae7_slot3_9_5, + FIELD_fld_ae8_slot0_13_12, + FIELD_fld_ae8_slot0_13_13, + FIELD_fld_ae8_slot0_13_4, + FIELD_fld_ae8_slot0_13_9, + FIELD_fld_ae8_slot0_17_4, + FIELD_fld_ae8_slot0_17_8, + FIELD_fld_ae8_slot0_31_12, + FIELD_fld_ae8_slot0_31_15, + FIELD_fld_ae8_slot0_31_18, + FIELD_fld_ae8_slot0_31_19, + FIELD_fld_ae8_slot0_31_20, + FIELD_fld_ae8_slot0_31_21, + FIELD_fld_ae8_slot0_31_22, + FIELD_fld_ae8_slot0_31_23, + FIELD_fld_ae8_slot0_31_7, + FIELD_fld_ae8_slot0_31_8, + FIELD_fld_ae8_slot0_31_9, + FIELD_fld_ae8_slot0_3_0, + FIELD_fld_ae8_slot0_6_0, + FIELD_fld_ae8_slot0_7_4, + FIELD_fld_ae8_slot0_7_5, + FIELD_fld_ae8_slot0_7_7, + FIELD_fld_ae8_slot0_8_0, + FIELD_fld_ae8_slot1_17_13, + FIELD_fld_ae8_slot1_17_14, + FIELD_fld_ae8_slot1_17_15, + FIELD_fld_ae8_slot1_17_8, + FIELD_fld_ae8_slot1_29_12, + FIELD_fld_ae8_slot1_29_13, + FIELD_fld_ae8_slot1_29_18, + FIELD_fld_ae8_slot1_29_20, + FIELD_fld_ae8_slot1_29_22, + FIELD_fld_ae8_slot1_29_23, + FIELD_fld_ae8_slot1_29_5, + FIELD_fld_ae8_slot1_29_8, + FIELD_fld_ae8_slot1_29_9, + FIELD_fld_ae8_slot1_3_0, + FIELD_fld_ae8_slot1_3_3, + FIELD_fld_ae8_slot1_4_0, + FIELD_fld_ae8_slot1_7_4, + FIELD_fld_ae8_slot2_19_10, + FIELD_fld_ae8_slot2_19_15, + FIELD_fld_ae8_slot2_33_15, + FIELD_fld_ae8_slot2_33_25, + FIELD_fld_ae8_slot2_33_9, + FIELD_fld_ae8_slot2_34_30, + FIELD_fld_ae8_slot2_39_35, + FIELD_fld_ae8_slot2_44_35, + FIELD_fld_ae8_slot2_58_34, + FIELD_fld_ae8_slot2_58_35, + FIELD_fld_ae8_slot2_58_40, + FIELD_fld_ae8_slot2_58_50, + FIELD_fld_ae8_slot2_8_0, + FIELD_fld_ae8_slot2_9_0, + FIELD_fld_ae_sem_mul_nn_c0, + FIELD_fld_ae_sem_mul_nn_c1, + FIELD_fld_ae_sem_mul_nn_c2, + FIELD_fld_ae_sem_mul_nn_c3, + FIELD_fld_ae_sem_mul_nn_q0, + FIELD_fld_ae_sem_mul_nn_q1, + FIELD_fld_ae_sem_mul_nn_q2, + FIELD_fld_ae_sem_mul_nn_q3, + FIELD_fld_ae_sem_mul_nn_v0, + FIELD_fld_ae_sem_mul_nn_v1, + FIELD_fld_ae_sem_mul_nn_v2, + FIELD_fld_ae_sem_mul_nn_v3, + FIELD_fld_ae9_slot0_0_0, + FIELD_fld_ae9_slot0_12_12, + FIELD_fld_ae9_slot0_12_5, + FIELD_fld_ae9_slot0_12_8, + FIELD_fld_ae9_slot0_17_13, + FIELD_fld_ae9_slot0_17_4, + FIELD_fld_ae9_slot0_17_8, + FIELD_fld_ae9_slot0_27_10, + FIELD_fld_ae9_slot0_27_12, + FIELD_fld_ae9_slot0_27_13, + FIELD_fld_ae9_slot0_27_16, + FIELD_fld_ae9_slot0_27_17, + FIELD_fld_ae9_slot0_27_18, + FIELD_fld_ae9_slot0_27_19, + FIELD_fld_ae9_slot0_27_20, + FIELD_fld_ae9_slot0_27_22, + FIELD_fld_ae9_slot0_27_23, + FIELD_fld_ae9_slot0_27_3, + FIELD_fld_ae9_slot0_27_8, + FIELD_fld_ae9_slot0_2_0, + FIELD_fld_ae9_slot0_3_0, + FIELD_fld_ae9_slot0_7_0, + FIELD_fld_ae9_slot0_7_4, + FIELD_fld_ae9_slot0_7_5, + FIELD_fld_ae9_slot0_7_6, + FIELD_fld_ae9_slot0_7_7, + FIELD_fld_ae9_slot0_8_4, + FIELD_fld_ae9_slot0_8_5, + FIELD_fld_ae9_slot0_9_5, + FIELD_fld_ae9_slot1_17_13, + FIELD_fld_ae9_slot1_17_8, + FIELD_fld_ae9_slot1_1_0, + FIELD_fld_ae9_slot1_26_12, + FIELD_fld_ae9_slot1_26_13, + FIELD_fld_ae9_slot1_26_16, + FIELD_fld_ae9_slot1_26_17, + FIELD_fld_ae9_slot1_26_18, + FIELD_fld_ae9_slot1_26_2, + FIELD_fld_ae9_slot1_26_20, + FIELD_fld_ae9_slot1_26_22, + FIELD_fld_ae9_slot1_26_23, + FIELD_fld_ae9_slot1_26_8, + FIELD_fld_ae9_slot1_26_9, + FIELD_fld_ae9_slot1_3_0, + FIELD_fld_ae9_slot1_3_2, + FIELD_fld_ae9_slot1_3_3, + FIELD_fld_ae9_slot1_7_4, + FIELD_fld_ae9_slot2_24_14, + FIELD_fld_ae9_slot2_24_15, + FIELD_fld_ae9_slot2_24_20, + FIELD_fld_ae9_slot2_33_14, + FIELD_fld_ae9_slot2_33_15, + FIELD_fld_ae9_slot2_33_20, + FIELD_fld_ae9_slot2_33_25, + FIELD_fld_ae9_slot2_33_26, + FIELD_fld_ae9_slot2_33_28, + FIELD_fld_ae9_slot2_33_30, + FIELD_fld_ae9_slot2_33_9, + FIELD_fld_ae9_slot2_4_0, + FIELD_fld_ae9_slot2_5_0, + FIELD_fld_ae9_slot2_6_0, + FIELD_fld_ae9_slot2_8_0, + FIELD_fld_ae9_slot2_9_0, + FIELD_fld_ae9_slot2_9_5, + FIELD_fld_ae9_slot2_9_9, + FIELD_fld_ae_sem_hpfma_vp, + FIELD_fld_ae_sem_hpfma_vu, + FIELD_fld_ae_sem_spfma_vu, + FIELD_fld_ae9_slot3_19_15, + FIELD_fld_ae9_slot3_24_20, + FIELD_fld_ae9_slot3_31_14, + FIELD_fld_ae9_slot3_31_15, + FIELD_fld_ae9_slot3_31_20, + FIELD_fld_ae9_slot3_31_25, + FIELD_fld_ae9_slot3_31_26, + FIELD_fld_ae9_slot3_31_28, + FIELD_fld_ae9_slot3_31_7, + FIELD_fld_ae9_slot3_4_0, + FIELD_fld_ae9_slot3_4_3, + FIELD_fld_ae9_slot3_4_4, + FIELD_fld_ae9_slot3_6_0, + FIELD_fld_ae9_slot3_9_0, + FIELD_fld_ae9_slot3_9_5, + FIELD_fld_ae10_slot0_17_13, + FIELD_fld_ae10_slot0_17_4, + FIELD_fld_ae10_slot0_17_8, + FIELD_fld_ae10_slot0_24_0, + FIELD_fld_ae10_slot0_24_10, + FIELD_fld_ae10_slot0_24_12, + FIELD_fld_ae10_slot0_24_13, + FIELD_fld_ae10_slot0_24_16, + FIELD_fld_ae10_slot0_24_17, + FIELD_fld_ae10_slot0_24_18, + FIELD_fld_ae10_slot0_24_20, + FIELD_fld_ae10_slot0_24_8, + FIELD_fld_ae10_slot0_3_0, + FIELD_fld_ae10_slot0_7_4, + FIELD_fld_ae10_slot0_7_6, + FIELD_fld_ae10_slot0_7_7, + FIELD_fld_ae10_slot0_8_4, + FIELD_fld_ae10_slot1_0_0, + FIELD_fld_ae10_slot1_17_13, + FIELD_fld_ae10_slot1_17_8, + FIELD_fld_ae10_slot1_25_1, + FIELD_fld_ae10_slot1_25_12, + FIELD_fld_ae10_slot1_25_13, + FIELD_fld_ae10_slot1_25_16, + FIELD_fld_ae10_slot1_25_17, + FIELD_fld_ae10_slot1_25_18, + FIELD_fld_ae10_slot1_25_20, + FIELD_fld_ae10_slot1_25_22, + FIELD_fld_ae10_slot1_25_23, + FIELD_fld_ae10_slot1_25_8, + FIELD_fld_ae10_slot1_25_9, + FIELD_fld_ae10_slot1_3_0, + FIELD_fld_ae10_slot1_3_2, + FIELD_fld_ae10_slot1_3_3, + FIELD_fld_ae10_slot1_7_4, + FIELD_fld_ae10_slot2_24_20, + FIELD_fld_ae10_slot2_29_20, + FIELD_fld_ae10_slot2_29_25, + FIELD_fld_ae10_slot2_34_10, + FIELD_fld_ae10_slot2_34_14, + FIELD_fld_ae10_slot2_34_15, + FIELD_fld_ae10_slot2_34_20, + FIELD_fld_ae10_slot2_34_25, + FIELD_fld_ae10_slot2_34_30, + FIELD_fld_ae10_slot2_34_31, + FIELD_fld_ae10_slot2_34_33, + FIELD_fld_ae10_slot2_4_0, + FIELD_fld_ae10_slot2_9_0, + FIELD_fld_ae10_slot2_9_5, + FIELD_fld_ae_sem_hpfma_vq, + FIELD_fld_ae_sem_spfma_vq, + FIELD_fld_ae10_slot3_19_15, + FIELD_fld_ae10_slot3_29_20, + FIELD_fld_ae10_slot3_29_25, + FIELD_fld_ae10_slot3_34_10, + FIELD_fld_ae10_slot3_34_14, + FIELD_fld_ae10_slot3_34_15, + FIELD_fld_ae10_slot3_34_20, + FIELD_fld_ae10_slot3_34_25, + FIELD_fld_ae10_slot3_34_30, + FIELD_fld_ae10_slot3_34_31, + FIELD_fld_ae10_slot3_34_33, + FIELD_fld_ae10_slot3_4_0, + FIELD_fld_ae10_slot3_4_3, + FIELD_fld_ae10_slot3_4_4, + FIELD_fld_ae10_slot3_9_0, + FIELD_fld_ae10_slot3_9_5, + FIELD_fld_ae4_slot0_22_0, + FIELD_fld_ae4_slot0_22_12, + FIELD_fld_ae4_slot0_22_13, + FIELD_fld_ae4_slot0_22_16, + FIELD_fld_ae4_slot0_22_17, + FIELD_fld_ae4_slot0_22_18, + FIELD_fld_ae4_slot0_22_20, + FIELD_fld_ae4_slot0_22_6, + FIELD_fld_ae4_slot0_22_8, + FIELD_fld_ae4_slot0_3_0, + FIELD_fld_ae4_slot0_3_1, + FIELD_fld_ae4_slot0_4_4, + FIELD_fld_ae4_slot0_7_4, + FIELD_fld_ae4_slot1_22_0, + FIELD_fld_ae4_slot1_22_12, + FIELD_fld_ae4_slot1_22_13, + FIELD_fld_ae4_slot1_22_16, + FIELD_fld_ae4_slot1_22_17, + FIELD_fld_ae4_slot1_22_18, + FIELD_fld_ae4_slot1_22_8, + FIELD_fld_ae4_slot1_3_0, + FIELD_fld_ae4_slot1_3_1, + FIELD_fld_ae4_slot1_7_4, + FIELD_fld_ae4_slot2_23_0, + FIELD_fld_ae4_slot2_23_12, + FIELD_fld_ae4_slot2_23_15, + FIELD_fld_ae4_slot2_23_17, + FIELD_fld_ae4_slot2_23_20, + FIELD_fld_ae4_slot2_4_0, + FIELD_fld_ae4_slot2_9_5, + FIELD_fld_ae4_slot3_14_10, + FIELD_fld_ae4_slot3_19_15, + FIELD_fld_ae4_slot3_19_19, + FIELD_fld_ae4_slot3_19_5, + FIELD_fld_ae4_slot3_27_20, + FIELD_fld_ae4_slot3_27_25, + FIELD_fld_ae4_slot3_27_3, + FIELD_fld_ae4_slot3_2_0, + FIELD_fld_ae4_slot3_9_0, + FIELD_fld_ae4_slot3_9_5, + FIELD_fld_ae4_slot4_22_0, + FIELD_fld_ae4_slot4_22_15, + FIELD_fld_ae4_slot4_22_20, + FIELD_fld_ae4_slot4_9_5, + FIELD_fld_Inst_11_8, + FIELD_fld_Inst_12_12, + FIELD_fld_Inst_12_8, + FIELD_fld_Inst_13_8, + FIELD_fld_Inst_15_12, + FIELD_fld_Inst_19_17, + FIELD_fld_Inst_19_18, + FIELD_fld_Inst_23_12, + FIELD_fld_Inst_23_16, + FIELD_fld_Inst_4_4, + FIELD_fld_Inst_5_4, + FIELD_fld_Inst_7_4, + FIELD_fld_Inst_7_6, + FIELD_fld_Inst_7_7, + FIELD_fld_Inst_9_8, + FIELD_bitindex, + FIELD_s3to1, + FIELD__ar0, + FIELD__ar4, + FIELD__ar8, + FIELD__ar12, + FIELD__bt16, + FIELD__bs16, + FIELD__br16, + FIELD__brall +}; + + +/* Functional units. */ + +static xtensa_funcUnit_internal funcUnits[] = { + {"XT_LOADSTORE_UNIT", 2}, + { "mul_function", 1 }, + { "mul_S2_function", 1 }, + { "ae_add32x27", 1 }, + { "ae_shift32x4", 1 }, + { "ae_shift32x5", 1 }, + { "ae_leftshift32x5", 2 } +}; + +enum xtensa_funcUnit_id { + FUNCUNIT_XT_LOADSTORE_UNIT, + FUNCUNIT_mul_function, + FUNCUNIT_mul_S2_function, + FUNCUNIT_ae_add32x27, + FUNCUNIT_ae_shift32x4, + FUNCUNIT_ae_shift32x5, + FUNCUNIT_ae_leftshift32x5 +}; + + +/* Register files. */ + +enum xtensa_regfile_id { + REGFILE_AR, + REGFILE_BR, + REGFILE_AE_DR, + REGFILE_AE_VALIGN, + REGFILE_AE_EP, + REGFILE_BR2, + REGFILE_BR4, + REGFILE_BR8, + REGFILE_BR16 +}; + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", REGFILE_AR, 32, 64 }, + { "BR", "b", REGFILE_BR, 1, 16 }, + { "AE_DR", "aed", REGFILE_AE_DR, 64, 32 }, + { "AE_VALIGN", "u", REGFILE_AE_VALIGN, 128, 4 }, + { "AE_EP", "aep", REGFILE_AE_EP, 8, 4 }, + { "BR2", "b", REGFILE_BR, 2, 8 }, + { "BR4", "b", REGFILE_BR, 4, 4 }, + { "BR8", "b", REGFILE_BR, 8, 2 }, + { "BR16", "b", REGFILE_BR, 16, 1 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + { "ERI_RD_Out", 14, 0, 0, 'o' }, + { "ERI_RD_In", 32, 0, 1, 'i' }, + { "ERI_RD_Rdy", 1, 0, 0, 'i' }, + { "ERI_WR_Out", 46, 0, 2, 'o' }, + { "ERI_WR_In", 1, 0, 3, 'i' }, + { "IMPWIRE", 32, 0, 4, 'i' } +}; + +enum xtensa_interface_id { + INTERFACE_ERI_RD_Out, + INTERFACE_ERI_RD_In, + INTERFACE_ERI_RD_Rdy, + INTERFACE_ERI_WR_Out, + INTERFACE_ERI_WR_In, + INTERFACE_IMPWIRE +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table bitmask8 */ +static const unsigned CONST_TBL_bitmask8_0[] = { + 0 & 0xff, + 0x1 & 0xff, + 0x3 & 0xff, + 0x7 & 0xff, + 0xf & 0xff, + 0x1f & 0xff, + 0x3f & 0xff, + 0x7f & 0xff, + 0 +}; + +/* constant table bitmask16 */ +static const unsigned CONST_TBL_bitmask16_0[] = { + 0 & 0xffff, + 0x1 & 0xffff, + 0x3 & 0xffff, + 0x7 & 0xffff, + 0xf & 0xffff, + 0x1f & 0xffff, + 0x3f & 0xffff, + 0x7f & 0xffff, + 0xff & 0xffff, + 0x1ff & 0xffff, + 0x3ff & 0xffff, + 0x7ff & 0xffff, + 0xfff & 0xffff, + 0x1fff & 0xffff, + 0x3fff & 0xffff, + 0x7fff & 0xffff, + 0 +}; + +/* constant table ae_ltr4_table */ +static const unsigned CONST_TBL_ae_ltr4_table_0[] = { + 0 & 0xf, + 0x8 & 0xf, + 0xc & 0xf, + 0xe & 0xf, + 0 +}; + +/* constant table ae_ltr8_table */ +static const unsigned CONST_TBL_ae_ltr8_table_0[] = { + 0 & 0xff, + 0x80 & 0xff, + 0xc0 & 0xff, + 0xe0 & 0xff, + 0xf0 & 0xff, + 0xf8 & 0xff, + 0xfc & 0xff, + 0xfe & 0xff, + 0 +}; + +/* constant table ae_immls64neg */ +static const unsigned CONST_TBL_ae_immls64neg_0[] = { + 0xffffffe0, + 0xffffffe8, + 0xfffffff0, + 0xfffffff8, + 0 +}; + +/* constant table ae_slai72table */ +static const unsigned CONST_TBL_ae_slai72table_0[] = { + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0 +}; + +/* constant table ae_seliencode */ +static const unsigned CONST_TBL_ae_seliencode_0[] = { + 0x4e5 & 0xfff, + 0x65 & 0xfff, + 0x77 & 0xfff, + 0x4f7 & 0xfff, + 0x72e & 0xfff, + 0x29c & 0xfff, + 0xaf & 0xfff, + 0xa6 & 0xfff, + 0x2ef & 0xfff, + 0x10d & 0xfff, + 0x599 & 0xfff, + 0x59f & 0xfff, + 0xb3e & 0xfff, + 0x18f & 0xfff, + 0x51d & 0xfff, + 0xa6 & 0xfff, + 0 +}; + +/* constant table ae_ohba */ +static const unsigned CONST_TBL_ae_ohba_0[] = { + 0x1 & 0x1f, + 0x2 & 0x1f, + 0x3 & 0x1f, + 0x4 & 0x1f, + 0x5 & 0x1f, + 0x6 & 0x1f, + 0x7 & 0x1f, + 0x8 & 0x1f, + 0x9 & 0x1f, + 0xa & 0x1f, + 0xb & 0x1f, + 0xc & 0x1f, + 0xd & 0x1f, + 0xe & 0x1f, + 0xf & 0x1f, + 0x10 & 0x1f, + 0 +}; + +/* constant table ae_ohba2 */ +static const unsigned CONST_TBL_ae_ohba2_0[] = { + 0x1 & 0x1f, + 0x2 & 0x1f, + 0x3 & 0x1f, + 0x4 & 0x1f, + 0x5 & 0x1f, + 0x6 & 0x1f, + 0x7 & 0x1f, + 0x8 & 0x1f, + 0x9 & 0x1f, + 0xa & 0x1f, + 0xb & 0x1f, + 0xc & 0x1f, + 0xd & 0x1f, + 0xe & 0x1f, + 0xf & 0x1f, + 0x10 & 0x1f, + 0 +}; + +/* constant table ae_opnd_tp7 */ +static const unsigned CONST_TBL_ae_opnd_tp7_0[] = { + 0x7 & 0x1f, + 0x8 & 0x1f, + 0x9 & 0x1f, + 0xa & 0x1f, + 0xb & 0x1f, + 0xc & 0x1f, + 0xd & 0x1f, + 0xe & 0x1f, + 0xf & 0x1f, + 0x10 & 0x1f, + 0x11 & 0x1f, + 0x12 & 0x1f, + 0x13 & 0x1f, + 0x14 & 0x1f, + 0x15 & 0x1f, + 0x16 & 0x1f, + 0 +}; + +/* constant table xd_seli_8x8_table0 */ +static const unsigned CONST_TBL_xd_seli_8x8_table0_0[] = { + 0xba987654, + 0xfedc7654, + 0xfedc3210, + 0xba983210, + 0x98765432, + 0xdcba9876, + 0xfeba5410, + 0xfeba7632, + 0xdc985410, + 0xfe76dc54, + 0xba3298dc, + 0xba329810, + 0x54761032, + 0xfe32dc10, + 0xba769854, + 0xfeba7632, + 0xedcba987, + 0xcba98765, + 0xa9876543, + 0x87654321, + 0xf7e6d5c4, + 0xb3a29180, + 0xf3e2d1c0, + 0xb7a69584, + 0xfe76ba32, + 0xeca86420, + 0xfdb97531, + 0xeca87531, + 0xfdb96420, + 0xdc987632, + 0xefcdab89, + 0x32107654, + 0 +}; + +/* constant table xd_seli_8x8_table0_be */ +static const unsigned CONST_TBL_xd_seli_8x8_table0_be_0[] = { + 0x456789ab, + 0x12389ab, + 0x123cdef, + 0x4567cdef, + 0x6789abcd, + 0x23456789, + 0x145abef, + 0x14589cd, + 0x2367abef, + 0x18923ab, + 0x45cd6723, + 0x45cd67ef, + 0xab89efcd, + 0x1cd23ef, + 0x458967ab, + 0x14589cd, + 0x12345678, + 0x3456789a, + 0x56789abc, + 0x789abcde, + 0x8192a3b, + 0x4c5d6e7f, + 0xc1d2e3f, + 0x48596a7b, + 0x18945cd, + 0x13579bdf, + 0x2468ace, + 0x13578ace, + 0x2469bdf, + 0x236789cd, + 0x10325476, + 0xcdef89ab, + 0 +}; + +/* constant table tab_lavunqz_8x8 */ +static const unsigned CONST_TBL_tab_lavunqz_8x8_0[] = { + 0, + 0x7, + 0x70, + 0x76, + 0x700, + 0x706, + 0x760, + 0x765, + 0x7000, + 0x7006, + 0x7060, + 0x7065, + 0x7600, + 0x7605, + 0x7650, + 0x7654, + 0x70000, + 0x70006, + 0x70060, + 0x70065, + 0x70600, + 0x70605, + 0x70650, + 0x70654, + 0x76000, + 0x76005, + 0x76050, + 0x76054, + 0x76500, + 0x76504, + 0x76540, + 0x76543, + 0x700000, + 0x700006, + 0x700060, + 0x700065, + 0x700600, + 0x700605, + 0x700650, + 0x700654, + 0x706000, + 0x706005, + 0x706050, + 0x706054, + 0x706500, + 0x706504, + 0x706540, + 0x706543, + 0x760000, + 0x760005, + 0x760050, + 0x760054, + 0x760500, + 0x760504, + 0x760540, + 0x760543, + 0x765000, + 0x765004, + 0x765040, + 0x765043, + 0x765400, + 0x765403, + 0x765430, + 0x765432, + 0x7000000, + 0x7000006, + 0x7000060, + 0x7000065, + 0x7000600, + 0x7000605, + 0x7000650, + 0x7000654, + 0x7006000, + 0x7006005, + 0x7006050, + 0x7006054, + 0x7006500, + 0x7006504, + 0x7006540, + 0x7006543, + 0x7060000, + 0x7060005, + 0x7060050, + 0x7060054, + 0x7060500, + 0x7060504, + 0x7060540, + 0x7060543, + 0x7065000, + 0x7065004, + 0x7065040, + 0x7065043, + 0x7065400, + 0x7065403, + 0x7065430, + 0x7065432, + 0x7600000, + 0x7600005, + 0x7600050, + 0x7600054, + 0x7600500, + 0x7600504, + 0x7600540, + 0x7600543, + 0x7605000, + 0x7605004, + 0x7605040, + 0x7605043, + 0x7605400, + 0x7605403, + 0x7605430, + 0x7605432, + 0x7650000, + 0x7650004, + 0x7650040, + 0x7650043, + 0x7650400, + 0x7650403, + 0x7650430, + 0x7650432, + 0x7654000, + 0x7654003, + 0x7654030, + 0x7654032, + 0x7654300, + 0x7654302, + 0x7654320, + 0x7654321, + 0x70000000, + 0x70000006, + 0x70000060, + 0x70000065, + 0x70000600, + 0x70000605, + 0x70000650, + 0x70000654, + 0x70006000, + 0x70006005, + 0x70006050, + 0x70006054, + 0x70006500, + 0x70006504, + 0x70006540, + 0x70006543, + 0x70060000, + 0x70060005, + 0x70060050, + 0x70060054, + 0x70060500, + 0x70060504, + 0x70060540, + 0x70060543, + 0x70065000, + 0x70065004, + 0x70065040, + 0x70065043, + 0x70065400, + 0x70065403, + 0x70065430, + 0x70065432, + 0x70600000, + 0x70600005, + 0x70600050, + 0x70600054, + 0x70600500, + 0x70600504, + 0x70600540, + 0x70600543, + 0x70605000, + 0x70605004, + 0x70605040, + 0x70605043, + 0x70605400, + 0x70605403, + 0x70605430, + 0x70605432, + 0x70650000, + 0x70650004, + 0x70650040, + 0x70650043, + 0x70650400, + 0x70650403, + 0x70650430, + 0x70650432, + 0x70654000, + 0x70654003, + 0x70654030, + 0x70654032, + 0x70654300, + 0x70654302, + 0x70654320, + 0x70654321, + 0x76000000, + 0x76000005, + 0x76000050, + 0x76000054, + 0x76000500, + 0x76000504, + 0x76000540, + 0x76000543, + 0x76005000, + 0x76005004, + 0x76005040, + 0x76005043, + 0x76005400, + 0x76005403, + 0x76005430, + 0x76005432, + 0x76050000, + 0x76050004, + 0x76050040, + 0x76050043, + 0x76050400, + 0x76050403, + 0x76050430, + 0x76050432, + 0x76054000, + 0x76054003, + 0x76054030, + 0x76054032, + 0x76054300, + 0x76054302, + 0x76054320, + 0x76054321, + 0x76500000, + 0x76500004, + 0x76500040, + 0x76500043, + 0x76500400, + 0x76500403, + 0x76500430, + 0x76500432, + 0x76504000, + 0x76504003, + 0x76504030, + 0x76504032, + 0x76504300, + 0x76504302, + 0x76504320, + 0x76504321, + 0x76540000, + 0x76540003, + 0x76540030, + 0x76540032, + 0x76540300, + 0x76540302, + 0x76540320, + 0x76540321, + 0x76543000, + 0x76543002, + 0x76543020, + 0x76543021, + 0x76543200, + 0x76543201, + 0x76543210, + 0x76543210, + 0 +}; + +/* constant table tab_lavunqz_16x4 */ +static const unsigned CONST_TBL_tab_lavunqz_16x4_0[] = { + 0 & 0xff, + 0x3 & 0xff, + 0xc & 0xff, + 0xe & 0xff, + 0x30 & 0xff, + 0x32 & 0xff, + 0x38 & 0xff, + 0x39 & 0xff, + 0xc0 & 0xff, + 0xc2 & 0xff, + 0xc8 & 0xff, + 0xc9 & 0xff, + 0xe0 & 0xff, + 0xe1 & 0xff, + 0xe4 & 0xff, + 0xe4 & 0xff, + 0 +}; + +/* constant table xd_recip0_table128_8 */ +static const unsigned CONST_TBL_xd_recip0_table128_8_0[] = { + 0xff & 0xff, + 0xfd & 0xff, + 0xfb & 0xff, + 0xf9 & 0xff, + 0xf7 & 0xff, + 0xf5 & 0xff, + 0xf4 & 0xff, + 0xf2 & 0xff, + 0xf0 & 0xff, + 0xee & 0xff, + 0xed & 0xff, + 0xeb & 0xff, + 0xe9 & 0xff, + 0xe8 & 0xff, + 0xe6 & 0xff, + 0xe4 & 0xff, + 0xe3 & 0xff, + 0xe1 & 0xff, + 0xe0 & 0xff, + 0xde & 0xff, + 0xdd & 0xff, + 0xdb & 0xff, + 0xda & 0xff, + 0xd8 & 0xff, + 0xd7 & 0xff, + 0xd5 & 0xff, + 0xd4 & 0xff, + 0xd3 & 0xff, + 0xd1 & 0xff, + 0xd0 & 0xff, + 0xcf & 0xff, + 0xcd & 0xff, + 0xcc & 0xff, + 0xcb & 0xff, + 0xca & 0xff, + 0xc8 & 0xff, + 0xc7 & 0xff, + 0xc6 & 0xff, + 0xc5 & 0xff, + 0xc4 & 0xff, + 0xc2 & 0xff, + 0xc1 & 0xff, + 0xc0 & 0xff, + 0xbf & 0xff, + 0xbe & 0xff, + 0xbd & 0xff, + 0xbc & 0xff, + 0xbb & 0xff, + 0xba & 0xff, + 0xb9 & 0xff, + 0xb8 & 0xff, + 0xb7 & 0xff, + 0xb6 & 0xff, + 0xb5 & 0xff, + 0xb4 & 0xff, + 0xb3 & 0xff, + 0xb2 & 0xff, + 0xb1 & 0xff, + 0xb0 & 0xff, + 0xaf & 0xff, + 0xae & 0xff, + 0xad & 0xff, + 0xac & 0xff, + 0xab & 0xff, + 0xaa & 0xff, + 0xa9 & 0xff, + 0xa8 & 0xff, + 0xa8 & 0xff, + 0xa7 & 0xff, + 0xa6 & 0xff, + 0xa5 & 0xff, + 0xa4 & 0xff, + 0xa3 & 0xff, + 0xa3 & 0xff, + 0xa2 & 0xff, + 0xa1 & 0xff, + 0xa0 & 0xff, + 0x9f & 0xff, + 0x9f & 0xff, + 0x9e & 0xff, + 0x9d & 0xff, + 0x9c & 0xff, + 0x9c & 0xff, + 0x9b & 0xff, + 0x9a & 0xff, + 0x99 & 0xff, + 0x99 & 0xff, + 0x98 & 0xff, + 0x97 & 0xff, + 0x97 & 0xff, + 0x96 & 0xff, + 0x95 & 0xff, + 0x95 & 0xff, + 0x94 & 0xff, + 0x93 & 0xff, + 0x93 & 0xff, + 0x92 & 0xff, + 0x91 & 0xff, + 0x91 & 0xff, + 0x90 & 0xff, + 0x8f & 0xff, + 0x8f & 0xff, + 0x8e & 0xff, + 0x8e & 0xff, + 0x8d & 0xff, + 0x8c & 0xff, + 0x8c & 0xff, + 0x8b & 0xff, + 0x8b & 0xff, + 0x8a & 0xff, + 0x89 & 0xff, + 0x89 & 0xff, + 0x88 & 0xff, + 0x88 & 0xff, + 0x87 & 0xff, + 0x87 & 0xff, + 0x86 & 0xff, + 0x85 & 0xff, + 0x85 & 0xff, + 0x84 & 0xff, + 0x84 & 0xff, + 0x83 & 0xff, + 0x83 & 0xff, + 0x82 & 0xff, + 0x82 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0 +}; + +/* constant table xd_rsqrt0_table128_8 */ +static const unsigned CONST_TBL_xd_rsqrt0_table128_8_0[] = { + 0xb4 & 0xff, + 0xb3 & 0xff, + 0xb2 & 0xff, + 0xb0 & 0xff, + 0xaf & 0xff, + 0xae & 0xff, + 0xac & 0xff, + 0xab & 0xff, + 0xaa & 0xff, + 0xa9 & 0xff, + 0xa8 & 0xff, + 0xa7 & 0xff, + 0xa6 & 0xff, + 0xa5 & 0xff, + 0xa3 & 0xff, + 0xa2 & 0xff, + 0xa1 & 0xff, + 0xa0 & 0xff, + 0x9f & 0xff, + 0x9e & 0xff, + 0x9e & 0xff, + 0x9d & 0xff, + 0x9c & 0xff, + 0x9b & 0xff, + 0x9a & 0xff, + 0x99 & 0xff, + 0x98 & 0xff, + 0x97 & 0xff, + 0x97 & 0xff, + 0x96 & 0xff, + 0x95 & 0xff, + 0x94 & 0xff, + 0x93 & 0xff, + 0x93 & 0xff, + 0x92 & 0xff, + 0x91 & 0xff, + 0x90 & 0xff, + 0x90 & 0xff, + 0x8f & 0xff, + 0x8e & 0xff, + 0x8e & 0xff, + 0x8d & 0xff, + 0x8c & 0xff, + 0x8c & 0xff, + 0x8b & 0xff, + 0x8a & 0xff, + 0x8a & 0xff, + 0x89 & 0xff, + 0x89 & 0xff, + 0x88 & 0xff, + 0x87 & 0xff, + 0x87 & 0xff, + 0x86 & 0xff, + 0x86 & 0xff, + 0x85 & 0xff, + 0x84 & 0xff, + 0x84 & 0xff, + 0x83 & 0xff, + 0x83 & 0xff, + 0x82 & 0xff, + 0x82 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0x80 & 0xff, + 0xff & 0xff, + 0xfd & 0xff, + 0xfb & 0xff, + 0xf9 & 0xff, + 0xf7 & 0xff, + 0xf6 & 0xff, + 0xf4 & 0xff, + 0xf2 & 0xff, + 0xf1 & 0xff, + 0xef & 0xff, + 0xed & 0xff, + 0xec & 0xff, + 0xea & 0xff, + 0xe9 & 0xff, + 0xe7 & 0xff, + 0xe6 & 0xff, + 0xe4 & 0xff, + 0xe3 & 0xff, + 0xe1 & 0xff, + 0xe0 & 0xff, + 0xdf & 0xff, + 0xdd & 0xff, + 0xdc & 0xff, + 0xdb & 0xff, + 0xda & 0xff, + 0xd8 & 0xff, + 0xd7 & 0xff, + 0xd6 & 0xff, + 0xd5 & 0xff, + 0xd4 & 0xff, + 0xd3 & 0xff, + 0xd2 & 0xff, + 0xd0 & 0xff, + 0xcf & 0xff, + 0xce & 0xff, + 0xcd & 0xff, + 0xcc & 0xff, + 0xcb & 0xff, + 0xca & 0xff, + 0xc9 & 0xff, + 0xc8 & 0xff, + 0xc7 & 0xff, + 0xc6 & 0xff, + 0xc6 & 0xff, + 0xc5 & 0xff, + 0xc4 & 0xff, + 0xc3 & 0xff, + 0xc2 & 0xff, + 0xc1 & 0xff, + 0xc0 & 0xff, + 0xbf & 0xff, + 0xbf & 0xff, + 0xbe & 0xff, + 0xbd & 0xff, + 0xbc & 0xff, + 0xbb & 0xff, + 0xbb & 0xff, + 0xba & 0xff, + 0xb9 & 0xff, + 0xb8 & 0xff, + 0xb8 & 0xff, + 0xb7 & 0xff, + 0xb6 & 0xff, + 0xb5 & 0xff, + 0 +}; + +/* constant table vfpu2_table_mulmux */ +static const unsigned CONST_TBL_vfpu2_table_mulmux_0[] = { + 0xe & 0x3f, + 0x1e & 0x3f, + 0 +}; + +/* constant table vfpu2_table_maddmux */ +static const unsigned CONST_TBL_vfpu2_table_maddmux_0[] = { + 0xe & 0x3f, + 0x21 & 0x3f, + 0x3e & 0x3f, + 0x11 & 0x3f, + 0x1e & 0x3f, + 0x1 & 0x3f, + 0x2e & 0x3f, + 0x31 & 0x3f, + 0 +}; + +/* constant table xdsem_tab_la_default */ +static const unsigned CONST_TBL_xdsem_tab_la_default_0[] = { + 0xffff & 0xffff, + 0xfffe & 0xffff, + 0xfffc & 0xffff, + 0xfff8 & 0xffff, + 0xfff0 & 0xffff, + 0xffe0 & 0xffff, + 0xffc0 & 0xffff, + 0xff80 & 0xffff, + 0xff00 & 0xffff, + 0xfe00 & 0xffff, + 0xfc00 & 0xffff, + 0xf800 & 0xffff, + 0xf000 & 0xffff, + 0xe000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_lahr */ +static const unsigned CONST_TBL_xdsem_tab_lahr_0[] = { + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0 +}; + +/* constant table xdsem_tab_lahs */ +static const unsigned CONST_TBL_xdsem_tab_lahs_0[] = { + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev8_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev8_m64_0[] = { + 0x100 & 0xffff, + 0x200 & 0xffff, + 0x400 & 0xffff, + 0x800 & 0xffff, + 0x1000 & 0xffff, + 0x2000 & 0xffff, + 0x4000 & 0xffff, + 0x8000 & 0xffff, + 0x1 & 0xffff, + 0x2 & 0xffff, + 0x4 & 0xffff, + 0x8 & 0xffff, + 0x10 & 0xffff, + 0x20 & 0xffff, + 0x40 & 0xffff, + 0x80 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev8_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev8_m32_0[] = { + 0x1010 & 0xffff, + 0x2020 & 0xffff, + 0x4040 & 0xffff, + 0x8080 & 0xffff, + 0x101 & 0xffff, + 0x202 & 0xffff, + 0x404 & 0xffff, + 0x808 & 0xffff, + 0x1010 & 0xffff, + 0x2020 & 0xffff, + 0x4040 & 0xffff, + 0x8080 & 0xffff, + 0x101 & 0xffff, + 0x202 & 0xffff, + 0x404 & 0xffff, + 0x808 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev8_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev8_m16_0[] = { + 0x4444 & 0xffff, + 0x8888 & 0xffff, + 0x1111 & 0xffff, + 0x2222 & 0xffff, + 0x4444 & 0xffff, + 0x8888 & 0xffff, + 0x1111 & 0xffff, + 0x2222 & 0xffff, + 0x4444 & 0xffff, + 0x8888 & 0xffff, + 0x1111 & 0xffff, + 0x2222 & 0xffff, + 0x4444 & 0xffff, + 0x8888 & 0xffff, + 0x1111 & 0xffff, + 0x2222 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev8_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev8_m8_0[] = { + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev16_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev16_m64_0[] = { + 0 & 0xffff, + 0 & 0xffff, + 0x3 & 0xffff, + 0x3 & 0xffff, + 0xf & 0xffff, + 0xf & 0xffff, + 0x3f & 0xffff, + 0x3f & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xfc & 0xffff, + 0xfc & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0xc0 & 0xffff, + 0xc0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev16_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev16_m32_0[] = { + 0xff & 0xffff, + 0xff & 0xffff, + 0xcc & 0xffff, + 0xcc & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0x33 & 0xffff, + 0x33 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xcc & 0xffff, + 0xcc & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev16_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev16_m16_0[] = { + 0xff & 0xffff, + 0xff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev16_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev16_m8_0[] = { + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_128rev16_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_128rev16_m32_0[] = { + 0xffff & 0xffff, + 0xffff & 0xffff, + 0xcccc & 0xffff, + 0xcccc & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0x33 & 0xffff, + 0x33 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xcc & 0xffff, + 0xcc & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_128rev16_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_128rev16_m16_0[] = { + 0xffff & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xf0ff & 0xffff, + 0xf0ff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev32_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev32_m64_0[] = { + 0xf00 & 0xffff, + 0xf00 & 0xffff, + 0xf00 & 0xffff, + 0xf00 & 0xffff, + 0xf000 & 0xffff, + 0xf000 & 0xffff, + 0xf000 & 0xffff, + 0xf000 & 0xffff, + 0xf & 0xffff, + 0xf & 0xffff, + 0xf & 0xffff, + 0xf & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev32_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev32_m32_0[] = { + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev64_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev64_m64_0[] = { + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_r16_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_r16_m64_0[] = { + 0x300 & 0xffff, + 0x300 & 0xffff, + 0xc00 & 0xffff, + 0xc00 & 0xffff, + 0x3000 & 0xffff, + 0x3000 & 0xffff, + 0xc000 & 0xffff, + 0xc000 & 0xffff, + 0x3 & 0xffff, + 0x3 & 0xffff, + 0xc & 0xffff, + 0xc & 0xffff, + 0x30 & 0xffff, + 0x30 & 0xffff, + 0xc0 & 0xffff, + 0xc0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_r16_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_r16_m32_0[] = { + 0x3030 & 0xffff, + 0x3030 & 0xffff, + 0xc0c0 & 0xffff, + 0xc0c0 & 0xffff, + 0x303 & 0xffff, + 0x303 & 0xffff, + 0xc0c & 0xffff, + 0xc0c & 0xffff, + 0x3030 & 0xffff, + 0x3030 & 0xffff, + 0xc0c0 & 0xffff, + 0xc0c0 & 0xffff, + 0x303 & 0xffff, + 0x303 & 0xffff, + 0xc0c & 0xffff, + 0xc0c & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_r16_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_r16_m16_0[] = { + 0xcccc & 0xffff, + 0xcccc & 0xffff, + 0x3333 & 0xffff, + 0x3333 & 0xffff, + 0xcccc & 0xffff, + 0xcccc & 0xffff, + 0x3333 & 0xffff, + 0x3333 & 0xffff, + 0xcccc & 0xffff, + 0xcccc & 0xffff, + 0x3333 & 0xffff, + 0x3333 & 0xffff, + 0xcccc & 0xffff, + 0xcccc & 0xffff, + 0x3333 & 0xffff, + 0x3333 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_shiftrot_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_shiftrot_m64_0[] = { + 0 & 0xffff, + 0x101 & 0xffff, + 0x303 & 0xffff, + 0x707 & 0xffff, + 0xf0f & 0xffff, + 0x1f1f & 0xffff, + 0x3f3f & 0xffff, + 0x7f7f & 0xffff, + 0xffff & 0xffff, + 0xfefe & 0xffff, + 0xfcfc & 0xffff, + 0xf8f8 & 0xffff, + 0xf0f0 & 0xffff, + 0xe0e0 & 0xffff, + 0xc0c0 & 0xffff, + 0x8080 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_shiftrot_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_shiftrot_m32_0[] = { + 0 & 0xffff, + 0x1111 & 0xffff, + 0x3333 & 0xffff, + 0x7777 & 0xffff, + 0xffff & 0xffff, + 0xeeee & 0xffff, + 0xcccc & 0xffff, + 0x8888 & 0xffff, + 0 & 0xffff, + 0x1111 & 0xffff, + 0x3333 & 0xffff, + 0x7777 & 0xffff, + 0xffff & 0xffff, + 0xeeee & 0xffff, + 0xcccc & 0xffff, + 0x8888 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_shiftrot_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_shiftrot_m16_0[] = { + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_shiftrot_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_shiftrot_m8_0[] = { + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to16_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to16_m64_0[] = { + 0xf000 & 0xffff, + 0xe000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 & 0xffff, + 0x1 & 0xffff, + 0x3 & 0xffff, + 0x7 & 0xffff, + 0xf & 0xffff, + 0x11e & 0xffff, + 0x33c & 0xffff, + 0x778 & 0xffff, + 0xff0 & 0xffff, + 0x1ee0 & 0xffff, + 0x3cc0 & 0xffff, + 0x7880 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to16_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to16_m32_0[] = { + 0x3c0 & 0xffff, + 0x1680 & 0xffff, + 0x3c00 & 0xffff, + 0x6801 & 0xffff, + 0xc003 & 0xffff, + 0x8016 & 0xffff, + 0x3c & 0xffff, + 0x168 & 0xffff, + 0x3c0 & 0xffff, + 0x1680 & 0xffff, + 0x3c00 & 0xffff, + 0x6801 & 0xffff, + 0xc003 & 0xffff, + 0x8016 & 0xffff, + 0x3c & 0xffff, + 0x168 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to16_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to16_m16_0[] = { + 0x1818 & 0xffff, + 0x6060 & 0xffff, + 0x8181 & 0xffff, + 0x606 & 0xffff, + 0x1818 & 0xffff, + 0x6060 & 0xffff, + 0x8181 & 0xffff, + 0x606 & 0xffff, + 0x1818 & 0xffff, + 0x6060 & 0xffff, + 0x8181 & 0xffff, + 0x606 & 0xffff, + 0x1818 & 0xffff, + 0x6060 & 0xffff, + 0x8181 & 0xffff, + 0x606 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to16_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to16_m8_0[] = { + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp16to32_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp16to32_m16_0[] = { + 0x3838 & 0xffff, + 0x6161 & 0xffff, + 0x8383 & 0xffff, + 0x1616 & 0xffff, + 0x3838 & 0xffff, + 0x6161 & 0xffff, + 0x8383 & 0xffff, + 0x1616 & 0xffff, + 0x3838 & 0xffff, + 0x6161 & 0xffff, + 0x8383 & 0xffff, + 0x1616 & 0xffff, + 0x3838 & 0xffff, + 0x6161 & 0xffff, + 0x8383 & 0xffff, + 0x1616 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp16to32_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp16to32_m8_0[] = { + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to32_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to32_m64_0[] = { + 0xc00 & 0xffff, + 0x1800 & 0xffff, + 0x3000 & 0xffff, + 0x6000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 & 0xffff, + 0x1 & 0xffff, + 0x3 & 0xffff, + 0x6 & 0xffff, + 0xc & 0xffff, + 0x18 & 0xffff, + 0x30 & 0xffff, + 0x160 & 0xffff, + 0x3c0 & 0xffff, + 0x680 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to32_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to32_m32_0[] = { + 0x8020 & 0xffff, + 0x40 & 0xffff, + 0x180 & 0xffff, + 0x200 & 0xffff, + 0x401 & 0xffff, + 0x1802 & 0xffff, + 0x2004 & 0xffff, + 0x4018 & 0xffff, + 0x8020 & 0xffff, + 0x40 & 0xffff, + 0x180 & 0xffff, + 0x200 & 0xffff, + 0x401 & 0xffff, + 0x1802 & 0xffff, + 0x2004 & 0xffff, + 0x4018 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to32_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to32_m16_0[] = { + 0x2184 & 0xffff, + 0x4218 & 0xffff, + 0x8421 & 0xffff, + 0x1842 & 0xffff, + 0x2184 & 0xffff, + 0x4218 & 0xffff, + 0x8421 & 0xffff, + 0x1842 & 0xffff, + 0x2184 & 0xffff, + 0x4218 & 0xffff, + 0x8421 & 0xffff, + 0x1842 & 0xffff, + 0x2184 & 0xffff, + 0x4218 & 0xffff, + 0x8421 & 0xffff, + 0x1842 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to32_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to32_m8_0[] = { + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp16to32h_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp16to32h_m16_0[] = { + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr16to8_m8 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr16to8_m8_0[] = { + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr16to8_m16 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr16to8_m16_0[] = { + 0x4242 & 0xffff, + 0x9090 & 0xffff, + 0x2424 & 0xffff, + 0x909 & 0xffff, + 0x4242 & 0xffff, + 0x9090 & 0xffff, + 0x2424 & 0xffff, + 0x909 & 0xffff, + 0x4242 & 0xffff, + 0x9090 & 0xffff, + 0x2424 & 0xffff, + 0x909 & 0xffff, + 0x4242 & 0xffff, + 0x9090 & 0xffff, + 0x2424 & 0xffff, + 0x909 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr16to8_m32 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr16to8_m32_0[] = { + 0x300c & 0xffff, + 0x6108 & 0xffff, + 0xc300 & 0xffff, + 0x8610 & 0xffff, + 0xc30 & 0xffff, + 0x861 & 0xffff, + 0xc3 & 0xffff, + 0x1086 & 0xffff, + 0x300c & 0xffff, + 0x6108 & 0xffff, + 0xc300 & 0xffff, + 0x8610 & 0xffff, + 0xc30 & 0xffff, + 0x861 & 0xffff, + 0xc3 & 0xffff, + 0x1086 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr16to8_m64 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr16to8_m64_0[] = { + 0xf0 & 0xffff, + 0xe0 & 0xffff, + 0xc0 & 0xffff, + 0x80 & 0xffff, + 0 & 0xffff, + 0x100 & 0xffff, + 0x300 & 0xffff, + 0x700 & 0xffff, + 0xf00 & 0xffff, + 0x1e01 & 0xffff, + 0x3c03 & 0xffff, + 0x7807 & 0xffff, + 0xf00f & 0xffff, + 0xe01e & 0xffff, + 0xc03c & 0xffff, + 0x8078 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to8_m8 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to8_m8_0[] = { + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to8_m16 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to8_m16_0[] = { + 0x8400 & 0xffff, + 0x840 & 0xffff, + 0x84 & 0xffff, + 0x4008 & 0xffff, + 0x8400 & 0xffff, + 0x840 & 0xffff, + 0x84 & 0xffff, + 0x4008 & 0xffff, + 0x8400 & 0xffff, + 0x840 & 0xffff, + 0x84 & 0xffff, + 0x4008 & 0xffff, + 0x8400 & 0xffff, + 0x840 & 0xffff, + 0x84 & 0xffff, + 0x4008 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to8_m32 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to8_m32_0[] = { + 0x802 & 0xffff, + 0x4 & 0xffff, + 0x1008 & 0xffff, + 0x2000 & 0xffff, + 0x4010 & 0xffff, + 0x8120 & 0xffff, + 0x240 & 0xffff, + 0x481 & 0xffff, + 0x802 & 0xffff, + 0x4 & 0xffff, + 0x1008 & 0xffff, + 0x2000 & 0xffff, + 0x4010 & 0xffff, + 0x8120 & 0xffff, + 0x240 & 0xffff, + 0x481 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to8_m64 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to8_m64_0[] = { + 0xc & 0xffff, + 0x18 & 0xffff, + 0x30 & 0xffff, + 0x60 & 0xffff, + 0xc0 & 0xffff, + 0x80 & 0xffff, + 0 & 0xffff, + 0x100 & 0xffff, + 0x300 & 0xffff, + 0x600 & 0xffff, + 0xc00 & 0xffff, + 0x1800 & 0xffff, + 0x3000 & 0xffff, + 0x6001 & 0xffff, + 0xc003 & 0xffff, + 0x8006 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to16_m8 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to16_m8_0[] = { + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to16_m16 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to16_m16_0[] = { + 0xc0c0 & 0xffff, + 0x8484 & 0xffff, + 0xc0c & 0xffff, + 0x4848 & 0xffff, + 0xc0c0 & 0xffff, + 0x8484 & 0xffff, + 0xc0c & 0xffff, + 0x4848 & 0xffff, + 0xc0c0 & 0xffff, + 0x8484 & 0xffff, + 0xc0c & 0xffff, + 0x4848 & 0xffff, + 0xc0c0 & 0xffff, + 0x8484 & 0xffff, + 0xc0c & 0xffff, + 0x4848 & 0xffff, + 0 +}; + +/* constant table bitmask16rev */ +static const unsigned CONST_TBL_bitmask16rev_0[] = { + 0xffff & 0xffff, + 0xfffe & 0xffff, + 0xfffc & 0xffff, + 0xfff8 & 0xffff, + 0xfff0 & 0xffff, + 0xffe0 & 0xffff, + 0xffc0 & 0xffff, + 0xff80 & 0xffff, + 0xff00 & 0xffff, + 0xfe00 & 0xffff, + 0xfc00 & 0xffff, + 0xf800 & 0xffff, + 0xf000 & 0xffff, + 0xe000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 +}; + +/* constant table bitmask16sbe */ +static const unsigned CONST_TBL_bitmask16sbe_0[] = { + 0xfffe & 0xffff, + 0xfffc & 0xffff, + 0xfff8 & 0xffff, + 0xfff0 & 0xffff, + 0xffe0 & 0xffff, + 0xffc0 & 0xffff, + 0xff80 & 0xffff, + 0xff00 & 0xffff, + 0xfe00 & 0xffff, + 0xfc00 & 0xffff, + 0xf800 & 0xffff, + 0xf000 & 0xffff, + 0xe000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table bitmask16rxp */ +static const unsigned CONST_TBL_bitmask16rxp_0[] = { + 0 & 0xffff, + 0x8000 & 0xffff, + 0xc000 & 0xffff, + 0xe000 & 0xffff, + 0xf000 & 0xffff, + 0xf800 & 0xffff, + 0xfc00 & 0xffff, + 0xfe00 & 0xffff, + 0xff00 & 0xffff, + 0xff80 & 0xffff, + 0xffc0 & 0xffff, + 0xffe0 & 0xffff, + 0xfff0 & 0xffff, + 0xfff8 & 0xffff, + 0xfffc & 0xffff, + 0xfffe & 0xffff, + 0 +}; + + +/* Instruction operands. */ + +static int +OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) +{ + unsigned soffsetx4_out_0; + unsigned soffsetx4_in_0; + soffsetx4_in_0 = *valp & 0x3ffff; + soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); + *valp = soffsetx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) +{ + unsigned soffsetx4_in_0; + unsigned soffsetx4_out_0; + soffsetx4_out_0 = *valp; + soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; + *valp = soffsetx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_immr_decode (uint32 *valp) +{ + unsigned immr_out_0; + unsigned immr_in_0; + immr_in_0 = *valp & 0xf; + immr_out_0 = immr_in_0; + *valp = immr_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immr_encode (uint32 *valp) +{ + unsigned immr_in_0; + unsigned immr_out_0; + immr_out_0 = *valp; + immr_in_0 = (immr_out_0 & 0xf); + *valp = immr_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) +{ + unsigned uimm12x8_out_0; + unsigned uimm12x8_in_0; + uimm12x8_in_0 = *valp & 0xfff; + uimm12x8_out_0 = uimm12x8_in_0 << 3; + *valp = uimm12x8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) +{ + unsigned uimm12x8_in_0; + unsigned uimm12x8_out_0; + uimm12x8_out_0 = *valp; + uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); + *valp = uimm12x8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_decode (uint32 *valp) +{ + unsigned simm4_out_0; + unsigned simm4_in_0; + simm4_in_0 = *valp & 0xf; + simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; + *valp = simm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_encode (uint32 *valp) +{ + unsigned simm4_in_0; + unsigned simm4_out_0; + simm4_out_0 = *valp; + simm4_in_0 = (simm4_out_0 & 0xf); + *valp = simm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_0_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_4_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_8_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_8_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_12_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_12_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_entry_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_immrx4_decode (uint32 *valp) +{ + unsigned immrx4_out_0; + unsigned immrx4_in_0; + immrx4_in_0 = *valp & 0xf; + immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; + *valp = immrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immrx4_encode (uint32 *valp) +{ + unsigned immrx4_in_0; + unsigned immrx4_out_0; + immrx4_out_0 = *valp; + immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); + *valp = immrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) +{ + unsigned lsi4x4_out_0; + unsigned lsi4x4_in_0; + lsi4x4_in_0 = *valp & 0xf; + lsi4x4_out_0 = lsi4x4_in_0 << 2; + *valp = lsi4x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) +{ + unsigned lsi4x4_in_0; + unsigned lsi4x4_out_0; + lsi4x4_out_0 = *valp; + lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); + *valp = lsi4x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_decode (uint32 *valp) +{ + unsigned simm7_out_0; + unsigned simm7_in_0; + simm7_in_0 = *valp & 0x7f; + simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; + *valp = simm7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_encode (uint32 *valp) +{ + unsigned simm7_in_0; + unsigned simm7_out_0; + simm7_out_0 = *valp; + simm7_in_0 = (simm7_out_0 & 0x7f); + *valp = simm7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_decode (uint32 *valp) +{ + unsigned uimm6_out_0; + unsigned uimm6_in_0; + uimm6_in_0 = *valp & 0x3f; + uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); + *valp = uimm6_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_encode (uint32 *valp) +{ + unsigned uimm6_in_0; + unsigned uimm6_out_0; + uimm6_out_0 = *valp; + uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; + *valp = uimm6_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_decode (uint32 *valp) +{ + unsigned ai4const_out_0; + unsigned ai4const_in_0; + ai4const_in_0 = *valp & 0xf; + ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; + *valp = ai4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_encode (uint32 *valp) +{ + unsigned ai4const_in_0; + unsigned ai4const_out_0; + ai4const_out_0 = *valp; + switch (ai4const_out_0) + { + case 0xffffffff: ai4const_in_0 = 0; break; + case 0x1: ai4const_in_0 = 0x1; break; + case 0x2: ai4const_in_0 = 0x2; break; + case 0x3: ai4const_in_0 = 0x3; break; + case 0x4: ai4const_in_0 = 0x4; break; + case 0x5: ai4const_in_0 = 0x5; break; + case 0x6: ai4const_in_0 = 0x6; break; + case 0x7: ai4const_in_0 = 0x7; break; + case 0x8: ai4const_in_0 = 0x8; break; + case 0x9: ai4const_in_0 = 0x9; break; + case 0xa: ai4const_in_0 = 0xa; break; + case 0xb: ai4const_in_0 = 0xb; break; + case 0xc: ai4const_in_0 = 0xc; break; + case 0xd: ai4const_in_0 = 0xd; break; + case 0xe: ai4const_in_0 = 0xe; break; + default: ai4const_in_0 = 0xf; break; + } + *valp = ai4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_decode (uint32 *valp) +{ + unsigned b4const_out_0; + unsigned b4const_in_0; + b4const_in_0 = *valp & 0xf; + b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; + *valp = b4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_encode (uint32 *valp) +{ + unsigned b4const_in_0; + unsigned b4const_out_0; + b4const_out_0 = *valp; + switch (b4const_out_0) + { + case 0xffffffff: b4const_in_0 = 0; break; + case 0x1: b4const_in_0 = 0x1; break; + case 0x2: b4const_in_0 = 0x2; break; + case 0x3: b4const_in_0 = 0x3; break; + case 0x4: b4const_in_0 = 0x4; break; + case 0x5: b4const_in_0 = 0x5; break; + case 0x6: b4const_in_0 = 0x6; break; + case 0x7: b4const_in_0 = 0x7; break; + case 0x8: b4const_in_0 = 0x8; break; + case 0xa: b4const_in_0 = 0x9; break; + case 0xc: b4const_in_0 = 0xa; break; + case 0x10: b4const_in_0 = 0xb; break; + case 0x20: b4const_in_0 = 0xc; break; + case 0x40: b4const_in_0 = 0xd; break; + case 0x80: b4const_in_0 = 0xe; break; + default: b4const_in_0 = 0xf; break; + } + *valp = b4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_decode (uint32 *valp) +{ + unsigned b4constu_out_0; + unsigned b4constu_in_0; + b4constu_in_0 = *valp & 0xf; + b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; + *valp = b4constu_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_encode (uint32 *valp) +{ + unsigned b4constu_in_0; + unsigned b4constu_out_0; + b4constu_out_0 = *valp; + switch (b4constu_out_0) + { + case 0x8000: b4constu_in_0 = 0; break; + case 0x10000: b4constu_in_0 = 0x1; break; + case 0x2: b4constu_in_0 = 0x2; break; + case 0x3: b4constu_in_0 = 0x3; break; + case 0x4: b4constu_in_0 = 0x4; break; + case 0x5: b4constu_in_0 = 0x5; break; + case 0x6: b4constu_in_0 = 0x6; break; + case 0x7: b4constu_in_0 = 0x7; break; + case 0x8: b4constu_in_0 = 0x8; break; + case 0xa: b4constu_in_0 = 0x9; break; + case 0xc: b4constu_in_0 = 0xa; break; + case 0x10: b4constu_in_0 = 0xb; break; + case 0x20: b4constu_in_0 = 0xc; break; + case 0x40: b4constu_in_0 = 0xd; break; + case 0x80: b4constu_in_0 = 0xe; break; + default: b4constu_in_0 = 0xf; break; + } + *valp = b4constu_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_decode (uint32 *valp) +{ + unsigned immt_out_0; + unsigned immt_in_0; + immt_in_0 = *valp & 0xf; + immt_out_0 = immt_in_0; + *valp = immt_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_encode (uint32 *valp) +{ + unsigned immt_in_0; + unsigned immt_out_0; + immt_out_0 = *valp; + immt_in_0 = immt_out_0 & 0xf; + *valp = immt_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimms8_decode (uint32 *valp) +{ + unsigned uimms8_out_0; + unsigned uimms8_in_0; + uimms8_in_0 = *valp & 0x7; + uimms8_out_0 = uimms8_in_0; + *valp = uimms8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimms8_encode (uint32 *valp) +{ + unsigned uimms8_in_0; + unsigned uimms8_out_0; + uimms8_out_0 = *valp; + uimms8_in_0 = uimms8_out_0 & 0x7; + *valp = uimms8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_decode (uint32 *valp) +{ + unsigned uimm8_out_0; + unsigned uimm8_in_0; + uimm8_in_0 = *valp & 0xff; + uimm8_out_0 = uimm8_in_0; + *valp = uimm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_encode (uint32 *valp) +{ + unsigned uimm8_in_0; + unsigned uimm8_out_0; + uimm8_out_0 = *valp; + uimm8_in_0 = (uimm8_out_0 & 0xff); + *valp = uimm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) +{ + unsigned uimm8x2_out_0; + unsigned uimm8x2_in_0; + uimm8x2_in_0 = *valp & 0xff; + uimm8x2_out_0 = uimm8x2_in_0 << 1; + *valp = uimm8x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) +{ + unsigned uimm8x2_in_0; + unsigned uimm8x2_out_0; + uimm8x2_out_0 = *valp; + uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); + *valp = uimm8x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) +{ + unsigned uimm8x4_out_0; + unsigned uimm8x4_in_0; + uimm8x4_in_0 = *valp & 0xff; + uimm8x4_out_0 = uimm8x4_in_0 << 2; + *valp = uimm8x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) +{ + unsigned uimm8x4_in_0; + unsigned uimm8x4_out_0; + uimm8x4_out_0 = *valp; + uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); + *valp = uimm8x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) +{ + unsigned uimm4x16_out_0; + unsigned uimm4x16_in_0; + uimm4x16_in_0 = *valp & 0xf; + uimm4x16_out_0 = ((0 << 4) | uimm4x16_in_0) << 4; + *valp = uimm4x16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) +{ + unsigned uimm4x16_in_0; + unsigned uimm4x16_out_0; + uimm4x16_out_0 = *valp; + uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); + *valp = uimm4x16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp) +{ + unsigned uimmrx4_out_0; + unsigned uimmrx4_in_0; + uimmrx4_in_0 = *valp & 0xf; + uimmrx4_out_0 = ((0 << 4) | uimmrx4_in_0) << 2; + *valp = uimmrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp) +{ + unsigned uimmrx4_in_0; + unsigned uimmrx4_out_0; + uimmrx4_out_0 = *valp; + uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf); + *valp = uimmrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_decode (uint32 *valp) +{ + unsigned simm8_out_0; + unsigned simm8_in_0; + simm8_in_0 = *valp & 0xff; + simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; + *valp = simm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_encode (uint32 *valp) +{ + unsigned simm8_in_0; + unsigned simm8_out_0; + simm8_out_0 = *valp; + simm8_in_0 = (simm8_out_0 & 0xff); + *valp = simm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) +{ + unsigned simm8x256_out_0; + unsigned simm8x256_in_0; + simm8x256_in_0 = *valp & 0xff; + simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; + *valp = simm8x256_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) +{ + unsigned simm8x256_in_0; + unsigned simm8x256_out_0; + simm8x256_out_0 = *valp; + simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); + *valp = simm8x256_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_decode (uint32 *valp) +{ + unsigned simm12b_out_0; + unsigned simm12b_in_0; + simm12b_in_0 = *valp & 0xfff; + simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; + *valp = simm12b_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_encode (uint32 *valp) +{ + unsigned simm12b_in_0; + unsigned simm12b_out_0; + simm12b_out_0 = *valp; + simm12b_in_0 = (simm12b_out_0 & 0xfff); + *valp = simm12b_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_decode (uint32 *valp) +{ + unsigned msalp32_out_0; + unsigned msalp32_in_0; + msalp32_in_0 = *valp & 0x1f; + msalp32_out_0 = 0x20 - msalp32_in_0; + *valp = msalp32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_encode (uint32 *valp) +{ + unsigned msalp32_in_0; + unsigned msalp32_out_0; + msalp32_out_0 = *valp; + msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; + *valp = msalp32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_out_0; + unsigned op2p1_in_0; + op2p1_in_0 = *valp & 0xf; + op2p1_out_0 = op2p1_in_0 + 0x1; + *valp = op2p1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_encode (uint32 *valp) +{ + unsigned op2p1_in_0; + unsigned op2p1_out_0; + op2p1_out_0 = *valp; + op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; + *valp = op2p1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_decode (uint32 *valp) +{ + unsigned label8_out_0; + unsigned label8_in_0; + label8_in_0 = *valp & 0xff; + label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); + *valp = label8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_encode (uint32 *valp) +{ + unsigned label8_in_0; + unsigned label8_out_0; + label8_out_0 = *valp; + label8_in_0 = (label8_out_0 - 0x4) & 0xff; + *valp = label8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_decode (uint32 *valp) +{ + unsigned ulabel8_out_0; + unsigned ulabel8_in_0; + ulabel8_in_0 = *valp & 0xff; + ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0); + *valp = ulabel8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_encode (uint32 *valp) +{ + unsigned ulabel8_in_0; + unsigned ulabel8_out_0; + ulabel8_out_0 = *valp; + ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff; + *valp = ulabel8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_decode (uint32 *valp) +{ + unsigned label12_out_0; + unsigned label12_in_0; + label12_in_0 = *valp & 0xfff; + label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); + *valp = label12_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_encode (uint32 *valp) +{ + unsigned label12_in_0; + unsigned label12_out_0; + label12_out_0 = *valp; + label12_in_0 = (label12_out_0 - 0x4) & 0xfff; + *valp = label12_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_decode (uint32 *valp) +{ + unsigned soffset_out_0; + unsigned soffset_in_0; + soffset_in_0 = *valp & 0x3ffff; + soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); + *valp = soffset_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_encode (uint32 *valp) +{ + unsigned soffset_in_0; + unsigned soffset_out_0; + soffset_out_0 = *valp; + soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; + *valp = soffset_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) +{ + unsigned uimm16x4_out_0; + unsigned uimm16x4_in_0; + uimm16x4_in_0 = *valp & 0xffff; + uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; + *valp = uimm16x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) +{ + unsigned uimm16x4_in_0; + unsigned uimm16x4_out_0; + uimm16x4_out_0 = *valp; + uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; + *valp = uimm16x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_decode (uint32 *valp) +{ + unsigned bbi_out_0; + unsigned bbi_in_0; + bbi_in_0 = *valp & 0x1f; + bbi_out_0 = (0 << 5) | bbi_in_0; + *valp = bbi_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_encode (uint32 *valp) +{ + unsigned bbi_in_0; + unsigned bbi_out_0; + bbi_out_0 = *valp; + bbi_in_0 = (bbi_out_0 & 0x1f); + *valp = bbi_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_decode (uint32 *valp) +{ + unsigned s_out_0; + unsigned s_in_0; + s_in_0 = *valp & 0xf; + s_out_0 = (0 << 4) | s_in_0; + *valp = s_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_encode (uint32 *valp) +{ + unsigned s_in_0; + unsigned s_out_0; + s_out_0 = *valp; + s_in_0 = (s_out_0 & 0xf); + *valp = s_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_imms_decode (uint32 *valp) +{ + unsigned imms_out_0; + unsigned imms_in_0; + imms_in_0 = *valp & 0xf; + imms_out_0 = imms_in_0; + *valp = imms_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_imms_encode (uint32 *valp) +{ + unsigned imms_in_0; + unsigned imms_out_0; + imms_out_0 = *valp; + imms_in_0 = imms_out_0 & 0xf; + *valp = imms_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_BR_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16); + return error; +} + +static int +OperandSem_opnd_sem_BR2_decode (uint32 *valp) +{ + *valp = *valp << 1; + return 0; +} + +static int +OperandSem_opnd_sem_BR2_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 1) != 0); + *valp = *valp >> 1; + return error; +} + +static int +OperandSem_opnd_sem_BR4_decode (uint32 *valp) +{ + *valp = *valp << 2; + return 0; +} + +static int +OperandSem_opnd_sem_BR4_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 3) != 0); + *valp = *valp >> 2; + return error; +} + +static int +OperandSem_opnd_sem_BR8_decode (uint32 *valp) +{ + *valp = *valp << 3; + return 0; +} + +static int +OperandSem_opnd_sem_BR8_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 7) != 0); + *valp = *valp >> 3; + return error; +} + +static int +OperandSem_opnd_sem_BR16_decode (uint32 *valp) +{ + *valp = *valp << 4; + return 0; +} + +static int +OperandSem_opnd_sem_BR16_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 15) != 0); + *valp = *valp >> 4; + return error; +} + +static int +OperandSem_opnd_sem_tp7_decode (uint32 *valp) +{ + unsigned tp7_out_0; + unsigned tp7_in_0; + tp7_in_0 = *valp & 0xf; + tp7_out_0 = tp7_in_0 + 0x7; + *valp = tp7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_tp7_encode (uint32 *valp) +{ + unsigned tp7_in_0; + unsigned tp7_out_0; + tp7_out_0 = *valp; + tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; + *valp = tp7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) +{ + unsigned xt_wbr15_label_out_0; + unsigned xt_wbr15_label_in_0; + xt_wbr15_label_in_0 = *valp & 0x7fff; + xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); + *valp = xt_wbr15_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) +{ + unsigned xt_wbr15_label_in_0; + unsigned xt_wbr15_label_out_0; + xt_wbr15_label_out_0 = *valp; + xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; + *valp = xt_wbr15_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp) +{ + unsigned xt_wbr18_label_out_0; + unsigned xt_wbr18_label_in_0; + xt_wbr18_label_in_0 = *valp & 0x3ffff; + xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14); + *valp = xt_wbr18_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp) +{ + unsigned xt_wbr18_label_in_0; + unsigned xt_wbr18_label_out_0; + xt_wbr18_label_out_0 = *valp; + xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff; + *valp = xt_wbr18_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_uimm2x2_decode (uint32 *valp) +{ + unsigned ae_uimm2x2_out_0; + unsigned ae_uimm2x2_in_0; + ae_uimm2x2_in_0 = *valp & 0x1; + ae_uimm2x2_out_0 = (0 << 2) | (ae_uimm2x2_in_0 << 1) | 0; + *valp = ae_uimm2x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_uimm2x2_encode (uint32 *valp) +{ + unsigned ae_uimm2x2_in_0; + unsigned ae_uimm2x2_out_0; + ae_uimm2x2_out_0 = *valp; + ae_uimm2x2_in_0 = (((ae_uimm2x2_out_0 >> 1) & 1)) & 0x1; + *valp = ae_uimm2x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AE_DR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_DR_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64_out_0; + unsigned opnd_ae_sem_loads_stores_i64_in_0; + opnd_ae_sem_loads_stores_i64_in_0 = *valp & 0xf; + opnd_ae_sem_loads_stores_i64_out_0 = (((int) opnd_ae_sem_loads_stores_i64_in_0 << 28) >> 28) << 3; + *valp = opnd_ae_sem_loads_stores_i64_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64_in_0; + unsigned opnd_ae_sem_loads_stores_i64_out_0; + opnd_ae_sem_loads_stores_i64_out_0 = *valp; + opnd_ae_sem_loads_stores_i64_in_0 = ((opnd_ae_sem_loads_stores_i64_out_0 >> 3) & 0xf); + *valp = opnd_ae_sem_loads_stores_i64_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_sb_loads_stores_iba_out_0; + unsigned opnd_ae_sem_sb_loads_stores_iba_in_0; + opnd_ae_sem_sb_loads_stores_iba_in_0 = *valp & 0xf; + opnd_ae_sem_sb_loads_stores_iba_out_0 = CONST_TBL_ae_ohba_0[opnd_ae_sem_sb_loads_stores_iba_in_0 & 0xf]; + *valp = opnd_ae_sem_sb_loads_stores_iba_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_sb_loads_stores_iba_in_0; + unsigned opnd_ae_sem_sb_loads_stores_iba_out_0; + opnd_ae_sem_sb_loads_stores_iba_out_0 = *valp; + switch (opnd_ae_sem_sb_loads_stores_iba_out_0) + { + case 0x1: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0; break; + case 0x2: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x1; break; + case 0x3: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x2; break; + case 0x4: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x3; break; + case 0x5: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x4; break; + case 0x6: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x5; break; + case 0x7: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x6; break; + case 0x8: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x7; break; + case 0x9: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x8; break; + case 0xa: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x9; break; + case 0xb: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xa; break; + case 0xc: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xb; break; + case 0xd: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xc; break; + case 0xe: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xd; break; + case 0xf: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xe; break; + default: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xf; break; + } + *valp = opnd_ae_sem_sb_loads_stores_iba_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_imm2_out_0; + unsigned opnd_ae_sem_loads_stores_imm2_in_0; + opnd_ae_sem_loads_stores_imm2_in_0 = *valp & 0x3; + opnd_ae_sem_loads_stores_imm2_out_0 = (0 << 2) | opnd_ae_sem_loads_stores_imm2_in_0; + *valp = opnd_ae_sem_loads_stores_imm2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_imm2_in_0; + unsigned opnd_ae_sem_loads_stores_imm2_out_0; + opnd_ae_sem_loads_stores_imm2_out_0 = *valp; + opnd_ae_sem_loads_stores_imm2_in_0 = (opnd_ae_sem_loads_stores_imm2_out_0 & 0x3); + *valp = opnd_ae_sem_loads_stores_imm2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_movi_imm_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_dr_to_dr_movi_imm_out_0; + unsigned opnd_ae_sem_dr_to_dr_movi_imm_in_0; + opnd_ae_sem_dr_to_dr_movi_imm_in_0 = *valp & 0x3f; + opnd_ae_sem_dr_to_dr_movi_imm_out_0 = (((-(( ( ((((opnd_ae_sem_dr_to_dr_movi_imm_in_0 >> 4) & 0x3)) | 0xfffffffc)) == 0xffffffff))) & 0x3ffffff) << 6) | opnd_ae_sem_dr_to_dr_movi_imm_in_0; + *valp = opnd_ae_sem_dr_to_dr_movi_imm_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_movi_imm_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_dr_to_dr_movi_imm_in_0; + unsigned opnd_ae_sem_dr_to_dr_movi_imm_out_0; + opnd_ae_sem_dr_to_dr_movi_imm_out_0 = *valp; + opnd_ae_sem_dr_to_dr_movi_imm_in_0 = (opnd_ae_sem_dr_to_dr_movi_imm_out_0 & 0x3f); + *valp = opnd_ae_sem_dr_to_dr_movi_imm_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_spfma_i_imm3_out_0; + unsigned opnd_ae_sem_spfma_i_imm3_in_0; + opnd_ae_sem_spfma_i_imm3_in_0 = *valp & 0x7; + opnd_ae_sem_spfma_i_imm3_out_0 = (0 << 3) | opnd_ae_sem_spfma_i_imm3_in_0; + *valp = opnd_ae_sem_spfma_i_imm3_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_spfma_i_imm3_in_0; + unsigned opnd_ae_sem_spfma_i_imm3_out_0; + opnd_ae_sem_spfma_i_imm3_out_0 = *valp; + opnd_ae_sem_spfma_i_imm3_in_0 = (opnd_ae_sem_spfma_i_imm3_out_0 & 0x7); + *valp = opnd_ae_sem_spfma_i_imm3_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AE_VALIGN_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_VALIGN_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i32_out_0; + unsigned opnd_ae_sem_loads_stores_i32_in_0; + opnd_ae_sem_loads_stores_i32_in_0 = *valp & 0xf; + opnd_ae_sem_loads_stores_i32_out_0 = (((int) opnd_ae_sem_loads_stores_i32_in_0 << 28) >> 28) << 2; + *valp = opnd_ae_sem_loads_stores_i32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i32_in_0; + unsigned opnd_ae_sem_loads_stores_i32_out_0; + opnd_ae_sem_loads_stores_i32_out_0 = *valp; + opnd_ae_sem_loads_stores_i32_in_0 = ((opnd_ae_sem_loads_stores_i32_out_0 >> 2) & 0xf); + *valp = opnd_ae_sem_loads_stores_i32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i16_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i16_out_0; + unsigned opnd_ae_sem_loads_stores_i16_in_0; + opnd_ae_sem_loads_stores_i16_in_0 = *valp & 0xf; + opnd_ae_sem_loads_stores_i16_out_0 = (((int) opnd_ae_sem_loads_stores_i16_in_0 << 28) >> 28) << 1; + *valp = opnd_ae_sem_loads_stores_i16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i16_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i16_in_0; + unsigned opnd_ae_sem_loads_stores_i16_out_0; + opnd_ae_sem_loads_stores_i16_out_0 = *valp; + opnd_ae_sem_loads_stores_i16_in_0 = ((opnd_ae_sem_loads_stores_i16_out_0 >> 1) & 0xf); + *valp = opnd_ae_sem_loads_stores_i16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i8_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i8_out_0; + unsigned opnd_ae_sem_loads_stores_i8_in_0; + opnd_ae_sem_loads_stores_i8_in_0 = *valp & 0xf; + opnd_ae_sem_loads_stores_i8_out_0 = ((int) opnd_ae_sem_loads_stores_i8_in_0 << 28) >> 28; + *valp = opnd_ae_sem_loads_stores_i8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i8_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i8_in_0; + unsigned opnd_ae_sem_loads_stores_i8_out_0; + opnd_ae_sem_loads_stores_i8_out_0 = *valp; + opnd_ae_sem_loads_stores_i8_in_0 = (opnd_ae_sem_loads_stores_i8_out_0 & 0xf); + *valp = opnd_ae_sem_loads_stores_i8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64pos_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64pos_out_0; + unsigned opnd_ae_sem_loads_stores_i64pos_in_0; + opnd_ae_sem_loads_stores_i64pos_in_0 = *valp & 0x7; + opnd_ae_sem_loads_stores_i64pos_out_0 = ((0 << 3) | opnd_ae_sem_loads_stores_i64pos_in_0) << 3; + *valp = opnd_ae_sem_loads_stores_i64pos_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64pos_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64pos_in_0; + unsigned opnd_ae_sem_loads_stores_i64pos_out_0; + opnd_ae_sem_loads_stores_i64pos_out_0 = *valp; + opnd_ae_sem_loads_stores_i64pos_in_0 = ((opnd_ae_sem_loads_stores_i64pos_out_0 >> 3) & 0x7); + *valp = opnd_ae_sem_loads_stores_i64pos_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64neg_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64neg_out_0; + unsigned opnd_ae_sem_loads_stores_i64neg_in_0; + opnd_ae_sem_loads_stores_i64neg_in_0 = *valp & 0x3; + opnd_ae_sem_loads_stores_i64neg_out_0 = CONST_TBL_ae_immls64neg_0[opnd_ae_sem_loads_stores_i64neg_in_0 & 0x3]; + *valp = opnd_ae_sem_loads_stores_i64neg_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64neg_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64neg_in_0; + unsigned opnd_ae_sem_loads_stores_i64neg_out_0; + opnd_ae_sem_loads_stores_i64neg_out_0 = *valp; + opnd_ae_sem_loads_stores_i64neg_in_0 = (((opnd_ae_sem_loads_stores_i64neg_out_0 == (CONST_TBL_ae_immls64neg_0[0]))) ? 0 : (((opnd_ae_sem_loads_stores_i64neg_out_0 == (CONST_TBL_ae_immls64neg_0[1]))) ? 0x1 : (((opnd_ae_sem_loads_stores_i64neg_out_0 == (CONST_TBL_ae_immls64neg_0[2]))) ? 0x2 : 0x3))) & 0x3; + *valp = opnd_ae_sem_loads_stores_i64neg_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64half_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64half_out_0; + unsigned opnd_ae_sem_loads_stores_i64half_in_0; + opnd_ae_sem_loads_stores_i64half_in_0 = *valp & 0x7; + opnd_ae_sem_loads_stores_i64half_out_0 = (((int) opnd_ae_sem_loads_stores_i64half_in_0 << 29) >> 29) << 3; + *valp = opnd_ae_sem_loads_stores_i64half_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64half_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64half_in_0; + unsigned opnd_ae_sem_loads_stores_i64half_out_0; + opnd_ae_sem_loads_stores_i64half_out_0 = *valp; + opnd_ae_sem_loads_stores_i64half_in_0 = ((opnd_ae_sem_loads_stores_i64half_out_0 >> 3) & 0x7); + *valp = opnd_ae_sem_loads_stores_i64half_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_hpcnv_i_imm4_out_0; + unsigned opnd_ae_sem_hpcnv_i_imm4_in_0; + opnd_ae_sem_hpcnv_i_imm4_in_0 = *valp & 0xf; + opnd_ae_sem_hpcnv_i_imm4_out_0 = (0 << 4) | opnd_ae_sem_hpcnv_i_imm4_in_0; + *valp = opnd_ae_sem_hpcnv_i_imm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_hpcnv_i_imm4_in_0; + unsigned opnd_ae_sem_hpcnv_i_imm4_out_0; + opnd_ae_sem_hpcnv_i_imm4_out_0 = *valp; + opnd_ae_sem_hpcnv_i_imm4_in_0 = (opnd_ae_sem_hpcnv_i_imm4_out_0 & 0xf); + *valp = opnd_ae_sem_hpcnv_i_imm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_sp32cvt_i_imm5_out_0; + unsigned opnd_ae_sem_sp32cvt_i_imm5_in_0; + opnd_ae_sem_sp32cvt_i_imm5_in_0 = *valp & 0x1f; + opnd_ae_sem_sp32cvt_i_imm5_out_0 = (0 << 5) | opnd_ae_sem_sp32cvt_i_imm5_in_0; + *valp = opnd_ae_sem_sp32cvt_i_imm5_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_sp32cvt_i_imm5_in_0; + unsigned opnd_ae_sem_sp32cvt_i_imm5_out_0; + opnd_ae_sem_sp32cvt_i_imm5_out_0 = *valp; + opnd_ae_sem_sp32cvt_i_imm5_in_0 = (opnd_ae_sem_sp32cvt_i_imm5_out_0 & 0x1f); + *valp = opnd_ae_sem_sp32cvt_i_imm5_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_shift_i64_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_shift_i64_out_0; + unsigned opnd_ae_sem_shift_i64_in_0; + opnd_ae_sem_shift_i64_in_0 = *valp & 0x3f; + opnd_ae_sem_shift_i64_out_0 = (0 << 6) | opnd_ae_sem_shift_i64_in_0; + *valp = opnd_ae_sem_shift_i64_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_shift_i64_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_shift_i64_in_0; + unsigned opnd_ae_sem_shift_i64_out_0; + opnd_ae_sem_shift_i64_out_0 = *valp; + opnd_ae_sem_shift_i64_in_0 = (opnd_ae_sem_shift_i64_out_0 & 0x3f); + *valp = opnd_ae_sem_shift_i64_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i128_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i128_out_0; + unsigned opnd_ae_sem_loads_stores_i128_in_0; + opnd_ae_sem_loads_stores_i128_in_0 = *valp & 0xf; + opnd_ae_sem_loads_stores_i128_out_0 = (((int) opnd_ae_sem_loads_stores_i128_in_0 << 28) >> 28) << 4; + *valp = opnd_ae_sem_loads_stores_i128_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i128_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i128_in_0; + unsigned opnd_ae_sem_loads_stores_i128_out_0; + opnd_ae_sem_loads_stores_i128_out_0 = *valp; + opnd_ae_sem_loads_stores_i128_in_0 = ((opnd_ae_sem_loads_stores_i128_out_0 >> 4) & 0xf); + *valp = opnd_ae_sem_loads_stores_i128_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AE_EP_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_EP_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_shift_i8_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_shift_i8_out_0; + unsigned opnd_ae_sem_shift_i8_in_0; + opnd_ae_sem_shift_i8_in_0 = *valp & 0x7; + opnd_ae_sem_shift_i8_out_0 = CONST_TBL_ae_slai72table_0[opnd_ae_sem_shift_i8_in_0 & 0x7]; + *valp = opnd_ae_sem_shift_i8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_shift_i8_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_shift_i8_in_0; + unsigned opnd_ae_sem_shift_i8_out_0; + opnd_ae_sem_shift_i8_out_0 = *valp; + switch (opnd_ae_sem_shift_i8_out_0) + { + case 0x1: opnd_ae_sem_shift_i8_in_0 = 0; break; + case 0x2: opnd_ae_sem_shift_i8_in_0 = 0x1; break; + case 0x3: opnd_ae_sem_shift_i8_in_0 = 0x2; break; + case 0x4: opnd_ae_sem_shift_i8_in_0 = 0x3; break; + case 0x5: opnd_ae_sem_shift_i8_in_0 = 0x4; break; + case 0x6: opnd_ae_sem_shift_i8_in_0 = 0x5; break; + case 0x7: opnd_ae_sem_shift_i8_in_0 = 0x6; break; + default: opnd_ae_sem_shift_i8_in_0 = 0x7; break; + } + *valp = opnd_ae_sem_shift_i8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_imm_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_dr_to_dr_imm_out_0; + unsigned opnd_ae_sem_dr_to_dr_imm_in_0; + opnd_ae_sem_dr_to_dr_imm_in_0 = *valp & 0xf; + opnd_ae_sem_dr_to_dr_imm_out_0 = CONST_TBL_ae_opnd_tp7_0[opnd_ae_sem_dr_to_dr_imm_in_0 & 0xf]; + *valp = opnd_ae_sem_dr_to_dr_imm_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_imm_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_dr_to_dr_imm_in_0; + unsigned opnd_ae_sem_dr_to_dr_imm_out_0; + opnd_ae_sem_dr_to_dr_imm_out_0 = *valp; + switch (opnd_ae_sem_dr_to_dr_imm_out_0) + { + case 0x7: opnd_ae_sem_dr_to_dr_imm_in_0 = 0; break; + case 0x8: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x1; break; + case 0x9: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x2; break; + case 0xa: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x3; break; + case 0xb: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x4; break; + case 0xc: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x5; break; + case 0xd: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x6; break; + case 0xe: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x7; break; + case 0xf: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x8; break; + case 0x10: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x9; break; + case 0x11: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xa; break; + case 0x12: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xb; break; + case 0x13: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xc; break; + case 0x14: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xd; break; + case 0x15: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xe; break; + default: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xf; break; + } + *valp = opnd_ae_sem_dr_to_dr_imm_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba2_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_sb_loads_stores_iba2_out_0; + unsigned opnd_ae_sem_sb_loads_stores_iba2_in_0; + opnd_ae_sem_sb_loads_stores_iba2_in_0 = *valp & 0xf; + opnd_ae_sem_sb_loads_stores_iba2_out_0 = CONST_TBL_ae_ohba2_0[opnd_ae_sem_sb_loads_stores_iba2_in_0 & 0xf]; + *valp = opnd_ae_sem_sb_loads_stores_iba2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba2_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_sb_loads_stores_iba2_in_0; + unsigned opnd_ae_sem_sb_loads_stores_iba2_out_0; + opnd_ae_sem_sb_loads_stores_iba2_out_0 = *valp; + switch (opnd_ae_sem_sb_loads_stores_iba2_out_0) + { + case 0x1: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0; break; + case 0x2: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x1; break; + case 0x3: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x2; break; + case 0x4: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x3; break; + case 0x5: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x4; break; + case 0x6: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x5; break; + case 0x7: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x6; break; + case 0x8: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x7; break; + case 0x9: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x8; break; + case 0xa: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x9; break; + case 0xb: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xa; break; + case 0xc: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xb; break; + case 0xd: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xc; break; + case 0xe: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xd; break; + case 0xf: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xe; break; + default: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xf; break; + } + *valp = opnd_ae_sem_sb_loads_stores_iba2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm1_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_spfma_i_imm1_out_0; + unsigned opnd_ae_sem_spfma_i_imm1_in_0; + opnd_ae_sem_spfma_i_imm1_in_0 = *valp & 0x1; + opnd_ae_sem_spfma_i_imm1_out_0 = (0 << 1) | opnd_ae_sem_spfma_i_imm1_in_0; + *valp = opnd_ae_sem_spfma_i_imm1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm1_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_spfma_i_imm1_in_0; + unsigned opnd_ae_sem_spfma_i_imm1_out_0; + opnd_ae_sem_spfma_i_imm1_out_0 = *valp; + opnd_ae_sem_spfma_i_imm1_in_0 = (((opnd_ae_sem_spfma_i_imm1_out_0 >> 0) & 1)) & 0x1; + *valp = opnd_ae_sem_spfma_i_imm1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bitindex_decode (uint32 *valp) +{ + unsigned bitindex_out_0; + unsigned bitindex_in_0; + bitindex_in_0 = *valp & 0x1f; + bitindex_out_0 = (0 << 5) | bitindex_in_0; + *valp = bitindex_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bitindex_encode (uint32 *valp) +{ + unsigned bitindex_in_0; + unsigned bitindex_out_0; + bitindex_out_0 = *valp; + bitindex_in_0 = (bitindex_out_0 & 0x1f); + *valp = bitindex_in_0; + return 0; +} + +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +{ + *valp -= (pc & ~0x3); + return 0; +} + +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += (pc & ~0x3); + return 0; +} + +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ulabel8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label12_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +{ + *valp -= ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static xtensa_operand_internal operands[] = { + { "soffsetx4", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa, + -1, 0 }, + { "immr", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_immr_encode, OperandSem_opnd_sem_immr_decode, + 0, 0, + -1, 0 }, + { "uimm12x8", FIELD_imm12, -1, 0, + 0, + OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, + 0, 0, + -1, 0 }, + { "simm4", FIELD_mn, -1, 0, + 0, + OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, + 0, 0, + -1, 0 }, + { "arr", FIELD_r, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "ars", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "*ars_invisible", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "art", FIELD_t, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "ar0", FIELD__ar0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, + 0, 0, + 0, 63 }, + { "ar4", FIELD__ar4, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, + 0, 0, + 0, 63 }, + { "ar8", FIELD__ar8, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_8_encode, OperandSem_opnd_sem_AR_8_decode, + 0, 0, + 0, 63 }, + { "ar12", FIELD__ar12, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_12_encode, OperandSem_opnd_sem_AR_12_decode, + 0, 0, + 0, 63 }, + { "ars_entry", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_entry_encode, OperandSem_opnd_sem_AR_entry_decode, + 0, 0, + 0, 63 }, + { "immrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, + 0, 0, + -1, 0 }, + { "lsi4x4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, + 0, 0, + -1, 0 }, + { "simm7", FIELD_imm7, -1, 0, + 0, + OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, + 0, 0, + -1, 0 }, + { "uimm6", FIELD_imm6, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa, + -1, 0 }, + { "ai4const", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, + 0, 0, + -1, 0 }, + { "b4const", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, + 0, 0, + -1, 0 }, + { "b4constu", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, + 0, 0, + -1, 0 }, + { "immt", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, + 0, 0, + -1, 0 }, + { "uimms8", FIELD_imms8, -1, 0, + 0, + OperandSem_opnd_sem_uimms8_encode, OperandSem_opnd_sem_uimms8_decode, + 0, 0, + -1, 0 }, + { "uimm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, + 0, 0, + -1, 0 }, + { "uimm8x2", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, + 0, 0, + -1, 0 }, + { "uimm8x4", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, + 0, 0, + -1, 0 }, + { "uimm4x16", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, + 0, 0, + -1, 0 }, + { "uimmrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode, + 0, 0, + -1, 0 }, + { "simm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, + 0, 0, + -1, 0 }, + { "simm8x256", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, + 0, 0, + -1, 0 }, + { "simm12b", FIELD_imm12b, -1, 0, + 0, + OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, + 0, 0, + -1, 0 }, + { "msalp32", FIELD_sal, -1, 0, + 0, + OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, + 0, 0, + -1, 0 }, + { "op2p1", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, + 0, 0, + -1, 0 }, + { "label8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, + Operand_label8_ator, Operand_label8_rtoa, + -1, 0 }, + { "ulabel8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode, + Operand_ulabel8_ator, Operand_ulabel8_rtoa, + -1, 0 }, + { "label12", FIELD_imm12, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, + Operand_label12_ator, Operand_label12_rtoa, + -1, 0 }, + { "soffset", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa, + -1, 0 }, + { "uimm16x4", FIELD_imm16, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa, + -1, 0 }, + { "bbi", FIELD_bbi, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "sae", FIELD_sae, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "sas", FIELD_sas, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "sargt", FIELD_sargt, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "s", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, + 0, 0, + -1, 0 }, + { "imms", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_imms_encode, OperandSem_opnd_sem_imms_decode, + 0, 0, + -1, 0 }, + { "imms1", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_imms_encode, OperandSem_opnd_sem_imms_decode, + 0, 0, + -1, 0 }, + { "bt", FIELD_t, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "bs", FIELD_s, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "br", FIELD_r, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "bt2", FIELD_t2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "bs2", FIELD_s2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "br2", FIELD_r2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "bt4", FIELD_t4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "bs4", FIELD_s4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "br4", FIELD_r4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "bt8", FIELD_t8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0, + 0, 15 }, + { "bs8", FIELD_s8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0, + 0, 15 }, + { "br8", FIELD_r8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0, + 0, 15 }, + { "bt16", FIELD__bt16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "bs16", FIELD__bs16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "br16", FIELD__br16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "brall", FIELD__brall, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "tp7", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, + 0, 0, + -1, 0 }, + { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa, + -1, 0 }, + { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode, + Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa, + -1, 0 }, + { "ae_uimm2x2", FIELD_ae_fld_Inst16b_12, -1, 0, + 0, + OperandSem_opnd_sem_ae_uimm2x2_encode, OperandSem_opnd_sem_ae_uimm2x2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_dr_v", FIELD_fld_ae_sem_dr_to_dr_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_arithmetic_v", FIELD_fld_ae_sem_arithmetic_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_arithmetic_v0", FIELD_fld_ae_sem_arithmetic_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_arithmetic_v1", FIELD_fld_ae_sem_arithmetic_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_a.0", FIELD_fld_ae_sem_loads_stores_a_0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_loads_stores_x", FIELD_fld_ae_sem_loads_stores_x, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_loads_stores_end", FIELD_fld_ae_sem_loads_stores_end, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_loads_stores_i64", FIELD_fld_ae_sem_loads_stores_i64, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_lb_ops_iba", FIELD_fld_ae_sem_lb_ops_iba, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_encode, OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_sb_loads_stores_iba", FIELD_fld_ae_sem_sb_loads_stores_iba, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_encode, OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_pks_d", FIELD_fld_ae_sem_pks_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_pks_pos", FIELD_fld_ae_sem_pks_pos, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_pks_s", FIELD_fld_ae_sem_pks_s, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_a", FIELD_fld_ae_sem_dr_to_ar_a, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_dr_to_ar_v0", FIELD_fld_ae_sem_dr_to_ar_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_v0", FIELD_fld_ae_sem_dr_to_dr_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_ab", FIELD_fld_ae_sem_dr_to_ar_ab, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_dr_to_ar_ai", FIELD_fld_ae_sem_dr_to_ar_ai, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_dr_to_ar_aoe", FIELD_fld_ae_sem_dr_to_ar_aoe, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_dr_to_dr_movi_imm", FIELD_fld_ae_sem_dr_to_dr_movi_imm, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_movi_imm_encode, OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_movi_imm_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_dr_ds", FIELD_fld_ae_sem_dr_to_dr_ds, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_v1", FIELD_fld_ae_sem_dr_to_dr_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_imm8", FIELD_fld_ae_sem_dr_to_ar_imm8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_encode, OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_a0", FIELD_fld_ae_sem_shift_a0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_shift_d", FIELD_fld_ae_sem_shift_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_shift_d0", FIELD_fld_ae_sem_shift_d0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_d", FIELD_fld_ae_sem_dr_to_ar_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_d0", FIELD_fld_ae_sem_dr_to_ar_d0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_d1", FIELD_fld_ae_sem_dr_to_ar_d1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_imm2", FIELD_fld_ae_sem_dr_to_dr_imm2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_arithmetic_ds", FIELD_fld_ae_sem_arithmetic_ds, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_uu", FIELD_fld_ae_sem_loads_stores_uu, REGFILE_AE_VALIGN, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_VALIGN_encode, OperandSem_opnd_sem_AE_VALIGN_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_loads_stores_vu", FIELD_fld_ae_sem_loads_stores_vu, REGFILE_AE_VALIGN, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_VALIGN_encode, OperandSem_opnd_sem_AE_VALIGN_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_loads_stores_i32", FIELD_fld_ae_sem_loads_stores_i32, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_v", FIELD_fld_ae_sem_loads_stores_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_i16", FIELD_fld_ae_sem_loads_stores_i16, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i16_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i16_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i8", FIELD_fld_ae_sem_loads_stores_i8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i8_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i8_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i64pos", FIELD_fld_ae_sem_loads_stores_i64pos, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64pos_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64pos_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i64neg", FIELD_fld_ae_sem_loads_stores_i64neg, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64neg_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64neg_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i64half", FIELD_fld_ae_sem_loads_stores_i64half, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64half_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64half_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_su", FIELD_fld_ae_sem_loads_stores_su, REGFILE_AE_VALIGN, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_VALIGN_encode, OperandSem_opnd_sem_AE_VALIGN_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_loads_stores_v1", FIELD_fld_ae_sem_loads_stores_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_av", FIELD_fld_ae_sem_loads_stores_av, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_shift_i16", FIELD_fld_ae_sem_shift_i16, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_encode, OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_i32", FIELD_fld_ae_sem_shift_i32, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_encode, OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_d1", FIELD_fld_ae_sem_shift_d1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_shift_da", FIELD_fld_ae_sem_shift_da, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_shift_imm32", FIELD_fld_ae_sem_shift_imm32, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_encode, OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_a", FIELD_fld_ae_sem_shift_a, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_shift_sd", FIELD_fld_ae_sem_shift_sd, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_shift_i64", FIELD_fld_ae_sem_shift_i64, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_shift_i64_encode, OperandSem_opnd_sem_opnd_ae_sem_shift_i64_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_imm8", FIELD_fld_ae_sem_shift_imm8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_encode, OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_dr_immed", FIELD_fld_ae_sem_dr_to_dr_immed, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_encode, OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_arithmetic_art", FIELD_fld_ae_sem_arithmetic_art, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_arithmetic_va", FIELD_fld_ae_sem_arithmetic_va, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_arithmetic_vs", FIELD_fld_ae_sem_arithmetic_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_i128", FIELD_fld_ae_sem_loads_stores_i128, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i128_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i128_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_av1", FIELD_fld_ae_sem_loads_stores_av1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_imm2", FIELD_fld_ae_sem_loads_stores_imm2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i3", FIELD_fld_ae_sem_loads_stores_i3, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_encode, OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_rng_v0", FIELD_fld_ae_sem_rng_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_rng_v1", FIELD_fld_ae_sem_rng_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_reduction_sort_v", FIELD_fld_ae_sem_reduction_sort_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_reduction_sort_v0", FIELD_fld_ae_sem_reduction_sort_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_reduction_sort_ds", FIELD_fld_ae_sem_reduction_sort_ds, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_multiply_d0", FIELD_fld_ae_sem_multiply_d0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_multiply_d2", FIELD_fld_ae_sem_multiply_d2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_multiply_q0", FIELD_fld_ae_sem_multiply_q0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_multiply_q1", FIELD_fld_ae_sem_multiply_q1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_immed.N", FIELD_fld_ae_sem_dr_to_dr_immed_N, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_ar_ei", FIELD_fld_ae_sem_dr_to_ar_ei, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_dr_to_ar_eo", FIELD_fld_ae_sem_dr_to_ar_eo, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_multiply_acc_ep", FIELD_fld_ae_sem_multiply_acc_ep, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_arithmetic_e", FIELD_fld_ae_sem_arithmetic_e, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_arithmetic_ep", FIELD_fld_ae_sem_arithmetic_ep, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_arithmetic_ep1", FIELD_fld_ae_sem_arithmetic_ep1, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_select_ss", FIELD_fld_ae_sem_select_ss, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_select_vr", FIELD_fld_ae_sem_select_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_select_vs", FIELD_fld_ae_sem_select_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_select_vt", FIELD_fld_ae_sem_select_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_select_vu", FIELD_fld_ae_sem_select_vu, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_select_isel", FIELD_fld_ae_sem_select_isel, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_encode, OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_e", FIELD_fld_ae_sem_shift_e, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_shift_i8", FIELD_fld_ae_sem_shift_i8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_shift_i8_encode, OperandSem_opnd_sem_opnd_ae_sem_shift_i8_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_multiply_d1", FIELD_fld_ae_sem_multiply_d1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_multiply_d3", FIELD_fld_ae_sem_multiply_d3, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_imm", FIELD_fld_ae_sem_dr_to_dr_imm, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_imm_encode, OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_imm_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_rng_d", FIELD_fld_ae_sem_rng_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_sb_loads_stores_iba2", FIELD_fld_ae_sem_sb_loads_stores_iba2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba2_encode, OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_ar_ar_s", FIELD_fld_ae_sem_dr_to_ar_ar_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_AE_ARDECNORM16_ar_u", FIELD_fld_AE_ARDECNORM16_ar_u, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_rng_a", FIELD_fld_ae_sem_rng_a, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_rng_art", FIELD_fld_ae_sem_rng_art, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_rng_i2", FIELD_fld_ae_sem_rng_i2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_rng_imm2", FIELD_fld_ae_sem_rng_imm2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_lb_db_ops_ar_u", FIELD_fld_ae_sem_lb_db_ops_ar_u, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_lb_db_ops_iba", FIELD_fld_ae_sem_lb_db_ops_iba, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_encode, OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_ar_vr", FIELD_fld_ae_sem_dr_to_ar_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spmisc_brt", FIELD_fld_ae_sem_spmisc_brt, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_spmisc_vr", FIELD_fld_ae_sem_spmisc_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spmisc_vs", FIELD_fld_ae_sem_spmisc_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_arr", FIELD_fld_ae_sem_dr_to_dr_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_dr_to_dr_bt", FIELD_fld_ae_sem_dr_to_dr_bt, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_sp32cvt_art", FIELD_fld_ae_sem_sp32cvt_art, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_sp32cvt_i_imm5", FIELD_fld_ae_sem_sp32cvt_i_imm5, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_encode, OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_sp32cvt_vr", FIELD_fld_ae_sem_sp32cvt_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_sp32cvt_vt", FIELD_fld_ae_sem_sp32cvt_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_sp32cvt_arr", FIELD_fld_ae_sem_sp32cvt_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_movfpstate_v", FIELD_fld_ae_sem_movfpstate_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_fpmov_vr", FIELD_fld_ae_sem_fpmov_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_fpmov_vt", FIELD_fld_ae_sem_fpmov_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_fpmov_i_imm4", FIELD_fld_ae_sem_fpmov_i_imm4, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_encode, OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_fpmov_vs", FIELD_fld_ae_sem_fpmov_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_fpmov_vu", FIELD_fld_ae_sem_fpmov_vu, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spmisc_vsM", FIELD_fld_ae_sem_spmisc_vsM, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spmisc_vtM", FIELD_fld_ae_sem_spmisc_vtM, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spmisc_vt", FIELD_fld_ae_sem_spmisc_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spaddsub_vr", FIELD_fld_ae_sem_spaddsub_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spaddsub_vs", FIELD_fld_ae_sem_spaddsub_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spaddsub_vt", FIELD_fld_ae_sem_spaddsub_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spaddsub_vu", FIELD_fld_ae_sem_spaddsub_vu, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vr", FIELD_fld_ae_sem_spfma_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vs", FIELD_fld_ae_sem_spfma_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vt", FIELD_fld_ae_sem_spfma_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vp", FIELD_fld_ae_sem_spfma_vp, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_i_imm1", FIELD_fld_ae_sem_spfma_i_imm1, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm1_encode, OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm1_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_spfma_i_imm3", FIELD_fld_ae_sem_spfma_i_imm3, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_encode, OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_spaddsub_vp", FIELD_fld_ae_sem_spaddsub_vp, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spaddsub_vq", FIELD_fld_ae_sem_spaddsub_vq, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vu", FIELD_fld_ae_sem_spfma_vu, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vq", FIELD_fld_ae_sem_spfma_vq, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hprminmaxnum_vr", FIELD_fld_ae_sem_hprminmaxnum_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hprminmaxnum_vt", FIELD_fld_ae_sem_hprminmaxnum_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcmp_br4t", FIELD_fld_ae_sem_hpcmp_br4t, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_hpcmp_vr", FIELD_fld_ae_sem_hpcmp_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcmp_vs", FIELD_fld_ae_sem_hpcmp_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcnv_art", FIELD_fld_ae_sem_hpcnv_art, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_hpcnv_i_imm4", FIELD_fld_ae_sem_hpcnv_i_imm4, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_encode, OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_hpcnv_vr", FIELD_fld_ae_sem_hpcnv_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcnv_arr", FIELD_fld_ae_sem_hpcnv_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_hpcnv_vt", FIELD_fld_ae_sem_hpcnv_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcmp_vt", FIELD_fld_ae_sem_hpcmp_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcnv_vs", FIELD_fld_ae_sem_hpcnv_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vr", FIELD_fld_ae_sem_hpfma_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vs", FIELD_fld_ae_sem_hpfma_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vt", FIELD_fld_ae_sem_hpfma_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vp", FIELD_fld_ae_sem_hpfma_vp, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vu", FIELD_fld_ae_sem_hpfma_vu, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vq", FIELD_fld_ae_sem_hpfma_vq, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_c0", FIELD_fld_ae_sem_mul_nn_c0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_c1", FIELD_fld_ae_sem_mul_nn_c1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_c2", FIELD_fld_ae_sem_mul_nn_c2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_c3", FIELD_fld_ae_sem_mul_nn_c3, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_q0", FIELD_fld_ae_sem_mul_nn_q0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_q1", FIELD_fld_ae_sem_mul_nn_q1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_v0", FIELD_fld_ae_sem_mul_nn_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_v1", FIELD_fld_ae_sem_mul_nn_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_q2", FIELD_fld_ae_sem_mul_nn_q2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_q3", FIELD_fld_ae_sem_mul_nn_q3, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_v2", FIELD_fld_ae_sem_mul_nn_v2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_v3", FIELD_fld_ae_sem_mul_nn_v3, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "bitindex", FIELD_bitindex, -1, 0, + 0, + OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode, + 0, 0, + -1, 0 }, + { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 }, + { "imms8", FIELD_imms8, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, + { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, + { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, + { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, + { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, + { "r_disp", FIELD_r_disp, -1, 0, 0, 0, 0, 0, 0 }, + { "r_3", FIELD_r_3, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, + { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, + { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, + { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, + { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 }, + { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 }, + { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 }, + { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 }, + { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 }, + { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 }, + { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 }, + { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_Inst16b_12", FIELD_ae_fld_Inst16b_12, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_Inst16b_15_13", FIELD_ae_fld_Inst16b_15_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_art", FIELD_fld_ae_sem_arithmetic_art, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_ds", FIELD_fld_ae_sem_arithmetic_ds, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_v", FIELD_fld_ae_sem_arithmetic_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_v0", FIELD_fld_ae_sem_arithmetic_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_v1", FIELD_fld_ae_sem_arithmetic_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_va", FIELD_fld_ae_sem_arithmetic_va, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_vs", FIELD_fld_ae_sem_arithmetic_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_a", FIELD_fld_ae_sem_dr_to_ar_a, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_ab", FIELD_fld_ae_sem_dr_to_ar_ab, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_ai", FIELD_fld_ae_sem_dr_to_ar_ai, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_aoe", FIELD_fld_ae_sem_dr_to_ar_aoe, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_d", FIELD_fld_ae_sem_dr_to_ar_d, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_d0", FIELD_fld_ae_sem_dr_to_ar_d0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_d1", FIELD_fld_ae_sem_dr_to_ar_d1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_imm8", FIELD_fld_ae_sem_dr_to_ar_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_v0", FIELD_fld_ae_sem_dr_to_ar_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_vr", FIELD_fld_ae_sem_dr_to_ar_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_arr", FIELD_fld_ae_sem_dr_to_dr_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_bt", FIELD_fld_ae_sem_dr_to_dr_bt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_ds", FIELD_fld_ae_sem_dr_to_dr_ds, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_imm2", FIELD_fld_ae_sem_dr_to_dr_imm2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_immed", FIELD_fld_ae_sem_dr_to_dr_immed, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_movi_imm", FIELD_fld_ae_sem_dr_to_dr_movi_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_v", FIELD_fld_ae_sem_dr_to_dr_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_v0", FIELD_fld_ae_sem_dr_to_dr_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_v1", FIELD_fld_ae_sem_dr_to_dr_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcmp_br4t", FIELD_fld_ae_sem_hpcmp_br4t, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcmp_vr", FIELD_fld_ae_sem_hpcmp_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcmp_vs", FIELD_fld_ae_sem_hpcmp_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_arr", FIELD_fld_ae_sem_hpcnv_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_art", FIELD_fld_ae_sem_hpcnv_art, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_i_imm4", FIELD_fld_ae_sem_hpcnv_i_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_vr", FIELD_fld_ae_sem_hpcnv_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_vt", FIELD_fld_ae_sem_hpcnv_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hprminmaxnum_vr", FIELD_fld_ae_sem_hprminmaxnum_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hprminmaxnum_vt", FIELD_fld_ae_sem_hprminmaxnum_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_lb_ops_iba", FIELD_fld_ae_sem_lb_ops_iba, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_a", FIELD_fld_ae_sem_loads_stores_a, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_a.0", FIELD_fld_ae_sem_loads_stores_a_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_av", FIELD_fld_ae_sem_loads_stores_av, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_av1", FIELD_fld_ae_sem_loads_stores_av1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_end", FIELD_fld_ae_sem_loads_stores_end, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i128", FIELD_fld_ae_sem_loads_stores_i128, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i16", FIELD_fld_ae_sem_loads_stores_i16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i3", FIELD_fld_ae_sem_loads_stores_i3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i32", FIELD_fld_ae_sem_loads_stores_i32, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i32pos", FIELD_fld_ae_sem_loads_stores_i32pos, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i64", FIELD_fld_ae_sem_loads_stores_i64, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i64half", FIELD_fld_ae_sem_loads_stores_i64half, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i64neg", FIELD_fld_ae_sem_loads_stores_i64neg, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i64pos", FIELD_fld_ae_sem_loads_stores_i64pos, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i64x2", FIELD_fld_ae_sem_loads_stores_i64x2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i8", FIELD_fld_ae_sem_loads_stores_i8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_imm2", FIELD_fld_ae_sem_loads_stores_imm2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_su", FIELD_fld_ae_sem_loads_stores_su, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_uu", FIELD_fld_ae_sem_loads_stores_uu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_v", FIELD_fld_ae_sem_loads_stores_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_v1", FIELD_fld_ae_sem_loads_stores_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_vu", FIELD_fld_ae_sem_loads_stores_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_x", FIELD_fld_ae_sem_loads_stores_x, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_pks_d", FIELD_fld_ae_sem_pks_d, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_pks_pos", FIELD_fld_ae_sem_pks_pos, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_pks_s", FIELD_fld_ae_sem_pks_s, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_v0", FIELD_fld_ae_sem_rng_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_v1", FIELD_fld_ae_sem_rng_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sb_loads_stores_iba", FIELD_fld_ae_sem_sb_loads_stores_iba, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_a", FIELD_fld_ae_sem_shift_a, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_a0", FIELD_fld_ae_sem_shift_a0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_d", FIELD_fld_ae_sem_shift_d, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_d0", FIELD_fld_ae_sem_shift_d0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_d1", FIELD_fld_ae_sem_shift_d1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_da", FIELD_fld_ae_sem_shift_da, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_i16", FIELD_fld_ae_sem_shift_i16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_i32", FIELD_fld_ae_sem_shift_i32, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_i64", FIELD_fld_ae_sem_shift_i64, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_imm32", FIELD_fld_ae_sem_shift_imm32, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_imm8", FIELD_fld_ae_sem_shift_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_sd", FIELD_fld_ae_sem_shift_sd, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sp32cvt_arr", FIELD_fld_ae_sem_sp32cvt_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sp32cvt_art", FIELD_fld_ae_sem_sp32cvt_art, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sp32cvt_i_imm5", FIELD_fld_ae_sem_sp32cvt_i_imm5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sp32cvt_vr", FIELD_fld_ae_sem_sp32cvt_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sp32cvt_vt", FIELD_fld_ae_sem_sp32cvt_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_brt", FIELD_fld_ae_sem_spmisc_brt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_vr", FIELD_fld_ae_sem_spmisc_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_vs", FIELD_fld_ae_sem_spmisc_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_10", FIELD_fld_ae_slot0_11_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_11", FIELD_fld_ae_slot0_11_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_8", FIELD_fld_ae_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_9", FIELD_fld_ae_slot0_11_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_0", FIELD_fld_ae_slot0_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_10", FIELD_fld_ae_slot0_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_12", FIELD_fld_ae_slot0_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_2", FIELD_fld_ae_slot0_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_6", FIELD_fld_ae_slot0_12_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_8", FIELD_fld_ae_slot0_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_9", FIELD_fld_ae_slot0_12_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_14_12", FIELD_fld_ae_slot0_14_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_14_13", FIELD_fld_ae_slot0_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_10", FIELD_fld_ae_slot0_17_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_12", FIELD_fld_ae_slot0_17_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_13", FIELD_fld_ae_slot0_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_14", FIELD_fld_ae_slot0_17_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_15", FIELD_fld_ae_slot0_17_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_16", FIELD_fld_ae_slot0_17_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_17", FIELD_fld_ae_slot0_17_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_8", FIELD_fld_ae_slot0_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_18_13", FIELD_fld_ae_slot0_18_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_18_15", FIELD_fld_ae_slot0_18_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_18_16", FIELD_fld_ae_slot0_18_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_18_8", FIELD_fld_ae_slot0_18_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_19_12", FIELD_fld_ae_slot0_19_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_19_15", FIELD_fld_ae_slot0_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_19_19", FIELD_fld_ae_slot0_19_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_19_8", FIELD_fld_ae_slot0_19_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_1_0", FIELD_fld_ae_slot0_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_1_1", FIELD_fld_ae_slot0_1_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_16", FIELD_fld_ae_slot0_20_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_20", FIELD_fld_ae_slot0_20_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_23_15", FIELD_fld_ae_slot0_23_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_23_17", FIELD_fld_ae_slot0_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_23_19", FIELD_fld_ae_slot0_23_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_23_22", FIELD_fld_ae_slot0_23_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_10", FIELD_fld_ae_slot0_28_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_12", FIELD_fld_ae_slot0_28_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_14", FIELD_fld_ae_slot0_28_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_15", FIELD_fld_ae_slot0_28_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_16", FIELD_fld_ae_slot0_28_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_17", FIELD_fld_ae_slot0_28_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_19", FIELD_fld_ae_slot0_28_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_21", FIELD_fld_ae_slot0_28_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_22", FIELD_fld_ae_slot0_28_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_24", FIELD_fld_ae_slot0_28_24, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_26", FIELD_fld_ae_slot0_28_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_27", FIELD_fld_ae_slot0_28_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_4", FIELD_fld_ae_slot0_28_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_8", FIELD_fld_ae_slot0_28_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_3_0", FIELD_fld_ae_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_3_1", FIELD_fld_ae_slot0_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_3_2", FIELD_fld_ae_slot0_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_3_3", FIELD_fld_ae_slot0_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_4_0", FIELD_fld_ae_slot0_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_4_4", FIELD_fld_ae_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_5_0", FIELD_fld_ae_slot0_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_5_4", FIELD_fld_ae_slot0_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_0", FIELD_fld_ae_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_2", FIELD_fld_ae_slot0_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_3", FIELD_fld_ae_slot0_7_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_4", FIELD_fld_ae_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_8_8", FIELD_fld_ae_slot0_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_9_4", FIELD_fld_ae_slot0_9_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_9_8", FIELD_fld_ae_slot0_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_9_9", FIELD_fld_ae_slot0_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_0_0", FIELD_fld_ae_slot1_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_12_8", FIELD_fld_ae_slot1_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_17_13", FIELD_fld_ae_slot1_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_17_17", FIELD_fld_ae_slot1_17_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_17_8", FIELD_fld_ae_slot1_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_1", FIELD_fld_ae_slot1_25_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_12", FIELD_fld_ae_slot1_25_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_13", FIELD_fld_ae_slot1_25_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_16", FIELD_fld_ae_slot1_25_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_17", FIELD_fld_ae_slot1_25_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_18", FIELD_fld_ae_slot1_25_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_20", FIELD_fld_ae_slot1_25_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_22", FIELD_fld_ae_slot1_25_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_23", FIELD_fld_ae_slot1_25_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_8", FIELD_fld_ae_slot1_25_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_9", FIELD_fld_ae_slot1_25_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_3_0", FIELD_fld_ae_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_3_2", FIELD_fld_ae_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_3_3", FIELD_fld_ae_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_7_4", FIELD_fld_ae_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_e", FIELD_fld_ae_sem_arithmetic_e, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_ep", FIELD_fld_ae_sem_arithmetic_ep, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_ep1", FIELD_fld_ae_sem_arithmetic_ep1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_ei", FIELD_fld_ae_sem_dr_to_ar_ei, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_eo", FIELD_fld_ae_sem_dr_to_ar_eo, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_immed.N", FIELD_fld_ae_sem_dr_to_dr_immed_N, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_fpmov_i_imm4", FIELD_fld_ae_sem_fpmov_i_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_fpmov_vr", FIELD_fld_ae_sem_fpmov_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_fpmov_vs", FIELD_fld_ae_sem_fpmov_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_fpmov_vt", FIELD_fld_ae_sem_fpmov_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_fpmov_vu", FIELD_fld_ae_sem_fpmov_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcmp_vt", FIELD_fld_ae_sem_hpcmp_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_vs", FIELD_fld_ae_sem_hpcnv_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vr", FIELD_fld_ae_sem_hpfma_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vs", FIELD_fld_ae_sem_hpfma_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vt", FIELD_fld_ae_sem_hpfma_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_movfpstate_v", FIELD_fld_ae_sem_movfpstate_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_acc_ep", FIELD_fld_ae_sem_multiply_acc_ep, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_d0", FIELD_fld_ae_sem_multiply_d0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_d2", FIELD_fld_ae_sem_multiply_d2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_q0", FIELD_fld_ae_sem_multiply_q0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_q1", FIELD_fld_ae_sem_multiply_q1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_reduction_sort_ds", FIELD_fld_ae_sem_reduction_sort_ds, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_reduction_sort_v", FIELD_fld_ae_sem_reduction_sort_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_reduction_sort_v0", FIELD_fld_ae_sem_reduction_sort_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_isel", FIELD_fld_ae_sem_select_isel, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_ss", FIELD_fld_ae_sem_select_ss, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_vr", FIELD_fld_ae_sem_select_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_vs", FIELD_fld_ae_sem_select_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_vt", FIELD_fld_ae_sem_select_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_vu", FIELD_fld_ae_sem_select_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vr", FIELD_fld_ae_sem_spaddsub_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vs", FIELD_fld_ae_sem_spaddsub_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vt", FIELD_fld_ae_sem_spaddsub_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vu", FIELD_fld_ae_sem_spaddsub_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_i_imm1", FIELD_fld_ae_sem_spfma_i_imm1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_i_imm3", FIELD_fld_ae_sem_spfma_i_imm3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vp", FIELD_fld_ae_sem_spfma_vp, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vr", FIELD_fld_ae_sem_spfma_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vs", FIELD_fld_ae_sem_spfma_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vt", FIELD_fld_ae_sem_spfma_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_vsM", FIELD_fld_ae_sem_spmisc_vsM, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_vt", FIELD_fld_ae_sem_spmisc_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_vtM", FIELD_fld_ae_sem_spmisc_vtM, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_14_0", FIELD_fld_ae_slot2_14_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_14_10", FIELD_fld_ae_slot2_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_14_14", FIELD_fld_ae_slot2_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_14_5", FIELD_fld_ae_slot2_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_16_15", FIELD_fld_ae_slot2_16_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_19_15", FIELD_fld_ae_slot2_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_15", FIELD_fld_ae_slot2_28_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_17", FIELD_fld_ae_slot2_28_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_19", FIELD_fld_ae_slot2_28_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_20", FIELD_fld_ae_slot2_28_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_25", FIELD_fld_ae_slot2_28_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_4", FIELD_fld_ae_slot2_28_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_5", FIELD_fld_ae_slot2_28_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_3_0", FIELD_fld_ae_slot2_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_0", FIELD_fld_ae_slot2_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_1", FIELD_fld_ae_slot2_9_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_2", FIELD_fld_ae_slot2_9_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_5", FIELD_fld_ae_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_6", FIELD_fld_ae_slot2_9_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_7", FIELD_fld_ae_slot2_9_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_8", FIELD_fld_ae_slot2_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_imm", FIELD_fld_ae_sem_dr_to_dr_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_d1", FIELD_fld_ae_sem_multiply_d1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_d3", FIELD_fld_ae_sem_multiply_d3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_d", FIELD_fld_ae_sem_rng_d, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_e", FIELD_fld_ae_sem_shift_e, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_i8", FIELD_fld_ae_sem_shift_i8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_11_0", FIELD_fld_ae_slot3_11_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_14_0", FIELD_fld_ae_slot3_14_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_14_10", FIELD_fld_ae_slot3_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_14_12", FIELD_fld_ae_slot3_14_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_14_13", FIELD_fld_ae_slot3_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_16_13", FIELD_fld_ae_slot3_16_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_0", FIELD_fld_ae_slot3_19_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_10", FIELD_fld_ae_slot3_19_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_15", FIELD_fld_ae_slot3_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_17", FIELD_fld_ae_slot3_19_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_18", FIELD_fld_ae_slot3_19_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_19", FIELD_fld_ae_slot3_19_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_24_10", FIELD_fld_ae_slot3_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_24_19", FIELD_fld_ae_slot3_24_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_24_20", FIELD_fld_ae_slot3_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_12", FIELD_fld_ae_slot3_36_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_16", FIELD_fld_ae_slot3_36_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_19", FIELD_fld_ae_slot3_36_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_20", FIELD_fld_ae_slot3_36_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_22", FIELD_fld_ae_slot3_36_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_25", FIELD_fld_ae_slot3_36_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_30", FIELD_fld_ae_slot3_36_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_4_0", FIELD_fld_ae_slot3_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_9_0", FIELD_fld_ae_slot3_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_9_1", FIELD_fld_ae_slot3_9_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_9_3", FIELD_fld_ae_slot3_9_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_9_5", FIELD_fld_ae_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_0_0", FIELD_fld_ae2_slot0_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_11_4", FIELD_fld_ae2_slot0_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_11_8", FIELD_fld_ae2_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_11_9", FIELD_fld_ae2_slot0_11_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_12_0", FIELD_fld_ae2_slot0_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_12_2", FIELD_fld_ae2_slot0_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_12_4", FIELD_fld_ae2_slot0_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_12_8", FIELD_fld_ae2_slot0_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_14_13", FIELD_fld_ae2_slot0_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_14_8", FIELD_fld_ae2_slot0_14_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_0", FIELD_fld_ae2_slot0_15_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_12", FIELD_fld_ae2_slot0_15_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_13", FIELD_fld_ae2_slot0_15_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_15", FIELD_fld_ae2_slot0_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_4", FIELD_fld_ae2_slot0_15_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_8", FIELD_fld_ae2_slot0_15_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_17_13", FIELD_fld_ae2_slot0_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_17_17", FIELD_fld_ae2_slot0_17_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_18_15", FIELD_fld_ae2_slot0_18_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_18_17", FIELD_fld_ae2_slot0_18_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_18_18", FIELD_fld_ae2_slot0_18_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_1_0", FIELD_fld_ae2_slot0_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_23_18", FIELD_fld_ae2_slot0_23_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_23_19", FIELD_fld_ae2_slot0_23_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_3_0", FIELD_fld_ae2_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_16", FIELD_fld_ae2_slot0_40_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_17", FIELD_fld_ae2_slot0_40_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_18", FIELD_fld_ae2_slot0_40_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_19", FIELD_fld_ae2_slot0_40_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_21", FIELD_fld_ae2_slot0_40_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_23", FIELD_fld_ae2_slot0_40_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_24", FIELD_fld_ae2_slot0_40_24, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_25", FIELD_fld_ae2_slot0_40_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_26", FIELD_fld_ae2_slot0_40_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_27", FIELD_fld_ae2_slot0_40_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_0", FIELD_fld_ae2_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_4", FIELD_fld_ae2_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_6", FIELD_fld_ae2_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_7", FIELD_fld_ae2_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_8_8", FIELD_fld_ae2_slot0_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_9_8", FIELD_fld_ae2_slot0_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_0_0", FIELD_fld_ae2_slot1_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_11_0", FIELD_fld_ae2_slot1_11_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_11_10", FIELD_fld_ae2_slot1_11_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_11_8", FIELD_fld_ae2_slot1_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_14_10", FIELD_fld_ae2_slot1_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_14_11", FIELD_fld_ae2_slot1_14_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_14_12", FIELD_fld_ae2_slot1_14_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_14_14", FIELD_fld_ae2_slot1_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_14_8", FIELD_fld_ae2_slot1_14_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_12", FIELD_fld_ae2_slot1_36_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_14", FIELD_fld_ae2_slot1_36_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_15", FIELD_fld_ae2_slot1_36_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_16", FIELD_fld_ae2_slot1_36_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_17", FIELD_fld_ae2_slot1_36_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_18", FIELD_fld_ae2_slot1_36_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_20", FIELD_fld_ae2_slot1_36_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_22", FIELD_fld_ae2_slot1_36_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_23", FIELD_fld_ae2_slot1_36_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_3_0", FIELD_fld_ae2_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_3_1", FIELD_fld_ae2_slot1_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_3_2", FIELD_fld_ae2_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_3_3", FIELD_fld_ae2_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_7_4", FIELD_fld_ae2_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_9_8", FIELD_fld_ae2_slot1_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_9_9", FIELD_fld_ae2_slot1_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_14_10", FIELD_fld_ae2_slot2_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_17_0", FIELD_fld_ae2_slot2_17_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_17_10", FIELD_fld_ae2_slot2_17_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_17_15", FIELD_fld_ae2_slot2_17_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_17_17", FIELD_fld_ae2_slot2_17_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_19_10", FIELD_fld_ae2_slot2_19_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_19_15", FIELD_fld_ae2_slot2_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_19_18", FIELD_fld_ae2_slot2_19_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_19_9", FIELD_fld_ae2_slot2_19_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_10", FIELD_fld_ae2_slot2_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_15", FIELD_fld_ae2_slot2_24_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_20", FIELD_fld_ae2_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_5", FIELD_fld_ae2_slot2_24_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_9", FIELD_fld_ae2_slot2_24_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_18", FIELD_fld_ae2_slot2_42_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_20", FIELD_fld_ae2_slot2_42_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_25", FIELD_fld_ae2_slot2_42_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_26", FIELD_fld_ae2_slot2_42_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_28", FIELD_fld_ae2_slot2_42_28, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_30", FIELD_fld_ae2_slot2_42_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_4_0", FIELD_fld_ae2_slot2_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_9_5", FIELD_fld_ae2_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vp", FIELD_fld_ae_sem_spaddsub_vp, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vq", FIELD_fld_ae_sem_spaddsub_vq, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_11_11", FIELD_fld_ae3_slot0_11_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_11_4", FIELD_fld_ae3_slot0_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_11_8", FIELD_fld_ae3_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_12_12", FIELD_fld_ae3_slot0_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_12_8", FIELD_fld_ae3_slot0_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_13_13", FIELD_fld_ae3_slot0_13_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_13_8", FIELD_fld_ae3_slot0_13_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_1_0", FIELD_fld_ae3_slot0_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_11", FIELD_fld_ae3_slot0_32_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_12", FIELD_fld_ae3_slot0_32_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_13", FIELD_fld_ae3_slot0_32_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_14", FIELD_fld_ae3_slot0_32_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_15", FIELD_fld_ae3_slot0_32_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_16", FIELD_fld_ae3_slot0_32_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_17", FIELD_fld_ae3_slot0_32_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_18", FIELD_fld_ae3_slot0_32_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_20", FIELD_fld_ae3_slot0_32_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_27", FIELD_fld_ae3_slot0_32_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_8", FIELD_fld_ae3_slot0_32_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_3_0", FIELD_fld_ae3_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_3_2", FIELD_fld_ae3_slot0_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_3_3", FIELD_fld_ae3_slot0_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_4_0", FIELD_fld_ae3_slot0_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_4_4", FIELD_fld_ae3_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_5_0", FIELD_fld_ae3_slot0_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_5_4", FIELD_fld_ae3_slot0_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_7_0", FIELD_fld_ae3_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_7_2", FIELD_fld_ae3_slot0_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_7_4", FIELD_fld_ae3_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_7_6", FIELD_fld_ae3_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_8_8", FIELD_fld_ae3_slot0_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_9_4", FIELD_fld_ae3_slot0_9_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_9_8", FIELD_fld_ae3_slot0_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_ar_s", FIELD_fld_ae_sem_dr_to_ar_ar_s, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sb_loads_stores_iba2", FIELD_fld_ae_sem_sb_loads_stores_iba2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_0", FIELD_fld_ae3_slot1_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_11", FIELD_fld_ae3_slot1_23_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_12", FIELD_fld_ae3_slot1_23_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_13", FIELD_fld_ae3_slot1_23_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_15", FIELD_fld_ae3_slot1_23_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_16", FIELD_fld_ae3_slot1_23_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_17", FIELD_fld_ae3_slot1_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_19", FIELD_fld_ae3_slot1_23_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_6", FIELD_fld_ae3_slot1_23_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_8", FIELD_fld_ae3_slot1_23_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_9", FIELD_fld_ae3_slot1_23_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_3_0", FIELD_fld_ae3_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_3_1", FIELD_fld_ae3_slot1_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_3_2", FIELD_fld_ae3_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_3_3", FIELD_fld_ae3_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_7_4", FIELD_fld_ae3_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_9_8", FIELD_fld_ae3_slot1_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_AE_ARDECNORM16_ar_u", FIELD_fld_AE_ARDECNORM16_ar_u, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_11_10", FIELD_fld_ae5_slot0_11_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_11_4", FIELD_fld_ae5_slot0_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_11_8", FIELD_fld_ae5_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_11_9", FIELD_fld_ae5_slot0_11_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_12_10", FIELD_fld_ae5_slot0_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_12_4", FIELD_fld_ae5_slot0_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_12_6", FIELD_fld_ae5_slot0_12_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_12_8", FIELD_fld_ae5_slot0_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_12_9", FIELD_fld_ae5_slot0_12_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_1_0", FIELD_fld_ae5_slot0_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_1_1", FIELD_fld_ae5_slot0_1_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_12", FIELD_fld_ae5_slot0_29_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_13", FIELD_fld_ae5_slot0_29_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_15", FIELD_fld_ae5_slot0_29_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_16", FIELD_fld_ae5_slot0_29_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_17", FIELD_fld_ae5_slot0_29_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_18", FIELD_fld_ae5_slot0_29_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_19", FIELD_fld_ae5_slot0_29_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_20", FIELD_fld_ae5_slot0_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_27", FIELD_fld_ae5_slot0_29_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_5", FIELD_fld_ae5_slot0_29_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_6", FIELD_fld_ae5_slot0_29_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_8", FIELD_fld_ae5_slot0_29_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_2_0", FIELD_fld_ae5_slot0_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_3_0", FIELD_fld_ae5_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_3_2", FIELD_fld_ae5_slot0_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_4_0", FIELD_fld_ae5_slot0_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_4_4", FIELD_fld_ae5_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_7_0", FIELD_fld_ae5_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_7_4", FIELD_fld_ae5_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_7_7", FIELD_fld_ae5_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_8_8", FIELD_fld_ae5_slot0_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_lb_db_ops_ar_u", FIELD_fld_ae_sem_lb_db_ops_ar_u, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_lb_db_ops_iba", FIELD_fld_ae_sem_lb_db_ops_iba, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_a", FIELD_fld_ae_sem_rng_a, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_art", FIELD_fld_ae_sem_rng_art, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_i2", FIELD_fld_ae_sem_rng_i2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_imm2", FIELD_fld_ae_sem_rng_imm2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot1_1_0", FIELD_fld_ae5_slot1_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_14_10", FIELD_fld_ae5_slot2_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_14_14", FIELD_fld_ae5_slot2_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_14_5", FIELD_fld_ae5_slot2_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_24_0", FIELD_fld_ae5_slot2_24_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_24_15", FIELD_fld_ae5_slot2_24_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_24_17", FIELD_fld_ae5_slot2_24_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_24_20", FIELD_fld_ae5_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_4_0", FIELD_fld_ae5_slot2_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_9_0", FIELD_fld_ae5_slot2_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_9_5", FIELD_fld_ae5_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_9_7", FIELD_fld_ae5_slot2_9_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_10_10", FIELD_fld_ae6_slot0_10_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_15_15", FIELD_fld_ae6_slot0_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_10", FIELD_fld_ae6_slot0_29_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_13", FIELD_fld_ae6_slot0_29_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_14", FIELD_fld_ae6_slot0_29_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_15", FIELD_fld_ae6_slot0_29_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_18", FIELD_fld_ae6_slot0_29_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_20", FIELD_fld_ae6_slot0_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_5", FIELD_fld_ae6_slot0_29_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_4_0", FIELD_fld_ae6_slot0_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_4_4", FIELD_fld_ae6_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_7_4", FIELD_fld_ae6_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_7_7", FIELD_fld_ae6_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_9_8", FIELD_fld_ae6_slot0_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_9_9", FIELD_fld_ae6_slot0_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_14_14", FIELD_fld_ae6_slot1_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_12", FIELD_fld_ae6_slot1_27_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_15", FIELD_fld_ae6_slot1_27_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_20", FIELD_fld_ae6_slot1_27_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_21", FIELD_fld_ae6_slot1_27_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_3", FIELD_fld_ae6_slot1_27_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_6", FIELD_fld_ae6_slot1_27_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_2_0", FIELD_fld_ae6_slot1_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_9_5", FIELD_fld_ae6_slot1_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_9_6", FIELD_fld_ae6_slot1_9_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_9_7", FIELD_fld_ae6_slot1_9_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_9_8", FIELD_fld_ae6_slot1_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_9_9", FIELD_fld_ae6_slot1_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_10_10", FIELD_fld_ae6_slot2_10_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_11_10", FIELD_fld_ae6_slot2_11_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_24_0", FIELD_fld_ae6_slot2_24_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_24_10", FIELD_fld_ae6_slot2_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_24_14", FIELD_fld_ae6_slot2_24_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_24_15", FIELD_fld_ae6_slot2_24_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_24_20", FIELD_fld_ae6_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_4_2", FIELD_fld_ae6_slot2_4_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_9_5", FIELD_fld_ae6_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_10_10", FIELD_fld_ae6_slot3_10_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_12_0", FIELD_fld_ae6_slot3_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_14_0", FIELD_fld_ae6_slot3_14_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_14_10", FIELD_fld_ae6_slot3_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_14_13", FIELD_fld_ae6_slot3_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_14_5", FIELD_fld_ae6_slot3_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_24_20", FIELD_fld_ae6_slot3_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_37_13", FIELD_fld_ae6_slot3_37_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_37_15", FIELD_fld_ae6_slot3_37_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_37_20", FIELD_fld_ae6_slot3_37_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_37_30", FIELD_fld_ae6_slot3_37_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_9_5", FIELD_fld_ae6_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_12_6", FIELD_fld_ae7_slot0_12_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_23_0", FIELD_fld_ae7_slot0_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_23_13", FIELD_fld_ae7_slot0_23_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_23_17", FIELD_fld_ae7_slot0_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_23_18", FIELD_fld_ae7_slot0_23_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_23_6", FIELD_fld_ae7_slot0_23_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_7_4", FIELD_fld_ae7_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_7_6", FIELD_fld_ae7_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_7_7", FIELD_fld_ae7_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_12_6", FIELD_fld_ae7_slot1_12_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_23_0", FIELD_fld_ae7_slot1_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_23_13", FIELD_fld_ae7_slot1_23_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_23_17", FIELD_fld_ae7_slot1_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_23_18", FIELD_fld_ae7_slot1_23_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_23_6", FIELD_fld_ae7_slot1_23_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_7_4", FIELD_fld_ae7_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_7_6", FIELD_fld_ae7_slot1_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_7_7", FIELD_fld_ae7_slot1_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_11_0", FIELD_fld_ae7_slot2_11_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_14_10", FIELD_fld_ae7_slot2_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_14_5", FIELD_fld_ae7_slot2_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_36_12", FIELD_fld_ae7_slot2_36_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_36_15", FIELD_fld_ae7_slot2_36_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_36_20", FIELD_fld_ae7_slot2_36_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_36_25", FIELD_fld_ae7_slot2_36_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_36_30", FIELD_fld_ae7_slot2_36_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_9_5", FIELD_fld_ae7_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_10_0", FIELD_fld_ae7_slot3_10_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_14_10", FIELD_fld_ae7_slot3_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_14_5", FIELD_fld_ae7_slot3_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_24_10", FIELD_fld_ae7_slot3_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_35_11", FIELD_fld_ae7_slot3_35_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_35_20", FIELD_fld_ae7_slot3_35_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_35_25", FIELD_fld_ae7_slot3_35_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_35_30", FIELD_fld_ae7_slot3_35_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_4_0", FIELD_fld_ae7_slot3_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_9_5", FIELD_fld_ae7_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_13_12", FIELD_fld_ae8_slot0_13_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_13_13", FIELD_fld_ae8_slot0_13_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_13_4", FIELD_fld_ae8_slot0_13_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_13_9", FIELD_fld_ae8_slot0_13_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_17_4", FIELD_fld_ae8_slot0_17_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_17_8", FIELD_fld_ae8_slot0_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_12", FIELD_fld_ae8_slot0_31_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_15", FIELD_fld_ae8_slot0_31_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_18", FIELD_fld_ae8_slot0_31_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_19", FIELD_fld_ae8_slot0_31_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_20", FIELD_fld_ae8_slot0_31_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_21", FIELD_fld_ae8_slot0_31_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_22", FIELD_fld_ae8_slot0_31_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_23", FIELD_fld_ae8_slot0_31_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_7", FIELD_fld_ae8_slot0_31_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_8", FIELD_fld_ae8_slot0_31_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_9", FIELD_fld_ae8_slot0_31_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_3_0", FIELD_fld_ae8_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_6_0", FIELD_fld_ae8_slot0_6_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_7_4", FIELD_fld_ae8_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_7_5", FIELD_fld_ae8_slot0_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_7_7", FIELD_fld_ae8_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_8_0", FIELD_fld_ae8_slot0_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_17_13", FIELD_fld_ae8_slot1_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_17_14", FIELD_fld_ae8_slot1_17_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_17_15", FIELD_fld_ae8_slot1_17_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_17_8", FIELD_fld_ae8_slot1_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_12", FIELD_fld_ae8_slot1_29_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_13", FIELD_fld_ae8_slot1_29_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_18", FIELD_fld_ae8_slot1_29_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_20", FIELD_fld_ae8_slot1_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_22", FIELD_fld_ae8_slot1_29_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_23", FIELD_fld_ae8_slot1_29_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_5", FIELD_fld_ae8_slot1_29_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_8", FIELD_fld_ae8_slot1_29_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_9", FIELD_fld_ae8_slot1_29_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_3_0", FIELD_fld_ae8_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_3_3", FIELD_fld_ae8_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_4_0", FIELD_fld_ae8_slot1_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_7_4", FIELD_fld_ae8_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_19_10", FIELD_fld_ae8_slot2_19_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_19_15", FIELD_fld_ae8_slot2_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_33_15", FIELD_fld_ae8_slot2_33_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_33_25", FIELD_fld_ae8_slot2_33_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_33_9", FIELD_fld_ae8_slot2_33_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_34_30", FIELD_fld_ae8_slot2_34_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_39_35", FIELD_fld_ae8_slot2_39_35, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_44_35", FIELD_fld_ae8_slot2_44_35, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_58_34", FIELD_fld_ae8_slot2_58_34, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_58_35", FIELD_fld_ae8_slot2_58_35, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_58_40", FIELD_fld_ae8_slot2_58_40, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_58_50", FIELD_fld_ae8_slot2_58_50, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_8_0", FIELD_fld_ae8_slot2_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_9_0", FIELD_fld_ae8_slot2_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_c0", FIELD_fld_ae_sem_mul_nn_c0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_c1", FIELD_fld_ae_sem_mul_nn_c1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_c2", FIELD_fld_ae_sem_mul_nn_c2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_c3", FIELD_fld_ae_sem_mul_nn_c3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_q0", FIELD_fld_ae_sem_mul_nn_q0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_q1", FIELD_fld_ae_sem_mul_nn_q1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_q2", FIELD_fld_ae_sem_mul_nn_q2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_q3", FIELD_fld_ae_sem_mul_nn_q3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_v0", FIELD_fld_ae_sem_mul_nn_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_v1", FIELD_fld_ae_sem_mul_nn_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_v2", FIELD_fld_ae_sem_mul_nn_v2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_v3", FIELD_fld_ae_sem_mul_nn_v3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_0_0", FIELD_fld_ae9_slot0_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_12_12", FIELD_fld_ae9_slot0_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_12_5", FIELD_fld_ae9_slot0_12_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_12_8", FIELD_fld_ae9_slot0_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_17_13", FIELD_fld_ae9_slot0_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_17_4", FIELD_fld_ae9_slot0_17_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_17_8", FIELD_fld_ae9_slot0_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_10", FIELD_fld_ae9_slot0_27_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_12", FIELD_fld_ae9_slot0_27_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_13", FIELD_fld_ae9_slot0_27_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_16", FIELD_fld_ae9_slot0_27_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_17", FIELD_fld_ae9_slot0_27_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_18", FIELD_fld_ae9_slot0_27_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_19", FIELD_fld_ae9_slot0_27_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_20", FIELD_fld_ae9_slot0_27_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_22", FIELD_fld_ae9_slot0_27_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_23", FIELD_fld_ae9_slot0_27_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_3", FIELD_fld_ae9_slot0_27_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_8", FIELD_fld_ae9_slot0_27_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_2_0", FIELD_fld_ae9_slot0_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_3_0", FIELD_fld_ae9_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_7_0", FIELD_fld_ae9_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_7_4", FIELD_fld_ae9_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_7_5", FIELD_fld_ae9_slot0_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_7_6", FIELD_fld_ae9_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_7_7", FIELD_fld_ae9_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_8_4", FIELD_fld_ae9_slot0_8_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_8_5", FIELD_fld_ae9_slot0_8_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_9_5", FIELD_fld_ae9_slot0_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_17_13", FIELD_fld_ae9_slot1_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_17_8", FIELD_fld_ae9_slot1_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_1_0", FIELD_fld_ae9_slot1_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_12", FIELD_fld_ae9_slot1_26_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_13", FIELD_fld_ae9_slot1_26_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_16", FIELD_fld_ae9_slot1_26_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_17", FIELD_fld_ae9_slot1_26_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_18", FIELD_fld_ae9_slot1_26_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_2", FIELD_fld_ae9_slot1_26_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_20", FIELD_fld_ae9_slot1_26_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_22", FIELD_fld_ae9_slot1_26_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_23", FIELD_fld_ae9_slot1_26_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_8", FIELD_fld_ae9_slot1_26_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_9", FIELD_fld_ae9_slot1_26_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_3_0", FIELD_fld_ae9_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_3_2", FIELD_fld_ae9_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_3_3", FIELD_fld_ae9_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_7_4", FIELD_fld_ae9_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_24_14", FIELD_fld_ae9_slot2_24_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_24_15", FIELD_fld_ae9_slot2_24_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_24_20", FIELD_fld_ae9_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_14", FIELD_fld_ae9_slot2_33_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_15", FIELD_fld_ae9_slot2_33_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_20", FIELD_fld_ae9_slot2_33_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_25", FIELD_fld_ae9_slot2_33_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_26", FIELD_fld_ae9_slot2_33_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_28", FIELD_fld_ae9_slot2_33_28, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_30", FIELD_fld_ae9_slot2_33_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_9", FIELD_fld_ae9_slot2_33_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_4_0", FIELD_fld_ae9_slot2_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_5_0", FIELD_fld_ae9_slot2_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_6_0", FIELD_fld_ae9_slot2_6_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_8_0", FIELD_fld_ae9_slot2_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_9_0", FIELD_fld_ae9_slot2_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_9_5", FIELD_fld_ae9_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_9_9", FIELD_fld_ae9_slot2_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vp", FIELD_fld_ae_sem_hpfma_vp, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vu", FIELD_fld_ae_sem_hpfma_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vu", FIELD_fld_ae_sem_spfma_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_19_15", FIELD_fld_ae9_slot3_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_24_20", FIELD_fld_ae9_slot3_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_14", FIELD_fld_ae9_slot3_31_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_15", FIELD_fld_ae9_slot3_31_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_20", FIELD_fld_ae9_slot3_31_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_25", FIELD_fld_ae9_slot3_31_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_26", FIELD_fld_ae9_slot3_31_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_28", FIELD_fld_ae9_slot3_31_28, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_7", FIELD_fld_ae9_slot3_31_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_4_0", FIELD_fld_ae9_slot3_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_4_3", FIELD_fld_ae9_slot3_4_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_4_4", FIELD_fld_ae9_slot3_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_6_0", FIELD_fld_ae9_slot3_6_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_9_0", FIELD_fld_ae9_slot3_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_9_5", FIELD_fld_ae9_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_17_13", FIELD_fld_ae10_slot0_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_17_4", FIELD_fld_ae10_slot0_17_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_17_8", FIELD_fld_ae10_slot0_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_0", FIELD_fld_ae10_slot0_24_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_10", FIELD_fld_ae10_slot0_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_12", FIELD_fld_ae10_slot0_24_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_13", FIELD_fld_ae10_slot0_24_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_16", FIELD_fld_ae10_slot0_24_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_17", FIELD_fld_ae10_slot0_24_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_18", FIELD_fld_ae10_slot0_24_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_20", FIELD_fld_ae10_slot0_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_8", FIELD_fld_ae10_slot0_24_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_3_0", FIELD_fld_ae10_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_7_4", FIELD_fld_ae10_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_7_6", FIELD_fld_ae10_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_7_7", FIELD_fld_ae10_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_8_4", FIELD_fld_ae10_slot0_8_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_0_0", FIELD_fld_ae10_slot1_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_17_13", FIELD_fld_ae10_slot1_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_17_8", FIELD_fld_ae10_slot1_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_1", FIELD_fld_ae10_slot1_25_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_12", FIELD_fld_ae10_slot1_25_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_13", FIELD_fld_ae10_slot1_25_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_16", FIELD_fld_ae10_slot1_25_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_17", FIELD_fld_ae10_slot1_25_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_18", FIELD_fld_ae10_slot1_25_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_20", FIELD_fld_ae10_slot1_25_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_22", FIELD_fld_ae10_slot1_25_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_23", FIELD_fld_ae10_slot1_25_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_8", FIELD_fld_ae10_slot1_25_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_9", FIELD_fld_ae10_slot1_25_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_3_0", FIELD_fld_ae10_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_3_2", FIELD_fld_ae10_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_3_3", FIELD_fld_ae10_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_7_4", FIELD_fld_ae10_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_24_20", FIELD_fld_ae10_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_29_20", FIELD_fld_ae10_slot2_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_29_25", FIELD_fld_ae10_slot2_29_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_10", FIELD_fld_ae10_slot2_34_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_14", FIELD_fld_ae10_slot2_34_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_15", FIELD_fld_ae10_slot2_34_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_20", FIELD_fld_ae10_slot2_34_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_25", FIELD_fld_ae10_slot2_34_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_30", FIELD_fld_ae10_slot2_34_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_31", FIELD_fld_ae10_slot2_34_31, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_33", FIELD_fld_ae10_slot2_34_33, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_4_0", FIELD_fld_ae10_slot2_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_9_0", FIELD_fld_ae10_slot2_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_9_5", FIELD_fld_ae10_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vq", FIELD_fld_ae_sem_hpfma_vq, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vq", FIELD_fld_ae_sem_spfma_vq, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_19_15", FIELD_fld_ae10_slot3_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_29_20", FIELD_fld_ae10_slot3_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_29_25", FIELD_fld_ae10_slot3_29_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_10", FIELD_fld_ae10_slot3_34_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_14", FIELD_fld_ae10_slot3_34_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_15", FIELD_fld_ae10_slot3_34_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_20", FIELD_fld_ae10_slot3_34_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_25", FIELD_fld_ae10_slot3_34_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_30", FIELD_fld_ae10_slot3_34_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_31", FIELD_fld_ae10_slot3_34_31, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_33", FIELD_fld_ae10_slot3_34_33, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_4_0", FIELD_fld_ae10_slot3_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_4_3", FIELD_fld_ae10_slot3_4_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_4_4", FIELD_fld_ae10_slot3_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_9_0", FIELD_fld_ae10_slot3_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_9_5", FIELD_fld_ae10_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_0", FIELD_fld_ae4_slot0_22_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_12", FIELD_fld_ae4_slot0_22_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_13", FIELD_fld_ae4_slot0_22_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_16", FIELD_fld_ae4_slot0_22_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_17", FIELD_fld_ae4_slot0_22_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_18", FIELD_fld_ae4_slot0_22_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_20", FIELD_fld_ae4_slot0_22_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_6", FIELD_fld_ae4_slot0_22_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_8", FIELD_fld_ae4_slot0_22_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_3_0", FIELD_fld_ae4_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_3_1", FIELD_fld_ae4_slot0_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_4_4", FIELD_fld_ae4_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_7_4", FIELD_fld_ae4_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_0", FIELD_fld_ae4_slot1_22_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_12", FIELD_fld_ae4_slot1_22_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_13", FIELD_fld_ae4_slot1_22_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_16", FIELD_fld_ae4_slot1_22_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_17", FIELD_fld_ae4_slot1_22_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_18", FIELD_fld_ae4_slot1_22_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_8", FIELD_fld_ae4_slot1_22_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_3_0", FIELD_fld_ae4_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_3_1", FIELD_fld_ae4_slot1_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_7_4", FIELD_fld_ae4_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_23_0", FIELD_fld_ae4_slot2_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_23_12", FIELD_fld_ae4_slot2_23_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_23_15", FIELD_fld_ae4_slot2_23_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_23_17", FIELD_fld_ae4_slot2_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_23_20", FIELD_fld_ae4_slot2_23_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_4_0", FIELD_fld_ae4_slot2_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_9_5", FIELD_fld_ae4_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_14_10", FIELD_fld_ae4_slot3_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_19_15", FIELD_fld_ae4_slot3_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_19_19", FIELD_fld_ae4_slot3_19_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_19_5", FIELD_fld_ae4_slot3_19_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_27_20", FIELD_fld_ae4_slot3_27_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_27_25", FIELD_fld_ae4_slot3_27_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_27_3", FIELD_fld_ae4_slot3_27_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_2_0", FIELD_fld_ae4_slot3_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_9_0", FIELD_fld_ae4_slot3_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_9_5", FIELD_fld_ae4_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot4_22_0", FIELD_fld_ae4_slot4_22_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot4_22_15", FIELD_fld_ae4_slot4_22_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot4_22_20", FIELD_fld_ae4_slot4_22_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot4_9_5", FIELD_fld_ae4_slot4_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_11_8", FIELD_fld_Inst_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_12_12", FIELD_fld_Inst_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_12_8", FIELD_fld_Inst_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_13_8", FIELD_fld_Inst_13_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_15_12", FIELD_fld_Inst_15_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_19_17", FIELD_fld_Inst_19_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_19_18", FIELD_fld_Inst_19_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_23_12", FIELD_fld_Inst_23_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_23_16", FIELD_fld_Inst_23_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_4_4", FIELD_fld_Inst_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_5_4", FIELD_fld_Inst_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_7_4", FIELD_fld_Inst_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_7_6", FIELD_fld_Inst_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_7_7", FIELD_fld_Inst_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_9_8", FIELD_fld_Inst_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 } +}; + +enum xtensa_operand_id { + OPERAND_soffsetx4, + OPERAND_immr, + OPERAND_uimm12x8, + OPERAND_simm4, + OPERAND_arr, + OPERAND_ars, + OPERAND__ars_invisible, + OPERAND_art, + OPERAND_ar0, + OPERAND_ar4, + OPERAND_ar8, + OPERAND_ar12, + OPERAND_ars_entry, + OPERAND_immrx4, + OPERAND_lsi4x4, + OPERAND_simm7, + OPERAND_uimm6, + OPERAND_ai4const, + OPERAND_b4const, + OPERAND_b4constu, + OPERAND_immt, + OPERAND_uimms8, + OPERAND_uimm8, + OPERAND_uimm8x2, + OPERAND_uimm8x4, + OPERAND_uimm4x16, + OPERAND_uimmrx4, + OPERAND_simm8, + OPERAND_simm8x256, + OPERAND_simm12b, + OPERAND_msalp32, + OPERAND_op2p1, + OPERAND_label8, + OPERAND_ulabel8, + OPERAND_label12, + OPERAND_soffset, + OPERAND_uimm16x4, + OPERAND_bbi, + OPERAND_sae, + OPERAND_sas, + OPERAND_sargt, + OPERAND_s, + OPERAND_imms, + OPERAND_imms1, + OPERAND_bt, + OPERAND_bs, + OPERAND_br, + OPERAND_bt2, + OPERAND_bs2, + OPERAND_br2, + OPERAND_bt4, + OPERAND_bs4, + OPERAND_br4, + OPERAND_bt8, + OPERAND_bs8, + OPERAND_br8, + OPERAND_bt16, + OPERAND_bs16, + OPERAND_br16, + OPERAND_brall, + OPERAND_tp7, + OPERAND_xt_wbr15_label, + OPERAND_xt_wbr18_label, + OPERAND_ae_uimm2x2, + OPERAND_opnd_ae_sem_dr_to_dr_v, + OPERAND_opnd_ae_sem_arithmetic_v, + OPERAND_opnd_ae_sem_arithmetic_v0, + OPERAND_opnd_ae_sem_arithmetic_v1, + OPERAND_opnd_ae_sem_loads_stores_a_0, + OPERAND_opnd_ae_sem_loads_stores_x, + OPERAND_opnd_ae_sem_loads_stores_end, + OPERAND_opnd_ae_sem_loads_stores_i64, + OPERAND_opnd_ae_sem_lb_ops_iba, + OPERAND_opnd_ae_sem_sb_loads_stores_iba, + OPERAND_opnd_ae_sem_pks_d, + OPERAND_opnd_ae_sem_pks_pos, + OPERAND_opnd_ae_sem_pks_s, + OPERAND_opnd_ae_sem_dr_to_ar_a, + OPERAND_opnd_ae_sem_dr_to_ar_v0, + OPERAND_opnd_ae_sem_dr_to_dr_v0, + OPERAND_opnd_ae_sem_dr_to_ar_ab, + OPERAND_opnd_ae_sem_dr_to_ar_ai, + OPERAND_opnd_ae_sem_dr_to_ar_aoe, + OPERAND_opnd_ae_sem_dr_to_dr_movi_imm, + OPERAND_opnd_ae_sem_dr_to_dr_ds, + OPERAND_opnd_ae_sem_dr_to_dr_v1, + OPERAND_opnd_ae_sem_dr_to_ar_imm8, + OPERAND_opnd_ae_sem_shift_a0, + OPERAND_opnd_ae_sem_shift_d, + OPERAND_opnd_ae_sem_shift_d0, + OPERAND_opnd_ae_sem_dr_to_ar_d, + OPERAND_opnd_ae_sem_dr_to_ar_d0, + OPERAND_opnd_ae_sem_dr_to_ar_d1, + OPERAND_opnd_ae_sem_dr_to_dr_imm2, + OPERAND_opnd_ae_sem_arithmetic_ds, + OPERAND_opnd_ae_sem_loads_stores_uu, + OPERAND_opnd_ae_sem_loads_stores_vu, + OPERAND_opnd_ae_sem_loads_stores_i32, + OPERAND_opnd_ae_sem_loads_stores_v, + OPERAND_opnd_ae_sem_loads_stores_i16, + OPERAND_opnd_ae_sem_loads_stores_i8, + OPERAND_opnd_ae_sem_loads_stores_i64pos, + OPERAND_opnd_ae_sem_loads_stores_i64neg, + OPERAND_opnd_ae_sem_loads_stores_i64half, + OPERAND_opnd_ae_sem_loads_stores_su, + OPERAND_opnd_ae_sem_loads_stores_v1, + OPERAND_opnd_ae_sem_loads_stores_av, + OPERAND_opnd_ae_sem_shift_i16, + OPERAND_opnd_ae_sem_shift_i32, + OPERAND_opnd_ae_sem_shift_d1, + OPERAND_opnd_ae_sem_shift_da, + OPERAND_opnd_ae_sem_shift_imm32, + OPERAND_opnd_ae_sem_shift_a, + OPERAND_opnd_ae_sem_shift_sd, + OPERAND_opnd_ae_sem_shift_i64, + OPERAND_opnd_ae_sem_shift_imm8, + OPERAND_opnd_ae_sem_dr_to_dr_immed, + OPERAND_opnd_ae_sem_arithmetic_art, + OPERAND_opnd_ae_sem_arithmetic_va, + OPERAND_opnd_ae_sem_arithmetic_vs, + OPERAND_opnd_ae_sem_loads_stores_i128, + OPERAND_opnd_ae_sem_loads_stores_av1, + OPERAND_opnd_ae_sem_loads_stores_imm2, + OPERAND_opnd_ae_sem_loads_stores_i3, + OPERAND_opnd_ae_sem_rng_v0, + OPERAND_opnd_ae_sem_rng_v1, + OPERAND_opnd_ae_sem_reduction_sort_v, + OPERAND_opnd_ae_sem_reduction_sort_v0, + OPERAND_opnd_ae_sem_reduction_sort_ds, + OPERAND_opnd_ae_sem_multiply_d0, + OPERAND_opnd_ae_sem_multiply_d2, + OPERAND_opnd_ae_sem_multiply_q0, + OPERAND_opnd_ae_sem_multiply_q1, + OPERAND_opnd_ae_sem_dr_to_dr_immed_N, + OPERAND_opnd_ae_sem_dr_to_ar_ei, + OPERAND_opnd_ae_sem_dr_to_ar_eo, + OPERAND_opnd_ae_sem_multiply_acc_ep, + OPERAND_opnd_ae_sem_arithmetic_e, + OPERAND_opnd_ae_sem_arithmetic_ep, + OPERAND_opnd_ae_sem_arithmetic_ep1, + OPERAND_opnd_ae_sem_select_ss, + OPERAND_opnd_ae_sem_select_vr, + OPERAND_opnd_ae_sem_select_vs, + OPERAND_opnd_ae_sem_select_vt, + OPERAND_opnd_ae_sem_select_vu, + OPERAND_opnd_ae_sem_select_isel, + OPERAND_opnd_ae_sem_shift_e, + OPERAND_opnd_ae_sem_shift_i8, + OPERAND_opnd_ae_sem_multiply_d1, + OPERAND_opnd_ae_sem_multiply_d3, + OPERAND_opnd_ae_sem_dr_to_dr_imm, + OPERAND_opnd_ae_sem_rng_d, + OPERAND_opnd_ae_sem_sb_loads_stores_iba2, + OPERAND_opnd_ae_sem_dr_to_ar_ar_s, + OPERAND_opnd_AE_ARDECNORM16_ar_u, + OPERAND_opnd_ae_sem_rng_a, + OPERAND_opnd_ae_sem_rng_art, + OPERAND_opnd_ae_sem_rng_i2, + OPERAND_opnd_ae_sem_rng_imm2, + OPERAND_opnd_ae_sem_lb_db_ops_ar_u, + OPERAND_opnd_ae_sem_lb_db_ops_iba, + OPERAND_opnd_ae_sem_dr_to_ar_vr, + OPERAND_opnd_ae_sem_spmisc_brt, + OPERAND_opnd_ae_sem_spmisc_vr, + OPERAND_opnd_ae_sem_spmisc_vs, + OPERAND_opnd_ae_sem_dr_to_dr_arr, + OPERAND_opnd_ae_sem_dr_to_dr_bt, + OPERAND_opnd_ae_sem_sp32cvt_art, + OPERAND_opnd_ae_sem_sp32cvt_i_imm5, + OPERAND_opnd_ae_sem_sp32cvt_vr, + OPERAND_opnd_ae_sem_sp32cvt_vt, + OPERAND_opnd_ae_sem_sp32cvt_arr, + OPERAND_opnd_ae_sem_movfpstate_v, + OPERAND_opnd_ae_sem_fpmov_vr, + OPERAND_opnd_ae_sem_fpmov_vt, + OPERAND_opnd_ae_sem_fpmov_i_imm4, + OPERAND_opnd_ae_sem_fpmov_vs, + OPERAND_opnd_ae_sem_fpmov_vu, + OPERAND_opnd_ae_sem_spmisc_vsM, + OPERAND_opnd_ae_sem_spmisc_vtM, + OPERAND_opnd_ae_sem_spmisc_vt, + OPERAND_opnd_ae_sem_spaddsub_vr, + OPERAND_opnd_ae_sem_spaddsub_vs, + OPERAND_opnd_ae_sem_spaddsub_vt, + OPERAND_opnd_ae_sem_spaddsub_vu, + OPERAND_opnd_ae_sem_spfma_vr, + OPERAND_opnd_ae_sem_spfma_vs, + OPERAND_opnd_ae_sem_spfma_vt, + OPERAND_opnd_ae_sem_spfma_vp, + OPERAND_opnd_ae_sem_spfma_i_imm1, + OPERAND_opnd_ae_sem_spfma_i_imm3, + OPERAND_opnd_ae_sem_spaddsub_vp, + OPERAND_opnd_ae_sem_spaddsub_vq, + OPERAND_opnd_ae_sem_spfma_vu, + OPERAND_opnd_ae_sem_spfma_vq, + OPERAND_opnd_ae_sem_hprminmaxnum_vr, + OPERAND_opnd_ae_sem_hprminmaxnum_vt, + OPERAND_opnd_ae_sem_hpcmp_br4t, + OPERAND_opnd_ae_sem_hpcmp_vr, + OPERAND_opnd_ae_sem_hpcmp_vs, + OPERAND_opnd_ae_sem_hpcnv_art, + OPERAND_opnd_ae_sem_hpcnv_i_imm4, + OPERAND_opnd_ae_sem_hpcnv_vr, + OPERAND_opnd_ae_sem_hpcnv_arr, + OPERAND_opnd_ae_sem_hpcnv_vt, + OPERAND_opnd_ae_sem_hpcmp_vt, + OPERAND_opnd_ae_sem_hpcnv_vs, + OPERAND_opnd_ae_sem_hpfma_vr, + OPERAND_opnd_ae_sem_hpfma_vs, + OPERAND_opnd_ae_sem_hpfma_vt, + OPERAND_opnd_ae_sem_hpfma_vp, + OPERAND_opnd_ae_sem_hpfma_vu, + OPERAND_opnd_ae_sem_hpfma_vq, + OPERAND_opnd_ae_sem_mul_nn_c0, + OPERAND_opnd_ae_sem_mul_nn_c1, + OPERAND_opnd_ae_sem_mul_nn_c2, + OPERAND_opnd_ae_sem_mul_nn_c3, + OPERAND_opnd_ae_sem_mul_nn_q0, + OPERAND_opnd_ae_sem_mul_nn_q1, + OPERAND_opnd_ae_sem_mul_nn_v0, + OPERAND_opnd_ae_sem_mul_nn_v1, + OPERAND_opnd_ae_sem_mul_nn_q2, + OPERAND_opnd_ae_sem_mul_nn_q3, + OPERAND_opnd_ae_sem_mul_nn_v2, + OPERAND_opnd_ae_sem_mul_nn_v3, + OPERAND_bitindex, + OPERAND_t, + OPERAND_bbi4, + OPERAND_imm12, + OPERAND_imm8, + OPERAND_s8, + OPERAND_imms8, + OPERAND_imm12b, + OPERAND_imm16, + OPERAND_m, + OPERAND_n, + OPERAND_offset, + OPERAND_op0, + OPERAND_op1, + OPERAND_op2, + OPERAND_r, + OPERAND_r_disp, + OPERAND_r_3, + OPERAND_sa4, + OPERAND_sae4, + OPERAND_sal, + OPERAND_sas4, + OPERAND_sr, + OPERAND_st, + OPERAND_thi3, + OPERAND_imm4, + OPERAND_mn, + OPERAND_i, + OPERAND_imm6lo, + OPERAND_imm6hi, + OPERAND_imm7lo, + OPERAND_imm7hi, + OPERAND_z, + OPERAND_imm6, + OPERAND_imm7, + OPERAND_t2, + OPERAND_s2, + OPERAND_r2, + OPERAND_t4, + OPERAND_s4, + OPERAND_r4, + OPERAND_t8, + OPERAND_r8, + OPERAND_xt_wbr15_imm, + OPERAND_xt_wbr18_imm, + OPERAND_ae_fld_Inst16b_12, + OPERAND_ae_fld_Inst16b_15_13, + OPERAND_fld_ae_sem_arithmetic_art, + OPERAND_fld_ae_sem_arithmetic_ds, + OPERAND_fld_ae_sem_arithmetic_v, + OPERAND_fld_ae_sem_arithmetic_v0, + OPERAND_fld_ae_sem_arithmetic_v1, + OPERAND_fld_ae_sem_arithmetic_va, + OPERAND_fld_ae_sem_arithmetic_vs, + OPERAND_fld_ae_sem_dr_to_ar_a, + OPERAND_fld_ae_sem_dr_to_ar_ab, + OPERAND_fld_ae_sem_dr_to_ar_ai, + OPERAND_fld_ae_sem_dr_to_ar_aoe, + OPERAND_fld_ae_sem_dr_to_ar_d, + OPERAND_fld_ae_sem_dr_to_ar_d0, + OPERAND_fld_ae_sem_dr_to_ar_d1, + OPERAND_fld_ae_sem_dr_to_ar_imm8, + OPERAND_fld_ae_sem_dr_to_ar_v0, + OPERAND_fld_ae_sem_dr_to_ar_vr, + OPERAND_fld_ae_sem_dr_to_dr_arr, + OPERAND_fld_ae_sem_dr_to_dr_bt, + OPERAND_fld_ae_sem_dr_to_dr_ds, + OPERAND_fld_ae_sem_dr_to_dr_imm2, + OPERAND_fld_ae_sem_dr_to_dr_immed, + OPERAND_fld_ae_sem_dr_to_dr_movi_imm, + OPERAND_fld_ae_sem_dr_to_dr_v, + OPERAND_fld_ae_sem_dr_to_dr_v0, + OPERAND_fld_ae_sem_dr_to_dr_v1, + OPERAND_fld_ae_sem_hpcmp_br4t, + OPERAND_fld_ae_sem_hpcmp_vr, + OPERAND_fld_ae_sem_hpcmp_vs, + OPERAND_fld_ae_sem_hpcnv_arr, + OPERAND_fld_ae_sem_hpcnv_art, + OPERAND_fld_ae_sem_hpcnv_i_imm4, + OPERAND_fld_ae_sem_hpcnv_vr, + OPERAND_fld_ae_sem_hpcnv_vt, + OPERAND_fld_ae_sem_hprminmaxnum_vr, + OPERAND_fld_ae_sem_hprminmaxnum_vt, + OPERAND_fld_ae_sem_lb_ops_iba, + OPERAND_fld_ae_sem_loads_stores_a, + OPERAND_fld_ae_sem_loads_stores_a_0, + OPERAND_fld_ae_sem_loads_stores_av, + OPERAND_fld_ae_sem_loads_stores_av1, + OPERAND_fld_ae_sem_loads_stores_end, + OPERAND_fld_ae_sem_loads_stores_i128, + OPERAND_fld_ae_sem_loads_stores_i16, + OPERAND_fld_ae_sem_loads_stores_i3, + OPERAND_fld_ae_sem_loads_stores_i32, + OPERAND_fld_ae_sem_loads_stores_i32pos, + OPERAND_fld_ae_sem_loads_stores_i64, + OPERAND_fld_ae_sem_loads_stores_i64half, + OPERAND_fld_ae_sem_loads_stores_i64neg, + OPERAND_fld_ae_sem_loads_stores_i64pos, + OPERAND_fld_ae_sem_loads_stores_i64x2, + OPERAND_fld_ae_sem_loads_stores_i8, + OPERAND_fld_ae_sem_loads_stores_imm2, + OPERAND_fld_ae_sem_loads_stores_su, + OPERAND_fld_ae_sem_loads_stores_uu, + OPERAND_fld_ae_sem_loads_stores_v, + OPERAND_fld_ae_sem_loads_stores_v1, + OPERAND_fld_ae_sem_loads_stores_vu, + OPERAND_fld_ae_sem_loads_stores_x, + OPERAND_fld_ae_sem_pks_d, + OPERAND_fld_ae_sem_pks_pos, + OPERAND_fld_ae_sem_pks_s, + OPERAND_fld_ae_sem_rng_v0, + OPERAND_fld_ae_sem_rng_v1, + OPERAND_fld_ae_sem_sb_loads_stores_iba, + OPERAND_fld_ae_sem_shift_a, + OPERAND_fld_ae_sem_shift_a0, + OPERAND_fld_ae_sem_shift_d, + OPERAND_fld_ae_sem_shift_d0, + OPERAND_fld_ae_sem_shift_d1, + OPERAND_fld_ae_sem_shift_da, + OPERAND_fld_ae_sem_shift_i16, + OPERAND_fld_ae_sem_shift_i32, + OPERAND_fld_ae_sem_shift_i64, + OPERAND_fld_ae_sem_shift_imm32, + OPERAND_fld_ae_sem_shift_imm8, + OPERAND_fld_ae_sem_shift_sd, + OPERAND_fld_ae_sem_sp32cvt_arr, + OPERAND_fld_ae_sem_sp32cvt_art, + OPERAND_fld_ae_sem_sp32cvt_i_imm5, + OPERAND_fld_ae_sem_sp32cvt_vr, + OPERAND_fld_ae_sem_sp32cvt_vt, + OPERAND_fld_ae_sem_spmisc_brt, + OPERAND_fld_ae_sem_spmisc_vr, + OPERAND_fld_ae_sem_spmisc_vs, + OPERAND_fld_ae_slot0_11_10, + OPERAND_fld_ae_slot0_11_11, + OPERAND_fld_ae_slot0_11_8, + OPERAND_fld_ae_slot0_11_9, + OPERAND_fld_ae_slot0_12_0, + OPERAND_fld_ae_slot0_12_10, + OPERAND_fld_ae_slot0_12_12, + OPERAND_fld_ae_slot0_12_2, + OPERAND_fld_ae_slot0_12_6, + OPERAND_fld_ae_slot0_12_8, + OPERAND_fld_ae_slot0_12_9, + OPERAND_fld_ae_slot0_14_12, + OPERAND_fld_ae_slot0_14_13, + OPERAND_fld_ae_slot0_17_10, + OPERAND_fld_ae_slot0_17_12, + OPERAND_fld_ae_slot0_17_13, + OPERAND_fld_ae_slot0_17_14, + OPERAND_fld_ae_slot0_17_15, + OPERAND_fld_ae_slot0_17_16, + OPERAND_fld_ae_slot0_17_17, + OPERAND_fld_ae_slot0_17_8, + OPERAND_fld_ae_slot0_18_13, + OPERAND_fld_ae_slot0_18_15, + OPERAND_fld_ae_slot0_18_16, + OPERAND_fld_ae_slot0_18_8, + OPERAND_fld_ae_slot0_19_12, + OPERAND_fld_ae_slot0_19_15, + OPERAND_fld_ae_slot0_19_19, + OPERAND_fld_ae_slot0_19_8, + OPERAND_fld_ae_slot0_1_0, + OPERAND_fld_ae_slot0_1_1, + OPERAND_fld_ae_slot0_20_16, + OPERAND_fld_ae_slot0_20_20, + OPERAND_fld_ae_slot0_23_15, + OPERAND_fld_ae_slot0_23_17, + OPERAND_fld_ae_slot0_23_19, + OPERAND_fld_ae_slot0_23_22, + OPERAND_fld_ae_slot0_28_10, + OPERAND_fld_ae_slot0_28_12, + OPERAND_fld_ae_slot0_28_14, + OPERAND_fld_ae_slot0_28_15, + OPERAND_fld_ae_slot0_28_16, + OPERAND_fld_ae_slot0_28_17, + OPERAND_fld_ae_slot0_28_19, + OPERAND_fld_ae_slot0_28_21, + OPERAND_fld_ae_slot0_28_22, + OPERAND_fld_ae_slot0_28_24, + OPERAND_fld_ae_slot0_28_26, + OPERAND_fld_ae_slot0_28_27, + OPERAND_fld_ae_slot0_28_4, + OPERAND_fld_ae_slot0_28_8, + OPERAND_fld_ae_slot0_3_0, + OPERAND_fld_ae_slot0_3_1, + OPERAND_fld_ae_slot0_3_2, + OPERAND_fld_ae_slot0_3_3, + OPERAND_fld_ae_slot0_4_0, + OPERAND_fld_ae_slot0_4_4, + OPERAND_fld_ae_slot0_5_0, + OPERAND_fld_ae_slot0_5_4, + OPERAND_fld_ae_slot0_7_0, + OPERAND_fld_ae_slot0_7_2, + OPERAND_fld_ae_slot0_7_3, + OPERAND_fld_ae_slot0_7_4, + OPERAND_fld_ae_slot0_8_8, + OPERAND_fld_ae_slot0_9_4, + OPERAND_fld_ae_slot0_9_8, + OPERAND_fld_ae_slot0_9_9, + OPERAND_fld_ae_slot1_0_0, + OPERAND_fld_ae_slot1_12_8, + OPERAND_fld_ae_slot1_17_13, + OPERAND_fld_ae_slot1_17_17, + OPERAND_fld_ae_slot1_17_8, + OPERAND_fld_ae_slot1_25_1, + OPERAND_fld_ae_slot1_25_12, + OPERAND_fld_ae_slot1_25_13, + OPERAND_fld_ae_slot1_25_16, + OPERAND_fld_ae_slot1_25_17, + OPERAND_fld_ae_slot1_25_18, + OPERAND_fld_ae_slot1_25_20, + OPERAND_fld_ae_slot1_25_22, + OPERAND_fld_ae_slot1_25_23, + OPERAND_fld_ae_slot1_25_8, + OPERAND_fld_ae_slot1_25_9, + OPERAND_fld_ae_slot1_3_0, + OPERAND_fld_ae_slot1_3_2, + OPERAND_fld_ae_slot1_3_3, + OPERAND_fld_ae_slot1_7_4, + OPERAND_fld_ae_sem_arithmetic_e, + OPERAND_fld_ae_sem_arithmetic_ep, + OPERAND_fld_ae_sem_arithmetic_ep1, + OPERAND_fld_ae_sem_dr_to_ar_ei, + OPERAND_fld_ae_sem_dr_to_ar_eo, + OPERAND_fld_ae_sem_dr_to_dr_immed_N, + OPERAND_fld_ae_sem_fpmov_i_imm4, + OPERAND_fld_ae_sem_fpmov_vr, + OPERAND_fld_ae_sem_fpmov_vs, + OPERAND_fld_ae_sem_fpmov_vt, + OPERAND_fld_ae_sem_fpmov_vu, + OPERAND_fld_ae_sem_hpcmp_vt, + OPERAND_fld_ae_sem_hpcnv_vs, + OPERAND_fld_ae_sem_hpfma_vr, + OPERAND_fld_ae_sem_hpfma_vs, + OPERAND_fld_ae_sem_hpfma_vt, + OPERAND_fld_ae_sem_movfpstate_v, + OPERAND_fld_ae_sem_multiply_acc_ep, + OPERAND_fld_ae_sem_multiply_d0, + OPERAND_fld_ae_sem_multiply_d2, + OPERAND_fld_ae_sem_multiply_q0, + OPERAND_fld_ae_sem_multiply_q1, + OPERAND_fld_ae_sem_reduction_sort_ds, + OPERAND_fld_ae_sem_reduction_sort_v, + OPERAND_fld_ae_sem_reduction_sort_v0, + OPERAND_fld_ae_sem_select_isel, + OPERAND_fld_ae_sem_select_ss, + OPERAND_fld_ae_sem_select_vr, + OPERAND_fld_ae_sem_select_vs, + OPERAND_fld_ae_sem_select_vt, + OPERAND_fld_ae_sem_select_vu, + OPERAND_fld_ae_sem_spaddsub_vr, + OPERAND_fld_ae_sem_spaddsub_vs, + OPERAND_fld_ae_sem_spaddsub_vt, + OPERAND_fld_ae_sem_spaddsub_vu, + OPERAND_fld_ae_sem_spfma_i_imm1, + OPERAND_fld_ae_sem_spfma_i_imm3, + OPERAND_fld_ae_sem_spfma_vp, + OPERAND_fld_ae_sem_spfma_vr, + OPERAND_fld_ae_sem_spfma_vs, + OPERAND_fld_ae_sem_spfma_vt, + OPERAND_fld_ae_sem_spmisc_vsM, + OPERAND_fld_ae_sem_spmisc_vt, + OPERAND_fld_ae_sem_spmisc_vtM, + OPERAND_fld_ae_slot2_14_0, + OPERAND_fld_ae_slot2_14_10, + OPERAND_fld_ae_slot2_14_14, + OPERAND_fld_ae_slot2_14_5, + OPERAND_fld_ae_slot2_16_15, + OPERAND_fld_ae_slot2_19_15, + OPERAND_fld_ae_slot2_28_15, + OPERAND_fld_ae_slot2_28_17, + OPERAND_fld_ae_slot2_28_19, + OPERAND_fld_ae_slot2_28_20, + OPERAND_fld_ae_slot2_28_25, + OPERAND_fld_ae_slot2_28_4, + OPERAND_fld_ae_slot2_28_5, + OPERAND_fld_ae_slot2_3_0, + OPERAND_fld_ae_slot2_9_0, + OPERAND_fld_ae_slot2_9_1, + OPERAND_fld_ae_slot2_9_2, + OPERAND_fld_ae_slot2_9_5, + OPERAND_fld_ae_slot2_9_6, + OPERAND_fld_ae_slot2_9_7, + OPERAND_fld_ae_slot2_9_8, + OPERAND_fld_ae_sem_dr_to_dr_imm, + OPERAND_fld_ae_sem_multiply_d1, + OPERAND_fld_ae_sem_multiply_d3, + OPERAND_fld_ae_sem_rng_d, + OPERAND_fld_ae_sem_shift_e, + OPERAND_fld_ae_sem_shift_i8, + OPERAND_fld_ae_slot3_11_0, + OPERAND_fld_ae_slot3_14_0, + OPERAND_fld_ae_slot3_14_10, + OPERAND_fld_ae_slot3_14_12, + OPERAND_fld_ae_slot3_14_13, + OPERAND_fld_ae_slot3_16_13, + OPERAND_fld_ae_slot3_19_0, + OPERAND_fld_ae_slot3_19_10, + OPERAND_fld_ae_slot3_19_15, + OPERAND_fld_ae_slot3_19_17, + OPERAND_fld_ae_slot3_19_18, + OPERAND_fld_ae_slot3_19_19, + OPERAND_fld_ae_slot3_24_10, + OPERAND_fld_ae_slot3_24_19, + OPERAND_fld_ae_slot3_24_20, + OPERAND_fld_ae_slot3_36_12, + OPERAND_fld_ae_slot3_36_16, + OPERAND_fld_ae_slot3_36_19, + OPERAND_fld_ae_slot3_36_20, + OPERAND_fld_ae_slot3_36_22, + OPERAND_fld_ae_slot3_36_25, + OPERAND_fld_ae_slot3_36_30, + OPERAND_fld_ae_slot3_4_0, + OPERAND_fld_ae_slot3_9_0, + OPERAND_fld_ae_slot3_9_1, + OPERAND_fld_ae_slot3_9_3, + OPERAND_fld_ae_slot3_9_5, + OPERAND_fld_ae2_slot0_0_0, + OPERAND_fld_ae2_slot0_11_4, + OPERAND_fld_ae2_slot0_11_8, + OPERAND_fld_ae2_slot0_11_9, + OPERAND_fld_ae2_slot0_12_0, + OPERAND_fld_ae2_slot0_12_2, + OPERAND_fld_ae2_slot0_12_4, + OPERAND_fld_ae2_slot0_12_8, + OPERAND_fld_ae2_slot0_14_13, + OPERAND_fld_ae2_slot0_14_8, + OPERAND_fld_ae2_slot0_15_0, + OPERAND_fld_ae2_slot0_15_12, + OPERAND_fld_ae2_slot0_15_13, + OPERAND_fld_ae2_slot0_15_15, + OPERAND_fld_ae2_slot0_15_4, + OPERAND_fld_ae2_slot0_15_8, + OPERAND_fld_ae2_slot0_17_13, + OPERAND_fld_ae2_slot0_17_17, + OPERAND_fld_ae2_slot0_18_15, + OPERAND_fld_ae2_slot0_18_17, + OPERAND_fld_ae2_slot0_18_18, + OPERAND_fld_ae2_slot0_1_0, + OPERAND_fld_ae2_slot0_23_18, + OPERAND_fld_ae2_slot0_23_19, + OPERAND_fld_ae2_slot0_3_0, + OPERAND_fld_ae2_slot0_40_16, + OPERAND_fld_ae2_slot0_40_17, + OPERAND_fld_ae2_slot0_40_18, + OPERAND_fld_ae2_slot0_40_19, + OPERAND_fld_ae2_slot0_40_21, + OPERAND_fld_ae2_slot0_40_23, + OPERAND_fld_ae2_slot0_40_24, + OPERAND_fld_ae2_slot0_40_25, + OPERAND_fld_ae2_slot0_40_26, + OPERAND_fld_ae2_slot0_40_27, + OPERAND_fld_ae2_slot0_7_0, + OPERAND_fld_ae2_slot0_7_4, + OPERAND_fld_ae2_slot0_7_6, + OPERAND_fld_ae2_slot0_7_7, + OPERAND_fld_ae2_slot0_8_8, + OPERAND_fld_ae2_slot0_9_8, + OPERAND_fld_ae2_slot1_0_0, + OPERAND_fld_ae2_slot1_11_0, + OPERAND_fld_ae2_slot1_11_10, + OPERAND_fld_ae2_slot1_11_8, + OPERAND_fld_ae2_slot1_14_10, + OPERAND_fld_ae2_slot1_14_11, + OPERAND_fld_ae2_slot1_14_12, + OPERAND_fld_ae2_slot1_14_14, + OPERAND_fld_ae2_slot1_14_8, + OPERAND_fld_ae2_slot1_36_12, + OPERAND_fld_ae2_slot1_36_14, + OPERAND_fld_ae2_slot1_36_15, + OPERAND_fld_ae2_slot1_36_16, + OPERAND_fld_ae2_slot1_36_17, + OPERAND_fld_ae2_slot1_36_18, + OPERAND_fld_ae2_slot1_36_20, + OPERAND_fld_ae2_slot1_36_22, + OPERAND_fld_ae2_slot1_36_23, + OPERAND_fld_ae2_slot1_3_0, + OPERAND_fld_ae2_slot1_3_1, + OPERAND_fld_ae2_slot1_3_2, + OPERAND_fld_ae2_slot1_3_3, + OPERAND_fld_ae2_slot1_7_4, + OPERAND_fld_ae2_slot1_9_8, + OPERAND_fld_ae2_slot1_9_9, + OPERAND_fld_ae2_slot2_14_10, + OPERAND_fld_ae2_slot2_17_0, + OPERAND_fld_ae2_slot2_17_10, + OPERAND_fld_ae2_slot2_17_15, + OPERAND_fld_ae2_slot2_17_17, + OPERAND_fld_ae2_slot2_19_10, + OPERAND_fld_ae2_slot2_19_15, + OPERAND_fld_ae2_slot2_19_18, + OPERAND_fld_ae2_slot2_19_9, + OPERAND_fld_ae2_slot2_24_10, + OPERAND_fld_ae2_slot2_24_15, + OPERAND_fld_ae2_slot2_24_20, + OPERAND_fld_ae2_slot2_24_5, + OPERAND_fld_ae2_slot2_24_9, + OPERAND_fld_ae2_slot2_42_18, + OPERAND_fld_ae2_slot2_42_20, + OPERAND_fld_ae2_slot2_42_25, + OPERAND_fld_ae2_slot2_42_26, + OPERAND_fld_ae2_slot2_42_28, + OPERAND_fld_ae2_slot2_42_30, + OPERAND_fld_ae2_slot2_4_0, + OPERAND_fld_ae2_slot2_9_5, + OPERAND_fld_ae_sem_spaddsub_vp, + OPERAND_fld_ae_sem_spaddsub_vq, + OPERAND_fld_ae3_slot0_11_11, + OPERAND_fld_ae3_slot0_11_4, + OPERAND_fld_ae3_slot0_11_8, + OPERAND_fld_ae3_slot0_12_12, + OPERAND_fld_ae3_slot0_12_8, + OPERAND_fld_ae3_slot0_13_13, + OPERAND_fld_ae3_slot0_13_8, + OPERAND_fld_ae3_slot0_1_0, + OPERAND_fld_ae3_slot0_32_11, + OPERAND_fld_ae3_slot0_32_12, + OPERAND_fld_ae3_slot0_32_13, + OPERAND_fld_ae3_slot0_32_14, + OPERAND_fld_ae3_slot0_32_15, + OPERAND_fld_ae3_slot0_32_16, + OPERAND_fld_ae3_slot0_32_17, + OPERAND_fld_ae3_slot0_32_18, + OPERAND_fld_ae3_slot0_32_20, + OPERAND_fld_ae3_slot0_32_27, + OPERAND_fld_ae3_slot0_32_8, + OPERAND_fld_ae3_slot0_3_0, + OPERAND_fld_ae3_slot0_3_2, + OPERAND_fld_ae3_slot0_3_3, + OPERAND_fld_ae3_slot0_4_0, + OPERAND_fld_ae3_slot0_4_4, + OPERAND_fld_ae3_slot0_5_0, + OPERAND_fld_ae3_slot0_5_4, + OPERAND_fld_ae3_slot0_7_0, + OPERAND_fld_ae3_slot0_7_2, + OPERAND_fld_ae3_slot0_7_4, + OPERAND_fld_ae3_slot0_7_6, + OPERAND_fld_ae3_slot0_8_8, + OPERAND_fld_ae3_slot0_9_4, + OPERAND_fld_ae3_slot0_9_8, + OPERAND_fld_ae_sem_dr_to_ar_ar_s, + OPERAND_fld_ae_sem_sb_loads_stores_iba2, + OPERAND_fld_ae3_slot1_23_0, + OPERAND_fld_ae3_slot1_23_11, + OPERAND_fld_ae3_slot1_23_12, + OPERAND_fld_ae3_slot1_23_13, + OPERAND_fld_ae3_slot1_23_15, + OPERAND_fld_ae3_slot1_23_16, + OPERAND_fld_ae3_slot1_23_17, + OPERAND_fld_ae3_slot1_23_19, + OPERAND_fld_ae3_slot1_23_6, + OPERAND_fld_ae3_slot1_23_8, + OPERAND_fld_ae3_slot1_23_9, + OPERAND_fld_ae3_slot1_3_0, + OPERAND_fld_ae3_slot1_3_1, + OPERAND_fld_ae3_slot1_3_2, + OPERAND_fld_ae3_slot1_3_3, + OPERAND_fld_ae3_slot1_7_4, + OPERAND_fld_ae3_slot1_9_8, + OPERAND_fld_AE_ARDECNORM16_ar_u, + OPERAND_fld_ae5_slot0_11_10, + OPERAND_fld_ae5_slot0_11_4, + OPERAND_fld_ae5_slot0_11_8, + OPERAND_fld_ae5_slot0_11_9, + OPERAND_fld_ae5_slot0_12_10, + OPERAND_fld_ae5_slot0_12_4, + OPERAND_fld_ae5_slot0_12_6, + OPERAND_fld_ae5_slot0_12_8, + OPERAND_fld_ae5_slot0_12_9, + OPERAND_fld_ae5_slot0_1_0, + OPERAND_fld_ae5_slot0_1_1, + OPERAND_fld_ae5_slot0_29_12, + OPERAND_fld_ae5_slot0_29_13, + OPERAND_fld_ae5_slot0_29_15, + OPERAND_fld_ae5_slot0_29_16, + OPERAND_fld_ae5_slot0_29_17, + OPERAND_fld_ae5_slot0_29_18, + OPERAND_fld_ae5_slot0_29_19, + OPERAND_fld_ae5_slot0_29_20, + OPERAND_fld_ae5_slot0_29_27, + OPERAND_fld_ae5_slot0_29_5, + OPERAND_fld_ae5_slot0_29_6, + OPERAND_fld_ae5_slot0_29_8, + OPERAND_fld_ae5_slot0_2_0, + OPERAND_fld_ae5_slot0_3_0, + OPERAND_fld_ae5_slot0_3_2, + OPERAND_fld_ae5_slot0_4_0, + OPERAND_fld_ae5_slot0_4_4, + OPERAND_fld_ae5_slot0_7_0, + OPERAND_fld_ae5_slot0_7_4, + OPERAND_fld_ae5_slot0_7_7, + OPERAND_fld_ae5_slot0_8_8, + OPERAND_fld_ae_sem_lb_db_ops_ar_u, + OPERAND_fld_ae_sem_lb_db_ops_iba, + OPERAND_fld_ae_sem_rng_a, + OPERAND_fld_ae_sem_rng_art, + OPERAND_fld_ae_sem_rng_i2, + OPERAND_fld_ae_sem_rng_imm2, + OPERAND_fld_ae5_slot1_1_0, + OPERAND_fld_ae5_slot2_14_10, + OPERAND_fld_ae5_slot2_14_14, + OPERAND_fld_ae5_slot2_14_5, + OPERAND_fld_ae5_slot2_24_0, + OPERAND_fld_ae5_slot2_24_15, + OPERAND_fld_ae5_slot2_24_17, + OPERAND_fld_ae5_slot2_24_20, + OPERAND_fld_ae5_slot2_4_0, + OPERAND_fld_ae5_slot2_9_0, + OPERAND_fld_ae5_slot2_9_5, + OPERAND_fld_ae5_slot2_9_7, + OPERAND_fld_ae6_slot0_10_10, + OPERAND_fld_ae6_slot0_15_15, + OPERAND_fld_ae6_slot0_29_10, + OPERAND_fld_ae6_slot0_29_13, + OPERAND_fld_ae6_slot0_29_14, + OPERAND_fld_ae6_slot0_29_15, + OPERAND_fld_ae6_slot0_29_18, + OPERAND_fld_ae6_slot0_29_20, + OPERAND_fld_ae6_slot0_29_5, + OPERAND_fld_ae6_slot0_4_0, + OPERAND_fld_ae6_slot0_4_4, + OPERAND_fld_ae6_slot0_7_4, + OPERAND_fld_ae6_slot0_7_7, + OPERAND_fld_ae6_slot0_9_8, + OPERAND_fld_ae6_slot0_9_9, + OPERAND_fld_ae6_slot1_14_14, + OPERAND_fld_ae6_slot1_27_12, + OPERAND_fld_ae6_slot1_27_15, + OPERAND_fld_ae6_slot1_27_20, + OPERAND_fld_ae6_slot1_27_21, + OPERAND_fld_ae6_slot1_27_3, + OPERAND_fld_ae6_slot1_27_6, + OPERAND_fld_ae6_slot1_2_0, + OPERAND_fld_ae6_slot1_9_5, + OPERAND_fld_ae6_slot1_9_6, + OPERAND_fld_ae6_slot1_9_7, + OPERAND_fld_ae6_slot1_9_8, + OPERAND_fld_ae6_slot1_9_9, + OPERAND_fld_ae6_slot2_10_10, + OPERAND_fld_ae6_slot2_11_10, + OPERAND_fld_ae6_slot2_24_0, + OPERAND_fld_ae6_slot2_24_10, + OPERAND_fld_ae6_slot2_24_14, + OPERAND_fld_ae6_slot2_24_15, + OPERAND_fld_ae6_slot2_24_20, + OPERAND_fld_ae6_slot2_4_2, + OPERAND_fld_ae6_slot2_9_5, + OPERAND_fld_ae6_slot3_10_10, + OPERAND_fld_ae6_slot3_12_0, + OPERAND_fld_ae6_slot3_14_0, + OPERAND_fld_ae6_slot3_14_10, + OPERAND_fld_ae6_slot3_14_13, + OPERAND_fld_ae6_slot3_14_5, + OPERAND_fld_ae6_slot3_24_20, + OPERAND_fld_ae6_slot3_37_13, + OPERAND_fld_ae6_slot3_37_15, + OPERAND_fld_ae6_slot3_37_20, + OPERAND_fld_ae6_slot3_37_30, + OPERAND_fld_ae6_slot3_9_5, + OPERAND_fld_ae7_slot0_12_6, + OPERAND_fld_ae7_slot0_23_0, + OPERAND_fld_ae7_slot0_23_13, + OPERAND_fld_ae7_slot0_23_17, + OPERAND_fld_ae7_slot0_23_18, + OPERAND_fld_ae7_slot0_23_6, + OPERAND_fld_ae7_slot0_7_4, + OPERAND_fld_ae7_slot0_7_6, + OPERAND_fld_ae7_slot0_7_7, + OPERAND_fld_ae7_slot1_12_6, + OPERAND_fld_ae7_slot1_23_0, + OPERAND_fld_ae7_slot1_23_13, + OPERAND_fld_ae7_slot1_23_17, + OPERAND_fld_ae7_slot1_23_18, + OPERAND_fld_ae7_slot1_23_6, + OPERAND_fld_ae7_slot1_7_4, + OPERAND_fld_ae7_slot1_7_6, + OPERAND_fld_ae7_slot1_7_7, + OPERAND_fld_ae7_slot2_11_0, + OPERAND_fld_ae7_slot2_14_10, + OPERAND_fld_ae7_slot2_14_5, + OPERAND_fld_ae7_slot2_36_12, + OPERAND_fld_ae7_slot2_36_15, + OPERAND_fld_ae7_slot2_36_20, + OPERAND_fld_ae7_slot2_36_25, + OPERAND_fld_ae7_slot2_36_30, + OPERAND_fld_ae7_slot2_9_5, + OPERAND_fld_ae7_slot3_10_0, + OPERAND_fld_ae7_slot3_14_10, + OPERAND_fld_ae7_slot3_14_5, + OPERAND_fld_ae7_slot3_24_10, + OPERAND_fld_ae7_slot3_35_11, + OPERAND_fld_ae7_slot3_35_20, + OPERAND_fld_ae7_slot3_35_25, + OPERAND_fld_ae7_slot3_35_30, + OPERAND_fld_ae7_slot3_4_0, + OPERAND_fld_ae7_slot3_9_5, + OPERAND_fld_ae8_slot0_13_12, + OPERAND_fld_ae8_slot0_13_13, + OPERAND_fld_ae8_slot0_13_4, + OPERAND_fld_ae8_slot0_13_9, + OPERAND_fld_ae8_slot0_17_4, + OPERAND_fld_ae8_slot0_17_8, + OPERAND_fld_ae8_slot0_31_12, + OPERAND_fld_ae8_slot0_31_15, + OPERAND_fld_ae8_slot0_31_18, + OPERAND_fld_ae8_slot0_31_19, + OPERAND_fld_ae8_slot0_31_20, + OPERAND_fld_ae8_slot0_31_21, + OPERAND_fld_ae8_slot0_31_22, + OPERAND_fld_ae8_slot0_31_23, + OPERAND_fld_ae8_slot0_31_7, + OPERAND_fld_ae8_slot0_31_8, + OPERAND_fld_ae8_slot0_31_9, + OPERAND_fld_ae8_slot0_3_0, + OPERAND_fld_ae8_slot0_6_0, + OPERAND_fld_ae8_slot0_7_4, + OPERAND_fld_ae8_slot0_7_5, + OPERAND_fld_ae8_slot0_7_7, + OPERAND_fld_ae8_slot0_8_0, + OPERAND_fld_ae8_slot1_17_13, + OPERAND_fld_ae8_slot1_17_14, + OPERAND_fld_ae8_slot1_17_15, + OPERAND_fld_ae8_slot1_17_8, + OPERAND_fld_ae8_slot1_29_12, + OPERAND_fld_ae8_slot1_29_13, + OPERAND_fld_ae8_slot1_29_18, + OPERAND_fld_ae8_slot1_29_20, + OPERAND_fld_ae8_slot1_29_22, + OPERAND_fld_ae8_slot1_29_23, + OPERAND_fld_ae8_slot1_29_5, + OPERAND_fld_ae8_slot1_29_8, + OPERAND_fld_ae8_slot1_29_9, + OPERAND_fld_ae8_slot1_3_0, + OPERAND_fld_ae8_slot1_3_3, + OPERAND_fld_ae8_slot1_4_0, + OPERAND_fld_ae8_slot1_7_4, + OPERAND_fld_ae8_slot2_19_10, + OPERAND_fld_ae8_slot2_19_15, + OPERAND_fld_ae8_slot2_33_15, + OPERAND_fld_ae8_slot2_33_25, + OPERAND_fld_ae8_slot2_33_9, + OPERAND_fld_ae8_slot2_34_30, + OPERAND_fld_ae8_slot2_39_35, + OPERAND_fld_ae8_slot2_44_35, + OPERAND_fld_ae8_slot2_58_34, + OPERAND_fld_ae8_slot2_58_35, + OPERAND_fld_ae8_slot2_58_40, + OPERAND_fld_ae8_slot2_58_50, + OPERAND_fld_ae8_slot2_8_0, + OPERAND_fld_ae8_slot2_9_0, + OPERAND_fld_ae_sem_mul_nn_c0, + OPERAND_fld_ae_sem_mul_nn_c1, + OPERAND_fld_ae_sem_mul_nn_c2, + OPERAND_fld_ae_sem_mul_nn_c3, + OPERAND_fld_ae_sem_mul_nn_q0, + OPERAND_fld_ae_sem_mul_nn_q1, + OPERAND_fld_ae_sem_mul_nn_q2, + OPERAND_fld_ae_sem_mul_nn_q3, + OPERAND_fld_ae_sem_mul_nn_v0, + OPERAND_fld_ae_sem_mul_nn_v1, + OPERAND_fld_ae_sem_mul_nn_v2, + OPERAND_fld_ae_sem_mul_nn_v3, + OPERAND_fld_ae9_slot0_0_0, + OPERAND_fld_ae9_slot0_12_12, + OPERAND_fld_ae9_slot0_12_5, + OPERAND_fld_ae9_slot0_12_8, + OPERAND_fld_ae9_slot0_17_13, + OPERAND_fld_ae9_slot0_17_4, + OPERAND_fld_ae9_slot0_17_8, + OPERAND_fld_ae9_slot0_27_10, + OPERAND_fld_ae9_slot0_27_12, + OPERAND_fld_ae9_slot0_27_13, + OPERAND_fld_ae9_slot0_27_16, + OPERAND_fld_ae9_slot0_27_17, + OPERAND_fld_ae9_slot0_27_18, + OPERAND_fld_ae9_slot0_27_19, + OPERAND_fld_ae9_slot0_27_20, + OPERAND_fld_ae9_slot0_27_22, + OPERAND_fld_ae9_slot0_27_23, + OPERAND_fld_ae9_slot0_27_3, + OPERAND_fld_ae9_slot0_27_8, + OPERAND_fld_ae9_slot0_2_0, + OPERAND_fld_ae9_slot0_3_0, + OPERAND_fld_ae9_slot0_7_0, + OPERAND_fld_ae9_slot0_7_4, + OPERAND_fld_ae9_slot0_7_5, + OPERAND_fld_ae9_slot0_7_6, + OPERAND_fld_ae9_slot0_7_7, + OPERAND_fld_ae9_slot0_8_4, + OPERAND_fld_ae9_slot0_8_5, + OPERAND_fld_ae9_slot0_9_5, + OPERAND_fld_ae9_slot1_17_13, + OPERAND_fld_ae9_slot1_17_8, + OPERAND_fld_ae9_slot1_1_0, + OPERAND_fld_ae9_slot1_26_12, + OPERAND_fld_ae9_slot1_26_13, + OPERAND_fld_ae9_slot1_26_16, + OPERAND_fld_ae9_slot1_26_17, + OPERAND_fld_ae9_slot1_26_18, + OPERAND_fld_ae9_slot1_26_2, + OPERAND_fld_ae9_slot1_26_20, + OPERAND_fld_ae9_slot1_26_22, + OPERAND_fld_ae9_slot1_26_23, + OPERAND_fld_ae9_slot1_26_8, + OPERAND_fld_ae9_slot1_26_9, + OPERAND_fld_ae9_slot1_3_0, + OPERAND_fld_ae9_slot1_3_2, + OPERAND_fld_ae9_slot1_3_3, + OPERAND_fld_ae9_slot1_7_4, + OPERAND_fld_ae9_slot2_24_14, + OPERAND_fld_ae9_slot2_24_15, + OPERAND_fld_ae9_slot2_24_20, + OPERAND_fld_ae9_slot2_33_14, + OPERAND_fld_ae9_slot2_33_15, + OPERAND_fld_ae9_slot2_33_20, + OPERAND_fld_ae9_slot2_33_25, + OPERAND_fld_ae9_slot2_33_26, + OPERAND_fld_ae9_slot2_33_28, + OPERAND_fld_ae9_slot2_33_30, + OPERAND_fld_ae9_slot2_33_9, + OPERAND_fld_ae9_slot2_4_0, + OPERAND_fld_ae9_slot2_5_0, + OPERAND_fld_ae9_slot2_6_0, + OPERAND_fld_ae9_slot2_8_0, + OPERAND_fld_ae9_slot2_9_0, + OPERAND_fld_ae9_slot2_9_5, + OPERAND_fld_ae9_slot2_9_9, + OPERAND_fld_ae_sem_hpfma_vp, + OPERAND_fld_ae_sem_hpfma_vu, + OPERAND_fld_ae_sem_spfma_vu, + OPERAND_fld_ae9_slot3_19_15, + OPERAND_fld_ae9_slot3_24_20, + OPERAND_fld_ae9_slot3_31_14, + OPERAND_fld_ae9_slot3_31_15, + OPERAND_fld_ae9_slot3_31_20, + OPERAND_fld_ae9_slot3_31_25, + OPERAND_fld_ae9_slot3_31_26, + OPERAND_fld_ae9_slot3_31_28, + OPERAND_fld_ae9_slot3_31_7, + OPERAND_fld_ae9_slot3_4_0, + OPERAND_fld_ae9_slot3_4_3, + OPERAND_fld_ae9_slot3_4_4, + OPERAND_fld_ae9_slot3_6_0, + OPERAND_fld_ae9_slot3_9_0, + OPERAND_fld_ae9_slot3_9_5, + OPERAND_fld_ae10_slot0_17_13, + OPERAND_fld_ae10_slot0_17_4, + OPERAND_fld_ae10_slot0_17_8, + OPERAND_fld_ae10_slot0_24_0, + OPERAND_fld_ae10_slot0_24_10, + OPERAND_fld_ae10_slot0_24_12, + OPERAND_fld_ae10_slot0_24_13, + OPERAND_fld_ae10_slot0_24_16, + OPERAND_fld_ae10_slot0_24_17, + OPERAND_fld_ae10_slot0_24_18, + OPERAND_fld_ae10_slot0_24_20, + OPERAND_fld_ae10_slot0_24_8, + OPERAND_fld_ae10_slot0_3_0, + OPERAND_fld_ae10_slot0_7_4, + OPERAND_fld_ae10_slot0_7_6, + OPERAND_fld_ae10_slot0_7_7, + OPERAND_fld_ae10_slot0_8_4, + OPERAND_fld_ae10_slot1_0_0, + OPERAND_fld_ae10_slot1_17_13, + OPERAND_fld_ae10_slot1_17_8, + OPERAND_fld_ae10_slot1_25_1, + OPERAND_fld_ae10_slot1_25_12, + OPERAND_fld_ae10_slot1_25_13, + OPERAND_fld_ae10_slot1_25_16, + OPERAND_fld_ae10_slot1_25_17, + OPERAND_fld_ae10_slot1_25_18, + OPERAND_fld_ae10_slot1_25_20, + OPERAND_fld_ae10_slot1_25_22, + OPERAND_fld_ae10_slot1_25_23, + OPERAND_fld_ae10_slot1_25_8, + OPERAND_fld_ae10_slot1_25_9, + OPERAND_fld_ae10_slot1_3_0, + OPERAND_fld_ae10_slot1_3_2, + OPERAND_fld_ae10_slot1_3_3, + OPERAND_fld_ae10_slot1_7_4, + OPERAND_fld_ae10_slot2_24_20, + OPERAND_fld_ae10_slot2_29_20, + OPERAND_fld_ae10_slot2_29_25, + OPERAND_fld_ae10_slot2_34_10, + OPERAND_fld_ae10_slot2_34_14, + OPERAND_fld_ae10_slot2_34_15, + OPERAND_fld_ae10_slot2_34_20, + OPERAND_fld_ae10_slot2_34_25, + OPERAND_fld_ae10_slot2_34_30, + OPERAND_fld_ae10_slot2_34_31, + OPERAND_fld_ae10_slot2_34_33, + OPERAND_fld_ae10_slot2_4_0, + OPERAND_fld_ae10_slot2_9_0, + OPERAND_fld_ae10_slot2_9_5, + OPERAND_fld_ae_sem_hpfma_vq, + OPERAND_fld_ae_sem_spfma_vq, + OPERAND_fld_ae10_slot3_19_15, + OPERAND_fld_ae10_slot3_29_20, + OPERAND_fld_ae10_slot3_29_25, + OPERAND_fld_ae10_slot3_34_10, + OPERAND_fld_ae10_slot3_34_14, + OPERAND_fld_ae10_slot3_34_15, + OPERAND_fld_ae10_slot3_34_20, + OPERAND_fld_ae10_slot3_34_25, + OPERAND_fld_ae10_slot3_34_30, + OPERAND_fld_ae10_slot3_34_31, + OPERAND_fld_ae10_slot3_34_33, + OPERAND_fld_ae10_slot3_4_0, + OPERAND_fld_ae10_slot3_4_3, + OPERAND_fld_ae10_slot3_4_4, + OPERAND_fld_ae10_slot3_9_0, + OPERAND_fld_ae10_slot3_9_5, + OPERAND_fld_ae4_slot0_22_0, + OPERAND_fld_ae4_slot0_22_12, + OPERAND_fld_ae4_slot0_22_13, + OPERAND_fld_ae4_slot0_22_16, + OPERAND_fld_ae4_slot0_22_17, + OPERAND_fld_ae4_slot0_22_18, + OPERAND_fld_ae4_slot0_22_20, + OPERAND_fld_ae4_slot0_22_6, + OPERAND_fld_ae4_slot0_22_8, + OPERAND_fld_ae4_slot0_3_0, + OPERAND_fld_ae4_slot0_3_1, + OPERAND_fld_ae4_slot0_4_4, + OPERAND_fld_ae4_slot0_7_4, + OPERAND_fld_ae4_slot1_22_0, + OPERAND_fld_ae4_slot1_22_12, + OPERAND_fld_ae4_slot1_22_13, + OPERAND_fld_ae4_slot1_22_16, + OPERAND_fld_ae4_slot1_22_17, + OPERAND_fld_ae4_slot1_22_18, + OPERAND_fld_ae4_slot1_22_8, + OPERAND_fld_ae4_slot1_3_0, + OPERAND_fld_ae4_slot1_3_1, + OPERAND_fld_ae4_slot1_7_4, + OPERAND_fld_ae4_slot2_23_0, + OPERAND_fld_ae4_slot2_23_12, + OPERAND_fld_ae4_slot2_23_15, + OPERAND_fld_ae4_slot2_23_17, + OPERAND_fld_ae4_slot2_23_20, + OPERAND_fld_ae4_slot2_4_0, + OPERAND_fld_ae4_slot2_9_5, + OPERAND_fld_ae4_slot3_14_10, + OPERAND_fld_ae4_slot3_19_15, + OPERAND_fld_ae4_slot3_19_19, + OPERAND_fld_ae4_slot3_19_5, + OPERAND_fld_ae4_slot3_27_20, + OPERAND_fld_ae4_slot3_27_25, + OPERAND_fld_ae4_slot3_27_3, + OPERAND_fld_ae4_slot3_2_0, + OPERAND_fld_ae4_slot3_9_0, + OPERAND_fld_ae4_slot3_9_5, + OPERAND_fld_ae4_slot4_22_0, + OPERAND_fld_ae4_slot4_22_15, + OPERAND_fld_ae4_slot4_22_20, + OPERAND_fld_ae4_slot4_9_5, + OPERAND_fld_Inst_11_8, + OPERAND_fld_Inst_12_12, + OPERAND_fld_Inst_12_8, + OPERAND_fld_Inst_13_8, + OPERAND_fld_Inst_15_12, + OPERAND_fld_Inst_19_17, + OPERAND_fld_Inst_19_18, + OPERAND_fld_Inst_23_12, + OPERAND_fld_Inst_23_16, + OPERAND_fld_Inst_4_4, + OPERAND_fld_Inst_5_4, + OPERAND_fld_Inst_7_4, + OPERAND_fld_Inst_7_6, + OPERAND_fld_Inst_7_7, + OPERAND_fld_Inst_9_8, + OPERAND_s3to1 +}; + + +/* Iclass table. */ + +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSRING }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { OPERAND_ars_entry }, 's' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm12x8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { OPERAND_simm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ai4const }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_simm7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8x256 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_label12 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sae }, 'i' }, + { { OPERAND_op2p1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { OPERAND_soffset }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_uimm16x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_simm12b }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ex_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ex_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_getex_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_getex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clrex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_simcall_args[] = { + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimmrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { OPERAND_sas }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_msalp32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sargt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { + { { STATE_LEND }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { + { { STATE_LEND }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { + { { STATE_LEND }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { + { { STATE_LCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MEMCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MEMCTL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MEMCTL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'i' }, + { { STATE_VECBASELOCK }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'm' }, + { { STATE_VECBASELOCK }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'm' }, + { { STATE_VECBASELOCK }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpucfg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpucfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUNUMENTRIES }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpucfg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpucfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUNUMENTRIES }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_salt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_opmode_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_opmode_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_OPMODEECCFENCE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_opmode_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_opmode_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_OPMODEECCFENCE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_opmode_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_opmode_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_OPMODEECCFENCE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_mul16_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_EPC5 }, 'i' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_EPS3 }, 'i' }, + { { STATE_EPS4 }, 'i' }, + { { STATE_EPS5 }, 'i' }, + { { STATE_EPS6 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTERRUPT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { OPERAND_imms }, 'i' }, + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC5 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_VECBASE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_bs }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { + { { OPERAND_bs }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_brall }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_brall }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_brall }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpfb_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpdngrd_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdcw_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdcw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldcw_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldcw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_stateArgs[] = { + { { STATE_PREFCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_stateArgs[] = { + { { STATE_PREFCTL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_stateArgs[] = { + { { STATE_PREFCTL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cacheadrdis_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cacheadrdis_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CACHEADRDIS }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cacheadrdis_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cacheadrdis_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CACHEADRDIS }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cacheadrdis_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cacheadrdis_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CACHEADRDIS }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb0_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wptlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wptlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpuenb_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpuenb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpuenb_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpuenb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_mpuenb_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_mpuenb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ERACCESS }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ERACCESS }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ERACCESS }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { + { { STATE_ERACCESS }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_ERI_RAW_INTERLOCK }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = { + INTERFACE_ERI_RD_In, + INTERFACE_ERI_RD_Out +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { + { { STATE_ERACCESS }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_ERI_RAW_INTERLOCK }, 'o' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = { + INTERFACE_ERI_WR_In, + INTERFACE_ERI_WR_Out +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_1_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_2_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_3_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'i' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'o' }, + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = { + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = { + { { STATE_AE_BITHEAD }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_TABLESIZE }, 'i' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = { + { { STATE_AE_BITPTR }, 'o' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cw_sd_no_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cw_sd_no_stateArgs[] = { + { { STATE_AE_CWRAP }, 'i' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cw_sd_no_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cw_sd_no_stateArgs[] = { + { { STATE_AE_CWRAP }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin0_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin0_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend0_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend0_stateArgs[] = { + { { STATE_AE_CEND0 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin1_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend1_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin2_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend2_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_sext16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_zext16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_zext8_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_clamps16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_fcr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fcr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = { + { { STATE_RoundMode }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_fsr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = { + { { STATE_InvalidFlag }, 'i' }, + { { STATE_DivZeroFlag }, 'i' }, + { { STATE_OverflowFlag }, 'i' }, + { { STATE_UnderflowFlag }, 'i' }, + { { STATE_InexactFlag }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fsr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = { + { { STATE_InvalidFlag }, 'o' }, + { { STATE_DivZeroFlag }, 'o' }, + { { STATE_OverflowFlag }, 'o' }, + { { STATE_UnderflowFlag }, 'o' }, + { { STATE_InexactFlag }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { + INTERFACE_IMPWIRE +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_OVERFLOW_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_OVERFLOW_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_OVERFLOW_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_OVERFLOW_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SAR_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SAR_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SAR_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SAR_stateArgs[] = { + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITPTR_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITPTR_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITPTR_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITPTR_stateArgs[] = { + { { STATE_AE_BITPTR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITSUSED_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITSUSED_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITSUSED_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITSUSED_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_TABLESIZE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_TABLESIZE_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_TABLESIZE_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_TABLESIZE_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_FIRST_TS_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_FIRST_TS_stateArgs[] = { + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_FIRST_TS_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_FIRST_TS_stateArgs[] = { + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_NEXTOFFSET_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_NEXTOFFSET_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_NEXTOFFSET_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_NEXTOFFSET_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SEARCHDONE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SEARCHDONE_stateArgs[] = { + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SEARCHDONE_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SEARCHDONE_stateArgs[] = { + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_CWRAP_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_CWRAP_stateArgs[] = { + { { STATE_AE_CWRAP }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_CWRAP_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_CWRAP_stateArgs[] = { + { { STATE_AE_CWRAP }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64neg }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RI_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64half }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_I_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_IP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_X_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_XP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_I_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_IP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_X_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_XP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_I_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_IP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_X_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_XP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_I_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_IP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_X_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_XP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ZALIGN64_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_ZALIGN64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LALIGN64_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LALIGN64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SALIGN64_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SALIGN64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVALIGN_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_vu }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVALIGN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA64_PP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA64_PP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8NEG_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8NEG_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64POS_FP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64POS_FP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64NEG_FP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64NEG_FP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDICIRC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_end }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_I_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_X_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_I_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_X_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RA64S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24X2RA64S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S24X2RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RA32S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RA32S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDBRBA32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_aoe }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ab }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ai }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_L_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BITSWAP_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_aoe }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ab }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32JS_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32JS_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32JS_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32JS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_H_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_H_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_L_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDRNG32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBRNG32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RNG32X2_args[] = { + { { OPERAND_opnd_ae_sem_rng_d }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RNG32X2_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_immed }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_N_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_immed_N }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_N_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHORTSWAP_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHORTSWAP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAB4_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAB2_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAB_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA1X2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVB2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVB4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT16X4_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF16X4_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT32X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF32X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARA7X2_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARA7X2_stateArgs[] = { + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARD7_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARD7_stateArgs[] = { + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVASAR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_MOVASAR_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVI_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_movi_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24A32X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24A32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT16X4_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT16X4_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_10_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_10_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_10_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_10_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LL_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LH_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HL_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HH_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24Q48X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24Q48X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32X2F64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32X2F64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32X2F64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32X2F64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32F64S_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32F64S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32F64S_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32F64S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP16_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SSYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SSYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SSYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SSYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2SYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2SYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2ASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2ASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24SYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24SYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24ASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24ASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOV_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT64_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF64_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56A32S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56A32S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48A32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48A32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64A32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64A32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64F32_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64F32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT48S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT48S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATQ56S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT24S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCQ32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCQ32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48SYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48SYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48ASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48ASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32Q48_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32Q48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_3_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_1_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_0_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRA64_32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRA64_32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR32_args[] = { + { { OPERAND_opnd_ae_sem_pks_d }, 'm' }, + { { OPERAND_opnd_ae_sem_pks_s }, 'i' }, + { { OPERAND_opnd_ae_sem_pks_pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR24_args[] = { + { { OPERAND_opnd_ae_sem_pks_d }, 'm' }, + { { OPERAND_opnd_ae_sem_pks_s }, 'i' }, + { { OPERAND_opnd_ae_sem_pks_pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR24_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSRF32_args[] = { + { { OPERAND_opnd_ae_sem_pks_d }, 'm' }, + { { OPERAND_opnd_ae_sem_pks_s }, 'i' }, + { { OPERAND_opnd_ae_sem_pks_pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSRF32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR16_args[] = { + { { OPERAND_opnd_ae_sem_pks_d }, 'm' }, + { { OPERAND_opnd_ae_sem_pks_s }, 'i' }, + { { OPERAND_opnd_ae_sem_pks_pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR16_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD24S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB24S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG24S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS24S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG16S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS16S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16JS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16JS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16JS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16JS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16JS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16JS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16JS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16JS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT16_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE16_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ16_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINMAX32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINMAX32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINMAX16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINMAX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSQ56S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBSQ56S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEGSQ56S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEGSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABSSQ56S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABSSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_AND_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_AND_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NAND_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NAND_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_OR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_OR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_XOR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_XOR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16R_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32R_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI16S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA16S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16RS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32RS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASQ56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLSQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLSQ56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRASQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRASQ56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAAQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAAQ56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLAQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLAQ56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAAQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAAQ56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS64_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS64_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAISQ56S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAISQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASSQ56S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAASQ56S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAASQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT64_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE64_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ64_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA64_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ16_0_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ16_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ32_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32U_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32U_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32U_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32U_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32U_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32U_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_33_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_33_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_21_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_21_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_31_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_31_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_30_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_30_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_10_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_10_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_20_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_20_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_11_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_11_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_33_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_33_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_21_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_21_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_31_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_31_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_30_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_30_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_10_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_10_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_20_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_20_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_11_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_11_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_33_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_33_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_21_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_21_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_31_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_31_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_30_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_30_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_10_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_10_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_20_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_20_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_11_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_11_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16S_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16S_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16S_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16S_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16S_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16S_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2R_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2R_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2R_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2TS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2TS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2TS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2TS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2TS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2TS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC24RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC24RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC24RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC24RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16X4SS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16X4SS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16X4SS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16X4SS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16X4SS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16X4SS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC16RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC16RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC16RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC16RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16JS_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16JS_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG16RAS_S1_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_vs }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG16RAS_S1_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG16RAS_S2_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_vs }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG16RAS_S2_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CONJ16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CONJ16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAFQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAFQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAFQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAFQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16_00_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16_00_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_H_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHA32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_aoe }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ai }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL32T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL32T_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16T_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IP_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IP_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC1_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDSHT_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDSHT_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_opnd_ae_sem_lb_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ae_sem_lb_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBS_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBS_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBSI_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_opnd_ae_sem_lb_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBSI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ARDECNORM16_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_opnd_AE_ARDECNORM16_ar_u }, 'm' }, + { { OPERAND_arr }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL32T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL32T_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL16T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL16T_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC1_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC1_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IP_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IP_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IP_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAE_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ei }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAE_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEA_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_eo }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ar_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEEP_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_eo }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ei }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEEP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT72_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ep1 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ep1 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72X64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72X64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72X64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72X64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32EP_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32EP_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32EP_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32EP_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32EP_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32EP_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32USEP_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32USEP_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32USEP_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32USEP_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI72_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_e }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI72_args[] = { + { { OPERAND_opnd_ae_sem_shift_e }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_e }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16SI_N_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_uimm2x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16UI_N_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_uimm2x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16I_N_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_uimm2x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LALIGN128_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LALIGN128_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SALIGN128_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SALIGN128_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA128_PP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA128_PP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA128POS_FP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA128POS_FP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X4S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X4S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X4U_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X4U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS8S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG8S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD8S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB8S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_art }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_art }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_art }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU16X4_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU16X4_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT32X2_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT32X2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU32X2_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU32X2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT8X8X16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT8X8X16_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU8X8X16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU8X8X16_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT8X4X32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT8X4X32_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU8X4X32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU8X4X32_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X8F16SSYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X8F16SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X8F16SASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X8F16SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X4F32SSYM_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X4F32SSYM_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X4F32SASYM_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X4F32SASYM_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA8_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD8_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDX2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDX2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32J_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32J_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW8U_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW8U_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW8U_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_HL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_HL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_HL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_HL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_HL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_HL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2R_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2R_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2R_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2R_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2R_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2R_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2R_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2R_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2R_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2R_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2R_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2R_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2P32X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2P32X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS2P32X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS2P32X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2P32X4T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2P32X4T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS2P32X4T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS2P32X4T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA32X2_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA32X2_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS32X2_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS32X2_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA32X2_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA32X2_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32X2_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32X2_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULCJ32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULCJ32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULACJ32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULACJ32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULADDF32RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULADDF32RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULADDF32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULADDF32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSUBF32RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSUBF32RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSUBF32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSUBF32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULCJ32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULCJ32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULACJ32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULACJ32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2D32X2WS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2D32X2WS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2C16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2C16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2C16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2C16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ16RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ16RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ16RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ16RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD16X16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD16X16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA2D16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA2D16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA2D16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA2D16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS2D16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS2D16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS2D16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS2D16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA2D16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA2D16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA2D16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA2D16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS2D16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS2D16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS2D16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS2D16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD16X16X4WS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD16X16X4WS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q16X8_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q16X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q16X8_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q16X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q8_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q8_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULPC32X16X2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULPC32X16X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAPC32X16X2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAPC32X16X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFPC32X16X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFPC32X16X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFPC32X16X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFPC32X16X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFPCJ32X16X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFPCJ32X16X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFPCJ32X16X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFPCJ32X16X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2Q32X16_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2Q32X16_FIR_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2Q32X16_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2Q32X16_FIR_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2Q32X16_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2Q32X16_FIR_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2Q32X16_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2Q32X16_FIR_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI8_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI8R_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI8R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI8_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI8_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI8S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA8_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA8_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA8S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA8RS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA8RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA8S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI16_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI16_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA16_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA16_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16SYM_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16SYM_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16SYMS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16SYMS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32SYM_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32SYM_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32SYMS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32SYMS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAV16RS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAV16RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAV32RS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAV32RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8S_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8S_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8S_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8S_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8U_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8U_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8U_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8US_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8US_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8US_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8US_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8U_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8U_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8U_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8US_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8US_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8US_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8US_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16S_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16S_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16U_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16US_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16US_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16U_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16US_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16US_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8S_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8S_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8U_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8US_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8US_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8U_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8US_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8US_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL8X8_args[] = { + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHFL8X8_args[] = { + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHFL8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16X4_args[] = { + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHFL16X4_args[] = { + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHFL16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DSEL8X8_args[] = { + { { OPERAND_opnd_ae_sem_select_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DSEL8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DSEL16X4_args[] = { + { { OPERAND_opnd_ae_sem_select_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DSEL16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL8X8I_args[] = { + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_isel }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL8X8I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMAX8X8_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMAX8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMIN8X8_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMIN8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMAX16X4_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMAX16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMIN16X4_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMIN16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SORT16X4_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SORT16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD8X8_H_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD8X8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA8X8_H_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'm' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA8X8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD8X8_L_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD8X8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA8X8_L_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'm' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA8X8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD16X4_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA16X4_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'm' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX8X8_H_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX8X8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX8X8_L_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX8X8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN8X8_H_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN8X8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN8X8_L_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN8X8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX16X4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN16X4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX32X2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN32X2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDINV16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDINV16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDINV32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDINV32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT16X8_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT16X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT8X16_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT8X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT8X16_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT8X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBD1X4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBD1X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBD1X2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBD1X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVNEG32S_T_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVNEG32S_T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDEXT_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDEXT_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVADEXT_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_a }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVADEXT_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVADEXT_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_a }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVADEXT_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA16X4_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_d }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ32X4_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_d }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ32X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA32X4_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_d }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA32X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI16X4F32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI16X4F32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI16X4F64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI16X4F64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16X4F32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16X4F32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16X4F64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16X4F64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDC32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDC32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBC32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBC32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDC32U_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDC32U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBC32U_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBC32U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPADD16_H_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPADD16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPSUB16_H_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPSUB16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPADD16_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPADD16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPSUB16_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPSUB16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCEXP32_H_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCEXP32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCEXP32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCEXP32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG16_args[] = { + { { OPERAND_opnd_ae_sem_rng_a }, 'o' }, + { { OPERAND_opnd_ae_sem_rng_art }, 'o' }, + { { OPERAND_opnd_ae_sem_rng_i2 }, 'i' }, + { { OPERAND_opnd_ae_sem_rng_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG16_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG32_args[] = { + { { OPERAND_opnd_ae_sem_rng_a }, 'o' }, + { { OPERAND_opnd_ae_sem_rng_art }, 'o' }, + { { OPERAND_opnd_ae_sem_rng_i2 }, 'i' }, + { { OPERAND_opnd_ae_sem_rng_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RNG32X4_args[] = { + { { OPERAND_opnd_ae_sem_rng_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_rng_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RNG32X4_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAV8X8X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAV8X8X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAV16X4X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAV16X4X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAV8X8X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAV8X8X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAV16X4X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAV16X4X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVZBVCDR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVZBVCDR_stateArgs[] = { + { { STATE_AE_ZBIASV8 }, 'o' }, + { { STATE_AE_ZBIASC8 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDRZBVC_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDRZBVC_stateArgs[] = { + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAVUNSQZ8X8_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAVUNSQZ8X8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAVUNSQZ16X4_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAVUNSQZ16X4_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_HL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_HL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_HL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_HL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_L_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_L_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_H_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_L_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_L_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_H_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVFCRFSRV_args[] = { + { { OPERAND_opnd_ae_sem_movfpstate_v }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVFCRFSRV_stateArgs[] = { + { { STATE_RoundMode }, 'o' }, + { { STATE_InvalidFlag }, 'o' }, + { { STATE_DivZeroFlag }, 'o' }, + { { STATE_OverflowFlag }, 'o' }, + { { STATE_UnderflowFlag }, 'o' }, + { { STATE_InexactFlag }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVVFCRFSR_args[] = { + { { OPERAND_opnd_ae_sem_movfpstate_v }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_MOVVFCRFSR_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_InvalidFlag }, 'i' }, + { { STATE_DivZeroFlag }, 'i' }, + { { STATE_OverflowFlag }, 'i' }, + { { STATE_UnderflowFlag }, 'i' }, + { { STATE_InexactFlag }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVT_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVT_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVF_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVF_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVEQZ_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVEQZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVNEZ_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVNEZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVGEZ_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVGEZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVLTZ_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVLTZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RFR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RFR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WFR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_WFR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBN_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBN_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_S_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_S_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'm' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_S_stateArgs[] = { + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vsM }, 'm' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vsM }, 'm' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MIN_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MIN_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAX_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAX_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUX_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUX_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUX_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUX_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_art }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_art }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_SX2_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_SX2_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_SX2_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_SX2_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FICEIL_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FICEIL_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIFLOOR_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIFLOOR_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIRINT_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIRINT_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIROUND_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIROUND_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FITRUNC_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FITRUNC_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_SX2_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_SX2_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_SX2_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_SX2_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_S_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_S_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_S_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_S_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_S_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CLSFY_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CLSFY_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUM_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUM_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUM_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUM_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDANDSUB_S_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDANDSUB_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDANDSUBJC_S_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDANDSUBJC_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_HL_LH_S_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_HL_LH_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDA_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDA_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FREXP_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vsM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FREXP_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOATEXP_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOATEXP_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUMABS_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUMABS_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUMABS_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUMABS_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUXQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUXQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUXQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUXQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMAXNUM_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMAXNUM_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMINNUM_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMINNUM_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMAXNUMABS_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMAXNUMABS_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMINNUMABS_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMINNUMABS_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_SX2X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_SX2X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_SX2X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_SX2X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_SX2X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUX_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUX_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUX_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUX_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'm' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'm' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CLSFY_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CLSFY_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_H_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_H_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MIN_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MIN_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAX_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAX_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUM_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUM_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUM_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUM_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_H_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FICEIL_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FICEIL_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIFLOOR_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIFLOOR_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIRINT_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIRINT_H_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIROUND_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIROUND_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FITRUNC_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FITRUNC_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vs }, 'm' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP0_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP0_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT16_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT16_H_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT16_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT16_H_stateArgs[] = { + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC16_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_art }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC16_H_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC16_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_art }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC16_H_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT16_HX4_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT16_HX4_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT16_HX4_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT16_HX4_stateArgs[] = { + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC16_HX4_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC16_HX4_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC16_HX4_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC16_HX4_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBN_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBN_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_H_stateArgs[] = { + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RMINNUM_H_args[] = { + { { OPERAND_opnd_ae_sem_hprminmaxnum_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hprminmaxnum_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RMINNUM_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RMAXNUM_H_args[] = { + { { OPERAND_opnd_ae_sem_hprminmaxnum_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hprminmaxnum_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RMAXNUM_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_HX4X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_HX4X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_HX4X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_HX4X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_HX4X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULQ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULQ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDQ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDQ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULCNVH_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULCNVH_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULACNVH_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULACNVH_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULCNVL_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULCNVL_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULACNVL_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULACNVL_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_iclass_internal iclasses[] = { + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_threadptr_args, + 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, + { 1, Iclass_wur_threadptr_args, + 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_loop_args, + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_loopz_args, + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32ex_args, + 1, Iclass_xt_iclass_l32ex_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_s32ex_args, + 1, Iclass_xt_iclass_s32ex_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_getex_args, + 1, Iclass_xt_iclass_getex_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_clrex */, + 1, Iclass_xt_iclass_clrex_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_simcall_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32nb_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lend_args, + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lend_args, + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lend_args, + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lcount_args, + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lcount_args, + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lcount_args, + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lbeg_args, + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lbeg_args, + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lbeg_args, + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_memctl_args, + 3, Iclass_xt_iclass_rsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_memctl_args, + 3, Iclass_xt_iclass_wsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_memctl_args, + 3, Iclass_xt_iclass_xsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid0_args, + 2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_configid0_args, + 2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid1_args, + 2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc3_args, + 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc3_args, + 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc3_args, + 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave3_args, + 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave3_args, + 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave3_args, + 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc4_args, + 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc4_args, + 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc4_args, + 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave4_args, + 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave4_args, + 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave4_args, + 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc5_args, + 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc5_args, + 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc5_args, + 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave5_args, + 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave5_args, + 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave5_args, + 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc6_args, + 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc6_args, + 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc6_args, + 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave6_args, + 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave6_args, + 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave6_args, + 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps3_args, + 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps3_args, + 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps3_args, + 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps4_args, + 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps4_args, + 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps4_args, + 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps5_args, + 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps5_args, + 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps5_args, + 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps6_args, + 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps6_args, + 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps6_args, + 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc0_args, + 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc0_args, + 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc0_args, + 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc1_args, + 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc1_args, + 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc1_args, + 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc2_args, + 3, Iclass_xt_iclass_rsr_misc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc2_args, + 3, Iclass_xt_iclass_wsr_misc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc2_args, + 3, Iclass_xt_iclass_xsr_misc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc3_args, + 3, Iclass_xt_iclass_rsr_misc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc3_args, + 3, Iclass_xt_iclass_wsr_misc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc3_args, + 3, Iclass_xt_iclass_xsr_misc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_vecbase_args, + 4, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_vecbase_args, + 4, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_vecbase_args, + 4, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_mpucfg_args, + 3, Iclass_xt_iclass_rsr_mpucfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mpucfg_args, + 3, Iclass_xt_iclass_wsr_mpucfg_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_salt_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_opmode_args, + 3, Iclass_xt_iclass_rsr_opmode_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_opmode_args, + 3, Iclass_xt_iclass_wsr_opmode_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_opmode_args, + 3, Iclass_xt_iclass_xsr_opmode_stateArgs, 0, 0 }, + { 3, Iclass_xt_mul16_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 19, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka0_args, + 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka0_args, + 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka0_args, + 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc0_args, + 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc0_args, + 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc0_args, + 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka1_args, + 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka1_args, + 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka1_args, + 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc1_args, + 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc1_args, + 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc1_args, + 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka0_args, + 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka0_args, + 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka0_args, + 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka1_args, + 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka1_args, + 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka1_args, + 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreakenable_args, + 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreakenable_args, + 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreakenable_args, + 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_lddr32_p_args, + 5, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sddr32_p_args, + 4, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfdo_args, + 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 2, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mmid_args, + 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_bbool1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbranch_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bmove_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_RSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_WSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_XSR_BR_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare1_args, + 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare1_args, + 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare1_args, + 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare2_args, + 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare2_args, + 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare2_args, + 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_lock_args, + 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_inv_args, + 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_licx_args, + 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sicx_args, + 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_dcache_dyn_args, + 2, Iclass_xt_iclass_dcache_dyn_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_ind_args, + 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_inv_args, + 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dpf_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dpfb_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_bpfnxt */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dpdngrd_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_bpfctl */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_lock_args, + 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sdct_args, + 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ldct_args, + 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sdcw_args, + 2, Iclass_xt_iclass_sdcw_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ldcw_args, + 2, Iclass_xt_iclass_ldcw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prefctl_args, + 1, Iclass_xt_iclass_rsr_prefctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_prefctl_args, + 1, Iclass_xt_iclass_wsr_prefctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_prefctl_args, + 1, Iclass_xt_iclass_xsr_prefctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cacheadrdis_args, + 4, Iclass_xt_iclass_wsr_cacheadrdis_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cacheadrdis_args, + 3, Iclass_xt_iclass_rsr_cacheadrdis_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cacheadrdis_args, + 4, Iclass_xt_iclass_xsr_cacheadrdis_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rptlb0_args, + 3, Iclass_xt_iclass_rptlb0_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rptlb_args, + 2, Iclass_xt_iclass_rptlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_wptlb_args, + 4, Iclass_xt_iclass_wptlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_mpuenb_args, + 3, Iclass_xt_iclass_rsr_mpuenb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mpuenb_args, + 4, Iclass_xt_iclass_wsr_mpuenb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_mpuenb_args, + 4, Iclass_xt_iclass_xsr_mpuenb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cpenable_args, + 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cpenable_args, + 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cpenable_args, + 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_clamp_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_minmax_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_sx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32ai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32ri_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_atomctl_args, + 4, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_atomctl_args, + 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_atomctl_args, + 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_div_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eraccess_args, + 3, Iclass_xt_iclass_rsr_eraccess_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eraccess_args, + 3, Iclass_xt_iclass_wsr_eraccess_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eraccess_args, + 3, Iclass_xt_iclass_xsr_eraccess_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rer_args, + 4, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs }, + { 2, Iclass_xt_iclass_wer_args, + 4, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs }, + { 2, Iclass_xt_iclass_wb15_0_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_1_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_2_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_3_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_ae_ovf_sar_args, + 3, Iclass_rur_ae_ovf_sar_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_ovf_sar_args, + 3, Iclass_wur_ae_ovf_sar_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_bithead_args, + 2, Iclass_rur_ae_bithead_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_bithead_args, + 2, Iclass_wur_ae_bithead_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_ts_fts_bu_bp_args, + 5, Iclass_rur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_ts_fts_bu_bp_args, + 5, Iclass_wur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cw_sd_no_args, + 4, Iclass_rur_ae_cw_sd_no_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cw_sd_no_args, + 4, Iclass_wur_ae_cw_sd_no_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cbegin0_args, + 2, Iclass_rur_ae_cbegin0_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cbegin0_args, + 2, Iclass_wur_ae_cbegin0_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cend0_args, + 2, Iclass_rur_ae_cend0_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cend0_args, + 2, Iclass_wur_ae_cend0_stateArgs, 0, 0 }, + { 1, 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}, + { 3, Iclass_AE_S16X4_XC1_args, + 3, Iclass_AE_S16X4_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_I_args, + 1, Iclass_AE_S16X4_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_IP_args, + 1, Iclass_AE_S16X4_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_X_args, + 1, Iclass_AE_S16X4_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_XP_args, + 1, Iclass_AE_S16X4_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S8X8_XC_args, + 3, Iclass_AE_S8X8_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S8X8_XC1_args, + 3, Iclass_AE_S8X8_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S8X8_I_args, + 1, Iclass_AE_S8X8_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S8X8_IP_args, + 1, Iclass_AE_S8X8_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S8X8_X_args, + 1, Iclass_AE_S8X8_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S8X8_XP_args, + 1, Iclass_AE_S8X8_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16M_L_XC_args, + 3, Iclass_AE_S16M_L_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16M_L_XC1_args, + 3, Iclass_AE_S16M_L_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16M_L_I_args, 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Iclass_AE_S16X4X2RNG_I_args, + 2, Iclass_AE_S16X4X2RNG_I_stateArgs, 0, 0 }, + { 4, Iclass_AE_S16X4X2RNG_IP_args, + 2, Iclass_AE_S16X4X2RNG_IP_stateArgs, 0, 0 }, + { 4, Iclass_AE_S16X4X2RNG_X_args, + 2, Iclass_AE_S16X4X2RNG_X_stateArgs, 0, 0 }, + { 4, Iclass_AE_S16X4X2RNG_XP_args, + 2, Iclass_AE_S16X4X2RNG_XP_stateArgs, 0, 0 }, + { 1, Iclass_AE_ZALIGN64_args, + 1, Iclass_AE_ZALIGN64_stateArgs, 0, 0 }, + { 3, Iclass_AE_LALIGN64_I_args, + 1, Iclass_AE_LALIGN64_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_SALIGN64_I_args, + 1, Iclass_AE_SALIGN64_I_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVALIGN_args, + 1, Iclass_AE_MOVALIGN_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA64_PP_args, + 1, Iclass_AE_LA64_PP_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24POS_PC_args, + 3, Iclass_AE_LA24POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24NEG_PC_args, + 3, Iclass_AE_LA24NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24POS_PC1_args, + 3, Iclass_AE_LA24POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24NEG_PC1_args, + 3, Iclass_AE_LA24NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24X2POS_PC_args, + 3, Iclass_AE_LA24X2POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24X2NEG_PC_args, + 3, Iclass_AE_LA24X2NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24X2POS_PC1_args, + 3, Iclass_AE_LA24X2POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24X2NEG_PC1_args, + 3, Iclass_AE_LA24X2NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2POS_PC_args, + 3, Iclass_AE_LA32X2POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2NEG_PC_args, + 3, Iclass_AE_LA32X2NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2POS_PC1_args, + 3, Iclass_AE_LA32X2POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2NEG_PC1_args, + 3, Iclass_AE_LA32X2NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2POS_PC2_args, + 3, Iclass_AE_LA32X2POS_PC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4POS_PC_args, + 3, Iclass_AE_LA16X4POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4NEG_PC_args, + 3, Iclass_AE_LA16X4NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4POS_PC1_args, + 3, Iclass_AE_LA16X4POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4NEG_PC1_args, + 3, Iclass_AE_LA16X4NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4POS_PC2_args, + 3, Iclass_AE_LA16X4POS_PC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8POS_PC_args, + 3, Iclass_AE_LA8X8POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8NEG_PC_args, + 3, Iclass_AE_LA8X8NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8POS_PC1_args, + 3, Iclass_AE_LA8X8POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8NEG_PC1_args, + 3, Iclass_AE_LA8X8NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8POS_PC2_args, + 3, Iclass_AE_LA8X8POS_PC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2X2POS_PC_args, + 3, Iclass_AE_LA32X2X2POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2X2POS_PC1_args, + 3, Iclass_AE_LA32X2X2POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2X2POS_PC2_args, + 3, Iclass_AE_LA32X2X2POS_PC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4X2POS_PC_args, + 3, Iclass_AE_LA16X4X2POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4X2POS_PC1_args, + 3, Iclass_AE_LA16X4X2POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4X2POS_PC2_args, + 3, Iclass_AE_LA16X4X2POS_PC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8X2POS_PC_args, + 3, Iclass_AE_LA8X8X2POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8X2POS_PC1_args, + 3, Iclass_AE_LA8X8X2POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8X2POS_PC2_args, + 3, Iclass_AE_LA8X8X2POS_PC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_SA64POS_FP_args, + 1, Iclass_AE_SA64POS_FP_stateArgs, 0, 0 }, + { 2, Iclass_AE_SA64NEG_FP_args, + 1, Iclass_AE_SA64NEG_FP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IC_args, + 3, Iclass_AE_LA32X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IC1_args, + 3, Iclass_AE_LA32X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IC2_args, + 3, Iclass_AE_LA32X2_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IP_args, + 1, Iclass_AE_LA32X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_RIP_args, + 1, Iclass_AE_LA32X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_RIC_args, + 3, Iclass_AE_LA32X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_RIC1_args, + 3, Iclass_AE_LA32X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IC_args, + 3, Iclass_AE_LA16X4_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IC1_args, + 3, Iclass_AE_LA16X4_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IC2_args, + 3, Iclass_AE_LA16X4_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IP_args, + 1, Iclass_AE_LA16X4_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_RIP_args, + 1, Iclass_AE_LA16X4_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_RIC_args, + 3, Iclass_AE_LA16X4_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_RIC1_args, + 3, Iclass_AE_LA16X4_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_IC_args, + 3, Iclass_AE_LA8X8_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_IC1_args, + 3, Iclass_AE_LA8X8_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_IC2_args, + 3, Iclass_AE_LA8X8_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_IP_args, + 1, Iclass_AE_LA8X8_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_RIP_args, + 1, Iclass_AE_LA8X8_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_RIC_args, + 3, Iclass_AE_LA8X8_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_RIC1_args, + 3, Iclass_AE_LA8X8_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_IC_args, + 3, Iclass_AE_LA32X2F24_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_IC1_args, + 3, Iclass_AE_LA32X2F24_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_IP_args, + 1, Iclass_AE_LA32X2F24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_RIP_args, + 1, Iclass_AE_LA32X2F24_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_RIC_args, + 3, Iclass_AE_LA32X2F24_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_RIC1_args, + 3, Iclass_AE_LA32X2F24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_IC_args, + 3, Iclass_AE_LA24_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_IC1_args, + 3, Iclass_AE_LA24_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_IP_args, + 1, Iclass_AE_LA24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_RIP_args, + 1, Iclass_AE_LA24_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_RIC_args, + 3, Iclass_AE_LA24_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_RIC1_args, + 3, Iclass_AE_LA24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_IC_args, + 3, Iclass_AE_LA24X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_IC1_args, + 3, Iclass_AE_LA24X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_IP_args, + 1, Iclass_AE_LA24X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_RIP_args, + 1, Iclass_AE_LA24X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_RIC_args, + 3, Iclass_AE_LA24X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_RIC1_args, + 3, Iclass_AE_LA24X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IC_args, + 3, Iclass_AE_SA32X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IC1_args, + 3, Iclass_AE_SA32X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IC2_args, + 3, Iclass_AE_SA32X2_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IP_args, + 1, Iclass_AE_SA32X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_RIP_args, + 1, Iclass_AE_SA32X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_RIC_args, + 3, Iclass_AE_SA32X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_RIC1_args, + 3, Iclass_AE_SA32X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IC_args, + 3, Iclass_AE_SA16X4_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IC1_args, + 3, Iclass_AE_SA16X4_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IC2_args, + 3, Iclass_AE_SA16X4_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IP_args, + 1, Iclass_AE_SA16X4_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_RIP_args, + 1, Iclass_AE_SA16X4_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_RIC_args, + 3, Iclass_AE_SA16X4_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_RIC1_args, + 3, Iclass_AE_SA16X4_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_IC_args, + 3, Iclass_AE_SA8X8_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_IC1_args, + 3, Iclass_AE_SA8X8_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_IC2_args, + 3, Iclass_AE_SA8X8_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_IP_args, + 1, Iclass_AE_SA8X8_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_RIP_args, + 1, Iclass_AE_SA8X8_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_RIC_args, + 3, Iclass_AE_SA8X8_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_RIC1_args, + 3, Iclass_AE_SA8X8_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_IC_args, + 3, Iclass_AE_SA32X2F24_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_IC1_args, + 3, Iclass_AE_SA32X2F24_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_IP_args, + 1, Iclass_AE_SA32X2F24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_RIP_args, + 1, Iclass_AE_SA32X2F24_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_RIC_args, + 3, Iclass_AE_SA32X2F24_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_RIC1_args, + 3, Iclass_AE_SA32X2F24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_IC_args, + 3, Iclass_AE_SA24_L_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_IC1_args, + 3, Iclass_AE_SA24_L_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_IP_args, + 1, Iclass_AE_SA24_L_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_RIP_args, + 1, Iclass_AE_SA24_L_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_RIC_args, + 3, Iclass_AE_SA24_L_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_RIC1_args, + 3, Iclass_AE_SA24_L_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_IC_args, + 3, Iclass_AE_SA24X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_IC1_args, + 3, Iclass_AE_SA24X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_IP_args, + 1, Iclass_AE_SA24X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_RIP_args, + 1, Iclass_AE_SA24X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_RIC_args, + 3, Iclass_AE_SA24X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_RIC1_args, + 3, Iclass_AE_SA24X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDICIRC_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_ADDCIRC_XC2_args, + 3, Iclass_AE_ADDCIRC_XC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_ADDCIRC_XC1_args, + 3, Iclass_AE_ADDCIRC_XC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_ADDCIRC_XC_args, + 3, Iclass_AE_ADDCIRC_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_I_args, + 2, Iclass_AE_S32RA64S_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_IP_args, + 2, Iclass_AE_S32RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_X_args, + 2, Iclass_AE_S32RA64S_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_XP_args, + 2, Iclass_AE_S32RA64S_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_XC_args, + 4, Iclass_AE_S32RA64S_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_XC1_args, + 4, Iclass_AE_S32RA64S_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_I_args, + 2, Iclass_AE_S24RA64S_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_IP_args, + 2, Iclass_AE_S24RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_X_args, + 2, Iclass_AE_S24RA64S_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_XP_args, + 2, Iclass_AE_S24RA64S_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_XC_args, + 4, Iclass_AE_S24RA64S_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_XC1_args, + 4, Iclass_AE_S24RA64S_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2RA64S_IP_args, + 2, Iclass_AE_S32X2RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24X2RA64S_IP_args, + 2, Iclass_AE_S24X2RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4RA32S_IP_args, + 2, Iclass_AE_S16X4RA32S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDBRBA32_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_S32X2_L_IP_args, + 1, Iclass_AE_S32X2_L_IP_stateArgs, 0, 0 }, + { 2, Iclass_AE_BITSWAP_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MUL32JS_args, + 1, Iclass_AE_MUL32JS_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUB32S_args, + 2, Iclass_AE_ADDANDSUB32S_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUB32JS_args, + 2, Iclass_AE_ADDANDSUB32JS_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUBRNG32_args, + 2, Iclass_AE_ADDANDSUBRNG32_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUBRNG32_H_args, + 2, Iclass_AE_ADDANDSUBRNG32_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUBRNG32_L_args, + 2, Iclass_AE_ADDANDSUBRNG32_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDRNG32_args, + 2, Iclass_AE_ADDRNG32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUBRNG32_args, + 2, Iclass_AE_SUBRNG32_stateArgs, 0, 0 }, + { 1, Iclass_AE_RNG32X2_args, + 2, Iclass_AE_RNG32X2_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL16I_args, + 1, Iclass_AE_SEL16I_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL16I_N_args, + 1, Iclass_AE_SEL16I_N_stateArgs, 0, 0 }, + { 2, Iclass_AE_SHORTSWAP_args, + 1, Iclass_AE_SHORTSWAP_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAB4_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVAB2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVAB_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVBA_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_MOVBA1X2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVBA4_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVBA2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVB2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVB4_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_MOVT16X4_args, + 1, Iclass_AE_MOVT16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVF16X4_args, + 1, Iclass_AE_MOVF16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVT32X2_args, + 1, Iclass_AE_MOVT32X2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVF32X2_args, + 1, Iclass_AE_MOVF32X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVSARA7X2_args, + 2, Iclass_AE_MOVSARA7X2_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVSARD7_args, + 2, Iclass_AE_MOVSARD7_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVASAR_args, + 2, Iclass_AE_MOVASAR_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVDA32X2_args, + 1, Iclass_AE_MOVDA32X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVDA32_args, + 1, Iclass_AE_MOVDA32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVDA16X2_args, + 1, Iclass_AE_MOVDA16X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVDA16_args, + 1, Iclass_AE_MOVDA16_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVI_args, + 1, Iclass_AE_MOVI_stateArgs, 0, 0 }, + { 3, Iclass_AE_TRUNCP24A32X2_args, + 1, Iclass_AE_TRUNCP24A32X2_stateArgs, 0, 0 }, + { 3, Iclass_AE_SAT16X4_args, + 2, Iclass_AE_SAT16X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT32X2F16_32_args, + 1, Iclass_AE_CVT32X2F16_32_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT32X2F16_10_args, + 1, Iclass_AE_CVT32X2F16_10_stateArgs, 0, 0 }, + { 2, Iclass_AE_SEXT32X2D16_32_args, + 1, Iclass_AE_SEXT32X2D16_32_stateArgs, 0, 0 }, + { 2, Iclass_AE_SEXT32X2D16_10_args, + 1, Iclass_AE_SEXT32X2D16_10_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTA32F24S_L_args, + 1, Iclass_AE_CVTA32F24S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTA32F24S_H_args, + 1, Iclass_AE_CVTA32F24S_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_LL_args, + 1, Iclass_AE_CVTP24A16X2_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_LH_args, + 1, Iclass_AE_CVTP24A16X2_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_HL_args, + 1, Iclass_AE_CVTP24A16X2_HL_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_HH_args, + 1, Iclass_AE_CVTP24A16X2_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_TRUNCP24Q48X2_args, + 1, Iclass_AE_TRUNCP24Q48X2_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCA32X2F64S_args, + 2, Iclass_AE_TRUNCA32X2F64S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCI32X2F64S_args, + 2, Iclass_AE_TRUNCI32X2F64S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCA32F64S_L_args, + 2, Iclass_AE_TRUNCA32F64S_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCI32F64S_L_args, + 2, Iclass_AE_TRUNCI32F64S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCP16_args, + 1, Iclass_AE_TRUNCP16_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F64SSYM_args, + 2, Iclass_AE_ROUND32X2F64SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F64SASYM_args, + 2, Iclass_AE_ROUND32X2F64SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F48SSYM_args, + 2, Iclass_AE_ROUND32X2F48SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F48SASYM_args, + 2, Iclass_AE_ROUND32X2F48SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND16X4F32SSYM_args, + 2, Iclass_AE_ROUND16X4F32SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND16X4F32SASYM_args, + 2, Iclass_AE_ROUND16X4F32SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND24X2F48SSYM_args, + 2, Iclass_AE_ROUND24X2F48SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND24X2F48SASYM_args, + 2, Iclass_AE_ROUND24X2F48SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUNDSP16Q48X2SYM_args, + 2, Iclass_AE_ROUNDSP16Q48X2SYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUNDSP16Q48X2ASYM_args, + 2, Iclass_AE_ROUNDSP16Q48X2ASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_MINABS32S_args, + 2, Iclass_AE_MINABS32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAXABS32S_args, + 2, Iclass_AE_MAXABS32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSP16F24SYM_args, + 2, Iclass_AE_ROUNDSP16F24SYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSP16F24ASYM_args, + 2, Iclass_AE_ROUNDSP16F24ASYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOV_args, + 1, Iclass_AE_MOV_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVT64_args, + 1, Iclass_AE_MOVT64_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVF64_args, + 1, Iclass_AE_MOVF64_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTQ56A32S_args, + 1, Iclass_AE_CVTQ56A32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT48A32_args, + 1, Iclass_AE_CVT48A32_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT64A32_args, + 1, Iclass_AE_CVT64A32_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTQ56P32S_L_args, + 1, Iclass_AE_CVTQ56P32S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTQ56P32S_H_args, + 1, Iclass_AE_CVTQ56P32S_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT64F32_H_args, + 1, Iclass_AE_CVT64F32_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT48F32_L_args, + 1, Iclass_AE_CVT48F32_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT48F32_H_args, + 1, Iclass_AE_CVT48F32_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_SAT48S_args, + 2, Iclass_AE_SAT48S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SATQ56S_args, + 2, Iclass_AE_SATQ56S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SAT24S_args, + 2, Iclass_AE_SAT24S_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCQ32_args, + 1, Iclass_AE_TRUNCQ32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MINABS64S_args, + 2, Iclass_AE_MINABS64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAXABS64S_args, + 2, Iclass_AE_MAXABS64S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSQ32F48SYM_args, + 2, Iclass_AE_ROUNDSQ32F48SYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSQ32F48ASYM_args, + 2, Iclass_AE_ROUNDSQ32F48ASYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCA32Q48_args, + 1, Iclass_AE_TRUNCA32Q48_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD32_L_args, + 1, Iclass_AE_MOVAD32_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD32_H_args, + 1, Iclass_AE_MOVAD32_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_3_args, + 1, Iclass_AE_MOVAD16_3_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_2_args, + 1, Iclass_AE_MOVAD16_2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_1_args, + 1, Iclass_AE_MOVAD16_1_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_0_args, + 1, Iclass_AE_MOVAD16_0_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRA64_32_args, + 1, Iclass_AE_SRA64_32_stateArgs, 0, 0 }, + { 3, Iclass_AE_PKSR32_args, + 2, Iclass_AE_PKSR32_stateArgs, 0, 0 }, + { 3, Iclass_AE_PKSR24_args, + 2, Iclass_AE_PKSR24_stateArgs, 0, 0 }, + { 3, Iclass_AE_PKSRF32_args, + 2, Iclass_AE_PKSRF32_stateArgs, 0, 0 }, + { 3, Iclass_AE_PKSR16_args, + 2, Iclass_AE_PKSR16_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCA16P24S_L_args, + 1, Iclass_AE_TRUNCA16P24S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCA16P24S_H_args, + 1, Iclass_AE_TRUNCA16P24S_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD32_args, + 1, Iclass_AE_ADD32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB32_args, + 1, Iclass_AE_SUB32_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDSUB32_args, + 1, Iclass_AE_ADDSUB32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUBADD32_args, + 1, Iclass_AE_SUBADD32_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD16_args, + 1, Iclass_AE_ADD16_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB16_args, + 1, Iclass_AE_SUB16_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD32_HL_LH_args, + 1, Iclass_AE_ADD32_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDSUB32_HL_LH_args, + 1, Iclass_AE_ADDSUB32_HL_LH_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG32_args, + 1, Iclass_AE_NEG32_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS32_args, + 1, Iclass_AE_ABS32_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG32_L_args, + 1, Iclass_AE_NEG32_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD24S_args, + 2, Iclass_AE_ADD24S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB24S_args, + 2, Iclass_AE_SUB24S_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD32S_args, + 2, Iclass_AE_ADD32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB32S_args, + 2, Iclass_AE_SUB32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDSUB32S_args, + 2, Iclass_AE_ADDSUB32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUBADD32S_args, + 2, Iclass_AE_SUBADD32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD16S_args, + 2, Iclass_AE_ADD16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB16S_args, + 2, Iclass_AE_SUB16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD32S_HL_LH_args, + 2, Iclass_AE_ADD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDSUB32S_HL_LH_args, + 2, Iclass_AE_ADDSUB32S_HL_LH_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG24S_args, + 2, Iclass_AE_NEG24S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS24S_args, + 2, Iclass_AE_ABS24S_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG32S_args, + 1, Iclass_AE_NEG32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS32S_args, + 1, Iclass_AE_ABS32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG16S_args, + 1, Iclass_AE_NEG16S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS16S_args, + 1, Iclass_AE_ABS16S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS16_args, + 1, Iclass_AE_ABS16_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULC16JS_H_args, + 2, Iclass_AE_MULC16JS_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULC16JS_L_args, + 2, Iclass_AE_MULC16JS_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAC16JS_H_args, + 2, Iclass_AE_MULAC16JS_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAC16JS_L_args, + 2, Iclass_AE_MULAC16JS_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_LT16_args, + 1, Iclass_AE_LT16_stateArgs, 0, 0 }, + { 3, Iclass_AE_LE16_args, + 1, Iclass_AE_LE16_stateArgs, 0, 0 }, + { 3, Iclass_AE_EQ16_args, + 1, Iclass_AE_EQ16_stateArgs, 0, 0 }, + { 3, Iclass_AE_LT32_args, + 1, Iclass_AE_LT32_stateArgs, 0, 0 }, + { 3, Iclass_AE_LE32_args, + 1, Iclass_AE_LE32_stateArgs, 0, 0 }, + { 3, Iclass_AE_EQ32_args, + 1, Iclass_AE_EQ32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MIN32_args, + 1, Iclass_AE_MIN32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAX32_args, + 1, Iclass_AE_MAX32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MINMAX32_args, + 1, Iclass_AE_MINMAX32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MINMAX16_args, + 1, Iclass_AE_MINMAX16_stateArgs, 0, 0 }, + { 3, Iclass_AE_MIN16_args, + 1, Iclass_AE_MIN16_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAX16_args, + 1, Iclass_AE_MAX16_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD64_args, + 1, Iclass_AE_ADD64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB64_args, + 1, Iclass_AE_SUB64_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG64_args, + 1, Iclass_AE_NEG64_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS64_args, + 1, Iclass_AE_ABS64_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDSQ56S_args, + 2, Iclass_AE_ADDSQ56S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUBSQ56S_args, + 2, Iclass_AE_SUBSQ56S_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD64S_args, + 2, Iclass_AE_ADD64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB64S_args, + 2, Iclass_AE_SUB64S_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEGSQ56S_args, + 2, Iclass_AE_NEGSQ56S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABSSQ56S_args, + 2, Iclass_AE_ABSSQ56S_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG64S_args, + 2, Iclass_AE_NEG64S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS64S_args, + 2, Iclass_AE_ABS64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_AND_args, + 1, Iclass_AE_AND_stateArgs, 0, 0 }, + { 3, Iclass_AE_NAND_args, + 1, Iclass_AE_NAND_stateArgs, 0, 0 }, + { 3, Iclass_AE_OR_args, + 1, Iclass_AE_OR_stateArgs, 0, 0 }, + { 3, Iclass_AE_XOR_args, + 1, Iclass_AE_XOR_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI24_args, + 1, Iclass_AE_SLAI24_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLI24_args, + 1, Iclass_AE_SRLI24_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI24_args, + 1, Iclass_AE_SRAI24_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS24_args, + 2, Iclass_AE_SLAS24_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRLS24_args, + 2, Iclass_AE_SRLS24_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRAS24_args, + 2, Iclass_AE_SRAS24_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI16_args, + 1, Iclass_AE_SRAI16_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI16R_args, + 1, Iclass_AE_SRAI16R_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI32_args, + 1, Iclass_AE_SLAI32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLI32_args, + 1, Iclass_AE_SRLI32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI32_args, + 1, Iclass_AE_SRAI32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI32R_args, + 1, Iclass_AE_SRAI32R_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS32_args, + 2, Iclass_AE_SLAS32_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRLS32_args, + 2, Iclass_AE_SRLS32_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRAS32_args, + 2, Iclass_AE_SRAS32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA32_args, + 1, Iclass_AE_SLAA32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLA32_args, + 1, Iclass_AE_SRLA32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA32_args, + 1, Iclass_AE_SRAA32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI16S_args, + 2, Iclass_AE_SLAI16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA16S_args, + 2, Iclass_AE_SLAA16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA16S_args, + 2, Iclass_AE_SRAA16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA16RS_args, + 2, Iclass_AE_SRAA16RS_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI24S_args, + 2, Iclass_AE_SLAI24S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS24S_args, + 3, Iclass_AE_SLAS24S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI32S_args, + 2, Iclass_AE_SLAI32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS32S_args, + 3, Iclass_AE_SLAS32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA32S_args, + 2, Iclass_AE_SLAA32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA32S_args, + 2, Iclass_AE_SRAA32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA32RS_args, + 2, Iclass_AE_SRAA32RS_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLASQ56_args, + 2, Iclass_AE_SLASQ56_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRLSQ56_args, + 2, Iclass_AE_SRLSQ56_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRASQ56_args, + 2, Iclass_AE_SRASQ56_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAAQ56_args, + 1, Iclass_AE_SLAAQ56_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLAQ56_args, + 1, Iclass_AE_SRLAQ56_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAAQ56_args, + 1, Iclass_AE_SRAAQ56_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI64_args, + 1, Iclass_AE_SLAI64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLI64_args, + 1, Iclass_AE_SRLI64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI64_args, + 1, Iclass_AE_SRAI64_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS64_args, + 2, Iclass_AE_SLAS64_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRLS64_args, + 2, Iclass_AE_SRLS64_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRAS64_args, + 2, Iclass_AE_SRAS64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA64_args, + 1, Iclass_AE_SLAA64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLA64_args, + 1, Iclass_AE_SRLA64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA64_args, + 1, Iclass_AE_SRAA64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAISQ56S_args, + 2, Iclass_AE_SLAISQ56S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLASSQ56S_args, + 3, Iclass_AE_SLASSQ56S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAASQ56S_args, + 2, Iclass_AE_SLAASQ56S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI64S_args, + 2, Iclass_AE_SLAI64S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS64S_args, + 3, Iclass_AE_SLAS64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA64S_args, + 2, Iclass_AE_SLAA64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_LT64_args, + 1, Iclass_AE_LT64_stateArgs, 0, 0 }, + { 3, Iclass_AE_LE64_args, + 1, Iclass_AE_LE64_stateArgs, 0, 0 }, + { 3, Iclass_AE_EQ64_args, + 1, Iclass_AE_EQ64_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAX64_args, + 1, Iclass_AE_MAX64_stateArgs, 0, 0 }, + { 3, Iclass_AE_MIN64_args, + 1, Iclass_AE_MIN64_stateArgs, 0, 0 }, + { 2, Iclass_AE_NSA64_args, + 1, Iclass_AE_NSA64_stateArgs, 0, 0 }, + { 2, Iclass_AE_NSAZ16_0_args, + 1, Iclass_AE_NSAZ16_0_stateArgs, 0, 0 }, + { 2, Iclass_AE_NSAZ32_L_args, + 1, Iclass_AE_NSAZ32_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32F48P16S_LL_args, + 2, Iclass_AE_MULS32F48P16S_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32S_LL_args, + 2, Iclass_AE_MULF32S_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32_LL_args, + 1, Iclass_AE_MUL32_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32R_LL_args, + 1, Iclass_AE_MULF32R_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32RA_LL_args, + 1, Iclass_AE_MULF32RA_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32F48P16S_LH_args, + 2, Iclass_AE_MULS32F48P16S_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32S_LH_args, + 2, Iclass_AE_MULF32S_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32_LH_args, + 1, Iclass_AE_MUL32_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32R_LH_args, + 1, Iclass_AE_MULF32R_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32RA_LH_args, + 1, Iclass_AE_MULF32RA_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32F48P16S_HH_args, + 2, Iclass_AE_MULS32F48P16S_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32S_HH_args, + 2, Iclass_AE_MULF32S_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32_HH_args, + 1, Iclass_AE_MUL32_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32R_HH_args, + 1, Iclass_AE_MULF32R_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32RA_HH_args, + 1, Iclass_AE_MULF32RA_HH_stateArgs, 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Iclass_AE_MULAF32S_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA32_HH_args, + 1, Iclass_AE_MULA32_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAF32R_HH_args, + 1, Iclass_AE_MULAF32R_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAF32RA_HH_args, + 1, Iclass_AE_MULAF32RA_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSS32F48P16S_LL_args, + 2, Iclass_AE_MULSS32F48P16S_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSF32S_LL_args, + 2, Iclass_AE_MULSF32S_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32_LL_args, + 1, Iclass_AE_MULS32_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSF32R_LL_args, + 1, Iclass_AE_MULSF32R_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSF32RA_LL_args, + 1, Iclass_AE_MULSF32RA_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSS32F48P16S_LH_args, + 2, Iclass_AE_MULSS32F48P16S_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSF32S_LH_args, + 2, Iclass_AE_MULSF32S_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32_LH_args, + 1, Iclass_AE_MULS32_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSF32R_LH_args, + 1, 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Iclass_AE_CVTI32X4F16U_args, + 1, Iclass_AE_CVTI32X4F16U_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTI32X4F16US_args, + 2, Iclass_AE_CVTI32X4F16US_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA32X4F16U_args, + 1, Iclass_AE_CVTA32X4F16U_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA32X4F16US_args, + 2, Iclass_AE_CVTA32X4F16US_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTI16X4X2F8_args, + 1, Iclass_AE_CVTI16X4X2F8_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTI16X4X2F8S_args, + 2, Iclass_AE_CVTI16X4X2F8S_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA16X4X2F8_args, + 1, Iclass_AE_CVTA16X4X2F8_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA16X4X2F8S_args, + 2, Iclass_AE_CVTA16X4X2F8S_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTI16X4X2F8U_args, + 1, Iclass_AE_CVTI16X4X2F8U_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTI16X4X2F8US_args, + 2, Iclass_AE_CVTI16X4X2F8US_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA16X4X2F8U_args, + 1, Iclass_AE_CVTA16X4X2F8U_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA16X4X2F8US_args, + 2, Iclass_AE_CVTA16X4X2F8US_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL8X8_args, + 1, Iclass_AE_SEL8X8_stateArgs, 0, 0 }, + { 3, Iclass_AE_SHFL8X8_args, + 1, Iclass_AE_SHFL8X8_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL16X4_args, + 1, Iclass_AE_SEL16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_SHFL16X4_args, + 1, Iclass_AE_SHFL16X4_stateArgs, 0, 0 }, + { 5, Iclass_AE_DSEL8X8_args, + 1, Iclass_AE_DSEL8X8_stateArgs, 0, 0 }, + { 5, Iclass_AE_DSEL16X4_args, + 1, Iclass_AE_DSEL16X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL8X8I_args, + 1, Iclass_AE_SEL8X8I_stateArgs, 0, 0 }, + { 2, Iclass_AE_RMAX8X8_args, + 1, Iclass_AE_RMAX8X8_stateArgs, 0, 0 }, + { 2, Iclass_AE_RMIN8X8_args, + 1, Iclass_AE_RMIN8X8_stateArgs, 0, 0 }, + { 2, Iclass_AE_RMAX16X4_args, + 1, Iclass_AE_RMAX16X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_RMIN16X4_args, + 1, Iclass_AE_RMIN16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_SORT16X4_args, + 1, Iclass_AE_SORT16X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADD8X8_H_args, + 1, Iclass_AE_RADD8X8_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADDA8X8_H_args, + 1, Iclass_AE_RADDA8X8_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADD8X8_L_args, + 1, Iclass_AE_RADD8X8_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADDA8X8_L_args, + 1, Iclass_AE_RADDA8X8_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADD16X4_args, + 1, Iclass_AE_RADD16X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADDA16X4_args, + 1, Iclass_AE_RADDA16X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMAX8X8_H_args, + 1, Iclass_AE_BMAX8X8_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMAX8X8_L_args, + 1, Iclass_AE_BMAX8X8_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMIN8X8_H_args, + 1, Iclass_AE_BMIN8X8_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMIN8X8_L_args, + 1, Iclass_AE_BMIN8X8_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMAX16X4_args, + 1, Iclass_AE_BMAX16X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMIN16X4_args, + 1, Iclass_AE_BMIN16X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMAX32X2_args, + 1, Iclass_AE_BMAX32X2_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMIN32X2_args, + 1, Iclass_AE_BMIN32X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_ADDINV16S_args, + 2, Iclass_AE_ADDINV16S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ADDINV32S_args, + 2, Iclass_AE_ADDINV32S_stateArgs, 0, 0 }, + { 6, Iclass_AE_MOVT16X8_args, + 1, Iclass_AE_MOVT16X8_stateArgs, 0, 0 }, + { 5, Iclass_AE_MOVT8X16_H_args, + 1, Iclass_AE_MOVT8X16_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MOVT8X16_L_args, + 1, Iclass_AE_MOVT8X16_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVBD1X4_args, + 1, Iclass_AE_MOVBD1X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVBD1X2_args, + 1, Iclass_AE_MOVBD1X2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVNEG32S_T_args, + 1, Iclass_AE_MOVNEG32S_T_stateArgs, 0, 0 }, + { 4, Iclass_AE_MOVDEXT_args, + 1, Iclass_AE_MOVDEXT_stateArgs, 0, 0 }, + { 4, Iclass_AE_MOVADEXT_H_args, + 1, Iclass_AE_MOVADEXT_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_MOVADEXT_L_args, + 1, Iclass_AE_MOVADEXT_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_NSA16X4_args, + 1, Iclass_AE_NSA16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_NSAZ32X4_args, + 1, Iclass_AE_NSAZ32X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_NSA32X4_args, + 1, Iclass_AE_NSA32X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCI16X4F32S_args, + 2, Iclass_AE_TRUNCI16X4F32S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCI16X4F64S_args, + 2, Iclass_AE_TRUNCI16X4F64S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCA16X4F32S_args, + 2, Iclass_AE_TRUNCA16X4F32S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCA16X4F64S_args, + 2, Iclass_AE_TRUNCA16X4F64S_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDC32_args, + 1, Iclass_AE_ADDC32_stateArgs, 0, 0 }, + { 4, Iclass_AE_SUBC32_args, + 1, Iclass_AE_SUBC32_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDC32U_args, + 1, Iclass_AE_ADDC32U_stateArgs, 0, 0 }, + { 4, Iclass_AE_SUBC32U_args, + 1, Iclass_AE_SUBC32U_stateArgs, 0, 0 }, + { 3, Iclass_AE_EXPADD16_H_args, + 1, Iclass_AE_EXPADD16_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_EXPSUB16_H_args, + 1, Iclass_AE_EXPSUB16_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_EXPADD16_L_args, + 1, Iclass_AE_EXPADD16_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_EXPSUB16_L_args, + 1, Iclass_AE_EXPSUB16_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDCEXP32_H_args, + 1, Iclass_AE_ADDCEXP32_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDCEXP32_L_args, + 1, Iclass_AE_ADDCEXP32_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_CALCRNG16_args, + 2, Iclass_AE_CALCRNG16_stateArgs, 0, 0 }, + { 4, Iclass_AE_CALCRNG32_args, + 2, Iclass_AE_CALCRNG32_stateArgs, 0, 0 }, + { 2, Iclass_AE_RNG32X4_args, + 2, Iclass_AE_RNG32X4_stateArgs, 0, 0 }, + { 5, Iclass_AE_LAV8X8X2_XP_args, + 1, Iclass_AE_LAV8X8X2_XP_stateArgs, 0, 0 }, + { 5, Iclass_AE_LAV16X4X2_XP_args, + 1, Iclass_AE_LAV16X4X2_XP_stateArgs, 0, 0 }, + { 5, Iclass_AE_SAV8X8X2_XP_args, + 1, Iclass_AE_SAV8X8X2_XP_stateArgs, 0, 0 }, + { 5, Iclass_AE_SAV16X4X2_XP_args, + 1, Iclass_AE_SAV16X4X2_XP_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVZBVCDR_args, + 3, Iclass_AE_MOVZBVCDR_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVDRZBVC_args, + 3, Iclass_AE_MOVDRZBVC_stateArgs, 0, 0 }, + { 6, Iclass_AE_LAVUNSQZ8X8_XP_args, + 1, Iclass_AE_LAVUNSQZ8X8_XP_stateArgs, 0, 0 }, + { 6, Iclass_AE_LAVUNSQZ16X4_XP_args, + 1, Iclass_AE_LAVUNSQZ16X4_XP_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL8Q8X8_args, + 1, Iclass_AE_MUL8Q8X8_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA8Q8X8_args, + 1, Iclass_AE_MULA8Q8X8_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL8Q4X16_args, + 1, Iclass_AE_MUL8Q4X16_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA8Q4X16_args, + 1, Iclass_AE_MULA8Q4X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL8Q8X16_args, + 1, Iclass_AE_MUL8Q8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA8Q8X16_args, + 1, Iclass_AE_MULA8Q8X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MUL8QW8X16_args, + 1, Iclass_AE_MUL8QW8X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MULA8QW8X16_args, + 1, Iclass_AE_MULA8QW8X16_stateArgs, 0, 0 }, + { 9, Iclass_AE_MUL4O8X8_args, + 1, Iclass_AE_MUL4O8X8_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULA4O8X8_args, + 1, Iclass_AE_MULA4O8X8_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O4X16_args, + 1, Iclass_AE_MUL4O4X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O4X16_args, + 1, Iclass_AE_MULA4O4X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MUL4O8X16_args, + 1, Iclass_AE_MUL4O8X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MULA4O8X16_args, + 1, Iclass_AE_MULA4O8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4QW8X16_args, + 1, Iclass_AE_MUL4QW8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4QW8X16_args, + 1, Iclass_AE_MULA4QW8X16_stateArgs, 0, 0 }, + { 5, Iclass_AE_MUL8Q8X8CNV_L_args, + 1, Iclass_AE_MUL8Q8X8CNV_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MUL8Q8X8CNV_H_args, + 1, Iclass_AE_MUL8Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULA8Q8X8CNV_L_args, + 1, Iclass_AE_MULA8Q8X8CNV_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULA8Q8X8CNV_H_args, + 1, Iclass_AE_MULA8Q8X8CNV_H_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL8Q8X16CNV_args, + 1, Iclass_AE_MUL8Q8X16CNV_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA8Q8X16CNV_args, + 1, Iclass_AE_MULA8Q8X16CNV_stateArgs, 0, 0 }, + { 5, Iclass_AE_MUL2X4Q8X8CNV_H_args, + 1, Iclass_AE_MUL2X4Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULA2X4Q8X8CNV_H_args, + 1, Iclass_AE_MULA2X4Q8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL2X4Q8X8CNV_L_args, + 1, Iclass_AE_MUL2X4Q8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA2X4Q8X8CNV_L_args, + 1, Iclass_AE_MULA2X4Q8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL2X4Q8X16CNV_args, + 1, Iclass_AE_MUL2X4Q8X16CNV_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA2X4Q8X16CNV_args, + 1, Iclass_AE_MULA2X4Q8X16CNV_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULQQ8X16CNV_args, + 1, Iclass_AE_MULQQ8X16CNV_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAQQ8X16CNV_args, + 1, Iclass_AE_MULAQQ8X16CNV_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL4O8X8CNV_H_args, + 1, Iclass_AE_MUL4O8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA4O8X8CNV_H_args, + 1, Iclass_AE_MULA4O8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL4O8X8CNV_L_args, + 1, Iclass_AE_MUL4O8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA4O8X8CNV_L_args, + 1, Iclass_AE_MULA4O8X8CNV_L_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O8X16CNV_H_args, + 1, Iclass_AE_MUL4O8X16CNV_H_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O8X16CNV_H_args, + 1, Iclass_AE_MULA4O8X16CNV_H_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O8X16CNV_L_args, + 1, Iclass_AE_MUL4O8X16CNV_L_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O8X16CNV_L_args, + 1, Iclass_AE_MULA4O8X16CNV_L_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL8Q4X16CNV_H_args, + 1, Iclass_AE_MUL8Q4X16CNV_H_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA8Q4X16CNV_H_args, + 1, Iclass_AE_MULA8Q4X16CNV_H_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL8Q4X16CNV_L_args, + 1, Iclass_AE_MUL8Q4X16CNV_L_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA8Q4X16CNV_L_args, + 1, Iclass_AE_MULA8Q4X16CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL2X4Q4X16CNV_H_args, + 1, Iclass_AE_MUL2X4Q4X16CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA2X4Q4X16CNV_H_args, + 1, Iclass_AE_MULA2X4Q4X16CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL2X4Q4X16CNV_L_args, + 1, Iclass_AE_MUL2X4Q4X16CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA2X4Q4X16CNV_L_args, + 1, Iclass_AE_MULA2X4Q4X16CNV_L_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULQQ4X16CNV_H_args, + 1, Iclass_AE_MULQQ4X16CNV_H_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAQQ4X16CNV_H_args, + 1, Iclass_AE_MULAQQ4X16CNV_H_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULQQ4X16CNV_L_args, + 1, Iclass_AE_MULQQ4X16CNV_L_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAQQ4X16CNV_L_args, + 1, Iclass_AE_MULAQQ4X16CNV_L_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O4X16CNV_HH_args, + 1, Iclass_AE_MUL4O4X16CNV_HH_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O4X16CNV_HL_args, + 1, Iclass_AE_MUL4O4X16CNV_HL_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O4X16CNV_LH_args, + 1, Iclass_AE_MUL4O4X16CNV_LH_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O4X16CNV_LL_args, + 1, Iclass_AE_MUL4O4X16CNV_LL_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O4X16CNV_HH_args, + 1, Iclass_AE_MULA4O4X16CNV_HH_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O4X16CNV_HL_args, + 1, Iclass_AE_MULA4O4X16CNV_HL_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O4X16CNV_LH_args, + 1, Iclass_AE_MULA4O4X16CNV_LH_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O4X16CNV_LL_args, + 1, Iclass_AE_MULA4O4X16CNV_LL_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUU8Q8X8_args, + 1, Iclass_AE_MULUU8Q8X8_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUU8Q8X8_args, + 1, Iclass_AE_MULAUU8Q8X8_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULUU4O8X8_args, + 1, Iclass_AE_MULUU4O8X8_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAUU4O8X8_args, + 1, Iclass_AE_MULAUU4O8X8_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULUU8Q8X8CNV_L_args, + 1, Iclass_AE_MULUU8Q8X8CNV_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAUU8Q8X8CNV_L_args, + 1, Iclass_AE_MULAUU8Q8X8CNV_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULUU8Q8X8CNV_H_args, + 1, Iclass_AE_MULUU8Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAUU8Q8X8CNV_H_args, + 1, Iclass_AE_MULAUU8Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULUU2X4Q8X8CNV_H_args, + 1, Iclass_AE_MULUU2X4Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAUU2X4Q8X8CNV_H_args, + 1, Iclass_AE_MULAUU2X4Q8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUU2X4Q8X8CNV_L_args, + 1, Iclass_AE_MULUU2X4Q8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUU2X4Q8X8CNV_L_args, + 1, Iclass_AE_MULAUU2X4Q8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUU4O8X8CNV_H_args, + 1, Iclass_AE_MULUU4O8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUU4O8X8CNV_H_args, + 1, Iclass_AE_MULAUU4O8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUU4O8X8CNV_L_args, + 1, Iclass_AE_MULUU4O8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUU4O8X8CNV_L_args, + 1, Iclass_AE_MULAUU4O8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUS8Q8X8_args, + 1, Iclass_AE_MULUS8Q8X8_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUS8Q8X8_args, + 1, Iclass_AE_MULAUS8Q8X8_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULUS8Q4X16_args, + 1, Iclass_AE_MULUS8Q4X16_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAUS8Q4X16_args, + 1, Iclass_AE_MULAUS8Q4X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULUS8Q8X16_args, + 1, Iclass_AE_MULUS8Q8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULAUS8Q8X16_args, + 1, Iclass_AE_MULAUS8Q8X16_stateArgs, 0, 0 }, + { 10, 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Iclass_ADDANDSUBJC_S_stateArgs, 0, 0 }, + { 3, Iclass_ADD_HL_LH_S_args, + 5, Iclass_ADD_HL_LH_S_stateArgs, 0, 0 }, + { 4, Iclass_MADDA_S_args, + 6, Iclass_MADDA_S_stateArgs, 0, 0 }, + { 3, Iclass_FREXP_S_args, + 1, Iclass_FREXP_S_stateArgs, 0, 0 }, + { 2, Iclass_FLOATEXP_S_args, + 1, Iclass_FLOATEXP_S_stateArgs, 0, 0 }, + { 3, Iclass_MINNUMABS_S_args, + 2, Iclass_MINNUMABS_S_stateArgs, 0, 0 }, + { 3, Iclass_MAXNUMABS_S_args, + 2, Iclass_MAXNUMABS_S_stateArgs, 0, 0 }, + { 5, Iclass_MULQ_S_args, + 6, Iclass_MULQ_S_stateArgs, 0, 0 }, + { 5, Iclass_MADDQ_S_args, + 6, Iclass_MADDQ_S_stateArgs, 0, 0 }, + { 5, Iclass_MSUBQ_S_args, + 6, Iclass_MSUBQ_S_stateArgs, 0, 0 }, + { 6, Iclass_MULMUXQ_S_args, + 6, Iclass_MULMUXQ_S_stateArgs, 0, 0 }, + { 6, Iclass_MADDMUXQ_S_args, + 6, Iclass_MADDMUXQ_S_stateArgs, 0, 0 }, + { 4, Iclass_BMAXNUM_S_args, + 2, Iclass_BMAXNUM_S_stateArgs, 0, 0 }, + { 4, Iclass_BMINNUM_S_args, + 2, Iclass_BMINNUM_S_stateArgs, 0, 0 }, + { 4, Iclass_BMAXNUMABS_S_args, + 2, Iclass_BMAXNUMABS_S_stateArgs, 0, 0 }, + { 4, Iclass_BMINNUMABS_S_args, + 2, Iclass_BMINNUMABS_S_stateArgs, 0, 0 }, + { 4, Iclass_ABS_SX2X2_args, + 1, Iclass_ABS_SX2X2_stateArgs, 0, 0 }, + { 4, Iclass_NEG_SX2X2_args, + 1, Iclass_NEG_SX2X2_stateArgs, 0, 0 }, + { 4, Iclass_CONJC_SX2X2_args, + 1, Iclass_CONJC_SX2X2_stateArgs, 0, 0 }, + { 4, Iclass_MULJC_SX2X2_args, + 1, Iclass_MULJC_SX2X2_stateArgs, 0, 0 }, + { 3, Iclass_CONST_SX2X2_args, + 1, Iclass_CONST_SX2X2_stateArgs, 0, 0 }, + { 6, Iclass_ADD_SX2X2_args, + 5, Iclass_ADD_SX2X2_stateArgs, 0, 0 }, + { 6, Iclass_SUB_SX2X2_args, + 5, Iclass_SUB_SX2X2_stateArgs, 0, 0 }, + { 6, Iclass_MUL_SX2X2_args, + 6, Iclass_MUL_SX2X2_stateArgs, 0, 0 }, + { 6, Iclass_MADD_SX2X2_args, + 6, Iclass_MADD_SX2X2_stateArgs, 0, 0 }, + { 6, Iclass_MSUB_SX2X2_args, + 6, Iclass_MSUB_SX2X2_stateArgs, 0, 0 }, + { 7, Iclass_MULMUX_SX2X2_args, + 6, Iclass_MULMUX_SX2X2_stateArgs, 0, 0 }, + { 7, Iclass_MADDMUX_SX2X2_args, + 6, Iclass_MADDMUX_SX2X2_stateArgs, 0, 0 }, + { 2, Iclass_ABS_H_args, + 1, Iclass_ABS_H_stateArgs, 0, 0 }, + { 2, Iclass_ADDEXP_H_args, + 1, Iclass_ADDEXP_H_stateArgs, 0, 0 }, + { 2, Iclass_ADDEXPM_H_args, + 1, Iclass_ADDEXPM_H_stateArgs, 0, 0 }, + { 2, Iclass_CLSFY_H_args, + 1, Iclass_CLSFY_H_stateArgs, 0, 0 }, + { 2, Iclass_CONJC_H_args, + 1, Iclass_CONJC_H_stateArgs, 0, 0 }, + { 2, Iclass_CONST_H_args, + 1, Iclass_CONST_H_stateArgs, 0, 0 }, + { 3, Iclass_MIN_H_args, + 2, Iclass_MIN_H_stateArgs, 0, 0 }, + { 3, Iclass_MAX_H_args, + 2, Iclass_MAX_H_stateArgs, 0, 0 }, + { 3, Iclass_MINNUM_H_args, + 2, Iclass_MINNUM_H_stateArgs, 0, 0 }, + { 3, Iclass_MAXNUM_H_args, + 2, Iclass_MAXNUM_H_stateArgs, 0, 0 }, + { 2, Iclass_MULJC_H_args, + 1, Iclass_MULJC_H_stateArgs, 0, 0 }, + { 2, Iclass_NEG_H_args, + 1, Iclass_NEG_H_stateArgs, 0, 0 }, + { 3, Iclass_OEQ_H_args, + 2, Iclass_OEQ_H_stateArgs, 0, 0 }, + { 3, Iclass_OLE_H_args, + 2, Iclass_OLE_H_stateArgs, 0, 0 }, + { 3, Iclass_OLT_H_args, + 2, Iclass_OLT_H_stateArgs, 0, 0 }, + { 3, Iclass_UEQ_H_args, + 2, Iclass_UEQ_H_stateArgs, 0, 0 }, + { 3, Iclass_ULE_H_args, + 2, Iclass_ULE_H_stateArgs, 0, 0 }, + { 3, Iclass_ULT_H_args, + 2, Iclass_ULT_H_stateArgs, 0, 0 }, + { 3, Iclass_UN_H_args, + 2, Iclass_UN_H_stateArgs, 0, 0 }, + { 2, Iclass_DIV0_H_args, + 1, Iclass_DIV0_H_stateArgs, 0, 0 }, + { 2, Iclass_FICEIL_H_args, + 2, Iclass_FICEIL_H_stateArgs, 0, 0 }, + { 2, Iclass_FIFLOOR_H_args, + 2, Iclass_FIFLOOR_H_stateArgs, 0, 0 }, + { 2, Iclass_FIRINT_H_args, + 4, Iclass_FIRINT_H_stateArgs, 0, 0 }, + { 2, Iclass_FIROUND_H_args, + 2, Iclass_FIROUND_H_stateArgs, 0, 0 }, + { 2, Iclass_FITRUNC_H_args, + 2, Iclass_FITRUNC_H_stateArgs, 0, 0 }, + { 2, Iclass_MKDADJ_H_args, + 3, Iclass_MKDADJ_H_stateArgs, 0, 0 }, + { 2, Iclass_MKSADJ_H_args, + 2, Iclass_MKSADJ_H_stateArgs, 0, 0 }, + { 2, Iclass_NEXP0_H_args, + 1, Iclass_NEXP0_H_stateArgs, 0, 0 }, + { 2, Iclass_NEXP01_H_args, + 1, Iclass_NEXP01_H_stateArgs, 0, 0 }, + { 2, Iclass_RECIP0_H_args, + 3, Iclass_RECIP0_H_stateArgs, 0, 0 }, + { 2, Iclass_RSQRT0_H_args, + 3, Iclass_RSQRT0_H_stateArgs, 0, 0 }, + { 2, Iclass_SQRT0_H_args, + 1, Iclass_SQRT0_H_stateArgs, 0, 0 }, + { 3, Iclass_FLOAT16_H_args, + 3, Iclass_FLOAT16_H_stateArgs, 0, 0 }, + { 3, Iclass_UFLOAT16_H_args, + 4, Iclass_UFLOAT16_H_stateArgs, 0, 0 }, + { 3, Iclass_TRUNC16_H_args, + 3, Iclass_TRUNC16_H_stateArgs, 0, 0 }, + { 3, Iclass_UTRUNC16_H_args, + 3, Iclass_UTRUNC16_H_stateArgs, 0, 0 }, + { 3, Iclass_FLOAT16_HX4_args, + 3, Iclass_FLOAT16_HX4_stateArgs, 0, 0 }, + { 3, Iclass_UFLOAT16_HX4_args, + 4, Iclass_UFLOAT16_HX4_stateArgs, 0, 0 }, + { 3, Iclass_TRUNC16_HX4_args, + 3, Iclass_TRUNC16_HX4_stateArgs, 0, 0 }, + { 3, Iclass_UTRUNC16_HX4_args, + 3, Iclass_UTRUNC16_HX4_stateArgs, 0, 0 }, + { 3, Iclass_ADD_H_args, + 5, Iclass_ADD_H_stateArgs, 0, 0 }, + { 3, Iclass_SUB_H_args, + 5, Iclass_SUB_H_stateArgs, 0, 0 }, + { 3, Iclass_MUL_H_args, + 6, Iclass_MUL_H_stateArgs, 0, 0 }, + { 3, Iclass_MADD_H_args, + 6, Iclass_MADD_H_stateArgs, 0, 0 }, + { 3, Iclass_MSUB_H_args, + 6, Iclass_MSUB_H_stateArgs, 0, 0 }, + { 3, Iclass_MADDN_H_args, + 1, Iclass_MADDN_H_stateArgs, 0, 0 }, + { 3, Iclass_MSUBN_H_args, + 1, Iclass_MSUBN_H_stateArgs, 0, 0 }, + { 3, Iclass_DIVN_H_args, + 5, Iclass_DIVN_H_stateArgs, 0, 0 }, + { 2, Iclass_RMINNUM_H_args, + 2, Iclass_RMINNUM_H_stateArgs, 0, 0 }, + { 2, Iclass_RMAXNUM_H_args, + 2, Iclass_RMAXNUM_H_stateArgs, 0, 0 }, + { 4, Iclass_ABS_HX4X2_args, + 1, Iclass_ABS_HX4X2_stateArgs, 0, 0 }, + { 4, Iclass_NEG_HX4X2_args, + 1, Iclass_NEG_HX4X2_stateArgs, 0, 0 }, + { 4, Iclass_CONJC_HX4X2_args, + 1, Iclass_CONJC_HX4X2_stateArgs, 0, 0 }, + { 3, Iclass_CONST_HX4X2_args, + 1, Iclass_CONST_HX4X2_stateArgs, 0, 0 }, + { 4, Iclass_MULJC_HX4X2_args, + 1, Iclass_MULJC_HX4X2_stateArgs, 0, 0 }, + { 6, Iclass_ADD_HX4X2_args, + 5, Iclass_ADD_HX4X2_stateArgs, 0, 0 }, + { 6, Iclass_SUB_HX4X2_args, + 5, Iclass_SUB_HX4X2_stateArgs, 0, 0 }, + { 6, Iclass_MUL_HX4X2_args, + 6, Iclass_MUL_HX4X2_stateArgs, 0, 0 }, + { 6, Iclass_MADD_HX4X2_args, + 6, Iclass_MADD_HX4X2_stateArgs, 0, 0 }, + { 6, Iclass_MSUB_HX4X2_args, + 6, Iclass_MSUB_HX4X2_stateArgs, 0, 0 }, + { 5, Iclass_MULQ_H_args, + 6, Iclass_MULQ_H_stateArgs, 0, 0 }, + { 5, Iclass_MADDQ_H_args, + 6, Iclass_MADDQ_H_stateArgs, 0, 0 }, + { 5, Iclass_MULCNVH_HX4X2_args, + 6, Iclass_MULCNVH_HX4X2_stateArgs, 0, 0 }, + { 5, Iclass_MULACNVH_HX4X2_args, + 6, Iclass_MULACNVH_HX4X2_stateArgs, 0, 0 }, + { 5, Iclass_MULCNVL_HX4X2_args, + 6, Iclass_MULCNVL_HX4X2_stateArgs, 0, 0 }, + { 5, Iclass_MULACNVL_HX4X2_args, + 6, Iclass_MULACNVL_HX4X2_stateArgs, 0, 0 } +}; + +enum xtensa_iclass_id { + ICLASS_xt_iclass_excw, + ICLASS_xt_iclass_rfe, + ICLASS_xt_iclass_rfde, + ICLASS_xt_iclass_syscall, + ICLASS_xt_iclass_call12, + ICLASS_xt_iclass_call8, + ICLASS_xt_iclass_call4, + ICLASS_xt_iclass_callx12, + ICLASS_xt_iclass_callx8, + ICLASS_xt_iclass_callx4, + ICLASS_xt_iclass_entry, + ICLASS_xt_iclass_movsp, + ICLASS_xt_iclass_rotw, + ICLASS_xt_iclass_retw, + ICLASS_xt_iclass_rfwou, + ICLASS_xt_iclass_l32e, + ICLASS_xt_iclass_s32e, + ICLASS_xt_iclass_rsr_windowbase, + ICLASS_xt_iclass_wsr_windowbase, + ICLASS_xt_iclass_xsr_windowbase, + ICLASS_xt_iclass_rsr_windowstart, + ICLASS_xt_iclass_wsr_windowstart, + ICLASS_xt_iclass_xsr_windowstart, + ICLASS_xt_iclass_add_n, + ICLASS_xt_iclass_addi_n, + ICLASS_xt_iclass_bz6, + ICLASS_xt_iclass_ill_n, + ICLASS_xt_iclass_loadi4, + ICLASS_xt_iclass_mov_n, + ICLASS_xt_iclass_movi_n, + ICLASS_xt_iclass_nopn, + ICLASS_xt_iclass_retn, + ICLASS_xt_iclass_storei4, + ICLASS_rur_threadptr, + ICLASS_wur_threadptr, + ICLASS_xt_iclass_addi, + ICLASS_xt_iclass_addmi, + ICLASS_xt_iclass_addsub, + ICLASS_xt_iclass_bit, + ICLASS_xt_iclass_bsi8, + ICLASS_xt_iclass_bsi8b, + ICLASS_xt_iclass_bsi8u, + ICLASS_xt_iclass_bst8, + ICLASS_xt_iclass_bsz12, + ICLASS_xt_iclass_call0, + ICLASS_xt_iclass_callx0, + ICLASS_xt_iclass_exti, + ICLASS_xt_iclass_ill, + ICLASS_xt_iclass_jump, + ICLASS_xt_iclass_jumpx, + ICLASS_xt_iclass_l16ui, + ICLASS_xt_iclass_l16si, + ICLASS_xt_iclass_l32i, + ICLASS_xt_iclass_l32r, + ICLASS_xt_iclass_l8i, + ICLASS_xt_iclass_loop, + ICLASS_xt_iclass_loopz, + ICLASS_xt_iclass_movi, + ICLASS_xt_iclass_movz, + ICLASS_xt_iclass_neg, + ICLASS_xt_iclass_nop, + ICLASS_xt_iclass_l32ex, + ICLASS_xt_iclass_s32ex, + ICLASS_xt_iclass_getex, + ICLASS_xt_iclass_clrex, + ICLASS_xt_iclass_return, + ICLASS_xt_iclass_simcall, + ICLASS_xt_iclass_s16i, + ICLASS_xt_iclass_s32i, + ICLASS_xt_iclass_s32nb, + ICLASS_xt_iclass_s8i, + ICLASS_xt_iclass_sar, + ICLASS_xt_iclass_sari, + ICLASS_xt_iclass_shifts, + ICLASS_xt_iclass_shiftst, + ICLASS_xt_iclass_shiftt, + ICLASS_xt_iclass_slli, + ICLASS_xt_iclass_srai, + ICLASS_xt_iclass_srli, + ICLASS_xt_iclass_memw, + ICLASS_xt_iclass_extw, + ICLASS_xt_iclass_isync, + ICLASS_xt_iclass_sync, + ICLASS_xt_iclass_rsil, + ICLASS_xt_iclass_rsr_lend, + ICLASS_xt_iclass_wsr_lend, + ICLASS_xt_iclass_xsr_lend, + ICLASS_xt_iclass_rsr_lcount, + ICLASS_xt_iclass_wsr_lcount, + ICLASS_xt_iclass_xsr_lcount, + ICLASS_xt_iclass_rsr_lbeg, + ICLASS_xt_iclass_wsr_lbeg, + ICLASS_xt_iclass_xsr_lbeg, + ICLASS_xt_iclass_rsr_sar, + ICLASS_xt_iclass_wsr_sar, + ICLASS_xt_iclass_xsr_sar, + ICLASS_xt_iclass_rsr_memctl, + ICLASS_xt_iclass_wsr_memctl, + ICLASS_xt_iclass_xsr_memctl, + ICLASS_xt_iclass_rsr_configid0, + ICLASS_xt_iclass_wsr_configid0, + ICLASS_xt_iclass_rsr_configid1, + ICLASS_xt_iclass_rsr_ps, + ICLASS_xt_iclass_wsr_ps, + ICLASS_xt_iclass_xsr_ps, + ICLASS_xt_iclass_rsr_epc1, + ICLASS_xt_iclass_wsr_epc1, + ICLASS_xt_iclass_xsr_epc1, + ICLASS_xt_iclass_rsr_excsave1, + ICLASS_xt_iclass_wsr_excsave1, + ICLASS_xt_iclass_xsr_excsave1, + ICLASS_xt_iclass_rsr_epc2, + ICLASS_xt_iclass_wsr_epc2, + ICLASS_xt_iclass_xsr_epc2, + ICLASS_xt_iclass_rsr_excsave2, + ICLASS_xt_iclass_wsr_excsave2, + ICLASS_xt_iclass_xsr_excsave2, + ICLASS_xt_iclass_rsr_epc3, + ICLASS_xt_iclass_wsr_epc3, + ICLASS_xt_iclass_xsr_epc3, + ICLASS_xt_iclass_rsr_excsave3, + ICLASS_xt_iclass_wsr_excsave3, + ICLASS_xt_iclass_xsr_excsave3, + ICLASS_xt_iclass_rsr_epc4, + ICLASS_xt_iclass_wsr_epc4, + ICLASS_xt_iclass_xsr_epc4, + ICLASS_xt_iclass_rsr_excsave4, + ICLASS_xt_iclass_wsr_excsave4, + ICLASS_xt_iclass_xsr_excsave4, + ICLASS_xt_iclass_rsr_epc5, + ICLASS_xt_iclass_wsr_epc5, + ICLASS_xt_iclass_xsr_epc5, + ICLASS_xt_iclass_rsr_excsave5, + ICLASS_xt_iclass_wsr_excsave5, + ICLASS_xt_iclass_xsr_excsave5, + ICLASS_xt_iclass_rsr_epc6, + ICLASS_xt_iclass_wsr_epc6, + ICLASS_xt_iclass_xsr_epc6, + ICLASS_xt_iclass_rsr_excsave6, + ICLASS_xt_iclass_wsr_excsave6, + ICLASS_xt_iclass_xsr_excsave6, + ICLASS_xt_iclass_rsr_eps2, + ICLASS_xt_iclass_wsr_eps2, + ICLASS_xt_iclass_xsr_eps2, + ICLASS_xt_iclass_rsr_eps3, + ICLASS_xt_iclass_wsr_eps3, + ICLASS_xt_iclass_xsr_eps3, + ICLASS_xt_iclass_rsr_eps4, + ICLASS_xt_iclass_wsr_eps4, + ICLASS_xt_iclass_xsr_eps4, + ICLASS_xt_iclass_rsr_eps5, + ICLASS_xt_iclass_wsr_eps5, + ICLASS_xt_iclass_xsr_eps5, + ICLASS_xt_iclass_rsr_eps6, + ICLASS_xt_iclass_wsr_eps6, + ICLASS_xt_iclass_xsr_eps6, + ICLASS_xt_iclass_rsr_excvaddr, + ICLASS_xt_iclass_wsr_excvaddr, + ICLASS_xt_iclass_xsr_excvaddr, + ICLASS_xt_iclass_rsr_depc, + ICLASS_xt_iclass_wsr_depc, + ICLASS_xt_iclass_xsr_depc, + ICLASS_xt_iclass_rsr_exccause, + ICLASS_xt_iclass_wsr_exccause, + ICLASS_xt_iclass_xsr_exccause, + ICLASS_xt_iclass_rsr_misc0, + ICLASS_xt_iclass_wsr_misc0, + ICLASS_xt_iclass_xsr_misc0, + ICLASS_xt_iclass_rsr_misc1, + ICLASS_xt_iclass_wsr_misc1, + ICLASS_xt_iclass_xsr_misc1, + ICLASS_xt_iclass_rsr_misc2, + ICLASS_xt_iclass_wsr_misc2, + ICLASS_xt_iclass_xsr_misc2, + ICLASS_xt_iclass_rsr_misc3, + ICLASS_xt_iclass_wsr_misc3, + ICLASS_xt_iclass_xsr_misc3, + ICLASS_xt_iclass_rsr_prid, + ICLASS_xt_iclass_rsr_vecbase, + ICLASS_xt_iclass_wsr_vecbase, + ICLASS_xt_iclass_xsr_vecbase, + ICLASS_xt_iclass_rsr_mpucfg, + ICLASS_xt_iclass_wsr_mpucfg, + ICLASS_xt_iclass_salt, + ICLASS_xt_iclass_rsr_opmode, + ICLASS_xt_iclass_wsr_opmode, + ICLASS_xt_iclass_xsr_opmode, + ICLASS_xt_mul16, + ICLASS_xt_mul32, + ICLASS_xt_iclass_rfi, + ICLASS_xt_iclass_wait, + ICLASS_xt_iclass_rsr_interrupt, + ICLASS_xt_iclass_wsr_intset, + ICLASS_xt_iclass_wsr_intclear, + ICLASS_xt_iclass_rsr_intenable, + ICLASS_xt_iclass_wsr_intenable, + ICLASS_xt_iclass_xsr_intenable, + ICLASS_xt_iclass_break, + ICLASS_xt_iclass_break_n, + ICLASS_xt_iclass_rsr_dbreaka0, + ICLASS_xt_iclass_wsr_dbreaka0, + ICLASS_xt_iclass_xsr_dbreaka0, + ICLASS_xt_iclass_rsr_dbreakc0, + ICLASS_xt_iclass_wsr_dbreakc0, + ICLASS_xt_iclass_xsr_dbreakc0, + ICLASS_xt_iclass_rsr_dbreaka1, + ICLASS_xt_iclass_wsr_dbreaka1, + ICLASS_xt_iclass_xsr_dbreaka1, + ICLASS_xt_iclass_rsr_dbreakc1, + ICLASS_xt_iclass_wsr_dbreakc1, + ICLASS_xt_iclass_xsr_dbreakc1, + ICLASS_xt_iclass_rsr_ibreaka0, + ICLASS_xt_iclass_wsr_ibreaka0, + ICLASS_xt_iclass_xsr_ibreaka0, + ICLASS_xt_iclass_rsr_ibreaka1, + ICLASS_xt_iclass_wsr_ibreaka1, + ICLASS_xt_iclass_xsr_ibreaka1, + ICLASS_xt_iclass_rsr_ibreakenable, + ICLASS_xt_iclass_wsr_ibreakenable, + ICLASS_xt_iclass_xsr_ibreakenable, + ICLASS_xt_iclass_rsr_debugcause, + ICLASS_xt_iclass_wsr_debugcause, + ICLASS_xt_iclass_xsr_debugcause, + ICLASS_xt_iclass_rsr_icount, + ICLASS_xt_iclass_wsr_icount, + ICLASS_xt_iclass_xsr_icount, + ICLASS_xt_iclass_rsr_icountlevel, + ICLASS_xt_iclass_wsr_icountlevel, + ICLASS_xt_iclass_xsr_icountlevel, + ICLASS_xt_iclass_rsr_ddr, + ICLASS_xt_iclass_wsr_ddr, + ICLASS_xt_iclass_xsr_ddr, + ICLASS_xt_iclass_lddr32_p, + ICLASS_xt_iclass_sddr32_p, + ICLASS_xt_iclass_rfdo, + ICLASS_xt_iclass_rfdd, + ICLASS_xt_iclass_wsr_mmid, + ICLASS_xt_iclass_bbool1, + ICLASS_xt_iclass_bbool4, + ICLASS_xt_iclass_bbool8, + ICLASS_xt_iclass_bbranch, + ICLASS_xt_iclass_bmove, + ICLASS_xt_iclass_RSR_BR, + ICLASS_xt_iclass_WSR_BR, + ICLASS_xt_iclass_XSR_BR, + ICLASS_xt_iclass_rsr_ccount, + ICLASS_xt_iclass_wsr_ccount, + ICLASS_xt_iclass_xsr_ccount, + ICLASS_xt_iclass_rsr_ccompare0, + ICLASS_xt_iclass_wsr_ccompare0, + ICLASS_xt_iclass_xsr_ccompare0, + ICLASS_xt_iclass_rsr_ccompare1, + ICLASS_xt_iclass_wsr_ccompare1, + ICLASS_xt_iclass_xsr_ccompare1, + ICLASS_xt_iclass_rsr_ccompare2, + ICLASS_xt_iclass_wsr_ccompare2, + ICLASS_xt_iclass_xsr_ccompare2, + ICLASS_xt_iclass_icache, + ICLASS_xt_iclass_icache_lock, + ICLASS_xt_iclass_icache_inv, + ICLASS_xt_iclass_licx, + ICLASS_xt_iclass_sicx, + ICLASS_xt_iclass_dcache, + ICLASS_xt_iclass_dcache_dyn, + ICLASS_xt_iclass_dcache_ind, + ICLASS_xt_iclass_dcache_inv, + ICLASS_xt_iclass_dpf, + ICLASS_xt_iclass_dpfb, + ICLASS_xt_iclass_bpfnxt, + ICLASS_xt_iclass_dpdngrd, + ICLASS_xt_iclass_bpfctl, + ICLASS_xt_iclass_dcache_lock, + ICLASS_xt_iclass_sdct, + ICLASS_xt_iclass_ldct, + ICLASS_xt_iclass_sdcw, + ICLASS_xt_iclass_ldcw, + ICLASS_xt_iclass_rsr_prefctl, + ICLASS_xt_iclass_wsr_prefctl, + ICLASS_xt_iclass_xsr_prefctl, + ICLASS_xt_iclass_wsr_cacheadrdis, + ICLASS_xt_iclass_rsr_cacheadrdis, + ICLASS_xt_iclass_xsr_cacheadrdis, + ICLASS_xt_iclass_rptlb0, + ICLASS_xt_iclass_rptlb, + ICLASS_xt_iclass_wptlb, + ICLASS_xt_iclass_rsr_mpuenb, + ICLASS_xt_iclass_wsr_mpuenb, + ICLASS_xt_iclass_xsr_mpuenb, + ICLASS_xt_iclass_rsr_cpenable, + ICLASS_xt_iclass_wsr_cpenable, + ICLASS_xt_iclass_xsr_cpenable, + ICLASS_xt_iclass_clamp, + ICLASS_xt_iclass_minmax, + ICLASS_xt_iclass_nsa, + ICLASS_xt_iclass_sx, + ICLASS_xt_iclass_l32ai, + ICLASS_xt_iclass_s32ri, + ICLASS_xt_iclass_rsr_atomctl, + ICLASS_xt_iclass_wsr_atomctl, + ICLASS_xt_iclass_xsr_atomctl, + ICLASS_xt_iclass_div, + ICLASS_xt_iclass_rsr_eraccess, + ICLASS_xt_iclass_wsr_eraccess, + ICLASS_xt_iclass_xsr_eraccess, + ICLASS_xt_iclass_rer, + ICLASS_xt_iclass_wer, + ICLASS_xt_iclass_wb15_0, + ICLASS_xt_iclass_wb15_1, + ICLASS_xt_iclass_wb15_2, + ICLASS_xt_iclass_wb15_3, + ICLASS_xt_iclass_wb15_4, + ICLASS_rur_ae_ovf_sar, + ICLASS_wur_ae_ovf_sar, + ICLASS_rur_ae_bithead, + ICLASS_wur_ae_bithead, + ICLASS_rur_ae_ts_fts_bu_bp, + ICLASS_wur_ae_ts_fts_bu_bp, + ICLASS_rur_ae_cw_sd_no, + ICLASS_wur_ae_cw_sd_no, + ICLASS_rur_ae_cbegin0, + ICLASS_wur_ae_cbegin0, + ICLASS_rur_ae_cend0, + ICLASS_wur_ae_cend0, + ICLASS_rur_ae_cbegin1, + ICLASS_wur_ae_cbegin1, + ICLASS_rur_ae_cend1, + ICLASS_wur_ae_cend1, + ICLASS_rur_ae_cbegin2, + ICLASS_wur_ae_cbegin2, + ICLASS_rur_ae_cend2, + ICLASS_wur_ae_cend2, + ICLASS_ic_sext16, + ICLASS_ic_zext16, + ICLASS_ic_zext8, + ICLASS_ic_clamps16, + ICLASS_rur_fcr, + ICLASS_wur_fcr, + ICLASS_rur_fsr, + ICLASS_wur_fsr, + ICLASS_rur_expstate, + ICLASS_wur_expstate, + ICLASS_iclass_READ_IMPWIRE, + ICLASS_iclass_SETB_EXPSTATE, + ICLASS_iclass_CLRB_EXPSTATE, + ICLASS_iclass_WRMSK_EXPSTATE, + ICLASS_RUR_AE_OVERFLOW, + ICLASS_WUR_AE_OVERFLOW, + ICLASS_RUR_AE_SAR, + ICLASS_WUR_AE_SAR, + ICLASS_RUR_AE_BITPTR, + ICLASS_WUR_AE_BITPTR, + ICLASS_RUR_AE_BITSUSED, + ICLASS_WUR_AE_BITSUSED, + ICLASS_RUR_AE_TABLESIZE, + ICLASS_WUR_AE_TABLESIZE, + ICLASS_RUR_AE_FIRST_TS, + ICLASS_WUR_AE_FIRST_TS, + ICLASS_RUR_AE_NEXTOFFSET, + ICLASS_WUR_AE_NEXTOFFSET, + ICLASS_RUR_AE_SEARCHDONE, + ICLASS_WUR_AE_SEARCHDONE, + ICLASS_RUR_AE_CWRAP, + ICLASS_WUR_AE_CWRAP, + ICLASS_AE_L8X4F_I, + ICLASS_AE_L8X4F_IP, + ICLASS_AE_L8X4F_X, + ICLASS_AE_L8X4F_XP, + ICLASS_AE_L8X4S_I, + ICLASS_AE_L8X4S_IP, + ICLASS_AE_L8X4S_X, + ICLASS_AE_L8X4S_XP, + ICLASS_AE_L8X4U_I, + ICLASS_AE_L8X4U_IP, + ICLASS_AE_L8X4U_X, + ICLASS_AE_L8X4U_XP, + ICLASS_AE_L16M_XC, + ICLASS_AE_L16M_XC1, + ICLASS_AE_L16M_I, + ICLASS_AE_L16M_IU, + ICLASS_AE_L16M_X, + ICLASS_AE_L16M_XU, + ICLASS_AE_L16_XC, + ICLASS_AE_L16_XC1, + ICLASS_AE_L16_I, + ICLASS_AE_L16_IP, + ICLASS_AE_L16_X, + ICLASS_AE_L16_XP, + ICLASS_AE_L8_XC, + ICLASS_AE_L8_XC1, + ICLASS_AE_L8_I, + ICLASS_AE_L8_IP, + ICLASS_AE_L8_X, + ICLASS_AE_L8_XP, + ICLASS_AE_L32F24_XC, + ICLASS_AE_L32F24_XC1, + ICLASS_AE_L32F24_I, + ICLASS_AE_L32F24_IP, + ICLASS_AE_L32F24_X, + ICLASS_AE_L32F24_XP, + ICLASS_AE_L32_XC, + ICLASS_AE_L32_XC1, + ICLASS_AE_L32_I, + ICLASS_AE_L32_IP, + ICLASS_AE_L32_X, + ICLASS_AE_L32_XP, + ICLASS_AE_L32M_XC, + ICLASS_AE_L32M_I, + ICLASS_AE_L32M_IU, + ICLASS_AE_L32M_X, + ICLASS_AE_L32M_XU, + ICLASS_AE_L16X2M_XC, + ICLASS_AE_L16X2M_XC1, + ICLASS_AE_L16X2M_I, + ICLASS_AE_L16X2M_IU, + ICLASS_AE_L16X2M_X, + ICLASS_AE_L16X2M_XU, + ICLASS_AE_L32X2F24_XC, + ICLASS_AE_L32X2F24_XC1, + ICLASS_AE_L32X2F24_I, + ICLASS_AE_L32X2F24_IP, + ICLASS_AE_L32X2F24_RIP, + ICLASS_AE_L32X2F24_RI, + ICLASS_AE_L32X2F24_RIC, + ICLASS_AE_L32X2F24_RIC1, + ICLASS_AE_L32X2F24_X, + ICLASS_AE_L32X2F24_XP, + ICLASS_AE_L32X2_XC, + ICLASS_AE_L32X2_XC1, + ICLASS_AE_L32X2_I, + ICLASS_AE_L32X2_IP, + ICLASS_AE_L32X2_RIC, + ICLASS_AE_L32X2_RIC1, + ICLASS_AE_L32X2_X, + ICLASS_AE_L32X2_XP, + ICLASS_AE_L16X4_XC, + ICLASS_AE_L16X4_XC1, + ICLASS_AE_L16X4_I, + ICLASS_AE_L16X4_IP, + ICLASS_AE_L16X4_X, + ICLASS_AE_L16X4_XP, + ICLASS_AE_L8X8_XC, + ICLASS_AE_L8X8_XC1, + ICLASS_AE_L8X8_I, + ICLASS_AE_L8X8_IP, + ICLASS_AE_L8X8_X, + ICLASS_AE_L8X8_XP, + ICLASS_AE_L64_XC, + ICLASS_AE_L64_XC1, + ICLASS_AE_L64_I, + ICLASS_AE_L64_IP, + ICLASS_AE_L64_X, + ICLASS_AE_L64_XP, + ICLASS_AE_S16X2M_XC, + ICLASS_AE_S16X2M_XC1, + ICLASS_AE_S16X2M_I, + ICLASS_AE_S16X2M_IU, + ICLASS_AE_S16X2M_X, + ICLASS_AE_S16X2M_XU, + ICLASS_AE_S32X2F24_XC, + ICLASS_AE_S32X2F24_XC1, + ICLASS_AE_S32X2F24_I, + ICLASS_AE_S32X2F24_IP, + ICLASS_AE_S32X2F24_RIP, + ICLASS_AE_S32X2F24_RIC, + ICLASS_AE_S32X2F24_RIC1, + ICLASS_AE_S32X2F24_X, + ICLASS_AE_S32X2F24_XP, + ICLASS_AE_S32X2_XC, + ICLASS_AE_S32X2_XC1, + ICLASS_AE_S32X2_I, + ICLASS_AE_S32X2_IP, + ICLASS_AE_S32X2_RIC, + ICLASS_AE_S32X2_RIC1, + ICLASS_AE_S32X2_X, + ICLASS_AE_S32X2_XP, + ICLASS_AE_S32X2RNG_I, + ICLASS_AE_S32X2RNG_IP, + ICLASS_AE_S32X2RNG_X, + ICLASS_AE_S32X2RNG_XP, + ICLASS_AE_S16X4_XC, + ICLASS_AE_S16X4_XC1, + ICLASS_AE_S16X4_I, + ICLASS_AE_S16X4_IP, + ICLASS_AE_S16X4_X, + ICLASS_AE_S16X4_XP, + ICLASS_AE_S8X8_XC, + ICLASS_AE_S8X8_XC1, + ICLASS_AE_S8X8_I, + ICLASS_AE_S8X8_IP, + ICLASS_AE_S8X8_X, + ICLASS_AE_S8X8_XP, + ICLASS_AE_S16M_L_XC, + ICLASS_AE_S16M_L_XC1, + ICLASS_AE_S16M_L_I, + ICLASS_AE_S16M_L_IU, + ICLASS_AE_S16M_L_X, + ICLASS_AE_S16M_L_XU, + ICLASS_AE_S32F24_L_XC, + ICLASS_AE_S32F24_L_XC1, + ICLASS_AE_S32F24_L_I, + ICLASS_AE_S32F24_L_IP, + ICLASS_AE_S32F24_L_X, + ICLASS_AE_S32F24_L_XP, + ICLASS_AE_S32_L_XC, + ICLASS_AE_S32_L_XC1, + ICLASS_AE_S32_L_I, + ICLASS_AE_S32_L_IP, + ICLASS_AE_S32_L_X, + ICLASS_AE_S32_L_XP, + ICLASS_AE_S32_H_XC, + ICLASS_AE_S32_H_XC1, + ICLASS_AE_S32_H_I, + ICLASS_AE_S32_H_IP, + ICLASS_AE_S32_H_X, + ICLASS_AE_S32_H_XP, + ICLASS_AE_S16_0_XC, + ICLASS_AE_S16_0_XC1, + ICLASS_AE_S16_0_I, + ICLASS_AE_S16_0_IP, + ICLASS_AE_S16_0_X, + ICLASS_AE_S16_0_XP, + ICLASS_AE_S8_0_XC, + ICLASS_AE_S8_0_XC1, + ICLASS_AE_S8_0_I, + ICLASS_AE_S8_0_IP, + ICLASS_AE_S8_0_X, + ICLASS_AE_S8_0_XP, + ICLASS_AE_S64_XC, + ICLASS_AE_S64_XC1, + ICLASS_AE_S64_I, + ICLASS_AE_S64_IP, + ICLASS_AE_S64_X, + ICLASS_AE_S64_XP, + ICLASS_AE_S32M_XC, + ICLASS_AE_S32M_I, + ICLASS_AE_S32M_IU, + ICLASS_AE_S32M_X, + ICLASS_AE_S32M_XU, + ICLASS_AE_L32X2_XC2, + ICLASS_AE_L16X4_XC2, + ICLASS_AE_L8X8_XC2, + ICLASS_AE_L64_XC2, + ICLASS_AE_S32X2_XC2, + ICLASS_AE_S16X4_XC2, + ICLASS_AE_S8X8_XC2, + ICLASS_AE_S64_XC2, + ICLASS_AE_S16X4RNG_I, + ICLASS_AE_S16X4RNG_IP, + ICLASS_AE_S16X4RNG_X, + ICLASS_AE_S16X4RNG_XP, + ICLASS_AE_L32X2X2_XC, + ICLASS_AE_L32X2X2_XC1, + ICLASS_AE_L32X2X2_I, + ICLASS_AE_L32X2X2_IP, + ICLASS_AE_L32X2X2_X, + ICLASS_AE_L32X2X2_XP, + ICLASS_AE_L16X4X2_XC, + ICLASS_AE_L16X4X2_XC1, + ICLASS_AE_L16X4X2_I, + ICLASS_AE_L16X4X2_IP, + ICLASS_AE_L16X4X2_X, + ICLASS_AE_L16X4X2_XP, + ICLASS_AE_L8X8X2_XC, + ICLASS_AE_L8X8X2_XC1, + ICLASS_AE_L8X8X2_I, + ICLASS_AE_L8X8X2_IP, + ICLASS_AE_L8X8X2_X, + ICLASS_AE_L8X8X2_XP, + ICLASS_AE_L64X2_XC, + ICLASS_AE_L64X2_XC1, + ICLASS_AE_L64X2_I, + ICLASS_AE_L64X2_IP, + ICLASS_AE_L64X2_X, + ICLASS_AE_L64X2_XP, + ICLASS_AE_S32X2X2_XC, + ICLASS_AE_S32X2X2_XC1, + ICLASS_AE_S32X2X2_I, + ICLASS_AE_S32X2X2_IP, + ICLASS_AE_S32X2X2_X, + ICLASS_AE_S32X2X2_XP, + ICLASS_AE_S32X2X2RNG_I, + ICLASS_AE_S32X2X2RNG_IP, + ICLASS_AE_S32X2X2RNG_X, + ICLASS_AE_S32X2X2RNG_XP, + ICLASS_AE_S16X4X2_XC, + ICLASS_AE_S16X4X2_XC1, + ICLASS_AE_S16X4X2_I, + ICLASS_AE_S16X4X2_IP, + ICLASS_AE_S16X4X2_X, + ICLASS_AE_S16X4X2_XP, + ICLASS_AE_S8X8X2_XC, + ICLASS_AE_S8X8X2_XC1, + ICLASS_AE_S8X8X2_I, + ICLASS_AE_S8X8X2_IP, + ICLASS_AE_S8X8X2_X, + ICLASS_AE_S8X8X2_XP, + ICLASS_AE_S64X2_XC, + ICLASS_AE_S64X2_XC1, + ICLASS_AE_S64X2_I, + ICLASS_AE_S64X2_IP, + ICLASS_AE_S64X2_X, + ICLASS_AE_S64X2_XP, + ICLASS_AE_L32X2X2_XC2, + ICLASS_AE_L16X4X2_XC2, + ICLASS_AE_L8X8X2_XC2, + ICLASS_AE_L64X2_XC2, + ICLASS_AE_S32X2X2_XC2, + ICLASS_AE_S16X4X2_XC2, + ICLASS_AE_S8X8X2_XC2, + ICLASS_AE_S64X2_XC2, + ICLASS_AE_S16X4X2RNG_I, + ICLASS_AE_S16X4X2RNG_IP, + ICLASS_AE_S16X4X2RNG_X, + ICLASS_AE_S16X4X2RNG_XP, + ICLASS_AE_ZALIGN64, + ICLASS_AE_LALIGN64_I, + ICLASS_AE_SALIGN64_I, + ICLASS_AE_MOVALIGN, + ICLASS_AE_LA64_PP, + ICLASS_AE_LA24POS_PC, + ICLASS_AE_LA24NEG_PC, + ICLASS_AE_LA24POS_PC1, + ICLASS_AE_LA24NEG_PC1, + ICLASS_AE_LA24X2POS_PC, + ICLASS_AE_LA24X2NEG_PC, + ICLASS_AE_LA24X2POS_PC1, + ICLASS_AE_LA24X2NEG_PC1, + ICLASS_AE_LA32X2POS_PC, + ICLASS_AE_LA32X2NEG_PC, + ICLASS_AE_LA32X2POS_PC1, + ICLASS_AE_LA32X2NEG_PC1, + ICLASS_AE_LA32X2POS_PC2, + ICLASS_AE_LA16X4POS_PC, + ICLASS_AE_LA16X4NEG_PC, + ICLASS_AE_LA16X4POS_PC1, + ICLASS_AE_LA16X4NEG_PC1, + ICLASS_AE_LA16X4POS_PC2, + ICLASS_AE_LA8X8POS_PC, + ICLASS_AE_LA8X8NEG_PC, + ICLASS_AE_LA8X8POS_PC1, + ICLASS_AE_LA8X8NEG_PC1, + ICLASS_AE_LA8X8POS_PC2, + ICLASS_AE_LA32X2X2POS_PC, + ICLASS_AE_LA32X2X2POS_PC1, + ICLASS_AE_LA32X2X2POS_PC2, + ICLASS_AE_LA16X4X2POS_PC, + ICLASS_AE_LA16X4X2POS_PC1, + ICLASS_AE_LA16X4X2POS_PC2, + ICLASS_AE_LA8X8X2POS_PC, + ICLASS_AE_LA8X8X2POS_PC1, + ICLASS_AE_LA8X8X2POS_PC2, + ICLASS_AE_SA64POS_FP, + ICLASS_AE_SA64NEG_FP, + ICLASS_AE_LA32X2_IC, + ICLASS_AE_LA32X2_IC1, + ICLASS_AE_LA32X2_IC2, + ICLASS_AE_LA32X2_IP, + ICLASS_AE_LA32X2_RIP, + ICLASS_AE_LA32X2_RIC, + ICLASS_AE_LA32X2_RIC1, + ICLASS_AE_LA16X4_IC, + ICLASS_AE_LA16X4_IC1, + ICLASS_AE_LA16X4_IC2, + ICLASS_AE_LA16X4_IP, + ICLASS_AE_LA16X4_RIP, + ICLASS_AE_LA16X4_RIC, + ICLASS_AE_LA16X4_RIC1, + ICLASS_AE_LA8X8_IC, + ICLASS_AE_LA8X8_IC1, + ICLASS_AE_LA8X8_IC2, + ICLASS_AE_LA8X8_IP, + ICLASS_AE_LA8X8_RIP, + ICLASS_AE_LA8X8_RIC, + ICLASS_AE_LA8X8_RIC1, + ICLASS_AE_LA32X2F24_IC, + ICLASS_AE_LA32X2F24_IC1, + ICLASS_AE_LA32X2F24_IP, + ICLASS_AE_LA32X2F24_RIP, + ICLASS_AE_LA32X2F24_RIC, + ICLASS_AE_LA32X2F24_RIC1, + ICLASS_AE_LA24_IC, + ICLASS_AE_LA24_IC1, + ICLASS_AE_LA24_IP, + ICLASS_AE_LA24_RIP, + ICLASS_AE_LA24_RIC, + ICLASS_AE_LA24_RIC1, + ICLASS_AE_LA24X2_IC, + ICLASS_AE_LA24X2_IC1, + ICLASS_AE_LA24X2_IP, + ICLASS_AE_LA24X2_RIP, + ICLASS_AE_LA24X2_RIC, + ICLASS_AE_LA24X2_RIC1, + ICLASS_AE_SA32X2_IC, + ICLASS_AE_SA32X2_IC1, + ICLASS_AE_SA32X2_IC2, + ICLASS_AE_SA32X2_IP, + ICLASS_AE_SA32X2_RIP, + ICLASS_AE_SA32X2_RIC, + ICLASS_AE_SA32X2_RIC1, + ICLASS_AE_SA16X4_IC, + ICLASS_AE_SA16X4_IC1, + ICLASS_AE_SA16X4_IC2, + ICLASS_AE_SA16X4_IP, + ICLASS_AE_SA16X4_RIP, + ICLASS_AE_SA16X4_RIC, + ICLASS_AE_SA16X4_RIC1, + ICLASS_AE_SA8X8_IC, + ICLASS_AE_SA8X8_IC1, + ICLASS_AE_SA8X8_IC2, + ICLASS_AE_SA8X8_IP, + ICLASS_AE_SA8X8_RIP, + ICLASS_AE_SA8X8_RIC, + ICLASS_AE_SA8X8_RIC1, + ICLASS_AE_SA32X2F24_IC, + ICLASS_AE_SA32X2F24_IC1, + ICLASS_AE_SA32X2F24_IP, + ICLASS_AE_SA32X2F24_RIP, + ICLASS_AE_SA32X2F24_RIC, + ICLASS_AE_SA32X2F24_RIC1, + ICLASS_AE_SA24_L_IC, + ICLASS_AE_SA24_L_IC1, + ICLASS_AE_SA24_L_IP, + ICLASS_AE_SA24_L_RIP, + ICLASS_AE_SA24_L_RIC, + ICLASS_AE_SA24_L_RIC1, + ICLASS_AE_SA24X2_IC, + ICLASS_AE_SA24X2_IC1, + ICLASS_AE_SA24X2_IP, + ICLASS_AE_SA24X2_RIP, + ICLASS_AE_SA24X2_RIC, + ICLASS_AE_SA24X2_RIC1, + ICLASS_AE_ADDICIRC, + ICLASS_AE_ADDCIRC_XC2, + ICLASS_AE_ADDCIRC_XC1, + ICLASS_AE_ADDCIRC_XC, + ICLASS_AE_S32RA64S_I, + ICLASS_AE_S32RA64S_IP, + ICLASS_AE_S32RA64S_X, + ICLASS_AE_S32RA64S_XP, + ICLASS_AE_S32RA64S_XC, + ICLASS_AE_S32RA64S_XC1, + ICLASS_AE_S24RA64S_I, + ICLASS_AE_S24RA64S_IP, + ICLASS_AE_S24RA64S_X, + ICLASS_AE_S24RA64S_XP, + ICLASS_AE_S24RA64S_XC, + ICLASS_AE_S24RA64S_XC1, + ICLASS_AE_S32X2RA64S_IP, + ICLASS_AE_S24X2RA64S_IP, + ICLASS_AE_S16X4RA32S_IP, + ICLASS_AE_ADDBRBA32, + ICLASS_AE_S32X2_L_IP, + ICLASS_AE_BITSWAP, + ICLASS_AE_MUL32JS, + ICLASS_AE_ADDANDSUB32S, + ICLASS_AE_ADDANDSUB32JS, + ICLASS_AE_ADDANDSUBRNG32, + ICLASS_AE_ADDANDSUBRNG32_H, + ICLASS_AE_ADDANDSUBRNG32_L, + ICLASS_AE_ADDRNG32, + ICLASS_AE_SUBRNG32, + ICLASS_AE_RNG32X2, + ICLASS_AE_SEL16I, + ICLASS_AE_SEL16I_N, + ICLASS_AE_SHORTSWAP, + ICLASS_AE_MOVAB4, + ICLASS_AE_MOVAB2, + ICLASS_AE_MOVAB, + ICLASS_AE_MOVBA, + ICLASS_AE_MOVBA1X2, + ICLASS_AE_MOVBA4, + ICLASS_AE_MOVBA2, + ICLASS_AE_MOVB2, + ICLASS_AE_MOVB4, + ICLASS_AE_MOVT16X4, + ICLASS_AE_MOVF16X4, + ICLASS_AE_MOVT32X2, + ICLASS_AE_MOVF32X2, + ICLASS_AE_MOVSARA7X2, + ICLASS_AE_MOVSARD7, + ICLASS_AE_MOVASAR, + ICLASS_AE_MOVDA32X2, + ICLASS_AE_MOVDA32, + ICLASS_AE_MOVDA16X2, + ICLASS_AE_MOVDA16, + ICLASS_AE_MOVI, + ICLASS_AE_TRUNCP24A32X2, + ICLASS_AE_SAT16X4, + ICLASS_AE_CVT32X2F16_32, + ICLASS_AE_CVT32X2F16_10, + ICLASS_AE_SEXT32X2D16_32, + ICLASS_AE_SEXT32X2D16_10, + ICLASS_AE_CVTA32F24S_L, + ICLASS_AE_CVTA32F24S_H, + ICLASS_AE_CVTP24A16X2_LL, + ICLASS_AE_CVTP24A16X2_LH, + ICLASS_AE_CVTP24A16X2_HL, + ICLASS_AE_CVTP24A16X2_HH, + ICLASS_AE_TRUNCP24Q48X2, + ICLASS_AE_TRUNCA32X2F64S, + ICLASS_AE_TRUNCI32X2F64S, + ICLASS_AE_TRUNCA32F64S_L, + ICLASS_AE_TRUNCI32F64S_L, + ICLASS_AE_TRUNCP16, + ICLASS_AE_ROUND32X2F64SSYM, + ICLASS_AE_ROUND32X2F64SASYM, + ICLASS_AE_ROUND32X2F48SSYM, + ICLASS_AE_ROUND32X2F48SASYM, + ICLASS_AE_ROUND16X4F32SSYM, + ICLASS_AE_ROUND16X4F32SASYM, + ICLASS_AE_ROUND24X2F48SSYM, + ICLASS_AE_ROUND24X2F48SASYM, + ICLASS_AE_ROUNDSP16Q48X2SYM, + ICLASS_AE_ROUNDSP16Q48X2ASYM, + ICLASS_AE_MINABS32S, + ICLASS_AE_MAXABS32S, + ICLASS_AE_ROUNDSP16F24SYM, + ICLASS_AE_ROUNDSP16F24ASYM, + ICLASS_AE_MOV, + ICLASS_AE_MOVT64, + ICLASS_AE_MOVF64, + ICLASS_AE_CVTQ56A32S, + ICLASS_AE_CVT48A32, + ICLASS_AE_CVT64A32, + ICLASS_AE_CVTQ56P32S_L, + ICLASS_AE_CVTQ56P32S_H, + ICLASS_AE_CVT64F32_H, + ICLASS_AE_CVT48F32_L, + ICLASS_AE_CVT48F32_H, + ICLASS_AE_SAT48S, + ICLASS_AE_SATQ56S, + ICLASS_AE_SAT24S, + ICLASS_AE_TRUNCQ32, + ICLASS_AE_MINABS64S, + ICLASS_AE_MAXABS64S, + ICLASS_AE_ROUNDSQ32F48SYM, + ICLASS_AE_ROUNDSQ32F48ASYM, + ICLASS_AE_TRUNCA32Q48, + ICLASS_AE_MOVAD32_L, + ICLASS_AE_MOVAD32_H, + ICLASS_AE_MOVAD16_3, + ICLASS_AE_MOVAD16_2, + ICLASS_AE_MOVAD16_1, + ICLASS_AE_MOVAD16_0, + ICLASS_AE_SRA64_32, + ICLASS_AE_PKSR32, + ICLASS_AE_PKSR24, + ICLASS_AE_PKSRF32, + ICLASS_AE_PKSR16, + ICLASS_AE_TRUNCA16P24S_L, + ICLASS_AE_TRUNCA16P24S_H, + ICLASS_AE_ADD32, + ICLASS_AE_SUB32, + ICLASS_AE_ADDSUB32, + ICLASS_AE_SUBADD32, + ICLASS_AE_ADD16, + ICLASS_AE_SUB16, + ICLASS_AE_ADD32_HL_LH, + ICLASS_AE_ADDSUB32_HL_LH, + ICLASS_AE_NEG32, + ICLASS_AE_ABS32, + ICLASS_AE_NEG32_L, + ICLASS_AE_ADD24S, + ICLASS_AE_SUB24S, + ICLASS_AE_ADD32S, + ICLASS_AE_SUB32S, + ICLASS_AE_ADDSUB32S, + ICLASS_AE_SUBADD32S, + ICLASS_AE_ADD16S, + ICLASS_AE_SUB16S, + ICLASS_AE_ADD32S_HL_LH, + ICLASS_AE_ADDSUB32S_HL_LH, + ICLASS_AE_NEG24S, + ICLASS_AE_ABS24S, + ICLASS_AE_NEG32S, + ICLASS_AE_ABS32S, + ICLASS_AE_NEG16S, + ICLASS_AE_ABS16S, + ICLASS_AE_ABS16, + ICLASS_AE_MULC16JS_H, + ICLASS_AE_MULC16JS_L, + ICLASS_AE_MULAC16JS_H, + ICLASS_AE_MULAC16JS_L, + ICLASS_AE_LT16, + ICLASS_AE_LE16, + ICLASS_AE_EQ16, + ICLASS_AE_LT32, + ICLASS_AE_LE32, + ICLASS_AE_EQ32, + ICLASS_AE_MIN32, + ICLASS_AE_MAX32, + ICLASS_AE_MINMAX32, + ICLASS_AE_MINMAX16, + ICLASS_AE_MIN16, + ICLASS_AE_MAX16, + ICLASS_AE_ADD64, + ICLASS_AE_SUB64, + ICLASS_AE_NEG64, + ICLASS_AE_ABS64, + ICLASS_AE_ADDSQ56S, + ICLASS_AE_SUBSQ56S, + ICLASS_AE_ADD64S, + ICLASS_AE_SUB64S, + ICLASS_AE_NEGSQ56S, + ICLASS_AE_ABSSQ56S, + ICLASS_AE_NEG64S, + ICLASS_AE_ABS64S, + ICLASS_AE_AND, + ICLASS_AE_NAND, + ICLASS_AE_OR, + ICLASS_AE_XOR, + ICLASS_AE_SLAI24, + ICLASS_AE_SRLI24, + ICLASS_AE_SRAI24, + ICLASS_AE_SLAS24, + ICLASS_AE_SRLS24, + ICLASS_AE_SRAS24, + ICLASS_AE_SRAI16, + ICLASS_AE_SRAI16R, + ICLASS_AE_SLAI32, + ICLASS_AE_SRLI32, + ICLASS_AE_SRAI32, + ICLASS_AE_SRAI32R, + ICLASS_AE_SLAS32, + ICLASS_AE_SRLS32, + ICLASS_AE_SRAS32, + ICLASS_AE_SLAA32, + ICLASS_AE_SRLA32, + ICLASS_AE_SRAA32, + ICLASS_AE_SLAI16S, + ICLASS_AE_SLAA16S, + ICLASS_AE_SRAA16S, + ICLASS_AE_SRAA16RS, + ICLASS_AE_SLAI24S, + ICLASS_AE_SLAS24S, + ICLASS_AE_SLAI32S, + ICLASS_AE_SLAS32S, + ICLASS_AE_SLAA32S, + ICLASS_AE_SRAA32S, + ICLASS_AE_SRAA32RS, + ICLASS_AE_SLASQ56, + ICLASS_AE_SRLSQ56, + ICLASS_AE_SRASQ56, + ICLASS_AE_SLAAQ56, + ICLASS_AE_SRLAQ56, + ICLASS_AE_SRAAQ56, + ICLASS_AE_SLAI64, + ICLASS_AE_SRLI64, + ICLASS_AE_SRAI64, + ICLASS_AE_SLAS64, + ICLASS_AE_SRLS64, + ICLASS_AE_SRAS64, + ICLASS_AE_SLAA64, + ICLASS_AE_SRLA64, + ICLASS_AE_SRAA64, + ICLASS_AE_SLAISQ56S, + ICLASS_AE_SLASSQ56S, + ICLASS_AE_SLAASQ56S, + ICLASS_AE_SLAI64S, + ICLASS_AE_SLAS64S, + ICLASS_AE_SLAA64S, + ICLASS_AE_LT64, + ICLASS_AE_LE64, + ICLASS_AE_EQ64, + ICLASS_AE_MAX64, + ICLASS_AE_MIN64, + ICLASS_AE_NSA64, + ICLASS_AE_NSAZ16_0, + ICLASS_AE_NSAZ32_L, + ICLASS_AE_MULS32F48P16S_LL, + ICLASS_AE_MULF32S_LL, + ICLASS_AE_MUL32_LL, + ICLASS_AE_MULF32R_LL, + ICLASS_AE_MULF32RA_LL, + ICLASS_AE_MULS32F48P16S_LH, + ICLASS_AE_MULF32S_LH, + ICLASS_AE_MUL32_LH, + ICLASS_AE_MULF32R_LH, + ICLASS_AE_MULF32RA_LH, + ICLASS_AE_MULS32F48P16S_HH, + ICLASS_AE_MULF32S_HH, + ICLASS_AE_MUL32_HH, + ICLASS_AE_MULF32R_HH, + ICLASS_AE_MULF32RA_HH, + ICLASS_AE_MULAS32F48P16S_LL, + ICLASS_AE_MULAF32S_LL, + ICLASS_AE_MULA32_LL, + ICLASS_AE_MULAF32R_LL, + ICLASS_AE_MULAF32RA_LL, + ICLASS_AE_MULAS32F48P16S_LH, + ICLASS_AE_MULAF32S_LH, + ICLASS_AE_MULA32_LH, + ICLASS_AE_MULAF32R_LH, + ICLASS_AE_MULAF32RA_LH, + ICLASS_AE_MULAS32F48P16S_HH, + ICLASS_AE_MULAF32S_HH, + ICLASS_AE_MULA32_HH, + ICLASS_AE_MULAF32R_HH, + ICLASS_AE_MULAF32RA_HH, + ICLASS_AE_MULSS32F48P16S_LL, + ICLASS_AE_MULSF32S_LL, + ICLASS_AE_MULS32_LL, + ICLASS_AE_MULSF32R_LL, + ICLASS_AE_MULSF32RA_LL, + ICLASS_AE_MULSS32F48P16S_LH, + ICLASS_AE_MULSF32S_LH, + ICLASS_AE_MULS32_LH, + ICLASS_AE_MULSF32R_LH, + ICLASS_AE_MULSF32RA_LH, + ICLASS_AE_MULSS32F48P16S_HH, + ICLASS_AE_MULSF32S_HH, + ICLASS_AE_MULS32_HH, + ICLASS_AE_MULSF32R_HH, + ICLASS_AE_MULSF32RA_HH, + ICLASS_AE_MUL32U_LL, + ICLASS_AE_MULA32U_LL, + ICLASS_AE_MULS32U_LL, + ICLASS_AE_MULF16SS_33, + ICLASS_AE_MULF16SS_22, + ICLASS_AE_MULF16SS_32, + ICLASS_AE_MULF16SS_21, + ICLASS_AE_MULF16SS_31, + ICLASS_AE_MULF16SS_30, + ICLASS_AE_MULF16SS_10, + ICLASS_AE_MULF16SS_20, + ICLASS_AE_MULF16SS_11, + ICLASS_AE_MULF16SS_00, + ICLASS_AE_MULSF16SS_33, + ICLASS_AE_MULSF16SS_22, + ICLASS_AE_MULSF16SS_32, + ICLASS_AE_MULSF16SS_21, + ICLASS_AE_MULSF16SS_31, + ICLASS_AE_MULSF16SS_30, + ICLASS_AE_MULSF16SS_10, + ICLASS_AE_MULSF16SS_20, + ICLASS_AE_MULSF16SS_11, + ICLASS_AE_MULSF16SS_00, + ICLASS_AE_MULAF16SS_33, + ICLASS_AE_MULAF16SS_22, + ICLASS_AE_MULAF16SS_32, + ICLASS_AE_MULAF16SS_21, + ICLASS_AE_MULAF16SS_31, + ICLASS_AE_MULAF16SS_30, + ICLASS_AE_MULAF16SS_10, + ICLASS_AE_MULAF16SS_20, + ICLASS_AE_MULAF16SS_11, + ICLASS_AE_MULAF16SS_00, + ICLASS_AE_MUL16S_00, + ICLASS_AE_MULA16S_00, + ICLASS_AE_MULS16S_00, + ICLASS_AE_MULAAFD16SS_33_22, + ICLASS_AE_MULAAFD16SS_13_02, + ICLASS_AE_MULAAFD16SS_11_00, + ICLASS_AE_MULSSFD16SS_33_22, + ICLASS_AE_MULSSFD16SS_13_02, + ICLASS_AE_MULSSFD16SS_11_00, + ICLASS_AE_MULZAAFD16SS_33_22, + ICLASS_AE_MULZAAFD16SS_13_02, + ICLASS_AE_MULZAAFD16SS_11_00, + ICLASS_AE_MULZSSFD16SS_33_22, + ICLASS_AE_MULZSSFD16SS_13_02, + ICLASS_AE_MULZSSFD16SS_11_00, + ICLASS_AE_MULF48Q32SP16S_L, + ICLASS_AE_MULF48Q32SP16U_L, + ICLASS_AE_MULQ32SP16S_L, + ICLASS_AE_MULQ32SP16U_L, + ICLASS_AE_MULAF48Q32SP16S_L, + ICLASS_AE_MULAF48Q32SP16U_L, + ICLASS_AE_MULAQ32SP16S_L, + ICLASS_AE_MULAQ32SP16U_L, + ICLASS_AE_MULSF48Q32SP16S_L, + ICLASS_AE_MULSF48Q32SP16U_L, + ICLASS_AE_MULSQ32SP16S_L, + ICLASS_AE_MULSQ32SP16U_L, + ICLASS_AE_MULFP24X2RA, + ICLASS_AE_MULFP24X2R, + ICLASS_AE_MULAFP24X2RA, + ICLASS_AE_MULAFP24X2R, + ICLASS_AE_MULSFP24X2RA, + ICLASS_AE_MULSFP24X2R, + ICLASS_AE_MULZAAFD32S_HH_LL, + ICLASS_AE_MULZAAFD32RA_HH_LL, + ICLASS_AE_MULZAAD32_HH_LL, + ICLASS_AE_MULZAAFD32S_HL_LH, + ICLASS_AE_MULZAAFD32RA_HL_LH, + ICLASS_AE_MULZAAD32_HL_LH, + ICLASS_AE_MULZASFD32S_HH_LL, + ICLASS_AE_MULZASFD32RA_HH_LL, + ICLASS_AE_MULZASD32_HH_LL, + ICLASS_AE_MULZASFD32S_HL_LH, + ICLASS_AE_MULZASFD32RA_HL_LH, + ICLASS_AE_MULZASD32_HL_LH, + ICLASS_AE_MULZSAFD32S_HH_LL, + ICLASS_AE_MULZSAFD32RA_HH_LL, + ICLASS_AE_MULZSAD32_HH_LL, + ICLASS_AE_MULZSSFD32S_HH_LL, + ICLASS_AE_MULZSSFD32RA_HH_LL, + ICLASS_AE_MULZSSD32_HH_LL, + ICLASS_AE_MULZSSFD32S_HL_LH, + ICLASS_AE_MULZSSFD32RA_HL_LH, + ICLASS_AE_MULZSSD32_HL_LH, + ICLASS_AE_MULAAFD32S_HH_LL, + ICLASS_AE_MULAAFD32RA_HH_LL, + ICLASS_AE_MULAAD32_HH_LL, + ICLASS_AE_MULAAFD32S_HL_LH, + ICLASS_AE_MULAAFD32RA_HL_LH, + ICLASS_AE_MULAAD32_HL_LH, + ICLASS_AE_MULASFD32S_HH_LL, + ICLASS_AE_MULASFD32RA_HH_LL, + ICLASS_AE_MULASD32_HH_LL, + ICLASS_AE_MULASFD32S_HL_LH, + ICLASS_AE_MULASFD32RA_HL_LH, + ICLASS_AE_MULASD32_HL_LH, + ICLASS_AE_MULSAFD32S_HH_LL, + ICLASS_AE_MULSAFD32RA_HH_LL, + ICLASS_AE_MULSAD32_HH_LL, + ICLASS_AE_MULSSFD32S_HH_LL, + ICLASS_AE_MULSSFD32RA_HH_LL, + ICLASS_AE_MULSSD32_HH_LL, + ICLASS_AE_MULSSFD32S_HL_LH, + ICLASS_AE_MULSSFD32RA_HL_LH, + ICLASS_AE_MULSSD32_HL_LH, + ICLASS_AE_MULF32X16_L0, + ICLASS_AE_MUL32X16_L0, + ICLASS_AE_MULF32X16_L1, + ICLASS_AE_MUL32X16_L1, + ICLASS_AE_MULF32X16_L2, + ICLASS_AE_MUL32X16_L2, + ICLASS_AE_MULF32X16_L3, + ICLASS_AE_MUL32X16_L3, + ICLASS_AE_MULF32X16_H0, + ICLASS_AE_MUL32X16_H0, + ICLASS_AE_MULF32X16_H1, + ICLASS_AE_MUL32X16_H1, + ICLASS_AE_MULF32X16_H2, + ICLASS_AE_MUL32X16_H2, + ICLASS_AE_MULF32X16_H3, + ICLASS_AE_MUL32X16_H3, + ICLASS_AE_MULAF32X16_L0, + ICLASS_AE_MULA32X16_L0, + ICLASS_AE_MULAF32X16_L1, + ICLASS_AE_MULA32X16_L1, + ICLASS_AE_MULAF32X16_L2, + ICLASS_AE_MULA32X16_L2, + ICLASS_AE_MULAF32X16_L3, + ICLASS_AE_MULA32X16_L3, + ICLASS_AE_MULAF32X16_H0, + ICLASS_AE_MULA32X16_H0, + ICLASS_AE_MULAF32X16_H1, + ICLASS_AE_MULA32X16_H1, + ICLASS_AE_MULAF32X16_H2, + ICLASS_AE_MULA32X16_H2, + ICLASS_AE_MULAF32X16_H3, + ICLASS_AE_MULA32X16_H3, + ICLASS_AE_MULSF32X16_L0, + ICLASS_AE_MULS32X16_L0, + ICLASS_AE_MULSF32X16_L1, + ICLASS_AE_MULS32X16_L1, + ICLASS_AE_MULSF32X16_L2, + ICLASS_AE_MULS32X16_L2, + ICLASS_AE_MULSF32X16_L3, + ICLASS_AE_MULS32X16_L3, + ICLASS_AE_MULSF32X16_H0, + ICLASS_AE_MULS32X16_H0, + ICLASS_AE_MULSF32X16_H1, + ICLASS_AE_MULS32X16_H1, + ICLASS_AE_MULSF32X16_H2, + ICLASS_AE_MULS32X16_H2, + ICLASS_AE_MULSF32X16_H3, + ICLASS_AE_MULS32X16_H3, + ICLASS_AE_MULAAFD32X16_H3_L2, + ICLASS_AE_MULAAD32X16_H3_L2, + ICLASS_AE_MULAAFD32X16_H1_L0, + ICLASS_AE_MULAAD32X16_H1_L0, + ICLASS_AE_MULASFD32X16_H3_L2, + ICLASS_AE_MULASD32X16_H3_L2, + ICLASS_AE_MULASFD32X16_H1_L0, + ICLASS_AE_MULASD32X16_H1_L0, + ICLASS_AE_MULSAFD32X16_H3_L2, + ICLASS_AE_MULSAD32X16_H3_L2, + ICLASS_AE_MULSAFD32X16_H1_L0, + ICLASS_AE_MULSAD32X16_H1_L0, + ICLASS_AE_MULSSFD32X16_H3_L2, + ICLASS_AE_MULSSD32X16_H3_L2, + ICLASS_AE_MULSSFD32X16_H1_L0, + ICLASS_AE_MULSSD32X16_H1_L0, + ICLASS_AE_MULZAAFD32X16_H3_L2, + ICLASS_AE_MULZAAD32X16_H3_L2, + ICLASS_AE_MULZAAFD32X16_H1_L0, + ICLASS_AE_MULZAAD32X16_H1_L0, + ICLASS_AE_MULZASFD32X16_H3_L2, + ICLASS_AE_MULZASD32X16_H3_L2, + ICLASS_AE_MULZASFD32X16_H1_L0, + ICLASS_AE_MULZASD32X16_H1_L0, + ICLASS_AE_MULZSAFD32X16_H3_L2, + ICLASS_AE_MULZSAD32X16_H3_L2, + ICLASS_AE_MULZSAFD32X16_H1_L0, + ICLASS_AE_MULZSAD32X16_H1_L0, + ICLASS_AE_MULZSSFD32X16_H3_L2, + ICLASS_AE_MULZSSD32X16_H3_L2, + ICLASS_AE_MULZSSFD32X16_H1_L0, + ICLASS_AE_MULZSSD32X16_H1_L0, + ICLASS_AE_MULZAAFD32X16_H2_L3, + ICLASS_AE_MULZAAFD32X16_H0_L1, + ICLASS_AE_MULAAFD32X16_H2_L3, + ICLASS_AE_MULAAFD32X16_H0_L1, + ICLASS_AE_MULZAAD32X16_H2_L3, + ICLASS_AE_MULZAAD32X16_H0_L1, + ICLASS_AE_MULAAD32X16_H2_L3, + ICLASS_AE_MULAAD32X16_H0_L1, + ICLASS_AE_MULP32X16X2_H, + ICLASS_AE_MULFP32X16X2RS_H, + ICLASS_AE_MULFP32X16X2RAS_H, + ICLASS_AE_MULFP32X16X2S_H, + ICLASS_AE_MULP32X16X2_L, + ICLASS_AE_MULFP32X16X2RS_L, + ICLASS_AE_MULFP32X16X2RAS_L, + ICLASS_AE_MULFP32X16X2S_L, + ICLASS_AE_MULAP32X16X2_H, + ICLASS_AE_MULAFP32X16X2RS_H, + ICLASS_AE_MULAFP32X16X2RAS_H, + ICLASS_AE_MULAFP32X16X2S_H, + ICLASS_AE_MULAP32X16X2_L, + ICLASS_AE_MULAFP32X16X2RS_L, + ICLASS_AE_MULAFP32X16X2RAS_L, + ICLASS_AE_MULAFP32X16X2S_L, + ICLASS_AE_MULSP32X16X2_H, + ICLASS_AE_MULSFP32X16X2RS_H, + ICLASS_AE_MULSFP32X16X2RAS_H, + ICLASS_AE_MULSFP32X16X2S_H, + ICLASS_AE_MULSP32X16X2_L, + ICLASS_AE_MULSFP32X16X2RS_L, + ICLASS_AE_MULSFP32X16X2RAS_L, + ICLASS_AE_MULSFP32X16X2S_L, + ICLASS_AE_MULP32X2, + ICLASS_AE_MULFP32X2RS, + ICLASS_AE_MULFP32X2RAS, + ICLASS_AE_MULFP32X2TS, + ICLASS_AE_MULP32X2T, + ICLASS_AE_MULAP32X2, + ICLASS_AE_MULAFP32X2RS, + ICLASS_AE_MULAFP32X2RAS, + ICLASS_AE_MULAFP32X2TS, + ICLASS_AE_MULAP32X2T, + ICLASS_AE_MULSP32X2, + ICLASS_AE_MULSFP32X2RS, + ICLASS_AE_MULSFP32X2RAS, + ICLASS_AE_MULSFP32X2TS, + ICLASS_AE_MULSP32X2T, + ICLASS_AE_MULFP16X4S, + ICLASS_AE_MULFP16X4RAS, + ICLASS_AE_MULC32, + ICLASS_AE_MULFC24RA, + ICLASS_AE_MULFC32RAS, + ICLASS_AE_MULC32X16_L, + ICLASS_AE_MULFC32X16RAS_L, + ICLASS_AE_MULC32X16_H, + ICLASS_AE_MULFC32X16RAS_H, + ICLASS_AE_MULAC32, + ICLASS_AE_MULAFC24RA, + ICLASS_AE_MULAFC32RAS, + ICLASS_AE_MULAC32X16_L, + ICLASS_AE_MULAFC32X16RAS_L, + ICLASS_AE_MULAC32X16_H, + ICLASS_AE_MULAFC32X16RAS_H, + ICLASS_AE_MULF16X4SS, + ICLASS_AE_MULAF16X4SS, + ICLASS_AE_MULSF16X4SS, + ICLASS_AE_MUL16X4S, + ICLASS_AE_MULA16X4S, + ICLASS_AE_MULS16X4S, + ICLASS_AE_MUL16X4, + ICLASS_AE_MULA16X4, + ICLASS_AE_MULS16X4, + ICLASS_AE_MULFD32X2S_FIR_H, + ICLASS_AE_MULFD32X2RA_FIR_H, + ICLASS_AE_MULFD32X2S_FIR_L, + ICLASS_AE_MULFD32X2RA_FIR_L, + ICLASS_AE_MULFD32X16X2_FIR_HH, + ICLASS_AE_MULFD32X16X2_FIR_HL, + ICLASS_AE_MULFD32X16X2_FIR_LH, + ICLASS_AE_MULFD32X16X2_FIR_LL, + ICLASS_AE_MULAFD32X2S_FIR_H, + ICLASS_AE_MULAFD32X2RA_FIR_H, + ICLASS_AE_MULAFD32X2S_FIR_L, + ICLASS_AE_MULAFD32X2RA_FIR_L, + ICLASS_AE_MULAFD32X16X2_FIR_HH, + ICLASS_AE_MULAFD32X16X2_FIR_HL, + ICLASS_AE_MULAFD32X16X2_FIR_LH, + ICLASS_AE_MULAFD32X16X2_FIR_LL, + ICLASS_AE_MULC16S_H, + ICLASS_AE_MULC16S_L, + ICLASS_AE_MULAC16S_H, + ICLASS_AE_MULAC16S_L, + ICLASS_AE_MULFC16RAS, + ICLASS_AE_MULAFC16RAS, + ICLASS_AE_MUL16JS, + ICLASS_AE_ADDANDSUBRNG16RAS_S1, + ICLASS_AE_ADDANDSUBRNG16RAS_S2, + ICLASS_AE_CONJ16S, + ICLASS_AE_MULFQ16X2_FIR_3, + ICLASS_AE_MULFQ16X2_FIR_2, + ICLASS_AE_MULFQ16X2_FIR_1, + ICLASS_AE_MULFQ16X2_FIR_0, + ICLASS_AE_MULAFQ16X2_FIR_3, + ICLASS_AE_MULAFQ16X2_FIR_2, + ICLASS_AE_MULAFQ16X2_FIR_1, + ICLASS_AE_MULAFQ16X2_FIR_0, + ICLASS_AE_MULZAAAAFQ32X16, + ICLASS_AE_MULAAAAFQ32X16, + ICLASS_AE_MULZAAAAQ32X16, + ICLASS_AE_MULAAAAQ32X16, + ICLASS_AE_MUL16_00, + ICLASS_AE_MULA16_00, + ICLASS_AE_MULZAAAAQ16, + ICLASS_AE_MULAAAAQ16, + ICLASS_AE_DIV64D32_H, + ICLASS_AE_DIV64D32_L, + ICLASS_AE_SHA32, + ICLASS_AE_VLDL32T, + ICLASS_AE_VLDL16T, + ICLASS_AE_VLDL16C, + ICLASS_AE_VLDL16C_IP, + ICLASS_AE_VLDL16C_IC, + ICLASS_AE_VLDL16C_IC1, + ICLASS_AE_VLDSHT, + ICLASS_AE_LB, + ICLASS_AE_LBI, + ICLASS_AE_LBK, + ICLASS_AE_LBKI, + ICLASS_AE_LBS, + ICLASS_AE_LBSI, + ICLASS_AE_DB, + ICLASS_AE_DBI, + ICLASS_AE_DB_IC, + ICLASS_AE_DBI_IC, + ICLASS_AE_DB_IC1, + ICLASS_AE_DBI_IC1, + ICLASS_AE_DB_IP, + ICLASS_AE_DBI_IP, + ICLASS_AE_ARDECNORM16, + ICLASS_AE_LBKI_DBI_IC, + ICLASS_AE_LBKI_DBI_IP, + ICLASS_AE_LBKI_DBI, + ICLASS_AE_LBI_DBI_IC, + ICLASS_AE_LBI_DBI_IP, + ICLASS_AE_LBI_DBI, + ICLASS_AE_LBK_DB_IC, + ICLASS_AE_LBK_DB_IP, + ICLASS_AE_LBK_DB, + ICLASS_AE_LB_DB_IC, + ICLASS_AE_LB_DB_IP, + ICLASS_AE_LB_DB, + ICLASS_AE_VLEL32T, + ICLASS_AE_VLEL16T, + ICLASS_AE_SB, + ICLASS_AE_SBI, + ICLASS_AE_VLES16C, + ICLASS_AE_SBF, + ICLASS_AE_SB_IC, + ICLASS_AE_SBI_IC, + ICLASS_AE_VLES16C_IC, + ICLASS_AE_SBF_IC, + ICLASS_AE_SB_IC1, + ICLASS_AE_SBI_IC1, + ICLASS_AE_VLES16C_IC1, + ICLASS_AE_SBF_IC1, + ICLASS_AE_SB_IP, + ICLASS_AE_SBI_IP, + ICLASS_AE_VLES16C_IP, + ICLASS_AE_SBF_IP, + ICLASS_AE_SEXT32, + ICLASS_AE_MOVAE, + ICLASS_AE_MOVEA, + ICLASS_AE_MOVEEP, + ICLASS_AE_SEXT72, + ICLASS_AE_ADD72, + ICLASS_AE_SUB72, + ICLASS_AE_ADD72X64, + ICLASS_AE_SUB72X64, + ICLASS_AE_MUL32EP_HH, + ICLASS_AE_MULA32EP_HH, + ICLASS_AE_MULS32EP_HH, + ICLASS_AE_MULZAAD32EP_HH_LL, + ICLASS_AE_MULZSSD32EP_HH_LL, + ICLASS_AE_MULAAD32EP_HH_LL, + ICLASS_AE_MULSSD32EP_HH_LL, + ICLASS_AE_MULAAD32USEP_HL_LH, + ICLASS_AE_MULZAAD32USEP_HL_LH, + ICLASS_AE_MUL32USEP_LH, + ICLASS_AE_MULA32USEP_LH, + ICLASS_AE_MUL32USEP_LL, + ICLASS_AE_MULA32USEP_LL, + ICLASS_AE_SRAI72, + ICLASS_AE_SLAI72, + ICLASS_AE_SAT64S, + ICLASS_AE_L16SI_N, + ICLASS_AE_L16UI_N, + ICLASS_AE_S16I_N, + ICLASS_AE_LALIGN128_I, + ICLASS_AE_SALIGN128_I, + ICLASS_AE_LA128_PP, + ICLASS_AE_SA128POS_FP, + ICLASS_AE_LA8X4S_IP, + ICLASS_AE_LA8X4U_IP, + ICLASS_AE_LA8X8X2_IP, + ICLASS_AE_LA16X4X2_IP, + ICLASS_AE_LA32X2X2_IP, + ICLASS_AE_LA8X8X2_IC, + ICLASS_AE_LA16X4X2_IC, + ICLASS_AE_LA32X2X2_IC, + ICLASS_AE_LA8X8X2_IC1, + ICLASS_AE_LA16X4X2_IC1, + ICLASS_AE_LA32X2X2_IC1, + ICLASS_AE_LA8X8X2_IC2, + ICLASS_AE_LA16X4X2_IC2, + ICLASS_AE_LA32X2X2_IC2, + ICLASS_AE_SA8X8X2_IP, + ICLASS_AE_SA16X4X2_IP, + ICLASS_AE_SA32X2X2_IP, + ICLASS_AE_SA8X8X2_IC, + ICLASS_AE_SA16X4X2_IC, + ICLASS_AE_SA32X2X2_IC, + ICLASS_AE_SA8X8X2_IC1, + ICLASS_AE_SA16X4X2_IC1, + ICLASS_AE_SA32X2X2_IC1, + ICLASS_AE_SA8X8X2_IC2, + ICLASS_AE_SA16X4X2_IC2, + ICLASS_AE_SA32X2X2_IC2, + ICLASS_AE_ABS8, + ICLASS_AE_ABS8S, + ICLASS_AE_NEG8S, + ICLASS_AE_ADD8, + ICLASS_AE_SUB8, + ICLASS_AE_MAX8, + ICLASS_AE_MIN8, + ICLASS_AE_ADD8S, + ICLASS_AE_SUB8S, + ICLASS_AE_LE8, + ICLASS_AE_LT8, + ICLASS_AE_EQ8, + ICLASS_AE_SATU16X4, + ICLASS_AE_SAT32X2, + ICLASS_AE_SATU32X2, + ICLASS_AE_SAT8X8X16, + ICLASS_AE_SATU8X8X16, + ICLASS_AE_SAT8X4X32_L, + ICLASS_AE_SATU8X4X32_L, + ICLASS_AE_ROUND8X8F16SSYM, + ICLASS_AE_ROUND8X8F16SASYM, + ICLASS_AE_ROUND8X4F32SSYM_L, + ICLASS_AE_ROUND8X4F32SASYM_L, + ICLASS_AE_MOVDA8, + ICLASS_AE_MOVAD8, + ICLASS_AE_MOVDX2, + ICLASS_AE_ADDANDSUB32J, + ICLASS_AE_ADDW8, + ICLASS_AE_ADDW16, + ICLASS_AE_ADDW32, + ICLASS_AE_SUBW8, + ICLASS_AE_SUBW16, + ICLASS_AE_SUBW32, + ICLASS_AE_ACCW8, + ICLASS_AE_ACCW16, + ICLASS_AE_ACCW32, + ICLASS_AE_ADDW8U, + ICLASS_AE_SUBW8U, + ICLASS_AE_ACCW8U, + ICLASS_AE_MULFP32X2S_HH_LL, + ICLASS_AE_MULAFP32X2S_HH_LL, + ICLASS_AE_MULSFP32X2S_HH_LL, + ICLASS_AE_MULFP32X2S_HL_LH, + ICLASS_AE_MULAFP32X2S_HL_LH, + ICLASS_AE_MULSFP32X2S_HL_LH, + ICLASS_AE_MULZAAF2D32S_HH_LL, + ICLASS_AE_MULZASF2D32S_HH_LL, + ICLASS_AE_MULZSAF2D32S_HH_LL, + ICLASS_AE_MULZSSF2D32S_HH_LL, + ICLASS_AE_MULAAF2D32S_HH_LL, + ICLASS_AE_MULASF2D32S_HH_LL, + ICLASS_AE_MULSAF2D32S_HH_LL, + ICLASS_AE_MULSSF2D32S_HH_LL, + ICLASS_AE_MULZAAF2D32S_HL_LH, + ICLASS_AE_MULZASF2D32S_HL_LH, + ICLASS_AE_MULZSAF2D32S_HL_LH, + ICLASS_AE_MULZSSF2D32S_HL_LH, + ICLASS_AE_MULAAF2D32S_HL_LH, + ICLASS_AE_MULASF2D32S_HL_LH, + ICLASS_AE_MULSAF2D32S_HL_LH, + ICLASS_AE_MULSSF2D32S_HL_LH, + ICLASS_AE_MUL32S_HH, + ICLASS_AE_MULA32S_HH, + ICLASS_AE_MULS32S_HH, + ICLASS_AE_MUL32S_LL, + ICLASS_AE_MULA32S_LL, + ICLASS_AE_MULS32S_LL, + ICLASS_AE_MUL32S_HL, + ICLASS_AE_MULA32S_HL, + ICLASS_AE_MULS32S_HL, + ICLASS_AE_MUL32S_LH, + ICLASS_AE_MULA32S_LH, + ICLASS_AE_MULS32S_LH, + ICLASS_AE_MUL32X2S_HH_LL, + ICLASS_AE_MULA32X2S_HH_LL, + ICLASS_AE_MULS32X2S_HH_LL, + ICLASS_AE_MUL32X2S_HL_LH, + ICLASS_AE_MULA32X2S_HL_LH, + ICLASS_AE_MULS32X2S_HL_LH, + ICLASS_AE_MULZAAD32S_HH_LL, + ICLASS_AE_MULZASD32S_HH_LL, + ICLASS_AE_MULZSAD32S_HH_LL, + ICLASS_AE_MULZSSD32S_HH_LL, + ICLASS_AE_MULAAD32S_HH_LL, + ICLASS_AE_MULASD32S_HH_LL, + ICLASS_AE_MULSAD32S_HH_LL, + ICLASS_AE_MULSSD32S_HH_LL, + ICLASS_AE_MULZAAD32S_HL_LH, + ICLASS_AE_MULZASD32S_HL_LH, + ICLASS_AE_MULZSAD32S_HL_LH, + ICLASS_AE_MULZSSD32S_HL_LH, + ICLASS_AE_MULAAD32S_HL_LH, + ICLASS_AE_MULASD32S_HL_LH, + ICLASS_AE_MULSAD32S_HL_LH, + ICLASS_AE_MULSSD32S_HL_LH, + ICLASS_AE_MULF32X2RA_HH_LL, + ICLASS_AE_MULAF32X2RA_HH_LL, + ICLASS_AE_MULSF32X2RA_HH_LL, + ICLASS_AE_MULF32X2RA_HL_LH, + ICLASS_AE_MULAF32X2RA_HL_LH, + ICLASS_AE_MULSF32X2RA_HL_LH, + ICLASS_AE_MULZAAF2D32RA_HH_LL, + ICLASS_AE_MULZASF2D32RA_HH_LL, + ICLASS_AE_MULZSAF2D32RA_HH_LL, + ICLASS_AE_MULZSSF2D32RA_HH_LL, + ICLASS_AE_MULAAF2D32RA_HH_LL, + ICLASS_AE_MULASF2D32RA_HH_LL, + ICLASS_AE_MULSAF2D32RA_HH_LL, + ICLASS_AE_MULSSF2D32RA_HH_LL, + ICLASS_AE_MULZAAF2D32RA_HL_LH, + ICLASS_AE_MULZASF2D32RA_HL_LH, + ICLASS_AE_MULZSAF2D32RA_HL_LH, + ICLASS_AE_MULZSSF2D32RA_HL_LH, + ICLASS_AE_MULAAF2D32RA_HL_LH, + ICLASS_AE_MULASF2D32RA_HL_LH, + ICLASS_AE_MULSAF2D32RA_HL_LH, + ICLASS_AE_MULSSF2D32RA_HL_LH, + ICLASS_AE_MULF32X2R_HH_LL, + ICLASS_AE_MULAF32X2R_HH_LL, + ICLASS_AE_MULSF32X2R_HH_LL, + ICLASS_AE_MULF32X2R_HL_LH, + ICLASS_AE_MULAF32X2R_HL_LH, + ICLASS_AE_MULSF32X2R_HL_LH, + ICLASS_AE_MULFC32W, + ICLASS_AE_MULAFC32W, + ICLASS_AE_MULFCJ32W, + ICLASS_AE_MULAFCJ32W, + ICLASS_AE_MULFCJ32RAS, + ICLASS_AE_MULAFCJ32RAS, + ICLASS_AE_MULF2P32X4RS, + ICLASS_AE_MULAF2P32X4RS, + ICLASS_AE_MULSF2P32X4RS, + ICLASS_AE_MULF2P32X4RAS, + ICLASS_AE_MULAF2P32X4RAS, + ICLASS_AE_MULSF2P32X4RAS, + ICLASS_AE_MULP32X2S, + ICLASS_AE_MUL2P32X4S, + ICLASS_AE_MUL2P32X4, + ICLASS_AE_MULA2P32X4, + ICLASS_AE_MULS2P32X4, + ICLASS_AE_MUL2P32X4T, + ICLASS_AE_MULA2P32X4T, + ICLASS_AE_MULS2P32X4T, + ICLASS_AE_MULZAA32X2_HH_LL, + ICLASS_AE_MULZSS32X2_HH_LL, + ICLASS_AE_MULAA32X2_HH_LL, + ICLASS_AE_MULSS32X2_HH_LL, + ICLASS_AE_MULCJ32, + ICLASS_AE_MULACJ32, + ICLASS_AE_MULADDF32RS, + ICLASS_AE_MULADDF32RAS, + ICLASS_AE_MULSUBF32RS, + ICLASS_AE_MULSUBF32RAS, + ICLASS_AE_MULFC32RA, + ICLASS_AE_MULAFC32RA, + ICLASS_AE_MULCJ32W, + ICLASS_AE_MULACJ32W, + ICLASS_AE_MULC32W, + ICLASS_AE_MULAC32W, + ICLASS_AE_MULF2D32X2WS, + ICLASS_AE_MULZAAAA2Q16, + ICLASS_AE_MULAAAA2Q16, + ICLASS_AE_MULP16S_H, + ICLASS_AE_MULAP16S_H, + ICLASS_AE_MULSP16S_H, + ICLASS_AE_MULP16S_L, + ICLASS_AE_MULAP16S_L, + ICLASS_AE_MULSP16S_L, + ICLASS_AE_MULC16W_H, + ICLASS_AE_MULAC16W_H, + ICLASS_AE_MULC16W_L, + ICLASS_AE_MULAC16W_L, + ICLASS_AE_MUL2C16S, + ICLASS_AE_MULA2C16S, + ICLASS_AE_MULFC16S, + ICLASS_AE_MULAFC16S, + ICLASS_AE_MULFCJ16S, + ICLASS_AE_MULAFCJ16S, + ICLASS_AE_MULFCJ16RAS, + ICLASS_AE_MULAFCJ16RAS, + ICLASS_AE_MULC16S, + ICLASS_AE_MULAC16S, + ICLASS_AE_MULFP16X4RS, + ICLASS_AE_MULFD16X16X4RAS, + ICLASS_AE_MULP16X16X4S, + ICLASS_AE_MULAP16X16X4S, + ICLASS_AE_MULSP16X16X4S, + ICLASS_AE_MULZAA2D16SS_HH_LL, + ICLASS_AE_MULZAA2D16SS_HL_LH, + ICLASS_AE_MULZSS2D16SS_HH_LL, + ICLASS_AE_MULZSS2D16SS_HL_LH, + ICLASS_AE_MULAA2D16SS_HH_LL, + ICLASS_AE_MULAA2D16SS_HL_LH, + ICLASS_AE_MULSS2D16SS_HH_LL, + ICLASS_AE_MULSS2D16SS_HL_LH, + ICLASS_AE_MULZAAFD16SS_HH_LL, + ICLASS_AE_MULZAAFD16SS_HL_LH, + ICLASS_AE_MULZSSFD16SS_HH_LL, + ICLASS_AE_MULZSSFD16SS_HL_LH, + ICLASS_AE_MULAAFD16SS_HH_LL, + ICLASS_AE_MULAAFD16SS_HL_LH, + ICLASS_AE_MULSSFD16SS_HH_LL, + ICLASS_AE_MULSSFD16SS_HL_LH, + ICLASS_AE_MULFD16X16X4WS, + ICLASS_AE_MULZAAAA2Q16X8, + ICLASS_AE_MULAAAA2Q16X8, + ICLASS_AE_MULZAAAA2Q8, + ICLASS_AE_MULAAAA2Q8, + ICLASS_AE_MULC32X16W_H, + ICLASS_AE_MULAC32X16W_H, + ICLASS_AE_MULC32X16W_L, + ICLASS_AE_MULAC32X16W_L, + ICLASS_AE_MULPC32X16X2, + ICLASS_AE_MULAPC32X16X2, + ICLASS_AE_MULFP32X16_H, + ICLASS_AE_MULAFP32X16_H, + ICLASS_AE_MULSFP32X16_H, + ICLASS_AE_MULFP32X16_L, + ICLASS_AE_MULAFP32X16_L, + ICLASS_AE_MULSFP32X16_L, + ICLASS_AE_MULFC32X16W_H, + ICLASS_AE_MULAFC32X16W_H, + ICLASS_AE_MULFC32X16W_L, + ICLASS_AE_MULAFC32X16W_L, + ICLASS_AE_MULFCJ32X16W_H, + ICLASS_AE_MULAFCJ32X16W_H, + ICLASS_AE_MULFCJ32X16W_L, + ICLASS_AE_MULAFCJ32X16W_L, + ICLASS_AE_MULF2P32X16X4RAS, + ICLASS_AE_MULAF2P32X16X4RAS, + ICLASS_AE_MULSF2P32X16X4RAS, + ICLASS_AE_MULF2P32X16X4RS, + ICLASS_AE_MULAF2P32X16X4RS, + ICLASS_AE_MULSF2P32X16X4RS, + ICLASS_AE_MULF2P32X16X4S, + ICLASS_AE_MULAF2P32X16X4S, + ICLASS_AE_MULSF2P32X16X4S, + ICLASS_AE_MULFPC32X16X2RAS, + ICLASS_AE_MULAFPC32X16X2RAS, + ICLASS_AE_MULFPCJ32X16X2RAS, + ICLASS_AE_MULAFPCJ32X16X2RAS, + ICLASS_AE_MULZAAAA2Q32X16, + ICLASS_AE_MULAAAA2Q32X16, + ICLASS_AE_MUL2Q32X16_FIR_H, + ICLASS_AE_MULA2Q32X16_FIR_H, + ICLASS_AE_MUL2Q32X16_FIR_L, + ICLASS_AE_MULA2Q32X16_FIR_L, + ICLASS_AE_SRAI8, + ICLASS_AE_SRAI8R, + ICLASS_AE_SRLI8, + ICLASS_AE_SLAI8, + ICLASS_AE_SLAI8S, + ICLASS_AE_SLAA8, + ICLASS_AE_SRLA8, + ICLASS_AE_SLAA8S, + ICLASS_AE_SRAA8RS, + ICLASS_AE_SRAA8S, + ICLASS_AE_SRLI16, + ICLASS_AE_SLAI16, + ICLASS_AE_SLAA16, + ICLASS_AE_SRLA16, + ICLASS_AE_SRAI16SYM, + ICLASS_AE_SRAA16SYMS, + ICLASS_AE_SRAI32SYM, + ICLASS_AE_SRAA32SYMS, + ICLASS_AE_SRAV16RS, + ICLASS_AE_SRAV32RS, + ICLASS_AE_CVTI32X4F8_H, + ICLASS_AE_CVTI32X4F8_L, + ICLASS_AE_CVTI32X4F8S_H, + ICLASS_AE_CVTI32X4F8S_L, + ICLASS_AE_CVTA32X4F8_H, + ICLASS_AE_CVTA32X4F8_L, + ICLASS_AE_CVTA32X4F8S_H, + ICLASS_AE_CVTA32X4F8S_L, + ICLASS_AE_CVTI32X4F8U_H, + ICLASS_AE_CVTI32X4F8U_L, + ICLASS_AE_CVTI32X4F8US_H, + ICLASS_AE_CVTI32X4F8US_L, + ICLASS_AE_CVTA32X4F8U_H, + ICLASS_AE_CVTA32X4F8U_L, + ICLASS_AE_CVTA32X4F8US_H, + ICLASS_AE_CVTA32X4F8US_L, + ICLASS_AE_CVTI32X4F16, + ICLASS_AE_CVTI32X4F16S, + ICLASS_AE_CVTA32X4F16, + ICLASS_AE_CVTA32X4F16S, + ICLASS_AE_CVTI32X4F16U, + ICLASS_AE_CVTI32X4F16US, + ICLASS_AE_CVTA32X4F16U, + ICLASS_AE_CVTA32X4F16US, + ICLASS_AE_CVTI16X4X2F8, + ICLASS_AE_CVTI16X4X2F8S, + ICLASS_AE_CVTA16X4X2F8, + ICLASS_AE_CVTA16X4X2F8S, + ICLASS_AE_CVTI16X4X2F8U, + ICLASS_AE_CVTI16X4X2F8US, + ICLASS_AE_CVTA16X4X2F8U, + ICLASS_AE_CVTA16X4X2F8US, + ICLASS_AE_SEL8X8, + ICLASS_AE_SHFL8X8, + ICLASS_AE_SEL16X4, + ICLASS_AE_SHFL16X4, + ICLASS_AE_DSEL8X8, + ICLASS_AE_DSEL16X4, + ICLASS_AE_SEL8X8I, + ICLASS_AE_RMAX8X8, + ICLASS_AE_RMIN8X8, + ICLASS_AE_RMAX16X4, + ICLASS_AE_RMIN16X4, + ICLASS_AE_SORT16X4, + ICLASS_AE_RADD8X8_H, + ICLASS_AE_RADDA8X8_H, + ICLASS_AE_RADD8X8_L, + ICLASS_AE_RADDA8X8_L, + ICLASS_AE_RADD16X4, + ICLASS_AE_RADDA16X4, + ICLASS_AE_BMAX8X8_H, + ICLASS_AE_BMAX8X8_L, + ICLASS_AE_BMIN8X8_H, + ICLASS_AE_BMIN8X8_L, + ICLASS_AE_BMAX16X4, + ICLASS_AE_BMIN16X4, + ICLASS_AE_BMAX32X2, + ICLASS_AE_BMIN32X2, + ICLASS_AE_ADDINV16S, + ICLASS_AE_ADDINV32S, + ICLASS_AE_MOVT16X8, + ICLASS_AE_MOVT8X16_H, + ICLASS_AE_MOVT8X16_L, + ICLASS_AE_MOVBD1X4, + ICLASS_AE_MOVBD1X2, + ICLASS_AE_MOVNEG32S_T, + ICLASS_AE_MOVDEXT, + ICLASS_AE_MOVADEXT_H, + ICLASS_AE_MOVADEXT_L, + ICLASS_AE_NSA16X4, + ICLASS_AE_NSAZ32X4, + ICLASS_AE_NSA32X4, + ICLASS_AE_TRUNCI16X4F32S, + ICLASS_AE_TRUNCI16X4F64S, + ICLASS_AE_TRUNCA16X4F32S, + ICLASS_AE_TRUNCA16X4F64S, + ICLASS_AE_ADDC32, + ICLASS_AE_SUBC32, + ICLASS_AE_ADDC32U, + ICLASS_AE_SUBC32U, + ICLASS_AE_EXPADD16_H, + ICLASS_AE_EXPSUB16_H, + ICLASS_AE_EXPADD16_L, + ICLASS_AE_EXPSUB16_L, + ICLASS_AE_ADDCEXP32_H, + ICLASS_AE_ADDCEXP32_L, + ICLASS_AE_CALCRNG16, + ICLASS_AE_CALCRNG32, + ICLASS_AE_RNG32X4, + ICLASS_AE_LAV8X8X2_XP, + ICLASS_AE_LAV16X4X2_XP, + ICLASS_AE_SAV8X8X2_XP, + ICLASS_AE_SAV16X4X2_XP, + ICLASS_AE_MOVZBVCDR, + ICLASS_AE_MOVDRZBVC, + ICLASS_AE_LAVUNSQZ8X8_XP, + ICLASS_AE_LAVUNSQZ16X4_XP, + ICLASS_AE_MUL8Q8X8, + ICLASS_AE_MULA8Q8X8, + ICLASS_AE_MUL8Q4X16, + ICLASS_AE_MULA8Q4X16, + ICLASS_AE_MUL8Q8X16, + ICLASS_AE_MULA8Q8X16, + ICLASS_AE_MUL8QW8X16, + ICLASS_AE_MULA8QW8X16, + ICLASS_AE_MUL4O8X8, + ICLASS_AE_MULA4O8X8, + ICLASS_AE_MUL4O4X16, + ICLASS_AE_MULA4O4X16, + ICLASS_AE_MUL4O8X16, + ICLASS_AE_MULA4O8X16, + ICLASS_AE_MUL4QW8X16, + ICLASS_AE_MULA4QW8X16, + ICLASS_AE_MUL8Q8X8CNV_L, + ICLASS_AE_MUL8Q8X8CNV_H, + ICLASS_AE_MULA8Q8X8CNV_L, + ICLASS_AE_MULA8Q8X8CNV_H, + ICLASS_AE_MUL8Q8X16CNV, + ICLASS_AE_MULA8Q8X16CNV, + ICLASS_AE_MUL2X4Q8X8CNV_H, + ICLASS_AE_MULA2X4Q8X8CNV_H, + ICLASS_AE_MUL2X4Q8X8CNV_L, + ICLASS_AE_MULA2X4Q8X8CNV_L, + ICLASS_AE_MUL2X4Q8X16CNV, + ICLASS_AE_MULA2X4Q8X16CNV, + ICLASS_AE_MULQQ8X16CNV, + ICLASS_AE_MULAQQ8X16CNV, + ICLASS_AE_MUL4O8X8CNV_H, + ICLASS_AE_MULA4O8X8CNV_H, + ICLASS_AE_MUL4O8X8CNV_L, + ICLASS_AE_MULA4O8X8CNV_L, + ICLASS_AE_MUL4O8X16CNV_H, + ICLASS_AE_MULA4O8X16CNV_H, + ICLASS_AE_MUL4O8X16CNV_L, + ICLASS_AE_MULA4O8X16CNV_L, + ICLASS_AE_MUL8Q4X16CNV_H, + ICLASS_AE_MULA8Q4X16CNV_H, + ICLASS_AE_MUL8Q4X16CNV_L, + ICLASS_AE_MULA8Q4X16CNV_L, + ICLASS_AE_MUL2X4Q4X16CNV_H, + ICLASS_AE_MULA2X4Q4X16CNV_H, + ICLASS_AE_MUL2X4Q4X16CNV_L, + ICLASS_AE_MULA2X4Q4X16CNV_L, + ICLASS_AE_MULQQ4X16CNV_H, + ICLASS_AE_MULAQQ4X16CNV_H, + ICLASS_AE_MULQQ4X16CNV_L, + ICLASS_AE_MULAQQ4X16CNV_L, + ICLASS_AE_MUL4O4X16CNV_HH, + ICLASS_AE_MUL4O4X16CNV_HL, + ICLASS_AE_MUL4O4X16CNV_LH, + ICLASS_AE_MUL4O4X16CNV_LL, + ICLASS_AE_MULA4O4X16CNV_HH, + ICLASS_AE_MULA4O4X16CNV_HL, + ICLASS_AE_MULA4O4X16CNV_LH, + ICLASS_AE_MULA4O4X16CNV_LL, + ICLASS_AE_MULUU8Q8X8, + ICLASS_AE_MULAUU8Q8X8, + ICLASS_AE_MULUU4O8X8, + ICLASS_AE_MULAUU4O8X8, + ICLASS_AE_MULUU8Q8X8CNV_L, + ICLASS_AE_MULAUU8Q8X8CNV_L, + ICLASS_AE_MULUU8Q8X8CNV_H, + ICLASS_AE_MULAUU8Q8X8CNV_H, + ICLASS_AE_MULUU2X4Q8X8CNV_H, + ICLASS_AE_MULAUU2X4Q8X8CNV_H, + ICLASS_AE_MULUU2X4Q8X8CNV_L, + ICLASS_AE_MULAUU2X4Q8X8CNV_L, + ICLASS_AE_MULUU4O8X8CNV_H, + ICLASS_AE_MULAUU4O8X8CNV_H, + ICLASS_AE_MULUU4O8X8CNV_L, + ICLASS_AE_MULAUU4O8X8CNV_L, + ICLASS_AE_MULUS8Q8X8, + ICLASS_AE_MULAUS8Q8X8, + ICLASS_AE_MULUS8Q4X16, + ICLASS_AE_MULAUS8Q4X16, + ICLASS_AE_MULUS8Q8X16, + ICLASS_AE_MULAUS8Q8X16, + ICLASS_AE_MULUS8QW8X16, + ICLASS_AE_MULAUS8QW8X16, + ICLASS_AE_MULUS4O8X8, + ICLASS_AE_MULAUS4O8X8, + ICLASS_AE_MULUS4O4X16, + ICLASS_AE_MULAUS4O4X16, + ICLASS_AE_MULUS4O8X16, + ICLASS_AE_MULAUS4O8X16, + ICLASS_AE_MULUS4QW8X16, + ICLASS_AE_MULAUS4QW8X16, + ICLASS_AE_MULUS8Q8X8CNV_L, + ICLASS_AE_MULAUS8Q8X8CNV_L, + ICLASS_AE_MULUS8Q8X8CNV_H, + ICLASS_AE_MULAUS8Q8X8CNV_H, + ICLASS_AE_MULUS8Q8X16CNV, + ICLASS_AE_MULAUS8Q8X16CNV, + ICLASS_AE_MULUS2X4Q8X8CNV_H, + ICLASS_AE_MULAUS2X4Q8X8CNV_H, + ICLASS_AE_MULUS2X4Q8X8CNV_L, + ICLASS_AE_MULAUS2X4Q8X8CNV_L, + ICLASS_AE_MULUS2X4Q8X16CNV, + ICLASS_AE_MULAUS2X4Q8X16CNV, + ICLASS_AE_MULUSQQ8X16CNV, + ICLASS_AE_MULAUSQQ8X16CNV, + ICLASS_AE_MULUS4O8X8CNV_H, + ICLASS_AE_MULAUS4O8X8CNV_H, + ICLASS_AE_MULUS4O8X8CNV_L, + ICLASS_AE_MULAUS4O8X8CNV_L, + ICLASS_AE_MULUS4O8X16CNV_H, + ICLASS_AE_MULAUS4O8X16CNV_H, + ICLASS_AE_MULUS4O8X16CNV_L, + ICLASS_AE_MULAUS4O8X16CNV_L, + ICLASS_AE_MULUS8Q4X16CNV_H, + ICLASS_AE_MULAUS8Q4X16CNV_H, + ICLASS_AE_MULUS8Q4X16CNV_L, + ICLASS_AE_MULAUS8Q4X16CNV_L, + ICLASS_AE_MULUS2X4Q4X16CNV_H, + ICLASS_AE_MULAUS2X4Q4X16CNV_H, + ICLASS_AE_MULUS2X4Q4X16CNV_L, + ICLASS_AE_MULAUS2X4Q4X16CNV_L, + ICLASS_AE_MULUSQQ4X16CNV_H, + ICLASS_AE_MULAUSQQ4X16CNV_H, + ICLASS_AE_MULUSQQ4X16CNV_L, + ICLASS_AE_MULAUSQQ4X16CNV_L, + ICLASS_AE_MULUS4O4X16CNV_HH, + ICLASS_AE_MULUS4O4X16CNV_HL, + ICLASS_AE_MULUS4O4X16CNV_LH, + ICLASS_AE_MULUS4O4X16CNV_LL, + ICLASS_AE_MULAUS4O4X16CNV_HH, + ICLASS_AE_MULAUS4O4X16CNV_HL, + ICLASS_AE_MULAUS4O4X16CNV_LH, + ICLASS_AE_MULAUS4O4X16CNV_LL, + ICLASS_AE_MULSU8Q8X8, + ICLASS_AE_MULASU8Q8X8, + ICLASS_AE_MULSU4O8X8, + ICLASS_AE_MULASU4O8X8, + ICLASS_AE_MULSU8Q8X8CNV_L, + ICLASS_AE_MULASU8Q8X8CNV_L, + ICLASS_AE_MULSU8Q8X8CNV_H, + ICLASS_AE_MULASU8Q8X8CNV_H, + ICLASS_AE_MULSU2X4Q8X8CNV_H, + ICLASS_AE_MULASU2X4Q8X8CNV_H, + ICLASS_AE_MULSU2X4Q8X8CNV_L, + ICLASS_AE_MULASU2X4Q8X8CNV_L, + ICLASS_AE_MULSU4O8X8CNV_H, + ICLASS_AE_MULASU4O8X8CNV_H, + ICLASS_AE_MULSU4O8X8CNV_L, + ICLASS_AE_MULASU4O8X8CNV_L, + ICLASS_AE_MULUUZB8Q8X8, + ICLASS_AE_MULAUUZB8Q8X8, + ICLASS_AE_MULUUZB4O8X8, + ICLASS_AE_MULAUUZB4O8X8, + ICLASS_AE_MULUUZB8Q8X8CNV_L, + ICLASS_AE_MULAUUZB8Q8X8CNV_L, + ICLASS_AE_MULUUZB8Q8X8CNV_H, + ICLASS_AE_MULAUUZB8Q8X8CNV_H, + ICLASS_AE_MULUUZB2X4Q8X8CNV_H, + ICLASS_AE_MULAUUZB2X4Q8X8CNV_H, + ICLASS_AE_MULUUZB2X4Q8X8CNV_L, + ICLASS_AE_MULAUUZB2X4Q8X8CNV_L, + ICLASS_AE_MULUUZB4O8X8CNV_H, + ICLASS_AE_MULAUUZB4O8X8CNV_H, + ICLASS_AE_MULUUZB4O8X8CNV_L, + ICLASS_AE_MULAUUZB4O8X8CNV_L, + ICLASS_CVTSF16_L, + ICLASS_CVTSF16_H, + ICLASS_CVTF16S_L, + ICLASS_CVTF16S_H, + ICLASS_AE_MOVFCRFSRV, + ICLASS_AE_MOVVFCRFSR, + ICLASS_MOVT_S, + ICLASS_MOVF_S, + ICLASS_MOVEQZ_S, + ICLASS_MOVNEZ_S, + ICLASS_MOVGEZ_S, + ICLASS_MOVLTZ_S, + ICLASS_RFR, + ICLASS_WFR, + ICLASS_MUL_S, + ICLASS_MADD_S, + ICLASS_MSUB_S, + ICLASS_MSUBN_S, + ICLASS_MADDN_S, + ICLASS_ADD_S, + ICLASS_SUB_S, + ICLASS_OLE_S, + ICLASS_OLT_S, + ICLASS_OEQ_S, + ICLASS_UN_S, + ICLASS_ULE_S, + ICLASS_ULT_S, + ICLASS_UEQ_S, + ICLASS_NEXP01_S, + ICLASS_MKSADJ_S, + ICLASS_MKDADJ_S, + ICLASS_DIV0_S, + ICLASS_SQRT0_S, + ICLASS_RECIP0_S, + ICLASS_RSQRT0_S, + ICLASS_DIVN_S, + ICLASS_ADDEXP_S, + ICLASS_ADDEXPM_S, + ICLASS_MIN_S, + ICLASS_MAX_S, + ICLASS_MULMUX_S, + ICLASS_MADDMUX_S, + ICLASS_TRUNC_S, + ICLASS_UTRUNC_S, + ICLASS_TRUNC_SX2, + ICLASS_UTRUNC_SX2, + ICLASS_FICEIL_S, + ICLASS_FIFLOOR_S, + ICLASS_FIRINT_S, + ICLASS_FIROUND_S, + ICLASS_FITRUNC_S, + ICLASS_FLOAT_S, + ICLASS_UFLOAT_S, + ICLASS_FLOAT_SX2, + ICLASS_UFLOAT_SX2, + ICLASS_ABS_S, + ICLASS_NEG_S, + ICLASS_CONJC_S, + ICLASS_MULJC_S, + ICLASS_CONST_S, + ICLASS_CLSFY_S, + ICLASS_MINNUM_S, + ICLASS_MAXNUM_S, + ICLASS_ADDANDSUB_S, + ICLASS_ADDANDSUBJC_S, + ICLASS_ADD_HL_LH_S, + ICLASS_MADDA_S, + ICLASS_FREXP_S, + ICLASS_FLOATEXP_S, + ICLASS_MINNUMABS_S, + ICLASS_MAXNUMABS_S, + ICLASS_MULQ_S, + ICLASS_MADDQ_S, + ICLASS_MSUBQ_S, + ICLASS_MULMUXQ_S, + ICLASS_MADDMUXQ_S, + ICLASS_BMAXNUM_S, + ICLASS_BMINNUM_S, + ICLASS_BMAXNUMABS_S, + ICLASS_BMINNUMABS_S, + ICLASS_ABS_SX2X2, + ICLASS_NEG_SX2X2, + ICLASS_CONJC_SX2X2, + ICLASS_MULJC_SX2X2, + ICLASS_CONST_SX2X2, + ICLASS_ADD_SX2X2, + ICLASS_SUB_SX2X2, + ICLASS_MUL_SX2X2, + ICLASS_MADD_SX2X2, + ICLASS_MSUB_SX2X2, + ICLASS_MULMUX_SX2X2, + ICLASS_MADDMUX_SX2X2, + ICLASS_ABS_H, + ICLASS_ADDEXP_H, + ICLASS_ADDEXPM_H, + ICLASS_CLSFY_H, + ICLASS_CONJC_H, + ICLASS_CONST_H, + ICLASS_MIN_H, + ICLASS_MAX_H, + ICLASS_MINNUM_H, + ICLASS_MAXNUM_H, + ICLASS_MULJC_H, + ICLASS_NEG_H, + ICLASS_OEQ_H, + ICLASS_OLE_H, + ICLASS_OLT_H, + ICLASS_UEQ_H, + ICLASS_ULE_H, + ICLASS_ULT_H, + ICLASS_UN_H, + ICLASS_DIV0_H, + ICLASS_FICEIL_H, + ICLASS_FIFLOOR_H, + ICLASS_FIRINT_H, + ICLASS_FIROUND_H, + ICLASS_FITRUNC_H, + ICLASS_MKDADJ_H, + ICLASS_MKSADJ_H, + ICLASS_NEXP0_H, + ICLASS_NEXP01_H, + ICLASS_RECIP0_H, + ICLASS_RSQRT0_H, + ICLASS_SQRT0_H, + ICLASS_FLOAT16_H, + ICLASS_UFLOAT16_H, + ICLASS_TRUNC16_H, + ICLASS_UTRUNC16_H, + ICLASS_FLOAT16_HX4, + ICLASS_UFLOAT16_HX4, + ICLASS_TRUNC16_HX4, + ICLASS_UTRUNC16_HX4, + ICLASS_ADD_H, + ICLASS_SUB_H, + ICLASS_MUL_H, + ICLASS_MADD_H, + ICLASS_MSUB_H, + ICLASS_MADDN_H, + ICLASS_MSUBN_H, + ICLASS_DIVN_H, + ICLASS_RMINNUM_H, + ICLASS_RMAXNUM_H, + ICLASS_ABS_HX4X2, + ICLASS_NEG_HX4X2, + ICLASS_CONJC_HX4X2, + ICLASS_CONST_HX4X2, + ICLASS_MULJC_HX4X2, + ICLASS_ADD_HX4X2, + ICLASS_SUB_HX4X2, + ICLASS_MUL_HX4X2, + ICLASS_MADD_HX4X2, + ICLASS_MSUB_HX4X2, + ICLASS_MULQ_H, + ICLASS_MADDQ_H, + ICLASS_MULCNVH_HX4X2, + ICLASS_MULACNVH_HX4X2, + ICLASS_MULCNVL_HX4X2, + ICLASS_MULACNVL_HX4X2 +}; + + +/* Opcode encodings. */ + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408000; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf01d; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3400; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3500; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34800; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134800; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614800; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34900; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134900; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614900; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf06d; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03d; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00d; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e70; +} + +static void +Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e700; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_addi_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e0000; +} + +static void +Opcode_addi_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_addi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6e0000; + slotbuf[1] = 0; +} + +static void +Opcode_addi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01000; + slotbuf[1] = 0; +} + +static void +Opcode_addi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103e0000; + slotbuf[1] = 0; +} + +static void +Opcode_addi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_addi_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000; +} + +static void +Opcode_addi_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_addi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10360000; +} + +static void +Opcode_addi_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2642000; +} + +static void +Opcode_addi_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308000; +} + +static void +Opcode_addi_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2360000; +} + +static void +Opcode_addi_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340000; +} + +static void +Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb900000; +} + +static void +Opcode_addi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340000; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002; +} + +static void +Opcode_addmi_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f0000; +} + +static void +Opcode_addmi_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1250000; +} + +static void +Opcode_addmi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6f0000; + slotbuf[1] = 0; +} + +static void +Opcode_addmi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01200; + slotbuf[1] = 0; +} + +static void +Opcode_addmi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103e2000; + slotbuf[1] = 0; +} + +static void +Opcode_addmi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_addmi_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000; +} + +static void +Opcode_addmi_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_addmi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10370000; +} + +static void +Opcode_addmi_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2643000; +} + +static void +Opcode_addmi_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130c000; +} + +static void +Opcode_addmi_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2370000; +} + +static void +Opcode_addmi_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1350000; +} + +static void +Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb901000; +} + +static void +Opcode_addmi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1350000; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_add_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc48000; +} + +static void +Opcode_add_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144c000; +} + +static void +Opcode_add_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ba000; + slotbuf[1] = 0; +} + +static void +Opcode_add_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e12000; + slotbuf[1] = 0; +} + +static void +Opcode_add_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10724000; + slotbuf[1] = 0; +} + +static void +Opcode_add_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4000; +} + +static void +Opcode_add_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c4000; +} + +static void +Opcode_add_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c000; +} + +static void +Opcode_add_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10614000; +} + +static void +Opcode_add_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a09000; +} + +static void +Opcode_add_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1588000; +} + +static void +Opcode_add_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2750000; +} + +static void +Opcode_add_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154e000; +} + +static void +Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a79004; +} + +static void +Opcode_add_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154c000; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addx2_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc49000; +} + +static void +Opcode_addx2_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144d000; +} + +static void +Opcode_addx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74bb000; + slotbuf[1] = 0; +} + +static void +Opcode_addx2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1a000; + slotbuf[1] = 0; +} + +static void +Opcode_addx2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10725000; + slotbuf[1] = 0; +} + +static void +Opcode_addx2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a5000; +} + +static void +Opcode_addx2_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c5000; +} + +static void +Opcode_addx2_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29d000; +} + +static void +Opcode_addx2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10615000; +} + +static void +Opcode_addx2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0d000; +} + +static void +Opcode_addx2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c8000; +} + +static void +Opcode_addx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2751000; +} + +static void +Opcode_addx2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f000; +} + +static void +Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b79004; +} + +static void +Opcode_addx2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154d000; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_addx4_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc88000; +} + +static void +Opcode_addx4_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148c000; +} + +static void +Opcode_addx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74bc000; + slotbuf[1] = 0; +} + +static void +Opcode_addx4_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e42000; + slotbuf[1] = 0; +} + +static void +Opcode_addx4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10726000; + slotbuf[1] = 0; +} + +static void +Opcode_addx4_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6000; +} + +static void +Opcode_addx4_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c6000; +} + +static void +Opcode_addx4_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29e000; +} + +static void +Opcode_addx4_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10616000; +} + +static void +Opcode_addx4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a11000; +} + +static void +Opcode_addx4_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1589000; +} + +static void +Opcode_addx4_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2752000; +} + +static void +Opcode_addx4_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158e000; +} + +static void +Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9928000; +} + +static void +Opcode_addx4_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158c000; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_addx8_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc89000; +} + +static void +Opcode_addx8_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148d000; +} + +static void +Opcode_addx8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74bd000; + slotbuf[1] = 0; +} + +static void +Opcode_addx8_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e4a000; + slotbuf[1] = 0; +} + +static void +Opcode_addx8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10727000; + slotbuf[1] = 0; +} + +static void +Opcode_addx8_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a7000; +} + +static void +Opcode_addx8_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c7000; +} + +static void +Opcode_addx8_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29f000; +} + +static void +Opcode_addx8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10617000; +} + +static void +Opcode_addx8_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a15000; +} + +static void +Opcode_addx8_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c9000; +} + +static void +Opcode_addx8_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2753000; +} + +static void +Opcode_addx8_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158f000; +} + +static void +Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9968000; +} + +static void +Opcode_addx8_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158d000; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_sub_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4d000; +} + +static void +Opcode_sub_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1451000; +} + +static void +Opcode_sub_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74eb000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eba000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072a000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6000; +} + +static void +Opcode_sub_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d5000; +} + +static void +Opcode_sub_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ad000; +} + +static void +Opcode_sub_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064b000; +} + +static void +Opcode_sub_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a4d000; +} + +static void +Opcode_sub_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154d000; +} + +static void +Opcode_sub_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2761000; +} + +static void +Opcode_sub_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1553000; +} + +static void +Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a7900c; +} + +static void +Opcode_sub_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1551000; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_subx2_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8c000; +} + +static void +Opcode_subx2_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1490000; +} + +static void +Opcode_subx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ec000; + slotbuf[1] = 0; +} + +static void +Opcode_subx2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec2000; + slotbuf[1] = 0; +} + +static void +Opcode_subx2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072b000; + slotbuf[1] = 0; +} + +static void +Opcode_subx2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7000; +} + +static void +Opcode_subx2_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d6000; +} + +static void +Opcode_subx2_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ae000; +} + +static void +Opcode_subx2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064d000; +} + +static void +Opcode_subx2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a51000; +} + +static void +Opcode_subx2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158d000; +} + +static void +Opcode_subx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2762000; +} + +static void +Opcode_subx2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1592000; +} + +static void +Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b7100c; +} + +static void +Opcode_subx2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1590000; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_subx4_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8d000; +} + +static void +Opcode_subx4_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1491000; +} + +static void +Opcode_subx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ed000; + slotbuf[1] = 0; +} + +static void +Opcode_subx4_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eca000; + slotbuf[1] = 0; +} + +static void +Opcode_subx4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072c000; + slotbuf[1] = 0; +} + +static void +Opcode_subx4_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8000; +} + +static void +Opcode_subx4_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d7000; +} + +static void +Opcode_subx4_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2af000; +} + +static void +Opcode_subx4_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064f000; +} + +static void +Opcode_subx4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a55000; +} + +static void +Opcode_subx4_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cd000; +} + +static void +Opcode_subx4_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2763000; +} + +static void +Opcode_subx4_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1593000; +} + +static void +Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b7900c; +} + +static void +Opcode_subx4_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1591000; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_subx8_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xccc000; +} + +static void +Opcode_subx8_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d0000; +} + +static void +Opcode_subx8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ee000; + slotbuf[1] = 0; +} + +static void +Opcode_subx8_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ed2000; + slotbuf[1] = 0; +} + +static void +Opcode_subx8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072d000; + slotbuf[1] = 0; +} + +static void +Opcode_subx8_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b9000; +} + +static void +Opcode_subx8_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d8000; +} + +static void +Opcode_subx8_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0000; +} + +static void +Opcode_subx8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10651000; +} + +static void +Opcode_subx8_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a59000; +} + +static void +Opcode_subx8_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150e000; +} + +static void +Opcode_subx8_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2764000; +} + +static void +Opcode_subx8_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d2000; +} + +static void +Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9920008; +} + +static void +Opcode_subx8_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d0000; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_and_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc8000; +} + +static void +Opcode_and_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14cc000; +} + +static void +Opcode_and_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74be000; + slotbuf[1] = 0; +} + +static void +Opcode_and_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e52000; + slotbuf[1] = 0; +} + +static void +Opcode_and_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054b000; + slotbuf[1] = 0; +} + +static void +Opcode_and_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9000; +} + +static void +Opcode_and_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c8000; +} + +static void +Opcode_and_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0000; +} + +static void +Opcode_and_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10638000; +} + +static void +Opcode_and_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a19000; +} + +static void +Opcode_and_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150a000; +} + +static void +Opcode_and_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2754000; +} + +static void +Opcode_and_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ce000; +} + +static void +Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9920004; +} + +static void +Opcode_and_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cc000; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_or_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xccb000; +} + +static void +Opcode_or_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14cf000; +} + +static void +Opcode_or_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e7000; + slotbuf[1] = 0; +} + +static void +Opcode_or_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e9a000; + slotbuf[1] = 0; +} + +static void +Opcode_or_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1075d000; + slotbuf[1] = 0; +} + +static void +Opcode_or_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2000; +} + +static void +Opcode_or_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d1000; +} + +static void +Opcode_or_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a9000; +} + +static void +Opcode_or_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10643000; +} + +static void +Opcode_or_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_or_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a3d000; +} + +static void +Opcode_or_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154c000; +} + +static void +Opcode_or_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275d000; +} + +static void +Opcode_or_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d1000; +} + +static void +Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a79008; +} + +static void +Opcode_or_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cf000; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_xor_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xccd000; +} + +static void +Opcode_xor_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d1000; +} + +static void +Opcode_xor_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ef000; + slotbuf[1] = 0; +} + +static void +Opcode_xor_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eda000; + slotbuf[1] = 0; +} + +static void +Opcode_xor_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072e000; + slotbuf[1] = 0; +} + +static void +Opcode_xor_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba000; +} + +static void +Opcode_xor_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d9000; +} + +static void +Opcode_xor_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b1000; +} + +static void +Opcode_xor_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10653000; +} + +static void +Opcode_xor_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa01000; +} + +static void +Opcode_xor_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a5d000; +} + +static void +Opcode_xor_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154e000; +} + +static void +Opcode_xor_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2765000; +} + +static void +Opcode_xor_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d3000; +} + +static void +Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9960008; +} + +static void +Opcode_xor_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d1000; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6007; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe007; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4007; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5007; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd007; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1007; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa007; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb007; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2007; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3007; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc007; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9007; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_call0_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940000; +} + +static void +Opcode_call0_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d620000; + slotbuf[1] = 0; +} + +static void +Opcode_call0_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340000; + slotbuf[1] = 0; +} + +static void +Opcode_call0_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_call0_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0000; +} + +static void +Opcode_call0_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c0000; +} + +static void +Opcode_call0_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22c0000; +} + +static void +Opcode_call0_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7300000; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_callx0_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21003; +} + +static void +Opcode_callx0_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520205; + slotbuf[1] = 0; +} + +static void +Opcode_callx0_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10587bc0; + slotbuf[1] = 0; +} + +static void +Opcode_callx0_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6402; +} + +static void +Opcode_callx0_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d230; +} + +static void +Opcode_callx0_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d001; +} + +static void +Opcode_callx0_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781003; +} + +static void +Opcode_callx0_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e10e0; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_extui_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0000; +} + +static void +Opcode_extui_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_extui_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6a0000; + slotbuf[1] = 0; +} + +static void +Opcode_extui_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00000; + slotbuf[1] = 0; +} + +static void +Opcode_extui_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103c0000; + slotbuf[1] = 0; +} + +static void +Opcode_extui_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_extui_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_extui_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_extui_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340000; +} + +static void +Opcode_extui_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2640000; +} + +static void +Opcode_extui_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_extui_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2340000; +} + +static void +Opcode_extui_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_extui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa900000; +} + +static void +Opcode_extui_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_j_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_j_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d600000; + slotbuf[1] = 0; +} + +static void +Opcode_j_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300000; + slotbuf[1] = 0; +} + +static void +Opcode_j_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_j_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280000; +} + +static void +Opcode_j_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2580000; +} + +static void +Opcode_j_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2280000; +} + +static void +Opcode_j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7200000; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; +} + +static void +Opcode_jx_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21203; +} + +static void +Opcode_jx_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520a05; + slotbuf[1] = 0; +} + +static void +Opcode_jx_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef00; + slotbuf[1] = 0; +} + +static void +Opcode_jx_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6404; +} + +static void +Opcode_jx_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d430; +} + +static void +Opcode_jx_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d201; +} + +static void +Opcode_jx_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781203; +} + +static void +Opcode_jx_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e12e0; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1002; +} + +static void +Opcode_l16ui_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa40000; +} + +static void +Opcode_l16ui_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_l16ui_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7c0000; + slotbuf[1] = 0; +} + +static void +Opcode_l16ui_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c02200; + slotbuf[1] = 0; +} + +static void +Opcode_l16ui_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10402000; + slotbuf[1] = 0; +} + +static void +Opcode_l16ui_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_l16ui_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x350000; +} + +static void +Opcode_l16ui_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250000; +} + +static void +Opcode_l16ui_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103c0000; +} + +static void +Opcode_l16ui_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c0000; +} + +static void +Opcode_l16ui_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1314000; +} + +static void +Opcode_l16ui_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2390000; +} + +static void +Opcode_l16ui_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c0000; +} + +static void +Opcode_l16ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb01000; +} + +static void +Opcode_l16ui_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c0000; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9002; +} + +static void +Opcode_l16si_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_l16si_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_l16si_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d780000; + slotbuf[1] = 0; +} + +static void +Opcode_l16si_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c02000; + slotbuf[1] = 0; +} + +static void +Opcode_l16si_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10400000; + slotbuf[1] = 0; +} + +static void +Opcode_l16si_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_l16si_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_l16si_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_l16si_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103b0000; +} + +static void +Opcode_l16si_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2680000; +} + +static void +Opcode_l16si_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1310000; +} + +static void +Opcode_l16si_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2380000; +} + +static void +Opcode_l16si_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380000; +} + +static void +Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb00000; +} + +static void +Opcode_l16si_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380000; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2002; +} + +static void +Opcode_l32i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa80000; +} + +static void +Opcode_l32i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1290000; +} + +static void +Opcode_l32i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d790000; + slotbuf[1] = 0; +} + +static void +Opcode_l32i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c03000; + slotbuf[1] = 0; +} + +static void +Opcode_l32i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10420000; + slotbuf[1] = 0; +} + +static void +Opcode_l32i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_l32i_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360000; +} + +static void +Opcode_l32i_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260000; +} + +static void +Opcode_l32i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103d0000; +} + +static void +Opcode_l32i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2681000; +} + +static void +Opcode_l32i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318000; +} + +static void +Opcode_l32i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23a0000; +} + +static void +Opcode_l32i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1390000; +} + +static void +Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7320000; +} + +static void +Opcode_l32i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1390000; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_l32r_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_l32r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7200000; + slotbuf[1] = 0; +} + +static void +Opcode_l32r_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0; +} + +static void +Opcode_l32r_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_l32r_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; +} + +static void +Opcode_l32r_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_l32r_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_l32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000000; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_l8ui_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac0000; +} + +static void +Opcode_l8ui_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12d0000; +} + +static void +Opcode_l8ui_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7d0000; + slotbuf[1] = 0; +} + +static void +Opcode_l8ui_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c03200; + slotbuf[1] = 0; +} + +static void +Opcode_l8ui_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10422000; + slotbuf[1] = 0; +} + +static void +Opcode_l8ui_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_l8ui_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370000; +} + +static void +Opcode_l8ui_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270000; +} + +static void +Opcode_l8ui_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103e0000; +} + +static void +Opcode_l8ui_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c1000; +} + +static void +Opcode_l8ui_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131c000; +} + +static void +Opcode_l8ui_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23b0000; +} + +static void +Opcode_l8ui_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d0000; +} + +static void +Opcode_l8ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7321000; +} + +static void +Opcode_l8ui_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d0000; +} + +static void +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8076; +} + +static void +Opcode_loop_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_loop_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520000; + slotbuf[1] = 0; +} + +static void +Opcode_loop_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10582000; + slotbuf[1] = 0; +} + +static void +Opcode_loop_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0000; +} + +static void +Opcode_loop_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690000; +} + +static void +Opcode_loop_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac1000; +} + +static void +Opcode_loop_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2780000; +} + +static void +Opcode_loop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b20000; +} + +static void +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa076; +} + +static void +Opcode_loopgtz_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20001; +} + +static void +Opcode_loopgtz_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520001; + slotbuf[1] = 0; +} + +static void +Opcode_loopgtz_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10582040; + slotbuf[1] = 0; +} + +static void +Opcode_loopgtz_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0001; +} + +static void +Opcode_loopgtz_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690010; +} + +static void +Opcode_loopgtz_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac1001; +} + +static void +Opcode_loopgtz_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2780001; +} + +static void +Opcode_loopgtz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b20040; +} + +static void +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9076; +} + +static void +Opcode_loopnez_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20002; +} + +static void +Opcode_loopnez_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520002; + slotbuf[1] = 0; +} + +static void +Opcode_loopnez_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10582080; + slotbuf[1] = 0; +} + +static void +Opcode_loopnez_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0002; +} + +static void +Opcode_loopnez_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690020; +} + +static void +Opcode_loopnez_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac1002; +} + +static void +Opcode_loopnez_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2780002; +} + +static void +Opcode_loopnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b20080; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa002; +} + +static void +Opcode_movi_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad0000; +} + +static void +Opcode_movi_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1220000; +} + +static void +Opcode_movi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7f0000; + slotbuf[1] = 0; +} + +static void +Opcode_movi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04000; + slotbuf[1] = 0; +} + +static void +Opcode_movi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480000; + slotbuf[1] = 0; +} + +static void +Opcode_movi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_movi_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0000; +} + +static void +Opcode_movi_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_movi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10450000; +} + +static void +Opcode_movi_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c3000; +} + +static void +Opcode_movi_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1320000; +} + +static void +Opcode_movi_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23f0000; +} + +static void +Opcode_movi_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1320000; +} + +static void +Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9820000; +} + +static void +Opcode_movi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1320000; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830000; +} + +static void +Opcode_moveqz_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4b000; +} + +static void +Opcode_moveqz_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144f000; +} + +static void +Opcode_moveqz_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e3000; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e7a000; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10755000; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae000; +} + +static void +Opcode_moveqz_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3cd000; +} + +static void +Opcode_moveqz_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a5000; +} + +static void +Opcode_moveqz_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063d000; +} + +static void +Opcode_moveqz_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a2d000; +} + +static void +Opcode_moveqz_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154b000; +} + +static void +Opcode_moveqz_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2759000; +} + +static void +Opcode_moveqz_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1551000; +} + +static void +Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9978008; +} + +static void +Opcode_moveqz_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f000; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30000; +} + +static void +Opcode_movgez_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8a000; +} + +static void +Opcode_movgez_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148e000; +} + +static void +Opcode_movgez_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e4000; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e82000; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10757000; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1af000; +} + +static void +Opcode_movgez_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ce000; +} + +static void +Opcode_movgez_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a6000; +} + +static void +Opcode_movgez_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063e000; +} + +static void +Opcode_movgez_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a31000; +} + +static void +Opcode_movgez_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158b000; +} + +static void +Opcode_movgez_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275a000; +} + +static void +Opcode_movgez_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1590000; +} + +static void +Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x997000c; +} + +static void +Opcode_movgez_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158e000; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_movltz_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8b000; +} + +static void +Opcode_movltz_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148f000; +} + +static void +Opcode_movltz_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e5000; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e8a000; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10759000; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_movltz_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3cf000; +} + +static void +Opcode_movltz_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a7000; +} + +static void +Opcode_movltz_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063f000; +} + +static void +Opcode_movltz_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a35000; +} + +static void +Opcode_movltz_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cb000; +} + +static void +Opcode_movltz_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275b000; +} + +static void +Opcode_movltz_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1591000; +} + +static void +Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x997800c; +} + +static void +Opcode_movltz_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158f000; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_movnez_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcca000; +} + +static void +Opcode_movnez_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14ce000; +} + +static void +Opcode_movnez_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e6000; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e92000; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1075b000; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1000; +} + +static void +Opcode_movnez_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d0000; +} + +static void +Opcode_movnez_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8000; +} + +static void +Opcode_movnez_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10641000; +} + +static void +Opcode_movnez_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a39000; +} + +static void +Opcode_movnez_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150c000; +} + +static void +Opcode_movnez_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275c000; +} + +static void +Opcode_movnez_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d0000; +} + +static void +Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a71008; +} + +static void +Opcode_movnez_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ce000; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600100; +} + +static void +Opcode_abs_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc12020; +} + +static void +Opcode_abs_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1453000; +} + +static void +Opcode_abs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191f6030; + slotbuf[1] = 0; +} + +static void +Opcode_abs_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e14000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a00e; + slotbuf[1] = 0; +} + +static void +Opcode_abs_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8000; +} + +static void +Opcode_abs_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e5000; +} + +static void +Opcode_abs_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6000; +} + +static void +Opcode_abs_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a200b; +} + +static void +Opcode_abs_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a89000; +} + +static void +Opcode_abs_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f000; +} + +static void +Opcode_abs_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c6010; +} + +static void +Opcode_abs_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1555000; +} + +static void +Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a3000; +} + +static void +Opcode_abs_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1521000; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_neg_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc12030; +} + +static void +Opcode_neg_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1453010; +} + +static void +Opcode_neg_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191f7030; + slotbuf[1] = 0; +} + +static void +Opcode_neg_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e14010; + slotbuf[1] = 0; +} + +static void +Opcode_neg_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071b00f; + slotbuf[1] = 0; +} + +static void +Opcode_neg_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8020; +} + +static void +Opcode_neg_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e5020; +} + +static void +Opcode_neg_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6010; +} + +static void +Opcode_neg_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a300b; +} + +static void +Opcode_neg_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a89010; +} + +static void +Opcode_neg_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f010; +} + +static void +Opcode_neg_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c7010; +} + +static void +Opcode_neg_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1555010; +} + +static void +Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a3002; +} + +static void +Opcode_neg_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1521020; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f0; +} + +static void +Opcode_nop_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21903; +} + +static void +Opcode_nop_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1496109; +} + +static void +Opcode_nop_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000065; + slotbuf[1] = 0x6; +} + +static void +Opcode_nop_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82164012; + slotbuf[1] = 0x5; +} + +static void +Opcode_nop_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b48fb5; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c702; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63f8c00; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef74; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9603; +} + +static void +Opcode_nop_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e640b; +} + +static void +Opcode_nop_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7306; +} + +static void +Opcode_nop_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x568001; +} + +static void +Opcode_nop_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40b84a0; +} + +static void +Opcode_nop_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x510040; +} + +static void +Opcode_nop_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069db31; +} + +static void +Opcode_nop_Slot_ae5_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_nop_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700212; +} + +static void +Opcode_nop_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133b800; +} + +static void +Opcode_nop_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08940; +} + +static void +Opcode_nop_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130060; +} + +static void +Opcode_nop_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000021; + slotbuf[1] = 0x2; +} + +static void +Opcode_nop_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x692180; +} + +static void +Opcode_nop_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x692180; +} + +static void +Opcode_nop_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00560; + slotbuf[1] = 0xe; +} + +static void +Opcode_nop_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000801; + slotbuf[1] = 0xe; +} + +static void +Opcode_nop_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d901; +} + +static void +Opcode_nop_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d260f; +} + +static void +Opcode_nop_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200001; + slotbuf[1] = 0x229860; +} + +static void +Opcode_nop_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781903; +} + +static void +Opcode_nop_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159690b; +} + +static void +Opcode_nop_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c10041; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d35801d; +} + +static void +Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab20055; +} + +static void +Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14b610c; +} + +static void +Opcode_nop_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00427; +} + +static void +Opcode_nop_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80426862; + slotbuf[1] = 0xe; +} + +static void +Opcode_l32ex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf14000; +} + +static void +Opcode_s32ex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf15000; +} + +static void +Opcode_getex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40a000; +} + +static void +Opcode_clrex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3120; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_ret_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21303; +} + +static void +Opcode_ret_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520e05; + slotbuf[1] = 0; +} + +static void +Opcode_ret_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef10; + slotbuf[1] = 0; +} + +static void +Opcode_ret_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6405; +} + +static void +Opcode_ret_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d530; +} + +static void +Opcode_ret_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d301; +} + +static void +Opcode_ret_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781303; +} + +static void +Opcode_ret_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e13e0; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5002; +} + +static void +Opcode_s16i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_s16i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7a0000; + slotbuf[1] = 0; +} + +static void +Opcode_s16i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10440000; + slotbuf[1] = 0; +} + +static void +Opcode_s16i_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_s16i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103f0000; +} + +static void +Opcode_s16i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2682000; +} + +static void +Opcode_s16i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23c0000; +} + +static void +Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7330000; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002; +} + +static void +Opcode_s32i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa50000; +} + +static void +Opcode_s32i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7e0000; + slotbuf[1] = 0; +} + +static void +Opcode_s32i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10442000; + slotbuf[1] = 0; +} + +static void +Opcode_s32i_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x390000; +} + +static void +Opcode_s32i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10400000; +} + +static void +Opcode_s32i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c2000; +} + +static void +Opcode_s32i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23d0000; +} + +static void +Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7331000; +} + +static void +Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590000; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_s8i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa90000; +} + +static void +Opcode_s8i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7b0000; + slotbuf[1] = 0; +} + +static void +Opcode_s8i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10460000; + slotbuf[1] = 0; +} + +static void +Opcode_s8i_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0000; +} + +static void +Opcode_s8i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10410000; +} + +static void +Opcode_s8i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2683000; +} + +static void +Opcode_s8i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23e0000; +} + +static void +Opcode_s8i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa980000; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403000; +} + +static void +Opcode_ssa8b_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21503; +} + +static void +Opcode_ssa8b_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145420a; +} + +static void +Opcode_ssa8b_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7521605; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8b_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00c03; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8b_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef30; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8b_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9103; +} + +static void +Opcode_ssa8b_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6407; +} + +static void +Opcode_ssa8b_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7302; +} + +static void +Opcode_ssa8b_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d730; +} + +static void +Opcode_ssa8b_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d501; +} + +static void +Opcode_ssa8b_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d220f; +} + +static void +Opcode_ssa8b_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781503; +} + +static void +Opcode_ssa8b_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556a0b; +} + +static void +Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e15e0; +} + +static void +Opcode_ssa8b_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d7204; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402000; +} + +static void +Opcode_ssa8l_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21603; +} + +static void +Opcode_ssa8l_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145430a; +} + +static void +Opcode_ssa8l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7521a05; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f08c03; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef40; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8l_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9503; +} + +static void +Opcode_ssa8l_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6408; +} + +static void +Opcode_ssa8l_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7303; +} + +static void +Opcode_ssa8l_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d830; +} + +static void +Opcode_ssa8l_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d601; +} + +static void +Opcode_ssa8l_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d230f; +} + +static void +Opcode_ssa8l_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781603; +} + +static void +Opcode_ssa8l_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556b0b; +} + +static void +Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e16e0; +} + +static void +Opcode_ssa8l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d7304; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401000; +} + +static void +Opcode_ssl_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21703; +} + +static void +Opcode_ssl_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416109; +} + +static void +Opcode_ssl_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7521e05; + slotbuf[1] = 0; +} + +static void +Opcode_ssl_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c402; + slotbuf[1] = 0; +} + +static void +Opcode_ssl_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef50; + slotbuf[1] = 0; +} + +static void +Opcode_ssl_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9203; +} + +static void +Opcode_ssl_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6409; +} + +static void +Opcode_ssl_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7304; +} + +static void +Opcode_ssl_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d930; +} + +static void +Opcode_ssl_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d701; +} + +static void +Opcode_ssl_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d240f; +} + +static void +Opcode_ssl_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781703; +} + +static void +Opcode_ssl_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151690b; +} + +static void +Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e17e0; +} + +static void +Opcode_ssl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143610c; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ssr_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21803; +} + +static void +Opcode_ssr_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1456109; +} + +static void +Opcode_ssr_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a4af00; + slotbuf[1] = 0; +} + +static void +Opcode_ssr_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c502; + slotbuf[1] = 0; +} + +static void +Opcode_ssr_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef60; + slotbuf[1] = 0; +} + +static void +Opcode_ssr_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9303; +} + +static void +Opcode_ssr_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e640a; +} + +static void +Opcode_ssr_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7305; +} + +static void +Opcode_ssr_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069da30; +} + +static void +Opcode_ssr_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d801; +} + +static void +Opcode_ssr_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d250f; +} + +static void +Opcode_ssr_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781803; +} + +static void +Opcode_ssr_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x155690b; +} + +static void +Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e18e0; +} + +static void +Opcode_ssr_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x147610c; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404000; +} + +static void +Opcode_ssai_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc92520; +} + +static void +Opcode_ssai_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145400a; +} + +static void +Opcode_ssai_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19034310; + slotbuf[1] = 0; +} + +static void +Opcode_ssai_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00c01; + slotbuf[1] = 0; +} + +static void +Opcode_ssai_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afa0a; + slotbuf[1] = 0; +} + +static void +Opcode_ssai_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9003; +} + +static void +Opcode_ssai_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6400; +} + +static void +Opcode_ssai_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7300; +} + +static void +Opcode_ssai_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687701; +} + +static void +Opcode_ssai_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a88640; +} + +static void +Opcode_ssai_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d200f; +} + +static void +Opcode_ssai_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b520; +} + +static void +Opcode_ssai_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516a0b; +} + +static void +Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa60005; +} + +static void +Opcode_ssai_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d7004; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_sll_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20003; +} + +static void +Opcode_sll_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x141400a; +} + +static void +Opcode_sll_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x752c003; + slotbuf[1] = 0; +} + +static void +Opcode_sll_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0c002; + slotbuf[1] = 0; +} + +static void +Opcode_sll_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105860c0; + slotbuf[1] = 0; +} + +static void +Opcode_sll_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9000; +} + +static void +Opcode_sll_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0003; +} + +static void +Opcode_sll_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b8000; +} + +static void +Opcode_sll_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069c030; +} + +static void +Opcode_sll_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d000; +} + +static void +Opcode_sll_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159200f; +} + +static void +Opcode_sll_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2780003; +} + +static void +Opcode_sll_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151600a; +} + +static void +Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e10e0; +} + +static void +Opcode_sll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1596004; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_src_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4c000; +} + +static void +Opcode_src_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1450000; +} + +static void +Opcode_src_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ea000; + slotbuf[1] = 0; +} + +static void +Opcode_src_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eb2000; + slotbuf[1] = 0; +} + +static void +Opcode_src_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10729000; + slotbuf[1] = 0; +} + +static void +Opcode_src_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b5000; +} + +static void +Opcode_src_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d4000; +} + +static void +Opcode_src_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac000; +} + +static void +Opcode_src_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10649000; +} + +static void +Opcode_src_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a49000; +} + +static void +Opcode_src_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150d000; +} + +static void +Opcode_src_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2760000; +} + +static void +Opcode_src_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1552000; +} + +static void +Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a7100c; +} + +static void +Opcode_src_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1550000; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10000; +} + +static void +Opcode_sra_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc52020; +} + +static void +Opcode_sra_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1453020; +} + +static void +Opcode_sra_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191fc030; + slotbuf[1] = 0; +} + +static void +Opcode_sra_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e14020; + slotbuf[1] = 0; +} + +static void +Opcode_sra_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af000; + slotbuf[1] = 0; +} + +static void +Opcode_sra_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8030; +} + +static void +Opcode_sra_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e5010; +} + +static void +Opcode_sra_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6020; +} + +static void +Opcode_sra_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2007; +} + +static void +Opcode_sra_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a89020; +} + +static void +Opcode_sra_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f020; +} + +static void +Opcode_sra_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b000; +} + +static void +Opcode_sra_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1555020; +} + +static void +Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a3003; +} + +static void +Opcode_sra_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1521030; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_srl_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc52030; +} + +static void +Opcode_srl_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1453030; +} + +static void +Opcode_srl_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191fe030; + slotbuf[1] = 0; +} + +static void +Opcode_srl_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e14030; + slotbuf[1] = 0; +} + +static void +Opcode_srl_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af001; + slotbuf[1] = 0; +} + +static void +Opcode_srl_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8040; +} + +static void +Opcode_srl_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e5030; +} + +static void +Opcode_srl_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6030; +} + +static void +Opcode_srl_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a200f; +} + +static void +Opcode_srl_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a89030; +} + +static void +Opcode_srl_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f030; +} + +static void +Opcode_srl_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b010; +} + +static void +Opcode_srl_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1555030; +} + +static void +Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a3000; +} + +static void +Opcode_srl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1521040; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_slli_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc6000; +} + +static void +Opcode_slli_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14ca000; +} + +static void +Opcode_slli_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74b6000; + slotbuf[1] = 0; +} + +static void +Opcode_slli_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e22000; + slotbuf[1] = 0; +} + +static void +Opcode_slli_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10542000; + slotbuf[1] = 0; +} + +static void +Opcode_slli_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_slli_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_slli_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290000; +} + +static void +Opcode_slli_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10610000; +} + +static void +Opcode_slli_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a01000; +} + +static void +Opcode_slli_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1508000; +} + +static void +Opcode_slli_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x274c000; +} + +static void +Opcode_slli_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cc000; +} + +static void +Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9920000; +} + +static void +Opcode_slli_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ca000; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_srai_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc08000; +} + +static void +Opcode_srai_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140c000; +} + +static void +Opcode_srai_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74b8000; + slotbuf[1] = 0; +} + +static void +Opcode_srai_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e02000; + slotbuf[1] = 0; +} + +static void +Opcode_srai_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10546000; + slotbuf[1] = 0; +} + +static void +Opcode_srai_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2000; +} + +static void +Opcode_srai_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c2000; +} + +static void +Opcode_srai_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x292000; +} + +static void +Opcode_srai_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10612000; +} + +static void +Opcode_srai_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000e0; +} + +static void +Opcode_srai_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1548000; +} + +static void +Opcode_srai_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x274e000; +} + +static void +Opcode_srai_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150e000; +} + +static void +Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9970004; +} + +static void +Opcode_srai_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150c000; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_srli_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8e000; +} + +static void +Opcode_srli_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1452000; +} + +static void +Opcode_srli_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f4000; + slotbuf[1] = 0; +} + +static void +Opcode_srli_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ef2000; + slotbuf[1] = 0; +} + +static void +Opcode_srli_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056a000; + slotbuf[1] = 0; +} + +static void +Opcode_srli_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bd000; +} + +static void +Opcode_srli_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3de000; +} + +static void +Opcode_srli_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b4000; +} + +static void +Opcode_srli_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065d000; +} + +static void +Opcode_srli_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a71000; +} + +static void +Opcode_srli_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150f000; +} + +static void +Opcode_srli_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276a000; +} + +static void +Opcode_srli_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1554000; +} + +static void +Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x992800c; +} + +static void +Opcode_srli_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1552000; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d0; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2030; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2020; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2010; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30100; +} + +static void +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610100; +} + +static void +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200; +} + +static void +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610200; +} + +static void +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30300; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610300; +} + +static void +Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36100; +} + +static void +Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136100; +} + +static void +Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616100; +} + +static void +Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b000; +} + +static void +Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e600; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e600; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e600; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b100; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b100; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b100; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d100; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d100; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d100; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b200; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b200; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b200; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d200; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d200; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d200; +} + +static void +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b300; +} + +static void +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b300; +} + +static void +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b300; +} + +static void +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d300; +} + +static void +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d300; +} + +static void +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d300; +} + +static void +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b400; +} + +static void +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b400; +} + +static void +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b400; +} + +static void +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d400; +} + +static void +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d400; +} + +static void +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d400; +} + +static void +Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b500; +} + +static void +Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b500; +} + +static void +Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b500; +} + +static void +Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d500; +} + +static void +Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d500; +} + +static void +Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d500; +} + +static void +Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b600; +} + +static void +Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b600; +} + +static void +Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b600; +} + +static void +Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d600; +} + +static void +Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d600; +} + +static void +Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d600; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c200; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c200; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c200; +} + +static void +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c300; +} + +static void +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c300; +} + +static void +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c300; +} + +static void +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400; +} + +static void +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c400; +} + +static void +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c400; +} + +static void +Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c500; +} + +static void +Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c500; +} + +static void +Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c500; +} + +static void +Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c600; +} + +static void +Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c600; +} + +static void +Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c600; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ee00; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee00; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ee00; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c000; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e800; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e800; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e800; +} + +static void +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f400; +} + +static void +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f400; +} + +static void +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f400; +} + +static void +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f500; +} + +static void +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f500; +} + +static void +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f500; +} + +static void +Opcode_rsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f600; +} + +static void +Opcode_wsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f600; +} + +static void +Opcode_xsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f600; +} + +static void +Opcode_rsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f700; +} + +static void +Opcode_wsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f700; +} + +static void +Opcode_xsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f700; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3eb00; +} + +static void +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e700; +} + +static void +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e700; +} + +static void +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e700; +} + +static void +Opcode_rsr_mpucfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35c00; +} + +static void +Opcode_wsr_mpucfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135c00; +} + +static void +Opcode_salt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720000; +} + +static void +Opcode_salt_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c000; +} + +static void +Opcode_salt_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1410000; +} + +static void +Opcode_salt_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e8000; + slotbuf[1] = 0; +} + +static void +Opcode_salt_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea2000; + slotbuf[1] = 0; +} + +static void +Opcode_salt_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1075f000; + slotbuf[1] = 0; +} + +static void +Opcode_salt_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b3000; +} + +static void +Opcode_salt_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d2000; +} + +static void +Opcode_salt_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2aa000; +} + +static void +Opcode_salt_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10645000; +} + +static void +Opcode_salt_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a41000; +} + +static void +Opcode_salt_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158c000; +} + +static void +Opcode_salt_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275e000; +} + +static void +Opcode_salt_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512000; +} + +static void +Opcode_salt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b71008; +} + +static void +Opcode_salt_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510000; +} + +static void +Opcode_saltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x620000; +} + +static void +Opcode_saltu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0d000; +} + +static void +Opcode_saltu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1411000; +} + +static void +Opcode_saltu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e9000; + slotbuf[1] = 0; +} + +static void +Opcode_saltu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eaa000; + slotbuf[1] = 0; +} + +static void +Opcode_saltu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10728000; + slotbuf[1] = 0; +} + +static void +Opcode_saltu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b4000; +} + +static void +Opcode_saltu_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d3000; +} + +static void +Opcode_saltu_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ab000; +} + +static void +Opcode_saltu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10647000; +} + +static void +Opcode_saltu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a45000; +} + +static void +Opcode_saltu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cc000; +} + +static void +Opcode_saltu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275f000; +} + +static void +Opcode_saltu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1513000; +} + +static void +Opcode_saltu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b79008; +} + +static void +Opcode_saltu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1511000; +} + +static void +Opcode_rsr_opmode_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37700; +} + +static void +Opcode_wsr_opmode_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137700; +} + +static void +Opcode_xsr_opmode_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x617700; +} + +static void +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820000; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3010; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e200; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e200; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e300; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e400; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e400; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf02d; +} + +static void +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139000; +} + +static void +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619000; +} + +static void +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a000; +} + +static void +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a000; +} + +static void +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39100; +} + +static void +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139100; +} + +static void +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619100; +} + +static void +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a100; +} + +static void +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a100; +} + +static void +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a100; +} + +static void +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618000; +} + +static void +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38100; +} + +static void +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138100; +} + +static void +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618100; +} + +static void +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000; +} + +static void +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136000; +} + +static void +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616000; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e900; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e900; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e900; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ec00; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec00; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ec00; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ed00; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ed00; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ed00; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36800; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136800; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616800; +} + +static void +Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e0; +} + +static void +Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f0; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e000; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e010; +} + +static void +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135900; +} + +static void +Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_andb_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8f000; +} + +static void +Opcode_andb_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f5000; + slotbuf[1] = 0; +} + +static void +Opcode_andb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056b000; + slotbuf[1] = 0; +} + +static void +Opcode_andb_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3df000; +} + +static void +Opcode_andb_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10661000; +} + +static void +Opcode_andb_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a75000; +} + +static void +Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996800c; +} + +static void +Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_andbc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcce000; +} + +static void +Opcode_andbc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f6000; + slotbuf[1] = 0; +} + +static void +Opcode_andbc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056e000; + slotbuf[1] = 0; +} + +static void +Opcode_andbc_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0000; +} + +static void +Opcode_andbc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10663000; +} + +static void +Opcode_andbc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a79000; +} + +static void +Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9921000; +} + +static void +Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_orb_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xccf000; +} + +static void +Opcode_orb_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f7000; + slotbuf[1] = 0; +} + +static void +Opcode_orb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056f000; + slotbuf[1] = 0; +} + +static void +Opcode_orb_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e1000; +} + +static void +Opcode_orb_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10665000; +} + +static void +Opcode_orb_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a7d000; +} + +static void +Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9961000; +} + +static void +Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000; +} + +static void +Opcode_orbc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_orbc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f8000; + slotbuf[1] = 0; +} + +static void +Opcode_orbc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10572000; + slotbuf[1] = 0; +} + +static void +Opcode_orbc_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e2000; +} + +static void +Opcode_orbc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10667000; +} + +static void +Opcode_orbc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a81000; +} + +static void +Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929000; +} + +static void +Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420000; +} + +static void +Opcode_xorb_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc11000; +} + +static void +Opcode_xorb_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f9000; + slotbuf[1] = 0; +} + +static void +Opcode_xorb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10573000; + slotbuf[1] = 0; +} + +static void +Opcode_xorb_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e3000; +} + +static void +Opcode_xorb_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10669000; +} + +static void +Opcode_xorb_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a85000; +} + +static void +Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9969000; +} + +static void +Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_all4_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc92020; +} + +static void +Opcode_all4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19034010; + slotbuf[1] = 0; +} + +static void +Opcode_all4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af00a; + slotbuf[1] = 0; +} + +static void +Opcode_all4_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6300; +} + +static void +Opcode_all4_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687602; +} + +static void +Opcode_all4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80640; +} + +static void +Opcode_all4_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b020; +} + +static void +Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a7400; +} + +static void +Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_any4_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc92030; +} + +static void +Opcode_any4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19036010; + slotbuf[1] = 0; +} + +static void +Opcode_any4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af00b; + slotbuf[1] = 0; +} + +static void +Opcode_any4_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6340; +} + +static void +Opcode_any4_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687603; +} + +static void +Opcode_any4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80650; +} + +static void +Opcode_any4_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b030; +} + +static void +Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a7401; +} + +static void +Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000; +} + +static void +Opcode_all8_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc92420; +} + +static void +Opcode_all8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19034210; + slotbuf[1] = 0; +} + +static void +Opcode_all8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af80a; + slotbuf[1] = 0; +} + +static void +Opcode_all8_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6380; +} + +static void +Opcode_all8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687700; +} + +static void +Opcode_all8_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80660; +} + +static void +Opcode_all8_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b420; +} + +static void +Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a7402; +} + +static void +Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_any8_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc92430; +} + +static void +Opcode_any8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19036210; + slotbuf[1] = 0; +} + +static void +Opcode_any8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af80b; + slotbuf[1] = 0; +} + +static void +Opcode_any8_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6390; +} + +static void +Opcode_any8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687704; +} + +static void +Opcode_any8_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80670; +} + +static void +Opcode_any8_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b430; +} + +static void +Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a7403; +} + +static void +Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76; +} + +static void +Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1076; +} + +static void +Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc30000; +} + +static void +Opcode_movf_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0e000; +} + +static void +Opcode_movf_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f0000; + slotbuf[1] = 0; +} + +static void +Opcode_movf_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055f000; + slotbuf[1] = 0; +} + +static void +Opcode_movf_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3da000; +} + +static void +Opcode_movf_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10655000; +} + +static void +Opcode_movf_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a61000; +} + +static void +Opcode_movf_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2766000; +} + +static void +Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9928008; +} + +static void +Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30000; +} + +static void +Opcode_movt_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0f000; +} + +static void +Opcode_movt_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f1000; + slotbuf[1] = 0; +} + +static void +Opcode_movt_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10562000; + slotbuf[1] = 0; +} + +static void +Opcode_movt_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3db000; +} + +static void +Opcode_movt_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10657000; +} + +static void +Opcode_movt_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a65000; +} + +static void +Opcode_movt_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2767000; +} + +static void +Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9968008; +} + +static void +Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30400; +} + +static void +Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130400; +} + +static void +Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610400; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ea00; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea00; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ea00; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f000; +} + +static void +Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f100; +} + +static void +Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f100; +} + +static void +Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f100; +} + +static void +Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f200; +} + +static void +Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f200; +} + +static void +Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f200; +} + +static void +Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e2; +} + +static void +Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70c2; +} + +static void +Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270d2; +} + +static void +Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370d2; +} + +static void +Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70d2; +} + +static void +Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f2; +} + +static void +Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10000; +} + +static void +Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf12000; +} + +static void +Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf11000; +} + +static void +Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13000; +} + +static void +Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7042; +} + +static void +Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7052; +} + +static void +Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf7082; +} + +static void +Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x47082; +} + +static void +Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57082; +} + +static void +Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7062; +} + +static void +Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7072; +} + +static void +Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7002; +} + +static void +Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7022; +} + +static void +Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7012; +} + +static void +Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7032; +} + +static void +Opcode_dpfm_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193000; +} + +static void +Opcode_dpfm_b_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a1af00; + slotbuf[1] = 0; +} + +static void +Opcode_dpfm_b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0130c; +} + +static void +Opcode_dpfm_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x197000; +} + +static void +Opcode_dpfm_bf_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a22f00; + slotbuf[1] = 0; +} + +static void +Opcode_dpfm_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0170c; +} + +static void +Opcode_dpfr_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191000; +} + +static void +Opcode_dpfr_b_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a2af00; + slotbuf[1] = 0; +} + +static void +Opcode_dpfr_b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01b0c; +} + +static void +Opcode_dpfr_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x195000; +} + +static void +Opcode_dpfr_bf_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a32f00; + slotbuf[1] = 0; +} + +static void +Opcode_dpfr_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01f0c; +} + +static void +Opcode_dpfw_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192000; +} + +static void +Opcode_dpfw_b_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a3af00; + slotbuf[1] = 0; +} + +static void +Opcode_dpfw_b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0930c; +} + +static void +Opcode_dpfw_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x196000; +} + +static void +Opcode_dpfw_bf_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a42f00; + slotbuf[1] = 0; +} + +static void +Opcode_dpfw_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0970c; +} + +static void +Opcode_pfnxt_f_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3430; +} + +static void +Opcode_dhi_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x199000; +} + +static void +Opcode_dhwbi_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19b000; +} + +static void +Opcode_dhwb_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a000; +} + +static void +Opcode_pfend_a_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3030; +} + +static void +Opcode_pfend_o_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3130; +} + +static void +Opcode_pfwait_a_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3230; +} + +static void +Opcode_pfwait_r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3330; +} + +static void +Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27082; +} + +static void +Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37082; +} + +static void +Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7082; +} + +static void +Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf19000; +} + +static void +Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf18000; +} + +static void +Opcode_sdcw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1b000; +} + +static void +Opcode_ldcw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1a000; +} + +static void +Opcode_rsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32800; +} + +static void +Opcode_wsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132800; +} + +static void +Opcode_xsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612800; +} + +static void +Opcode_wsr_cacheadrdis_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136200; +} + +static void +Opcode_rsr_cacheadrdis_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36200; +} + +static void +Opcode_xsr_cacheadrdis_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616200; +} + +static void +Opcode_rptlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50b000; +} + +static void +Opcode_pptlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50d000; +} + +static void +Opcode_rptlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50f000; +} + +static void +Opcode_wptlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50e000; +} + +static void +Opcode_rsr_mpuenb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35a00; +} + +static void +Opcode_wsr_mpuenb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135a00; +} + +static void +Opcode_xsr_mpuenb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615a00; +} + +static void +Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e000; +} + +static void +Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e000; +} + +static void +Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000; +} + +static void +Opcode_clamps_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4e000; +} + +static void +Opcode_clamps_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1412000; +} + +static void +Opcode_clamps_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f2000; + slotbuf[1] = 0; +} + +static void +Opcode_clamps_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee2000; + slotbuf[1] = 0; +} + +static void +Opcode_clamps_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10566000; + slotbuf[1] = 0; +} + +static void +Opcode_clamps_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb000; +} + +static void +Opcode_clamps_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3dc000; +} + +static void +Opcode_clamps_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b2000; +} + +static void +Opcode_clamps_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10659000; +} + +static void +Opcode_clamps_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a69000; +} + +static void +Opcode_clamps_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158e000; +} + +static void +Opcode_clamps_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2768000; +} + +static void +Opcode_clamps_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514000; +} + +static void +Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x992000c; +} + +static void +Opcode_clamps_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512000; +} + +static void +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_max_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc9000; +} + +static void +Opcode_max_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14cd000; +} + +static void +Opcode_max_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74bf000; + slotbuf[1] = 0; +} + +static void +Opcode_max_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e5a000; + slotbuf[1] = 0; +} + +static void +Opcode_max_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054e000; + slotbuf[1] = 0; +} + +static void +Opcode_max_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa000; +} + +static void +Opcode_max_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c9000; +} + +static void +Opcode_max_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a1000; +} + +static void +Opcode_max_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10639000; +} + +static void +Opcode_max_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a1d000; +} + +static void +Opcode_max_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154a000; +} + +static void +Opcode_max_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2755000; +} + +static void +Opcode_max_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cf000; +} + +static void +Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9960004; +} + +static void +Opcode_max_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cd000; +} + +static void +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_maxu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a000; +} + +static void +Opcode_maxu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140e000; +} + +static void +Opcode_maxu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e0000; + slotbuf[1] = 0; +} + +static void +Opcode_maxu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e62000; + slotbuf[1] = 0; +} + +static void +Opcode_maxu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054f000; + slotbuf[1] = 0; +} + +static void +Opcode_maxu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab000; +} + +static void +Opcode_maxu_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ca000; +} + +static void +Opcode_maxu_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a2000; +} + +static void +Opcode_maxu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063a000; +} + +static void +Opcode_maxu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a21000; +} + +static void +Opcode_maxu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158a000; +} + +static void +Opcode_maxu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2756000; +} + +static void +Opcode_maxu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510000; +} + +static void +Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9928004; +} + +static void +Opcode_maxu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150e000; +} + +static void +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_min_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0b000; +} + +static void +Opcode_min_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140f000; +} + +static void +Opcode_min_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e1000; + slotbuf[1] = 0; +} + +static void +Opcode_min_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6a000; + slotbuf[1] = 0; +} + +static void +Opcode_min_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10751000; + slotbuf[1] = 0; +} + +static void +Opcode_min_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac000; +} + +static void +Opcode_min_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3cb000; +} + +static void +Opcode_min_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a3000; +} + +static void +Opcode_min_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063b000; +} + +static void +Opcode_min_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a25000; +} + +static void +Opcode_min_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ca000; +} + +static void +Opcode_min_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2757000; +} + +static void +Opcode_min_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1511000; +} + +static void +Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9968004; +} + +static void +Opcode_min_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150f000; +} + +static void +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_minu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4a000; +} + +static void +Opcode_minu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144e000; +} + +static void +Opcode_minu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e2000; + slotbuf[1] = 0; +} + +static void +Opcode_minu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e72000; + slotbuf[1] = 0; +} + +static void +Opcode_minu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10753000; + slotbuf[1] = 0; +} + +static void +Opcode_minu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ad000; +} + +static void +Opcode_minu_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3cc000; +} + +static void +Opcode_minu_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a4000; +} + +static void +Opcode_minu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063c000; +} + +static void +Opcode_minu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a29000; +} + +static void +Opcode_minu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150b000; +} + +static void +Opcode_minu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2758000; +} + +static void +Opcode_minu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1550000; +} + +static void +Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9970008; +} + +static void +Opcode_minu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154e000; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40e000; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40f000; +} + +static void +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_sext_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4f000; +} + +static void +Opcode_sext_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1413000; +} + +static void +Opcode_sext_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f3000; + slotbuf[1] = 0; +} + +static void +Opcode_sext_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eea000; + slotbuf[1] = 0; +} + +static void +Opcode_sext_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10567000; + slotbuf[1] = 0; +} + +static void +Opcode_sext_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc000; +} + +static void +Opcode_sext_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3dd000; +} + +static void +Opcode_sext_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b3000; +} + +static void +Opcode_sext_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065b000; +} + +static void +Opcode_sext_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a6d000; +} + +static void +Opcode_sext_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ce000; +} + +static void +Opcode_sext_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2769000; +} + +static void +Opcode_sext_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1515000; +} + +static void +Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996000c; +} + +static void +Opcode_sext_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1513000; +} + +static void +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb002; +} + +static void +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002; +} + +static void +Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36300; +} + +static void +Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136300; +} + +static void +Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616300; +} + +static void +Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20000; +} + +static void +Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf20000; +} + +static void +Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe20000; +} + +static void +Opcode_rsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35f00; +} + +static void +Opcode_wsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135f00; +} + +static void +Opcode_xsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615f00; +} + +static void +Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x406000; +} + +static void +Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x407000; +} + +static void +Opcode_beqz_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000a; + slotbuf[1] = 0; +} + +static void +Opcode_beqz_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000a0; + slotbuf[1] = 0; +} + +static void +Opcode_beqz_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c0; +} + +static void +Opcode_bgez_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000e; + slotbuf[1] = 0; +} + +static void +Opcode_bgez_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000e0; + slotbuf[1] = 0; +} + +static void +Opcode_bgez_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000e0; +} + +static void +Opcode_bltz_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000040a; + slotbuf[1] = 0; +} + +static void +Opcode_bltz_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004a0; + slotbuf[1] = 0; +} + +static void +Opcode_bltz_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001c0; +} + +static void +Opcode_bnez_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000040e; + slotbuf[1] = 0; +} + +static void +Opcode_bnez_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004e0; + slotbuf[1] = 0; +} + +static void +Opcode_bnez_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001e0; +} + +static void +Opcode_beqi_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0; +} + +static void +Opcode_beqi_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0; +} + +static void +Opcode_beqi_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; +} + +static void +Opcode_bgei_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000004; + slotbuf[1] = 0; +} + +static void +Opcode_bgei_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000040; + slotbuf[1] = 0; +} + +static void +Opcode_bgei_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; +} + +static void +Opcode_blti_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000c; + slotbuf[1] = 0; +} + +static void +Opcode_blti_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c0; + slotbuf[1] = 0; +} + +static void +Opcode_blti_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000060; +} + +static void +Opcode_bnei_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000006; + slotbuf[1] = 0; +} + +static void +Opcode_bnei_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000060; + slotbuf[1] = 0; +} + +static void +Opcode_bnei_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000a0; +} + +static void +Opcode_bgeui_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000008; + slotbuf[1] = 0; +} + +static void +Opcode_bgeui_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000080; + slotbuf[1] = 0; +} + +static void +Opcode_bgeui_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000040; +} + +static void +Opcode_bltui_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000002; + slotbuf[1] = 0; +} + +static void +Opcode_bltui_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; + slotbuf[1] = 0; +} + +static void +Opcode_bltui_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000080; +} + +static void +Opcode_bbci_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0; +} + +static void +Opcode_bbci_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_bbci_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_bbsi_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000400; + slotbuf[1] = 0; +} + +static void +Opcode_bbsi_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; + slotbuf[1] = 0; +} + +static void +Opcode_bbsi_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; +} + +static void +Opcode_ball_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000800; + slotbuf[1] = 0; +} + +static void +Opcode_ball_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; + slotbuf[1] = 0; +} + +static void +Opcode_ball_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; +} + +static void +Opcode_bany_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000c00; + slotbuf[1] = 0; +} + +static void +Opcode_bany_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600; + slotbuf[1] = 0; +} + +static void +Opcode_bany_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500; +} + +static void +Opcode_bbc_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000900; + slotbuf[1] = 0; +} + +static void +Opcode_bbc_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00; + slotbuf[1] = 0; +} + +static void +Opcode_bbc_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600; +} + +static void +Opcode_bbs_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000d00; + slotbuf[1] = 0; +} + +static void +Opcode_bbs_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00; + slotbuf[1] = 0; +} + +static void +Opcode_bbs_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700; +} + +static void +Opcode_beq_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000200; + slotbuf[1] = 0; +} + +static void +Opcode_beq_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100; + slotbuf[1] = 0; +} + +static void +Opcode_beq_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; +} + +static void +Opcode_bgeu_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000600; + slotbuf[1] = 0; +} + +static void +Opcode_bgeu_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500; + slotbuf[1] = 0; +} + +static void +Opcode_bgeu_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900; +} + +static void +Opcode_bge_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000a00; + slotbuf[1] = 0; +} + +static void +Opcode_bge_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900; + slotbuf[1] = 0; +} + +static void +Opcode_bge_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00; +} + +static void +Opcode_bltu_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000e00; + slotbuf[1] = 0; +} + +static void +Opcode_bltu_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00; + slotbuf[1] = 0; +} + +static void +Opcode_bltu_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00; +} + +static void +Opcode_blt_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000300; + slotbuf[1] = 0; +} + +static void +Opcode_blt_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300; + slotbuf[1] = 0; +} + +static void +Opcode_blt_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00; +} + +static void +Opcode_bnall_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000700; + slotbuf[1] = 0; +} + +static void +Opcode_bnall_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700; + slotbuf[1] = 0; +} + +static void +Opcode_bnall_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00; +} + +static void +Opcode_bne_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000b00; + slotbuf[1] = 0; +} + +static void +Opcode_bne_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00; + slotbuf[1] = 0; +} + +static void +Opcode_bne_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00; +} + +static void +Opcode_bnone_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000f00; + slotbuf[1] = 0; +} + +static void +Opcode_bnone_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00; + slotbuf[1] = 0; +} + +static void +Opcode_bnone_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00; +} + +static void +Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f00; +} + +static void +Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f000; +} + +static void +Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f10; +} + +static void +Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f100; +} + +static void +Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f20; +} + +static void +Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f200; +} + +static void +Opcode_rur_ae_cw_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f30; +} + +static void +Opcode_wur_ae_cw_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f300; +} + +static void +Opcode_rur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f60; +} + +static void +Opcode_wur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f600; +} + +static void +Opcode_rur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f70; +} + +static void +Opcode_wur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f700; +} + +static void +Opcode_rur_ae_cbegin1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f80; +} + +static void +Opcode_wur_ae_cbegin1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f800; +} + +static void +Opcode_rur_ae_cend1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f90; +} + +static void +Opcode_wur_ae_cend1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f900; +} + +static void +Opcode_rur_ae_cbegin2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30fa0; +} + +static void +Opcode_wur_ae_cbegin2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3fa00; +} + +static void +Opcode_rur_ae_cend2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30fb0; +} + +static void +Opcode_wur_ae_cend2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3fb00; +} + +static void +Opcode_ae_sext16_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800d; +} + +static void +Opcode_ae_zext16_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900d; +} + +static void +Opcode_ae_zext8_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00d; +} + +static void +Opcode_ae_clamps16_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00d; +} + +static void +Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e80; +} + +static void +Opcode_rur_fcr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a7030; +} + +static void +Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e800; +} + +static void +Opcode_wur_fcr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa64005; +} + +static void +Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e90; +} + +static void +Opcode_rur_fsr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a7070; +} + +static void +Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e900; +} + +static void +Opcode_wur_fsr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa66005; +} + +static void +Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e60; +} + +static void +Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e600; +} + +static void +Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1200; +} + +static void +Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static void +Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ea04; +} + +static void +Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67eb04; +} + +static void +Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ec04; +} + +static void +Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ed04; +} + +static void +Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ee04; +} + +static void +Opcode_rur_ae_bitptr_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afe0b; + slotbuf[1] = 0; +} + +static void +Opcode_rur_ae_bitptr_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687705; +} + +static void +Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ef04; +} + +static void +Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f004; +} + +static void +Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f104; +} + +static void +Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f204; +} + +static void +Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f304; +} + +static void +Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f404; +} + +static void +Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f504; +} + +static void +Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f604; +} + +static void +Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f704; +} + +static void +Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f804; +} + +static void +Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f904; +} + +static void +Opcode_rur_ae_cwrap_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67fa04; +} + +static void +Opcode_wur_ae_cwrap_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67fb04; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3c000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7450000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10676000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168300; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054c000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901800; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133c000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2676000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c0000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb980008; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13be000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7c000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1440000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7452000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10678000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054e000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941800; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137c000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2678000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1502000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c0008; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fe000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1480000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7454000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1067a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170100; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10550000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981800; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13bc000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x267a000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1542000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb98000c; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xafc000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c0000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7456000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1067c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170200; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10552000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1800; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fc000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x267c000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1582000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c000c; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1540000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3e000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1402000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7458000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1067e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170300; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10554000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901a00; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133e000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x267e000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c2000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb981000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7e000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1442000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x745a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10556000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941a00; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137e000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2680000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1504000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c1000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c0000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabe000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1482000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x745c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10682000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178100; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10558000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981a00; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13be000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2682000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1544000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb981004; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1502000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xafe000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c2000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x745e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10684000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178200; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055a000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1a00; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fe000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2684000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1584000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c1004; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1542000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1404000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7490000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10686000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178300; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055c000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901c00; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2686000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c4000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb981008; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1582000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1444000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7492000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10688000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055e000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941c00; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1540000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2688000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1506000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c1008; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c2000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1484000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7494000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1068a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180100; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10560000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981c00; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268a000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1546000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb98100c; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1504000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c4000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7496000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1068c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180200; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10562000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1c00; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c0000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268c000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1586000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c100c; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1544000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae0000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1266000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c836000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110300; +} + +static void +Opcode_ae_l16m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10466000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e4000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2606000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1366000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a60004; +} + +static void +Opcode_ae_l16m_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1366000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa22000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1268000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c874000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10468000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900200; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1326000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2608000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1368000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1368000; +} + +static void +Opcode_ae_l16m_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa20000; +} + +static void +Opcode_ae_l16m_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1260000; +} + +static void +Opcode_ae_l16m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c832000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ec000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ae_l16m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10460000; +} + +static void +Opcode_ae_l16m_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900000; +} + +static void +Opcode_ae_l16m_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1324000; +} + +static void +Opcode_ae_l16m_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2600000; +} + +static void +Opcode_ae_l16m_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1360000; +} + +static void +Opcode_ae_l16m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9860000; +} + +static void +Opcode_ae_l16m_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1360000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1262000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c872000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_iu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ee000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_iu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110100; +} + +static void +Opcode_ae_l16m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10462000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1364000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2602000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1362000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9860004; +} + +static void +Opcode_ae_l16m_iu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1362000; +} + +static void +Opcode_ae_l16m_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa0000; +} + +static void +Opcode_ae_l16m_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1264000; +} + +static void +Opcode_ae_l16m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c834000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110200; +} + +static void +Opcode_ae_l16m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10464000; +} + +static void +Opcode_ae_l16m_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980000; +} + +static void +Opcode_ae_l16m_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a4000; +} + +static void +Opcode_ae_l16m_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2604000; +} + +static void +Opcode_ae_l16m_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1364000; +} + +static void +Opcode_ae_l16m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a60000; +} + +static void +Opcode_ae_l16m_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1364000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa62000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x126a000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c876000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1046a000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940200; +} + +static void +Opcode_ae_l16m_xu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1366000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260a000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136a000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e0000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136a000; +} + +static void +Opcode_ae_l16_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2a000; +} + +static void +Opcode_ae_l16_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ac000; +} + +static void +Opcode_ae_l16_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8cc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1047e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_ae_l16_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10508000; +} + +static void +Opcode_ae_l16_xc_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x920300; +} + +static void +Opcode_ae_l16_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940a00; +} + +static void +Opcode_ae_l16_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136e000; +} + +static void +Opcode_ae_l16_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262a000; +} + +static void +Opcode_ae_l16_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec000; +} + +static void +Opcode_ae_l16_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x982000c; +} + +static void +Opcode_ae_l16_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ac000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6a000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ec000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8ce000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050a000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980a00; +} + +static void +Opcode_ae_l16_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ae000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262c000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ae000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x986000c; +} + +static void +Opcode_ae_l16_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec000; +} + +static void +Opcode_ae_l16_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa68000; +} + +static void +Opcode_ae_l16_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e8000; +} + +static void +Opcode_ae_l16_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8c6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10472000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128200; +} + +static void +Opcode_ae_l16_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10502000; +} + +static void +Opcode_ae_l16_i_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x908300; +} + +static void +Opcode_ae_l16_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980800; +} + +static void +Opcode_ae_l16_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ac000; +} + +static void +Opcode_ae_l16_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2624000; +} + +static void +Opcode_ae_l16_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13aa000; +} + +static void +Opcode_ae_l16_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9c100c; +} + +static void +Opcode_ae_l16_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e8000; +} + +static void +Opcode_ae_l16_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa8000; +} + +static void +Opcode_ae_l16_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12aa000; +} + +static void +Opcode_ae_l16_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8c8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10476000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128300; +} + +static void +Opcode_ae_l16_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10504000; +} + +static void +Opcode_ae_l16_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910300; +} + +static void +Opcode_ae_l16_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0800; +} + +static void +Opcode_ae_l16_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec000; +} + +static void +Opcode_ae_l16_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2626000; +} + +static void +Opcode_ae_l16_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea000; +} + +static void +Opcode_ae_l16_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9820008; +} + +static void +Opcode_ae_l16_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13aa000; +} + +static void +Opcode_ae_l16_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae8000; +} + +static void +Opcode_ae_l16_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ea000; +} + +static void +Opcode_ae_l16_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8ca000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1047a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ae_l16_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10506000; +} + +static void +Opcode_ae_l16_x_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x918300; +} + +static void +Opcode_ae_l16_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900a00; +} + +static void +Opcode_ae_l16_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132e000; +} + +static void +Opcode_ae_l16_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2628000; +} + +static void +Opcode_ae_l16_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ac000; +} + +static void +Opcode_ae_l16_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9860008; +} + +static void +Opcode_ae_l16_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea000; +} + +static void +Opcode_ae_l16_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaaa000; +} + +static void +Opcode_ae_l16_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ae000; +} + +static void +Opcode_ae_l16_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_ae_l16_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050c000; +} + +static void +Opcode_ae_l16_xp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x928300; +} + +static void +Opcode_ae_l16_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0a00; +} + +static void +Opcode_ae_l16_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee000; +} + +static void +Opcode_ae_l16_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262e000; +} + +static void +Opcode_ae_l16_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee000; +} + +static void +Opcode_ae_l16_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a20008; +} + +static void +Opcode_ae_l16_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ae000; +} + +static void +Opcode_ae_l8_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc06000; +} + +static void +Opcode_ae_l8_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140a000; +} + +static void +Opcode_ae_l8_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74d8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190200; +} + +static void +Opcode_ae_l8_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10574000; +} + +static void +Opcode_ae_l8_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942200; +} + +static void +Opcode_ae_l8_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1546000; +} + +static void +Opcode_ae_l8_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a0000; +} + +static void +Opcode_ae_l8_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150c000; +} + +static void +Opcode_ae_l8_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab40000; +} + +static void +Opcode_ae_l8_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1588000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc46000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144a000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74da000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10576000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982200; +} + +static void +Opcode_ae_l8_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1586000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a2000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154c000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab40004; +} + +static void +Opcode_ae_l8_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c8000; +} + +static void +Opcode_ae_l8_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc44000; +} + +static void +Opcode_ae_l8_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1448000; +} + +static void +Opcode_ae_l8_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74d2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10696000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188300; +} + +static void +Opcode_ae_l8_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056e000; +} + +static void +Opcode_ae_l8_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982000; +} + +static void +Opcode_ae_l8_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1584000; +} + +static void +Opcode_ae_l8_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269a000; +} + +static void +Opcode_ae_l8_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154a000; +} + +static void +Opcode_ae_l8_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa941004; +} + +static void +Opcode_ae_l8_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c6000; +} + +static void +Opcode_ae_l8_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc84000; +} + +static void +Opcode_ae_l8_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1488000; +} + +static void +Opcode_ae_l8_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74d4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10698000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_ae_l8_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10570000; +} + +static void +Opcode_ae_l8_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2000; +} + +static void +Opcode_ae_l8_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c4000; +} + +static void +Opcode_ae_l8_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269c000; +} + +static void +Opcode_ae_l8_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158a000; +} + +static void +Opcode_ae_l8_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa941008; +} + +static void +Opcode_ae_l8_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1508000; +} + +static void +Opcode_ae_l8_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc4000; +} + +static void +Opcode_ae_l8_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c8000; +} + +static void +Opcode_ae_l8_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74d6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190100; +} + +static void +Opcode_ae_l8_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10572000; +} + +static void +Opcode_ae_l8_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902200; +} + +static void +Opcode_ae_l8_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1506000; +} + +static void +Opcode_ae_l8_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269e000; +} + +static void +Opcode_ae_l8_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ca000; +} + +static void +Opcode_ae_l8_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa94100c; +} + +static void +Opcode_ae_l8_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1548000; +} + +static void +Opcode_ae_l8_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc86000; +} + +static void +Opcode_ae_l8_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148a000; +} + +static void +Opcode_ae_l8_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74dc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190300; +} + +static void +Opcode_ae_l8_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10578000; +} + +static void +Opcode_ae_l8_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2200; +} + +static void +Opcode_ae_l8_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c6000; +} + +static void +Opcode_ae_l8_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a4000; +} + +static void +Opcode_ae_l8_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158c000; +} + +static void +Opcode_ae_l8_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab40008; +} + +static void +Opcode_ae_l8_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150a000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaac000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b0000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8d8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10648000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138200; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10514000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2636000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f0000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a0008; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b0000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaec000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f0000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8da000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10516000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2638000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1332000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e0008; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f0000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaea000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ee000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8d2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10642000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_ae_l32f24_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050e000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2630000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a60008; +} + +static void +Opcode_ae_l32f24_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2c000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1230000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8d4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10644000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10510000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2632000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1370000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a2000c; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6c000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1270000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8d6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10646000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138100; +} + +static void +Opcode_ae_l32f24_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10512000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2634000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b0000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a6000c; +} + +static void +Opcode_ae_l32f24_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1370000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2e000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1232000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8dc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138300; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10518000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263a000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1372000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a000c; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1332000; +} + +static void +Opcode_ae_l32_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf6000; +} + +static void +Opcode_ae_l32_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12fa000; +} + +static void +Opcode_ae_l32_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7410000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1066a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ae_l32_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1053c000; +} + +static void +Opcode_ae_l32_xc_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x960300; +} + +static void +Opcode_ae_l32_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981200; +} + +static void +Opcode_ae_l32_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b6000; +} + +static void +Opcode_ae_l32_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2662000; +} + +static void +Opcode_ae_l32_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137c000; +} + +static void +Opcode_ae_l32_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3a100c; +} + +static void +Opcode_ae_l32_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ba000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa38000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x123c000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7412000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1053e000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1200; +} + +static void +Opcode_ae_l32_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f6000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2664000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13bc000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3e100c; +} + +static void +Opcode_ae_l32_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fa000; +} + +static void +Opcode_ae_l32_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa36000; +} + +static void +Opcode_ae_l32_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x123a000; +} + +static void +Opcode_ae_l32_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8fa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10664000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158100; +} + +static void +Opcode_ae_l32_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10536000; +} + +static void +Opcode_ae_l32_i_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x948300; +} + +static void +Opcode_ae_l32_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1000; +} + +static void +Opcode_ae_l32_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f4000; +} + +static void +Opcode_ae_l32_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x265c000; +} + +static void +Opcode_ae_l32_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ba000; +} + +static void +Opcode_ae_l32_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3e100c; +} + +static void +Opcode_ae_l32_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f8000; +} + +static void +Opcode_ae_l32_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa76000; +} + +static void +Opcode_ae_l32_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x127a000; +} + +static void +Opcode_ae_l32_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8fc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10666000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158200; +} + +static void +Opcode_ae_l32_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10538000; +} + +static void +Opcode_ae_l32_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x950300; +} + +static void +Opcode_ae_l32_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901200; +} + +static void +Opcode_ae_l32_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1336000; +} + +static void +Opcode_ae_l32_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x265e000; +} + +static void +Opcode_ae_l32_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fa000; +} + +static void +Opcode_ae_l32_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3a100c; +} + +static void +Opcode_ae_l32_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a000; +} + +static void +Opcode_ae_l32_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab6000; +} + +static void +Opcode_ae_l32_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ba000; +} + +static void +Opcode_ae_l32_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8fe000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10668000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158300; +} + +static void +Opcode_ae_l32_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1053a000; +} + +static void +Opcode_ae_l32_x_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x958300; +} + +static void +Opcode_ae_l32_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941200; +} + +static void +Opcode_ae_l32_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1376000; +} + +static void +Opcode_ae_l32_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2660000; +} + +static void +Opcode_ae_l32_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133c000; +} + +static void +Opcode_ae_l32_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3e100c; +} + +static void +Opcode_ae_l32_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137a000; +} + +static void +Opcode_ae_l32_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa78000; +} + +static void +Opcode_ae_l32_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x127c000; +} + +static void +Opcode_ae_l32_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7414000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1066c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160100; +} + +static void +Opcode_ae_l32_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10540000; +} + +static void +Opcode_ae_l32_xp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x968300; +} + +static void +Opcode_ae_l32_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901400; +} + +static void +Opcode_ae_l32_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338000; +} + +static void +Opcode_ae_l32_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2666000; +} + +static void +Opcode_ae_l32_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fc000; +} + +static void +Opcode_ae_l32_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3a100c; +} + +static void +Opcode_ae_l32_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133c000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1234000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8e4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10652000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140300; +} + +static void +Opcode_ae_l32m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10520000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0c00; +} + +static void +Opcode_ae_l32m_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f0000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2642000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1374000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa000c; +} + +static void +Opcode_ae_l32m_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1334000; +} + +static void +Opcode_ae_l32m_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6e000; +} + +static void +Opcode_ae_l32m_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1272000; +} + +static void +Opcode_ae_l32m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8de000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_l32m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1051a000; +} + +static void +Opcode_ae_l32m_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900c00; +} + +static void +Opcode_ae_l32m_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330000; +} + +static void +Opcode_ae_l32m_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263c000; +} + +static void +Opcode_ae_l32m_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b2000; +} + +static void +Opcode_ae_l32m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e000c; +} + +static void +Opcode_ae_l32m_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1372000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaae000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b2000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_iu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_iu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140100; +} + +static void +Opcode_ae_l32m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1051c000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940c00; +} + +static void +Opcode_ae_l32m_iu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1370000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263e000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f2000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa0008; +} + +static void +Opcode_ae_l32m_iu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b2000; +} + +static void +Opcode_ae_l32m_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaee000; +} + +static void +Opcode_ae_l32m_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f2000; +} + +static void +Opcode_ae_l32m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8e2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10650000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140200; +} + +static void +Opcode_ae_l32m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1051e000; +} + +static void +Opcode_ae_l32m_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980c00; +} + +static void +Opcode_ae_l32m_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b0000; +} + +static void +Opcode_ae_l32m_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2640000; +} + +static void +Opcode_ae_l32m_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1334000; +} + +static void +Opcode_ae_l32m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae0008; +} + +static void +Opcode_ae_l32m_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f2000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa70000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1274000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8e6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10654000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10522000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900e00; +} + +static void +Opcode_ae_l32m_xu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1332000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2644000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b4000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae000c; +} + +static void +Opcode_ae_l32m_xu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1374000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa64000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e0000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c83e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10472000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940400; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1368000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2612000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e0000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa981000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e0000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa4000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a2000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c878000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10474000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980400; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a8000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2614000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a2000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a2000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa2000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x126c000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c838000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118100; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1046c000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980200; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a6000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260c000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136c000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e0004; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136c000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae2000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x126e000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c83a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118200; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1046e000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0200; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e6000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260e000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136e000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae0000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136e000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa24000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a0000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c83c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118300; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10470000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900400; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1328000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2610000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a0000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae0004; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a0000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae4000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e2000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c87a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fe000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120100; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10476000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0400; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e8000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2616000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e2000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9c1000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e2000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa32000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1236000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8ea000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10658000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148300; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10526000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ca000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ca000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264a000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1376000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83e100c; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f4000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa72000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1276000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8ec000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10528000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6cc000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6cc000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264c000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b6000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x93a100c; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1336000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab0000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b4000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19002030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00202; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148100; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10618008; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680050; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680050; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2646000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f4000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9871001; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000d; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc50080; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d2000; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d86a080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10576008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198300; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c2002; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea000; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea000; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276e000; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d4000; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b70006; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d2000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd0080; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1454000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d834080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1061e004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0100; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fc003; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea080; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea080; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277e000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996100e; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1554000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1492008; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74fc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01e01; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198208; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c4002; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276c080; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1594008; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b7000a; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1592008; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd00c0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1454004; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8340c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c010e; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2001; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6080; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6080; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277e040; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556004; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0303; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516002; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd00d0; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1454005; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8360c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00402; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2009; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6090; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6090; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277e050; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556005; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a0303; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556002; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf0000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f4000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8e8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10656000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148200; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10524000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c8000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c8000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2648000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1336000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a100c; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b4000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab2000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b6000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8ee000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1052a000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ce000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ce000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264e000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f6000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x93e100c; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1376000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa74000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1278000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8f2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150300; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1052e000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d2000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d2000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0e00; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f2000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2654000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b8000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3e100c; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f6000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab4000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b8000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8f4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10530000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d4000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d4000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1334000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2656000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f8000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3a100c; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf2000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f6000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19004030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04203; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150100; +} + +static void +Opcode_ae_l32x2_i_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x298000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10618004; +} + +static void +Opcode_ae_l32x2_i_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930300; +} + +static void +Opcode_ae_l32x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680060; +} + +static void +Opcode_ae_l32x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680060; +} + +static void +Opcode_ae_l32x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940e00; +} + +static void +Opcode_ae_l32x2_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1372000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2650000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9871002; +} + +static void +Opcode_ae_l32x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000e; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90080; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d2008; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74fe000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01f01; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057a008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198308; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c6002; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x970380; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee000; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee000; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac0400; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1550000; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276e080; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d4008; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b7000e; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d2008; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd00e0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1454006; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8340d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00401; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c010f; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2005; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f60a0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f60a0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80600; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200f; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277e060; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556006; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e0303; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1596002; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd00f0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1454007; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8360d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00403; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a200d; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f60b0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f60b0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80610; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x155200f; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277e070; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556007; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e0303; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d6002; +} + +static void +Opcode_ae_l32x2_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa34000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1238000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8f0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150200; +} + +static void +Opcode_ae_l32x2_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1052c000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x938300; +} + +static void +Opcode_ae_l32x2_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980e00; +} + +static void +Opcode_ae_l32x2_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b2000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2652000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1378000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3a100c; +} + +static void +Opcode_ae_l32x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b6000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf4000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f8000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8f8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10662000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29a000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10534000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940300; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d6000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d6000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b4000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x265a000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137a000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3a100c; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b8000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa6000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a6000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c87e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10466000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1047a000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c2000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c2000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980600; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13aa000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261c000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a6000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9c1004; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e4000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae6000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e6000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1047c000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c4000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c4000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0600; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261e000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e6000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa981008; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a6000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa26000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a4000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00203; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120200; +} + +static void +Opcode_ae_l16x4_i_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x294000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10618000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900300; +} + +static void +Opcode_ae_l16x4_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680040; +} + +static void +Opcode_ae_l16x4_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680040; +} + +static void +Opcode_ae_l16x4_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900600; +} + +static void +Opcode_ae_l16x4_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132a000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2618000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a4000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9871000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000c; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc50000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1492000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d82a080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10576000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198200; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0002; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x970300; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e8000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e8000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80400; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276c000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1594000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b70002; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1592000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa66000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e4000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c87c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10462000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120300; +} + +static void +Opcode_ae_l16x4_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10478000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940600; +} + +static void +Opcode_ae_l16x4_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136a000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261a000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e4000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa981004; +} + +static void +Opcode_ae_l16x4_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a4000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa28000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a8000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8c4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1046e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128100; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x296000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c6000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c6000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940800; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136c000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2622000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e8000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa98100c; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a8000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc82000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1486000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x749a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188100; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10566000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e2000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e2000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981e00; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1582000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2692000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1548000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa940004; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c4000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc2000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c6000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x749c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10568000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e4000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e4000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1e00; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c2000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2694000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1588000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa940008; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1506000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc02000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1406000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19082030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0420b; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10708001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180300; +} + +static void +Opcode_ae_l8x8_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10620008; +} + +static void +Opcode_ae_l8x8_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0050; +} + +static void +Opcode_ae_l8x8_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0050; +} + +static void +Opcode_ae_l8x8_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901e00; +} + +static void +Opcode_ae_l8x8_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1502000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268e000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c6000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9971001; +} + +static void +Opcode_ae_l8x8_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144000d; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd0000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1414000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74fc080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c8002; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e8080; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e8080; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80480; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1590000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2770000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9921008; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc42000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1446000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7498000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1068e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10564000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941e00; +} + +static void +Opcode_ae_l8x8_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1542000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2690000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1508000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa940000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1584000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc04000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1408000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10694000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188200; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056c000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e6000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e6000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1544000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2698000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150a000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa941000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1586000; +} + +static void +Opcode_ae_l64_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7a000; +} + +static void +Opcode_ae_l64_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x127e000; +} + +static void +Opcode_ae_l64_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7418000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10670000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168100; +} + +static void +Opcode_ae_l64_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10544000; +} + +static void +Opcode_ae_l64_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6da000; +} + +static void +Opcode_ae_l64_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6da000; +} + +static void +Opcode_ae_l64_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901600; +} + +static void +Opcode_ae_l64_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a000; +} + +static void +Opcode_ae_l64_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x266e000; +} + +static void +Opcode_ae_l64_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fe000; +} + +static void +Opcode_ae_l64_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb980000; +} + +static void +Opcode_ae_l64_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13bc000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaba000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12be000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x741a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10546000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6dc000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6dc000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941600; +} + +static void +Opcode_ae_l64_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137a000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2670000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c0000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fc000; +} + +static void +Opcode_ae_l64_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab8000; +} + +static void +Opcode_ae_l64_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12bc000; +} + +static void +Opcode_ae_l64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19006030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04202; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160200; +} + +static void +Opcode_ae_l64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1061800c; +} + +static void +Opcode_ae_l64_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680070; +} + +static void +Opcode_ae_l64_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680070; +} + +static void +Opcode_ae_l64_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941400; +} + +static void +Opcode_ae_l64_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1378000; +} + +static void +Opcode_ae_l64_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2668000; +} + +static void +Opcode_ae_l64_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133e000; +} + +static void +Opcode_ae_l64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9871003; +} + +static void +Opcode_ae_l64_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000f; +} + +static void +Opcode_ae_l64_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf8000; +} + +static void +Opcode_ae_l64_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12fc000; +} + +static void +Opcode_ae_l64_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19080030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0020b; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10708000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160300; +} + +static void +Opcode_ae_l64_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10620000; +} + +static void +Opcode_ae_l64_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0040; +} + +static void +Opcode_ae_l64_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0040; +} + +static void +Opcode_ae_l64_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981400; +} + +static void +Opcode_ae_l64_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b8000; +} + +static void +Opcode_ae_l64_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x266a000; +} + +static void +Opcode_ae_l64_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137e000; +} + +static void +Opcode_ae_l64_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9971000; +} + +static void +Opcode_ae_l64_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144000c; +} + +static void +Opcode_ae_l64_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3a000; +} + +static void +Opcode_ae_l64_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x123e000; +} + +static void +Opcode_ae_l64_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7416000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1066e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_ae_l64_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10542000; +} + +static void +Opcode_ae_l64_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d8000; +} + +static void +Opcode_ae_l64_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d8000; +} + +static void +Opcode_ae_l64_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1400; +} + +static void +Opcode_ae_l64_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f8000; +} + +static void +Opcode_ae_l64_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x266c000; +} + +static void +Opcode_ae_l64_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13be000; +} + +static void +Opcode_ae_l64_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e100c; +} + +static void +Opcode_ae_l64_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137c000; +} + +static void +Opcode_ae_l64_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xafa000; +} + +static void +Opcode_ae_l64_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12fe000; +} + +static void +Opcode_ae_l64_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x741e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10674000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168200; +} + +static void +Opcode_ae_l64_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054a000; +} + +static void +Opcode_ae_l64_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6de000; +} + +static void +Opcode_ae_l64_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6de000; +} + +static void +Opcode_ae_l64_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1600; +} + +static void +Opcode_ae_l64_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fa000; +} + +static void +Opcode_ae_l64_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2674000; +} + +static void +Opcode_ae_l64_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580000; +} + +static void +Opcode_ae_l64_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c0004; +} + +static void +Opcode_ae_l64_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137e000; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7550000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058c000; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942800; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b8000; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9821008; +} + +static void +Opcode_ae_s16x2m_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7552000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058e000; +} + +static void +Opcode_ae_s16x2m_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982800; +} + +static void +Opcode_ae_s16x2m_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ba000; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x751a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106aa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10586000; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982600; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b2000; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9861000; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x751c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ac000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10588000; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2600; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b4000; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9821004; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x751e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ae000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058a000; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902800; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b6000; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9861004; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7554000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10590000; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2800; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26bc000; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9861008; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7428000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c4000; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f6000; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae100c; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c6000; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f8000; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab80000; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19100030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10710000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10628000; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318000; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f2000; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a70000; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d82e080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10730008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ce002; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380000; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2776000; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996100a; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8340f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718007; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2006; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2984010; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996110f; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8340e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718006; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2002; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2904010; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996100f; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8360e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a200a; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2944010; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996120f; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7426000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106de000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c2000; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f4000; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa100c; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c8000; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26fa000; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc0000; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7434000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ea000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d0000; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3200; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2706000; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc0008; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7436000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d2000; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903400; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2708000; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab8000c; +} + +static void +Opcode_ae_s32x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19104030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10710002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10628004; +} + +static void +Opcode_ae_s32x2_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318010; +} + +static void +Opcode_ae_s32x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943200; +} + +static void +Opcode_ae_s32x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2702000; +} + +static void +Opcode_ae_s32x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a70002; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d86e080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10732008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d2002; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380200; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00600; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277a000; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996100c; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8360f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071800a; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a200e; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80620; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c4010; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996130f; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191a4030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2003; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80630; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2906010; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0120c; +} + +static void +Opcode_ae_s32x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7432000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ce000; +} + +static void +Opcode_ae_s32x2_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308200; +} + +static void +Opcode_ae_s32x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983200; +} + +static void +Opcode_ae_s32x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2704000; +} + +static void +Opcode_ae_s32x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab80008; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x743a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ee000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d6000; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308300; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983400; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270c000; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab81000; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19102030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10710001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10628008; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318200; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26fc000; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a70001; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d86c080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10732000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d0002; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380100; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2778000; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x992100c; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ca000; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308000; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26fe000; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab80004; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7430000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105cc000; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308100; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700000; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc0004; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x755c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ba000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10598000; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982a00; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c8000; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a61000; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x755e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1059a000; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2a00; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ca000; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a21004; +} + +static void +Opcode_ae_s16x4_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19086030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10708003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1062000c; +} + +static void +Opcode_ae_s16x4_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1310210; +} + +static void +Opcode_ae_s16x4_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902a00; +} + +static void +Opcode_ae_s16x4_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c4000; +} + +static void +Opcode_ae_s16x4_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9971003; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d82c080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10730000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104cc002; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318310; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac0480; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2774000; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x992100a; +} + +static void +Opcode_ae_s16x4_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x755a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10596000; +} + +static void +Opcode_ae_s16x4_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330200; +} + +static void +Opcode_ae_s16x4_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942a00; +} + +static void +Opcode_ae_s16x4_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c6000; +} + +static void +Opcode_ae_s16x4_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a21000; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7592000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106be000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1059e000; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330300; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942c00; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ce000; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a21008; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1051e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105fc000; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00000; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2738000; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc1004; +} + +static void +Opcode_ae_s8x8_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74a2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105fe000; +} + +static void +Opcode_ae_s8x8_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a40000; +} + +static void +Opcode_ae_s8x8_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x273a000; +} + +static void +Opcode_ae_s8x8_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb81008; +} + +static void +Opcode_ae_s8x8_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19182030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10630008; +} + +static void +Opcode_ae_s8x8_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983e00; +} + +static void +Opcode_ae_s8x8_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2734000; +} + +static void +Opcode_ae_s8x8_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b70001; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d830080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10734000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d4002; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a40600; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277c000; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x992100e; +} + +static void +Opcode_ae_s8x8_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x747e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1051a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105fa000; +} + +static void +Opcode_ae_s8x8_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3e00; +} + +static void +Opcode_ae_s8x8_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2736000; +} + +static void +Opcode_ae_s8x8_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb81004; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74a6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10526000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10602000; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac0000; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x273e000; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb8100c; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7514000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10580000; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2400; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ac000; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab41008; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7516000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10582000; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902600; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ae000; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab4100c; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74de000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057a000; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902400; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a6000; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab4000c; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7510000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057c000; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942400; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a8000; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab41000; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7512000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057e000; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982400; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26aa000; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab41004; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7518000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10584000; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942600; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b0000; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9821000; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75d6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b2000; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e2000; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a100c; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75d8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b4000; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e4000; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e100c; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ca000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ac000; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26dc000; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e1004; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75d2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106cc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae000; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26de000; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a1008; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75d4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ce000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b0000; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e0000; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e1008; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75da000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b6000; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e6000; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa1000; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x746e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10502000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ea000; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903a00; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2720000; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb80004; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7470000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ec000; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943a00; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2722000; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc0004; +} + +static void +Opcode_ae_s32_l_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7468000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106fa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e4000; +} + +static void +Opcode_ae_s32_l_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943800; +} + +static void +Opcode_ae_s32_l_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x271a000; +} + +static void +Opcode_ae_s32_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc100c; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x746a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106fc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e6000; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983800; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x271c000; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb80000; +} + +static void +Opcode_ae_s32_l_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x746c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106fe000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e8000; +} + +static void +Opcode_ae_s32_l_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3800; +} + +static void +Opcode_ae_s32_l_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x271e000; +} + +static void +Opcode_ae_s32_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc0000; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7472000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10506000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ee000; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983a00; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2724000; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb80008; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7462000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105de000; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983600; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2714000; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab81008; +} + +static void +Opcode_ae_s32_h_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7464000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e0000; +} + +static void +Opcode_ae_s32_h_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3600; +} + +static void +Opcode_ae_s32_h_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2716000; +} + +static void +Opcode_ae_s32_h_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc1008; +} + +static void +Opcode_ae_s32_h_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x743c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d8000; +} + +static void +Opcode_ae_s32_h_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3400; +} + +static void +Opcode_ae_s32_h_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270e000; +} + +static void +Opcode_ae_s32_h_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc1000; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x743e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105da000; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903600; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2710000; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab81004; +} + +static void +Opcode_ae_s32_h_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7460000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105dc000; +} + +static void +Opcode_ae_s32_h_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943600; +} + +static void +Opcode_ae_s32_h_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2712000; +} + +static void +Opcode_ae_s32_h_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc1004; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7466000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e2000; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903800; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2718000; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab8100c; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x759a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a6000; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942e00; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d6000; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a1000; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x759c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a8000; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982e00; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d8000; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e1000; +} + +static void +Opcode_ae_s16_0_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7594000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a0000; +} + +static void +Opcode_ae_s16_0_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982c00; +} + +static void +Opcode_ae_s16_0_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d0000; +} + +static void +Opcode_ae_s16_0_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a61008; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7596000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a2000; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2c00; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d2000; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a2100c; +} + +static void +Opcode_ae_s16_0_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7598000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a4000; +} + +static void +Opcode_ae_s16_0_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902e00; +} + +static void +Opcode_ae_s16_0_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d4000; +} + +static void +Opcode_ae_s16_0_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a6100c; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x759e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa000; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2e00; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26da000; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a1004; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ae000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10536000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060a000; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac0200; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2746000; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9870008; +} + +static void +Opcode_ae_s8_0_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74b0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060c000; +} + +static void +Opcode_ae_s8_0_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00400; +} + +static void +Opcode_ae_s8_0_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2748000; +} + +static void +Opcode_ae_s8_0_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x987000c; +} + +static void +Opcode_ae_s8_0_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74a8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1052a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10604000; +} + +static void +Opcode_ae_s8_0_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00200; +} + +static void +Opcode_ae_s8_0_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2740000; +} + +static void +Opcode_ae_s8_0_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc100c; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74aa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1052e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10606000; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a40200; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2742000; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9870000; +} + +static void +Opcode_ae_s8_0_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ac000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10532000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10608000; +} + +static void +Opcode_ae_s8_0_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80200; +} + +static void +Opcode_ae_s8_0_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2744000; +} + +static void +Opcode_ae_s8_0_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9870004; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74b2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1053a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060e000; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a40400; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x274a000; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9970000; +} + +static void +Opcode_ae_s64_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7476000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f2000; +} + +static void +Opcode_ae_s64_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983c00; +} + +static void +Opcode_ae_s64_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x272c000; +} + +static void +Opcode_ae_s64_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb8000c; +} + +static void +Opcode_ae_s64_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7478000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f4000; +} + +static void +Opcode_ae_s64_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3c00; +} + +static void +Opcode_ae_s64_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x272e000; +} + +static void +Opcode_ae_s64_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc000c; +} + +static void +Opcode_ae_s64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19106030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10710003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1062800c; +} + +static void +Opcode_ae_s64_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3a00; +} + +static void +Opcode_ae_s64_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2726000; +} + +static void +Opcode_ae_s64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a70003; +} + +static void +Opcode_ae_s64_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19180030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10630000; +} + +static void +Opcode_ae_s64_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903c00; +} + +static void +Opcode_ae_s64_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2728000; +} + +static void +Opcode_ae_s64_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b70000; +} + +static void +Opcode_ae_s64_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7474000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0000; +} + +static void +Opcode_ae_s64_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943c00; +} + +static void +Opcode_ae_s64_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x272a000; +} + +static void +Opcode_ae_s64_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc0008; +} + +static void +Opcode_ae_s64_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x747c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10516000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f8000; +} + +static void +Opcode_ae_s64_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943e00; +} + +static void +Opcode_ae_s64_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2732000; +} + +static void +Opcode_ae_s64_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc1000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7422000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106da000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105be000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ee000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa1008; +} + +static void +Opcode_ae_s32m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75dc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b8000; +} + +static void +Opcode_ae_s32m_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903000; +} + +static void +Opcode_ae_s32m_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e8000; +} + +static void +Opcode_ae_s32m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae1000; +} + +static void +Opcode_ae_s32m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75de000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ba000; +} + +static void +Opcode_ae_s32m_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943000; +} + +static void +Opcode_ae_s32m_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ea000; +} + +static void +Opcode_ae_s32m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa1004; +} + +static void +Opcode_ae_s32m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7420000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105bc000; +} + +static void +Opcode_ae_s32m_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983000; +} + +static void +Opcode_ae_s32m_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ec000; +} + +static void +Opcode_ae_s32m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae1004; +} + +static void +Opcode_ae_s32m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7424000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106dc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c0000; +} + +static void +Opcode_ae_s32m_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903200; +} + +static void +Opcode_ae_s32m_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f0000; +} + +static void +Opcode_ae_s32m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae1008; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8f6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10660000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10532000; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941000; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1374000; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2658000; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a000; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3e100c; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1378000; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8c2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1046a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1047e000; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900800; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132c000; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2620000; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a8000; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9c1008; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e6000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x749e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10692000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056a000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1504000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2696000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c8000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa94000c; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1546000; +} + +static void +Opcode_ae_l64_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x741c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10672000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10548000; +} + +static void +Opcode_ae_l64_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981600; +} + +static void +Opcode_ae_l64_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ba000; +} + +static void +Opcode_ae_l64_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2672000; +} + +static void +Opcode_ae_l64_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1540000; +} + +static void +Opcode_ae_l64_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb980004; +} + +static void +Opcode_ae_l64_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133e000; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7438000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ec000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d4000; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943400; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270a000; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc000c; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7590000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106bc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1059c000; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902c00; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26cc000; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a61004; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74a4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10522000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600000; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80000; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x273c000; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc1008; +} + +static void +Opcode_ae_s64_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x747a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10512000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f6000; +} + +static void +Opcode_ae_s64_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903e00; +} + +static void +Opcode_ae_s64_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2730000; +} + +static void +Opcode_ae_s64_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb81000; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19084030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10708002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10620004; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1310010; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26be000; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9971002; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74fe080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057e008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ca002; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318210; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2772000; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9961008; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7556000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10592000; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330000; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c0000; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x982100c; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7558000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10594000; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330100; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c2000; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x986100c; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c500000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe150000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c540000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a40000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1540000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf150000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1940000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1440000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb150000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7340000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900100; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1480000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc150000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19c0000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c0000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd150000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c5c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7840000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1840000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7570000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d480000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1880000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8150000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c380000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1780000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7430000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c3c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c0000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7470000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c480000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7240000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa150000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d380000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d80000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1880000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7830000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc0000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c0000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7870000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc0000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c0000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7860000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900200; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7920000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d340000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d40000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1840000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7960000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c640000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e40000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1940000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7970000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d5c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7850000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d200000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7910000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d500000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7900000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d540000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b40000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1640000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7940000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d580000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b80000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1680000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7810000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d280000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1780000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7820000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_s32x2x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2100000; +} + +static void +Opcode_ae_s32x2x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00000; +} + +static void +Opcode_ae_s32x2x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9800000; +} + +static void +Opcode_ae_s32x2x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2140000; +} + +static void +Opcode_ae_s32x2x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e40000; +} + +static void +Opcode_ae_s32x2x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9840000; +} + +static void +Opcode_ae_s32x2x2_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180000; +} + +static void +Opcode_ae_s32x2x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2040000; +} + +static void +Opcode_ae_s32x2x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d40000; +} + +static void +Opcode_ae_s32x2x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d70000; +} + +static void +Opcode_ae_s32x2x2_ip_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_s32x2x2_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0000; +} + +static void +Opcode_ae_s32x2x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080000; +} + +static void +Opcode_ae_s32x2x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d80000; +} + +static void +Opcode_ae_s32x2x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8800000; +} + +static void +Opcode_ae_s32x2x2_x_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_s32x2x2_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_s32x2x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0000; +} + +static void +Opcode_ae_s32x2x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc0000; +} + +static void +Opcode_ae_s32x2x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8840000; +} + +static void +Opcode_ae_s32x2x2_xp_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_s32x2x2_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_ae_s32x2x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21c0000; +} + +static void +Opcode_ae_s32x2x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec0000; +} + +static void +Opcode_ae_s32x2x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa840000; +} + +static void +Opcode_ae_s32x2x2rng_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c40000; +} + +static void +Opcode_ae_s32x2x2rng_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d60000; +} + +static void +Opcode_ae_s32x2x2rng_ip_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_s32x2x2rng_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80000; +} + +static void +Opcode_ae_s32x2x2rng_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c30000; +} + +static void +Opcode_ae_s32x2x2rng_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc0000; +} + +static void +Opcode_ae_s32x2x2rng_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c70000; +} + +static void +Opcode_ae_s32x2x2rng_xp_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_s32x2x2rng_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00000; +} + +static void +Opcode_ae_s32x2x2rng_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d30000; +} + +static void +Opcode_ae_s16x4x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f40000; +} + +static void +Opcode_ae_s16x4x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b40000; +} + +static void +Opcode_ae_s16x4x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d50000; +} + +static void +Opcode_ae_s16x4x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f80000; +} + +static void +Opcode_ae_s16x4x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b80000; +} + +static void +Opcode_ae_s16x4x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c20000; +} + +static void +Opcode_ae_s16x4x2_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_s16x4x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e80000; +} + +static void +Opcode_ae_s16x4x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a80000; +} + +static void +Opcode_ae_s16x4x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c10000; +} + +static void +Opcode_ae_s16x4x2_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_s16x4x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec0000; +} + +static void +Opcode_ae_s16x4x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac0000; +} + +static void +Opcode_ae_s16x4x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c50000; +} + +static void +Opcode_ae_s16x4x2_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_s16x4x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00000; +} + +static void +Opcode_ae_s16x4x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00000; +} + +static void +Opcode_ae_s16x4x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d10000; +} + +static void +Opcode_ae_s16x4x2_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140000; +} + +static void +Opcode_ae_s16x4x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ae_s16x4x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00000; +} + +static void +Opcode_ae_s16x4x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d20000; +} + +static void +Opcode_ae_s8x8x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2480000; +} + +static void +Opcode_ae_s8x8x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2180000; +} + +static void +Opcode_ae_s8x8x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8900000; +} + +static void +Opcode_ae_s8x8x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24c0000; +} + +static void +Opcode_ae_s8x8x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21c0000; +} + +static void +Opcode_ae_s8x8x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8940000; +} + +static void +Opcode_ae_s8x8x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23c0000; +} + +static void +Opcode_ae_s8x8x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0000; +} + +static void +Opcode_ae_s8x8x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe840000; +} + +static void +Opcode_ae_s8x8x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400000; +} + +static void +Opcode_ae_s8x8x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2100000; +} + +static void +Opcode_ae_s8x8x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf800000; +} + +static void +Opcode_ae_s8x8x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2440000; +} + +static void +Opcode_ae_s8x8x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2140000; +} + +static void +Opcode_ae_s8x8x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf840000; +} + +static void +Opcode_ae_s8x8x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540000; +} + +static void +Opcode_ae_s8x8x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2240000; +} + +static void +Opcode_ae_s8x8x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9940000; +} + +static void +Opcode_ae_s64x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22c0000; +} + +static void +Opcode_ae_s64x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fc0000; +} + +static void +Opcode_ae_s64x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc840000; +} + +static void +Opcode_ae_s64x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300000; +} + +static void +Opcode_ae_s64x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ae_s64x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd800000; +} + +static void +Opcode_ae_s64x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200000; +} + +static void +Opcode_ae_s64x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00000; +} + +static void +Opcode_ae_s64x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb800000; +} + +static void +Opcode_ae_s64x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2240000; +} + +static void +Opcode_ae_s64x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f40000; +} + +static void +Opcode_ae_s64x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb840000; +} + +static void +Opcode_ae_s64x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2280000; +} + +static void +Opcode_ae_s64x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f80000; +} + +static void +Opcode_ae_s64x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc800000; +} + +static void +Opcode_ae_s64x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2380000; +} + +static void +Opcode_ae_s64x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080000; +} + +static void +Opcode_ae_s64x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe800000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c580000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a80000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7800000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d4c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c0000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c0000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9150000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c600000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7930000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d240000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c40000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1740000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7950000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_s32x2x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2180000; +} + +static void +Opcode_ae_s32x2x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e80000; +} + +static void +Opcode_ae_s32x2x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800000; +} + +static void +Opcode_ae_s16x4x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fc0000; +} + +static void +Opcode_ae_s16x4x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc0000; +} + +static void +Opcode_ae_s16x4x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c60000; +} + +static void +Opcode_ae_s8x8x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500000; +} + +static void +Opcode_ae_s8x8x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200000; +} + +static void +Opcode_ae_s8x8x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9900000; +} + +static void +Opcode_ae_s64x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2340000; +} + +static void +Opcode_ae_s64x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2040000; +} + +static void +Opcode_ae_s64x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd840000; +} + +static void +Opcode_ae_s16x4x2rng_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980000; +} + +static void +Opcode_ae_s16x4x2rng_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c00000; +} + +static void +Opcode_ae_s16x4x2rng_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19c0000; +} + +static void +Opcode_ae_s16x4x2rng_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c40000; +} + +static void +Opcode_ae_s16x4x2rng_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00000; +} + +static void +Opcode_ae_s16x4x2rng_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d00000; +} + +static void +Opcode_ae_s16x4x2rng_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a40000; +} + +static void +Opcode_ae_s16x4x2rng_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d40000; +} + +static void +Opcode_ae_zalign64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b48fb4; + slotbuf[1] = 0; +} + +static void +Opcode_ae_zalign64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef70; + slotbuf[1] = 0; +} + +static void +Opcode_ae_zalign64_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069db30; +} + +static void +Opcode_ae_zalign64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab20045; +} + +static void +Opcode_ae_lalign64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f10; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lalign64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10748300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lalign64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680600; +} + +static void +Opcode_ae_lalign64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9839c01; +} + +static void +Opcode_ae_salign64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f20; + slotbuf[1] = 0; +} + +static void +Opcode_ae_salign64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10748700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_salign64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680700; +} + +static void +Opcode_ae_salign64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70ab000; +} + +static void +Opcode_ae_movalign_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b48fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movalign_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef80; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movalign_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687702; +} + +static void +Opcode_ae_movalign_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab20005; +} + +static void +Opcode_ae_la64_pp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b20fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la64_pp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afa0c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la64_pp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf500; +} + +static void +Opcode_ae_la64_pp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685602; +} + +static void +Opcode_ae_la64_pp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08540; +} + +static void +Opcode_ae_la64_pp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09a0e; +} + +static void +Opcode_ae_la64_pp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142e10c; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b50f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af00c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681703; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09a0d; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b40f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074cf0c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681701; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0920d; +} + +static void +Opcode_ae_la24pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b58f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683600; +} + +static void +Opcode_ae_la24pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09e0d; +} + +static void +Opcode_ae_la24neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b48f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681702; +} + +static void +Opcode_ae_la24neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0960d; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b70f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af80c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683603; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0160e; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b60f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af40c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683601; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0120e; +} + +static void +Opcode_ae_la24x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b78f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683700; +} + +static void +Opcode_ae_la24x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0160f; +} + +static void +Opcode_ae_la24x2neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b68f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683602; +} + +static void +Opcode_ae_la24x2neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0120f; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b08fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af20c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683703; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01e0e; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afc0c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683701; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01a0e; +} + +static void +Opcode_ae_la32x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b08fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685600; +} + +static void +Opcode_ae_la32x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01e0f; +} + +static void +Opcode_ae_la32x2neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683702; +} + +static void +Opcode_ae_la32x2neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01a0f; +} + +static void +Opcode_ae_la32x2pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b10fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2pos_pc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af60c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2pos_pc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685601; +} + +static void +Opcode_ae_la32x2pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0920e; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b10f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074cf04; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681602; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09f0e; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074cf00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681600; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09f0c; +} + +static void +Opcode_ae_la16x4pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b18f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681603; +} + +static void +Opcode_ae_la16x4pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09f0f; +} + +static void +Opcode_ae_la16x4neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b08f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681601; +} + +static void +Opcode_ae_la16x4neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09f0d; +} + +static void +Opcode_ae_la16x4pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b20f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4pos_pc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074cf08; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4pos_pc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681700; +} + +static void +Opcode_ae_la16x4pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0120d; +} + +static void +Opcode_ae_la8x8pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b28fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074eb00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685701; +} + +static void +Opcode_ae_la8x8pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09e0f; +} + +static void +Opcode_ae_la8x8neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b20fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afe0c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685603; +} + +static void +Opcode_ae_la8x8neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09a0f; +} + +static void +Opcode_ae_la8x8pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b30fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685702; +} + +static void +Opcode_ae_la8x8pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa820005; +} + +static void +Opcode_ae_la8x8neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b28fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685700; +} + +static void +Opcode_ae_la8x8neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09e0e; +} + +static void +Opcode_ae_la8x8pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b30fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8pos_pc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074eb04; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8pos_pc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685703; +} + +static void +Opcode_ae_la8x8pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa860005; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14230; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416103; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b10fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0ec02; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x686180; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x686180; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f30; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514103; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002430; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151630b; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0920f; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142810c; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14240; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416104; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b18fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0f002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x688180; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x688180; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f40; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514104; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002440; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151640b; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0960e; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142a10c; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14250; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416105; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b18fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0f402; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68a180; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68a180; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f50; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514105; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002450; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151650b; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0960f; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142c10c; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14200; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416100; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b28f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0e002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680180; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680180; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f00; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514100; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002400; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151600b; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0160d; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142210c; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14210; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416101; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b30f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0e402; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x682180; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x682180; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f10; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514101; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002410; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151610b; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01a0d; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142410c; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14220; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416102; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b38f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0e802; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x684180; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x684180; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f20; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514102; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002420; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151620b; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01e0d; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142610c; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14260; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416106; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b38fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0f802; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68c180; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68c180; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f60; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514106; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002460; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151660b; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa920005; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143010c; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14270; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416107; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b38fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0fc02; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68e180; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68e180; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f70; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514107; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002470; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151670b; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa960005; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143210c; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14280; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416108; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b40fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690180; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690180; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f80; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514108; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002480; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151680b; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa20005; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143410c; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b48fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074eb0c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687601; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8a4004; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b40fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074eb08; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687600; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa26004; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193c0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060a004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ee003; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fe000; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fe000; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006f0; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000f; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c40205; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19388030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f0002; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0040; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0040; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00800; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512000; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08205; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193c8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060c004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f0003; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00810; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512001; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48205; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19390030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060e004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0008; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f2002; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08000; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2040; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2040; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00820; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512002; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00305; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400c; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193d8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10612004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f4003; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08040; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f8040; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f8040; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00850; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512005; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48305; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400d; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193d0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10610004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f2003; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4040; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4040; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00830; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512003; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c40305; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19398030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f4002; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6040; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6040; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00840; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512004; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08305; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d838080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10736000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d6002; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea0c0; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea0c0; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00680; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510008; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08208; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d838090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d6003; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec080; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec080; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00690; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510009; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48208; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10736004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d8002; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006a0; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000a; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08209; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10736008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0104; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d8003; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x978300; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee080; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee080; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006b0; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000b; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48209; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514008; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104dc002; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x978340; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0000; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0000; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006e0; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000e; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0820b; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514009; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073600c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104da002; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec0c0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec0c0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006c0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000c; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0820a; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104da003; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee0c0; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee0c0; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006d0; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000d; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c4820a; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193a8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10614004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f6002; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fa040; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fa040; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00880; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512008; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c18201; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193e8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f6003; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fc040; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fc040; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00890; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512009; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c58201; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193b0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10616004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f8002; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008a0; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200a; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c10301; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193f0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10618004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0108; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f8003; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08080; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fe040; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fe040; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008b0; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200b; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c50301; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516000; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1061c004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fc002; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa080c0; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4080; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4080; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008e0; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200e; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c10205; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516001; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193b8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1061a004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fa002; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0080; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0080; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008c0; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200c; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c18301; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193f8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fa003; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2080; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2080; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008d0; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200d; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c58301; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10602004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e8003; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2000; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2000; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48201; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ea002; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4000; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4000; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00301; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10604004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ea003; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x978380; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6000; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6000; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c40301; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400a; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19380030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10608004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ee002; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9783c0; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fc000; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fc000; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00205; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400b; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10606004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ec002; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f8000; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f8000; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08301; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ec003; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fa000; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fa000; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48301; +} + +static void +Opcode_ae_la24_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073e004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e2003; +} + +static void +Opcode_ae_la24_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c4830a; +} + +static void +Opcode_ae_la24_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e4002; +} + +static void +Opcode_ae_la24_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0830b; +} + +static void +Opcode_ae_la24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073e008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e4003; +} + +static void +Opcode_ae_la24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c4830b; +} + +static void +Opcode_ae_la24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e8002; +} + +static void +Opcode_ae_la24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08201; +} + +static void +Opcode_ae_la24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073e00c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e6002; +} + +static void +Opcode_ae_la24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00201; +} + +static void +Opcode_ae_la24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e6003; +} + +static void +Opcode_ae_la24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c40201; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073c004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104dc003; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c4820b; +} + +static void +Opcode_ae_la24x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d870080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104de002; +} + +static void +Opcode_ae_la24x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08308; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d878080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073c008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104de003; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48308; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e2002; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0830a; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d870090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073c00c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e0002; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08309; +} + +static void +Opcode_ae_la24x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d878090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e0003; +} + +static void +Opcode_ae_la24x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48309; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a2004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ee001; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a60; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000d; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f0001; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a70; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000e; +} + +static void +Opcode_ae_sa32x2_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a2008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f2001; +} + +static void +Opcode_ae_sa32x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a80; +} + +static void +Opcode_ae_sa32x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000f; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a200c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f4001; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a90; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010c; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19038010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a6004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fa001; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00ac0; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010f; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f6001; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00aa0; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010d; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f8001; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00ab0; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010e; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10620004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fe002; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008f0; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0000; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fe003; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a00; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0001; +} + +static void +Opcode_ae_sa16x4_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10622004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0001; +} + +static void +Opcode_ae_sa16x4_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a10; +} + +static void +Opcode_ae_sa16x4_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0002; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10624004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c2001; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a20; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0003; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10628004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c8001; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a50; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0102; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10626004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c4001; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a30; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0100; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c6001; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a40; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0101; +} + +static void +Opcode_ae_sa8x8_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19078010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a6008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fc001; +} + +static void +Opcode_ae_sa8x8_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00ad0; +} + +static void +Opcode_ae_sa8x8_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0200; +} + +static void +Opcode_ae_sa8x8_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190b8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fe001; +} + +static void +Opcode_ae_sa8x8_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00ae0; +} + +static void +Opcode_ae_sa8x8_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0201; +} + +static void +Opcode_ae_sa8x8_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190f8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a600c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0000; +} + +static void +Opcode_ae_sa8x8_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00af0; +} + +static void +Opcode_ae_sa8x8_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0202; +} + +static void +Opcode_ae_sa8x8_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19138010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0001; +} + +static void +Opcode_ae_sa8x8_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00c00; +} + +static void +Opcode_ae_sa8x8_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0203; +} + +static void +Opcode_ae_sa8x8_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191f8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2000; +} + +static void +Opcode_ae_sa8x8_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00c30; +} + +static void +Opcode_ae_sa8x8_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0302; +} + +static void +Opcode_ae_sa8x8_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19178010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0002; +} + +static void +Opcode_ae_sa8x8_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00c10; +} + +static void +Opcode_ae_sa8x8_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0300; +} + +static void +Opcode_ae_sa8x8_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191b8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0003; +} + +static void +Opcode_ae_sa8x8_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00c20; +} + +static void +Opcode_ae_sa8x8_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0301; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063a004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e2001; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000b; +} + +static void +Opcode_ae_sa32x2f24_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e4001; +} + +static void +Opcode_ae_sa32x2f24_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0108; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063c004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e6001; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0109; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ec001; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000c; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063e004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e8001; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010a; +} + +static void +Opcode_ae_sa32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ea001; +} + +static void +Opcode_ae_sa32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010b; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530070; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10632004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d6001; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0105; +} + +static void +Opcode_ae_sa24_l_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538070; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d8001; +} + +static void +Opcode_ae_sa24_l_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0106; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10634004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104da001; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0107; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10638004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e0001; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000a; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10636004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104dc001; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0008; +} + +static void +Opcode_ae_sa24_l_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104de001; +} + +static void +Opcode_ae_sa24_l_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0009; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530040; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1062a004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ca001; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0103; +} + +static void +Opcode_ae_sa24x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538040; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104cc001; +} + +static void +Opcode_ae_sa24x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0004; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530050; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1062c004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ce001; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0005; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538060; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10630004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d4001; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0104; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538050; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1062e004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d0001; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0006; +} + +static void +Opcode_ae_sa24x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530060; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d2001; +} + +static void +Opcode_ae_sa24x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0007; +} + +static void +Opcode_ae_addicirc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a00f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addicirc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e04000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addicirc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9838c00; +} + +static void +Opcode_ae_addicirc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1520000; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a12f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6200; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7200; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a5400; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1523200; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a0af00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6100; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7100; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a7000; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1523100; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a02f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6000; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7000; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a5000; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1523000; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18800f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481900; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983c400; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18840f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481b00; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983e400; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18880f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481c00; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9838800; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18940f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481f00; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983e800; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188c0f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481e00; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983a800; +} + +static void +Opcode_ae_s32ra64s_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18900f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481d00; +} + +static void +Opcode_ae_s32ra64s_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983c800; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18780f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481400; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9838000; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18781f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481600; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983a000; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187c0b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481500; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983c000; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187c1f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481a00; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983a400; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187c0f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481700; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983e000; +} + +static void +Opcode_ae_s24ra64s_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187c1b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481800; +} + +static void +Opcode_ae_s24ra64s_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9838400; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0004; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830203; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0008; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830302; +} + +static void +Opcode_ae_s16x4ra32s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4ra32s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4ra32s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0000; +} + +static void +Opcode_ae_s16x4ra32s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830202; +} + +static void +Opcode_ae_addbrba32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74fa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addbrba32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1efa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addbrba32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1be000; +} + +static void +Opcode_ae_addbrba32_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e4000; +} + +static void +Opcode_ae_addbrba32_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b5000; +} + +static void +Opcode_ae_addbrba32_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa02000; +} + +static void +Opcode_ae_addbrba32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9921004; +} + +static void +Opcode_ae_addbrba32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1553000; +} + +static void +Opcode_ae_s32x2_l_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340000; +} + +static void +Opcode_ae_bitswap_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191fd030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bitswap_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0d002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bitswap_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9002; +} + +static void +Opcode_ae_bitswap_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a5000; +} + +static void +Opcode_ae_bitswap_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1597004; +} + +static void +Opcode_ae_mul32js_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32js_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80211420; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32js_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x560020; +} + +static void +Opcode_ae_mul32js_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40b00a1; +} + +static void +Opcode_ae_mul32js_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x510020; +} + +static void +Opcode_ae_mul32js_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c0008; +} + +static void +Opcode_ae_mul32js_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700220; +} + +static void +Opcode_ae_mul32js_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a800; +} + +static void +Opcode_ae_mul32js_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130040; +} + +static void +Opcode_ae_mul32js_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00d0; +} + +static void +Opcode_ae_mul32js_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2c0000; +} + +static void +Opcode_ae_mul32js_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8009e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsub32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsub32s_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000020; +} + +static void +Opcode_ae_addandsub32s_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsub32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9400000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5400000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000026; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsub32js_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsub32js_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_addandsub32js_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; +} + +static void +Opcode_ae_addandsub32js_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_addandsub32js_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_addandsub32js_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsub32js_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8400800; +} + +static void +Opcode_ae_addandsub32js_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5300000; +} + +static void +Opcode_ae_addandsub32js_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000025; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000040; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9400800; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5500000; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000027; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000060; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa400000; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5600000; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000028; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000080; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa400800; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5700000; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000029; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addrng32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007860; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subrng32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rng32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40069c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel16i_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82050000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_sel16i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sel16i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_sel16i_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000a0; +} + +static void +Opcode_ae_sel16i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200000; +} + +static void +Opcode_ae_sel16i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700000; +} + +static void +Opcode_ae_sel16i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_sel16i_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c050000; +} + +static void +Opcode_ae_sel16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7420000; +} + +static void +Opcode_ae_sel16i_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40080002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel16i_n_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_sel16i_n_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_sel16i_n_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00380; +} + +static void +Opcode_ae_shortswap_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401d1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movab4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af007; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movab4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a7010; +} + +static void +Opcode_ae_movab2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af006; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movab2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a7000; +} + +static void +Opcode_ae_movab_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movab_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a3002; +} + +static void +Opcode_ae_movba_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movba_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a3001; +} + +static void +Opcode_ae_movba1x2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movba1x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa820000; +} + +static void +Opcode_ae_movba4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af009; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movba4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa862004; +} + +static void +Opcode_ae_movba2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movba2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa822004; +} + +static void +Opcode_ae_movb2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af016; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movb4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af027; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192c0033; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt16x4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt16x4_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132c400; +} + +static void +Opcode_ae_movt16x4_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x124400; +} + +static void +Opcode_ae_movt16x4_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00221; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9832021; +} + +static void +Opcode_ae_movf16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192c0031; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf16x4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf16x4_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132c000; +} + +static void +Opcode_ae_movf16x4_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x124000; +} + +static void +Opcode_ae_movf16x4_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00201; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830021; +} + +static void +Opcode_ae_movt32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800f1; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt32x2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10720010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt32x2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132a000; +} + +static void +Opcode_ae_movt32x2_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120400; +} + +static void +Opcode_ae_movt32x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00021; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7468011; +} + +static void +Opcode_ae_movf32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf32x2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10720000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf32x2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1328000; +} + +static void +Opcode_ae_movf32x2_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ae_movf32x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7468001; +} + +static void +Opcode_ae_movsara7x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9969e04; +} + +static void +Opcode_ae_movsara7x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1523300; +} + +static void +Opcode_ae_movsard7_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19140026; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movsard7_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c401; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movsard7_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058a0c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movsard7_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069e030; +} + +static void +Opcode_ae_movsard7_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8a6004; +} + +static void +Opcode_ae_movasar_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19036310; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movasar_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c602; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movasar_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e19e0; +} + +static void +Opcode_ae_movda32x2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198000; +} + +static void +Opcode_ae_movda32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a79000; +} + +static void +Opcode_ae_movda32x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154a000; +} + +static void +Opcode_ae_movda32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7528003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00801; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107820e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0300; +} + +static void +Opcode_ae_movda32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640650; +} + +static void +Opcode_ae_movda32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e1080; +} + +static void +Opcode_ae_movda32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516004; +} + +static void +Opcode_ae_movda16x2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640400; +} + +static void +Opcode_ae_movda16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7526003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda16_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0310e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107800e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda16_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0203; +} + +static void +Opcode_ae_movda16_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640640; +} + +static void +Opcode_ae_movda16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e1060; +} + +static void +Opcode_ae_movda16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d6003; +} + +static void +Opcode_ae_movi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d836080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa00c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000c; +} + +static void +Opcode_ae_movi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640600; +} + +static void +Opcode_ae_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a1000; +} + +static void +Opcode_ae_movi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1554004; +} + +static void +Opcode_ae_movi_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa400024; +} + +static void +Opcode_ae_movi_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44100003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74b4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198100; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a71004; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158a000; +} + +static void +Opcode_ae_sat16x4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000a0; +} + +static void +Opcode_ae_sat16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000026; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03904; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98320e0; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40189002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000022; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03804; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107800c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98300e0; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40181002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19080026; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00802; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9836061; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800026; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401c9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19080022; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107800a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9836021; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800025; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401c1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvta32f24s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191ac030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32f24s_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e4b400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32f24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01708; +} + +static void +Opcode_ae_cvta32f24s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191a6030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32f24s_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e43400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32f24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01308; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1053e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640300; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a71000; +} + +static void +Opcode_ae_cvtp24a16x2_lh_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640100; +} + +static void +Opcode_ae_cvtp24a16x2_hl_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640200; +} + +static void +Opcode_ae_cvtp24a16x2_hh_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640000; +} + +static void +Opcode_ae_truncp24q48x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40098c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d180000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580000; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81a0300; +} + +static void +Opcode_ae_trunci32x2f64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c280000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunci32x2f64s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10202000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunci32x2f64s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x804000; +} + +static void +Opcode_ae_trunci32x2f64s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1680000; +} + +static void +Opcode_ae_trunca32f64s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d100000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca32f64s_l_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_trunca32f64s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81a0200; +} + +static void +Opcode_ae_trunci32f64s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c200000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunci32f64s_l_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600000; +} + +static void +Opcode_ae_truncp16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401d9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round32x2f64ssym_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80f0000; +} + +static void +Opcode_ae_round32x2f64ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round32x2f64sasym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280400; +} + +static void +Opcode_ae_round32x2f64sasym_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80e8000; +} + +static void +Opcode_ae_round32x2f64sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round32x2f48ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round32x2f48sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round16x4f32ssym_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800090; +} + +static void +Opcode_ae_round16x4f32ssym_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80e0000; +} + +static void +Opcode_ae_round16x4f32ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round16x4f32sasym_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104b0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_round16x4f32sasym_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800080; +} + +static void +Opcode_ae_round16x4f32sasym_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80d8000; +} + +static void +Opcode_ae_round16x4f32sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round24x2f48ssym_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104b8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_round24x2f48ssym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280000; +} + +static void +Opcode_ae_round24x2f48ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round24x2f48sasym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180e00; +} + +static void +Opcode_ae_round24x2f48sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsp16q48x2sym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsp16q48x2asym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_minabs32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_maxabs32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsp16f24sym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80106862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsp16f24asym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mov_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800f; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mov_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160011; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mov_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1904002e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mov_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03b06; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mov_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80f11801; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mov_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780060; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mov_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c010c; +} + +static void +Opcode_ae_mov_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x568000; +} + +static void +Opcode_ae_mov_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40b80a0; +} + +static void +Opcode_ae_mov_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c0000; +} + +static void +Opcode_ae_mov_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020f; +} + +static void +Opcode_ae_mov_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133ac00; +} + +static void +Opcode_ae_mov_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08100; +} + +static void +Opcode_ae_mov_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x124800; +} + +static void +Opcode_ae_mov_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000020; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mov_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00540; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mov_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000800; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mov_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2880080; +} + +static void +Opcode_ae_mov_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x229860; +} + +static void +Opcode_ae_mov_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25402e0; +} + +static void +Opcode_ae_mov_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00361; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mov_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d15801d; +} + +static void +Opcode_ae_mov_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98340e1; +} + +static void +Opcode_ae_mov_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800024; +} + +static void +Opcode_ae_mov_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401b9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movt64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt64_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1324000; +} + +static void +Opcode_ae_movt64_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c000; +} + +static void +Opcode_ae_movt64_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8b00201; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742a001; +} + +static void +Opcode_ae_movf64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf64_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1320000; +} + +static void +Opcode_ae_movf64_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118000; +} + +static void +Opcode_ae_movf64_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8b00001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7428001; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7524003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0310c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0202; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e1040; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1596003; +} + +static void +Opcode_ae_cvt48a32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48a32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03108; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48a32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0200; +} + +static void +Opcode_ae_cvt48a32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e1000; +} + +static void +Opcode_ae_cvt48a32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516003; +} + +static void +Opcode_ae_cvt64a32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7522003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt64a32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0310a; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt64a32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0201; +} + +static void +Opcode_ae_cvt64a32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e1020; +} + +static void +Opcode_ae_cvt64a32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556003; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1904002a; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03a06; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98340a1; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401b1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19040026; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03906; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9834061; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401a9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19040022; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03806; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9834021; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401a1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900002e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03b04; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98360e0; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40199002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900002a; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03a04; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98340e0; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40191002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat48s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa158000; +} + +static void +Opcode_ae_sat48s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800f6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_satq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800fe462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800ee462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_truncq32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98360a1; +} + +static void +Opcode_ae_truncq32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401e1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_minabs64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_maxabs64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsq32f48sym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80306862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsq32f48asym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80206862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_trunca32q48_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191f4030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca32q48_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0cc01; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929604; +} + +static void +Opcode_ae_movad32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191e4030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e7b400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a006; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_l_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf000; +} + +static void +Opcode_ae_movad32_l_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069a030; +} + +static void +Opcode_ae_movad32_l_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2986010; +} + +static void +Opcode_ae_movad32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09f08; +} + +static void +Opcode_ae_movad32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191be030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e73400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_h_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_h_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10698030; +} + +static void +Opcode_ae_movad32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09b08; +} + +static void +Opcode_ae_movad16_3_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191bc030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_3_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6b400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_3_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_3_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10696030; +} + +static void +Opcode_ae_movad16_3_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09708; +} + +static void +Opcode_ae_movad16_2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191b6030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e63400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071800f; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10694030; +} + +static void +Opcode_ae_movad16_2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09308; +} + +static void +Opcode_ae_movad16_1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191b4030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e5b400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071800e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10692030; +} + +static void +Opcode_ae_movad16_1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01f08; +} + +static void +Opcode_ae_movad16_0_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191ae030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_0_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e53400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_0_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071800b; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_0_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690030; +} + +static void +Opcode_ae_movad16_0_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2946010; +} + +static void +Opcode_ae_movad16_0_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01b08; +} + +static void +Opcode_ae_sra64_32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d818000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sra64_32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1000; +} + +static void +Opcode_ae_pksr32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19340032; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6340c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr32_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x55a000; +} + +static void +Opcode_ae_pksr32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c008c; +} + +static void +Opcode_ae_pksr32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17401e0; +} + +static void +Opcode_ae_pksr32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338000; +} + +static void +Opcode_ae_pksr32_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128008; +} + +static void +Opcode_ae_pksr32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830060; +} + +static void +Opcode_ae_pksr32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa200024; +} + +static void +Opcode_ae_pksr24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19340031; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr24_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6320c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr24_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x559000; +} + +static void +Opcode_ae_pksr24_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c001c; +} + +static void +Opcode_ae_pksr24_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17201e0; +} + +static void +Opcode_ae_pksr24_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132e400; +} + +static void +Opcode_ae_pksr24_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128004; +} + +static void +Opcode_ae_pksr24_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa100024; +} + +static void +Opcode_ae_pksrf32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19340033; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksrf32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6360c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksrf32_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x55b000; +} + +static void +Opcode_ae_pksrf32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c009c; +} + +static void +Opcode_ae_pksrf32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17601e0; +} + +static void +Opcode_ae_pksrf32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338400; +} + +static void +Opcode_ae_pksrf32_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12800c; +} + +static void +Opcode_ae_pksrf32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98300a0; +} + +static void +Opcode_ae_pksrf32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa300024; +} + +static void +Opcode_ae_pksr16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19340030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6300c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr16_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x558000; +} + +static void +Opcode_ae_pksr16_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c000c; +} + +static void +Opcode_ae_pksr16_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17001e0; +} + +static void +Opcode_ae_pksr16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132e000; +} + +static void +Opcode_ae_pksr16_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128000; +} + +static void +Opcode_ae_pksr16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830020; +} + +static void +Opcode_ae_pksr16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000024; +} + +static void +Opcode_ae_trunca16p24s_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a00b; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929204; +} + +static void +Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929c04; +} + +static void +Opcode_ae_add32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480000; +} + +static void +Opcode_ae_add32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89a0c00; +} + +static void +Opcode_ae_add32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8038000; +} + +static void +Opcode_ae_add32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005c60; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18500b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280600; +} + +static void +Opcode_ae_sub32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8110000; +} + +static void +Opcode_ae_sub32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addsub32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18100b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addsub32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080200; +} + +static void +Opcode_ae_addsub32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8070000; +} + +static void +Opcode_ae_addsub32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subadd32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18680b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subadd32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380c00; +} + +static void +Opcode_ae_subadd32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8130000; +} + +static void +Opcode_ae_subadd32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88a0800; +} + +static void +Opcode_ae_add16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8020000; +} + +static void +Opcode_ae_add16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18400f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280800; +} + +static void +Opcode_ae_sub16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80f8000; +} + +static void +Opcode_ae_sub16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ba0800; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8050000; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006860; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addsub32_hl_lh_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18180f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addsub32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8088000; +} + +static void +Opcode_ae_addsub32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f30; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0220; +} + +static void +Opcode_ae_neg32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2d8000; +} + +static void +Opcode_ae_neg32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800b6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f60; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0060; +} + +static void +Opcode_ae_abs32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3e8000; +} + +static void +Opcode_ae_abs32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8003e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg32_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2e8000; +} + +static void +Opcode_ae_neg32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800c6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89a0800; +} + +static void +Opcode_ae_add24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8030000; +} + +static void +Opcode_ae_add24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005860; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18480f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280200; +} + +static void +Opcode_ae_sub24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8108000; +} + +static void +Opcode_ae_sub24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10498000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add32s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480400; +} + +static void +Opcode_ae_add32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002400; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_add32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8aa0800; +} + +static void +Opcode_ae_add32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8040000; +} + +static void +Opcode_ae_add32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18500f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_sub32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280a00; +} + +static void +Opcode_ae_sub32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8118000; +} + +static void +Opcode_ae_sub32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addsub32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18100f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addsub32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080600; +} + +static void +Opcode_ae_addsub32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8078000; +} + +static void +Opcode_ae_addsub32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subadd32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18680f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subadd32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380200; +} + +static void +Opcode_ae_subadd32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8138000; +} + +static void +Opcode_ae_subadd32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004062; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10490000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add16s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_add16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88a0c00; +} + +static void +Opcode_ae_add16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8028000; +} + +static void +Opcode_ae_add16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005460; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18480b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub16s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002c00; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_sub16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280c00; +} + +static void +Opcode_ae_sub16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8100000; +} + +static void +Opcode_ae_sub16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002062; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8aa0c00; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8048000; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006460; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addsub32s_hl_lh_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18180b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addsub32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8080000; +} + +static void +Opcode_ae_addsub32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f20; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg24s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107380f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0200; +} + +static void +Opcode_ae_neg24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2d0000; +} + +static void +Opcode_ae_neg24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800ae462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f50; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs24s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738050; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0040; +} + +static void +Opcode_ae_abs24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3c8000; +} + +static void +Opcode_ae_abs24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80036462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f40; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780040; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003860; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_neg32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0240; +} + +static void +Opcode_ae_neg32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2e0000; +} + +static void +Opcode_ae_neg32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800be462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f70; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107380d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003c00; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_abs32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0080; +} + +static void +Opcode_ae_abs32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa390000; +} + +static void +Opcode_ae_abs32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80046462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f10; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107380b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg16s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003c40; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_neg16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00f0; +} + +static void +Opcode_ae_neg16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2c8000; +} + +static void +Opcode_ae_neg16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800a6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f40; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs16s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80211400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs16s_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x560000; +} + +static void +Opcode_ae_abs16s_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40b00a0; +} + +static void +Opcode_ae_abs16s_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x510000; +} + +static void +Opcode_ae_abs16s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003800; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_abs16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0020; +} + +static void +Opcode_ae_abs16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3a8000; +} + +static void +Opcode_ae_abs16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8002e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f30; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0000; +} + +static void +Opcode_ae_abs16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa388000; +} + +static void +Opcode_ae_abs16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80026462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16js_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc16js_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b001c0; +} + +static void +Opcode_ae_mulc16js_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16js_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc16js_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b001e0; +} + +static void +Opcode_ae_mulc16js_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16js_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac16js_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f003c0; +} + +static void +Opcode_ae_mulac16js_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16js_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac16js_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f003e0; +} + +static void +Opcode_ae_mulac16js_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_lt16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880009; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340014; +} + +static void +Opcode_ae_lt16_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400e0; +} + +static void +Opcode_ae_lt16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2a00; +} + +static void +Opcode_ae_le16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880205; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10749300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1348013; +} + +static void +Opcode_ae_le16_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25403c0; +} + +static void +Opcode_ae_le16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022e00; +} + +static void +Opcode_ae_eq16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880005; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10749100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340013; +} + +static void +Opcode_ae_eq16_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25401c0; +} + +static void +Opcode_ae_eq16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022a00; +} + +static void +Opcode_ae_lt32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10749000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340012; +} + +static void +Opcode_ae_lt32_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400c0; +} + +static void +Opcode_ae_lt32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022800; +} + +static void +Opcode_ae_le32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d88010e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10741100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340011; +} + +static void +Opcode_ae_le32_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25001e0; +} + +static void +Opcode_ae_le32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022400; +} + +static void +Opcode_ae_eq32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d88000e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10741000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340010; +} + +static void +Opcode_ae_eq32_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000e0; +} + +static void +Opcode_ae_eq32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022000; +} + +static void +Opcode_ae_min32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18300f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0110080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104a8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min32_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ae_min32_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40a00a0; +} + +static void +Opcode_ae_min32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180c00; +} + +static void +Opcode_ae_min32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80b0000; +} + +static void +Opcode_ae_min32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_max32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18200f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0110020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max32_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x528000; +} + +static void +Opcode_ae_max32_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40880a0; +} + +static void +Opcode_ae_max32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080e00; +} + +static void +Opcode_ae_max32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8098000; +} + +static void +Opcode_ae_max32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_minmax32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80c8000; +} + +static void +Opcode_ae_minmax32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_minmax16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80c0000; +} + +static void +Opcode_ae_minmax16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_min16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18300b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0110060; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min16_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x538000; +} + +static void +Opcode_ae_min16_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40980a0; +} + +static void +Opcode_ae_min16_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x508000; +} + +static void +Opcode_ae_min16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180800; +} + +static void +Opcode_ae_min16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a8000; +} + +static void +Opcode_ae_min16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_max16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18200b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0110000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max16_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x520000; +} + +static void +Opcode_ae_max16_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40800a0; +} + +static void +Opcode_ae_max16_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_max16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080a00; +} + +static void +Opcode_ae_max16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8090000; +} + +static void +Opcode_ae_max16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ba0c00; +} + +static void +Opcode_ae_add64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8058000; +} + +static void +Opcode_ae_add64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006c60; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18580b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280e00; +} + +static void +Opcode_ae_sub64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8120000; +} + +static void +Opcode_ae_sub64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003062; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f50; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0260; +} + +static void +Opcode_ae_neg64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2f0000; +} + +static void +Opcode_ae_neg64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800ce462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f80; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00a0; +} + +static void +Opcode_ae_abs64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa398000; +} + +static void +Opcode_ae_abs64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8004e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addsq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18080f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addsq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080c00; +} + +static void +Opcode_ae_addsq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8068000; +} + +static void +Opcode_ae_addsq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007c60; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subsq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18700b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subsq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380600; +} + +static void +Opcode_ae_subsq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8140000; +} + +static void +Opcode_ae_subsq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080000; +} + +static void +Opcode_ae_add64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8060000; +} + +static void +Opcode_ae_add64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18580f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380000; +} + +static void +Opcode_ae_sub64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8128000; +} + +static void +Opcode_ae_sub64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_negsq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f80; + slotbuf[1] = 0; +} + +static void +Opcode_ae_negsq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a02c0; +} + +static void +Opcode_ae_negsq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa058000; +} + +static void +Opcode_ae_negsq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800e6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abssq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80fc0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0030; +} + +static void +Opcode_ae_abssq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3b8000; +} + +static void +Opcode_ae_abssq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80066462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f60; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0280; +} + +static void +Opcode_ae_neg64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2f8000; +} + +static void +Opcode_ae_neg64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800d6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00c0; +} + +static void +Opcode_ae_abs64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3b0000; +} + +static void +Opcode_ae_abs64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80056462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_and_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_and_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7428000; +} + +static void +Opcode_ae_and_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40080c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_nand_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nand_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742a000; +} + +static void +Opcode_ae_nand_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40088c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_or_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880040; + slotbuf[1] = 0; +} + +static void +Opcode_ae_or_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742c000; +} + +static void +Opcode_ae_or_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40090c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_xor_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880050; + slotbuf[1] = 0; +} + +static void +Opcode_ae_xor_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742e000; +} + +static void +Opcode_ae_xor_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400a0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slai24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c800000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8424003; +} + +static void +Opcode_ae_slai24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40006003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srli24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c810000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srli24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842400b; +} + +static void +Opcode_ae_srli24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c808000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8424007; +} + +static void +Opcode_ae_srai24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40007403; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19238010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c18205; +} + +static void +Opcode_ae_slas24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42080c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srls24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193b8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srls24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04308; +} + +static void +Opcode_ae_srls24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420e0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sras24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19338010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sras24_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500d01; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sras24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c18305; +} + +static void +Opcode_ae_sras24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420c0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c820000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1204; +} + +static void +Opcode_ae_srai16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42080803; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai16r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c822000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai16r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1304; +} + +static void +Opcode_ae_srai16r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slai32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c804000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842c003; +} + +static void +Opcode_ae_slai32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40006803; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srli32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c812000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srli32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842600b; +} + +static void +Opcode_ae_srli32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000403; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8426007; +} + +static void +Opcode_ae_srai32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40007803; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai32r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842c007; +} + +static void +Opcode_ae_srai32r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40007c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1923c010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1c205; +} + +static void +Opcode_ae_slas32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42090c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srls32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193ba010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srls32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c06308; +} + +static void +Opcode_ae_srls32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420e8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sras32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1933a010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sras32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1a305; +} + +static void +Opcode_ae_sras32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420c8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaa32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d814000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8208; +} + +static void +Opcode_ae_srla32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c828000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1008; +} + +static void +Opcode_ae_sraa32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1200; +} + +static void +Opcode_ae_slai16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c81e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a830c; +} + +static void +Opcode_ae_slai16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000803; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaa16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c816000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8108; +} + +static void +Opcode_ae_sraa16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d81c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9000; +} + +static void +Opcode_ae_sraa16rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d81a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa16rs_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa16rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1100; +} + +static void +Opcode_ae_slai24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c802000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8426003; +} + +static void +Opcode_ae_slai24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40006403; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1923a010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas24s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1a205; +} + +static void +Opcode_ae_slas24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42088c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slai32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c806000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842e003; +} + +static void +Opcode_ae_slai32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40006c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1923e010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1e205; +} + +static void +Opcode_ae_slas32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42098c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaa32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d816000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8308; +} + +static void +Opcode_ae_sraa32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x748c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9200; +} + +static void +Opcode_ae_sraa32rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa32rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1300; +} + +static void +Opcode_ae_slasq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192bc010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c14305; +} + +static void +Opcode_ae_slasq56_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420b0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srlsq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193be010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c06309; +} + +static void +Opcode_ae_srlsq56_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420f8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srasq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1933e010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1e305; +} + +static void +Opcode_ae_srasq56_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420d8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaaq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c818000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaaq56_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a020c; +} + +static void +Opcode_ae_srlaq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c82e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9108; +} + +static void +Opcode_ae_sraaq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x758e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraaq56_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9104; +} + +static void +Opcode_ae_slai64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a0000; +} + +static void +Opcode_ae_slai64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srli64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7408000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srli64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a0008; +} + +static void +Opcode_ae_srli64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40004003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7406000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8004; +} + +static void +Opcode_ae_srai64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4001a003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192b8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c10305; +} + +static void +Opcode_ae_slas64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420a0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srls64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193bc010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srls64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04309; +} + +static void +Opcode_ae_srls64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420f0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sras64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1933c010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sras64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1c305; +} + +static void +Opcode_ae_sras64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420d0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaa64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a000c; +} + +static void +Opcode_ae_srla64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c82a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1108; +} + +static void +Opcode_ae_sraa64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1004; +} + +static void +Opcode_ae_slaisq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7404000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a0004; +} + +static void +Opcode_ae_slaisq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40012003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slassq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192be010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slassq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c16305; +} + +static void +Opcode_ae_slassq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420b8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaasq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c81a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaasq56s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a030c; +} + +static void +Opcode_ae_slai64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7402000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8000; +} + +static void +Opcode_ae_slai64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000a003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192ba010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c12305; +} + +static void +Opcode_ae_slas64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420a8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaa64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x748a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a010c; +} + +static void +Opcode_ae_lt64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt64_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1310000; +} + +static void +Opcode_ae_lt64_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000c0; +} + +static void +Opcode_ae_lt64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6202000; +} + +static void +Opcode_ae_le64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le64_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300010; +} + +static void +Opcode_ae_le64_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000a0; +} + +static void +Opcode_ae_le64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6102000; +} + +static void +Opcode_ae_eq64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq64_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ae_eq64_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500080; +} + +static void +Opcode_ae_eq64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002000; +} + +static void +Opcode_ae_max64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18280b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180000; +} + +static void +Opcode_ae_max64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_min64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18380b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180200; +} + +static void +Opcode_ae_min64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_nsa64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191e6030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsa64_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0c001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsa64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929004; +} + +static void +Opcode_ae_nsaz16_0_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191ec030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz16_0_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0c401; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz16_0_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a007; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz16_0_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929404; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191ee030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0c801; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a00a; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929804; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca004800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200280; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d001a0; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce001c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100140; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72001a0; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002a0; +} + +static void +Opcode_ae_mul32_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00260; +} + +static void +Opcode_ae_mul32_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88d00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8001c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000e0; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71001c0; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32ra_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca001800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32ra_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70001e0; +} + +static void +Opcode_ae_mulf32ra_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8004800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200260; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d00180; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc001c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100120; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7200180; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00280; +} + +static void +Opcode_ae_mul32_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00240; +} + +static void +Opcode_ae_mul32_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ec00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce001800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000c0; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71001a0; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32ra_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8001800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32ra_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70001c0; +} + +static void +Opcode_ae_mulf32ra_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce004400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200240; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c001e0; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca001c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100100; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71001e0; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00260; +} + +static void +Opcode_ae_mul32_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00220; +} + +static void +Opcode_ae_mul32_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8cc00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc001800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000a0; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7100180; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32ra_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce001400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32ra_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70001a0; +} + +static void +Opcode_ae_mulf32ra_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000240; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68001a0; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8bf00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00160; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7900160; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f500040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6003400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000e0; +} + +static void +Opcode_ae_mula32_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f000a0; +} + +static void +Opcode_ae_mula32_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00100; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7600160; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89500040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32ra_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32ra_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7300160; +} + +static void +Opcode_ae_mulaf32ra_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000220; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800180; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89f00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00140; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7800160; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d500040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6003000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000c0; +} + +static void +Opcode_ae_mula32_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00080; +} + +static void +Opcode_ae_mula32_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000e0; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7500160; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32ra_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32ra_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7200160; +} + +static void +Opcode_ae_mulaf32ra_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000200; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67001e0; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8fe00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00120; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7700160; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b500040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6002c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000a0; +} + +static void +Opcode_ae_mula32_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00060; +} + +static void +Opcode_ae_mula32_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000c0; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400160; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32ra_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32ra_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7100160; +} + +static void +Opcode_ae_mulaf32ra_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f300040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14002a0; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400280; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc006800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300240; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200220; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca005800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300080; +} + +static void +Opcode_ae_muls32_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60002a0; +} + +static void +Opcode_ae_muls32_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce006400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13001e0; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61003c0; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32ra_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8006400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32ra_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100360; +} + +static void +Opcode_ae_mulsf32ra_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400280; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400260; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca006800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300220; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200200; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8005800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300060; +} + +static void +Opcode_ae_muls32_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000280; +} + +static void +Opcode_ae_muls32_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc006400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13001c0; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61003a0; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32ra_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32ra_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100340; +} + +static void +Opcode_ae_mulsf32ra_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400260; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400240; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8006800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300200; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61003e0; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce005400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300040; +} + +static void +Opcode_ae_muls32_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000260; +} + +static void +Opcode_ae_muls32_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca006400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13001a0; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100380; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32ra_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32ra_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100320; +} + +static void +Opcode_ae_mulsf32ra_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32u_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32u_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00140; +} + +static void +Opcode_ae_mul32u_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00100; +} + +static void +Opcode_ae_mula32u_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32u_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00380; +} + +static void +Opcode_ae_mula32u_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00340; +} + +static void +Opcode_ae_muls32u_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc004c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32u_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200320; +} + +static void +Opcode_ae_muls32u_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e001c0; +} + +static void +Opcode_ae_mulf16ss_33_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000180; +} + +static void +Opcode_ae_mulf16ss_33_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f00180; +} + +static void +Opcode_ae_mulf16ss_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f001e0; +} + +static void +Opcode_ae_mulf16ss_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_21_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e001e0; +} + +static void +Opcode_ae_mulf16ss_21_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_31_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f001c0; +} + +static void +Opcode_ae_mulf16ss_31_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_30_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f001a0; +} + +static void +Opcode_ae_mulf16ss_30_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e00180; +} + +static void +Opcode_ae_mulf16ss_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_20_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e001c0; +} + +static void +Opcode_ae_mulf16ss_20_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_11_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e001a0; +} + +static void +Opcode_ae_mulf16ss_11_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc001400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100080; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d001e0; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_33_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100300; +} + +static void +Opcode_ae_mulsf16ss_33_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100280; +} + +static void +Opcode_ae_mulsf16ss_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61002e0; +} + +static void +Opcode_ae_mulsf16ss_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_21_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100260; +} + +static void +Opcode_ae_mulsf16ss_21_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_31_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61002c0; +} + +static void +Opcode_ae_mulsf16ss_31_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_30_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61002a0; +} + +static void +Opcode_ae_mulsf16ss_30_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100200; +} + +static void +Opcode_ae_mulsf16ss_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_20_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100240; +} + +static void +Opcode_ae_mulsf16ss_20_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_11_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100220; +} + +static void +Opcode_ae_mulsf16ss_11_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300180; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60003e0; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_33_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000160; +} + +static void +Opcode_ae_mulaf16ss_33_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d300040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c00160; +} + +static void +Opcode_ae_mulaf16ss_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d200040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f00160; +} + +static void +Opcode_ae_mulaf16ss_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b300040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_21_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b00160; +} + +static void +Opcode_ae_mulaf16ss_21_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b200040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_31_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e00160; +} + +static void +Opcode_ae_mulaf16ss_31_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89300040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_30_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d00160; +} + +static void +Opcode_ae_mulaf16ss_30_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f200040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800160; +} + +static void +Opcode_ae_mulaf16ss_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d100040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_20_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a00160; +} + +static void +Opcode_ae_mulaf16ss_20_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89200040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_11_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900160; +} + +static void +Opcode_ae_mulaf16ss_11_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f100040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000a0; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700160; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b100040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul16s_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul16s_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00080; +} + +static void +Opcode_ae_mul16s_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00040; +} + +static void +Opcode_ae_mul16s_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula16s_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula16s_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002c0; +} + +static void +Opcode_ae_mula16s_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00280; +} + +static void +Opcode_ae_mula16s_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ad00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls16s_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc004400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls16s_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200220; +} + +static void +Opcode_ae_muls16s_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c001c0; +} + +static void +Opcode_ae_muls16s_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6006c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002a0; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00260; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6006800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00280; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00240; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6006400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00260; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00220; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14003c0; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64003a0; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14003a0; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400380; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400380; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400360; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500280; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600260; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500260; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600240; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500240; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600220; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600380; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68003a0; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600360; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800380; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600340; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800360; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8002800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100260; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74001c0; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca002800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100280; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74001e0; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8004400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12001e0; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c00180; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca004400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200200; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c001a0; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00280; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60001c0; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002a0; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60001e0; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10001c0; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67001a0; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8be00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10001e0; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67001c0; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8de00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce007000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300360; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200340; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8007400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300380; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200360; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14001e0; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63003c0; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400200; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63003e0; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce003000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11003c0; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77001e0; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc003000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11003a0; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77001c0; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf003a0; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300180; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8da00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00380; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62001e0; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ba00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc007400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13003c0; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62003a0; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca007400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13003a0; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200380; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500320; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600300; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15002e0; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66002c0; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500200; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65003e0; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500340; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600320; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500300; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66002e0; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500220; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600200; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000e0; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67002c0; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000a0; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700280; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600060; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700240; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600100; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67002e0; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000c0; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67002a0; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600080; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700260; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16001e0; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800200; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16001c0; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67003e0; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16001a0; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67003c0; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700020; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900240; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003e0; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900200; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600300; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800320; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700040; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900260; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700000; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900220; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600320; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800340; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00340; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00300; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6007800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00300; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f002c0; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6005c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00220; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f001e0; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00360; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00320; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6007c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00320; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f002e0; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00240; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00200; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000360; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a001c0; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000320; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12600020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a00180; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10002e0; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69001c0; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000380; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a001e0; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000340; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12700020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a001a0; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000300; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69001e0; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc005c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300120; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000380; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca005c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300100; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12600040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000360; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8005c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000e0; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000340; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500060; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500240; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500020; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x169000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12700040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500200; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400340; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400320; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500080; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500260; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500040; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x169000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12600060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500220; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400360; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400340; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8002400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11001e0; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73001c0; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd001e0; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e001a0; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8cb00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca002400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100200; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73001e0; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00200; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e001c0; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8eb00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc002400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100220; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400180; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00220; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e001e0; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88c00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce002400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100240; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74001a0; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00240; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00200; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ac00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100160; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72001c0; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00160; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00120; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100180; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72001e0; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00180; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00140; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11001a0; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7300180; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd001a0; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00160; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ca00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11001c0; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73001a0; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd001c0; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00180; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ea00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00200; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e00160; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89700040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6001c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00020; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e003e0; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ef00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00220; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f00160; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b700040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00040; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00000; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00240; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000180; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d700040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6002400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00060; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00020; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00260; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60001a0; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f700040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6002800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00080; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00040; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00180; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a00160; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89600040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd003a0; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00360; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ee00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf001a0; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b00160; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b600040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6001000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd003c0; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00380; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88f00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf001c0; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c00160; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d600040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6001400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd003e0; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e003a0; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8af00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf001e0; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d00160; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f600040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6001800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e003c0; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8cf00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce006c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13002e0; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62002c0; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce005000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12003c0; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f001e0; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8007000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300300; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62002e0; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8005400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12003e0; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000200; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca007000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300320; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200300; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca005400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000220; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc007000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300340; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200320; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc005400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300020; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000240; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce006800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300260; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200240; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce004c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200340; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e001e0; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8006c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300280; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200260; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8005000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200360; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f00180; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca006c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13002a0; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200280; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca005000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200380; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f001a0; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc006c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13002c0; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62002a0; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc005000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12003a0; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f001c0; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe003e0; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f003a0; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6005800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00200; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f001c0; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe003a0; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00360; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6005000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe001c0; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00180; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10003c0; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b001a0; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10002c0; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69001a0; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10003a0; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b00180; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10002a0; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900180; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300160; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60003c0; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000320; +} + +static void +Opcode_ae_mulsad32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce005c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300140; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60003a0; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000300; +} + +static void +Opcode_ae_mulsad32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000c0; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65002a0; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400320; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400300; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000a0; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500280; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400300; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64002e0; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15003c0; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66003a0; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15001e0; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65003c0; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500380; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600360; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15001a0; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500380; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600140; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700320; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600040; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700220; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600120; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700300; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600020; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700200; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600220; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800240; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67003a0; +} + +static void +Opcode_ae_mulzsad32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600200; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800220; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700380; +} + +static void +Opcode_ae_mulzsad32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700080; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69002a0; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002e0; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800300; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700060; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900280; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002c0; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68002e0; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15003a0; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600380; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500360; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600340; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe003c0; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00380; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00380; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00340; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15001c0; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65003a0; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500180; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500360; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6005400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe001e0; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f001a0; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6004c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe001a0; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00160; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200160; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b00180; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc003400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200020; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78001c0; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8003400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11003e0; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7800180; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8003800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200060; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7900180; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200180; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b001a0; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce003400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200040; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78001e0; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca003400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78001a0; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca003800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200080; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x79001a0; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000140; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66001a0; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8dd00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63001e0; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8bb00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf003c0; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63001a0; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8fa00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000040; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64001a0; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8fb00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000160; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66001c0; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8fd00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000020; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400180; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8db00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf003e0; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63001c0; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89b00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000060; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64001c0; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89c00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400160; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300340; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca007800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400020; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300200; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce007400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13003e0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62003c0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce007800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400060; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300240; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400180; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300360; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc007800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400040; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300220; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8007800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62003e0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8007c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400080; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300260; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulp32x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp32x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12001a0; +} + +static void +Opcode_ae_mulp32x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b001c0; +} + +static void +Opcode_ae_mulp32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce003800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000c0; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x79001e0; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc003800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000a0; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x79001c0; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x2ts_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8003c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x2ts_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000e0; +} + +static void +Opcode_ae_mulfp32x2ts_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a00180; +} + +static void +Opcode_ae_mulp32x2t_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp32x2t_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12001c0; +} + +static void +Opcode_ae_mulp32x2t_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b001e0; +} + +static void +Opcode_ae_mulap32x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap32x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000180; +} + +static void +Opcode_ae_mulap32x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66001e0; +} + +static void +Opcode_ae_mulap32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89e00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000a0; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500180; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8dc00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000080; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64001e0; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8bc00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x2ts_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x2ts_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000c0; +} + +static void +Opcode_ae_mulafp32x2ts_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65001a0; +} + +static void +Opcode_ae_mulap32x2t_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap32x2t_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10001a0; +} + +static void +Opcode_ae_mulap32x2t_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700180; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14001a0; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300380; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc007c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000c0; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63002a0; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca007c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000a0; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300280; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x2ts_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce007c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x2ts_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000e0; +} + +static void +Opcode_ae_mulsfp32x2ts_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63002c0; +} + +static void +Opcode_ae_mulsp32x2t_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp32x2t_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14001c0; +} + +static void +Opcode_ae_mulsp32x2t_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63003a0; +} + +static void +Opcode_ae_mulfp16x4s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100380; +} + +static void +Opcode_ae_mulfp16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77001a0; +} + +static void +Opcode_ae_mulfp16x4ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76001e0; +} + +static void +Opcode_ae_mulc32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc001000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_mulc32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c001e0; +} + +static void +Opcode_ae_mulc32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce002800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11002a0; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75001a0; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8002c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x550000; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11002c0; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75001c0; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc32x16_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8001400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc32x16_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100040; +} + +static void +Opcode_ae_mulc32x16_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d001a0; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc002c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100300; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7600180; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc32x16_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce001000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc32x16_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100020; +} + +static void +Opcode_ae_mulc32x16_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d00180; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca002c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11002e0; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108000; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75001e0; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00020; +} + +static void +Opcode_ae_mulac32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300160; +} + +static void +Opcode_ae_mulac32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002c0; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61001a0; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002e0; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61001c0; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32x16_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac32x16_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00060; +} + +static void +Opcode_ae_mulac32x16_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500160; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00320; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200180; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32x16_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac32x16_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00040; +} + +static void +Opcode_ae_mulac32x16_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400160; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00300; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61001e0; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16x4ss_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16x4ss_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16x4ss_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul16x4s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_mul16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4100000; +} + +static void +Opcode_ae_mul16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4300000; +} + +static void +Opcode_ae_mula16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f00000; +} + +static void +Opcode_ae_muls16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul16x4_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mul16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; +} + +static void +Opcode_ae_mul16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4200000; +} + +static void +Opcode_ae_mula16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e00000; +} + +static void +Opcode_ae_muls16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfd32x2s_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2s_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2s_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2s_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2s_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2s_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulc16s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8001000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc16s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c001a0; +} + +static void +Opcode_ae_mulc16s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca001000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c001c0; +} + +static void +Opcode_ae_mulc16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac16s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100160; +} + +static void +Opcode_ae_mulac16s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200160; +} + +static void +Opcode_ae_mulac16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc16ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc002800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc16ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7500180; +} + +static void +Opcode_ae_mulfc16ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc16ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc16ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100180; +} + +static void +Opcode_ae_mulafc16ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul16js_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80ff0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul16js_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80096462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1910002e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133b000; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98360e1; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa00026; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40069462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19140022; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133b400; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18008000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x746a001; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa00027; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40069862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_conj16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_3_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_3_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_2_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_1_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_1_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_0_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_0_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafq16x2_fir_3_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_3_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_2_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_1_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_1_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_0_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_0_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzaaaafq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaafq32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaafq32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaafq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaafq32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaafq32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaaq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaaq32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaaq32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaaq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaaq32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaaq32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul16_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul16_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd000a0; +} + +static void +Opcode_ae_mul16_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00060; +} + +static void +Opcode_ae_mul16_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula16_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula16_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002e0; +} + +static void +Opcode_ae_mula16_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e002a0; +} + +static void +Opcode_ae_mula16_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8cd00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500120; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500300; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00140; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00100; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_div64d32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0090; +} + +static void +Opcode_ae_div64d32_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3f0000; +} + +static void +Opcode_ae_div64d32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80086462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_div64d32_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738070; + slotbuf[1] = 0; +} + +static void +Opcode_ae_div64d32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00b0; +} + +static void +Opcode_ae_div64d32_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3f8000; +} + +static void +Opcode_ae_div64d32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8008e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sha32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074cb00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl32t_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl16t_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10557000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl16c_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105872c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl16c_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10587ac0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl16c_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105876c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl16c_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d030; +} + +static void +Opcode_ae_vldsht_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afa0b; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a00f; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lb_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8010; +} + +static void +Opcode_ae_lb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a3001; +} + +static void +Opcode_ae_lb_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1521010; +} + +static void +Opcode_ae_lbi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lbi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9001; +} + +static void +Opcode_ae_lbi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a3003; +} + +static void +Opcode_ae_lbi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d6004; +} + +static void +Opcode_ae_lbk_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lbk_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8000; +} + +static void +Opcode_ae_lbki_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10563000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lbs_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071b00e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lbsi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af005; + slotbuf[1] = 0; +} + +static void +Opcode_ae_db_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_db_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929e04; +} + +static void +Opcode_ae_dbi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10748b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dbi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09b0c; +} + +static void +Opcode_ae_db_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dbi_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10748f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_db_ic1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dbi_ic1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ab00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_db_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aed00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dbi_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074af00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_ardecnorm16_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065f000; +} + +static void +Opcode_ae_lbki_dbi_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10430000; +} + +static void +Opcode_ae_lbki_dbi_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10440000; +} + +static void +Opcode_ae_lbki_dbi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10420000; +} + +static void +Opcode_ae_lbi_dbi_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680400; +} + +static void +Opcode_ae_lbi_dbi_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680500; +} + +static void +Opcode_ae_lbi_dbi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680300; +} + +static void +Opcode_ae_lbk_db_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10390000; +} + +static void +Opcode_ae_lbk_db_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103a0000; +} + +static void +Opcode_ae_lbk_db_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10380000; +} + +static void +Opcode_ae_lb_db_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680100; +} + +static void +Opcode_ae_lb_db_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680200; +} + +static void +Opcode_ae_lb_db_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680000; +} + +static void +Opcode_ae_vlel32t_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vlel16t_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055b000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072f000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vles16c_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10587ec0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbf_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105871c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sb_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbi_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10552000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vles16c_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105873c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbf_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105875c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sb_ic1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aeb00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbi_ic1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10553000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vles16c_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d130; +} + +static void +Opcode_ae_sbf_ic1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105879c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sb_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aef00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbi_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10556000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vles16c_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105877c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbf_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10587dc0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40081002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movae_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af209; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movae_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf400; +} + +static void +Opcode_ae_movea_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105870c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movea_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf440; +} + +static void +Opcode_ae_moveep_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00426; +} + +static void +Opcode_ae_moveep_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80406862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sext72_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa480000; +} + +static void +Opcode_ae_add72_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa080000; +} + +static void +Opcode_ae_sub72_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa180000; +} + +static void +Opcode_ae_add72x64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa280000; +} + +static void +Opcode_ae_sub72x64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2a0000; +} + +static void +Opcode_ae_mul32ep_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00100; +} + +static void +Opcode_ae_mul32ep_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32ep_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00280; +} + +static void +Opcode_ae_mula32ep_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32ep_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00100; +} + +static void +Opcode_ae_muls32ep_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00200; +} + +static void +Opcode_ae_mulzaad32ep_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00300; +} + +static void +Opcode_ae_mulzssd32ep_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00000; +} + +static void +Opcode_ae_mulaad32ep_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00180; +} + +static void +Opcode_ae_mulssd32ep_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32usep_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00080; +} + +static void +Opcode_ae_mulaad32usep_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32usep_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00280; +} + +static void +Opcode_ae_mulzaad32usep_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32usep_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00180; +} + +static void +Opcode_ae_mula32usep_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00300; +} + +static void +Opcode_ae_mul32usep_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00200; +} + +static void +Opcode_ae_mula32usep_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00380; +} + +static void +Opcode_ae_srai72_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slai72_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40007003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa380000; +} + +static void +Opcode_ae_sat64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_l16si_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200d; +} + +static void +Opcode_ae_l16ui_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400d; +} + +static void +Opcode_ae_s16i_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600d; +} + +static void +Opcode_ae_lalign128_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14000; +} + +static void +Opcode_ae_lalign128_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416000; +} + +static void +Opcode_ae_lalign128_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lalign128_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lalign128_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680080; +} + +static void +Opcode_ae_lalign128_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680080; +} + +static void +Opcode_ae_lalign128_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00e00; +} + +static void +Opcode_ae_lalign128_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514000; +} + +static void +Opcode_ae_lalign128_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000400; +} + +static void +Opcode_ae_lalign128_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1518000; +} + +static void +Opcode_ae_lalign128_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9839c00; +} + +static void +Opcode_ae_lalign128_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142000c; +} + +static void +Opcode_ae_salign128_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000600; +} + +static void +Opcode_ae_salign128_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a9000; +} + +static void +Opcode_ae_la128_pp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08140; +} + +static void +Opcode_ae_la128_pp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142010c; +} + +static void +Opcode_ae_sa128pos_fp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002490; +} + +static void +Opcode_ae_sa128pos_fp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa826004; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc12000; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1414008; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193a0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00860; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512006; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2804010; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516008; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c10201; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400e; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc12010; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1414009; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193e0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03802; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00870; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512007; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2806010; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516009; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c50201; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400f; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00080; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300008; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19068010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000d; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000b0; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000b; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000b0; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000b; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8818101; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000b; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00020; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300002; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19048010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00007; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600080; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600080; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700030; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400003; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400030; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400003; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810101; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400003; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00050; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300005; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19058010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000f; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640040; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640040; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700070; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400007; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400070; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400007; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810103; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400007; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00060; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300006; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19020010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640080; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640080; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700080; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400008; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400080; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400008; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8818000; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400008; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00030; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300003; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19010010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000c0; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000c0; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700040; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400004; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400040; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400004; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810002; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400004; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00070; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300007; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19028010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00009; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400c0; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400c0; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700090; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400009; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400090; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400009; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8818001; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400009; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00010; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300001; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19008010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00006; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600040; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600040; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700010; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400001; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400010; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400001; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810001; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400001; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00040; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300004; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19018010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700050; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400005; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400050; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400005; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810003; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400005; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19060010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00005; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000a0; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000a; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000a0; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000a; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8818100; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000a; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19040010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700020; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400002; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400020; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400002; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810100; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400002; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19050010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700060; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400006; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400060; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400006; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810102; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400006; +} + +static void +Opcode_ae_sa8x8x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800070; +} + +static void +Opcode_ae_sa8x8x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500070; +} + +static void +Opcode_ae_sa8x8x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830301; +} + +static void +Opcode_ae_sa16x4x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000f0; +} + +static void +Opcode_ae_sa16x4x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000f0; +} + +static void +Opcode_ae_sa16x4x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820301; +} + +static void +Opcode_ae_sa32x2x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800030; +} + +static void +Opcode_ae_sa32x2x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500030; +} + +static void +Opcode_ae_sa32x2x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820303; +} + +static void +Opcode_ae_sa8x8x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800040; +} + +static void +Opcode_ae_sa8x8x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500040; +} + +static void +Opcode_ae_sa8x8x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830200; +} + +static void +Opcode_ae_sa16x4x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000c0; +} + +static void +Opcode_ae_sa16x4x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000c0; +} + +static void +Opcode_ae_sa16x4x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820200; +} + +static void +Opcode_ae_sa32x2x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800000; +} + +static void +Opcode_ae_sa32x2x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500000; +} + +static void +Opcode_ae_sa32x2x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820202; +} + +static void +Opcode_ae_sa8x8x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800050; +} + +static void +Opcode_ae_sa8x8x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500050; +} + +static void +Opcode_ae_sa8x8x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830201; +} + +static void +Opcode_ae_sa16x4x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000d0; +} + +static void +Opcode_ae_sa16x4x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000d0; +} + +static void +Opcode_ae_sa16x4x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820201; +} + +static void +Opcode_ae_sa32x2x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800010; +} + +static void +Opcode_ae_sa32x2x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500010; +} + +static void +Opcode_ae_sa32x2x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820203; +} + +static void +Opcode_ae_sa8x8x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800060; +} + +static void +Opcode_ae_sa8x8x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500060; +} + +static void +Opcode_ae_sa8x8x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830300; +} + +static void +Opcode_ae_sa16x4x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000e0; +} + +static void +Opcode_ae_sa16x4x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000e0; +} + +static void +Opcode_ae_sa16x4x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820300; +} + +static void +Opcode_ae_sa32x2x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800020; +} + +static void +Opcode_ae_sa32x2x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500020; +} + +static void +Opcode_ae_sa32x2x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820302; +} + +static void +Opcode_ae_abs8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00e0; +} + +static void +Opcode_ae_abs8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs8s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003820; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_abs8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0010; +} + +static void +Opcode_ae_abs8s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8005e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f70; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg8s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003c60; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_neg8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a02a0; +} + +static void +Opcode_ae_neg8s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800de462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080400; +} + +static void +Opcode_ae_sub8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18600b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380400; +} + +static void +Opcode_ae_max8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18280f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0110040; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max8_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_ae_max8_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40900a0; +} + +static void +Opcode_ae_max8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180400; +} + +static void +Opcode_ae_max8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a0000; +} + +static void +Opcode_ae_min8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18380f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc01100a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min8_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x548000; +} + +static void +Opcode_ae_min8_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40a80a0; +} + +static void +Opcode_ae_min8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180600; +} + +static void +Opcode_ae_min8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80b8000; +} + +static void +Opcode_ae_add8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18080b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add8s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002800; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_add8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080800; +} + +static void +Opcode_ae_add8s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007460; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18600f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub8s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003400; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_sub8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380800; +} + +static void +Opcode_ae_sub8s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_le8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18740f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380e00; +} + +static void +Opcode_ae_lt8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18780b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380b00; +} + +static void +Opcode_ae_eq8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18700f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380a00; +} + +static void +Opcode_ae_satu16x4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000c0; +} + +static void +Opcode_ae_satu16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000062; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_satu32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001062; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat8x8x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_satu8x8x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat8x4x32_l_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000b0; +} + +static void +Opcode_ae_sat8x4x32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_satu8x4x32_l_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000d0; +} + +static void +Opcode_ae_satu8x4x32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round8x8f16ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round8x8f16sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round8x4f32ssym_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round8x4f32sasym_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movda8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x752a003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda8_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00803; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105820c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda8_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0301; +} + +static void +Opcode_ae_movda8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640660; +} + +static void +Opcode_ae_movda8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e10a0; +} + +static void +Opcode_ae_movda8_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556004; +} + +static void +Opcode_ae_movad8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d832080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad8_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10734008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690080; +} + +static void +Opcode_ae_movad8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01208; +} + +static void +Opcode_ae_movdx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movdx2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movdx2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10100000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movdx2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10100000; +} + +static void +Opcode_ae_movdx2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_movdx2_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_movdx2_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_movdx2_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_movdx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_movdx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; +} + +static void +Opcode_ae_movdx2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000100; +} + +static void +Opcode_ae_movdx2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsub32j_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsub32j_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_addandsub32j_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsub32j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8400000; +} + +static void +Opcode_ae_addandsub32j_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5200000; +} + +static void +Opcode_ae_addandsub32j_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000024; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addw8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addw8_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_addw8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc400000; +} + +static void +Opcode_ae_addw8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002e; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addw16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addw16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_addw16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb400000; +} + +static void +Opcode_ae_addw16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002c; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addw32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addw32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ae_addw32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb400800; +} + +static void +Opcode_ae_addw32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002d; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subw8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subw8_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_subw8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe400000; +} + +static void +Opcode_ae_subw8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000032; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subw16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subw16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_ae_subw16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd400000; +} + +static void +Opcode_ae_subw16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000030; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subw32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subw32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_ae_subw32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd400800; +} + +static void +Opcode_ae_subw32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000031; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_accw8_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_accw8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000022; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_accw16_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_accw16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_accw32_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_accw32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000021; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addw8u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addw8u_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_ae_addw8u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc400800; +} + +static void +Opcode_ae_addw8u_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002f; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subw8u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subw8u_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_subw8u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe400800; +} + +static void +Opcode_ae_subw8u_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000033; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_accw8u_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_accw8u_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000023; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x2s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c00000; +} + +static void +Opcode_ae_mulfp32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x2s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4700000; +} + +static void +Opcode_ae_mulafp32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x2s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000000; +} + +static void +Opcode_ae_mulsfp32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x2s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d00000; +} + +static void +Opcode_ae_mulfp32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x2s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4800000; +} + +static void +Opcode_ae_mulafp32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x2s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100000; +} + +static void +Opcode_ae_mulsfp32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulasf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulssf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulasf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulasf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulasf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulssf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulssf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulssf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mul32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd000c0; +} + +static void +Opcode_ae_mul32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00080; +} + +static void +Opcode_ae_mul32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8aa00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00300; +} + +static void +Opcode_ae_mula32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e002c0; +} + +static void +Opcode_ae_mula32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ed00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc004800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12002a0; +} + +static void +Opcode_ae_muls32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d001c0; +} + +static void +Opcode_ae_muls32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00120; +} + +static void +Opcode_ae_mul32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e000e0; +} + +static void +Opcode_ae_mul32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00360; +} + +static void +Opcode_ae_mula32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00320; +} + +static void +Opcode_ae_mula32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ce00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca004c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200300; +} + +static void +Opcode_ae_muls32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e001a0; +} + +static void +Opcode_ae_muls32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32s_hl_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32s_hl_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd000e0; +} + +static void +Opcode_ae_mul32s_hl_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e000a0; +} + +static void +Opcode_ae_mul32s_hl_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ab00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32s_hl_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32s_hl_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00320; +} + +static void +Opcode_ae_mula32s_hl_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e002e0; +} + +static void +Opcode_ae_mula32s_hl_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88e00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32s_hl_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce004800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32s_hl_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12002c0; +} + +static void +Opcode_ae_muls32s_hl_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d001e0; +} + +static void +Opcode_ae_muls32s_hl_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00100; +} + +static void +Opcode_ae_mul32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e000c0; +} + +static void +Opcode_ae_mul32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00340; +} + +static void +Opcode_ae_mula32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00300; +} + +static void +Opcode_ae_mula32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ae00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8004c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12002e0; +} + +static void +Opcode_ae_muls32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e00180; +} + +static void +Opcode_ae_muls32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500140; +} + +static void +Opcode_ae_mulzaad32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500320; +} + +static void +Opcode_ae_mulzaad32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15003e0; +} + +static void +Opcode_ae_mulzasd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66003c0; +} + +static void +Opcode_ae_mulzasd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsad32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsad32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600160; +} + +static void +Opcode_ae_mulzsad32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700340; +} + +static void +Opcode_ae_mulzsad32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600280; +} + +static void +Opcode_ae_mulzssd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68002a0; +} + +static void +Opcode_ae_mulzssd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6004400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00160; +} + +static void +Opcode_ae_mulaad32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00120; +} + +static void +Opcode_ae_mulaad32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000260; +} + +static void +Opcode_ae_mulasd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68001c0; +} + +static void +Opcode_ae_mulasd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8df00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsad32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc005800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsad32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000a0; +} + +static void +Opcode_ae_mulsad32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60002c0; +} + +static void +Opcode_ae_mulsad32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14002c0; +} + +static void +Opcode_ae_mulssd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64002a0; +} + +static void +Opcode_ae_mulssd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500160; +} + +static void +Opcode_ae_mulzaad32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500340; +} + +static void +Opcode_ae_mulzaad32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600000; +} + +static void +Opcode_ae_mulzasd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66003e0; +} + +static void +Opcode_ae_mulzasd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsad32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsad32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600180; +} + +static void +Opcode_ae_mulzsad32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700360; +} + +static void +Opcode_ae_mulzsad32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002a0; +} + +static void +Opcode_ae_mulzssd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68002c0; +} + +static void +Opcode_ae_mulzssd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6004800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00180; +} + +static void +Opcode_ae_mulaad32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00140; +} + +static void +Opcode_ae_mulaad32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000280; +} + +static void +Opcode_ae_mulasd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68001e0; +} + +static void +Opcode_ae_mulasd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ff00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsad32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce005800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsad32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000c0; +} + +static void +Opcode_ae_mulsad32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60002e0; +} + +static void +Opcode_ae_mulsad32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14002e0; +} + +static void +Opcode_ae_mulssd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64002c0; +} + +static void +Opcode_ae_mulssd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x2ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x2ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x2ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x2ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x2ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x2ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulf32x2r_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x2r_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x2r_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x2r_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x2r_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x2r_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj32ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8003000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfcj32ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100340; +} + +static void +Opcode_ae_mulfcj32ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76001c0; +} + +static void +Opcode_ae_mulfcj32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj32ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafcj32ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00360; +} + +static void +Opcode_ae_mulafcj32ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62001c0; +} + +static void +Opcode_ae_mulafcj32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89a00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf2p32x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2p32x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2p32x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulaf2p32x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulaf2p32x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulaf2p32x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulsf2p32x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulsf2p32x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulsf2p32x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulf2p32x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2p32x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2p32x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulaf2p32x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaf2p32x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaf2p32x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulsf2p32x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsf2p32x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsf2p32x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulp32x2s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul2p32x4s_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4s_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula2p32x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2p32x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2p32x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_muls2p32x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_muls2p32x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_muls2p32x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mul2p32x4t_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4t_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4t_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula2p32x4t_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2p32x4t_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2p32x4t_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_muls2p32x4t_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_muls2p32x4t_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_muls2p32x4t_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulzaa32x2_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzss32x2_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaa32x2_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss32x2_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulcj32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca001400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulcj32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100060; +} + +static void +Opcode_ae_mulcj32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d001c0; +} + +static void +Opcode_ae_mulcj32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulacj32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulacj32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00080; +} + +static void +Opcode_ae_mulacj32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600160; +} + +static void +Opcode_ae_mulacj32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89100040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc32ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc32ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_mulfc32ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4900000; +} + +static void +Opcode_ae_mulfc32ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc32ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc32ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_mulafc32ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4400000; +} + +static void +Opcode_ae_mulafc32ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulcj32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulacj32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf2d32x2ws_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2d32x2ws_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2d32x2ws_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulzaaaa2q16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaaa2q16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaaa2q16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulaaaa2q16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaaa2q16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaaa2q16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulp16s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca003c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp16s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200100; +} + +static void +Opcode_ae_mulp16s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a001a0; +} + +static void +Opcode_ae_mulp16s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulap16s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap16s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000e0; +} + +static void +Opcode_ae_mulap16s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65001c0; +} + +static void +Opcode_ae_mulap16s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8fc00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsp16s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp16s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400100; +} + +static void +Opcode_ae_mulsp16s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63002e0; +} + +static void +Opcode_ae_mulsp16s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc003c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200120; +} + +static void +Opcode_ae_mulp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a001c0; +} + +static void +Opcode_ae_mulp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulap16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000100; +} + +static void +Opcode_ae_mulap16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65001e0; +} + +static void +Opcode_ae_mulap16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89d00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400120; +} + +static void +Opcode_ae_mulsp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300300; +} + +static void +Opcode_ae_mulsp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul2c16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula2c16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj16ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce002c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfcj16ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100320; +} + +static void +Opcode_ae_mulfcj16ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76001a0; +} + +static void +Opcode_ae_mulfcj16ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj16ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafcj16ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00340; +} + +static void +Opcode_ae_mulafcj16ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62001a0; +} + +static void +Opcode_ae_mulafcj16ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc16s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10003e0; +} + +static void +Opcode_ae_mulc16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c00180; +} + +static void +Opcode_ae_mulc16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac16s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_mulac16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000160; +} + +static void +Opcode_ae_mulac16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp16x4rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca003000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp16x4rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100360; +} + +static void +Opcode_ae_mulfp16x4rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7700180; +} + +static void +Opcode_ae_mulfp16x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfd16x16x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfd16x16x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfd16x16x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulp16x16x4s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce003c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp16x16x4s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200140; +} + +static void +Opcode_ae_mulp16x16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a001e0; +} + +static void +Opcode_ae_mulp16x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulap16x16x4s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap16x16x4s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000120; +} + +static void +Opcode_ae_mulap16x16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600180; +} + +static void +Opcode_ae_mulap16x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8bd00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsp16x16x4s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp16x16x4s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400140; +} + +static void +Opcode_ae_mulsp16x16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300320; +} + +static void +Opcode_ae_mulsp16x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000e0; +} + +static void +Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65002c0; +} + +static void +Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500100; +} + +static void +Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65002e0; +} + +static void +Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600240; +} + +static void +Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800260; +} + +static void +Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600260; +} + +static void +Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800280; +} + +static void +Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6003800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00100; +} + +static void +Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f000c0; +} + +static void +Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6003c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00120; +} + +static void +Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f000e0; +} + +static void +Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss2d16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulss2d16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400220; +} + +static void +Opcode_ae_mulss2d16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400200; +} + +static void +Opcode_ae_mulss2d16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss2d16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulss2d16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400240; +} + +static void +Opcode_ae_mulss2d16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400220; +} + +static void +Opcode_ae_mulss2d16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15002a0; +} + +static void +Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600280; +} + +static void +Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15002c0; +} + +static void +Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66002a0; +} + +static void +Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003a0; +} + +static void +Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68003c0; +} + +static void +Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003c0; +} + +static void +Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68003e0; +} + +static void +Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6007000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002c0; +} + +static void +Opcode_ae_mulaafd16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00280; +} + +static void +Opcode_ae_mulaafd16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6007400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002e0; +} + +static void +Opcode_ae_mulaafd16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f002a0; +} + +static void +Opcode_ae_mulaafd16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14003e0; +} + +static void +Opcode_ae_mulssfd16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64003c0; +} + +static void +Opcode_ae_mulssfd16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_mulssfd16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64003e0; +} + +static void +Opcode_ae_mulssfd16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfd16x16x4ws_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulfd16x16x4ws_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulfd16x16x4ws_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulzaaaa2q16x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaa2q16x8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaa2q16x8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaa2q16x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaaaa2q16x8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaaaa2q16x8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzaaaa2q8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaa2q8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaa2q8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaa2q8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaa2q8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaa2q8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulpc32x16x2_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulpc32x16x2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulpc32x16x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulapc32x16x2_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulapc32x16x2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulapc32x16x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfp32x16_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc32x16w_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a00000; +} + +static void +Opcode_ae_mulfc32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc32x16w_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4500000; +} + +static void +Opcode_ae_mulafc32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc32x16w_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b00000; +} + +static void +Opcode_ae_mulfc32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc32x16w_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4600000; +} + +static void +Opcode_ae_mulafc32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf2p32x16x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulsf2p32x16x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf2p32x16x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulsf2p32x16x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf2p32x16x4s_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4s_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4s_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4s_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulsf2p32x16x4s_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4s_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfpc32x16x2ras_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mulfpc32x16x2ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfpc32x16x2ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfpc32x16x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpc32x16x2ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpc32x16x2ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpc32x16x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfpcj32x16x2ras_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ae_mulfpcj32x16x2ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfpcj32x16x2ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfpcj32x16x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpcj32x16x2ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpcj32x16x2ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpcj32x16x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzaaaa2q32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaaa2q32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaaa2q32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulaaaa2q32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaaa2q32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaaa2q32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mul2q32x16_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2q32x16_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2q32x16_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula2q32x16_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2q32x16_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2q32x16_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mul2q32x16_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mul2q32x16_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mul2q32x16_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2q32x16_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mula2q32x16_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mula2q32x16_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_srai8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d824080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00208; +} + +static void +Opcode_ae_srai8r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d826080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai8r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04208; +} + +static void +Opcode_ae_srli8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d828080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srli8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00308; +} + +static void +Opcode_ae_slai8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d820080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9308; +} + +static void +Opcode_ae_slai8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d822080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83ad308; +} + +static void +Opcode_ae_slaa8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a800c; +} + +static void +Opcode_ae_srla8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c82c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9008; +} + +static void +Opcode_ae_slaa8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x758a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a810c; +} + +static void +Opcode_ae_sraa8rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa8rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1104; +} + +static void +Opcode_ae_sraa8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x758c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9004; +} + +static void +Opcode_ae_srli16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c830000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srli16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1208; +} + +static void +Opcode_ae_slai16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c81c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a820c; +} + +static void +Opcode_ae_slaa16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c814000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8008; +} + +static void +Opcode_ae_srla16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c826000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9304; +} + +static void +Opcode_ae_srai16sym_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c824000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai16sym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9204; +} + +static void +Opcode_ae_sraa16syms_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d81e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa16syms_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9100; +} + +static void +Opcode_ae_srai32sym_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai32sym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842e007; +} + +static void +Opcode_ae_sraa32syms_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x748e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa32syms_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9300; +} + +static void +Opcode_ae_srav16rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srav16rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00000; +} + +static void +Opcode_ae_srav32rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srav32rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c02000; +} + +static void +Opcode_ae_cvti32x4f8_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a014000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8424002; +} + +static void +Opcode_ae_cvti32x4f8_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a016000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8426002; +} + +static void +Opcode_ae_cvti32x4f8s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a008000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8420001; +} + +static void +Opcode_ae_cvti32x4f8s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8422001; +} + +static void +Opcode_ae_cvta32x4f8_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a034000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8120200; +} + +static void +Opcode_ae_cvta32x4f8_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a036000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8120300; +} + +static void +Opcode_ae_cvta32x4f8s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a028000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82a0000; +} + +static void +Opcode_ae_cvta32x4f8s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a02a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82a0100; +} + +static void +Opcode_ae_cvti32x4f8u_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a010000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8u_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8420002; +} + +static void +Opcode_ae_cvti32x4f8u_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a012000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8u_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8422002; +} + +static void +Opcode_ae_cvti32x4f8us_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8us_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8424001; +} + +static void +Opcode_ae_cvti32x4f8us_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8us_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8426001; +} + +static void +Opcode_ae_cvta32x4f8u_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a030000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8u_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8120000; +} + +static void +Opcode_ae_cvta32x4f8u_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a032000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8u_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8120100; +} + +static void +Opcode_ae_cvta32x4f8us_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a02c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8us_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82a0200; +} + +static void +Opcode_ae_cvta32x4f8us_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a02e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8us_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82a0300; +} + +static void +Opcode_ae_cvti32x4f16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8420000; +} + +static void +Opcode_ae_cvti32x4f16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8422000; +} + +static void +Opcode_ae_cvta32x4f16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a020000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a0000; +} + +static void +Opcode_ae_cvta32x4f16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a022000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a0100; +} + +static void +Opcode_ae_cvti32x4f16u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f16u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8424000; +} + +static void +Opcode_ae_cvti32x4f16us_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f16us_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8426000; +} + +static void +Opcode_ae_cvta32x4f16u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a024000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f16u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a0200; +} + +static void +Opcode_ae_cvta32x4f16us_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a026000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f16us_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a0300; +} + +static void +Opcode_ae_cvti16x4x2f8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a038000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti16x4x2f8_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500200; +} + +static void +Opcode_ae_cvti16x4x2f8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8320000; +} + +static void +Opcode_ae_cvti16x4x2f8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a03a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti16x4x2f8s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_cvti16x4x2f8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8320100; +} + +static void +Opcode_ae_cvta16x4x2f8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b018000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta16x4x2f8_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_cvta16x4x2f8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220000; +} + +static void +Opcode_ae_cvta16x4x2f8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b01a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta16x4x2f8s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400200; +} + +static void +Opcode_ae_cvta16x4x2f8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220100; +} + +static void +Opcode_ae_cvti16x4x2f8u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a03c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti16x4x2f8u_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600200; +} + +static void +Opcode_ae_cvti16x4x2f8u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8320200; +} + +static void +Opcode_ae_cvti16x4x2f8us_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a03e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti16x4x2f8us_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8320300; +} + +static void +Opcode_ae_cvta16x4x2f8u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b01c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta16x4x2f8u_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_cvta16x4x2f8u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220200; +} + +static void +Opcode_ae_cvta16x4x2f8us_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b01e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta16x4x2f8us_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220300; +} + +static void +Opcode_ae_sel8x8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0108000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sel8x8_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_ae_sel8x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel8x8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000440; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel8x8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a00000; +} + +static void +Opcode_ae_sel8x8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000036; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl8x8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc01100e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_shfl8x8_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900400; +} + +static void +Opcode_ae_shfl8x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a08000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl8x8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000c40; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl8x8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8200400; +} + +static void +Opcode_ae_shfl8x8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000063; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel16x4_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_sel16x4_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000020; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_sel16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0100000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sel16x4_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_ae_sel16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel16x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel16x4_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sel16x4_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000020; +} + +static void +Opcode_ae_sel16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5900000; +} + +static void +Opcode_ae_sel16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000035; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc01100c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_shfl16x4_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900000; +} + +static void +Opcode_ae_shfl16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl16x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c40; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8200000; +} + +static void +Opcode_ae_shfl16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000063; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel8x8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80008000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dsel8x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel8x8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000400; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel8x8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ae_dsel8x8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000001; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel16x4_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_dsel16x4_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_dsel16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dsel16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel16x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel16x4_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dsel16x4_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000000; +} + +static void +Opcode_ae_dsel16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_dsel16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel8x8i_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sel8x8i_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_sel8x8i_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel8x8i_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000840; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel8x8i_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b00000; +} + +static void +Opcode_ae_sel8x8i_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000037; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rmax8x8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63d0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_rmax8x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b004e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rmax8x8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac58000; +} + +static void +Opcode_ae_rmin8x8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63e0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_rmin8x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00520; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rmin8x8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae58000; +} + +static void +Opcode_ae_rmax16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63c8c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_rmax16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b004c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rmax16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab58000; +} + +static void +Opcode_ae_rmin16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63d8c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_rmin16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00500; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rmin16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad58000; +} + +static void +Opcode_ae_sort16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e048000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sort16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sort16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa038000; +} + +static void +Opcode_ae_radd8x8_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63a0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radd8x8_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00420; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radd8x8_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa658000; +} + +static void +Opcode_ae_radda8x8_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63b8c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radda8x8_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00480; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radda8x8_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa958000; +} + +static void +Opcode_ae_radd8x8_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63a8c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radd8x8_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00440; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radd8x8_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa758000; +} + +static void +Opcode_ae_radda8x8_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63c0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radda8x8_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b004a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radda8x8_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa58000; +} + +static void +Opcode_ae_radd16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6398c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radd16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00400; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radd16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa558000; +} + +static void +Opcode_ae_radda16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63b0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radda16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00460; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radda16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa858000; +} + +static void +Opcode_ae_bmax8x8_h_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14004400; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmax8x8_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_bmax8x8_l_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1288000; +} + +static void +Opcode_ae_bmax8x8_l_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14006000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmax8x8_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_bmin8x8_h_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmin8x8_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_bmin8x8_l_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c8000; +} + +static void +Opcode_ae_bmin8x8_l_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000400; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmin8x8_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_bmax16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bmax16x4_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ae_bmax16x4_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14004000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmax16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820800; +} + +static void +Opcode_ae_bmin16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bmin16x4_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ae_bmin16x4_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14006400; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmin16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820c00; +} + +static void +Opcode_ae_bmax32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c700000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bmax32x2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ae_bmax32x2_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmax32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400a00; +} + +static void +Opcode_ae_bmin32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c700100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bmin32x2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ae_bmin32x2_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14002000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmin32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400e00; +} + +static void +Opcode_ae_addinv16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80fd0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addinv16s_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a000; +} + +static void +Opcode_ae_addinv16s_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ae_addinv16s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003c20; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addinv16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0050; +} + +static void +Opcode_ae_addinv16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3d0000; +} + +static void +Opcode_ae_addinv16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8006e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addinv32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80fe0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addinv32s_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a400; +} + +static void +Opcode_ae_addinv32s_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130020; +} + +static void +Opcode_ae_addinv32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003840; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addinv32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0070; +} + +static void +Opcode_ae_addinv32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3d8000; +} + +static void +Opcode_ae_addinv32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80076462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movt16x8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt16x8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_movt8x16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt8x16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; +} + +static void +Opcode_ae_movt8x16_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt8x16_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000000; +} + +static void +Opcode_ae_movbd1x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520005; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movbd1x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa824004; +} + +static void +Opcode_ae_movbd1x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movbd1x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa820004; +} + +static void +Opcode_ae_movneg32s_t_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18400b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movneg32s_t_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180a00; +} + +static void +Opcode_ae_movneg32s_t_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80d0000; +} + +static void +Opcode_ae_movneg32s_t_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movdext_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movdext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8420003; +} + +static void +Opcode_ae_movadext_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c400000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movadext_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400000; +} + +static void +Opcode_ae_movadext_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c440000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movadext_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400400; +} + +static void +Opcode_ae_nsa16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19196030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsa16x4_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03021; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsa16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0220c; +} + +static void +Opcode_ae_nsaz32x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880070; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz32x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c06001; +} + +static void +Opcode_ae_nsa32x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880060; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsa32x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04001; +} + +static void +Opcode_ae_trunci16x4f32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c080000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunci16x4f32s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_trunci16x4f32s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ae_trunci16x4f32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8422003; +} + +static void +Opcode_ae_trunci16x4f64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunci16x4f64s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_trunci16x4f64s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_trunci16x4f64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8020000; +} + +static void +Opcode_ae_trunca16x4f32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c100000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca16x4f32s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ae_trunca16x4f32s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_trunca16x4f32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81a0000; +} + +static void +Opcode_ae_trunca16x4f64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c180000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca16x4f64s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x704000; +} + +static void +Opcode_ae_trunca16x4f64s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1480000; +} + +static void +Opcode_ae_trunca16x4f64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81a0100; +} + +static void +Opcode_ae_addc32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c680000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addc32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_addc32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400800; +} + +static void +Opcode_ae_subc32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c780000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subc32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_subc32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820000; +} + +static void +Opcode_ae_addc32u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c680100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addc32u_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_ae_addc32u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400c00; +} + +static void +Opcode_ae_subc32u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c780100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subc32u_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_subc32u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820400; +} + +static void +Opcode_ae_expadd16_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; +} + +static void +Opcode_ae_expadd16_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_expsub16_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010000; +} + +static void +Opcode_ae_expsub16_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004860; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_expadd16_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8008000; +} + +static void +Opcode_ae_expadd16_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004460; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_expsub16_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8018000; +} + +static void +Opcode_ae_expsub16_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004c60; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addcexp32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002a; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addcexp32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002b; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_calcrng16_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680800; +} + +static void +Opcode_ae_calcrng32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680c00; +} + +static void +Opcode_ae_rng32x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7382f00; +} + +static void +Opcode_ae_lav8x8x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_lav8x8x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a058000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lav8x8x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_lav8x8x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_lav8x8x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8118000; +} + +static void +Opcode_ae_lav16x4x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lav16x4x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a018000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lav16x4x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_lav16x4x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_lav16x4x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8110000; +} + +static void +Opcode_ae_sav8x8x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_sav8x8x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_sav8x8x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf410000; +} + +static void +Opcode_ae_sav16x4x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_sav16x4x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_sav16x4x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf400000; +} + +static void +Opcode_ae_movzbvcdr_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100001; + slotbuf[1] = 0x229860; +} + +static void +Opcode_ae_movzbvcdr_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00027; +} + +static void +Opcode_ae_movdrzbvc_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; + slotbuf[1] = 0x229860; +} + +static void +Opcode_ae_movdrzbvc_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00026; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6040000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mul8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002000; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mul8q4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula8q4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400; + slotbuf[1] = 0x2c0100; +} + +static void +Opcode_ae_mul8q8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula8q8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mul8qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x40000; +} + +static void +Opcode_ae_mula8qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xc0000; +} + +static void +Opcode_ae_mul4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x240000; +} + +static void +Opcode_ae_mula4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x240000; +} + +static void +Opcode_ae_mul4o4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x280000; +} + +static void +Opcode_ae_mula4o4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x284000; +} + +static void +Opcode_ae_mul4o8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula4o8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x80000; +} + +static void +Opcode_ae_mul4qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x282000; +} + +static void +Opcode_ae_mula4qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x286000; +} + +static void +Opcode_ae_mul8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0728; +} + +static void +Opcode_ae_mul8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0628; +} + +static void +Opcode_ae_mula8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c2628; +} + +static void +Opcode_ae_mula8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c2628; +} + +static void +Opcode_ae_mul8q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0128; +} + +static void +Opcode_ae_mula8q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0228; +} + +static void +Opcode_ae_mul2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0628; +} + +static void +Opcode_ae_mula2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0728; +} + +static void +Opcode_ae_mul2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0008; +} + +static void +Opcode_ae_mul2x4q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula2x4q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0008; +} + +static void +Opcode_ae_mulqq8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200040; +} + +static void +Opcode_ae_mulaqq8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200010; +} + +static void +Opcode_ae_mul4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201860; +} + +static void +Opcode_ae_mula4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x205860; +} + +static void +Opcode_ae_mul4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x203860; +} + +static void +Opcode_ae_mula4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x207860; +} + +static void +Opcode_ae_mul4o8x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200460; +} + +static void +Opcode_ae_mula4o8x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200a60; +} + +static void +Opcode_ae_mul4o8x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200560; +} + +static void +Opcode_ae_mula4o8x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200b60; +} + +static void +Opcode_ae_mul8q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0028; +} + +static void +Opcode_ae_mula8q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0128; +} + +static void +Opcode_ae_mul8q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0028; +} + +static void +Opcode_ae_mula8q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0228; +} + +static void +Opcode_ae_mul2x4q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula2x4q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0008; +} + +static void +Opcode_ae_mul2x4q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula2x4q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0008; +} + +static void +Opcode_ae_mulqq4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200030; +} + +static void +Opcode_ae_mulaqq4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200000; +} + +static void +Opcode_ae_mulqq4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200038; +} + +static void +Opcode_ae_mulaqq4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200008; +} + +static void +Opcode_ae_mul4o4x16cnv_hh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200060; +} + +static void +Opcode_ae_mul4o4x16cnv_hl_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200160; +} + +static void +Opcode_ae_mul4o4x16cnv_lh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200260; +} + +static void +Opcode_ae_mul4o4x16cnv_ll_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200360; +} + +static void +Opcode_ae_mula4o4x16cnv_hh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200660; +} + +static void +Opcode_ae_mula4o4x16cnv_hl_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200760; +} + +static void +Opcode_ae_mula4o4x16cnv_lh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200860; +} + +static void +Opcode_ae_mula4o4x16cnv_ll_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200960; +} + +static void +Opcode_ae_muluu8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; + slotbuf[1] = 0x2c0002; +} + +static void +Opcode_ae_mulauu8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; + slotbuf[1] = 0x2c0001; +} + +static void +Opcode_ae_muluu4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x240002; +} + +static void +Opcode_ae_mulauu4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x240001; +} + +static void +Opcode_ae_muluu8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2cc728; +} + +static void +Opcode_ae_mulauu8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c6728; +} + +static void +Opcode_ae_muluu8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2cc628; +} + +static void +Opcode_ae_mulauu8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c6628; +} + +static void +Opcode_ae_muluu2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2cc628; +} + +static void +Opcode_ae_mulauu2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c6628; +} + +static void +Opcode_ae_muluu2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0028; +} + +static void +Opcode_ae_mulauu2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0018; +} + +static void +Opcode_ae_muluu4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x221860; +} + +static void +Opcode_ae_mulauu4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x211860; +} + +static void +Opcode_ae_muluu4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x223860; +} + +static void +Opcode_ae_mulauu4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x213860; +} + +static void +Opcode_ae_mulus8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0002000; + slotbuf[1] = 0x2c0001; +} + +static void +Opcode_ae_mulaus8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0002000; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mulus8q4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400; + slotbuf[1] = 0x2c0300; +} + +static void +Opcode_ae_mulaus8q4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400; + slotbuf[1] = 0x2c0200; +} + +static void +Opcode_ae_mulus8q8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mulaus8q8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mulus8qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x1c0000; +} + +static void +Opcode_ae_mulaus8qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x140000; +} + +static void +Opcode_ae_mulus4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x240001; +} + +static void +Opcode_ae_mulaus4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x240000; +} + +static void +Opcode_ae_mulus4o4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x28c000; +} + +static void +Opcode_ae_mulaus4o4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x288000; +} + +static void +Opcode_ae_mulus4o8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x180000; +} + +static void +Opcode_ae_mulaus4o8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x100000; +} + +static void +Opcode_ae_mulus4qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x28e000; +} + +static void +Opcode_ae_mulaus4qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x28a000; +} + +static void +Opcode_ae_mulus8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2ca728; +} + +static void +Opcode_ae_mulaus8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c4728; +} + +static void +Opcode_ae_mulus8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2ca728; +} + +static void +Opcode_ae_mulaus8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c4728; +} + +static void +Opcode_ae_mulus8q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0528; +} + +static void +Opcode_ae_mulaus8q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0428; +} + +static void +Opcode_ae_mulus2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2ca628; +} + +static void +Opcode_ae_mulaus2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c4628; +} + +static void +Opcode_ae_mulus2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0020; +} + +static void +Opcode_ae_mulaus2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0018; +} + +static void +Opcode_ae_mulus2x4q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0020; +} + +static void +Opcode_ae_mulaus2x4q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0010; +} + +static void +Opcode_ae_mulusqq8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200058; +} + +static void +Opcode_ae_mulausqq8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200028; +} + +static void +Opcode_ae_mulus4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x21d860; +} + +static void +Opcode_ae_mulaus4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x20d860; +} + +static void +Opcode_ae_mulus4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x21f860; +} + +static void +Opcode_ae_mulaus4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x20f860; +} + +static void +Opcode_ae_mulus4o8x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201660; +} + +static void +Opcode_ae_mulaus4o8x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201060; +} + +static void +Opcode_ae_mulus4o8x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201760; +} + +static void +Opcode_ae_mulaus4o8x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201160; +} + +static void +Opcode_ae_mulus8q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0428; +} + +static void +Opcode_ae_mulaus8q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0328; +} + +static void +Opcode_ae_mulus8q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0528; +} + +static void +Opcode_ae_mulaus8q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0328; +} + +static void +Opcode_ae_mulus2x4q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0020; +} + +static void +Opcode_ae_mulaus2x4q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0010; +} + +static void +Opcode_ae_mulus2x4q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0020; +} + +static void +Opcode_ae_mulaus2x4q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0010; +} + +static void +Opcode_ae_mulusqq4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200048; +} + +static void +Opcode_ae_mulausqq4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200018; +} + +static void +Opcode_ae_mulusqq4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200050; +} + +static void +Opcode_ae_mulausqq4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200020; +} + +static void +Opcode_ae_mulus4o4x16cnv_hh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201260; +} + +static void +Opcode_ae_mulus4o4x16cnv_hl_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201360; +} + +static void +Opcode_ae_mulus4o4x16cnv_lh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201460; +} + +static void +Opcode_ae_mulus4o4x16cnv_ll_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201560; +} + +static void +Opcode_ae_mulaus4o4x16cnv_hh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200c60; +} + +static void +Opcode_ae_mulaus4o4x16cnv_hl_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200d60; +} + +static void +Opcode_ae_mulaus4o4x16cnv_lh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200e60; +} + +static void +Opcode_ae_mulaus4o4x16cnv_ll_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200f60; +} + +static void +Opcode_ae_mulsu8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002000; + slotbuf[1] = 0x2c0001; +} + +static void +Opcode_ae_mulasu8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002000; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mulsu4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x240001; +} + +static void +Opcode_ae_mulasu4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x240000; +} + +static void +Opcode_ae_mulsu8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2ca628; +} + +static void +Opcode_ae_mulasu8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c4628; +} + +static void +Opcode_ae_mulsu8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c8728; +} + +static void +Opcode_ae_mulasu8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c2728; +} + +static void +Opcode_ae_mulsu2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c8728; +} + +static void +Opcode_ae_mulasu2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c2728; +} + +static void +Opcode_ae_mulsu2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0018; +} + +static void +Opcode_ae_mulasu2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0010; +} + +static void +Opcode_ae_mulsu4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x219860; +} + +static void +Opcode_ae_mulasu4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x209860; +} + +static void +Opcode_ae_mulsu4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x21b860; +} + +static void +Opcode_ae_mulasu4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x20b860; +} + +static void +Opcode_ae_muluuzb8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002000; + slotbuf[1] = 0x2c0002; +} + +static void +Opcode_ae_mulauuzb8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002000; + slotbuf[1] = 0x2c0001; +} + +static void +Opcode_ae_muluuzb4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x240002; +} + +static void +Opcode_ae_mulauuzb4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x240001; +} + +static void +Opcode_ae_muluuzb8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2ce628; +} + +static void +Opcode_ae_mulauuzb8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c8628; +} + +static void +Opcode_ae_muluuzb8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2ce628; +} + +static void +Opcode_ae_mulauuzb8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c8628; +} + +static void +Opcode_ae_muluuzb2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2cc728; +} + +static void +Opcode_ae_mulauuzb2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c6728; +} + +static void +Opcode_ae_muluuzb2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0028; +} + +static void +Opcode_ae_mulauuzb2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0018; +} + +static void +Opcode_ae_muluuzb4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x225860; +} + +static void +Opcode_ae_mulauuzb4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x215860; +} + +static void +Opcode_ae_muluuzb4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x227860; +} + +static void +Opcode_ae_mulauuzb4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x217860; +} + +static void +Opcode_cvtsf16_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190c0026; + slotbuf[1] = 0; +} + +static void +Opcode_cvtsf16_l_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b7; +} + +static void +Opcode_cvtsf16_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a2f00; +} + +static void +Opcode_cvtsf16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190c0022; + slotbuf[1] = 0; +} + +static void +Opcode_cvtsf16_h_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b5; +} + +static void +Opcode_cvtsf16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a2b00; +} + +static void +Opcode_cvtf16s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1908002e; + slotbuf[1] = 0; +} + +static void +Opcode_cvtf16s_l_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b3; +} + +static void +Opcode_cvtf16s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2f00; +} + +static void +Opcode_cvtf16s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1908002a; + slotbuf[1] = 0; +} + +static void +Opcode_cvtf16s_h_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b1; +} + +static void +Opcode_cvtf16s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2b00; +} + +static void +Opcode_ae_movfcrfsrv_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4a0000; +} + +static void +Opcode_ae_movvfcrfsr_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4a8000; +} + +static void +Opcode_movt_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800e0; + slotbuf[1] = 0; +} + +static void +Opcode_movt_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481200; +} + +static void +Opcode_movt_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742e001; +} + +static void +Opcode_movf_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800d0; + slotbuf[1] = 0; +} + +static void +Opcode_movf_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480a00; +} + +static void +Opcode_movf_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742c001; +} + +static void +Opcode_moveqz_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d88000c; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04200; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480800; +} + +static void +Opcode_moveqz_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830000; +} + +static void +Opcode_movnez_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d88000a; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04b00; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481000; +} + +static void +Opcode_movnez_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98300c0; +} + +static void +Opcode_movgez_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880002; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04300; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480c00; +} + +static void +Opcode_movgez_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830040; +} + +static void +Opcode_movltz_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880006; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04a00; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480e00; +} + +static void +Opcode_movltz_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830080; +} + +static void +Opcode_rfr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929a04; +} + +static void +Opcode_wfr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e10c0; +} + +static void +Opcode_mul_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000020; + slotbuf[1] = 0x7; +} + +static void +Opcode_mul_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000020; + slotbuf[1] = 0x5; +} + +static void +Opcode_mul_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4300c00; + slotbuf[1] = 0; +} + +static void +Opcode_mul_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17001c0; +} + +static void +Opcode_mul_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae000080; + slotbuf[1] = 0; +} + +static void +Opcode_mul_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e000020; +} + +static void +Opcode_mul_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69003e0; +} + +static void +Opcode_mul_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003f; + slotbuf[1] = 0xe; +} + +static void +Opcode_madd_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; + slotbuf[1] = 0x7; +} + +static void +Opcode_madd_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000020; + slotbuf[1] = 0x5; +} + +static void +Opcode_madd_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe300800; + slotbuf[1] = 0; +} + +static void +Opcode_madd_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700160; +} + +static void +Opcode_madd_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8000080; + slotbuf[1] = 0; +} + +static void +Opcode_madd_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000020; +} + +static void +Opcode_madd_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900300; +} + +static void +Opcode_madd_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003c; + slotbuf[1] = 0xe; +} + +static void +Opcode_msub_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000020; + slotbuf[1] = 0x7; +} + +static void +Opcode_msub_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000020; + slotbuf[1] = 0x5; +} + +static void +Opcode_msub_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2300c00; + slotbuf[1] = 0; +} + +static void +Opcode_msub_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17001a0; +} + +static void +Opcode_msub_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac000080; + slotbuf[1] = 0; +} + +static void +Opcode_msub_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c000020; +} + +static void +Opcode_msub_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69003c0; +} + +static void +Opcode_msub_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003e; + slotbuf[1] = 0xe; +} + +static void +Opcode_msubn_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000020; + slotbuf[1] = 0x7; +} + +static void +Opcode_msubn_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44000020; + slotbuf[1] = 0x5; +} + +static void +Opcode_msubn_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0300c00; + slotbuf[1] = 0; +} + +static void +Opcode_msubn_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700180; +} + +static void +Opcode_msubn_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa000080; + slotbuf[1] = 0; +} + +static void +Opcode_msubn_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a000020; +} + +static void +Opcode_msubn_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69003a0; +} + +static void +Opcode_msubn_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003d; + slotbuf[1] = 0xe; +} + +static void +Opcode_maddn_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000020; + slotbuf[1] = 0x6; +} + +static void +Opcode_maddn_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000020; + slotbuf[1] = 0x4; +} + +static void +Opcode_maddn_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc300800; + slotbuf[1] = 0; +} + +static void +Opcode_maddn_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700140; +} + +static void +Opcode_maddn_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6000080; + slotbuf[1] = 0; +} + +static void +Opcode_maddn_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26000020; +} + +static void +Opcode_maddn_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69002e0; +} + +static void +Opcode_maddn_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003b; + slotbuf[1] = 0xe; +} + +static void +Opcode_add_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000022; + slotbuf[1] = 0x5; +} + +static void +Opcode_add_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000a0; + slotbuf[1] = 0x5; +} + +static void +Opcode_add_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a050000; + slotbuf[1] = 0; +} + +static void +Opcode_add_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1848000; +} + +static void +Opcode_add_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00021; + slotbuf[1] = 0; +} + +static void +Opcode_add_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000a0; +} + +static void +Opcode_add_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa048000; +} + +static void +Opcode_add_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068022; + slotbuf[1] = 0xe; +} + +static void +Opcode_sub_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000042; + slotbuf[1] = 0x5; +} + +static void +Opcode_sub_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000c0; + slotbuf[1] = 0x5; +} + +static void +Opcode_sub_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c050000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1870000; +} + +static void +Opcode_sub_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a000a1; + slotbuf[1] = 0; +} + +static void +Opcode_sub_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000c0; +} + +static void +Opcode_sub_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa050000; +} + +static void +Opcode_sub_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068042; + slotbuf[1] = 0xe; +} + +static void +Opcode_ole_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19200031; + slotbuf[1] = 0; +} + +static void +Opcode_ole_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640510; +} + +static void +Opcode_ole_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540081; +} + +static void +Opcode_ole_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022100; +} + +static void +Opcode_olt_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19240030; + slotbuf[1] = 0; +} + +static void +Opcode_olt_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640800; +} + +static void +Opcode_olt_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540090; +} + +static void +Opcode_olt_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022500; +} + +static void +Opcode_oeq_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19200030; + slotbuf[1] = 0; +} + +static void +Opcode_oeq_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640500; +} + +static void +Opcode_oeq_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540080; +} + +static void +Opcode_oeq_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022c00; +} + +static void +Opcode_un_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192c0030; + slotbuf[1] = 0; +} + +static void +Opcode_un_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640c00; +} + +static void +Opcode_un_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b0; +} + +static void +Opcode_un_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022600; +} + +static void +Opcode_ule_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19280030; + slotbuf[1] = 0; +} + +static void +Opcode_ule_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640900; +} + +static void +Opcode_ule_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400a0; +} + +static void +Opcode_ule_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022d00; +} + +static void +Opcode_ult_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19280031; + slotbuf[1] = 0; +} + +static void +Opcode_ult_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640910; +} + +static void +Opcode_ult_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400a1; +} + +static void +Opcode_ult_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022200; +} + +static void +Opcode_ueq_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19240031; + slotbuf[1] = 0; +} + +static void +Opcode_ueq_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640810; +} + +static void +Opcode_ueq_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540091; +} + +static void +Opcode_ueq_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022900; +} + +static void +Opcode_nexp01_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808008; + slotbuf[1] = 0x7; +} + +static void +Opcode_nexp01_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160004; + slotbuf[1] = 0x5; +} + +static void +Opcode_nexp01_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80211801; + slotbuf[1] = 0; +} + +static void +Opcode_nexp01_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700202; +} + +static void +Opcode_nexp01_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0c08001; + slotbuf[1] = 0; +} + +static void +Opcode_nexp01_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c45801d; +} + +static void +Opcode_nexp01_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa600026; +} + +static void +Opcode_nexp01_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40381002; + slotbuf[1] = 0xe; +} + +static void +Opcode_mksadj_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808004; + slotbuf[1] = 0x7; +} + +static void +Opcode_mksadj_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160003; + slotbuf[1] = 0x5; +} + +static void +Opcode_mksadj_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80111801; + slotbuf[1] = 0; +} + +static void +Opcode_mksadj_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700201; +} + +static void +Opcode_mksadj_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8c08001; + slotbuf[1] = 0; +} + +static void +Opcode_mksadj_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c35801d; +} + +static void +Opcode_mksadj_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa500026; +} + +static void +Opcode_mksadj_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40281002; + slotbuf[1] = 0xe; +} + +static void +Opcode_mkdadj_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000062; + slotbuf[1] = 0x6; +} + +static void +Opcode_mkdadj_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000e2; + slotbuf[1] = 0x5; +} + +static void +Opcode_mkdadj_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6390c00; + slotbuf[1] = 0; +} + +static void +Opcode_mkdadj_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17901e0; +} + +static void +Opcode_mkdadj_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab002c1; + slotbuf[1] = 0; +} + +static void +Opcode_mkdadj_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000e2; +} + +static void +Opcode_mkdadj_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa458000; +} + +static void +Opcode_mkdadj_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068862; + slotbuf[1] = 0xe; +} + +static void +Opcode_div0_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808003; + slotbuf[1] = 0x7; +} + +static void +Opcode_div0_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160001; + slotbuf[1] = 0x5; +} + +static void +Opcode_div0_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80011801; + slotbuf[1] = 0; +} + +static void +Opcode_div0_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700200; +} + +static void +Opcode_div0_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6c08001; + slotbuf[1] = 0; +} + +static void +Opcode_div0_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c15801d; +} + +static void +Opcode_div0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa500025; +} + +static void +Opcode_div0_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401f1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_sqrt0_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800b; + slotbuf[1] = 0x7; +} + +static void +Opcode_sqrt0_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160007; + slotbuf[1] = 0x5; +} + +static void +Opcode_sqrt0_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80511801; + slotbuf[1] = 0; +} + +static void +Opcode_sqrt0_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700205; +} + +static void +Opcode_sqrt0_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6c08001; + slotbuf[1] = 0; +} + +static void +Opcode_sqrt0_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c75801d; +} + +static void +Opcode_sqrt0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa700025; +} + +static void +Opcode_sqrt0_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40291002; + slotbuf[1] = 0xe; +} + +static void +Opcode_recip0_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808009; + slotbuf[1] = 0x7; +} + +static void +Opcode_recip0_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160005; + slotbuf[1] = 0x5; +} + +static void +Opcode_recip0_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80311801; + slotbuf[1] = 0; +} + +static void +Opcode_recip0_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700203; +} + +static void +Opcode_recip0_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2c08001; + slotbuf[1] = 0; +} + +static void +Opcode_recip0_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c55801d; +} + +static void +Opcode_recip0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa600027; +} + +static void +Opcode_recip0_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40289002; + slotbuf[1] = 0xe; +} + +static void +Opcode_rsqrt0_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800a; + slotbuf[1] = 0x7; +} + +static void +Opcode_rsqrt0_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160006; + slotbuf[1] = 0x5; +} + +static void +Opcode_rsqrt0_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80411801; + slotbuf[1] = 0; +} + +static void +Opcode_rsqrt0_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700204; +} + +static void +Opcode_rsqrt0_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4c08001; + slotbuf[1] = 0; +} + +static void +Opcode_rsqrt0_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c65801d; +} + +static void +Opcode_rsqrt0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa700024; +} + +static void +Opcode_rsqrt0_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40389002; + slotbuf[1] = 0xe; +} + +static void +Opcode_divn_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000020; + slotbuf[1] = 0x6; +} + +static void +Opcode_divn_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000020; + slotbuf[1] = 0x4; +} + +static void +Opcode_divn_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa300800; + slotbuf[1] = 0; +} + +static void +Opcode_divn_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700120; +} + +static void +Opcode_divn_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4000080; + slotbuf[1] = 0; +} + +static void +Opcode_divn_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000020; +} + +static void +Opcode_divn_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69002c0; +} + +static void +Opcode_divn_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003a; + slotbuf[1] = 0xe; +} + +static void +Opcode_addexp_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000061; + slotbuf[1] = 0x6; +} + +static void +Opcode_addexp_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000e1; + slotbuf[1] = 0x5; +} + +static void +Opcode_addexp_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6388c00; + slotbuf[1] = 0; +} + +static void +Opcode_addexp_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17881e0; +} + +static void +Opcode_addexp_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00261; + slotbuf[1] = 0; +} + +static void +Opcode_addexp_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000e1; +} + +static void +Opcode_addexp_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa358000; +} + +static void +Opcode_addexp_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068462; + slotbuf[1] = 0xe; +} + +static void +Opcode_addexpm_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000060; + slotbuf[1] = 0x6; +} + +static void +Opcode_addexpm_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000e0; + slotbuf[1] = 0x5; +} + +static void +Opcode_addexpm_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6380c00; + slotbuf[1] = 0; +} + +static void +Opcode_addexpm_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17801e0; +} + +static void +Opcode_addexpm_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00241; + slotbuf[1] = 0; +} + +static void +Opcode_addexpm_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000e0; +} + +static void +Opcode_addexpm_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa258000; +} + +static void +Opcode_addexpm_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068062; + slotbuf[1] = 0xe; +} + +static void +Opcode_min_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000040; + slotbuf[1] = 0x6; +} + +static void +Opcode_min_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205001b; + slotbuf[1] = 0x5; +} + +static void +Opcode_min_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c048000; + slotbuf[1] = 0; +} + +static void +Opcode_min_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1830000; +} + +static void +Opcode_min_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00141; + slotbuf[1] = 0; +} + +static void +Opcode_min_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05001b; +} + +static void +Opcode_min_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa030000; +} + +static void +Opcode_min_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400d8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_max_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000060; + slotbuf[1] = 0x6; +} + +static void +Opcode_max_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82058019; + slotbuf[1] = 0x5; +} + +static void +Opcode_max_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e040000; + slotbuf[1] = 0; +} + +static void +Opcode_max_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1818000; +} + +static void +Opcode_max_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00181; + slotbuf[1] = 0; +} + +static void +Opcode_max_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c058019; +} + +static void +Opcode_max_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa018000; +} + +static void +Opcode_max_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_mulmux_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulmux_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000020; + slotbuf[1] = 0x4; +} + +static void +Opcode_mulmux_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0300000; + slotbuf[1] = 0; +} + +static void +Opcode_mulmux_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000080; + slotbuf[1] = 0; +} + +static void +Opcode_mulmux_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000020; +} + +static void +Opcode_mulmux_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00000; +} + +static void +Opcode_mulmux_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80100038; + slotbuf[1] = 0xe; +} + +static void +Opcode_maddmux_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_maddmux_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_maddmux_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0300000; + slotbuf[1] = 0; +} + +static void +Opcode_maddmux_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000000; + slotbuf[1] = 0; +} + +static void +Opcode_maddmux_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000000; +} + +static void +Opcode_maddmux_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00000; +} + +static void +Opcode_maddmux_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000038; + slotbuf[1] = 0xe; +} + +static void +Opcode_trunc_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19030010; + slotbuf[1] = 0; +} + +static void +Opcode_trunc_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800010; +} + +static void +Opcode_trunc_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1308; +} + +static void +Opcode_utrunc_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19032010; + slotbuf[1] = 0; +} + +static void +Opcode_utrunc_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2802010; +} + +static void +Opcode_utrunc_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9208; +} + +static void +Opcode_trunc_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000024; + slotbuf[1] = 0; +} + +static void +Opcode_trunc_sx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800002; +} + +static void +Opcode_trunc_sx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c06000; +} + +static void +Opcode_utrunc_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900002c; + slotbuf[1] = 0; +} + +static void +Opcode_utrunc_sx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800006; +} + +static void +Opcode_utrunc_sx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c02001; +} + +static void +Opcode_ficeil_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190c002a; + slotbuf[1] = 0; +} + +static void +Opcode_ficeil_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b9; +} + +static void +Opcode_ficeil_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62a2b00; +} + +static void +Opcode_fifloor_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190c002e; + slotbuf[1] = 0; +} + +static void +Opcode_fifloor_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400bb; +} + +static void +Opcode_fifloor_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62a2f00; +} + +static void +Opcode_firint_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19100022; + slotbuf[1] = 0; +} + +static void +Opcode_firint_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400bd; +} + +static void +Opcode_firint_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63a2b00; +} + +static void +Opcode_firound_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19100026; + slotbuf[1] = 0; +} + +static void +Opcode_firound_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400bf; +} + +static void +Opcode_firound_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63a2f00; +} + +static void +Opcode_fitrunc_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1910002a; + slotbuf[1] = 0; +} + +static void +Opcode_fitrunc_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800008; +} + +static void +Opcode_fitrunc_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380f00; +} + +static void +Opcode_float_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18800b00; + slotbuf[1] = 0; +} + +static void +Opcode_float_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000000; +} + +static void +Opcode_float_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00100; +} + +static void +Opcode_ufloat_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18800b04; + slotbuf[1] = 0; +} + +static void +Opcode_ufloat_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000002; +} + +static void +Opcode_ufloat_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00140; +} + +static void +Opcode_float_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000020; + slotbuf[1] = 0; +} + +static void +Opcode_float_sx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800000; +} + +static void +Opcode_float_sx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04000; +} + +static void +Opcode_ufloat_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000028; + slotbuf[1] = 0; +} + +static void +Opcode_ufloat_sx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800004; +} + +static void +Opcode_ufloat_sx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00001; +} + +static void +Opcode_abs_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808000; + slotbuf[1] = 0x7; +} + +static void +Opcode_abs_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160008; + slotbuf[1] = 0x5; +} + +static void +Opcode_abs_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000a; + slotbuf[1] = 0; +} + +static void +Opcode_abs_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80611801; + slotbuf[1] = 0; +} + +static void +Opcode_abs_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700206; +} + +static void +Opcode_abs_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c08001; + slotbuf[1] = 0; +} + +static void +Opcode_abs_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c85801d; +} + +static void +Opcode_abs_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa400026; +} + +static void +Opcode_abs_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40391002; + slotbuf[1] = 0xe; +} + +static void +Opcode_neg_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808007; + slotbuf[1] = 0x7; +} + +static void +Opcode_neg_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000d; + slotbuf[1] = 0x5; +} + +static void +Opcode_neg_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2800a; + slotbuf[1] = 0; +} + +static void +Opcode_neg_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80b11801; + slotbuf[1] = 0; +} + +static void +Opcode_neg_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020b; +} + +static void +Opcode_neg_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcec08001; + slotbuf[1] = 0; +} + +static void +Opcode_neg_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cd5801d; +} + +static void +Opcode_neg_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa600025; +} + +static void +Opcode_neg_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402a9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_conjc_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808002; + slotbuf[1] = 0x7; +} + +static void +Opcode_conjc_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000a; + slotbuf[1] = 0x5; +} + +static void +Opcode_conjc_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d1000a; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80811801; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700208; +} + +static void +Opcode_conjc_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4c08001; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca5801d; +} + +static void +Opcode_conjc_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa500024; +} + +static void +Opcode_conjc_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40399002; + slotbuf[1] = 0xe; +} + +static void +Opcode_muljc_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808006; + slotbuf[1] = 0x7; +} + +static void +Opcode_muljc_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000c; + slotbuf[1] = 0x5; +} + +static void +Opcode_muljc_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2000a; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a11801; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020a; +} + +static void +Opcode_muljc_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xccc08001; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc5801d; +} + +static void +Opcode_muljc_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa600024; +} + +static void +Opcode_muljc_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403a1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_const_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808011; + slotbuf[1] = 0x7; +} + +static void +Opcode_const_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160013; + slotbuf[1] = 0x5; +} + +static void +Opcode_const_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3000b; + slotbuf[1] = 0; +} + +static void +Opcode_const_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81011a01; + slotbuf[1] = 0; +} + +static void +Opcode_const_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700211; +} + +static void +Opcode_const_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdec0c001; + slotbuf[1] = 0; +} + +static void +Opcode_const_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d25c01d; +} + +static void +Opcode_const_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00025; +} + +static void +Opcode_const_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44300003; + slotbuf[1] = 0xe; +} + +static void +Opcode_clsfy_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82810000; + slotbuf[1] = 0x7; +} + +static void +Opcode_clsfy_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160000; + slotbuf[1] = 0x5; +} + +static void +Opcode_clsfy_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e050000; + slotbuf[1] = 0; +} + +static void +Opcode_clsfy_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1878000; +} + +static void +Opcode_clsfy_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c10001; + slotbuf[1] = 0; +} + +static void +Opcode_clsfy_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05801d; +} + +static void +Opcode_clsfy_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000021; +} + +static void +Opcode_clsfy_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401e9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_minnum_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000060; + slotbuf[1] = 0x6; +} + +static void +Opcode_minnum_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205801a; + slotbuf[1] = 0x5; +} + +static void +Opcode_minnum_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a048000; + slotbuf[1] = 0; +} + +static void +Opcode_minnum_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1828000; +} + +static void +Opcode_minnum_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a000c1; + slotbuf[1] = 0; +} + +static void +Opcode_minnum_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05801a; +} + +static void +Opcode_minnum_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa028000; +} + +static void +Opcode_minnum_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400d0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_maxnum_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000040; + slotbuf[1] = 0x6; +} + +static void +Opcode_maxnum_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82050019; + slotbuf[1] = 0x5; +} + +static void +Opcode_maxnum_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c040000; + slotbuf[1] = 0; +} + +static void +Opcode_maxnum_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1810000; +} + +static void +Opcode_maxnum_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00101; + slotbuf[1] = 0; +} + +static void +Opcode_maxnum_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c050019; +} + +static void +Opcode_maxnum_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa010000; +} + +static void +Opcode_maxnum_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400b8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_addandsub_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000001; + slotbuf[1] = 0x5; +} + +static void +Opcode_addandsub_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82048000; + slotbuf[1] = 0x5; +} + +static void +Opcode_addandsub_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80019000; + slotbuf[1] = 0; +} + +static void +Opcode_addandsub_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addandsub_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0900001; + slotbuf[1] = 0; +} + +static void +Opcode_addandsub_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c048000; +} + +static void +Opcode_addandsub_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000140; +} + +static void +Opcode_addandsub_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40048002; + slotbuf[1] = 0xe; +} + +static void +Opcode_addandsubjc_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_addandsubjc_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82040000; + slotbuf[1] = 0x5; +} + +static void +Opcode_addandsubjc_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80011000; + slotbuf[1] = 0; +} + +static void +Opcode_addandsubjc_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_addandsubjc_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0800001; + slotbuf[1] = 0; +} + +static void +Opcode_addandsubjc_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c040000; +} + +static void +Opcode_addandsubjc_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000120; +} + +static void +Opcode_addandsubjc_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40060002; + slotbuf[1] = 0xe; +} + +static void +Opcode_add_hl_lh_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000002; + slotbuf[1] = 0x5; +} + +static void +Opcode_add_hl_lh_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000080; + slotbuf[1] = 0x5; +} + +static void +Opcode_add_hl_lh_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88050000; + slotbuf[1] = 0; +} + +static void +Opcode_add_hl_lh_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1840000; +} + +static void +Opcode_add_hl_lh_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a001c1; + slotbuf[1] = 0; +} + +static void +Opcode_add_hl_lh_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000080; +} + +static void +Opcode_add_hl_lh_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa040000; +} + +static void +Opcode_add_hl_lh_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068002; + slotbuf[1] = 0xe; +} + +static void +Opcode_madda_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_madda_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_madda_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000000; + slotbuf[1] = 0; +} + +static void +Opcode_madda_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000000; + slotbuf[1] = 0; +} + +static void +Opcode_madda_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000000; +} + +static void +Opcode_madda_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5800000; +} + +static void +Opcode_madda_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000034; + slotbuf[1] = 0xe; +} + +static void +Opcode_frexp_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000040; + slotbuf[1] = 0x6; +} + +static void +Opcode_frexp_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82050018; + slotbuf[1] = 0x5; +} + +static void +Opcode_frexp_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88040000; + slotbuf[1] = 0; +} + +static void +Opcode_frexp_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; +} + +static void +Opcode_frexp_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00001; + slotbuf[1] = 0; +} + +static void +Opcode_frexp_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c050018; +} + +static void +Opcode_frexp_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; +} + +static void +Opcode_frexp_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400a8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_floatexp_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82810020; + slotbuf[1] = 0x7; +} + +static void +Opcode_floatexp_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160002; + slotbuf[1] = 0x5; +} + +static void +Opcode_floatexp_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e050001; + slotbuf[1] = 0; +} + +static void +Opcode_floatexp_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1878001; +} + +static void +Opcode_floatexp_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c10021; + slotbuf[1] = 0; +} + +static void +Opcode_floatexp_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c25801d; +} + +static void +Opcode_floatexp_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa008021; +} + +static void +Opcode_floatexp_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401f9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_minnumabs_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000040; + slotbuf[1] = 0x6; +} + +static void +Opcode_minnumabs_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205001a; + slotbuf[1] = 0x5; +} + +static void +Opcode_minnumabs_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88048000; + slotbuf[1] = 0; +} + +static void +Opcode_minnumabs_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1820000; +} + +static void +Opcode_minnumabs_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00041; + slotbuf[1] = 0; +} + +static void +Opcode_minnumabs_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05001a; +} + +static void +Opcode_minnumabs_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa020000; +} + +static void +Opcode_minnumabs_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_maxnumabs_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000060; + slotbuf[1] = 0x6; +} + +static void +Opcode_maxnumabs_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82058018; + slotbuf[1] = 0x5; +} + +static void +Opcode_maxnumabs_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a040000; + slotbuf[1] = 0; +} + +static void +Opcode_maxnumabs_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1808000; +} + +static void +Opcode_maxnumabs_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00081; + slotbuf[1] = 0; +} + +static void +Opcode_maxnumabs_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c058018; +} + +static void +Opcode_maxnumabs_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa008000; +} + +static void +Opcode_maxnumabs_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400b0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_mulq_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_mulq_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulq_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98000000; + slotbuf[1] = 0; +} + +static void +Opcode_mulq_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000000; +} + +static void +Opcode_maddq_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_maddq_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_maddq_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94000000; + slotbuf[1] = 0; +} + +static void +Opcode_maddq_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000000; +} + +static void +Opcode_msubq_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_msubq_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_msubq_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96000000; + slotbuf[1] = 0; +} + +static void +Opcode_msubq_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000000; +} + +static void +Opcode_mulmuxq_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulmuxq_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_mulmuxq_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000000; + slotbuf[1] = 0; +} + +static void +Opcode_mulmuxq_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; +} + +static void +Opcode_maddmuxq_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x6; +} + +static void +Opcode_maddmuxq_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4; +} + +static void +Opcode_maddmuxq_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_maddmuxq_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_bmaxnum_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82058008; + slotbuf[1] = 0x5; +} + +static void +Opcode_bmaxnum_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82040000; + slotbuf[1] = 0; +} + +static void +Opcode_bmaxnum_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c058008; +} + +static void +Opcode_bmaxnum_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c0402; + slotbuf[1] = 0xe; +} + +static void +Opcode_bminnum_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82058010; + slotbuf[1] = 0x5; +} + +static void +Opcode_bminnum_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86040000; + slotbuf[1] = 0; +} + +static void +Opcode_bminnum_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c058010; +} + +static void +Opcode_bminnum_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c0802; + slotbuf[1] = 0xe; +} + +static void +Opcode_bmaxnumabs_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82058000; + slotbuf[1] = 0x5; +} + +static void +Opcode_bmaxnumabs_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80040000; + slotbuf[1] = 0; +} + +static void +Opcode_bmaxnumabs_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c058000; +} + +static void +Opcode_bmaxnumabs_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40080402; + slotbuf[1] = 0xe; +} + +static void +Opcode_bminnumabs_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82050010; + slotbuf[1] = 0x5; +} + +static void +Opcode_bminnumabs_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84040000; + slotbuf[1] = 0; +} + +static void +Opcode_bminnumabs_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c050010; +} + +static void +Opcode_bminnumabs_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40080802; + slotbuf[1] = 0xe; +} + +static void +Opcode_abs_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82100000; + slotbuf[1] = 0x7; +} + +static void +Opcode_abs_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82008000; + slotbuf[1] = 0x5; +} + +static void +Opcode_abs_sx2x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80018000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_sx2x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_abs_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0100001; + slotbuf[1] = 0; +} + +static void +Opcode_abs_sx2x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c008000; +} + +static void +Opcode_abs_sx2x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000020; +} + +static void +Opcode_abs_sx2x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40008002; + slotbuf[1] = 0xe; +} + +static void +Opcode_neg_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82700000; + slotbuf[1] = 0x7; +} + +static void +Opcode_neg_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82038000; + slotbuf[1] = 0x5; +} + +static void +Opcode_neg_sx2x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; + slotbuf[1] = 0; +} + +static void +Opcode_neg_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80018c00; + slotbuf[1] = 0; +} + +static void +Opcode_neg_sx2x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_neg_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0700001; + slotbuf[1] = 0; +} + +static void +Opcode_neg_sx2x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c038000; +} + +static void +Opcode_neg_sx2x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000e0; +} + +static void +Opcode_neg_sx2x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40040002; + slotbuf[1] = 0xe; +} + +static void +Opcode_conjc_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82300000; + slotbuf[1] = 0x7; +} + +static void +Opcode_conjc_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82018000; + slotbuf[1] = 0x5; +} + +static void +Opcode_conjc_sx2x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80018400; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_sx2x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_conjc_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0300001; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_sx2x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c018000; +} + +static void +Opcode_conjc_sx2x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000060; +} + +static void +Opcode_conjc_sx2x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40010002; + slotbuf[1] = 0xe; +} + +static void +Opcode_muljc_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82500000; + slotbuf[1] = 0x7; +} + +static void +Opcode_muljc_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82028000; + slotbuf[1] = 0x5; +} + +static void +Opcode_muljc_sx2x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80018800; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_sx2x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_muljc_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0500001; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_sx2x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c028000; +} + +static void +Opcode_muljc_sx2x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000a0; +} + +static void +Opcode_muljc_sx2x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40018002; + slotbuf[1] = 0xe; +} + +static void +Opcode_const_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82804000; + slotbuf[1] = 0x7; +} + +static void +Opcode_const_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82064000; + slotbuf[1] = 0x5; +} + +static void +Opcode_const_sx2x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00003; + slotbuf[1] = 0; +} + +static void +Opcode_const_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80011a00; + slotbuf[1] = 0; +} + +static void +Opcode_const_sx2x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1904001; +} + +static void +Opcode_const_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c04001; + slotbuf[1] = 0; +} + +static void +Opcode_const_sx2x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c064000; +} + +static void +Opcode_const_sx2x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa004020; +} + +static void +Opcode_const_sx2x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46000003; + slotbuf[1] = 0xe; +} + +static void +Opcode_add_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_add_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_add_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_sub_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_sub_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_mul_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x3; +} + +static void +Opcode_mul_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x3; +} + +static void +Opcode_madd_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_madd_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_msub_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_msub_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_mulmux_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_mulmux_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_maddmux_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_maddmux_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_abs_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800c; + slotbuf[1] = 0x7; +} + +static void +Opcode_abs_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000e; + slotbuf[1] = 0x5; +} + +static void +Opcode_abs_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03001; + slotbuf[1] = 0; +} + +static void +Opcode_abs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80c11801; + slotbuf[1] = 0; +} + +static void +Opcode_abs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020c; +} + +static void +Opcode_abs_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8c08001; + slotbuf[1] = 0; +} + +static void +Opcode_abs_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce5801d; +} + +static void +Opcode_abs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf58000; +} + +static void +Opcode_abs_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403a9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_addexp_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000064; + slotbuf[1] = 0x6; +} + +static void +Opcode_addexp_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000e4; + slotbuf[1] = 0x5; +} + +static void +Opcode_addexp_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63f0c00; + slotbuf[1] = 0; +} + +static void +Opcode_addexp_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a01e0; +} + +static void +Opcode_addexp_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00341; + slotbuf[1] = 0; +} + +static void +Opcode_addexp_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000e4; +} + +static void +Opcode_addexp_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa700027; +} + +static void +Opcode_addexp_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40069062; + slotbuf[1] = 0xe; +} + +static void +Opcode_addexpm_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000063; + slotbuf[1] = 0x6; +} + +static void +Opcode_addexpm_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000e3; + slotbuf[1] = 0x5; +} + +static void +Opcode_addexpm_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63e8c00; + slotbuf[1] = 0; +} + +static void +Opcode_addexpm_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17981e0; +} + +static void +Opcode_addexpm_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab002e1; + slotbuf[1] = 0; +} + +static void +Opcode_addexpm_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000e3; +} + +static void +Opcode_addexpm_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa700026; +} + +static void +Opcode_addexpm_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_clsfy_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800d; + slotbuf[1] = 0x7; +} + +static void +Opcode_clsfy_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000f; + slotbuf[1] = 0x5; +} + +static void +Opcode_clsfy_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80d11801; + slotbuf[1] = 0; +} + +static void +Opcode_clsfy_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020d; +} + +static void +Opcode_clsfy_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdac08001; + slotbuf[1] = 0; +} + +static void +Opcode_clsfy_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cf5801d; +} + +static void +Opcode_clsfy_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb058000; +} + +static void +Opcode_clsfy_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402b1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_conjc_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808001; + slotbuf[1] = 0x7; +} + +static void +Opcode_conjc_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160009; + slotbuf[1] = 0x5; +} + +static void +Opcode_conjc_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0800a; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80711801; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700207; +} + +static void +Opcode_conjc_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2c08001; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c95801d; +} + +static void +Opcode_conjc_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa400027; +} + +static void +Opcode_conjc_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40299002; + slotbuf[1] = 0xe; +} + +static void +Opcode_const_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808010; + slotbuf[1] = 0x7; +} + +static void +Opcode_const_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160012; + slotbuf[1] = 0x5; +} + +static void +Opcode_const_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3000a; + slotbuf[1] = 0; +} + +static void +Opcode_const_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81011801; + slotbuf[1] = 0; +} + +static void +Opcode_const_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700210; +} + +static void +Opcode_const_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdec08001; + slotbuf[1] = 0; +} + +static void +Opcode_const_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d25801d; +} + +static void +Opcode_const_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00024; +} + +static void +Opcode_const_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44200003; + slotbuf[1] = 0xe; +} + +static void +Opcode_min_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4100003; + slotbuf[1] = 0x6; +} + +static void +Opcode_min_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205001d; + slotbuf[1] = 0x5; +} + +static void +Opcode_min_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80119400; + slotbuf[1] = 0; +} + +static void +Opcode_min_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700100; +} + +static void +Opcode_min_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6b00001; + slotbuf[1] = 0; +} + +static void +Opcode_min_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05001d; +} + +static void +Opcode_min_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900380; +} + +static void +Opcode_min_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400f8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_max_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000003; + slotbuf[1] = 0x6; +} + +static void +Opcode_max_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205001c; + slotbuf[1] = 0x5; +} + +static void +Opcode_max_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80019400; + slotbuf[1] = 0; +} + +static void +Opcode_max_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000c0; +} + +static void +Opcode_max_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2b00001; + slotbuf[1] = 0; +} + +static void +Opcode_max_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05001c; +} + +static void +Opcode_max_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900340; +} + +static void +Opcode_max_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400e8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_minnum_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4100002; + slotbuf[1] = 0x6; +} + +static void +Opcode_minnum_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205801c; + slotbuf[1] = 0x5; +} + +static void +Opcode_minnum_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80111400; + slotbuf[1] = 0; +} + +static void +Opcode_minnum_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000e0; +} + +static void +Opcode_minnum_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4b00001; + slotbuf[1] = 0; +} + +static void +Opcode_minnum_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05801c; +} + +static void +Opcode_minnum_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900360; +} + +static void +Opcode_minnum_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400f0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_maxnum_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000002; + slotbuf[1] = 0x6; +} + +static void +Opcode_maxnum_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205801b; + slotbuf[1] = 0x5; +} + +static void +Opcode_maxnum_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80011400; + slotbuf[1] = 0; +} + +static void +Opcode_maxnum_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000a0; +} + +static void +Opcode_maxnum_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0b00001; + slotbuf[1] = 0; +} + +static void +Opcode_maxnum_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05801b; +} + +static void +Opcode_maxnum_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900320; +} + +static void +Opcode_maxnum_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400e0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_muljc_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808005; + slotbuf[1] = 0x7; +} + +static void +Opcode_muljc_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000b; + slotbuf[1] = 0x5; +} + +static void +Opcode_muljc_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d1800a; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80911801; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700209; +} + +static void +Opcode_muljc_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcac08001; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cb5801d; +} + +static void +Opcode_muljc_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa500027; +} + +static void +Opcode_muljc_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402a1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_neg_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800e; + slotbuf[1] = 0x7; +} + +static void +Opcode_neg_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160010; + slotbuf[1] = 0x5; +} + +static void +Opcode_neg_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03011; + slotbuf[1] = 0; +} + +static void +Opcode_neg_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80e11801; + slotbuf[1] = 0; +} + +static void +Opcode_neg_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020e; +} + +static void +Opcode_neg_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdcc08001; + slotbuf[1] = 0; +} + +static void +Opcode_neg_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d05801d; +} + +static void +Opcode_neg_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb158000; +} + +static void +Opcode_neg_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403b1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_oeq_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2e00; +} + +static void +Opcode_ole_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022300; +} + +static void +Opcode_olt_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022700; +} + +static void +Opcode_ueq_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022b00; +} + +static void +Opcode_ule_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022f00; +} + +static void +Opcode_ult_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2300; +} + +static void +Opcode_un_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2700; +} + +static void +Opcode_div0_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800027; +} + +static void +Opcode_ficeil_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19184030; + slotbuf[1] = 0; +} + +static void +Opcode_ficeil_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0430a; +} + +static void +Opcode_fifloor_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19186030; + slotbuf[1] = 0; +} + +static void +Opcode_fifloor_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0630a; +} + +static void +Opcode_firint_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1918c030; + slotbuf[1] = 0; +} + +static void +Opcode_firint_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0430b; +} + +static void +Opcode_firound_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1918e030; + slotbuf[1] = 0; +} + +static void +Opcode_firound_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0630b; +} + +static void +Opcode_fitrunc_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19194030; + slotbuf[1] = 0; +} + +static void +Opcode_fitrunc_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0020c; +} + +static void +Opcode_mkdadj_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb258000; +} + +static void +Opcode_mksadj_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa900024; +} + +static void +Opcode_nexp0_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa900026; +} + +static void +Opcode_nexp01_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa900025; +} + +static void +Opcode_recip0_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa900027; +} + +static void +Opcode_rsqrt0_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa00024; +} + +static void +Opcode_sqrt0_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa00025; +} + +static void +Opcode_float16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18980f00; + slotbuf[1] = 0; +} + +static void +Opcode_float16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c01200; +} + +static void +Opcode_ufloat16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x189a0f00; + slotbuf[1] = 0; +} + +static void +Opcode_ufloat16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c01240; +} + +static void +Opcode_trunc16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19300030; + slotbuf[1] = 0; +} + +static void +Opcode_trunc16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c01208; +} + +static void +Opcode_utrunc16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19320030; + slotbuf[1] = 0; +} + +static void +Opcode_utrunc16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c01608; +} + +static void +Opcode_float16_hx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d820000; + slotbuf[1] = 0; +} + +static void +Opcode_float16_hx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00200; +} + +static void +Opcode_ufloat16_hx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d820020; + slotbuf[1] = 0; +} + +static void +Opcode_ufloat16_hx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04200; +} + +static void +Opcode_trunc16_hx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d820010; + slotbuf[1] = 0; +} + +static void +Opcode_trunc16_hx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c02200; +} + +static void +Opcode_utrunc16_hx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d820030; + slotbuf[1] = 0; +} + +static void +Opcode_utrunc16_hx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c06200; +} + +static void +Opcode_add_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000001; + slotbuf[1] = 0x6; +} + +static void +Opcode_add_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000040; + slotbuf[1] = 0x5; +} + +static void +Opcode_add_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0118000; + slotbuf[1] = 0; +} + +static void +Opcode_add_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1838000; +} + +static void +Opcode_add_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000080; + slotbuf[1] = 0; +} + +static void +Opcode_add_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000040; +} + +static void +Opcode_add_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8148000; +} + +static void +Opcode_add_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_sub_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000a1; + slotbuf[1] = 0x6; +} + +static void +Opcode_sub_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000062; + slotbuf[1] = 0x5; +} + +static void +Opcode_sub_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc118000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1868000; +} + +static void +Opcode_sub_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000085; + slotbuf[1] = 0; +} + +static void +Opcode_sub_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000062; +} + +static void +Opcode_sub_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8178000; +} + +static void +Opcode_sub_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006062; + slotbuf[1] = 0xe; +} + +static void +Opcode_mul_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000081; + slotbuf[1] = 0x6; +} + +static void +Opcode_mul_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000042; + slotbuf[1] = 0x5; +} + +static void +Opcode_mul_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca118000; + slotbuf[1] = 0; +} + +static void +Opcode_mul_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1860000; +} + +static void +Opcode_mul_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000084; + slotbuf[1] = 0; +} + +static void +Opcode_mul_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000042; +} + +static void +Opcode_mul_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8170000; +} + +static void +Opcode_mul_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_madd_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000021; + slotbuf[1] = 0x6; +} + +static void +Opcode_madd_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000060; + slotbuf[1] = 0x5; +} + +static void +Opcode_madd_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6118000; + slotbuf[1] = 0; +} + +static void +Opcode_madd_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1850000; +} + +static void +Opcode_madd_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000081; + slotbuf[1] = 0; +} + +static void +Opcode_madd_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000060; +} + +static void +Opcode_madd_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8160000; +} + +static void +Opcode_madd_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005062; + slotbuf[1] = 0xe; +} + +static void +Opcode_msub_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000061; + slotbuf[1] = 0x6; +} + +static void +Opcode_msub_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000061; + slotbuf[1] = 0x5; +} + +static void +Opcode_msub_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8118000; + slotbuf[1] = 0; +} + +static void +Opcode_msub_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1858000; +} + +static void +Opcode_msub_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000083; + slotbuf[1] = 0; +} + +static void +Opcode_msub_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000061; +} + +static void +Opcode_msub_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8168000; +} + +static void +Opcode_msub_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005862; + slotbuf[1] = 0xe; +} + +static void +Opcode_maddn_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4118000; + slotbuf[1] = 0; +} + +static void +Opcode_maddn_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8158000; +} + +static void +Opcode_msubn_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000041; + slotbuf[1] = 0x6; +} + +static void +Opcode_msubn_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000041; + slotbuf[1] = 0x5; +} + +static void +Opcode_msubn_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000082; + slotbuf[1] = 0; +} + +static void +Opcode_msubn_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000041; +} + +static void +Opcode_msubn_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005462; + slotbuf[1] = 0xe; +} + +static void +Opcode_divn_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2118000; + slotbuf[1] = 0; +} + +static void +Opcode_divn_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8150000; +} + +static void +Opcode_rminnum_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1919e030; + slotbuf[1] = 0; +} + +static void +Opcode_rminnum_h_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540ae0; +} + +static void +Opcode_rminnum_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0620c; +} + +static void +Opcode_rmaxnum_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1919c030; + slotbuf[1] = 0; +} + +static void +Opcode_rmaxnum_h_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25406e0; +} + +static void +Opcode_rmaxnum_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0420c; +} + +static void +Opcode_abs_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_abs_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_abs_hx4x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_hx4x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80010000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_hx4x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000001; + slotbuf[1] = 0; +} + +static void +Opcode_abs_hx4x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000000; +} + +static void +Opcode_abs_hx4x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; +} + +static void +Opcode_abs_hx4x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40020002; + slotbuf[1] = 0xe; +} + +static void +Opcode_neg_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82600000; + slotbuf[1] = 0x7; +} + +static void +Opcode_neg_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82030000; + slotbuf[1] = 0x5; +} + +static void +Opcode_neg_hx4x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; + slotbuf[1] = 0; +} + +static void +Opcode_neg_hx4x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80010c00; + slotbuf[1] = 0; +} + +static void +Opcode_neg_hx4x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0600001; + slotbuf[1] = 0; +} + +static void +Opcode_neg_hx4x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c030000; +} + +static void +Opcode_neg_hx4x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000c0; +} + +static void +Opcode_neg_hx4x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40038002; + slotbuf[1] = 0xe; +} + +static void +Opcode_conjc_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82200000; + slotbuf[1] = 0x7; +} + +static void +Opcode_conjc_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82010000; + slotbuf[1] = 0x5; +} + +static void +Opcode_conjc_hx4x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_hx4x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80010400; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_hx4x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200001; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_hx4x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c010000; +} + +static void +Opcode_conjc_hx4x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000040; +} + +static void +Opcode_conjc_hx4x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40028002; + slotbuf[1] = 0xe; +} + +static void +Opcode_const_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82800000; + slotbuf[1] = 0x7; +} + +static void +Opcode_const_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82060000; + slotbuf[1] = 0x5; +} + +static void +Opcode_const_hx4x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00002; + slotbuf[1] = 0; +} + +static void +Opcode_const_hx4x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80011800; + slotbuf[1] = 0; +} + +static void +Opcode_const_hx4x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1904000; +} + +static void +Opcode_const_hx4x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c00001; + slotbuf[1] = 0; +} + +static void +Opcode_const_hx4x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c060000; +} + +static void +Opcode_const_hx4x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000020; +} + +static void +Opcode_const_hx4x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44000003; + slotbuf[1] = 0xe; +} + +static void +Opcode_muljc_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82400000; + slotbuf[1] = 0x7; +} + +static void +Opcode_muljc_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82020000; + slotbuf[1] = 0x5; +} + +static void +Opcode_muljc_hx4x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_hx4x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80010800; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_hx4x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0400001; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_hx4x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c020000; +} + +static void +Opcode_muljc_hx4x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000080; +} + +static void +Opcode_muljc_hx4x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40030002; + slotbuf[1] = 0xe; +} + +static void +Opcode_add_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_sub_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_mul_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4; +} + +static void +Opcode_mul_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_madd_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_madd_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_msub_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_msub_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_mulq_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulq_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulq_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a000000; + slotbuf[1] = 0; +} + +static void +Opcode_maddq_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x5; +} + +static void +Opcode_maddq_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulcnvh_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulcnvh_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulacnvh_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulacnvh_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulcnvl_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulcnvl_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulacnvl_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulacnvl_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40; + slotbuf[1] = 0x6; +} + +static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { + Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { + Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0, Opcode_addi_Slot_ae_slot0_encode, Opcode_addi_Slot_ae_slot1_encode, 0, 0, Opcode_addi_Slot_ae2_slot0_encode, Opcode_addi_Slot_ae2_slot1_encode, 0, Opcode_addi_Slot_ae3_slot0_encode, Opcode_addi_Slot_ae3_slot1_encode, Opcode_addi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addi_Slot_ae8_slot0_encode, Opcode_addi_Slot_ae8_slot1_encode, 0, Opcode_addi_Slot_ae9_slot0_encode, Opcode_addi_Slot_ae9_slot1_encode, 0, 0, Opcode_addi_Slot_ae10_slot0_encode, Opcode_addi_Slot_ae10_slot1_encode, 0, 0, Opcode_addi_Slot_ae4_slot0_encode, Opcode_addi_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0, Opcode_addmi_Slot_ae_slot0_encode, Opcode_addmi_Slot_ae_slot1_encode, 0, 0, Opcode_addmi_Slot_ae2_slot0_encode, Opcode_addmi_Slot_ae2_slot1_encode, 0, Opcode_addmi_Slot_ae3_slot0_encode, Opcode_addmi_Slot_ae3_slot1_encode, Opcode_addmi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addmi_Slot_ae8_slot0_encode, Opcode_addmi_Slot_ae8_slot1_encode, 0, Opcode_addmi_Slot_ae9_slot0_encode, Opcode_addmi_Slot_ae9_slot1_encode, 0, 0, Opcode_addmi_Slot_ae10_slot0_encode, Opcode_addmi_Slot_ae10_slot1_encode, 0, 0, Opcode_addmi_Slot_ae4_slot0_encode, Opcode_addmi_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0, Opcode_add_Slot_ae_slot0_encode, Opcode_add_Slot_ae_slot1_encode, 0, 0, Opcode_add_Slot_ae2_slot0_encode, Opcode_add_Slot_ae2_slot1_encode, 0, Opcode_add_Slot_ae3_slot0_encode, Opcode_add_Slot_ae3_slot1_encode, Opcode_add_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_Slot_ae8_slot0_encode, Opcode_add_Slot_ae8_slot1_encode, 0, Opcode_add_Slot_ae9_slot0_encode, Opcode_add_Slot_ae9_slot1_encode, 0, 0, Opcode_add_Slot_ae10_slot0_encode, Opcode_add_Slot_ae10_slot1_encode, 0, 0, Opcode_add_Slot_ae4_slot0_encode, Opcode_add_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0, Opcode_addx2_Slot_ae_slot0_encode, Opcode_addx2_Slot_ae_slot1_encode, 0, 0, Opcode_addx2_Slot_ae2_slot0_encode, Opcode_addx2_Slot_ae2_slot1_encode, 0, Opcode_addx2_Slot_ae3_slot0_encode, Opcode_addx2_Slot_ae3_slot1_encode, Opcode_addx2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addx2_Slot_ae8_slot0_encode, Opcode_addx2_Slot_ae8_slot1_encode, 0, Opcode_addx2_Slot_ae9_slot0_encode, Opcode_addx2_Slot_ae9_slot1_encode, 0, 0, Opcode_addx2_Slot_ae10_slot0_encode, Opcode_addx2_Slot_ae10_slot1_encode, 0, 0, Opcode_addx2_Slot_ae4_slot0_encode, Opcode_addx2_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0, Opcode_addx4_Slot_ae_slot0_encode, Opcode_addx4_Slot_ae_slot1_encode, 0, 0, Opcode_addx4_Slot_ae2_slot0_encode, Opcode_addx4_Slot_ae2_slot1_encode, 0, Opcode_addx4_Slot_ae3_slot0_encode, Opcode_addx4_Slot_ae3_slot1_encode, Opcode_addx4_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addx4_Slot_ae8_slot0_encode, Opcode_addx4_Slot_ae8_slot1_encode, 0, Opcode_addx4_Slot_ae9_slot0_encode, Opcode_addx4_Slot_ae9_slot1_encode, 0, 0, Opcode_addx4_Slot_ae10_slot0_encode, Opcode_addx4_Slot_ae10_slot1_encode, 0, 0, Opcode_addx4_Slot_ae4_slot0_encode, Opcode_addx4_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0, Opcode_addx8_Slot_ae_slot0_encode, Opcode_addx8_Slot_ae_slot1_encode, 0, 0, Opcode_addx8_Slot_ae2_slot0_encode, Opcode_addx8_Slot_ae2_slot1_encode, 0, Opcode_addx8_Slot_ae3_slot0_encode, Opcode_addx8_Slot_ae3_slot1_encode, Opcode_addx8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addx8_Slot_ae8_slot0_encode, Opcode_addx8_Slot_ae8_slot1_encode, 0, Opcode_addx8_Slot_ae9_slot0_encode, Opcode_addx8_Slot_ae9_slot1_encode, 0, 0, Opcode_addx8_Slot_ae10_slot0_encode, Opcode_addx8_Slot_ae10_slot1_encode, 0, 0, Opcode_addx8_Slot_ae4_slot0_encode, Opcode_addx8_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0, Opcode_sub_Slot_ae_slot0_encode, Opcode_sub_Slot_ae_slot1_encode, 0, 0, Opcode_sub_Slot_ae2_slot0_encode, Opcode_sub_Slot_ae2_slot1_encode, 0, Opcode_sub_Slot_ae3_slot0_encode, Opcode_sub_Slot_ae3_slot1_encode, Opcode_sub_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_Slot_ae8_slot0_encode, Opcode_sub_Slot_ae8_slot1_encode, 0, Opcode_sub_Slot_ae9_slot0_encode, Opcode_sub_Slot_ae9_slot1_encode, 0, 0, Opcode_sub_Slot_ae10_slot0_encode, Opcode_sub_Slot_ae10_slot1_encode, 0, 0, Opcode_sub_Slot_ae4_slot0_encode, Opcode_sub_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0, Opcode_subx2_Slot_ae_slot0_encode, Opcode_subx2_Slot_ae_slot1_encode, 0, 0, Opcode_subx2_Slot_ae2_slot0_encode, Opcode_subx2_Slot_ae2_slot1_encode, 0, Opcode_subx2_Slot_ae3_slot0_encode, Opcode_subx2_Slot_ae3_slot1_encode, Opcode_subx2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_subx2_Slot_ae8_slot0_encode, Opcode_subx2_Slot_ae8_slot1_encode, 0, Opcode_subx2_Slot_ae9_slot0_encode, Opcode_subx2_Slot_ae9_slot1_encode, 0, 0, Opcode_subx2_Slot_ae10_slot0_encode, Opcode_subx2_Slot_ae10_slot1_encode, 0, 0, Opcode_subx2_Slot_ae4_slot0_encode, Opcode_subx2_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0, Opcode_subx4_Slot_ae_slot0_encode, Opcode_subx4_Slot_ae_slot1_encode, 0, 0, Opcode_subx4_Slot_ae2_slot0_encode, Opcode_subx4_Slot_ae2_slot1_encode, 0, Opcode_subx4_Slot_ae3_slot0_encode, Opcode_subx4_Slot_ae3_slot1_encode, Opcode_subx4_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_subx4_Slot_ae8_slot0_encode, Opcode_subx4_Slot_ae8_slot1_encode, 0, Opcode_subx4_Slot_ae9_slot0_encode, Opcode_subx4_Slot_ae9_slot1_encode, 0, 0, Opcode_subx4_Slot_ae10_slot0_encode, Opcode_subx4_Slot_ae10_slot1_encode, 0, 0, Opcode_subx4_Slot_ae4_slot0_encode, Opcode_subx4_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0, Opcode_subx8_Slot_ae_slot0_encode, Opcode_subx8_Slot_ae_slot1_encode, 0, 0, Opcode_subx8_Slot_ae2_slot0_encode, Opcode_subx8_Slot_ae2_slot1_encode, 0, Opcode_subx8_Slot_ae3_slot0_encode, Opcode_subx8_Slot_ae3_slot1_encode, Opcode_subx8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_subx8_Slot_ae8_slot0_encode, Opcode_subx8_Slot_ae8_slot1_encode, 0, Opcode_subx8_Slot_ae9_slot0_encode, Opcode_subx8_Slot_ae9_slot1_encode, 0, 0, Opcode_subx8_Slot_ae10_slot0_encode, Opcode_subx8_Slot_ae10_slot1_encode, 0, 0, Opcode_subx8_Slot_ae4_slot0_encode, Opcode_subx8_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0, Opcode_and_Slot_ae_slot0_encode, Opcode_and_Slot_ae_slot1_encode, 0, 0, Opcode_and_Slot_ae2_slot0_encode, Opcode_and_Slot_ae2_slot1_encode, 0, Opcode_and_Slot_ae3_slot0_encode, Opcode_and_Slot_ae3_slot1_encode, Opcode_and_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_and_Slot_ae8_slot0_encode, Opcode_and_Slot_ae8_slot1_encode, 0, Opcode_and_Slot_ae9_slot0_encode, Opcode_and_Slot_ae9_slot1_encode, 0, 0, Opcode_and_Slot_ae10_slot0_encode, Opcode_and_Slot_ae10_slot1_encode, 0, 0, Opcode_and_Slot_ae4_slot0_encode, Opcode_and_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0, Opcode_or_Slot_ae_slot0_encode, Opcode_or_Slot_ae_slot1_encode, 0, 0, Opcode_or_Slot_ae2_slot0_encode, Opcode_or_Slot_ae2_slot1_encode, 0, Opcode_or_Slot_ae3_slot0_encode, Opcode_or_Slot_ae3_slot1_encode, Opcode_or_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_or_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_or_Slot_ae8_slot0_encode, Opcode_or_Slot_ae8_slot1_encode, 0, Opcode_or_Slot_ae9_slot0_encode, Opcode_or_Slot_ae9_slot1_encode, 0, 0, Opcode_or_Slot_ae10_slot0_encode, Opcode_or_Slot_ae10_slot1_encode, 0, 0, Opcode_or_Slot_ae4_slot0_encode, Opcode_or_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0, Opcode_xor_Slot_ae_slot0_encode, Opcode_xor_Slot_ae_slot1_encode, 0, 0, Opcode_xor_Slot_ae2_slot0_encode, Opcode_xor_Slot_ae2_slot1_encode, 0, Opcode_xor_Slot_ae3_slot0_encode, Opcode_xor_Slot_ae3_slot1_encode, Opcode_xor_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_xor_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_xor_Slot_ae8_slot0_encode, Opcode_xor_Slot_ae8_slot1_encode, 0, Opcode_xor_Slot_ae9_slot0_encode, Opcode_xor_Slot_ae9_slot1_encode, 0, 0, Opcode_xor_Slot_ae10_slot0_encode, Opcode_xor_Slot_ae10_slot1_encode, 0, 0, Opcode_xor_Slot_ae4_slot0_encode, Opcode_xor_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0, Opcode_call0_Slot_ae_slot0_encode, 0, 0, 0, Opcode_call0_Slot_ae2_slot0_encode, 0, 0, Opcode_call0_Slot_ae3_slot0_encode, 0, Opcode_call0_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_call0_Slot_ae8_slot0_encode, 0, 0, Opcode_call0_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_call0_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_call0_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0, Opcode_callx0_Slot_ae_slot0_encode, 0, 0, 0, Opcode_callx0_Slot_ae2_slot0_encode, 0, 0, Opcode_callx0_Slot_ae3_slot0_encode, 0, Opcode_callx0_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_callx0_Slot_ae8_slot0_encode, 0, 0, Opcode_callx0_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_callx0_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_callx0_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0, Opcode_extui_Slot_ae_slot0_encode, Opcode_extui_Slot_ae_slot1_encode, 0, 0, Opcode_extui_Slot_ae2_slot0_encode, Opcode_extui_Slot_ae2_slot1_encode, 0, Opcode_extui_Slot_ae3_slot0_encode, Opcode_extui_Slot_ae3_slot1_encode, Opcode_extui_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_extui_Slot_ae8_slot0_encode, Opcode_extui_Slot_ae8_slot1_encode, 0, Opcode_extui_Slot_ae9_slot0_encode, Opcode_extui_Slot_ae9_slot1_encode, 0, 0, Opcode_extui_Slot_ae10_slot0_encode, Opcode_extui_Slot_ae10_slot1_encode, 0, 0, Opcode_extui_Slot_ae4_slot0_encode, Opcode_extui_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0, Opcode_j_Slot_ae_slot0_encode, 0, 0, 0, Opcode_j_Slot_ae2_slot0_encode, 0, 0, Opcode_j_Slot_ae3_slot0_encode, 0, Opcode_j_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_j_Slot_ae8_slot0_encode, 0, 0, Opcode_j_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_j_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_j_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0, Opcode_jx_Slot_ae_slot0_encode, 0, 0, 0, Opcode_jx_Slot_ae2_slot0_encode, 0, 0, Opcode_jx_Slot_ae3_slot0_encode, 0, Opcode_jx_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_jx_Slot_ae8_slot0_encode, 0, 0, Opcode_jx_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_jx_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_jx_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode, Opcode_l16ui_Slot_ae_slot1_encode, 0, 0, Opcode_l16ui_Slot_ae2_slot0_encode, Opcode_l16ui_Slot_ae2_slot1_encode, 0, Opcode_l16ui_Slot_ae3_slot0_encode, Opcode_l16ui_Slot_ae3_slot1_encode, Opcode_l16ui_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l16ui_Slot_ae8_slot0_encode, Opcode_l16ui_Slot_ae8_slot1_encode, 0, Opcode_l16ui_Slot_ae9_slot0_encode, Opcode_l16ui_Slot_ae9_slot1_encode, 0, 0, Opcode_l16ui_Slot_ae10_slot0_encode, Opcode_l16ui_Slot_ae10_slot1_encode, 0, 0, Opcode_l16ui_Slot_ae4_slot0_encode, Opcode_l16ui_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0, Opcode_l16si_Slot_ae_slot0_encode, Opcode_l16si_Slot_ae_slot1_encode, 0, 0, Opcode_l16si_Slot_ae2_slot0_encode, Opcode_l16si_Slot_ae2_slot1_encode, 0, Opcode_l16si_Slot_ae3_slot0_encode, Opcode_l16si_Slot_ae3_slot1_encode, Opcode_l16si_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l16si_Slot_ae8_slot0_encode, Opcode_l16si_Slot_ae8_slot1_encode, 0, Opcode_l16si_Slot_ae9_slot0_encode, Opcode_l16si_Slot_ae9_slot1_encode, 0, 0, Opcode_l16si_Slot_ae10_slot0_encode, Opcode_l16si_Slot_ae10_slot1_encode, 0, 0, Opcode_l16si_Slot_ae4_slot0_encode, Opcode_l16si_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0, Opcode_l32i_Slot_ae_slot0_encode, Opcode_l32i_Slot_ae_slot1_encode, 0, 0, Opcode_l32i_Slot_ae2_slot0_encode, Opcode_l32i_Slot_ae2_slot1_encode, 0, Opcode_l32i_Slot_ae3_slot0_encode, Opcode_l32i_Slot_ae3_slot1_encode, Opcode_l32i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l32i_Slot_ae8_slot0_encode, Opcode_l32i_Slot_ae8_slot1_encode, 0, Opcode_l32i_Slot_ae9_slot0_encode, Opcode_l32i_Slot_ae9_slot1_encode, 0, 0, Opcode_l32i_Slot_ae10_slot0_encode, Opcode_l32i_Slot_ae10_slot1_encode, 0, 0, Opcode_l32i_Slot_ae4_slot0_encode, Opcode_l32i_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0, Opcode_l32r_Slot_ae_slot0_encode, 0, 0, 0, Opcode_l32r_Slot_ae2_slot0_encode, 0, 0, Opcode_l32r_Slot_ae3_slot0_encode, 0, Opcode_l32r_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l32r_Slot_ae8_slot0_encode, 0, 0, Opcode_l32r_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_l32r_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_l32r_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode, Opcode_l8ui_Slot_ae_slot1_encode, 0, 0, Opcode_l8ui_Slot_ae2_slot0_encode, Opcode_l8ui_Slot_ae2_slot1_encode, 0, Opcode_l8ui_Slot_ae3_slot0_encode, Opcode_l8ui_Slot_ae3_slot1_encode, Opcode_l8ui_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l8ui_Slot_ae8_slot0_encode, Opcode_l8ui_Slot_ae8_slot1_encode, 0, Opcode_l8ui_Slot_ae9_slot0_encode, Opcode_l8ui_Slot_ae9_slot1_encode, 0, 0, Opcode_l8ui_Slot_ae10_slot0_encode, Opcode_l8ui_Slot_ae10_slot1_encode, 0, 0, Opcode_l8ui_Slot_ae4_slot0_encode, Opcode_l8ui_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { + Opcode_loop_Slot_inst_encode, 0, 0, Opcode_loop_Slot_ae_slot0_encode, 0, 0, 0, Opcode_loop_Slot_ae2_slot0_encode, 0, 0, Opcode_loop_Slot_ae3_slot0_encode, 0, Opcode_loop_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_loop_Slot_ae8_slot0_encode, 0, 0, Opcode_loop_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_loop_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_loop_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { + Opcode_loopgtz_Slot_inst_encode, 0, 0, Opcode_loopgtz_Slot_ae_slot0_encode, 0, 0, 0, Opcode_loopgtz_Slot_ae2_slot0_encode, 0, 0, Opcode_loopgtz_Slot_ae3_slot0_encode, 0, Opcode_loopgtz_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_loopgtz_Slot_ae8_slot0_encode, 0, 0, Opcode_loopgtz_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_loopgtz_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_loopgtz_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { + Opcode_loopnez_Slot_inst_encode, 0, 0, Opcode_loopnez_Slot_ae_slot0_encode, 0, 0, 0, Opcode_loopnez_Slot_ae2_slot0_encode, 0, 0, Opcode_loopnez_Slot_ae3_slot0_encode, 0, Opcode_loopnez_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_loopnez_Slot_ae8_slot0_encode, 0, 0, Opcode_loopnez_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_loopnez_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_loopnez_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0, Opcode_movi_Slot_ae_slot0_encode, Opcode_movi_Slot_ae_slot1_encode, 0, 0, Opcode_movi_Slot_ae2_slot0_encode, Opcode_movi_Slot_ae2_slot1_encode, 0, Opcode_movi_Slot_ae3_slot0_encode, Opcode_movi_Slot_ae3_slot1_encode, Opcode_movi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movi_Slot_ae8_slot0_encode, Opcode_movi_Slot_ae8_slot1_encode, 0, Opcode_movi_Slot_ae9_slot0_encode, Opcode_movi_Slot_ae9_slot1_encode, 0, 0, Opcode_movi_Slot_ae10_slot0_encode, Opcode_movi_Slot_ae10_slot1_encode, 0, 0, Opcode_movi_Slot_ae4_slot0_encode, Opcode_movi_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode, Opcode_moveqz_Slot_ae_slot1_encode, 0, 0, Opcode_moveqz_Slot_ae2_slot0_encode, Opcode_moveqz_Slot_ae2_slot1_encode, 0, Opcode_moveqz_Slot_ae3_slot0_encode, Opcode_moveqz_Slot_ae3_slot1_encode, Opcode_moveqz_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_moveqz_Slot_ae8_slot0_encode, Opcode_moveqz_Slot_ae8_slot1_encode, 0, Opcode_moveqz_Slot_ae9_slot0_encode, Opcode_moveqz_Slot_ae9_slot1_encode, 0, 0, Opcode_moveqz_Slot_ae10_slot0_encode, Opcode_moveqz_Slot_ae10_slot1_encode, 0, 0, Opcode_moveqz_Slot_ae4_slot0_encode, Opcode_moveqz_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0, Opcode_movgez_Slot_ae_slot0_encode, Opcode_movgez_Slot_ae_slot1_encode, 0, 0, Opcode_movgez_Slot_ae2_slot0_encode, Opcode_movgez_Slot_ae2_slot1_encode, 0, Opcode_movgez_Slot_ae3_slot0_encode, Opcode_movgez_Slot_ae3_slot1_encode, Opcode_movgez_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movgez_Slot_ae8_slot0_encode, Opcode_movgez_Slot_ae8_slot1_encode, 0, Opcode_movgez_Slot_ae9_slot0_encode, Opcode_movgez_Slot_ae9_slot1_encode, 0, 0, Opcode_movgez_Slot_ae10_slot0_encode, Opcode_movgez_Slot_ae10_slot1_encode, 0, 0, Opcode_movgez_Slot_ae4_slot0_encode, Opcode_movgez_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0, Opcode_movltz_Slot_ae_slot0_encode, Opcode_movltz_Slot_ae_slot1_encode, 0, 0, Opcode_movltz_Slot_ae2_slot0_encode, Opcode_movltz_Slot_ae2_slot1_encode, 0, Opcode_movltz_Slot_ae3_slot0_encode, Opcode_movltz_Slot_ae3_slot1_encode, Opcode_movltz_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movltz_Slot_ae8_slot0_encode, Opcode_movltz_Slot_ae8_slot1_encode, 0, Opcode_movltz_Slot_ae9_slot0_encode, Opcode_movltz_Slot_ae9_slot1_encode, 0, 0, Opcode_movltz_Slot_ae10_slot0_encode, Opcode_movltz_Slot_ae10_slot1_encode, 0, 0, Opcode_movltz_Slot_ae4_slot0_encode, Opcode_movltz_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0, Opcode_movnez_Slot_ae_slot0_encode, Opcode_movnez_Slot_ae_slot1_encode, 0, 0, Opcode_movnez_Slot_ae2_slot0_encode, Opcode_movnez_Slot_ae2_slot1_encode, 0, Opcode_movnez_Slot_ae3_slot0_encode, Opcode_movnez_Slot_ae3_slot1_encode, Opcode_movnez_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movnez_Slot_ae8_slot0_encode, Opcode_movnez_Slot_ae8_slot1_encode, 0, Opcode_movnez_Slot_ae9_slot0_encode, Opcode_movnez_Slot_ae9_slot1_encode, 0, 0, Opcode_movnez_Slot_ae10_slot0_encode, Opcode_movnez_Slot_ae10_slot1_encode, 0, 0, Opcode_movnez_Slot_ae4_slot0_encode, Opcode_movnez_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0, Opcode_abs_Slot_ae_slot0_encode, Opcode_abs_Slot_ae_slot1_encode, 0, 0, Opcode_abs_Slot_ae2_slot0_encode, Opcode_abs_Slot_ae2_slot1_encode, 0, Opcode_abs_Slot_ae3_slot0_encode, Opcode_abs_Slot_ae3_slot1_encode, Opcode_abs_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_abs_Slot_ae8_slot0_encode, Opcode_abs_Slot_ae8_slot1_encode, 0, Opcode_abs_Slot_ae9_slot0_encode, Opcode_abs_Slot_ae9_slot1_encode, 0, 0, Opcode_abs_Slot_ae10_slot0_encode, Opcode_abs_Slot_ae10_slot1_encode, 0, 0, Opcode_abs_Slot_ae4_slot0_encode, Opcode_abs_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0, Opcode_neg_Slot_ae_slot0_encode, Opcode_neg_Slot_ae_slot1_encode, 0, 0, Opcode_neg_Slot_ae2_slot0_encode, Opcode_neg_Slot_ae2_slot1_encode, 0, Opcode_neg_Slot_ae3_slot0_encode, Opcode_neg_Slot_ae3_slot1_encode, Opcode_neg_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_neg_Slot_ae8_slot0_encode, Opcode_neg_Slot_ae8_slot1_encode, 0, Opcode_neg_Slot_ae9_slot0_encode, Opcode_neg_Slot_ae9_slot1_encode, 0, 0, Opcode_neg_Slot_ae10_slot0_encode, Opcode_neg_Slot_ae10_slot1_encode, 0, 0, Opcode_neg_Slot_ae4_slot0_encode, Opcode_neg_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot0_encode, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot2_encode, Opcode_nop_Slot_ae_slot3_encode, Opcode_nop_Slot_ae2_slot0_encode, Opcode_nop_Slot_ae2_slot1_encode, Opcode_nop_Slot_ae2_slot2_encode, Opcode_nop_Slot_ae3_slot0_encode, Opcode_nop_Slot_ae3_slot1_encode, Opcode_nop_Slot_ae5_slot0_encode, Opcode_nop_Slot_ae5_slot1_encode, Opcode_nop_Slot_ae5_slot2_encode, Opcode_nop_Slot_ae6_slot0_encode, Opcode_nop_Slot_ae6_slot1_encode, Opcode_nop_Slot_ae6_slot2_encode, Opcode_nop_Slot_ae6_slot3_encode, Opcode_nop_Slot_ae7_slot0_encode, Opcode_nop_Slot_ae7_slot1_encode, Opcode_nop_Slot_ae7_slot2_encode, Opcode_nop_Slot_ae7_slot3_encode, Opcode_nop_Slot_ae8_slot0_encode, Opcode_nop_Slot_ae8_slot1_encode, Opcode_nop_Slot_ae8_slot2_encode, Opcode_nop_Slot_ae9_slot0_encode, Opcode_nop_Slot_ae9_slot1_encode, Opcode_nop_Slot_ae9_slot2_encode, Opcode_nop_Slot_ae9_slot3_encode, Opcode_nop_Slot_ae10_slot0_encode, Opcode_nop_Slot_ae10_slot1_encode, Opcode_nop_Slot_ae10_slot2_encode, Opcode_nop_Slot_ae10_slot3_encode, Opcode_nop_Slot_ae4_slot0_encode, Opcode_nop_Slot_ae4_slot1_encode, Opcode_nop_Slot_ae4_slot2_encode, Opcode_nop_Slot_ae4_slot3_encode, Opcode_nop_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32ex_encode_fns[] = { + Opcode_l32ex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32ex_encode_fns[] = { + Opcode_s32ex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_getex_encode_fns[] = { + Opcode_getex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clrex_encode_fns[] = { + Opcode_clrex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0, Opcode_ret_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ret_Slot_ae2_slot0_encode, 0, 0, Opcode_ret_Slot_ae3_slot0_encode, 0, Opcode_ret_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ret_Slot_ae8_slot0_encode, 0, 0, Opcode_ret_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_ret_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_ret_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0, Opcode_s16i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_s16i_Slot_ae2_slot0_encode, 0, 0, Opcode_s16i_Slot_ae3_slot0_encode, 0, Opcode_s16i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s16i_Slot_ae8_slot0_encode, 0, 0, Opcode_s16i_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_s16i_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_s16i_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0, Opcode_s32i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_s32i_Slot_ae2_slot0_encode, 0, 0, Opcode_s32i_Slot_ae3_slot0_encode, 0, Opcode_s32i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s32i_Slot_ae8_slot0_encode, 0, 0, Opcode_s32i_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_s32i_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_s32i_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = { + Opcode_s32nb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0, Opcode_s8i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_s8i_Slot_ae2_slot0_encode, 0, 0, Opcode_s8i_Slot_ae3_slot0_encode, 0, Opcode_s8i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s8i_Slot_ae8_slot0_encode, 0, 0, Opcode_s8i_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_s8i_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_s8i_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode, Opcode_ssa8b_Slot_ae_slot1_encode, 0, 0, Opcode_ssa8b_Slot_ae2_slot0_encode, Opcode_ssa8b_Slot_ae2_slot1_encode, 0, Opcode_ssa8b_Slot_ae3_slot0_encode, Opcode_ssa8b_Slot_ae3_slot1_encode, Opcode_ssa8b_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssa8b_Slot_ae8_slot0_encode, Opcode_ssa8b_Slot_ae8_slot1_encode, 0, Opcode_ssa8b_Slot_ae9_slot0_encode, Opcode_ssa8b_Slot_ae9_slot1_encode, 0, 0, Opcode_ssa8b_Slot_ae10_slot0_encode, Opcode_ssa8b_Slot_ae10_slot1_encode, 0, 0, Opcode_ssa8b_Slot_ae4_slot0_encode, Opcode_ssa8b_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode, Opcode_ssa8l_Slot_ae_slot1_encode, 0, 0, Opcode_ssa8l_Slot_ae2_slot0_encode, Opcode_ssa8l_Slot_ae2_slot1_encode, 0, Opcode_ssa8l_Slot_ae3_slot0_encode, Opcode_ssa8l_Slot_ae3_slot1_encode, Opcode_ssa8l_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssa8l_Slot_ae8_slot0_encode, Opcode_ssa8l_Slot_ae8_slot1_encode, 0, Opcode_ssa8l_Slot_ae9_slot0_encode, Opcode_ssa8l_Slot_ae9_slot1_encode, 0, 0, Opcode_ssa8l_Slot_ae10_slot0_encode, Opcode_ssa8l_Slot_ae10_slot1_encode, 0, 0, Opcode_ssa8l_Slot_ae4_slot0_encode, Opcode_ssa8l_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0, Opcode_ssl_Slot_ae_slot0_encode, Opcode_ssl_Slot_ae_slot1_encode, 0, 0, Opcode_ssl_Slot_ae2_slot0_encode, Opcode_ssl_Slot_ae2_slot1_encode, 0, Opcode_ssl_Slot_ae3_slot0_encode, Opcode_ssl_Slot_ae3_slot1_encode, Opcode_ssl_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssl_Slot_ae8_slot0_encode, Opcode_ssl_Slot_ae8_slot1_encode, 0, Opcode_ssl_Slot_ae9_slot0_encode, Opcode_ssl_Slot_ae9_slot1_encode, 0, 0, Opcode_ssl_Slot_ae10_slot0_encode, Opcode_ssl_Slot_ae10_slot1_encode, 0, 0, Opcode_ssl_Slot_ae4_slot0_encode, Opcode_ssl_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0, Opcode_ssr_Slot_ae_slot0_encode, Opcode_ssr_Slot_ae_slot1_encode, 0, 0, Opcode_ssr_Slot_ae2_slot0_encode, Opcode_ssr_Slot_ae2_slot1_encode, 0, Opcode_ssr_Slot_ae3_slot0_encode, Opcode_ssr_Slot_ae3_slot1_encode, Opcode_ssr_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssr_Slot_ae8_slot0_encode, Opcode_ssr_Slot_ae8_slot1_encode, 0, Opcode_ssr_Slot_ae9_slot0_encode, Opcode_ssr_Slot_ae9_slot1_encode, 0, 0, Opcode_ssr_Slot_ae10_slot0_encode, Opcode_ssr_Slot_ae10_slot1_encode, 0, 0, Opcode_ssr_Slot_ae4_slot0_encode, Opcode_ssr_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0, Opcode_ssai_Slot_ae_slot0_encode, Opcode_ssai_Slot_ae_slot1_encode, 0, 0, Opcode_ssai_Slot_ae2_slot0_encode, Opcode_ssai_Slot_ae2_slot1_encode, 0, Opcode_ssai_Slot_ae3_slot0_encode, Opcode_ssai_Slot_ae3_slot1_encode, Opcode_ssai_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssai_Slot_ae8_slot0_encode, Opcode_ssai_Slot_ae8_slot1_encode, 0, Opcode_ssai_Slot_ae9_slot0_encode, Opcode_ssai_Slot_ae9_slot1_encode, 0, 0, Opcode_ssai_Slot_ae10_slot0_encode, Opcode_ssai_Slot_ae10_slot1_encode, 0, 0, Opcode_ssai_Slot_ae4_slot0_encode, Opcode_ssai_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0, Opcode_sll_Slot_ae_slot0_encode, Opcode_sll_Slot_ae_slot1_encode, 0, 0, Opcode_sll_Slot_ae2_slot0_encode, Opcode_sll_Slot_ae2_slot1_encode, 0, Opcode_sll_Slot_ae3_slot0_encode, Opcode_sll_Slot_ae3_slot1_encode, Opcode_sll_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sll_Slot_ae8_slot0_encode, Opcode_sll_Slot_ae8_slot1_encode, 0, Opcode_sll_Slot_ae9_slot0_encode, Opcode_sll_Slot_ae9_slot1_encode, 0, 0, Opcode_sll_Slot_ae10_slot0_encode, Opcode_sll_Slot_ae10_slot1_encode, 0, 0, Opcode_sll_Slot_ae4_slot0_encode, Opcode_sll_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0, Opcode_src_Slot_ae_slot0_encode, Opcode_src_Slot_ae_slot1_encode, 0, 0, Opcode_src_Slot_ae2_slot0_encode, Opcode_src_Slot_ae2_slot1_encode, 0, Opcode_src_Slot_ae3_slot0_encode, Opcode_src_Slot_ae3_slot1_encode, Opcode_src_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_src_Slot_ae8_slot0_encode, Opcode_src_Slot_ae8_slot1_encode, 0, Opcode_src_Slot_ae9_slot0_encode, Opcode_src_Slot_ae9_slot1_encode, 0, 0, Opcode_src_Slot_ae10_slot0_encode, Opcode_src_Slot_ae10_slot1_encode, 0, 0, Opcode_src_Slot_ae4_slot0_encode, Opcode_src_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0, Opcode_sra_Slot_ae_slot0_encode, Opcode_sra_Slot_ae_slot1_encode, 0, 0, Opcode_sra_Slot_ae2_slot0_encode, Opcode_sra_Slot_ae2_slot1_encode, 0, Opcode_sra_Slot_ae3_slot0_encode, Opcode_sra_Slot_ae3_slot1_encode, Opcode_sra_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sra_Slot_ae8_slot0_encode, Opcode_sra_Slot_ae8_slot1_encode, 0, Opcode_sra_Slot_ae9_slot0_encode, Opcode_sra_Slot_ae9_slot1_encode, 0, 0, Opcode_sra_Slot_ae10_slot0_encode, Opcode_sra_Slot_ae10_slot1_encode, 0, 0, Opcode_sra_Slot_ae4_slot0_encode, Opcode_sra_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0, Opcode_srl_Slot_ae_slot0_encode, Opcode_srl_Slot_ae_slot1_encode, 0, 0, Opcode_srl_Slot_ae2_slot0_encode, Opcode_srl_Slot_ae2_slot1_encode, 0, Opcode_srl_Slot_ae3_slot0_encode, Opcode_srl_Slot_ae3_slot1_encode, Opcode_srl_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_srl_Slot_ae8_slot0_encode, Opcode_srl_Slot_ae8_slot1_encode, 0, Opcode_srl_Slot_ae9_slot0_encode, Opcode_srl_Slot_ae9_slot1_encode, 0, 0, Opcode_srl_Slot_ae10_slot0_encode, Opcode_srl_Slot_ae10_slot1_encode, 0, 0, Opcode_srl_Slot_ae4_slot0_encode, Opcode_srl_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0, Opcode_slli_Slot_ae_slot0_encode, Opcode_slli_Slot_ae_slot1_encode, 0, 0, Opcode_slli_Slot_ae2_slot0_encode, Opcode_slli_Slot_ae2_slot1_encode, 0, Opcode_slli_Slot_ae3_slot0_encode, Opcode_slli_Slot_ae3_slot1_encode, Opcode_slli_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_slli_Slot_ae8_slot0_encode, Opcode_slli_Slot_ae8_slot1_encode, 0, Opcode_slli_Slot_ae9_slot0_encode, Opcode_slli_Slot_ae9_slot1_encode, 0, 0, Opcode_slli_Slot_ae10_slot0_encode, Opcode_slli_Slot_ae10_slot1_encode, 0, 0, Opcode_slli_Slot_ae4_slot0_encode, Opcode_slli_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0, Opcode_srai_Slot_ae_slot0_encode, Opcode_srai_Slot_ae_slot1_encode, 0, 0, Opcode_srai_Slot_ae2_slot0_encode, Opcode_srai_Slot_ae2_slot1_encode, 0, Opcode_srai_Slot_ae3_slot0_encode, Opcode_srai_Slot_ae3_slot1_encode, Opcode_srai_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_srai_Slot_ae8_slot0_encode, Opcode_srai_Slot_ae8_slot1_encode, 0, Opcode_srai_Slot_ae9_slot0_encode, Opcode_srai_Slot_ae9_slot1_encode, 0, 0, Opcode_srai_Slot_ae10_slot0_encode, Opcode_srai_Slot_ae10_slot1_encode, 0, 0, Opcode_srai_Slot_ae4_slot0_encode, Opcode_srai_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0, Opcode_srli_Slot_ae_slot0_encode, Opcode_srli_Slot_ae_slot1_encode, 0, 0, Opcode_srli_Slot_ae2_slot0_encode, Opcode_srli_Slot_ae2_slot1_encode, 0, Opcode_srli_Slot_ae3_slot0_encode, Opcode_srli_Slot_ae3_slot1_encode, Opcode_srli_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_srli_Slot_ae8_slot0_encode, Opcode_srli_Slot_ae8_slot1_encode, 0, Opcode_srli_Slot_ae9_slot0_encode, Opcode_srli_Slot_ae9_slot1_encode, 0, 0, Opcode_srli_Slot_ae10_slot0_encode, Opcode_srli_Slot_ae10_slot1_encode, 0, 0, Opcode_srli_Slot_ae4_slot0_encode, Opcode_srli_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { + Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { + Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { + Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { + Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { + Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { + Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = { + Opcode_rsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = { + Opcode_wsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = { + Opcode_xsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { + Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { + Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { + Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { + Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { + Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { + Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { + Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { + Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { + Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { + Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { + Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { + Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { + Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { + Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { + Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { + Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { + Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { + Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { + Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { + Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { + Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { + Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { + Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { + Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { + Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { + Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { + Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { + Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { + Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { + Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { + Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { + Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { + Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { + Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { + Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { + Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { + Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { + Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { + Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc2_encode_fns[] = { + Opcode_rsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc2_encode_fns[] = { + Opcode_wsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc2_encode_fns[] = { + Opcode_xsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc3_encode_fns[] = { + Opcode_rsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc3_encode_fns[] = { + Opcode_wsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc3_encode_fns[] = { + Opcode_xsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_mpucfg_encode_fns[] = { + Opcode_rsr_mpucfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mpucfg_encode_fns[] = { + Opcode_wsr_mpucfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_salt_encode_fns[] = { + Opcode_salt_Slot_inst_encode, 0, 0, Opcode_salt_Slot_ae_slot0_encode, Opcode_salt_Slot_ae_slot1_encode, 0, 0, Opcode_salt_Slot_ae2_slot0_encode, Opcode_salt_Slot_ae2_slot1_encode, 0, Opcode_salt_Slot_ae3_slot0_encode, Opcode_salt_Slot_ae3_slot1_encode, Opcode_salt_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_salt_Slot_ae8_slot0_encode, Opcode_salt_Slot_ae8_slot1_encode, 0, Opcode_salt_Slot_ae9_slot0_encode, Opcode_salt_Slot_ae9_slot1_encode, 0, 0, Opcode_salt_Slot_ae10_slot0_encode, Opcode_salt_Slot_ae10_slot1_encode, 0, 0, Opcode_salt_Slot_ae4_slot0_encode, Opcode_salt_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_saltu_encode_fns[] = { + Opcode_saltu_Slot_inst_encode, 0, 0, Opcode_saltu_Slot_ae_slot0_encode, Opcode_saltu_Slot_ae_slot1_encode, 0, 0, Opcode_saltu_Slot_ae2_slot0_encode, Opcode_saltu_Slot_ae2_slot1_encode, 0, Opcode_saltu_Slot_ae3_slot0_encode, Opcode_saltu_Slot_ae3_slot1_encode, Opcode_saltu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_saltu_Slot_ae8_slot0_encode, Opcode_saltu_Slot_ae8_slot1_encode, 0, Opcode_saltu_Slot_ae9_slot0_encode, Opcode_saltu_Slot_ae9_slot1_encode, 0, 0, Opcode_saltu_Slot_ae10_slot0_encode, Opcode_saltu_Slot_ae10_slot1_encode, 0, 0, Opcode_saltu_Slot_ae4_slot0_encode, Opcode_saltu_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_opmode_encode_fns[] = { + Opcode_rsr_opmode_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_opmode_encode_fns[] = { + Opcode_wsr_opmode_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_opmode_encode_fns[] = { + Opcode_xsr_opmode_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { + Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { + Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { + Opcode_mull_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = { + Opcode_lddr32_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = { + Opcode_sddr32_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { + Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { + Opcode_andb_Slot_inst_encode, 0, 0, Opcode_andb_Slot_ae_slot0_encode, 0, 0, 0, Opcode_andb_Slot_ae2_slot0_encode, 0, 0, Opcode_andb_Slot_ae3_slot0_encode, 0, Opcode_andb_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_andb_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_andb_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_andb_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { + Opcode_andbc_Slot_inst_encode, 0, 0, Opcode_andbc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_andbc_Slot_ae2_slot0_encode, 0, 0, Opcode_andbc_Slot_ae3_slot0_encode, 0, Opcode_andbc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_andbc_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_andbc_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_andbc_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { + Opcode_orb_Slot_inst_encode, 0, 0, Opcode_orb_Slot_ae_slot0_encode, 0, 0, 0, Opcode_orb_Slot_ae2_slot0_encode, 0, 0, Opcode_orb_Slot_ae3_slot0_encode, 0, Opcode_orb_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_orb_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_orb_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_orb_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { + Opcode_orbc_Slot_inst_encode, 0, 0, Opcode_orbc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_orbc_Slot_ae2_slot0_encode, 0, 0, Opcode_orbc_Slot_ae3_slot0_encode, 0, Opcode_orbc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_orbc_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_orbc_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_orbc_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { + Opcode_xorb_Slot_inst_encode, 0, 0, Opcode_xorb_Slot_ae_slot0_encode, 0, 0, 0, Opcode_xorb_Slot_ae2_slot0_encode, 0, 0, Opcode_xorb_Slot_ae3_slot0_encode, 0, Opcode_xorb_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_xorb_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_xorb_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_xorb_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { + Opcode_all4_Slot_inst_encode, 0, 0, Opcode_all4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_all4_Slot_ae2_slot0_encode, 0, 0, Opcode_all4_Slot_ae3_slot0_encode, 0, Opcode_all4_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_all4_Slot_ae8_slot0_encode, 0, 0, Opcode_all4_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_all4_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_all4_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { + Opcode_any4_Slot_inst_encode, 0, 0, Opcode_any4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_any4_Slot_ae2_slot0_encode, 0, 0, Opcode_any4_Slot_ae3_slot0_encode, 0, Opcode_any4_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_any4_Slot_ae8_slot0_encode, 0, 0, Opcode_any4_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_any4_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_any4_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { + Opcode_all8_Slot_inst_encode, 0, 0, Opcode_all8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_all8_Slot_ae2_slot0_encode, 0, 0, Opcode_all8_Slot_ae3_slot0_encode, 0, Opcode_all8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_all8_Slot_ae8_slot0_encode, 0, 0, Opcode_all8_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_all8_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_all8_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { + Opcode_any8_Slot_inst_encode, 0, 0, Opcode_any8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_any8_Slot_ae2_slot0_encode, 0, 0, Opcode_any8_Slot_ae3_slot0_encode, 0, Opcode_any8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_any8_Slot_ae8_slot0_encode, 0, 0, Opcode_any8_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_any8_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_any8_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { + Opcode_bf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { + Opcode_bt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { + Opcode_movf_Slot_inst_encode, 0, 0, Opcode_movf_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movf_Slot_ae2_slot0_encode, 0, 0, Opcode_movf_Slot_ae3_slot0_encode, 0, Opcode_movf_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movf_Slot_ae8_slot0_encode, 0, 0, Opcode_movf_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_movf_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_movf_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { + Opcode_movt_Slot_inst_encode, 0, 0, Opcode_movt_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movt_Slot_ae2_slot0_encode, 0, 0, Opcode_movt_Slot_ae3_slot0_encode, 0, Opcode_movt_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movt_Slot_ae8_slot0_encode, 0, 0, Opcode_movt_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_movt_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_movt_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { + Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { + Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { + Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { + Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { + Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { + Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { + Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { + Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { + Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { + Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { + Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { + Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { + Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { + Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { + Opcode_iii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { + Opcode_lict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { + Opcode_licw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { + Opcode_sict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { + Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { + Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { + Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = { + Opcode_diwbui_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { + Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { + Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { + Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { + Opcode_dii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { + Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { + Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { + Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { + Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfm_b_encode_fns[] = { + Opcode_dpfm_b_Slot_inst_encode, 0, 0, Opcode_dpfm_b_Slot_ae_slot0_encode, 0, 0, 0, Opcode_dpfm_b_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfm_bf_encode_fns[] = { + Opcode_dpfm_bf_Slot_inst_encode, 0, 0, Opcode_dpfm_bf_Slot_ae_slot0_encode, 0, 0, 0, Opcode_dpfm_bf_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_b_encode_fns[] = { + Opcode_dpfr_b_Slot_inst_encode, 0, 0, Opcode_dpfr_b_Slot_ae_slot0_encode, 0, 0, 0, Opcode_dpfr_b_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_bf_encode_fns[] = { + Opcode_dpfr_bf_Slot_inst_encode, 0, 0, Opcode_dpfr_bf_Slot_ae_slot0_encode, 0, 0, 0, Opcode_dpfr_bf_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_b_encode_fns[] = { + Opcode_dpfw_b_Slot_inst_encode, 0, 0, Opcode_dpfw_b_Slot_ae_slot0_encode, 0, 0, 0, Opcode_dpfw_b_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_bf_encode_fns[] = { + Opcode_dpfw_bf_Slot_inst_encode, 0, 0, Opcode_dpfw_bf_Slot_ae_slot0_encode, 0, 0, 0, Opcode_dpfw_bf_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pfnxt_f_encode_fns[] = { + Opcode_pfnxt_f_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhi_b_encode_fns[] = { + Opcode_dhi_b_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwbi_b_encode_fns[] = { + Opcode_dhwbi_b_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwb_b_encode_fns[] = { + Opcode_dhwb_b_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pfend_a_encode_fns[] = { + Opcode_pfend_a_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pfend_o_encode_fns[] = { + Opcode_pfend_o_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pfwait_a_encode_fns[] = { + Opcode_pfwait_a_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pfwait_r_encode_fns[] = { + Opcode_pfwait_r_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { + Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { + Opcode_diu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { + Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { + Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { + Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdcw_encode_fns[] = { + Opcode_sdcw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldcw_encode_fns[] = { + Opcode_ldcw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prefctl_encode_fns[] = { + Opcode_rsr_prefctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_prefctl_encode_fns[] = { + Opcode_wsr_prefctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_prefctl_encode_fns[] = { + Opcode_xsr_prefctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_cacheadrdis_encode_fns[] = { + Opcode_wsr_cacheadrdis_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_cacheadrdis_encode_fns[] = { + Opcode_rsr_cacheadrdis_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_cacheadrdis_encode_fns[] = { + Opcode_xsr_cacheadrdis_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rptlb0_encode_fns[] = { + Opcode_rptlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pptlb_encode_fns[] = { + Opcode_pptlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rptlb1_encode_fns[] = { + Opcode_rptlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wptlb_encode_fns[] = { + Opcode_wptlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_mpuenb_encode_fns[] = { + Opcode_rsr_mpuenb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mpuenb_encode_fns[] = { + Opcode_wsr_mpuenb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_mpuenb_encode_fns[] = { + Opcode_xsr_mpuenb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { + Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { + Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { + Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { + Opcode_clamps_Slot_inst_encode, 0, 0, Opcode_clamps_Slot_ae_slot0_encode, Opcode_clamps_Slot_ae_slot1_encode, 0, 0, Opcode_clamps_Slot_ae2_slot0_encode, Opcode_clamps_Slot_ae2_slot1_encode, 0, Opcode_clamps_Slot_ae3_slot0_encode, Opcode_clamps_Slot_ae3_slot1_encode, Opcode_clamps_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_clamps_Slot_ae8_slot0_encode, Opcode_clamps_Slot_ae8_slot1_encode, 0, Opcode_clamps_Slot_ae9_slot0_encode, Opcode_clamps_Slot_ae9_slot1_encode, 0, 0, Opcode_clamps_Slot_ae10_slot0_encode, Opcode_clamps_Slot_ae10_slot1_encode, 0, 0, Opcode_clamps_Slot_ae4_slot0_encode, Opcode_clamps_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { + Opcode_max_Slot_inst_encode, 0, 0, Opcode_max_Slot_ae_slot0_encode, Opcode_max_Slot_ae_slot1_encode, 0, 0, Opcode_max_Slot_ae2_slot0_encode, Opcode_max_Slot_ae2_slot1_encode, 0, Opcode_max_Slot_ae3_slot0_encode, Opcode_max_Slot_ae3_slot1_encode, Opcode_max_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_max_Slot_ae8_slot0_encode, Opcode_max_Slot_ae8_slot1_encode, 0, Opcode_max_Slot_ae9_slot0_encode, Opcode_max_Slot_ae9_slot1_encode, 0, 0, Opcode_max_Slot_ae10_slot0_encode, Opcode_max_Slot_ae10_slot1_encode, 0, 0, Opcode_max_Slot_ae4_slot0_encode, Opcode_max_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { + Opcode_maxu_Slot_inst_encode, 0, 0, Opcode_maxu_Slot_ae_slot0_encode, Opcode_maxu_Slot_ae_slot1_encode, 0, 0, Opcode_maxu_Slot_ae2_slot0_encode, Opcode_maxu_Slot_ae2_slot1_encode, 0, Opcode_maxu_Slot_ae3_slot0_encode, Opcode_maxu_Slot_ae3_slot1_encode, Opcode_maxu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maxu_Slot_ae8_slot0_encode, Opcode_maxu_Slot_ae8_slot1_encode, 0, Opcode_maxu_Slot_ae9_slot0_encode, Opcode_maxu_Slot_ae9_slot1_encode, 0, 0, Opcode_maxu_Slot_ae10_slot0_encode, Opcode_maxu_Slot_ae10_slot1_encode, 0, 0, Opcode_maxu_Slot_ae4_slot0_encode, Opcode_maxu_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { + Opcode_min_Slot_inst_encode, 0, 0, Opcode_min_Slot_ae_slot0_encode, Opcode_min_Slot_ae_slot1_encode, 0, 0, Opcode_min_Slot_ae2_slot0_encode, Opcode_min_Slot_ae2_slot1_encode, 0, Opcode_min_Slot_ae3_slot0_encode, Opcode_min_Slot_ae3_slot1_encode, Opcode_min_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_min_Slot_ae8_slot0_encode, Opcode_min_Slot_ae8_slot1_encode, 0, Opcode_min_Slot_ae9_slot0_encode, Opcode_min_Slot_ae9_slot1_encode, 0, 0, Opcode_min_Slot_ae10_slot0_encode, Opcode_min_Slot_ae10_slot1_encode, 0, 0, Opcode_min_Slot_ae4_slot0_encode, Opcode_min_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { + Opcode_minu_Slot_inst_encode, 0, 0, Opcode_minu_Slot_ae_slot0_encode, Opcode_minu_Slot_ae_slot1_encode, 0, 0, Opcode_minu_Slot_ae2_slot0_encode, Opcode_minu_Slot_ae2_slot1_encode, 0, Opcode_minu_Slot_ae3_slot0_encode, Opcode_minu_Slot_ae3_slot1_encode, Opcode_minu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_minu_Slot_ae8_slot0_encode, Opcode_minu_Slot_ae8_slot1_encode, 0, Opcode_minu_Slot_ae9_slot0_encode, Opcode_minu_Slot_ae9_slot1_encode, 0, 0, Opcode_minu_Slot_ae10_slot0_encode, Opcode_minu_Slot_ae10_slot1_encode, 0, 0, Opcode_minu_Slot_ae4_slot0_encode, Opcode_minu_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { + Opcode_sext_Slot_inst_encode, 0, 0, Opcode_sext_Slot_ae_slot0_encode, Opcode_sext_Slot_ae_slot1_encode, 0, 0, Opcode_sext_Slot_ae2_slot0_encode, Opcode_sext_Slot_ae2_slot1_encode, 0, Opcode_sext_Slot_ae3_slot0_encode, Opcode_sext_Slot_ae3_slot1_encode, Opcode_sext_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sext_Slot_ae8_slot0_encode, Opcode_sext_Slot_ae8_slot1_encode, 0, Opcode_sext_Slot_ae9_slot0_encode, Opcode_sext_Slot_ae9_slot1_encode, 0, 0, Opcode_sext_Slot_ae10_slot0_encode, Opcode_sext_Slot_ae10_slot1_encode, 0, 0, Opcode_sext_Slot_ae4_slot0_encode, Opcode_sext_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { + Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { + Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { + Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { + Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { + Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { + Opcode_quos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { + Opcode_quou_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { + Opcode_rems_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { + Opcode_remu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eraccess_encode_fns[] = { + Opcode_rsr_eraccess_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eraccess_encode_fns[] = { + Opcode_wsr_eraccess_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eraccess_encode_fns[] = { + Opcode_xsr_eraccess_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { + Opcode_rer_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { + Opcode_wer_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_beqz_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_beqz_w15_Slot_ae3_slot0_encode, 0, Opcode_beqz_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bgez_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bgez_w15_Slot_ae3_slot0_encode, 0, Opcode_bgez_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bltz_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bltz_w15_Slot_ae3_slot0_encode, 0, Opcode_bltz_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bnez_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bnez_w15_Slot_ae3_slot0_encode, 0, Opcode_bnez_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_beqi_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_beqi_w15_Slot_ae3_slot0_encode, 0, Opcode_beqi_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bgei_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bgei_w15_Slot_ae3_slot0_encode, 0, Opcode_bgei_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_blti_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_blti_w15_Slot_ae3_slot0_encode, 0, Opcode_blti_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bnei_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bnei_w15_Slot_ae3_slot0_encode, 0, Opcode_bnei_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bgeui_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bgeui_w15_Slot_ae3_slot0_encode, 0, Opcode_bgeui_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bltui_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bltui_w15_Slot_ae3_slot0_encode, 0, Opcode_bltui_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bbci_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bbci_w15_Slot_ae3_slot0_encode, 0, Opcode_bbci_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bbsi_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bbsi_w15_Slot_ae3_slot0_encode, 0, Opcode_bbsi_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ball_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_ball_w15_Slot_ae3_slot0_encode, 0, Opcode_ball_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bany_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bany_w15_Slot_ae3_slot0_encode, 0, Opcode_bany_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bbc_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bbc_w15_Slot_ae3_slot0_encode, 0, Opcode_bbc_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bbs_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bbs_w15_Slot_ae3_slot0_encode, 0, Opcode_bbs_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_beq_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_beq_w15_Slot_ae3_slot0_encode, 0, Opcode_beq_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bgeu_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bgeu_w15_Slot_ae3_slot0_encode, 0, Opcode_bgeu_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bge_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bge_w15_Slot_ae3_slot0_encode, 0, Opcode_bge_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bltu_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bltu_w15_Slot_ae3_slot0_encode, 0, Opcode_bltu_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_blt_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_blt_w15_Slot_ae3_slot0_encode, 0, Opcode_blt_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bnall_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bnall_w15_Slot_ae3_slot0_encode, 0, Opcode_bnall_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bne_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bne_w15_Slot_ae3_slot0_encode, 0, Opcode_bne_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bnone_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bnone_w15_Slot_ae3_slot0_encode, 0, Opcode_bnone_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = { + Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = { + Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = { + Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = { + Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = { + Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = { + Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cw_sd_no_encode_fns[] = { + Opcode_rur_ae_cw_sd_no_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cw_sd_no_encode_fns[] = { + Opcode_wur_ae_cw_sd_no_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cbegin0_encode_fns[] = { + Opcode_rur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cbegin0_encode_fns[] = { + Opcode_wur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cend0_encode_fns[] = { + Opcode_rur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cend0_encode_fns[] = { + Opcode_wur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cbegin1_encode_fns[] = { + Opcode_rur_ae_cbegin1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cbegin1_encode_fns[] = { + Opcode_wur_ae_cbegin1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cend1_encode_fns[] = { + Opcode_rur_ae_cend1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cend1_encode_fns[] = { + Opcode_wur_ae_cend1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cbegin2_encode_fns[] = { + Opcode_rur_ae_cbegin2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cbegin2_encode_fns[] = { + Opcode_wur_ae_cbegin2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cend2_encode_fns[] = { + Opcode_rur_ae_cend2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cend2_encode_fns[] = { + Opcode_wur_ae_cend2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext16_encode_fns[] = { + 0, 0, Opcode_ae_sext16_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_zext16_encode_fns[] = { + 0, 0, Opcode_ae_zext16_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_zext8_encode_fns[] = { + 0, 0, Opcode_ae_zext8_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_clamps16_encode_fns[] = { + 0, 0, Opcode_ae_clamps16_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = { + Opcode_rur_fcr_Slot_inst_encode, 0, 0, Opcode_rur_fcr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = { + Opcode_wur_fcr_Slot_inst_encode, 0, 0, Opcode_wur_fcr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = { + Opcode_rur_fsr_Slot_inst_encode, 0, 0, Opcode_rur_fsr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = { + Opcode_wur_fsr_Slot_inst_encode, 0, 0, Opcode_wur_fsr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { + Opcode_rur_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { + Opcode_wur_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { + Opcode_read_impwire_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { + Opcode_setb_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { + Opcode_clrb_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { + Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = { + Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = { + Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = { + Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = { + Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = { + Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rur_ae_bitptr_Slot_ae3_slot0_encode, 0, Opcode_rur_ae_bitptr_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = { + Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = { + Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = { + Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = { + Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = { + Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = { + Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = { + Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = { + Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = { + Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = { + Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = { + Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cwrap_encode_fns[] = { + Opcode_rur_ae_cwrap_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cwrap_encode_fns[] = { + Opcode_wur_ae_cwrap_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4f_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4f_i_Slot_ae_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4f_i_Slot_ae2_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4f_i_Slot_ae3_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae3_slot1_encode, Opcode_ae_l8x4f_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4f_i_Slot_ae8_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4f_i_Slot_ae9_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4f_i_Slot_ae10_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4f_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4f_ip_Slot_ae_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4f_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4f_ip_Slot_ae3_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae3_slot1_encode, Opcode_ae_l8x4f_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4f_ip_Slot_ae8_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4f_ip_Slot_ae9_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4f_ip_Slot_ae10_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4f_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4f_x_Slot_ae_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4f_x_Slot_ae2_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4f_x_Slot_ae3_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae3_slot1_encode, Opcode_ae_l8x4f_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4f_x_Slot_ae8_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4f_x_Slot_ae9_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4f_x_Slot_ae10_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4f_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4f_xp_Slot_ae_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4f_xp_Slot_ae2_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4f_xp_Slot_ae3_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae3_slot1_encode, Opcode_ae_l8x4f_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4f_xp_Slot_ae8_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4f_xp_Slot_ae9_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4f_xp_Slot_ae10_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4s_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4s_i_Slot_ae_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4s_i_Slot_ae2_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4s_i_Slot_ae3_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae3_slot1_encode, Opcode_ae_l8x4s_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4s_i_Slot_ae8_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4s_i_Slot_ae9_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4s_i_Slot_ae10_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4s_ip_Slot_ae_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4s_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4s_ip_Slot_ae3_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae3_slot1_encode, Opcode_ae_l8x4s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4s_ip_Slot_ae8_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4s_ip_Slot_ae9_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4s_ip_Slot_ae10_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4s_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4s_x_Slot_ae_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4s_x_Slot_ae2_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4s_x_Slot_ae3_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae3_slot1_encode, Opcode_ae_l8x4s_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4s_x_Slot_ae8_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4s_x_Slot_ae9_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4s_x_Slot_ae10_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4s_xp_Slot_ae_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4s_xp_Slot_ae2_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4s_xp_Slot_ae3_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae3_slot1_encode, Opcode_ae_l8x4s_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4s_xp_Slot_ae8_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4s_xp_Slot_ae9_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4s_xp_Slot_ae10_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4u_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4u_i_Slot_ae_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4u_i_Slot_ae2_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4u_i_Slot_ae3_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae3_slot1_encode, Opcode_ae_l8x4u_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4u_i_Slot_ae8_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4u_i_Slot_ae9_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4u_i_Slot_ae10_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4u_ip_Slot_ae_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4u_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4u_ip_Slot_ae3_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae3_slot1_encode, Opcode_ae_l8x4u_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4u_ip_Slot_ae8_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4u_ip_Slot_ae9_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4u_ip_Slot_ae10_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4u_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4u_x_Slot_ae_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4u_x_Slot_ae2_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4u_x_Slot_ae3_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae3_slot1_encode, Opcode_ae_l8x4u_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4u_x_Slot_ae8_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4u_x_Slot_ae9_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4u_x_Slot_ae10_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4u_xp_Slot_ae_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4u_xp_Slot_ae2_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4u_xp_Slot_ae3_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae3_slot1_encode, Opcode_ae_l8x4u_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4u_xp_Slot_ae8_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4u_xp_Slot_ae9_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4u_xp_Slot_ae10_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16m_xc_Slot_ae_slot0_encode, Opcode_ae_l16m_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_xc_Slot_ae2_slot0_encode, Opcode_ae_l16m_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l16m_xc_Slot_ae3_slot0_encode, Opcode_ae_l16m_xc_Slot_ae3_slot1_encode, Opcode_ae_l16m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_xc_Slot_ae8_slot0_encode, Opcode_ae_l16m_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_xc_Slot_ae9_slot0_encode, Opcode_ae_l16m_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_xc_Slot_ae10_slot0_encode, Opcode_ae_l16m_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_xc1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_l16m_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_xc1_Slot_ae2_slot0_encode, Opcode_ae_l16m_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l16m_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_xc1_Slot_ae8_slot0_encode, Opcode_ae_l16m_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_xc1_Slot_ae9_slot0_encode, Opcode_ae_l16m_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_xc1_Slot_ae10_slot0_encode, Opcode_ae_l16m_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16m_i_Slot_ae_slot0_encode, Opcode_ae_l16m_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_i_Slot_ae2_slot0_encode, Opcode_ae_l16m_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l16m_i_Slot_ae3_slot0_encode, Opcode_ae_l16m_i_Slot_ae3_slot1_encode, Opcode_ae_l16m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_i_Slot_ae8_slot0_encode, Opcode_ae_l16m_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_i_Slot_ae9_slot0_encode, Opcode_ae_l16m_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_i_Slot_ae10_slot0_encode, Opcode_ae_l16m_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16m_iu_Slot_ae_slot0_encode, Opcode_ae_l16m_iu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_iu_Slot_ae2_slot0_encode, Opcode_ae_l16m_iu_Slot_ae2_slot1_encode, 0, Opcode_ae_l16m_iu_Slot_ae3_slot0_encode, Opcode_ae_l16m_iu_Slot_ae3_slot1_encode, Opcode_ae_l16m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_iu_Slot_ae8_slot0_encode, Opcode_ae_l16m_iu_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_iu_Slot_ae9_slot0_encode, Opcode_ae_l16m_iu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_iu_Slot_ae10_slot0_encode, Opcode_ae_l16m_iu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16m_x_Slot_ae_slot0_encode, Opcode_ae_l16m_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_x_Slot_ae2_slot0_encode, Opcode_ae_l16m_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l16m_x_Slot_ae3_slot0_encode, Opcode_ae_l16m_x_Slot_ae3_slot1_encode, Opcode_ae_l16m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_x_Slot_ae8_slot0_encode, Opcode_ae_l16m_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_x_Slot_ae9_slot0_encode, Opcode_ae_l16m_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_x_Slot_ae10_slot0_encode, Opcode_ae_l16m_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16m_xu_Slot_ae_slot0_encode, Opcode_ae_l16m_xu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_xu_Slot_ae2_slot0_encode, Opcode_ae_l16m_xu_Slot_ae2_slot1_encode, 0, Opcode_ae_l16m_xu_Slot_ae3_slot0_encode, Opcode_ae_l16m_xu_Slot_ae3_slot1_encode, Opcode_ae_l16m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_xu_Slot_ae8_slot0_encode, Opcode_ae_l16m_xu_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_xu_Slot_ae9_slot0_encode, Opcode_ae_l16m_xu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_xu_Slot_ae10_slot0_encode, Opcode_ae_l16m_xu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_xc_Slot_ae_slot0_encode, Opcode_ae_l16_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_xc_Slot_ae2_slot0_encode, Opcode_ae_l16_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l16_xc_Slot_ae3_slot0_encode, Opcode_ae_l16_xc_Slot_ae3_slot1_encode, Opcode_ae_l16_xc_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16_xc_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_xc_Slot_ae8_slot0_encode, Opcode_ae_l16_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_xc_Slot_ae9_slot0_encode, Opcode_ae_l16_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_xc_Slot_ae10_slot0_encode, Opcode_ae_l16_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_xc1_Slot_ae_slot0_encode, Opcode_ae_l16_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_xc1_Slot_ae2_slot0_encode, Opcode_ae_l16_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l16_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_xc1_Slot_ae8_slot0_encode, Opcode_ae_l16_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_xc1_Slot_ae9_slot0_encode, Opcode_ae_l16_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_xc1_Slot_ae10_slot0_encode, Opcode_ae_l16_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_i_Slot_ae_slot0_encode, Opcode_ae_l16_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_i_Slot_ae2_slot0_encode, Opcode_ae_l16_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l16_i_Slot_ae3_slot0_encode, Opcode_ae_l16_i_Slot_ae3_slot1_encode, Opcode_ae_l16_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16_i_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_i_Slot_ae8_slot0_encode, Opcode_ae_l16_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_i_Slot_ae9_slot0_encode, Opcode_ae_l16_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_i_Slot_ae10_slot0_encode, Opcode_ae_l16_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_ip_Slot_ae_slot0_encode, Opcode_ae_l16_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_ip_Slot_ae2_slot0_encode, Opcode_ae_l16_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l16_ip_Slot_ae3_slot0_encode, Opcode_ae_l16_ip_Slot_ae3_slot1_encode, Opcode_ae_l16_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16_ip_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_ip_Slot_ae8_slot0_encode, Opcode_ae_l16_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_ip_Slot_ae9_slot0_encode, Opcode_ae_l16_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_ip_Slot_ae10_slot0_encode, Opcode_ae_l16_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_x_Slot_ae_slot0_encode, Opcode_ae_l16_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_x_Slot_ae2_slot0_encode, Opcode_ae_l16_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l16_x_Slot_ae3_slot0_encode, Opcode_ae_l16_x_Slot_ae3_slot1_encode, Opcode_ae_l16_x_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16_x_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_x_Slot_ae8_slot0_encode, Opcode_ae_l16_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_x_Slot_ae9_slot0_encode, Opcode_ae_l16_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_x_Slot_ae10_slot0_encode, Opcode_ae_l16_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_xp_Slot_ae_slot0_encode, Opcode_ae_l16_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_xp_Slot_ae2_slot0_encode, Opcode_ae_l16_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l16_xp_Slot_ae3_slot0_encode, Opcode_ae_l16_xp_Slot_ae3_slot1_encode, Opcode_ae_l16_xp_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16_xp_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_xp_Slot_ae8_slot0_encode, Opcode_ae_l16_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_xp_Slot_ae9_slot0_encode, Opcode_ae_l16_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_xp_Slot_ae10_slot0_encode, Opcode_ae_l16_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_xc_Slot_ae_slot0_encode, Opcode_ae_l8_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_xc_Slot_ae2_slot0_encode, Opcode_ae_l8_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l8_xc_Slot_ae3_slot0_encode, Opcode_ae_l8_xc_Slot_ae3_slot1_encode, Opcode_ae_l8_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_xc_Slot_ae8_slot0_encode, Opcode_ae_l8_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_xc_Slot_ae9_slot0_encode, Opcode_ae_l8_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_xc_Slot_ae10_slot0_encode, Opcode_ae_l8_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_xc1_Slot_ae_slot0_encode, Opcode_ae_l8_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_xc1_Slot_ae2_slot0_encode, Opcode_ae_l8_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l8_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_xc1_Slot_ae8_slot0_encode, Opcode_ae_l8_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_xc1_Slot_ae9_slot0_encode, Opcode_ae_l8_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_xc1_Slot_ae10_slot0_encode, Opcode_ae_l8_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_i_Slot_ae_slot0_encode, Opcode_ae_l8_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_i_Slot_ae2_slot0_encode, Opcode_ae_l8_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l8_i_Slot_ae3_slot0_encode, Opcode_ae_l8_i_Slot_ae3_slot1_encode, Opcode_ae_l8_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_i_Slot_ae8_slot0_encode, Opcode_ae_l8_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_i_Slot_ae9_slot0_encode, Opcode_ae_l8_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_i_Slot_ae10_slot0_encode, Opcode_ae_l8_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_ip_Slot_ae_slot0_encode, Opcode_ae_l8_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_ip_Slot_ae2_slot0_encode, Opcode_ae_l8_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l8_ip_Slot_ae3_slot0_encode, Opcode_ae_l8_ip_Slot_ae3_slot1_encode, Opcode_ae_l8_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_ip_Slot_ae8_slot0_encode, Opcode_ae_l8_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_ip_Slot_ae9_slot0_encode, Opcode_ae_l8_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_ip_Slot_ae10_slot0_encode, Opcode_ae_l8_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_x_Slot_ae_slot0_encode, Opcode_ae_l8_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_x_Slot_ae2_slot0_encode, Opcode_ae_l8_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l8_x_Slot_ae3_slot0_encode, Opcode_ae_l8_x_Slot_ae3_slot1_encode, Opcode_ae_l8_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_x_Slot_ae8_slot0_encode, Opcode_ae_l8_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_x_Slot_ae9_slot0_encode, Opcode_ae_l8_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_x_Slot_ae10_slot0_encode, Opcode_ae_l8_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_xp_Slot_ae_slot0_encode, Opcode_ae_l8_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_xp_Slot_ae2_slot0_encode, Opcode_ae_l8_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l8_xp_Slot_ae3_slot0_encode, Opcode_ae_l8_xp_Slot_ae3_slot1_encode, Opcode_ae_l8_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_xp_Slot_ae8_slot0_encode, Opcode_ae_l8_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_xp_Slot_ae9_slot0_encode, Opcode_ae_l8_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_xp_Slot_ae10_slot0_encode, Opcode_ae_l8_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_xc_Slot_ae_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_xc_Slot_ae2_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l32f24_xc_Slot_ae3_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae3_slot1_encode, Opcode_ae_l32f24_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_xc_Slot_ae9_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_xc_Slot_ae10_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae_slot0_encode, Opcode_ae_l32f24_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae2_slot0_encode, Opcode_ae_l32f24_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae9_slot0_encode, Opcode_ae_l32f24_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae10_slot0_encode, Opcode_ae_l32f24_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_i_Slot_ae_slot0_encode, Opcode_ae_l32f24_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_i_Slot_ae2_slot0_encode, Opcode_ae_l32f24_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l32f24_i_Slot_ae3_slot0_encode, Opcode_ae_l32f24_i_Slot_ae3_slot1_encode, Opcode_ae_l32f24_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_i_Slot_ae9_slot0_encode, Opcode_ae_l32f24_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_i_Slot_ae10_slot0_encode, Opcode_ae_l32f24_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_ip_Slot_ae_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_ip_Slot_ae2_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l32f24_ip_Slot_ae3_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae3_slot1_encode, Opcode_ae_l32f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_ip_Slot_ae9_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_ip_Slot_ae10_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_x_Slot_ae_slot0_encode, Opcode_ae_l32f24_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_x_Slot_ae2_slot0_encode, Opcode_ae_l32f24_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l32f24_x_Slot_ae3_slot0_encode, Opcode_ae_l32f24_x_Slot_ae3_slot1_encode, Opcode_ae_l32f24_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_x_Slot_ae9_slot0_encode, Opcode_ae_l32f24_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_x_Slot_ae10_slot0_encode, Opcode_ae_l32f24_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_xp_Slot_ae_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_xp_Slot_ae2_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l32f24_xp_Slot_ae3_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae3_slot1_encode, Opcode_ae_l32f24_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_xp_Slot_ae9_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_xp_Slot_ae10_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_xc_Slot_ae_slot0_encode, Opcode_ae_l32_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_xc_Slot_ae2_slot0_encode, Opcode_ae_l32_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l32_xc_Slot_ae3_slot0_encode, Opcode_ae_l32_xc_Slot_ae3_slot1_encode, Opcode_ae_l32_xc_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32_xc_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_xc_Slot_ae8_slot0_encode, Opcode_ae_l32_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_xc_Slot_ae9_slot0_encode, Opcode_ae_l32_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_xc_Slot_ae10_slot0_encode, Opcode_ae_l32_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_xc1_Slot_ae_slot0_encode, Opcode_ae_l32_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_xc1_Slot_ae2_slot0_encode, Opcode_ae_l32_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_xc1_Slot_ae8_slot0_encode, Opcode_ae_l32_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_xc1_Slot_ae9_slot0_encode, Opcode_ae_l32_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_xc1_Slot_ae10_slot0_encode, Opcode_ae_l32_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_i_Slot_ae_slot0_encode, Opcode_ae_l32_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_i_Slot_ae2_slot0_encode, Opcode_ae_l32_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l32_i_Slot_ae3_slot0_encode, Opcode_ae_l32_i_Slot_ae3_slot1_encode, Opcode_ae_l32_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32_i_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_i_Slot_ae8_slot0_encode, Opcode_ae_l32_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_i_Slot_ae9_slot0_encode, Opcode_ae_l32_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_i_Slot_ae10_slot0_encode, Opcode_ae_l32_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_ip_Slot_ae_slot0_encode, Opcode_ae_l32_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_ip_Slot_ae2_slot0_encode, Opcode_ae_l32_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l32_ip_Slot_ae3_slot0_encode, Opcode_ae_l32_ip_Slot_ae3_slot1_encode, Opcode_ae_l32_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32_ip_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_ip_Slot_ae8_slot0_encode, Opcode_ae_l32_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_ip_Slot_ae9_slot0_encode, Opcode_ae_l32_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_ip_Slot_ae10_slot0_encode, Opcode_ae_l32_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_x_Slot_ae_slot0_encode, Opcode_ae_l32_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_x_Slot_ae2_slot0_encode, Opcode_ae_l32_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l32_x_Slot_ae3_slot0_encode, Opcode_ae_l32_x_Slot_ae3_slot1_encode, Opcode_ae_l32_x_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32_x_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_x_Slot_ae8_slot0_encode, Opcode_ae_l32_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_x_Slot_ae9_slot0_encode, Opcode_ae_l32_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_x_Slot_ae10_slot0_encode, Opcode_ae_l32_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_xp_Slot_ae_slot0_encode, Opcode_ae_l32_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_xp_Slot_ae2_slot0_encode, Opcode_ae_l32_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l32_xp_Slot_ae3_slot0_encode, Opcode_ae_l32_xp_Slot_ae3_slot1_encode, Opcode_ae_l32_xp_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32_xp_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_xp_Slot_ae8_slot0_encode, Opcode_ae_l32_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_xp_Slot_ae9_slot0_encode, Opcode_ae_l32_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_xp_Slot_ae10_slot0_encode, Opcode_ae_l32_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32m_xc_Slot_ae_slot0_encode, Opcode_ae_l32m_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32m_xc_Slot_ae2_slot0_encode, Opcode_ae_l32m_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l32m_xc_Slot_ae3_slot0_encode, Opcode_ae_l32m_xc_Slot_ae3_slot1_encode, Opcode_ae_l32m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32m_xc_Slot_ae8_slot0_encode, Opcode_ae_l32m_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l32m_xc_Slot_ae9_slot0_encode, Opcode_ae_l32m_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32m_xc_Slot_ae10_slot0_encode, Opcode_ae_l32m_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32m_i_Slot_ae_slot0_encode, Opcode_ae_l32m_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32m_i_Slot_ae2_slot0_encode, Opcode_ae_l32m_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l32m_i_Slot_ae3_slot0_encode, Opcode_ae_l32m_i_Slot_ae3_slot1_encode, Opcode_ae_l32m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32m_i_Slot_ae8_slot0_encode, Opcode_ae_l32m_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l32m_i_Slot_ae9_slot0_encode, Opcode_ae_l32m_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32m_i_Slot_ae10_slot0_encode, Opcode_ae_l32m_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32m_iu_Slot_ae_slot0_encode, Opcode_ae_l32m_iu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32m_iu_Slot_ae2_slot0_encode, Opcode_ae_l32m_iu_Slot_ae2_slot1_encode, 0, Opcode_ae_l32m_iu_Slot_ae3_slot0_encode, Opcode_ae_l32m_iu_Slot_ae3_slot1_encode, Opcode_ae_l32m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32m_iu_Slot_ae8_slot0_encode, Opcode_ae_l32m_iu_Slot_ae8_slot1_encode, 0, Opcode_ae_l32m_iu_Slot_ae9_slot0_encode, Opcode_ae_l32m_iu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32m_iu_Slot_ae10_slot0_encode, Opcode_ae_l32m_iu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32m_x_Slot_ae_slot0_encode, Opcode_ae_l32m_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32m_x_Slot_ae2_slot0_encode, Opcode_ae_l32m_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l32m_x_Slot_ae3_slot0_encode, Opcode_ae_l32m_x_Slot_ae3_slot1_encode, Opcode_ae_l32m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32m_x_Slot_ae8_slot0_encode, Opcode_ae_l32m_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l32m_x_Slot_ae9_slot0_encode, Opcode_ae_l32m_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32m_x_Slot_ae10_slot0_encode, Opcode_ae_l32m_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32m_xu_Slot_ae_slot0_encode, Opcode_ae_l32m_xu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32m_xu_Slot_ae2_slot0_encode, Opcode_ae_l32m_xu_Slot_ae2_slot1_encode, 0, Opcode_ae_l32m_xu_Slot_ae3_slot0_encode, Opcode_ae_l32m_xu_Slot_ae3_slot1_encode, Opcode_ae_l32m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32m_xu_Slot_ae8_slot0_encode, Opcode_ae_l32m_xu_Slot_ae8_slot1_encode, 0, Opcode_ae_l32m_xu_Slot_ae9_slot0_encode, Opcode_ae_l32m_xu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32m_xu_Slot_ae10_slot0_encode, Opcode_ae_l32m_xu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x2m_xc_Slot_ae_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_xc_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x2m_xc_Slot_ae3_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_xc_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_xc_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_xc_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_xc1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_xc1_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x2m_i_Slot_ae_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_i_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x2m_i_Slot_ae3_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_i_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_i_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_i_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x2m_iu_Slot_ae_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_iu_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x2m_iu_Slot_ae3_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_iu_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_iu_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_iu_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x2m_x_Slot_ae_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_x_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x2m_x_Slot_ae3_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_x_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_x_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_x_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x2m_xu_Slot_ae_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_xu_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x2m_xu_Slot_ae3_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_xu_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_xu_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_xu_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_xc_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_xc1_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_i_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_ip_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_rip_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ri_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_ri_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_ri_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_ric_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_ric1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ric1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_ric1_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_ric1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_ric1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_x_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_xp_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_xc_Slot_ae_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_xc_Slot_ae3_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae3_slot1_encode, Opcode_ae_l32x2_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_xc_Slot_ae7_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_xc_Slot_ae8_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_xc_Slot_ae9_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_xc_Slot_ae10_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae2_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae7_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae8_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_xc1_Slot_ae9_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae10_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_i_Slot_ae_slot0_encode, Opcode_ae_l32x2_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_i_Slot_ae2_slot0_encode, Opcode_ae_l32x2_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_i_Slot_ae3_slot0_encode, Opcode_ae_l32x2_i_Slot_ae3_slot1_encode, Opcode_ae_l32x2_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32x2_i_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l32x2_i_Slot_ae7_slot0_encode, Opcode_ae_l32x2_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_i_Slot_ae8_slot0_encode, Opcode_ae_l32x2_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_i_Slot_ae9_slot0_encode, Opcode_ae_l32x2_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_i_Slot_ae10_slot0_encode, Opcode_ae_l32x2_i_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2_i_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_ip_Slot_ae_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_ip_Slot_ae3_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae3_slot1_encode, Opcode_ae_l32x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32x2_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l32x2_ip_Slot_ae7_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_ip_Slot_ae8_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_ip_Slot_ae9_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_ip_Slot_ae10_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_ric_Slot_ae_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_ric_Slot_ae2_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_ric_Slot_ae3_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae3_slot1_encode, Opcode_ae_l32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_ric_Slot_ae7_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_ric_Slot_ae8_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_ric_Slot_ae9_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_ric_Slot_ae10_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae2_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae7_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae8_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_ric1_Slot_ae9_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae10_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_x_Slot_ae_slot0_encode, Opcode_ae_l32x2_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_x_Slot_ae2_slot0_encode, Opcode_ae_l32x2_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_x_Slot_ae3_slot0_encode, Opcode_ae_l32x2_x_Slot_ae3_slot1_encode, Opcode_ae_l32x2_x_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32x2_x_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l32x2_x_Slot_ae7_slot0_encode, Opcode_ae_l32x2_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_x_Slot_ae8_slot0_encode, Opcode_ae_l32x2_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_x_Slot_ae9_slot0_encode, Opcode_ae_l32x2_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_x_Slot_ae10_slot0_encode, Opcode_ae_l32x2_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_xp_Slot_ae_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_xp_Slot_ae3_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae3_slot1_encode, Opcode_ae_l32x2_xp_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32x2_xp_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l32x2_xp_Slot_ae7_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_xp_Slot_ae8_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_xp_Slot_ae9_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_xp_Slot_ae10_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2_xp_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_xc_Slot_ae_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_xc_Slot_ae2_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_xc_Slot_ae3_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae3_slot1_encode, Opcode_ae_l16x4_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc_Slot_ae7_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_xc_Slot_ae8_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_xc_Slot_ae9_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_xc_Slot_ae10_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae2_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae7_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae8_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_xc1_Slot_ae9_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae10_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_i_Slot_ae_slot0_encode, Opcode_ae_l16x4_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_i_Slot_ae2_slot0_encode, Opcode_ae_l16x4_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_i_Slot_ae3_slot0_encode, Opcode_ae_l16x4_i_Slot_ae3_slot1_encode, Opcode_ae_l16x4_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16x4_i_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l16x4_i_Slot_ae7_slot0_encode, Opcode_ae_l16x4_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_i_Slot_ae8_slot0_encode, Opcode_ae_l16x4_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_i_Slot_ae9_slot0_encode, Opcode_ae_l16x4_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_i_Slot_ae10_slot0_encode, Opcode_ae_l16x4_i_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4_i_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_ip_Slot_ae_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_ip_Slot_ae2_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_ip_Slot_ae3_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae3_slot1_encode, Opcode_ae_l16x4_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16x4_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l16x4_ip_Slot_ae7_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_ip_Slot_ae8_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_ip_Slot_ae9_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_ip_Slot_ae10_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_x_Slot_ae_slot0_encode, Opcode_ae_l16x4_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_x_Slot_ae2_slot0_encode, Opcode_ae_l16x4_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_x_Slot_ae3_slot0_encode, Opcode_ae_l16x4_x_Slot_ae3_slot1_encode, Opcode_ae_l16x4_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_x_Slot_ae7_slot0_encode, Opcode_ae_l16x4_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_x_Slot_ae8_slot0_encode, Opcode_ae_l16x4_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_x_Slot_ae9_slot0_encode, Opcode_ae_l16x4_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_x_Slot_ae10_slot0_encode, Opcode_ae_l16x4_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_xp_Slot_ae_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_xp_Slot_ae2_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_xp_Slot_ae3_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae3_slot1_encode, Opcode_ae_l16x4_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xp_Slot_ae7_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_xp_Slot_ae8_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_xp_Slot_ae9_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_xp_Slot_ae10_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4_xp_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_xc_Slot_ae_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_xc_Slot_ae2_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_xc_Slot_ae3_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae3_slot1_encode, Opcode_ae_l8x8_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_xc_Slot_ae7_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_xc_Slot_ae8_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_xc_Slot_ae9_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_xc_Slot_ae10_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae2_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae7_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae8_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_xc1_Slot_ae9_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae10_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_i_Slot_ae_slot0_encode, Opcode_ae_l8x8_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_i_Slot_ae2_slot0_encode, Opcode_ae_l8x8_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_i_Slot_ae3_slot0_encode, Opcode_ae_l8x8_i_Slot_ae3_slot1_encode, Opcode_ae_l8x8_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_i_Slot_ae7_slot0_encode, Opcode_ae_l8x8_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_i_Slot_ae8_slot0_encode, Opcode_ae_l8x8_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_i_Slot_ae9_slot0_encode, Opcode_ae_l8x8_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_i_Slot_ae10_slot0_encode, Opcode_ae_l8x8_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_ip_Slot_ae_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_ip_Slot_ae3_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae3_slot1_encode, Opcode_ae_l8x8_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_ip_Slot_ae7_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_ip_Slot_ae8_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_ip_Slot_ae9_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_ip_Slot_ae10_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_x_Slot_ae_slot0_encode, Opcode_ae_l8x8_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_x_Slot_ae2_slot0_encode, Opcode_ae_l8x8_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_x_Slot_ae3_slot0_encode, Opcode_ae_l8x8_x_Slot_ae3_slot1_encode, Opcode_ae_l8x8_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_x_Slot_ae7_slot0_encode, Opcode_ae_l8x8_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_x_Slot_ae8_slot0_encode, Opcode_ae_l8x8_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_x_Slot_ae9_slot0_encode, Opcode_ae_l8x8_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_x_Slot_ae10_slot0_encode, Opcode_ae_l8x8_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_xp_Slot_ae_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_xp_Slot_ae2_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_xp_Slot_ae3_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae3_slot1_encode, Opcode_ae_l8x8_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_xp_Slot_ae7_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_xp_Slot_ae8_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_xp_Slot_ae9_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_xp_Slot_ae10_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_xc_Slot_ae_slot0_encode, Opcode_ae_l64_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_xc_Slot_ae2_slot0_encode, Opcode_ae_l64_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_xc_Slot_ae3_slot0_encode, Opcode_ae_l64_xc_Slot_ae3_slot1_encode, Opcode_ae_l64_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_xc_Slot_ae7_slot0_encode, Opcode_ae_l64_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_xc_Slot_ae8_slot0_encode, Opcode_ae_l64_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_xc_Slot_ae9_slot0_encode, Opcode_ae_l64_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_xc_Slot_ae10_slot0_encode, Opcode_ae_l64_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_xc1_Slot_ae_slot0_encode, Opcode_ae_l64_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_xc1_Slot_ae2_slot0_encode, Opcode_ae_l64_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l64_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_xc1_Slot_ae7_slot0_encode, Opcode_ae_l64_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_xc1_Slot_ae8_slot0_encode, Opcode_ae_l64_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_xc1_Slot_ae9_slot0_encode, Opcode_ae_l64_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_xc1_Slot_ae10_slot0_encode, Opcode_ae_l64_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_i_Slot_ae_slot0_encode, Opcode_ae_l64_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_i_Slot_ae2_slot0_encode, Opcode_ae_l64_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_i_Slot_ae3_slot0_encode, Opcode_ae_l64_i_Slot_ae3_slot1_encode, Opcode_ae_l64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_i_Slot_ae7_slot0_encode, Opcode_ae_l64_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_i_Slot_ae8_slot0_encode, Opcode_ae_l64_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_i_Slot_ae9_slot0_encode, Opcode_ae_l64_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_i_Slot_ae10_slot0_encode, Opcode_ae_l64_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_ip_Slot_ae_slot0_encode, Opcode_ae_l64_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_ip_Slot_ae2_slot0_encode, Opcode_ae_l64_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_ip_Slot_ae3_slot0_encode, Opcode_ae_l64_ip_Slot_ae3_slot1_encode, Opcode_ae_l64_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_ip_Slot_ae7_slot0_encode, Opcode_ae_l64_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_ip_Slot_ae8_slot0_encode, Opcode_ae_l64_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_ip_Slot_ae9_slot0_encode, Opcode_ae_l64_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_ip_Slot_ae10_slot0_encode, Opcode_ae_l64_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_x_Slot_ae_slot0_encode, Opcode_ae_l64_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_x_Slot_ae2_slot0_encode, Opcode_ae_l64_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_x_Slot_ae3_slot0_encode, Opcode_ae_l64_x_Slot_ae3_slot1_encode, Opcode_ae_l64_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_x_Slot_ae7_slot0_encode, Opcode_ae_l64_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_x_Slot_ae8_slot0_encode, Opcode_ae_l64_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_x_Slot_ae9_slot0_encode, Opcode_ae_l64_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_x_Slot_ae10_slot0_encode, Opcode_ae_l64_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_xp_Slot_ae_slot0_encode, Opcode_ae_l64_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_xp_Slot_ae2_slot0_encode, Opcode_ae_l64_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_xp_Slot_ae3_slot0_encode, Opcode_ae_l64_xp_Slot_ae3_slot1_encode, Opcode_ae_l64_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_xp_Slot_ae7_slot0_encode, Opcode_ae_l64_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_xp_Slot_ae8_slot0_encode, Opcode_ae_l64_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_xp_Slot_ae9_slot0_encode, Opcode_ae_l64_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_xp_Slot_ae10_slot0_encode, Opcode_ae_l64_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x2m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x2m_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x2m_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x2m_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x2m_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x2m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x2m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x2m_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x2m_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x2m_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x2m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x2m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_ric_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_ric_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_x_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_xp_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2rng_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2rng_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2rng_x_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2rng_xp_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_x_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_xp_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s8x8_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s16m_l_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16m_l_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s16m_l_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae3_slot0_encode, 0, Opcode_ae_s16m_l_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16m_l_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s16m_l_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae3_slot0_encode, 0, Opcode_ae_s16m_l_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32f24_l_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32f24_l_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32f24_l_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32f24_l_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32f24_l_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_l_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_l_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_l_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_l_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_l_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_l_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_l_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_l_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_l_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_l_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_h_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_h_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32_h_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_h_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_h_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_h_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_h_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_h_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_h_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_h_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_h_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16_0_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s16_0_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16_0_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s16_0_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16_0_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s16_0_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16_0_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s16_0_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16_0_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s16_0_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8_0_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s8_0_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s8_0_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8_0_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s8_0_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8_0_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s8_0_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8_0_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s8_0_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8_0_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s8_0_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s64_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32m_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32m_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32m_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32m_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32m_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32m_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32m_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32m_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32m_iu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32m_iu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32m_iu_Slot_ae3_slot0_encode, 0, Opcode_ae_s32m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_iu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32m_iu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32m_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32m_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32m_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32m_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32m_xu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32m_xu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32m_xu_Slot_ae3_slot0_encode, 0, Opcode_ae_s32m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_xu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32m_xu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_xc2_Slot_ae_slot0_encode, Opcode_ae_l32x2_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_xc2_Slot_ae2_slot0_encode, Opcode_ae_l32x2_xc2_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_l32x2_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_xc2_Slot_ae8_slot0_encode, Opcode_ae_l32x2_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_xc2_Slot_ae9_slot0_encode, Opcode_ae_l32x2_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_xc2_Slot_ae_slot0_encode, Opcode_ae_l16x4_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_xc2_Slot_ae2_slot0_encode, Opcode_ae_l16x4_xc2_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_l16x4_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc2_Slot_ae8_slot0_encode, Opcode_ae_l16x4_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_xc2_Slot_ae9_slot0_encode, Opcode_ae_l16x4_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_xc2_Slot_ae_slot0_encode, Opcode_ae_l8x8_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_xc2_Slot_ae2_slot0_encode, Opcode_ae_l8x8_xc2_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_l8x8_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_xc2_Slot_ae8_slot0_encode, Opcode_ae_l8x8_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_xc2_Slot_ae9_slot0_encode, Opcode_ae_l8x8_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_xc2_Slot_ae_slot0_encode, Opcode_ae_l64_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_xc2_Slot_ae2_slot0_encode, Opcode_ae_l64_xc2_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_l64_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_xc2_Slot_ae8_slot0_encode, Opcode_ae_l64_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_xc2_Slot_ae9_slot0_encode, Opcode_ae_l64_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_xc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_xc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_xc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_xc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_xc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_xc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_xc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_xc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4rng_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4rng_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4rng_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4rng_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4rng_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4rng_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4rng_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4rng_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4rng_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4rng_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4rng_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4rng_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4rng_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4rng_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4rng_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4rng_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4rng_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4rng_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4rng_x_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4rng_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4rng_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4rng_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4rng_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4rng_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4rng_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4rng_xp_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4rng_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4rng_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_xc_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_xc1_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_i_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_i_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_i_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_i_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_i_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_i_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_ip_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_x_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_x_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_x_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_x_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_x_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_x_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_xp_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_xc_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_xc1_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_i_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_i_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_i_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_i_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_i_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_i_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_ip_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_x_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_x_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_x_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_x_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_x_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_x_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_xp_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_xc_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_xc_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_xc_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_xc1_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc1_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_xc1_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc1_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_xc1_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc1_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_i_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_i_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_i_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_i_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_i_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_i_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_ip_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_x_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_x_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_x_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_x_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_x_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_x_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_xp_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_xp_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xp_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_xp_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xp_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_xc_Slot_ae_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_xc_Slot_ae7_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_xc_Slot_ae8_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_xc_Slot_ae9_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_xc_Slot_ae10_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_xc1_Slot_ae_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_xc1_Slot_ae2_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_xc1_Slot_ae7_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_xc1_Slot_ae8_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_xc1_Slot_ae9_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_xc1_Slot_ae10_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_i_Slot_ae_slot0_encode, Opcode_ae_l64x2_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_i_Slot_ae2_slot0_encode, Opcode_ae_l64x2_i_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_i_Slot_ae7_slot0_encode, Opcode_ae_l64x2_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_i_Slot_ae8_slot0_encode, Opcode_ae_l64x2_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_i_Slot_ae9_slot0_encode, Opcode_ae_l64x2_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_i_Slot_ae10_slot0_encode, Opcode_ae_l64x2_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_ip_Slot_ae_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_ip_Slot_ae7_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_ip_Slot_ae8_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_ip_Slot_ae9_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_ip_Slot_ae10_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_x_Slot_ae_slot0_encode, Opcode_ae_l64x2_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_x_Slot_ae2_slot0_encode, Opcode_ae_l64x2_x_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_x_Slot_ae7_slot0_encode, Opcode_ae_l64x2_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_x_Slot_ae8_slot0_encode, Opcode_ae_l64x2_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_x_Slot_ae9_slot0_encode, Opcode_ae_l64x2_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_x_Slot_ae10_slot0_encode, Opcode_ae_l64x2_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_xp_Slot_ae_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_xp_Slot_ae7_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_xp_Slot_ae8_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_xp_Slot_ae9_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_xp_Slot_ae10_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_xc_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_xc1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_ip_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_x_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xp_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2rng_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2rng_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2rng_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2rng_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_ip_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2rng_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2rng_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2rng_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2rng_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_xp_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_xc_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_xc1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_xc_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_xc1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_xc_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_xc1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_xc2_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc2_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_xc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_xc2_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_xc2_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_xc2_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc2_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_xc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_xc2_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_xc2_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_xc2_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc2_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_xc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_xc2_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_xc2_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_xc2_Slot_ae_slot0_encode, Opcode_ae_l64x2_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_xc2_Slot_ae2_slot0_encode, Opcode_ae_l64x2_xc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_xc2_Slot_ae8_slot0_encode, Opcode_ae_l64x2_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_xc2_Slot_ae9_slot0_encode, Opcode_ae_l64x2_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_xc2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_xc2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_xc2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_xc2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2rng_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2rng_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2rng_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2rng_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2rng_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2rng_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2rng_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2rng_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2rng_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2rng_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2rng_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2rng_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_zalign64_encode_fns[] = { + 0, 0, 0, Opcode_ae_zalign64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_zalign64_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_zalign64_Slot_ae3_slot0_encode, 0, Opcode_ae_zalign64_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lalign64_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_lalign64_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lalign64_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_lalign64_i_Slot_ae3_slot0_encode, 0, Opcode_ae_lalign64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_salign64_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_salign64_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_salign64_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_salign64_i_Slot_ae3_slot0_encode, 0, Opcode_ae_salign64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movalign_encode_fns[] = { + 0, 0, 0, Opcode_ae_movalign_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movalign_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movalign_Slot_ae3_slot0_encode, 0, Opcode_ae_movalign_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la64_pp_encode_fns[] = { + 0, 0, 0, Opcode_ae_la64_pp_Slot_ae_slot0_encode, Opcode_ae_la64_pp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la64_pp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la64_pp_Slot_ae3_slot0_encode, Opcode_ae_la64_pp_Slot_ae3_slot1_encode, Opcode_ae_la64_pp_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la64_pp_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24pos_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24pos_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24pos_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la24pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24neg_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24neg_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24neg_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24neg_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la24neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24pos_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24neg_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24neg_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2pos_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2pos_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2pos_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2neg_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2neg_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2neg_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2neg_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2pos_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2neg_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2neg_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2pos_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2pos_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2pos_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2neg_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2neg_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2neg_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2neg_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2pos_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2neg_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2neg_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2pos_pc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2pos_pc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2pos_pc2_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2pos_pc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4pos_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4pos_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4pos_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4neg_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4neg_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4neg_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4neg_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4pos_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4neg_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4neg_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4pos_pc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4pos_pc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4pos_pc2_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4pos_pc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8pos_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8pos_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8pos_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8neg_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8neg_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8neg_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8neg_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8pos_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la8x8pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8neg_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8neg_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la8x8neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8pos_pc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8pos_pc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8pos_pc2_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8pos_pc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa64pos_fp_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa64pos_fp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa64pos_fp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa64pos_fp_Slot_ae3_slot0_encode, 0, Opcode_ae_sa64pos_fp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa64neg_fp_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa64neg_fp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa64neg_fp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa64neg_fp_Slot_ae3_slot0_encode, 0, Opcode_ae_sa64neg_fp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic_Slot_ae7_slot0_encode, Opcode_ae_la32x2_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_ic_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ic_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae7_slot0_encode, Opcode_ae_la32x2_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ic1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic2_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ic2_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ip_Slot_ae_slot0_encode, Opcode_ae_la32x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2_ip_Slot_ae3_slot0_encode, Opcode_ae_la32x2_ip_Slot_ae3_slot1_encode, Opcode_ae_la32x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la32x2_ip_Slot_ae7_slot0_encode, Opcode_ae_la32x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_ip_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_rip_Slot_ae_slot0_encode, Opcode_ae_la32x2_rip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_rip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la32x2_rip_Slot_ae7_slot0_encode, Opcode_ae_la32x2_rip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_rip_Slot_ae8_slot0_encode, Opcode_ae_la32x2_rip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ric_Slot_ae7_slot0_encode, Opcode_ae_la32x2_ric_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_ric_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ric_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae7_slot0_encode, Opcode_ae_la32x2_ric1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ric1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic_Slot_ae7_slot0_encode, Opcode_ae_la16x4_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_ic_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ic_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae7_slot0_encode, Opcode_ae_la16x4_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ic1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic2_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ic2_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ip_Slot_ae_slot0_encode, Opcode_ae_la16x4_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4_ip_Slot_ae3_slot0_encode, Opcode_ae_la16x4_ip_Slot_ae3_slot1_encode, Opcode_ae_la16x4_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la16x4_ip_Slot_ae7_slot0_encode, Opcode_ae_la16x4_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_ip_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_rip_Slot_ae_slot0_encode, Opcode_ae_la16x4_rip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4_rip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_rip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la16x4_rip_Slot_ae7_slot0_encode, Opcode_ae_la16x4_rip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_rip_Slot_ae8_slot0_encode, Opcode_ae_la16x4_rip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ric_Slot_ae7_slot0_encode, Opcode_ae_la16x4_ric_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_ric_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ric_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae7_slot0_encode, Opcode_ae_la16x4_ric1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ric1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8_ic_Slot_ae7_slot0_encode, Opcode_ae_la8x8_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_ic_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ic_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la8x8_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8_ic1_Slot_ae7_slot0_encode, Opcode_ae_la8x8_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_ic1_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ic1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8_ic2_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ic2_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ip_Slot_ae_slot0_encode, Opcode_ae_la8x8_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8_ip_Slot_ae3_slot0_encode, Opcode_ae_la8x8_ip_Slot_ae3_slot1_encode, Opcode_ae_la8x8_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la8x8_ip_Slot_ae7_slot0_encode, Opcode_ae_la8x8_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_ip_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_rip_Slot_ae_slot0_encode, Opcode_ae_la8x8_rip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8_rip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_rip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la8x8_rip_Slot_ae7_slot0_encode, Opcode_ae_la8x8_rip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_rip_Slot_ae8_slot0_encode, Opcode_ae_la8x8_rip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8_ric_Slot_ae7_slot0_encode, Opcode_ae_la8x8_ric_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_ric_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ric_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la8x8_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8_ric1_Slot_ae7_slot0_encode, Opcode_ae_la8x8_ric1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_ric1_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ric1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2f24_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_ic_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_ic1_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae_slot0_encode, Opcode_ae_la32x2f24_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_ip_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae_slot0_encode, Opcode_ae_la32x2f24_rip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_rip_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_ric_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_ric1_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la24_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_la24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ic2_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa16x4_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa16x4_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_sa16x4_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ic2_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa16x4_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa16x4_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa16x4_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa8x8_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa8x8_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ic_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa8x8_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ic1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa8x8_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_sa8x8_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ic2_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa8x8_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa8x8_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa8x8_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa8x8_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_rip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa8x8_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa8x8_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ric_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa8x8_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ric1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2f24_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24_l_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24_l_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24_l_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24_l_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24_l_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24_l_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24_l_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24_l_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24_l_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24_l_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24x2_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24x2_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24x2_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24x2_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addicirc_encode_fns[] = { + 0, 0, 0, Opcode_ae_addicirc_Slot_ae_slot0_encode, Opcode_ae_addicirc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_addicirc_Slot_ae2_slot0_encode, Opcode_ae_addicirc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcirc_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_addcirc_xc2_Slot_ae_slot0_encode, Opcode_ae_addcirc_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_addcirc_xc2_Slot_ae2_slot0_encode, Opcode_ae_addcirc_xc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addcirc_xc2_Slot_ae4_slot0_encode, Opcode_ae_addcirc_xc2_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcirc_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_addcirc_xc1_Slot_ae_slot0_encode, Opcode_ae_addcirc_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_addcirc_xc1_Slot_ae2_slot0_encode, Opcode_ae_addcirc_xc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addcirc_xc1_Slot_ae4_slot0_encode, Opcode_ae_addcirc_xc1_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcirc_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_addcirc_xc_Slot_ae_slot0_encode, Opcode_ae_addcirc_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_addcirc_xc_Slot_ae2_slot0_encode, Opcode_ae_addcirc_xc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addcirc_xc_Slot_ae4_slot0_encode, Opcode_ae_addcirc_xc_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32ra64s_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32ra64s_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32ra64s_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32ra64s_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32ra64s_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32ra64s_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32ra64s_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32ra64s_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32ra64s_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32ra64s_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24ra64s_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s24ra64s_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24ra64s_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s24ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24ra64s_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s24ra64s_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24ra64s_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s24ra64s_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24ra64s_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s24ra64s_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s24ra64s_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2ra64s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24x2ra64s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4ra32s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4ra32s_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4ra32s_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4ra32s_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4ra32s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addbrba32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addbrba32_Slot_ae_slot0_encode, Opcode_ae_addbrba32_Slot_ae_slot1_encode, 0, 0, Opcode_ae_addbrba32_Slot_ae2_slot0_encode, Opcode_ae_addbrba32_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_addbrba32_Slot_ae3_slot1_encode, 0, 0, 0, 0, Opcode_ae_addbrba32_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addbrba32_Slot_ae4_slot0_encode, Opcode_ae_addbrba32_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_l_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_l_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bitswap_encode_fns[] = { + 0, 0, 0, Opcode_ae_bitswap_Slot_ae_slot0_encode, Opcode_ae_bitswap_Slot_ae_slot1_encode, 0, 0, Opcode_ae_bitswap_Slot_ae2_slot0_encode, Opcode_ae_bitswap_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_bitswap_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32js_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32js_Slot_ae_slot0_encode, 0, Opcode_ae_mul32js_Slot_ae_slot2_encode, Opcode_ae_mul32js_Slot_ae_slot3_encode, Opcode_ae_mul32js_Slot_ae2_slot0_encode, 0, Opcode_ae_mul32js_Slot_ae2_slot2_encode, 0, 0, Opcode_ae_mul32js_Slot_ae5_slot0_encode, 0, Opcode_ae_mul32js_Slot_ae5_slot2_encode, Opcode_ae_mul32js_Slot_ae6_slot0_encode, 0, Opcode_ae_mul32js_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32js_Slot_ae4_slot2_encode, Opcode_ae_mul32js_Slot_ae4_slot3_encode, Opcode_ae_mul32js_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsub32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsub32s_Slot_ae_slot0_encode, 0, Opcode_ae_addandsub32s_Slot_ae_slot2_encode, Opcode_ae_addandsub32s_Slot_ae_slot3_encode, Opcode_ae_addandsub32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32s_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsub32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32s_Slot_ae4_slot2_encode, Opcode_ae_addandsub32s_Slot_ae4_slot3_encode, Opcode_ae_addandsub32s_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsub32js_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsub32js_Slot_ae_slot0_encode, 0, Opcode_ae_addandsub32js_Slot_ae_slot2_encode, Opcode_ae_addandsub32js_Slot_ae_slot3_encode, Opcode_ae_addandsub32js_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32js_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsub32js_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32js_Slot_ae4_slot2_encode, Opcode_ae_addandsub32js_Slot_ae4_slot3_encode, Opcode_ae_addandsub32js_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsubrng32_Slot_ae_slot0_encode, 0, Opcode_ae_addandsubrng32_Slot_ae_slot2_encode, Opcode_ae_addandsubrng32_Slot_ae_slot3_encode, Opcode_ae_addandsubrng32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsubrng32_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_Slot_ae4_slot2_encode, Opcode_ae_addandsubrng32_Slot_ae4_slot3_encode, Opcode_ae_addandsubrng32_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsubrng32_h_Slot_ae_slot0_encode, 0, Opcode_ae_addandsubrng32_h_Slot_ae_slot2_encode, Opcode_ae_addandsubrng32_h_Slot_ae_slot3_encode, Opcode_ae_addandsubrng32_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_h_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsubrng32_h_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_h_Slot_ae4_slot2_encode, Opcode_ae_addandsubrng32_h_Slot_ae4_slot3_encode, Opcode_ae_addandsubrng32_h_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsubrng32_l_Slot_ae_slot0_encode, 0, Opcode_ae_addandsubrng32_l_Slot_ae_slot2_encode, Opcode_ae_addandsubrng32_l_Slot_ae_slot3_encode, Opcode_ae_addandsubrng32_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_l_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsubrng32_l_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_l_Slot_ae4_slot2_encode, Opcode_ae_addandsubrng32_l_Slot_ae4_slot3_encode, Opcode_ae_addandsubrng32_l_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addrng32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_addrng32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subrng32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_subrng32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rng32x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_rng32x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel16i_encode_fns[] = { + 0, 0, 0, Opcode_ae_sel16i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sel16i_Slot_ae_slot3_encode, Opcode_ae_sel16i_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_ae_sel16i_Slot_ae3_slot1_encode, Opcode_ae_sel16i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sel16i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sel16i_Slot_ae9_slot0_encode, 0, 0, Opcode_ae_sel16i_Slot_ae9_slot3_encode, 0, 0, 0, Opcode_ae_sel16i_Slot_ae10_slot3_encode, 0, 0, 0, Opcode_ae_sel16i_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel16i_n_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sel16i_n_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sel16i_n_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sel16i_n_Slot_ae4_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_shortswap_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_shortswap_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movab4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movab4_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movab4_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movab2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movab2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movab2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movab_encode_fns[] = { + 0, 0, 0, Opcode_ae_movab_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movab_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba_encode_fns[] = { + 0, 0, 0, Opcode_ae_movba_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movba_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba1x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movba1x2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movba1x2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movba4_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movba4_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movba2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movba2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movb2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movb2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movb4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movb4_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt16x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt16x4_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movt16x4_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movt16x4_Slot_ae6_slot0_encode, 0, Opcode_ae_movt16x4_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movt16x4_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movf16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movf16x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movf16x4_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movf16x4_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movf16x4_Slot_ae6_slot0_encode, 0, Opcode_ae_movf16x4_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movf16x4_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt32x2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt32x2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movt32x2_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movt32x2_Slot_ae6_slot0_encode, 0, Opcode_ae_movt32x2_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movt32x2_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movf32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movf32x2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movf32x2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movf32x2_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movf32x2_Slot_ae6_slot0_encode, 0, Opcode_ae_movf32x2_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movf32x2_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movsara7x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movsara7x2_Slot_ae_slot0_encode, Opcode_ae_movsara7x2_Slot_ae_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movsard7_encode_fns[] = { + 0, 0, 0, Opcode_ae_movsard7_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movsard7_Slot_ae2_slot0_encode, Opcode_ae_movsard7_Slot_ae2_slot1_encode, 0, Opcode_ae_movsard7_Slot_ae3_slot0_encode, 0, Opcode_ae_movsard7_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movasar_encode_fns[] = { + 0, 0, 0, Opcode_ae_movasar_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movasar_Slot_ae2_slot0_encode, Opcode_ae_movasar_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movda32x2_Slot_ae_slot0_encode, Opcode_ae_movda32x2_Slot_ae_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movda32x2_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda32_encode_fns[] = { + 0, 0, 0, Opcode_ae_movda32_Slot_ae_slot0_encode, Opcode_ae_movda32_Slot_ae_slot1_encode, 0, 0, Opcode_ae_movda32_Slot_ae2_slot0_encode, Opcode_ae_movda32_Slot_ae2_slot1_encode, 0, Opcode_ae_movda32_Slot_ae3_slot0_encode, Opcode_ae_movda32_Slot_ae3_slot1_encode, Opcode_ae_movda32_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda16x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movda16x2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda16_encode_fns[] = { + 0, 0, 0, Opcode_ae_movda16_Slot_ae_slot0_encode, Opcode_ae_movda16_Slot_ae_slot1_encode, 0, 0, Opcode_ae_movda16_Slot_ae2_slot0_encode, Opcode_ae_movda16_Slot_ae2_slot1_encode, 0, Opcode_ae_movda16_Slot_ae3_slot0_encode, Opcode_ae_movda16_Slot_ae3_slot1_encode, Opcode_ae_movda16_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movi_encode_fns[] = { + 0, 0, 0, Opcode_ae_movi_Slot_ae_slot0_encode, Opcode_ae_movi_Slot_ae_slot1_encode, Opcode_ae_movi_Slot_ae_slot2_encode, Opcode_ae_movi_Slot_ae_slot3_encode, Opcode_ae_movi_Slot_ae2_slot0_encode, Opcode_ae_movi_Slot_ae2_slot1_encode, 0, Opcode_ae_movi_Slot_ae3_slot0_encode, Opcode_ae_movi_Slot_ae3_slot1_encode, Opcode_ae_movi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode, Opcode_ae_truncp24a32x2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae2_slot0_encode, Opcode_ae_truncp24a32x2_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat16x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sat16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sat16x4_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt32x2f16_32_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt32x2f16_32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvt32x2f16_32_Slot_ae_slot3_encode, Opcode_ae_cvt32x2f16_32_Slot_ae2_slot0_encode, Opcode_ae_cvt32x2f16_32_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt32x2f16_10_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt32x2f16_10_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvt32x2f16_10_Slot_ae_slot3_encode, Opcode_ae_cvt32x2f16_10_Slot_ae2_slot0_encode, Opcode_ae_cvt32x2f16_10_Slot_ae2_slot1_encode, 0, Opcode_ae_cvt32x2f16_10_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext32x2d16_32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sext32x2d16_32_Slot_ae_slot0_encode, 0, Opcode_ae_sext32x2d16_32_Slot_ae_slot2_encode, Opcode_ae_sext32x2d16_32_Slot_ae_slot3_encode, Opcode_ae_sext32x2d16_32_Slot_ae2_slot0_encode, Opcode_ae_sext32x2d16_32_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext32x2d16_10_encode_fns[] = { + 0, 0, 0, Opcode_ae_sext32x2d16_10_Slot_ae_slot0_encode, 0, Opcode_ae_sext32x2d16_10_Slot_ae_slot2_encode, Opcode_ae_sext32x2d16_10_Slot_ae_slot3_encode, Opcode_ae_sext32x2d16_10_Slot_ae2_slot0_encode, Opcode_ae_sext32x2d16_10_Slot_ae2_slot1_encode, 0, Opcode_ae_sext32x2d16_10_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32f24s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32f24s_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32f24s_l_Slot_ae2_slot0_encode, Opcode_ae_cvta32f24s_l_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32f24s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32f24s_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32f24s_h_Slot_ae2_slot0_encode, Opcode_ae_cvta32f24s_h_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae3_slot0_encode, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca32x2f64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunci32x2f64s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci32x2f64s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_trunci32x2f64s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, Opcode_ae_trunci32x2f64s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci32x2f64s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca32f64s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca32f64s_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunca32f64s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca32f64s_l_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunci32f64s_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci32f64s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci32f64s_l_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f64ssym_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_round32x2f64ssym_Slot_ae_slot2_encode, Opcode_ae_round32x2f64ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f64sasym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round32x2f64sasym_Slot_ae_slot0_encode, 0, Opcode_ae_round32x2f64sasym_Slot_ae_slot2_encode, Opcode_ae_round32x2f64sasym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f48ssym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round32x2f48ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f48sasym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round32x2f48sasym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round16x4f32ssym_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_round16x4f32ssym_Slot_ae_slot2_encode, Opcode_ae_round16x4f32ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_round16x4f32ssym_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round16x4f32sasym_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_round16x4f32sasym_Slot_ae_slot2_encode, Opcode_ae_round16x4f32sasym_Slot_ae_slot3_encode, 0, 0, 0, Opcode_ae_round16x4f32sasym_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_round16x4f32sasym_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round24x2f48ssym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round24x2f48ssym_Slot_ae_slot0_encode, 0, 0, Opcode_ae_round24x2f48ssym_Slot_ae_slot3_encode, 0, 0, 0, Opcode_ae_round24x2f48ssym_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round24x2f48sasym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round24x2f48sasym_Slot_ae_slot0_encode, 0, 0, Opcode_ae_round24x2f48sasym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48x2sym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsp16q48x2sym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48x2asym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsp16q48x2asym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minabs32s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_minabs32s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxabs32s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_maxabs32s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16f24sym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsp16f24sym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16f24asym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsp16f24asym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mov_encode_fns[] = { + 0, 0, 0, Opcode_ae_mov_Slot_ae_slot0_encode, 0, Opcode_ae_mov_Slot_ae_slot2_encode, Opcode_ae_mov_Slot_ae_slot3_encode, Opcode_ae_mov_Slot_ae2_slot0_encode, Opcode_ae_mov_Slot_ae2_slot1_encode, Opcode_ae_mov_Slot_ae2_slot2_encode, Opcode_ae_mov_Slot_ae3_slot0_encode, Opcode_ae_mov_Slot_ae3_slot1_encode, Opcode_ae_mov_Slot_ae5_slot0_encode, 0, Opcode_ae_mov_Slot_ae5_slot2_encode, Opcode_ae_mov_Slot_ae6_slot0_encode, Opcode_ae_mov_Slot_ae6_slot1_encode, Opcode_ae_mov_Slot_ae6_slot2_encode, Opcode_ae_mov_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mov_Slot_ae7_slot2_encode, Opcode_ae_mov_Slot_ae7_slot3_encode, Opcode_ae_mov_Slot_ae8_slot0_encode, 0, Opcode_ae_mov_Slot_ae8_slot2_encode, Opcode_ae_mov_Slot_ae9_slot0_encode, 0, Opcode_ae_mov_Slot_ae9_slot2_encode, Opcode_ae_mov_Slot_ae9_slot3_encode, 0, 0, Opcode_ae_mov_Slot_ae10_slot2_encode, Opcode_ae_mov_Slot_ae10_slot3_encode, 0, 0, Opcode_ae_mov_Slot_ae4_slot2_encode, Opcode_ae_mov_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt64_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt64_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movt64_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movt64_Slot_ae6_slot0_encode, 0, Opcode_ae_movt64_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movt64_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movf64_encode_fns[] = { + 0, 0, 0, Opcode_ae_movf64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movf64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movf64_Slot_ae6_slot0_encode, 0, Opcode_ae_movf64_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movf64_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq56a32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvtq56a32s_Slot_ae_slot0_encode, Opcode_ae_cvtq56a32s_Slot_ae_slot1_encode, 0, 0, Opcode_ae_cvtq56a32s_Slot_ae2_slot0_encode, Opcode_ae_cvtq56a32s_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_cvtq56a32s_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt48a32_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt48a32_Slot_ae_slot0_encode, Opcode_ae_cvt48a32_Slot_ae_slot1_encode, 0, 0, Opcode_ae_cvt48a32_Slot_ae2_slot0_encode, Opcode_ae_cvt48a32_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_cvt48a32_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt64a32_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt64a32_Slot_ae_slot0_encode, Opcode_ae_cvt64a32_Slot_ae_slot1_encode, 0, 0, Opcode_ae_cvt64a32_Slot_ae2_slot0_encode, Opcode_ae_cvt64a32_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_cvt64a32_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq56p32s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvtq56p32s_l_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvtq56p32s_l_Slot_ae_slot3_encode, Opcode_ae_cvtq56p32s_l_Slot_ae2_slot0_encode, Opcode_ae_cvtq56p32s_l_Slot_ae2_slot1_encode, 0, Opcode_ae_cvtq56p32s_l_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq56p32s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvtq56p32s_h_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvtq56p32s_h_Slot_ae_slot3_encode, Opcode_ae_cvtq56p32s_h_Slot_ae2_slot0_encode, Opcode_ae_cvtq56p32s_h_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt64f32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt64f32_h_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvt64f32_h_Slot_ae_slot3_encode, Opcode_ae_cvt64f32_h_Slot_ae2_slot0_encode, Opcode_ae_cvt64f32_h_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt48f32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt48f32_l_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvt48f32_l_Slot_ae_slot3_encode, Opcode_ae_cvt48f32_l_Slot_ae2_slot0_encode, Opcode_ae_cvt48f32_l_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt48f32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt48f32_h_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvt48f32_h_Slot_ae_slot3_encode, Opcode_ae_cvt48f32_h_Slot_ae2_slot0_encode, Opcode_ae_cvt48f32_h_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat48s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sat48s_Slot_ae_slot2_encode, Opcode_ae_sat48s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satq56s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_satq56s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat24s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sat24s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = { + 0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_truncq32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minabs64s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_minabs64s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxabs64s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_maxabs64s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsq32f48sym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsq32f48sym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsq32f48asym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsq32f48asym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae2_slot0_encode, Opcode_ae_trunca32q48_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad32_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad32_l_Slot_ae2_slot0_encode, Opcode_ae_movad32_l_Slot_ae2_slot1_encode, 0, Opcode_ae_movad32_l_Slot_ae3_slot0_encode, Opcode_ae_movad32_l_Slot_ae3_slot1_encode, Opcode_ae_movad32_l_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movad32_l_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad32_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad32_h_Slot_ae2_slot0_encode, Opcode_ae_movad32_h_Slot_ae2_slot1_encode, 0, Opcode_ae_movad32_h_Slot_ae3_slot0_encode, 0, Opcode_ae_movad32_h_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_3_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad16_3_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad16_3_Slot_ae2_slot0_encode, Opcode_ae_movad16_3_Slot_ae2_slot1_encode, 0, Opcode_ae_movad16_3_Slot_ae3_slot0_encode, 0, Opcode_ae_movad16_3_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad16_2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad16_2_Slot_ae2_slot0_encode, Opcode_ae_movad16_2_Slot_ae2_slot1_encode, 0, Opcode_ae_movad16_2_Slot_ae3_slot0_encode, 0, Opcode_ae_movad16_2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_1_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad16_1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad16_1_Slot_ae2_slot0_encode, Opcode_ae_movad16_1_Slot_ae2_slot1_encode, 0, Opcode_ae_movad16_1_Slot_ae3_slot0_encode, 0, Opcode_ae_movad16_1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_0_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad16_0_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad16_0_Slot_ae2_slot0_encode, Opcode_ae_movad16_0_Slot_ae2_slot1_encode, 0, Opcode_ae_movad16_0_Slot_ae3_slot0_encode, 0, Opcode_ae_movad16_0_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movad16_0_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sra64_32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sra64_32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sra64_32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksr32_encode_fns[] = { + 0, 0, 0, Opcode_ae_pksr32_Slot_ae_slot0_encode, 0, Opcode_ae_pksr32_Slot_ae_slot2_encode, 0, Opcode_ae_pksr32_Slot_ae2_slot0_encode, 0, Opcode_ae_pksr32_Slot_ae2_slot2_encode, 0, 0, Opcode_ae_pksr32_Slot_ae5_slot0_encode, 0, Opcode_ae_pksr32_Slot_ae5_slot2_encode, Opcode_ae_pksr32_Slot_ae6_slot0_encode, 0, Opcode_ae_pksr32_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_pksr32_Slot_ae4_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksr24_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_pksr24_Slot_ae_slot2_encode, 0, Opcode_ae_pksr24_Slot_ae2_slot0_encode, 0, Opcode_ae_pksr24_Slot_ae2_slot2_encode, 0, 0, Opcode_ae_pksr24_Slot_ae5_slot0_encode, 0, Opcode_ae_pksr24_Slot_ae5_slot2_encode, Opcode_ae_pksr24_Slot_ae6_slot0_encode, 0, Opcode_ae_pksr24_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_pksr24_Slot_ae4_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksrf32_encode_fns[] = { + 0, 0, 0, Opcode_ae_pksrf32_Slot_ae_slot0_encode, 0, Opcode_ae_pksrf32_Slot_ae_slot2_encode, 0, Opcode_ae_pksrf32_Slot_ae2_slot0_encode, 0, Opcode_ae_pksrf32_Slot_ae2_slot2_encode, 0, 0, Opcode_ae_pksrf32_Slot_ae5_slot0_encode, 0, Opcode_ae_pksrf32_Slot_ae5_slot2_encode, Opcode_ae_pksrf32_Slot_ae6_slot0_encode, 0, Opcode_ae_pksrf32_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_pksrf32_Slot_ae4_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksr16_encode_fns[] = { + 0, 0, 0, Opcode_ae_pksr16_Slot_ae_slot0_encode, 0, Opcode_ae_pksr16_Slot_ae_slot2_encode, 0, Opcode_ae_pksr16_Slot_ae2_slot0_encode, 0, Opcode_ae_pksr16_Slot_ae2_slot2_encode, 0, 0, Opcode_ae_pksr16_Slot_ae5_slot0_encode, 0, Opcode_ae_pksr16_Slot_ae5_slot2_encode, Opcode_ae_pksr16_Slot_ae6_slot0_encode, 0, Opcode_ae_pksr16_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_pksr16_Slot_ae4_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32_encode_fns[] = { + 0, 0, 0, Opcode_ae_add32_Slot_ae_slot0_encode, 0, Opcode_ae_add32_Slot_ae_slot2_encode, Opcode_ae_add32_Slot_ae_slot3_encode, Opcode_ae_add32_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_add32_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub32_Slot_ae_slot0_encode, 0, Opcode_ae_sub32_Slot_ae_slot2_encode, Opcode_ae_sub32_Slot_ae_slot3_encode, Opcode_ae_sub32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsub32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsub32_Slot_ae_slot0_encode, 0, Opcode_ae_addsub32_Slot_ae_slot2_encode, Opcode_ae_addsub32_Slot_ae_slot3_encode, Opcode_ae_addsub32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subadd32_encode_fns[] = { + 0, 0, 0, Opcode_ae_subadd32_Slot_ae_slot0_encode, 0, Opcode_ae_subadd32_Slot_ae_slot2_encode, Opcode_ae_subadd32_Slot_ae_slot3_encode, Opcode_ae_subadd32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add16_encode_fns[] = { + 0, 0, 0, Opcode_ae_add16_Slot_ae_slot0_encode, 0, Opcode_ae_add16_Slot_ae_slot2_encode, Opcode_ae_add16_Slot_ae_slot3_encode, Opcode_ae_add16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub16_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub16_Slot_ae_slot0_encode, 0, Opcode_ae_sub16_Slot_ae_slot2_encode, Opcode_ae_sub16_Slot_ae_slot3_encode, Opcode_ae_sub16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_add32_hl_lh_Slot_ae_slot0_encode, 0, Opcode_ae_add32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_add32_hl_lh_Slot_ae_slot3_encode, Opcode_ae_add32_hl_lh_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsub32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_addsub32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_addsub32_hl_lh_Slot_ae_slot3_encode, Opcode_ae_addsub32_hl_lh_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg32_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg32_Slot_ae_slot0_encode, 0, Opcode_ae_neg32_Slot_ae_slot2_encode, Opcode_ae_neg32_Slot_ae_slot3_encode, Opcode_ae_neg32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_neg32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs32_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs32_Slot_ae_slot0_encode, 0, Opcode_ae_abs32_Slot_ae_slot2_encode, Opcode_ae_abs32_Slot_ae_slot3_encode, Opcode_ae_abs32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_abs32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg32_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_neg32_l_Slot_ae_slot2_encode, Opcode_ae_neg32_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add24s_Slot_ae_slot0_encode, 0, Opcode_ae_add24s_Slot_ae_slot2_encode, Opcode_ae_add24s_Slot_ae_slot3_encode, Opcode_ae_add24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub24s_Slot_ae_slot0_encode, 0, Opcode_ae_sub24s_Slot_ae_slot2_encode, Opcode_ae_sub24s_Slot_ae_slot3_encode, Opcode_ae_sub24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add32s_Slot_ae_slot0_encode, 0, Opcode_ae_add32s_Slot_ae_slot2_encode, Opcode_ae_add32s_Slot_ae_slot3_encode, Opcode_ae_add32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_add32s_Slot_ae3_slot0_encode, 0, Opcode_ae_add32s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, Opcode_ae_add32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub32s_Slot_ae_slot0_encode, 0, Opcode_ae_sub32s_Slot_ae_slot2_encode, Opcode_ae_sub32s_Slot_ae_slot3_encode, Opcode_ae_sub32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sub32s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sub32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsub32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsub32s_Slot_ae_slot0_encode, 0, Opcode_ae_addsub32s_Slot_ae_slot2_encode, Opcode_ae_addsub32s_Slot_ae_slot3_encode, Opcode_ae_addsub32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subadd32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_subadd32s_Slot_ae_slot0_encode, 0, Opcode_ae_subadd32s_Slot_ae_slot2_encode, Opcode_ae_subadd32s_Slot_ae_slot3_encode, Opcode_ae_subadd32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add16s_Slot_ae_slot0_encode, 0, Opcode_ae_add16s_Slot_ae_slot2_encode, Opcode_ae_add16s_Slot_ae_slot3_encode, Opcode_ae_add16s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_add16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_add16s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub16s_Slot_ae_slot0_encode, 0, Opcode_ae_sub16s_Slot_ae_slot2_encode, Opcode_ae_sub16s_Slot_ae_slot3_encode, Opcode_ae_sub16s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sub16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sub16s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_add32s_hl_lh_Slot_ae_slot0_encode, 0, Opcode_ae_add32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_add32s_hl_lh_Slot_ae_slot3_encode, Opcode_ae_add32s_hl_lh_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsub32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_addsub32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_addsub32s_hl_lh_Slot_ae_slot3_encode, Opcode_ae_addsub32s_hl_lh_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg24s_Slot_ae_slot0_encode, 0, Opcode_ae_neg24s_Slot_ae_slot2_encode, Opcode_ae_neg24s_Slot_ae_slot3_encode, Opcode_ae_neg24s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_neg24s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs24s_Slot_ae_slot0_encode, 0, Opcode_ae_abs24s_Slot_ae_slot2_encode, Opcode_ae_abs24s_Slot_ae_slot3_encode, Opcode_ae_abs24s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_abs24s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg32s_Slot_ae_slot0_encode, 0, Opcode_ae_neg32s_Slot_ae_slot2_encode, Opcode_ae_neg32s_Slot_ae_slot3_encode, Opcode_ae_neg32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_neg32s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_neg32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs32s_Slot_ae_slot0_encode, 0, Opcode_ae_abs32s_Slot_ae_slot2_encode, Opcode_ae_abs32s_Slot_ae_slot3_encode, Opcode_ae_abs32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_abs32s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_abs32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg16s_Slot_ae_slot0_encode, 0, Opcode_ae_neg16s_Slot_ae_slot2_encode, Opcode_ae_neg16s_Slot_ae_slot3_encode, Opcode_ae_neg16s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_neg16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_neg16s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs16s_Slot_ae_slot0_encode, 0, Opcode_ae_abs16s_Slot_ae_slot2_encode, Opcode_ae_abs16s_Slot_ae_slot3_encode, Opcode_ae_abs16s_Slot_ae2_slot0_encode, 0, Opcode_ae_abs16s_Slot_ae2_slot2_encode, Opcode_ae_abs16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_abs16s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_abs16s_Slot_ae4_slot2_encode, Opcode_ae_abs16s_Slot_ae4_slot3_encode, Opcode_ae_abs16s_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs16_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs16_Slot_ae_slot0_encode, 0, Opcode_ae_abs16_Slot_ae_slot2_encode, Opcode_ae_abs16_Slot_ae_slot3_encode, Opcode_ae_abs16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16js_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc16js_h_Slot_ae_slot2_encode, Opcode_ae_mulc16js_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc16js_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16js_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc16js_l_Slot_ae_slot2_encode, Opcode_ae_mulc16js_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc16js_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16js_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac16js_h_Slot_ae_slot2_encode, Opcode_ae_mulac16js_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac16js_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16js_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac16js_l_Slot_ae_slot2_encode, Opcode_ae_mulac16js_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac16js_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt16_encode_fns[] = { + 0, 0, 0, Opcode_ae_lt16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lt16_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_lt16_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_lt16_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lt16_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le16_encode_fns[] = { + 0, 0, 0, Opcode_ae_le16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_le16_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_le16_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_le16_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_le16_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq16_encode_fns[] = { + 0, 0, 0, Opcode_ae_eq16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_eq16_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_eq16_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_eq16_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_eq16_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt32_encode_fns[] = { + 0, 0, 0, Opcode_ae_lt32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lt32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_lt32_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_lt32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lt32_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le32_encode_fns[] = { + 0, 0, 0, Opcode_ae_le32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_le32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_le32_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_le32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_le32_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq32_encode_fns[] = { + 0, 0, 0, Opcode_ae_eq32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_eq32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_eq32_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_eq32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_eq32_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_min32_encode_fns[] = { + 0, 0, 0, Opcode_ae_min32_Slot_ae_slot0_encode, 0, Opcode_ae_min32_Slot_ae_slot2_encode, Opcode_ae_min32_Slot_ae_slot3_encode, Opcode_ae_min32_Slot_ae2_slot0_encode, 0, Opcode_ae_min32_Slot_ae2_slot2_encode, Opcode_ae_min32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_min32_Slot_ae4_slot2_encode, Opcode_ae_min32_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_max32_encode_fns[] = { + 0, 0, 0, Opcode_ae_max32_Slot_ae_slot0_encode, 0, Opcode_ae_max32_Slot_ae_slot2_encode, Opcode_ae_max32_Slot_ae_slot3_encode, Opcode_ae_max32_Slot_ae2_slot0_encode, 0, Opcode_ae_max32_Slot_ae2_slot2_encode, Opcode_ae_max32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_max32_Slot_ae4_slot2_encode, Opcode_ae_max32_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minmax32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_minmax32_Slot_ae_slot2_encode, Opcode_ae_minmax32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minmax16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_minmax16_Slot_ae_slot2_encode, Opcode_ae_minmax16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_min16_encode_fns[] = { + 0, 0, 0, Opcode_ae_min16_Slot_ae_slot0_encode, 0, Opcode_ae_min16_Slot_ae_slot2_encode, Opcode_ae_min16_Slot_ae_slot3_encode, Opcode_ae_min16_Slot_ae2_slot0_encode, 0, Opcode_ae_min16_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_min16_Slot_ae4_slot2_encode, Opcode_ae_min16_Slot_ae4_slot3_encode, Opcode_ae_min16_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_max16_encode_fns[] = { + 0, 0, 0, Opcode_ae_max16_Slot_ae_slot0_encode, 0, Opcode_ae_max16_Slot_ae_slot2_encode, Opcode_ae_max16_Slot_ae_slot3_encode, Opcode_ae_max16_Slot_ae2_slot0_encode, 0, Opcode_ae_max16_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_max16_Slot_ae4_slot2_encode, Opcode_ae_max16_Slot_ae4_slot3_encode, Opcode_ae_max16_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_add64_encode_fns[] = { + 0, 0, 0, Opcode_ae_add64_Slot_ae_slot0_encode, 0, Opcode_ae_add64_Slot_ae_slot2_encode, Opcode_ae_add64_Slot_ae_slot3_encode, Opcode_ae_add64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub64_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub64_Slot_ae_slot0_encode, 0, Opcode_ae_sub64_Slot_ae_slot2_encode, Opcode_ae_sub64_Slot_ae_slot3_encode, Opcode_ae_sub64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg64_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg64_Slot_ae_slot0_encode, 0, Opcode_ae_neg64_Slot_ae_slot2_encode, Opcode_ae_neg64_Slot_ae_slot3_encode, Opcode_ae_neg64_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_neg64_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs64_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs64_Slot_ae_slot0_encode, 0, Opcode_ae_abs64_Slot_ae_slot2_encode, Opcode_ae_abs64_Slot_ae_slot3_encode, Opcode_ae_abs64_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_abs64_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot0_encode, 0, Opcode_ae_addsq56s_Slot_ae_slot2_encode, Opcode_ae_addsq56s_Slot_ae_slot3_encode, Opcode_ae_addsq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot0_encode, 0, Opcode_ae_subsq56s_Slot_ae_slot2_encode, Opcode_ae_subsq56s_Slot_ae_slot3_encode, Opcode_ae_subsq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add64s_Slot_ae_slot0_encode, 0, Opcode_ae_add64s_Slot_ae_slot2_encode, Opcode_ae_add64s_Slot_ae_slot3_encode, Opcode_ae_add64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub64s_Slot_ae_slot0_encode, 0, Opcode_ae_sub64s_Slot_ae_slot2_encode, Opcode_ae_sub64s_Slot_ae_slot3_encode, Opcode_ae_sub64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot0_encode, 0, Opcode_ae_negsq56s_Slot_ae_slot2_encode, Opcode_ae_negsq56s_Slot_ae_slot3_encode, Opcode_ae_negsq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot0_encode, 0, Opcode_ae_abssq56s_Slot_ae_slot2_encode, Opcode_ae_abssq56s_Slot_ae_slot3_encode, Opcode_ae_abssq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg64s_Slot_ae_slot0_encode, 0, Opcode_ae_neg64s_Slot_ae_slot2_encode, Opcode_ae_neg64s_Slot_ae_slot3_encode, Opcode_ae_neg64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs64s_Slot_ae_slot0_encode, 0, Opcode_ae_abs64s_Slot_ae_slot2_encode, Opcode_ae_abs64s_Slot_ae_slot3_encode, Opcode_ae_abs64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_and_encode_fns[] = { + 0, 0, 0, Opcode_ae_and_Slot_ae_slot0_encode, 0, 0, Opcode_ae_and_Slot_ae_slot3_encode, Opcode_ae_and_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_and_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nand_encode_fns[] = { + 0, 0, 0, Opcode_ae_nand_Slot_ae_slot0_encode, 0, 0, Opcode_ae_nand_Slot_ae_slot3_encode, Opcode_ae_nand_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_or_encode_fns[] = { + 0, 0, 0, Opcode_ae_or_Slot_ae_slot0_encode, 0, 0, Opcode_ae_or_Slot_ae_slot3_encode, Opcode_ae_or_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_or_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_xor_encode_fns[] = { + 0, 0, 0, Opcode_ae_xor_Slot_ae_slot0_encode, 0, 0, Opcode_ae_xor_Slot_ae_slot3_encode, Opcode_ae_xor_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_xor_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai24_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai24_Slot_ae_slot3_encode, Opcode_ae_slai24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srli24_Slot_ae_slot3_encode, Opcode_ae_srli24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai24_Slot_ae_slot3_encode, Opcode_ae_srai24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas24_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas24_Slot_ae_slot3_encode, Opcode_ae_slas24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srls24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srls24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srls24_Slot_ae_slot3_encode, Opcode_ae_srls24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sras24_encode_fns[] = { + 0, 0, 0, Opcode_ae_sras24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sras24_Slot_ae_slot3_encode, Opcode_ae_sras24_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sras24_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai16_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai16_Slot_ae_slot3_encode, Opcode_ae_srai16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai16r_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai16r_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai16r_Slot_ae_slot3_encode, Opcode_ae_srai16r_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai32_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai32_Slot_ae_slot3_encode, Opcode_ae_slai32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli32_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srli32_Slot_ae_slot3_encode, Opcode_ae_srli32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai32_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai32_Slot_ae_slot3_encode, Opcode_ae_srai32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai32r_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai32r_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai32r_Slot_ae_slot3_encode, Opcode_ae_srai32r_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas32_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas32_Slot_ae_slot3_encode, Opcode_ae_slas32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srls32_encode_fns[] = { + 0, 0, 0, Opcode_ae_srls32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srls32_Slot_ae_slot3_encode, Opcode_ae_srls32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sras32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sras32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sras32_Slot_ae_slot3_encode, Opcode_ae_sras32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa32_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srla32_encode_fns[] = { + 0, 0, 0, Opcode_ae_srla32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srla32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_srla32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai16s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai16s_Slot_ae_slot3_encode, Opcode_ae_slai16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa16s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa16s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slaa16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa16s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa16s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sraa16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa16rs_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa16rs_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa16rs_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sraa16rs_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai24s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai24s_Slot_ae_slot3_encode, Opcode_ae_slai24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas24s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas24s_Slot_ae_slot3_encode, Opcode_ae_slas24s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slas24s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai32s_Slot_ae_slot3_encode, Opcode_ae_slai32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas32s_Slot_ae_slot3_encode, Opcode_ae_slas32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa32s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slaa32s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa32s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sraa32s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32rs_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa32rs_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa32rs_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slasq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_slasq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slasq56_Slot_ae_slot3_encode, Opcode_ae_slasq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot3_encode, Opcode_ae_srlsq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srasq56_Slot_ae_slot3_encode, Opcode_ae_srasq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaaq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaaq56_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaaq56_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slaaq56_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sraaq56_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai64_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai64_Slot_ae_slot3_encode, Opcode_ae_slai64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli64_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srli64_Slot_ae_slot3_encode, Opcode_ae_srli64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai64_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai64_Slot_ae_slot3_encode, Opcode_ae_srai64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas64_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas64_Slot_ae_slot3_encode, Opcode_ae_slas64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srls64_encode_fns[] = { + 0, 0, 0, Opcode_ae_srls64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srls64_Slot_ae_slot3_encode, Opcode_ae_srls64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sras64_encode_fns[] = { + 0, 0, 0, Opcode_ae_sras64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sras64_Slot_ae_slot3_encode, Opcode_ae_sras64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa64_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa64_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slaa64_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srla64_encode_fns[] = { + 0, 0, 0, Opcode_ae_srla64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srla64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa64_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaisq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaisq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slaisq56s_Slot_ae_slot3_encode, Opcode_ae_slaisq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slassq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slassq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slassq56s_Slot_ae_slot3_encode, Opcode_ae_slassq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaasq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaasq56s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaasq56s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slaasq56s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai64s_Slot_ae_slot3_encode, Opcode_ae_slai64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas64s_Slot_ae_slot3_encode, Opcode_ae_slas64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa64s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt64_encode_fns[] = { + 0, 0, 0, Opcode_ae_lt64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lt64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lt64_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lt64_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le64_encode_fns[] = { + 0, 0, 0, Opcode_ae_le64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_le64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_le64_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_le64_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq64_encode_fns[] = { + 0, 0, 0, Opcode_ae_eq64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_eq64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_eq64_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_eq64_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_max64_encode_fns[] = { + 0, 0, 0, Opcode_ae_max64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_max64_Slot_ae_slot3_encode, Opcode_ae_max64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_min64_encode_fns[] = { + 0, 0, 0, Opcode_ae_min64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_min64_Slot_ae_slot3_encode, Opcode_ae_min64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsa64_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsa64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsa64_Slot_ae2_slot0_encode, Opcode_ae_nsa64_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsaz16_0_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsaz16_0_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsaz16_0_Slot_ae2_slot0_encode, Opcode_ae_nsaz16_0_Slot_ae2_slot1_encode, 0, Opcode_ae_nsaz16_0_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsaz32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsaz32_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsaz32_l_Slot_ae2_slot0_encode, Opcode_ae_nsaz32_l_Slot_ae2_slot1_encode, 0, Opcode_ae_nsaz32_l_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_ll_Slot_ae_slot2_encode, Opcode_ae_muls32f48p16s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32f48p16s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32s_ll_Slot_ae_slot2_encode, Opcode_ae_mulf32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32_ll_Slot_ae_slot2_encode, Opcode_ae_mul32_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32r_ll_Slot_ae_slot2_encode, Opcode_ae_mulf32r_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32r_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32r_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32ra_ll_Slot_ae_slot2_encode, Opcode_ae_mulf32ra_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32ra_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_lh_Slot_ae_slot2_encode, Opcode_ae_muls32f48p16s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32f48p16s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32s_lh_Slot_ae_slot2_encode, Opcode_ae_mulf32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32_lh_Slot_ae_slot2_encode, Opcode_ae_mul32_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32r_lh_Slot_ae_slot2_encode, Opcode_ae_mulf32r_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32r_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32r_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32ra_lh_Slot_ae_slot2_encode, Opcode_ae_mulf32ra_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32ra_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_hh_Slot_ae_slot2_encode, Opcode_ae_muls32f48p16s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32f48p16s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32s_hh_Slot_ae_slot2_encode, Opcode_ae_mulf32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32_hh_Slot_ae_slot2_encode, Opcode_ae_mul32_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32r_hh_Slot_ae_slot2_encode, Opcode_ae_mulf32r_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32r_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32r_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32ra_hh_Slot_ae_slot2_encode, Opcode_ae_mulf32ra_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32ra_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_ll_Slot_ae_slot2_encode, Opcode_ae_mulas32f48p16s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulas32f48p16s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32s_ll_Slot_ae_slot2_encode, Opcode_ae_mulaf32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32_ll_Slot_ae_slot2_encode, Opcode_ae_mula32_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32r_ll_Slot_ae_slot2_encode, Opcode_ae_mulaf32r_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32r_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32r_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32ra_ll_Slot_ae_slot2_encode, Opcode_ae_mulaf32ra_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32ra_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_lh_Slot_ae_slot2_encode, Opcode_ae_mulas32f48p16s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulas32f48p16s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32s_lh_Slot_ae_slot2_encode, Opcode_ae_mulaf32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32_lh_Slot_ae_slot2_encode, Opcode_ae_mula32_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32r_lh_Slot_ae_slot2_encode, Opcode_ae_mulaf32r_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32r_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32r_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32ra_lh_Slot_ae_slot2_encode, Opcode_ae_mulaf32ra_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32ra_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_hh_Slot_ae_slot2_encode, Opcode_ae_mulas32f48p16s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulas32f48p16s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32s_hh_Slot_ae_slot2_encode, Opcode_ae_mulaf32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32_hh_Slot_ae_slot2_encode, Opcode_ae_mula32_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32r_hh_Slot_ae_slot2_encode, Opcode_ae_mulaf32r_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32r_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32r_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32ra_hh_Slot_ae_slot2_encode, Opcode_ae_mulaf32ra_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32ra_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_ll_Slot_ae_slot2_encode, Opcode_ae_mulss32f48p16s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulss32f48p16s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32s_ll_Slot_ae_slot2_encode, Opcode_ae_mulsf32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32_ll_Slot_ae_slot2_encode, Opcode_ae_muls32_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32r_ll_Slot_ae_slot2_encode, Opcode_ae_mulsf32r_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32r_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32r_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32ra_ll_Slot_ae_slot2_encode, Opcode_ae_mulsf32ra_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32ra_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_lh_Slot_ae_slot2_encode, Opcode_ae_mulss32f48p16s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulss32f48p16s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32s_lh_Slot_ae_slot2_encode, Opcode_ae_mulsf32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32_lh_Slot_ae_slot2_encode, Opcode_ae_muls32_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32r_lh_Slot_ae_slot2_encode, Opcode_ae_mulsf32r_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32r_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32r_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32ra_lh_Slot_ae_slot2_encode, Opcode_ae_mulsf32ra_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32ra_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_hh_Slot_ae_slot2_encode, Opcode_ae_mulss32f48p16s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulss32f48p16s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32s_hh_Slot_ae_slot2_encode, Opcode_ae_mulsf32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32_hh_Slot_ae_slot2_encode, Opcode_ae_muls32_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32r_hh_Slot_ae_slot2_encode, Opcode_ae_mulsf32r_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32r_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32r_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32ra_hh_Slot_ae_slot2_encode, Opcode_ae_mulsf32ra_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32ra_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32u_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32u_ll_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mul32u_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32u_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32u_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32u_ll_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mula32u_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32u_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32u_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32u_ll_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_muls32u_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32u_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_33_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_33_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_33_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_22_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_22_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_32_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_21_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_21_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_21_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_31_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_31_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_31_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_30_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_30_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_30_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_10_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_10_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_10_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_20_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_20_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_20_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_11_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_11_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_11_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_00_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf16ss_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf16ss_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_33_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_33_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_33_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_22_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_22_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_32_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_21_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_21_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_21_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_31_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_31_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_31_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_30_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_30_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_30_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_10_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_10_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_10_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_20_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_20_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_20_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_11_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_11_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_11_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_00_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf16ss_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf16ss_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_33_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_33_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_33_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_22_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_22_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_32_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_21_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_21_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_21_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_31_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_31_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_31_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_30_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_30_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_30_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_10_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_10_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_10_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_20_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_20_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_20_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_11_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_11_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_11_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_00_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf16ss_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf16ss_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16s_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul16s_00_Slot_ae_slot2_encode, Opcode_ae_mul16s_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul16s_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul16s_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16s_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula16s_00_Slot_ae_slot2_encode, Opcode_ae_mula16s_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula16s_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula16s_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls16s_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls16s_00_Slot_ae_slot2_encode, Opcode_ae_muls16s_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls16s_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls16s_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_33_22_Slot_ae_slot2_encode, Opcode_ae_mulaafd16ss_33_22_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_13_02_Slot_ae_slot2_encode, Opcode_ae_mulaafd16ss_13_02_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_11_00_Slot_ae_slot2_encode, Opcode_ae_mulaafd16ss_11_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_33_22_Slot_ae_slot2_encode, Opcode_ae_mulssfd16ss_33_22_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_13_02_Slot_ae_slot2_encode, Opcode_ae_mulssfd16ss_13_02_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_11_00_Slot_ae_slot2_encode, Opcode_ae_mulssfd16ss_11_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_33_22_Slot_ae_slot2_encode, Opcode_ae_mulzaafd16ss_33_22_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_13_02_Slot_ae_slot2_encode, Opcode_ae_mulzaafd16ss_13_02_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_11_00_Slot_ae_slot2_encode, Opcode_ae_mulzaafd16ss_11_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_33_22_Slot_ae_slot2_encode, Opcode_ae_mulzssfd16ss_33_22_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_13_02_Slot_ae_slot2_encode, Opcode_ae_mulzssfd16ss_13_02_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_11_00_Slot_ae_slot2_encode, Opcode_ae_mulzssfd16ss_11_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf48q32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf48q32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulf48q32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf48q32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf48q32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf48q32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf48q32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulf48q32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf48q32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf48q32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulq32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulq32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf48q32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulaf48q32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf48q32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf48q32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulaf48q32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf48q32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf48q32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulsf48q32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf48q32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf48q32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulsf48q32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf48q32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24x2ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp24x2ra_Slot_ae_slot2_encode, Opcode_ae_mulfp24x2ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp24x2ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp24x2ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24x2r_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp24x2r_Slot_ae_slot2_encode, Opcode_ae_mulfp24x2r_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp24x2r_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp24x2r_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24x2ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp24x2ra_Slot_ae_slot2_encode, Opcode_ae_mulafp24x2ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp24x2ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp24x2ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24x2r_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp24x2r_Slot_ae_slot2_encode, Opcode_ae_mulafp24x2r_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp24x2r_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp24x2r_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24x2ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp24x2ra_Slot_ae_slot2_encode, Opcode_ae_mulsfp24x2ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp24x2ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp24x2ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24x2r_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp24x2r_Slot_ae_slot2_encode, Opcode_ae_mulsfp24x2r_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp24x2r_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp24x2r_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaad32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaad32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzasd32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzasd32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsad32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzsad32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssd32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzssd32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaafd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaad32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaafd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaad32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulasfd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulasd32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulasfd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulasd32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsafd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulsafd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsad32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulsad32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssfd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssd32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulssfd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulssd32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l0_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l0_Slot_ae_slot2_encode, Opcode_ae_mul32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l1_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l1_Slot_ae_slot2_encode, Opcode_ae_mul32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l2_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l2_Slot_ae_slot2_encode, Opcode_ae_mul32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l3_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l3_Slot_ae_slot2_encode, Opcode_ae_mul32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h0_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h0_Slot_ae_slot2_encode, Opcode_ae_mul32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h1_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h1_Slot_ae_slot2_encode, Opcode_ae_mul32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h2_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h2_Slot_ae_slot2_encode, Opcode_ae_mul32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h3_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h3_Slot_ae_slot2_encode, Opcode_ae_mul32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l0_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l0_Slot_ae_slot2_encode, Opcode_ae_mula32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l1_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l1_Slot_ae_slot2_encode, Opcode_ae_mula32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l2_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l2_Slot_ae_slot2_encode, Opcode_ae_mula32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l3_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l3_Slot_ae_slot2_encode, Opcode_ae_mula32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h0_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h0_Slot_ae_slot2_encode, Opcode_ae_mula32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h1_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h1_Slot_ae_slot2_encode, Opcode_ae_mula32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h2_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h2_Slot_ae_slot2_encode, Opcode_ae_mula32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h3_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h3_Slot_ae_slot2_encode, Opcode_ae_mula32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l0_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l0_Slot_ae_slot2_encode, Opcode_ae_muls32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l1_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l1_Slot_ae_slot2_encode, Opcode_ae_muls32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l2_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l2_Slot_ae_slot2_encode, Opcode_ae_muls32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l3_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l3_Slot_ae_slot2_encode, Opcode_ae_muls32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h0_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h0_Slot_ae_slot2_encode, Opcode_ae_muls32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h1_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h1_Slot_ae_slot2_encode, Opcode_ae_muls32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h2_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h2_Slot_ae_slot2_encode, Opcode_ae_muls32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h3_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h3_Slot_ae_slot2_encode, Opcode_ae_muls32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulaad32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulaad32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulasd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulasd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsad32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulsad32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsad32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulsad32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulssd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulssd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsad32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzsad32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsad32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzsad32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae_slot2_encode, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae_slot2_encode, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae_slot2_encode, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae_slot2_encode, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h2_l3_Slot_ae_slot2_encode, Opcode_ae_mulaad32x16_h2_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h0_l1_Slot_ae_slot2_encode, Opcode_ae_mulaad32x16_h0_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x16x2_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp32x16x2_h_Slot_ae_slot2_encode, Opcode_ae_mulp32x16x2_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp32x16x2_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp32x16x2_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2rs_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_h_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2rs_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2rs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2ras_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_h_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2ras_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_h_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x16x2_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp32x16x2_l_Slot_ae_slot2_encode, Opcode_ae_mulp32x16x2_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp32x16x2_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp32x16x2_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2rs_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_l_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2rs_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2rs_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2ras_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_l_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2ras_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_l_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x16x2_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap32x16x2_h_Slot_ae_slot2_encode, Opcode_ae_mulap32x16x2_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap32x16x2_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap32x16x2_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2rs_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_h_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2rs_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2rs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2ras_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_h_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2ras_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_h_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x16x2_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap32x16x2_l_Slot_ae_slot2_encode, Opcode_ae_mulap32x16x2_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap32x16x2_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap32x16x2_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2rs_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_l_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2rs_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2rs_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2ras_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_l_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2ras_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_l_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x16x2_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_h_Slot_ae_slot2_encode, Opcode_ae_mulsp32x16x2_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp32x16x2_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2rs_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2ras_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_h_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x16x2_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_l_Slot_ae_slot2_encode, Opcode_ae_mulsp32x16x2_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp32x16x2_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2rs_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2ras_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_l_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp32x2_Slot_ae_slot2_encode, Opcode_ae_mulp32x2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp32x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp32x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2rs_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2rs_Slot_ae_slot2_encode, Opcode_ae_mulfp32x2rs_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x2rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x2rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2ras_Slot_ae_slot2_encode, Opcode_ae_mulfp32x2ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x2ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x2ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2ts_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2ts_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulfp32x2ts_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x2ts_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x2t_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp32x2t_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulp32x2t_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp32x2t_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap32x2_Slot_ae_slot2_encode, Opcode_ae_mulap32x2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap32x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap32x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2rs_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2rs_Slot_ae_slot2_encode, Opcode_ae_mulafp32x2rs_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x2rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x2rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2ras_Slot_ae_slot2_encode, Opcode_ae_mulafp32x2ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x2ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x2ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2ts_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2ts_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulafp32x2ts_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x2ts_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x2t_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap32x2t_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulap32x2t_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap32x2t_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp32x2_Slot_ae_slot2_encode, Opcode_ae_mulsp32x2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp32x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp32x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2rs_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2rs_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x2rs_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x2rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x2rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2ras_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x2ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x2ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x2ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2ts_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2ts_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulsfp32x2ts_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x2ts_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x2t_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp32x2t_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulsp32x2t_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp32x2t_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp16x4s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp16x4s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp16x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp16x4ras_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc32_Slot_ae_slot2_encode, Opcode_ae_mulc32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc32_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulc32_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc24ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc24ra_Slot_ae_slot2_encode, Opcode_ae_mulfc24ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc24ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfc24ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32ras_Slot_ae_slot2_encode, Opcode_ae_mulfc32ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc32ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfc32ras_Slot_ae5_slot2_encode, 0, 0, Opcode_ae_mulfc32ras_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfc32ras_Slot_ae4_slot2_encode, Opcode_ae_mulfc32ras_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32x16_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc32x16_l_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulc32x16_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulc32x16_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32x16ras_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae_slot2_encode, Opcode_ae_mulfc32x16ras_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae5_slot2_encode, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32x16_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc32x16_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulc32x16_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulc32x16_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32x16ras_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae_slot2_encode, Opcode_ae_mulfc32x16ras_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae5_slot2_encode, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac32_Slot_ae_slot2_encode, Opcode_ae_mulac32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac32_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulac32_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc24ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc24ra_Slot_ae_slot2_encode, Opcode_ae_mulafc24ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc24ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafc24ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32ras_Slot_ae_slot2_encode, Opcode_ae_mulafc32ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc32ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafc32ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32x16_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac32x16_l_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulac32x16_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulac32x16_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32x16ras_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_l_Slot_ae_slot2_encode, Opcode_ae_mulafc32x16ras_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc32x16ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32x16_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac32x16_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulac32x16_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulac32x16_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32x16ras_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_h_Slot_ae_slot2_encode, Opcode_ae_mulafc32x16ras_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc32x16ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16x4ss_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf16x4ss_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16x4ss_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf16x4ss_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16x4ss_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf16x4ss_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul16x4s_Slot_ae_slot2_encode, Opcode_ae_mul16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul16x4s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula16x4s_Slot_ae_slot2_encode, Opcode_ae_mula16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls16x4s_Slot_ae_slot2_encode, Opcode_ae_muls16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul16x4_Slot_ae_slot2_encode, Opcode_ae_mul16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul16x4_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula16x4_Slot_ae_slot2_encode, Opcode_ae_mula16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls16x4_Slot_ae_slot2_encode, Opcode_ae_muls16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2s_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2s_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2s_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x2s_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2ra_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2ra_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2ra_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x2ra_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2s_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2s_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2s_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x2s_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2ra_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2ra_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2ra_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x2ra_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2s_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2s_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2s_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x2s_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2ra_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2ra_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2ra_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x2ra_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2s_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2s_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2s_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x2s_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2ra_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2ra_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2ra_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x2ra_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc16s_h_Slot_ae_slot2_encode, Opcode_ae_mulc16s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc16s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc16s_l_Slot_ae_slot2_encode, Opcode_ae_mulc16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac16s_h_Slot_ae_slot2_encode, Opcode_ae_mulac16s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac16s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac16s_l_Slot_ae_slot2_encode, Opcode_ae_mulac16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc16ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc16ras_Slot_ae_slot2_encode, Opcode_ae_mulfc16ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc16ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc16ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc16ras_Slot_ae_slot2_encode, Opcode_ae_mulafc16ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc16ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16js_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul16js_Slot_ae_slot3_encode, Opcode_ae_mul16js_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng16ras_s1_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot0_encode, 0, Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot2_encode, Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot3_encode, Opcode_ae_addandsubrng16ras_s1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng16ras_s1_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsubrng16ras_s1_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng16ras_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot0_encode, 0, Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot2_encode, Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot3_encode, Opcode_ae_addandsubrng16ras_s2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng16ras_s2_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsubrng16ras_s2_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_conj16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_conj16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq16x2_fir_3_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_3_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_3_Slot_ae7_slot2_encode, Opcode_ae_mulfq16x2_fir_3_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq16x2_fir_2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_2_Slot_ae7_slot2_encode, Opcode_ae_mulfq16x2_fir_2_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq16x2_fir_1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_1_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_1_Slot_ae7_slot2_encode, Opcode_ae_mulfq16x2_fir_1_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq16x2_fir_0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_0_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_0_Slot_ae7_slot2_encode, Opcode_ae_mulfq16x2_fir_0_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq16x2_fir_3_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_3_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_3_Slot_ae7_slot2_encode, Opcode_ae_mulafq16x2_fir_3_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq16x2_fir_2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_2_Slot_ae7_slot2_encode, Opcode_ae_mulafq16x2_fir_2_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq16x2_fir_1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_1_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_1_Slot_ae7_slot2_encode, Opcode_ae_mulafq16x2_fir_1_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq16x2_fir_0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_0_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_0_Slot_ae7_slot2_encode, Opcode_ae_mulafq16x2_fir_0_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaafq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaafq32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaafq32x16_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaafq32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaafq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaafq32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaafq32x16_Slot_ae7_slot2_encode, Opcode_ae_mulaaaafq32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaaq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaaq32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaaq32x16_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaaq32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaaq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaaq32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaaq32x16_Slot_ae7_slot2_encode, Opcode_ae_mulaaaaq32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul16_00_Slot_ae_slot2_encode, Opcode_ae_mul16_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul16_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul16_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula16_00_Slot_ae_slot2_encode, Opcode_ae_mula16_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula16_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula16_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaaq16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaaaaq16_Slot_ae_slot2_encode, Opcode_ae_mulzaaaaq16_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaaaaq16_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaaaaq16_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaaq16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaaaaq16_Slot_ae_slot2_encode, Opcode_ae_mulaaaaq16_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaaaaq16_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaaaaq16_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_div64d32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_div64d32_h_Slot_ae_slot0_encode, 0, Opcode_ae_div64d32_h_Slot_ae_slot2_encode, Opcode_ae_div64d32_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_div64d32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_div64d32_l_Slot_ae_slot0_encode, 0, Opcode_ae_div64d32_l_Slot_ae_slot2_encode, Opcode_ae_div64d32_l_Slot_ae_slot3_encode, 0, 0, 0, Opcode_ae_div64d32_l_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sha32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl32t_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16t_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16c_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16c_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16c_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16c_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldsht_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = { + 0, 0, 0, Opcode_ae_lb_Slot_ae_slot0_encode, Opcode_ae_lb_Slot_ae_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_lb_Slot_ae3_slot0_encode, Opcode_ae_lb_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = { + 0, 0, 0, Opcode_ae_lbi_Slot_ae_slot0_encode, Opcode_ae_lbi_Slot_ae_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_lbi_Slot_ae3_slot0_encode, Opcode_ae_lbi_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbk_Slot_ae3_slot0_encode, Opcode_ae_lbk_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbki_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbs_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbsi_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbsi_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = { + 0, 0, 0, Opcode_ae_db_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_db_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = { + 0, 0, 0, Opcode_ae_dbi_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_dbi_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_db_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_dbi_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_db_ic1_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_dbi_ic1_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_db_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_dbi_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_ardecnorm16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_ardecnorm16_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbki_dbi_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbki_dbi_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbki_dbi_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbki_dbi_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbki_dbi_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbki_dbi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbi_dbi_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbi_dbi_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbi_dbi_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbi_dbi_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbi_dbi_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbi_dbi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbk_db_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbk_db_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbk_db_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbk_db_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbk_db_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbk_db_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lb_db_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lb_db_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lb_db_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lb_db_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lb_db_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lb_db_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vlel32t_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vlel16t_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sb_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbi_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vles16c_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbf_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sb_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbi_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vles16c_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbf_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sb_ic1_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbi_ic1_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vles16c_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbf_ic1_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sb_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbi_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vles16c_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbf_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sext32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movae_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movae_Slot_ae3_slot0_encode, Opcode_ae_movae_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movea_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movea_Slot_ae3_slot0_encode, Opcode_ae_movea_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_moveep_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_moveep_Slot_ae_slot2_encode, Opcode_ae_moveep_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext72_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sext72_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add72_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_add72_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub72_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sub72_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add72x64_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_add72x64_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub72x64_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sub72x64_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32ep_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32ep_hh_Slot_ae_slot2_encode, Opcode_ae_mul32ep_hh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32ep_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32ep_hh_Slot_ae_slot2_encode, Opcode_ae_mula32ep_hh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32ep_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32ep_hh_Slot_ae_slot2_encode, Opcode_ae_muls32ep_hh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32ep_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaad32ep_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32ep_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssd32ep_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32ep_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaad32ep_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32ep_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssd32ep_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32usep_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32usep_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaad32usep_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32usep_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32usep_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaad32usep_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32usep_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32usep_lh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32usep_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32usep_lh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32usep_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32usep_ll_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32usep_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32usep_ll_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai72_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_srai72_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai72_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_slai72_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat64s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sat64s_Slot_ae_slot2_encode, Opcode_ae_sat64s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16si_n_encode_fns[] = { + 0, 0, Opcode_ae_l16si_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16ui_n_encode_fns[] = { + 0, 0, Opcode_ae_l16ui_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16i_n_encode_fns[] = { + 0, 0, Opcode_ae_s16i_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lalign128_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_lalign128_i_Slot_ae_slot0_encode, Opcode_ae_lalign128_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_lalign128_i_Slot_ae2_slot0_encode, Opcode_ae_lalign128_i_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lalign128_i_Slot_ae7_slot0_encode, Opcode_ae_lalign128_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_lalign128_i_Slot_ae8_slot0_encode, Opcode_ae_lalign128_i_Slot_ae8_slot1_encode, 0, Opcode_ae_lalign128_i_Slot_ae9_slot0_encode, Opcode_ae_lalign128_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_lalign128_i_Slot_ae10_slot0_encode, Opcode_ae_lalign128_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_salign128_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_salign128_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_salign128_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la128_pp_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_la128_pp_Slot_ae_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la128_pp_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa128pos_fp_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa128pos_fp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa128pos_fp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x4s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x4s_ip_Slot_ae_slot0_encode, Opcode_ae_la8x4s_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x4s_ip_Slot_ae2_slot0_encode, Opcode_ae_la8x4s_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x4s_ip_Slot_ae8_slot0_encode, Opcode_ae_la8x4s_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x4s_ip_Slot_ae9_slot0_encode, Opcode_ae_la8x4s_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x4s_ip_Slot_ae10_slot0_encode, Opcode_ae_la8x4s_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x4u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x4u_ip_Slot_ae_slot0_encode, Opcode_ae_la8x4u_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x4u_ip_Slot_ae2_slot0_encode, Opcode_ae_la8x4u_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x4u_ip_Slot_ae8_slot0_encode, Opcode_ae_la8x4u_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x4u_ip_Slot_ae9_slot0_encode, Opcode_ae_la8x4u_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x4u_ip_Slot_ae10_slot0_encode, Opcode_ae_la8x4u_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2_ip_Slot_ae_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ip_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2_ip_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ip_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2_ip_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ip_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2_ip_Slot_ae_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ip_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2_ip_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ip_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2_ip_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ip_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2_ip_Slot_ae_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ip_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2_ip_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ip_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2_ip_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ip_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2_ic_Slot_ae_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2_ic_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2_ic_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2_ic_Slot_ae_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2_ic_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2_ic_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2_ic_Slot_ae_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2_ic_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2_ic_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2_ic1_Slot_ae_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic1_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2_ic1_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic1_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2_ic1_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic1_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2_ic1_Slot_ae_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic1_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2_ic1_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic1_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2_ic1_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic1_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2_ic1_Slot_ae_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic1_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2_ic1_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic1_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2_ic1_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic1_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2_ic2_Slot_ae_slot0_encode, Opcode_ae_la8x8x2_ic2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic2_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2_ic2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2_ic2_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2_ic2_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2_ic2_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2_ic2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2_ic2_Slot_ae_slot0_encode, Opcode_ae_la16x4x2_ic2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic2_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2_ic2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2_ic2_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2_ic2_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2_ic2_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2_ic2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2_ic2_Slot_ae_slot0_encode, Opcode_ae_la32x2x2_ic2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic2_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2_ic2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2_ic2_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2_ic2_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2_ic2_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2_ic2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa8x8x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa16x4x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa32x2x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8x2_ic_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8x2_ic_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa8x8x2_ic_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4x2_ic_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4x2_ic_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa16x4x2_ic_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2x2_ic_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2x2_ic_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa32x2x2_ic_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8x2_ic1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa8x8x2_ic1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4x2_ic1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa16x4x2_ic1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2x2_ic1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa32x2x2_ic1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8x2_ic2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8x2_ic2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa8x8x2_ic2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4x2_ic2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4x2_ic2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa16x4x2_ic2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2x2_ic2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2x2_ic2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa32x2x2_ic2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs8_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_abs8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs8s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_abs8s_Slot_ae_slot3_encode, Opcode_ae_abs8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_abs8s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg8s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_neg8s_Slot_ae_slot3_encode, Opcode_ae_neg8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_neg8s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add8_encode_fns[] = { + 0, 0, 0, Opcode_ae_add8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_add8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub8_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sub8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_max8_encode_fns[] = { + 0, 0, 0, Opcode_ae_max8_Slot_ae_slot0_encode, 0, Opcode_ae_max8_Slot_ae_slot2_encode, 0, Opcode_ae_max8_Slot_ae2_slot0_encode, 0, Opcode_ae_max8_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_max8_Slot_ae4_slot2_encode, Opcode_ae_max8_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_min8_encode_fns[] = { + 0, 0, 0, Opcode_ae_min8_Slot_ae_slot0_encode, 0, Opcode_ae_min8_Slot_ae_slot2_encode, 0, Opcode_ae_min8_Slot_ae2_slot0_encode, 0, Opcode_ae_min8_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_min8_Slot_ae4_slot2_encode, Opcode_ae_min8_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add8s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add8s_Slot_ae_slot3_encode, Opcode_ae_add8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_add8s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub8s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sub8s_Slot_ae_slot3_encode, Opcode_ae_sub8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sub8s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le8_encode_fns[] = { + 0, 0, 0, Opcode_ae_le8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_le8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt8_encode_fns[] = { + 0, 0, 0, Opcode_ae_lt8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lt8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq8_encode_fns[] = { + 0, 0, 0, Opcode_ae_eq8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_eq8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satu16x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_satu16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_satu16x4_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat32x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sat32x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satu32x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_satu32x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat8x8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sat8x8x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satu8x8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_satu8x8x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat8x4x32_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sat8x4x32_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sat8x4x32_l_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satu8x4x32_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_satu8x4x32_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_satu8x4x32_l_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round8x8f16ssym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round8x8f16ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round8x8f16sasym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round8x8f16sasym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round8x4f32ssym_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round8x4f32ssym_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round8x4f32sasym_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round8x4f32sasym_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda8_encode_fns[] = { + 0, 0, 0, Opcode_ae_movda8_Slot_ae_slot0_encode, Opcode_ae_movda8_Slot_ae_slot1_encode, 0, 0, Opcode_ae_movda8_Slot_ae2_slot0_encode, Opcode_ae_movda8_Slot_ae2_slot1_encode, 0, Opcode_ae_movda8_Slot_ae3_slot0_encode, Opcode_ae_movda8_Slot_ae3_slot1_encode, Opcode_ae_movda8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad8_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad8_Slot_ae2_slot0_encode, Opcode_ae_movad8_Slot_ae2_slot1_encode, 0, Opcode_ae_movad8_Slot_ae3_slot0_encode, 0, Opcode_ae_movad8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movdx2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movdx2_Slot_ae_slot0_encode, 0, Opcode_ae_movdx2_Slot_ae_slot2_encode, Opcode_ae_movdx2_Slot_ae_slot3_encode, Opcode_ae_movdx2_Slot_ae2_slot0_encode, Opcode_ae_movdx2_Slot_ae2_slot1_encode, 0, Opcode_ae_movdx2_Slot_ae3_slot0_encode, 0, Opcode_ae_movdx2_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_movdx2_Slot_ae6_slot0_encode, Opcode_ae_movdx2_Slot_ae6_slot1_encode, Opcode_ae_movdx2_Slot_ae6_slot2_encode, Opcode_ae_movdx2_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movdx2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsub32j_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsub32j_Slot_ae_slot0_encode, 0, Opcode_ae_addandsub32j_Slot_ae_slot2_encode, Opcode_ae_addandsub32j_Slot_ae_slot3_encode, Opcode_ae_addandsub32j_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32j_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsub32j_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addw8_encode_fns[] = { + 0, 0, 0, Opcode_ae_addw8_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addw8_Slot_ae_slot3_encode, Opcode_ae_addw8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addw8_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addw16_encode_fns[] = { + 0, 0, 0, Opcode_ae_addw16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addw16_Slot_ae_slot3_encode, Opcode_ae_addw16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addw16_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addw32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addw32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addw32_Slot_ae_slot3_encode, Opcode_ae_addw32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addw32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subw8_encode_fns[] = { + 0, 0, 0, Opcode_ae_subw8_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subw8_Slot_ae_slot3_encode, Opcode_ae_subw8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subw8_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subw16_encode_fns[] = { + 0, 0, 0, Opcode_ae_subw16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subw16_Slot_ae_slot3_encode, Opcode_ae_subw16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subw16_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subw32_encode_fns[] = { + 0, 0, 0, Opcode_ae_subw32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subw32_Slot_ae_slot3_encode, Opcode_ae_subw32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subw32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_accw8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_accw8_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_accw8_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_accw16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_accw16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_accw16_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_accw32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_accw32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_accw32_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addw8u_encode_fns[] = { + 0, 0, 0, Opcode_ae_addw8u_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addw8u_Slot_ae_slot3_encode, Opcode_ae_addw8u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addw8u_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subw8u_encode_fns[] = { + 0, 0, 0, Opcode_ae_subw8u_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subw8u_Slot_ae_slot3_encode, Opcode_ae_subw8u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subw8u_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_accw8u_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_accw8u_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_accw8u_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulfp32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulafp32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulfp32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulafp32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulasf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsaf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulssf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulasf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsaf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulssf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32s_hh_Slot_ae_slot2_encode, Opcode_ae_mul32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32s_hh_Slot_ae_slot2_encode, Opcode_ae_mula32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32s_hh_Slot_ae_slot2_encode, Opcode_ae_muls32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32s_ll_Slot_ae_slot2_encode, Opcode_ae_mul32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32s_ll_Slot_ae_slot2_encode, Opcode_ae_mula32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32s_ll_Slot_ae_slot2_encode, Opcode_ae_muls32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32s_hl_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32s_hl_Slot_ae_slot2_encode, Opcode_ae_mul32s_hl_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32s_hl_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32s_hl_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32s_hl_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32s_hl_Slot_ae_slot2_encode, Opcode_ae_mula32s_hl_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32s_hl_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32s_hl_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32s_hl_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32s_hl_Slot_ae_slot2_encode, Opcode_ae_muls32s_hl_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32s_hl_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32s_hl_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32s_lh_Slot_ae_slot2_encode, Opcode_ae_mul32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32s_lh_Slot_ae_slot2_encode, Opcode_ae_mula32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32s_lh_Slot_ae_slot2_encode, Opcode_ae_muls32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaad32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzasd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsad32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzsad32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsad32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsad32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaad32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulasd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsad32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulsad32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsad32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsad32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaad32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzasd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsad32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzsad32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsad32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsad32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzssd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaad32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulasd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsad32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulsad32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsad32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsad32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulssd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x2ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x2ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x2ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x2ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x2ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x2ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x2ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x2ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x2ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x2ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x2ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x2ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsaf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsaf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x2r_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x2r_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x2r_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x2r_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x2r_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x2r_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x2r_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x2r_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x2r_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x2r_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x2r_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x2r_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfc32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafc32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfcj32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafcj32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj32ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfcj32ras_Slot_ae_slot2_encode, Opcode_ae_mulfcj32ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfcj32ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfcj32ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj32ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafcj32ras_Slot_ae_slot2_encode, Opcode_ae_mulafcj32ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafcj32ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafcj32ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2p32x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulf2p32x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf2p32x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulaf2p32x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf2p32x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulsf2p32x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2p32x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulf2p32x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf2p32x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulaf2p32x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf2p32x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulsf2p32x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x2s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulp32x2s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2p32x4s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4s_Slot_ae7_slot2_encode, Opcode_ae_mul2p32x4s_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2p32x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4_Slot_ae7_slot2_encode, Opcode_ae_mul2p32x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2p32x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula2p32x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2p32x4_Slot_ae7_slot2_encode, Opcode_ae_mula2p32x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls2p32x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muls2p32x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muls2p32x4_Slot_ae7_slot2_encode, Opcode_ae_muls2p32x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2p32x4t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4t_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4t_Slot_ae7_slot2_encode, Opcode_ae_mul2p32x4t_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2p32x4t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula2p32x4t_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2p32x4t_Slot_ae7_slot2_encode, Opcode_ae_mula2p32x4t_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls2p32x4t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muls2p32x4t_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muls2p32x4t_Slot_ae7_slot2_encode, Opcode_ae_muls2p32x4t_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaa32x2_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaa32x2_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzss32x2_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzss32x2_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaa32x2_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaa32x2_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32x2_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulss32x2_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulcj32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulcj32_Slot_ae_slot2_encode, Opcode_ae_mulcj32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulcj32_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulcj32_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulacj32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulacj32_Slot_ae_slot2_encode, Opcode_ae_mulacj32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulacj32_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulacj32_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muladdf32rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muladdf32rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muladdf32rs_Slot_ae7_slot2_encode, Opcode_ae_muladdf32rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muladdf32ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muladdf32ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muladdf32ras_Slot_ae7_slot2_encode, Opcode_ae_muladdf32ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsubf32rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsubf32rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsubf32rs_Slot_ae7_slot2_encode, Opcode_ae_mulsubf32rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsubf32ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsubf32ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsubf32ras_Slot_ae7_slot2_encode, Opcode_ae_mulsubf32ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32ra_Slot_ae_slot2_encode, Opcode_ae_mulfc32ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc32ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfc32ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32ra_Slot_ae_slot2_encode, Opcode_ae_mulafc32ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc32ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafc32ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulcj32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulcj32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulacj32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulacj32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulc32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulac32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2d32x2ws_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2d32x2ws_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2d32x2ws_Slot_ae7_slot2_encode, Opcode_ae_mulf2d32x2ws_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaa2q16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q16_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaa2q16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaa2q16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q16_Slot_ae7_slot2_encode, Opcode_ae_mulaaaa2q16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp16s_h_Slot_ae_slot2_encode, Opcode_ae_mulp16s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp16s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp16s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap16s_h_Slot_ae_slot2_encode, Opcode_ae_mulap16s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap16s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap16s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp16s_h_Slot_ae_slot2_encode, Opcode_ae_mulsp16s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp16s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp16s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap16s_l_Slot_ae_slot2_encode, Opcode_ae_mulap16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulsp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulc16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulac16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulc16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulac16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2c16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2c16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2c16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula2c16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfc16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafc16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfcj16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafcj16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj16ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfcj16ras_Slot_ae_slot2_encode, Opcode_ae_mulfcj16ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfcj16ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfcj16ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj16ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafcj16ras_Slot_ae_slot2_encode, Opcode_ae_mulafcj16ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafcj16ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafcj16ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc16s_Slot_ae_slot2_encode, Opcode_ae_mulc16s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc16s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulc16s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac16s_Slot_ae_slot2_encode, Opcode_ae_mulac16s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac16s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulac16s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp16x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp16x4rs_Slot_ae_slot2_encode, Opcode_ae_mulfp16x4rs_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp16x4rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp16x4rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd16x16x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd16x16x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd16x16x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulfd16x16x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp16x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp16x16x4s_Slot_ae_slot2_encode, Opcode_ae_mulp16x16x4s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp16x16x4s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp16x16x4s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap16x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap16x16x4s_Slot_ae_slot2_encode, Opcode_ae_mulap16x16x4s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap16x16x4s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap16x16x4s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp16x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp16x16x4s_Slot_ae_slot2_encode, Opcode_ae_mulsp16x16x4s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp16x16x4s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp16x16x4s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaa2d16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaa2d16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzss2d16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzss2d16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaa2d16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaa2d16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss2d16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulss2d16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulss2d16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulss2d16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulss2d16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss2d16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulss2d16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulss2d16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulss2d16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulss2d16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaafd16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaafd16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssfd16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulssfd16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd16x16x4ws_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd16x16x4ws_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd16x16x4ws_Slot_ae7_slot2_encode, Opcode_ae_mulfd16x16x4ws_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaa2q16x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q16x8_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q16x8_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaa2q16x8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaa2q16x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q16x8_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q16x8_Slot_ae7_slot2_encode, Opcode_ae_mulaaaa2q16x8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaa2q8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q8_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q8_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaa2q8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaa2q8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q8_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q8_Slot_ae7_slot2_encode, Opcode_ae_mulaaaa2q8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulc32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulac32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulc32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulac32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulpc32x16x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulpc32x16x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulpc32x16x2_Slot_ae7_slot2_encode, Opcode_ae_mulpc32x16x2_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulapc32x16x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulapc32x16x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulapc32x16x2_Slot_ae7_slot2_encode, Opcode_ae_mulapc32x16x2_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32x16w_h_Slot_ae_slot2_encode, Opcode_ae_mulfc32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32x16w_h_Slot_ae_slot2_encode, Opcode_ae_mulafc32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32x16w_l_Slot_ae_slot2_encode, Opcode_ae_mulfc32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32x16w_l_Slot_ae_slot2_encode, Opcode_ae_mulafc32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfcj32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafcj32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfcj32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafcj32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2p32x16x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulf2p32x16x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf2p32x16x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulaf2p32x16x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf2p32x16x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulsf2p32x16x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2p32x16x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulf2p32x16x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf2p32x16x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulaf2p32x16x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf2p32x16x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulsf2p32x16x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2p32x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4s_Slot_ae7_slot2_encode, Opcode_ae_mulf2p32x16x4s_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf2p32x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4s_Slot_ae7_slot2_encode, Opcode_ae_mulaf2p32x16x4s_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf2p32x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4s_Slot_ae7_slot2_encode, Opcode_ae_mulsf2p32x16x4s_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfpc32x16x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpc32x16x2ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpc32x16x2ras_Slot_ae7_slot2_encode, Opcode_ae_mulfpc32x16x2ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpc32x16x2ras_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafpc32x16x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafpc32x16x2ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafpc32x16x2ras_Slot_ae7_slot2_encode, Opcode_ae_mulafpc32x16x2ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfpcj32x16x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpcj32x16x2ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpcj32x16x2ras_Slot_ae7_slot2_encode, Opcode_ae_mulfpcj32x16x2ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpcj32x16x2ras_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafpcj32x16x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafpcj32x16x2ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafpcj32x16x2ras_Slot_ae7_slot2_encode, Opcode_ae_mulafpcj32x16x2ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaa2q32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q32x16_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaa2q32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaa2q32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q32x16_Slot_ae7_slot2_encode, Opcode_ae_mulaaaa2q32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2q32x16_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2q32x16_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2q32x16_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mul2q32x16_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2q32x16_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula2q32x16_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2q32x16_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mula2q32x16_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2q32x16_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2q32x16_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2q32x16_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mul2q32x16_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2q32x16_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula2q32x16_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2q32x16_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mula2q32x16_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai8_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srai8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai8r_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai8r_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srai8r_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli8_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srli8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai8_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slai8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai8s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slai8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa8_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srla8_encode_fns[] = { + 0, 0, 0, Opcode_ae_srla8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srla8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa8s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa8rs_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa8rs_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa8rs_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa8s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli16_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srli16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai16_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slai16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa16_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srla16_encode_fns[] = { + 0, 0, 0, Opcode_ae_srla16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srla16_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_srla16_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai16sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai16sym_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srai16sym_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa16syms_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa16syms_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa16syms_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai32sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai32sym_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srai32sym_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32syms_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa32syms_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa32syms_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srav16rs_encode_fns[] = { + 0, 0, 0, Opcode_ae_srav16rs_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srav16rs_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srav32rs_encode_fns[] = { + 0, 0, 0, Opcode_ae_srav32rs_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srav32rs_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8s_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8s_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8s_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8s_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8s_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8s_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8u_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8u_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8u_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8u_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8u_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8u_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8us_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8us_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8us_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8us_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8us_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8us_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8u_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8u_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8u_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8u_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8u_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8u_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8us_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8us_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8us_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8us_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8us_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8us_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f16_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f16s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f16_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f16s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f16u_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f16u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f16u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f16us_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f16us_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f16us_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f16u_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f16u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f16u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f16us_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f16us_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f16us_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti16x4x2f8_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti16x4x2f8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti16x4x2f8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvti16x4x2f8_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti16x4x2f8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti16x4x2f8s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti16x4x2f8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvti16x4x2f8s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta16x4x2f8_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta16x4x2f8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta16x4x2f8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvta16x4x2f8_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta16x4x2f8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta16x4x2f8s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta16x4x2f8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvta16x4x2f8s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti16x4x2f8u_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti16x4x2f8u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti16x4x2f8u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvti16x4x2f8u_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti16x4x2f8us_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti16x4x2f8us_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti16x4x2f8us_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta16x4x2f8u_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta16x4x2f8u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta16x4x2f8u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvta16x4x2f8u_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta16x4x2f8us_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta16x4x2f8us_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta16x4x2f8us_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel8x8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sel8x8_Slot_ae_slot2_encode, Opcode_ae_sel8x8_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sel8x8_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_sel8x8_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sel8x8_Slot_ae7_slot2_encode, Opcode_ae_sel8x8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_shfl8x8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_shfl8x8_Slot_ae_slot2_encode, Opcode_ae_shfl8x8_Slot_ae_slot3_encode, 0, 0, Opcode_ae_shfl8x8_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_shfl8x8_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_shfl8x8_Slot_ae7_slot2_encode, Opcode_ae_shfl8x8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sel16x4_Slot_ae_slot2_encode, Opcode_ae_sel16x4_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sel16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_sel16x4_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sel16x4_Slot_ae7_slot2_encode, Opcode_ae_sel16x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, Opcode_ae_sel16x4_Slot_ae9_slot2_encode, Opcode_ae_sel16x4_Slot_ae9_slot3_encode, 0, 0, Opcode_ae_sel16x4_Slot_ae10_slot2_encode, Opcode_ae_sel16x4_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_shfl16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_shfl16x4_Slot_ae_slot2_encode, Opcode_ae_shfl16x4_Slot_ae_slot3_encode, 0, 0, Opcode_ae_shfl16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_shfl16x4_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_shfl16x4_Slot_ae7_slot2_encode, Opcode_ae_shfl16x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dsel8x8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_dsel8x8_Slot_ae_slot2_encode, Opcode_ae_dsel8x8_Slot_ae_slot3_encode, 0, 0, Opcode_ae_dsel8x8_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_dsel8x8_Slot_ae7_slot2_encode, Opcode_ae_dsel8x8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dsel16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_dsel16x4_Slot_ae_slot2_encode, Opcode_ae_dsel16x4_Slot_ae_slot3_encode, 0, 0, Opcode_ae_dsel16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_dsel16x4_Slot_ae7_slot2_encode, Opcode_ae_dsel16x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, Opcode_ae_dsel16x4_Slot_ae9_slot2_encode, Opcode_ae_dsel16x4_Slot_ae9_slot3_encode, 0, 0, Opcode_ae_dsel16x4_Slot_ae10_slot2_encode, Opcode_ae_dsel16x4_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel8x8i_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sel8x8i_Slot_ae_slot2_encode, Opcode_ae_sel8x8i_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sel8x8i_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_sel8x8i_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sel8x8i_Slot_ae7_slot2_encode, Opcode_ae_sel8x8i_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rmax8x8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_rmax8x8_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_rmax8x8_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_rmax8x8_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rmin8x8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_rmin8x8_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_rmin8x8_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_rmin8x8_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rmax16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_rmax16x4_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_rmax16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_rmax16x4_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rmin16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_rmin16x4_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_rmin16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_rmin16x4_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sort16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sort16x4_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_sort16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sort16x4_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radd8x8_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radd8x8_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radd8x8_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radd8x8_h_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radda8x8_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radda8x8_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radda8x8_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radda8x8_h_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radd8x8_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radd8x8_l_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radd8x8_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radd8x8_l_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radda8x8_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radda8x8_l_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radda8x8_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radda8x8_l_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radd16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radd16x4_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radd16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radd16x4_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radda16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radda16x4_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radda16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radda16x4_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmax8x8_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_bmax8x8_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmax8x8_h_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmax8x8_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_bmax8x8_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmax8x8_l_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmax8x8_l_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmin8x8_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_bmin8x8_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmin8x8_h_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmin8x8_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_bmin8x8_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmin8x8_l_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmin8x8_l_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmax16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_bmax16x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_bmax16x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmax16x4_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmax16x4_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmin16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_bmin16x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_bmin16x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmin16x4_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmin16x4_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmax32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_bmax32x2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_bmax32x2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmax32x2_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmax32x2_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmin32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_bmin32x2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_bmin32x2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmin32x2_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmin32x2_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addinv16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addinv16s_Slot_ae_slot0_encode, 0, Opcode_ae_addinv16s_Slot_ae_slot2_encode, Opcode_ae_addinv16s_Slot_ae_slot3_encode, Opcode_ae_addinv16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addinv16s_Slot_ae6_slot0_encode, 0, Opcode_ae_addinv16s_Slot_ae6_slot2_encode, Opcode_ae_addinv16s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addinv32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addinv32s_Slot_ae_slot0_encode, 0, Opcode_ae_addinv32s_Slot_ae_slot2_encode, Opcode_ae_addinv32s_Slot_ae_slot3_encode, Opcode_ae_addinv32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addinv32s_Slot_ae6_slot0_encode, 0, Opcode_ae_addinv32s_Slot_ae6_slot2_encode, Opcode_ae_addinv32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt16x8_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt16x8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt16x8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt8x16_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt8x16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt8x16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt8x16_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt8x16_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt8x16_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movbd1x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movbd1x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movbd1x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movbd1x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movbd1x2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movbd1x2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movneg32s_t_encode_fns[] = { + 0, 0, 0, Opcode_ae_movneg32s_t_Slot_ae_slot0_encode, 0, Opcode_ae_movneg32s_t_Slot_ae_slot2_encode, Opcode_ae_movneg32s_t_Slot_ae_slot3_encode, Opcode_ae_movneg32s_t_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movdext_encode_fns[] = { + 0, 0, 0, Opcode_ae_movdext_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movdext_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movadext_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_movadext_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movadext_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movadext_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_movadext_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movadext_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsa16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsa16x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsa16x4_Slot_ae2_slot0_encode, Opcode_ae_nsa16x4_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsaz32x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsaz32x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsaz32x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsa32x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsa32x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsa32x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunci16x4f32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunci16x4f32s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunci16x4f32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci16x4f32s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci16x4f32s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunci16x4f64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunci16x4f64s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunci16x4f64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci16x4f64s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci16x4f64s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16x4f32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca16x4f32s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunca16x4f32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca16x4f32s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca16x4f32s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16x4f64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca16x4f64s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunca16x4f64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca16x4f64s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca16x4f64s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addc32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addc32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_addc32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addc32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subc32_encode_fns[] = { + 0, 0, 0, Opcode_ae_subc32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_subc32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subc32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addc32u_encode_fns[] = { + 0, 0, 0, Opcode_ae_addc32u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_addc32u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addc32u_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subc32u_encode_fns[] = { + 0, 0, 0, Opcode_ae_subc32u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_subc32u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subc32u_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_expadd16_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_expadd16_h_Slot_ae_slot2_encode, Opcode_ae_expadd16_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_expsub16_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_expsub16_h_Slot_ae_slot2_encode, Opcode_ae_expsub16_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_expadd16_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_expadd16_l_Slot_ae_slot2_encode, Opcode_ae_expadd16_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_expsub16_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_expsub16_l_Slot_ae_slot2_encode, Opcode_ae_expsub16_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcexp32_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_addcexp32_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcexp32_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_addcexp32_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_calcrng16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_calcrng16_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_calcrng32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_calcrng32_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rng32x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_rng32x4_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lav8x8x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_lav8x8x2_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lav8x8x2_xp_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lav8x8x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_lav8x8x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_ae_lav8x8x2_xp_Slot_ae10_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lav16x4x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_lav16x4x2_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lav16x4x2_xp_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lav16x4x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_lav16x4x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_ae_lav16x4x2_xp_Slot_ae10_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sav8x8x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_sav8x8x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sav8x8x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sav8x8x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sav16x4x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_sav16x4x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sav16x4x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sav16x4x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movzbvcdr_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_movzbvcdr_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movzbvcdr_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movdrzbvc_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_movdrzbvc_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movdrzbvc_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lavunsqz8x8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_lavunsqz8x8_xp_Slot_ae_slot0_encode, Opcode_ae_lavunsqz8x8_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_lavunsqz8x8_xp_Slot_ae2_slot0_encode, Opcode_ae_lavunsqz8x8_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lavunsqz8x8_xp_Slot_ae8_slot0_encode, Opcode_ae_lavunsqz8x8_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_lavunsqz8x8_xp_Slot_ae9_slot0_encode, Opcode_ae_lavunsqz8x8_xp_Slot_ae9_slot1_encode, 0, 0, 0, Opcode_ae_lavunsqz8x8_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lavunsqz16x4_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_lavunsqz16x4_xp_Slot_ae_slot0_encode, Opcode_ae_lavunsqz16x4_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_lavunsqz16x4_xp_Slot_ae2_slot0_encode, Opcode_ae_lavunsqz16x4_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lavunsqz16x4_xp_Slot_ae8_slot0_encode, Opcode_ae_lavunsqz16x4_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_lavunsqz16x4_xp_Slot_ae9_slot0_encode, Opcode_ae_lavunsqz16x4_xp_Slot_ae9_slot1_encode, 0, 0, 0, Opcode_ae_lavunsqz16x4_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2x4q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2x4q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2x4q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2x4q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulqq8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulqq8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaqq8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaqq8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2x4q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2x4q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2x4q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2x4q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2x4q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2x4q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2x4q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2x4q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulqq4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulqq4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaqq4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaqq4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulqq4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulqq4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaqq4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaqq4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o4x16cnv_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o4x16cnv_hh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o4x16cnv_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o4x16cnv_hl_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o4x16cnv_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o4x16cnv_lh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o4x16cnv_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o4x16cnv_ll_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o4x16cnv_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o4x16cnv_hh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o4x16cnv_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o4x16cnv_hl_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o4x16cnv_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o4x16cnv_lh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o4x16cnv_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o4x16cnv_ll_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus2x4q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus2x4q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus2x4q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus2x4q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulusqq8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulusqq8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulausqq8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulausqq8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus2x4q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus2x4q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus2x4q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus2x4q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus2x4q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus2x4q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus2x4q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus2x4q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulusqq4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulusqq4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulausqq4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulausqq4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulusqq4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulusqq4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulausqq4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulausqq4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o4x16cnv_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o4x16cnv_hh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o4x16cnv_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o4x16cnv_hl_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o4x16cnv_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o4x16cnv_lh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o4x16cnv_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o4x16cnv_ll_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o4x16cnv_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o4x16cnv_hh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o4x16cnv_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o4x16cnv_hl_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o4x16cnv_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o4x16cnv_lh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o4x16cnv_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o4x16cnv_ll_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtsf16_l_encode_fns[] = { + 0, 0, 0, Opcode_cvtsf16_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_cvtsf16_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtsf16_l_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtsf16_h_encode_fns[] = { + 0, 0, 0, Opcode_cvtsf16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_cvtsf16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtsf16_h_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtf16s_l_encode_fns[] = { + 0, 0, 0, Opcode_cvtf16s_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_cvtf16s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtf16s_l_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtf16s_h_encode_fns[] = { + 0, 0, 0, Opcode_cvtf16s_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_cvtf16s_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtf16s_h_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movfcrfsrv_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_movfcrfsrv_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movvfcrfsr_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_movvfcrfsr_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = { + 0, 0, 0, Opcode_movt_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movt_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_movt_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = { + 0, 0, 0, Opcode_movf_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movf_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_movf_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = { + 0, 0, 0, Opcode_moveqz_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_moveqz_s_Slot_ae2_slot0_encode, Opcode_moveqz_s_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_moveqz_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = { + 0, 0, 0, Opcode_movnez_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movnez_s_Slot_ae2_slot0_encode, Opcode_movnez_s_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_movnez_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = { + 0, 0, 0, Opcode_movgez_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movgez_s_Slot_ae2_slot0_encode, Opcode_movgez_s_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_movgez_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = { + 0, 0, 0, Opcode_movltz_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movltz_s_Slot_ae2_slot0_encode, Opcode_movltz_s_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_movltz_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = { + 0, 0, 0, Opcode_rfr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = { + 0, 0, 0, Opcode_wfr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mul_s_Slot_ae_slot2_encode, Opcode_mul_s_Slot_ae_slot3_encode, 0, 0, Opcode_mul_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_mul_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mul_s_Slot_ae9_slot2_encode, Opcode_mul_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mul_s_Slot_ae10_slot2_encode, Opcode_mul_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_madd_s_Slot_ae_slot2_encode, Opcode_madd_s_Slot_ae_slot3_encode, 0, 0, Opcode_madd_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_madd_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_madd_s_Slot_ae9_slot2_encode, Opcode_madd_s_Slot_ae9_slot3_encode, 0, 0, Opcode_madd_s_Slot_ae10_slot2_encode, Opcode_madd_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_msub_s_Slot_ae_slot2_encode, Opcode_msub_s_Slot_ae_slot3_encode, 0, 0, Opcode_msub_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_msub_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msub_s_Slot_ae9_slot2_encode, Opcode_msub_s_Slot_ae9_slot3_encode, 0, 0, Opcode_msub_s_Slot_ae10_slot2_encode, Opcode_msub_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msubn_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_msubn_s_Slot_ae_slot2_encode, Opcode_msubn_s_Slot_ae_slot3_encode, 0, 0, Opcode_msubn_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_msubn_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msubn_s_Slot_ae9_slot2_encode, Opcode_msubn_s_Slot_ae9_slot3_encode, 0, 0, Opcode_msubn_s_Slot_ae10_slot2_encode, Opcode_msubn_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddn_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maddn_s_Slot_ae_slot2_encode, Opcode_maddn_s_Slot_ae_slot3_encode, 0, 0, Opcode_maddn_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_maddn_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddn_s_Slot_ae9_slot2_encode, Opcode_maddn_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maddn_s_Slot_ae10_slot2_encode, Opcode_maddn_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_add_s_Slot_ae_slot2_encode, Opcode_add_s_Slot_ae_slot3_encode, 0, 0, Opcode_add_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_add_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_s_Slot_ae9_slot2_encode, Opcode_add_s_Slot_ae9_slot3_encode, 0, 0, Opcode_add_s_Slot_ae10_slot2_encode, Opcode_add_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_sub_s_Slot_ae_slot2_encode, Opcode_sub_s_Slot_ae_slot3_encode, 0, 0, Opcode_sub_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_sub_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_s_Slot_ae9_slot2_encode, Opcode_sub_s_Slot_ae9_slot3_encode, 0, 0, Opcode_sub_s_Slot_ae10_slot2_encode, Opcode_sub_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = { + 0, 0, 0, Opcode_ole_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ole_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ole_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ole_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = { + 0, 0, 0, Opcode_olt_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_olt_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_olt_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_olt_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = { + 0, 0, 0, Opcode_oeq_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_oeq_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_oeq_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_oeq_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = { + 0, 0, 0, Opcode_un_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_un_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_un_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_un_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = { + 0, 0, 0, Opcode_ule_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ule_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ule_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ule_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = { + 0, 0, 0, Opcode_ult_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ult_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ult_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ult_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = { + 0, 0, 0, Opcode_ueq_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ueq_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ueq_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ueq_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nexp01_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_nexp01_s_Slot_ae_slot2_encode, Opcode_nexp01_s_Slot_ae_slot3_encode, 0, 0, Opcode_nexp01_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_nexp01_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_nexp01_s_Slot_ae9_slot2_encode, Opcode_nexp01_s_Slot_ae9_slot3_encode, 0, 0, Opcode_nexp01_s_Slot_ae10_slot2_encode, Opcode_nexp01_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mksadj_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mksadj_s_Slot_ae_slot2_encode, Opcode_mksadj_s_Slot_ae_slot3_encode, 0, 0, Opcode_mksadj_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_mksadj_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mksadj_s_Slot_ae9_slot2_encode, Opcode_mksadj_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mksadj_s_Slot_ae10_slot2_encode, Opcode_mksadj_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mkdadj_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mkdadj_s_Slot_ae_slot2_encode, Opcode_mkdadj_s_Slot_ae_slot3_encode, 0, 0, Opcode_mkdadj_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_mkdadj_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mkdadj_s_Slot_ae9_slot2_encode, Opcode_mkdadj_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mkdadj_s_Slot_ae10_slot2_encode, Opcode_mkdadj_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_div0_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_div0_s_Slot_ae_slot2_encode, Opcode_div0_s_Slot_ae_slot3_encode, 0, 0, Opcode_div0_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_div0_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_div0_s_Slot_ae9_slot2_encode, Opcode_div0_s_Slot_ae9_slot3_encode, 0, 0, Opcode_div0_s_Slot_ae10_slot2_encode, Opcode_div0_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sqrt0_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_sqrt0_s_Slot_ae_slot2_encode, Opcode_sqrt0_s_Slot_ae_slot3_encode, 0, 0, Opcode_sqrt0_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_sqrt0_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sqrt0_s_Slot_ae9_slot2_encode, Opcode_sqrt0_s_Slot_ae9_slot3_encode, 0, 0, Opcode_sqrt0_s_Slot_ae10_slot2_encode, Opcode_sqrt0_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_recip0_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_recip0_s_Slot_ae_slot2_encode, Opcode_recip0_s_Slot_ae_slot3_encode, 0, 0, Opcode_recip0_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_recip0_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_recip0_s_Slot_ae9_slot2_encode, Opcode_recip0_s_Slot_ae9_slot3_encode, 0, 0, Opcode_recip0_s_Slot_ae10_slot2_encode, Opcode_recip0_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsqrt0_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_rsqrt0_s_Slot_ae_slot2_encode, Opcode_rsqrt0_s_Slot_ae_slot3_encode, 0, 0, Opcode_rsqrt0_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_rsqrt0_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rsqrt0_s_Slot_ae9_slot2_encode, Opcode_rsqrt0_s_Slot_ae9_slot3_encode, 0, 0, Opcode_rsqrt0_s_Slot_ae10_slot2_encode, Opcode_rsqrt0_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_divn_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_divn_s_Slot_ae_slot2_encode, Opcode_divn_s_Slot_ae_slot3_encode, 0, 0, Opcode_divn_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_divn_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_divn_s_Slot_ae9_slot2_encode, Opcode_divn_s_Slot_ae9_slot3_encode, 0, 0, Opcode_divn_s_Slot_ae10_slot2_encode, Opcode_divn_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexp_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addexp_s_Slot_ae_slot2_encode, Opcode_addexp_s_Slot_ae_slot3_encode, 0, 0, Opcode_addexp_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addexp_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addexp_s_Slot_ae9_slot2_encode, Opcode_addexp_s_Slot_ae9_slot3_encode, 0, 0, Opcode_addexp_s_Slot_ae10_slot2_encode, Opcode_addexp_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexpm_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addexpm_s_Slot_ae_slot2_encode, Opcode_addexpm_s_Slot_ae_slot3_encode, 0, 0, Opcode_addexpm_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addexpm_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addexpm_s_Slot_ae9_slot2_encode, Opcode_addexpm_s_Slot_ae9_slot3_encode, 0, 0, Opcode_addexpm_s_Slot_ae10_slot2_encode, Opcode_addexpm_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_min_s_Slot_ae_slot2_encode, Opcode_min_s_Slot_ae_slot3_encode, 0, 0, Opcode_min_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_min_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_min_s_Slot_ae9_slot2_encode, Opcode_min_s_Slot_ae9_slot3_encode, 0, 0, Opcode_min_s_Slot_ae10_slot2_encode, Opcode_min_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_max_s_Slot_ae_slot2_encode, Opcode_max_s_Slot_ae_slot3_encode, 0, 0, Opcode_max_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_max_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_max_s_Slot_ae9_slot2_encode, Opcode_max_s_Slot_ae9_slot3_encode, 0, 0, Opcode_max_s_Slot_ae10_slot2_encode, Opcode_max_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulmux_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mulmux_s_Slot_ae_slot2_encode, Opcode_mulmux_s_Slot_ae_slot3_encode, 0, 0, Opcode_mulmux_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulmux_s_Slot_ae9_slot2_encode, Opcode_mulmux_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mulmux_s_Slot_ae10_slot2_encode, Opcode_mulmux_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddmux_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maddmux_s_Slot_ae_slot2_encode, Opcode_maddmux_s_Slot_ae_slot3_encode, 0, 0, Opcode_maddmux_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddmux_s_Slot_ae9_slot2_encode, Opcode_maddmux_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maddmux_s_Slot_ae10_slot2_encode, Opcode_maddmux_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = { + 0, 0, 0, Opcode_trunc_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_trunc_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_trunc_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = { + 0, 0, 0, Opcode_utrunc_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_utrunc_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_utrunc_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc_sx2_encode_fns[] = { + 0, 0, 0, Opcode_trunc_sx2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_trunc_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_trunc_sx2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc_sx2_encode_fns[] = { + 0, 0, 0, Opcode_utrunc_sx2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_utrunc_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_utrunc_sx2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ficeil_s_encode_fns[] = { + 0, 0, 0, Opcode_ficeil_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ficeil_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ficeil_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_fifloor_s_encode_fns[] = { + 0, 0, 0, Opcode_fifloor_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_fifloor_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_fifloor_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_firint_s_encode_fns[] = { + 0, 0, 0, Opcode_firint_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_firint_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_firint_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_firound_s_encode_fns[] = { + 0, 0, 0, Opcode_firound_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_firound_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_firound_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_fitrunc_s_encode_fns[] = { + 0, 0, 0, Opcode_fitrunc_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_fitrunc_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_fitrunc_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = { + 0, 0, 0, Opcode_float_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_float_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_float_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = { + 0, 0, 0, Opcode_ufloat_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ufloat_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ufloat_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float_sx2_encode_fns[] = { + 0, 0, 0, Opcode_float_sx2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_float_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_float_sx2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat_sx2_encode_fns[] = { + 0, 0, 0, Opcode_ufloat_sx2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ufloat_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ufloat_sx2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_abs_s_Slot_ae_slot2_encode, Opcode_abs_s_Slot_ae_slot3_encode, 0, Opcode_abs_s_Slot_ae2_slot1_encode, Opcode_abs_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_abs_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_abs_s_Slot_ae9_slot2_encode, Opcode_abs_s_Slot_ae9_slot3_encode, 0, 0, Opcode_abs_s_Slot_ae10_slot2_encode, Opcode_abs_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_neg_s_Slot_ae_slot2_encode, Opcode_neg_s_Slot_ae_slot3_encode, 0, Opcode_neg_s_Slot_ae2_slot1_encode, Opcode_neg_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_neg_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_neg_s_Slot_ae9_slot2_encode, Opcode_neg_s_Slot_ae9_slot3_encode, 0, 0, Opcode_neg_s_Slot_ae10_slot2_encode, Opcode_neg_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_conjc_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_conjc_s_Slot_ae_slot2_encode, Opcode_conjc_s_Slot_ae_slot3_encode, 0, Opcode_conjc_s_Slot_ae2_slot1_encode, Opcode_conjc_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_conjc_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_conjc_s_Slot_ae9_slot2_encode, Opcode_conjc_s_Slot_ae9_slot3_encode, 0, 0, Opcode_conjc_s_Slot_ae10_slot2_encode, Opcode_conjc_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muljc_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_muljc_s_Slot_ae_slot2_encode, Opcode_muljc_s_Slot_ae_slot3_encode, 0, Opcode_muljc_s_Slot_ae2_slot1_encode, Opcode_muljc_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_muljc_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_muljc_s_Slot_ae9_slot2_encode, Opcode_muljc_s_Slot_ae9_slot3_encode, 0, 0, Opcode_muljc_s_Slot_ae10_slot2_encode, Opcode_muljc_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_const_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_const_s_Slot_ae_slot2_encode, Opcode_const_s_Slot_ae_slot3_encode, 0, Opcode_const_s_Slot_ae2_slot1_encode, Opcode_const_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_const_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_const_s_Slot_ae9_slot2_encode, Opcode_const_s_Slot_ae9_slot3_encode, 0, 0, Opcode_const_s_Slot_ae10_slot2_encode, Opcode_const_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clsfy_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_clsfy_s_Slot_ae_slot2_encode, Opcode_clsfy_s_Slot_ae_slot3_encode, 0, 0, Opcode_clsfy_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_clsfy_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_clsfy_s_Slot_ae9_slot2_encode, Opcode_clsfy_s_Slot_ae9_slot3_encode, 0, 0, Opcode_clsfy_s_Slot_ae10_slot2_encode, Opcode_clsfy_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minnum_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_minnum_s_Slot_ae_slot2_encode, Opcode_minnum_s_Slot_ae_slot3_encode, 0, 0, Opcode_minnum_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_minnum_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_minnum_s_Slot_ae9_slot2_encode, Opcode_minnum_s_Slot_ae9_slot3_encode, 0, 0, Opcode_minnum_s_Slot_ae10_slot2_encode, Opcode_minnum_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxnum_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maxnum_s_Slot_ae_slot2_encode, Opcode_maxnum_s_Slot_ae_slot3_encode, 0, 0, Opcode_maxnum_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_maxnum_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maxnum_s_Slot_ae9_slot2_encode, Opcode_maxnum_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maxnum_s_Slot_ae10_slot2_encode, Opcode_maxnum_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addandsub_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addandsub_s_Slot_ae_slot2_encode, Opcode_addandsub_s_Slot_ae_slot3_encode, 0, 0, Opcode_addandsub_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addandsub_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addandsub_s_Slot_ae9_slot2_encode, Opcode_addandsub_s_Slot_ae9_slot3_encode, 0, 0, Opcode_addandsub_s_Slot_ae10_slot2_encode, Opcode_addandsub_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addandsubjc_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addandsubjc_s_Slot_ae_slot2_encode, Opcode_addandsubjc_s_Slot_ae_slot3_encode, 0, 0, Opcode_addandsubjc_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addandsubjc_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addandsubjc_s_Slot_ae9_slot2_encode, Opcode_addandsubjc_s_Slot_ae9_slot3_encode, 0, 0, Opcode_addandsubjc_s_Slot_ae10_slot2_encode, Opcode_addandsubjc_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_hl_lh_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_add_hl_lh_s_Slot_ae_slot2_encode, Opcode_add_hl_lh_s_Slot_ae_slot3_encode, 0, 0, Opcode_add_hl_lh_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_add_hl_lh_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_hl_lh_s_Slot_ae9_slot2_encode, Opcode_add_hl_lh_s_Slot_ae9_slot3_encode, 0, 0, Opcode_add_hl_lh_s_Slot_ae10_slot2_encode, Opcode_add_hl_lh_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madda_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_madda_s_Slot_ae_slot2_encode, Opcode_madda_s_Slot_ae_slot3_encode, 0, 0, Opcode_madda_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_madda_s_Slot_ae9_slot2_encode, Opcode_madda_s_Slot_ae9_slot3_encode, 0, 0, Opcode_madda_s_Slot_ae10_slot2_encode, Opcode_madda_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_frexp_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_frexp_s_Slot_ae_slot2_encode, Opcode_frexp_s_Slot_ae_slot3_encode, 0, 0, Opcode_frexp_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_frexp_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_frexp_s_Slot_ae9_slot2_encode, Opcode_frexp_s_Slot_ae9_slot3_encode, 0, 0, Opcode_frexp_s_Slot_ae10_slot2_encode, Opcode_frexp_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_floatexp_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_floatexp_s_Slot_ae_slot2_encode, Opcode_floatexp_s_Slot_ae_slot3_encode, 0, 0, Opcode_floatexp_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_floatexp_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_floatexp_s_Slot_ae9_slot2_encode, Opcode_floatexp_s_Slot_ae9_slot3_encode, 0, 0, Opcode_floatexp_s_Slot_ae10_slot2_encode, Opcode_floatexp_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minnumabs_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_minnumabs_s_Slot_ae_slot2_encode, Opcode_minnumabs_s_Slot_ae_slot3_encode, 0, 0, Opcode_minnumabs_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_minnumabs_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_minnumabs_s_Slot_ae9_slot2_encode, Opcode_minnumabs_s_Slot_ae9_slot3_encode, 0, 0, Opcode_minnumabs_s_Slot_ae10_slot2_encode, Opcode_minnumabs_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxnumabs_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maxnumabs_s_Slot_ae_slot2_encode, Opcode_maxnumabs_s_Slot_ae_slot3_encode, 0, 0, Opcode_maxnumabs_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_maxnumabs_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maxnumabs_s_Slot_ae9_slot2_encode, Opcode_maxnumabs_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maxnumabs_s_Slot_ae10_slot2_encode, Opcode_maxnumabs_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulq_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulq_s_Slot_ae9_slot2_encode, Opcode_mulq_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mulq_s_Slot_ae10_slot2_encode, Opcode_mulq_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddq_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddq_s_Slot_ae9_slot2_encode, Opcode_maddq_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maddq_s_Slot_ae10_slot2_encode, Opcode_maddq_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msubq_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msubq_s_Slot_ae9_slot2_encode, Opcode_msubq_s_Slot_ae9_slot3_encode, 0, 0, Opcode_msubq_s_Slot_ae10_slot2_encode, Opcode_msubq_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulmuxq_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulmuxq_s_Slot_ae9_slot2_encode, Opcode_mulmuxq_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mulmuxq_s_Slot_ae10_slot2_encode, Opcode_mulmuxq_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddmuxq_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddmuxq_s_Slot_ae9_slot2_encode, Opcode_maddmuxq_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maddmuxq_s_Slot_ae10_slot2_encode, Opcode_maddmuxq_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bmaxnum_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_bmaxnum_s_Slot_ae_slot3_encode, 0, 0, Opcode_bmaxnum_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bmaxnum_s_Slot_ae9_slot3_encode, 0, 0, 0, Opcode_bmaxnum_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bminnum_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_bminnum_s_Slot_ae_slot3_encode, 0, 0, Opcode_bminnum_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bminnum_s_Slot_ae9_slot3_encode, 0, 0, 0, Opcode_bminnum_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bmaxnumabs_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_bmaxnumabs_s_Slot_ae_slot3_encode, 0, 0, Opcode_bmaxnumabs_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bmaxnumabs_s_Slot_ae9_slot3_encode, 0, 0, 0, Opcode_bmaxnumabs_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bminnumabs_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_bminnumabs_s_Slot_ae_slot3_encode, 0, 0, Opcode_bminnumabs_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bminnumabs_s_Slot_ae9_slot3_encode, 0, 0, 0, Opcode_bminnumabs_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_abs_sx2x2_Slot_ae_slot2_encode, Opcode_abs_sx2x2_Slot_ae_slot3_encode, 0, Opcode_abs_sx2x2_Slot_ae2_slot1_encode, Opcode_abs_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_abs_sx2x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_abs_sx2x2_Slot_ae9_slot2_encode, Opcode_abs_sx2x2_Slot_ae9_slot3_encode, 0, 0, Opcode_abs_sx2x2_Slot_ae10_slot2_encode, Opcode_abs_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_neg_sx2x2_Slot_ae_slot2_encode, Opcode_neg_sx2x2_Slot_ae_slot3_encode, 0, Opcode_neg_sx2x2_Slot_ae2_slot1_encode, Opcode_neg_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_neg_sx2x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_neg_sx2x2_Slot_ae9_slot2_encode, Opcode_neg_sx2x2_Slot_ae9_slot3_encode, 0, 0, Opcode_neg_sx2x2_Slot_ae10_slot2_encode, Opcode_neg_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_conjc_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_conjc_sx2x2_Slot_ae_slot2_encode, Opcode_conjc_sx2x2_Slot_ae_slot3_encode, 0, Opcode_conjc_sx2x2_Slot_ae2_slot1_encode, Opcode_conjc_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_conjc_sx2x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_conjc_sx2x2_Slot_ae9_slot2_encode, Opcode_conjc_sx2x2_Slot_ae9_slot3_encode, 0, 0, Opcode_conjc_sx2x2_Slot_ae10_slot2_encode, Opcode_conjc_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muljc_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_muljc_sx2x2_Slot_ae_slot2_encode, Opcode_muljc_sx2x2_Slot_ae_slot3_encode, 0, Opcode_muljc_sx2x2_Slot_ae2_slot1_encode, Opcode_muljc_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_muljc_sx2x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_muljc_sx2x2_Slot_ae9_slot2_encode, Opcode_muljc_sx2x2_Slot_ae9_slot3_encode, 0, 0, Opcode_muljc_sx2x2_Slot_ae10_slot2_encode, Opcode_muljc_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_const_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_const_sx2x2_Slot_ae_slot2_encode, Opcode_const_sx2x2_Slot_ae_slot3_encode, 0, Opcode_const_sx2x2_Slot_ae2_slot1_encode, Opcode_const_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_const_sx2x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_const_sx2x2_Slot_ae9_slot2_encode, Opcode_const_sx2x2_Slot_ae9_slot3_encode, 0, 0, Opcode_const_sx2x2_Slot_ae10_slot2_encode, Opcode_const_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_sx2x2_Slot_ae9_slot2_encode, 0, 0, 0, Opcode_add_sx2x2_Slot_ae10_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_sx2x2_Slot_ae9_slot2_encode, 0, 0, 0, Opcode_sub_sx2x2_Slot_ae10_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mul_sx2x2_Slot_ae10_slot2_encode, Opcode_mul_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madd_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_madd_sx2x2_Slot_ae10_slot2_encode, Opcode_madd_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msub_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msub_sx2x2_Slot_ae10_slot2_encode, Opcode_msub_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulmux_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulmux_sx2x2_Slot_ae10_slot2_encode, Opcode_mulmux_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddmux_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddmux_sx2x2_Slot_ae10_slot2_encode, Opcode_maddmux_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_abs_h_Slot_ae_slot2_encode, Opcode_abs_h_Slot_ae_slot3_encode, 0, Opcode_abs_h_Slot_ae2_slot1_encode, Opcode_abs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_abs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_abs_h_Slot_ae9_slot2_encode, Opcode_abs_h_Slot_ae9_slot3_encode, 0, 0, Opcode_abs_h_Slot_ae10_slot2_encode, Opcode_abs_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexp_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addexp_h_Slot_ae_slot2_encode, Opcode_addexp_h_Slot_ae_slot3_encode, 0, 0, Opcode_addexp_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addexp_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addexp_h_Slot_ae9_slot2_encode, Opcode_addexp_h_Slot_ae9_slot3_encode, 0, 0, Opcode_addexp_h_Slot_ae10_slot2_encode, Opcode_addexp_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexpm_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addexpm_h_Slot_ae_slot2_encode, Opcode_addexpm_h_Slot_ae_slot3_encode, 0, 0, Opcode_addexpm_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addexpm_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addexpm_h_Slot_ae9_slot2_encode, Opcode_addexpm_h_Slot_ae9_slot3_encode, 0, 0, Opcode_addexpm_h_Slot_ae10_slot2_encode, Opcode_addexpm_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clsfy_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_clsfy_h_Slot_ae_slot2_encode, Opcode_clsfy_h_Slot_ae_slot3_encode, 0, 0, Opcode_clsfy_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_clsfy_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_clsfy_h_Slot_ae9_slot2_encode, Opcode_clsfy_h_Slot_ae9_slot3_encode, 0, 0, Opcode_clsfy_h_Slot_ae10_slot2_encode, Opcode_clsfy_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_conjc_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_conjc_h_Slot_ae_slot2_encode, Opcode_conjc_h_Slot_ae_slot3_encode, 0, Opcode_conjc_h_Slot_ae2_slot1_encode, Opcode_conjc_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_conjc_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_conjc_h_Slot_ae9_slot2_encode, Opcode_conjc_h_Slot_ae9_slot3_encode, 0, 0, Opcode_conjc_h_Slot_ae10_slot2_encode, Opcode_conjc_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_const_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_const_h_Slot_ae_slot2_encode, Opcode_const_h_Slot_ae_slot3_encode, 0, Opcode_const_h_Slot_ae2_slot1_encode, Opcode_const_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_const_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_const_h_Slot_ae9_slot2_encode, Opcode_const_h_Slot_ae9_slot3_encode, 0, 0, Opcode_const_h_Slot_ae10_slot2_encode, Opcode_const_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_min_h_Slot_ae_slot2_encode, Opcode_min_h_Slot_ae_slot3_encode, 0, 0, Opcode_min_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_min_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_min_h_Slot_ae9_slot2_encode, Opcode_min_h_Slot_ae9_slot3_encode, 0, 0, Opcode_min_h_Slot_ae10_slot2_encode, Opcode_min_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_max_h_Slot_ae_slot2_encode, Opcode_max_h_Slot_ae_slot3_encode, 0, 0, Opcode_max_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_max_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_max_h_Slot_ae9_slot2_encode, Opcode_max_h_Slot_ae9_slot3_encode, 0, 0, Opcode_max_h_Slot_ae10_slot2_encode, Opcode_max_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minnum_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_minnum_h_Slot_ae_slot2_encode, Opcode_minnum_h_Slot_ae_slot3_encode, 0, 0, Opcode_minnum_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_minnum_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_minnum_h_Slot_ae9_slot2_encode, Opcode_minnum_h_Slot_ae9_slot3_encode, 0, 0, Opcode_minnum_h_Slot_ae10_slot2_encode, Opcode_minnum_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxnum_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maxnum_h_Slot_ae_slot2_encode, Opcode_maxnum_h_Slot_ae_slot3_encode, 0, 0, Opcode_maxnum_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_maxnum_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maxnum_h_Slot_ae9_slot2_encode, Opcode_maxnum_h_Slot_ae9_slot3_encode, 0, 0, Opcode_maxnum_h_Slot_ae10_slot2_encode, Opcode_maxnum_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muljc_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_muljc_h_Slot_ae_slot2_encode, Opcode_muljc_h_Slot_ae_slot3_encode, 0, Opcode_muljc_h_Slot_ae2_slot1_encode, Opcode_muljc_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_muljc_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_muljc_h_Slot_ae9_slot2_encode, Opcode_muljc_h_Slot_ae9_slot3_encode, 0, 0, Opcode_muljc_h_Slot_ae10_slot2_encode, Opcode_muljc_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_neg_h_Slot_ae_slot2_encode, Opcode_neg_h_Slot_ae_slot3_encode, 0, Opcode_neg_h_Slot_ae2_slot1_encode, Opcode_neg_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_neg_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_neg_h_Slot_ae9_slot2_encode, Opcode_neg_h_Slot_ae9_slot3_encode, 0, 0, Opcode_neg_h_Slot_ae10_slot2_encode, Opcode_neg_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_oeq_h_encode_fns[] = { + 0, 0, 0, Opcode_oeq_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ole_h_encode_fns[] = { + 0, 0, 0, Opcode_ole_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_olt_h_encode_fns[] = { + 0, 0, 0, Opcode_olt_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ueq_h_encode_fns[] = { + 0, 0, 0, Opcode_ueq_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ule_h_encode_fns[] = { + 0, 0, 0, Opcode_ule_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ult_h_encode_fns[] = { + 0, 0, 0, Opcode_ult_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_un_h_encode_fns[] = { + 0, 0, 0, Opcode_un_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_div0_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_div0_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ficeil_h_encode_fns[] = { + 0, 0, 0, Opcode_ficeil_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ficeil_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_fifloor_h_encode_fns[] = { + 0, 0, 0, Opcode_fifloor_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_fifloor_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_firint_h_encode_fns[] = { + 0, 0, 0, Opcode_firint_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_firint_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_firound_h_encode_fns[] = { + 0, 0, 0, Opcode_firound_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_firound_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_fitrunc_h_encode_fns[] = { + 0, 0, 0, Opcode_fitrunc_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_fitrunc_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mkdadj_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mkdadj_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mksadj_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mksadj_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nexp0_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_nexp0_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nexp01_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_nexp01_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_recip0_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_recip0_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsqrt0_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_rsqrt0_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sqrt0_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_sqrt0_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float16_h_encode_fns[] = { + 0, 0, 0, Opcode_float16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_float16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat16_h_encode_fns[] = { + 0, 0, 0, Opcode_ufloat16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ufloat16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc16_h_encode_fns[] = { + 0, 0, 0, Opcode_trunc16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_trunc16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc16_h_encode_fns[] = { + 0, 0, 0, Opcode_utrunc16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_utrunc16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float16_hx4_encode_fns[] = { + 0, 0, 0, Opcode_float16_hx4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_float16_hx4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat16_hx4_encode_fns[] = { + 0, 0, 0, Opcode_ufloat16_hx4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ufloat16_hx4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc16_hx4_encode_fns[] = { + 0, 0, 0, Opcode_trunc16_hx4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_trunc16_hx4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc16_hx4_encode_fns[] = { + 0, 0, 0, Opcode_utrunc16_hx4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_utrunc16_hx4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_add_h_Slot_ae_slot2_encode, Opcode_add_h_Slot_ae_slot3_encode, 0, 0, Opcode_add_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_add_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_h_Slot_ae9_slot2_encode, Opcode_add_h_Slot_ae9_slot3_encode, 0, 0, Opcode_add_h_Slot_ae10_slot2_encode, Opcode_add_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_sub_h_Slot_ae_slot2_encode, Opcode_sub_h_Slot_ae_slot3_encode, 0, 0, Opcode_sub_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_sub_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_h_Slot_ae9_slot2_encode, Opcode_sub_h_Slot_ae9_slot3_encode, 0, 0, Opcode_sub_h_Slot_ae10_slot2_encode, Opcode_sub_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mul_h_Slot_ae_slot2_encode, Opcode_mul_h_Slot_ae_slot3_encode, 0, 0, Opcode_mul_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_mul_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mul_h_Slot_ae9_slot2_encode, Opcode_mul_h_Slot_ae9_slot3_encode, 0, 0, Opcode_mul_h_Slot_ae10_slot2_encode, Opcode_mul_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madd_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_madd_h_Slot_ae_slot2_encode, Opcode_madd_h_Slot_ae_slot3_encode, 0, 0, Opcode_madd_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_madd_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_madd_h_Slot_ae9_slot2_encode, Opcode_madd_h_Slot_ae9_slot3_encode, 0, 0, Opcode_madd_h_Slot_ae10_slot2_encode, Opcode_madd_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msub_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_msub_h_Slot_ae_slot2_encode, Opcode_msub_h_Slot_ae_slot3_encode, 0, 0, Opcode_msub_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_msub_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msub_h_Slot_ae9_slot2_encode, Opcode_msub_h_Slot_ae9_slot3_encode, 0, 0, Opcode_msub_h_Slot_ae10_slot2_encode, Opcode_msub_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddn_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maddn_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_maddn_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msubn_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_msubn_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msubn_h_Slot_ae9_slot2_encode, Opcode_msubn_h_Slot_ae9_slot3_encode, 0, 0, Opcode_msubn_h_Slot_ae10_slot2_encode, Opcode_msubn_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_divn_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_divn_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_divn_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rminnum_h_encode_fns[] = { + 0, 0, 0, Opcode_rminnum_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_rminnum_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rminnum_h_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rmaxnum_h_encode_fns[] = { + 0, 0, 0, Opcode_rmaxnum_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_rmaxnum_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rmaxnum_h_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_abs_hx4x2_Slot_ae_slot2_encode, Opcode_abs_hx4x2_Slot_ae_slot3_encode, 0, Opcode_abs_hx4x2_Slot_ae2_slot1_encode, Opcode_abs_hx4x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_abs_hx4x2_Slot_ae9_slot2_encode, Opcode_abs_hx4x2_Slot_ae9_slot3_encode, 0, 0, Opcode_abs_hx4x2_Slot_ae10_slot2_encode, Opcode_abs_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_neg_hx4x2_Slot_ae_slot2_encode, Opcode_neg_hx4x2_Slot_ae_slot3_encode, 0, Opcode_neg_hx4x2_Slot_ae2_slot1_encode, Opcode_neg_hx4x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_neg_hx4x2_Slot_ae9_slot2_encode, Opcode_neg_hx4x2_Slot_ae9_slot3_encode, 0, 0, Opcode_neg_hx4x2_Slot_ae10_slot2_encode, Opcode_neg_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_conjc_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_conjc_hx4x2_Slot_ae_slot2_encode, Opcode_conjc_hx4x2_Slot_ae_slot3_encode, 0, Opcode_conjc_hx4x2_Slot_ae2_slot1_encode, Opcode_conjc_hx4x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_conjc_hx4x2_Slot_ae9_slot2_encode, Opcode_conjc_hx4x2_Slot_ae9_slot3_encode, 0, 0, Opcode_conjc_hx4x2_Slot_ae10_slot2_encode, Opcode_conjc_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_const_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_const_hx4x2_Slot_ae_slot2_encode, Opcode_const_hx4x2_Slot_ae_slot3_encode, 0, Opcode_const_hx4x2_Slot_ae2_slot1_encode, Opcode_const_hx4x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_const_hx4x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_const_hx4x2_Slot_ae9_slot2_encode, Opcode_const_hx4x2_Slot_ae9_slot3_encode, 0, 0, Opcode_const_hx4x2_Slot_ae10_slot2_encode, Opcode_const_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muljc_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_muljc_hx4x2_Slot_ae_slot2_encode, Opcode_muljc_hx4x2_Slot_ae_slot3_encode, 0, Opcode_muljc_hx4x2_Slot_ae2_slot1_encode, Opcode_muljc_hx4x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_muljc_hx4x2_Slot_ae9_slot2_encode, Opcode_muljc_hx4x2_Slot_ae9_slot3_encode, 0, 0, Opcode_muljc_hx4x2_Slot_ae10_slot2_encode, Opcode_muljc_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_hx4x2_Slot_ae10_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_hx4x2_Slot_ae10_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mul_hx4x2_Slot_ae10_slot2_encode, Opcode_mul_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madd_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_madd_hx4x2_Slot_ae10_slot2_encode, Opcode_madd_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msub_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msub_hx4x2_Slot_ae10_slot2_encode, Opcode_msub_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulq_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulq_h_Slot_ae9_slot2_encode, 0, 0, 0, Opcode_mulq_h_Slot_ae10_slot2_encode, Opcode_mulq_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddq_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddq_h_Slot_ae10_slot2_encode, Opcode_maddq_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulcnvh_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulcnvh_hx4x2_Slot_ae10_slot2_encode, Opcode_mulcnvh_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulacnvh_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulacnvh_hx4x2_Slot_ae10_slot2_encode, Opcode_mulacnvh_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulcnvl_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulcnvl_hx4x2_Slot_ae10_slot2_encode, Opcode_mulcnvl_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulacnvl_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulacnvl_hx4x2_Slot_ae10_slot2_encode, Opcode_mulacnvl_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +int num_bypass_groups() { + return 0; +} + +int num_bypass_group_chunks() { + return 0; +} + +uint32 *bypass_entry(int i) { + return 0; +} + + +/* Opcode table. */ + +static xtensa_funcUnit_use Opcode_l32e_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32e_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32i_n_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32i_n_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l16ui_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l16si_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32r_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l8ui_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32ex_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32ex_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s16i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32nb_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s8i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_lddr32_p_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sddr32_p_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_lict_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_licw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sict_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sicw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sdct_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ldct_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sdcw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ldcw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32ai_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32ri_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4f_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4f_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4f_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4f_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4s_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4s_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4s_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4u_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4u_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4u_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4u_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ri_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4rng_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4rng_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4rng_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4rng_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2rng_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2rng_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2rng_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2rng_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2rng_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2rng_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2rng_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2rng_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lalign64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_salign64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la64_pp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa64pos_fp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa64neg_fp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24x2ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4ra32s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 } +}; + +static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbs_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbsi_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbki_dbi_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbki_dbi_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbki_dbi_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbi_dbi_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbi_dbi_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbi_dbi_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbk_db_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbk_db_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbk_db_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lb_db_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lb_db_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lb_db_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16si_n_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16ui_n_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16i_n_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lalign128_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_salign128_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la128_pp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa128pos_fp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x4s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x4u_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lav8x8x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lav16x4x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sav8x8x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sav16x4x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lavunsqz8x8_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lavunsqz16x4_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_opcode_internal opcodes[] = { + { "excw", ICLASS_xt_iclass_excw, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", ICLASS_xt_iclass_rfe, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", ICLASS_xt_iclass_rfde, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", ICLASS_xt_iclass_syscall, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "call12", ICLASS_xt_iclass_call12, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", ICLASS_xt_iclass_call8, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", ICLASS_xt_iclass_call4, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", ICLASS_xt_iclass_callx12, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", ICLASS_xt_iclass_callx8, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", ICLASS_xt_iclass_callx4, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", ICLASS_xt_iclass_entry, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", ICLASS_xt_iclass_movsp, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", ICLASS_xt_iclass_rotw, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", ICLASS_xt_iclass_l32e, + 0, + Opcode_l32e_encode_fns, 1, Opcode_l32e_funcUnit_uses }, + { "s32e", ICLASS_xt_iclass_s32e, + 0, + Opcode_s32e_encode_fns, 1, Opcode_s32e_funcUnit_uses }, + { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", ICLASS_xt_iclass_add_n, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", ICLASS_xt_iclass_addi_n, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", ICLASS_xt_iclass_ill_n, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", ICLASS_xt_iclass_loadi4, + 0, + Opcode_l32i_n_encode_fns, 1, Opcode_l32i_n_funcUnit_uses }, + { "mov.n", ICLASS_xt_iclass_mov_n, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", ICLASS_xt_iclass_movi_n, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", ICLASS_xt_iclass_nopn, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", ICLASS_xt_iclass_retn, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", ICLASS_xt_iclass_storei4, + 0, + Opcode_s32i_n_encode_fns, 1, Opcode_s32i_n_funcUnit_uses }, + { "rur.threadptr", ICLASS_rur_threadptr, + 0, + Opcode_rur_threadptr_encode_fns, 0, 0 }, + { "wur.threadptr", ICLASS_wur_threadptr, + 0, + Opcode_wur_threadptr_encode_fns, 0, 0 }, + { "addi", ICLASS_xt_iclass_addi, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", ICLASS_xt_iclass_addmi, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", ICLASS_xt_iclass_addsub, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "addx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "sub", ICLASS_xt_iclass_addsub, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "subx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", ICLASS_xt_iclass_bit, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", ICLASS_xt_iclass_bit, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", ICLASS_xt_iclass_bit, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bgei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bnei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bbci", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "ball", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bany", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bbc", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beq", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bge", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "bgeu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "blt", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bltu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bnall", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bne", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bnone", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "beqz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bgez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "bnez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "call0", ICLASS_xt_iclass_call0, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", ICLASS_xt_iclass_callx0, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "extui", ICLASS_xt_iclass_exti, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", ICLASS_xt_iclass_ill, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", ICLASS_xt_iclass_jump, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", ICLASS_xt_iclass_jumpx, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", ICLASS_xt_iclass_l16ui, + 0, + Opcode_l16ui_encode_fns, 1, Opcode_l16ui_funcUnit_uses }, + { "l16si", ICLASS_xt_iclass_l16si, + 0, + Opcode_l16si_encode_fns, 1, Opcode_l16si_funcUnit_uses }, + { "l32i", ICLASS_xt_iclass_l32i, + 0, + Opcode_l32i_encode_fns, 1, Opcode_l32i_funcUnit_uses }, + { "l32r", ICLASS_xt_iclass_l32r, + 0, + Opcode_l32r_encode_fns, 1, Opcode_l32r_funcUnit_uses }, + { "l8ui", ICLASS_xt_iclass_l8i, + 0, + Opcode_l8ui_encode_fns, 1, Opcode_l8ui_funcUnit_uses }, + { "loop", ICLASS_xt_iclass_loop, + XTENSA_OPCODE_IS_LOOP, + Opcode_loop_encode_fns, 0, 0 }, + { "loopgtz", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopgtz_encode_fns, 0, 0 }, + { "loopnez", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopnez_encode_fns, 0, 0 }, + { "movi", ICLASS_xt_iclass_movi, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", ICLASS_xt_iclass_movz, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movgez", ICLASS_xt_iclass_movz, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "movltz", ICLASS_xt_iclass_movz, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movnez", ICLASS_xt_iclass_movz, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "abs", ICLASS_xt_iclass_neg, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "neg", ICLASS_xt_iclass_neg, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "nop", ICLASS_xt_iclass_nop, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "l32ex", ICLASS_xt_iclass_l32ex, + 0, + Opcode_l32ex_encode_fns, 1, Opcode_l32ex_funcUnit_uses }, + { "s32ex", ICLASS_xt_iclass_s32ex, + 0, + Opcode_s32ex_encode_fns, 1, Opcode_s32ex_funcUnit_uses }, + { "getex", ICLASS_xt_iclass_getex, + 0, + Opcode_getex_encode_fns, 0, 0 }, + { "clrex", ICLASS_xt_iclass_clrex, + 0, + Opcode_clrex_encode_fns, 0, 0 }, + { "ret", ICLASS_xt_iclass_return, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "simcall", ICLASS_xt_iclass_simcall, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "s16i", ICLASS_xt_iclass_s16i, + 0, + Opcode_s16i_encode_fns, 1, Opcode_s16i_funcUnit_uses }, + { "s32i", ICLASS_xt_iclass_s32i, + 0, + Opcode_s32i_encode_fns, 1, Opcode_s32i_funcUnit_uses }, + { "s32nb", ICLASS_xt_iclass_s32nb, + 0, + Opcode_s32nb_encode_fns, 1, Opcode_s32nb_funcUnit_uses }, + { "s8i", ICLASS_xt_iclass_s8i, + 0, + Opcode_s8i_encode_fns, 1, Opcode_s8i_funcUnit_uses }, + { "ssa8b", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssa8l", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssl", ICLASS_xt_iclass_sar, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssr", ICLASS_xt_iclass_sar, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssai", ICLASS_xt_iclass_sari, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", ICLASS_xt_iclass_shifts, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", ICLASS_xt_iclass_shiftst, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "sra", ICLASS_xt_iclass_shiftt, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "srl", ICLASS_xt_iclass_shiftt, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "slli", ICLASS_xt_iclass_slli, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", ICLASS_xt_iclass_srai, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", ICLASS_xt_iclass_srli, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", ICLASS_xt_iclass_memw, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", ICLASS_xt_iclass_extw, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", ICLASS_xt_iclass_isync, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "dsync", ICLASS_xt_iclass_sync, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "esync", ICLASS_xt_iclass_sync, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "rsync", ICLASS_xt_iclass_sync, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "rsil", ICLASS_xt_iclass_rsil, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.lend", ICLASS_xt_iclass_rsr_lend, + 0, + Opcode_rsr_lend_encode_fns, 0, 0 }, + { "wsr.lend", ICLASS_xt_iclass_wsr_lend, + 0, + Opcode_wsr_lend_encode_fns, 0, 0 }, + { "xsr.lend", ICLASS_xt_iclass_xsr_lend, + 0, + Opcode_xsr_lend_encode_fns, 0, 0 }, + { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, + 0, + Opcode_rsr_lcount_encode_fns, 0, 0 }, + { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, + 0, + Opcode_wsr_lcount_encode_fns, 0, 0 }, + { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, + 0, + Opcode_xsr_lcount_encode_fns, 0, 0 }, + { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, + 0, + Opcode_rsr_lbeg_encode_fns, 0, 0 }, + { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, + 0, + Opcode_wsr_lbeg_encode_fns, 0, 0 }, + { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, + 0, + Opcode_xsr_lbeg_encode_fns, 0, 0 }, + { "rsr.sar", ICLASS_xt_iclass_rsr_sar, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", ICLASS_xt_iclass_wsr_sar, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", ICLASS_xt_iclass_xsr_sar, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl, + 0, + Opcode_rsr_memctl_encode_fns, 0, 0 }, + { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl, + 0, + Opcode_wsr_memctl_encode_fns, 0, 0 }, + { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl, + 0, + Opcode_xsr_memctl_encode_fns, 0, 0 }, + { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, + 0, + Opcode_rsr_configid0_encode_fns, 0, 0 }, + { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, + 0, + Opcode_wsr_configid0_encode_fns, 0, 0 }, + { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, + 0, + Opcode_rsr_configid1_encode_fns, 0, 0 }, + { "rsr.ps", ICLASS_xt_iclass_rsr_ps, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", ICLASS_xt_iclass_wsr_ps, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", ICLASS_xt_iclass_xsr_ps, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, + 0, + Opcode_rsr_epc3_encode_fns, 0, 0 }, + { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, + 0, + Opcode_wsr_epc3_encode_fns, 0, 0 }, + { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, + 0, + Opcode_xsr_epc3_encode_fns, 0, 0 }, + { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, + 0, + Opcode_rsr_excsave3_encode_fns, 0, 0 }, + { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, + 0, + Opcode_wsr_excsave3_encode_fns, 0, 0 }, + { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, + 0, + Opcode_xsr_excsave3_encode_fns, 0, 0 }, + { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, + 0, + Opcode_rsr_epc4_encode_fns, 0, 0 }, + { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, + 0, + Opcode_wsr_epc4_encode_fns, 0, 0 }, + { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, + 0, + Opcode_xsr_epc4_encode_fns, 0, 0 }, + { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, + 0, + Opcode_rsr_excsave4_encode_fns, 0, 0 }, + { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, + 0, + Opcode_wsr_excsave4_encode_fns, 0, 0 }, + { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, + 0, + Opcode_xsr_excsave4_encode_fns, 0, 0 }, + { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, + 0, + Opcode_rsr_epc5_encode_fns, 0, 0 }, + { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, + 0, + Opcode_wsr_epc5_encode_fns, 0, 0 }, + { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, + 0, + Opcode_xsr_epc5_encode_fns, 0, 0 }, + { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, + 0, + Opcode_rsr_excsave5_encode_fns, 0, 0 }, + { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, + 0, + Opcode_wsr_excsave5_encode_fns, 0, 0 }, + { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, + 0, + Opcode_xsr_excsave5_encode_fns, 0, 0 }, + { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, + 0, + Opcode_rsr_epc6_encode_fns, 0, 0 }, + { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, + 0, + Opcode_wsr_epc6_encode_fns, 0, 0 }, + { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, + 0, + Opcode_xsr_epc6_encode_fns, 0, 0 }, + { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, + 0, + Opcode_rsr_excsave6_encode_fns, 0, 0 }, + { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, + 0, + Opcode_wsr_excsave6_encode_fns, 0, 0 }, + { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, + 0, + Opcode_xsr_excsave6_encode_fns, 0, 0 }, + { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, + 0, + Opcode_rsr_eps3_encode_fns, 0, 0 }, + { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, + 0, + Opcode_wsr_eps3_encode_fns, 0, 0 }, + { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, + 0, + Opcode_xsr_eps3_encode_fns, 0, 0 }, + { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, + 0, + Opcode_rsr_eps4_encode_fns, 0, 0 }, + { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, + 0, + Opcode_wsr_eps4_encode_fns, 0, 0 }, + { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, + 0, + Opcode_xsr_eps4_encode_fns, 0, 0 }, + { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, + 0, + Opcode_rsr_eps5_encode_fns, 0, 0 }, + { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, + 0, + Opcode_wsr_eps5_encode_fns, 0, 0 }, + { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, + 0, + Opcode_xsr_eps5_encode_fns, 0, 0 }, + { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, + 0, + Opcode_rsr_eps6_encode_fns, 0, 0 }, + { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, + 0, + Opcode_wsr_eps6_encode_fns, 0, 0 }, + { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, + 0, + Opcode_xsr_eps6_encode_fns, 0, 0 }, + { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", ICLASS_xt_iclass_rsr_depc, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", ICLASS_xt_iclass_wsr_depc, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", ICLASS_xt_iclass_xsr_depc, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, + 0, + Opcode_rsr_misc0_encode_fns, 0, 0 }, + { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, + 0, + Opcode_wsr_misc0_encode_fns, 0, 0 }, + { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, + 0, + Opcode_xsr_misc0_encode_fns, 0, 0 }, + { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, + 0, + Opcode_rsr_misc1_encode_fns, 0, 0 }, + { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, + 0, + Opcode_wsr_misc1_encode_fns, 0, 0 }, + { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, + 0, + Opcode_xsr_misc1_encode_fns, 0, 0 }, + { "rsr.misc2", ICLASS_xt_iclass_rsr_misc2, + 0, + Opcode_rsr_misc2_encode_fns, 0, 0 }, + { "wsr.misc2", ICLASS_xt_iclass_wsr_misc2, + 0, + Opcode_wsr_misc2_encode_fns, 0, 0 }, + { "xsr.misc2", ICLASS_xt_iclass_xsr_misc2, + 0, + Opcode_xsr_misc2_encode_fns, 0, 0 }, + { "rsr.misc3", ICLASS_xt_iclass_rsr_misc3, + 0, + Opcode_rsr_misc3_encode_fns, 0, 0 }, + { "wsr.misc3", ICLASS_xt_iclass_wsr_misc3, + 0, + Opcode_wsr_misc3_encode_fns, 0, 0 }, + { "xsr.misc3", ICLASS_xt_iclass_xsr_misc3, + 0, + Opcode_xsr_misc3_encode_fns, 0, 0 }, + { "rsr.prid", ICLASS_xt_iclass_rsr_prid, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, + 0, + Opcode_rsr_vecbase_encode_fns, 0, 0 }, + { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, + 0, + Opcode_wsr_vecbase_encode_fns, 0, 0 }, + { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, + 0, + Opcode_xsr_vecbase_encode_fns, 0, 0 }, + { "rsr.mpucfg", ICLASS_xt_iclass_rsr_mpucfg, + 0, + Opcode_rsr_mpucfg_encode_fns, 0, 0 }, + { "wsr.mpucfg", ICLASS_xt_iclass_wsr_mpucfg, + 0, + Opcode_wsr_mpucfg_encode_fns, 0, 0 }, + { "salt", ICLASS_xt_iclass_salt, + 0, + Opcode_salt_encode_fns, 0, 0 }, + { "saltu", ICLASS_xt_iclass_salt, + 0, + Opcode_saltu_encode_fns, 0, 0 }, + { "rsr.opmode", ICLASS_xt_iclass_rsr_opmode, + 0, + Opcode_rsr_opmode_encode_fns, 0, 0 }, + { "wsr.opmode", ICLASS_xt_iclass_wsr_opmode, + 0, + Opcode_wsr_opmode_encode_fns, 0, 0 }, + { "xsr.opmode", ICLASS_xt_iclass_xsr_opmode, + 0, + Opcode_xsr_opmode_encode_fns, 0, 0 }, + { "mul16s", ICLASS_xt_mul16, + 0, + Opcode_mul16s_encode_fns, 0, 0 }, + { "mul16u", ICLASS_xt_mul16, + 0, + Opcode_mul16u_encode_fns, 0, 0 }, + { "mull", ICLASS_xt_mul32, + 0, + Opcode_mull_encode_fns, 0, 0 }, + { "rfi", ICLASS_xt_iclass_rfi, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", ICLASS_xt_iclass_wait, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", ICLASS_xt_iclass_wsr_intset, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", ICLASS_xt_iclass_break, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", ICLASS_xt_iclass_break_n, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, + 0, + Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, + { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, + 0, + Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, + { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, + 0, + Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, + { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, + 0, + Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, + { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, + 0, + Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, + { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, + 0, + Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, + { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, + 0, + Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, + { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, + 0, + Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, + { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, + 0, + Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, + { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, + 0, + Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, + { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, + 0, + Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, + { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, + 0, + Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, + { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, + 0, + Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, + { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, + 0, + Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, + { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, + 0, + Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, + { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, + 0, + Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, + { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, + 0, + Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, + { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, + 0, + Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, + { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, + 0, + Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, + { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, + 0, + Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, + { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, + 0, + Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, + { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", ICLASS_xt_iclass_rsr_icount, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", ICLASS_xt_iclass_wsr_icount, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", ICLASS_xt_iclass_xsr_icount, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "lddr32.p", ICLASS_xt_iclass_lddr32_p, + 0, + Opcode_lddr32_p_encode_fns, 1, Opcode_lddr32_p_funcUnit_uses }, + { "sddr32.p", ICLASS_xt_iclass_sddr32_p, + 0, + Opcode_sddr32_p_encode_fns, 1, Opcode_sddr32_p_funcUnit_uses }, + { "rfdo", ICLASS_xt_iclass_rfdo, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", ICLASS_xt_iclass_rfdd, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, + 0, + Opcode_wsr_mmid_encode_fns, 0, 0 }, + { "andb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andb_encode_fns, 0, 0 }, + { "andbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andbc_encode_fns, 0, 0 }, + { "orb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orb_encode_fns, 0, 0 }, + { "orbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orbc_encode_fns, 0, 0 }, + { "xorb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_xorb_encode_fns, 0, 0 }, + { "all4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_all4_encode_fns, 0, 0 }, + { "any4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_any4_encode_fns, 0, 0 }, + { "all8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_all8_encode_fns, 0, 0 }, + { "any8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_any8_encode_fns, 0, 0 }, + { "bf", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bf_encode_fns, 0, 0 }, + { "bt", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bt_encode_fns, 0, 0 }, + { "movf", ICLASS_xt_iclass_bmove, + 0, + Opcode_movf_encode_fns, 0, 0 }, + { "movt", ICLASS_xt_iclass_bmove, + 0, + Opcode_movt_encode_fns, 0, 0 }, + { "rsr.br", ICLASS_xt_iclass_RSR_BR, + 0, + Opcode_rsr_br_encode_fns, 0, 0 }, + { "wsr.br", ICLASS_xt_iclass_WSR_BR, + 0, + Opcode_wsr_br_encode_fns, 0, 0 }, + { "xsr.br", ICLASS_xt_iclass_XSR_BR, + 0, + Opcode_xsr_br_encode_fns, 0, 0 }, + { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, + 0, + Opcode_rsr_ccompare1_encode_fns, 0, 0 }, + { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, + 0, + Opcode_wsr_ccompare1_encode_fns, 0, 0 }, + { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, + 0, + Opcode_xsr_ccompare1_encode_fns, 0, 0 }, + { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, + 0, + Opcode_rsr_ccompare2_encode_fns, 0, 0 }, + { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, + 0, + Opcode_wsr_ccompare2_encode_fns, 0, 0 }, + { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, + 0, + Opcode_xsr_ccompare2_encode_fns, 0, 0 }, + { "ihi", ICLASS_xt_iclass_icache, + 0, + Opcode_ihi_encode_fns, 0, 0 }, + { "ipf", ICLASS_xt_iclass_icache, + 0, + Opcode_ipf_encode_fns, 0, 0 }, + { "ihu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ihu_encode_fns, 0, 0 }, + { "iiu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_iiu_encode_fns, 0, 0 }, + { "ipfl", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ipfl_encode_fns, 0, 0 }, + { "iii", ICLASS_xt_iclass_icache_inv, + 0, + Opcode_iii_encode_fns, 0, 0 }, + { "lict", ICLASS_xt_iclass_licx, + 0, + Opcode_lict_encode_fns, 1, Opcode_lict_funcUnit_uses }, + { "licw", ICLASS_xt_iclass_licx, + 0, + Opcode_licw_encode_fns, 1, Opcode_licw_funcUnit_uses }, + { "sict", ICLASS_xt_iclass_sicx, + 0, + Opcode_sict_encode_fns, 1, Opcode_sict_funcUnit_uses }, + { "sicw", ICLASS_xt_iclass_sicx, + 0, + Opcode_sicw_encode_fns, 1, Opcode_sicw_funcUnit_uses }, + { "dhwb", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwb_encode_fns, 0, 0 }, + { "dhwbi", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwbi_encode_fns, 0, 0 }, + { "diwbui.p", ICLASS_xt_iclass_dcache_dyn, + 0, + Opcode_diwbui_p_encode_fns, 0, 0 }, + { "diwb", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwb_encode_fns, 0, 0 }, + { "diwbi", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwbi_encode_fns, 0, 0 }, + { "dhi", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dhi_encode_fns, 0, 0 }, + { "dii", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dii_encode_fns, 0, 0 }, + { "dpfr", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfr_encode_fns, 0, 0 }, + { "dpfro", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfro_encode_fns, 0, 0 }, + { "dpfw", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfw_encode_fns, 0, 0 }, + { "dpfwo", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfwo_encode_fns, 0, 0 }, + { "dpfm.b", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfm_b_encode_fns, 0, 0 }, + { "dpfm.bf", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfm_bf_encode_fns, 0, 0 }, + { "dpfr.b", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfr_b_encode_fns, 0, 0 }, + { "dpfr.bf", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfr_bf_encode_fns, 0, 0 }, + { "dpfw.b", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfw_b_encode_fns, 0, 0 }, + { "dpfw.bf", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfw_bf_encode_fns, 0, 0 }, + { "pfnxt.f", ICLASS_xt_iclass_bpfnxt, + 0, + Opcode_pfnxt_f_encode_fns, 0, 0 }, + { "dhi.b", ICLASS_xt_iclass_dpdngrd, + 0, + Opcode_dhi_b_encode_fns, 0, 0 }, + { "dhwbi.b", ICLASS_xt_iclass_dpdngrd, + 0, + Opcode_dhwbi_b_encode_fns, 0, 0 }, + { "dhwb.b", ICLASS_xt_iclass_dpdngrd, + 0, + Opcode_dhwb_b_encode_fns, 0, 0 }, + { "pfend.a", ICLASS_xt_iclass_bpfctl, + 0, + Opcode_pfend_a_encode_fns, 0, 0 }, + { "pfend.o", ICLASS_xt_iclass_bpfctl, + 0, + Opcode_pfend_o_encode_fns, 0, 0 }, + { "pfwait.a", ICLASS_xt_iclass_bpfctl, + 0, + Opcode_pfwait_a_encode_fns, 0, 0 }, + { "pfwait.r", ICLASS_xt_iclass_bpfctl, + 0, + Opcode_pfwait_r_encode_fns, 0, 0 }, + { "dhu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dhu_encode_fns, 0, 0 }, + { "diu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_diu_encode_fns, 0, 0 }, + { "dpfl", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dpfl_encode_fns, 0, 0 }, + { "sdct", ICLASS_xt_iclass_sdct, + 0, + Opcode_sdct_encode_fns, 1, Opcode_sdct_funcUnit_uses }, + { "ldct", ICLASS_xt_iclass_ldct, + 0, + Opcode_ldct_encode_fns, 1, Opcode_ldct_funcUnit_uses }, + { "sdcw", ICLASS_xt_iclass_sdcw, + 0, + Opcode_sdcw_encode_fns, 1, Opcode_sdcw_funcUnit_uses }, + { "ldcw", ICLASS_xt_iclass_ldcw, + 0, + Opcode_ldcw_encode_fns, 1, Opcode_ldcw_funcUnit_uses }, + { "rsr.prefctl", ICLASS_xt_iclass_rsr_prefctl, + 0, + Opcode_rsr_prefctl_encode_fns, 0, 0 }, + { "wsr.prefctl", ICLASS_xt_iclass_wsr_prefctl, + 0, + Opcode_wsr_prefctl_encode_fns, 0, 0 }, + { "xsr.prefctl", ICLASS_xt_iclass_xsr_prefctl, + 0, + Opcode_xsr_prefctl_encode_fns, 0, 0 }, + { "wsr.cacheadrdis", ICLASS_xt_iclass_wsr_cacheadrdis, + 0, + Opcode_wsr_cacheadrdis_encode_fns, 0, 0 }, + { "rsr.cacheadrdis", ICLASS_xt_iclass_rsr_cacheadrdis, + 0, + Opcode_rsr_cacheadrdis_encode_fns, 0, 0 }, + { "xsr.cacheadrdis", ICLASS_xt_iclass_xsr_cacheadrdis, + 0, + Opcode_xsr_cacheadrdis_encode_fns, 0, 0 }, + { "rptlb0", ICLASS_xt_iclass_rptlb0, + 0, + Opcode_rptlb0_encode_fns, 0, 0 }, + { "pptlb", ICLASS_xt_iclass_rptlb, + 0, + Opcode_pptlb_encode_fns, 0, 0 }, + { "rptlb1", ICLASS_xt_iclass_rptlb, + 0, + Opcode_rptlb1_encode_fns, 0, 0 }, + { "wptlb", ICLASS_xt_iclass_wptlb, + 0, + Opcode_wptlb_encode_fns, 0, 0 }, + { "rsr.mpuenb", ICLASS_xt_iclass_rsr_mpuenb, + 0, + Opcode_rsr_mpuenb_encode_fns, 0, 0 }, + { "wsr.mpuenb", ICLASS_xt_iclass_wsr_mpuenb, + 0, + Opcode_wsr_mpuenb_encode_fns, 0, 0 }, + { "xsr.mpuenb", ICLASS_xt_iclass_xsr_mpuenb, + 0, + Opcode_xsr_mpuenb_encode_fns, 0, 0 }, + { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, + 0, + Opcode_rsr_cpenable_encode_fns, 0, 0 }, + { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, + 0, + Opcode_wsr_cpenable_encode_fns, 0, 0 }, + { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, + 0, + Opcode_xsr_cpenable_encode_fns, 0, 0 }, + { "clamps", ICLASS_xt_iclass_clamp, + 0, + Opcode_clamps_encode_fns, 0, 0 }, + { "max", ICLASS_xt_iclass_minmax, + 0, + Opcode_max_encode_fns, 0, 0 }, + { "maxu", ICLASS_xt_iclass_minmax, + 0, + Opcode_maxu_encode_fns, 0, 0 }, + { "min", ICLASS_xt_iclass_minmax, + 0, + Opcode_min_encode_fns, 0, 0 }, + { "minu", ICLASS_xt_iclass_minmax, + 0, + Opcode_minu_encode_fns, 0, 0 }, + { "nsa", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsau_encode_fns, 0, 0 }, + { "sext", ICLASS_xt_iclass_sx, + 0, + Opcode_sext_encode_fns, 0, 0 }, + { "l32ai", ICLASS_xt_iclass_l32ai, + 0, + Opcode_l32ai_encode_fns, 1, Opcode_l32ai_funcUnit_uses }, + { "s32ri", ICLASS_xt_iclass_s32ri, + 0, + Opcode_s32ri_encode_fns, 1, Opcode_s32ri_funcUnit_uses }, + { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, + 0, + Opcode_rsr_atomctl_encode_fns, 0, 0 }, + { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, + 0, + Opcode_wsr_atomctl_encode_fns, 0, 0 }, + { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, + 0, + Opcode_xsr_atomctl_encode_fns, 0, 0 }, + { "quos", ICLASS_xt_iclass_div, + 0, + Opcode_quos_encode_fns, 0, 0 }, + { "quou", ICLASS_xt_iclass_div, + 0, + Opcode_quou_encode_fns, 0, 0 }, + { "rems", ICLASS_xt_iclass_div, + 0, + Opcode_rems_encode_fns, 0, 0 }, + { "remu", ICLASS_xt_iclass_div, + 0, + Opcode_remu_encode_fns, 0, 0 }, + { "rsr.eraccess", ICLASS_xt_iclass_rsr_eraccess, + 0, + Opcode_rsr_eraccess_encode_fns, 0, 0 }, + { "wsr.eraccess", ICLASS_xt_iclass_wsr_eraccess, + 0, + Opcode_wsr_eraccess_encode_fns, 0, 0 }, + { "xsr.eraccess", ICLASS_xt_iclass_xsr_eraccess, + 0, + Opcode_xsr_eraccess_encode_fns, 0, 0 }, + { "rer", ICLASS_xt_iclass_rer, + 0, + Opcode_rer_encode_fns, 0, 0 }, + { "wer", ICLASS_xt_iclass_wer, + 0, + Opcode_wer_encode_fns, 0, 0 }, + { "beqz.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_w15_encode_fns, 0, 0 }, + { "bgez.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_w15_encode_fns, 0, 0 }, + { "bltz.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_w15_encode_fns, 0, 0 }, + { "bnez.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_w15_encode_fns, 0, 0 }, + { "beqi.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_w15_encode_fns, 0, 0 }, + { "bgei.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_w15_encode_fns, 0, 0 }, + { "blti.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_w15_encode_fns, 0, 0 }, + { "bnei.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_w15_encode_fns, 0, 0 }, + { "bgeui.w15", ICLASS_xt_iclass_wb15_2, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_w15_encode_fns, 0, 0 }, + { "bltui.w15", ICLASS_xt_iclass_wb15_2, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_w15_encode_fns, 0, 0 }, + { "bbci.w15", ICLASS_xt_iclass_wb15_3, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_w15_encode_fns, 0, 0 }, + { "bbsi.w15", ICLASS_xt_iclass_wb15_3, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_w15_encode_fns, 0, 0 }, + { "ball.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_w15_encode_fns, 0, 0 }, + { "bany.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_w15_encode_fns, 0, 0 }, + { "bbc.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_w15_encode_fns, 0, 0 }, + { "bbs.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_w15_encode_fns, 0, 0 }, + { "beq.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_w15_encode_fns, 0, 0 }, + { "bgeu.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_w15_encode_fns, 0, 0 }, + { "bge.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_w15_encode_fns, 0, 0 }, + { "bltu.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_w15_encode_fns, 0, 0 }, + { "blt.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_w15_encode_fns, 0, 0 }, + { "bnall.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_w15_encode_fns, 0, 0 }, + { "bne.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_w15_encode_fns, 0, 0 }, + { "bnone.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_w15_encode_fns, 0, 0 }, + { "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar, + 0, + Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 }, + { "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar, + 0, + Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 }, + { "rur.ae_bithead", ICLASS_rur_ae_bithead, + 0, + Opcode_rur_ae_bithead_encode_fns, 0, 0 }, + { "wur.ae_bithead", ICLASS_wur_ae_bithead, + 0, + Opcode_wur_ae_bithead_encode_fns, 0, 0 }, + { "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp, + 0, + Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, + { "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp, + 0, + Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, + { "rur.ae_cw_sd_no", ICLASS_rur_ae_cw_sd_no, + 0, + Opcode_rur_ae_cw_sd_no_encode_fns, 0, 0 }, + { "wur.ae_cw_sd_no", ICLASS_wur_ae_cw_sd_no, + 0, + Opcode_wur_ae_cw_sd_no_encode_fns, 0, 0 }, + { "rur.ae_cbegin0", ICLASS_rur_ae_cbegin0, + 0, + Opcode_rur_ae_cbegin0_encode_fns, 0, 0 }, + { "wur.ae_cbegin0", ICLASS_wur_ae_cbegin0, + 0, + Opcode_wur_ae_cbegin0_encode_fns, 0, 0 }, + { "rur.ae_cend0", ICLASS_rur_ae_cend0, + 0, + Opcode_rur_ae_cend0_encode_fns, 0, 0 }, + { "wur.ae_cend0", ICLASS_wur_ae_cend0, + 0, + Opcode_wur_ae_cend0_encode_fns, 0, 0 }, + { "rur.ae_cbegin1", ICLASS_rur_ae_cbegin1, + 0, + Opcode_rur_ae_cbegin1_encode_fns, 0, 0 }, + { "wur.ae_cbegin1", ICLASS_wur_ae_cbegin1, + 0, + Opcode_wur_ae_cbegin1_encode_fns, 0, 0 }, + { "rur.ae_cend1", ICLASS_rur_ae_cend1, + 0, + Opcode_rur_ae_cend1_encode_fns, 0, 0 }, + { "wur.ae_cend1", ICLASS_wur_ae_cend1, + 0, + Opcode_wur_ae_cend1_encode_fns, 0, 0 }, + { "rur.ae_cbegin2", ICLASS_rur_ae_cbegin2, + 0, + Opcode_rur_ae_cbegin2_encode_fns, 0, 0 }, + { "wur.ae_cbegin2", ICLASS_wur_ae_cbegin2, + 0, + Opcode_wur_ae_cbegin2_encode_fns, 0, 0 }, + { "rur.ae_cend2", ICLASS_rur_ae_cend2, + 0, + Opcode_rur_ae_cend2_encode_fns, 0, 0 }, + { "wur.ae_cend2", ICLASS_wur_ae_cend2, + 0, + Opcode_wur_ae_cend2_encode_fns, 0, 0 }, + { "ae_sext16", ICLASS_ic_sext16, + 0, + Opcode_ae_sext16_encode_fns, 0, 0 }, + { "ae_zext16", ICLASS_ic_zext16, + 0, + Opcode_ae_zext16_encode_fns, 0, 0 }, + { "ae_zext8", ICLASS_ic_zext8, + 0, + Opcode_ae_zext8_encode_fns, 0, 0 }, + { "ae_clamps16", ICLASS_ic_clamps16, + 0, + Opcode_ae_clamps16_encode_fns, 0, 0 }, + { "rur.fcr", ICLASS_rur_fcr, + 0, + Opcode_rur_fcr_encode_fns, 0, 0 }, + { "wur.fcr", ICLASS_wur_fcr, + 0, + Opcode_wur_fcr_encode_fns, 0, 0 }, + { "rur.fsr", ICLASS_rur_fsr, + 0, + Opcode_rur_fsr_encode_fns, 0, 0 }, + { "wur.fsr", ICLASS_wur_fsr, + 0, + Opcode_wur_fsr_encode_fns, 0, 0 }, + { "rur.expstate", ICLASS_rur_expstate, + 0, + Opcode_rur_expstate_encode_fns, 0, 0 }, + { "wur.expstate", ICLASS_wur_expstate, + 0, + Opcode_wur_expstate_encode_fns, 0, 0 }, + { "read_impwire", ICLASS_iclass_READ_IMPWIRE, + 0, + Opcode_read_impwire_encode_fns, 0, 0 }, + { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, + 0, + Opcode_setb_expstate_encode_fns, 0, 0 }, + { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, + 0, + Opcode_clrb_expstate_encode_fns, 0, 0 }, + { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, + 0, + Opcode_wrmsk_expstate_encode_fns, 0, 0 }, + { "rur.ae_overflow", ICLASS_RUR_AE_OVERFLOW, + 0, + Opcode_rur_ae_overflow_encode_fns, 0, 0 }, + { "wur.ae_overflow", ICLASS_WUR_AE_OVERFLOW, + 0, + Opcode_wur_ae_overflow_encode_fns, 0, 0 }, + { "rur.ae_sar", ICLASS_RUR_AE_SAR, + 0, + Opcode_rur_ae_sar_encode_fns, 0, 0 }, + { "wur.ae_sar", ICLASS_WUR_AE_SAR, + 0, + Opcode_wur_ae_sar_encode_fns, 0, 0 }, + { "rur.ae_bitptr", ICLASS_RUR_AE_BITPTR, + 0, + Opcode_rur_ae_bitptr_encode_fns, 0, 0 }, + { "wur.ae_bitptr", ICLASS_WUR_AE_BITPTR, + 0, + Opcode_wur_ae_bitptr_encode_fns, 0, 0 }, + { "rur.ae_bitsused", ICLASS_RUR_AE_BITSUSED, + 0, + Opcode_rur_ae_bitsused_encode_fns, 0, 0 }, + { "wur.ae_bitsused", ICLASS_WUR_AE_BITSUSED, + 0, + Opcode_wur_ae_bitsused_encode_fns, 0, 0 }, + { "rur.ae_tablesize", ICLASS_RUR_AE_TABLESIZE, + 0, + Opcode_rur_ae_tablesize_encode_fns, 0, 0 }, + { "wur.ae_tablesize", ICLASS_WUR_AE_TABLESIZE, + 0, + Opcode_wur_ae_tablesize_encode_fns, 0, 0 }, + { "rur.ae_first_ts", ICLASS_RUR_AE_FIRST_TS, + 0, + Opcode_rur_ae_first_ts_encode_fns, 0, 0 }, + { "wur.ae_first_ts", ICLASS_WUR_AE_FIRST_TS, + 0, + Opcode_wur_ae_first_ts_encode_fns, 0, 0 }, + { "rur.ae_nextoffset", ICLASS_RUR_AE_NEXTOFFSET, + 0, + Opcode_rur_ae_nextoffset_encode_fns, 0, 0 }, + { "wur.ae_nextoffset", ICLASS_WUR_AE_NEXTOFFSET, + 0, + Opcode_wur_ae_nextoffset_encode_fns, 0, 0 }, + { "rur.ae_searchdone", ICLASS_RUR_AE_SEARCHDONE, + 0, + Opcode_rur_ae_searchdone_encode_fns, 0, 0 }, + { "wur.ae_searchdone", ICLASS_WUR_AE_SEARCHDONE, + 0, + Opcode_wur_ae_searchdone_encode_fns, 0, 0 }, + { "rur.ae_cwrap", ICLASS_RUR_AE_CWRAP, + 0, + Opcode_rur_ae_cwrap_encode_fns, 0, 0 }, + { "wur.ae_cwrap", ICLASS_WUR_AE_CWRAP, + 0, + Opcode_wur_ae_cwrap_encode_fns, 0, 0 }, + { "ae_l8x4f.i", ICLASS_AE_L8X4F_I, + 0, + Opcode_ae_l8x4f_i_encode_fns, 1, Opcode_ae_l8x4f_i_funcUnit_uses }, + { "ae_l8x4f.ip", ICLASS_AE_L8X4F_IP, + 0, + Opcode_ae_l8x4f_ip_encode_fns, 1, Opcode_ae_l8x4f_ip_funcUnit_uses }, + { "ae_l8x4f.x", ICLASS_AE_L8X4F_X, + 0, + Opcode_ae_l8x4f_x_encode_fns, 1, Opcode_ae_l8x4f_x_funcUnit_uses }, + { "ae_l8x4f.xp", ICLASS_AE_L8X4F_XP, + 0, + Opcode_ae_l8x4f_xp_encode_fns, 1, Opcode_ae_l8x4f_xp_funcUnit_uses }, + { "ae_l8x4s.i", ICLASS_AE_L8X4S_I, + 0, + Opcode_ae_l8x4s_i_encode_fns, 1, Opcode_ae_l8x4s_i_funcUnit_uses }, + { "ae_l8x4s.ip", ICLASS_AE_L8X4S_IP, + 0, + Opcode_ae_l8x4s_ip_encode_fns, 1, Opcode_ae_l8x4s_ip_funcUnit_uses }, + { "ae_l8x4s.x", ICLASS_AE_L8X4S_X, + 0, + Opcode_ae_l8x4s_x_encode_fns, 1, Opcode_ae_l8x4s_x_funcUnit_uses }, + { "ae_l8x4s.xp", ICLASS_AE_L8X4S_XP, + 0, + Opcode_ae_l8x4s_xp_encode_fns, 1, Opcode_ae_l8x4s_xp_funcUnit_uses }, + { "ae_l8x4u.i", ICLASS_AE_L8X4U_I, + 0, + Opcode_ae_l8x4u_i_encode_fns, 1, Opcode_ae_l8x4u_i_funcUnit_uses }, + { "ae_l8x4u.ip", ICLASS_AE_L8X4U_IP, + 0, + Opcode_ae_l8x4u_ip_encode_fns, 1, Opcode_ae_l8x4u_ip_funcUnit_uses }, + { "ae_l8x4u.x", ICLASS_AE_L8X4U_X, + 0, + Opcode_ae_l8x4u_x_encode_fns, 1, Opcode_ae_l8x4u_x_funcUnit_uses }, + { "ae_l8x4u.xp", ICLASS_AE_L8X4U_XP, + 0, + Opcode_ae_l8x4u_xp_encode_fns, 1, Opcode_ae_l8x4u_xp_funcUnit_uses }, + { "ae_l16m.xc", ICLASS_AE_L16M_XC, + 0, + Opcode_ae_l16m_xc_encode_fns, 1, Opcode_ae_l16m_xc_funcUnit_uses }, + { "ae_l16m.xc1", ICLASS_AE_L16M_XC1, + 0, + Opcode_ae_l16m_xc1_encode_fns, 1, Opcode_ae_l16m_xc1_funcUnit_uses }, + { "ae_l16m.i", ICLASS_AE_L16M_I, + 0, + Opcode_ae_l16m_i_encode_fns, 1, Opcode_ae_l16m_i_funcUnit_uses }, + { "ae_l16m.iu", ICLASS_AE_L16M_IU, + 0, + Opcode_ae_l16m_iu_encode_fns, 1, Opcode_ae_l16m_iu_funcUnit_uses }, + { "ae_l16m.x", ICLASS_AE_L16M_X, + 0, + Opcode_ae_l16m_x_encode_fns, 1, Opcode_ae_l16m_x_funcUnit_uses }, + { "ae_l16m.xu", ICLASS_AE_L16M_XU, + 0, + Opcode_ae_l16m_xu_encode_fns, 1, Opcode_ae_l16m_xu_funcUnit_uses }, + { "ae_l16.xc", ICLASS_AE_L16_XC, + 0, + Opcode_ae_l16_xc_encode_fns, 1, Opcode_ae_l16_xc_funcUnit_uses }, + { "ae_l16.xc1", ICLASS_AE_L16_XC1, + 0, + Opcode_ae_l16_xc1_encode_fns, 1, Opcode_ae_l16_xc1_funcUnit_uses }, + { "ae_l16.i", ICLASS_AE_L16_I, + 0, + Opcode_ae_l16_i_encode_fns, 1, Opcode_ae_l16_i_funcUnit_uses }, + { "ae_l16.ip", ICLASS_AE_L16_IP, + 0, + Opcode_ae_l16_ip_encode_fns, 1, Opcode_ae_l16_ip_funcUnit_uses }, + { "ae_l16.x", ICLASS_AE_L16_X, + 0, + Opcode_ae_l16_x_encode_fns, 1, Opcode_ae_l16_x_funcUnit_uses }, + { "ae_l16.xp", ICLASS_AE_L16_XP, + 0, + Opcode_ae_l16_xp_encode_fns, 1, Opcode_ae_l16_xp_funcUnit_uses }, + { "ae_l8.xc", ICLASS_AE_L8_XC, + 0, + Opcode_ae_l8_xc_encode_fns, 1, Opcode_ae_l8_xc_funcUnit_uses }, + { "ae_l8.xc1", ICLASS_AE_L8_XC1, + 0, + Opcode_ae_l8_xc1_encode_fns, 1, Opcode_ae_l8_xc1_funcUnit_uses }, + { "ae_l8.i", ICLASS_AE_L8_I, + 0, + Opcode_ae_l8_i_encode_fns, 1, Opcode_ae_l8_i_funcUnit_uses }, + { "ae_l8.ip", ICLASS_AE_L8_IP, + 0, + Opcode_ae_l8_ip_encode_fns, 1, Opcode_ae_l8_ip_funcUnit_uses }, + { "ae_l8.x", ICLASS_AE_L8_X, + 0, + Opcode_ae_l8_x_encode_fns, 1, Opcode_ae_l8_x_funcUnit_uses }, + { "ae_l8.xp", ICLASS_AE_L8_XP, + 0, + Opcode_ae_l8_xp_encode_fns, 1, Opcode_ae_l8_xp_funcUnit_uses }, + { "ae_l32f24.xc", ICLASS_AE_L32F24_XC, + 0, + Opcode_ae_l32f24_xc_encode_fns, 1, Opcode_ae_l32f24_xc_funcUnit_uses }, + { "ae_l32f24.xc1", ICLASS_AE_L32F24_XC1, + 0, + Opcode_ae_l32f24_xc1_encode_fns, 1, Opcode_ae_l32f24_xc1_funcUnit_uses }, + { "ae_l32f24.i", ICLASS_AE_L32F24_I, + 0, + Opcode_ae_l32f24_i_encode_fns, 1, Opcode_ae_l32f24_i_funcUnit_uses }, + { "ae_l32f24.ip", ICLASS_AE_L32F24_IP, + 0, + Opcode_ae_l32f24_ip_encode_fns, 1, Opcode_ae_l32f24_ip_funcUnit_uses }, + { "ae_l32f24.x", ICLASS_AE_L32F24_X, + 0, + Opcode_ae_l32f24_x_encode_fns, 1, Opcode_ae_l32f24_x_funcUnit_uses }, + { "ae_l32f24.xp", ICLASS_AE_L32F24_XP, + 0, + Opcode_ae_l32f24_xp_encode_fns, 1, Opcode_ae_l32f24_xp_funcUnit_uses }, + { "ae_l32.xc", ICLASS_AE_L32_XC, + 0, + Opcode_ae_l32_xc_encode_fns, 1, Opcode_ae_l32_xc_funcUnit_uses }, + { "ae_l32.xc1", ICLASS_AE_L32_XC1, + 0, + Opcode_ae_l32_xc1_encode_fns, 1, Opcode_ae_l32_xc1_funcUnit_uses }, + { "ae_l32.i", ICLASS_AE_L32_I, + 0, + Opcode_ae_l32_i_encode_fns, 1, Opcode_ae_l32_i_funcUnit_uses }, + { "ae_l32.ip", ICLASS_AE_L32_IP, + 0, + Opcode_ae_l32_ip_encode_fns, 1, Opcode_ae_l32_ip_funcUnit_uses }, + { "ae_l32.x", ICLASS_AE_L32_X, + 0, + Opcode_ae_l32_x_encode_fns, 1, Opcode_ae_l32_x_funcUnit_uses }, + { "ae_l32.xp", ICLASS_AE_L32_XP, + 0, + Opcode_ae_l32_xp_encode_fns, 1, Opcode_ae_l32_xp_funcUnit_uses }, + { "ae_l32m.xc", ICLASS_AE_L32M_XC, + 0, + Opcode_ae_l32m_xc_encode_fns, 1, Opcode_ae_l32m_xc_funcUnit_uses }, + { "ae_l32m.i", ICLASS_AE_L32M_I, + 0, + Opcode_ae_l32m_i_encode_fns, 1, Opcode_ae_l32m_i_funcUnit_uses }, + { "ae_l32m.iu", ICLASS_AE_L32M_IU, + 0, + Opcode_ae_l32m_iu_encode_fns, 1, Opcode_ae_l32m_iu_funcUnit_uses }, + { "ae_l32m.x", ICLASS_AE_L32M_X, + 0, + Opcode_ae_l32m_x_encode_fns, 1, Opcode_ae_l32m_x_funcUnit_uses }, + { "ae_l32m.xu", ICLASS_AE_L32M_XU, + 0, + Opcode_ae_l32m_xu_encode_fns, 1, Opcode_ae_l32m_xu_funcUnit_uses }, + { "ae_l16x2m.xc", ICLASS_AE_L16X2M_XC, + 0, + Opcode_ae_l16x2m_xc_encode_fns, 1, Opcode_ae_l16x2m_xc_funcUnit_uses }, + { "ae_l16x2m.xc1", ICLASS_AE_L16X2M_XC1, + 0, + Opcode_ae_l16x2m_xc1_encode_fns, 1, Opcode_ae_l16x2m_xc1_funcUnit_uses }, + { "ae_l16x2m.i", ICLASS_AE_L16X2M_I, + 0, + Opcode_ae_l16x2m_i_encode_fns, 1, Opcode_ae_l16x2m_i_funcUnit_uses }, + { "ae_l16x2m.iu", ICLASS_AE_L16X2M_IU, + 0, + Opcode_ae_l16x2m_iu_encode_fns, 1, Opcode_ae_l16x2m_iu_funcUnit_uses }, + { "ae_l16x2m.x", ICLASS_AE_L16X2M_X, + 0, + Opcode_ae_l16x2m_x_encode_fns, 1, Opcode_ae_l16x2m_x_funcUnit_uses }, + { "ae_l16x2m.xu", ICLASS_AE_L16X2M_XU, + 0, + Opcode_ae_l16x2m_xu_encode_fns, 1, Opcode_ae_l16x2m_xu_funcUnit_uses }, + { "ae_l32x2f24.xc", ICLASS_AE_L32X2F24_XC, + 0, + Opcode_ae_l32x2f24_xc_encode_fns, 1, Opcode_ae_l32x2f24_xc_funcUnit_uses }, + { "ae_l32x2f24.xc1", ICLASS_AE_L32X2F24_XC1, + 0, + Opcode_ae_l32x2f24_xc1_encode_fns, 1, Opcode_ae_l32x2f24_xc1_funcUnit_uses }, + { "ae_l32x2f24.i", ICLASS_AE_L32X2F24_I, + 0, + Opcode_ae_l32x2f24_i_encode_fns, 1, Opcode_ae_l32x2f24_i_funcUnit_uses }, + { "ae_l32x2f24.ip", ICLASS_AE_L32X2F24_IP, + 0, + Opcode_ae_l32x2f24_ip_encode_fns, 1, Opcode_ae_l32x2f24_ip_funcUnit_uses }, + { "ae_l32x2f24.rip", ICLASS_AE_L32X2F24_RIP, + 0, + Opcode_ae_l32x2f24_rip_encode_fns, 1, Opcode_ae_l32x2f24_rip_funcUnit_uses }, + { "ae_l32x2f24.ri", ICLASS_AE_L32X2F24_RI, + 0, + Opcode_ae_l32x2f24_ri_encode_fns, 1, Opcode_ae_l32x2f24_ri_funcUnit_uses }, + { "ae_l32x2f24.ric", ICLASS_AE_L32X2F24_RIC, + 0, + Opcode_ae_l32x2f24_ric_encode_fns, 1, Opcode_ae_l32x2f24_ric_funcUnit_uses }, + { "ae_l32x2f24.ric1", ICLASS_AE_L32X2F24_RIC1, + 0, + Opcode_ae_l32x2f24_ric1_encode_fns, 1, Opcode_ae_l32x2f24_ric1_funcUnit_uses }, + { "ae_l32x2f24.x", ICLASS_AE_L32X2F24_X, + 0, + Opcode_ae_l32x2f24_x_encode_fns, 1, Opcode_ae_l32x2f24_x_funcUnit_uses }, + { "ae_l32x2f24.xp", ICLASS_AE_L32X2F24_XP, + 0, + Opcode_ae_l32x2f24_xp_encode_fns, 1, Opcode_ae_l32x2f24_xp_funcUnit_uses }, + { "ae_l32x2.xc", ICLASS_AE_L32X2_XC, + 0, + Opcode_ae_l32x2_xc_encode_fns, 1, Opcode_ae_l32x2_xc_funcUnit_uses }, + { "ae_l32x2.xc1", ICLASS_AE_L32X2_XC1, + 0, + Opcode_ae_l32x2_xc1_encode_fns, 1, Opcode_ae_l32x2_xc1_funcUnit_uses }, + { "ae_l32x2.i", ICLASS_AE_L32X2_I, + 0, + Opcode_ae_l32x2_i_encode_fns, 1, Opcode_ae_l32x2_i_funcUnit_uses }, + { "ae_l32x2.ip", ICLASS_AE_L32X2_IP, + 0, + Opcode_ae_l32x2_ip_encode_fns, 1, Opcode_ae_l32x2_ip_funcUnit_uses }, + { "ae_l32x2.ric", ICLASS_AE_L32X2_RIC, + 0, + Opcode_ae_l32x2_ric_encode_fns, 1, Opcode_ae_l32x2_ric_funcUnit_uses }, + { "ae_l32x2.ric1", ICLASS_AE_L32X2_RIC1, + 0, + Opcode_ae_l32x2_ric1_encode_fns, 1, Opcode_ae_l32x2_ric1_funcUnit_uses }, + { "ae_l32x2.x", ICLASS_AE_L32X2_X, + 0, + Opcode_ae_l32x2_x_encode_fns, 1, Opcode_ae_l32x2_x_funcUnit_uses }, + { "ae_l32x2.xp", ICLASS_AE_L32X2_XP, + 0, + Opcode_ae_l32x2_xp_encode_fns, 1, Opcode_ae_l32x2_xp_funcUnit_uses }, + { "ae_l16x4.xc", ICLASS_AE_L16X4_XC, + 0, + Opcode_ae_l16x4_xc_encode_fns, 1, Opcode_ae_l16x4_xc_funcUnit_uses }, + { "ae_l16x4.xc1", ICLASS_AE_L16X4_XC1, + 0, + Opcode_ae_l16x4_xc1_encode_fns, 1, Opcode_ae_l16x4_xc1_funcUnit_uses }, + { "ae_l16x4.i", ICLASS_AE_L16X4_I, + 0, + Opcode_ae_l16x4_i_encode_fns, 1, Opcode_ae_l16x4_i_funcUnit_uses }, + { "ae_l16x4.ip", ICLASS_AE_L16X4_IP, + 0, + Opcode_ae_l16x4_ip_encode_fns, 1, Opcode_ae_l16x4_ip_funcUnit_uses }, + { "ae_l16x4.x", ICLASS_AE_L16X4_X, + 0, + Opcode_ae_l16x4_x_encode_fns, 1, Opcode_ae_l16x4_x_funcUnit_uses }, + { "ae_l16x4.xp", ICLASS_AE_L16X4_XP, + 0, + Opcode_ae_l16x4_xp_encode_fns, 1, Opcode_ae_l16x4_xp_funcUnit_uses }, + { "ae_l8x8.xc", ICLASS_AE_L8X8_XC, + 0, + Opcode_ae_l8x8_xc_encode_fns, 1, Opcode_ae_l8x8_xc_funcUnit_uses }, + { "ae_l8x8.xc1", ICLASS_AE_L8X8_XC1, + 0, + Opcode_ae_l8x8_xc1_encode_fns, 1, Opcode_ae_l8x8_xc1_funcUnit_uses }, + { "ae_l8x8.i", ICLASS_AE_L8X8_I, + 0, + Opcode_ae_l8x8_i_encode_fns, 1, Opcode_ae_l8x8_i_funcUnit_uses }, + { "ae_l8x8.ip", ICLASS_AE_L8X8_IP, + 0, + Opcode_ae_l8x8_ip_encode_fns, 1, Opcode_ae_l8x8_ip_funcUnit_uses }, + { "ae_l8x8.x", ICLASS_AE_L8X8_X, + 0, + Opcode_ae_l8x8_x_encode_fns, 1, Opcode_ae_l8x8_x_funcUnit_uses }, + { "ae_l8x8.xp", ICLASS_AE_L8X8_XP, + 0, + Opcode_ae_l8x8_xp_encode_fns, 1, Opcode_ae_l8x8_xp_funcUnit_uses }, + { "ae_l64.xc", ICLASS_AE_L64_XC, + 0, + Opcode_ae_l64_xc_encode_fns, 1, Opcode_ae_l64_xc_funcUnit_uses }, + { "ae_l64.xc1", ICLASS_AE_L64_XC1, + 0, + Opcode_ae_l64_xc1_encode_fns, 1, Opcode_ae_l64_xc1_funcUnit_uses }, + { "ae_l64.i", ICLASS_AE_L64_I, + 0, + Opcode_ae_l64_i_encode_fns, 1, Opcode_ae_l64_i_funcUnit_uses }, + { "ae_l64.ip", ICLASS_AE_L64_IP, + 0, + Opcode_ae_l64_ip_encode_fns, 1, Opcode_ae_l64_ip_funcUnit_uses }, + { "ae_l64.x", ICLASS_AE_L64_X, + 0, + Opcode_ae_l64_x_encode_fns, 1, Opcode_ae_l64_x_funcUnit_uses }, + { "ae_l64.xp", ICLASS_AE_L64_XP, + 0, + Opcode_ae_l64_xp_encode_fns, 1, Opcode_ae_l64_xp_funcUnit_uses }, + { "ae_s16x2m.xc", ICLASS_AE_S16X2M_XC, + 0, + Opcode_ae_s16x2m_xc_encode_fns, 1, Opcode_ae_s16x2m_xc_funcUnit_uses }, + { "ae_s16x2m.xc1", ICLASS_AE_S16X2M_XC1, + 0, + Opcode_ae_s16x2m_xc1_encode_fns, 1, Opcode_ae_s16x2m_xc1_funcUnit_uses }, + { "ae_s16x2m.i", ICLASS_AE_S16X2M_I, + 0, + Opcode_ae_s16x2m_i_encode_fns, 1, Opcode_ae_s16x2m_i_funcUnit_uses }, + { "ae_s16x2m.iu", ICLASS_AE_S16X2M_IU, + 0, + Opcode_ae_s16x2m_iu_encode_fns, 1, Opcode_ae_s16x2m_iu_funcUnit_uses }, + { "ae_s16x2m.x", ICLASS_AE_S16X2M_X, + 0, + Opcode_ae_s16x2m_x_encode_fns, 1, Opcode_ae_s16x2m_x_funcUnit_uses }, + { "ae_s16x2m.xu", ICLASS_AE_S16X2M_XU, + 0, + Opcode_ae_s16x2m_xu_encode_fns, 1, Opcode_ae_s16x2m_xu_funcUnit_uses }, + { "ae_s32x2f24.xc", ICLASS_AE_S32X2F24_XC, + 0, + Opcode_ae_s32x2f24_xc_encode_fns, 1, Opcode_ae_s32x2f24_xc_funcUnit_uses }, + { "ae_s32x2f24.xc1", ICLASS_AE_S32X2F24_XC1, + 0, + Opcode_ae_s32x2f24_xc1_encode_fns, 1, Opcode_ae_s32x2f24_xc1_funcUnit_uses }, + { "ae_s32x2f24.i", ICLASS_AE_S32X2F24_I, + 0, + Opcode_ae_s32x2f24_i_encode_fns, 1, Opcode_ae_s32x2f24_i_funcUnit_uses }, + { "ae_s32x2f24.ip", ICLASS_AE_S32X2F24_IP, + 0, + Opcode_ae_s32x2f24_ip_encode_fns, 1, Opcode_ae_s32x2f24_ip_funcUnit_uses }, + { "ae_s32x2f24.rip", ICLASS_AE_S32X2F24_RIP, + 0, + Opcode_ae_s32x2f24_rip_encode_fns, 1, Opcode_ae_s32x2f24_rip_funcUnit_uses }, + { "ae_s32x2f24.ric", ICLASS_AE_S32X2F24_RIC, + 0, + Opcode_ae_s32x2f24_ric_encode_fns, 1, Opcode_ae_s32x2f24_ric_funcUnit_uses }, + { "ae_s32x2f24.ric1", ICLASS_AE_S32X2F24_RIC1, + 0, + Opcode_ae_s32x2f24_ric1_encode_fns, 1, Opcode_ae_s32x2f24_ric1_funcUnit_uses }, + { "ae_s32x2f24.x", ICLASS_AE_S32X2F24_X, + 0, + Opcode_ae_s32x2f24_x_encode_fns, 1, Opcode_ae_s32x2f24_x_funcUnit_uses }, + { "ae_s32x2f24.xp", ICLASS_AE_S32X2F24_XP, + 0, + Opcode_ae_s32x2f24_xp_encode_fns, 1, Opcode_ae_s32x2f24_xp_funcUnit_uses }, + { "ae_s32x2.xc", ICLASS_AE_S32X2_XC, + 0, + Opcode_ae_s32x2_xc_encode_fns, 1, Opcode_ae_s32x2_xc_funcUnit_uses }, + { "ae_s32x2.xc1", ICLASS_AE_S32X2_XC1, + 0, + Opcode_ae_s32x2_xc1_encode_fns, 1, Opcode_ae_s32x2_xc1_funcUnit_uses }, + { "ae_s32x2.i", ICLASS_AE_S32X2_I, + 0, + Opcode_ae_s32x2_i_encode_fns, 1, Opcode_ae_s32x2_i_funcUnit_uses }, + { "ae_s32x2.ip", ICLASS_AE_S32X2_IP, + 0, + Opcode_ae_s32x2_ip_encode_fns, 1, Opcode_ae_s32x2_ip_funcUnit_uses }, + { "ae_s32x2.ric", ICLASS_AE_S32X2_RIC, + 0, + Opcode_ae_s32x2_ric_encode_fns, 1, Opcode_ae_s32x2_ric_funcUnit_uses }, + { "ae_s32x2.ric1", ICLASS_AE_S32X2_RIC1, + 0, + Opcode_ae_s32x2_ric1_encode_fns, 1, Opcode_ae_s32x2_ric1_funcUnit_uses }, + { "ae_s32x2.x", ICLASS_AE_S32X2_X, + 0, + Opcode_ae_s32x2_x_encode_fns, 1, Opcode_ae_s32x2_x_funcUnit_uses }, + { "ae_s32x2.xp", ICLASS_AE_S32X2_XP, + 0, + Opcode_ae_s32x2_xp_encode_fns, 1, Opcode_ae_s32x2_xp_funcUnit_uses }, + { "ae_s32x2rng.i", ICLASS_AE_S32X2RNG_I, + 0, + Opcode_ae_s32x2rng_i_encode_fns, 1, Opcode_ae_s32x2rng_i_funcUnit_uses }, + { "ae_s32x2rng.ip", ICLASS_AE_S32X2RNG_IP, + 0, + Opcode_ae_s32x2rng_ip_encode_fns, 1, Opcode_ae_s32x2rng_ip_funcUnit_uses }, + { "ae_s32x2rng.x", ICLASS_AE_S32X2RNG_X, + 0, + Opcode_ae_s32x2rng_x_encode_fns, 1, Opcode_ae_s32x2rng_x_funcUnit_uses }, + { "ae_s32x2rng.xp", ICLASS_AE_S32X2RNG_XP, + 0, + Opcode_ae_s32x2rng_xp_encode_fns, 1, Opcode_ae_s32x2rng_xp_funcUnit_uses }, + { "ae_s16x4.xc", ICLASS_AE_S16X4_XC, + 0, + Opcode_ae_s16x4_xc_encode_fns, 1, Opcode_ae_s16x4_xc_funcUnit_uses }, + { "ae_s16x4.xc1", ICLASS_AE_S16X4_XC1, + 0, + Opcode_ae_s16x4_xc1_encode_fns, 1, Opcode_ae_s16x4_xc1_funcUnit_uses }, + { "ae_s16x4.i", ICLASS_AE_S16X4_I, + 0, + Opcode_ae_s16x4_i_encode_fns, 1, Opcode_ae_s16x4_i_funcUnit_uses }, + { "ae_s16x4.ip", ICLASS_AE_S16X4_IP, + 0, + Opcode_ae_s16x4_ip_encode_fns, 1, Opcode_ae_s16x4_ip_funcUnit_uses }, + { "ae_s16x4.x", ICLASS_AE_S16X4_X, + 0, + Opcode_ae_s16x4_x_encode_fns, 1, Opcode_ae_s16x4_x_funcUnit_uses }, + { "ae_s16x4.xp", ICLASS_AE_S16X4_XP, + 0, + Opcode_ae_s16x4_xp_encode_fns, 1, Opcode_ae_s16x4_xp_funcUnit_uses }, + { "ae_s8x8.xc", ICLASS_AE_S8X8_XC, + 0, + Opcode_ae_s8x8_xc_encode_fns, 1, Opcode_ae_s8x8_xc_funcUnit_uses }, + { "ae_s8x8.xc1", ICLASS_AE_S8X8_XC1, + 0, + Opcode_ae_s8x8_xc1_encode_fns, 1, Opcode_ae_s8x8_xc1_funcUnit_uses }, + { "ae_s8x8.i", ICLASS_AE_S8X8_I, + 0, + Opcode_ae_s8x8_i_encode_fns, 1, Opcode_ae_s8x8_i_funcUnit_uses }, + { "ae_s8x8.ip", ICLASS_AE_S8X8_IP, + 0, + Opcode_ae_s8x8_ip_encode_fns, 1, Opcode_ae_s8x8_ip_funcUnit_uses }, + { "ae_s8x8.x", ICLASS_AE_S8X8_X, + 0, + Opcode_ae_s8x8_x_encode_fns, 1, Opcode_ae_s8x8_x_funcUnit_uses }, + { "ae_s8x8.xp", ICLASS_AE_S8X8_XP, + 0, + Opcode_ae_s8x8_xp_encode_fns, 1, Opcode_ae_s8x8_xp_funcUnit_uses }, + { "ae_s16m.l.xc", ICLASS_AE_S16M_L_XC, + 0, + Opcode_ae_s16m_l_xc_encode_fns, 1, Opcode_ae_s16m_l_xc_funcUnit_uses }, + { "ae_s16m.l.xc1", ICLASS_AE_S16M_L_XC1, + 0, + Opcode_ae_s16m_l_xc1_encode_fns, 1, Opcode_ae_s16m_l_xc1_funcUnit_uses }, + { "ae_s16m.l.i", ICLASS_AE_S16M_L_I, + 0, + Opcode_ae_s16m_l_i_encode_fns, 1, Opcode_ae_s16m_l_i_funcUnit_uses }, + { "ae_s16m.l.iu", ICLASS_AE_S16M_L_IU, + 0, + Opcode_ae_s16m_l_iu_encode_fns, 1, Opcode_ae_s16m_l_iu_funcUnit_uses }, + { "ae_s16m.l.x", ICLASS_AE_S16M_L_X, + 0, + Opcode_ae_s16m_l_x_encode_fns, 1, Opcode_ae_s16m_l_x_funcUnit_uses }, + { "ae_s16m.l.xu", ICLASS_AE_S16M_L_XU, + 0, + Opcode_ae_s16m_l_xu_encode_fns, 1, Opcode_ae_s16m_l_xu_funcUnit_uses }, + { "ae_s32f24.l.xc", ICLASS_AE_S32F24_L_XC, + 0, + Opcode_ae_s32f24_l_xc_encode_fns, 1, Opcode_ae_s32f24_l_xc_funcUnit_uses }, + { "ae_s32f24.l.xc1", ICLASS_AE_S32F24_L_XC1, + 0, + Opcode_ae_s32f24_l_xc1_encode_fns, 1, Opcode_ae_s32f24_l_xc1_funcUnit_uses }, + { "ae_s32f24.l.i", ICLASS_AE_S32F24_L_I, + 0, + Opcode_ae_s32f24_l_i_encode_fns, 1, Opcode_ae_s32f24_l_i_funcUnit_uses }, + { "ae_s32f24.l.ip", ICLASS_AE_S32F24_L_IP, + 0, + Opcode_ae_s32f24_l_ip_encode_fns, 1, Opcode_ae_s32f24_l_ip_funcUnit_uses }, + { "ae_s32f24.l.x", ICLASS_AE_S32F24_L_X, + 0, + Opcode_ae_s32f24_l_x_encode_fns, 1, Opcode_ae_s32f24_l_x_funcUnit_uses }, + { "ae_s32f24.l.xp", ICLASS_AE_S32F24_L_XP, + 0, + Opcode_ae_s32f24_l_xp_encode_fns, 1, Opcode_ae_s32f24_l_xp_funcUnit_uses }, + { "ae_s32.l.xc", ICLASS_AE_S32_L_XC, + 0, + Opcode_ae_s32_l_xc_encode_fns, 1, Opcode_ae_s32_l_xc_funcUnit_uses }, + { "ae_s32.l.xc1", ICLASS_AE_S32_L_XC1, + 0, + Opcode_ae_s32_l_xc1_encode_fns, 1, Opcode_ae_s32_l_xc1_funcUnit_uses }, + { "ae_s32.l.i", ICLASS_AE_S32_L_I, + 0, + Opcode_ae_s32_l_i_encode_fns, 1, Opcode_ae_s32_l_i_funcUnit_uses }, + { "ae_s32.l.ip", ICLASS_AE_S32_L_IP, + 0, + Opcode_ae_s32_l_ip_encode_fns, 1, Opcode_ae_s32_l_ip_funcUnit_uses }, + { "ae_s32.l.x", ICLASS_AE_S32_L_X, + 0, + Opcode_ae_s32_l_x_encode_fns, 1, Opcode_ae_s32_l_x_funcUnit_uses }, + { "ae_s32.l.xp", ICLASS_AE_S32_L_XP, + 0, + Opcode_ae_s32_l_xp_encode_fns, 1, Opcode_ae_s32_l_xp_funcUnit_uses }, + { "ae_s32.h.xc", ICLASS_AE_S32_H_XC, + 0, + Opcode_ae_s32_h_xc_encode_fns, 1, Opcode_ae_s32_h_xc_funcUnit_uses }, + { "ae_s32.h.xc1", ICLASS_AE_S32_H_XC1, + 0, + Opcode_ae_s32_h_xc1_encode_fns, 1, Opcode_ae_s32_h_xc1_funcUnit_uses }, + { "ae_s32.h.i", ICLASS_AE_S32_H_I, + 0, + Opcode_ae_s32_h_i_encode_fns, 1, Opcode_ae_s32_h_i_funcUnit_uses }, + { "ae_s32.h.ip", ICLASS_AE_S32_H_IP, + 0, + Opcode_ae_s32_h_ip_encode_fns, 1, Opcode_ae_s32_h_ip_funcUnit_uses }, + { "ae_s32.h.x", ICLASS_AE_S32_H_X, + 0, + Opcode_ae_s32_h_x_encode_fns, 1, Opcode_ae_s32_h_x_funcUnit_uses }, + { "ae_s32.h.xp", ICLASS_AE_S32_H_XP, + 0, + Opcode_ae_s32_h_xp_encode_fns, 1, Opcode_ae_s32_h_xp_funcUnit_uses }, + { "ae_s16.0.xc", ICLASS_AE_S16_0_XC, + 0, + Opcode_ae_s16_0_xc_encode_fns, 1, Opcode_ae_s16_0_xc_funcUnit_uses }, + { "ae_s16.0.xc1", ICLASS_AE_S16_0_XC1, + 0, + Opcode_ae_s16_0_xc1_encode_fns, 1, Opcode_ae_s16_0_xc1_funcUnit_uses }, + { "ae_s16.0.i", ICLASS_AE_S16_0_I, + 0, + Opcode_ae_s16_0_i_encode_fns, 1, Opcode_ae_s16_0_i_funcUnit_uses }, + { "ae_s16.0.ip", ICLASS_AE_S16_0_IP, + 0, + Opcode_ae_s16_0_ip_encode_fns, 1, Opcode_ae_s16_0_ip_funcUnit_uses }, + { "ae_s16.0.x", ICLASS_AE_S16_0_X, + 0, + Opcode_ae_s16_0_x_encode_fns, 1, Opcode_ae_s16_0_x_funcUnit_uses }, + { "ae_s16.0.xp", ICLASS_AE_S16_0_XP, + 0, + Opcode_ae_s16_0_xp_encode_fns, 1, Opcode_ae_s16_0_xp_funcUnit_uses }, + { "ae_s8.0.xc", ICLASS_AE_S8_0_XC, + 0, + Opcode_ae_s8_0_xc_encode_fns, 1, Opcode_ae_s8_0_xc_funcUnit_uses }, + { "ae_s8.0.xc1", ICLASS_AE_S8_0_XC1, + 0, + Opcode_ae_s8_0_xc1_encode_fns, 1, Opcode_ae_s8_0_xc1_funcUnit_uses }, + { "ae_s8.0.i", ICLASS_AE_S8_0_I, + 0, + Opcode_ae_s8_0_i_encode_fns, 1, Opcode_ae_s8_0_i_funcUnit_uses }, + { "ae_s8.0.ip", ICLASS_AE_S8_0_IP, + 0, + Opcode_ae_s8_0_ip_encode_fns, 1, Opcode_ae_s8_0_ip_funcUnit_uses }, + { "ae_s8.0.x", ICLASS_AE_S8_0_X, + 0, + Opcode_ae_s8_0_x_encode_fns, 1, Opcode_ae_s8_0_x_funcUnit_uses }, + { "ae_s8.0.xp", ICLASS_AE_S8_0_XP, + 0, + Opcode_ae_s8_0_xp_encode_fns, 1, Opcode_ae_s8_0_xp_funcUnit_uses }, + { "ae_s64.xc", ICLASS_AE_S64_XC, + 0, + Opcode_ae_s64_xc_encode_fns, 1, Opcode_ae_s64_xc_funcUnit_uses }, + { "ae_s64.xc1", ICLASS_AE_S64_XC1, + 0, + Opcode_ae_s64_xc1_encode_fns, 1, Opcode_ae_s64_xc1_funcUnit_uses }, + { "ae_s64.i", ICLASS_AE_S64_I, + 0, + Opcode_ae_s64_i_encode_fns, 1, Opcode_ae_s64_i_funcUnit_uses }, + { "ae_s64.ip", ICLASS_AE_S64_IP, + 0, + Opcode_ae_s64_ip_encode_fns, 1, Opcode_ae_s64_ip_funcUnit_uses }, + { "ae_s64.x", ICLASS_AE_S64_X, + 0, + Opcode_ae_s64_x_encode_fns, 1, Opcode_ae_s64_x_funcUnit_uses }, + { "ae_s64.xp", ICLASS_AE_S64_XP, + 0, + Opcode_ae_s64_xp_encode_fns, 1, Opcode_ae_s64_xp_funcUnit_uses }, + { "ae_s32m.xc", ICLASS_AE_S32M_XC, + 0, + Opcode_ae_s32m_xc_encode_fns, 1, Opcode_ae_s32m_xc_funcUnit_uses }, + { "ae_s32m.i", ICLASS_AE_S32M_I, + 0, + Opcode_ae_s32m_i_encode_fns, 1, Opcode_ae_s32m_i_funcUnit_uses }, + { "ae_s32m.iu", ICLASS_AE_S32M_IU, + 0, + Opcode_ae_s32m_iu_encode_fns, 1, Opcode_ae_s32m_iu_funcUnit_uses }, + { "ae_s32m.x", ICLASS_AE_S32M_X, + 0, + Opcode_ae_s32m_x_encode_fns, 1, Opcode_ae_s32m_x_funcUnit_uses }, + { "ae_s32m.xu", ICLASS_AE_S32M_XU, + 0, + Opcode_ae_s32m_xu_encode_fns, 1, Opcode_ae_s32m_xu_funcUnit_uses }, + { "ae_l32x2.xc2", ICLASS_AE_L32X2_XC2, + 0, + Opcode_ae_l32x2_xc2_encode_fns, 1, Opcode_ae_l32x2_xc2_funcUnit_uses }, + { "ae_l16x4.xc2", ICLASS_AE_L16X4_XC2, + 0, + Opcode_ae_l16x4_xc2_encode_fns, 1, Opcode_ae_l16x4_xc2_funcUnit_uses }, + { "ae_l8x8.xc2", ICLASS_AE_L8X8_XC2, + 0, + Opcode_ae_l8x8_xc2_encode_fns, 1, Opcode_ae_l8x8_xc2_funcUnit_uses }, + { "ae_l64.xc2", ICLASS_AE_L64_XC2, + 0, + Opcode_ae_l64_xc2_encode_fns, 1, Opcode_ae_l64_xc2_funcUnit_uses }, + { "ae_s32x2.xc2", ICLASS_AE_S32X2_XC2, + 0, + Opcode_ae_s32x2_xc2_encode_fns, 1, Opcode_ae_s32x2_xc2_funcUnit_uses }, + { "ae_s16x4.xc2", ICLASS_AE_S16X4_XC2, + 0, + Opcode_ae_s16x4_xc2_encode_fns, 1, Opcode_ae_s16x4_xc2_funcUnit_uses }, + { "ae_s8x8.xc2", ICLASS_AE_S8X8_XC2, + 0, + Opcode_ae_s8x8_xc2_encode_fns, 1, Opcode_ae_s8x8_xc2_funcUnit_uses }, + { "ae_s64.xc2", ICLASS_AE_S64_XC2, + 0, + Opcode_ae_s64_xc2_encode_fns, 1, Opcode_ae_s64_xc2_funcUnit_uses }, + { "ae_s16x4rng.i", ICLASS_AE_S16X4RNG_I, + 0, + Opcode_ae_s16x4rng_i_encode_fns, 1, Opcode_ae_s16x4rng_i_funcUnit_uses }, + { "ae_s16x4rng.ip", ICLASS_AE_S16X4RNG_IP, + 0, + Opcode_ae_s16x4rng_ip_encode_fns, 1, Opcode_ae_s16x4rng_ip_funcUnit_uses }, + { "ae_s16x4rng.x", ICLASS_AE_S16X4RNG_X, + 0, + Opcode_ae_s16x4rng_x_encode_fns, 1, Opcode_ae_s16x4rng_x_funcUnit_uses }, + { "ae_s16x4rng.xp", ICLASS_AE_S16X4RNG_XP, + 0, + Opcode_ae_s16x4rng_xp_encode_fns, 1, Opcode_ae_s16x4rng_xp_funcUnit_uses }, + { "ae_l32x2x2.xc", ICLASS_AE_L32X2X2_XC, + 0, + Opcode_ae_l32x2x2_xc_encode_fns, 1, Opcode_ae_l32x2x2_xc_funcUnit_uses }, + { "ae_l32x2x2.xc1", ICLASS_AE_L32X2X2_XC1, + 0, + Opcode_ae_l32x2x2_xc1_encode_fns, 1, Opcode_ae_l32x2x2_xc1_funcUnit_uses }, + { "ae_l32x2x2.i", ICLASS_AE_L32X2X2_I, + 0, + Opcode_ae_l32x2x2_i_encode_fns, 1, Opcode_ae_l32x2x2_i_funcUnit_uses }, + { "ae_l32x2x2.ip", ICLASS_AE_L32X2X2_IP, + 0, + Opcode_ae_l32x2x2_ip_encode_fns, 1, Opcode_ae_l32x2x2_ip_funcUnit_uses }, + { "ae_l32x2x2.x", ICLASS_AE_L32X2X2_X, + 0, + Opcode_ae_l32x2x2_x_encode_fns, 1, Opcode_ae_l32x2x2_x_funcUnit_uses }, + { "ae_l32x2x2.xp", ICLASS_AE_L32X2X2_XP, + 0, + Opcode_ae_l32x2x2_xp_encode_fns, 1, Opcode_ae_l32x2x2_xp_funcUnit_uses }, + { "ae_l16x4x2.xc", ICLASS_AE_L16X4X2_XC, + 0, + Opcode_ae_l16x4x2_xc_encode_fns, 1, Opcode_ae_l16x4x2_xc_funcUnit_uses }, + { "ae_l16x4x2.xc1", ICLASS_AE_L16X4X2_XC1, + 0, + Opcode_ae_l16x4x2_xc1_encode_fns, 1, Opcode_ae_l16x4x2_xc1_funcUnit_uses }, + { "ae_l16x4x2.i", ICLASS_AE_L16X4X2_I, + 0, + Opcode_ae_l16x4x2_i_encode_fns, 1, Opcode_ae_l16x4x2_i_funcUnit_uses }, + { "ae_l16x4x2.ip", ICLASS_AE_L16X4X2_IP, + 0, + Opcode_ae_l16x4x2_ip_encode_fns, 1, Opcode_ae_l16x4x2_ip_funcUnit_uses }, + { "ae_l16x4x2.x", ICLASS_AE_L16X4X2_X, + 0, + Opcode_ae_l16x4x2_x_encode_fns, 1, Opcode_ae_l16x4x2_x_funcUnit_uses }, + { "ae_l16x4x2.xp", ICLASS_AE_L16X4X2_XP, + 0, + Opcode_ae_l16x4x2_xp_encode_fns, 1, Opcode_ae_l16x4x2_xp_funcUnit_uses }, + { "ae_l8x8x2.xc", ICLASS_AE_L8X8X2_XC, + 0, + Opcode_ae_l8x8x2_xc_encode_fns, 1, Opcode_ae_l8x8x2_xc_funcUnit_uses }, + { "ae_l8x8x2.xc1", ICLASS_AE_L8X8X2_XC1, + 0, + Opcode_ae_l8x8x2_xc1_encode_fns, 1, Opcode_ae_l8x8x2_xc1_funcUnit_uses }, + { "ae_l8x8x2.i", ICLASS_AE_L8X8X2_I, + 0, + Opcode_ae_l8x8x2_i_encode_fns, 1, Opcode_ae_l8x8x2_i_funcUnit_uses }, + { "ae_l8x8x2.ip", ICLASS_AE_L8X8X2_IP, + 0, + Opcode_ae_l8x8x2_ip_encode_fns, 1, Opcode_ae_l8x8x2_ip_funcUnit_uses }, + { "ae_l8x8x2.x", ICLASS_AE_L8X8X2_X, + 0, + Opcode_ae_l8x8x2_x_encode_fns, 1, Opcode_ae_l8x8x2_x_funcUnit_uses }, + { "ae_l8x8x2.xp", ICLASS_AE_L8X8X2_XP, + 0, + Opcode_ae_l8x8x2_xp_encode_fns, 1, Opcode_ae_l8x8x2_xp_funcUnit_uses }, + { "ae_l64x2.xc", ICLASS_AE_L64X2_XC, + 0, + Opcode_ae_l64x2_xc_encode_fns, 1, Opcode_ae_l64x2_xc_funcUnit_uses }, + { "ae_l64x2.xc1", ICLASS_AE_L64X2_XC1, + 0, + Opcode_ae_l64x2_xc1_encode_fns, 1, Opcode_ae_l64x2_xc1_funcUnit_uses }, + { "ae_l64x2.i", ICLASS_AE_L64X2_I, + 0, + Opcode_ae_l64x2_i_encode_fns, 1, Opcode_ae_l64x2_i_funcUnit_uses }, + { "ae_l64x2.ip", ICLASS_AE_L64X2_IP, + 0, + Opcode_ae_l64x2_ip_encode_fns, 1, Opcode_ae_l64x2_ip_funcUnit_uses }, + { "ae_l64x2.x", ICLASS_AE_L64X2_X, + 0, + Opcode_ae_l64x2_x_encode_fns, 1, Opcode_ae_l64x2_x_funcUnit_uses }, + { "ae_l64x2.xp", ICLASS_AE_L64X2_XP, + 0, + Opcode_ae_l64x2_xp_encode_fns, 1, Opcode_ae_l64x2_xp_funcUnit_uses }, + { "ae_s32x2x2.xc", ICLASS_AE_S32X2X2_XC, + 0, + Opcode_ae_s32x2x2_xc_encode_fns, 1, Opcode_ae_s32x2x2_xc_funcUnit_uses }, + { "ae_s32x2x2.xc1", ICLASS_AE_S32X2X2_XC1, + 0, + Opcode_ae_s32x2x2_xc1_encode_fns, 1, Opcode_ae_s32x2x2_xc1_funcUnit_uses }, + { "ae_s32x2x2.i", ICLASS_AE_S32X2X2_I, + 0, + Opcode_ae_s32x2x2_i_encode_fns, 1, Opcode_ae_s32x2x2_i_funcUnit_uses }, + { "ae_s32x2x2.ip", ICLASS_AE_S32X2X2_IP, + 0, + Opcode_ae_s32x2x2_ip_encode_fns, 1, Opcode_ae_s32x2x2_ip_funcUnit_uses }, + { "ae_s32x2x2.x", ICLASS_AE_S32X2X2_X, + 0, + Opcode_ae_s32x2x2_x_encode_fns, 1, Opcode_ae_s32x2x2_x_funcUnit_uses }, + { "ae_s32x2x2.xp", ICLASS_AE_S32X2X2_XP, + 0, + Opcode_ae_s32x2x2_xp_encode_fns, 1, Opcode_ae_s32x2x2_xp_funcUnit_uses }, + { "ae_s32x2x2rng.i", ICLASS_AE_S32X2X2RNG_I, + 0, + Opcode_ae_s32x2x2rng_i_encode_fns, 1, Opcode_ae_s32x2x2rng_i_funcUnit_uses }, + { "ae_s32x2x2rng.ip", ICLASS_AE_S32X2X2RNG_IP, + 0, + Opcode_ae_s32x2x2rng_ip_encode_fns, 1, Opcode_ae_s32x2x2rng_ip_funcUnit_uses }, + { "ae_s32x2x2rng.x", ICLASS_AE_S32X2X2RNG_X, + 0, + Opcode_ae_s32x2x2rng_x_encode_fns, 1, Opcode_ae_s32x2x2rng_x_funcUnit_uses }, + { "ae_s32x2x2rng.xp", ICLASS_AE_S32X2X2RNG_XP, + 0, + Opcode_ae_s32x2x2rng_xp_encode_fns, 1, Opcode_ae_s32x2x2rng_xp_funcUnit_uses }, + { "ae_s16x4x2.xc", ICLASS_AE_S16X4X2_XC, + 0, + Opcode_ae_s16x4x2_xc_encode_fns, 1, Opcode_ae_s16x4x2_xc_funcUnit_uses }, + { "ae_s16x4x2.xc1", ICLASS_AE_S16X4X2_XC1, + 0, + Opcode_ae_s16x4x2_xc1_encode_fns, 1, Opcode_ae_s16x4x2_xc1_funcUnit_uses }, + { "ae_s16x4x2.i", ICLASS_AE_S16X4X2_I, + 0, + Opcode_ae_s16x4x2_i_encode_fns, 1, Opcode_ae_s16x4x2_i_funcUnit_uses }, + { "ae_s16x4x2.ip", ICLASS_AE_S16X4X2_IP, + 0, + Opcode_ae_s16x4x2_ip_encode_fns, 1, Opcode_ae_s16x4x2_ip_funcUnit_uses }, + { "ae_s16x4x2.x", ICLASS_AE_S16X4X2_X, + 0, + Opcode_ae_s16x4x2_x_encode_fns, 1, Opcode_ae_s16x4x2_x_funcUnit_uses }, + { "ae_s16x4x2.xp", ICLASS_AE_S16X4X2_XP, + 0, + Opcode_ae_s16x4x2_xp_encode_fns, 1, Opcode_ae_s16x4x2_xp_funcUnit_uses }, + { "ae_s8x8x2.xc", ICLASS_AE_S8X8X2_XC, + 0, + Opcode_ae_s8x8x2_xc_encode_fns, 1, Opcode_ae_s8x8x2_xc_funcUnit_uses }, + { "ae_s8x8x2.xc1", ICLASS_AE_S8X8X2_XC1, + 0, + Opcode_ae_s8x8x2_xc1_encode_fns, 1, Opcode_ae_s8x8x2_xc1_funcUnit_uses }, + { "ae_s8x8x2.i", ICLASS_AE_S8X8X2_I, + 0, + Opcode_ae_s8x8x2_i_encode_fns, 1, Opcode_ae_s8x8x2_i_funcUnit_uses }, + { "ae_s8x8x2.ip", ICLASS_AE_S8X8X2_IP, + 0, + Opcode_ae_s8x8x2_ip_encode_fns, 1, Opcode_ae_s8x8x2_ip_funcUnit_uses }, + { "ae_s8x8x2.x", ICLASS_AE_S8X8X2_X, + 0, + Opcode_ae_s8x8x2_x_encode_fns, 1, Opcode_ae_s8x8x2_x_funcUnit_uses }, + { "ae_s8x8x2.xp", ICLASS_AE_S8X8X2_XP, + 0, + Opcode_ae_s8x8x2_xp_encode_fns, 1, Opcode_ae_s8x8x2_xp_funcUnit_uses }, + { "ae_s64x2.xc", ICLASS_AE_S64X2_XC, + 0, + Opcode_ae_s64x2_xc_encode_fns, 1, Opcode_ae_s64x2_xc_funcUnit_uses }, + { "ae_s64x2.xc1", ICLASS_AE_S64X2_XC1, + 0, + Opcode_ae_s64x2_xc1_encode_fns, 1, Opcode_ae_s64x2_xc1_funcUnit_uses }, + { "ae_s64x2.i", ICLASS_AE_S64X2_I, + 0, + Opcode_ae_s64x2_i_encode_fns, 1, Opcode_ae_s64x2_i_funcUnit_uses }, + { "ae_s64x2.ip", ICLASS_AE_S64X2_IP, + 0, + Opcode_ae_s64x2_ip_encode_fns, 1, Opcode_ae_s64x2_ip_funcUnit_uses }, + { "ae_s64x2.x", ICLASS_AE_S64X2_X, + 0, + Opcode_ae_s64x2_x_encode_fns, 1, Opcode_ae_s64x2_x_funcUnit_uses }, + { "ae_s64x2.xp", ICLASS_AE_S64X2_XP, + 0, + Opcode_ae_s64x2_xp_encode_fns, 1, Opcode_ae_s64x2_xp_funcUnit_uses }, + { "ae_l32x2x2.xc2", ICLASS_AE_L32X2X2_XC2, + 0, + Opcode_ae_l32x2x2_xc2_encode_fns, 1, Opcode_ae_l32x2x2_xc2_funcUnit_uses }, + { "ae_l16x4x2.xc2", ICLASS_AE_L16X4X2_XC2, + 0, + Opcode_ae_l16x4x2_xc2_encode_fns, 1, Opcode_ae_l16x4x2_xc2_funcUnit_uses }, + { "ae_l8x8x2.xc2", ICLASS_AE_L8X8X2_XC2, + 0, + Opcode_ae_l8x8x2_xc2_encode_fns, 1, Opcode_ae_l8x8x2_xc2_funcUnit_uses }, + { "ae_l64x2.xc2", ICLASS_AE_L64X2_XC2, + 0, + Opcode_ae_l64x2_xc2_encode_fns, 1, Opcode_ae_l64x2_xc2_funcUnit_uses }, + { "ae_s32x2x2.xc2", ICLASS_AE_S32X2X2_XC2, + 0, + Opcode_ae_s32x2x2_xc2_encode_fns, 1, Opcode_ae_s32x2x2_xc2_funcUnit_uses }, + { "ae_s16x4x2.xc2", ICLASS_AE_S16X4X2_XC2, + 0, + Opcode_ae_s16x4x2_xc2_encode_fns, 1, Opcode_ae_s16x4x2_xc2_funcUnit_uses }, + { "ae_s8x8x2.xc2", ICLASS_AE_S8X8X2_XC2, + 0, + Opcode_ae_s8x8x2_xc2_encode_fns, 1, Opcode_ae_s8x8x2_xc2_funcUnit_uses }, + { "ae_s64x2.xc2", ICLASS_AE_S64X2_XC2, + 0, + Opcode_ae_s64x2_xc2_encode_fns, 1, Opcode_ae_s64x2_xc2_funcUnit_uses }, + { "ae_s16x4x2rng.i", ICLASS_AE_S16X4X2RNG_I, + 0, + Opcode_ae_s16x4x2rng_i_encode_fns, 1, Opcode_ae_s16x4x2rng_i_funcUnit_uses }, + { "ae_s16x4x2rng.ip", ICLASS_AE_S16X4X2RNG_IP, + 0, + Opcode_ae_s16x4x2rng_ip_encode_fns, 1, Opcode_ae_s16x4x2rng_ip_funcUnit_uses }, + { "ae_s16x4x2rng.x", ICLASS_AE_S16X4X2RNG_X, + 0, + Opcode_ae_s16x4x2rng_x_encode_fns, 1, Opcode_ae_s16x4x2rng_x_funcUnit_uses }, + { "ae_s16x4x2rng.xp", ICLASS_AE_S16X4X2RNG_XP, + 0, + Opcode_ae_s16x4x2rng_xp_encode_fns, 1, Opcode_ae_s16x4x2rng_xp_funcUnit_uses }, + { "ae_zalign64", ICLASS_AE_ZALIGN64, + 0, + Opcode_ae_zalign64_encode_fns, 0, 0 }, + { "ae_lalign64.i", ICLASS_AE_LALIGN64_I, + 0, + Opcode_ae_lalign64_i_encode_fns, 1, Opcode_ae_lalign64_i_funcUnit_uses }, + { "ae_salign64.i", ICLASS_AE_SALIGN64_I, + 0, + Opcode_ae_salign64_i_encode_fns, 1, Opcode_ae_salign64_i_funcUnit_uses }, + { "ae_movalign", ICLASS_AE_MOVALIGN, + 0, + Opcode_ae_movalign_encode_fns, 0, 0 }, + { "ae_la64.pp", ICLASS_AE_LA64_PP, + 0, + Opcode_ae_la64_pp_encode_fns, 1, Opcode_ae_la64_pp_funcUnit_uses }, + { "ae_la24pos.pc", ICLASS_AE_LA24POS_PC, + 0, + Opcode_ae_la24pos_pc_encode_fns, 1, Opcode_ae_la24pos_pc_funcUnit_uses }, + { "ae_la24neg.pc", ICLASS_AE_LA24NEG_PC, + 0, + Opcode_ae_la24neg_pc_encode_fns, 1, Opcode_ae_la24neg_pc_funcUnit_uses }, + { "ae_la24pos.pc1", ICLASS_AE_LA24POS_PC1, + 0, + Opcode_ae_la24pos_pc1_encode_fns, 1, Opcode_ae_la24pos_pc1_funcUnit_uses }, + { "ae_la24neg.pc1", ICLASS_AE_LA24NEG_PC1, + 0, + Opcode_ae_la24neg_pc1_encode_fns, 1, Opcode_ae_la24neg_pc1_funcUnit_uses }, + { "ae_la24x2pos.pc", ICLASS_AE_LA24X2POS_PC, + 0, + Opcode_ae_la24x2pos_pc_encode_fns, 1, Opcode_ae_la24x2pos_pc_funcUnit_uses }, + { "ae_la24x2neg.pc", ICLASS_AE_LA24X2NEG_PC, + 0, + Opcode_ae_la24x2neg_pc_encode_fns, 1, Opcode_ae_la24x2neg_pc_funcUnit_uses }, + { "ae_la24x2pos.pc1", ICLASS_AE_LA24X2POS_PC1, + 0, + Opcode_ae_la24x2pos_pc1_encode_fns, 1, Opcode_ae_la24x2pos_pc1_funcUnit_uses }, + { "ae_la24x2neg.pc1", ICLASS_AE_LA24X2NEG_PC1, + 0, + Opcode_ae_la24x2neg_pc1_encode_fns, 1, Opcode_ae_la24x2neg_pc1_funcUnit_uses }, + { "ae_la32x2pos.pc", ICLASS_AE_LA32X2POS_PC, + 0, + Opcode_ae_la32x2pos_pc_encode_fns, 1, Opcode_ae_la32x2pos_pc_funcUnit_uses }, + { "ae_la32x2neg.pc", ICLASS_AE_LA32X2NEG_PC, + 0, + Opcode_ae_la32x2neg_pc_encode_fns, 1, Opcode_ae_la32x2neg_pc_funcUnit_uses }, + { "ae_la32x2pos.pc1", ICLASS_AE_LA32X2POS_PC1, + 0, + Opcode_ae_la32x2pos_pc1_encode_fns, 1, Opcode_ae_la32x2pos_pc1_funcUnit_uses }, + { "ae_la32x2neg.pc1", ICLASS_AE_LA32X2NEG_PC1, + 0, + Opcode_ae_la32x2neg_pc1_encode_fns, 1, Opcode_ae_la32x2neg_pc1_funcUnit_uses }, + { "ae_la32x2pos.pc2", ICLASS_AE_LA32X2POS_PC2, + 0, + Opcode_ae_la32x2pos_pc2_encode_fns, 1, Opcode_ae_la32x2pos_pc2_funcUnit_uses }, + { "ae_la16x4pos.pc", ICLASS_AE_LA16X4POS_PC, + 0, + Opcode_ae_la16x4pos_pc_encode_fns, 1, Opcode_ae_la16x4pos_pc_funcUnit_uses }, + { "ae_la16x4neg.pc", ICLASS_AE_LA16X4NEG_PC, + 0, + Opcode_ae_la16x4neg_pc_encode_fns, 1, Opcode_ae_la16x4neg_pc_funcUnit_uses }, + { "ae_la16x4pos.pc1", ICLASS_AE_LA16X4POS_PC1, + 0, + Opcode_ae_la16x4pos_pc1_encode_fns, 1, Opcode_ae_la16x4pos_pc1_funcUnit_uses }, + { "ae_la16x4neg.pc1", ICLASS_AE_LA16X4NEG_PC1, + 0, + Opcode_ae_la16x4neg_pc1_encode_fns, 1, Opcode_ae_la16x4neg_pc1_funcUnit_uses }, + { "ae_la16x4pos.pc2", ICLASS_AE_LA16X4POS_PC2, + 0, + Opcode_ae_la16x4pos_pc2_encode_fns, 1, Opcode_ae_la16x4pos_pc2_funcUnit_uses }, + { "ae_la8x8pos.pc", ICLASS_AE_LA8X8POS_PC, + 0, + Opcode_ae_la8x8pos_pc_encode_fns, 1, Opcode_ae_la8x8pos_pc_funcUnit_uses }, + { "ae_la8x8neg.pc", ICLASS_AE_LA8X8NEG_PC, + 0, + Opcode_ae_la8x8neg_pc_encode_fns, 1, Opcode_ae_la8x8neg_pc_funcUnit_uses }, + { "ae_la8x8pos.pc1", ICLASS_AE_LA8X8POS_PC1, + 0, + Opcode_ae_la8x8pos_pc1_encode_fns, 1, Opcode_ae_la8x8pos_pc1_funcUnit_uses }, + { "ae_la8x8neg.pc1", ICLASS_AE_LA8X8NEG_PC1, + 0, + Opcode_ae_la8x8neg_pc1_encode_fns, 1, Opcode_ae_la8x8neg_pc1_funcUnit_uses }, + { "ae_la8x8pos.pc2", ICLASS_AE_LA8X8POS_PC2, + 0, + Opcode_ae_la8x8pos_pc2_encode_fns, 1, Opcode_ae_la8x8pos_pc2_funcUnit_uses }, + { "ae_la32x2x2pos.pc", ICLASS_AE_LA32X2X2POS_PC, + 0, + Opcode_ae_la32x2x2pos_pc_encode_fns, 1, Opcode_ae_la32x2x2pos_pc_funcUnit_uses }, + { "ae_la32x2x2pos.pc1", ICLASS_AE_LA32X2X2POS_PC1, + 0, + Opcode_ae_la32x2x2pos_pc1_encode_fns, 1, Opcode_ae_la32x2x2pos_pc1_funcUnit_uses }, + { "ae_la32x2x2pos.pc2", ICLASS_AE_LA32X2X2POS_PC2, + 0, + Opcode_ae_la32x2x2pos_pc2_encode_fns, 1, Opcode_ae_la32x2x2pos_pc2_funcUnit_uses }, + { "ae_la16x4x2pos.pc", ICLASS_AE_LA16X4X2POS_PC, + 0, + Opcode_ae_la16x4x2pos_pc_encode_fns, 1, Opcode_ae_la16x4x2pos_pc_funcUnit_uses }, + { "ae_la16x4x2pos.pc1", ICLASS_AE_LA16X4X2POS_PC1, + 0, + Opcode_ae_la16x4x2pos_pc1_encode_fns, 1, Opcode_ae_la16x4x2pos_pc1_funcUnit_uses }, + { "ae_la16x4x2pos.pc2", ICLASS_AE_LA16X4X2POS_PC2, + 0, + Opcode_ae_la16x4x2pos_pc2_encode_fns, 1, Opcode_ae_la16x4x2pos_pc2_funcUnit_uses }, + { "ae_la8x8x2pos.pc", ICLASS_AE_LA8X8X2POS_PC, + 0, + Opcode_ae_la8x8x2pos_pc_encode_fns, 1, Opcode_ae_la8x8x2pos_pc_funcUnit_uses }, + { "ae_la8x8x2pos.pc1", ICLASS_AE_LA8X8X2POS_PC1, + 0, + Opcode_ae_la8x8x2pos_pc1_encode_fns, 1, Opcode_ae_la8x8x2pos_pc1_funcUnit_uses }, + { "ae_la8x8x2pos.pc2", ICLASS_AE_LA8X8X2POS_PC2, + 0, + Opcode_ae_la8x8x2pos_pc2_encode_fns, 1, Opcode_ae_la8x8x2pos_pc2_funcUnit_uses }, + { "ae_sa64pos.fp", ICLASS_AE_SA64POS_FP, + 0, + Opcode_ae_sa64pos_fp_encode_fns, 1, Opcode_ae_sa64pos_fp_funcUnit_uses }, + { "ae_sa64neg.fp", ICLASS_AE_SA64NEG_FP, + 0, + Opcode_ae_sa64neg_fp_encode_fns, 1, Opcode_ae_sa64neg_fp_funcUnit_uses }, + { "ae_la32x2.ic", ICLASS_AE_LA32X2_IC, + 0, + Opcode_ae_la32x2_ic_encode_fns, 1, Opcode_ae_la32x2_ic_funcUnit_uses }, + { "ae_la32x2.ic1", ICLASS_AE_LA32X2_IC1, + 0, + Opcode_ae_la32x2_ic1_encode_fns, 1, Opcode_ae_la32x2_ic1_funcUnit_uses }, + { "ae_la32x2.ic2", ICLASS_AE_LA32X2_IC2, + 0, + Opcode_ae_la32x2_ic2_encode_fns, 1, Opcode_ae_la32x2_ic2_funcUnit_uses }, + { "ae_la32x2.ip", ICLASS_AE_LA32X2_IP, + 0, + Opcode_ae_la32x2_ip_encode_fns, 1, Opcode_ae_la32x2_ip_funcUnit_uses }, + { "ae_la32x2.rip", ICLASS_AE_LA32X2_RIP, + 0, + Opcode_ae_la32x2_rip_encode_fns, 1, Opcode_ae_la32x2_rip_funcUnit_uses }, + { "ae_la32x2.ric", ICLASS_AE_LA32X2_RIC, + 0, + Opcode_ae_la32x2_ric_encode_fns, 1, Opcode_ae_la32x2_ric_funcUnit_uses }, + { "ae_la32x2.ric1", ICLASS_AE_LA32X2_RIC1, + 0, + Opcode_ae_la32x2_ric1_encode_fns, 1, Opcode_ae_la32x2_ric1_funcUnit_uses }, + { "ae_la16x4.ic", ICLASS_AE_LA16X4_IC, + 0, + Opcode_ae_la16x4_ic_encode_fns, 1, Opcode_ae_la16x4_ic_funcUnit_uses }, + { "ae_la16x4.ic1", ICLASS_AE_LA16X4_IC1, + 0, + Opcode_ae_la16x4_ic1_encode_fns, 1, Opcode_ae_la16x4_ic1_funcUnit_uses }, + { "ae_la16x4.ic2", ICLASS_AE_LA16X4_IC2, + 0, + Opcode_ae_la16x4_ic2_encode_fns, 1, Opcode_ae_la16x4_ic2_funcUnit_uses }, + { "ae_la16x4.ip", ICLASS_AE_LA16X4_IP, + 0, + Opcode_ae_la16x4_ip_encode_fns, 1, Opcode_ae_la16x4_ip_funcUnit_uses }, + { "ae_la16x4.rip", ICLASS_AE_LA16X4_RIP, + 0, + Opcode_ae_la16x4_rip_encode_fns, 1, Opcode_ae_la16x4_rip_funcUnit_uses }, + { "ae_la16x4.ric", ICLASS_AE_LA16X4_RIC, + 0, + Opcode_ae_la16x4_ric_encode_fns, 1, Opcode_ae_la16x4_ric_funcUnit_uses }, + { "ae_la16x4.ric1", ICLASS_AE_LA16X4_RIC1, + 0, + Opcode_ae_la16x4_ric1_encode_fns, 1, Opcode_ae_la16x4_ric1_funcUnit_uses }, + { "ae_la8x8.ic", ICLASS_AE_LA8X8_IC, + 0, + Opcode_ae_la8x8_ic_encode_fns, 1, Opcode_ae_la8x8_ic_funcUnit_uses }, + { "ae_la8x8.ic1", ICLASS_AE_LA8X8_IC1, + 0, + Opcode_ae_la8x8_ic1_encode_fns, 1, Opcode_ae_la8x8_ic1_funcUnit_uses }, + { "ae_la8x8.ic2", ICLASS_AE_LA8X8_IC2, + 0, + Opcode_ae_la8x8_ic2_encode_fns, 1, Opcode_ae_la8x8_ic2_funcUnit_uses }, + { "ae_la8x8.ip", ICLASS_AE_LA8X8_IP, + 0, + Opcode_ae_la8x8_ip_encode_fns, 1, Opcode_ae_la8x8_ip_funcUnit_uses }, + { "ae_la8x8.rip", ICLASS_AE_LA8X8_RIP, + 0, + Opcode_ae_la8x8_rip_encode_fns, 1, Opcode_ae_la8x8_rip_funcUnit_uses }, + { "ae_la8x8.ric", ICLASS_AE_LA8X8_RIC, + 0, + Opcode_ae_la8x8_ric_encode_fns, 1, Opcode_ae_la8x8_ric_funcUnit_uses }, + { "ae_la8x8.ric1", ICLASS_AE_LA8X8_RIC1, + 0, + Opcode_ae_la8x8_ric1_encode_fns, 1, Opcode_ae_la8x8_ric1_funcUnit_uses }, + { "ae_la32x2f24.ic", ICLASS_AE_LA32X2F24_IC, + 0, + Opcode_ae_la32x2f24_ic_encode_fns, 1, Opcode_ae_la32x2f24_ic_funcUnit_uses }, + { "ae_la32x2f24.ic1", ICLASS_AE_LA32X2F24_IC1, + 0, + Opcode_ae_la32x2f24_ic1_encode_fns, 1, Opcode_ae_la32x2f24_ic1_funcUnit_uses }, + { "ae_la32x2f24.ip", ICLASS_AE_LA32X2F24_IP, + 0, + Opcode_ae_la32x2f24_ip_encode_fns, 1, Opcode_ae_la32x2f24_ip_funcUnit_uses }, + { "ae_la32x2f24.rip", ICLASS_AE_LA32X2F24_RIP, + 0, + Opcode_ae_la32x2f24_rip_encode_fns, 1, Opcode_ae_la32x2f24_rip_funcUnit_uses }, + { "ae_la32x2f24.ric", ICLASS_AE_LA32X2F24_RIC, + 0, + Opcode_ae_la32x2f24_ric_encode_fns, 1, Opcode_ae_la32x2f24_ric_funcUnit_uses }, + { "ae_la32x2f24.ric1", ICLASS_AE_LA32X2F24_RIC1, + 0, + Opcode_ae_la32x2f24_ric1_encode_fns, 1, Opcode_ae_la32x2f24_ric1_funcUnit_uses }, + { "ae_la24.ic", ICLASS_AE_LA24_IC, + 0, + Opcode_ae_la24_ic_encode_fns, 1, Opcode_ae_la24_ic_funcUnit_uses }, + { "ae_la24.ic1", ICLASS_AE_LA24_IC1, + 0, + Opcode_ae_la24_ic1_encode_fns, 1, Opcode_ae_la24_ic1_funcUnit_uses }, + { "ae_la24.ip", ICLASS_AE_LA24_IP, + 0, + Opcode_ae_la24_ip_encode_fns, 1, Opcode_ae_la24_ip_funcUnit_uses }, + { "ae_la24.rip", ICLASS_AE_LA24_RIP, + 0, + Opcode_ae_la24_rip_encode_fns, 1, Opcode_ae_la24_rip_funcUnit_uses }, + { "ae_la24.ric", ICLASS_AE_LA24_RIC, + 0, + Opcode_ae_la24_ric_encode_fns, 1, Opcode_ae_la24_ric_funcUnit_uses }, + { "ae_la24.ric1", ICLASS_AE_LA24_RIC1, + 0, + Opcode_ae_la24_ric1_encode_fns, 1, Opcode_ae_la24_ric1_funcUnit_uses }, + { "ae_la24x2.ic", ICLASS_AE_LA24X2_IC, + 0, + Opcode_ae_la24x2_ic_encode_fns, 1, Opcode_ae_la24x2_ic_funcUnit_uses }, + { "ae_la24x2.ic1", ICLASS_AE_LA24X2_IC1, + 0, + Opcode_ae_la24x2_ic1_encode_fns, 1, Opcode_ae_la24x2_ic1_funcUnit_uses }, + { "ae_la24x2.ip", ICLASS_AE_LA24X2_IP, + 0, + Opcode_ae_la24x2_ip_encode_fns, 1, Opcode_ae_la24x2_ip_funcUnit_uses }, + { "ae_la24x2.rip", ICLASS_AE_LA24X2_RIP, + 0, + Opcode_ae_la24x2_rip_encode_fns, 1, Opcode_ae_la24x2_rip_funcUnit_uses }, + { "ae_la24x2.ric", ICLASS_AE_LA24X2_RIC, + 0, + Opcode_ae_la24x2_ric_encode_fns, 1, Opcode_ae_la24x2_ric_funcUnit_uses }, + { "ae_la24x2.ric1", ICLASS_AE_LA24X2_RIC1, + 0, + Opcode_ae_la24x2_ric1_encode_fns, 1, Opcode_ae_la24x2_ric1_funcUnit_uses }, + { "ae_sa32x2.ic", ICLASS_AE_SA32X2_IC, + 0, + Opcode_ae_sa32x2_ic_encode_fns, 1, Opcode_ae_sa32x2_ic_funcUnit_uses }, + { "ae_sa32x2.ic1", ICLASS_AE_SA32X2_IC1, + 0, + Opcode_ae_sa32x2_ic1_encode_fns, 1, Opcode_ae_sa32x2_ic1_funcUnit_uses }, + { "ae_sa32x2.ic2", ICLASS_AE_SA32X2_IC2, + 0, + Opcode_ae_sa32x2_ic2_encode_fns, 1, Opcode_ae_sa32x2_ic2_funcUnit_uses }, + { "ae_sa32x2.ip", ICLASS_AE_SA32X2_IP, + 0, + Opcode_ae_sa32x2_ip_encode_fns, 1, Opcode_ae_sa32x2_ip_funcUnit_uses }, + { "ae_sa32x2.rip", ICLASS_AE_SA32X2_RIP, + 0, + Opcode_ae_sa32x2_rip_encode_fns, 1, Opcode_ae_sa32x2_rip_funcUnit_uses }, + { "ae_sa32x2.ric", ICLASS_AE_SA32X2_RIC, + 0, + Opcode_ae_sa32x2_ric_encode_fns, 1, Opcode_ae_sa32x2_ric_funcUnit_uses }, + { "ae_sa32x2.ric1", ICLASS_AE_SA32X2_RIC1, + 0, + Opcode_ae_sa32x2_ric1_encode_fns, 1, Opcode_ae_sa32x2_ric1_funcUnit_uses }, + { "ae_sa16x4.ic", ICLASS_AE_SA16X4_IC, + 0, + Opcode_ae_sa16x4_ic_encode_fns, 1, Opcode_ae_sa16x4_ic_funcUnit_uses }, + { "ae_sa16x4.ic1", ICLASS_AE_SA16X4_IC1, + 0, + Opcode_ae_sa16x4_ic1_encode_fns, 1, Opcode_ae_sa16x4_ic1_funcUnit_uses }, + { "ae_sa16x4.ic2", ICLASS_AE_SA16X4_IC2, + 0, + Opcode_ae_sa16x4_ic2_encode_fns, 1, Opcode_ae_sa16x4_ic2_funcUnit_uses }, + { "ae_sa16x4.ip", ICLASS_AE_SA16X4_IP, + 0, + Opcode_ae_sa16x4_ip_encode_fns, 1, Opcode_ae_sa16x4_ip_funcUnit_uses }, + { "ae_sa16x4.rip", ICLASS_AE_SA16X4_RIP, + 0, + Opcode_ae_sa16x4_rip_encode_fns, 1, Opcode_ae_sa16x4_rip_funcUnit_uses }, + { "ae_sa16x4.ric", ICLASS_AE_SA16X4_RIC, + 0, + Opcode_ae_sa16x4_ric_encode_fns, 1, Opcode_ae_sa16x4_ric_funcUnit_uses }, + { "ae_sa16x4.ric1", ICLASS_AE_SA16X4_RIC1, + 0, + Opcode_ae_sa16x4_ric1_encode_fns, 1, Opcode_ae_sa16x4_ric1_funcUnit_uses }, + { "ae_sa8x8.ic", ICLASS_AE_SA8X8_IC, + 0, + Opcode_ae_sa8x8_ic_encode_fns, 1, Opcode_ae_sa8x8_ic_funcUnit_uses }, + { "ae_sa8x8.ic1", ICLASS_AE_SA8X8_IC1, + 0, + Opcode_ae_sa8x8_ic1_encode_fns, 1, Opcode_ae_sa8x8_ic1_funcUnit_uses }, + { "ae_sa8x8.ic2", ICLASS_AE_SA8X8_IC2, + 0, + Opcode_ae_sa8x8_ic2_encode_fns, 1, Opcode_ae_sa8x8_ic2_funcUnit_uses }, + { "ae_sa8x8.ip", ICLASS_AE_SA8X8_IP, + 0, + Opcode_ae_sa8x8_ip_encode_fns, 1, Opcode_ae_sa8x8_ip_funcUnit_uses }, + { "ae_sa8x8.rip", ICLASS_AE_SA8X8_RIP, + 0, + Opcode_ae_sa8x8_rip_encode_fns, 1, Opcode_ae_sa8x8_rip_funcUnit_uses }, + { "ae_sa8x8.ric", ICLASS_AE_SA8X8_RIC, + 0, + Opcode_ae_sa8x8_ric_encode_fns, 1, Opcode_ae_sa8x8_ric_funcUnit_uses }, + { "ae_sa8x8.ric1", ICLASS_AE_SA8X8_RIC1, + 0, + Opcode_ae_sa8x8_ric1_encode_fns, 1, Opcode_ae_sa8x8_ric1_funcUnit_uses }, + { "ae_sa32x2f24.ic", ICLASS_AE_SA32X2F24_IC, + 0, + Opcode_ae_sa32x2f24_ic_encode_fns, 1, Opcode_ae_sa32x2f24_ic_funcUnit_uses }, + { "ae_sa32x2f24.ic1", ICLASS_AE_SA32X2F24_IC1, + 0, + Opcode_ae_sa32x2f24_ic1_encode_fns, 1, Opcode_ae_sa32x2f24_ic1_funcUnit_uses }, + { "ae_sa32x2f24.ip", ICLASS_AE_SA32X2F24_IP, + 0, + Opcode_ae_sa32x2f24_ip_encode_fns, 1, Opcode_ae_sa32x2f24_ip_funcUnit_uses }, + { "ae_sa32x2f24.rip", ICLASS_AE_SA32X2F24_RIP, + 0, + Opcode_ae_sa32x2f24_rip_encode_fns, 1, Opcode_ae_sa32x2f24_rip_funcUnit_uses }, + { "ae_sa32x2f24.ric", ICLASS_AE_SA32X2F24_RIC, + 0, + Opcode_ae_sa32x2f24_ric_encode_fns, 1, Opcode_ae_sa32x2f24_ric_funcUnit_uses }, + { "ae_sa32x2f24.ric1", ICLASS_AE_SA32X2F24_RIC1, + 0, + Opcode_ae_sa32x2f24_ric1_encode_fns, 1, Opcode_ae_sa32x2f24_ric1_funcUnit_uses }, + { "ae_sa24.l.ic", ICLASS_AE_SA24_L_IC, + 0, + Opcode_ae_sa24_l_ic_encode_fns, 1, Opcode_ae_sa24_l_ic_funcUnit_uses }, + { "ae_sa24.l.ic1", ICLASS_AE_SA24_L_IC1, + 0, + Opcode_ae_sa24_l_ic1_encode_fns, 1, Opcode_ae_sa24_l_ic1_funcUnit_uses }, + { "ae_sa24.l.ip", ICLASS_AE_SA24_L_IP, + 0, + Opcode_ae_sa24_l_ip_encode_fns, 1, Opcode_ae_sa24_l_ip_funcUnit_uses }, + { "ae_sa24.l.rip", ICLASS_AE_SA24_L_RIP, + 0, + Opcode_ae_sa24_l_rip_encode_fns, 1, Opcode_ae_sa24_l_rip_funcUnit_uses }, + { "ae_sa24.l.ric", ICLASS_AE_SA24_L_RIC, + 0, + Opcode_ae_sa24_l_ric_encode_fns, 1, Opcode_ae_sa24_l_ric_funcUnit_uses }, + { "ae_sa24.l.ric1", ICLASS_AE_SA24_L_RIC1, + 0, + Opcode_ae_sa24_l_ric1_encode_fns, 1, Opcode_ae_sa24_l_ric1_funcUnit_uses }, + { "ae_sa24x2.ic", ICLASS_AE_SA24X2_IC, + 0, + Opcode_ae_sa24x2_ic_encode_fns, 1, Opcode_ae_sa24x2_ic_funcUnit_uses }, + { "ae_sa24x2.ic1", ICLASS_AE_SA24X2_IC1, + 0, + Opcode_ae_sa24x2_ic1_encode_fns, 1, Opcode_ae_sa24x2_ic1_funcUnit_uses }, + { "ae_sa24x2.ip", ICLASS_AE_SA24X2_IP, + 0, + Opcode_ae_sa24x2_ip_encode_fns, 1, Opcode_ae_sa24x2_ip_funcUnit_uses }, + { "ae_sa24x2.rip", ICLASS_AE_SA24X2_RIP, + 0, + Opcode_ae_sa24x2_rip_encode_fns, 1, Opcode_ae_sa24x2_rip_funcUnit_uses }, + { "ae_sa24x2.ric", ICLASS_AE_SA24X2_RIC, + 0, + Opcode_ae_sa24x2_ric_encode_fns, 1, Opcode_ae_sa24x2_ric_funcUnit_uses }, + { "ae_sa24x2.ric1", ICLASS_AE_SA24X2_RIC1, + 0, + Opcode_ae_sa24x2_ric1_encode_fns, 1, Opcode_ae_sa24x2_ric1_funcUnit_uses }, + { "ae_addicirc", ICLASS_AE_ADDICIRC, + 0, + Opcode_ae_addicirc_encode_fns, 0, 0 }, + { "ae_addcirc.xc2", ICLASS_AE_ADDCIRC_XC2, + 0, + Opcode_ae_addcirc_xc2_encode_fns, 0, 0 }, + { "ae_addcirc.xc1", ICLASS_AE_ADDCIRC_XC1, + 0, + Opcode_ae_addcirc_xc1_encode_fns, 0, 0 }, + { "ae_addcirc.xc", ICLASS_AE_ADDCIRC_XC, + 0, + Opcode_ae_addcirc_xc_encode_fns, 0, 0 }, + { "ae_s32ra64s.i", ICLASS_AE_S32RA64S_I, + 0, + Opcode_ae_s32ra64s_i_encode_fns, 1, Opcode_ae_s32ra64s_i_funcUnit_uses }, + { "ae_s32ra64s.ip", ICLASS_AE_S32RA64S_IP, + 0, + Opcode_ae_s32ra64s_ip_encode_fns, 1, Opcode_ae_s32ra64s_ip_funcUnit_uses }, + { "ae_s32ra64s.x", ICLASS_AE_S32RA64S_X, + 0, + Opcode_ae_s32ra64s_x_encode_fns, 1, Opcode_ae_s32ra64s_x_funcUnit_uses }, + { "ae_s32ra64s.xp", ICLASS_AE_S32RA64S_XP, + 0, + Opcode_ae_s32ra64s_xp_encode_fns, 1, Opcode_ae_s32ra64s_xp_funcUnit_uses }, + { "ae_s32ra64s.xc", ICLASS_AE_S32RA64S_XC, + 0, + Opcode_ae_s32ra64s_xc_encode_fns, 1, Opcode_ae_s32ra64s_xc_funcUnit_uses }, + { "ae_s32ra64s.xc1", ICLASS_AE_S32RA64S_XC1, + 0, + Opcode_ae_s32ra64s_xc1_encode_fns, 1, Opcode_ae_s32ra64s_xc1_funcUnit_uses }, + { "ae_s24ra64s.i", ICLASS_AE_S24RA64S_I, + 0, + Opcode_ae_s24ra64s_i_encode_fns, 1, Opcode_ae_s24ra64s_i_funcUnit_uses }, + { "ae_s24ra64s.ip", ICLASS_AE_S24RA64S_IP, + 0, + Opcode_ae_s24ra64s_ip_encode_fns, 1, Opcode_ae_s24ra64s_ip_funcUnit_uses }, + { "ae_s24ra64s.x", ICLASS_AE_S24RA64S_X, + 0, + Opcode_ae_s24ra64s_x_encode_fns, 1, Opcode_ae_s24ra64s_x_funcUnit_uses }, + { "ae_s24ra64s.xp", ICLASS_AE_S24RA64S_XP, + 0, + Opcode_ae_s24ra64s_xp_encode_fns, 1, Opcode_ae_s24ra64s_xp_funcUnit_uses }, + { "ae_s24ra64s.xc", ICLASS_AE_S24RA64S_XC, + 0, + Opcode_ae_s24ra64s_xc_encode_fns, 1, Opcode_ae_s24ra64s_xc_funcUnit_uses }, + { "ae_s24ra64s.xc1", ICLASS_AE_S24RA64S_XC1, + 0, + Opcode_ae_s24ra64s_xc1_encode_fns, 1, Opcode_ae_s24ra64s_xc1_funcUnit_uses }, + { "ae_s32x2ra64s.ip", ICLASS_AE_S32X2RA64S_IP, + 0, + Opcode_ae_s32x2ra64s_ip_encode_fns, 1, Opcode_ae_s32x2ra64s_ip_funcUnit_uses }, + { "ae_s24x2ra64s.ip", ICLASS_AE_S24X2RA64S_IP, + 0, + Opcode_ae_s24x2ra64s_ip_encode_fns, 1, Opcode_ae_s24x2ra64s_ip_funcUnit_uses }, + { "ae_s16x4ra32s.ip", ICLASS_AE_S16X4RA32S_IP, + 0, + Opcode_ae_s16x4ra32s_ip_encode_fns, 1, Opcode_ae_s16x4ra32s_ip_funcUnit_uses }, + { "ae_addbrba32", ICLASS_AE_ADDBRBA32, + 0, + Opcode_ae_addbrba32_encode_fns, 0, 0 }, + { "ae_s32x2.l.ip", ICLASS_AE_S32X2_L_IP, + 0, + Opcode_ae_s32x2_l_ip_encode_fns, 1, Opcode_ae_s32x2_l_ip_funcUnit_uses }, + { "ae_bitswap", ICLASS_AE_BITSWAP, + 0, + Opcode_ae_bitswap_encode_fns, 0, 0 }, + { "ae_mul32js", ICLASS_AE_MUL32JS, + 0, + Opcode_ae_mul32js_encode_fns, 0, 0 }, + { "ae_addandsub32s", ICLASS_AE_ADDANDSUB32S, + 0, + Opcode_ae_addandsub32s_encode_fns, 0, 0 }, + { "ae_addandsub32js", ICLASS_AE_ADDANDSUB32JS, + 0, + Opcode_ae_addandsub32js_encode_fns, 0, 0 }, + { "ae_addandsubrng32", ICLASS_AE_ADDANDSUBRNG32, + 0, + Opcode_ae_addandsubrng32_encode_fns, 0, 0 }, + { "ae_addandsubrng32.h", ICLASS_AE_ADDANDSUBRNG32_H, + 0, + Opcode_ae_addandsubrng32_h_encode_fns, 0, 0 }, + { "ae_addandsubrng32.l", ICLASS_AE_ADDANDSUBRNG32_L, + 0, + Opcode_ae_addandsubrng32_l_encode_fns, 0, 0 }, + { "ae_addrng32", ICLASS_AE_ADDRNG32, + 0, + Opcode_ae_addrng32_encode_fns, 0, 0 }, + { "ae_subrng32", ICLASS_AE_SUBRNG32, + 0, + Opcode_ae_subrng32_encode_fns, 0, 0 }, + { "ae_rng32x2", ICLASS_AE_RNG32X2, + 0, + Opcode_ae_rng32x2_encode_fns, 0, 0 }, + { "ae_sel16i", ICLASS_AE_SEL16I, + 0, + Opcode_ae_sel16i_encode_fns, 0, 0 }, + { "ae_sel16i.n", ICLASS_AE_SEL16I_N, + 0, + Opcode_ae_sel16i_n_encode_fns, 0, 0 }, + { "ae_shortswap", ICLASS_AE_SHORTSWAP, + 0, + Opcode_ae_shortswap_encode_fns, 0, 0 }, + { "ae_movab4", ICLASS_AE_MOVAB4, + 0, + Opcode_ae_movab4_encode_fns, 0, 0 }, + { "ae_movab2", ICLASS_AE_MOVAB2, + 0, + Opcode_ae_movab2_encode_fns, 0, 0 }, + { "ae_movab", ICLASS_AE_MOVAB, + 0, + Opcode_ae_movab_encode_fns, 0, 0 }, + { "ae_movba", ICLASS_AE_MOVBA, + 0, + Opcode_ae_movba_encode_fns, 0, 0 }, + { "ae_movba1x2", ICLASS_AE_MOVBA1X2, + 0, + Opcode_ae_movba1x2_encode_fns, 0, 0 }, + { "ae_movba4", ICLASS_AE_MOVBA4, + 0, + Opcode_ae_movba4_encode_fns, 0, 0 }, + { "ae_movba2", ICLASS_AE_MOVBA2, + 0, + Opcode_ae_movba2_encode_fns, 0, 0 }, + { "ae_movb2", ICLASS_AE_MOVB2, + 0, + Opcode_ae_movb2_encode_fns, 0, 0 }, + { "ae_movb4", ICLASS_AE_MOVB4, + 0, + Opcode_ae_movb4_encode_fns, 0, 0 }, + { "ae_movt16x4", ICLASS_AE_MOVT16X4, + 0, + Opcode_ae_movt16x4_encode_fns, 0, 0 }, + { "ae_movf16x4", ICLASS_AE_MOVF16X4, + 0, + Opcode_ae_movf16x4_encode_fns, 0, 0 }, + { "ae_movt32x2", ICLASS_AE_MOVT32X2, + 0, + Opcode_ae_movt32x2_encode_fns, 0, 0 }, + { "ae_movf32x2", ICLASS_AE_MOVF32X2, + 0, + Opcode_ae_movf32x2_encode_fns, 0, 0 }, + { "ae_movsara7x2", ICLASS_AE_MOVSARA7X2, + 0, + Opcode_ae_movsara7x2_encode_fns, 0, 0 }, + { "ae_movsard7", ICLASS_AE_MOVSARD7, + 0, + Opcode_ae_movsard7_encode_fns, 0, 0 }, + { "ae_movasar", ICLASS_AE_MOVASAR, + 0, + Opcode_ae_movasar_encode_fns, 0, 0 }, + { "ae_movda32x2", ICLASS_AE_MOVDA32X2, + 0, + Opcode_ae_movda32x2_encode_fns, 0, 0 }, + { "ae_movda32", ICLASS_AE_MOVDA32, + 0, + Opcode_ae_movda32_encode_fns, 0, 0 }, + { "ae_movda16x2", ICLASS_AE_MOVDA16X2, + 0, + Opcode_ae_movda16x2_encode_fns, 0, 0 }, + { "ae_movda16", ICLASS_AE_MOVDA16, + 0, + Opcode_ae_movda16_encode_fns, 0, 0 }, + { "ae_movi", ICLASS_AE_MOVI, + 0, + Opcode_ae_movi_encode_fns, 0, 0 }, + { "ae_truncp24a32x2", ICLASS_AE_TRUNCP24A32X2, + 0, + Opcode_ae_truncp24a32x2_encode_fns, 0, 0 }, + { "ae_sat16x4", ICLASS_AE_SAT16X4, + 0, + Opcode_ae_sat16x4_encode_fns, 0, 0 }, + { "ae_cvt32x2f16.32", ICLASS_AE_CVT32X2F16_32, + 0, + Opcode_ae_cvt32x2f16_32_encode_fns, 0, 0 }, + { "ae_cvt32x2f16.10", ICLASS_AE_CVT32X2F16_10, + 0, + Opcode_ae_cvt32x2f16_10_encode_fns, 0, 0 }, + { "ae_sext32x2d16.32", ICLASS_AE_SEXT32X2D16_32, + 0, + Opcode_ae_sext32x2d16_32_encode_fns, 0, 0 }, + { "ae_sext32x2d16.10", ICLASS_AE_SEXT32X2D16_10, + 0, + Opcode_ae_sext32x2d16_10_encode_fns, 0, 0 }, + { "ae_cvta32f24s.l", ICLASS_AE_CVTA32F24S_L, + 0, + Opcode_ae_cvta32f24s_l_encode_fns, 0, 0 }, + { "ae_cvta32f24s.h", ICLASS_AE_CVTA32F24S_H, + 0, + Opcode_ae_cvta32f24s_h_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.ll", ICLASS_AE_CVTP24A16X2_LL, + 0, + Opcode_ae_cvtp24a16x2_ll_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.lh", ICLASS_AE_CVTP24A16X2_LH, + 0, + Opcode_ae_cvtp24a16x2_lh_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.hl", ICLASS_AE_CVTP24A16X2_HL, + 0, + Opcode_ae_cvtp24a16x2_hl_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.hh", ICLASS_AE_CVTP24A16X2_HH, + 0, + Opcode_ae_cvtp24a16x2_hh_encode_fns, 0, 0 }, + { "ae_truncp24q48x2", ICLASS_AE_TRUNCP24Q48X2, + 0, + Opcode_ae_truncp24q48x2_encode_fns, 0, 0 }, + { "ae_trunca32x2f64s", ICLASS_AE_TRUNCA32X2F64S, + 0, + Opcode_ae_trunca32x2f64s_encode_fns, 0, 0 }, + { "ae_trunci32x2f64s", ICLASS_AE_TRUNCI32X2F64S, + 0, + Opcode_ae_trunci32x2f64s_encode_fns, 0, 0 }, + { "ae_trunca32f64s.l", ICLASS_AE_TRUNCA32F64S_L, + 0, + Opcode_ae_trunca32f64s_l_encode_fns, 0, 0 }, + { "ae_trunci32f64s.l", ICLASS_AE_TRUNCI32F64S_L, + 0, + Opcode_ae_trunci32f64s_l_encode_fns, 0, 0 }, + { "ae_truncp16", ICLASS_AE_TRUNCP16, + 0, + Opcode_ae_truncp16_encode_fns, 0, 0 }, + { "ae_round32x2f64ssym", ICLASS_AE_ROUND32X2F64SSYM, + 0, + Opcode_ae_round32x2f64ssym_encode_fns, 0, 0 }, + { "ae_round32x2f64sasym", ICLASS_AE_ROUND32X2F64SASYM, + 0, + Opcode_ae_round32x2f64sasym_encode_fns, 0, 0 }, + { "ae_round32x2f48ssym", ICLASS_AE_ROUND32X2F48SSYM, + 0, + Opcode_ae_round32x2f48ssym_encode_fns, 0, 0 }, + { "ae_round32x2f48sasym", ICLASS_AE_ROUND32X2F48SASYM, + 0, + Opcode_ae_round32x2f48sasym_encode_fns, 0, 0 }, + { "ae_round16x4f32ssym", ICLASS_AE_ROUND16X4F32SSYM, + 0, + Opcode_ae_round16x4f32ssym_encode_fns, 0, 0 }, + { "ae_round16x4f32sasym", ICLASS_AE_ROUND16X4F32SASYM, + 0, + Opcode_ae_round16x4f32sasym_encode_fns, 0, 0 }, + { "ae_round24x2f48ssym", ICLASS_AE_ROUND24X2F48SSYM, + 0, + Opcode_ae_round24x2f48ssym_encode_fns, 0, 0 }, + { "ae_round24x2f48sasym", ICLASS_AE_ROUND24X2F48SASYM, + 0, + Opcode_ae_round24x2f48sasym_encode_fns, 0, 0 }, + { "ae_roundsp16q48x2sym", ICLASS_AE_ROUNDSP16Q48X2SYM, + 0, + Opcode_ae_roundsp16q48x2sym_encode_fns, 0, 0 }, + { "ae_roundsp16q48x2asym", ICLASS_AE_ROUNDSP16Q48X2ASYM, + 0, + Opcode_ae_roundsp16q48x2asym_encode_fns, 0, 0 }, + { "ae_minabs32s", ICLASS_AE_MINABS32S, + 0, + Opcode_ae_minabs32s_encode_fns, 0, 0 }, + { "ae_maxabs32s", ICLASS_AE_MAXABS32S, + 0, + Opcode_ae_maxabs32s_encode_fns, 0, 0 }, + { "ae_roundsp16f24sym", ICLASS_AE_ROUNDSP16F24SYM, + 0, + Opcode_ae_roundsp16f24sym_encode_fns, 0, 0 }, + { "ae_roundsp16f24asym", ICLASS_AE_ROUNDSP16F24ASYM, + 0, + Opcode_ae_roundsp16f24asym_encode_fns, 0, 0 }, + { "ae_mov", ICLASS_AE_MOV, + 0, + Opcode_ae_mov_encode_fns, 0, 0 }, + { "ae_movt64", ICLASS_AE_MOVT64, + 0, + Opcode_ae_movt64_encode_fns, 0, 0 }, + { "ae_movf64", ICLASS_AE_MOVF64, + 0, + Opcode_ae_movf64_encode_fns, 0, 0 }, + { "ae_cvtq56a32s", ICLASS_AE_CVTQ56A32S, + 0, + Opcode_ae_cvtq56a32s_encode_fns, 0, 0 }, + { "ae_cvt48a32", ICLASS_AE_CVT48A32, + 0, + Opcode_ae_cvt48a32_encode_fns, 0, 0 }, + { "ae_cvt64a32", ICLASS_AE_CVT64A32, + 0, + Opcode_ae_cvt64a32_encode_fns, 0, 0 }, + { "ae_cvtq56p32s.l", ICLASS_AE_CVTQ56P32S_L, + 0, + Opcode_ae_cvtq56p32s_l_encode_fns, 0, 0 }, + { "ae_cvtq56p32s.h", ICLASS_AE_CVTQ56P32S_H, + 0, + Opcode_ae_cvtq56p32s_h_encode_fns, 0, 0 }, + { "ae_cvt64f32.h", ICLASS_AE_CVT64F32_H, + 0, + Opcode_ae_cvt64f32_h_encode_fns, 0, 0 }, + { "ae_cvt48f32.l", ICLASS_AE_CVT48F32_L, + 0, + Opcode_ae_cvt48f32_l_encode_fns, 0, 0 }, + { "ae_cvt48f32.h", ICLASS_AE_CVT48F32_H, + 0, + Opcode_ae_cvt48f32_h_encode_fns, 0, 0 }, + { "ae_sat48s", ICLASS_AE_SAT48S, + 0, + Opcode_ae_sat48s_encode_fns, 0, 0 }, + { "ae_satq56s", ICLASS_AE_SATQ56S, + 0, + Opcode_ae_satq56s_encode_fns, 0, 0 }, + { "ae_sat24s", ICLASS_AE_SAT24S, + 0, + Opcode_ae_sat24s_encode_fns, 0, 0 }, + { "ae_truncq32", ICLASS_AE_TRUNCQ32, + 0, + Opcode_ae_truncq32_encode_fns, 0, 0 }, + { "ae_minabs64s", ICLASS_AE_MINABS64S, + 0, + Opcode_ae_minabs64s_encode_fns, 0, 0 }, + { "ae_maxabs64s", ICLASS_AE_MAXABS64S, + 0, + Opcode_ae_maxabs64s_encode_fns, 0, 0 }, + { "ae_roundsq32f48sym", ICLASS_AE_ROUNDSQ32F48SYM, + 0, + Opcode_ae_roundsq32f48sym_encode_fns, 0, 0 }, + { "ae_roundsq32f48asym", ICLASS_AE_ROUNDSQ32F48ASYM, + 0, + Opcode_ae_roundsq32f48asym_encode_fns, 0, 0 }, + { "ae_trunca32q48", ICLASS_AE_TRUNCA32Q48, + 0, + Opcode_ae_trunca32q48_encode_fns, 0, 0 }, + { "ae_movad32.l", ICLASS_AE_MOVAD32_L, + 0, + Opcode_ae_movad32_l_encode_fns, 0, 0 }, + { "ae_movad32.h", ICLASS_AE_MOVAD32_H, + 0, + Opcode_ae_movad32_h_encode_fns, 0, 0 }, + { "ae_movad16.3", ICLASS_AE_MOVAD16_3, + 0, + Opcode_ae_movad16_3_encode_fns, 0, 0 }, + { "ae_movad16.2", ICLASS_AE_MOVAD16_2, + 0, + Opcode_ae_movad16_2_encode_fns, 0, 0 }, + { "ae_movad16.1", ICLASS_AE_MOVAD16_1, + 0, + Opcode_ae_movad16_1_encode_fns, 0, 0 }, + { "ae_movad16.0", ICLASS_AE_MOVAD16_0, + 0, + Opcode_ae_movad16_0_encode_fns, 0, 0 }, + { "ae_sra64_32", ICLASS_AE_SRA64_32, + 0, + Opcode_ae_sra64_32_encode_fns, 0, 0 }, + { "ae_pksr32", ICLASS_AE_PKSR32, + 0, + Opcode_ae_pksr32_encode_fns, 0, 0 }, + { "ae_pksr24", ICLASS_AE_PKSR24, + 0, + Opcode_ae_pksr24_encode_fns, 0, 0 }, + { "ae_pksrf32", ICLASS_AE_PKSRF32, + 0, + Opcode_ae_pksrf32_encode_fns, 0, 0 }, + { "ae_pksr16", ICLASS_AE_PKSR16, + 0, + Opcode_ae_pksr16_encode_fns, 0, 0 }, + { "ae_trunca16p24s.l", ICLASS_AE_TRUNCA16P24S_L, + 0, + Opcode_ae_trunca16p24s_l_encode_fns, 0, 0 }, + { "ae_trunca16p24s.h", ICLASS_AE_TRUNCA16P24S_H, + 0, + Opcode_ae_trunca16p24s_h_encode_fns, 0, 0 }, + { "ae_add32", ICLASS_AE_ADD32, + 0, + Opcode_ae_add32_encode_fns, 0, 0 }, + { "ae_sub32", ICLASS_AE_SUB32, + 0, + Opcode_ae_sub32_encode_fns, 0, 0 }, + { "ae_addsub32", ICLASS_AE_ADDSUB32, + 0, + Opcode_ae_addsub32_encode_fns, 0, 0 }, + { "ae_subadd32", ICLASS_AE_SUBADD32, + 0, + Opcode_ae_subadd32_encode_fns, 0, 0 }, + { "ae_add16", ICLASS_AE_ADD16, + 0, + Opcode_ae_add16_encode_fns, 0, 0 }, + { "ae_sub16", ICLASS_AE_SUB16, + 0, + Opcode_ae_sub16_encode_fns, 0, 0 }, + { "ae_add32_hl_lh", ICLASS_AE_ADD32_HL_LH, + 0, + Opcode_ae_add32_hl_lh_encode_fns, 0, 0 }, + { "ae_addsub32_hl_lh", ICLASS_AE_ADDSUB32_HL_LH, + 0, + Opcode_ae_addsub32_hl_lh_encode_fns, 0, 0 }, + { "ae_neg32", ICLASS_AE_NEG32, + 0, + Opcode_ae_neg32_encode_fns, 0, 0 }, + { "ae_abs32", ICLASS_AE_ABS32, + 0, + Opcode_ae_abs32_encode_fns, 0, 0 }, + { "ae_neg32_l", ICLASS_AE_NEG32_L, + 0, + Opcode_ae_neg32_l_encode_fns, 0, 0 }, + { "ae_add24s", ICLASS_AE_ADD24S, + 0, + Opcode_ae_add24s_encode_fns, 0, 0 }, + { "ae_sub24s", ICLASS_AE_SUB24S, + 0, + Opcode_ae_sub24s_encode_fns, 0, 0 }, + { "ae_add32s", ICLASS_AE_ADD32S, + 0, + Opcode_ae_add32s_encode_fns, 0, 0 }, + { "ae_sub32s", ICLASS_AE_SUB32S, + 0, + Opcode_ae_sub32s_encode_fns, 0, 0 }, + { "ae_addsub32s", ICLASS_AE_ADDSUB32S, + 0, + Opcode_ae_addsub32s_encode_fns, 0, 0 }, + { "ae_subadd32s", ICLASS_AE_SUBADD32S, + 0, + Opcode_ae_subadd32s_encode_fns, 0, 0 }, + { "ae_add16s", ICLASS_AE_ADD16S, + 0, + Opcode_ae_add16s_encode_fns, 0, 0 }, + { "ae_sub16s", ICLASS_AE_SUB16S, + 0, + Opcode_ae_sub16s_encode_fns, 0, 0 }, + { "ae_add32s_hl_lh", ICLASS_AE_ADD32S_HL_LH, + 0, + Opcode_ae_add32s_hl_lh_encode_fns, 0, 0 }, + { "ae_addsub32s_hl_lh", ICLASS_AE_ADDSUB32S_HL_LH, + 0, + Opcode_ae_addsub32s_hl_lh_encode_fns, 0, 0 }, + { "ae_neg24s", ICLASS_AE_NEG24S, + 0, + Opcode_ae_neg24s_encode_fns, 0, 0 }, + { "ae_abs24s", ICLASS_AE_ABS24S, + 0, + Opcode_ae_abs24s_encode_fns, 0, 0 }, + { "ae_neg32s", ICLASS_AE_NEG32S, + 0, + Opcode_ae_neg32s_encode_fns, 0, 0 }, + { "ae_abs32s", ICLASS_AE_ABS32S, + 0, + Opcode_ae_abs32s_encode_fns, 0, 0 }, + { "ae_neg16s", ICLASS_AE_NEG16S, + 0, + Opcode_ae_neg16s_encode_fns, 0, 0 }, + { "ae_abs16s", ICLASS_AE_ABS16S, + 0, + Opcode_ae_abs16s_encode_fns, 0, 0 }, + { "ae_abs16", ICLASS_AE_ABS16, + 0, + Opcode_ae_abs16_encode_fns, 0, 0 }, + { "ae_mulc16js.h", ICLASS_AE_MULC16JS_H, + 0, + Opcode_ae_mulc16js_h_encode_fns, 0, 0 }, + { "ae_mulc16js.l", ICLASS_AE_MULC16JS_L, + 0, + Opcode_ae_mulc16js_l_encode_fns, 0, 0 }, + { "ae_mulac16js.h", ICLASS_AE_MULAC16JS_H, + 0, + Opcode_ae_mulac16js_h_encode_fns, 0, 0 }, + { "ae_mulac16js.l", ICLASS_AE_MULAC16JS_L, + 0, + Opcode_ae_mulac16js_l_encode_fns, 0, 0 }, + { "ae_lt16", ICLASS_AE_LT16, + 0, + Opcode_ae_lt16_encode_fns, 0, 0 }, + { "ae_le16", ICLASS_AE_LE16, + 0, + Opcode_ae_le16_encode_fns, 0, 0 }, + { "ae_eq16", ICLASS_AE_EQ16, + 0, + Opcode_ae_eq16_encode_fns, 0, 0 }, + { "ae_lt32", ICLASS_AE_LT32, + 0, + Opcode_ae_lt32_encode_fns, 0, 0 }, + { "ae_le32", ICLASS_AE_LE32, + 0, + Opcode_ae_le32_encode_fns, 0, 0 }, + { "ae_eq32", ICLASS_AE_EQ32, + 0, + Opcode_ae_eq32_encode_fns, 0, 0 }, + { "ae_min32", ICLASS_AE_MIN32, + 0, + Opcode_ae_min32_encode_fns, 0, 0 }, + { "ae_max32", ICLASS_AE_MAX32, + 0, + Opcode_ae_max32_encode_fns, 0, 0 }, + { "ae_minmax32", ICLASS_AE_MINMAX32, + 0, + Opcode_ae_minmax32_encode_fns, 0, 0 }, + { "ae_minmax16", ICLASS_AE_MINMAX16, + 0, + Opcode_ae_minmax16_encode_fns, 0, 0 }, + { "ae_min16", ICLASS_AE_MIN16, + 0, + Opcode_ae_min16_encode_fns, 0, 0 }, + { "ae_max16", ICLASS_AE_MAX16, + 0, + Opcode_ae_max16_encode_fns, 0, 0 }, + { "ae_add64", ICLASS_AE_ADD64, + 0, + Opcode_ae_add64_encode_fns, 0, 0 }, + { "ae_sub64", ICLASS_AE_SUB64, + 0, + Opcode_ae_sub64_encode_fns, 0, 0 }, + { "ae_neg64", ICLASS_AE_NEG64, + 0, + Opcode_ae_neg64_encode_fns, 0, 0 }, + { "ae_abs64", ICLASS_AE_ABS64, + 0, + Opcode_ae_abs64_encode_fns, 0, 0 }, + { "ae_addsq56s", ICLASS_AE_ADDSQ56S, + 0, + Opcode_ae_addsq56s_encode_fns, 0, 0 }, + { "ae_subsq56s", ICLASS_AE_SUBSQ56S, + 0, + Opcode_ae_subsq56s_encode_fns, 0, 0 }, + { "ae_add64s", ICLASS_AE_ADD64S, + 0, + Opcode_ae_add64s_encode_fns, 0, 0 }, + { "ae_sub64s", ICLASS_AE_SUB64S, + 0, + Opcode_ae_sub64s_encode_fns, 0, 0 }, + { "ae_negsq56s", ICLASS_AE_NEGSQ56S, + 0, + Opcode_ae_negsq56s_encode_fns, 0, 0 }, + { "ae_abssq56s", ICLASS_AE_ABSSQ56S, + 0, + Opcode_ae_abssq56s_encode_fns, 0, 0 }, + { "ae_neg64s", ICLASS_AE_NEG64S, + 0, + Opcode_ae_neg64s_encode_fns, 0, 0 }, + { "ae_abs64s", ICLASS_AE_ABS64S, + 0, + Opcode_ae_abs64s_encode_fns, 0, 0 }, + { "ae_and", ICLASS_AE_AND, + 0, + Opcode_ae_and_encode_fns, 0, 0 }, + { "ae_nand", ICLASS_AE_NAND, + 0, + Opcode_ae_nand_encode_fns, 0, 0 }, + { "ae_or", ICLASS_AE_OR, + 0, + Opcode_ae_or_encode_fns, 0, 0 }, + { "ae_xor", ICLASS_AE_XOR, + 0, + Opcode_ae_xor_encode_fns, 0, 0 }, + { "ae_slai24", ICLASS_AE_SLAI24, + 0, + Opcode_ae_slai24_encode_fns, 0, 0 }, + { "ae_srli24", ICLASS_AE_SRLI24, + 0, + Opcode_ae_srli24_encode_fns, 0, 0 }, + { "ae_srai24", ICLASS_AE_SRAI24, + 0, + Opcode_ae_srai24_encode_fns, 0, 0 }, + { "ae_slas24", ICLASS_AE_SLAS24, + 0, + Opcode_ae_slas24_encode_fns, 0, 0 }, + { "ae_srls24", ICLASS_AE_SRLS24, + 0, + Opcode_ae_srls24_encode_fns, 0, 0 }, + { "ae_sras24", ICLASS_AE_SRAS24, + 0, + Opcode_ae_sras24_encode_fns, 0, 0 }, + { "ae_srai16", ICLASS_AE_SRAI16, + 0, + Opcode_ae_srai16_encode_fns, 0, 0 }, + { "ae_srai16r", ICLASS_AE_SRAI16R, + 0, + Opcode_ae_srai16r_encode_fns, 0, 0 }, + { "ae_slai32", ICLASS_AE_SLAI32, + 0, + Opcode_ae_slai32_encode_fns, 0, 0 }, + { "ae_srli32", ICLASS_AE_SRLI32, + 0, + Opcode_ae_srli32_encode_fns, 0, 0 }, + { "ae_srai32", ICLASS_AE_SRAI32, + 0, + Opcode_ae_srai32_encode_fns, 0, 0 }, + { "ae_srai32r", ICLASS_AE_SRAI32R, + 0, + Opcode_ae_srai32r_encode_fns, 0, 0 }, + { "ae_slas32", ICLASS_AE_SLAS32, + 0, + Opcode_ae_slas32_encode_fns, 0, 0 }, + { "ae_srls32", ICLASS_AE_SRLS32, + 0, + Opcode_ae_srls32_encode_fns, 0, 0 }, + { "ae_sras32", ICLASS_AE_SRAS32, + 0, + Opcode_ae_sras32_encode_fns, 0, 0 }, + { "ae_slaa32", ICLASS_AE_SLAA32, + 0, + Opcode_ae_slaa32_encode_fns, 0, 0 }, + { "ae_srla32", ICLASS_AE_SRLA32, + 0, + Opcode_ae_srla32_encode_fns, 0, 0 }, + { "ae_sraa32", ICLASS_AE_SRAA32, + 0, + Opcode_ae_sraa32_encode_fns, 0, 0 }, + { "ae_slai16s", ICLASS_AE_SLAI16S, + 0, + Opcode_ae_slai16s_encode_fns, 0, 0 }, + { "ae_slaa16s", ICLASS_AE_SLAA16S, + 0, + Opcode_ae_slaa16s_encode_fns, 0, 0 }, + { "ae_sraa16s", ICLASS_AE_SRAA16S, + 0, + Opcode_ae_sraa16s_encode_fns, 0, 0 }, + { "ae_sraa16rs", ICLASS_AE_SRAA16RS, + 0, + Opcode_ae_sraa16rs_encode_fns, 0, 0 }, + { "ae_slai24s", ICLASS_AE_SLAI24S, + 0, + Opcode_ae_slai24s_encode_fns, 0, 0 }, + { "ae_slas24s", ICLASS_AE_SLAS24S, + 0, + Opcode_ae_slas24s_encode_fns, 0, 0 }, + { "ae_slai32s", ICLASS_AE_SLAI32S, + 0, + Opcode_ae_slai32s_encode_fns, 0, 0 }, + { "ae_slas32s", ICLASS_AE_SLAS32S, + 0, + Opcode_ae_slas32s_encode_fns, 0, 0 }, + { "ae_slaa32s", ICLASS_AE_SLAA32S, + 0, + Opcode_ae_slaa32s_encode_fns, 0, 0 }, + { "ae_sraa32s", ICLASS_AE_SRAA32S, + 0, + Opcode_ae_sraa32s_encode_fns, 0, 0 }, + { "ae_sraa32rs", ICLASS_AE_SRAA32RS, + 0, + Opcode_ae_sraa32rs_encode_fns, 0, 0 }, + { "ae_slasq56", ICLASS_AE_SLASQ56, + 0, + Opcode_ae_slasq56_encode_fns, 0, 0 }, + { "ae_srlsq56", ICLASS_AE_SRLSQ56, + 0, + Opcode_ae_srlsq56_encode_fns, 0, 0 }, + { "ae_srasq56", ICLASS_AE_SRASQ56, + 0, + Opcode_ae_srasq56_encode_fns, 0, 0 }, + { "ae_slaaq56", ICLASS_AE_SLAAQ56, + 0, + Opcode_ae_slaaq56_encode_fns, 0, 0 }, + { "ae_srlaq56", ICLASS_AE_SRLAQ56, + 0, + Opcode_ae_srlaq56_encode_fns, 0, 0 }, + { "ae_sraaq56", ICLASS_AE_SRAAQ56, + 0, + Opcode_ae_sraaq56_encode_fns, 0, 0 }, + { "ae_slai64", ICLASS_AE_SLAI64, + 0, + Opcode_ae_slai64_encode_fns, 0, 0 }, + { "ae_srli64", ICLASS_AE_SRLI64, + 0, + Opcode_ae_srli64_encode_fns, 0, 0 }, + { "ae_srai64", ICLASS_AE_SRAI64, + 0, + Opcode_ae_srai64_encode_fns, 0, 0 }, + { "ae_slas64", ICLASS_AE_SLAS64, + 0, + Opcode_ae_slas64_encode_fns, 0, 0 }, + { "ae_srls64", ICLASS_AE_SRLS64, + 0, + Opcode_ae_srls64_encode_fns, 0, 0 }, + { "ae_sras64", ICLASS_AE_SRAS64, + 0, + Opcode_ae_sras64_encode_fns, 0, 0 }, + { "ae_slaa64", ICLASS_AE_SLAA64, + 0, + Opcode_ae_slaa64_encode_fns, 0, 0 }, + { "ae_srla64", ICLASS_AE_SRLA64, + 0, + Opcode_ae_srla64_encode_fns, 0, 0 }, + { "ae_sraa64", ICLASS_AE_SRAA64, + 0, + Opcode_ae_sraa64_encode_fns, 0, 0 }, + { "ae_slaisq56s", ICLASS_AE_SLAISQ56S, + 0, + Opcode_ae_slaisq56s_encode_fns, 0, 0 }, + { "ae_slassq56s", ICLASS_AE_SLASSQ56S, + 0, + Opcode_ae_slassq56s_encode_fns, 0, 0 }, + { "ae_slaasq56s", ICLASS_AE_SLAASQ56S, + 0, + Opcode_ae_slaasq56s_encode_fns, 0, 0 }, + { "ae_slai64s", ICLASS_AE_SLAI64S, + 0, + Opcode_ae_slai64s_encode_fns, 0, 0 }, + { "ae_slas64s", ICLASS_AE_SLAS64S, + 0, + Opcode_ae_slas64s_encode_fns, 0, 0 }, + { "ae_slaa64s", ICLASS_AE_SLAA64S, + 0, + Opcode_ae_slaa64s_encode_fns, 0, 0 }, + { "ae_lt64", ICLASS_AE_LT64, + 0, + Opcode_ae_lt64_encode_fns, 0, 0 }, + { "ae_le64", ICLASS_AE_LE64, + 0, + Opcode_ae_le64_encode_fns, 0, 0 }, + { "ae_eq64", ICLASS_AE_EQ64, + 0, + Opcode_ae_eq64_encode_fns, 0, 0 }, + { "ae_max64", ICLASS_AE_MAX64, + 0, + Opcode_ae_max64_encode_fns, 0, 0 }, + { "ae_min64", ICLASS_AE_MIN64, + 0, + Opcode_ae_min64_encode_fns, 0, 0 }, + { "ae_nsa64", ICLASS_AE_NSA64, + 0, + Opcode_ae_nsa64_encode_fns, 0, 0 }, + { "ae_nsaz16.0", ICLASS_AE_NSAZ16_0, + 0, + Opcode_ae_nsaz16_0_encode_fns, 0, 0 }, + { "ae_nsaz32.l", ICLASS_AE_NSAZ32_L, + 0, + Opcode_ae_nsaz32_l_encode_fns, 0, 0 }, + { "ae_muls32f48p16s.ll", ICLASS_AE_MULS32F48P16S_LL, + 0, + Opcode_ae_muls32f48p16s_ll_encode_fns, 0, 0 }, + { "ae_mulf32s.ll", ICLASS_AE_MULF32S_LL, + 0, + Opcode_ae_mulf32s_ll_encode_fns, 0, 0 }, + { "ae_mul32.ll", ICLASS_AE_MUL32_LL, + 0, + Opcode_ae_mul32_ll_encode_fns, 0, 0 }, + { "ae_mulf32r.ll", ICLASS_AE_MULF32R_LL, + 0, + Opcode_ae_mulf32r_ll_encode_fns, 0, 0 }, + { "ae_mulf32ra.ll", ICLASS_AE_MULF32RA_LL, + 0, + Opcode_ae_mulf32ra_ll_encode_fns, 0, 0 }, + { "ae_muls32f48p16s.lh", ICLASS_AE_MULS32F48P16S_LH, + 0, + Opcode_ae_muls32f48p16s_lh_encode_fns, 0, 0 }, + { "ae_mulf32s.lh", ICLASS_AE_MULF32S_LH, + 0, + Opcode_ae_mulf32s_lh_encode_fns, 0, 0 }, + { "ae_mul32.lh", ICLASS_AE_MUL32_LH, + 0, + Opcode_ae_mul32_lh_encode_fns, 0, 0 }, + { "ae_mulf32r.lh", ICLASS_AE_MULF32R_LH, + 0, + Opcode_ae_mulf32r_lh_encode_fns, 0, 0 }, + { "ae_mulf32ra.lh", ICLASS_AE_MULF32RA_LH, + 0, + Opcode_ae_mulf32ra_lh_encode_fns, 0, 0 }, + { "ae_muls32f48p16s.hh", ICLASS_AE_MULS32F48P16S_HH, + 0, + Opcode_ae_muls32f48p16s_hh_encode_fns, 0, 0 }, + { "ae_mulf32s.hh", ICLASS_AE_MULF32S_HH, + 0, + Opcode_ae_mulf32s_hh_encode_fns, 0, 0 }, + { "ae_mul32.hh", ICLASS_AE_MUL32_HH, + 0, + Opcode_ae_mul32_hh_encode_fns, 0, 0 }, + { "ae_mulf32r.hh", ICLASS_AE_MULF32R_HH, + 0, + Opcode_ae_mulf32r_hh_encode_fns, 0, 0 }, + { "ae_mulf32ra.hh", ICLASS_AE_MULF32RA_HH, + 0, + Opcode_ae_mulf32ra_hh_encode_fns, 0, 0 }, + { "ae_mulas32f48p16s.ll", ICLASS_AE_MULAS32F48P16S_LL, + 0, + Opcode_ae_mulas32f48p16s_ll_encode_fns, 0, 0 }, + { "ae_mulaf32s.ll", ICLASS_AE_MULAF32S_LL, + 0, + Opcode_ae_mulaf32s_ll_encode_fns, 0, 0 }, + { "ae_mula32.ll", ICLASS_AE_MULA32_LL, + 0, + Opcode_ae_mula32_ll_encode_fns, 0, 0 }, + { "ae_mulaf32r.ll", ICLASS_AE_MULAF32R_LL, + 0, + Opcode_ae_mulaf32r_ll_encode_fns, 0, 0 }, + { "ae_mulaf32ra.ll", ICLASS_AE_MULAF32RA_LL, + 0, + Opcode_ae_mulaf32ra_ll_encode_fns, 0, 0 }, + { "ae_mulas32f48p16s.lh", ICLASS_AE_MULAS32F48P16S_LH, + 0, + Opcode_ae_mulas32f48p16s_lh_encode_fns, 0, 0 }, + { "ae_mulaf32s.lh", ICLASS_AE_MULAF32S_LH, + 0, + Opcode_ae_mulaf32s_lh_encode_fns, 0, 0 }, + { "ae_mula32.lh", ICLASS_AE_MULA32_LH, + 0, + Opcode_ae_mula32_lh_encode_fns, 0, 0 }, + { "ae_mulaf32r.lh", ICLASS_AE_MULAF32R_LH, + 0, + Opcode_ae_mulaf32r_lh_encode_fns, 0, 0 }, + { "ae_mulaf32ra.lh", ICLASS_AE_MULAF32RA_LH, + 0, + Opcode_ae_mulaf32ra_lh_encode_fns, 0, 0 }, + { "ae_mulas32f48p16s.hh", ICLASS_AE_MULAS32F48P16S_HH, + 0, + Opcode_ae_mulas32f48p16s_hh_encode_fns, 0, 0 }, + { "ae_mulaf32s.hh", ICLASS_AE_MULAF32S_HH, + 0, + Opcode_ae_mulaf32s_hh_encode_fns, 0, 0 }, + { "ae_mula32.hh", ICLASS_AE_MULA32_HH, + 0, + Opcode_ae_mula32_hh_encode_fns, 0, 0 }, + { "ae_mulaf32r.hh", ICLASS_AE_MULAF32R_HH, + 0, + Opcode_ae_mulaf32r_hh_encode_fns, 0, 0 }, + { "ae_mulaf32ra.hh", ICLASS_AE_MULAF32RA_HH, + 0, + Opcode_ae_mulaf32ra_hh_encode_fns, 0, 0 }, + { "ae_mulss32f48p16s.ll", ICLASS_AE_MULSS32F48P16S_LL, + 0, + Opcode_ae_mulss32f48p16s_ll_encode_fns, 0, 0 }, + { "ae_mulsf32s.ll", ICLASS_AE_MULSF32S_LL, + 0, + Opcode_ae_mulsf32s_ll_encode_fns, 0, 0 }, + { "ae_muls32.ll", ICLASS_AE_MULS32_LL, + 0, + Opcode_ae_muls32_ll_encode_fns, 0, 0 }, + { "ae_mulsf32r.ll", ICLASS_AE_MULSF32R_LL, + 0, + Opcode_ae_mulsf32r_ll_encode_fns, 0, 0 }, + { "ae_mulsf32ra.ll", ICLASS_AE_MULSF32RA_LL, + 0, + Opcode_ae_mulsf32ra_ll_encode_fns, 0, 0 }, + { "ae_mulss32f48p16s.lh", ICLASS_AE_MULSS32F48P16S_LH, + 0, + Opcode_ae_mulss32f48p16s_lh_encode_fns, 0, 0 }, + { "ae_mulsf32s.lh", ICLASS_AE_MULSF32S_LH, + 0, + Opcode_ae_mulsf32s_lh_encode_fns, 0, 0 }, + { "ae_muls32.lh", ICLASS_AE_MULS32_LH, + 0, + Opcode_ae_muls32_lh_encode_fns, 0, 0 }, + { "ae_mulsf32r.lh", ICLASS_AE_MULSF32R_LH, + 0, + Opcode_ae_mulsf32r_lh_encode_fns, 0, 0 }, + { "ae_mulsf32ra.lh", ICLASS_AE_MULSF32RA_LH, + 0, + Opcode_ae_mulsf32ra_lh_encode_fns, 0, 0 }, + { "ae_mulss32f48p16s.hh", ICLASS_AE_MULSS32F48P16S_HH, + 0, + Opcode_ae_mulss32f48p16s_hh_encode_fns, 0, 0 }, + { "ae_mulsf32s.hh", ICLASS_AE_MULSF32S_HH, + 0, + Opcode_ae_mulsf32s_hh_encode_fns, 0, 0 }, + { "ae_muls32.hh", ICLASS_AE_MULS32_HH, + 0, + Opcode_ae_muls32_hh_encode_fns, 0, 0 }, + { "ae_mulsf32r.hh", ICLASS_AE_MULSF32R_HH, + 0, + Opcode_ae_mulsf32r_hh_encode_fns, 0, 0 }, + { "ae_mulsf32ra.hh", ICLASS_AE_MULSF32RA_HH, + 0, + Opcode_ae_mulsf32ra_hh_encode_fns, 0, 0 }, + { "ae_mul32u.ll", ICLASS_AE_MUL32U_LL, + 0, + Opcode_ae_mul32u_ll_encode_fns, 0, 0 }, + { "ae_mula32u.ll", ICLASS_AE_MULA32U_LL, + 0, + Opcode_ae_mula32u_ll_encode_fns, 0, 0 }, + { "ae_muls32u.ll", ICLASS_AE_MULS32U_LL, + 0, + Opcode_ae_muls32u_ll_encode_fns, 0, 0 }, + { "ae_mulf16ss.33", ICLASS_AE_MULF16SS_33, + 0, + Opcode_ae_mulf16ss_33_encode_fns, 0, 0 }, + { "ae_mulf16ss.22", ICLASS_AE_MULF16SS_22, + 0, + Opcode_ae_mulf16ss_22_encode_fns, 0, 0 }, + { "ae_mulf16ss.32", ICLASS_AE_MULF16SS_32, + 0, + Opcode_ae_mulf16ss_32_encode_fns, 0, 0 }, + { "ae_mulf16ss.21", ICLASS_AE_MULF16SS_21, + 0, + Opcode_ae_mulf16ss_21_encode_fns, 0, 0 }, + { "ae_mulf16ss.31", ICLASS_AE_MULF16SS_31, + 0, + Opcode_ae_mulf16ss_31_encode_fns, 0, 0 }, + { "ae_mulf16ss.30", ICLASS_AE_MULF16SS_30, + 0, + Opcode_ae_mulf16ss_30_encode_fns, 0, 0 }, + { "ae_mulf16ss.10", ICLASS_AE_MULF16SS_10, + 0, + Opcode_ae_mulf16ss_10_encode_fns, 0, 0 }, + { "ae_mulf16ss.20", ICLASS_AE_MULF16SS_20, + 0, + Opcode_ae_mulf16ss_20_encode_fns, 0, 0 }, + { "ae_mulf16ss.11", ICLASS_AE_MULF16SS_11, + 0, + Opcode_ae_mulf16ss_11_encode_fns, 0, 0 }, + { "ae_mulf16ss.00", ICLASS_AE_MULF16SS_00, + 0, + Opcode_ae_mulf16ss_00_encode_fns, 0, 0 }, + { "ae_mulsf16ss.33", ICLASS_AE_MULSF16SS_33, + 0, + Opcode_ae_mulsf16ss_33_encode_fns, 0, 0 }, + { "ae_mulsf16ss.22", ICLASS_AE_MULSF16SS_22, + 0, + Opcode_ae_mulsf16ss_22_encode_fns, 0, 0 }, + { "ae_mulsf16ss.32", ICLASS_AE_MULSF16SS_32, + 0, + Opcode_ae_mulsf16ss_32_encode_fns, 0, 0 }, + { "ae_mulsf16ss.21", ICLASS_AE_MULSF16SS_21, + 0, + Opcode_ae_mulsf16ss_21_encode_fns, 0, 0 }, + { "ae_mulsf16ss.31", ICLASS_AE_MULSF16SS_31, + 0, + Opcode_ae_mulsf16ss_31_encode_fns, 0, 0 }, + { "ae_mulsf16ss.30", ICLASS_AE_MULSF16SS_30, + 0, + Opcode_ae_mulsf16ss_30_encode_fns, 0, 0 }, + { "ae_mulsf16ss.10", ICLASS_AE_MULSF16SS_10, + 0, + Opcode_ae_mulsf16ss_10_encode_fns, 0, 0 }, + { "ae_mulsf16ss.20", ICLASS_AE_MULSF16SS_20, + 0, + Opcode_ae_mulsf16ss_20_encode_fns, 0, 0 }, + { "ae_mulsf16ss.11", ICLASS_AE_MULSF16SS_11, + 0, + Opcode_ae_mulsf16ss_11_encode_fns, 0, 0 }, + { "ae_mulsf16ss.00", ICLASS_AE_MULSF16SS_00, + 0, + Opcode_ae_mulsf16ss_00_encode_fns, 0, 0 }, + { "ae_mulaf16ss.33", ICLASS_AE_MULAF16SS_33, + 0, + Opcode_ae_mulaf16ss_33_encode_fns, 0, 0 }, + { "ae_mulaf16ss.22", ICLASS_AE_MULAF16SS_22, + 0, + Opcode_ae_mulaf16ss_22_encode_fns, 0, 0 }, + { "ae_mulaf16ss.32", ICLASS_AE_MULAF16SS_32, + 0, + Opcode_ae_mulaf16ss_32_encode_fns, 0, 0 }, + { "ae_mulaf16ss.21", ICLASS_AE_MULAF16SS_21, + 0, + Opcode_ae_mulaf16ss_21_encode_fns, 0, 0 }, + { "ae_mulaf16ss.31", ICLASS_AE_MULAF16SS_31, + 0, + Opcode_ae_mulaf16ss_31_encode_fns, 0, 0 }, + { "ae_mulaf16ss.30", ICLASS_AE_MULAF16SS_30, + 0, + Opcode_ae_mulaf16ss_30_encode_fns, 0, 0 }, + { "ae_mulaf16ss.10", ICLASS_AE_MULAF16SS_10, + 0, + Opcode_ae_mulaf16ss_10_encode_fns, 0, 0 }, + { "ae_mulaf16ss.20", ICLASS_AE_MULAF16SS_20, + 0, + Opcode_ae_mulaf16ss_20_encode_fns, 0, 0 }, + { "ae_mulaf16ss.11", ICLASS_AE_MULAF16SS_11, + 0, + Opcode_ae_mulaf16ss_11_encode_fns, 0, 0 }, + { "ae_mulaf16ss.00", ICLASS_AE_MULAF16SS_00, + 0, + Opcode_ae_mulaf16ss_00_encode_fns, 0, 0 }, + { "ae_mul16s.00", ICLASS_AE_MUL16S_00, + 0, + Opcode_ae_mul16s_00_encode_fns, 0, 0 }, + { "ae_mula16s.00", ICLASS_AE_MULA16S_00, + 0, + Opcode_ae_mula16s_00_encode_fns, 0, 0 }, + { "ae_muls16s.00", ICLASS_AE_MULS16S_00, + 0, + Opcode_ae_muls16s_00_encode_fns, 0, 0 }, + { "ae_mulaafd16ss.33_22", ICLASS_AE_MULAAFD16SS_33_22, + 0, + Opcode_ae_mulaafd16ss_33_22_encode_fns, 0, 0 }, + { "ae_mulaafd16ss.13_02", ICLASS_AE_MULAAFD16SS_13_02, + 0, + Opcode_ae_mulaafd16ss_13_02_encode_fns, 0, 0 }, + { "ae_mulaafd16ss.11_00", ICLASS_AE_MULAAFD16SS_11_00, + 0, + Opcode_ae_mulaafd16ss_11_00_encode_fns, 0, 0 }, + { "ae_mulssfd16ss.33_22", ICLASS_AE_MULSSFD16SS_33_22, + 0, + Opcode_ae_mulssfd16ss_33_22_encode_fns, 0, 0 }, + { "ae_mulssfd16ss.13_02", ICLASS_AE_MULSSFD16SS_13_02, + 0, + Opcode_ae_mulssfd16ss_13_02_encode_fns, 0, 0 }, + { "ae_mulssfd16ss.11_00", ICLASS_AE_MULSSFD16SS_11_00, + 0, + Opcode_ae_mulssfd16ss_11_00_encode_fns, 0, 0 }, + { "ae_mulzaafd16ss.33_22", ICLASS_AE_MULZAAFD16SS_33_22, + 0, + Opcode_ae_mulzaafd16ss_33_22_encode_fns, 0, 0 }, + { "ae_mulzaafd16ss.13_02", ICLASS_AE_MULZAAFD16SS_13_02, + 0, + Opcode_ae_mulzaafd16ss_13_02_encode_fns, 0, 0 }, + { "ae_mulzaafd16ss.11_00", ICLASS_AE_MULZAAFD16SS_11_00, + 0, + Opcode_ae_mulzaafd16ss_11_00_encode_fns, 0, 0 }, + { "ae_mulzssfd16ss.33_22", ICLASS_AE_MULZSSFD16SS_33_22, + 0, + Opcode_ae_mulzssfd16ss_33_22_encode_fns, 0, 0 }, + { "ae_mulzssfd16ss.13_02", ICLASS_AE_MULZSSFD16SS_13_02, + 0, + Opcode_ae_mulzssfd16ss_13_02_encode_fns, 0, 0 }, + { "ae_mulzssfd16ss.11_00", ICLASS_AE_MULZSSFD16SS_11_00, + 0, + Opcode_ae_mulzssfd16ss_11_00_encode_fns, 0, 0 }, + { "ae_mulf48q32sp16s.l", ICLASS_AE_MULF48Q32SP16S_L, + 0, + Opcode_ae_mulf48q32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulf48q32sp16u.l", ICLASS_AE_MULF48Q32SP16U_L, + 0, + Opcode_ae_mulf48q32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulq32sp16s.l", ICLASS_AE_MULQ32SP16S_L, + 0, + Opcode_ae_mulq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulq32sp16u.l", ICLASS_AE_MULQ32SP16U_L, + 0, + Opcode_ae_mulq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulaf48q32sp16s.l", ICLASS_AE_MULAF48Q32SP16S_L, + 0, + Opcode_ae_mulaf48q32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulaf48q32sp16u.l", ICLASS_AE_MULAF48Q32SP16U_L, + 0, + Opcode_ae_mulaf48q32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulaq32sp16s.l", ICLASS_AE_MULAQ32SP16S_L, + 0, + Opcode_ae_mulaq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulaq32sp16u.l", ICLASS_AE_MULAQ32SP16U_L, + 0, + Opcode_ae_mulaq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulsf48q32sp16s.l", ICLASS_AE_MULSF48Q32SP16S_L, + 0, + Opcode_ae_mulsf48q32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulsf48q32sp16u.l", ICLASS_AE_MULSF48Q32SP16U_L, + 0, + Opcode_ae_mulsf48q32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulsq32sp16s.l", ICLASS_AE_MULSQ32SP16S_L, + 0, + Opcode_ae_mulsq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulsq32sp16u.l", ICLASS_AE_MULSQ32SP16U_L, + 0, + Opcode_ae_mulsq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulfp24x2ra", ICLASS_AE_MULFP24X2RA, + 0, + Opcode_ae_mulfp24x2ra_encode_fns, 0, 0 }, + { "ae_mulfp24x2r", ICLASS_AE_MULFP24X2R, + 0, + Opcode_ae_mulfp24x2r_encode_fns, 0, 0 }, + { "ae_mulafp24x2ra", ICLASS_AE_MULAFP24X2RA, + 0, + Opcode_ae_mulafp24x2ra_encode_fns, 0, 0 }, + { "ae_mulafp24x2r", ICLASS_AE_MULAFP24X2R, + 0, + Opcode_ae_mulafp24x2r_encode_fns, 0, 0 }, + { "ae_mulsfp24x2ra", ICLASS_AE_MULSFP24X2RA, + 0, + Opcode_ae_mulsfp24x2ra_encode_fns, 0, 0 }, + { "ae_mulsfp24x2r", ICLASS_AE_MULSFP24X2R, + 0, + Opcode_ae_mulsfp24x2r_encode_fns, 0, 0 }, + { "ae_mulzaafd32s.hh.ll", ICLASS_AE_MULZAAFD32S_HH_LL, + 0, + Opcode_ae_mulzaafd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaafd32ra.hh.ll", ICLASS_AE_MULZAAFD32RA_HH_LL, + 0, + Opcode_ae_mulzaafd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaad32.hh.ll", ICLASS_AE_MULZAAD32_HH_LL, + 0, + Opcode_ae_mulzaad32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaafd32s.hl.lh", ICLASS_AE_MULZAAFD32S_HL_LH, + 0, + Opcode_ae_mulzaafd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaafd32ra.hl.lh", ICLASS_AE_MULZAAFD32RA_HL_LH, + 0, + Opcode_ae_mulzaafd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaad32.hl.lh", ICLASS_AE_MULZAAD32_HL_LH, + 0, + Opcode_ae_mulzaad32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasfd32s.hh.ll", ICLASS_AE_MULZASFD32S_HH_LL, + 0, + Opcode_ae_mulzasfd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasfd32ra.hh.ll", ICLASS_AE_MULZASFD32RA_HH_LL, + 0, + Opcode_ae_mulzasfd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasd32.hh.ll", ICLASS_AE_MULZASD32_HH_LL, + 0, + Opcode_ae_mulzasd32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasfd32s.hl.lh", ICLASS_AE_MULZASFD32S_HL_LH, + 0, + Opcode_ae_mulzasfd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasfd32ra.hl.lh", ICLASS_AE_MULZASFD32RA_HL_LH, + 0, + Opcode_ae_mulzasfd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasd32.hl.lh", ICLASS_AE_MULZASD32_HL_LH, + 0, + Opcode_ae_mulzasd32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzsafd32s.hh.ll", ICLASS_AE_MULZSAFD32S_HH_LL, + 0, + Opcode_ae_mulzsafd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsafd32ra.hh.ll", ICLASS_AE_MULZSAFD32RA_HH_LL, + 0, + Opcode_ae_mulzsafd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsad32.hh.ll", ICLASS_AE_MULZSAD32_HH_LL, + 0, + Opcode_ae_mulzsad32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssfd32s.hh.ll", ICLASS_AE_MULZSSFD32S_HH_LL, + 0, + Opcode_ae_mulzssfd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssfd32ra.hh.ll", ICLASS_AE_MULZSSFD32RA_HH_LL, + 0, + Opcode_ae_mulzssfd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssd32.hh.ll", ICLASS_AE_MULZSSD32_HH_LL, + 0, + Opcode_ae_mulzssd32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssfd32s.hl.lh", ICLASS_AE_MULZSSFD32S_HL_LH, + 0, + Opcode_ae_mulzssfd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssfd32ra.hl.lh", ICLASS_AE_MULZSSFD32RA_HL_LH, + 0, + Opcode_ae_mulzssfd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssd32.hl.lh", ICLASS_AE_MULZSSD32_HL_LH, + 0, + Opcode_ae_mulzssd32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaafd32s.hh.ll", ICLASS_AE_MULAAFD32S_HH_LL, + 0, + Opcode_ae_mulaafd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaafd32ra.hh.ll", ICLASS_AE_MULAAFD32RA_HH_LL, + 0, + Opcode_ae_mulaafd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaad32.hh.ll", ICLASS_AE_MULAAD32_HH_LL, + 0, + Opcode_ae_mulaad32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaafd32s.hl.lh", ICLASS_AE_MULAAFD32S_HL_LH, + 0, + Opcode_ae_mulaafd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaafd32ra.hl.lh", ICLASS_AE_MULAAFD32RA_HL_LH, + 0, + Opcode_ae_mulaafd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaad32.hl.lh", ICLASS_AE_MULAAD32_HL_LH, + 0, + Opcode_ae_mulaad32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasfd32s.hh.ll", ICLASS_AE_MULASFD32S_HH_LL, + 0, + Opcode_ae_mulasfd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasfd32ra.hh.ll", ICLASS_AE_MULASFD32RA_HH_LL, + 0, + Opcode_ae_mulasfd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasd32.hh.ll", ICLASS_AE_MULASD32_HH_LL, + 0, + Opcode_ae_mulasd32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasfd32s.hl.lh", ICLASS_AE_MULASFD32S_HL_LH, + 0, + Opcode_ae_mulasfd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasfd32ra.hl.lh", ICLASS_AE_MULASFD32RA_HL_LH, + 0, + Opcode_ae_mulasfd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasd32.hl.lh", ICLASS_AE_MULASD32_HL_LH, + 0, + Opcode_ae_mulasd32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsafd32s.hh.ll", ICLASS_AE_MULSAFD32S_HH_LL, + 0, + Opcode_ae_mulsafd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsafd32ra.hh.ll", ICLASS_AE_MULSAFD32RA_HH_LL, + 0, + Opcode_ae_mulsafd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsad32.hh.ll", ICLASS_AE_MULSAD32_HH_LL, + 0, + Opcode_ae_mulsad32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssfd32s.hh.ll", ICLASS_AE_MULSSFD32S_HH_LL, + 0, + Opcode_ae_mulssfd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssfd32ra.hh.ll", ICLASS_AE_MULSSFD32RA_HH_LL, + 0, + Opcode_ae_mulssfd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssd32.hh.ll", ICLASS_AE_MULSSD32_HH_LL, + 0, + Opcode_ae_mulssd32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssfd32s.hl.lh", ICLASS_AE_MULSSFD32S_HL_LH, + 0, + Opcode_ae_mulssfd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssfd32ra.hl.lh", ICLASS_AE_MULSSFD32RA_HL_LH, + 0, + Opcode_ae_mulssfd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssd32.hl.lh", ICLASS_AE_MULSSD32_HL_LH, + 0, + Opcode_ae_mulssd32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulf32x16.l0", ICLASS_AE_MULF32X16_L0, + 0, + Opcode_ae_mulf32x16_l0_encode_fns, 0, 0 }, + { "ae_mul32x16.l0", ICLASS_AE_MUL32X16_L0, + 0, + Opcode_ae_mul32x16_l0_encode_fns, 0, 0 }, + { "ae_mulf32x16.l1", ICLASS_AE_MULF32X16_L1, + 0, + Opcode_ae_mulf32x16_l1_encode_fns, 0, 0 }, + { "ae_mul32x16.l1", ICLASS_AE_MUL32X16_L1, + 0, + Opcode_ae_mul32x16_l1_encode_fns, 0, 0 }, + { "ae_mulf32x16.l2", ICLASS_AE_MULF32X16_L2, + 0, + Opcode_ae_mulf32x16_l2_encode_fns, 0, 0 }, + { "ae_mul32x16.l2", ICLASS_AE_MUL32X16_L2, + 0, + Opcode_ae_mul32x16_l2_encode_fns, 0, 0 }, + { "ae_mulf32x16.l3", ICLASS_AE_MULF32X16_L3, + 0, + Opcode_ae_mulf32x16_l3_encode_fns, 0, 0 }, + { "ae_mul32x16.l3", ICLASS_AE_MUL32X16_L3, + 0, + Opcode_ae_mul32x16_l3_encode_fns, 0, 0 }, + { "ae_mulf32x16.h0", ICLASS_AE_MULF32X16_H0, + 0, + Opcode_ae_mulf32x16_h0_encode_fns, 0, 0 }, + { "ae_mul32x16.h0", ICLASS_AE_MUL32X16_H0, + 0, + Opcode_ae_mul32x16_h0_encode_fns, 0, 0 }, + { "ae_mulf32x16.h1", ICLASS_AE_MULF32X16_H1, + 0, + Opcode_ae_mulf32x16_h1_encode_fns, 0, 0 }, + { "ae_mul32x16.h1", ICLASS_AE_MUL32X16_H1, + 0, + Opcode_ae_mul32x16_h1_encode_fns, 0, 0 }, + { "ae_mulf32x16.h2", ICLASS_AE_MULF32X16_H2, + 0, + Opcode_ae_mulf32x16_h2_encode_fns, 0, 0 }, + { "ae_mul32x16.h2", ICLASS_AE_MUL32X16_H2, + 0, + Opcode_ae_mul32x16_h2_encode_fns, 0, 0 }, + { "ae_mulf32x16.h3", ICLASS_AE_MULF32X16_H3, + 0, + Opcode_ae_mulf32x16_h3_encode_fns, 0, 0 }, + { "ae_mul32x16.h3", ICLASS_AE_MUL32X16_H3, + 0, + Opcode_ae_mul32x16_h3_encode_fns, 0, 0 }, + { "ae_mulaf32x16.l0", ICLASS_AE_MULAF32X16_L0, + 0, + Opcode_ae_mulaf32x16_l0_encode_fns, 0, 0 }, + { "ae_mula32x16.l0", ICLASS_AE_MULA32X16_L0, + 0, + Opcode_ae_mula32x16_l0_encode_fns, 0, 0 }, + { "ae_mulaf32x16.l1", ICLASS_AE_MULAF32X16_L1, + 0, + Opcode_ae_mulaf32x16_l1_encode_fns, 0, 0 }, + { "ae_mula32x16.l1", ICLASS_AE_MULA32X16_L1, + 0, + Opcode_ae_mula32x16_l1_encode_fns, 0, 0 }, + { "ae_mulaf32x16.l2", ICLASS_AE_MULAF32X16_L2, + 0, + Opcode_ae_mulaf32x16_l2_encode_fns, 0, 0 }, + { "ae_mula32x16.l2", ICLASS_AE_MULA32X16_L2, + 0, + Opcode_ae_mula32x16_l2_encode_fns, 0, 0 }, + { "ae_mulaf32x16.l3", ICLASS_AE_MULAF32X16_L3, + 0, + Opcode_ae_mulaf32x16_l3_encode_fns, 0, 0 }, + { "ae_mula32x16.l3", ICLASS_AE_MULA32X16_L3, + 0, + Opcode_ae_mula32x16_l3_encode_fns, 0, 0 }, + { "ae_mulaf32x16.h0", ICLASS_AE_MULAF32X16_H0, + 0, + Opcode_ae_mulaf32x16_h0_encode_fns, 0, 0 }, + { "ae_mula32x16.h0", ICLASS_AE_MULA32X16_H0, + 0, + Opcode_ae_mula32x16_h0_encode_fns, 0, 0 }, + { "ae_mulaf32x16.h1", ICLASS_AE_MULAF32X16_H1, + 0, + Opcode_ae_mulaf32x16_h1_encode_fns, 0, 0 }, + { "ae_mula32x16.h1", ICLASS_AE_MULA32X16_H1, + 0, + Opcode_ae_mula32x16_h1_encode_fns, 0, 0 }, + { "ae_mulaf32x16.h2", ICLASS_AE_MULAF32X16_H2, + 0, + Opcode_ae_mulaf32x16_h2_encode_fns, 0, 0 }, + { "ae_mula32x16.h2", ICLASS_AE_MULA32X16_H2, + 0, + Opcode_ae_mula32x16_h2_encode_fns, 0, 0 }, + { "ae_mulaf32x16.h3", ICLASS_AE_MULAF32X16_H3, + 0, + Opcode_ae_mulaf32x16_h3_encode_fns, 0, 0 }, + { "ae_mula32x16.h3", ICLASS_AE_MULA32X16_H3, + 0, + Opcode_ae_mula32x16_h3_encode_fns, 0, 0 }, + { "ae_mulsf32x16.l0", ICLASS_AE_MULSF32X16_L0, + 0, + Opcode_ae_mulsf32x16_l0_encode_fns, 0, 0 }, + { "ae_muls32x16.l0", ICLASS_AE_MULS32X16_L0, + 0, + Opcode_ae_muls32x16_l0_encode_fns, 0, 0 }, + { "ae_mulsf32x16.l1", ICLASS_AE_MULSF32X16_L1, + 0, + Opcode_ae_mulsf32x16_l1_encode_fns, 0, 0 }, + { "ae_muls32x16.l1", ICLASS_AE_MULS32X16_L1, + 0, + Opcode_ae_muls32x16_l1_encode_fns, 0, 0 }, + { "ae_mulsf32x16.l2", ICLASS_AE_MULSF32X16_L2, + 0, + Opcode_ae_mulsf32x16_l2_encode_fns, 0, 0 }, + { "ae_muls32x16.l2", ICLASS_AE_MULS32X16_L2, + 0, + Opcode_ae_muls32x16_l2_encode_fns, 0, 0 }, + { "ae_mulsf32x16.l3", ICLASS_AE_MULSF32X16_L3, + 0, + Opcode_ae_mulsf32x16_l3_encode_fns, 0, 0 }, + { "ae_muls32x16.l3", ICLASS_AE_MULS32X16_L3, + 0, + Opcode_ae_muls32x16_l3_encode_fns, 0, 0 }, + { "ae_mulsf32x16.h0", ICLASS_AE_MULSF32X16_H0, + 0, + Opcode_ae_mulsf32x16_h0_encode_fns, 0, 0 }, + { "ae_muls32x16.h0", ICLASS_AE_MULS32X16_H0, + 0, + Opcode_ae_muls32x16_h0_encode_fns, 0, 0 }, + { "ae_mulsf32x16.h1", ICLASS_AE_MULSF32X16_H1, + 0, + Opcode_ae_mulsf32x16_h1_encode_fns, 0, 0 }, + { "ae_muls32x16.h1", ICLASS_AE_MULS32X16_H1, + 0, + Opcode_ae_muls32x16_h1_encode_fns, 0, 0 }, + { "ae_mulsf32x16.h2", ICLASS_AE_MULSF32X16_H2, + 0, + Opcode_ae_mulsf32x16_h2_encode_fns, 0, 0 }, + { "ae_muls32x16.h2", ICLASS_AE_MULS32X16_H2, + 0, + Opcode_ae_muls32x16_h2_encode_fns, 0, 0 }, + { "ae_mulsf32x16.h3", ICLASS_AE_MULSF32X16_H3, + 0, + Opcode_ae_mulsf32x16_h3_encode_fns, 0, 0 }, + { "ae_muls32x16.h3", ICLASS_AE_MULS32X16_H3, + 0, + Opcode_ae_muls32x16_h3_encode_fns, 0, 0 }, + { "ae_mulaafd32x16.h3.l2", ICLASS_AE_MULAAFD32X16_H3_L2, + 0, + Opcode_ae_mulaafd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulaad32x16.h3.l2", ICLASS_AE_MULAAD32X16_H3_L2, + 0, + Opcode_ae_mulaad32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulaafd32x16.h1.l0", ICLASS_AE_MULAAFD32X16_H1_L0, + 0, + Opcode_ae_mulaafd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulaad32x16.h1.l0", ICLASS_AE_MULAAD32X16_H1_L0, + 0, + Opcode_ae_mulaad32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulasfd32x16.h3.l2", ICLASS_AE_MULASFD32X16_H3_L2, + 0, + Opcode_ae_mulasfd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulasd32x16.h3.l2", ICLASS_AE_MULASD32X16_H3_L2, + 0, + Opcode_ae_mulasd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulasfd32x16.h1.l0", ICLASS_AE_MULASFD32X16_H1_L0, + 0, + Opcode_ae_mulasfd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulasd32x16.h1.l0", ICLASS_AE_MULASD32X16_H1_L0, + 0, + Opcode_ae_mulasd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulsafd32x16.h3.l2", ICLASS_AE_MULSAFD32X16_H3_L2, + 0, + Opcode_ae_mulsafd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulsad32x16.h3.l2", ICLASS_AE_MULSAD32X16_H3_L2, + 0, + Opcode_ae_mulsad32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulsafd32x16.h1.l0", ICLASS_AE_MULSAFD32X16_H1_L0, + 0, + Opcode_ae_mulsafd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulsad32x16.h1.l0", ICLASS_AE_MULSAD32X16_H1_L0, + 0, + Opcode_ae_mulsad32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulssfd32x16.h3.l2", ICLASS_AE_MULSSFD32X16_H3_L2, + 0, + Opcode_ae_mulssfd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulssd32x16.h3.l2", ICLASS_AE_MULSSD32X16_H3_L2, + 0, + Opcode_ae_mulssd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulssfd32x16.h1.l0", ICLASS_AE_MULSSFD32X16_H1_L0, + 0, + Opcode_ae_mulssfd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulssd32x16.h1.l0", ICLASS_AE_MULSSD32X16_H1_L0, + 0, + Opcode_ae_mulssd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzaafd32x16.h3.l2", ICLASS_AE_MULZAAFD32X16_H3_L2, + 0, + Opcode_ae_mulzaafd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzaad32x16.h3.l2", ICLASS_AE_MULZAAD32X16_H3_L2, + 0, + Opcode_ae_mulzaad32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzaafd32x16.h1.l0", ICLASS_AE_MULZAAFD32X16_H1_L0, + 0, + Opcode_ae_mulzaafd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzaad32x16.h1.l0", ICLASS_AE_MULZAAD32X16_H1_L0, + 0, + Opcode_ae_mulzaad32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzasfd32x16.h3.l2", ICLASS_AE_MULZASFD32X16_H3_L2, + 0, + Opcode_ae_mulzasfd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzasd32x16.h3.l2", ICLASS_AE_MULZASD32X16_H3_L2, + 0, + Opcode_ae_mulzasd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzasfd32x16.h1.l0", ICLASS_AE_MULZASFD32X16_H1_L0, + 0, + Opcode_ae_mulzasfd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzasd32x16.h1.l0", ICLASS_AE_MULZASD32X16_H1_L0, + 0, + Opcode_ae_mulzasd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzsafd32x16.h3.l2", ICLASS_AE_MULZSAFD32X16_H3_L2, + 0, + Opcode_ae_mulzsafd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzsad32x16.h3.l2", ICLASS_AE_MULZSAD32X16_H3_L2, + 0, + Opcode_ae_mulzsad32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzsafd32x16.h1.l0", ICLASS_AE_MULZSAFD32X16_H1_L0, + 0, + Opcode_ae_mulzsafd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzsad32x16.h1.l0", ICLASS_AE_MULZSAD32X16_H1_L0, + 0, + Opcode_ae_mulzsad32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzssfd32x16.h3.l2", ICLASS_AE_MULZSSFD32X16_H3_L2, + 0, + Opcode_ae_mulzssfd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzssd32x16.h3.l2", ICLASS_AE_MULZSSD32X16_H3_L2, + 0, + Opcode_ae_mulzssd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzssfd32x16.h1.l0", ICLASS_AE_MULZSSFD32X16_H1_L0, + 0, + Opcode_ae_mulzssfd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzssd32x16.h1.l0", ICLASS_AE_MULZSSD32X16_H1_L0, + 0, + Opcode_ae_mulzssd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzaafd32x16.h2.l3", ICLASS_AE_MULZAAFD32X16_H2_L3, + 0, + Opcode_ae_mulzaafd32x16_h2_l3_encode_fns, 0, 0 }, + { "ae_mulzaafd32x16.h0.l1", ICLASS_AE_MULZAAFD32X16_H0_L1, + 0, + Opcode_ae_mulzaafd32x16_h0_l1_encode_fns, 0, 0 }, + { "ae_mulaafd32x16.h2.l3", ICLASS_AE_MULAAFD32X16_H2_L3, + 0, + Opcode_ae_mulaafd32x16_h2_l3_encode_fns, 0, 0 }, + { "ae_mulaafd32x16.h0.l1", ICLASS_AE_MULAAFD32X16_H0_L1, + 0, + Opcode_ae_mulaafd32x16_h0_l1_encode_fns, 0, 0 }, + { "ae_mulzaad32x16.h2.l3", ICLASS_AE_MULZAAD32X16_H2_L3, + 0, + Opcode_ae_mulzaad32x16_h2_l3_encode_fns, 0, 0 }, + { "ae_mulzaad32x16.h0.l1", ICLASS_AE_MULZAAD32X16_H0_L1, + 0, + Opcode_ae_mulzaad32x16_h0_l1_encode_fns, 0, 0 }, + { "ae_mulaad32x16.h2.l3", ICLASS_AE_MULAAD32X16_H2_L3, + 0, + Opcode_ae_mulaad32x16_h2_l3_encode_fns, 0, 0 }, + { "ae_mulaad32x16.h0.l1", ICLASS_AE_MULAAD32X16_H0_L1, + 0, + Opcode_ae_mulaad32x16_h0_l1_encode_fns, 0, 0 }, + { "ae_mulp32x16x2.h", ICLASS_AE_MULP32X16X2_H, + 0, + Opcode_ae_mulp32x16x2_h_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2rs.h", ICLASS_AE_MULFP32X16X2RS_H, + 0, + Opcode_ae_mulfp32x16x2rs_h_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2ras.h", ICLASS_AE_MULFP32X16X2RAS_H, + 0, + Opcode_ae_mulfp32x16x2ras_h_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2s.h", ICLASS_AE_MULFP32X16X2S_H, + 0, + Opcode_ae_mulfp32x16x2s_h_encode_fns, 0, 0 }, + { "ae_mulp32x16x2.l", ICLASS_AE_MULP32X16X2_L, + 0, + Opcode_ae_mulp32x16x2_l_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2rs.l", ICLASS_AE_MULFP32X16X2RS_L, + 0, + Opcode_ae_mulfp32x16x2rs_l_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2ras.l", ICLASS_AE_MULFP32X16X2RAS_L, + 0, + Opcode_ae_mulfp32x16x2ras_l_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2s.l", ICLASS_AE_MULFP32X16X2S_L, + 0, + Opcode_ae_mulfp32x16x2s_l_encode_fns, 0, 0 }, + { "ae_mulap32x16x2.h", ICLASS_AE_MULAP32X16X2_H, + 0, + Opcode_ae_mulap32x16x2_h_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2rs.h", ICLASS_AE_MULAFP32X16X2RS_H, + 0, + Opcode_ae_mulafp32x16x2rs_h_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2ras.h", ICLASS_AE_MULAFP32X16X2RAS_H, + 0, + Opcode_ae_mulafp32x16x2ras_h_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2s.h", ICLASS_AE_MULAFP32X16X2S_H, + 0, + Opcode_ae_mulafp32x16x2s_h_encode_fns, 0, 0 }, + { "ae_mulap32x16x2.l", ICLASS_AE_MULAP32X16X2_L, + 0, + Opcode_ae_mulap32x16x2_l_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2rs.l", ICLASS_AE_MULAFP32X16X2RS_L, + 0, + Opcode_ae_mulafp32x16x2rs_l_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2ras.l", ICLASS_AE_MULAFP32X16X2RAS_L, + 0, + Opcode_ae_mulafp32x16x2ras_l_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2s.l", ICLASS_AE_MULAFP32X16X2S_L, + 0, + Opcode_ae_mulafp32x16x2s_l_encode_fns, 0, 0 }, + { "ae_mulsp32x16x2.h", ICLASS_AE_MULSP32X16X2_H, + 0, + Opcode_ae_mulsp32x16x2_h_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2rs.h", ICLASS_AE_MULSFP32X16X2RS_H, + 0, + Opcode_ae_mulsfp32x16x2rs_h_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2ras.h", ICLASS_AE_MULSFP32X16X2RAS_H, + 0, + Opcode_ae_mulsfp32x16x2ras_h_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2s.h", ICLASS_AE_MULSFP32X16X2S_H, + 0, + Opcode_ae_mulsfp32x16x2s_h_encode_fns, 0, 0 }, + { "ae_mulsp32x16x2.l", ICLASS_AE_MULSP32X16X2_L, + 0, + Opcode_ae_mulsp32x16x2_l_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2rs.l", ICLASS_AE_MULSFP32X16X2RS_L, + 0, + Opcode_ae_mulsfp32x16x2rs_l_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2ras.l", ICLASS_AE_MULSFP32X16X2RAS_L, + 0, + Opcode_ae_mulsfp32x16x2ras_l_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2s.l", ICLASS_AE_MULSFP32X16X2S_L, + 0, + Opcode_ae_mulsfp32x16x2s_l_encode_fns, 0, 0 }, + { "ae_mulp32x2", ICLASS_AE_MULP32X2, + 0, + Opcode_ae_mulp32x2_encode_fns, 0, 0 }, + { "ae_mulfp32x2rs", ICLASS_AE_MULFP32X2RS, + 0, + Opcode_ae_mulfp32x2rs_encode_fns, 0, 0 }, + { "ae_mulfp32x2ras", ICLASS_AE_MULFP32X2RAS, + 0, + Opcode_ae_mulfp32x2ras_encode_fns, 0, 0 }, + { "ae_mulfp32x2ts", ICLASS_AE_MULFP32X2TS, + 0, + Opcode_ae_mulfp32x2ts_encode_fns, 0, 0 }, + { "ae_mulp32x2t", ICLASS_AE_MULP32X2T, + 0, + Opcode_ae_mulp32x2t_encode_fns, 0, 0 }, + { "ae_mulap32x2", ICLASS_AE_MULAP32X2, + 0, + Opcode_ae_mulap32x2_encode_fns, 0, 0 }, + { "ae_mulafp32x2rs", ICLASS_AE_MULAFP32X2RS, + 0, + Opcode_ae_mulafp32x2rs_encode_fns, 0, 0 }, + { "ae_mulafp32x2ras", ICLASS_AE_MULAFP32X2RAS, + 0, + Opcode_ae_mulafp32x2ras_encode_fns, 0, 0 }, + { "ae_mulafp32x2ts", ICLASS_AE_MULAFP32X2TS, + 0, + Opcode_ae_mulafp32x2ts_encode_fns, 0, 0 }, + { "ae_mulap32x2t", ICLASS_AE_MULAP32X2T, + 0, + Opcode_ae_mulap32x2t_encode_fns, 0, 0 }, + { "ae_mulsp32x2", ICLASS_AE_MULSP32X2, + 0, + Opcode_ae_mulsp32x2_encode_fns, 0, 0 }, + { "ae_mulsfp32x2rs", ICLASS_AE_MULSFP32X2RS, + 0, + Opcode_ae_mulsfp32x2rs_encode_fns, 0, 0 }, + { "ae_mulsfp32x2ras", ICLASS_AE_MULSFP32X2RAS, + 0, + Opcode_ae_mulsfp32x2ras_encode_fns, 0, 0 }, + { "ae_mulsfp32x2ts", ICLASS_AE_MULSFP32X2TS, + 0, + Opcode_ae_mulsfp32x2ts_encode_fns, 0, 0 }, + { "ae_mulsp32x2t", ICLASS_AE_MULSP32X2T, + 0, + Opcode_ae_mulsp32x2t_encode_fns, 0, 0 }, + { "ae_mulfp16x4s", ICLASS_AE_MULFP16X4S, + 0, + Opcode_ae_mulfp16x4s_encode_fns, 0, 0 }, + { "ae_mulfp16x4ras", ICLASS_AE_MULFP16X4RAS, + 0, + Opcode_ae_mulfp16x4ras_encode_fns, 0, 0 }, + { "ae_mulc32", ICLASS_AE_MULC32, + 0, + Opcode_ae_mulc32_encode_fns, 0, 0 }, + { "ae_mulfc24ra", ICLASS_AE_MULFC24RA, + 0, + Opcode_ae_mulfc24ra_encode_fns, 0, 0 }, + { "ae_mulfc32ras", ICLASS_AE_MULFC32RAS, + 0, + Opcode_ae_mulfc32ras_encode_fns, 0, 0 }, + { "ae_mulc32x16.l", ICLASS_AE_MULC32X16_L, + 0, + Opcode_ae_mulc32x16_l_encode_fns, 0, 0 }, + { "ae_mulfc32x16ras.l", ICLASS_AE_MULFC32X16RAS_L, + 0, + Opcode_ae_mulfc32x16ras_l_encode_fns, 0, 0 }, + { "ae_mulc32x16.h", ICLASS_AE_MULC32X16_H, + 0, + Opcode_ae_mulc32x16_h_encode_fns, 0, 0 }, + { "ae_mulfc32x16ras.h", ICLASS_AE_MULFC32X16RAS_H, + 0, + Opcode_ae_mulfc32x16ras_h_encode_fns, 0, 0 }, + { "ae_mulac32", ICLASS_AE_MULAC32, + 0, + Opcode_ae_mulac32_encode_fns, 0, 0 }, + { "ae_mulafc24ra", ICLASS_AE_MULAFC24RA, + 0, + Opcode_ae_mulafc24ra_encode_fns, 0, 0 }, + { "ae_mulafc32ras", ICLASS_AE_MULAFC32RAS, + 0, + Opcode_ae_mulafc32ras_encode_fns, 0, 0 }, + { "ae_mulac32x16.l", ICLASS_AE_MULAC32X16_L, + 0, + Opcode_ae_mulac32x16_l_encode_fns, 0, 0 }, + { "ae_mulafc32x16ras.l", ICLASS_AE_MULAFC32X16RAS_L, + 0, + Opcode_ae_mulafc32x16ras_l_encode_fns, 0, 0 }, + { "ae_mulac32x16.h", ICLASS_AE_MULAC32X16_H, + 0, + Opcode_ae_mulac32x16_h_encode_fns, 0, 0 }, + { "ae_mulafc32x16ras.h", ICLASS_AE_MULAFC32X16RAS_H, + 0, + Opcode_ae_mulafc32x16ras_h_encode_fns, 0, 0 }, + { "ae_mulf16x4ss", ICLASS_AE_MULF16X4SS, + 0, + Opcode_ae_mulf16x4ss_encode_fns, 0, 0 }, + { "ae_mulaf16x4ss", ICLASS_AE_MULAF16X4SS, + 0, + Opcode_ae_mulaf16x4ss_encode_fns, 0, 0 }, + { "ae_mulsf16x4ss", ICLASS_AE_MULSF16X4SS, + 0, + Opcode_ae_mulsf16x4ss_encode_fns, 0, 0 }, + { "ae_mul16x4s", ICLASS_AE_MUL16X4S, + 0, + Opcode_ae_mul16x4s_encode_fns, 0, 0 }, + { "ae_mula16x4s", ICLASS_AE_MULA16X4S, + 0, + Opcode_ae_mula16x4s_encode_fns, 0, 0 }, + { "ae_muls16x4s", ICLASS_AE_MULS16X4S, + 0, + Opcode_ae_muls16x4s_encode_fns, 0, 0 }, + { "ae_mul16x4", ICLASS_AE_MUL16X4, + 0, + Opcode_ae_mul16x4_encode_fns, 0, 0 }, + { "ae_mula16x4", ICLASS_AE_MULA16X4, + 0, + Opcode_ae_mula16x4_encode_fns, 0, 0 }, + { "ae_muls16x4", ICLASS_AE_MULS16X4, + 0, + Opcode_ae_muls16x4_encode_fns, 0, 0 }, + { "ae_mulfd32x2s.fir.h", ICLASS_AE_MULFD32X2S_FIR_H, + 0, + Opcode_ae_mulfd32x2s_fir_h_encode_fns, 0, 0 }, + { "ae_mulfd32x2ra.fir.h", ICLASS_AE_MULFD32X2RA_FIR_H, + 0, + Opcode_ae_mulfd32x2ra_fir_h_encode_fns, 0, 0 }, + { "ae_mulfd32x2s.fir.l", ICLASS_AE_MULFD32X2S_FIR_L, + 0, + Opcode_ae_mulfd32x2s_fir_l_encode_fns, 0, 0 }, + { "ae_mulfd32x2ra.fir.l", ICLASS_AE_MULFD32X2RA_FIR_L, + 0, + Opcode_ae_mulfd32x2ra_fir_l_encode_fns, 0, 0 }, + { "ae_mulfd32x16x2.fir.hh", ICLASS_AE_MULFD32X16X2_FIR_HH, + 0, + Opcode_ae_mulfd32x16x2_fir_hh_encode_fns, 0, 0 }, + { "ae_mulfd32x16x2.fir.hl", ICLASS_AE_MULFD32X16X2_FIR_HL, + 0, + Opcode_ae_mulfd32x16x2_fir_hl_encode_fns, 0, 0 }, + { "ae_mulfd32x16x2.fir.lh", ICLASS_AE_MULFD32X16X2_FIR_LH, + 0, + Opcode_ae_mulfd32x16x2_fir_lh_encode_fns, 0, 0 }, + { "ae_mulfd32x16x2.fir.ll", ICLASS_AE_MULFD32X16X2_FIR_LL, + 0, + Opcode_ae_mulfd32x16x2_fir_ll_encode_fns, 0, 0 }, + { "ae_mulafd32x2s.fir.h", ICLASS_AE_MULAFD32X2S_FIR_H, + 0, + Opcode_ae_mulafd32x2s_fir_h_encode_fns, 0, 0 }, + { "ae_mulafd32x2ra.fir.h", ICLASS_AE_MULAFD32X2RA_FIR_H, + 0, + Opcode_ae_mulafd32x2ra_fir_h_encode_fns, 0, 0 }, + { "ae_mulafd32x2s.fir.l", ICLASS_AE_MULAFD32X2S_FIR_L, + 0, + Opcode_ae_mulafd32x2s_fir_l_encode_fns, 0, 0 }, + { "ae_mulafd32x2ra.fir.l", ICLASS_AE_MULAFD32X2RA_FIR_L, + 0, + Opcode_ae_mulafd32x2ra_fir_l_encode_fns, 0, 0 }, + { "ae_mulafd32x16x2.fir.hh", ICLASS_AE_MULAFD32X16X2_FIR_HH, + 0, + Opcode_ae_mulafd32x16x2_fir_hh_encode_fns, 0, 0 }, + { "ae_mulafd32x16x2.fir.hl", ICLASS_AE_MULAFD32X16X2_FIR_HL, + 0, + Opcode_ae_mulafd32x16x2_fir_hl_encode_fns, 0, 0 }, + { "ae_mulafd32x16x2.fir.lh", ICLASS_AE_MULAFD32X16X2_FIR_LH, + 0, + Opcode_ae_mulafd32x16x2_fir_lh_encode_fns, 0, 0 }, + { "ae_mulafd32x16x2.fir.ll", ICLASS_AE_MULAFD32X16X2_FIR_LL, + 0, + Opcode_ae_mulafd32x16x2_fir_ll_encode_fns, 0, 0 }, + { "ae_mulc16s.h", ICLASS_AE_MULC16S_H, + 0, + Opcode_ae_mulc16s_h_encode_fns, 0, 0 }, + { "ae_mulc16s.l", ICLASS_AE_MULC16S_L, + 0, + Opcode_ae_mulc16s_l_encode_fns, 0, 0 }, + { "ae_mulac16s.h", ICLASS_AE_MULAC16S_H, + 0, + Opcode_ae_mulac16s_h_encode_fns, 0, 0 }, + { "ae_mulac16s.l", ICLASS_AE_MULAC16S_L, + 0, + Opcode_ae_mulac16s_l_encode_fns, 0, 0 }, + { "ae_mulfc16ras", ICLASS_AE_MULFC16RAS, + 0, + Opcode_ae_mulfc16ras_encode_fns, 0, 0 }, + { "ae_mulafc16ras", ICLASS_AE_MULAFC16RAS, + 0, + Opcode_ae_mulafc16ras_encode_fns, 0, 0 }, + { "ae_mul16js", ICLASS_AE_MUL16JS, + 0, + Opcode_ae_mul16js_encode_fns, 0, 0 }, + { "ae_addandsubrng16ras_s1", ICLASS_AE_ADDANDSUBRNG16RAS_S1, + 0, + Opcode_ae_addandsubrng16ras_s1_encode_fns, 0, 0 }, + { "ae_addandsubrng16ras_s2", ICLASS_AE_ADDANDSUBRNG16RAS_S2, + 0, + Opcode_ae_addandsubrng16ras_s2_encode_fns, 0, 0 }, + { "ae_conj16s", ICLASS_AE_CONJ16S, + 0, + Opcode_ae_conj16s_encode_fns, 0, 0 }, + { "ae_mulfq16x2.fir.3", ICLASS_AE_MULFQ16X2_FIR_3, + 0, + Opcode_ae_mulfq16x2_fir_3_encode_fns, 0, 0 }, + { "ae_mulfq16x2.fir.2", ICLASS_AE_MULFQ16X2_FIR_2, + 0, + Opcode_ae_mulfq16x2_fir_2_encode_fns, 0, 0 }, + { "ae_mulfq16x2.fir.1", ICLASS_AE_MULFQ16X2_FIR_1, + 0, + Opcode_ae_mulfq16x2_fir_1_encode_fns, 0, 0 }, + { "ae_mulfq16x2.fir.0", ICLASS_AE_MULFQ16X2_FIR_0, + 0, + Opcode_ae_mulfq16x2_fir_0_encode_fns, 0, 0 }, + { "ae_mulafq16x2.fir.3", ICLASS_AE_MULAFQ16X2_FIR_3, + 0, + Opcode_ae_mulafq16x2_fir_3_encode_fns, 0, 0 }, + { "ae_mulafq16x2.fir.2", ICLASS_AE_MULAFQ16X2_FIR_2, + 0, + Opcode_ae_mulafq16x2_fir_2_encode_fns, 0, 0 }, + { "ae_mulafq16x2.fir.1", ICLASS_AE_MULAFQ16X2_FIR_1, + 0, + Opcode_ae_mulafq16x2_fir_1_encode_fns, 0, 0 }, + { "ae_mulafq16x2.fir.0", ICLASS_AE_MULAFQ16X2_FIR_0, + 0, + Opcode_ae_mulafq16x2_fir_0_encode_fns, 0, 0 }, + { "ae_mulzaaaafq32x16", ICLASS_AE_MULZAAAAFQ32X16, + 0, + Opcode_ae_mulzaaaafq32x16_encode_fns, 0, 0 }, + { "ae_mulaaaafq32x16", ICLASS_AE_MULAAAAFQ32X16, + 0, + Opcode_ae_mulaaaafq32x16_encode_fns, 0, 0 }, + { "ae_mulzaaaaq32x16", ICLASS_AE_MULZAAAAQ32X16, + 0, + Opcode_ae_mulzaaaaq32x16_encode_fns, 0, 0 }, + { "ae_mulaaaaq32x16", ICLASS_AE_MULAAAAQ32X16, + 0, + Opcode_ae_mulaaaaq32x16_encode_fns, 0, 0 }, + { "ae_mul16.00", ICLASS_AE_MUL16_00, + 0, + Opcode_ae_mul16_00_encode_fns, 0, 0 }, + { "ae_mula16.00", ICLASS_AE_MULA16_00, + 0, + Opcode_ae_mula16_00_encode_fns, 0, 0 }, + { "ae_mulzaaaaq16", ICLASS_AE_MULZAAAAQ16, + 0, + Opcode_ae_mulzaaaaq16_encode_fns, 0, 0 }, + { "ae_mulaaaaq16", ICLASS_AE_MULAAAAQ16, + 0, + Opcode_ae_mulaaaaq16_encode_fns, 0, 0 }, + { "ae_div64d32.h", ICLASS_AE_DIV64D32_H, + 0, + Opcode_ae_div64d32_h_encode_fns, 0, 0 }, + { "ae_div64d32.l", ICLASS_AE_DIV64D32_L, + 0, + Opcode_ae_div64d32_l_encode_fns, 0, 0 }, + { "ae_sha32", ICLASS_AE_SHA32, + 0, + Opcode_ae_sha32_encode_fns, 0, 0 }, + { "ae_vldl32t", ICLASS_AE_VLDL32T, + 0, + Opcode_ae_vldl32t_encode_fns, 2, Opcode_ae_vldl32t_funcUnit_uses }, + { "ae_vldl16t", ICLASS_AE_VLDL16T, + 0, + Opcode_ae_vldl16t_encode_fns, 2, Opcode_ae_vldl16t_funcUnit_uses }, + { "ae_vldl16c", ICLASS_AE_VLDL16C, + 0, + Opcode_ae_vldl16c_encode_fns, 4, Opcode_ae_vldl16c_funcUnit_uses }, + { "ae_vldl16c.ip", ICLASS_AE_VLDL16C_IP, + 0, + Opcode_ae_vldl16c_ip_encode_fns, 4, Opcode_ae_vldl16c_ip_funcUnit_uses }, + { "ae_vldl16c.ic", ICLASS_AE_VLDL16C_IC, + 0, + Opcode_ae_vldl16c_ic_encode_fns, 4, Opcode_ae_vldl16c_ic_funcUnit_uses }, + { "ae_vldl16c.ic1", ICLASS_AE_VLDL16C_IC1, + 0, + Opcode_ae_vldl16c_ic1_encode_fns, 4, Opcode_ae_vldl16c_ic1_funcUnit_uses }, + { "ae_vldsht", ICLASS_AE_VLDSHT, + 0, + Opcode_ae_vldsht_encode_fns, 3, Opcode_ae_vldsht_funcUnit_uses }, + { "ae_lb", ICLASS_AE_LB, + 0, + Opcode_ae_lb_encode_fns, 1, Opcode_ae_lb_funcUnit_uses }, + { "ae_lbi", ICLASS_AE_LBI, + 0, + Opcode_ae_lbi_encode_fns, 1, Opcode_ae_lbi_funcUnit_uses }, + { "ae_lbk", ICLASS_AE_LBK, + 0, + Opcode_ae_lbk_encode_fns, 1, Opcode_ae_lbk_funcUnit_uses }, + { "ae_lbki", ICLASS_AE_LBKI, + 0, + Opcode_ae_lbki_encode_fns, 1, Opcode_ae_lbki_funcUnit_uses }, + { "ae_lbs", ICLASS_AE_LBS, + 0, + Opcode_ae_lbs_encode_fns, 1, Opcode_ae_lbs_funcUnit_uses }, + { "ae_lbsi", ICLASS_AE_LBSI, + 0, + Opcode_ae_lbsi_encode_fns, 1, Opcode_ae_lbsi_funcUnit_uses }, + { "ae_db", ICLASS_AE_DB, + 0, + Opcode_ae_db_encode_fns, 3, Opcode_ae_db_funcUnit_uses }, + { "ae_dbi", ICLASS_AE_DBI, + 0, + Opcode_ae_dbi_encode_fns, 3, Opcode_ae_dbi_funcUnit_uses }, + { "ae_db.ic", ICLASS_AE_DB_IC, + 0, + Opcode_ae_db_ic_encode_fns, 3, Opcode_ae_db_ic_funcUnit_uses }, + { "ae_dbi.ic", ICLASS_AE_DBI_IC, + 0, + Opcode_ae_dbi_ic_encode_fns, 3, Opcode_ae_dbi_ic_funcUnit_uses }, + { "ae_db.ic1", ICLASS_AE_DB_IC1, + 0, + Opcode_ae_db_ic1_encode_fns, 3, Opcode_ae_db_ic1_funcUnit_uses }, + { "ae_dbi.ic1", ICLASS_AE_DBI_IC1, + 0, + Opcode_ae_dbi_ic1_encode_fns, 3, Opcode_ae_dbi_ic1_funcUnit_uses }, + { "ae_db.ip", ICLASS_AE_DB_IP, + 0, + Opcode_ae_db_ip_encode_fns, 3, Opcode_ae_db_ip_funcUnit_uses }, + { "ae_dbi.ip", ICLASS_AE_DBI_IP, + 0, + Opcode_ae_dbi_ip_encode_fns, 3, Opcode_ae_dbi_ip_funcUnit_uses }, + { "ae_ardecnorm16", ICLASS_AE_ARDECNORM16, + 0, + Opcode_ae_ardecnorm16_encode_fns, 0, 0 }, + { "ae_lbki_dbi.ic", ICLASS_AE_LBKI_DBI_IC, + 0, + Opcode_ae_lbki_dbi_ic_encode_fns, 1, Opcode_ae_lbki_dbi_ic_funcUnit_uses }, + { "ae_lbki_dbi.ip", ICLASS_AE_LBKI_DBI_IP, + 0, + Opcode_ae_lbki_dbi_ip_encode_fns, 1, Opcode_ae_lbki_dbi_ip_funcUnit_uses }, + { "ae_lbki_dbi", ICLASS_AE_LBKI_DBI, + 0, + Opcode_ae_lbki_dbi_encode_fns, 1, Opcode_ae_lbki_dbi_funcUnit_uses }, + { "ae_lbi_dbi.ic", ICLASS_AE_LBI_DBI_IC, + 0, + Opcode_ae_lbi_dbi_ic_encode_fns, 1, Opcode_ae_lbi_dbi_ic_funcUnit_uses }, + { "ae_lbi_dbi.ip", ICLASS_AE_LBI_DBI_IP, + 0, + Opcode_ae_lbi_dbi_ip_encode_fns, 1, Opcode_ae_lbi_dbi_ip_funcUnit_uses }, + { "ae_lbi_dbi", ICLASS_AE_LBI_DBI, + 0, + Opcode_ae_lbi_dbi_encode_fns, 1, Opcode_ae_lbi_dbi_funcUnit_uses }, + { "ae_lbk_db.ic", ICLASS_AE_LBK_DB_IC, + 0, + Opcode_ae_lbk_db_ic_encode_fns, 1, Opcode_ae_lbk_db_ic_funcUnit_uses }, + { "ae_lbk_db.ip", ICLASS_AE_LBK_DB_IP, + 0, + Opcode_ae_lbk_db_ip_encode_fns, 1, Opcode_ae_lbk_db_ip_funcUnit_uses }, + { "ae_lbk_db", ICLASS_AE_LBK_DB, + 0, + Opcode_ae_lbk_db_encode_fns, 1, Opcode_ae_lbk_db_funcUnit_uses }, + { "ae_lb_db.ic", ICLASS_AE_LB_DB_IC, + 0, + Opcode_ae_lb_db_ic_encode_fns, 1, Opcode_ae_lb_db_ic_funcUnit_uses }, + { "ae_lb_db.ip", ICLASS_AE_LB_DB_IP, + 0, + Opcode_ae_lb_db_ip_encode_fns, 1, Opcode_ae_lb_db_ip_funcUnit_uses }, + { "ae_lb_db", ICLASS_AE_LB_DB, + 0, + Opcode_ae_lb_db_encode_fns, 1, Opcode_ae_lb_db_funcUnit_uses }, + { "ae_vlel32t", ICLASS_AE_VLEL32T, + 0, + Opcode_ae_vlel32t_encode_fns, 2, Opcode_ae_vlel32t_funcUnit_uses }, + { "ae_vlel16t", ICLASS_AE_VLEL16T, + 0, + Opcode_ae_vlel16t_encode_fns, 2, Opcode_ae_vlel16t_funcUnit_uses }, + { "ae_sb", ICLASS_AE_SB, + 0, + Opcode_ae_sb_encode_fns, 3, Opcode_ae_sb_funcUnit_uses }, + { "ae_sbi", ICLASS_AE_SBI, + 0, + Opcode_ae_sbi_encode_fns, 3, Opcode_ae_sbi_funcUnit_uses }, + { "ae_vles16c", ICLASS_AE_VLES16C, + 0, + Opcode_ae_vles16c_encode_fns, 3, Opcode_ae_vles16c_funcUnit_uses }, + { "ae_sbf", ICLASS_AE_SBF, + 0, + Opcode_ae_sbf_encode_fns, 3, Opcode_ae_sbf_funcUnit_uses }, + { "ae_sb.ic", ICLASS_AE_SB_IC, + 0, + Opcode_ae_sb_ic_encode_fns, 3, Opcode_ae_sb_ic_funcUnit_uses }, + { "ae_sbi.ic", ICLASS_AE_SBI_IC, + 0, + Opcode_ae_sbi_ic_encode_fns, 3, Opcode_ae_sbi_ic_funcUnit_uses }, + { "ae_vles16c.ic", ICLASS_AE_VLES16C_IC, + 0, + Opcode_ae_vles16c_ic_encode_fns, 3, Opcode_ae_vles16c_ic_funcUnit_uses }, + { "ae_sbf.ic", ICLASS_AE_SBF_IC, + 0, + Opcode_ae_sbf_ic_encode_fns, 3, Opcode_ae_sbf_ic_funcUnit_uses }, + { "ae_sb.ic1", ICLASS_AE_SB_IC1, + 0, + Opcode_ae_sb_ic1_encode_fns, 3, Opcode_ae_sb_ic1_funcUnit_uses }, + { "ae_sbi.ic1", ICLASS_AE_SBI_IC1, + 0, + Opcode_ae_sbi_ic1_encode_fns, 3, Opcode_ae_sbi_ic1_funcUnit_uses }, + { "ae_vles16c.ic1", ICLASS_AE_VLES16C_IC1, + 0, + Opcode_ae_vles16c_ic1_encode_fns, 3, Opcode_ae_vles16c_ic1_funcUnit_uses }, + { "ae_sbf.ic1", ICLASS_AE_SBF_IC1, + 0, + Opcode_ae_sbf_ic1_encode_fns, 3, Opcode_ae_sbf_ic1_funcUnit_uses }, + { "ae_sb.ip", ICLASS_AE_SB_IP, + 0, + Opcode_ae_sb_ip_encode_fns, 3, Opcode_ae_sb_ip_funcUnit_uses }, + { "ae_sbi.ip", ICLASS_AE_SBI_IP, + 0, + Opcode_ae_sbi_ip_encode_fns, 3, Opcode_ae_sbi_ip_funcUnit_uses }, + { "ae_vles16c.ip", ICLASS_AE_VLES16C_IP, + 0, + Opcode_ae_vles16c_ip_encode_fns, 3, Opcode_ae_vles16c_ip_funcUnit_uses }, + { "ae_sbf.ip", ICLASS_AE_SBF_IP, + 0, + Opcode_ae_sbf_ip_encode_fns, 3, Opcode_ae_sbf_ip_funcUnit_uses }, + { "ae_sext32", ICLASS_AE_SEXT32, + 0, + Opcode_ae_sext32_encode_fns, 0, 0 }, + { "ae_movae", ICLASS_AE_MOVAE, + 0, + Opcode_ae_movae_encode_fns, 0, 0 }, + { "ae_movea", ICLASS_AE_MOVEA, + 0, + Opcode_ae_movea_encode_fns, 0, 0 }, + { "ae_moveep", ICLASS_AE_MOVEEP, + 0, + Opcode_ae_moveep_encode_fns, 0, 0 }, + { "ae_sext72", ICLASS_AE_SEXT72, + 0, + Opcode_ae_sext72_encode_fns, 0, 0 }, + { "ae_add72", ICLASS_AE_ADD72, + 0, + Opcode_ae_add72_encode_fns, 0, 0 }, + { "ae_sub72", ICLASS_AE_SUB72, + 0, + Opcode_ae_sub72_encode_fns, 0, 0 }, + { "ae_add72x64", ICLASS_AE_ADD72X64, + 0, + Opcode_ae_add72x64_encode_fns, 0, 0 }, + { "ae_sub72x64", ICLASS_AE_SUB72X64, + 0, + Opcode_ae_sub72x64_encode_fns, 0, 0 }, + { "ae_mul32ep.hh", ICLASS_AE_MUL32EP_HH, + 0, + Opcode_ae_mul32ep_hh_encode_fns, 0, 0 }, + { "ae_mula32ep.hh", ICLASS_AE_MULA32EP_HH, + 0, + Opcode_ae_mula32ep_hh_encode_fns, 0, 0 }, + { "ae_muls32ep.hh", ICLASS_AE_MULS32EP_HH, + 0, + Opcode_ae_muls32ep_hh_encode_fns, 0, 0 }, + { "ae_mulzaad32ep.hh.ll", ICLASS_AE_MULZAAD32EP_HH_LL, + 0, + Opcode_ae_mulzaad32ep_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssd32ep.hh.ll", ICLASS_AE_MULZSSD32EP_HH_LL, + 0, + Opcode_ae_mulzssd32ep_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaad32ep.hh.ll", ICLASS_AE_MULAAD32EP_HH_LL, + 0, + Opcode_ae_mulaad32ep_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssd32ep.hh.ll", ICLASS_AE_MULSSD32EP_HH_LL, + 0, + Opcode_ae_mulssd32ep_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaad32usep.hl.lh", ICLASS_AE_MULAAD32USEP_HL_LH, + 0, + Opcode_ae_mulaad32usep_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaad32usep.hl.lh", ICLASS_AE_MULZAAD32USEP_HL_LH, + 0, + Opcode_ae_mulzaad32usep_hl_lh_encode_fns, 0, 0 }, + { "ae_mul32usep.lh", ICLASS_AE_MUL32USEP_LH, + 0, + Opcode_ae_mul32usep_lh_encode_fns, 0, 0 }, + { "ae_mula32usep.lh", ICLASS_AE_MULA32USEP_LH, + 0, + Opcode_ae_mula32usep_lh_encode_fns, 0, 0 }, + { "ae_mul32usep.ll", ICLASS_AE_MUL32USEP_LL, + 0, + Opcode_ae_mul32usep_ll_encode_fns, 0, 0 }, + { "ae_mula32usep.ll", ICLASS_AE_MULA32USEP_LL, + 0, + Opcode_ae_mula32usep_ll_encode_fns, 0, 0 }, + { "ae_srai72", ICLASS_AE_SRAI72, + 0, + Opcode_ae_srai72_encode_fns, 0, 0 }, + { "ae_slai72", ICLASS_AE_SLAI72, + 0, + Opcode_ae_slai72_encode_fns, 0, 0 }, + { "ae_sat64s", ICLASS_AE_SAT64S, + 0, + Opcode_ae_sat64s_encode_fns, 0, 0 }, + { "ae_l16si.n", ICLASS_AE_L16SI_N, + 0, + Opcode_ae_l16si_n_encode_fns, 2, Opcode_ae_l16si_n_funcUnit_uses }, + { "ae_l16ui.n", ICLASS_AE_L16UI_N, + 0, + Opcode_ae_l16ui_n_encode_fns, 2, Opcode_ae_l16ui_n_funcUnit_uses }, + { "ae_s16i.n", ICLASS_AE_S16I_N, + 0, + Opcode_ae_s16i_n_encode_fns, 2, Opcode_ae_s16i_n_funcUnit_uses }, + { "ae_lalign128.i", ICLASS_AE_LALIGN128_I, + 0, + Opcode_ae_lalign128_i_encode_fns, 1, Opcode_ae_lalign128_i_funcUnit_uses }, + { "ae_salign128.i", ICLASS_AE_SALIGN128_I, + 0, + Opcode_ae_salign128_i_encode_fns, 1, Opcode_ae_salign128_i_funcUnit_uses }, + { "ae_la128.pp", ICLASS_AE_LA128_PP, + 0, + Opcode_ae_la128_pp_encode_fns, 1, Opcode_ae_la128_pp_funcUnit_uses }, + { "ae_sa128pos.fp", ICLASS_AE_SA128POS_FP, + 0, + Opcode_ae_sa128pos_fp_encode_fns, 1, Opcode_ae_sa128pos_fp_funcUnit_uses }, + { "ae_la8x4s_ip", ICLASS_AE_LA8X4S_IP, + 0, + Opcode_ae_la8x4s_ip_encode_fns, 1, Opcode_ae_la8x4s_ip_funcUnit_uses }, + { "ae_la8x4u_ip", ICLASS_AE_LA8X4U_IP, + 0, + Opcode_ae_la8x4u_ip_encode_fns, 1, Opcode_ae_la8x4u_ip_funcUnit_uses }, + { "ae_la8x8x2_ip", ICLASS_AE_LA8X8X2_IP, + 0, + Opcode_ae_la8x8x2_ip_encode_fns, 1, Opcode_ae_la8x8x2_ip_funcUnit_uses }, + { "ae_la16x4x2_ip", ICLASS_AE_LA16X4X2_IP, + 0, + Opcode_ae_la16x4x2_ip_encode_fns, 1, Opcode_ae_la16x4x2_ip_funcUnit_uses }, + { "ae_la32x2x2_ip", ICLASS_AE_LA32X2X2_IP, + 0, + Opcode_ae_la32x2x2_ip_encode_fns, 1, Opcode_ae_la32x2x2_ip_funcUnit_uses }, + { "ae_la8x8x2_ic", ICLASS_AE_LA8X8X2_IC, + 0, + Opcode_ae_la8x8x2_ic_encode_fns, 1, Opcode_ae_la8x8x2_ic_funcUnit_uses }, + { "ae_la16x4x2_ic", ICLASS_AE_LA16X4X2_IC, + 0, + Opcode_ae_la16x4x2_ic_encode_fns, 1, Opcode_ae_la16x4x2_ic_funcUnit_uses }, + { "ae_la32x2x2_ic", ICLASS_AE_LA32X2X2_IC, + 0, + Opcode_ae_la32x2x2_ic_encode_fns, 1, Opcode_ae_la32x2x2_ic_funcUnit_uses }, + { "ae_la8x8x2_ic1", ICLASS_AE_LA8X8X2_IC1, + 0, + Opcode_ae_la8x8x2_ic1_encode_fns, 1, Opcode_ae_la8x8x2_ic1_funcUnit_uses }, + { "ae_la16x4x2_ic1", ICLASS_AE_LA16X4X2_IC1, + 0, + Opcode_ae_la16x4x2_ic1_encode_fns, 1, Opcode_ae_la16x4x2_ic1_funcUnit_uses }, + { "ae_la32x2x2_ic1", ICLASS_AE_LA32X2X2_IC1, + 0, + Opcode_ae_la32x2x2_ic1_encode_fns, 1, Opcode_ae_la32x2x2_ic1_funcUnit_uses }, + { "ae_la8x8x2_ic2", ICLASS_AE_LA8X8X2_IC2, + 0, + Opcode_ae_la8x8x2_ic2_encode_fns, 1, Opcode_ae_la8x8x2_ic2_funcUnit_uses }, + { "ae_la16x4x2_ic2", ICLASS_AE_LA16X4X2_IC2, + 0, + Opcode_ae_la16x4x2_ic2_encode_fns, 1, Opcode_ae_la16x4x2_ic2_funcUnit_uses }, + { "ae_la32x2x2_ic2", ICLASS_AE_LA32X2X2_IC2, + 0, + Opcode_ae_la32x2x2_ic2_encode_fns, 1, Opcode_ae_la32x2x2_ic2_funcUnit_uses }, + { "ae_sa8x8x2_ip", ICLASS_AE_SA8X8X2_IP, + 0, + Opcode_ae_sa8x8x2_ip_encode_fns, 1, Opcode_ae_sa8x8x2_ip_funcUnit_uses }, + { "ae_sa16x4x2_ip", ICLASS_AE_SA16X4X2_IP, + 0, + Opcode_ae_sa16x4x2_ip_encode_fns, 1, Opcode_ae_sa16x4x2_ip_funcUnit_uses }, + { "ae_sa32x2x2_ip", ICLASS_AE_SA32X2X2_IP, + 0, + Opcode_ae_sa32x2x2_ip_encode_fns, 1, Opcode_ae_sa32x2x2_ip_funcUnit_uses }, + { "ae_sa8x8x2_ic", ICLASS_AE_SA8X8X2_IC, + 0, + Opcode_ae_sa8x8x2_ic_encode_fns, 1, Opcode_ae_sa8x8x2_ic_funcUnit_uses }, + { "ae_sa16x4x2_ic", ICLASS_AE_SA16X4X2_IC, + 0, + Opcode_ae_sa16x4x2_ic_encode_fns, 1, Opcode_ae_sa16x4x2_ic_funcUnit_uses }, + { "ae_sa32x2x2_ic", ICLASS_AE_SA32X2X2_IC, + 0, + Opcode_ae_sa32x2x2_ic_encode_fns, 1, Opcode_ae_sa32x2x2_ic_funcUnit_uses }, + { "ae_sa8x8x2_ic1", ICLASS_AE_SA8X8X2_IC1, + 0, + Opcode_ae_sa8x8x2_ic1_encode_fns, 1, Opcode_ae_sa8x8x2_ic1_funcUnit_uses }, + { "ae_sa16x4x2_ic1", ICLASS_AE_SA16X4X2_IC1, + 0, + Opcode_ae_sa16x4x2_ic1_encode_fns, 1, Opcode_ae_sa16x4x2_ic1_funcUnit_uses }, + { "ae_sa32x2x2_ic1", ICLASS_AE_SA32X2X2_IC1, + 0, + Opcode_ae_sa32x2x2_ic1_encode_fns, 1, Opcode_ae_sa32x2x2_ic1_funcUnit_uses }, + { "ae_sa8x8x2_ic2", ICLASS_AE_SA8X8X2_IC2, + 0, + Opcode_ae_sa8x8x2_ic2_encode_fns, 1, Opcode_ae_sa8x8x2_ic2_funcUnit_uses }, + { "ae_sa16x4x2_ic2", ICLASS_AE_SA16X4X2_IC2, + 0, + Opcode_ae_sa16x4x2_ic2_encode_fns, 1, Opcode_ae_sa16x4x2_ic2_funcUnit_uses }, + { "ae_sa32x2x2_ic2", ICLASS_AE_SA32X2X2_IC2, + 0, + Opcode_ae_sa32x2x2_ic2_encode_fns, 1, Opcode_ae_sa32x2x2_ic2_funcUnit_uses }, + { "ae_abs8", ICLASS_AE_ABS8, + 0, + Opcode_ae_abs8_encode_fns, 0, 0 }, + { "ae_abs8s", ICLASS_AE_ABS8S, + 0, + Opcode_ae_abs8s_encode_fns, 0, 0 }, + { "ae_neg8s", ICLASS_AE_NEG8S, + 0, + Opcode_ae_neg8s_encode_fns, 0, 0 }, + { "ae_add8", ICLASS_AE_ADD8, + 0, + Opcode_ae_add8_encode_fns, 0, 0 }, + { "ae_sub8", ICLASS_AE_SUB8, + 0, + Opcode_ae_sub8_encode_fns, 0, 0 }, + { "ae_max8", ICLASS_AE_MAX8, + 0, + Opcode_ae_max8_encode_fns, 0, 0 }, + { "ae_min8", ICLASS_AE_MIN8, + 0, + Opcode_ae_min8_encode_fns, 0, 0 }, + { "ae_add8s", ICLASS_AE_ADD8S, + 0, + Opcode_ae_add8s_encode_fns, 0, 0 }, + { "ae_sub8s", ICLASS_AE_SUB8S, + 0, + Opcode_ae_sub8s_encode_fns, 0, 0 }, + { "ae_le8", ICLASS_AE_LE8, + 0, + Opcode_ae_le8_encode_fns, 0, 0 }, + { "ae_lt8", ICLASS_AE_LT8, + 0, + Opcode_ae_lt8_encode_fns, 0, 0 }, + { "ae_eq8", ICLASS_AE_EQ8, + 0, + Opcode_ae_eq8_encode_fns, 0, 0 }, + { "ae_satu16x4", ICLASS_AE_SATU16X4, + 0, + Opcode_ae_satu16x4_encode_fns, 0, 0 }, + { "ae_sat32x2", ICLASS_AE_SAT32X2, + 0, + Opcode_ae_sat32x2_encode_fns, 0, 0 }, + { "ae_satu32x2", ICLASS_AE_SATU32X2, + 0, + Opcode_ae_satu32x2_encode_fns, 0, 0 }, + { "ae_sat8x8x16", ICLASS_AE_SAT8X8X16, + 0, + Opcode_ae_sat8x8x16_encode_fns, 0, 0 }, + { "ae_satu8x8x16", ICLASS_AE_SATU8X8X16, + 0, + Opcode_ae_satu8x8x16_encode_fns, 0, 0 }, + { "ae_sat8x4x32_l", ICLASS_AE_SAT8X4X32_L, + 0, + Opcode_ae_sat8x4x32_l_encode_fns, 0, 0 }, + { "ae_satu8x4x32_l", ICLASS_AE_SATU8X4X32_L, + 0, + Opcode_ae_satu8x4x32_l_encode_fns, 0, 0 }, + { "ae_round8x8f16ssym", ICLASS_AE_ROUND8X8F16SSYM, + 0, + Opcode_ae_round8x8f16ssym_encode_fns, 0, 0 }, + { "ae_round8x8f16sasym", ICLASS_AE_ROUND8X8F16SASYM, + 0, + Opcode_ae_round8x8f16sasym_encode_fns, 0, 0 }, + { "ae_round8x4f32ssym_l", ICLASS_AE_ROUND8X4F32SSYM_L, + 0, + Opcode_ae_round8x4f32ssym_l_encode_fns, 0, 0 }, + { "ae_round8x4f32sasym_l", ICLASS_AE_ROUND8X4F32SASYM_L, + 0, + Opcode_ae_round8x4f32sasym_l_encode_fns, 0, 0 }, + { "ae_movda8", ICLASS_AE_MOVDA8, + 0, + Opcode_ae_movda8_encode_fns, 0, 0 }, + { "ae_movad8", ICLASS_AE_MOVAD8, + 0, + Opcode_ae_movad8_encode_fns, 0, 0 }, + { "ae_movdx2", ICLASS_AE_MOVDX2, + 0, + Opcode_ae_movdx2_encode_fns, 0, 0 }, + { "ae_addandsub32j", ICLASS_AE_ADDANDSUB32J, + 0, + Opcode_ae_addandsub32j_encode_fns, 0, 0 }, + { "ae_addw8", ICLASS_AE_ADDW8, + 0, + Opcode_ae_addw8_encode_fns, 0, 0 }, + { "ae_addw16", ICLASS_AE_ADDW16, + 0, + Opcode_ae_addw16_encode_fns, 0, 0 }, + { "ae_addw32", ICLASS_AE_ADDW32, + 0, + Opcode_ae_addw32_encode_fns, 0, 0 }, + { "ae_subw8", ICLASS_AE_SUBW8, + 0, + Opcode_ae_subw8_encode_fns, 0, 0 }, + { "ae_subw16", ICLASS_AE_SUBW16, + 0, + Opcode_ae_subw16_encode_fns, 0, 0 }, + { "ae_subw32", ICLASS_AE_SUBW32, + 0, + Opcode_ae_subw32_encode_fns, 0, 0 }, + { "ae_accw8", ICLASS_AE_ACCW8, + 0, + Opcode_ae_accw8_encode_fns, 0, 0 }, + { "ae_accw16", ICLASS_AE_ACCW16, + 0, + Opcode_ae_accw16_encode_fns, 0, 0 }, + { "ae_accw32", ICLASS_AE_ACCW32, + 0, + Opcode_ae_accw32_encode_fns, 0, 0 }, + { "ae_addw8u", ICLASS_AE_ADDW8U, + 0, + Opcode_ae_addw8u_encode_fns, 0, 0 }, + { "ae_subw8u", ICLASS_AE_SUBW8U, + 0, + Opcode_ae_subw8u_encode_fns, 0, 0 }, + { "ae_accw8u", ICLASS_AE_ACCW8U, + 0, + Opcode_ae_accw8u_encode_fns, 0, 0 }, + { "ae_mulfp32x2s.hh.ll", ICLASS_AE_MULFP32X2S_HH_LL, + 0, + Opcode_ae_mulfp32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulafp32x2s.hh.ll", ICLASS_AE_MULAFP32X2S_HH_LL, + 0, + Opcode_ae_mulafp32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsfp32x2s.hh.ll", ICLASS_AE_MULSFP32X2S_HH_LL, + 0, + Opcode_ae_mulsfp32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulfp32x2s.hl.lh", ICLASS_AE_MULFP32X2S_HL_LH, + 0, + Opcode_ae_mulfp32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulafp32x2s.hl.lh", ICLASS_AE_MULAFP32X2S_HL_LH, + 0, + Opcode_ae_mulafp32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsfp32x2s.hl.lh", ICLASS_AE_MULSFP32X2S_HL_LH, + 0, + Opcode_ae_mulsfp32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaaf2d32s.hh.ll", ICLASS_AE_MULZAAF2D32S_HH_LL, + 0, + Opcode_ae_mulzaaf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasf2d32s.hh.ll", ICLASS_AE_MULZASF2D32S_HH_LL, + 0, + Opcode_ae_mulzasf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsaf2d32s.hh.ll", ICLASS_AE_MULZSAF2D32S_HH_LL, + 0, + Opcode_ae_mulzsaf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssf2d32s.hh.ll", ICLASS_AE_MULZSSF2D32S_HH_LL, + 0, + Opcode_ae_mulzssf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaaf2d32s.hh.ll", ICLASS_AE_MULAAF2D32S_HH_LL, + 0, + Opcode_ae_mulaaf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasf2d32s.hh.ll", ICLASS_AE_MULASF2D32S_HH_LL, + 0, + Opcode_ae_mulasf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsaf2d32s.hh.ll", ICLASS_AE_MULSAF2D32S_HH_LL, + 0, + Opcode_ae_mulsaf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssf2d32s.hh.ll", ICLASS_AE_MULSSF2D32S_HH_LL, + 0, + Opcode_ae_mulssf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaaf2d32s.hl.lh", ICLASS_AE_MULZAAF2D32S_HL_LH, + 0, + Opcode_ae_mulzaaf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasf2d32s.hl.lh", ICLASS_AE_MULZASF2D32S_HL_LH, + 0, + Opcode_ae_mulzasf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzsaf2d32s.hl.lh", ICLASS_AE_MULZSAF2D32S_HL_LH, + 0, + Opcode_ae_mulzsaf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssf2d32s.hl.lh", ICLASS_AE_MULZSSF2D32S_HL_LH, + 0, + Opcode_ae_mulzssf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaaf2d32s.hl.lh", ICLASS_AE_MULAAF2D32S_HL_LH, + 0, + Opcode_ae_mulaaf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasf2d32s.hl.lh", ICLASS_AE_MULASF2D32S_HL_LH, + 0, + Opcode_ae_mulasf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsaf2d32s.hl.lh", ICLASS_AE_MULSAF2D32S_HL_LH, + 0, + Opcode_ae_mulsaf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssf2d32s.hl.lh", ICLASS_AE_MULSSF2D32S_HL_LH, + 0, + Opcode_ae_mulssf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mul32s.hh", ICLASS_AE_MUL32S_HH, + 0, + Opcode_ae_mul32s_hh_encode_fns, 0, 0 }, + { "ae_mula32s.hh", ICLASS_AE_MULA32S_HH, + 0, + Opcode_ae_mula32s_hh_encode_fns, 0, 0 }, + { "ae_muls32s.hh", ICLASS_AE_MULS32S_HH, + 0, + Opcode_ae_muls32s_hh_encode_fns, 0, 0 }, + { "ae_mul32s.ll", ICLASS_AE_MUL32S_LL, + 0, + Opcode_ae_mul32s_ll_encode_fns, 0, 0 }, + { "ae_mula32s.ll", ICLASS_AE_MULA32S_LL, + 0, + Opcode_ae_mula32s_ll_encode_fns, 0, 0 }, + { "ae_muls32s.ll", ICLASS_AE_MULS32S_LL, + 0, + Opcode_ae_muls32s_ll_encode_fns, 0, 0 }, + { "ae_mul32s.hl", ICLASS_AE_MUL32S_HL, + 0, + Opcode_ae_mul32s_hl_encode_fns, 0, 0 }, + { "ae_mula32s.hl", ICLASS_AE_MULA32S_HL, + 0, + Opcode_ae_mula32s_hl_encode_fns, 0, 0 }, + { "ae_muls32s.hl", ICLASS_AE_MULS32S_HL, + 0, + Opcode_ae_muls32s_hl_encode_fns, 0, 0 }, + { "ae_mul32s.lh", ICLASS_AE_MUL32S_LH, + 0, + Opcode_ae_mul32s_lh_encode_fns, 0, 0 }, + { "ae_mula32s.lh", ICLASS_AE_MULA32S_LH, + 0, + Opcode_ae_mula32s_lh_encode_fns, 0, 0 }, + { "ae_muls32s.lh", ICLASS_AE_MULS32S_LH, + 0, + Opcode_ae_muls32s_lh_encode_fns, 0, 0 }, + { "ae_mul32x2s.hh.ll", ICLASS_AE_MUL32X2S_HH_LL, + 0, + Opcode_ae_mul32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_mula32x2s.hh.ll", ICLASS_AE_MULA32X2S_HH_LL, + 0, + Opcode_ae_mula32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_muls32x2s.hh.ll", ICLASS_AE_MULS32X2S_HH_LL, + 0, + Opcode_ae_muls32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_mul32x2s.hl.lh", ICLASS_AE_MUL32X2S_HL_LH, + 0, + Opcode_ae_mul32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_mula32x2s.hl.lh", ICLASS_AE_MULA32X2S_HL_LH, + 0, + Opcode_ae_mula32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_muls32x2s.hl.lh", ICLASS_AE_MULS32X2S_HL_LH, + 0, + Opcode_ae_muls32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaad32s.hh.ll", ICLASS_AE_MULZAAD32S_HH_LL, + 0, + Opcode_ae_mulzaad32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasd32s.hh.ll", ICLASS_AE_MULZASD32S_HH_LL, + 0, + Opcode_ae_mulzasd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsad32s.hh.ll", ICLASS_AE_MULZSAD32S_HH_LL, + 0, + Opcode_ae_mulzsad32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssd32s.hh.ll", ICLASS_AE_MULZSSD32S_HH_LL, + 0, + Opcode_ae_mulzssd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaad32s.hh.ll", ICLASS_AE_MULAAD32S_HH_LL, + 0, + Opcode_ae_mulaad32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasd32s.hh.ll", ICLASS_AE_MULASD32S_HH_LL, + 0, + Opcode_ae_mulasd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsad32s.hh.ll", ICLASS_AE_MULSAD32S_HH_LL, + 0, + Opcode_ae_mulsad32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssd32s.hh.ll", ICLASS_AE_MULSSD32S_HH_LL, + 0, + Opcode_ae_mulssd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaad32s.hl.lh", ICLASS_AE_MULZAAD32S_HL_LH, + 0, + Opcode_ae_mulzaad32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasd32s.hl.lh", ICLASS_AE_MULZASD32S_HL_LH, + 0, + Opcode_ae_mulzasd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzsad32s.hl.lh", ICLASS_AE_MULZSAD32S_HL_LH, + 0, + Opcode_ae_mulzsad32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssd32s.hl.lh", ICLASS_AE_MULZSSD32S_HL_LH, + 0, + Opcode_ae_mulzssd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaad32s.hl.lh", ICLASS_AE_MULAAD32S_HL_LH, + 0, + Opcode_ae_mulaad32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasd32s.hl.lh", ICLASS_AE_MULASD32S_HL_LH, + 0, + Opcode_ae_mulasd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsad32s.hl.lh", ICLASS_AE_MULSAD32S_HL_LH, + 0, + Opcode_ae_mulsad32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssd32s.hl.lh", ICLASS_AE_MULSSD32S_HL_LH, + 0, + Opcode_ae_mulssd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulf32x2ra.hh.ll", ICLASS_AE_MULF32X2RA_HH_LL, + 0, + Opcode_ae_mulf32x2ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaf32x2ra.hh.ll", ICLASS_AE_MULAF32X2RA_HH_LL, + 0, + Opcode_ae_mulaf32x2ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsf32x2ra.hh.ll", ICLASS_AE_MULSF32X2RA_HH_LL, + 0, + Opcode_ae_mulsf32x2ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulf32x2ra.hl.lh", ICLASS_AE_MULF32X2RA_HL_LH, + 0, + Opcode_ae_mulf32x2ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaf32x2ra.hl.lh", ICLASS_AE_MULAF32X2RA_HL_LH, + 0, + Opcode_ae_mulaf32x2ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsf32x2ra.hl.lh", ICLASS_AE_MULSF32X2RA_HL_LH, + 0, + Opcode_ae_mulsf32x2ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaaf2d32ra.hh.ll", ICLASS_AE_MULZAAF2D32RA_HH_LL, + 0, + Opcode_ae_mulzaaf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasf2d32ra.hh.ll", ICLASS_AE_MULZASF2D32RA_HH_LL, + 0, + Opcode_ae_mulzasf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsaf2d32ra.hh.ll", ICLASS_AE_MULZSAF2D32RA_HH_LL, + 0, + Opcode_ae_mulzsaf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssf2d32ra.hh.ll", ICLASS_AE_MULZSSF2D32RA_HH_LL, + 0, + Opcode_ae_mulzssf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaaf2d32ra.hh.ll", ICLASS_AE_MULAAF2D32RA_HH_LL, + 0, + Opcode_ae_mulaaf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasf2d32ra.hh.ll", ICLASS_AE_MULASF2D32RA_HH_LL, + 0, + Opcode_ae_mulasf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsaf2d32ra.hh.ll", ICLASS_AE_MULSAF2D32RA_HH_LL, + 0, + Opcode_ae_mulsaf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssf2d32ra.hh.ll", ICLASS_AE_MULSSF2D32RA_HH_LL, + 0, + Opcode_ae_mulssf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaaf2d32ra.hl.lh", ICLASS_AE_MULZAAF2D32RA_HL_LH, + 0, + Opcode_ae_mulzaaf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasf2d32ra.hl.lh", ICLASS_AE_MULZASF2D32RA_HL_LH, + 0, + Opcode_ae_mulzasf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzsaf2d32ra.hl.lh", ICLASS_AE_MULZSAF2D32RA_HL_LH, + 0, + Opcode_ae_mulzsaf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssf2d32ra.hl.lh", ICLASS_AE_MULZSSF2D32RA_HL_LH, + 0, + Opcode_ae_mulzssf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaaf2d32ra.hl.lh", ICLASS_AE_MULAAF2D32RA_HL_LH, + 0, + Opcode_ae_mulaaf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasf2d32ra.hl.lh", ICLASS_AE_MULASF2D32RA_HL_LH, + 0, + Opcode_ae_mulasf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsaf2d32ra.hl.lh", ICLASS_AE_MULSAF2D32RA_HL_LH, + 0, + Opcode_ae_mulsaf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssf2d32ra.hl.lh", ICLASS_AE_MULSSF2D32RA_HL_LH, + 0, + Opcode_ae_mulssf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulf32x2r.hh.ll", ICLASS_AE_MULF32X2R_HH_LL, + 0, + Opcode_ae_mulf32x2r_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaf32x2r.hh.ll", ICLASS_AE_MULAF32X2R_HH_LL, + 0, + Opcode_ae_mulaf32x2r_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsf32x2r.hh.ll", ICLASS_AE_MULSF32X2R_HH_LL, + 0, + Opcode_ae_mulsf32x2r_hh_ll_encode_fns, 0, 0 }, + { "ae_mulf32x2r.hl.lh", ICLASS_AE_MULF32X2R_HL_LH, + 0, + Opcode_ae_mulf32x2r_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaf32x2r.hl.lh", ICLASS_AE_MULAF32X2R_HL_LH, + 0, + Opcode_ae_mulaf32x2r_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsf32x2r.hl.lh", ICLASS_AE_MULSF32X2R_HL_LH, + 0, + Opcode_ae_mulsf32x2r_hl_lh_encode_fns, 0, 0 }, + { "ae_mulfc32w", ICLASS_AE_MULFC32W, + 0, + Opcode_ae_mulfc32w_encode_fns, 0, 0 }, + { "ae_mulafc32w", ICLASS_AE_MULAFC32W, + 0, + Opcode_ae_mulafc32w_encode_fns, 0, 0 }, + { "ae_mulfcj32w", ICLASS_AE_MULFCJ32W, + 0, + Opcode_ae_mulfcj32w_encode_fns, 0, 0 }, + { "ae_mulafcj32w", ICLASS_AE_MULAFCJ32W, + 0, + Opcode_ae_mulafcj32w_encode_fns, 0, 0 }, + { "ae_mulfcj32ras", ICLASS_AE_MULFCJ32RAS, + 0, + Opcode_ae_mulfcj32ras_encode_fns, 0, 0 }, + { "ae_mulafcj32ras", ICLASS_AE_MULAFCJ32RAS, + 0, + Opcode_ae_mulafcj32ras_encode_fns, 0, 0 }, + { "ae_mulf2p32x4rs", ICLASS_AE_MULF2P32X4RS, + 0, + Opcode_ae_mulf2p32x4rs_encode_fns, 0, 0 }, + { "ae_mulaf2p32x4rs", ICLASS_AE_MULAF2P32X4RS, + 0, + Opcode_ae_mulaf2p32x4rs_encode_fns, 0, 0 }, + { "ae_mulsf2p32x4rs", ICLASS_AE_MULSF2P32X4RS, + 0, + Opcode_ae_mulsf2p32x4rs_encode_fns, 0, 0 }, + { "ae_mulf2p32x4ras", ICLASS_AE_MULF2P32X4RAS, + 0, + Opcode_ae_mulf2p32x4ras_encode_fns, 0, 0 }, + { "ae_mulaf2p32x4ras", ICLASS_AE_MULAF2P32X4RAS, + 0, + Opcode_ae_mulaf2p32x4ras_encode_fns, 0, 0 }, + { "ae_mulsf2p32x4ras", ICLASS_AE_MULSF2P32X4RAS, + 0, + Opcode_ae_mulsf2p32x4ras_encode_fns, 0, 0 }, + { "ae_mulp32x2s", ICLASS_AE_MULP32X2S, + 0, + Opcode_ae_mulp32x2s_encode_fns, 0, 0 }, + { "ae_mul2p32x4s", ICLASS_AE_MUL2P32X4S, + 0, + Opcode_ae_mul2p32x4s_encode_fns, 0, 0 }, + { "ae_mul2p32x4", ICLASS_AE_MUL2P32X4, + 0, + Opcode_ae_mul2p32x4_encode_fns, 0, 0 }, + { "ae_mula2p32x4", ICLASS_AE_MULA2P32X4, + 0, + Opcode_ae_mula2p32x4_encode_fns, 0, 0 }, + { "ae_muls2p32x4", ICLASS_AE_MULS2P32X4, + 0, + Opcode_ae_muls2p32x4_encode_fns, 0, 0 }, + { "ae_mul2p32x4t", ICLASS_AE_MUL2P32X4T, + 0, + Opcode_ae_mul2p32x4t_encode_fns, 0, 0 }, + { "ae_mula2p32x4t", ICLASS_AE_MULA2P32X4T, + 0, + Opcode_ae_mula2p32x4t_encode_fns, 0, 0 }, + { "ae_muls2p32x4t", ICLASS_AE_MULS2P32X4T, + 0, + Opcode_ae_muls2p32x4t_encode_fns, 0, 0 }, + { "ae_mulzaa32x2.hh.ll", ICLASS_AE_MULZAA32X2_HH_LL, + 0, + Opcode_ae_mulzaa32x2_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzss32x2.hh.ll", ICLASS_AE_MULZSS32X2_HH_LL, + 0, + Opcode_ae_mulzss32x2_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaa32x2.hh.ll", ICLASS_AE_MULAA32X2_HH_LL, + 0, + Opcode_ae_mulaa32x2_hh_ll_encode_fns, 0, 0 }, + { "ae_mulss32x2.hh.ll", ICLASS_AE_MULSS32X2_HH_LL, + 0, + Opcode_ae_mulss32x2_hh_ll_encode_fns, 0, 0 }, + { "ae_mulcj32", ICLASS_AE_MULCJ32, + 0, + Opcode_ae_mulcj32_encode_fns, 0, 0 }, + { "ae_mulacj32", ICLASS_AE_MULACJ32, + 0, + Opcode_ae_mulacj32_encode_fns, 0, 0 }, + { "ae_muladdf32rs", ICLASS_AE_MULADDF32RS, + 0, + Opcode_ae_muladdf32rs_encode_fns, 0, 0 }, + { "ae_muladdf32ras", ICLASS_AE_MULADDF32RAS, + 0, + Opcode_ae_muladdf32ras_encode_fns, 0, 0 }, + { "ae_mulsubf32rs", ICLASS_AE_MULSUBF32RS, + 0, + Opcode_ae_mulsubf32rs_encode_fns, 0, 0 }, + { "ae_mulsubf32ras", ICLASS_AE_MULSUBF32RAS, + 0, + Opcode_ae_mulsubf32ras_encode_fns, 0, 0 }, + { "ae_mulfc32ra", ICLASS_AE_MULFC32RA, + 0, + Opcode_ae_mulfc32ra_encode_fns, 0, 0 }, + { "ae_mulafc32ra", ICLASS_AE_MULAFC32RA, + 0, + Opcode_ae_mulafc32ra_encode_fns, 0, 0 }, + { "ae_mulcj32w", ICLASS_AE_MULCJ32W, + 0, + Opcode_ae_mulcj32w_encode_fns, 0, 0 }, + { "ae_mulacj32w", ICLASS_AE_MULACJ32W, + 0, + Opcode_ae_mulacj32w_encode_fns, 0, 0 }, + { "ae_mulc32w", ICLASS_AE_MULC32W, + 0, + Opcode_ae_mulc32w_encode_fns, 0, 0 }, + { "ae_mulac32w", ICLASS_AE_MULAC32W, + 0, + Opcode_ae_mulac32w_encode_fns, 0, 0 }, + { "ae_mulf2d32x2ws", ICLASS_AE_MULF2D32X2WS, + 0, + Opcode_ae_mulf2d32x2ws_encode_fns, 0, 0 }, + { "ae_mulzaaaa2q16", ICLASS_AE_MULZAAAA2Q16, + 0, + Opcode_ae_mulzaaaa2q16_encode_fns, 0, 0 }, + { "ae_mulaaaa2q16", ICLASS_AE_MULAAAA2Q16, + 0, + Opcode_ae_mulaaaa2q16_encode_fns, 0, 0 }, + { "ae_mulp16s.h", ICLASS_AE_MULP16S_H, + 0, + Opcode_ae_mulp16s_h_encode_fns, 0, 0 }, + { "ae_mulap16s.h", ICLASS_AE_MULAP16S_H, + 0, + Opcode_ae_mulap16s_h_encode_fns, 0, 0 }, + { "ae_mulsp16s.h", ICLASS_AE_MULSP16S_H, + 0, + Opcode_ae_mulsp16s_h_encode_fns, 0, 0 }, + { "ae_mulp16s.l", ICLASS_AE_MULP16S_L, + 0, + Opcode_ae_mulp16s_l_encode_fns, 0, 0 }, + { "ae_mulap16s.l", ICLASS_AE_MULAP16S_L, + 0, + Opcode_ae_mulap16s_l_encode_fns, 0, 0 }, + { "ae_mulsp16s.l", ICLASS_AE_MULSP16S_L, + 0, + Opcode_ae_mulsp16s_l_encode_fns, 0, 0 }, + { "ae_mulc16w.h", ICLASS_AE_MULC16W_H, + 0, + Opcode_ae_mulc16w_h_encode_fns, 0, 0 }, + { "ae_mulac16w.h", ICLASS_AE_MULAC16W_H, + 0, + Opcode_ae_mulac16w_h_encode_fns, 0, 0 }, + { "ae_mulc16w.l", ICLASS_AE_MULC16W_L, + 0, + Opcode_ae_mulc16w_l_encode_fns, 0, 0 }, + { "ae_mulac16w.l", ICLASS_AE_MULAC16W_L, + 0, + Opcode_ae_mulac16w_l_encode_fns, 0, 0 }, + { "ae_mul2c16s", ICLASS_AE_MUL2C16S, + 0, + Opcode_ae_mul2c16s_encode_fns, 0, 0 }, + { "ae_mula2c16s", ICLASS_AE_MULA2C16S, + 0, + Opcode_ae_mula2c16s_encode_fns, 0, 0 }, + { "ae_mulfc16s", ICLASS_AE_MULFC16S, + 0, + Opcode_ae_mulfc16s_encode_fns, 0, 0 }, + { "ae_mulafc16s", ICLASS_AE_MULAFC16S, + 0, + Opcode_ae_mulafc16s_encode_fns, 0, 0 }, + { "ae_mulfcj16s", ICLASS_AE_MULFCJ16S, + 0, + Opcode_ae_mulfcj16s_encode_fns, 0, 0 }, + { "ae_mulafcj16s", ICLASS_AE_MULAFCJ16S, + 0, + Opcode_ae_mulafcj16s_encode_fns, 0, 0 }, + { "ae_mulfcj16ras", ICLASS_AE_MULFCJ16RAS, + 0, + Opcode_ae_mulfcj16ras_encode_fns, 0, 0 }, + { "ae_mulafcj16ras", ICLASS_AE_MULAFCJ16RAS, + 0, + Opcode_ae_mulafcj16ras_encode_fns, 0, 0 }, + { "ae_mulc16s", ICLASS_AE_MULC16S, + 0, + Opcode_ae_mulc16s_encode_fns, 0, 0 }, + { "ae_mulac16s", ICLASS_AE_MULAC16S, + 0, + Opcode_ae_mulac16s_encode_fns, 0, 0 }, + { "ae_mulfp16x4rs", ICLASS_AE_MULFP16X4RS, + 0, + Opcode_ae_mulfp16x4rs_encode_fns, 0, 0 }, + { "ae_mulfd16x16x4ras", ICLASS_AE_MULFD16X16X4RAS, + 0, + Opcode_ae_mulfd16x16x4ras_encode_fns, 0, 0 }, + { "ae_mulp16x16x4s", ICLASS_AE_MULP16X16X4S, + 0, + Opcode_ae_mulp16x16x4s_encode_fns, 0, 0 }, + { "ae_mulap16x16x4s", ICLASS_AE_MULAP16X16X4S, + 0, + Opcode_ae_mulap16x16x4s_encode_fns, 0, 0 }, + { "ae_mulsp16x16x4s", ICLASS_AE_MULSP16X16X4S, + 0, + Opcode_ae_mulsp16x16x4s_encode_fns, 0, 0 }, + { "ae_mulzaa2d16ss.hh_ll", ICLASS_AE_MULZAA2D16SS_HH_LL, + 0, + Opcode_ae_mulzaa2d16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaa2d16ss.hl_lh", ICLASS_AE_MULZAA2D16SS_HL_LH, + 0, + Opcode_ae_mulzaa2d16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzss2d16ss.hh_ll", ICLASS_AE_MULZSS2D16SS_HH_LL, + 0, + Opcode_ae_mulzss2d16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzss2d16ss.hl_lh", ICLASS_AE_MULZSS2D16SS_HL_LH, + 0, + Opcode_ae_mulzss2d16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaa2d16ss.hh_ll", ICLASS_AE_MULAA2D16SS_HH_LL, + 0, + Opcode_ae_mulaa2d16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaa2d16ss.hl_lh", ICLASS_AE_MULAA2D16SS_HL_LH, + 0, + Opcode_ae_mulaa2d16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulss2d16ss.hh_ll", ICLASS_AE_MULSS2D16SS_HH_LL, + 0, + Opcode_ae_mulss2d16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulss2d16ss.hl_lh", ICLASS_AE_MULSS2D16SS_HL_LH, + 0, + Opcode_ae_mulss2d16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaafd16ss.hh_ll", ICLASS_AE_MULZAAFD16SS_HH_LL, + 0, + Opcode_ae_mulzaafd16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaafd16ss.hl_lh", ICLASS_AE_MULZAAFD16SS_HL_LH, + 0, + Opcode_ae_mulzaafd16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssfd16ss.hh_ll", ICLASS_AE_MULZSSFD16SS_HH_LL, + 0, + Opcode_ae_mulzssfd16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssfd16ss.hl_lh", ICLASS_AE_MULZSSFD16SS_HL_LH, + 0, + Opcode_ae_mulzssfd16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaafd16ss.hh_ll", ICLASS_AE_MULAAFD16SS_HH_LL, + 0, + Opcode_ae_mulaafd16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaafd16ss.hl_lh", ICLASS_AE_MULAAFD16SS_HL_LH, + 0, + Opcode_ae_mulaafd16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssfd16ss.hh_ll", ICLASS_AE_MULSSFD16SS_HH_LL, + 0, + Opcode_ae_mulssfd16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssfd16ss.hl_lh", ICLASS_AE_MULSSFD16SS_HL_LH, + 0, + Opcode_ae_mulssfd16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulfd16x16x4ws", ICLASS_AE_MULFD16X16X4WS, + 0, + Opcode_ae_mulfd16x16x4ws_encode_fns, 0, 0 }, + { "ae_mulzaaaa2q16x8", ICLASS_AE_MULZAAAA2Q16X8, + 0, + Opcode_ae_mulzaaaa2q16x8_encode_fns, 0, 0 }, + { "ae_mulaaaa2q16x8", ICLASS_AE_MULAAAA2Q16X8, + 0, + Opcode_ae_mulaaaa2q16x8_encode_fns, 0, 0 }, + { "ae_mulzaaaa2q8", ICLASS_AE_MULZAAAA2Q8, + 0, + Opcode_ae_mulzaaaa2q8_encode_fns, 0, 0 }, + { "ae_mulaaaa2q8", ICLASS_AE_MULAAAA2Q8, + 0, + Opcode_ae_mulaaaa2q8_encode_fns, 0, 0 }, + { "ae_mulc32x16w.h", ICLASS_AE_MULC32X16W_H, + 0, + Opcode_ae_mulc32x16w_h_encode_fns, 0, 0 }, + { "ae_mulac32x16w.h", ICLASS_AE_MULAC32X16W_H, + 0, + Opcode_ae_mulac32x16w_h_encode_fns, 0, 0 }, + { "ae_mulc32x16w.l", ICLASS_AE_MULC32X16W_L, + 0, + Opcode_ae_mulc32x16w_l_encode_fns, 0, 0 }, + { "ae_mulac32x16w.l", ICLASS_AE_MULAC32X16W_L, + 0, + Opcode_ae_mulac32x16w_l_encode_fns, 0, 0 }, + { "ae_mulpc32x16x2", ICLASS_AE_MULPC32X16X2, + 0, + Opcode_ae_mulpc32x16x2_encode_fns, 0, 0 }, + { "ae_mulapc32x16x2", ICLASS_AE_MULAPC32X16X2, + 0, + Opcode_ae_mulapc32x16x2_encode_fns, 0, 0 }, + { "ae_mulfp32x16.h", ICLASS_AE_MULFP32X16_H, + 0, + Opcode_ae_mulfp32x16_h_encode_fns, 0, 0 }, + { "ae_mulafp32x16.h", ICLASS_AE_MULAFP32X16_H, + 0, + Opcode_ae_mulafp32x16_h_encode_fns, 0, 0 }, + { "ae_mulsfp32x16.h", ICLASS_AE_MULSFP32X16_H, + 0, + Opcode_ae_mulsfp32x16_h_encode_fns, 0, 0 }, + { "ae_mulfp32x16.l", ICLASS_AE_MULFP32X16_L, + 0, + Opcode_ae_mulfp32x16_l_encode_fns, 0, 0 }, + { "ae_mulafp32x16.l", ICLASS_AE_MULAFP32X16_L, + 0, + Opcode_ae_mulafp32x16_l_encode_fns, 0, 0 }, + { "ae_mulsfp32x16.l", ICLASS_AE_MULSFP32X16_L, + 0, + Opcode_ae_mulsfp32x16_l_encode_fns, 0, 0 }, + { "ae_mulfc32x16w.h", ICLASS_AE_MULFC32X16W_H, + 0, + Opcode_ae_mulfc32x16w_h_encode_fns, 0, 0 }, + { "ae_mulafc32x16w.h", ICLASS_AE_MULAFC32X16W_H, + 0, + Opcode_ae_mulafc32x16w_h_encode_fns, 0, 0 }, + { "ae_mulfc32x16w.l", ICLASS_AE_MULFC32X16W_L, + 0, + Opcode_ae_mulfc32x16w_l_encode_fns, 0, 0 }, + { "ae_mulafc32x16w.l", ICLASS_AE_MULAFC32X16W_L, + 0, + Opcode_ae_mulafc32x16w_l_encode_fns, 0, 0 }, + { "ae_mulfcj32x16w.h", ICLASS_AE_MULFCJ32X16W_H, + 0, + Opcode_ae_mulfcj32x16w_h_encode_fns, 0, 0 }, + { "ae_mulafcj32x16w.h", ICLASS_AE_MULAFCJ32X16W_H, + 0, + Opcode_ae_mulafcj32x16w_h_encode_fns, 0, 0 }, + { "ae_mulfcj32x16w.l", ICLASS_AE_MULFCJ32X16W_L, + 0, + Opcode_ae_mulfcj32x16w_l_encode_fns, 0, 0 }, + { "ae_mulafcj32x16w.l", ICLASS_AE_MULAFCJ32X16W_L, + 0, + Opcode_ae_mulafcj32x16w_l_encode_fns, 0, 0 }, + { "ae_mulf2p32x16x4ras", ICLASS_AE_MULF2P32X16X4RAS, + 0, + Opcode_ae_mulf2p32x16x4ras_encode_fns, 0, 0 }, + { "ae_mulaf2p32x16x4ras", ICLASS_AE_MULAF2P32X16X4RAS, + 0, + Opcode_ae_mulaf2p32x16x4ras_encode_fns, 0, 0 }, + { "ae_mulsf2p32x16x4ras", ICLASS_AE_MULSF2P32X16X4RAS, + 0, + Opcode_ae_mulsf2p32x16x4ras_encode_fns, 0, 0 }, + { "ae_mulf2p32x16x4rs", ICLASS_AE_MULF2P32X16X4RS, + 0, + Opcode_ae_mulf2p32x16x4rs_encode_fns, 0, 0 }, + { "ae_mulaf2p32x16x4rs", ICLASS_AE_MULAF2P32X16X4RS, + 0, + Opcode_ae_mulaf2p32x16x4rs_encode_fns, 0, 0 }, + { "ae_mulsf2p32x16x4rs", ICLASS_AE_MULSF2P32X16X4RS, + 0, + Opcode_ae_mulsf2p32x16x4rs_encode_fns, 0, 0 }, + { "ae_mulf2p32x16x4s", ICLASS_AE_MULF2P32X16X4S, + 0, + Opcode_ae_mulf2p32x16x4s_encode_fns, 0, 0 }, + { "ae_mulaf2p32x16x4s", ICLASS_AE_MULAF2P32X16X4S, + 0, + Opcode_ae_mulaf2p32x16x4s_encode_fns, 0, 0 }, + { "ae_mulsf2p32x16x4s", ICLASS_AE_MULSF2P32X16X4S, + 0, + Opcode_ae_mulsf2p32x16x4s_encode_fns, 0, 0 }, + { "ae_mulfpc32x16x2ras", ICLASS_AE_MULFPC32X16X2RAS, + 0, + Opcode_ae_mulfpc32x16x2ras_encode_fns, 0, 0 }, + { "ae_mulafpc32x16x2ras", ICLASS_AE_MULAFPC32X16X2RAS, + 0, + Opcode_ae_mulafpc32x16x2ras_encode_fns, 0, 0 }, + { "ae_mulfpcj32x16x2ras", ICLASS_AE_MULFPCJ32X16X2RAS, + 0, + Opcode_ae_mulfpcj32x16x2ras_encode_fns, 0, 0 }, + { "ae_mulafpcj32x16x2ras", ICLASS_AE_MULAFPCJ32X16X2RAS, + 0, + Opcode_ae_mulafpcj32x16x2ras_encode_fns, 0, 0 }, + { "ae_mulzaaaa2q32x16", ICLASS_AE_MULZAAAA2Q32X16, + 0, + Opcode_ae_mulzaaaa2q32x16_encode_fns, 0, 0 }, + { "ae_mulaaaa2q32x16", ICLASS_AE_MULAAAA2Q32X16, + 0, + Opcode_ae_mulaaaa2q32x16_encode_fns, 0, 0 }, + { "ae_mul2q32x16.fir.h", ICLASS_AE_MUL2Q32X16_FIR_H, + 0, + Opcode_ae_mul2q32x16_fir_h_encode_fns, 0, 0 }, + { "ae_mula2q32x16.fir.h", ICLASS_AE_MULA2Q32X16_FIR_H, + 0, + Opcode_ae_mula2q32x16_fir_h_encode_fns, 0, 0 }, + { "ae_mul2q32x16.fir.l", ICLASS_AE_MUL2Q32X16_FIR_L, + 0, + Opcode_ae_mul2q32x16_fir_l_encode_fns, 0, 0 }, + { "ae_mula2q32x16.fir.l", ICLASS_AE_MULA2Q32X16_FIR_L, + 0, + Opcode_ae_mula2q32x16_fir_l_encode_fns, 0, 0 }, + { "ae_srai8", ICLASS_AE_SRAI8, + 0, + Opcode_ae_srai8_encode_fns, 0, 0 }, + { "ae_srai8r", ICLASS_AE_SRAI8R, + 0, + Opcode_ae_srai8r_encode_fns, 0, 0 }, + { "ae_srli8", ICLASS_AE_SRLI8, + 0, + Opcode_ae_srli8_encode_fns, 0, 0 }, + { "ae_slai8", ICLASS_AE_SLAI8, + 0, + Opcode_ae_slai8_encode_fns, 0, 0 }, + { "ae_slai8s", ICLASS_AE_SLAI8S, + 0, + Opcode_ae_slai8s_encode_fns, 0, 0 }, + { "ae_slaa8", ICLASS_AE_SLAA8, + 0, + Opcode_ae_slaa8_encode_fns, 0, 0 }, + { "ae_srla8", ICLASS_AE_SRLA8, + 0, + Opcode_ae_srla8_encode_fns, 0, 0 }, + { "ae_slaa8s", ICLASS_AE_SLAA8S, + 0, + Opcode_ae_slaa8s_encode_fns, 0, 0 }, + { "ae_sraa8rs", ICLASS_AE_SRAA8RS, + 0, + Opcode_ae_sraa8rs_encode_fns, 0, 0 }, + { "ae_sraa8s", ICLASS_AE_SRAA8S, + 0, + Opcode_ae_sraa8s_encode_fns, 0, 0 }, + { "ae_srli16", ICLASS_AE_SRLI16, + 0, + Opcode_ae_srli16_encode_fns, 0, 0 }, + { "ae_slai16", ICLASS_AE_SLAI16, + 0, + Opcode_ae_slai16_encode_fns, 0, 0 }, + { "ae_slaa16", ICLASS_AE_SLAA16, + 0, + Opcode_ae_slaa16_encode_fns, 0, 0 }, + { "ae_srla16", ICLASS_AE_SRLA16, + 0, + Opcode_ae_srla16_encode_fns, 0, 0 }, + { "ae_srai16sym", ICLASS_AE_SRAI16SYM, + 0, + Opcode_ae_srai16sym_encode_fns, 0, 0 }, + { "ae_sraa16syms", ICLASS_AE_SRAA16SYMS, + 0, + Opcode_ae_sraa16syms_encode_fns, 0, 0 }, + { "ae_srai32sym", ICLASS_AE_SRAI32SYM, + 0, + Opcode_ae_srai32sym_encode_fns, 0, 0 }, + { "ae_sraa32syms", ICLASS_AE_SRAA32SYMS, + 0, + Opcode_ae_sraa32syms_encode_fns, 0, 0 }, + { "ae_srav16rs", ICLASS_AE_SRAV16RS, + 0, + Opcode_ae_srav16rs_encode_fns, 0, 0 }, + { "ae_srav32rs", ICLASS_AE_SRAV32RS, + 0, + Opcode_ae_srav32rs_encode_fns, 0, 0 }, + { "ae_cvti32x4f8.h", ICLASS_AE_CVTI32X4F8_H, + 0, + Opcode_ae_cvti32x4f8_h_encode_fns, 0, 0 }, + { "ae_cvti32x4f8.l", ICLASS_AE_CVTI32X4F8_L, + 0, + Opcode_ae_cvti32x4f8_l_encode_fns, 0, 0 }, + { "ae_cvti32x4f8s.h", ICLASS_AE_CVTI32X4F8S_H, + 0, + Opcode_ae_cvti32x4f8s_h_encode_fns, 0, 0 }, + { "ae_cvti32x4f8s.l", ICLASS_AE_CVTI32X4F8S_L, + 0, + Opcode_ae_cvti32x4f8s_l_encode_fns, 0, 0 }, + { "ae_cvta32x4f8.h", ICLASS_AE_CVTA32X4F8_H, + 0, + Opcode_ae_cvta32x4f8_h_encode_fns, 0, 0 }, + { "ae_cvta32x4f8.l", ICLASS_AE_CVTA32X4F8_L, + 0, + Opcode_ae_cvta32x4f8_l_encode_fns, 0, 0 }, + { "ae_cvta32x4f8s.h", ICLASS_AE_CVTA32X4F8S_H, + 0, + Opcode_ae_cvta32x4f8s_h_encode_fns, 0, 0 }, + { "ae_cvta32x4f8s.l", ICLASS_AE_CVTA32X4F8S_L, + 0, + Opcode_ae_cvta32x4f8s_l_encode_fns, 0, 0 }, + { "ae_cvti32x4f8u.h", ICLASS_AE_CVTI32X4F8U_H, + 0, + Opcode_ae_cvti32x4f8u_h_encode_fns, 0, 0 }, + { "ae_cvti32x4f8u.l", ICLASS_AE_CVTI32X4F8U_L, + 0, + Opcode_ae_cvti32x4f8u_l_encode_fns, 0, 0 }, + { "ae_cvti32x4f8us.h", ICLASS_AE_CVTI32X4F8US_H, + 0, + Opcode_ae_cvti32x4f8us_h_encode_fns, 0, 0 }, + { "ae_cvti32x4f8us.l", ICLASS_AE_CVTI32X4F8US_L, + 0, + Opcode_ae_cvti32x4f8us_l_encode_fns, 0, 0 }, + { "ae_cvta32x4f8u.h", ICLASS_AE_CVTA32X4F8U_H, + 0, + Opcode_ae_cvta32x4f8u_h_encode_fns, 0, 0 }, + { "ae_cvta32x4f8u.l", ICLASS_AE_CVTA32X4F8U_L, + 0, + Opcode_ae_cvta32x4f8u_l_encode_fns, 0, 0 }, + { "ae_cvta32x4f8us.h", ICLASS_AE_CVTA32X4F8US_H, + 0, + Opcode_ae_cvta32x4f8us_h_encode_fns, 0, 0 }, + { "ae_cvta32x4f8us.l", ICLASS_AE_CVTA32X4F8US_L, + 0, + Opcode_ae_cvta32x4f8us_l_encode_fns, 0, 0 }, + { "ae_cvti32x4f16", ICLASS_AE_CVTI32X4F16, + 0, + Opcode_ae_cvti32x4f16_encode_fns, 0, 0 }, + { "ae_cvti32x4f16s", ICLASS_AE_CVTI32X4F16S, + 0, + Opcode_ae_cvti32x4f16s_encode_fns, 0, 0 }, + { "ae_cvta32x4f16", ICLASS_AE_CVTA32X4F16, + 0, + Opcode_ae_cvta32x4f16_encode_fns, 0, 0 }, + { "ae_cvta32x4f16s", ICLASS_AE_CVTA32X4F16S, + 0, + Opcode_ae_cvta32x4f16s_encode_fns, 0, 0 }, + { "ae_cvti32x4f16u", ICLASS_AE_CVTI32X4F16U, + 0, + Opcode_ae_cvti32x4f16u_encode_fns, 0, 0 }, + { "ae_cvti32x4f16us", ICLASS_AE_CVTI32X4F16US, + 0, + Opcode_ae_cvti32x4f16us_encode_fns, 0, 0 }, + { "ae_cvta32x4f16u", ICLASS_AE_CVTA32X4F16U, + 0, + Opcode_ae_cvta32x4f16u_encode_fns, 0, 0 }, + { "ae_cvta32x4f16us", ICLASS_AE_CVTA32X4F16US, + 0, + Opcode_ae_cvta32x4f16us_encode_fns, 0, 0 }, + { "ae_cvti16x4x2f8", ICLASS_AE_CVTI16X4X2F8, + 0, + Opcode_ae_cvti16x4x2f8_encode_fns, 0, 0 }, + { "ae_cvti16x4x2f8s", ICLASS_AE_CVTI16X4X2F8S, + 0, + Opcode_ae_cvti16x4x2f8s_encode_fns, 0, 0 }, + { "ae_cvta16x4x2f8", ICLASS_AE_CVTA16X4X2F8, + 0, + Opcode_ae_cvta16x4x2f8_encode_fns, 0, 0 }, + { "ae_cvta16x4x2f8s", ICLASS_AE_CVTA16X4X2F8S, + 0, + Opcode_ae_cvta16x4x2f8s_encode_fns, 0, 0 }, + { "ae_cvti16x4x2f8u", ICLASS_AE_CVTI16X4X2F8U, + 0, + Opcode_ae_cvti16x4x2f8u_encode_fns, 0, 0 }, + { "ae_cvti16x4x2f8us", ICLASS_AE_CVTI16X4X2F8US, + 0, + Opcode_ae_cvti16x4x2f8us_encode_fns, 0, 0 }, + { "ae_cvta16x4x2f8u", ICLASS_AE_CVTA16X4X2F8U, + 0, + Opcode_ae_cvta16x4x2f8u_encode_fns, 0, 0 }, + { "ae_cvta16x4x2f8us", ICLASS_AE_CVTA16X4X2F8US, + 0, + Opcode_ae_cvta16x4x2f8us_encode_fns, 0, 0 }, + { "ae_sel8x8", ICLASS_AE_SEL8X8, + 0, + Opcode_ae_sel8x8_encode_fns, 0, 0 }, + { "ae_shfl8x8", ICLASS_AE_SHFL8X8, + 0, + Opcode_ae_shfl8x8_encode_fns, 0, 0 }, + { "ae_sel16x4", ICLASS_AE_SEL16X4, + 0, + Opcode_ae_sel16x4_encode_fns, 0, 0 }, + { "ae_shfl16x4", ICLASS_AE_SHFL16X4, + 0, + Opcode_ae_shfl16x4_encode_fns, 0, 0 }, + { "ae_dsel8x8", ICLASS_AE_DSEL8X8, + 0, + Opcode_ae_dsel8x8_encode_fns, 0, 0 }, + { "ae_dsel16x4", ICLASS_AE_DSEL16X4, + 0, + Opcode_ae_dsel16x4_encode_fns, 0, 0 }, + { "ae_sel8x8i", ICLASS_AE_SEL8X8I, + 0, + Opcode_ae_sel8x8i_encode_fns, 0, 0 }, + { "ae_rmax8x8", ICLASS_AE_RMAX8X8, + 0, + Opcode_ae_rmax8x8_encode_fns, 0, 0 }, + { "ae_rmin8x8", ICLASS_AE_RMIN8X8, + 0, + Opcode_ae_rmin8x8_encode_fns, 0, 0 }, + { "ae_rmax16x4", ICLASS_AE_RMAX16X4, + 0, + Opcode_ae_rmax16x4_encode_fns, 0, 0 }, + { "ae_rmin16x4", ICLASS_AE_RMIN16X4, + 0, + Opcode_ae_rmin16x4_encode_fns, 0, 0 }, + { "ae_sort16x4", ICLASS_AE_SORT16X4, + 0, + Opcode_ae_sort16x4_encode_fns, 0, 0 }, + { "ae_radd8x8.h", ICLASS_AE_RADD8X8_H, + 0, + Opcode_ae_radd8x8_h_encode_fns, 0, 0 }, + { "ae_radda8x8.h", ICLASS_AE_RADDA8X8_H, + 0, + Opcode_ae_radda8x8_h_encode_fns, 0, 0 }, + { "ae_radd8x8.l", ICLASS_AE_RADD8X8_L, + 0, + Opcode_ae_radd8x8_l_encode_fns, 0, 0 }, + { "ae_radda8x8.l", ICLASS_AE_RADDA8X8_L, + 0, + Opcode_ae_radda8x8_l_encode_fns, 0, 0 }, + { "ae_radd16x4", ICLASS_AE_RADD16X4, + 0, + Opcode_ae_radd16x4_encode_fns, 0, 0 }, + { "ae_radda16x4", ICLASS_AE_RADDA16X4, + 0, + Opcode_ae_radda16x4_encode_fns, 0, 0 }, + { "ae_bmax8x8.h", ICLASS_AE_BMAX8X8_H, + 0, + Opcode_ae_bmax8x8_h_encode_fns, 0, 0 }, + { "ae_bmax8x8.l", ICLASS_AE_BMAX8X8_L, + 0, + Opcode_ae_bmax8x8_l_encode_fns, 0, 0 }, + { "ae_bmin8x8.h", ICLASS_AE_BMIN8X8_H, + 0, + Opcode_ae_bmin8x8_h_encode_fns, 0, 0 }, + { "ae_bmin8x8.l", ICLASS_AE_BMIN8X8_L, + 0, + Opcode_ae_bmin8x8_l_encode_fns, 0, 0 }, + { "ae_bmax16x4", ICLASS_AE_BMAX16X4, + 0, + Opcode_ae_bmax16x4_encode_fns, 0, 0 }, + { "ae_bmin16x4", ICLASS_AE_BMIN16X4, + 0, + Opcode_ae_bmin16x4_encode_fns, 0, 0 }, + { "ae_bmax32x2", ICLASS_AE_BMAX32X2, + 0, + Opcode_ae_bmax32x2_encode_fns, 0, 0 }, + { "ae_bmin32x2", ICLASS_AE_BMIN32X2, + 0, + Opcode_ae_bmin32x2_encode_fns, 0, 0 }, + { "ae_addinv16s", ICLASS_AE_ADDINV16S, + 0, + Opcode_ae_addinv16s_encode_fns, 0, 0 }, + { "ae_addinv32s", ICLASS_AE_ADDINV32S, + 0, + Opcode_ae_addinv32s_encode_fns, 0, 0 }, + { "ae_movt16x8", ICLASS_AE_MOVT16X8, + 0, + Opcode_ae_movt16x8_encode_fns, 0, 0 }, + { "ae_movt8x16.h", ICLASS_AE_MOVT8X16_H, + 0, + Opcode_ae_movt8x16_h_encode_fns, 0, 0 }, + { "ae_movt8x16.l", ICLASS_AE_MOVT8X16_L, + 0, + Opcode_ae_movt8x16_l_encode_fns, 0, 0 }, + { "ae_movbd1x4", ICLASS_AE_MOVBD1X4, + 0, + Opcode_ae_movbd1x4_encode_fns, 0, 0 }, + { "ae_movbd1x2", ICLASS_AE_MOVBD1X2, + 0, + Opcode_ae_movbd1x2_encode_fns, 0, 0 }, + { "ae_movneg32s_t", ICLASS_AE_MOVNEG32S_T, + 0, + Opcode_ae_movneg32s_t_encode_fns, 0, 0 }, + { "ae_movdext", ICLASS_AE_MOVDEXT, + 0, + Opcode_ae_movdext_encode_fns, 0, 0 }, + { "ae_movadext.h", ICLASS_AE_MOVADEXT_H, + 0, + Opcode_ae_movadext_h_encode_fns, 0, 0 }, + { "ae_movadext.l", ICLASS_AE_MOVADEXT_L, + 0, + Opcode_ae_movadext_l_encode_fns, 0, 0 }, + { "ae_nsa16x4", ICLASS_AE_NSA16X4, + 0, + Opcode_ae_nsa16x4_encode_fns, 0, 0 }, + { "ae_nsaz32x4", ICLASS_AE_NSAZ32X4, + 0, + Opcode_ae_nsaz32x4_encode_fns, 0, 0 }, + { "ae_nsa32x4", ICLASS_AE_NSA32X4, + 0, + Opcode_ae_nsa32x4_encode_fns, 0, 0 }, + { "ae_trunci16x4f32s", ICLASS_AE_TRUNCI16X4F32S, + 0, + Opcode_ae_trunci16x4f32s_encode_fns, 0, 0 }, + { "ae_trunci16x4f64s", ICLASS_AE_TRUNCI16X4F64S, + 0, + Opcode_ae_trunci16x4f64s_encode_fns, 0, 0 }, + { "ae_trunca16x4f32s", ICLASS_AE_TRUNCA16X4F32S, + 0, + Opcode_ae_trunca16x4f32s_encode_fns, 0, 0 }, + { "ae_trunca16x4f64s", ICLASS_AE_TRUNCA16X4F64S, + 0, + Opcode_ae_trunca16x4f64s_encode_fns, 0, 0 }, + { "ae_addc32", ICLASS_AE_ADDC32, + 0, + Opcode_ae_addc32_encode_fns, 0, 0 }, + { "ae_subc32", ICLASS_AE_SUBC32, + 0, + Opcode_ae_subc32_encode_fns, 0, 0 }, + { "ae_addc32u", ICLASS_AE_ADDC32U, + 0, + Opcode_ae_addc32u_encode_fns, 0, 0 }, + { "ae_subc32u", ICLASS_AE_SUBC32U, + 0, + Opcode_ae_subc32u_encode_fns, 0, 0 }, + { "ae_expadd16.h", ICLASS_AE_EXPADD16_H, + 0, + Opcode_ae_expadd16_h_encode_fns, 0, 0 }, + { "ae_expsub16.h", ICLASS_AE_EXPSUB16_H, + 0, + Opcode_ae_expsub16_h_encode_fns, 0, 0 }, + { "ae_expadd16.l", ICLASS_AE_EXPADD16_L, + 0, + Opcode_ae_expadd16_l_encode_fns, 0, 0 }, + { "ae_expsub16.l", ICLASS_AE_EXPSUB16_L, + 0, + Opcode_ae_expsub16_l_encode_fns, 0, 0 }, + { "ae_addcexp32.h", ICLASS_AE_ADDCEXP32_H, + 0, + Opcode_ae_addcexp32_h_encode_fns, 0, 0 }, + { "ae_addcexp32.l", ICLASS_AE_ADDCEXP32_L, + 0, + Opcode_ae_addcexp32_l_encode_fns, 0, 0 }, + { "ae_calcrng16", ICLASS_AE_CALCRNG16, + 0, + Opcode_ae_calcrng16_encode_fns, 0, 0 }, + { "ae_calcrng32", ICLASS_AE_CALCRNG32, + 0, + Opcode_ae_calcrng32_encode_fns, 0, 0 }, + { "ae_rng32x4", ICLASS_AE_RNG32X4, + 0, + Opcode_ae_rng32x4_encode_fns, 0, 0 }, + { "ae_lav8x8x2_xp", ICLASS_AE_LAV8X8X2_XP, + 0, + Opcode_ae_lav8x8x2_xp_encode_fns, 1, Opcode_ae_lav8x8x2_xp_funcUnit_uses }, + { "ae_lav16x4x2_xp", ICLASS_AE_LAV16X4X2_XP, + 0, + Opcode_ae_lav16x4x2_xp_encode_fns, 1, Opcode_ae_lav16x4x2_xp_funcUnit_uses }, + { "ae_sav8x8x2_xp", ICLASS_AE_SAV8X8X2_XP, + 0, + Opcode_ae_sav8x8x2_xp_encode_fns, 1, Opcode_ae_sav8x8x2_xp_funcUnit_uses }, + { "ae_sav16x4x2_xp", ICLASS_AE_SAV16X4X2_XP, + 0, + Opcode_ae_sav16x4x2_xp_encode_fns, 1, Opcode_ae_sav16x4x2_xp_funcUnit_uses }, + { "ae_movzbvcdr", ICLASS_AE_MOVZBVCDR, + 0, + Opcode_ae_movzbvcdr_encode_fns, 0, 0 }, + { "ae_movdrzbvc", ICLASS_AE_MOVDRZBVC, + 0, + Opcode_ae_movdrzbvc_encode_fns, 0, 0 }, + { "ae_lavunsqz8x8_xp", ICLASS_AE_LAVUNSQZ8X8_XP, + 0, + Opcode_ae_lavunsqz8x8_xp_encode_fns, 1, Opcode_ae_lavunsqz8x8_xp_funcUnit_uses }, + { "ae_lavunsqz16x4_xp", ICLASS_AE_LAVUNSQZ16X4_XP, + 0, + Opcode_ae_lavunsqz16x4_xp_encode_fns, 1, Opcode_ae_lavunsqz16x4_xp_funcUnit_uses }, + { "ae_mul8q8x8", ICLASS_AE_MUL8Q8X8, + 0, + Opcode_ae_mul8q8x8_encode_fns, 0, 0 }, + { "ae_mula8q8x8", ICLASS_AE_MULA8Q8X8, + 0, + Opcode_ae_mula8q8x8_encode_fns, 0, 0 }, + { "ae_mul8q4x16", ICLASS_AE_MUL8Q4X16, + 0, + Opcode_ae_mul8q4x16_encode_fns, 0, 0 }, + { "ae_mula8q4x16", ICLASS_AE_MULA8Q4X16, + 0, + Opcode_ae_mula8q4x16_encode_fns, 0, 0 }, + { "ae_mul8q8x16", ICLASS_AE_MUL8Q8X16, + 0, + Opcode_ae_mul8q8x16_encode_fns, 0, 0 }, + { "ae_mula8q8x16", ICLASS_AE_MULA8Q8X16, + 0, + Opcode_ae_mula8q8x16_encode_fns, 0, 0 }, + { "ae_mul8qw8x16", ICLASS_AE_MUL8QW8X16, + 0, + Opcode_ae_mul8qw8x16_encode_fns, 0, 0 }, + { "ae_mula8qw8x16", ICLASS_AE_MULA8QW8X16, + 0, + Opcode_ae_mula8qw8x16_encode_fns, 0, 0 }, + { "ae_mul4o8x8", ICLASS_AE_MUL4O8X8, + 0, + Opcode_ae_mul4o8x8_encode_fns, 0, 0 }, + { "ae_mula4o8x8", ICLASS_AE_MULA4O8X8, + 0, + Opcode_ae_mula4o8x8_encode_fns, 0, 0 }, + { "ae_mul4o4x16", ICLASS_AE_MUL4O4X16, + 0, + Opcode_ae_mul4o4x16_encode_fns, 0, 0 }, + { "ae_mula4o4x16", ICLASS_AE_MULA4O4X16, + 0, + Opcode_ae_mula4o4x16_encode_fns, 0, 0 }, + { "ae_mul4o8x16", ICLASS_AE_MUL4O8X16, + 0, + Opcode_ae_mul4o8x16_encode_fns, 0, 0 }, + { "ae_mula4o8x16", ICLASS_AE_MULA4O8X16, + 0, + Opcode_ae_mula4o8x16_encode_fns, 0, 0 }, + { "ae_mul4qw8x16", ICLASS_AE_MUL4QW8X16, + 0, + Opcode_ae_mul4qw8x16_encode_fns, 0, 0 }, + { "ae_mula4qw8x16", ICLASS_AE_MULA4QW8X16, + 0, + Opcode_ae_mula4qw8x16_encode_fns, 0, 0 }, + { "ae_mul8q8x8cnv_l", ICLASS_AE_MUL8Q8X8CNV_L, + 0, + Opcode_ae_mul8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mul8q8x8cnv_h", ICLASS_AE_MUL8Q8X8CNV_H, + 0, + Opcode_ae_mul8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mula8q8x8cnv_l", ICLASS_AE_MULA8Q8X8CNV_L, + 0, + Opcode_ae_mula8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mula8q8x8cnv_h", ICLASS_AE_MULA8Q8X8CNV_H, + 0, + Opcode_ae_mula8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mul8q8x16cnv", ICLASS_AE_MUL8Q8X16CNV, + 0, + Opcode_ae_mul8q8x16cnv_encode_fns, 0, 0 }, + { "ae_mula8q8x16cnv", ICLASS_AE_MULA8Q8X16CNV, + 0, + Opcode_ae_mula8q8x16cnv_encode_fns, 0, 0 }, + { "ae_mul2x4q8x8cnv_h", ICLASS_AE_MUL2X4Q8X8CNV_H, + 0, + Opcode_ae_mul2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mula2x4q8x8cnv_h", ICLASS_AE_MULA2X4Q8X8CNV_H, + 0, + Opcode_ae_mula2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mul2x4q8x8cnv_l", ICLASS_AE_MUL2X4Q8X8CNV_L, + 0, + Opcode_ae_mul2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mula2x4q8x8cnv_l", ICLASS_AE_MULA2X4Q8X8CNV_L, + 0, + Opcode_ae_mula2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mul2x4q8x16cnv", ICLASS_AE_MUL2X4Q8X16CNV, + 0, + Opcode_ae_mul2x4q8x16cnv_encode_fns, 0, 0 }, + { "ae_mula2x4q8x16cnv", ICLASS_AE_MULA2X4Q8X16CNV, + 0, + Opcode_ae_mula2x4q8x16cnv_encode_fns, 0, 0 }, + { "ae_mulqq8x16cnv", ICLASS_AE_MULQQ8X16CNV, + 0, + Opcode_ae_mulqq8x16cnv_encode_fns, 0, 0 }, + { "ae_mulaqq8x16cnv", ICLASS_AE_MULAQQ8X16CNV, + 0, + Opcode_ae_mulaqq8x16cnv_encode_fns, 0, 0 }, + { "ae_mul4o8x8cnv_h", ICLASS_AE_MUL4O8X8CNV_H, + 0, + Opcode_ae_mul4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mula4o8x8cnv_h", ICLASS_AE_MULA4O8X8CNV_H, + 0, + Opcode_ae_mula4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mul4o8x8cnv_l", ICLASS_AE_MUL4O8X8CNV_L, + 0, + Opcode_ae_mul4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mula4o8x8cnv_l", ICLASS_AE_MULA4O8X8CNV_L, + 0, + Opcode_ae_mula4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mul4o8x16cnv_h", ICLASS_AE_MUL4O8X16CNV_H, + 0, + Opcode_ae_mul4o8x16cnv_h_encode_fns, 0, 0 }, + { "ae_mula4o8x16cnv_h", ICLASS_AE_MULA4O8X16CNV_H, + 0, + Opcode_ae_mula4o8x16cnv_h_encode_fns, 0, 0 }, + { "ae_mul4o8x16cnv_l", ICLASS_AE_MUL4O8X16CNV_L, + 0, + Opcode_ae_mul4o8x16cnv_l_encode_fns, 0, 0 }, + { "ae_mula4o8x16cnv_l", ICLASS_AE_MULA4O8X16CNV_L, + 0, + Opcode_ae_mula4o8x16cnv_l_encode_fns, 0, 0 }, + { "ae_mul8q4x16cnv_h", ICLASS_AE_MUL8Q4X16CNV_H, + 0, + Opcode_ae_mul8q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mula8q4x16cnv_h", ICLASS_AE_MULA8Q4X16CNV_H, + 0, + Opcode_ae_mula8q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mul8q4x16cnv_l", ICLASS_AE_MUL8Q4X16CNV_L, + 0, + Opcode_ae_mul8q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mula8q4x16cnv_l", ICLASS_AE_MULA8Q4X16CNV_L, + 0, + Opcode_ae_mula8q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mul2x4q4x16cnv_h", ICLASS_AE_MUL2X4Q4X16CNV_H, + 0, + Opcode_ae_mul2x4q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mula2x4q4x16cnv_h", ICLASS_AE_MULA2X4Q4X16CNV_H, + 0, + Opcode_ae_mula2x4q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mul2x4q4x16cnv_l", ICLASS_AE_MUL2X4Q4X16CNV_L, + 0, + Opcode_ae_mul2x4q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mula2x4q4x16cnv_l", ICLASS_AE_MULA2X4Q4X16CNV_L, + 0, + Opcode_ae_mula2x4q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulqq4x16cnv_h", ICLASS_AE_MULQQ4X16CNV_H, + 0, + Opcode_ae_mulqq4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulaqq4x16cnv_h", ICLASS_AE_MULAQQ4X16CNV_H, + 0, + Opcode_ae_mulaqq4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulqq4x16cnv_l", ICLASS_AE_MULQQ4X16CNV_L, + 0, + Opcode_ae_mulqq4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulaqq4x16cnv_l", ICLASS_AE_MULAQQ4X16CNV_L, + 0, + Opcode_ae_mulaqq4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mul4o4x16cnv_hh", ICLASS_AE_MUL4O4X16CNV_HH, + 0, + Opcode_ae_mul4o4x16cnv_hh_encode_fns, 0, 0 }, + { "ae_mul4o4x16cnv_hl", ICLASS_AE_MUL4O4X16CNV_HL, + 0, + Opcode_ae_mul4o4x16cnv_hl_encode_fns, 0, 0 }, + { "ae_mul4o4x16cnv_lh", ICLASS_AE_MUL4O4X16CNV_LH, + 0, + Opcode_ae_mul4o4x16cnv_lh_encode_fns, 0, 0 }, + { "ae_mul4o4x16cnv_ll", ICLASS_AE_MUL4O4X16CNV_LL, + 0, + Opcode_ae_mul4o4x16cnv_ll_encode_fns, 0, 0 }, + { "ae_mula4o4x16cnv_hh", ICLASS_AE_MULA4O4X16CNV_HH, + 0, + Opcode_ae_mula4o4x16cnv_hh_encode_fns, 0, 0 }, + { "ae_mula4o4x16cnv_hl", ICLASS_AE_MULA4O4X16CNV_HL, + 0, + Opcode_ae_mula4o4x16cnv_hl_encode_fns, 0, 0 }, + { "ae_mula4o4x16cnv_lh", ICLASS_AE_MULA4O4X16CNV_LH, + 0, + Opcode_ae_mula4o4x16cnv_lh_encode_fns, 0, 0 }, + { "ae_mula4o4x16cnv_ll", ICLASS_AE_MULA4O4X16CNV_LL, + 0, + Opcode_ae_mula4o4x16cnv_ll_encode_fns, 0, 0 }, + { "ae_muluu8q8x8", ICLASS_AE_MULUU8Q8X8, + 0, + Opcode_ae_muluu8q8x8_encode_fns, 0, 0 }, + { "ae_mulauu8q8x8", ICLASS_AE_MULAUU8Q8X8, + 0, + Opcode_ae_mulauu8q8x8_encode_fns, 0, 0 }, + { "ae_muluu4o8x8", ICLASS_AE_MULUU4O8X8, + 0, + Opcode_ae_muluu4o8x8_encode_fns, 0, 0 }, + { "ae_mulauu4o8x8", ICLASS_AE_MULAUU4O8X8, + 0, + Opcode_ae_mulauu4o8x8_encode_fns, 0, 0 }, + { "ae_muluu8q8x8cnv_l", ICLASS_AE_MULUU8Q8X8CNV_L, + 0, + Opcode_ae_muluu8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauu8q8x8cnv_l", ICLASS_AE_MULAUU8Q8X8CNV_L, + 0, + Opcode_ae_mulauu8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluu8q8x8cnv_h", ICLASS_AE_MULUU8Q8X8CNV_H, + 0, + Opcode_ae_muluu8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauu8q8x8cnv_h", ICLASS_AE_MULAUU8Q8X8CNV_H, + 0, + Opcode_ae_mulauu8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluu2x4q8x8cnv_h", ICLASS_AE_MULUU2X4Q8X8CNV_H, + 0, + Opcode_ae_muluu2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauu2x4q8x8cnv_h", ICLASS_AE_MULAUU2X4Q8X8CNV_H, + 0, + Opcode_ae_mulauu2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluu2x4q8x8cnv_l", ICLASS_AE_MULUU2X4Q8X8CNV_L, + 0, + Opcode_ae_muluu2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauu2x4q8x8cnv_l", ICLASS_AE_MULAUU2X4Q8X8CNV_L, + 0, + Opcode_ae_mulauu2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluu4o8x8cnv_h", ICLASS_AE_MULUU4O8X8CNV_H, + 0, + Opcode_ae_muluu4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauu4o8x8cnv_h", ICLASS_AE_MULAUU4O8X8CNV_H, + 0, + Opcode_ae_mulauu4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluu4o8x8cnv_l", ICLASS_AE_MULUU4O8X8CNV_L, + 0, + Opcode_ae_muluu4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauu4o8x8cnv_l", ICLASS_AE_MULAUU4O8X8CNV_L, + 0, + Opcode_ae_mulauu4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulus8q8x8", ICLASS_AE_MULUS8Q8X8, + 0, + Opcode_ae_mulus8q8x8_encode_fns, 0, 0 }, + { "ae_mulaus8q8x8", ICLASS_AE_MULAUS8Q8X8, + 0, + Opcode_ae_mulaus8q8x8_encode_fns, 0, 0 }, + { "ae_mulus8q4x16", ICLASS_AE_MULUS8Q4X16, + 0, + Opcode_ae_mulus8q4x16_encode_fns, 0, 0 }, + { "ae_mulaus8q4x16", ICLASS_AE_MULAUS8Q4X16, + 0, + Opcode_ae_mulaus8q4x16_encode_fns, 0, 0 }, + { "ae_mulus8q8x16", ICLASS_AE_MULUS8Q8X16, + 0, + Opcode_ae_mulus8q8x16_encode_fns, 0, 0 }, + { "ae_mulaus8q8x16", ICLASS_AE_MULAUS8Q8X16, + 0, + Opcode_ae_mulaus8q8x16_encode_fns, 0, 0 }, + { "ae_mulus8qw8x16", ICLASS_AE_MULUS8QW8X16, + 0, + Opcode_ae_mulus8qw8x16_encode_fns, 0, 0 }, + { "ae_mulaus8qw8x16", ICLASS_AE_MULAUS8QW8X16, + 0, + Opcode_ae_mulaus8qw8x16_encode_fns, 0, 0 }, + { "ae_mulus4o8x8", ICLASS_AE_MULUS4O8X8, + 0, + Opcode_ae_mulus4o8x8_encode_fns, 0, 0 }, + { "ae_mulaus4o8x8", ICLASS_AE_MULAUS4O8X8, + 0, + Opcode_ae_mulaus4o8x8_encode_fns, 0, 0 }, + { "ae_mulus4o4x16", ICLASS_AE_MULUS4O4X16, + 0, + Opcode_ae_mulus4o4x16_encode_fns, 0, 0 }, + { "ae_mulaus4o4x16", ICLASS_AE_MULAUS4O4X16, + 0, + Opcode_ae_mulaus4o4x16_encode_fns, 0, 0 }, + { "ae_mulus4o8x16", ICLASS_AE_MULUS4O8X16, + 0, + Opcode_ae_mulus4o8x16_encode_fns, 0, 0 }, + { "ae_mulaus4o8x16", ICLASS_AE_MULAUS4O8X16, + 0, + Opcode_ae_mulaus4o8x16_encode_fns, 0, 0 }, + { "ae_mulus4qw8x16", ICLASS_AE_MULUS4QW8X16, + 0, + Opcode_ae_mulus4qw8x16_encode_fns, 0, 0 }, + { "ae_mulaus4qw8x16", ICLASS_AE_MULAUS4QW8X16, + 0, + Opcode_ae_mulaus4qw8x16_encode_fns, 0, 0 }, + { "ae_mulus8q8x8cnv_l", ICLASS_AE_MULUS8Q8X8CNV_L, + 0, + Opcode_ae_mulus8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulaus8q8x8cnv_l", ICLASS_AE_MULAUS8Q8X8CNV_L, + 0, + Opcode_ae_mulaus8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulus8q8x8cnv_h", ICLASS_AE_MULUS8Q8X8CNV_H, + 0, + Opcode_ae_mulus8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulaus8q8x8cnv_h", ICLASS_AE_MULAUS8Q8X8CNV_H, + 0, + Opcode_ae_mulaus8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulus8q8x16cnv", ICLASS_AE_MULUS8Q8X16CNV, + 0, + Opcode_ae_mulus8q8x16cnv_encode_fns, 0, 0 }, + { "ae_mulaus8q8x16cnv", ICLASS_AE_MULAUS8Q8X16CNV, + 0, + Opcode_ae_mulaus8q8x16cnv_encode_fns, 0, 0 }, + { "ae_mulus2x4q8x8cnv_h", ICLASS_AE_MULUS2X4Q8X8CNV_H, + 0, + Opcode_ae_mulus2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulaus2x4q8x8cnv_h", ICLASS_AE_MULAUS2X4Q8X8CNV_H, + 0, + Opcode_ae_mulaus2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulus2x4q8x8cnv_l", ICLASS_AE_MULUS2X4Q8X8CNV_L, + 0, + Opcode_ae_mulus2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulaus2x4q8x8cnv_l", ICLASS_AE_MULAUS2X4Q8X8CNV_L, + 0, + Opcode_ae_mulaus2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulus2x4q8x16cnv", ICLASS_AE_MULUS2X4Q8X16CNV, + 0, + Opcode_ae_mulus2x4q8x16cnv_encode_fns, 0, 0 }, + { "ae_mulaus2x4q8x16cnv", ICLASS_AE_MULAUS2X4Q8X16CNV, + 0, + Opcode_ae_mulaus2x4q8x16cnv_encode_fns, 0, 0 }, + { "ae_mulusqq8x16cnv", ICLASS_AE_MULUSQQ8X16CNV, + 0, + Opcode_ae_mulusqq8x16cnv_encode_fns, 0, 0 }, + { "ae_mulausqq8x16cnv", ICLASS_AE_MULAUSQQ8X16CNV, + 0, + Opcode_ae_mulausqq8x16cnv_encode_fns, 0, 0 }, + { "ae_mulus4o8x8cnv_h", ICLASS_AE_MULUS4O8X8CNV_H, + 0, + Opcode_ae_mulus4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulaus4o8x8cnv_h", ICLASS_AE_MULAUS4O8X8CNV_H, + 0, + Opcode_ae_mulaus4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulus4o8x8cnv_l", ICLASS_AE_MULUS4O8X8CNV_L, + 0, + Opcode_ae_mulus4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulaus4o8x8cnv_l", ICLASS_AE_MULAUS4O8X8CNV_L, + 0, + Opcode_ae_mulaus4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulus4o8x16cnv_h", ICLASS_AE_MULUS4O8X16CNV_H, + 0, + Opcode_ae_mulus4o8x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulaus4o8x16cnv_h", ICLASS_AE_MULAUS4O8X16CNV_H, + 0, + Opcode_ae_mulaus4o8x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulus4o8x16cnv_l", ICLASS_AE_MULUS4O8X16CNV_L, + 0, + Opcode_ae_mulus4o8x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulaus4o8x16cnv_l", ICLASS_AE_MULAUS4O8X16CNV_L, + 0, + Opcode_ae_mulaus4o8x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulus8q4x16cnv_h", ICLASS_AE_MULUS8Q4X16CNV_H, + 0, + Opcode_ae_mulus8q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulaus8q4x16cnv_h", ICLASS_AE_MULAUS8Q4X16CNV_H, + 0, + Opcode_ae_mulaus8q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulus8q4x16cnv_l", ICLASS_AE_MULUS8Q4X16CNV_L, + 0, + Opcode_ae_mulus8q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulaus8q4x16cnv_l", ICLASS_AE_MULAUS8Q4X16CNV_L, + 0, + Opcode_ae_mulaus8q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulus2x4q4x16cnv_h", ICLASS_AE_MULUS2X4Q4X16CNV_H, + 0, + Opcode_ae_mulus2x4q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulaus2x4q4x16cnv_h", ICLASS_AE_MULAUS2X4Q4X16CNV_H, + 0, + Opcode_ae_mulaus2x4q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulus2x4q4x16cnv_l", ICLASS_AE_MULUS2X4Q4X16CNV_L, + 0, + Opcode_ae_mulus2x4q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulaus2x4q4x16cnv_l", ICLASS_AE_MULAUS2X4Q4X16CNV_L, + 0, + Opcode_ae_mulaus2x4q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulusqq4x16cnv_h", ICLASS_AE_MULUSQQ4X16CNV_H, + 0, + Opcode_ae_mulusqq4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulausqq4x16cnv_h", ICLASS_AE_MULAUSQQ4X16CNV_H, + 0, + Opcode_ae_mulausqq4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulusqq4x16cnv_l", ICLASS_AE_MULUSQQ4X16CNV_L, + 0, + Opcode_ae_mulusqq4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulausqq4x16cnv_l", ICLASS_AE_MULAUSQQ4X16CNV_L, + 0, + Opcode_ae_mulausqq4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulus4o4x16cnv_hh", ICLASS_AE_MULUS4O4X16CNV_HH, + 0, + Opcode_ae_mulus4o4x16cnv_hh_encode_fns, 0, 0 }, + { "ae_mulus4o4x16cnv_hl", ICLASS_AE_MULUS4O4X16CNV_HL, + 0, + Opcode_ae_mulus4o4x16cnv_hl_encode_fns, 0, 0 }, + { "ae_mulus4o4x16cnv_lh", ICLASS_AE_MULUS4O4X16CNV_LH, + 0, + Opcode_ae_mulus4o4x16cnv_lh_encode_fns, 0, 0 }, + { "ae_mulus4o4x16cnv_ll", ICLASS_AE_MULUS4O4X16CNV_LL, + 0, + Opcode_ae_mulus4o4x16cnv_ll_encode_fns, 0, 0 }, + { "ae_mulaus4o4x16cnv_hh", ICLASS_AE_MULAUS4O4X16CNV_HH, + 0, + Opcode_ae_mulaus4o4x16cnv_hh_encode_fns, 0, 0 }, + { "ae_mulaus4o4x16cnv_hl", ICLASS_AE_MULAUS4O4X16CNV_HL, + 0, + Opcode_ae_mulaus4o4x16cnv_hl_encode_fns, 0, 0 }, + { "ae_mulaus4o4x16cnv_lh", ICLASS_AE_MULAUS4O4X16CNV_LH, + 0, + Opcode_ae_mulaus4o4x16cnv_lh_encode_fns, 0, 0 }, + { "ae_mulaus4o4x16cnv_ll", ICLASS_AE_MULAUS4O4X16CNV_LL, + 0, + Opcode_ae_mulaus4o4x16cnv_ll_encode_fns, 0, 0 }, + { "ae_mulsu8q8x8", ICLASS_AE_MULSU8Q8X8, + 0, + Opcode_ae_mulsu8q8x8_encode_fns, 0, 0 }, + { "ae_mulasu8q8x8", ICLASS_AE_MULASU8Q8X8, + 0, + Opcode_ae_mulasu8q8x8_encode_fns, 0, 0 }, + { "ae_mulsu4o8x8", ICLASS_AE_MULSU4O8X8, + 0, + Opcode_ae_mulsu4o8x8_encode_fns, 0, 0 }, + { "ae_mulasu4o8x8", ICLASS_AE_MULASU4O8X8, + 0, + Opcode_ae_mulasu4o8x8_encode_fns, 0, 0 }, + { "ae_mulsu8q8x8cnv_l", ICLASS_AE_MULSU8Q8X8CNV_L, + 0, + Opcode_ae_mulsu8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulasu8q8x8cnv_l", ICLASS_AE_MULASU8Q8X8CNV_L, + 0, + Opcode_ae_mulasu8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulsu8q8x8cnv_h", ICLASS_AE_MULSU8Q8X8CNV_H, + 0, + Opcode_ae_mulsu8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulasu8q8x8cnv_h", ICLASS_AE_MULASU8Q8X8CNV_H, + 0, + Opcode_ae_mulasu8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulsu2x4q8x8cnv_h", ICLASS_AE_MULSU2X4Q8X8CNV_H, + 0, + Opcode_ae_mulsu2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulasu2x4q8x8cnv_h", ICLASS_AE_MULASU2X4Q8X8CNV_H, + 0, + Opcode_ae_mulasu2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulsu2x4q8x8cnv_l", ICLASS_AE_MULSU2X4Q8X8CNV_L, + 0, + Opcode_ae_mulsu2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulasu2x4q8x8cnv_l", ICLASS_AE_MULASU2X4Q8X8CNV_L, + 0, + Opcode_ae_mulasu2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulsu4o8x8cnv_h", ICLASS_AE_MULSU4O8X8CNV_H, + 0, + Opcode_ae_mulsu4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulasu4o8x8cnv_h", ICLASS_AE_MULASU4O8X8CNV_H, + 0, + Opcode_ae_mulasu4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulsu4o8x8cnv_l", ICLASS_AE_MULSU4O8X8CNV_L, + 0, + Opcode_ae_mulsu4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulasu4o8x8cnv_l", ICLASS_AE_MULASU4O8X8CNV_L, + 0, + Opcode_ae_mulasu4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluuzb8q8x8", ICLASS_AE_MULUUZB8Q8X8, + 0, + Opcode_ae_muluuzb8q8x8_encode_fns, 0, 0 }, + { "ae_mulauuzb8q8x8", ICLASS_AE_MULAUUZB8Q8X8, + 0, + Opcode_ae_mulauuzb8q8x8_encode_fns, 0, 0 }, + { "ae_muluuzb4o8x8", ICLASS_AE_MULUUZB4O8X8, + 0, + Opcode_ae_muluuzb4o8x8_encode_fns, 0, 0 }, + { "ae_mulauuzb4o8x8", ICLASS_AE_MULAUUZB4O8X8, + 0, + Opcode_ae_mulauuzb4o8x8_encode_fns, 0, 0 }, + { "ae_muluuzb8q8x8cnv_l", ICLASS_AE_MULUUZB8Q8X8CNV_L, + 0, + Opcode_ae_muluuzb8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauuzb8q8x8cnv_l", ICLASS_AE_MULAUUZB8Q8X8CNV_L, + 0, + Opcode_ae_mulauuzb8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluuzb8q8x8cnv_h", ICLASS_AE_MULUUZB8Q8X8CNV_H, + 0, + Opcode_ae_muluuzb8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauuzb8q8x8cnv_h", ICLASS_AE_MULAUUZB8Q8X8CNV_H, + 0, + Opcode_ae_mulauuzb8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluuzb2x4q8x8cnv_h", ICLASS_AE_MULUUZB2X4Q8X8CNV_H, + 0, + Opcode_ae_muluuzb2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauuzb2x4q8x8cnv_h", ICLASS_AE_MULAUUZB2X4Q8X8CNV_H, + 0, + Opcode_ae_mulauuzb2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluuzb2x4q8x8cnv_l", ICLASS_AE_MULUUZB2X4Q8X8CNV_L, + 0, + Opcode_ae_muluuzb2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauuzb2x4q8x8cnv_l", ICLASS_AE_MULAUUZB2X4Q8X8CNV_L, + 0, + Opcode_ae_mulauuzb2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluuzb4o8x8cnv_h", ICLASS_AE_MULUUZB4O8X8CNV_H, + 0, + Opcode_ae_muluuzb4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauuzb4o8x8cnv_h", ICLASS_AE_MULAUUZB4O8X8CNV_H, + 0, + Opcode_ae_mulauuzb4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluuzb4o8x8cnv_l", ICLASS_AE_MULUUZB4O8X8CNV_L, + 0, + Opcode_ae_muluuzb4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauuzb4o8x8cnv_l", ICLASS_AE_MULAUUZB4O8X8CNV_L, + 0, + Opcode_ae_mulauuzb4o8x8cnv_l_encode_fns, 0, 0 }, + { "cvtsf16.l", ICLASS_CVTSF16_L, + 0, + Opcode_cvtsf16_l_encode_fns, 0, 0 }, + { "cvtsf16.h", ICLASS_CVTSF16_H, + 0, + Opcode_cvtsf16_h_encode_fns, 0, 0 }, + { "cvtf16s.l", ICLASS_CVTF16S_L, + 0, + Opcode_cvtf16s_l_encode_fns, 0, 0 }, + { "cvtf16s.h", ICLASS_CVTF16S_H, + 0, + Opcode_cvtf16s_h_encode_fns, 0, 0 }, + { "ae_movfcrfsrv", ICLASS_AE_MOVFCRFSRV, + 0, + Opcode_ae_movfcrfsrv_encode_fns, 0, 0 }, + { "ae_movvfcrfsr", ICLASS_AE_MOVVFCRFSR, + 0, + Opcode_ae_movvfcrfsr_encode_fns, 0, 0 }, + { "movt.s", ICLASS_MOVT_S, + 0, + Opcode_movt_s_encode_fns, 0, 0 }, + { "movf.s", ICLASS_MOVF_S, + 0, + Opcode_movf_s_encode_fns, 0, 0 }, + { "moveqz.s", ICLASS_MOVEQZ_S, + 0, + Opcode_moveqz_s_encode_fns, 0, 0 }, + { "movnez.s", ICLASS_MOVNEZ_S, + 0, + Opcode_movnez_s_encode_fns, 0, 0 }, + { "movgez.s", ICLASS_MOVGEZ_S, + 0, + Opcode_movgez_s_encode_fns, 0, 0 }, + { "movltz.s", ICLASS_MOVLTZ_S, + 0, + Opcode_movltz_s_encode_fns, 0, 0 }, + { "rfr", ICLASS_RFR, + 0, + Opcode_rfr_encode_fns, 0, 0 }, + { "wfr", ICLASS_WFR, + 0, + Opcode_wfr_encode_fns, 0, 0 }, + { "mul.s", ICLASS_MUL_S, + 0, + Opcode_mul_s_encode_fns, 0, 0 }, + { "madd.s", ICLASS_MADD_S, + 0, + Opcode_madd_s_encode_fns, 0, 0 }, + { "msub.s", ICLASS_MSUB_S, + 0, + Opcode_msub_s_encode_fns, 0, 0 }, + { "msubn.s", ICLASS_MSUBN_S, + 0, + Opcode_msubn_s_encode_fns, 0, 0 }, + { "maddn.s", ICLASS_MADDN_S, + 0, + Opcode_maddn_s_encode_fns, 0, 0 }, + { "add.s", ICLASS_ADD_S, + 0, + Opcode_add_s_encode_fns, 0, 0 }, + { "sub.s", ICLASS_SUB_S, + 0, + Opcode_sub_s_encode_fns, 0, 0 }, + { "ole.s", ICLASS_OLE_S, + 0, + Opcode_ole_s_encode_fns, 0, 0 }, + { "olt.s", ICLASS_OLT_S, + 0, + Opcode_olt_s_encode_fns, 0, 0 }, + { "oeq.s", ICLASS_OEQ_S, + 0, + Opcode_oeq_s_encode_fns, 0, 0 }, + { "un.s", ICLASS_UN_S, + 0, + Opcode_un_s_encode_fns, 0, 0 }, + { "ule.s", ICLASS_ULE_S, + 0, + Opcode_ule_s_encode_fns, 0, 0 }, + { "ult.s", ICLASS_ULT_S, + 0, + Opcode_ult_s_encode_fns, 0, 0 }, + { "ueq.s", ICLASS_UEQ_S, + 0, + Opcode_ueq_s_encode_fns, 0, 0 }, + { "nexp01.s", ICLASS_NEXP01_S, + 0, + Opcode_nexp01_s_encode_fns, 0, 0 }, + { "mksadj.s", ICLASS_MKSADJ_S, + 0, + Opcode_mksadj_s_encode_fns, 0, 0 }, + { "mkdadj.s", ICLASS_MKDADJ_S, + 0, + Opcode_mkdadj_s_encode_fns, 0, 0 }, + { "div0.s", ICLASS_DIV0_S, + 0, + Opcode_div0_s_encode_fns, 0, 0 }, + { "sqrt0.s", ICLASS_SQRT0_S, + 0, + Opcode_sqrt0_s_encode_fns, 0, 0 }, + { "recip0.s", ICLASS_RECIP0_S, + 0, + Opcode_recip0_s_encode_fns, 0, 0 }, + { "rsqrt0.s", ICLASS_RSQRT0_S, + 0, + Opcode_rsqrt0_s_encode_fns, 0, 0 }, + { "divn.s", ICLASS_DIVN_S, + 0, + Opcode_divn_s_encode_fns, 0, 0 }, + { "addexp.s", ICLASS_ADDEXP_S, + 0, + Opcode_addexp_s_encode_fns, 0, 0 }, + { "addexpm.s", ICLASS_ADDEXPM_S, + 0, + Opcode_addexpm_s_encode_fns, 0, 0 }, + { "min.s", ICLASS_MIN_S, + 0, + Opcode_min_s_encode_fns, 0, 0 }, + { "max.s", ICLASS_MAX_S, + 0, + Opcode_max_s_encode_fns, 0, 0 }, + { "mulmux.s", ICLASS_MULMUX_S, + 0, + Opcode_mulmux_s_encode_fns, 0, 0 }, + { "maddmux.s", ICLASS_MADDMUX_S, + 0, + Opcode_maddmux_s_encode_fns, 0, 0 }, + { "trunc.s", ICLASS_TRUNC_S, + 0, + Opcode_trunc_s_encode_fns, 0, 0 }, + { "utrunc.s", ICLASS_UTRUNC_S, + 0, + Opcode_utrunc_s_encode_fns, 0, 0 }, + { "trunc.sx2", ICLASS_TRUNC_SX2, + 0, + Opcode_trunc_sx2_encode_fns, 0, 0 }, + { "utrunc.sx2", ICLASS_UTRUNC_SX2, + 0, + Opcode_utrunc_sx2_encode_fns, 0, 0 }, + { "ficeil.s", ICLASS_FICEIL_S, + 0, + Opcode_ficeil_s_encode_fns, 0, 0 }, + { "fifloor.s", ICLASS_FIFLOOR_S, + 0, + Opcode_fifloor_s_encode_fns, 0, 0 }, + { "firint.s", ICLASS_FIRINT_S, + 0, + Opcode_firint_s_encode_fns, 0, 0 }, + { "firound.s", ICLASS_FIROUND_S, + 0, + Opcode_firound_s_encode_fns, 0, 0 }, + { "fitrunc.s", ICLASS_FITRUNC_S, + 0, + Opcode_fitrunc_s_encode_fns, 0, 0 }, + { "float.s", ICLASS_FLOAT_S, + 0, + Opcode_float_s_encode_fns, 0, 0 }, + { "ufloat.s", ICLASS_UFLOAT_S, + 0, + Opcode_ufloat_s_encode_fns, 0, 0 }, + { "float.sx2", ICLASS_FLOAT_SX2, + 0, + Opcode_float_sx2_encode_fns, 0, 0 }, + { "ufloat.sx2", ICLASS_UFLOAT_SX2, + 0, + Opcode_ufloat_sx2_encode_fns, 0, 0 }, + { "abs.s", ICLASS_ABS_S, + 0, + Opcode_abs_s_encode_fns, 0, 0 }, + { "neg.s", ICLASS_NEG_S, + 0, + Opcode_neg_s_encode_fns, 0, 0 }, + { "conjc.s", ICLASS_CONJC_S, + 0, + Opcode_conjc_s_encode_fns, 0, 0 }, + { "muljc.s", ICLASS_MULJC_S, + 0, + Opcode_muljc_s_encode_fns, 0, 0 }, + { "const.s", ICLASS_CONST_S, + 0, + Opcode_const_s_encode_fns, 0, 0 }, + { "clsfy.s", ICLASS_CLSFY_S, + 0, + Opcode_clsfy_s_encode_fns, 0, 0 }, + { "minnum.s", ICLASS_MINNUM_S, + 0, + Opcode_minnum_s_encode_fns, 0, 0 }, + { "maxnum.s", ICLASS_MAXNUM_S, + 0, + Opcode_maxnum_s_encode_fns, 0, 0 }, + { "addandsub.s", ICLASS_ADDANDSUB_S, + 0, + Opcode_addandsub_s_encode_fns, 0, 0 }, + { "addandsubjc.s", ICLASS_ADDANDSUBJC_S, + 0, + Opcode_addandsubjc_s_encode_fns, 0, 0 }, + { "add_hl_lh.s", ICLASS_ADD_HL_LH_S, + 0, + Opcode_add_hl_lh_s_encode_fns, 0, 0 }, + { "madda.s", ICLASS_MADDA_S, + 0, + Opcode_madda_s_encode_fns, 0, 0 }, + { "frexp.s", ICLASS_FREXP_S, + 0, + Opcode_frexp_s_encode_fns, 0, 0 }, + { "floatexp.s", ICLASS_FLOATEXP_S, + 0, + Opcode_floatexp_s_encode_fns, 0, 0 }, + { "minnumabs.s", ICLASS_MINNUMABS_S, + 0, + Opcode_minnumabs_s_encode_fns, 0, 0 }, + { "maxnumabs.s", ICLASS_MAXNUMABS_S, + 0, + Opcode_maxnumabs_s_encode_fns, 0, 0 }, + { "mulq.s", ICLASS_MULQ_S, + 0, + Opcode_mulq_s_encode_fns, 0, 0 }, + { "maddq.s", ICLASS_MADDQ_S, + 0, + Opcode_maddq_s_encode_fns, 0, 0 }, + { "msubq.s", ICLASS_MSUBQ_S, + 0, + Opcode_msubq_s_encode_fns, 0, 0 }, + { "mulmuxq.s", ICLASS_MULMUXQ_S, + 0, + Opcode_mulmuxq_s_encode_fns, 0, 0 }, + { "maddmuxq.s", ICLASS_MADDMUXQ_S, + 0, + Opcode_maddmuxq_s_encode_fns, 0, 0 }, + { "bmaxnum.s", ICLASS_BMAXNUM_S, + 0, + Opcode_bmaxnum_s_encode_fns, 0, 0 }, + { "bminnum.s", ICLASS_BMINNUM_S, + 0, + Opcode_bminnum_s_encode_fns, 0, 0 }, + { "bmaxnumabs.s", ICLASS_BMAXNUMABS_S, + 0, + Opcode_bmaxnumabs_s_encode_fns, 0, 0 }, + { "bminnumabs.s", ICLASS_BMINNUMABS_S, + 0, + Opcode_bminnumabs_s_encode_fns, 0, 0 }, + { "abs.sx2x2", ICLASS_ABS_SX2X2, + 0, + Opcode_abs_sx2x2_encode_fns, 0, 0 }, + { "neg.sx2x2", ICLASS_NEG_SX2X2, + 0, + Opcode_neg_sx2x2_encode_fns, 0, 0 }, + { "conjc.sx2x2", ICLASS_CONJC_SX2X2, + 0, + Opcode_conjc_sx2x2_encode_fns, 0, 0 }, + { "muljc.sx2x2", ICLASS_MULJC_SX2X2, + 0, + Opcode_muljc_sx2x2_encode_fns, 0, 0 }, + { "const.sx2x2", ICLASS_CONST_SX2X2, + 0, + Opcode_const_sx2x2_encode_fns, 0, 0 }, + { "add.sx2x2", ICLASS_ADD_SX2X2, + 0, + Opcode_add_sx2x2_encode_fns, 0, 0 }, + { "sub.sx2x2", ICLASS_SUB_SX2X2, + 0, + Opcode_sub_sx2x2_encode_fns, 0, 0 }, + { "mul.sx2x2", ICLASS_MUL_SX2X2, + 0, + Opcode_mul_sx2x2_encode_fns, 0, 0 }, + { "madd.sx2x2", ICLASS_MADD_SX2X2, + 0, + Opcode_madd_sx2x2_encode_fns, 0, 0 }, + { "msub.sx2x2", ICLASS_MSUB_SX2X2, + 0, + Opcode_msub_sx2x2_encode_fns, 0, 0 }, + { "mulmux.sx2x2", ICLASS_MULMUX_SX2X2, + 0, + Opcode_mulmux_sx2x2_encode_fns, 0, 0 }, + { "maddmux.sx2x2", ICLASS_MADDMUX_SX2X2, + 0, + Opcode_maddmux_sx2x2_encode_fns, 0, 0 }, + { "abs.h", ICLASS_ABS_H, + 0, + Opcode_abs_h_encode_fns, 0, 0 }, + { "addexp.h", ICLASS_ADDEXP_H, + 0, + Opcode_addexp_h_encode_fns, 0, 0 }, + { "addexpm.h", ICLASS_ADDEXPM_H, + 0, + Opcode_addexpm_h_encode_fns, 0, 0 }, + { "clsfy.h", ICLASS_CLSFY_H, + 0, + Opcode_clsfy_h_encode_fns, 0, 0 }, + { "conjc.h", ICLASS_CONJC_H, + 0, + Opcode_conjc_h_encode_fns, 0, 0 }, + { "const.h", ICLASS_CONST_H, + 0, + Opcode_const_h_encode_fns, 0, 0 }, + { "min.h", ICLASS_MIN_H, + 0, + Opcode_min_h_encode_fns, 0, 0 }, + { "max.h", ICLASS_MAX_H, + 0, + Opcode_max_h_encode_fns, 0, 0 }, + { "minnum.h", ICLASS_MINNUM_H, + 0, + Opcode_minnum_h_encode_fns, 0, 0 }, + { "maxnum.h", ICLASS_MAXNUM_H, + 0, + Opcode_maxnum_h_encode_fns, 0, 0 }, + { "muljc.h", ICLASS_MULJC_H, + 0, + Opcode_muljc_h_encode_fns, 0, 0 }, + { "neg.h", ICLASS_NEG_H, + 0, + Opcode_neg_h_encode_fns, 0, 0 }, + { "oeq.h", ICLASS_OEQ_H, + 0, + Opcode_oeq_h_encode_fns, 0, 0 }, + { "ole.h", ICLASS_OLE_H, + 0, + Opcode_ole_h_encode_fns, 0, 0 }, + { "olt.h", ICLASS_OLT_H, + 0, + Opcode_olt_h_encode_fns, 0, 0 }, + { "ueq.h", ICLASS_UEQ_H, + 0, + Opcode_ueq_h_encode_fns, 0, 0 }, + { "ule.h", ICLASS_ULE_H, + 0, + Opcode_ule_h_encode_fns, 0, 0 }, + { "ult.h", ICLASS_ULT_H, + 0, + Opcode_ult_h_encode_fns, 0, 0 }, + { "un.h", ICLASS_UN_H, + 0, + Opcode_un_h_encode_fns, 0, 0 }, + { "div0.h", ICLASS_DIV0_H, + 0, + Opcode_div0_h_encode_fns, 0, 0 }, + { "ficeil.h", ICLASS_FICEIL_H, + 0, + Opcode_ficeil_h_encode_fns, 0, 0 }, + { "fifloor.h", ICLASS_FIFLOOR_H, + 0, + Opcode_fifloor_h_encode_fns, 0, 0 }, + { "firint.h", ICLASS_FIRINT_H, + 0, + Opcode_firint_h_encode_fns, 0, 0 }, + { "firound.h", ICLASS_FIROUND_H, + 0, + Opcode_firound_h_encode_fns, 0, 0 }, + { "fitrunc.h", ICLASS_FITRUNC_H, + 0, + Opcode_fitrunc_h_encode_fns, 0, 0 }, + { "mkdadj.h", ICLASS_MKDADJ_H, + 0, + Opcode_mkdadj_h_encode_fns, 0, 0 }, + { "mksadj.h", ICLASS_MKSADJ_H, + 0, + Opcode_mksadj_h_encode_fns, 0, 0 }, + { "nexp0.h", ICLASS_NEXP0_H, + 0, + Opcode_nexp0_h_encode_fns, 0, 0 }, + { "nexp01.h", ICLASS_NEXP01_H, + 0, + Opcode_nexp01_h_encode_fns, 0, 0 }, + { "recip0.h", ICLASS_RECIP0_H, + 0, + Opcode_recip0_h_encode_fns, 0, 0 }, + { "rsqrt0.h", ICLASS_RSQRT0_H, + 0, + Opcode_rsqrt0_h_encode_fns, 0, 0 }, + { "sqrt0.h", ICLASS_SQRT0_H, + 0, + Opcode_sqrt0_h_encode_fns, 0, 0 }, + { "float16.h", ICLASS_FLOAT16_H, + 0, + Opcode_float16_h_encode_fns, 0, 0 }, + { "ufloat16.h", ICLASS_UFLOAT16_H, + 0, + Opcode_ufloat16_h_encode_fns, 0, 0 }, + { "trunc16.h", ICLASS_TRUNC16_H, + 0, + Opcode_trunc16_h_encode_fns, 0, 0 }, + { "utrunc16.h", ICLASS_UTRUNC16_H, + 0, + Opcode_utrunc16_h_encode_fns, 0, 0 }, + { "float16.hx4", ICLASS_FLOAT16_HX4, + 0, + Opcode_float16_hx4_encode_fns, 0, 0 }, + { "ufloat16.hx4", ICLASS_UFLOAT16_HX4, + 0, + Opcode_ufloat16_hx4_encode_fns, 0, 0 }, + { "trunc16.hx4", ICLASS_TRUNC16_HX4, + 0, + Opcode_trunc16_hx4_encode_fns, 0, 0 }, + { "utrunc16.hx4", ICLASS_UTRUNC16_HX4, + 0, + Opcode_utrunc16_hx4_encode_fns, 0, 0 }, + { "add.h", ICLASS_ADD_H, + 0, + Opcode_add_h_encode_fns, 0, 0 }, + { "sub.h", ICLASS_SUB_H, + 0, + Opcode_sub_h_encode_fns, 0, 0 }, + { "mul.h", ICLASS_MUL_H, + 0, + Opcode_mul_h_encode_fns, 0, 0 }, + { "madd.h", ICLASS_MADD_H, + 0, + Opcode_madd_h_encode_fns, 0, 0 }, + { "msub.h", ICLASS_MSUB_H, + 0, + Opcode_msub_h_encode_fns, 0, 0 }, + { "maddn.h", ICLASS_MADDN_H, + 0, + Opcode_maddn_h_encode_fns, 0, 0 }, + { "msubn.h", ICLASS_MSUBN_H, + 0, + Opcode_msubn_h_encode_fns, 0, 0 }, + { "divn.h", ICLASS_DIVN_H, + 0, + Opcode_divn_h_encode_fns, 0, 0 }, + { "rminnum.h", ICLASS_RMINNUM_H, + 0, + Opcode_rminnum_h_encode_fns, 0, 0 }, + { "rmaxnum.h", ICLASS_RMAXNUM_H, + 0, + Opcode_rmaxnum_h_encode_fns, 0, 0 }, + { "abs.hx4x2", ICLASS_ABS_HX4X2, + 0, + Opcode_abs_hx4x2_encode_fns, 0, 0 }, + { "neg.hx4x2", ICLASS_NEG_HX4X2, + 0, + Opcode_neg_hx4x2_encode_fns, 0, 0 }, + { "conjc.hx4x2", ICLASS_CONJC_HX4X2, + 0, + Opcode_conjc_hx4x2_encode_fns, 0, 0 }, + { "const.hx4x2", ICLASS_CONST_HX4X2, + 0, + Opcode_const_hx4x2_encode_fns, 0, 0 }, + { "muljc.hx4x2", ICLASS_MULJC_HX4X2, + 0, + Opcode_muljc_hx4x2_encode_fns, 0, 0 }, + { "add.hx4x2", ICLASS_ADD_HX4X2, + 0, + Opcode_add_hx4x2_encode_fns, 0, 0 }, + { "sub.hx4x2", ICLASS_SUB_HX4X2, + 0, + Opcode_sub_hx4x2_encode_fns, 0, 0 }, + { "mul.hx4x2", ICLASS_MUL_HX4X2, + 0, + Opcode_mul_hx4x2_encode_fns, 0, 0 }, + { "madd.hx4x2", ICLASS_MADD_HX4X2, + 0, + Opcode_madd_hx4x2_encode_fns, 0, 0 }, + { "msub.hx4x2", ICLASS_MSUB_HX4X2, + 0, + Opcode_msub_hx4x2_encode_fns, 0, 0 }, + { "mulq.h", ICLASS_MULQ_H, + 0, + Opcode_mulq_h_encode_fns, 0, 0 }, + { "maddq.h", ICLASS_MADDQ_H, + 0, + Opcode_maddq_h_encode_fns, 0, 0 }, + { "mulcnvh.hx4x2", ICLASS_MULCNVH_HX4X2, + 0, + Opcode_mulcnvh_hx4x2_encode_fns, 0, 0 }, + { "mulacnvh.hx4x2", ICLASS_MULACNVH_HX4X2, + 0, + Opcode_mulacnvh_hx4x2_encode_fns, 0, 0 }, + { "mulcnvl.hx4x2", ICLASS_MULCNVL_HX4X2, + 0, + Opcode_mulcnvl_hx4x2_encode_fns, 0, 0 }, + { "mulacnvl.hx4x2", ICLASS_MULACNVL_HX4X2, + 0, + Opcode_mulacnvl_hx4x2_encode_fns, 0, 0 } +}; + +enum xtensa_opcode_id { + OPCODE_EXCW, + OPCODE_RFE, + OPCODE_RFDE, + OPCODE_SYSCALL, + OPCODE_CALL12, + OPCODE_CALL8, + OPCODE_CALL4, + OPCODE_CALLX12, + OPCODE_CALLX8, + OPCODE_CALLX4, + OPCODE_ENTRY, + OPCODE_MOVSP, + OPCODE_ROTW, + OPCODE_RETW, + OPCODE_RETW_N, + OPCODE_RFWO, + OPCODE_RFWU, + OPCODE_L32E, + OPCODE_S32E, + OPCODE_RSR_WINDOWBASE, + OPCODE_WSR_WINDOWBASE, + OPCODE_XSR_WINDOWBASE, + OPCODE_RSR_WINDOWSTART, + OPCODE_WSR_WINDOWSTART, + OPCODE_XSR_WINDOWSTART, + OPCODE_ADD_N, + OPCODE_ADDI_N, + OPCODE_BEQZ_N, + OPCODE_BNEZ_N, + OPCODE_ILL_N, + OPCODE_L32I_N, + OPCODE_MOV_N, + OPCODE_MOVI_N, + OPCODE_NOP_N, + OPCODE_RET_N, + OPCODE_S32I_N, + OPCODE_RUR_THREADPTR, + OPCODE_WUR_THREADPTR, + OPCODE_ADDI, + OPCODE_ADDMI, + OPCODE_ADD, + OPCODE_ADDX2, + OPCODE_ADDX4, + OPCODE_ADDX8, + OPCODE_SUB, + OPCODE_SUBX2, + OPCODE_SUBX4, + OPCODE_SUBX8, + OPCODE_AND, + OPCODE_OR, + OPCODE_XOR, + OPCODE_BEQI, + OPCODE_BGEI, + OPCODE_BLTI, + OPCODE_BNEI, + OPCODE_BBCI, + OPCODE_BBSI, + OPCODE_BGEUI, + OPCODE_BLTUI, + OPCODE_BALL, + OPCODE_BANY, + OPCODE_BBC, + OPCODE_BBS, + OPCODE_BEQ, + OPCODE_BGE, + OPCODE_BGEU, + OPCODE_BLT, + OPCODE_BLTU, + OPCODE_BNALL, + OPCODE_BNE, + OPCODE_BNONE, + OPCODE_BEQZ, + OPCODE_BGEZ, + OPCODE_BLTZ, + OPCODE_BNEZ, + OPCODE_CALL0, + OPCODE_CALLX0, + OPCODE_EXTUI, + OPCODE_ILL, + OPCODE_J, + OPCODE_JX, + OPCODE_L16UI, + OPCODE_L16SI, + OPCODE_L32I, + OPCODE_L32R, + OPCODE_L8UI, + OPCODE_LOOP, + OPCODE_LOOPGTZ, + OPCODE_LOOPNEZ, + OPCODE_MOVI, + OPCODE_MOVEQZ, + OPCODE_MOVGEZ, + OPCODE_MOVLTZ, + OPCODE_MOVNEZ, + OPCODE_ABS, + OPCODE_NEG, + OPCODE_NOP, + OPCODE_L32EX, + OPCODE_S32EX, + OPCODE_GETEX, + OPCODE_CLREX, + OPCODE_RET, + OPCODE_SIMCALL, + OPCODE_S16I, + OPCODE_S32I, + OPCODE_S32NB, + OPCODE_S8I, + OPCODE_SSA8B, + OPCODE_SSA8L, + OPCODE_SSL, + OPCODE_SSR, + OPCODE_SSAI, + OPCODE_SLL, + OPCODE_SRC, + OPCODE_SRA, + OPCODE_SRL, + OPCODE_SLLI, + OPCODE_SRAI, + OPCODE_SRLI, + OPCODE_MEMW, + OPCODE_EXTW, + OPCODE_ISYNC, + OPCODE_DSYNC, + OPCODE_ESYNC, + OPCODE_RSYNC, + OPCODE_RSIL, + OPCODE_RSR_LEND, + OPCODE_WSR_LEND, + OPCODE_XSR_LEND, + OPCODE_RSR_LCOUNT, + OPCODE_WSR_LCOUNT, + OPCODE_XSR_LCOUNT, + OPCODE_RSR_LBEG, + OPCODE_WSR_LBEG, + OPCODE_XSR_LBEG, + OPCODE_RSR_SAR, + OPCODE_WSR_SAR, + OPCODE_XSR_SAR, + OPCODE_RSR_MEMCTL, + OPCODE_WSR_MEMCTL, + OPCODE_XSR_MEMCTL, + OPCODE_RSR_CONFIGID0, + OPCODE_WSR_CONFIGID0, + OPCODE_RSR_CONFIGID1, + OPCODE_RSR_PS, + OPCODE_WSR_PS, + OPCODE_XSR_PS, + OPCODE_RSR_EPC1, + OPCODE_WSR_EPC1, + OPCODE_XSR_EPC1, + OPCODE_RSR_EXCSAVE1, + OPCODE_WSR_EXCSAVE1, + OPCODE_XSR_EXCSAVE1, + OPCODE_RSR_EPC2, + OPCODE_WSR_EPC2, + OPCODE_XSR_EPC2, + OPCODE_RSR_EXCSAVE2, + OPCODE_WSR_EXCSAVE2, + OPCODE_XSR_EXCSAVE2, + OPCODE_RSR_EPC3, + OPCODE_WSR_EPC3, + OPCODE_XSR_EPC3, + OPCODE_RSR_EXCSAVE3, + OPCODE_WSR_EXCSAVE3, + OPCODE_XSR_EXCSAVE3, + OPCODE_RSR_EPC4, + OPCODE_WSR_EPC4, + OPCODE_XSR_EPC4, + OPCODE_RSR_EXCSAVE4, + OPCODE_WSR_EXCSAVE4, + OPCODE_XSR_EXCSAVE4, + OPCODE_RSR_EPC5, + OPCODE_WSR_EPC5, + OPCODE_XSR_EPC5, + OPCODE_RSR_EXCSAVE5, + OPCODE_WSR_EXCSAVE5, + OPCODE_XSR_EXCSAVE5, + OPCODE_RSR_EPC6, + OPCODE_WSR_EPC6, + OPCODE_XSR_EPC6, + OPCODE_RSR_EXCSAVE6, + OPCODE_WSR_EXCSAVE6, + OPCODE_XSR_EXCSAVE6, + OPCODE_RSR_EPS2, + OPCODE_WSR_EPS2, + OPCODE_XSR_EPS2, + OPCODE_RSR_EPS3, + OPCODE_WSR_EPS3, + OPCODE_XSR_EPS3, + OPCODE_RSR_EPS4, + OPCODE_WSR_EPS4, + OPCODE_XSR_EPS4, + OPCODE_RSR_EPS5, + OPCODE_WSR_EPS5, + OPCODE_XSR_EPS5, + OPCODE_RSR_EPS6, + OPCODE_WSR_EPS6, + OPCODE_XSR_EPS6, + OPCODE_RSR_EXCVADDR, + OPCODE_WSR_EXCVADDR, + OPCODE_XSR_EXCVADDR, + OPCODE_RSR_DEPC, + OPCODE_WSR_DEPC, + OPCODE_XSR_DEPC, + OPCODE_RSR_EXCCAUSE, + OPCODE_WSR_EXCCAUSE, + OPCODE_XSR_EXCCAUSE, + OPCODE_RSR_MISC0, + OPCODE_WSR_MISC0, + OPCODE_XSR_MISC0, + OPCODE_RSR_MISC1, + OPCODE_WSR_MISC1, + OPCODE_XSR_MISC1, + OPCODE_RSR_MISC2, + OPCODE_WSR_MISC2, + OPCODE_XSR_MISC2, + OPCODE_RSR_MISC3, + OPCODE_WSR_MISC3, + OPCODE_XSR_MISC3, + OPCODE_RSR_PRID, + OPCODE_RSR_VECBASE, + OPCODE_WSR_VECBASE, + OPCODE_XSR_VECBASE, + OPCODE_RSR_MPUCFG, + OPCODE_WSR_MPUCFG, + OPCODE_SALT, + OPCODE_SALTU, + OPCODE_RSR_OPMODE, + OPCODE_WSR_OPMODE, + OPCODE_XSR_OPMODE, + OPCODE_MUL16S, + OPCODE_MUL16U, + OPCODE_MULL, + OPCODE_RFI, + OPCODE_WAITI, + OPCODE_RSR_INTERRUPT, + OPCODE_WSR_INTSET, + OPCODE_WSR_INTCLEAR, + OPCODE_RSR_INTENABLE, + OPCODE_WSR_INTENABLE, + OPCODE_XSR_INTENABLE, + OPCODE_BREAK, + OPCODE_BREAK_N, + OPCODE_RSR_DBREAKA0, + OPCODE_WSR_DBREAKA0, + OPCODE_XSR_DBREAKA0, + OPCODE_RSR_DBREAKC0, + OPCODE_WSR_DBREAKC0, + OPCODE_XSR_DBREAKC0, + OPCODE_RSR_DBREAKA1, + OPCODE_WSR_DBREAKA1, + OPCODE_XSR_DBREAKA1, + OPCODE_RSR_DBREAKC1, + OPCODE_WSR_DBREAKC1, + OPCODE_XSR_DBREAKC1, + OPCODE_RSR_IBREAKA0, + OPCODE_WSR_IBREAKA0, + OPCODE_XSR_IBREAKA0, + OPCODE_RSR_IBREAKA1, + OPCODE_WSR_IBREAKA1, + OPCODE_XSR_IBREAKA1, + OPCODE_RSR_IBREAKENABLE, + OPCODE_WSR_IBREAKENABLE, + OPCODE_XSR_IBREAKENABLE, + OPCODE_RSR_DEBUGCAUSE, + OPCODE_WSR_DEBUGCAUSE, + OPCODE_XSR_DEBUGCAUSE, + OPCODE_RSR_ICOUNT, + OPCODE_WSR_ICOUNT, + OPCODE_XSR_ICOUNT, + OPCODE_RSR_ICOUNTLEVEL, + OPCODE_WSR_ICOUNTLEVEL, + OPCODE_XSR_ICOUNTLEVEL, + OPCODE_RSR_DDR, + OPCODE_WSR_DDR, + OPCODE_XSR_DDR, + OPCODE_LDDR32_P, + OPCODE_SDDR32_P, + OPCODE_RFDO, + OPCODE_RFDD, + OPCODE_WSR_MMID, + OPCODE_ANDB, + OPCODE_ANDBC, + OPCODE_ORB, + OPCODE_ORBC, + OPCODE_XORB, + OPCODE_ALL4, + OPCODE_ANY4, + OPCODE_ALL8, + OPCODE_ANY8, + OPCODE_BF, + OPCODE_BT, + OPCODE_MOVF, + OPCODE_MOVT, + OPCODE_RSR_BR, + OPCODE_WSR_BR, + OPCODE_XSR_BR, + OPCODE_RSR_CCOUNT, + OPCODE_WSR_CCOUNT, + OPCODE_XSR_CCOUNT, + OPCODE_RSR_CCOMPARE0, + OPCODE_WSR_CCOMPARE0, + OPCODE_XSR_CCOMPARE0, + OPCODE_RSR_CCOMPARE1, + OPCODE_WSR_CCOMPARE1, + OPCODE_XSR_CCOMPARE1, + OPCODE_RSR_CCOMPARE2, + OPCODE_WSR_CCOMPARE2, + OPCODE_XSR_CCOMPARE2, + OPCODE_IHI, + OPCODE_IPF, + OPCODE_IHU, + OPCODE_IIU, + OPCODE_IPFL, + OPCODE_III, + OPCODE_LICT, + OPCODE_LICW, + OPCODE_SICT, + OPCODE_SICW, + OPCODE_DHWB, + OPCODE_DHWBI, + OPCODE_DIWBUI_P, + OPCODE_DIWB, + OPCODE_DIWBI, + OPCODE_DHI, + OPCODE_DII, + OPCODE_DPFR, + OPCODE_DPFRO, + OPCODE_DPFW, + OPCODE_DPFWO, + OPCODE_DPFM_B, + OPCODE_DPFM_BF, + OPCODE_DPFR_B, + OPCODE_DPFR_BF, + OPCODE_DPFW_B, + OPCODE_DPFW_BF, + OPCODE_PFNXT_F, + OPCODE_DHI_B, + OPCODE_DHWBI_B, + OPCODE_DHWB_B, + OPCODE_PFEND_A, + OPCODE_PFEND_O, + OPCODE_PFWAIT_A, + OPCODE_PFWAIT_R, + OPCODE_DHU, + OPCODE_DIU, + OPCODE_DPFL, + OPCODE_SDCT, + OPCODE_LDCT, + OPCODE_SDCW, + OPCODE_LDCW, + OPCODE_RSR_PREFCTL, + OPCODE_WSR_PREFCTL, + OPCODE_XSR_PREFCTL, + OPCODE_WSR_CACHEADRDIS, + OPCODE_RSR_CACHEADRDIS, + OPCODE_XSR_CACHEADRDIS, + OPCODE_RPTLB0, + OPCODE_PPTLB, + OPCODE_RPTLB1, + OPCODE_WPTLB, + OPCODE_RSR_MPUENB, + OPCODE_WSR_MPUENB, + OPCODE_XSR_MPUENB, + OPCODE_RSR_CPENABLE, + OPCODE_WSR_CPENABLE, + OPCODE_XSR_CPENABLE, + OPCODE_CLAMPS, + OPCODE_MAX, + OPCODE_MAXU, + OPCODE_MIN, + OPCODE_MINU, + OPCODE_NSA, + OPCODE_NSAU, + OPCODE_SEXT, + OPCODE_L32AI, + OPCODE_S32RI, + OPCODE_RSR_ATOMCTL, + OPCODE_WSR_ATOMCTL, + OPCODE_XSR_ATOMCTL, + OPCODE_QUOS, + OPCODE_QUOU, + OPCODE_REMS, + OPCODE_REMU, + OPCODE_RSR_ERACCESS, + OPCODE_WSR_ERACCESS, + OPCODE_XSR_ERACCESS, + OPCODE_RER, + OPCODE_WER, + OPCODE_BEQZ_W15, + OPCODE_BGEZ_W15, + OPCODE_BLTZ_W15, + OPCODE_BNEZ_W15, + OPCODE_BEQI_W15, + OPCODE_BGEI_W15, + OPCODE_BLTI_W15, + OPCODE_BNEI_W15, + OPCODE_BGEUI_W15, + OPCODE_BLTUI_W15, + OPCODE_BBCI_W15, + OPCODE_BBSI_W15, + OPCODE_BALL_W15, + OPCODE_BANY_W15, + OPCODE_BBC_W15, + OPCODE_BBS_W15, + OPCODE_BEQ_W15, + OPCODE_BGEU_W15, + OPCODE_BGE_W15, + OPCODE_BLTU_W15, + OPCODE_BLT_W15, + OPCODE_BNALL_W15, + OPCODE_BNE_W15, + OPCODE_BNONE_W15, + OPCODE_RUR_AE_OVF_SAR, + OPCODE_WUR_AE_OVF_SAR, + OPCODE_RUR_AE_BITHEAD, + OPCODE_WUR_AE_BITHEAD, + OPCODE_RUR_AE_TS_FTS_BU_BP, + OPCODE_WUR_AE_TS_FTS_BU_BP, + OPCODE_RUR_AE_CW_SD_NO, + OPCODE_WUR_AE_CW_SD_NO, + OPCODE_RUR_AE_CBEGIN0, + OPCODE_WUR_AE_CBEGIN0, + OPCODE_RUR_AE_CEND0, + OPCODE_WUR_AE_CEND0, + OPCODE_RUR_AE_CBEGIN1, + OPCODE_WUR_AE_CBEGIN1, + OPCODE_RUR_AE_CEND1, + OPCODE_WUR_AE_CEND1, + OPCODE_RUR_AE_CBEGIN2, + OPCODE_WUR_AE_CBEGIN2, + OPCODE_RUR_AE_CEND2, + OPCODE_WUR_AE_CEND2, + OPCODE_AE_SEXT16, + OPCODE_AE_ZEXT16, + OPCODE_AE_ZEXT8, + OPCODE_AE_CLAMPS16, + OPCODE_RUR_FCR, + OPCODE_WUR_FCR, + OPCODE_RUR_FSR, + OPCODE_WUR_FSR, + OPCODE_RUR_EXPSTATE, + OPCODE_WUR_EXPSTATE, + OPCODE_READ_IMPWIRE, + OPCODE_SETB_EXPSTATE, + OPCODE_CLRB_EXPSTATE, + OPCODE_WRMSK_EXPSTATE, + OPCODE_RUR_AE_OVERFLOW, + OPCODE_WUR_AE_OVERFLOW, + OPCODE_RUR_AE_SAR, + OPCODE_WUR_AE_SAR, + OPCODE_RUR_AE_BITPTR, + OPCODE_WUR_AE_BITPTR, + OPCODE_RUR_AE_BITSUSED, + OPCODE_WUR_AE_BITSUSED, + OPCODE_RUR_AE_TABLESIZE, + OPCODE_WUR_AE_TABLESIZE, + OPCODE_RUR_AE_FIRST_TS, + OPCODE_WUR_AE_FIRST_TS, + OPCODE_RUR_AE_NEXTOFFSET, + OPCODE_WUR_AE_NEXTOFFSET, + OPCODE_RUR_AE_SEARCHDONE, + OPCODE_WUR_AE_SEARCHDONE, + OPCODE_RUR_AE_CWRAP, + OPCODE_WUR_AE_CWRAP, + OPCODE_AE_L8X4F_I, + OPCODE_AE_L8X4F_IP, + OPCODE_AE_L8X4F_X, + OPCODE_AE_L8X4F_XP, + OPCODE_AE_L8X4S_I, + OPCODE_AE_L8X4S_IP, + OPCODE_AE_L8X4S_X, + OPCODE_AE_L8X4S_XP, + OPCODE_AE_L8X4U_I, + OPCODE_AE_L8X4U_IP, + OPCODE_AE_L8X4U_X, + OPCODE_AE_L8X4U_XP, + OPCODE_AE_L16M_XC, + OPCODE_AE_L16M_XC1, + OPCODE_AE_L16M_I, + OPCODE_AE_L16M_IU, + OPCODE_AE_L16M_X, + OPCODE_AE_L16M_XU, + OPCODE_AE_L16_XC, + OPCODE_AE_L16_XC1, + OPCODE_AE_L16_I, + OPCODE_AE_L16_IP, + OPCODE_AE_L16_X, + OPCODE_AE_L16_XP, + OPCODE_AE_L8_XC, + OPCODE_AE_L8_XC1, + OPCODE_AE_L8_I, + OPCODE_AE_L8_IP, + OPCODE_AE_L8_X, + OPCODE_AE_L8_XP, + OPCODE_AE_L32F24_XC, + OPCODE_AE_L32F24_XC1, + OPCODE_AE_L32F24_I, + OPCODE_AE_L32F24_IP, + OPCODE_AE_L32F24_X, + OPCODE_AE_L32F24_XP, + OPCODE_AE_L32_XC, + OPCODE_AE_L32_XC1, + OPCODE_AE_L32_I, + OPCODE_AE_L32_IP, + OPCODE_AE_L32_X, + OPCODE_AE_L32_XP, + OPCODE_AE_L32M_XC, + OPCODE_AE_L32M_I, + OPCODE_AE_L32M_IU, + OPCODE_AE_L32M_X, + OPCODE_AE_L32M_XU, + OPCODE_AE_L16X2M_XC, + OPCODE_AE_L16X2M_XC1, + OPCODE_AE_L16X2M_I, + OPCODE_AE_L16X2M_IU, + OPCODE_AE_L16X2M_X, + OPCODE_AE_L16X2M_XU, + OPCODE_AE_L32X2F24_XC, + OPCODE_AE_L32X2F24_XC1, + OPCODE_AE_L32X2F24_I, + OPCODE_AE_L32X2F24_IP, + OPCODE_AE_L32X2F24_RIP, + OPCODE_AE_L32X2F24_RI, + OPCODE_AE_L32X2F24_RIC, + OPCODE_AE_L32X2F24_RIC1, + OPCODE_AE_L32X2F24_X, + OPCODE_AE_L32X2F24_XP, + OPCODE_AE_L32X2_XC, + OPCODE_AE_L32X2_XC1, + OPCODE_AE_L32X2_I, + OPCODE_AE_L32X2_IP, + OPCODE_AE_L32X2_RIC, + OPCODE_AE_L32X2_RIC1, + OPCODE_AE_L32X2_X, + OPCODE_AE_L32X2_XP, + OPCODE_AE_L16X4_XC, + OPCODE_AE_L16X4_XC1, + OPCODE_AE_L16X4_I, + OPCODE_AE_L16X4_IP, + OPCODE_AE_L16X4_X, + OPCODE_AE_L16X4_XP, + OPCODE_AE_L8X8_XC, + OPCODE_AE_L8X8_XC1, + OPCODE_AE_L8X8_I, + OPCODE_AE_L8X8_IP, + OPCODE_AE_L8X8_X, + OPCODE_AE_L8X8_XP, + OPCODE_AE_L64_XC, + OPCODE_AE_L64_XC1, + OPCODE_AE_L64_I, + OPCODE_AE_L64_IP, + OPCODE_AE_L64_X, + OPCODE_AE_L64_XP, + OPCODE_AE_S16X2M_XC, + OPCODE_AE_S16X2M_XC1, + OPCODE_AE_S16X2M_I, + OPCODE_AE_S16X2M_IU, + OPCODE_AE_S16X2M_X, + OPCODE_AE_S16X2M_XU, + OPCODE_AE_S32X2F24_XC, + OPCODE_AE_S32X2F24_XC1, + OPCODE_AE_S32X2F24_I, + OPCODE_AE_S32X2F24_IP, + OPCODE_AE_S32X2F24_RIP, + OPCODE_AE_S32X2F24_RIC, + OPCODE_AE_S32X2F24_RIC1, + OPCODE_AE_S32X2F24_X, + OPCODE_AE_S32X2F24_XP, + OPCODE_AE_S32X2_XC, + OPCODE_AE_S32X2_XC1, + OPCODE_AE_S32X2_I, + OPCODE_AE_S32X2_IP, + OPCODE_AE_S32X2_RIC, + OPCODE_AE_S32X2_RIC1, + OPCODE_AE_S32X2_X, + OPCODE_AE_S32X2_XP, + OPCODE_AE_S32X2RNG_I, + OPCODE_AE_S32X2RNG_IP, + OPCODE_AE_S32X2RNG_X, + OPCODE_AE_S32X2RNG_XP, + OPCODE_AE_S16X4_XC, + OPCODE_AE_S16X4_XC1, + OPCODE_AE_S16X4_I, + OPCODE_AE_S16X4_IP, + OPCODE_AE_S16X4_X, + OPCODE_AE_S16X4_XP, + OPCODE_AE_S8X8_XC, + OPCODE_AE_S8X8_XC1, + OPCODE_AE_S8X8_I, + OPCODE_AE_S8X8_IP, + OPCODE_AE_S8X8_X, + OPCODE_AE_S8X8_XP, + OPCODE_AE_S16M_L_XC, + OPCODE_AE_S16M_L_XC1, + OPCODE_AE_S16M_L_I, + OPCODE_AE_S16M_L_IU, + OPCODE_AE_S16M_L_X, + OPCODE_AE_S16M_L_XU, + OPCODE_AE_S32F24_L_XC, + OPCODE_AE_S32F24_L_XC1, + OPCODE_AE_S32F24_L_I, + OPCODE_AE_S32F24_L_IP, + OPCODE_AE_S32F24_L_X, + OPCODE_AE_S32F24_L_XP, + OPCODE_AE_S32_L_XC, + OPCODE_AE_S32_L_XC1, + OPCODE_AE_S32_L_I, + OPCODE_AE_S32_L_IP, + OPCODE_AE_S32_L_X, + OPCODE_AE_S32_L_XP, + OPCODE_AE_S32_H_XC, + OPCODE_AE_S32_H_XC1, + OPCODE_AE_S32_H_I, + OPCODE_AE_S32_H_IP, + OPCODE_AE_S32_H_X, + OPCODE_AE_S32_H_XP, + OPCODE_AE_S16_0_XC, + OPCODE_AE_S16_0_XC1, + OPCODE_AE_S16_0_I, + OPCODE_AE_S16_0_IP, + OPCODE_AE_S16_0_X, + OPCODE_AE_S16_0_XP, + OPCODE_AE_S8_0_XC, + OPCODE_AE_S8_0_XC1, + OPCODE_AE_S8_0_I, + OPCODE_AE_S8_0_IP, + OPCODE_AE_S8_0_X, + OPCODE_AE_S8_0_XP, + OPCODE_AE_S64_XC, + OPCODE_AE_S64_XC1, + OPCODE_AE_S64_I, + OPCODE_AE_S64_IP, + OPCODE_AE_S64_X, + OPCODE_AE_S64_XP, + OPCODE_AE_S32M_XC, + OPCODE_AE_S32M_I, + OPCODE_AE_S32M_IU, + OPCODE_AE_S32M_X, + OPCODE_AE_S32M_XU, + OPCODE_AE_L32X2_XC2, + OPCODE_AE_L16X4_XC2, + OPCODE_AE_L8X8_XC2, + OPCODE_AE_L64_XC2, + OPCODE_AE_S32X2_XC2, + OPCODE_AE_S16X4_XC2, + OPCODE_AE_S8X8_XC2, + OPCODE_AE_S64_XC2, + OPCODE_AE_S16X4RNG_I, + OPCODE_AE_S16X4RNG_IP, + OPCODE_AE_S16X4RNG_X, + OPCODE_AE_S16X4RNG_XP, + OPCODE_AE_L32X2X2_XC, + OPCODE_AE_L32X2X2_XC1, + OPCODE_AE_L32X2X2_I, + OPCODE_AE_L32X2X2_IP, + OPCODE_AE_L32X2X2_X, + OPCODE_AE_L32X2X2_XP, + OPCODE_AE_L16X4X2_XC, + OPCODE_AE_L16X4X2_XC1, + OPCODE_AE_L16X4X2_I, + OPCODE_AE_L16X4X2_IP, + OPCODE_AE_L16X4X2_X, + OPCODE_AE_L16X4X2_XP, + OPCODE_AE_L8X8X2_XC, + OPCODE_AE_L8X8X2_XC1, + OPCODE_AE_L8X8X2_I, + OPCODE_AE_L8X8X2_IP, + OPCODE_AE_L8X8X2_X, + OPCODE_AE_L8X8X2_XP, + OPCODE_AE_L64X2_XC, + OPCODE_AE_L64X2_XC1, + OPCODE_AE_L64X2_I, + OPCODE_AE_L64X2_IP, + OPCODE_AE_L64X2_X, + OPCODE_AE_L64X2_XP, + OPCODE_AE_S32X2X2_XC, + OPCODE_AE_S32X2X2_XC1, + OPCODE_AE_S32X2X2_I, + OPCODE_AE_S32X2X2_IP, + OPCODE_AE_S32X2X2_X, + OPCODE_AE_S32X2X2_XP, + OPCODE_AE_S32X2X2RNG_I, + OPCODE_AE_S32X2X2RNG_IP, + OPCODE_AE_S32X2X2RNG_X, + OPCODE_AE_S32X2X2RNG_XP, + OPCODE_AE_S16X4X2_XC, + OPCODE_AE_S16X4X2_XC1, + OPCODE_AE_S16X4X2_I, + OPCODE_AE_S16X4X2_IP, + OPCODE_AE_S16X4X2_X, + OPCODE_AE_S16X4X2_XP, + OPCODE_AE_S8X8X2_XC, + OPCODE_AE_S8X8X2_XC1, + OPCODE_AE_S8X8X2_I, + OPCODE_AE_S8X8X2_IP, + OPCODE_AE_S8X8X2_X, + OPCODE_AE_S8X8X2_XP, + OPCODE_AE_S64X2_XC, + OPCODE_AE_S64X2_XC1, + OPCODE_AE_S64X2_I, + OPCODE_AE_S64X2_IP, + OPCODE_AE_S64X2_X, + OPCODE_AE_S64X2_XP, + OPCODE_AE_L32X2X2_XC2, + OPCODE_AE_L16X4X2_XC2, + OPCODE_AE_L8X8X2_XC2, + OPCODE_AE_L64X2_XC2, + OPCODE_AE_S32X2X2_XC2, + OPCODE_AE_S16X4X2_XC2, + OPCODE_AE_S8X8X2_XC2, + OPCODE_AE_S64X2_XC2, + OPCODE_AE_S16X4X2RNG_I, + OPCODE_AE_S16X4X2RNG_IP, + OPCODE_AE_S16X4X2RNG_X, + OPCODE_AE_S16X4X2RNG_XP, + OPCODE_AE_ZALIGN64, + OPCODE_AE_LALIGN64_I, + OPCODE_AE_SALIGN64_I, + OPCODE_AE_MOVALIGN, + OPCODE_AE_LA64_PP, + OPCODE_AE_LA24POS_PC, + OPCODE_AE_LA24NEG_PC, + OPCODE_AE_LA24POS_PC1, + OPCODE_AE_LA24NEG_PC1, + OPCODE_AE_LA24X2POS_PC, + OPCODE_AE_LA24X2NEG_PC, + OPCODE_AE_LA24X2POS_PC1, + OPCODE_AE_LA24X2NEG_PC1, + OPCODE_AE_LA32X2POS_PC, + OPCODE_AE_LA32X2NEG_PC, + OPCODE_AE_LA32X2POS_PC1, + OPCODE_AE_LA32X2NEG_PC1, + OPCODE_AE_LA32X2POS_PC2, + OPCODE_AE_LA16X4POS_PC, + OPCODE_AE_LA16X4NEG_PC, + OPCODE_AE_LA16X4POS_PC1, + OPCODE_AE_LA16X4NEG_PC1, + OPCODE_AE_LA16X4POS_PC2, + OPCODE_AE_LA8X8POS_PC, + OPCODE_AE_LA8X8NEG_PC, + OPCODE_AE_LA8X8POS_PC1, + OPCODE_AE_LA8X8NEG_PC1, + OPCODE_AE_LA8X8POS_PC2, + OPCODE_AE_LA32X2X2POS_PC, + OPCODE_AE_LA32X2X2POS_PC1, + OPCODE_AE_LA32X2X2POS_PC2, + OPCODE_AE_LA16X4X2POS_PC, + OPCODE_AE_LA16X4X2POS_PC1, + OPCODE_AE_LA16X4X2POS_PC2, + OPCODE_AE_LA8X8X2POS_PC, + OPCODE_AE_LA8X8X2POS_PC1, + OPCODE_AE_LA8X8X2POS_PC2, + OPCODE_AE_SA64POS_FP, + OPCODE_AE_SA64NEG_FP, + OPCODE_AE_LA32X2_IC, + OPCODE_AE_LA32X2_IC1, + OPCODE_AE_LA32X2_IC2, + OPCODE_AE_LA32X2_IP, + OPCODE_AE_LA32X2_RIP, + OPCODE_AE_LA32X2_RIC, + OPCODE_AE_LA32X2_RIC1, + OPCODE_AE_LA16X4_IC, + OPCODE_AE_LA16X4_IC1, + OPCODE_AE_LA16X4_IC2, + OPCODE_AE_LA16X4_IP, + OPCODE_AE_LA16X4_RIP, + OPCODE_AE_LA16X4_RIC, + OPCODE_AE_LA16X4_RIC1, + OPCODE_AE_LA8X8_IC, + OPCODE_AE_LA8X8_IC1, + OPCODE_AE_LA8X8_IC2, + OPCODE_AE_LA8X8_IP, + OPCODE_AE_LA8X8_RIP, + OPCODE_AE_LA8X8_RIC, + OPCODE_AE_LA8X8_RIC1, + OPCODE_AE_LA32X2F24_IC, + OPCODE_AE_LA32X2F24_IC1, + OPCODE_AE_LA32X2F24_IP, + OPCODE_AE_LA32X2F24_RIP, + OPCODE_AE_LA32X2F24_RIC, + OPCODE_AE_LA32X2F24_RIC1, + OPCODE_AE_LA24_IC, + OPCODE_AE_LA24_IC1, + OPCODE_AE_LA24_IP, + OPCODE_AE_LA24_RIP, + OPCODE_AE_LA24_RIC, + OPCODE_AE_LA24_RIC1, + OPCODE_AE_LA24X2_IC, + OPCODE_AE_LA24X2_IC1, + OPCODE_AE_LA24X2_IP, + OPCODE_AE_LA24X2_RIP, + OPCODE_AE_LA24X2_RIC, + OPCODE_AE_LA24X2_RIC1, + OPCODE_AE_SA32X2_IC, + OPCODE_AE_SA32X2_IC1, + OPCODE_AE_SA32X2_IC2, + OPCODE_AE_SA32X2_IP, + OPCODE_AE_SA32X2_RIP, + OPCODE_AE_SA32X2_RIC, + OPCODE_AE_SA32X2_RIC1, + OPCODE_AE_SA16X4_IC, + OPCODE_AE_SA16X4_IC1, + OPCODE_AE_SA16X4_IC2, + OPCODE_AE_SA16X4_IP, + OPCODE_AE_SA16X4_RIP, + OPCODE_AE_SA16X4_RIC, + OPCODE_AE_SA16X4_RIC1, + OPCODE_AE_SA8X8_IC, + OPCODE_AE_SA8X8_IC1, + OPCODE_AE_SA8X8_IC2, + OPCODE_AE_SA8X8_IP, + OPCODE_AE_SA8X8_RIP, + OPCODE_AE_SA8X8_RIC, + OPCODE_AE_SA8X8_RIC1, + OPCODE_AE_SA32X2F24_IC, + OPCODE_AE_SA32X2F24_IC1, + OPCODE_AE_SA32X2F24_IP, + OPCODE_AE_SA32X2F24_RIP, + OPCODE_AE_SA32X2F24_RIC, + OPCODE_AE_SA32X2F24_RIC1, + OPCODE_AE_SA24_L_IC, + OPCODE_AE_SA24_L_IC1, + OPCODE_AE_SA24_L_IP, + OPCODE_AE_SA24_L_RIP, + OPCODE_AE_SA24_L_RIC, + OPCODE_AE_SA24_L_RIC1, + OPCODE_AE_SA24X2_IC, + OPCODE_AE_SA24X2_IC1, + OPCODE_AE_SA24X2_IP, + OPCODE_AE_SA24X2_RIP, + OPCODE_AE_SA24X2_RIC, + OPCODE_AE_SA24X2_RIC1, + OPCODE_AE_ADDICIRC, + OPCODE_AE_ADDCIRC_XC2, + OPCODE_AE_ADDCIRC_XC1, + OPCODE_AE_ADDCIRC_XC, + OPCODE_AE_S32RA64S_I, + OPCODE_AE_S32RA64S_IP, + OPCODE_AE_S32RA64S_X, + OPCODE_AE_S32RA64S_XP, + OPCODE_AE_S32RA64S_XC, + OPCODE_AE_S32RA64S_XC1, + OPCODE_AE_S24RA64S_I, + OPCODE_AE_S24RA64S_IP, + OPCODE_AE_S24RA64S_X, + OPCODE_AE_S24RA64S_XP, + OPCODE_AE_S24RA64S_XC, + OPCODE_AE_S24RA64S_XC1, + OPCODE_AE_S32X2RA64S_IP, + OPCODE_AE_S24X2RA64S_IP, + OPCODE_AE_S16X4RA32S_IP, + OPCODE_AE_ADDBRBA32, + OPCODE_AE_S32X2_L_IP, + OPCODE_AE_BITSWAP, + OPCODE_AE_MUL32JS, + OPCODE_AE_ADDANDSUB32S, + OPCODE_AE_ADDANDSUB32JS, + OPCODE_AE_ADDANDSUBRNG32, + OPCODE_AE_ADDANDSUBRNG32_H, + OPCODE_AE_ADDANDSUBRNG32_L, + OPCODE_AE_ADDRNG32, + OPCODE_AE_SUBRNG32, + OPCODE_AE_RNG32X2, + OPCODE_AE_SEL16I, + OPCODE_AE_SEL16I_N, + OPCODE_AE_SHORTSWAP, + OPCODE_AE_MOVAB4, + OPCODE_AE_MOVAB2, + OPCODE_AE_MOVAB, + OPCODE_AE_MOVBA, + OPCODE_AE_MOVBA1X2, + OPCODE_AE_MOVBA4, + OPCODE_AE_MOVBA2, + OPCODE_AE_MOVB2, + OPCODE_AE_MOVB4, + OPCODE_AE_MOVT16X4, + OPCODE_AE_MOVF16X4, + OPCODE_AE_MOVT32X2, + OPCODE_AE_MOVF32X2, + OPCODE_AE_MOVSARA7X2, + OPCODE_AE_MOVSARD7, + OPCODE_AE_MOVASAR, + OPCODE_AE_MOVDA32X2, + OPCODE_AE_MOVDA32, + OPCODE_AE_MOVDA16X2, + OPCODE_AE_MOVDA16, + OPCODE_AE_MOVI, + OPCODE_AE_TRUNCP24A32X2, + OPCODE_AE_SAT16X4, + OPCODE_AE_CVT32X2F16_32, + OPCODE_AE_CVT32X2F16_10, + OPCODE_AE_SEXT32X2D16_32, + OPCODE_AE_SEXT32X2D16_10, + OPCODE_AE_CVTA32F24S_L, + OPCODE_AE_CVTA32F24S_H, + OPCODE_AE_CVTP24A16X2_LL, + OPCODE_AE_CVTP24A16X2_LH, + OPCODE_AE_CVTP24A16X2_HL, + OPCODE_AE_CVTP24A16X2_HH, + OPCODE_AE_TRUNCP24Q48X2, + OPCODE_AE_TRUNCA32X2F64S, + OPCODE_AE_TRUNCI32X2F64S, + OPCODE_AE_TRUNCA32F64S_L, + OPCODE_AE_TRUNCI32F64S_L, + OPCODE_AE_TRUNCP16, + OPCODE_AE_ROUND32X2F64SSYM, + OPCODE_AE_ROUND32X2F64SASYM, + OPCODE_AE_ROUND32X2F48SSYM, + OPCODE_AE_ROUND32X2F48SASYM, + OPCODE_AE_ROUND16X4F32SSYM, + OPCODE_AE_ROUND16X4F32SASYM, + OPCODE_AE_ROUND24X2F48SSYM, + OPCODE_AE_ROUND24X2F48SASYM, + OPCODE_AE_ROUNDSP16Q48X2SYM, + OPCODE_AE_ROUNDSP16Q48X2ASYM, + OPCODE_AE_MINABS32S, + OPCODE_AE_MAXABS32S, + OPCODE_AE_ROUNDSP16F24SYM, + OPCODE_AE_ROUNDSP16F24ASYM, + OPCODE_AE_MOV, + OPCODE_AE_MOVT64, + OPCODE_AE_MOVF64, + OPCODE_AE_CVTQ56A32S, + OPCODE_AE_CVT48A32, + OPCODE_AE_CVT64A32, + OPCODE_AE_CVTQ56P32S_L, + OPCODE_AE_CVTQ56P32S_H, + OPCODE_AE_CVT64F32_H, + OPCODE_AE_CVT48F32_L, + OPCODE_AE_CVT48F32_H, + OPCODE_AE_SAT48S, + OPCODE_AE_SATQ56S, + OPCODE_AE_SAT24S, + OPCODE_AE_TRUNCQ32, + OPCODE_AE_MINABS64S, + OPCODE_AE_MAXABS64S, + OPCODE_AE_ROUNDSQ32F48SYM, + OPCODE_AE_ROUNDSQ32F48ASYM, + OPCODE_AE_TRUNCA32Q48, + OPCODE_AE_MOVAD32_L, + OPCODE_AE_MOVAD32_H, + OPCODE_AE_MOVAD16_3, + OPCODE_AE_MOVAD16_2, + OPCODE_AE_MOVAD16_1, + OPCODE_AE_MOVAD16_0, + OPCODE_AE_SRA64_32, + OPCODE_AE_PKSR32, + OPCODE_AE_PKSR24, + OPCODE_AE_PKSRF32, + OPCODE_AE_PKSR16, + OPCODE_AE_TRUNCA16P24S_L, + OPCODE_AE_TRUNCA16P24S_H, + OPCODE_AE_ADD32, + OPCODE_AE_SUB32, + OPCODE_AE_ADDSUB32, + OPCODE_AE_SUBADD32, + OPCODE_AE_ADD16, + OPCODE_AE_SUB16, + OPCODE_AE_ADD32_HL_LH, + OPCODE_AE_ADDSUB32_HL_LH, + OPCODE_AE_NEG32, + OPCODE_AE_ABS32, + OPCODE_AE_NEG32_L, + OPCODE_AE_ADD24S, + OPCODE_AE_SUB24S, + OPCODE_AE_ADD32S, + OPCODE_AE_SUB32S, + OPCODE_AE_ADDSUB32S, + OPCODE_AE_SUBADD32S, + OPCODE_AE_ADD16S, + OPCODE_AE_SUB16S, + OPCODE_AE_ADD32S_HL_LH, + OPCODE_AE_ADDSUB32S_HL_LH, + OPCODE_AE_NEG24S, + OPCODE_AE_ABS24S, + OPCODE_AE_NEG32S, + OPCODE_AE_ABS32S, + OPCODE_AE_NEG16S, + OPCODE_AE_ABS16S, + OPCODE_AE_ABS16, + OPCODE_AE_MULC16JS_H, + OPCODE_AE_MULC16JS_L, + OPCODE_AE_MULAC16JS_H, + OPCODE_AE_MULAC16JS_L, + OPCODE_AE_LT16, + OPCODE_AE_LE16, + OPCODE_AE_EQ16, + OPCODE_AE_LT32, + OPCODE_AE_LE32, + OPCODE_AE_EQ32, + OPCODE_AE_MIN32, + OPCODE_AE_MAX32, + OPCODE_AE_MINMAX32, + OPCODE_AE_MINMAX16, + OPCODE_AE_MIN16, + OPCODE_AE_MAX16, + OPCODE_AE_ADD64, + OPCODE_AE_SUB64, + OPCODE_AE_NEG64, + OPCODE_AE_ABS64, + OPCODE_AE_ADDSQ56S, + OPCODE_AE_SUBSQ56S, + OPCODE_AE_ADD64S, + OPCODE_AE_SUB64S, + OPCODE_AE_NEGSQ56S, + OPCODE_AE_ABSSQ56S, + OPCODE_AE_NEG64S, + OPCODE_AE_ABS64S, + OPCODE_AE_AND, + OPCODE_AE_NAND, + OPCODE_AE_OR, + OPCODE_AE_XOR, + OPCODE_AE_SLAI24, + OPCODE_AE_SRLI24, + OPCODE_AE_SRAI24, + OPCODE_AE_SLAS24, + OPCODE_AE_SRLS24, + OPCODE_AE_SRAS24, + OPCODE_AE_SRAI16, + OPCODE_AE_SRAI16R, + OPCODE_AE_SLAI32, + OPCODE_AE_SRLI32, + OPCODE_AE_SRAI32, + OPCODE_AE_SRAI32R, + OPCODE_AE_SLAS32, + OPCODE_AE_SRLS32, + OPCODE_AE_SRAS32, + OPCODE_AE_SLAA32, + OPCODE_AE_SRLA32, + OPCODE_AE_SRAA32, + OPCODE_AE_SLAI16S, + OPCODE_AE_SLAA16S, + OPCODE_AE_SRAA16S, + OPCODE_AE_SRAA16RS, + OPCODE_AE_SLAI24S, + OPCODE_AE_SLAS24S, + OPCODE_AE_SLAI32S, + OPCODE_AE_SLAS32S, + OPCODE_AE_SLAA32S, + OPCODE_AE_SRAA32S, + OPCODE_AE_SRAA32RS, + OPCODE_AE_SLASQ56, + OPCODE_AE_SRLSQ56, + OPCODE_AE_SRASQ56, + OPCODE_AE_SLAAQ56, + OPCODE_AE_SRLAQ56, + OPCODE_AE_SRAAQ56, + OPCODE_AE_SLAI64, + OPCODE_AE_SRLI64, + OPCODE_AE_SRAI64, + OPCODE_AE_SLAS64, + OPCODE_AE_SRLS64, + OPCODE_AE_SRAS64, + OPCODE_AE_SLAA64, + OPCODE_AE_SRLA64, + OPCODE_AE_SRAA64, + OPCODE_AE_SLAISQ56S, + OPCODE_AE_SLASSQ56S, + OPCODE_AE_SLAASQ56S, + OPCODE_AE_SLAI64S, + OPCODE_AE_SLAS64S, + OPCODE_AE_SLAA64S, + OPCODE_AE_LT64, + OPCODE_AE_LE64, + OPCODE_AE_EQ64, + OPCODE_AE_MAX64, + OPCODE_AE_MIN64, + OPCODE_AE_NSA64, + OPCODE_AE_NSAZ16_0, + OPCODE_AE_NSAZ32_L, + OPCODE_AE_MULS32F48P16S_LL, + OPCODE_AE_MULF32S_LL, + OPCODE_AE_MUL32_LL, + OPCODE_AE_MULF32R_LL, + OPCODE_AE_MULF32RA_LL, + OPCODE_AE_MULS32F48P16S_LH, + OPCODE_AE_MULF32S_LH, + OPCODE_AE_MUL32_LH, + OPCODE_AE_MULF32R_LH, + OPCODE_AE_MULF32RA_LH, + OPCODE_AE_MULS32F48P16S_HH, + OPCODE_AE_MULF32S_HH, + OPCODE_AE_MUL32_HH, + OPCODE_AE_MULF32R_HH, + OPCODE_AE_MULF32RA_HH, + OPCODE_AE_MULAS32F48P16S_LL, + OPCODE_AE_MULAF32S_LL, + OPCODE_AE_MULA32_LL, + OPCODE_AE_MULAF32R_LL, + OPCODE_AE_MULAF32RA_LL, + OPCODE_AE_MULAS32F48P16S_LH, + OPCODE_AE_MULAF32S_LH, + OPCODE_AE_MULA32_LH, + OPCODE_AE_MULAF32R_LH, + OPCODE_AE_MULAF32RA_LH, + OPCODE_AE_MULAS32F48P16S_HH, + OPCODE_AE_MULAF32S_HH, + OPCODE_AE_MULA32_HH, + OPCODE_AE_MULAF32R_HH, + OPCODE_AE_MULAF32RA_HH, + OPCODE_AE_MULSS32F48P16S_LL, + OPCODE_AE_MULSF32S_LL, + OPCODE_AE_MULS32_LL, + OPCODE_AE_MULSF32R_LL, + OPCODE_AE_MULSF32RA_LL, + OPCODE_AE_MULSS32F48P16S_LH, + OPCODE_AE_MULSF32S_LH, + OPCODE_AE_MULS32_LH, + OPCODE_AE_MULSF32R_LH, + OPCODE_AE_MULSF32RA_LH, + OPCODE_AE_MULSS32F48P16S_HH, + OPCODE_AE_MULSF32S_HH, + OPCODE_AE_MULS32_HH, + OPCODE_AE_MULSF32R_HH, + OPCODE_AE_MULSF32RA_HH, + OPCODE_AE_MUL32U_LL, + OPCODE_AE_MULA32U_LL, + OPCODE_AE_MULS32U_LL, + OPCODE_AE_MULF16SS_33, + OPCODE_AE_MULF16SS_22, + OPCODE_AE_MULF16SS_32, + OPCODE_AE_MULF16SS_21, + OPCODE_AE_MULF16SS_31, + OPCODE_AE_MULF16SS_30, + OPCODE_AE_MULF16SS_10, + OPCODE_AE_MULF16SS_20, + OPCODE_AE_MULF16SS_11, + OPCODE_AE_MULF16SS_00, + OPCODE_AE_MULSF16SS_33, + OPCODE_AE_MULSF16SS_22, + OPCODE_AE_MULSF16SS_32, + OPCODE_AE_MULSF16SS_21, + OPCODE_AE_MULSF16SS_31, + OPCODE_AE_MULSF16SS_30, + OPCODE_AE_MULSF16SS_10, + OPCODE_AE_MULSF16SS_20, + OPCODE_AE_MULSF16SS_11, + OPCODE_AE_MULSF16SS_00, + OPCODE_AE_MULAF16SS_33, + OPCODE_AE_MULAF16SS_22, + OPCODE_AE_MULAF16SS_32, + OPCODE_AE_MULAF16SS_21, + OPCODE_AE_MULAF16SS_31, + OPCODE_AE_MULAF16SS_30, + OPCODE_AE_MULAF16SS_10, + OPCODE_AE_MULAF16SS_20, + OPCODE_AE_MULAF16SS_11, + OPCODE_AE_MULAF16SS_00, + OPCODE_AE_MUL16S_00, + OPCODE_AE_MULA16S_00, + OPCODE_AE_MULS16S_00, + OPCODE_AE_MULAAFD16SS_33_22, + OPCODE_AE_MULAAFD16SS_13_02, + OPCODE_AE_MULAAFD16SS_11_00, + OPCODE_AE_MULSSFD16SS_33_22, + OPCODE_AE_MULSSFD16SS_13_02, + OPCODE_AE_MULSSFD16SS_11_00, + OPCODE_AE_MULZAAFD16SS_33_22, + OPCODE_AE_MULZAAFD16SS_13_02, + OPCODE_AE_MULZAAFD16SS_11_00, + OPCODE_AE_MULZSSFD16SS_33_22, + OPCODE_AE_MULZSSFD16SS_13_02, + OPCODE_AE_MULZSSFD16SS_11_00, + OPCODE_AE_MULF48Q32SP16S_L, + OPCODE_AE_MULF48Q32SP16U_L, + OPCODE_AE_MULQ32SP16S_L, + OPCODE_AE_MULQ32SP16U_L, + OPCODE_AE_MULAF48Q32SP16S_L, + OPCODE_AE_MULAF48Q32SP16U_L, + OPCODE_AE_MULAQ32SP16S_L, + OPCODE_AE_MULAQ32SP16U_L, + OPCODE_AE_MULSF48Q32SP16S_L, + OPCODE_AE_MULSF48Q32SP16U_L, + OPCODE_AE_MULSQ32SP16S_L, + OPCODE_AE_MULSQ32SP16U_L, + OPCODE_AE_MULFP24X2RA, + OPCODE_AE_MULFP24X2R, + OPCODE_AE_MULAFP24X2RA, + OPCODE_AE_MULAFP24X2R, + OPCODE_AE_MULSFP24X2RA, + OPCODE_AE_MULSFP24X2R, + OPCODE_AE_MULZAAFD32S_HH_LL, + OPCODE_AE_MULZAAFD32RA_HH_LL, + OPCODE_AE_MULZAAD32_HH_LL, + OPCODE_AE_MULZAAFD32S_HL_LH, + OPCODE_AE_MULZAAFD32RA_HL_LH, + OPCODE_AE_MULZAAD32_HL_LH, + OPCODE_AE_MULZASFD32S_HH_LL, + OPCODE_AE_MULZASFD32RA_HH_LL, + OPCODE_AE_MULZASD32_HH_LL, + OPCODE_AE_MULZASFD32S_HL_LH, + OPCODE_AE_MULZASFD32RA_HL_LH, + OPCODE_AE_MULZASD32_HL_LH, + OPCODE_AE_MULZSAFD32S_HH_LL, + OPCODE_AE_MULZSAFD32RA_HH_LL, + OPCODE_AE_MULZSAD32_HH_LL, + OPCODE_AE_MULZSSFD32S_HH_LL, + OPCODE_AE_MULZSSFD32RA_HH_LL, + OPCODE_AE_MULZSSD32_HH_LL, + OPCODE_AE_MULZSSFD32S_HL_LH, + OPCODE_AE_MULZSSFD32RA_HL_LH, + OPCODE_AE_MULZSSD32_HL_LH, + OPCODE_AE_MULAAFD32S_HH_LL, + OPCODE_AE_MULAAFD32RA_HH_LL, + OPCODE_AE_MULAAD32_HH_LL, + OPCODE_AE_MULAAFD32S_HL_LH, + OPCODE_AE_MULAAFD32RA_HL_LH, + OPCODE_AE_MULAAD32_HL_LH, + OPCODE_AE_MULASFD32S_HH_LL, + OPCODE_AE_MULASFD32RA_HH_LL, + OPCODE_AE_MULASD32_HH_LL, + OPCODE_AE_MULASFD32S_HL_LH, + OPCODE_AE_MULASFD32RA_HL_LH, + OPCODE_AE_MULASD32_HL_LH, + OPCODE_AE_MULSAFD32S_HH_LL, + OPCODE_AE_MULSAFD32RA_HH_LL, + OPCODE_AE_MULSAD32_HH_LL, + OPCODE_AE_MULSSFD32S_HH_LL, + OPCODE_AE_MULSSFD32RA_HH_LL, + OPCODE_AE_MULSSD32_HH_LL, + OPCODE_AE_MULSSFD32S_HL_LH, + OPCODE_AE_MULSSFD32RA_HL_LH, + OPCODE_AE_MULSSD32_HL_LH, + OPCODE_AE_MULF32X16_L0, + OPCODE_AE_MUL32X16_L0, + OPCODE_AE_MULF32X16_L1, + OPCODE_AE_MUL32X16_L1, + OPCODE_AE_MULF32X16_L2, + OPCODE_AE_MUL32X16_L2, + OPCODE_AE_MULF32X16_L3, + OPCODE_AE_MUL32X16_L3, + OPCODE_AE_MULF32X16_H0, + OPCODE_AE_MUL32X16_H0, + OPCODE_AE_MULF32X16_H1, + OPCODE_AE_MUL32X16_H1, + OPCODE_AE_MULF32X16_H2, + OPCODE_AE_MUL32X16_H2, + OPCODE_AE_MULF32X16_H3, + OPCODE_AE_MUL32X16_H3, + OPCODE_AE_MULAF32X16_L0, + OPCODE_AE_MULA32X16_L0, + OPCODE_AE_MULAF32X16_L1, + OPCODE_AE_MULA32X16_L1, + OPCODE_AE_MULAF32X16_L2, + OPCODE_AE_MULA32X16_L2, + OPCODE_AE_MULAF32X16_L3, + OPCODE_AE_MULA32X16_L3, + OPCODE_AE_MULAF32X16_H0, + OPCODE_AE_MULA32X16_H0, + OPCODE_AE_MULAF32X16_H1, + OPCODE_AE_MULA32X16_H1, + OPCODE_AE_MULAF32X16_H2, + OPCODE_AE_MULA32X16_H2, + OPCODE_AE_MULAF32X16_H3, + OPCODE_AE_MULA32X16_H3, + OPCODE_AE_MULSF32X16_L0, + OPCODE_AE_MULS32X16_L0, + OPCODE_AE_MULSF32X16_L1, + OPCODE_AE_MULS32X16_L1, + OPCODE_AE_MULSF32X16_L2, + OPCODE_AE_MULS32X16_L2, + OPCODE_AE_MULSF32X16_L3, + OPCODE_AE_MULS32X16_L3, + OPCODE_AE_MULSF32X16_H0, + OPCODE_AE_MULS32X16_H0, + OPCODE_AE_MULSF32X16_H1, + OPCODE_AE_MULS32X16_H1, + OPCODE_AE_MULSF32X16_H2, + OPCODE_AE_MULS32X16_H2, + OPCODE_AE_MULSF32X16_H3, + OPCODE_AE_MULS32X16_H3, + OPCODE_AE_MULAAFD32X16_H3_L2, + OPCODE_AE_MULAAD32X16_H3_L2, + OPCODE_AE_MULAAFD32X16_H1_L0, + OPCODE_AE_MULAAD32X16_H1_L0, + OPCODE_AE_MULASFD32X16_H3_L2, + OPCODE_AE_MULASD32X16_H3_L2, + OPCODE_AE_MULASFD32X16_H1_L0, + OPCODE_AE_MULASD32X16_H1_L0, + OPCODE_AE_MULSAFD32X16_H3_L2, + OPCODE_AE_MULSAD32X16_H3_L2, + OPCODE_AE_MULSAFD32X16_H1_L0, + OPCODE_AE_MULSAD32X16_H1_L0, + OPCODE_AE_MULSSFD32X16_H3_L2, + OPCODE_AE_MULSSD32X16_H3_L2, + OPCODE_AE_MULSSFD32X16_H1_L0, + OPCODE_AE_MULSSD32X16_H1_L0, + OPCODE_AE_MULZAAFD32X16_H3_L2, + OPCODE_AE_MULZAAD32X16_H3_L2, + OPCODE_AE_MULZAAFD32X16_H1_L0, + OPCODE_AE_MULZAAD32X16_H1_L0, + OPCODE_AE_MULZASFD32X16_H3_L2, + OPCODE_AE_MULZASD32X16_H3_L2, + OPCODE_AE_MULZASFD32X16_H1_L0, + OPCODE_AE_MULZASD32X16_H1_L0, + OPCODE_AE_MULZSAFD32X16_H3_L2, + OPCODE_AE_MULZSAD32X16_H3_L2, + OPCODE_AE_MULZSAFD32X16_H1_L0, + OPCODE_AE_MULZSAD32X16_H1_L0, + OPCODE_AE_MULZSSFD32X16_H3_L2, + OPCODE_AE_MULZSSD32X16_H3_L2, + OPCODE_AE_MULZSSFD32X16_H1_L0, + OPCODE_AE_MULZSSD32X16_H1_L0, + OPCODE_AE_MULZAAFD32X16_H2_L3, + OPCODE_AE_MULZAAFD32X16_H0_L1, + OPCODE_AE_MULAAFD32X16_H2_L3, + OPCODE_AE_MULAAFD32X16_H0_L1, + OPCODE_AE_MULZAAD32X16_H2_L3, + OPCODE_AE_MULZAAD32X16_H0_L1, + OPCODE_AE_MULAAD32X16_H2_L3, + OPCODE_AE_MULAAD32X16_H0_L1, + OPCODE_AE_MULP32X16X2_H, + OPCODE_AE_MULFP32X16X2RS_H, + OPCODE_AE_MULFP32X16X2RAS_H, + OPCODE_AE_MULFP32X16X2S_H, + OPCODE_AE_MULP32X16X2_L, + OPCODE_AE_MULFP32X16X2RS_L, + OPCODE_AE_MULFP32X16X2RAS_L, + OPCODE_AE_MULFP32X16X2S_L, + OPCODE_AE_MULAP32X16X2_H, + OPCODE_AE_MULAFP32X16X2RS_H, + OPCODE_AE_MULAFP32X16X2RAS_H, + OPCODE_AE_MULAFP32X16X2S_H, + OPCODE_AE_MULAP32X16X2_L, + OPCODE_AE_MULAFP32X16X2RS_L, + OPCODE_AE_MULAFP32X16X2RAS_L, + OPCODE_AE_MULAFP32X16X2S_L, + OPCODE_AE_MULSP32X16X2_H, + OPCODE_AE_MULSFP32X16X2RS_H, + OPCODE_AE_MULSFP32X16X2RAS_H, + OPCODE_AE_MULSFP32X16X2S_H, + OPCODE_AE_MULSP32X16X2_L, + OPCODE_AE_MULSFP32X16X2RS_L, + OPCODE_AE_MULSFP32X16X2RAS_L, + OPCODE_AE_MULSFP32X16X2S_L, + OPCODE_AE_MULP32X2, + OPCODE_AE_MULFP32X2RS, + OPCODE_AE_MULFP32X2RAS, + OPCODE_AE_MULFP32X2TS, + OPCODE_AE_MULP32X2T, + OPCODE_AE_MULAP32X2, + OPCODE_AE_MULAFP32X2RS, + OPCODE_AE_MULAFP32X2RAS, + OPCODE_AE_MULAFP32X2TS, + OPCODE_AE_MULAP32X2T, + OPCODE_AE_MULSP32X2, + OPCODE_AE_MULSFP32X2RS, + OPCODE_AE_MULSFP32X2RAS, + OPCODE_AE_MULSFP32X2TS, + OPCODE_AE_MULSP32X2T, + OPCODE_AE_MULFP16X4S, + OPCODE_AE_MULFP16X4RAS, + OPCODE_AE_MULC32, + OPCODE_AE_MULFC24RA, + OPCODE_AE_MULFC32RAS, + OPCODE_AE_MULC32X16_L, + OPCODE_AE_MULFC32X16RAS_L, + OPCODE_AE_MULC32X16_H, + OPCODE_AE_MULFC32X16RAS_H, + OPCODE_AE_MULAC32, + OPCODE_AE_MULAFC24RA, + OPCODE_AE_MULAFC32RAS, + OPCODE_AE_MULAC32X16_L, + OPCODE_AE_MULAFC32X16RAS_L, + OPCODE_AE_MULAC32X16_H, + OPCODE_AE_MULAFC32X16RAS_H, + OPCODE_AE_MULF16X4SS, + OPCODE_AE_MULAF16X4SS, + OPCODE_AE_MULSF16X4SS, + OPCODE_AE_MUL16X4S, + OPCODE_AE_MULA16X4S, + OPCODE_AE_MULS16X4S, + OPCODE_AE_MUL16X4, + OPCODE_AE_MULA16X4, + OPCODE_AE_MULS16X4, + OPCODE_AE_MULFD32X2S_FIR_H, + OPCODE_AE_MULFD32X2RA_FIR_H, + OPCODE_AE_MULFD32X2S_FIR_L, + OPCODE_AE_MULFD32X2RA_FIR_L, + OPCODE_AE_MULFD32X16X2_FIR_HH, + OPCODE_AE_MULFD32X16X2_FIR_HL, + OPCODE_AE_MULFD32X16X2_FIR_LH, + OPCODE_AE_MULFD32X16X2_FIR_LL, + OPCODE_AE_MULAFD32X2S_FIR_H, + OPCODE_AE_MULAFD32X2RA_FIR_H, + OPCODE_AE_MULAFD32X2S_FIR_L, + OPCODE_AE_MULAFD32X2RA_FIR_L, + OPCODE_AE_MULAFD32X16X2_FIR_HH, + OPCODE_AE_MULAFD32X16X2_FIR_HL, + OPCODE_AE_MULAFD32X16X2_FIR_LH, + OPCODE_AE_MULAFD32X16X2_FIR_LL, + OPCODE_AE_MULC16S_H, + OPCODE_AE_MULC16S_L, + OPCODE_AE_MULAC16S_H, + OPCODE_AE_MULAC16S_L, + OPCODE_AE_MULFC16RAS, + OPCODE_AE_MULAFC16RAS, + OPCODE_AE_MUL16JS, + OPCODE_AE_ADDANDSUBRNG16RAS_S1, + OPCODE_AE_ADDANDSUBRNG16RAS_S2, + OPCODE_AE_CONJ16S, + OPCODE_AE_MULFQ16X2_FIR_3, + OPCODE_AE_MULFQ16X2_FIR_2, + OPCODE_AE_MULFQ16X2_FIR_1, + OPCODE_AE_MULFQ16X2_FIR_0, + OPCODE_AE_MULAFQ16X2_FIR_3, + OPCODE_AE_MULAFQ16X2_FIR_2, + OPCODE_AE_MULAFQ16X2_FIR_1, + OPCODE_AE_MULAFQ16X2_FIR_0, + OPCODE_AE_MULZAAAAFQ32X16, + OPCODE_AE_MULAAAAFQ32X16, + OPCODE_AE_MULZAAAAQ32X16, + OPCODE_AE_MULAAAAQ32X16, + OPCODE_AE_MUL16_00, + OPCODE_AE_MULA16_00, + OPCODE_AE_MULZAAAAQ16, + OPCODE_AE_MULAAAAQ16, + OPCODE_AE_DIV64D32_H, + OPCODE_AE_DIV64D32_L, + OPCODE_AE_SHA32, + OPCODE_AE_VLDL32T, + OPCODE_AE_VLDL16T, + OPCODE_AE_VLDL16C, + OPCODE_AE_VLDL16C_IP, + OPCODE_AE_VLDL16C_IC, + OPCODE_AE_VLDL16C_IC1, + OPCODE_AE_VLDSHT, + OPCODE_AE_LB, + OPCODE_AE_LBI, + OPCODE_AE_LBK, + OPCODE_AE_LBKI, + OPCODE_AE_LBS, + OPCODE_AE_LBSI, + OPCODE_AE_DB, + OPCODE_AE_DBI, + OPCODE_AE_DB_IC, + OPCODE_AE_DBI_IC, + OPCODE_AE_DB_IC1, + OPCODE_AE_DBI_IC1, + OPCODE_AE_DB_IP, + OPCODE_AE_DBI_IP, + OPCODE_AE_ARDECNORM16, + OPCODE_AE_LBKI_DBI_IC, + OPCODE_AE_LBKI_DBI_IP, + OPCODE_AE_LBKI_DBI, + OPCODE_AE_LBI_DBI_IC, + OPCODE_AE_LBI_DBI_IP, + OPCODE_AE_LBI_DBI, + OPCODE_AE_LBK_DB_IC, + OPCODE_AE_LBK_DB_IP, + OPCODE_AE_LBK_DB, + OPCODE_AE_LB_DB_IC, + OPCODE_AE_LB_DB_IP, + OPCODE_AE_LB_DB, + OPCODE_AE_VLEL32T, + OPCODE_AE_VLEL16T, + OPCODE_AE_SB, + OPCODE_AE_SBI, + OPCODE_AE_VLES16C, + OPCODE_AE_SBF, + OPCODE_AE_SB_IC, + OPCODE_AE_SBI_IC, + OPCODE_AE_VLES16C_IC, + OPCODE_AE_SBF_IC, + OPCODE_AE_SB_IC1, + OPCODE_AE_SBI_IC1, + OPCODE_AE_VLES16C_IC1, + OPCODE_AE_SBF_IC1, + OPCODE_AE_SB_IP, + OPCODE_AE_SBI_IP, + OPCODE_AE_VLES16C_IP, + OPCODE_AE_SBF_IP, + OPCODE_AE_SEXT32, + OPCODE_AE_MOVAE, + OPCODE_AE_MOVEA, + OPCODE_AE_MOVEEP, + OPCODE_AE_SEXT72, + OPCODE_AE_ADD72, + OPCODE_AE_SUB72, + OPCODE_AE_ADD72X64, + OPCODE_AE_SUB72X64, + OPCODE_AE_MUL32EP_HH, + OPCODE_AE_MULA32EP_HH, + OPCODE_AE_MULS32EP_HH, + OPCODE_AE_MULZAAD32EP_HH_LL, + OPCODE_AE_MULZSSD32EP_HH_LL, + OPCODE_AE_MULAAD32EP_HH_LL, + OPCODE_AE_MULSSD32EP_HH_LL, + OPCODE_AE_MULAAD32USEP_HL_LH, + OPCODE_AE_MULZAAD32USEP_HL_LH, + OPCODE_AE_MUL32USEP_LH, + OPCODE_AE_MULA32USEP_LH, + OPCODE_AE_MUL32USEP_LL, + OPCODE_AE_MULA32USEP_LL, + OPCODE_AE_SRAI72, + OPCODE_AE_SLAI72, + OPCODE_AE_SAT64S, + OPCODE_AE_L16SI_N, + OPCODE_AE_L16UI_N, + OPCODE_AE_S16I_N, + OPCODE_AE_LALIGN128_I, + OPCODE_AE_SALIGN128_I, + OPCODE_AE_LA128_PP, + OPCODE_AE_SA128POS_FP, + OPCODE_AE_LA8X4S_IP, + OPCODE_AE_LA8X4U_IP, + OPCODE_AE_LA8X8X2_IP, + OPCODE_AE_LA16X4X2_IP, + OPCODE_AE_LA32X2X2_IP, + OPCODE_AE_LA8X8X2_IC, + OPCODE_AE_LA16X4X2_IC, + OPCODE_AE_LA32X2X2_IC, + OPCODE_AE_LA8X8X2_IC1, + OPCODE_AE_LA16X4X2_IC1, + OPCODE_AE_LA32X2X2_IC1, + OPCODE_AE_LA8X8X2_IC2, + OPCODE_AE_LA16X4X2_IC2, + OPCODE_AE_LA32X2X2_IC2, + OPCODE_AE_SA8X8X2_IP, + OPCODE_AE_SA16X4X2_IP, + OPCODE_AE_SA32X2X2_IP, + OPCODE_AE_SA8X8X2_IC, + OPCODE_AE_SA16X4X2_IC, + OPCODE_AE_SA32X2X2_IC, + OPCODE_AE_SA8X8X2_IC1, + OPCODE_AE_SA16X4X2_IC1, + OPCODE_AE_SA32X2X2_IC1, + OPCODE_AE_SA8X8X2_IC2, + OPCODE_AE_SA16X4X2_IC2, + OPCODE_AE_SA32X2X2_IC2, + OPCODE_AE_ABS8, + OPCODE_AE_ABS8S, + OPCODE_AE_NEG8S, + OPCODE_AE_ADD8, + OPCODE_AE_SUB8, + OPCODE_AE_MAX8, + OPCODE_AE_MIN8, + OPCODE_AE_ADD8S, + OPCODE_AE_SUB8S, + OPCODE_AE_LE8, + OPCODE_AE_LT8, + OPCODE_AE_EQ8, + OPCODE_AE_SATU16X4, + OPCODE_AE_SAT32X2, + OPCODE_AE_SATU32X2, + OPCODE_AE_SAT8X8X16, + OPCODE_AE_SATU8X8X16, + OPCODE_AE_SAT8X4X32_L, + OPCODE_AE_SATU8X4X32_L, + OPCODE_AE_ROUND8X8F16SSYM, + OPCODE_AE_ROUND8X8F16SASYM, + OPCODE_AE_ROUND8X4F32SSYM_L, + OPCODE_AE_ROUND8X4F32SASYM_L, + OPCODE_AE_MOVDA8, + OPCODE_AE_MOVAD8, + OPCODE_AE_MOVDX2, + OPCODE_AE_ADDANDSUB32J, + OPCODE_AE_ADDW8, + OPCODE_AE_ADDW16, + OPCODE_AE_ADDW32, + OPCODE_AE_SUBW8, + OPCODE_AE_SUBW16, + OPCODE_AE_SUBW32, + OPCODE_AE_ACCW8, + OPCODE_AE_ACCW16, + OPCODE_AE_ACCW32, + OPCODE_AE_ADDW8U, + OPCODE_AE_SUBW8U, + OPCODE_AE_ACCW8U, + OPCODE_AE_MULFP32X2S_HH_LL, + OPCODE_AE_MULAFP32X2S_HH_LL, + OPCODE_AE_MULSFP32X2S_HH_LL, + OPCODE_AE_MULFP32X2S_HL_LH, + OPCODE_AE_MULAFP32X2S_HL_LH, + OPCODE_AE_MULSFP32X2S_HL_LH, + OPCODE_AE_MULZAAF2D32S_HH_LL, + OPCODE_AE_MULZASF2D32S_HH_LL, + OPCODE_AE_MULZSAF2D32S_HH_LL, + OPCODE_AE_MULZSSF2D32S_HH_LL, + OPCODE_AE_MULAAF2D32S_HH_LL, + OPCODE_AE_MULASF2D32S_HH_LL, + OPCODE_AE_MULSAF2D32S_HH_LL, + OPCODE_AE_MULSSF2D32S_HH_LL, + OPCODE_AE_MULZAAF2D32S_HL_LH, + OPCODE_AE_MULZASF2D32S_HL_LH, + OPCODE_AE_MULZSAF2D32S_HL_LH, + OPCODE_AE_MULZSSF2D32S_HL_LH, + OPCODE_AE_MULAAF2D32S_HL_LH, + OPCODE_AE_MULASF2D32S_HL_LH, + OPCODE_AE_MULSAF2D32S_HL_LH, + OPCODE_AE_MULSSF2D32S_HL_LH, + OPCODE_AE_MUL32S_HH, + OPCODE_AE_MULA32S_HH, + OPCODE_AE_MULS32S_HH, + OPCODE_AE_MUL32S_LL, + OPCODE_AE_MULA32S_LL, + OPCODE_AE_MULS32S_LL, + OPCODE_AE_MUL32S_HL, + OPCODE_AE_MULA32S_HL, + OPCODE_AE_MULS32S_HL, + OPCODE_AE_MUL32S_LH, + OPCODE_AE_MULA32S_LH, + OPCODE_AE_MULS32S_LH, + OPCODE_AE_MUL32X2S_HH_LL, + OPCODE_AE_MULA32X2S_HH_LL, + OPCODE_AE_MULS32X2S_HH_LL, + OPCODE_AE_MUL32X2S_HL_LH, + OPCODE_AE_MULA32X2S_HL_LH, + OPCODE_AE_MULS32X2S_HL_LH, + OPCODE_AE_MULZAAD32S_HH_LL, + OPCODE_AE_MULZASD32S_HH_LL, + OPCODE_AE_MULZSAD32S_HH_LL, + OPCODE_AE_MULZSSD32S_HH_LL, + OPCODE_AE_MULAAD32S_HH_LL, + OPCODE_AE_MULASD32S_HH_LL, + OPCODE_AE_MULSAD32S_HH_LL, + OPCODE_AE_MULSSD32S_HH_LL, + OPCODE_AE_MULZAAD32S_HL_LH, + OPCODE_AE_MULZASD32S_HL_LH, + OPCODE_AE_MULZSAD32S_HL_LH, + OPCODE_AE_MULZSSD32S_HL_LH, + OPCODE_AE_MULAAD32S_HL_LH, + OPCODE_AE_MULASD32S_HL_LH, + OPCODE_AE_MULSAD32S_HL_LH, + OPCODE_AE_MULSSD32S_HL_LH, + OPCODE_AE_MULF32X2RA_HH_LL, + OPCODE_AE_MULAF32X2RA_HH_LL, + OPCODE_AE_MULSF32X2RA_HH_LL, + OPCODE_AE_MULF32X2RA_HL_LH, + OPCODE_AE_MULAF32X2RA_HL_LH, + OPCODE_AE_MULSF32X2RA_HL_LH, + OPCODE_AE_MULZAAF2D32RA_HH_LL, + OPCODE_AE_MULZASF2D32RA_HH_LL, + OPCODE_AE_MULZSAF2D32RA_HH_LL, + OPCODE_AE_MULZSSF2D32RA_HH_LL, + OPCODE_AE_MULAAF2D32RA_HH_LL, + OPCODE_AE_MULASF2D32RA_HH_LL, + OPCODE_AE_MULSAF2D32RA_HH_LL, + OPCODE_AE_MULSSF2D32RA_HH_LL, + OPCODE_AE_MULZAAF2D32RA_HL_LH, + OPCODE_AE_MULZASF2D32RA_HL_LH, + OPCODE_AE_MULZSAF2D32RA_HL_LH, + OPCODE_AE_MULZSSF2D32RA_HL_LH, + OPCODE_AE_MULAAF2D32RA_HL_LH, + OPCODE_AE_MULASF2D32RA_HL_LH, + OPCODE_AE_MULSAF2D32RA_HL_LH, + OPCODE_AE_MULSSF2D32RA_HL_LH, + OPCODE_AE_MULF32X2R_HH_LL, + OPCODE_AE_MULAF32X2R_HH_LL, + OPCODE_AE_MULSF32X2R_HH_LL, + OPCODE_AE_MULF32X2R_HL_LH, + OPCODE_AE_MULAF32X2R_HL_LH, + OPCODE_AE_MULSF32X2R_HL_LH, + OPCODE_AE_MULFC32W, + OPCODE_AE_MULAFC32W, + OPCODE_AE_MULFCJ32W, + OPCODE_AE_MULAFCJ32W, + OPCODE_AE_MULFCJ32RAS, + OPCODE_AE_MULAFCJ32RAS, + OPCODE_AE_MULF2P32X4RS, + OPCODE_AE_MULAF2P32X4RS, + OPCODE_AE_MULSF2P32X4RS, + OPCODE_AE_MULF2P32X4RAS, + OPCODE_AE_MULAF2P32X4RAS, + OPCODE_AE_MULSF2P32X4RAS, + OPCODE_AE_MULP32X2S, + OPCODE_AE_MUL2P32X4S, + OPCODE_AE_MUL2P32X4, + OPCODE_AE_MULA2P32X4, + OPCODE_AE_MULS2P32X4, + OPCODE_AE_MUL2P32X4T, + OPCODE_AE_MULA2P32X4T, + OPCODE_AE_MULS2P32X4T, + OPCODE_AE_MULZAA32X2_HH_LL, + OPCODE_AE_MULZSS32X2_HH_LL, + OPCODE_AE_MULAA32X2_HH_LL, + OPCODE_AE_MULSS32X2_HH_LL, + OPCODE_AE_MULCJ32, + OPCODE_AE_MULACJ32, + OPCODE_AE_MULADDF32RS, + OPCODE_AE_MULADDF32RAS, + OPCODE_AE_MULSUBF32RS, + OPCODE_AE_MULSUBF32RAS, + OPCODE_AE_MULFC32RA, + OPCODE_AE_MULAFC32RA, + OPCODE_AE_MULCJ32W, + OPCODE_AE_MULACJ32W, + OPCODE_AE_MULC32W, + OPCODE_AE_MULAC32W, + OPCODE_AE_MULF2D32X2WS, + OPCODE_AE_MULZAAAA2Q16, + OPCODE_AE_MULAAAA2Q16, + OPCODE_AE_MULP16S_H, + OPCODE_AE_MULAP16S_H, + OPCODE_AE_MULSP16S_H, + OPCODE_AE_MULP16S_L, + OPCODE_AE_MULAP16S_L, + OPCODE_AE_MULSP16S_L, + OPCODE_AE_MULC16W_H, + OPCODE_AE_MULAC16W_H, + OPCODE_AE_MULC16W_L, + OPCODE_AE_MULAC16W_L, + OPCODE_AE_MUL2C16S, + OPCODE_AE_MULA2C16S, + OPCODE_AE_MULFC16S, + OPCODE_AE_MULAFC16S, + OPCODE_AE_MULFCJ16S, + OPCODE_AE_MULAFCJ16S, + OPCODE_AE_MULFCJ16RAS, + OPCODE_AE_MULAFCJ16RAS, + OPCODE_AE_MULC16S, + OPCODE_AE_MULAC16S, + OPCODE_AE_MULFP16X4RS, + OPCODE_AE_MULFD16X16X4RAS, + OPCODE_AE_MULP16X16X4S, + OPCODE_AE_MULAP16X16X4S, + OPCODE_AE_MULSP16X16X4S, + OPCODE_AE_MULZAA2D16SS_HH_LL, + OPCODE_AE_MULZAA2D16SS_HL_LH, + OPCODE_AE_MULZSS2D16SS_HH_LL, + OPCODE_AE_MULZSS2D16SS_HL_LH, + OPCODE_AE_MULAA2D16SS_HH_LL, + OPCODE_AE_MULAA2D16SS_HL_LH, + OPCODE_AE_MULSS2D16SS_HH_LL, + OPCODE_AE_MULSS2D16SS_HL_LH, + OPCODE_AE_MULZAAFD16SS_HH_LL, + OPCODE_AE_MULZAAFD16SS_HL_LH, + OPCODE_AE_MULZSSFD16SS_HH_LL, + OPCODE_AE_MULZSSFD16SS_HL_LH, + OPCODE_AE_MULAAFD16SS_HH_LL, + OPCODE_AE_MULAAFD16SS_HL_LH, + OPCODE_AE_MULSSFD16SS_HH_LL, + OPCODE_AE_MULSSFD16SS_HL_LH, + OPCODE_AE_MULFD16X16X4WS, + OPCODE_AE_MULZAAAA2Q16X8, + OPCODE_AE_MULAAAA2Q16X8, + OPCODE_AE_MULZAAAA2Q8, + OPCODE_AE_MULAAAA2Q8, + OPCODE_AE_MULC32X16W_H, + OPCODE_AE_MULAC32X16W_H, + OPCODE_AE_MULC32X16W_L, + OPCODE_AE_MULAC32X16W_L, + OPCODE_AE_MULPC32X16X2, + OPCODE_AE_MULAPC32X16X2, + OPCODE_AE_MULFP32X16_H, + OPCODE_AE_MULAFP32X16_H, + OPCODE_AE_MULSFP32X16_H, + OPCODE_AE_MULFP32X16_L, + OPCODE_AE_MULAFP32X16_L, + OPCODE_AE_MULSFP32X16_L, + OPCODE_AE_MULFC32X16W_H, + OPCODE_AE_MULAFC32X16W_H, + OPCODE_AE_MULFC32X16W_L, + OPCODE_AE_MULAFC32X16W_L, + OPCODE_AE_MULFCJ32X16W_H, + OPCODE_AE_MULAFCJ32X16W_H, + OPCODE_AE_MULFCJ32X16W_L, + OPCODE_AE_MULAFCJ32X16W_L, + OPCODE_AE_MULF2P32X16X4RAS, + OPCODE_AE_MULAF2P32X16X4RAS, + OPCODE_AE_MULSF2P32X16X4RAS, + OPCODE_AE_MULF2P32X16X4RS, + OPCODE_AE_MULAF2P32X16X4RS, + OPCODE_AE_MULSF2P32X16X4RS, + OPCODE_AE_MULF2P32X16X4S, + OPCODE_AE_MULAF2P32X16X4S, + OPCODE_AE_MULSF2P32X16X4S, + OPCODE_AE_MULFPC32X16X2RAS, + OPCODE_AE_MULAFPC32X16X2RAS, + OPCODE_AE_MULFPCJ32X16X2RAS, + OPCODE_AE_MULAFPCJ32X16X2RAS, + OPCODE_AE_MULZAAAA2Q32X16, + OPCODE_AE_MULAAAA2Q32X16, + OPCODE_AE_MUL2Q32X16_FIR_H, + OPCODE_AE_MULA2Q32X16_FIR_H, + OPCODE_AE_MUL2Q32X16_FIR_L, + OPCODE_AE_MULA2Q32X16_FIR_L, + OPCODE_AE_SRAI8, + OPCODE_AE_SRAI8R, + OPCODE_AE_SRLI8, + OPCODE_AE_SLAI8, + OPCODE_AE_SLAI8S, + OPCODE_AE_SLAA8, + OPCODE_AE_SRLA8, + OPCODE_AE_SLAA8S, + OPCODE_AE_SRAA8RS, + OPCODE_AE_SRAA8S, + OPCODE_AE_SRLI16, + OPCODE_AE_SLAI16, + OPCODE_AE_SLAA16, + OPCODE_AE_SRLA16, + OPCODE_AE_SRAI16SYM, + OPCODE_AE_SRAA16SYMS, + OPCODE_AE_SRAI32SYM, + OPCODE_AE_SRAA32SYMS, + OPCODE_AE_SRAV16RS, + OPCODE_AE_SRAV32RS, + OPCODE_AE_CVTI32X4F8_H, + OPCODE_AE_CVTI32X4F8_L, + OPCODE_AE_CVTI32X4F8S_H, + OPCODE_AE_CVTI32X4F8S_L, + OPCODE_AE_CVTA32X4F8_H, + OPCODE_AE_CVTA32X4F8_L, + OPCODE_AE_CVTA32X4F8S_H, + OPCODE_AE_CVTA32X4F8S_L, + OPCODE_AE_CVTI32X4F8U_H, + OPCODE_AE_CVTI32X4F8U_L, + OPCODE_AE_CVTI32X4F8US_H, + OPCODE_AE_CVTI32X4F8US_L, + OPCODE_AE_CVTA32X4F8U_H, + OPCODE_AE_CVTA32X4F8U_L, + OPCODE_AE_CVTA32X4F8US_H, + OPCODE_AE_CVTA32X4F8US_L, + OPCODE_AE_CVTI32X4F16, + OPCODE_AE_CVTI32X4F16S, + OPCODE_AE_CVTA32X4F16, + OPCODE_AE_CVTA32X4F16S, + OPCODE_AE_CVTI32X4F16U, + OPCODE_AE_CVTI32X4F16US, + OPCODE_AE_CVTA32X4F16U, + OPCODE_AE_CVTA32X4F16US, + OPCODE_AE_CVTI16X4X2F8, + OPCODE_AE_CVTI16X4X2F8S, + OPCODE_AE_CVTA16X4X2F8, + OPCODE_AE_CVTA16X4X2F8S, + OPCODE_AE_CVTI16X4X2F8U, + OPCODE_AE_CVTI16X4X2F8US, + OPCODE_AE_CVTA16X4X2F8U, + OPCODE_AE_CVTA16X4X2F8US, + OPCODE_AE_SEL8X8, + OPCODE_AE_SHFL8X8, + OPCODE_AE_SEL16X4, + OPCODE_AE_SHFL16X4, + OPCODE_AE_DSEL8X8, + OPCODE_AE_DSEL16X4, + OPCODE_AE_SEL8X8I, + OPCODE_AE_RMAX8X8, + OPCODE_AE_RMIN8X8, + OPCODE_AE_RMAX16X4, + OPCODE_AE_RMIN16X4, + OPCODE_AE_SORT16X4, + OPCODE_AE_RADD8X8_H, + OPCODE_AE_RADDA8X8_H, + OPCODE_AE_RADD8X8_L, + OPCODE_AE_RADDA8X8_L, + OPCODE_AE_RADD16X4, + OPCODE_AE_RADDA16X4, + OPCODE_AE_BMAX8X8_H, + OPCODE_AE_BMAX8X8_L, + OPCODE_AE_BMIN8X8_H, + OPCODE_AE_BMIN8X8_L, + OPCODE_AE_BMAX16X4, + OPCODE_AE_BMIN16X4, + OPCODE_AE_BMAX32X2, + OPCODE_AE_BMIN32X2, + OPCODE_AE_ADDINV16S, + OPCODE_AE_ADDINV32S, + OPCODE_AE_MOVT16X8, + OPCODE_AE_MOVT8X16_H, + OPCODE_AE_MOVT8X16_L, + OPCODE_AE_MOVBD1X4, + OPCODE_AE_MOVBD1X2, + OPCODE_AE_MOVNEG32S_T, + OPCODE_AE_MOVDEXT, + OPCODE_AE_MOVADEXT_H, + OPCODE_AE_MOVADEXT_L, + OPCODE_AE_NSA16X4, + OPCODE_AE_NSAZ32X4, + OPCODE_AE_NSA32X4, + OPCODE_AE_TRUNCI16X4F32S, + OPCODE_AE_TRUNCI16X4F64S, + OPCODE_AE_TRUNCA16X4F32S, + OPCODE_AE_TRUNCA16X4F64S, + OPCODE_AE_ADDC32, + OPCODE_AE_SUBC32, + OPCODE_AE_ADDC32U, + OPCODE_AE_SUBC32U, + OPCODE_AE_EXPADD16_H, + OPCODE_AE_EXPSUB16_H, + OPCODE_AE_EXPADD16_L, + OPCODE_AE_EXPSUB16_L, + OPCODE_AE_ADDCEXP32_H, + OPCODE_AE_ADDCEXP32_L, + OPCODE_AE_CALCRNG16, + OPCODE_AE_CALCRNG32, + OPCODE_AE_RNG32X4, + OPCODE_AE_LAV8X8X2_XP, + OPCODE_AE_LAV16X4X2_XP, + OPCODE_AE_SAV8X8X2_XP, + OPCODE_AE_SAV16X4X2_XP, + OPCODE_AE_MOVZBVCDR, + OPCODE_AE_MOVDRZBVC, + OPCODE_AE_LAVUNSQZ8X8_XP, + OPCODE_AE_LAVUNSQZ16X4_XP, + OPCODE_AE_MUL8Q8X8, + OPCODE_AE_MULA8Q8X8, + OPCODE_AE_MUL8Q4X16, + OPCODE_AE_MULA8Q4X16, + OPCODE_AE_MUL8Q8X16, + OPCODE_AE_MULA8Q8X16, + OPCODE_AE_MUL8QW8X16, + OPCODE_AE_MULA8QW8X16, + OPCODE_AE_MUL4O8X8, + OPCODE_AE_MULA4O8X8, + OPCODE_AE_MUL4O4X16, + OPCODE_AE_MULA4O4X16, + OPCODE_AE_MUL4O8X16, + OPCODE_AE_MULA4O8X16, + OPCODE_AE_MUL4QW8X16, + OPCODE_AE_MULA4QW8X16, + OPCODE_AE_MUL8Q8X8CNV_L, + OPCODE_AE_MUL8Q8X8CNV_H, + OPCODE_AE_MULA8Q8X8CNV_L, + OPCODE_AE_MULA8Q8X8CNV_H, + OPCODE_AE_MUL8Q8X16CNV, + OPCODE_AE_MULA8Q8X16CNV, + OPCODE_AE_MUL2X4Q8X8CNV_H, + OPCODE_AE_MULA2X4Q8X8CNV_H, + OPCODE_AE_MUL2X4Q8X8CNV_L, + OPCODE_AE_MULA2X4Q8X8CNV_L, + OPCODE_AE_MUL2X4Q8X16CNV, + OPCODE_AE_MULA2X4Q8X16CNV, + OPCODE_AE_MULQQ8X16CNV, + OPCODE_AE_MULAQQ8X16CNV, + OPCODE_AE_MUL4O8X8CNV_H, + OPCODE_AE_MULA4O8X8CNV_H, + OPCODE_AE_MUL4O8X8CNV_L, + OPCODE_AE_MULA4O8X8CNV_L, + OPCODE_AE_MUL4O8X16CNV_H, + OPCODE_AE_MULA4O8X16CNV_H, + OPCODE_AE_MUL4O8X16CNV_L, + OPCODE_AE_MULA4O8X16CNV_L, + OPCODE_AE_MUL8Q4X16CNV_H, + OPCODE_AE_MULA8Q4X16CNV_H, + OPCODE_AE_MUL8Q4X16CNV_L, + OPCODE_AE_MULA8Q4X16CNV_L, + OPCODE_AE_MUL2X4Q4X16CNV_H, + OPCODE_AE_MULA2X4Q4X16CNV_H, + OPCODE_AE_MUL2X4Q4X16CNV_L, + OPCODE_AE_MULA2X4Q4X16CNV_L, + OPCODE_AE_MULQQ4X16CNV_H, + OPCODE_AE_MULAQQ4X16CNV_H, + OPCODE_AE_MULQQ4X16CNV_L, + OPCODE_AE_MULAQQ4X16CNV_L, + OPCODE_AE_MUL4O4X16CNV_HH, + OPCODE_AE_MUL4O4X16CNV_HL, + OPCODE_AE_MUL4O4X16CNV_LH, + OPCODE_AE_MUL4O4X16CNV_LL, + OPCODE_AE_MULA4O4X16CNV_HH, + OPCODE_AE_MULA4O4X16CNV_HL, + OPCODE_AE_MULA4O4X16CNV_LH, + OPCODE_AE_MULA4O4X16CNV_LL, + OPCODE_AE_MULUU8Q8X8, + OPCODE_AE_MULAUU8Q8X8, + OPCODE_AE_MULUU4O8X8, + OPCODE_AE_MULAUU4O8X8, + OPCODE_AE_MULUU8Q8X8CNV_L, + OPCODE_AE_MULAUU8Q8X8CNV_L, + OPCODE_AE_MULUU8Q8X8CNV_H, + OPCODE_AE_MULAUU8Q8X8CNV_H, + OPCODE_AE_MULUU2X4Q8X8CNV_H, + OPCODE_AE_MULAUU2X4Q8X8CNV_H, + OPCODE_AE_MULUU2X4Q8X8CNV_L, + OPCODE_AE_MULAUU2X4Q8X8CNV_L, + OPCODE_AE_MULUU4O8X8CNV_H, + OPCODE_AE_MULAUU4O8X8CNV_H, + OPCODE_AE_MULUU4O8X8CNV_L, + OPCODE_AE_MULAUU4O8X8CNV_L, + OPCODE_AE_MULUS8Q8X8, + OPCODE_AE_MULAUS8Q8X8, + OPCODE_AE_MULUS8Q4X16, + OPCODE_AE_MULAUS8Q4X16, + OPCODE_AE_MULUS8Q8X16, + OPCODE_AE_MULAUS8Q8X16, + OPCODE_AE_MULUS8QW8X16, + OPCODE_AE_MULAUS8QW8X16, + OPCODE_AE_MULUS4O8X8, + OPCODE_AE_MULAUS4O8X8, + OPCODE_AE_MULUS4O4X16, + OPCODE_AE_MULAUS4O4X16, + OPCODE_AE_MULUS4O8X16, + OPCODE_AE_MULAUS4O8X16, + OPCODE_AE_MULUS4QW8X16, + OPCODE_AE_MULAUS4QW8X16, + OPCODE_AE_MULUS8Q8X8CNV_L, + OPCODE_AE_MULAUS8Q8X8CNV_L, + OPCODE_AE_MULUS8Q8X8CNV_H, + OPCODE_AE_MULAUS8Q8X8CNV_H, + OPCODE_AE_MULUS8Q8X16CNV, + OPCODE_AE_MULAUS8Q8X16CNV, + OPCODE_AE_MULUS2X4Q8X8CNV_H, + OPCODE_AE_MULAUS2X4Q8X8CNV_H, + OPCODE_AE_MULUS2X4Q8X8CNV_L, + OPCODE_AE_MULAUS2X4Q8X8CNV_L, + OPCODE_AE_MULUS2X4Q8X16CNV, + OPCODE_AE_MULAUS2X4Q8X16CNV, + OPCODE_AE_MULUSQQ8X16CNV, + OPCODE_AE_MULAUSQQ8X16CNV, + OPCODE_AE_MULUS4O8X8CNV_H, + OPCODE_AE_MULAUS4O8X8CNV_H, + OPCODE_AE_MULUS4O8X8CNV_L, + OPCODE_AE_MULAUS4O8X8CNV_L, + OPCODE_AE_MULUS4O8X16CNV_H, + OPCODE_AE_MULAUS4O8X16CNV_H, + OPCODE_AE_MULUS4O8X16CNV_L, + OPCODE_AE_MULAUS4O8X16CNV_L, + OPCODE_AE_MULUS8Q4X16CNV_H, + OPCODE_AE_MULAUS8Q4X16CNV_H, + OPCODE_AE_MULUS8Q4X16CNV_L, + OPCODE_AE_MULAUS8Q4X16CNV_L, + OPCODE_AE_MULUS2X4Q4X16CNV_H, + OPCODE_AE_MULAUS2X4Q4X16CNV_H, + OPCODE_AE_MULUS2X4Q4X16CNV_L, + OPCODE_AE_MULAUS2X4Q4X16CNV_L, + OPCODE_AE_MULUSQQ4X16CNV_H, + OPCODE_AE_MULAUSQQ4X16CNV_H, + OPCODE_AE_MULUSQQ4X16CNV_L, + OPCODE_AE_MULAUSQQ4X16CNV_L, + OPCODE_AE_MULUS4O4X16CNV_HH, + OPCODE_AE_MULUS4O4X16CNV_HL, + OPCODE_AE_MULUS4O4X16CNV_LH, + OPCODE_AE_MULUS4O4X16CNV_LL, + OPCODE_AE_MULAUS4O4X16CNV_HH, + OPCODE_AE_MULAUS4O4X16CNV_HL, + OPCODE_AE_MULAUS4O4X16CNV_LH, + OPCODE_AE_MULAUS4O4X16CNV_LL, + OPCODE_AE_MULSU8Q8X8, + OPCODE_AE_MULASU8Q8X8, + OPCODE_AE_MULSU4O8X8, + OPCODE_AE_MULASU4O8X8, + OPCODE_AE_MULSU8Q8X8CNV_L, + OPCODE_AE_MULASU8Q8X8CNV_L, + OPCODE_AE_MULSU8Q8X8CNV_H, + OPCODE_AE_MULASU8Q8X8CNV_H, + OPCODE_AE_MULSU2X4Q8X8CNV_H, + OPCODE_AE_MULASU2X4Q8X8CNV_H, + OPCODE_AE_MULSU2X4Q8X8CNV_L, + OPCODE_AE_MULASU2X4Q8X8CNV_L, + OPCODE_AE_MULSU4O8X8CNV_H, + OPCODE_AE_MULASU4O8X8CNV_H, + OPCODE_AE_MULSU4O8X8CNV_L, + OPCODE_AE_MULASU4O8X8CNV_L, + OPCODE_AE_MULUUZB8Q8X8, + OPCODE_AE_MULAUUZB8Q8X8, + OPCODE_AE_MULUUZB4O8X8, + OPCODE_AE_MULAUUZB4O8X8, + OPCODE_AE_MULUUZB8Q8X8CNV_L, + OPCODE_AE_MULAUUZB8Q8X8CNV_L, + OPCODE_AE_MULUUZB8Q8X8CNV_H, + OPCODE_AE_MULAUUZB8Q8X8CNV_H, + OPCODE_AE_MULUUZB2X4Q8X8CNV_H, + OPCODE_AE_MULAUUZB2X4Q8X8CNV_H, + OPCODE_AE_MULUUZB2X4Q8X8CNV_L, + OPCODE_AE_MULAUUZB2X4Q8X8CNV_L, + OPCODE_AE_MULUUZB4O8X8CNV_H, + OPCODE_AE_MULAUUZB4O8X8CNV_H, + OPCODE_AE_MULUUZB4O8X8CNV_L, + OPCODE_AE_MULAUUZB4O8X8CNV_L, + OPCODE_CVTSF16_L, + OPCODE_CVTSF16_H, + OPCODE_CVTF16S_L, + OPCODE_CVTF16S_H, + OPCODE_AE_MOVFCRFSRV, + OPCODE_AE_MOVVFCRFSR, + OPCODE_MOVT_S, + OPCODE_MOVF_S, + OPCODE_MOVEQZ_S, + OPCODE_MOVNEZ_S, + OPCODE_MOVGEZ_S, + OPCODE_MOVLTZ_S, + OPCODE_RFR, + OPCODE_WFR, + OPCODE_MUL_S, + OPCODE_MADD_S, + OPCODE_MSUB_S, + OPCODE_MSUBN_S, + OPCODE_MADDN_S, + OPCODE_ADD_S, + OPCODE_SUB_S, + OPCODE_OLE_S, + OPCODE_OLT_S, + OPCODE_OEQ_S, + OPCODE_UN_S, + OPCODE_ULE_S, + OPCODE_ULT_S, + OPCODE_UEQ_S, + OPCODE_NEXP01_S, + OPCODE_MKSADJ_S, + OPCODE_MKDADJ_S, + OPCODE_DIV0_S, + OPCODE_SQRT0_S, + OPCODE_RECIP0_S, + OPCODE_RSQRT0_S, + OPCODE_DIVN_S, + OPCODE_ADDEXP_S, + OPCODE_ADDEXPM_S, + OPCODE_MIN_S, + OPCODE_MAX_S, + OPCODE_MULMUX_S, + OPCODE_MADDMUX_S, + OPCODE_TRUNC_S, + OPCODE_UTRUNC_S, + OPCODE_TRUNC_SX2, + OPCODE_UTRUNC_SX2, + OPCODE_FICEIL_S, + OPCODE_FIFLOOR_S, + OPCODE_FIRINT_S, + OPCODE_FIROUND_S, + OPCODE_FITRUNC_S, + OPCODE_FLOAT_S, + OPCODE_UFLOAT_S, + OPCODE_FLOAT_SX2, + OPCODE_UFLOAT_SX2, + OPCODE_ABS_S, + OPCODE_NEG_S, + OPCODE_CONJC_S, + OPCODE_MULJC_S, + OPCODE_CONST_S, + OPCODE_CLSFY_S, + OPCODE_MINNUM_S, + OPCODE_MAXNUM_S, + OPCODE_ADDANDSUB_S, + OPCODE_ADDANDSUBJC_S, + OPCODE_ADD_HL_LH_S, + OPCODE_MADDA_S, + OPCODE_FREXP_S, + OPCODE_FLOATEXP_S, + OPCODE_MINNUMABS_S, + OPCODE_MAXNUMABS_S, + OPCODE_MULQ_S, + OPCODE_MADDQ_S, + OPCODE_MSUBQ_S, + OPCODE_MULMUXQ_S, + OPCODE_MADDMUXQ_S, + OPCODE_BMAXNUM_S, + OPCODE_BMINNUM_S, + OPCODE_BMAXNUMABS_S, + OPCODE_BMINNUMABS_S, + OPCODE_ABS_SX2X2, + OPCODE_NEG_SX2X2, + OPCODE_CONJC_SX2X2, + OPCODE_MULJC_SX2X2, + OPCODE_CONST_SX2X2, + OPCODE_ADD_SX2X2, + OPCODE_SUB_SX2X2, + OPCODE_MUL_SX2X2, + OPCODE_MADD_SX2X2, + OPCODE_MSUB_SX2X2, + OPCODE_MULMUX_SX2X2, + OPCODE_MADDMUX_SX2X2, + OPCODE_ABS_H, + OPCODE_ADDEXP_H, + OPCODE_ADDEXPM_H, + OPCODE_CLSFY_H, + OPCODE_CONJC_H, + OPCODE_CONST_H, + OPCODE_MIN_H, + OPCODE_MAX_H, + OPCODE_MINNUM_H, + OPCODE_MAXNUM_H, + OPCODE_MULJC_H, + OPCODE_NEG_H, + OPCODE_OEQ_H, + OPCODE_OLE_H, + OPCODE_OLT_H, + OPCODE_UEQ_H, + OPCODE_ULE_H, + OPCODE_ULT_H, + OPCODE_UN_H, + OPCODE_DIV0_H, + OPCODE_FICEIL_H, + OPCODE_FIFLOOR_H, + OPCODE_FIRINT_H, + OPCODE_FIROUND_H, + OPCODE_FITRUNC_H, + OPCODE_MKDADJ_H, + OPCODE_MKSADJ_H, + OPCODE_NEXP0_H, + OPCODE_NEXP01_H, + OPCODE_RECIP0_H, + OPCODE_RSQRT0_H, + OPCODE_SQRT0_H, + OPCODE_FLOAT16_H, + OPCODE_UFLOAT16_H, + OPCODE_TRUNC16_H, + OPCODE_UTRUNC16_H, + OPCODE_FLOAT16_HX4, + OPCODE_UFLOAT16_HX4, + OPCODE_TRUNC16_HX4, + OPCODE_UTRUNC16_HX4, + OPCODE_ADD_H, + OPCODE_SUB_H, + OPCODE_MUL_H, + OPCODE_MADD_H, + OPCODE_MSUB_H, + OPCODE_MADDN_H, + OPCODE_MSUBN_H, + OPCODE_DIVN_H, + OPCODE_RMINNUM_H, + OPCODE_RMAXNUM_H, + OPCODE_ABS_HX4X2, + OPCODE_NEG_HX4X2, + OPCODE_CONJC_HX4X2, + OPCODE_CONST_HX4X2, + OPCODE_MULJC_HX4X2, + OPCODE_ADD_HX4X2, + OPCODE_SUB_HX4X2, + OPCODE_MUL_HX4X2, + OPCODE_MADD_HX4X2, + OPCODE_MSUB_HX4X2, + OPCODE_MULQ_H, + OPCODE_MADDQ_H, + OPCODE_MULCNVH_HX4X2, + OPCODE_MULACNVH_HX4X2, + OPCODE_MULCNVL_HX4X2, + OPCODE_MULACNVL_HX4X2 +}; + + +/* Slot-specific opcode decode functions. */ + +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst_get (insn) == 0) + { + if (Field_op1_Slot_inst_get (insn) == 0) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_r_Slot_inst_get (insn) == 0) + { + if (Field_m_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return OPCODE_ILL; + if (Field_m_Slot_inst_get (insn) == 2) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_RET; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_RETW; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_JX; + } + if (Field_m_Slot_inst_get (insn) == 3) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALLX0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALLX4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALLX8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALLX12; + } + } + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_MOVSP; + if (Field_r_Slot_inst_get (insn) == 2) + { + if (Field_s_Slot_inst_get (insn) == 0) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_ISYNC; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RSYNC; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_ESYNC; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DSYNC; + if (Field_t_Slot_inst_get (insn) == 8) + return OPCODE_EXCW; + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_MEMW; + if (Field_t_Slot_inst_get (insn) == 13) + return OPCODE_EXTW; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_NOP; + } + } + if (Field_r_Slot_inst_get (insn) == 3) + { + if (Field_t_Slot_inst_get (insn) == 0) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_RFE; + if (Field_s_Slot_inst_get (insn) == 2) + return OPCODE_RFDE; + if (Field_s_Slot_inst_get (insn) == 4) + return OPCODE_RFWO; + if (Field_s_Slot_inst_get (insn) == 5) + return OPCODE_RFWU; + } + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFI; + if (Field_t_Slot_inst_get (insn) == 2 && + Field_s_Slot_inst_get (insn) == 1) + return OPCODE_CLREX; + } + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 4 && + Field_t_Slot_inst_get (insn) == 3) + return OPCODE_PFNXT_F; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 3) + return OPCODE_PFEND_A; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 3) + return OPCODE_PFEND_O; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 3) + return OPCODE_PFWAIT_A; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 3) + return OPCODE_PFWAIT_R; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BREAK; + if (Field_r_Slot_inst_get (insn) == 5) + { + if (Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SYSCALL; + if (Field_s_Slot_inst_get (insn) == 1) + return OPCODE_SIMCALL; + } + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RSIL; + if (Field_r_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_WAITI; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_LDDR32_P; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_SDDR32_P; + } + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_ANY4; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_ALL4; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_ANY8; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_ALL8; + } + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_AND; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_OR; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_XOR; + if (Field_op2_Slot_inst_get (insn) == 4) + { + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSR; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSL; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8L; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8B; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_thi3_Slot_inst_get (insn) == 0) + return OPCODE_SSAI; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RER; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_WER; + if (Field_r_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_ROTW; + if (Field_r_Slot_inst_get (insn) == 10 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_GETEX; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_NSA; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_NSAU; + } + if (Field_op2_Slot_inst_get (insn) == 5) + { + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_RPTLB0; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_PPTLB; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_WPTLB; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_RPTLB1; + } + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_NEG; + if (Field_s_Slot_inst_get (insn) == 1) + return OPCODE_ABS; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_ADD; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_ADDX2; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_ADDX4; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_ADDX8; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_SUB; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_SUBX2; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_SUBX4; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_SUBX8; + } + if (Field_op1_Slot_inst_get (insn) == 1) + { + if ((Field_op2_Slot_inst_get (insn) == 0 || + Field_op2_Slot_inst_get (insn) == 1)) + return OPCODE_SLLI; + if ((Field_op2_Slot_inst_get (insn) == 2 || + Field_op2_Slot_inst_get (insn) == 3)) + return OPCODE_SRAI; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_SRLI; + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_XSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_XSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_XSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_XSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_XSR_BR; + if (Field_sr_Slot_inst_get (insn) == 40) + return OPCODE_XSR_PREFCTL; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_XSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_XSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_XSR_MPUENB; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_XSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_XSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_XSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 98) + return OPCODE_XSR_CACHEADRDIS; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_XSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_XSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 119) + return OPCODE_XSR_OPMODE; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_XSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_XSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_XSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_XSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_XSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_XSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_XSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_XSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_XSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_XSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_XSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_XSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_XSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_XSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_XSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_XSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_XSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_XSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_XSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_XSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_XSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_XSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_XSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_XSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_XSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_XSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_XSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_XSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_XSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_XSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_XSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_XSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_XSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_XSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_XSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_XSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_XSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_XSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_XSR_MISC1; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_XSR_MISC2; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_XSR_MISC3; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_SRC; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRL; + if (Field_op2_Slot_inst_get (insn) == 10 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SLL; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRA; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MUL16U; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MUL16S; + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_LICT; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_SICT; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_LICW; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_SICW; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_L32EX; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_S32EX; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LDCT; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_SDCT; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_LDCW; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_SDCW; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_RFDO; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFDD; + } + } + if (Field_op1_Slot_inst_get (insn) == 2) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_ANDB; + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_ANDBC; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_ORB; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_ORBC; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_XORB; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_SALTU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_SALT; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MULL; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_QUOU; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_QUOS; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_REMU; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_REMS; + } + if (Field_op1_Slot_inst_get (insn) == 3) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_RSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_RSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_RSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_RSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_RSR_BR; + if (Field_sr_Slot_inst_get (insn) == 40) + return OPCODE_RSR_PREFCTL; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_RSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_RSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_RSR_MPUENB; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_RSR_MPUCFG; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_RSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_RSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_RSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 98) + return OPCODE_RSR_CACHEADRDIS; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_RSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_RSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 119) + return OPCODE_RSR_OPMODE; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_RSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_RSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_RSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_RSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_RSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_RSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_RSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_RSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_RSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_RSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_RSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_RSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_RSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_RSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_RSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_RSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_RSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_RSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_RSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 208) + return OPCODE_RSR_CONFIGID1; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_RSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_RSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_RSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_RSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_RSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_RSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_RSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_RSR_INTERRUPT; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_RSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_RSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_RSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_RSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_RSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_RSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 235) + return OPCODE_RSR_PRID; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_RSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_RSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_RSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_RSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_RSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_RSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_RSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_RSR_MISC1; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_RSR_MISC2; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_RSR_MISC3; + } + if (Field_op2_Slot_inst_get (insn) == 1) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_WSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_WSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_WSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_WSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_WSR_BR; + if (Field_sr_Slot_inst_get (insn) == 40) + return OPCODE_WSR_PREFCTL; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_WSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_WSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 89) + return OPCODE_WSR_MMID; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_WSR_MPUENB; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_WSR_MPUCFG; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_WSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_WSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_WSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 98) + return OPCODE_WSR_CACHEADRDIS; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_WSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_WSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 119) + return OPCODE_WSR_OPMODE; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_WSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_WSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_WSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_WSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_WSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_WSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_WSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_WSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_WSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_WSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_WSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_WSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_WSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_WSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_WSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_WSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_WSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_WSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_WSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_WSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_WSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_WSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_WSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_WSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_WSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_WSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_WSR_INTSET; + if (Field_sr_Slot_inst_get (insn) == 227) + return OPCODE_WSR_INTCLEAR; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_WSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_WSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_WSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_WSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_WSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_WSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_WSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_WSR_MISC1; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_WSR_MISC2; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_WSR_MISC3; + } + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_SEXT; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_CLAMPS; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_MIN; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_MAX; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_MINU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_MAXU; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MOVEQZ; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_MOVNEZ; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MOVLTZ; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MOVGEZ; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MOVF; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MOVT; + if (Field_op2_Slot_inst_get (insn) == 14) + { + if (Field_st_Slot_inst_get (insn) == 230) + return OPCODE_RUR_EXPSTATE; + if (Field_st_Slot_inst_get (insn) == 231) + return OPCODE_RUR_THREADPTR; + if (Field_st_Slot_inst_get (insn) == 232) + return OPCODE_RUR_FCR; + if (Field_st_Slot_inst_get (insn) == 233) + return OPCODE_RUR_FSR; + if (Field_st_Slot_inst_get (insn) == 240) + return OPCODE_RUR_AE_OVF_SAR; + if (Field_st_Slot_inst_get (insn) == 241) + return OPCODE_RUR_AE_BITHEAD; + if (Field_st_Slot_inst_get (insn) == 242) + return OPCODE_RUR_AE_TS_FTS_BU_BP; + if (Field_st_Slot_inst_get (insn) == 243) + return OPCODE_RUR_AE_CW_SD_NO; + if (Field_st_Slot_inst_get (insn) == 246) + return OPCODE_RUR_AE_CBEGIN0; + if (Field_st_Slot_inst_get (insn) == 247) + return OPCODE_RUR_AE_CEND0; + if (Field_st_Slot_inst_get (insn) == 248) + return OPCODE_RUR_AE_CBEGIN1; + if (Field_st_Slot_inst_get (insn) == 249) + return OPCODE_RUR_AE_CEND1; + if (Field_st_Slot_inst_get (insn) == 250) + return OPCODE_RUR_AE_CBEGIN2; + if (Field_st_Slot_inst_get (insn) == 251) + return OPCODE_RUR_AE_CEND2; + } + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WUR_EXPSTATE; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WUR_THREADPTR; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WUR_FCR; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WUR_FSR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WUR_AE_OVF_SAR; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WUR_AE_BITHEAD; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_WUR_AE_TS_FTS_BU_BP; + if (Field_sr_Slot_inst_get (insn) == 243) + return OPCODE_WUR_AE_CW_SD_NO; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_WUR_AE_CBEGIN0; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_WUR_AE_CEND0; + if (Field_sr_Slot_inst_get (insn) == 248) + return OPCODE_WUR_AE_CBEGIN1; + if (Field_sr_Slot_inst_get (insn) == 249) + return OPCODE_WUR_AE_CEND1; + if (Field_sr_Slot_inst_get (insn) == 250) + return OPCODE_WUR_AE_CBEGIN2; + if (Field_sr_Slot_inst_get (insn) == 251) + return OPCODE_WUR_AE_CEND2; + } + } + if ((Field_op1_Slot_inst_get (insn) == 4 || + Field_op1_Slot_inst_get (insn) == 5)) + return OPCODE_EXTUI; + if (Field_op1_Slot_inst_get (insn) == 9) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_L32E; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 3) + return OPCODE_DPFM_B; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 7) + return OPCODE_DPFM_BF; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 1) + return OPCODE_DPFR_B; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 5) + return OPCODE_DPFR_BF; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 2) + return OPCODE_DPFW_B; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 6) + return OPCODE_DPFW_BF; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 9) + return OPCODE_DHI_B; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 11) + return OPCODE_DHWBI_B; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 10) + return OPCODE_DHWB_B; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_S32E; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_S32NB; + } + if (Field_r_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_READ_IMPWIRE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_SETB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_CLRB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_WRMSK_EXPSTATE; + } + if (Field_op0_Slot_inst_get (insn) == 1) + return OPCODE_L32R; + if (Field_op0_Slot_inst_get (insn) == 2) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_L8UI; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_L16UI; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_L32I; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_S8I; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_S16I; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_S32I; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_DPFR; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_DPFW; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_DPFRO; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DPFWO; + if (Field_t_Slot_inst_get (insn) == 4) + return OPCODE_DHWB; + if (Field_t_Slot_inst_get (insn) == 5) + return OPCODE_DHWBI; + if (Field_t_Slot_inst_get (insn) == 6) + return OPCODE_DHI; + if (Field_t_Slot_inst_get (insn) == 7) + return OPCODE_DII; + if (Field_t_Slot_inst_get (insn) == 8) + { + if (Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_DPFL; + if (Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_DHU; + if (Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_DIU; + if (Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_DIWB; + if (Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_DIWBI; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_DIWBUI_P; + } + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_IPF; + if (Field_t_Slot_inst_get (insn) == 13) + { + if (Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_IPFL; + if (Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_IHU; + if (Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_IIU; + } + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_IHI; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_III; + } + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_L16SI; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_MOVI; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_L32AI; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_ADDI; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_ADDMI; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_S32RI; + } + if (Field_op0_Slot_inst_get (insn) == 4) + { + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 10) + return OPCODE_RUR_AE_OVERFLOW; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 11) + return OPCODE_WUR_AE_OVERFLOW; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_SAR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 13) + return OPCODE_WUR_AE_SAR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 14) + return OPCODE_RUR_AE_BITPTR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 15) + return OPCODE_WUR_AE_BITPTR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 0) + return OPCODE_RUR_AE_BITSUSED; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 1) + return OPCODE_WUR_AE_BITSUSED; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 2) + return OPCODE_RUR_AE_TABLESIZE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 3) + return OPCODE_WUR_AE_TABLESIZE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 4) + return OPCODE_RUR_AE_FIRST_TS; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 5) + return OPCODE_WUR_AE_FIRST_TS; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 6) + return OPCODE_RUR_AE_NEXTOFFSET; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 7) + return OPCODE_WUR_AE_NEXTOFFSET; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 8) + return OPCODE_RUR_AE_SEARCHDONE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 9) + return OPCODE_WUR_AE_SEARCHDONE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 10) + return OPCODE_RUR_AE_CWRAP; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 11) + return OPCODE_WUR_AE_CWRAP; + } + if (Field_op0_Slot_inst_get (insn) == 5) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALL0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALL4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALL8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALL12; + } + if (Field_op0_Slot_inst_get (insn) == 6) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_J; + if (Field_n_Slot_inst_get (insn) == 1) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQZ; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEZ; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTZ; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEZ; + } + if (Field_n_Slot_inst_get (insn) == 2) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQI; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEI; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEI; + } + if (Field_n_Slot_inst_get (insn) == 3) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_ENTRY; + if (Field_m_Slot_inst_get (insn) == 1) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BF; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BT; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LOOP; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_LOOPNEZ; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_LOOPGTZ; + } + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTUI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEUI; + } + } + if (Field_op0_Slot_inst_get (insn) == 7) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BNONE; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BEQ; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_BLT; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_BLTU; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BALL; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_BBC; + if ((Field_r_Slot_inst_get (insn) == 6 || + Field_r_Slot_inst_get (insn) == 7)) + return OPCODE_BBCI; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_BANY; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_BNE; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_BGE; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_BGEU; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_BNALL; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_BBS; + if ((Field_r_Slot_inst_get (insn) == 14 || + Field_r_Slot_inst_get (insn) == 15)) + return OPCODE_BBSI; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16b_get (insn) == 12) + { + if (Field_i_Slot_inst16b_get (insn) == 0) + return OPCODE_MOVI_N; + if (Field_i_Slot_inst16b_get (insn) == 1) + { + if (Field_z_Slot_inst16b_get (insn) == 0) + return OPCODE_BEQZ_N; + if (Field_z_Slot_inst16b_get (insn) == 1) + return OPCODE_BNEZ_N; + } + } + if (Field_op0_Slot_inst16b_get (insn) == 13) + { + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 1) + return OPCODE_AE_L16SI_N; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 2) + return OPCODE_AE_L16UI_N; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 3) + return OPCODE_AE_S16I_N; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 4 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 0) + return OPCODE_AE_SEXT16; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 4 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 1) + return OPCODE_AE_ZEXT16; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 5 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 1) + return OPCODE_AE_ZEXT8; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 5 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 0) + return OPCODE_AE_CLAMPS16; + if (Field_r_Slot_inst16b_get (insn) == 0) + return OPCODE_MOV_N; + if (Field_r_Slot_inst16b_get (insn) == 15) + { + if (Field_t_Slot_inst16b_get (insn) == 0) + return OPCODE_RET_N; + if (Field_t_Slot_inst16b_get (insn) == 1) + return OPCODE_RETW_N; + if (Field_t_Slot_inst16b_get (insn) == 2) + return OPCODE_BREAK_N; + if (Field_t_Slot_inst16b_get (insn) == 3 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_NOP_N; + if (Field_t_Slot_inst16b_get (insn) == 6 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_ILL_N; + } + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16a_get (insn) == 8) + return OPCODE_L32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 9) + return OPCODE_S32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 10) + return OPCODE_ADD_N; + if (Field_op0_Slot_inst16a_get (insn) == 11) + return OPCODE_ADDI_N; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae10_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae10_slot0_24_0_Slot_ae10_slot0_get (insn) == 12720387) + return OPCODE_NOP; + if (Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (insn) == 12872 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_ALL4; + if (Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (insn) == 12872 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_ANY4; + if (Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (insn) == 12873 && + Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_get (insn) == 18) + return OPCODE_SSAI; + if (Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (insn) == 12873 && + Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_ALL8; + if (Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (insn) == 12873 && + Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_ANY8; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3082) + return OPCODE_MAXU; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3083) + return OPCODE_MIN; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3084) + return OPCODE_SALT; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3085) + return OPCODE_SALTU; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3086) + return OPCODE_MOVF; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3087) + return OPCODE_MOVT; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3088) + return OPCODE_ORBC; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3089) + return OPCODE_XORB; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3090 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_ABS; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3090 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_NEG; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3104 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3144) + return OPCODE_ADD; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3145) + return OPCODE_ADDX2; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3146) + return OPCODE_MINU; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3147) + return OPCODE_MOVEQZ; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3148) + return OPCODE_SRC; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3149) + return OPCODE_SUB; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3150) + return OPCODE_CLAMPS; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3151) + return OPCODE_SEXT; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3154 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3154 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3208) + return OPCODE_ADDX4; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3209) + return OPCODE_ADDX8; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3210) + return OPCODE_MOVGEZ; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3211) + return OPCODE_MOVLTZ; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3212) + return OPCODE_SUBX2; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3213) + return OPCODE_SUBX4; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3214) + return OPCODE_SRLI; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3215) + return OPCODE_ANDB; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3272) + return OPCODE_AND; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3273) + return OPCODE_MAX; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3274) + return OPCODE_MOVNEZ; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3275) + return OPCODE_OR; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3276) + return OPCODE_SUBX8; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3277) + return OPCODE_XOR; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3278) + return OPCODE_ANDBC; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3279) + return OPCODE_ORB; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1296) + return OPCODE_AE_L16M_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1297) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1298) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1299) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1300) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1301) + return OPCODE_AE_L16_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1302) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1303) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1304) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1305) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1306) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1307) + return OPCODE_AE_L32_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1308) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1309) + return OPCODE_AE_L64_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1310) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1311) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1328) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1329) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1330) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1331) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1332) + return OPCODE_AE_L16_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1333) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1334) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1335) + return OPCODE_AE_L32M_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1336) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1337) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1338) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1339) + return OPCODE_AE_L32_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1340) + return OPCODE_AE_L32_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1341) + return OPCODE_AE_L64_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1342) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1343) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1360) + return OPCODE_AE_L16M_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1361) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1362) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1363) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1364) + return OPCODE_AE_L16_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1365) + return OPCODE_AE_L16_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1366) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1367) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1368) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1369) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1370) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1371) + return OPCODE_AE_L32_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1372) + return OPCODE_AE_L64_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1373) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1374) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1375) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1392) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1393) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1394) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1395) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1396) + return OPCODE_AE_L16_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1397) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1398) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1399) + return OPCODE_AE_L32M_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1400) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1401) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1402) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1403) + return OPCODE_AE_L32_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1404) + return OPCODE_AE_L64_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1405) + return OPCODE_AE_L64_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1406) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1407) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1536) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1537) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1538) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1539) + return OPCODE_AE_L8_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1540) + return OPCODE_SRAI; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1568) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1569) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1570) + return OPCODE_AE_L8_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1571) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1576 && + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1576 && + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1600) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1601) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1602) + return OPCODE_AE_L8_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1603) + return OPCODE_AE_L8_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1608 && + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1608 && + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1632) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1633) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1634) + return OPCODE_AE_L8_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1635) + return OPCODE_SLLI; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_6_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 12) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 13) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 14) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 15) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 158) + return OPCODE_ADDI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 159) + return OPCODE_ADDMI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 160) + return OPCODE_L16SI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 161) + return OPCODE_S16I; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 164) + return OPCODE_L16UI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 165) + return OPCODE_S32I; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 168) + return OPCODE_L32I; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 169) + return OPCODE_S8I; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 172) + return OPCODE_L8UI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 173) + return OPCODE_MOVI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 194 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 194 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 194 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae10_slot0_24_17_Slot_ae10_slot0_get (insn) == 78) + return OPCODE_EXTUI; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 12) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 13) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 14) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 15) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 16) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 17) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 18) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 19) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 20) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 21) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 22) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 23) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 24) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 25) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 26) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 27) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 28) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 29) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 30) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 31) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 32) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 33) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 34) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 35) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 36) + return OPCODE_J; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 37) + return OPCODE_CALL0; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_LAV16X4X2_XP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_AE_LAV8X8X2_XP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_L32R; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 6) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 7) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5155) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5156) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5157) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5152) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5153) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5154) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5158) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5159) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5160) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_8_Slot_ae10_slot0_get (insn) == 320) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_get (insn) == 9 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_get (insn) == 9 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49680 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_CALLX0; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49682 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_JX; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49683 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_RET; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49685 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SSA8B; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49686 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SSA8L; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49687 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SSL; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49688 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SSR; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae10_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae10_slot1_25_1_Slot_ae10_slot1_get (insn) == 10793092 && + Field_fld_ae10_slot1_0_0_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5134) + return OPCODE_MAXU; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5135) + return OPCODE_MIN; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5136) + return OPCODE_SALT; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5137) + return OPCODE_SALTU; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5138) + return OPCODE_CLAMPS; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5139) + return OPCODE_SEXT; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5140 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 10) + return OPCODE_SLL; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5196) + return OPCODE_ADD; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5197) + return OPCODE_ADDX2; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5198) + return OPCODE_MINU; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5199) + return OPCODE_MOVEQZ; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5200) + return OPCODE_SRC; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5201) + return OPCODE_SUB; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5202) + return OPCODE_SRLI; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5203 && + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5203 && + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5203 && + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5203 && + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5260) + return OPCODE_ADDX4; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5261) + return OPCODE_ADDX8; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5262) + return OPCODE_MOVGEZ; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5263) + return OPCODE_MOVLTZ; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5264) + return OPCODE_SUBX2; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5265) + return OPCODE_SUBX4; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5324) + return OPCODE_AND; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5325) + return OPCODE_MAX; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5326) + return OPCODE_MOVNEZ; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5327) + return OPCODE_OR; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5328) + return OPCODE_SUBX8; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5329) + return OPCODE_XOR; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2328) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2329) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2330) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2331) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2332) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2333) + return OPCODE_AE_L32_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2334) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2335) + return OPCODE_AE_L64_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2352) + return OPCODE_AE_L16M_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2353) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2354) + return OPCODE_AE_L16M_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2355) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2356) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2357) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2358) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2359) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2360) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2361) + return OPCODE_AE_L32M_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2362) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2363) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2364) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2365) + return OPCODE_AE_L32_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2366) + return OPCODE_AE_L32_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2367) + return OPCODE_AE_L64_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2384) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2385) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2386) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2387) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2388) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2389) + return OPCODE_AE_L16_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2390) + return OPCODE_AE_L16_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2391) + return OPCODE_AE_L16_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2392) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2393) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2394) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2395) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2396) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2397) + return OPCODE_AE_L32_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2398) + return OPCODE_AE_L64_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2399) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2416) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2417) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2418) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2419) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2420) + return OPCODE_AE_L16_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2421) + return OPCODE_AE_L16_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2422) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2423) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2424) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2425) + return OPCODE_AE_L32M_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2426) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2427) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2428) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2429) + return OPCODE_AE_L32_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2430) + return OPCODE_AE_L64_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2431) + return OPCODE_AE_L64_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2560) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2561) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2562) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2563) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2564) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2565) + return OPCODE_AE_L8_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2566) + return OPCODE_SRAI; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2570 && + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2592) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2593) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2594) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2595) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2596) + return OPCODE_AE_L8_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2597) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2602 && + Field_fld_ae10_slot1_3_2_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2602 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 4) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2602 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 5) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2602 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 6) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2602 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 7) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2624) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2625) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2626) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2627) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2628) + return OPCODE_AE_L8_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2629) + return OPCODE_AE_L8_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2633 && + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2633 && + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2656) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2657) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2658) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2659) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2660) + return OPCODE_AE_L8_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2661) + return OPCODE_SLLI; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2665 && + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2665 && + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 290) + return OPCODE_MOVI; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 292) + return OPCODE_ADDI; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 293) + return OPCODE_ADDMI; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 296) + return OPCODE_L16SI; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 297) + return OPCODE_L32I; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 300) + return OPCODE_L16UI; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 301) + return OPCODE_L8UI; + if (Field_fld_ae10_slot1_25_17_Slot_ae10_slot1_get (insn) == 144) + return OPCODE_EXTUI; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 48) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 49) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 50) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 51) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 52) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 53) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 54) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 55) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 56) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 57) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 58) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 59) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 60) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 61) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 62) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 63) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 64) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 65) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 66) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 67) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 68) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 69) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 70) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 71) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 6) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 7) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 6) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 7) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 352) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_get (insn) == 10 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 8) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_get (insn) == 10 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 9) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae10_slot1_25_22_Slot_ae10_slot1_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae10_slot1_25_23_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get (insn) == 82273 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 9) + return OPCODE_SSL; + if (Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get (insn) == 83266 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 10) + return OPCODE_SSA8B; + if (Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get (insn) == 83267 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 10) + return OPCODE_SSA8L; + if (Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get (insn) == 83297 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 9) + return OPCODE_SSR; + if (Field_fld_ae10_slot1_25_9_Slot_ae10_slot1_get (insn) == 41632 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 10) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae2_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L64_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L64_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L64_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32M_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S32_H_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S64_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S64_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S64_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_ADD; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_ADDX2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_ADDX4; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_ADDX8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AND; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SLLI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_SRAI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_MAX; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S8_0_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L8_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L8_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L8_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L8_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L8_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_SUB; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_SUBX2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_SUBX4; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_SUBX8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_OR; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_XOR; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_MOVEQZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_MOVGEZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_MOVLTZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_MOVNEZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_SRC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_SALT; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_SALTU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_MAXU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_MIN; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_MINU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_SRLI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_ANDB; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_ANDBC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_ORB; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_ORBC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_XORB; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_MOVF; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_MOVT; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_CLAMPS; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SEXT; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_CALLX0; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 10 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_JX; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_RET; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 22 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_SSA8B; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_SSA8L; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 30 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_SSL; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 12 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_MOVBD1X4; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_MOVBD1X2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_SA32X2_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_SA32X2F24_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_SA32X2F24_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SA24_L_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SA24_L_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_SA24X2_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SA24X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16X2M_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S32M_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6304 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 175) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6304 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 47) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6305 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 175) + return OPCODE_DPFM_B; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6305 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 47) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6306 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 47) + return OPCODE_DPFM_BF; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6306 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 175) + return OPCODE_DPFR_B; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6307 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 47) + return OPCODE_DPFR_BF; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6307 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 175) + return OPCODE_DPFW_B; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6308 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 175 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_SSR; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6308 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 47) + return OPCODE_DPFW_BF; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA32X2POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA32X2NEG_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4NEG_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA32X2POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA8X8POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA8X8NEG_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA8X8NEG_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA8X8POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA8X8POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_0_Slot_ae2_slot0_get (insn) == 36789) + return OPCODE_NOP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_0_Slot_ae2_slot0_get (insn) == 4020) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_2_Slot_ae2_slot0_get (insn) == 1004) + return OPCODE_AE_MOVALIGN; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24NEG_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6325 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6325 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6326 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6326 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24X2NEG_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6327 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6327 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24X2POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 49) + return OPCODE_SSAI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_ALL4; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_ANY4; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 33) + return OPCODE_ALL8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 33) + return OPCODE_ANY8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_4_Slot_ae2_slot0_get (insn) == 1585) + return OPCODE_AE_MOVASAR; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6407 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6411 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6415 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6419 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6420 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6423 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6426 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6426 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVTA32F24S_L; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6426 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVTA32F24S_H; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6426 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6427 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6427 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6427 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6427 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6427 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6430 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6430 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_NSA64; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6430 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_NSAZ16_0; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6430 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_ABS; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_NEG; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 12 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_TRUNCA32Q48; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6456 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6456 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6457 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6457 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6458 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6458 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6459 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6459 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6460 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6460 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6461 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6461 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6462 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6462 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6463 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6463 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16M_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L16M_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7534) + return OPCODE_ADDI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7535) + return OPCODE_ADDMI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7544) + return OPCODE_L16SI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7545) + return OPCODE_L32I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7546) + return OPCODE_S16I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7547) + return OPCODE_S8I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7548) + return OPCODE_L16UI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7549) + return OPCODE_L8UI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7550) + return OPCODE_S32I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7551) + return OPCODE_MOVI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7554 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7554 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7554 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_MOVI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_MOVAD8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7558 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7558 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7558 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_LA24_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_LA24_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_LA24X2_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_LA24X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L16_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L16_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L16_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L16_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L16_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L32M_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32M_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L32_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L32_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L32_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_get (insn) == 3224 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_TRUNC16_H; + if (Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_get (insn) == 3225 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_UTRUNC16_H; + if (Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_get (insn) == 3765) + return OPCODE_EXTUI; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 457) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 459) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 461) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 463) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1564 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_EQ8; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1565 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_LE8; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1566 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1566 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 31) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1566 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_LT8; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1567 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1567 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 31) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1567 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1567 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 27) + return OPCODE_AE_S24RA64S_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1568 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1569 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1570 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1571 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1572 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1573 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1600 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1600 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1600 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1600 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1601 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_AE_MOV; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1601 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1601 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1601 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1602 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1602 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1602 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_CVTF16S_L; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1602 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_CVTF16S_H; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1603 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_CVTSF16_L; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1603 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_CVTSF16_H; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1603 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_FICEIL_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1603 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_FIFLOOR_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1604 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1604 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_FIRINT_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1604 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_FIROUND_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1604 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_FITRUNC_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1605 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1608 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_OLE_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1608 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_OEQ_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1609 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_OLT_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1609 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_UEQ_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1610 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_ULE_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1610 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_ULT_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1611 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1611 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1611 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_UN_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1613 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_PKSR32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1613 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_PKSR24; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1613 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1613 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_PKSR16; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1806) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1807) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1810) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1811) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1812) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1813) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1814) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1815) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1816) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1817) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_S16X4RA32S_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_MOVT64; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MOVF64; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_MOVT_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_MOVF_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1864) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1865) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1866) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1867) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1868) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1869) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1870) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1871) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1874) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1875) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1876) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1877) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1878) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1879) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_LT16; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_LE16; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_EQ16; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LT32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_LE32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_EQ32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_LT64; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_LE64; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_EQ64; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_MOVEQZ_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_MOVNEZ_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_MOVGEZ_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_MOVLTZ_S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 232 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRAA32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 232 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRAA32RS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 232 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SLAA64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 233 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRAA32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 233 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SLAA64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 233 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRAA32SYMS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 234 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRAA64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 234 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SLAA8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 234 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRAA8RS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 235 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRAAQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 235 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SLAA8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 235 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRAA8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 768 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADD64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 768 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADD8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 769 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 769 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADD8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 770 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 770 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 771 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADDSUB32_HL_LH; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 771 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADDSUB32S_HL_LH; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 772 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_MAX32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 772 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MAX16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 773 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MAX64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 773 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_MAX8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 774 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_MIN32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 774 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MIN16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 775 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MIN64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 775 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_MIN8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 776 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUB16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 776 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MOVNEG32S_T; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 777 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUB24S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 777 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUB16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 778 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUB32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 778 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUB32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 779 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUB64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 779 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUB64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 780 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUB8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 780 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUB8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 781 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 781 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 782 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 787 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_FLOAT16_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 787 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_UFLOAT16_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 788 && + Field_fld_ae2_slot0_14_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 241) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 242) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 246) + return OPCODE_AE_ABS32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 245) + return OPCODE_AE_ABS24S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 247) + return OPCODE_AE_ABS32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 244) + return OPCODE_AE_ABS16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 243) + return OPCODE_AE_ABS16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 248) + return OPCODE_AE_ABS64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 252) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_ABS64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 255) + return OPCODE_AE_MUL16JS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 240) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_ABS8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_ABS8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 253) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 254) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 240) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 243) + return OPCODE_AE_NEG32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 242) + return OPCODE_AE_NEG24S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 244) + return OPCODE_AE_NEG32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 241) + return OPCODE_AE_NEG16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 245) + return OPCODE_AE_NEG64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 248) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 246) + return OPCODE_AE_NEG64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 247) + return OPCODE_AE_NEG8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 800 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 800 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 800 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 800 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 801 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 801 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L64_IP; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 801 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 801 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 802 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 802 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 802 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 802 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S64_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S64_IP; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_NSA16X4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FICEIL_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FIFLOOR_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FIRINT_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FIROUND_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 10 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FITRUNC_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 15 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_RMINNUM_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_RMAXNUM_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 804 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 28 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS24; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 804 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 30 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 804 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 29 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 804 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 31 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 805 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 30 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLASQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 805 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 28 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 805 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 31 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLASSQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 805 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 29 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 806 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 28 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAS24; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 806 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 29 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAS32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 806 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 31 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRASQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 806 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 30 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAS64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 807 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 28 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRLS24; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 807 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 29 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRLS32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 807 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 31 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRLSQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 807 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 30 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRLS64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 898) + return OPCODE_AE_TRUNCA16X4F32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 899) + return OPCODE_AE_TRUNCA16X4F64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 900) + return OPCODE_AE_TRUNCI32F64S_L; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 901) + return OPCODE_AE_TRUNCI32X2F64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 902) + return OPCODE_AE_SEL16I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 909 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_ADDC32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 909 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_ADDC32U; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 910 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_BMAX32X2; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 910 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_BMIN32X2; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 911 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SUBC32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 911 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SUBC32U; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 16) + return OPCODE_AE_SRAI16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 17) + return OPCODE_AE_SRAI16R; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 20) + return OPCODE_AE_SRLA32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SLAI16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SLAA16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_SLAAQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 23) + return OPCODE_AE_SRLAQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 21) + return OPCODE_AE_SRLA64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SLAASQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 22) + return OPCODE_AE_SRLA8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 24) + return OPCODE_AE_SRLI16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_SLAI16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_SLAA16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 19) + return OPCODE_AE_SRLA16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 18) + return OPCODE_AE_SRAI16SYM; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_AND; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_NAND; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_OR; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_XOR; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SRAV16RS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAV32RS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_NSAZ32X4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_NSA32X4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 930) + return OPCODE_AE_TRUNCA32F64S_L; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 931) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 940 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_CALL0; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 940 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_J; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_ADD32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_ADD16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_ADD24S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_ADD32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_ADD16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADD64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_BMAX16X4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_BMIN16X4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_SRA64_32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_SLAA32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_SRAA16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SRAA16RS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SLAA32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 18 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAI8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 19 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAI8R; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 20 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRLI8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAI8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 17 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAI8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SRAA16SYMS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_FLOAT16_HX4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_UFLOAT16_HX4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_TRUNC16_HX4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_UTRUNC16_HX4; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 56) + return OPCODE_AE_TRUNCI16X4F64S; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 57 && + Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_L32R; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 58 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SLAI64; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 58 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_SRLI64; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 58 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SRAI64; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 58 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SLAISQ56S; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 58 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAI64S; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 49 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_FLOAT_S; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 49 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_UFLOAT_S; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_TRUNC_S; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_UTRUNC_S; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 36) + return OPCODE_TRUNC_SX2; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 44) + return OPCODE_UTRUNC_SX2; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 32) + return OPCODE_FLOAT_SX2; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 40) + return OPCODE_UFLOAT_SX2; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_MOVT8X16_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_MOVT8X16_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_18_17_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_ADDW8; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_ADDW16; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_ADDW32; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SUBW8; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SUBW16; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SUBW32; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_ADDW8U; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SUBW8U; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 9 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 4 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 12 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 8 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 10 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 26) + return OPCODE_AE_CVTA32X4F8_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 27) + return OPCODE_AE_CVTA32X4F8_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 20) + return OPCODE_AE_CVTA32X4F8S_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 21) + return OPCODE_AE_CVTA32X4F8S_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 24) + return OPCODE_AE_CVTA32X4F8U_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 25) + return OPCODE_AE_CVTA32X4F8U_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 22) + return OPCODE_AE_CVTA32X4F8US_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 23) + return OPCODE_AE_CVTA32X4F8US_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 16) + return OPCODE_AE_CVTA32X4F16; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 17) + return OPCODE_AE_CVTA32X4F16S; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 18) + return OPCODE_AE_CVTA32X4F16U; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 19) + return OPCODE_AE_CVTA32X4F16US; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 28) + return OPCODE_AE_CVTI16X4X2F8; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 29) + return OPCODE_AE_CVTI16X4X2F8S; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 30) + return OPCODE_AE_CVTI16X4X2F8U; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 31) + return OPCODE_AE_CVTI16X4X2F8US; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_LAV8X8X2_XP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LAV16X4X2_XP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 27 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_CVTA16X4X2F8; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 27 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_CVTA16X4X2F8S; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 27 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_CVTA16X4X2F8U; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 27 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_CVTA16X4X2F8US; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_CVTI32X4F8_H; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_CVTI32X4F8_L; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_CVTI32X4F8S_H; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_CVTI32X4F8S_L; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_CVTI32X4F8U_H; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_CVTI32X4F8U_L; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_CVTI32X4F8US_H; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_CVTI32X4F8US_L; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_CVTI32X4F16; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_CVTI32X4F16S; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_CVTI32X4F16U; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVTI32X4F16US; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SLAI24; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_SRLI24; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_SRAI24; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SLAI32; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SRLI32; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SRAI32; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRAI32R; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAI24S; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SLAI32S; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRAI32SYM; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVDEXT; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_get (insn) == 16) + return OPCODE_AE_MOVADEXT_H; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_get (insn) == 17) + return OPCODE_AE_MOVADEXT_L; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCI16X4F32S; + if (Field_fld_ae2_slot0_40_26_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVT16X8; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_BBSI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_BALL_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_BANY_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_BBC_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_BBS_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_BEQ_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_BGEU_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_BGE_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_BLTU_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_BLT_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_BNALL_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_BNE_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_BNONE_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_BEQZ_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_BGEZ_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_BLTZ_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_BNEZ_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_BEQI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_BGEI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_BLTI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_BNEI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_BGEUI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_BLTUI_W15; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae2_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7692 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_SLL; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7692 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_TRUNCA32Q48; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7692 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_NSA64; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7692 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_NSAZ16_0; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7692 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7693 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7694 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7694 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7694 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7694 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7695 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7695 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7695 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7695 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7698) + return OPCODE_ADD; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7700 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7700 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7700 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7700 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7706) + return OPCODE_ADDX2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_0_Slot_ae2_slot1_get (insn) == 1794) + return OPCODE_NOP; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_SSL; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 5 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_SSR; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 6 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_MOVASAR; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7746) + return OPCODE_ADDX4; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7747 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_CVTA32F24S_H; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7754) + return OPCODE_ADDX8; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7755 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_CVTA32F24S_L; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7762) + return OPCODE_AND; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7763 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7770) + return OPCODE_MAX; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7771 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7778) + return OPCODE_MAXU; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7779 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7786) + return OPCODE_MIN; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7787 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7794) + return OPCODE_MINU; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7795 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7802) + return OPCODE_MOVEQZ; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7803 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7810) + return OPCODE_MOVGEZ; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7818) + return OPCODE_MOVLTZ; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7826) + return OPCODE_MOVNEZ; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7834) + return OPCODE_OR; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7842) + return OPCODE_SALT; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7850) + return OPCODE_SALTU; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7858) + return OPCODE_SRC; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7866) + return OPCODE_SUB; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7874) + return OPCODE_SUBX2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7882) + return OPCODE_SUBX4; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7890) + return OPCODE_SUBX8; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7898) + return OPCODE_XOR; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7906) + return OPCODE_CLAMPS; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7914) + return OPCODE_SEXT; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7922) + return OPCODE_SRLI; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7930) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7936 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_SSA8B; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7944 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_SSA8L; + if (Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_get (insn) == 1921 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_get (insn) == 1923 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 928 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_ABS_S; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 929 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_CONJC_H; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 930 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_CONJC_S; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 931 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_MULJC_H; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 932 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_MULJC_S; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 933 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_NEG_S; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 934 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 11) + return OPCODE_CONST_S; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 934 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 10) + return OPCODE_CONST_H; + if (Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_get (insn) == 480 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_SRAI; + if (Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_get (insn) == 496 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_SSAI; + if (Field_fld_ae2_slot1_36_17_Slot_ae2_slot1_get (insn) == 241 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_SLLI; + if (Field_fld_ae2_slot1_36_18_Slot_ae2_slot1_get (insn) == 120 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 13 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD8; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 12) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 13) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 14) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 15) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 16) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 17) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 18) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 19) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 20) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 21 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 21 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 21 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 21 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 22 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 22 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 22 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 22 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 23 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 23 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 23 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 23 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 24 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 24 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 24 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 24 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 25 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 25 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 25 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 25 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 26 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 26 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 26 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 26 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 27 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 27 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 27 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 27 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_ADDI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_ADDMI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_L16UI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_L16SI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_L32I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_L8UI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_MOVI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 83) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 84) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 80) + return OPCODE_AE_L16M_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 81) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 82) + return OPCODE_AE_L16M_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 85) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 100) + return OPCODE_AE_L16_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 101) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 97) + return OPCODE_AE_L16_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 98) + return OPCODE_AE_L16_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 99) + return OPCODE_AE_L16_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 102) + return OPCODE_AE_L16_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 106) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 107) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 103) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 104) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 105) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 108) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 126) + return OPCODE_AE_L32_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 127) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 123) + return OPCODE_AE_L32_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 124) + return OPCODE_AE_L32_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 125) + return OPCODE_AE_L32_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 112) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 109) + return OPCODE_AE_L32M_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 110) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 111) + return OPCODE_AE_L32M_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 113) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 89) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 90) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 86) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 87) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 88) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 91) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 115) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 116) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 114) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 117) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 119) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 120) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 118) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 122) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 93) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 94) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 92) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 96) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 121) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 95) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 8 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_MOVEQZ_S; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 9 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_MOVNEZ_S; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 8 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_MOVGEZ_S; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 9 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_MOVLTZ_S; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 11) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L64_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 11) + return OPCODE_AE_L64_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 13) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 7) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 15) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 8) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 14) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 12) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 7) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 8) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 9) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 10) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 11) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 12) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 13) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 14) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 15) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 16) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 17) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 26) + return OPCODE_AE_L8_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 27) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 23) + return OPCODE_AE_L8_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 24) + return OPCODE_AE_L8_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 25) + return OPCODE_AE_L8_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 28) + return OPCODE_AE_L8_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 49 && + Field_fld_ae2_slot1_3_3_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 19) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 20) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 48 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 18) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 22) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L64_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L64_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_AE_L64_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 21) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 49 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 14) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 29) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_MOV; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 49 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 12) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 49 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 8) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 49 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 10) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 14 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 14 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_NSA16X4; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_ABS_H; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_NEG_H; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 8 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_2_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 8 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae2_slot1_36_22_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae2_slot1_36_23_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae3_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (insn) == 133982 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_ALL4; + if (Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (insn) == 133982 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_ANY4; + if (Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (insn) == 133983 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 2 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_SSAI; + if (Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (insn) == 133983 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_ALL8; + if (Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (insn) == 133983 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_ANY8; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66890) + return OPCODE_AE_LBK; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66891) + return OPCODE_AND; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66894) + return OPCODE_MAX; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66895) + return OPCODE_MAXU; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66898) + return OPCODE_AE_SBI_IC; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66899) + return OPCODE_AE_SBI_IC1; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66902) + return OPCODE_AE_SBI_IP; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66903) + return OPCODE_AE_VLDL16T; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66906) + return OPCODE_AE_VLDL32T; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66907) + return OPCODE_AE_VLEL16T; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66910) + return OPCODE_AE_VLEL32T; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66911) + return OPCODE_MOVF; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66914) + return OPCODE_MOVT; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66915) + return OPCODE_AE_LBKI; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66918) + return OPCODE_CLAMPS; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66919) + return OPCODE_SEXT; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66922) + return OPCODE_SRLI; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66923) + return OPCODE_ANDB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66926) + return OPCODE_ANDBC; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66927) + return OPCODE_ORB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66930) + return OPCODE_ORBC; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66931) + return OPCODE_XORB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66950 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_SLL; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66951 && + Field_fld_ae3_slot0_9_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_MOVEA; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66990 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVBA1X2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_SRA; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_SRL; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_MOVAB4; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_MOVAB2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_MOVAB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_MOVBA; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_MOVBA4; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_AE_MOVBA2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get (insn) == 22) + return OPCODE_AE_MOVB2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get (insn) == 39) + return OPCODE_AE_MOVB4; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_AE_LBI; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_LBSI; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 2 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_MOVAE; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67354 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_ABS; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67354 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_AE_LB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67355 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_NEG; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67355 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_LBS; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67364) + return OPCODE_ADD; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67365) + return OPCODE_ADDX2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67366) + return OPCODE_ADDX4; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67367) + return OPCODE_ADDX8; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67368) + return OPCODE_SALTU; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67369) + return OPCODE_SRC; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67370) + return OPCODE_SUB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67371) + return OPCODE_SUBX2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67372) + return OPCODE_SUBX4; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67373) + return OPCODE_SUBX8; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67374) + return OPCODE_XOR; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67375) + return OPCODE_AE_SBI; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67409) + return OPCODE_MIN; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67411) + return OPCODE_MINU; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67413) + return OPCODE_MOVEQZ; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67415) + return OPCODE_MOVGEZ; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67417) + return OPCODE_MOVLTZ; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67419) + return OPCODE_MOVNEZ; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67421) + return OPCODE_OR; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67423) + return OPCODE_SALT; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33329) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33331) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33333) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33335) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33337) + return OPCODE_AE_L16_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33339) + return OPCODE_AE_L16_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33341) + return OPCODE_AE_L16_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33343) + return OPCODE_AE_L16_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33398) + return OPCODE_AE_L16M_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33399) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33400) + return OPCODE_AE_L16M_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33401) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33402) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33403) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33404) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33405) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33406) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33407) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33409) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33411) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33413) + return OPCODE_AE_S64_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33415) + return OPCODE_AE_S64_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33417) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33419) + return OPCODE_AE_S64_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33421) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33423) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33425) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33427) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33429) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33431) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33433) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33435) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33437) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33439) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33441) + return OPCODE_SLLI; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33443) + return OPCODE_SRAI; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33467 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33467 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33469 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33469 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33471 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33471 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33473 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33477 && + Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_get (insn) == 192) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33489 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33489 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33489 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33489 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33491 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33491 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33491 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33491 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA8X8_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33493 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33493 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33493 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33493 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_MOVI; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33536 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33537 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33538 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33539 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33540 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33541 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33542 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33543 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33544 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33545 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33546 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33547 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33548 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33549 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33550 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33551 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33552 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33553 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33554 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33555 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33556 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33557 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33558 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33559 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33560 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33561 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33562 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33563 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33564 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33565 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33566 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33567 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33568) + return OPCODE_AE_L16_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33569) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33570) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33571) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33572) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33573) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33574) + return OPCODE_AE_L32M_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33575) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33576) + return OPCODE_AE_L32M_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33577) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33578) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33579) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33580) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33581) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33582) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33583) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33584) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33585) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33586) + return OPCODE_AE_L32_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33587) + return OPCODE_AE_L32_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33588) + return OPCODE_AE_L32_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33589) + return OPCODE_AE_L32_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33590) + return OPCODE_AE_L32_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33591) + return OPCODE_AE_L64_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33592) + return OPCODE_AE_L64_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33593) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33594) + return OPCODE_AE_L64_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33595) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33596) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33597) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33598) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33599) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33600) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33601) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33602) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33603) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33604) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33605) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33606) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33607) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33608) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33609) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33610) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33611) + return OPCODE_AE_L8_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33612) + return OPCODE_AE_L8_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33613) + return OPCODE_AE_L8_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33614) + return OPCODE_AE_L8_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33615) + return OPCODE_AE_L8_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33616) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33617) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33618) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33619) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33620) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33621) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33622) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33623) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33624) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33625) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33626) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33627) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33628) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33629) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33630) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33631) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33632) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33633) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33634) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33635) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33636) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33637) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33638) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33639) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33640) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33641) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33642) + return OPCODE_AE_S32M_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33643) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33644) + return OPCODE_AE_S32M_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33645) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33646) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33647) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33648) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33649) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33650) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33651) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33652) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33653) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33654) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33655) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33656) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33657) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33658) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33659) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33660) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33661) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33662) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33663) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_AE_TRUNCA16P24S_L; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_NSAZ16_0; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33688 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33688 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33689 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33689 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33690 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33690 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_MOVAD8; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33691 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33691 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33691 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33691 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33694 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33694 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33694 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33694 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33695 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33695 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33695 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33695 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33728 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33729 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16698) + return OPCODE_AE_MOVT64; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16840 && + Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16840 && + Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_ABS32; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_AE_NEG24S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_ABS24S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 13) + return OPCODE_AE_ABS32S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_AE_NEG16S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_ABS16S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_ABS64; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_MOV; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_NEG32; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_AE_NEG32S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_AE_NEG64; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8338) + return OPCODE_AE_ADD16S; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8339) + return OPCODE_AE_ADD32S; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8340) + return OPCODE_AE_MAX32; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8341) + return OPCODE_AE_MIN32; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8342) + return OPCODE_AE_ROUND16X4F32SASYM; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8343) + return OPCODE_AE_ROUND24X2F48SSYM; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8344) + return OPCODE_AE_SUB16S; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8345) + return OPCODE_AE_SUB32S; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8346) + return OPCODE_AE_AND; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8347) + return OPCODE_AE_OR; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8348) + return OPCODE_AE_XOR; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8416 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8416 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8416 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8416 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8417 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8417 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L64_IP; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8417 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8417 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8418 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8418 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8418 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8418 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_S64_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8419 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8419 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S64_IP; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8424 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LT16; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8424 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LE32; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8424 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_EQ32; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8425 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8425 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8425 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LE16; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8425 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_EQ16; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8425 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LT32; + if (Field_fld_ae3_slot0_32_16_Slot_ae3_slot0_get (insn) == 4168) + return OPCODE_MOVI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2078) + return OPCODE_EXTUI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2079 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_ADDI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2079 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_ADDMI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2080 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_L16UI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2080 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_L16SI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2081 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_L32I; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2081 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_L8UI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2082 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_S16I; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2082 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_S32I; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2083 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_S8I; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2092 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2092 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_LOOPGTZ; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2092 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_LOOPNEZ; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1036) + return OPCODE_J; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1037) + return OPCODE_CALL0; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1048 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1048 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1048 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S16X4RA32S_IP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 256) + return OPCODE_L32R; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 257) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 258 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 258 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCI32X2F64S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 13 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SRAS24; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_SRLA32; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_SLAA16S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_SRAA16S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_SRAA16RS; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 13 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_AE_SLAA32S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_SRAA32S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_SLAAQ56; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SRAAQ56; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_AE_SLAA64; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SLAASQ56S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_SRLA16; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_BBSI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_BALL_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_BANY_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_BBC_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_BBS_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_BEQ_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_BGEU_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_BGE_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 13) + return OPCODE_BLTU_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_BLT_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_BNALL_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_BNE_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_BNONE_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_BEQZ_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_BGEZ_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get (insn) == 74) + return OPCODE_BLTZ_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get (insn) == 78) + return OPCODE_BNEZ_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_BEQI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_BGEI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_BLTI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_BNEI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_BGEUI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_BLTUI_W15; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071217 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_SBF; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071218 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLDL16C; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071219 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLES16C_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071221 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_SBF_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071222 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLDL16C_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071223 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLES16C_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071225 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_SBF_IC1; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071226 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLDL16C_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071227 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_CALLX0; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071229 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_SBF_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071230 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLES16C; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071841) + return OPCODE_AE_DB; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071843) + return OPCODE_AE_SB; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071845) + return OPCODE_AE_DB_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071847) + return OPCODE_AE_SB_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071849) + return OPCODE_AE_DB_IC1; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071851) + return OPCODE_AE_SB_IC1; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071853) + return OPCODE_AE_DB_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071855) + return OPCODE_AE_SB_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071856 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071858 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071860 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071862 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2POS_PC2; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071864 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071866 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071866 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_AE_VLDSHT; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071868 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071870 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_RUR_AE_BITPTR; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071870 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8NEG_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078411) + return OPCODE_AE_DBI; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078415) + return OPCODE_AE_DBI_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078443) + return OPCODE_AE_DBI_IC1; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078447) + return OPCODE_AE_DBI_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078475) + return OPCODE_AE_SHA32; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078479 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078479 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078479 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078479 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4POS_PC2; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078507 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8POS_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078507 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8POS_PC2; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078507 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078507 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_JX; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_get (insn) == 116) + return OPCODE_NOP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_RET; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_SSA8B; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_SSA8L; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_SSL; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_SSR; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_2_Slot_ae3_slot0_get (insn) == 28) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 2 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVALIGN; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae3_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae3_slot1_23_0_Slot_ae3_slot1_get (insn) == 1873411) + return OPCODE_NOP; + if (Field_fld_ae3_slot1_23_11_Slot_ae3_slot1_get (insn) == 914 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSAI; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 420) + return OPCODE_ADD; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 421) + return OPCODE_ADDX2; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 422) + return OPCODE_ADDX4; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 423) + return OPCODE_ADDX8; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 424) + return OPCODE_AE_LBK; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 425) + return OPCODE_AND; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 426) + return OPCODE_MAX; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 427) + return OPCODE_MAXU; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 428) + return OPCODE_MIN; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 429) + return OPCODE_MINU; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 430) + return OPCODE_MOVEQZ; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 431) + return OPCODE_MOVGEZ; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 432) + return OPCODE_MOVLTZ; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 433) + return OPCODE_MOVNEZ; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 434) + return OPCODE_OR; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 435) + return OPCODE_SALT; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 436) + return OPCODE_SALTU; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 437) + return OPCODE_SRC; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 438) + return OPCODE_SUB; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 439) + return OPCODE_SUBX2; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 440) + return OPCODE_SUBX4; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 441) + return OPCODE_SUBX8; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 442) + return OPCODE_XOR; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 443) + return OPCODE_CLAMPS; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 444) + return OPCODE_SEXT; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 445) + return OPCODE_SRLI; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 446) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 456 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 456 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 456 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 456 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 4) + return OPCODE_SRL; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 456 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_LB; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 457 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 457 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 457 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_LBI; + if (Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_get (insn) == 208) + return OPCODE_SLLI; + if (Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_get (insn) == 209) + return OPCODE_SRAI; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 34 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 34 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16M_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 34 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 34 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L16M_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 35 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 35 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 35 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 35 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 36 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 36 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 36 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 36 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 37 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L16_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 37 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L16_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 37 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 37 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 38 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L16_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 38 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 38 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L16_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 38 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 39 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 39 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 39 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 39 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 40 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 40 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32M_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 40 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 40 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L32M_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 41 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 41 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 41 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 41 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 42 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 42 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 42 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 42 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 43 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 43 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L32_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 43 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 43 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 44 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 44 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 44 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L64_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 44 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L64_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 45 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 45 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L64_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 45 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L64_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 45 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L64_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 46 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 46 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 46 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 46 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 47 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 47 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 47 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 47 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 48 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 48 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 48 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 48 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 49 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 49 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 49 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 49 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 50 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L8_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 50 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 50 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L8_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 50 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3 && + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3 && + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_MOVDA32X2; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 14) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 15) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0 && + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_MOVI; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_1_Slot_ae3_slot1_get (insn) == 6) + return OPCODE_AE_MOV; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 10) + return OPCODE_ADDI; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 11) + return OPCODE_ADDMI; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 12) + return OPCODE_L16SI; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 13) + return OPCODE_L16UI; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 14) + return OPCODE_L32I; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 15) + return OPCODE_L8UI; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 16) + return OPCODE_MOVI; + if (Field_fld_ae3_slot1_23_17_Slot_ae3_slot1_get (insn) == 4) + return OPCODE_EXTUI; + if (Field_fld_ae3_slot1_23_19_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_SEL16I; + if (Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_get (insn) == 28624) + return OPCODE_AE_MOVAE; + if (Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_get (insn) == 28625) + return OPCODE_AE_MOVEA; + if (Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (insn) == 7157 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (insn) == 7313 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSA8B; + if (Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (insn) == 7314 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSL; + if (Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (insn) == 7315 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSR; + if (Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (insn) == 7317 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSA8L; + if (Field_fld_ae3_slot1_23_9_Slot_ae3_slot1_get (insn) == 3576) + return OPCODE_AE_MOVAD32_L; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot0_22_0_Slot_ae4_slot0_get (insn) == 4088843) + return OPCODE_NOP; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 964) + return OPCODE_ADD; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 965) + return OPCODE_ADDX2; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 966) + return OPCODE_ADDX4; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 967) + return OPCODE_ADDX8; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 968) + return OPCODE_AND; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 969) + return OPCODE_MAX; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 970) + return OPCODE_MAXU; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 971) + return OPCODE_MIN; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 972) + return OPCODE_MINU; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 973) + return OPCODE_MOVEQZ; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 974) + return OPCODE_MOVGEZ; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 975) + return OPCODE_MOVLTZ; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 976) + return OPCODE_MOVNEZ; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 977) + return OPCODE_OR; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 978) + return OPCODE_SALT; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 979) + return OPCODE_SALTU; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 980) + return OPCODE_SRC; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 981) + return OPCODE_SUB; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 982) + return OPCODE_SUBX2; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 983) + return OPCODE_SUBX4; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 984) + return OPCODE_SUBX8; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 985) + return OPCODE_XOR; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 986) + return OPCODE_MOVF; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 987) + return OPCODE_MOVT; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 988) + return OPCODE_CLAMPS; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 989) + return OPCODE_SEXT; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 990) + return OPCODE_SRLI; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 991) + return OPCODE_ANDB; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 992) + return OPCODE_ANDBC; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 993) + return OPCODE_ORB; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 994) + return OPCODE_ORBC; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 995) + return OPCODE_XORB; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 996) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 997 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 997 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 997 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 1) + return OPCODE_SRA; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 997 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 1008 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_get (insn) == 480) + return OPCODE_SLLI; + if (Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_get (insn) == 481) + return OPCODE_SRAI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 50) + return OPCODE_ADDI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 51) + return OPCODE_ADDMI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 52) + return OPCODE_L16SI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 53) + return OPCODE_L16UI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 54) + return OPCODE_L32I; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 55) + return OPCODE_L8UI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 56) + return OPCODE_S16I; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 57) + return OPCODE_S32I; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 58) + return OPCODE_S8I; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 59) + return OPCODE_MOVI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 63 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 63 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 63 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae4_slot0_22_17_Slot_ae4_slot0_get (insn) == 24) + return OPCODE_EXTUI; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 4) + return OPCODE_AE_S32X2X2RNG_IP; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 5) + return OPCODE_AE_S32X2X2RNG_XP; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 6) + return OPCODE_AE_S32X2X2_IP; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 7) + return OPCODE_AE_S32X2X2_X; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 8) + return OPCODE_AE_S32X2X2_XP; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 9) + return OPCODE_J; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 10) + return OPCODE_CALL0; + if (Field_fld_ae4_slot0_22_20_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_L32R; + if (Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get (insn) == 63884) + return OPCODE_ALL4; + if (Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get (insn) == 63885) + return OPCODE_ANY4; + if (Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get (insn) == 63886 && + Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_ALL8; + if (Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get (insn) == 63886 && + Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_get (insn) == 1) + return OPCODE_ANY8; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15968) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15969) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15970) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 2) + return OPCODE_CALLX0; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 4) + return OPCODE_JX; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 5) + return OPCODE_RET; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 7) + return OPCODE_SSA8B; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 8) + return OPCODE_SSA8L; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 9) + return OPCODE_SSL; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 10) + return OPCODE_SSR; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_1_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot1_22_0_Slot_ae4_slot1_get (insn) == 2847494) + return OPCODE_NOP; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 668) + return OPCODE_ADD; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 669) + return OPCODE_ADDX2; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 670) + return OPCODE_ADDX4; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 671) + return OPCODE_ADDX8; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 672) + return OPCODE_AND; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 673) + return OPCODE_MAX; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 674) + return OPCODE_MAXU; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 675) + return OPCODE_MIN; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 676) + return OPCODE_MINU; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 677) + return OPCODE_MOVEQZ; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 678) + return OPCODE_MOVGEZ; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 679) + return OPCODE_MOVLTZ; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 680) + return OPCODE_MOVNEZ; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 681) + return OPCODE_OR; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 682) + return OPCODE_SALT; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 683) + return OPCODE_SALTU; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 684) + return OPCODE_SRC; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 685) + return OPCODE_SUB; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 686) + return OPCODE_SUBX2; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 687) + return OPCODE_SUBX4; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 688) + return OPCODE_SUBX8; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 689) + return OPCODE_XOR; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 690) + return OPCODE_CLAMPS; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 691) + return OPCODE_SEXT; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 692) + return OPCODE_SRLI; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 693) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 694 && + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 694 && + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 694 && + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 694 && + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 696 && + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 328) + return OPCODE_SLLI; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 329) + return OPCODE_SRAI; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 330) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 331) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 332) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 333) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 34) + return OPCODE_ADDI; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 35) + return OPCODE_ADDMI; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 36) + return OPCODE_L16SI; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 37) + return OPCODE_L16UI; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 38) + return OPCODE_L32I; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 39) + return OPCODE_L8UI; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 40) + return OPCODE_MOVI; + if (Field_fld_ae4_slot1_22_17_Slot_ae4_slot1_get (insn) == 16) + return OPCODE_EXTUI; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 0) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 1) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 2) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 3) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 4) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 5) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 6) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 7) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11120) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11121) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11122) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11123 && + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (insn) == 2) + return OPCODE_SSA8B; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11123 && + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (insn) == 3) + return OPCODE_SSA8L; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11123 && + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (insn) == 4) + return OPCODE_SSL; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11123 && + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (insn) == 5) + return OPCODE_SSR; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11123 && + Field_fld_ae4_slot1_3_1_Slot_ae4_slot1_get (insn) == 0) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae5_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67092) + return OPCODE_ADD; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67093) + return OPCODE_ADDX2; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67094) + return OPCODE_ADDX4; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67095) + return OPCODE_ADDX8; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67128) + return OPCODE_AND; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67129) + return OPCODE_MAX; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67130) + return OPCODE_MAXU; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67131) + return OPCODE_MIN; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67132) + return OPCODE_MINU; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67133) + return OPCODE_MOVEQZ; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67134) + return OPCODE_MOVGEZ; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67135) + return OPCODE_MOVLTZ; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67137) + return OPCODE_MOVNEZ; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67139) + return OPCODE_OR; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67141) + return OPCODE_SALT; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67143) + return OPCODE_SALTU; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67145) + return OPCODE_SRC; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67147) + return OPCODE_SUB; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67149) + return OPCODE_SUBX2; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67151) + return OPCODE_SUBX4; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67153) + return OPCODE_SUBX8; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67155) + return OPCODE_XOR; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67157) + return OPCODE_MOVF; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67159) + return OPCODE_MOVT; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67161) + return OPCODE_CLAMPS; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67163) + return OPCODE_SEXT; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67165) + return OPCODE_SRLI; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67167) + return OPCODE_AE_ARDECNORM16; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67169) + return OPCODE_ANDB; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67171) + return OPCODE_ANDBC; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67173) + return OPCODE_ORB; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67175) + return OPCODE_ORBC; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67177) + return OPCODE_XORB; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67228 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67234 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 11) + return OPCODE_ABS; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67234 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 7) + return OPCODE_SRA; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67234 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 15) + return OPCODE_SRL; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67235 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 11) + return OPCODE_NEG; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33328) + return OPCODE_AE_L16M_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33329) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33330) + return OPCODE_AE_L16M_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33331) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33332) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33333) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33334) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33335) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33336) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33337) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33338) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33339) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33340) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33341) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33342) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33343) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33376 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33376 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33377 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33377 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33378 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33378 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33379 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33379 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33380 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33380 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33381 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33381 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33382 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33382 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33383 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33383 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33384 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33384 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33385 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33385 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33386 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33386 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33387 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33387 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33387 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33388 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33388 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33388 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33389 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33389 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33389 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33390 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33390 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33390 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33391 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33391 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33391 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33392 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33392 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33392 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33393 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33393 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33393 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33394 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33394 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33394 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33395 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33395 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33395 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33396 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33396 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33396 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33397 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33397 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33397 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33398 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33398 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33398 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33399 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33399 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33399 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33400 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33400 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33400 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33401 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33401 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33401 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33402 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33402 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33402 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33403 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33403 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33403 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33404 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33404 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33404 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33405 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33405 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33405 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33406 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33406 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33406 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33407 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33407 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33407 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33408) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33409) + return OPCODE_AE_L16_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33410) + return OPCODE_AE_L16_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33411) + return OPCODE_AE_L16_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33412) + return OPCODE_AE_L16_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33413) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33414) + return OPCODE_AE_L16_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33415) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33416) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33417) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33418) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33419) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33420) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33421) + return OPCODE_AE_L32M_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33422) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33423) + return OPCODE_AE_L32M_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33424) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33425) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33426) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33427) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33428) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33429) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33430) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33431) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33432) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33433) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33434) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33435) + return OPCODE_AE_L32_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33436) + return OPCODE_AE_L32_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33437) + return OPCODE_AE_L32_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33438) + return OPCODE_AE_L32_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33439) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33440) + return OPCODE_AE_L32_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33441) + return OPCODE_AE_L64_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33442) + return OPCODE_AE_L64_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33443) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33444) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33445) + return OPCODE_AE_L64_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33446) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33447) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33448) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33449) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33450) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33451) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33452) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33453) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33454) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33455) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33456) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33457) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33458) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33459) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33460) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33461) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33462) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33463) + return OPCODE_AE_L8_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33464) + return OPCODE_AE_L8_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33465) + return OPCODE_AE_L8_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33466) + return OPCODE_AE_L8_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33467) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33468) + return OPCODE_AE_L8_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33469) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33470) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33471) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33472) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33473) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33474) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33475) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33476) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33477) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33478) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33479) + return OPCODE_AE_S16X2M_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33480) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33481) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33482) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33483) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33484) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33485) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33486) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33487) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33488) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33489) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33490) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33491) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33492) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33493) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33494) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33495) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33496) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33497) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33498) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33499) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33500) + return OPCODE_AE_S32M_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33501) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33502) + return OPCODE_AE_S32M_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33503) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33504) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33505) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33506) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33507) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33508) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33509) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33510) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33511) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33512) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33513) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33514) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33515) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33516) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33517) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33518) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33519) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33520) + return OPCODE_AE_S32_H_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33521) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33522) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33523) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33524) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33525) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33526) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33527) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33528) + return OPCODE_AE_S64_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33529) + return OPCODE_AE_S64_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33530) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33531) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33532) + return OPCODE_AE_S64_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33533) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33534) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33535) + return OPCODE_AE_S8X8_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33536) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33537) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33538) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33539) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33540) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33541) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33542) + return OPCODE_AE_S8_0_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33543) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33544) + return OPCODE_SLLI; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33545) + return OPCODE_SRAI; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33608 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33608 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_MOVAD8; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33609 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33610 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33611 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33612 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33613 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33615 && + Field_fld_ae5_slot0_7_0_Slot_ae5_slot0_get (insn) == 48) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33616 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33616 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33616 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33616 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA8X8_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 9) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 13) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 10) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 14) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_RIP; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8387 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8387 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8387 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8387 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8388 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8388 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_L64_IP; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8388 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8388 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8389 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8389 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8389 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8389 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_S64_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8390 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8390 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_S64_IP; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8400 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8400 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 7) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4150) + return OPCODE_ADDI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4151) + return OPCODE_ADDMI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4152) + return OPCODE_AE_LBK_DB; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4153) + return OPCODE_AE_LBK_DB_IC; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4154) + return OPCODE_AE_LBK_DB_IP; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4155) + return OPCODE_L16SI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4156) + return OPCODE_L16UI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4157) + return OPCODE_L32I; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4158) + return OPCODE_L8UI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4159) + return OPCODE_S16I; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4160) + return OPCODE_S32I; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4161) + return OPCODE_S8I; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4162) + return OPCODE_AE_LBKI_DBI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4163) + return OPCODE_AE_LBKI_DBI_IC; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4164) + return OPCODE_AE_LBKI_DBI_IP; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4165) + return OPCODE_MOVI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_AE_LBI_DBI_IC; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_AE_LBI_DBI_IP; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LBI_DBI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LB_DB_IC; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LB_DB_IP; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LB_DB; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_get (insn) == 2 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_CALCRNG16; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_get (insn) == 3 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_CALCRNG32; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4201 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4201 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4201 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae5_slot0_29_17_Slot_ae5_slot0_get (insn) == 2074) + return OPCODE_EXTUI; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1034) + return OPCODE_J; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1035) + return OPCODE_CALL0; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 25) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 27) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 28) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 31) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 30) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 29) + return OPCODE_AE_S32RA64S_XC1; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 20) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 22) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 21) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 26) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 23) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 24) + return OPCODE_AE_S24RA64S_XC1; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_ADD32; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_ADD32S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 9) + return OPCODE_MOVT_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_MOVF_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_MOVEQZ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_MOVNEZ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_MOVGEZ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 7) + return OPCODE_MOVLTZ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_S16X4RA32S_IP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (insn) == 12) + return OPCODE_AE_PKSR32; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (insn) == 28) + return OPCODE_AE_PKSR24; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (insn) == 28) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (insn) == 12) + return OPCODE_AE_PKSR16; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_get (insn) == 101) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_AE_MOVDA16X2; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_get (insn) == 100) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_6_Slot_ae5_slot0_get (insn) == 24) + return OPCODE_AE_MOVI; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_CVTP24A16X2_LH; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_CVTP24A16X2_HL; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_CVTP24A16X2_HH; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_get (insn) == 102) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_OLE_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 2 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_OLT_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_OEQ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 3 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_UN_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 2 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_ULE_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 2 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_ULT_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 2 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_UEQ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1051 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1051 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_MOV; + if (Field_fld_ae5_slot0_29_19_Slot_ae5_slot0_get (insn) == 516) + return OPCODE_AE_SEL16I; + if (Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_get (insn) == 256) + return OPCODE_L32R; + if (Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_get (insn) == 257) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_BBSI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_BALL_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_BANY_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_BBC_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 7) + return OPCODE_BBS_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_BEQ_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 9) + return OPCODE_BGEU_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 10) + return OPCODE_BGE_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 11) + return OPCODE_BLTU_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 12) + return OPCODE_BLT_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 13) + return OPCODE_BNALL_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 14) + return OPCODE_BNE_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 15) + return OPCODE_BNONE_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get (insn) == 12) + return OPCODE_BEQZ_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get (insn) == 14) + return OPCODE_BGEZ_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get (insn) == 28) + return OPCODE_BLTZ_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get (insn) == 30) + return OPCODE_BNEZ_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_BEQI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_BGEI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_BLTI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 10) + return OPCODE_BNEI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_BGEUI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_BLTUI_W15; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605313 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_VLDL16C_IC1; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605321 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_VLES16C_IC1; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605329 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_CALLX0; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605345 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_JX; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605353 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_RET; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605369 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_SSA8B; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605377 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_SSA8L; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605385 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_SSL; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605393 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_SSR; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605401 && + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (insn) == 17) + return OPCODE_NOP; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605401 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae5_slot0_29_6_Slot_ae5_slot0_get (insn) == 4301276 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_MOVALIGN; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075222 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075222 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075222 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4POS_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075222 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4NEG_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075223 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075223 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075223 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24NEG_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075223 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4POS_PC2; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075254 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA24POS_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075254 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075254 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075254 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2NEG_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075255 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA24X2POS_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075255 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075255 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075255 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2NEG_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075286 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075286 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2POS_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075286 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2POS_PC2; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075286 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8NEG_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075287 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8POS_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075287 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8POS_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075287 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8NEG_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075287 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8POS_PC2; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075318 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_ALL4; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075318 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_ANY4; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075318 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075318 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075319 && + Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_SSAI; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075319 && + Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_ALL8; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075319 && + Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_ANY8; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075319 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_RUR_AE_BITPTR; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae8_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10761) + return OPCODE_ADD; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10765) + return OPCODE_ADDX2; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10769) + return OPCODE_ADDX4; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10773) + return OPCODE_ADDX8; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10777) + return OPCODE_AND; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10781) + return OPCODE_MAX; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10785) + return OPCODE_MAXU; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10789) + return OPCODE_MIN; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10793) + return OPCODE_MINU; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10797) + return OPCODE_MOVEQZ; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10801) + return OPCODE_MOVGEZ; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10805) + return OPCODE_MOVLTZ; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10809) + return OPCODE_MOVNEZ; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10813) + return OPCODE_OR; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10817) + return OPCODE_SALT; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10821) + return OPCODE_SALTU; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10825) + return OPCODE_SRC; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10829) + return OPCODE_SUB; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10833) + return OPCODE_SUBX2; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10837) + return OPCODE_SUBX4; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10841) + return OPCODE_SUBX8; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10845) + return OPCODE_XOR; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10849) + return OPCODE_MOVF; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10853) + return OPCODE_MOVT; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10857) + return OPCODE_CLAMPS; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10861) + return OPCODE_SEXT; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10865) + return OPCODE_SRLI; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10869) + return OPCODE_ANDB; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10873) + return OPCODE_ANDBC; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10877) + return OPCODE_ORB; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10881) + return OPCODE_ORBC; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10885) + return OPCODE_XORB; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10889 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10889 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10889 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10889 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10893 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (insn) == 1344 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_SLLI; + if (Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (insn) == 1360 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_ALL4; + if (Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (insn) == 1360 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_ANY4; + if (Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (insn) == 1360 && + Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_get (insn) == 102) + return OPCODE_ALL8; + if (Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (insn) == 1360 && + Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_get (insn) == 103) + return OPCODE_ANY8; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 94) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 95) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 96) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 97) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 98) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 99) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 100) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 101) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 102) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 103) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 104) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 105) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 106) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 107) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 108) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 109) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 110) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 111) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 112) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 113) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 114) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 115) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 116) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 117) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 118) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 119) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 120) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 121) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 122) + return OPCODE_AE_S16X4X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 123) + return OPCODE_AE_S16X4X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 124) + return OPCODE_AE_S16X4X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 125) + return OPCODE_AE_S16X4X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 126) + return OPCODE_AE_S16X4X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 127) + return OPCODE_AE_S16X4X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 128) + return OPCODE_AE_S16X4X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 129) + return OPCODE_AE_S32X2X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 130) + return OPCODE_AE_S32X2X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 131) + return OPCODE_AE_S32X2X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 132) + return OPCODE_AE_S32X2X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 133) + return OPCODE_AE_S32X2X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 134) + return OPCODE_AE_S32X2X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 135) + return OPCODE_AE_S32X2X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 136) + return OPCODE_AE_S64X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 137) + return OPCODE_AE_S64X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 138) + return OPCODE_AE_S64X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 139) + return OPCODE_AE_S64X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 140) + return OPCODE_AE_S64X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 141) + return OPCODE_AE_S64X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 142) + return OPCODE_AE_S64X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 143) + return OPCODE_AE_S8X8X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 144) + return OPCODE_AE_S8X8X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 145) + return OPCODE_AE_S8X8X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 146) + return OPCODE_AE_S8X8X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 147) + return OPCODE_AE_S8X8X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 148) + return OPCODE_AE_S8X8X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 149) + return OPCODE_AE_S8X8X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 150) + return OPCODE_J; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 151) + return OPCODE_CALL0; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 153 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 153 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 153 && + Field_fld_ae8_slot0_13_13_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 154 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_L16SI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 154 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_L32I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 154 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_S16I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 154 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_S8I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 155 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_L16UI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 155 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_L8UI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 155 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_MOVI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 155 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_S32I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 160 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 0 && + Field_fld_ae8_slot0_7_5_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_SRAI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L16M_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_L16_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 17) + return OPCODE_AE_L8_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_L32_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_L32_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_L32M_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_L64_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 20) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 26) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 21) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 19) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 18) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 29) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 27) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 28) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 23) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 30) + return OPCODE_AE_S64_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 24) + return OPCODE_AE_S32M_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 25) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 16) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 22) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 31) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_L16_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 17) + return OPCODE_AE_L8_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_L32_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 16) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_L64_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 20) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 25) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 21) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 22) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 18) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 19) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 29) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 28) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 27) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 23) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 30) + return OPCODE_AE_S64_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 31) + return OPCODE_AE_S64_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 24) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 26) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L16M_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_L16_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 17) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 16) + return OPCODE_AE_L8_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_L32_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_L32M_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_L64_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 20) + return OPCODE_AE_S16X2M_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 19) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 25) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 26) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 21) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 31) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 18) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 28) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 29) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 27) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 23) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 22) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 30) + return OPCODE_AE_S64_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 24) + return OPCODE_AE_S32M_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_L16_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_L16_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 16) + return OPCODE_AE_L8_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 17) + return OPCODE_AE_L8_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_L32_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_L64_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_L64_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 19) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 20) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 25) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 21) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 31) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 18) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 28) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 27) + return OPCODE_AE_S32_H_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 26) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 22) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 23) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 30) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 29) + return OPCODE_AE_S64_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 24) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 168 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 168 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 168 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_S8_0_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 168 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 169 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 169 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 169 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 169 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 40) + return OPCODE_AE_TRUNCA16X4F32S; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 41) + return OPCODE_AE_TRUNCA16X4F64S; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 42) + return OPCODE_AE_TRUNCA32F64S_L; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 43) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 44) + return OPCODE_AE_TRUNCI32F64S_L; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 45) + return OPCODE_AE_TRUNCI32X2F64S; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 46) + return OPCODE_AE_SEL16I; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_SAT16X4; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_ROUND16X4F32SSYM; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_ROUND16X4F32SASYM; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_SATU16X4; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_SAT8X4X32_L; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_SATU8X4X32_L; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 81 && + Field_fld_ae8_slot0_8_0_Slot_ae8_slot0_get (insn) == 128) + return OPCODE_AE_MOV; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_LAV16X4X2_XP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_LAV8X8X2_XP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 16) + return OPCODE_AE_SAV16X4X2_XP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 17) + return OPCODE_AE_SAV8X8X2_XP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 18) + return OPCODE_L32R; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 19) + return OPCODE_AE_TRUNCI16X4F32S; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_SA16X4X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_SA16X4X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_SA16X4X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_SA16X4X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_SA8X8X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_SA8X8X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_SA8X8X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_SA8X8X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 243) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 244) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 245) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 240) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 241) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 242) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 246) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 247) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 248) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_SA32X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_SA8X8_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_SA8X8_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_SA8X8_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_SA8X8_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_8_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae8_slot0_31_21_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_TRUNCI16X4F64S; + if (Field_fld_ae8_slot0_31_22_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae8_slot0_31_23_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae8_slot0_31_7_Slot_ae8_slot0_get (insn) == 348594 && + Field_fld_ae8_slot0_6_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174288 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_CALLX0; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174290 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_JX; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174291 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_RET; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174293 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_SSA8B; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174294 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_SSA8L; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174295 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_SSL; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174296 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_SSR; + if (Field_fld_ae8_slot0_31_9_Slot_ae8_slot0_get (insn) == 87107 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae8_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5386) + return OPCODE_AND; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5387) + return OPCODE_MINU; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5388) + return OPCODE_MOVNEZ; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5389) + return OPCODE_SRC; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5390) + return OPCODE_SUBX8; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5391) + return OPCODE_SRLI; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5450) + return OPCODE_MAX; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5451) + return OPCODE_MOVEQZ; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5452) + return OPCODE_OR; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5453) + return OPCODE_SUB; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5454) + return OPCODE_XOR; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5455 && + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5455 && + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5455 && + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5455 && + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5512) + return OPCODE_ADD; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5513) + return OPCODE_ADDX4; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5514) + return OPCODE_MAXU; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5515) + return OPCODE_MOVGEZ; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5516) + return OPCODE_SALT; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5517) + return OPCODE_SUBX2; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5518) + return OPCODE_CLAMPS; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5522 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SLL; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5576) + return OPCODE_ADDX2; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5577) + return OPCODE_ADDX8; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5578) + return OPCODE_MIN; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5579) + return OPCODE_MOVLTZ; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5580) + return OPCODE_SALTU; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5581) + return OPCODE_SUBX4; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5582) + return OPCODE_SEXT; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2450) + return OPCODE_AE_L16M_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2451) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2452) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2453) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2454) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2455) + return OPCODE_AE_L16_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2456) + return OPCODE_AE_L32M_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2457) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2458) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2459) + return OPCODE_AE_L32_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2460) + return OPCODE_AE_L32_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2461) + return OPCODE_AE_L64_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2462) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2463) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2482) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2483) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2484) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2485) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2486) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2487) + return OPCODE_AE_L16_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2488) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2489) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2490) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2491) + return OPCODE_AE_L32_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2492) + return OPCODE_AE_L64_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2493) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2494) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2495) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2514) + return OPCODE_AE_L16M_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2515) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2516) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2517) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2518) + return OPCODE_AE_L16_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2519) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2520) + return OPCODE_AE_L32M_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2521) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2522) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2523) + return OPCODE_AE_L32_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2524) + return OPCODE_AE_L64_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2525) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2526) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2527) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2546) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2547) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2548) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2549) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2550) + return OPCODE_AE_L16_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2551) + return OPCODE_AE_L16_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2552) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2553) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2554) + return OPCODE_AE_L32_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2555) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2556) + return OPCODE_AE_L64_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2557) + return OPCODE_AE_L64_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2558) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2559) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2688) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2689) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2690) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2691) + return OPCODE_AE_L8_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2692) + return OPCODE_SLLI; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2696 && + Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2697 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2720) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2721) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2722) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2723) + return OPCODE_AE_L8_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2724) + return OPCODE_SRAI; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2728 && + Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2729 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2752) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2753) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2754) + return OPCODE_AE_L8_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2755) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2760 && + Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2784) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2785) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2786) + return OPCODE_AE_L8_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2787) + return OPCODE_AE_L8_XP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 48) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 49) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 50) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 51) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 52) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 53) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 54) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 55) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 56) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 57) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 58) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 59) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 60) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 61) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 62) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 63) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 64) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 65) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 66) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 67) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 68) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 69) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 70) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 71) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 72) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 73) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 74) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 75) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_15_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 5) + return OPCODE_L16UI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 4) + return OPCODE_L16SI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 6) + return OPCODE_L32I; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 7) + return OPCODE_L8UI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 8) + return OPCODE_MOVI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 7) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 10) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 6) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 6) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 7) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 8) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 9) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 10) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 11) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 14) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 12) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 13) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 9) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 10) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 14) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 12) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 13) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 320) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 6) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 7) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae8_slot1_29_22_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae8_slot1_29_23_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae8_slot1_29_5_Slot_ae8_slot1_get (insn) == 715056 && + Field_fld_ae8_slot1_4_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_NOP; + if (Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get (insn) == 89378 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SSA8B; + if (Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get (insn) == 89379 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SSA8L; + if (Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get (insn) == 89380 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SSL; + if (Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get (insn) == 89381 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SSR; + if (Field_fld_ae8_slot1_29_9_Slot_ae8_slot1_get (insn) == 44688 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae9_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (insn) == 40364 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_ALL4; + if (Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (insn) == 40364 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_ANY4; + if (Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (insn) == 40365 && + Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_get (insn) == 18) + return OPCODE_SSAI; + if (Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (insn) == 40365 && + Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_ALL8; + if (Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (insn) == 40365 && + Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_ANY8; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10064) + return OPCODE_ADD; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10065) + return OPCODE_ADDX2; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10066) + return OPCODE_ADDX4; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10067) + return OPCODE_ADDX8; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10068) + return OPCODE_AND; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10069) + return OPCODE_MAX; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10070) + return OPCODE_MAXU; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10071) + return OPCODE_MIN; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10072) + return OPCODE_MINU; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10073) + return OPCODE_MOVEQZ; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10074) + return OPCODE_MOVGEZ; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10075) + return OPCODE_MOVLTZ; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10076) + return OPCODE_MOVNEZ; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10077) + return OPCODE_OR; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10078) + return OPCODE_SALT; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10079) + return OPCODE_SALTU; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10080) + return OPCODE_SRC; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10081) + return OPCODE_SUB; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10082) + return OPCODE_SUBX2; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10083) + return OPCODE_SUBX4; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10084) + return OPCODE_SUBX8; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10085) + return OPCODE_XOR; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10086) + return OPCODE_MOVF; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10087) + return OPCODE_MOVT; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10088) + return OPCODE_CLAMPS; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10089) + return OPCODE_SEXT; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10090) + return OPCODE_SRLI; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10091 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_SRA; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10091 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_SRL; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10112 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10694 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_ABS; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10695 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4864) + return OPCODE_AE_L16M_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4865) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4866) + return OPCODE_AE_L16M_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4867) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4868) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4869) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4870) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4871) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4872) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4873) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4874) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4875) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4876) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4877) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4878) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4879) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4880) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4881) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4882) + return OPCODE_AE_L16_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4883) + return OPCODE_AE_L16_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4884) + return OPCODE_AE_L16_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4885) + return OPCODE_AE_L16_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4886) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4887) + return OPCODE_AE_L16_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4888) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4889) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4890) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4891) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4892) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4893) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4894) + return OPCODE_AE_L32M_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4895) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4896) + return OPCODE_AE_L32M_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4897) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4898) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4899) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4900) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4901) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4902) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4903) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4904) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4905) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4906) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4907) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4908) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4909) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4910) + return OPCODE_AE_L32_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4911) + return OPCODE_AE_L32_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4912) + return OPCODE_AE_L32_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4913) + return OPCODE_AE_L32_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4914) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4915) + return OPCODE_AE_L32_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4916) + return OPCODE_AE_L64_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4917) + return OPCODE_AE_L64_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4918) + return OPCODE_AE_L64_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4919) + return OPCODE_AE_L64_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4920) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4921) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4922) + return OPCODE_AE_L64_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4923) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4924) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4925) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4926) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4927) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4928) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4929) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4930) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4931) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4932) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4933) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4934) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4935) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4936) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4937) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4938) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4939) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4940) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4941) + return OPCODE_AE_L8_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4942) + return OPCODE_AE_L8_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4943) + return OPCODE_AE_L8_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4944) + return OPCODE_AE_L8_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4945) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4946) + return OPCODE_AE_L8_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4947) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4948) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4949) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4950) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4951) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4952) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4953) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4954) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4955) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4956) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4957) + return OPCODE_AE_S16X2M_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4958) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4959) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4960) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4961) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4962) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4963) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4964) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4965) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4966) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4967) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4968) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4969) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4970) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4971) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4972) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4973) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4974) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4975) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4976) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4977) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4978) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4979) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4980) + return OPCODE_AE_S32M_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4981) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4982) + return OPCODE_AE_S32M_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4983) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4984) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4985) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4986) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4987) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4988) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4989) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4990) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4991) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4992) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4993) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4994) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4995) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4996) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4997) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4998) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4999) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5000) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5001) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5002) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5003) + return OPCODE_AE_S32_H_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5004) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5005) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5006) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5007) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5008) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5009) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5010) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5011) + return OPCODE_AE_S64_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5012) + return OPCODE_AE_S64_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5013) + return OPCODE_AE_S64_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5014) + return OPCODE_AE_S64_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5015) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5016) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5017) + return OPCODE_AE_S64_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5018) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5019) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5020) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5021) + return OPCODE_AE_S8X8_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5022) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5023) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5024) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5025) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5026) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5027) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5028) + return OPCODE_AE_S8_0_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5029) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5030) + return OPCODE_SLLI; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5031) + return OPCODE_SRAI; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5046 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5046 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5047 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5047 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5048 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5049 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5050 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5051 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5052 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5053 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5054 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5055 && + Field_fld_ae9_slot0_7_6_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5055 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5055 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5055 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5055 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5250 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5251 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5282 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5283 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5314 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5315 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5346 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 566) + return OPCODE_ADDI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 567) + return OPCODE_ADDMI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 568) + return OPCODE_L16SI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 569) + return OPCODE_L16UI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 570) + return OPCODE_L32I; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 571) + return OPCODE_L8UI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 572) + return OPCODE_S16I; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 573) + return OPCODE_S32I; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 574) + return OPCODE_S8I; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 575) + return OPCODE_MOVI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 632 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 632 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 632 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae9_slot0_27_17_Slot_ae9_slot0_get (insn) == 282) + return OPCODE_EXTUI; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 74) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 75) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 76) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 77) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 78) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 79) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 80) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 81) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 82) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 83) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 84) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 85) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 86) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 87) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 88) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 89) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 90) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 91) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 92) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 93) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 94) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 95) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 96) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 97) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 98) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 99) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 100) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 101) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 102) + return OPCODE_AE_S16X4X2RNG_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 103) + return OPCODE_AE_S16X4X2RNG_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 104) + return OPCODE_AE_S16X4X2RNG_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 105) + return OPCODE_AE_S16X4X2RNG_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 106) + return OPCODE_AE_S16X4X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 107) + return OPCODE_AE_S16X4X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 108) + return OPCODE_AE_S16X4X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 109) + return OPCODE_AE_S16X4X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 110) + return OPCODE_AE_S16X4X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 111) + return OPCODE_AE_S16X4X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 112) + return OPCODE_AE_S16X4X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 113) + return OPCODE_AE_S32X2X2RNG_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 114) + return OPCODE_AE_S32X2X2RNG_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 115) + return OPCODE_AE_S32X2X2RNG_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 116) + return OPCODE_AE_S32X2X2RNG_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 117) + return OPCODE_AE_S32X2X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 118) + return OPCODE_AE_S32X2X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 119) + return OPCODE_AE_S32X2X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 120) + return OPCODE_AE_S32X2X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 121) + return OPCODE_AE_S32X2X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 122) + return OPCODE_AE_S32X2X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 123) + return OPCODE_AE_S32X2X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 124) + return OPCODE_AE_S64X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 125) + return OPCODE_AE_S64X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 126) + return OPCODE_AE_S64X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 127) + return OPCODE_AE_S64X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 128) + return OPCODE_AE_S64X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 129) + return OPCODE_AE_S64X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 130) + return OPCODE_AE_S64X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 131) + return OPCODE_AE_S8X8X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 132) + return OPCODE_AE_S8X8X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 133) + return OPCODE_AE_S8X8X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 134) + return OPCODE_AE_S8X8X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 135) + return OPCODE_AE_S8X8X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 136) + return OPCODE_AE_S8X8X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 137) + return OPCODE_AE_S8X8X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 138) + return OPCODE_J; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 139) + return OPCODE_CALL0; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 148 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_get (insn) == 15) + return OPCODE_AE_LE32; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 148 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_get (insn) == 7) + return OPCODE_AE_EQ32; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 148 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_LT64; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 148 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_get (insn) == 5) + return OPCODE_AE_LE64; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 148 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_AE_EQ64; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_get (insn) == 23) + return OPCODE_AE_MOV; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_get (insn) == 7) + return OPCODE_AE_LT16; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_get (insn) == 30) + return OPCODE_AE_LE16; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_get (insn) == 14) + return OPCODE_AE_EQ16; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_LT32; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 183) + return OPCODE_CVTSF16_L; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 181) + return OPCODE_CVTSF16_H; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 179) + return OPCODE_CVTF16S_L; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 177) + return OPCODE_CVTF16S_H; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 8 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_OLE_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 9 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_OLT_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 8 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_OEQ_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 11 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_UN_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 10 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_ULE_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 10 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_ULT_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 9 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_UEQ_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 185) + return OPCODE_FICEIL_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 187) + return OPCODE_FIFLOOR_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 189) + return OPCODE_FIRINT_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 191) + return OPCODE_FIROUND_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_get (insn) == 87) + return OPCODE_RMINNUM_H; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_get (insn) == 55) + return OPCODE_RMAXNUM_H; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 160 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 8) + return OPCODE_FITRUNC_S; + if (Field_fld_ae9_slot0_27_19_Slot_ae9_slot0_get (insn) == 36) + return OPCODE_AE_SEL16I; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 12) + return OPCODE_AE_LAV16X4X2_XP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 13) + return OPCODE_AE_LAV8X8X2_XP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 14) + return OPCODE_AE_SAV16X4X2_XP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 15) + return OPCODE_AE_SAV8X8X2_XP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 16) + return OPCODE_L32R; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 17) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 11) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 7) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 10) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 15) + return OPCODE_AE_SA16X4X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 12) + return OPCODE_AE_SA16X4X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 13) + return OPCODE_AE_SA16X4X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 14) + return OPCODE_AE_SA16X4X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 7) + return OPCODE_AE_SA8X8X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_AE_SA8X8X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 5) + return OPCODE_AE_SA8X8X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_SA8X8X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 40 && + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get (insn) == 2 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 40 && + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get (insn) == 3 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 579) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 580) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 581) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 576) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 577) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 578) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 582) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 583) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 584) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_SALIGN128_I; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 585) + return OPCODE_AE_SA128POS_FP; + if (Field_fld_ae9_slot0_27_22_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_TRUNC_S; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get (insn) == 1 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_UTRUNC_S; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_TRUNC_SX2; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_UTRUNC_SX2; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_FLOAT_SX2; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_UFLOAT_SX2; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 6 && + Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_FLOAT_S; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 6 && + Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_UFLOAT_S; + if (Field_fld_ae9_slot0_27_3_Slot_ae9_slot0_get (insn) == 5178144 && + Field_fld_ae9_slot0_2_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_NOP; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161808 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_CALLX0; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161810 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_JX; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161811 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_RET; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161813 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_SSA8B; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161814 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_SSA8L; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161815 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_SSL; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161816 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_SSR; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae9_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5392) + return OPCODE_MAXU; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5393) + return OPCODE_MIN; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5394) + return OPCODE_SALT; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5395) + return OPCODE_SALTU; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5396) + return OPCODE_CLAMPS; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5397) + return OPCODE_SEXT; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5398 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 10) + return OPCODE_SLL; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5454) + return OPCODE_ADD; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5455) + return OPCODE_ADDX2; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5456) + return OPCODE_MINU; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5457) + return OPCODE_MOVEQZ; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5458) + return OPCODE_SRC; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5459) + return OPCODE_SUB; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5460) + return OPCODE_SRLI; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5461 && + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5461 && + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5461 && + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5461 && + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5518) + return OPCODE_ADDX4; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5519) + return OPCODE_ADDX8; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5520) + return OPCODE_MOVGEZ; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5521) + return OPCODE_MOVLTZ; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5522) + return OPCODE_SUBX2; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5523) + return OPCODE_SUBX4; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5582) + return OPCODE_AND; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5583) + return OPCODE_MAX; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5584) + return OPCODE_MOVNEZ; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5585) + return OPCODE_OR; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5586) + return OPCODE_SUBX8; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5587) + return OPCODE_XOR; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2456) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2457) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2458) + return OPCODE_AE_L32M_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2459) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2460) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2461) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2462) + return OPCODE_AE_L32_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2463) + return OPCODE_AE_L64_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2480) + return OPCODE_AE_L16M_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2481) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2482) + return OPCODE_AE_L16M_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2483) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2484) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2485) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2486) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2487) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2488) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2489) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2490) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2491) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2492) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2493) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2494) + return OPCODE_AE_L32_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2495) + return OPCODE_AE_L64_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2512) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2513) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2514) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2515) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2516) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2517) + return OPCODE_AE_L16_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2518) + return OPCODE_AE_L16_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2519) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2520) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2521) + return OPCODE_AE_L32M_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2522) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2523) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2524) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2525) + return OPCODE_AE_L32_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2526) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2527) + return OPCODE_AE_L64_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2544) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2545) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2546) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2547) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2548) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2549) + return OPCODE_AE_L16_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2550) + return OPCODE_AE_L16_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2551) + return OPCODE_AE_L16_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2552) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2553) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2554) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2555) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2556) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2557) + return OPCODE_AE_L32_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2558) + return OPCODE_AE_L32_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2559) + return OPCODE_AE_L64_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2688) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2689) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2690) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2691) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2692) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2693) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2694) + return OPCODE_AE_L8_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2695) + return OPCODE_SRAI; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2699 && + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2720) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2721) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2722) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2723) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2724) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2725) + return OPCODE_AE_L8_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2726) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2731 && + Field_fld_ae9_slot1_3_2_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2731 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 4) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2731 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 5) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2731 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 6) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2731 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 7) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2752) + return OPCODE_AE_L64_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2753) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2754) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2755) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2756) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2757) + return OPCODE_AE_L8_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2758) + return OPCODE_AE_L8_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2762 && + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2762 && + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2784) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2785) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2786) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2787) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2788) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2789) + return OPCODE_AE_L8_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2790) + return OPCODE_SLLI; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2794 && + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2794 && + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 306) + return OPCODE_MOVI; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 308) + return OPCODE_ADDI; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 309) + return OPCODE_ADDMI; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 312) + return OPCODE_L16SI; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 313) + return OPCODE_L32I; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 316) + return OPCODE_L16UI; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 317) + return OPCODE_L8UI; + if (Field_fld_ae9_slot1_26_17_Slot_ae9_slot1_get (insn) == 152) + return OPCODE_EXTUI; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 48) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 49) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 50) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 51) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 52) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 53) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 54) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 55) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 56) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 57) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 58) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 59) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 60) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 61) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 62) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 63) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 64) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 65) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 66) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 67) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 68) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 69) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 70) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 71) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 72) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 73) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 74) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 75) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae9_slot1_26_2_Slot_ae9_slot1_get (insn) == 5659202 && + Field_fld_ae9_slot1_1_0_Slot_ae9_slot1_get (insn) == 3) + return OPCODE_NOP; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 7) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 10) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 6) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 355 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 356 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 357 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 352 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 353 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 354 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 358 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 359 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 360 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 384) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_get (insn) == 11 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 8) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_get (insn) == 11 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 9) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae9_slot1_26_22_Slot_ae9_slot1_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae9_slot1_26_23_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get (insn) == 86377 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_SSL; + if (Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get (insn) == 87401 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_SSR; + if (Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get (insn) == 87402 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_SSA8B; + if (Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get (insn) == 87403 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_SSA8L; + if (Field_fld_ae9_slot1_26_9_Slot_ae9_slot1_get (insn) == 43189 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116372 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116373 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116380 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116381 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ALL4; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116381 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ANY4; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116381 && + Field_fld_ae_slot0_8_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_ALL8; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116381 && + Field_fld_ae_slot0_8_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_ANY8; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28835 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28835 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28835 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28835 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LB; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28837 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28839 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 48) + return OPCODE_RUR_FCR; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28839 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 112) + return OPCODE_RUR_FSR; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28839 && + Field_fld_ae_slot0_5_0_Slot_ae_slot0_get (insn) == 16) + return OPCODE_AE_MOVAB4; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28839 && + Field_fld_ae_slot0_4_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVAB2; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 29091 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_SRL; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 29091 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAB; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 29091 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVBA; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 29091 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LBI; + if (Field_fld_ae_slot0_28_14_Slot_ae_slot0_get (insn) == 10904 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_SSAI; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3612 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 56) + return OPCODE_SLL; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1080) + return OPCODE_CALLX0; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1208) + return OPCODE_JX; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1272) + return OPCODE_RET; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1400) + return OPCODE_SSA8B; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1464) + return OPCODE_SSA8L; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1528) + return OPCODE_SSL; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1592) + return OPCODE_SSR; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1656) + return OPCODE_AE_MOVASAR; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4871 && + Field_fld_ae_slot0_12_10_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4871 && + Field_fld_ae_slot0_12_10_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4871 && + Field_fld_ae_slot0_12_10_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4900 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_SUBX8; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4900 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AND; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4900 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ANDBC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4900 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_CLAMPS; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4900 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ADDX4; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SRLI; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ORBC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_MOVF; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MAXU; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_DB; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4908 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_XOR; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4908 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ORB; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4908 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MAX; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4908 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SEXT; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ADDX8; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_ANDB; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_XORB; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_MOVT; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MIN; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVSARA7X2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4910 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_MOVGEZ; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4910 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_MINU; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4911 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_MOVEQZ; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4911 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_MOVLTZ; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4942 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_MOVNEZ; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4942 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SRC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4943 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADD; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4943 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SUB; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4943 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_OR; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4974 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SUBX2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4974 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_SALT; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4975 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADDX2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4975 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SUBX4; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4975 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_SALTU; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_DPFM_B; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_DPFM_BF; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_DPFR_B; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_DPFR_BF; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA24X2POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA24X2NEG_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2NEG_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_DPFW_B; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_DPFW_BF; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA24POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA24NEG_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA16X4POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4NEG_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA8X8POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA8X8NEG_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA8X8NEG_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_DBI; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5380 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5388 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5412 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5420 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5444 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5476 && + Field_fld_ae_slot0_12_0_Slot_ae_slot0_get (insn) == 69) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5476 && + Field_fld_ae_slot0_12_6_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_MOVALIGN; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 1802 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 1806 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 1818 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 1822 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2106 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2110 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2362 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2366 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16M_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S8_0_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32M_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2450 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2450 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2450 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2450 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SRAI; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L64_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16M_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2471 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2471 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2471 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2471 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S64_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32M_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32M_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32M_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2496 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2618 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2622 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2712 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2712 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2712 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2712 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2716 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2716 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2716 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2716 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L8_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32_H_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2874 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2878 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L64_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L64_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S8X8_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S64_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S64_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3130 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3134 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3386 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3390 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3642 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3646 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3898 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3902 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L64_X; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_NEG32; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ABS32; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_NEG24S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ABS24S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_NEG32S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_ABS32S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_NEG16S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_ABS16S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ABS16; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_NEG64; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_ABS64; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_NEG64S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_ABS64S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_DIV64D32_H; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_ABS8; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ABS8S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_NEG8S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 192 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_EQ64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 193 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_CVTF16S_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 193 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_CVTF16S_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 194 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LE64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 195 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_CVTSF16_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 195 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_CVTSF16_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 196 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LT64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 197 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FICEIL_S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 197 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FIFLOOR_S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 199 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FIRINT_S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 199 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FIROUND_S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_MAX32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_MAX16; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADD64S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_ADD8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADD8S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_ROUND24X2F48SASYM; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_MIN32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MIN16; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MAX64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MIN64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MAX8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_MIN8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_MOVNEG32S_T; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 228 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0) + return OPCODE_J; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_ROUND32X2F64SASYM; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ROUND24X2F48SSYM; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SUB32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SUB16; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SUB24S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SUB32S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_SUB16S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SUB64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 230 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0) + return OPCODE_CALL0; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 230 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0) + return OPCODE_L32I; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 230 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1) + return OPCODE_L8UI; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 230 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0) + return OPCODE_S16I; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 230 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1) + return OPCODE_S32I; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SUB64S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SUB8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SUB8S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LE8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LT8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_EQ8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_RNG32X4; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FITRUNC_S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 273 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADD16; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 273 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADD16S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 275 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADD32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 275 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADD24S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 277 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADD32S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 277 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 279 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 279 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADD64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 280 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_9_Slot_ae_slot0_get (insn) == 9 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 1) + return OPCODE_TRUNC16_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 280 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_9_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 1) + return OPCODE_UTRUNC16_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_SLLI; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCA32Q48; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCA16P24S_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCA16P24S_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSA64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSAZ16_0; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_RFR; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 310 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 310 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_LOOPGTZ; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 310 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 8) + return OPCODE_LOOPNEZ; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32F24S_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32F24S_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 337 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 608 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 339 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0) + return OPCODE_S8I; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 370 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ADDI; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 370 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADDMI; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 374 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1) + return OPCODE_L16UI; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 374 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0) + return OPCODE_L16SI; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0) + return OPCODE_L32R; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_10_Slot_ae_slot0_get (insn) == 172 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_SA32X2_IC2; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IC2; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_IC2; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SA8X8_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_SA32X2F24_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_SA32X2F24_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_SA24_L_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_SA24_L_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SA24X2_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SA24X2_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 32) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 24) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_12_Slot_ae_slot0_get (insn) == 161 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 16) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_10_Slot_ae_slot0_get (insn) == 164 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SALIGN128_I; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 40) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 48) + return OPCODE_WFR; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 77 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVDA32X2; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 77 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 77 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 84 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 576 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 84 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 608 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SA128POS_FP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 85 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 608 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LT16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LE16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_EQ16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LT32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LE32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_EQ32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OLE_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OLT_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OEQ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UN_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ULE_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ULT_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UEQ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OEQ_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OLE_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OLT_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UEQ_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ULE_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ULT_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UN_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SEL16I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 52 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 52 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVT64; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVF64; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_13_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_AND; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_13_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_NAND; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_13_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_OR; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_13_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_XOR; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 53 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_BMAX32X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_BMIN32X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVADEXT_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVADEXT_L; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADDC32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADDC32U; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVT_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVF_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S32X2X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S32X2X2RNG_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2X2RNG_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S32X2X2RNG_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2X2RNG_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S16X4X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X4X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X4X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S16X4X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X4X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X4X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S16X4X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X4X2RNG_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S16X4X2RNG_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X4X2RNG_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S16X4X2RNG_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 32 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 33 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 33 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S32X2X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8X8X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S8X8X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X4RA32S_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8X2_IC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4X2_IC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2X2_IC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8X2_IC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4X2_IC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2X2_IC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8X2_IC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4X2_IC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2X2_IC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_BMAX16X4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_BMIN16X4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SUBC32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SUBC32U; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 36 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 37 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 37 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 0) + return OPCODE_MOVI; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S32X2X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S8X8X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8X8X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S24RA64S_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOV; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCQ32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_PKSR32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_PKSR16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_MOVEQZ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 12) + return OPCODE_MOVNEZ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_MOVGEZ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 8) + return OPCODE_MOVLTZ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 40 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 41 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 41 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16) + return OPCODE_EXTUI; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S32X2X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVBA1X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_19_8_Slot_ae_slot0_get (insn) == 1568 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVBA4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_18_8_Slot_ae_slot0_get (insn) == 544 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVBA2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 576 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVBD1X4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 512 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVBD1X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 44 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 45 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDW16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 45 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDW32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 46 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 46 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S64X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 48 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 49 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDW8; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 49 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDW8U; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 50 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S64X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 50 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 52 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 53 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SUBW16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 53 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SUBW32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 54 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 54 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S64X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 57 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SUBW8; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 57 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SUBW8U; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 58 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S8X8X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 58 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 60 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 61 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SAV8X8X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 61 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SAV16X4X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 62 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8X8X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 62 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S8X8X2_X; + if (Field_fld_ae_slot0_28_24_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVT8X16_H; + if (Field_fld_ae_slot0_28_24_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_MOVT8X16_L; + if (Field_fld_ae_slot0_28_24_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae_slot0_28_26_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVT16X8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 392 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 384 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 392 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 387 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 395 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 386 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 394 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 386 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 387 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 395 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 384 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 392 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 384 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LA24_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 384 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 392 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA24_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_LA24X2_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_LA24X2_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_TRUNCA32F64S_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRA64_32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 36 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 36 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_SRLI24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 36 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SRAI24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_SRLS24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SRAS24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAI16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAI16R; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 44 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_SRLI32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SRAI32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 44 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SRAI32R; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_SRLS32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SRAS32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAA32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLA32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI16S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAA16S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA16S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA16RS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI24S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 46 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAA32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA32RS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLASQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_SRLSQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SRASQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAAQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLAQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAAQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SLAI64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLI64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAI64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_SRLS64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SRAS64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAA64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLA64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAA64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLAISQ56S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLASSQ56S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAASQ56S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SLAI64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAA64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 386 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 394 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRAI8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRAI8R; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLI8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAI8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAI8S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAA8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLA8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAA8S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAA8RS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAA8S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLI16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAA16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRLA16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAI16SYM; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA16SYMS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 46 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SRAI32SYM; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA32SYMS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAV16RS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAV32RS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTI32X4F8_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTI32X4F8_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTI32X4F8S_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTI32X4F8S_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32X4F8_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_CVTA32X4F8_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTA32X4F8S_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTA32X4F8S_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTI32X4F8U_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTI32X4F8U_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTI32X4F8US_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTI32X4F8US_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTA32X4F8U_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTA32X4F8U_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32X4F8US_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_CVTA32X4F8US_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTI32X4F16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTI32X4F16S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTA32X4F16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTA32X4F16S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTI32X4F16U; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTI32X4F16US; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32X4F16U; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_CVTA32X4F16US; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTI16X4X2F8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTI16X4X2F8S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTA16X4X2F8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTA16X4X2F8S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTI16X4X2F8U; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_CVTI16X4X2F8US; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA16X4X2F8U; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_CVTA16X4X2F8US; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_MOVDEXT; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_NSA16X4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSAZ32X4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSA32X4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_TRUNCI16X4F32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCI16X4F64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_TRUNCA16X4F32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCA16X4F64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LAV8X8X2_XP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LAV16X4X2_XP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_TRUNC_S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_UTRUNC_S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_TRUNC_SX2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_UTRUNC_SX2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_17_Slot_ae_slot0_get (insn) == 96 && + Field_fld_ae_slot0_9_4_Slot_ae_slot0_get (insn) == 16) + return OPCODE_FLOAT_S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_17_Slot_ae_slot0_get (insn) == 96 && + Field_fld_ae_slot0_9_4_Slot_ae_slot0_get (insn) == 20) + return OPCODE_UFLOAT_S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FLOAT_SX2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_UFLOAT_SX2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_FICEIL_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_FIFLOOR_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_FIRINT_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_FIROUND_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_FITRUNC_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_17_Slot_ae_slot0_get (insn) == 96 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_3_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FLOAT16_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_17_Slot_ae_slot0_get (insn) == 96 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_3_Slot_ae_slot0_get (insn) == 8) + return OPCODE_UFLOAT16_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FLOAT16_HX4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UFLOAT16_HX4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_12_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_TRUNC16_HX4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UTRUNC16_HX4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_RMINNUM_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_RMAXNUM_H; + if (Field_fld_ae_slot0_28_4_Slot_ae_slot0_get (insn) == 11214853 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_NOP; + if (Field_fld_ae_slot0_28_8_Slot_ae_slot0_get (insn) == 697920 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_WUR_FCR; + if (Field_fld_ae_slot0_28_8_Slot_ae_slot0_get (insn) == 697952 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_WUR_FSR; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot1_25_1_Slot_ae_slot1_get (insn) == 10858630 && + Field_fld_ae_slot1_0_0_Slot_ae_slot1_get (insn) == 0) + return OPCODE_NOP; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5390) + return OPCODE_MAXU; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5391) + return OPCODE_MIN; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5392) + return OPCODE_SALT; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5393) + return OPCODE_SALTU; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5394) + return OPCODE_CLAMPS; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5395) + return OPCODE_SEXT; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5409 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5409 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5409 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5409 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SRL; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5409 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_LB; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5452) + return OPCODE_ADD; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5453) + return OPCODE_ADDX2; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5454) + return OPCODE_MINU; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5455) + return OPCODE_MOVEQZ; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5456) + return OPCODE_SRC; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5457) + return OPCODE_SUB; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5458) + return OPCODE_SRLI; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5459) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5516) + return OPCODE_ADDX4; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5517) + return OPCODE_ADDX8; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5518) + return OPCODE_MOVGEZ; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5519) + return OPCODE_MOVLTZ; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5520) + return OPCODE_SUBX2; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5521) + return OPCODE_SUBX4; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5526 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SLL; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5527 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5580) + return OPCODE_AND; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5581) + return OPCODE_MAX; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5582) + return OPCODE_MOVNEZ; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5583) + return OPCODE_OR; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5584) + return OPCODE_SUBX8; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5585) + return OPCODE_XOR; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5590 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_LBI; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2456) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2457) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2458) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2459) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2460) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2461) + return OPCODE_AE_L32_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2462) + return OPCODE_AE_L32_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2463) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2480) + return OPCODE_AE_L16M_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2481) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2482) + return OPCODE_AE_L16M_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2483) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2484) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2485) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2486) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2487) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2488) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2489) + return OPCODE_AE_L32M_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2490) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2491) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2492) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2493) + return OPCODE_AE_L32_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2494) + return OPCODE_AE_L64_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2495) + return OPCODE_AE_L64_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2512) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2513) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2514) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2515) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2516) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2517) + return OPCODE_AE_L16_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2518) + return OPCODE_AE_L16_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2519) + return OPCODE_AE_L16_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2520) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2521) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2522) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2523) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2524) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2525) + return OPCODE_AE_L32_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2526) + return OPCODE_AE_L64_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2527) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2544) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2545) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2546) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2547) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2548) + return OPCODE_AE_L16_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2549) + return OPCODE_AE_L16_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2550) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2551) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2552) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2553) + return OPCODE_AE_L32M_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2554) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2555) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2556) + return OPCODE_AE_L32_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2557) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2558) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2559) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2688) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2689) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2690) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2691) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2692) + return OPCODE_AE_L8_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2693) + return OPCODE_AE_L8_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2694) + return OPCODE_SRAI; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2698 && + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2699 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2699 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2699 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2720) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2721) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2722) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2723) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2724) + return OPCODE_AE_L8_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2725) + return OPCODE_AE_MOVDA32X2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2730 && + Field_fld_ae_slot1_3_2_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2730 && + Field_fld_ae_slot1_3_2_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2731 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2731 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2731 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2752) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2753) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2754) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2755) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2756) + return OPCODE_AE_L8_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2757) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2761 && + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2761 && + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2763 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2763 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2784) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2785) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2786) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2787) + return OPCODE_AE_L8_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2788) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2789) + return OPCODE_SLLI; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2793 && + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2793 && + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2795 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2795 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 306) + return OPCODE_MOVI; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 308) + return OPCODE_ADDI; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 309) + return OPCODE_ADDMI; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 312) + return OPCODE_L16SI; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 313) + return OPCODE_L32I; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 316) + return OPCODE_L16UI; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 317) + return OPCODE_L8UI; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 152) + return OPCODE_EXTUI; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 160 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 13) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 160 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 14) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 160 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 160 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 15) + return OPCODE_AE_L64_I; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 162 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 13) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 162 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_L64_IP; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 169 && + Field_fld_ae_slot1_12_8_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 48) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 49) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 50) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 51) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 52) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 53) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 54) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 55) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 56) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 57) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 58) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 59) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 60) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 61) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 62) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 63) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 64) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 65) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 66) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 67) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 68) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 69) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 70) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 71) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 72) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 73) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 74) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 75) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 737 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 641 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 673 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 705 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 545 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 577 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 609 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 769 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 801 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 833 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_17_Slot_ae_slot1_get (insn) == 1 && + Field_fld_ae_slot1_12_8_Slot_ae_slot1_get (insn) == 0 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 513 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA128_PP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 7) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 10) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 13) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 8) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 9) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 11 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 11 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 10) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 11) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 14) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 15) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae_slot1_25_22_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae_slot1_25_23_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 82785 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_SSL; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 83809 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_SSR; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 86576) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 86577) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 86578) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 86579) + return OPCODE_AE_MOVSARA7X2; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 89458 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SSA8B; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 89459 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SSA8L; + if (Field_fld_ae_slot1_25_9_Slot_ae_slot1_get (insn) == 44728 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_get (insn) == 2560) + return OPCODE_OR; + if (Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_get (insn) == 2561) + return OPCODE_XOR; + if (Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_get (insn) == 2562) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 288 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 289 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16_I; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 290 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 291 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16_X; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 292 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16_XC; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 293 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16_XP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 294 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 295 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 296 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 297 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32_I; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 298 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 299 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32_X; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 300 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32_XC; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 301 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32_XP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 302 && + Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_get (insn) == 7) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 302 && + Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_get (insn) == 6) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 303 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 12) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 303 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 13) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 303 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 14) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 303 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 15) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 321 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 321 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 321 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 321 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 321 && + Field_fld_ae6_slot1_9_5_Slot_ae6_slot1_get (insn) == 8) + return OPCODE_AE_MOV; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 2) + return OPCODE_AE_TRUNCI16X4F32S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 4 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_CVTA16X4X2F8; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 4 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_CVTA16X4X2F8S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 5 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_CVTI16X4X2F8; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 5 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_CVTA16X4X2F8U; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 6 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_CVTI16X4X2F8S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 6 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_CVTI16X4X2F8U; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 7 && + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_TRUNCA16X4F32S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 7 && + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_TRUNCA16X4F64S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 8 && + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 8 && + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_TRUNCI32X2F64S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 9 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 9 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 9 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 2) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae6_slot1_27_21_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_TRUNCI16X4F64S; + if (Field_fld_ae6_slot1_27_3_Slot_ae6_slot1_get (insn) == 1315112 && + Field_fld_ae6_slot1_2_0_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_NOP; + if (Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_get (insn) == 164357) + return OPCODE_AE_LA128_PP; + if (Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_get (insn) == 164373) + return OPCODE_AE_LA64_PP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae10_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae10_slot2_34_10_Slot_ae10_slot2_get (insn) == 28442624 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 101) + return OPCODE_NOP; + if (Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get (insn) == 1968640) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get (insn) == 1968641) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get (insn) == 1968642 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 17) + return OPCODE_CONST_S; + if (Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get (insn) == 1968642 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 16) + return OPCODE_CONST_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 15) + return OPCODE_AE_MOV; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 8) + return OPCODE_NEXP01_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 4) + return OPCODE_MKSADJ_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_DIV0_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 11) + return OPCODE_SQRT0_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 9) + return OPCODE_RECIP0_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 10) + return OPCODE_RSQRT0_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_ABS_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 7) + return OPCODE_NEG_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_CONJC_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 6) + return OPCODE_MULJC_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 12) + return OPCODE_ABS_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 13) + return OPCODE_CLSFY_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_CONJC_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 5) + return OPCODE_MULJC_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 14) + return OPCODE_NEG_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984322 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_CLSFY_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984322 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24640 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MAX_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24640 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MAXNUM_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24641 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MIN_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24641 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MINNUM_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24704 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_FREXP_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24704 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 25728 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MAX_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 25728 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MAXNUM_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 26752 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_DIVN_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 26752 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MINNUM_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 26752 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MADDN_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 98) + return OPCODE_MKDADJ_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 97) + return OPCODE_ADDEXP_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 96) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MIN_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 100) + return OPCODE_ADDEXP_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 99) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 28800 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MADD_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 29824 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MSUBN_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30752) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30753) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30754) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30755) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30756) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30757) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30758) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30759) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30848 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MSUB_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 31872 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MUL_S; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_ADD_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 161) + return OPCODE_SUB_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 129) + return OPCODE_MUL_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 33) + return OPCODE_MADD_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 97) + return OPCODE_MSUB_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 65) + return OPCODE_MSUBN_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 833) + return OPCODE_MADDQ_S; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 865) + return OPCODE_MSUBQ_S; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 897) + return OPCODE_MULQ_S; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 929) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 993 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_MADDA_S; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 10) + return OPCODE_MADD_SX2X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 11) + return OPCODE_MSUB_SX2X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 12) + return OPCODE_MUL_SX2X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 13) + return OPCODE_ADD_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 14) + return OPCODE_MADD_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 15) + return OPCODE_MSUB_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 16) + return OPCODE_MUL_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 17) + return OPCODE_SUB_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 18) + return OPCODE_ADD_SX2X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 19) + return OPCODE_SUB_SX2X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 5) + return OPCODE_MULQ_H; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_MADDQ_H; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MULCNVH_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MULACNVH_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 4) + return OPCODE_MULCNVL_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MULACNVL_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 21 && + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (insn) == 0 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 34) + return OPCODE_ADD_S; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 21 && + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (insn) == 0 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 66) + return OPCODE_SUB_S; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 21 && + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (insn) == 0 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 21 && + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (insn) == 0 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 21 && + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (insn) == 0 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_get (insn) == 4) + return OPCODE_MULMUX_SX2X2; + if (Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_get (insn) == 12 && + Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_get (insn) == 128 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MULMUX_S; + if (Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_get (insn) == 12 && + Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MULMUXQ_S; + if (Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_MADDMUX_SX2X2; + if (Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_get (insn) == 3 && + Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_get (insn) == 128 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_get (insn) == 3 && + Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_MADDMUXQ_S; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae10_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae10_slot3_34_10_Slot_ae10_slot3_get (insn) == 23102864 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 18) + return OPCODE_NOP; + if (Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get (insn) == 1443864) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get (insn) == 1443865) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get (insn) == 1443928 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 19) + return OPCODE_CONST_S; + if (Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get (insn) == 1443928 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 18) + return OPCODE_CONST_H; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 17) + return OPCODE_AE_MOV; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 4) + return OPCODE_NEXP01_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 3) + return OPCODE_MKSADJ_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_DIV0_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 7) + return OPCODE_SQRT0_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 5) + return OPCODE_RECIP0_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 6) + return OPCODE_RSQRT0_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 8) + return OPCODE_ABS_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 13) + return OPCODE_NEG_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 10) + return OPCODE_CONJC_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 12) + return OPCODE_MULJC_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_CLSFY_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 2) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 14) + return OPCODE_ABS_H; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 15) + return OPCODE_CLSFY_H; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 9) + return OPCODE_CONJC_H; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 11) + return OPCODE_MULJC_H; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 16) + return OPCODE_NEG_H; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 18496 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_DIVN_S; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 19520 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MADDN_S; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 20544 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MADD_S; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 21568 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MSUBN_S; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 22592 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MSUB_S; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 23616 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MUL_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 577) + return OPCODE_MADDQ_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 609) + return OPCODE_MSUBQ_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 641) + return OPCODE_MULQ_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 673) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_4_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_AE_SEL16I; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 27) + return OPCODE_MIN_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 25) + return OPCODE_MAX_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 26) + return OPCODE_MINNUM_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 25) + return OPCODE_MAXNUM_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 9) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 8) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 24) + return OPCODE_FREXP_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 26) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 24) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_BMAXNUM_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get (insn) == 2) + return OPCODE_BMINNUM_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_BMAXNUMABS_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get (insn) == 2) + return OPCODE_BMINNUMABS_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 7) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 3) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 5) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 29) + return OPCODE_MIN_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 28) + return OPCODE_MAX_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 28) + return OPCODE_MINNUM_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 27) + return OPCODE_MAXNUM_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 6) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 2) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 4) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 5) + return OPCODE_ADD_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 6) + return OPCODE_SUB_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 226) + return OPCODE_MKDADJ_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 225) + return OPCODE_ADDEXP_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 224) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 4) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_MADDA_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 228) + return OPCODE_ADDEXP_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 227) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 64) + return OPCODE_ADD_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 98) + return OPCODE_SUB_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 66) + return OPCODE_MUL_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 96) + return OPCODE_MADD_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 97) + return OPCODE_MSUB_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 65) + return OPCODE_MSUBN_H; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 10) + return OPCODE_MADD_SX2X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 11) + return OPCODE_MSUB_SX2X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 12) + return OPCODE_MUL_SX2X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 13) + return OPCODE_MADD_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 14) + return OPCODE_MSUB_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 15) + return OPCODE_MUL_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 5) + return OPCODE_MULQ_H; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_MADDQ_H; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 3) + return OPCODE_MULCNVH_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MULACNVH_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 4) + return OPCODE_MULCNVL_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 2) + return OPCODE_MULACNVL_HX4X2; + if (Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_get (insn) == 4) + return OPCODE_MULMUX_SX2X2; + if (Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_get (insn) == 8 && + Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_get (insn) == 64 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MULMUX_S; + if (Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_get (insn) == 8 && + Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MULMUXQ_S; + if (Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_MADDMUX_SX2X2; + if (Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_get (insn) == 2 && + Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_get (insn) == 64 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_get (insn) == 2 && + Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_MADDMUXQ_S; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae2_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12292 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_ADD_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12420 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_DIVN_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12548 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MADDN_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12676 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MADD_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12684 && + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_PKSR24; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12684 && + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get (insn) == 0 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_PKSR16; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12685 && + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get (insn) == 0 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_PKSR32; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12685 && + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 131) + return OPCODE_AE_RADD8X8_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 227) + return OPCODE_AE_RADDA8X8_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 163) + return OPCODE_AE_RADD8X8_L; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 99) + return OPCODE_AE_RADD16X4; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 195) + return OPCODE_AE_RADDA16X4; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 67) + return OPCODE_MKDADJ_S; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 35) + return OPCODE_ADDEXP_S; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_0_Slot_ae2_slot2_get (insn) == 232448) + return OPCODE_NOP; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 67) + return OPCODE_AE_RMAX8X8; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 131) + return OPCODE_AE_RMIN8X8; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 35) + return OPCODE_AE_RMAX16X4; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 99) + return OPCODE_AE_RMIN16X4; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_RADDA8X8_L; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 195) + return OPCODE_ADDEXP_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 163) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12804 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MSUB_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12932 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MUL_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 13060 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_SUB_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3072) + return OPCODE_AE_MULAFC32RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3074 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3074 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP16S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3074 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAA2D16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3075 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3075 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3075 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MSUBN_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3104) + return OPCODE_AE_MULFC32RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3106 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3106 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3106 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3107 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3107 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3107 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MSUB_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3136) + return OPCODE_MADDA_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3138 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3138 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3138 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP16X16X4S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3139 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3139 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3139 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MUL_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULA32U_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 27) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 26) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 25) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 30) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 23) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 31) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 24) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 22) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 20) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 21) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 19) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 16) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULA32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 17) + return OPCODE_AE_MULAAD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 18) + return OPCODE_AE_MULAAD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULAA2D16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULAA2D16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 28) + return OPCODE_AE_MULAAFD16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 29) + return OPCODE_AE_MULAAFD16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3170 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3170 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3170 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3171 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFC16RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3171 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 18) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULF32RA_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32RA_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 22) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 17) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 29) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 23) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 28) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 21) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 27) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 20) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 24) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 16) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULFP32X2TS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULC32X16_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULC16S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 19) + return OPCODE_AE_MULS32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULFCJ32RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3202 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3202 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3202 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3203 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3203 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULC16JS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 18) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULF32RA_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 22) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 24) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 17) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 29) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 23) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 28) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 21) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 27) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 20) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 16) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULC16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 19) + return OPCODE_AE_MULS32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULASD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULCJ32; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULP16S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULFP16X4RS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3234 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3234 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3234 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3235 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3235 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULC16JS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 24) + return OPCODE_AE_MULSF32RA_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 19) + return OPCODE_AE_MULS32U_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 17) + return OPCODE_AE_MULS16S_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 29) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 23) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 28) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 21) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 27) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 20) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 16) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULC32; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULFC16RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 18) + return OPCODE_AE_MULS32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 22) + return OPCODE_AE_MULSAD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULASD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3266 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC16JS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3266 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3266 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP32X2T; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3267 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3267 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 17) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULF32RA_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 24) + return OPCODE_AE_MULSF32RA_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 21) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 28) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 27) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 20) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 19) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 23) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 29) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 16) + return OPCODE_AE_MULP32X2T; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X2TS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULC32X16_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 18) + return OPCODE_AE_MULS32S_HL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 22) + return OPCODE_AE_MULSAD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULFCJ16RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULC16S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULP16X16X4S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3298 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC16JS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3298 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3298 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3299 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3299 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3330 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3330 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3330 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC16S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3331 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3331 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFCJ16RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3362 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3362 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC16S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3362 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSS2D16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3363 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3363 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFCJ32RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3394 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3394 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3394 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSS2D16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3395 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL16S_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3395 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3395 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSS2D16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3426 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3426 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3426 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC32; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3427 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3427 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3427 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSS2D16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3458 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3458 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3458 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC32X16_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3459 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3459 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3459 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3490 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3490 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC32X16_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3490 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3491 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3491 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32S_HL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3491 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3522 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3522 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULACJ32; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3522 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3523 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3523 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3523 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3554 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3554 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3554 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3555 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3555 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3555 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3586 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32RA_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3586 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3586 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3587 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32U_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3587 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3587 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3618 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32RA_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3618 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3618 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3619 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3619 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3619 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3650 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32RA_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3650 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3650 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3651 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3651 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3651 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3682 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3682 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3682 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3683 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3683 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3683 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3714 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3714 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3714 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3715 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3715 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3715 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X2TS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3746 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3746 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3746 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3747 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3747 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP16S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3747 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3778 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3778 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3778 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3779 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3779 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3779 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3810 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3810 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3810 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3811 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3811 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3811 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP16X16X4S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3842 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3842 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3842 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3843 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3843 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3843 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3874 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3874 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3874 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3875 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3875 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3875 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3906 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3906 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3906 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3907 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3907 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3907 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3938 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3938 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3938 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3939 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3939 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3939 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP32X2T; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3970 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3970 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3970 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3971 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA16S_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3971 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3971 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4002 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4002 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4002 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4003 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4003 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4003 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_DIVN_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4034 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4034 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4034 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4035 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4035 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4035 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_MADDN_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4066 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4066 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4066 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZAA2D16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4067 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4067 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA32S_HL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4067 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_MADD_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 64 && + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_BMAXNUMABS_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 65 && + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_BMAXNUM_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 66 && + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_BMINNUMABS_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 67 && + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_BMINNUM_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 68 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 320) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 68 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 256) + return OPCODE_FREXP_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 68 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 288) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 69 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 320) + return OPCODE_ADD_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 69 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 288) + return OPCODE_MINNUM_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 69 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 256) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 70 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 320) + return OPCODE_SUB_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 70 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 288) + return OPCODE_MIN_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 70 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 256) + return OPCODE_MAXNUM_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 71 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 288) + return OPCODE_AE_SORT16X4; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 71 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 256) + return OPCODE_MAX_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 71 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 320 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_CLSFY_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 71 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 320 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae2_slot2_42_26_Slot_ae2_slot2_get (insn) == 52 && + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_MULMUX_S; + if (Field_fld_ae2_slot2_42_28_Slot_ae2_slot2_get (insn) == 12 && + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_ADD_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_SUB_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_get (insn) == 67745) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 15430 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MOV; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_get (insn) == 67744) + return OPCODE_AE_ABS16S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_DSEL8X8; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 2118 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_NEXP01_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 1094 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_MKSADJ_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 70 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_DIV0_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 5190 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_SQRT0_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 3142 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_RECIP0_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 4166 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_RSQRT0_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 6214 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_ABS_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 11334 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_NEG_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 8262 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_CONJC_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 10310 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_MULJC_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_get (insn) == 32909 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_CONST_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 100) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 68) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 96) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 99) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 97) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 98) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_get (insn) == 141 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 12358 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_ABS_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 13382 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_CLSFY_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 7238 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_CONJC_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_get (insn) == 32908 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_CONST_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 1125) + return OPCODE_MIN_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 101) + return OPCODE_MAX_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 1093) + return OPCODE_MINNUM_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 69) + return OPCODE_MAXNUM_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 9286 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_MULJC_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 14406 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_NEG_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 64) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 67) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 65) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_get (insn) == 140 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 66) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MIN32; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MAX32; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MIN16; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MAX16; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MAX8; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MIN8; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 33) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 32) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_SEL8X8I; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot2_23_0_Slot_ae4_slot2_get (insn) == 5668865) + return OPCODE_NOP; + if (Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get (insn) == 1368) + return OPCODE_AE_PKSR16; + if (Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get (insn) == 1369) + return OPCODE_AE_PKSR24; + if (Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get (insn) == 1370) + return OPCODE_AE_PKSR32; + if (Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get (insn) == 1371) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 164) + return OPCODE_AE_MAX16; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 165) + return OPCODE_AE_MAX32; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 166) + return OPCODE_AE_MAX8; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 167) + return OPCODE_AE_MIN16; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 168) + return OPCODE_AE_MIN32; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 169) + return OPCODE_AE_MIN8; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 170) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 172 && + Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_get (insn) == 1) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 172 && + Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_get (insn) == 0) + return OPCODE_AE_ABS16S; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 173 && + Field_fld_ae4_slot2_4_0_Slot_ae4_slot2_get (insn) == 0) + return OPCODE_AE_MOV; + if (Field_fld_ae4_slot2_23_17_Slot_ae4_slot2_get (insn) == 40) + return OPCODE_AE_SEL16I_N; + if (Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (insn) == 1) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (insn) == 2) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (insn) == 3) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (insn) == 4) + return OPCODE_AE_ADDANDSUBRNG32_L; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot3_27_20_Slot_ae4_slot3_get (insn) == 96 && + Field_fld_ae4_slot3_14_10_Slot_ae4_slot3_get (insn) == 0) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 0) + return OPCODE_AE_MULFPC32X16X2RAS; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 1) + return OPCODE_AE_MULFPCJ32X16X2RAS; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 22 && + Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_get (insn) == 161) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 1) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 2) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 3) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 4) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_19_Slot_ae4_slot3_get (insn) == 0 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_SEL16I; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_5_Slot_ae4_slot3_get (insn) == 23557) + return OPCODE_AE_MOV; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 22 && + Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_get (insn) == 160) + return OPCODE_AE_ABS16S; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 20 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MIN32; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 17 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MAX32; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 19 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MIN16; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 16 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MAX16; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 18 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MAX8; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 21 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MIN8; + if (Field_fld_ae4_slot3_27_3_Slot_ae4_slot3_get (insn) == 8482964 && + Field_fld_ae4_slot3_2_0_Slot_ae4_slot3_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot4_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot4_22_0_Slot_ae4_slot4_get (insn) == 5308480) + return OPCODE_NOP; + if (Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get (insn) == 160) + return OPCODE_AE_MAX16; + if (Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get (insn) == 161) + return OPCODE_AE_MIN16; + if (Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get (insn) == 162 && + Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_get (insn) == 1) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get (insn) == 162 && + Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_get (insn) == 0) + return OPCODE_AE_ABS16S; + if (Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (insn) == 1) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (insn) == 2) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (insn) == 3) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (insn) == 4) + return OPCODE_AE_ADDANDSUBRNG32_L; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae5_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae5_slot1_1_0_Slot_ae5_slot1_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae5_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae5_slot2_24_0_Slot_ae5_slot2_get (insn) == 24117778) + return OPCODE_NOP; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 752 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 753 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_ADDEXP_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 754 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_MKDADJ_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 755 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 756 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_ADDEXP_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 768) + return OPCODE_FREXP_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 769) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 770) + return OPCODE_MAXNUM_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 771) + return OPCODE_MAX_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 772) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 773) + return OPCODE_MINNUM_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 774) + return OPCODE_MIN_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 775) + return OPCODE_ADD_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 776) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 777) + return OPCODE_ADD_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 778) + return OPCODE_MADD_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 779) + return OPCODE_MSUB_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 780) + return OPCODE_MUL_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 781) + return OPCODE_SUB_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 782) + return OPCODE_SUB_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 783 && + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_CLSFY_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 783 && + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get (insn) == 184 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_PKSR16; + if (Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get (insn) == 185 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_PKSR24; + if (Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get (insn) == 186 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_PKSR32; + if (Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get (insn) == 187 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MUL16X4; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MUL16X4S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULAFC32RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULFC32RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_SEL8X8I; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_7_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_SEL16I_N; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MUL32U_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULA32U_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MUL16S_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULA16S_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MUL32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULA32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MUL32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULA32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MUL32S_HL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULA32S_HL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MUL32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULA32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULAAD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULAAD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULAA2D16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULAA2D16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULAAFD16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULAAFD16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULAC32; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULAC32X16_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULAC32X16_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULAFCJ32RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULACJ32; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULAFCJ16RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULAC16S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULAFP32X2TS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULAP32X2T; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULASD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULASD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULAP16S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULAP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULC16S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULAP16X16X4S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULFP16X4S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULC32; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULC32X16_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULC32X16_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULFCJ32RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULCJ32; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULFCJ16RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULFP16X4RS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULS32U_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULS16S_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULFP32X2TS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULP32X2T; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULS32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULS32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULS32S_HL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULS32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULP16S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULP16X16X4S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULSAD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULSAD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULSFP32X2TS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULSP32X2T; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULSSD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULSSD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULSP16S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULSP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULSP16X16X4S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULSS2D16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULSS2D16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULSSFD16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULZAAD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULZASD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULZAAD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULZAA2D16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULZAA2D16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULZAAFD16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULZAAFD16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULSSFD16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULZSAD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULZSSD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULZASD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULZSAD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULZSSD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULZSS2D16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULZSS2D16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULZSSFD16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULZSSFD16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_14_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 527) + return OPCODE_AE_MOV; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_MUL_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_MADD_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_MSUB_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_MSUBN_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_MADDN_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 514) + return OPCODE_NEXP01_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 513) + return OPCODE_MKSADJ_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 512) + return OPCODE_DIV0_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 517) + return OPCODE_SQRT0_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 515) + return OPCODE_RECIP0_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 516) + return OPCODE_RSQRT0_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_DIVN_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 518) + return OPCODE_ABS_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 523) + return OPCODE_NEG_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 520) + return OPCODE_CONJC_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 522) + return OPCODE_MULJC_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get (insn) == 0 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 529) + return OPCODE_CONST_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 524) + return OPCODE_ABS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 525) + return OPCODE_CLSFY_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 519) + return OPCODE_CONJC_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get (insn) == 0 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 528) + return OPCODE_CONST_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_MIN_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_MAX_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_MINNUM_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_MAXNUM_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 521) + return OPCODE_MULJC_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 526) + return OPCODE_NEG_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 25 && + Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 25 && + Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 25 && + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get (insn) == 1 && + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 25 && + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get (insn) == 1 && + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_CONST_HX4X2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19688) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19689) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19690) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19691) + return OPCODE_AE_MOV; + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19692) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19693) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2452) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2453) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2454 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2454 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2455 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_PKSR24; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2455 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_PKSR16; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2460 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_PKSR32; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2460 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_get (insn) == 1224) + return OPCODE_AE_MOVF64; + if (Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_get (insn) == 1225) + return OPCODE_AE_MOVT64; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 608 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_LE64; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 608 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_EQ64; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 609 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 609 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 609 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 609 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 610 && + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (insn) == 1 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 610 && + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 610 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_LT64; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 611 && + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 611 && + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 611 && + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (insn) == 1 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 611 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 3 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 611 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 2 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 614 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 2) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 614 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 3) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 614 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 614 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 624 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 624 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 2 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 624 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 1 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 60) + return OPCODE_AE_ADDC32; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 61) + return OPCODE_AE_ADDC32U; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 62) + return OPCODE_AE_BMAX32X2; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 63) + return OPCODE_AE_BMIN32X2; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 64) + return OPCODE_AE_SUBC32; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 65) + return OPCODE_AE_SUBC32U; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 66) + return OPCODE_AE_S16X4X2_I; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 67) + return OPCODE_AE_S16X4X2_IP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 68) + return OPCODE_AE_S16X4X2_X; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 69) + return OPCODE_AE_S16X4X2_XP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 70) + return OPCODE_AE_S32X2X2_I; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 71) + return OPCODE_AE_S32X2X2_IP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 72) + return OPCODE_AE_S32X2X2_X; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 73) + return OPCODE_AE_S32X2X2_XP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 74 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_BMAX8X8_L; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 74 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_BMAX16X4; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 75 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_BMIN8X8_L; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 75 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_BMIN16X4; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_7_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_L_IP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 20) + return OPCODE_AE_LT16; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 1 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 19) + return OPCODE_AE_LE16; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 19) + return OPCODE_AE_EQ16; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 18) + return OPCODE_AE_LT32; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 17) + return OPCODE_AE_LE32; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 16) + return OPCODE_AE_EQ32; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 2) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 3) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 4) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 5) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 6) + return OPCODE_AE_ADDW16; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 7) + return OPCODE_AE_ADDW32; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 8) + return OPCODE_AE_ADDW8; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 9) + return OPCODE_AE_ADDW8U; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 10) + return OPCODE_AE_SUBW16; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 11) + return OPCODE_AE_SUBW32; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 12) + return OPCODE_AE_SUBW8; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 13) + return OPCODE_AE_SUBW8U; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 14) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae6_slot0_29_5_Slot_ae6_slot0_get (insn) == 630208 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot2_24_0_Slot_ae6_slot2_get (insn) == 1245280) + return OPCODE_NOP; + if (Field_fld_ae6_slot2_24_10_Slot_ae6_slot2_get (insn) == 1170) + return OPCODE_AE_MOV; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 70) + return OPCODE_AE_MOVF64; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 71) + return OPCODE_AE_MOVT64; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 72 && + Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_get (insn) == 1) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 72 && + Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 73 && + Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_get (insn) == 1) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 73 && + Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 32) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 33) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 34) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 37 && + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get (insn) == 2) + return OPCODE_AE_PKSR32; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 37 && + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get (insn) == 1) + return OPCODE_AE_PKSR24; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 37 && + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get (insn) == 3) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 37 && + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_PKSR16; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 38 && + Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_get (insn) == 2) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 38 && + Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 38 && + Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_get (insn) == 1) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae6_slot2_24_20_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_MOVDX2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot3_37_13_Slot_ae6_slot3_get (insn) == 1179648 && + Field_fld_ae6_slot3_12_0_Slot_ae6_slot3_get (insn) == 33) + return OPCODE_NOP; + if (Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_get (insn) == 274432 && + Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_get (insn) == 274433 && + Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8192) + return OPCODE_AE_ACCW16; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8224) + return OPCODE_AE_ACCW32; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8256) + return OPCODE_AE_ACCW8; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8288) + return OPCODE_AE_ACCW8U; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8320) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8352) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8384) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8416) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8448) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8480) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 2 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_BMAX8X8_H; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 3 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_BMAX8X8_L; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 2 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_BMAX16X4; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 3 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_BMIN16X4; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_BMAX32X2; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_BMIN32X2; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 9) + return OPCODE_AE_ADD32S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 12) + return OPCODE_AE_SUB32S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 8) + return OPCODE_AE_ADD16S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 11) + return OPCODE_AE_SUB16S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 451) + return OPCODE_AE_NEG32S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 480) + return OPCODE_AE_ABS32S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 482) + return OPCODE_AE_NEG16S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 448) + return OPCODE_AE_ABS16S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 449) + return OPCODE_AE_ABS8S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 483) + return OPCODE_AE_NEG8S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 10) + return OPCODE_AE_ADD8S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 13) + return OPCODE_AE_SUB8S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 0 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_BMIN8X8_H; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 0 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_BMIN8X8_L; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 481) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 450) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_MULZAAF2D32RA_HH_LL; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_MULZAAF2D32RA_HL_LH; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 2) + return OPCODE_AE_MULZASF2D32RA_HH_LL; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 3) + return OPCODE_AE_MULZASF2D32RA_HL_LH; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 4) + return OPCODE_AE_MULZSAF2D32RA_HH_LL; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 5) + return OPCODE_AE_MULZSAF2D32RA_HL_LH; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 6) + return OPCODE_AE_MULZSSF2D32RA_HH_LL; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 7) + return OPCODE_AE_MULZSSF2D32RA_HL_LH; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 9 && + Field_fld_ae6_slot3_24_20_Slot_ae6_slot3_get (insn) == 0 && + Field_fld_ae6_slot3_14_0_Slot_ae6_slot3_get (insn) == 32) + return OPCODE_AE_MOV; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 9 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_MOVDX2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot0_23_0_Slot_ae7_slot0_get (insn) == 6889856) + return OPCODE_NOP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 864) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 865) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 866) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 867) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 868) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 869) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 870) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 871) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 872) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 873) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 874) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 875) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 876) + return OPCODE_AE_L64_X; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 877) + return OPCODE_AE_L64_XC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 878) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 879) + return OPCODE_AE_L64_XP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 880) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 881) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 882) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 883) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 884 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 884 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 885 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 885 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 885 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 886 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 886 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 886 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 887 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 887 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 887 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 888 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 888 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 888 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 889 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 889 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 889 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 890 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 890 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 890 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 8) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 9) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 10) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 11) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 892 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 892 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 893 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 893 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 894 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 894 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 895 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 895 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 52 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 52 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 6) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 52 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 4) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 52 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 7) + return OPCODE_AE_L64_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 52 && + Field_fld_ae7_slot0_12_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 53 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 5) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 53 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 4) + return OPCODE_AE_L64_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 4) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 5) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 6) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 7) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 8) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 9) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 10) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 11) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 12) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 13) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 14) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 15) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 16) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 17) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 18) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 19) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 20) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 21) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 22) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 23) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 24 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 24 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 24 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 24 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 25 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 25 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 25 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 25 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 26 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 106502) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 106630) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 106758) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 106886) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 107014) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 107142) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 107270) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 107398) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 107526) + return OPCODE_AE_LA8X8X2POS_PC2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot1_23_0_Slot_ae7_slot1_get (insn) == 6889856) + return OPCODE_NOP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 864) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 865) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 866) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 867) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 868) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 869) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 870) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 871) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 872) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 873) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 874) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 875) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 876) + return OPCODE_AE_L64_X; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 877) + return OPCODE_AE_L64_XC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 878) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 879) + return OPCODE_AE_L64_XP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 880) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 881) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 882) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 883) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 884 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 884 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 885 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 885 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 885 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 886 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 886 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 886 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 887 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 887 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 887 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 888 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 888 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 888 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 889 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 889 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 889 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 890 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 890 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 890 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 8) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 9) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 10) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 11) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 892 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 892 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 893 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 893 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 894 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 894 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 895 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 895 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 52 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 5) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 52 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 6) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 52 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 4) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 52 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 7) + return OPCODE_AE_L64_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 52 && + Field_fld_ae7_slot1_12_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 53 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 5) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 53 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 4) + return OPCODE_AE_L64_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 4) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 5) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 6) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 7) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 8) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 9) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 10) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 11) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 12) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 13) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 14) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 15) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 16) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 17) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 18) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 19) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 20) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 21) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 22) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 23) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 24 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 24 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 24 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 24 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 25 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 25 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 25 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 25 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 26 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 106502) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 106630) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 106758) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 106886) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 107014) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 107142) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 107270) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 107398) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 107526) + return OPCODE_AE_LA8X8X2POS_PC2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot2_36_12_Slot_ae7_slot2_get (insn) == 14772992 && + Field_fld_ae7_slot2_11_0_Slot_ae7_slot2_get (insn) == 1376) + return OPCODE_NOP; + if (Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_get (insn) == 1846592) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_get (insn) == 1846593) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57696) + return OPCODE_AE_MULAAAA2Q8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57697) + return OPCODE_AE_MULADDF32RAS; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57698) + return OPCODE_AE_MULADDF32RS; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57699) + return OPCODE_AE_MULSUBF32RAS; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57700) + return OPCODE_AE_MULSUBF32RS; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57701) + return OPCODE_AE_MULZAAAA2Q8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57702) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57703) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57704) + return OPCODE_AE_SEL8X8I; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 0) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 2) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 3) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 4) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 5) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 6) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 42) + return OPCODE_AE_MOV; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 39) + return OPCODE_AE_RMAX8X8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 41) + return OPCODE_AE_RMIN8X8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 38) + return OPCODE_AE_RMAX16X4; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 40) + return OPCODE_AE_RMIN16X4; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_10_Slot_ae7_slot2_get (insn) == 0) + return OPCODE_AE_SORT16X4; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 33) + return OPCODE_AE_RADD8X8_H; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 36) + return OPCODE_AE_RADDA8X8_H; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 34) + return OPCODE_AE_RADD8X8_L; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 37) + return OPCODE_AE_RADDA8X8_L; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 32) + return OPCODE_AE_RADD16X4; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 35) + return OPCODE_AE_RADDA16X4; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1760) + return OPCODE_AE_MULAAAA2Q16X8; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1761) + return OPCODE_AE_MULAF2P32X16X4RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1762) + return OPCODE_AE_MULAF2P32X16X4RS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1763) + return OPCODE_AE_MULAF2P32X16X4S; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1764) + return OPCODE_AE_MULAFD32X16X2_FIR_HH; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1765) + return OPCODE_AE_MULAFD32X16X2_FIR_HL; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1766) + return OPCODE_AE_MULAFD32X16X2_FIR_LH; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1767) + return OPCODE_AE_MULAFD32X16X2_FIR_LL; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1768) + return OPCODE_AE_MULAFD32X2RA_FIR_H; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1769) + return OPCODE_AE_MULAFD32X2RA_FIR_L; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1770) + return OPCODE_AE_MULAFD32X2S_FIR_H; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1771) + return OPCODE_AE_MULAFD32X2S_FIR_L; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1772) + return OPCODE_AE_MULAFPC32X16X2RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1773) + return OPCODE_AE_MULAFPCJ32X16X2RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1774) + return OPCODE_AE_MULAFQ16X2_FIR_0; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1775) + return OPCODE_AE_MULAFQ16X2_FIR_1; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1776) + return OPCODE_AE_MULAFQ16X2_FIR_2; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1777) + return OPCODE_AE_MULAFQ16X2_FIR_3; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1778) + return OPCODE_AE_MULAPC32X16X2; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1779) + return OPCODE_AE_MULF2P32X16X4RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1780) + return OPCODE_AE_MULF2P32X16X4RS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1781) + return OPCODE_AE_MULF2P32X16X4S; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1782) + return OPCODE_AE_MULFD32X16X2_FIR_HH; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1783) + return OPCODE_AE_MULFD32X16X2_FIR_HL; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1784) + return OPCODE_AE_MULFD32X16X2_FIR_LH; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1785) + return OPCODE_AE_MULFD32X16X2_FIR_LL; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1786) + return OPCODE_AE_MULFD32X2RA_FIR_H; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1787) + return OPCODE_AE_MULFD32X2RA_FIR_L; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1788) + return OPCODE_AE_MULFD32X2S_FIR_H; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1789) + return OPCODE_AE_MULFD32X2S_FIR_L; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1790) + return OPCODE_AE_MULFPC32X16X2RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1791) + return OPCODE_AE_MULFPCJ32X16X2RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1792) + return OPCODE_AE_MULFQ16X2_FIR_0; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1793) + return OPCODE_AE_MULFQ16X2_FIR_1; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1794) + return OPCODE_AE_MULFQ16X2_FIR_2; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1795) + return OPCODE_AE_MULFQ16X2_FIR_3; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1796) + return OPCODE_AE_MULPC32X16X2; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1797) + return OPCODE_AE_MULSF2P32X16X4RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1798) + return OPCODE_AE_MULSF2P32X16X4RS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1799) + return OPCODE_AE_MULSF2P32X16X4S; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1800) + return OPCODE_AE_MULZAAAA2Q16X8; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1801) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1802) + return OPCODE_AE_DSEL8X8; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1824 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULAAAAFQ32X16; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1825 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULAAAAQ32X16; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1826 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULZAAAAFQ32X16; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1827 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULZAAAAQ32X16; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 0) + return OPCODE_AE_MUL2P32X4; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MUL2P32X4S; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 2) + return OPCODE_AE_MUL2P32X4T; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 3) + return OPCODE_AE_MUL2Q32X16_FIR_H; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 4) + return OPCODE_AE_MUL2Q32X16_FIR_L; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 5) + return OPCODE_AE_MULA2P32X4; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 6) + return OPCODE_AE_MULA2P32X4T; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 7) + return OPCODE_AE_MULA2Q32X16_FIR_H; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 8) + return OPCODE_AE_MULA2Q32X16_FIR_L; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 9) + return OPCODE_AE_MULAAAA2Q16; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 10) + return OPCODE_AE_MULAAAA2Q32X16; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 11) + return OPCODE_AE_MULAAF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 12) + return OPCODE_AE_MULAAF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 13) + return OPCODE_AE_MULAAF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 14) + return OPCODE_AE_MULAAF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 15) + return OPCODE_AE_MULAF2P32X4RAS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 16) + return OPCODE_AE_MULAF2P32X4RS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 17) + return OPCODE_AE_MULASF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 18) + return OPCODE_AE_MULASF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 19) + return OPCODE_AE_MULASF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 20) + return OPCODE_AE_MULASF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 21) + return OPCODE_AE_MULF2D32X2WS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 22) + return OPCODE_AE_MULF2P32X4RAS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 23) + return OPCODE_AE_MULF2P32X4RS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 24) + return OPCODE_AE_MULFD16X16X4WS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 25) + return OPCODE_AE_MULS2P32X4; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 26) + return OPCODE_AE_MULS2P32X4T; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 27) + return OPCODE_AE_MULSAF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 28) + return OPCODE_AE_MULSAF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 29) + return OPCODE_AE_MULSAF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 30) + return OPCODE_AE_MULSAF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 31) + return OPCODE_AE_MULSF2P32X4RAS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 32) + return OPCODE_AE_MULSF2P32X4RS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 33) + return OPCODE_AE_MULSSF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 34) + return OPCODE_AE_MULSSF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 35) + return OPCODE_AE_MULSSF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 36) + return OPCODE_AE_MULSSF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 37) + return OPCODE_AE_MULZAAAA2Q16; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 38) + return OPCODE_AE_MULZAAAA2Q32X16; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 39) + return OPCODE_AE_MULZAAF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 40) + return OPCODE_AE_MULZAAF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 41) + return OPCODE_AE_MULZAAF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 42) + return OPCODE_AE_MULZAAF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 43) + return OPCODE_AE_MULZASF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 44) + return OPCODE_AE_MULZASF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 45) + return OPCODE_AE_MULZASF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 46) + return OPCODE_AE_MULZASF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 47) + return OPCODE_AE_MULZSAF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 48) + return OPCODE_AE_MULZSAF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 49) + return OPCODE_AE_MULZSAF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 50) + return OPCODE_AE_MULZSAF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 51) + return OPCODE_AE_MULZSSF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 52) + return OPCODE_AE_MULZSSF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 53) + return OPCODE_AE_MULZSSF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 54) + return OPCODE_AE_MULZSSF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 57 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 0) + return OPCODE_AE_MULFD16X16X4RAS; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot3_35_11_Slot_ae7_slot3_get (insn) == 29884417 && + Field_fld_ae7_slot3_10_0_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57632) + return OPCODE_AE_MULAAAA2Q8; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57633) + return OPCODE_AE_MULADDF32RAS; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57634) + return OPCODE_AE_MULADDF32RS; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57635) + return OPCODE_AE_MULSUBF32RAS; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57636) + return OPCODE_AE_MULSUBF32RS; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57637) + return OPCODE_AE_MULZAAAA2Q8; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57638 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57638 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57638 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 2) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57638 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 3) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57639 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57639 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57639 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 2) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1760) + return OPCODE_AE_MULAAAA2Q16X8; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1761) + return OPCODE_AE_MULAF2P32X16X4RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1762) + return OPCODE_AE_MULAF2P32X16X4RS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1763) + return OPCODE_AE_MULAF2P32X16X4S; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1764) + return OPCODE_AE_MULAFD32X16X2_FIR_HH; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1765) + return OPCODE_AE_MULAFD32X16X2_FIR_HL; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1766) + return OPCODE_AE_MULAFD32X16X2_FIR_LH; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1767) + return OPCODE_AE_MULAFD32X16X2_FIR_LL; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1768) + return OPCODE_AE_MULAFD32X2RA_FIR_H; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1769) + return OPCODE_AE_MULAFD32X2RA_FIR_L; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1770) + return OPCODE_AE_MULAFD32X2S_FIR_H; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1771) + return OPCODE_AE_MULAFD32X2S_FIR_L; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1772) + return OPCODE_AE_MULAFPC32X16X2RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1773) + return OPCODE_AE_MULAFPCJ32X16X2RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1774) + return OPCODE_AE_MULAFQ16X2_FIR_0; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1775) + return OPCODE_AE_MULAFQ16X2_FIR_1; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1776) + return OPCODE_AE_MULAFQ16X2_FIR_2; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1777) + return OPCODE_AE_MULAFQ16X2_FIR_3; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1778) + return OPCODE_AE_MULAPC32X16X2; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1779) + return OPCODE_AE_MULF2P32X16X4RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1780) + return OPCODE_AE_MULF2P32X16X4RS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1781) + return OPCODE_AE_MULF2P32X16X4S; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1782) + return OPCODE_AE_MULFD32X16X2_FIR_HH; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1783) + return OPCODE_AE_MULFD32X16X2_FIR_HL; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1784) + return OPCODE_AE_MULFD32X16X2_FIR_LH; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1785) + return OPCODE_AE_MULFD32X16X2_FIR_LL; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1786) + return OPCODE_AE_MULFD32X2RA_FIR_H; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1787) + return OPCODE_AE_MULFD32X2RA_FIR_L; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1788) + return OPCODE_AE_MULFD32X2S_FIR_H; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1789) + return OPCODE_AE_MULFD32X2S_FIR_L; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1790) + return OPCODE_AE_MULFPC32X16X2RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1791) + return OPCODE_AE_MULFPCJ32X16X2RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1792) + return OPCODE_AE_MULFQ16X2_FIR_0; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1793) + return OPCODE_AE_MULFQ16X2_FIR_1; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1794) + return OPCODE_AE_MULFQ16X2_FIR_2; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1795) + return OPCODE_AE_MULFQ16X2_FIR_3; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1796) + return OPCODE_AE_MULPC32X16X2; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1797) + return OPCODE_AE_MULSF2P32X16X4RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1798) + return OPCODE_AE_MULSF2P32X16X4RS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1799) + return OPCODE_AE_MULSF2P32X16X4S; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1800) + return OPCODE_AE_MULZAAAA2Q16X8; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1856 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULAAAAFQ32X16; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1856 && + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (insn) == 98) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1857 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULAAAAQ32X16; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1857 && + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (insn) == 98) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1858 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULZAAAAFQ32X16; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1859 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULZAAAAQ32X16; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MUL2P32X4; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MUL2P32X4S; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 2) + return OPCODE_AE_MUL2P32X4T; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 3) + return OPCODE_AE_MUL2Q32X16_FIR_H; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 4) + return OPCODE_AE_MUL2Q32X16_FIR_L; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 5) + return OPCODE_AE_MULA2P32X4; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 6) + return OPCODE_AE_MULA2P32X4T; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 7) + return OPCODE_AE_MULA2Q32X16_FIR_H; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 8) + return OPCODE_AE_MULA2Q32X16_FIR_L; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 9) + return OPCODE_AE_MULAAAA2Q16; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 10) + return OPCODE_AE_MULAAAA2Q32X16; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 11) + return OPCODE_AE_MULAAF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 12) + return OPCODE_AE_MULAAF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 13) + return OPCODE_AE_MULAAF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 14) + return OPCODE_AE_MULAAF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 15) + return OPCODE_AE_MULAF2P32X4RAS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 16) + return OPCODE_AE_MULAF2P32X4RS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 17) + return OPCODE_AE_MULASF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 18) + return OPCODE_AE_MULASF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 19) + return OPCODE_AE_MULASF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 20) + return OPCODE_AE_MULASF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 21) + return OPCODE_AE_MULF2D32X2WS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 22) + return OPCODE_AE_MULF2P32X4RAS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 23) + return OPCODE_AE_MULF2P32X4RS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 24) + return OPCODE_AE_MULFD16X16X4WS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 25) + return OPCODE_AE_MULS2P32X4; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 26) + return OPCODE_AE_MULS2P32X4T; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 27) + return OPCODE_AE_MULSAF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 28) + return OPCODE_AE_MULSAF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 29) + return OPCODE_AE_MULSAF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 30) + return OPCODE_AE_MULSAF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 31) + return OPCODE_AE_MULSF2P32X4RAS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 32) + return OPCODE_AE_MULSF2P32X4RS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 33) + return OPCODE_AE_MULSSF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 34) + return OPCODE_AE_MULSSF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 35) + return OPCODE_AE_MULSSF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 36) + return OPCODE_AE_MULSSF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 37) + return OPCODE_AE_MULZAAAA2Q16; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 38) + return OPCODE_AE_MULZAAAA2Q32X16; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 39) + return OPCODE_AE_MULZAAF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 40) + return OPCODE_AE_MULZAAF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 41) + return OPCODE_AE_MULZAAF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 42) + return OPCODE_AE_MULZAAF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 43) + return OPCODE_AE_MULZASF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 44) + return OPCODE_AE_MULZASF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 45) + return OPCODE_AE_MULZASF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 46) + return OPCODE_AE_MULZASF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 47) + return OPCODE_AE_MULZSAF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 48) + return OPCODE_AE_MULZSAF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 49) + return OPCODE_AE_MULZSAF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 50) + return OPCODE_AE_MULZSAF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 51) + return OPCODE_AE_MULZSSF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 52) + return OPCODE_AE_MULZSSF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 53) + return OPCODE_AE_MULZSSF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 54) + return OPCODE_AE_MULZSSF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 57 && + Field_fld_ae7_slot3_24_10_Slot_ae7_slot3_get (insn) == 2 && + Field_fld_ae7_slot3_4_0_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MOV; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 57 && + Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_DSEL8X8; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 57 && + Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 58 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MULFD16X16X4RAS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 58 && + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (insn) == 34) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 58 && + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (insn) == 2) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 58 && + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (insn) == 66) + return OPCODE_AE_SEL8X8I; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae8_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get (insn) == 566808 && + Field_fld_ae8_slot2_33_9_Slot_ae8_slot2_get (insn) == 4096 && + Field_fld_ae8_slot2_8_0_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get (insn) == 566808 && + Field_fld_ae8_slot2_33_25_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_15_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_get (insn) == 0) + return OPCODE_AE_MOV; + if (Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get (insn) == 566808 && + Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_get (insn) == 32 && + Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MOVZBVCDR; + if (Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get (insn) == 566808 && + Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MOVDRZBVC; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 262924) + return OPCODE_AE_MUL4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 263948) + return OPCODE_AE_MUL4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 264972) + return OPCODE_AE_MULA4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 265996) + return OPCODE_AE_MULA4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 267020) + return OPCODE_AE_MULASU4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 268044) + return OPCODE_AE_MULASU4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 269068) + return OPCODE_AE_MULAUS4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 270092) + return OPCODE_AE_MULAUS4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 271116) + return OPCODE_AE_MULAUU4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 272140) + return OPCODE_AE_MULAUU4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 273164) + return OPCODE_AE_MULAUUZB4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 274188) + return OPCODE_AE_MULAUUZB4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 275212) + return OPCODE_AE_MULSU4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 276236) + return OPCODE_AE_MULSU4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 277260) + return OPCODE_AE_MULUS4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 278284) + return OPCODE_AE_MULUS4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 279308) + return OPCODE_AE_MULUU4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 280332) + return OPCODE_AE_MULUU4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 281356) + return OPCODE_AE_MULUUZB4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 282380) + return OPCODE_AE_MULUUZB4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 360645 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MUL8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 360645 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MUL2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 360677 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MUL8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 360677 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULA2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 361669 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULA8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 361669 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULA8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 361701 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULASU8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 361701 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULASU2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 362693 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUS2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 362693 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULASU8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 362725 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUS8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 362725 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUS8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 363717 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUU8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 363717 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUU2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 363749 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUU8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 363749 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUUZB2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 364741 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUUZB8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 364741 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUUZB8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 364773 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULSU8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 364773 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULSU2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 365765 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 365765 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULSU8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 365797 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 365797 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUS8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 366789 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUU8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 366789 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUU2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 366821 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUU8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 366821 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUUZB2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 367813 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUUZB8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 367813 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUUZB8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10240) + return OPCODE_AE_MUL4O4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10272) + return OPCODE_AE_MUL4QW8X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10304) + return OPCODE_AE_MULA4O4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10336) + return OPCODE_AE_MULA4QW8X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10368) + return OPCODE_AE_MULAUS4O4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10400) + return OPCODE_AE_MULAUS4QW8X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10432) + return OPCODE_AE_MULUS4O4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10464) + return OPCODE_AE_MULUS4QW8X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 11264 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MUL8Q4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 11265 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MULA8Q4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 11266 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MULAUS8Q4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 11267 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MULUS8Q4X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 0) + return OPCODE_AE_MUL4O8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MUL8QW8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 2) + return OPCODE_AE_MULA4O8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 3) + return OPCODE_AE_MULA8QW8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULAUS4O8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULAUS8QW8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUS4O8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS8QW8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULQQ8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 2) + return OPCODE_AE_MULAQQ8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 140) + return OPCODE_AE_MUL4O8X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 332) + return OPCODE_AE_MULA4O8X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 172) + return OPCODE_AE_MUL4O8X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 364) + return OPCODE_AE_MULA4O8X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULQQ4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 0) + return OPCODE_AE_MULAQQ4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULQQ4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MULAQQ4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 12) + return OPCODE_AE_MUL4O4X16CNV_HH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 44) + return OPCODE_AE_MUL4O4X16CNV_HL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 76) + return OPCODE_AE_MUL4O4X16CNV_LH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 108) + return OPCODE_AE_MUL4O4X16CNV_LL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 204) + return OPCODE_AE_MULA4O4X16CNV_HH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 236) + return OPCODE_AE_MULA4O4X16CNV_HL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 268) + return OPCODE_AE_MULA4O4X16CNV_LH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 300) + return OPCODE_AE_MULA4O4X16CNV_LL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 11) + return OPCODE_AE_MULUSQQ8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULAUSQQ8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 716) + return OPCODE_AE_MULUS4O8X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 524) + return OPCODE_AE_MULAUS4O8X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 748) + return OPCODE_AE_MULUS4O8X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 556) + return OPCODE_AE_MULAUS4O8X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MULUSQQ4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3) + return OPCODE_AE_MULAUSQQ4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 10) + return OPCODE_AE_MULUSQQ4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULAUSQQ4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 588) + return OPCODE_AE_MULUS4O4X16CNV_HH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 620) + return OPCODE_AE_MULUS4O4X16CNV_HL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 652) + return OPCODE_AE_MULUS4O4X16CNV_LH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 684) + return OPCODE_AE_MULUS4O4X16CNV_LL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 396) + return OPCODE_AE_MULAUS4O4X16CNV_HH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 428) + return OPCODE_AE_MULAUS4O4X16CNV_HL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 460) + return OPCODE_AE_MULAUS4O4X16CNV_LH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 492) + return OPCODE_AE_MULAUS4O4X16CNV_LL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 0) + return OPCODE_AE_MUL4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MULA4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULUU4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULAUU4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 3) + return OPCODE_AE_MULAUS4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULSU4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 2) + return OPCODE_AE_MULASU4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MULUUZB4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULAUUZB4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MUL8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 1 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULA8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 0) + return OPCODE_AE_MUL8Q8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MULA8Q8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 37 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MUL8Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 69 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULA8Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MUL2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 1 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULA2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MUL2X4Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 1 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULA2X4Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 5 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MUL8Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 37 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULA8Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 5 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MUL8Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 69 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULA8Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MUL2X4Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 1 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULA2X4Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MUL2X4Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 1 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULA2X4Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULUU8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 4 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULAUU8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 5 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULUU2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULAUU2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 7 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULUS8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULAUS8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 3) + return OPCODE_AE_MULUS8Q8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 2) + return OPCODE_AE_MULAUS8Q8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 165 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS8Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 133 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUS8Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 4 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULAUS2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 4 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUS2X4Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 2 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUS2X4Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 133 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS8Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 101 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUS8Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 165 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUS8Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 101 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUS8Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 4 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULUS2X4Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 2 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULAUS2X4Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 4 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULUS2X4Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 2 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUS2X4Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 6 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULSU8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 2 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULASU8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULSU2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 2 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULASU2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULUUZB8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 5 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULAUUZB8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 5 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULUUZB2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUUZB2X4Q8X8CNV_L; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae9_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_get (insn) == 228098 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONST_H; + if (Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_get (insn) == 228099 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONST_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 98689 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ABS_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 99713 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONJC_H; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 100737 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONJC_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 101761 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_DIV0_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 102785 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MKSADJ_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 103809 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MULJC_H; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 104833 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MULJC_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 105857 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_NEG_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 106881 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_NEXP01_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 107905 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_RECIP0_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 108929 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_RSQRT0_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 109953 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_SQRT0_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 110977 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ABS_H; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 112001 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CLSFY_H; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 113025 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_NEG_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2624 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_DIVN_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2656 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MADDN_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2688 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MADD_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2720 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MSUBN_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2752 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MSUB_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2784 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MUL_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3083 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MAXNUM_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3115 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MAX_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3147 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MINNUM_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3179 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MIN_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3211 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 1 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_AE_MOVT64; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3211 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_AE_MOVF64; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 1 && + Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_get (insn) == 33) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 1 && + Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_get (insn) == 33) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 865) + return OPCODE_AE_MOV; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 705) + return OPCODE_MKDADJ_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 609) + return OPCODE_ADDEXP_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 577) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 833) + return OPCODE_ADDEXP_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 737) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 74) + return OPCODE_MADDQ_S; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 75) + return OPCODE_MSUBQ_S; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 76) + return OPCODE_MULQ_S; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 77) + return OPCODE_MULQ_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 0) + return OPCODE_MADDA_S; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 128) + return OPCODE_ADD_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 133) + return OPCODE_SUB_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 132) + return OPCODE_MUL_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 129) + return OPCODE_MADD_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 131) + return OPCODE_MSUB_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 130) + return OPCODE_MSUBN_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 96 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 2) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_get (insn) == 36) + return OPCODE_MULMUXQ_S; + if (Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_get (insn) == 40 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MULMUX_S; + if (Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_get (insn) == 8) + return OPCODE_MADDMUXQ_S; + if (Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 0) + return OPCODE_ADD_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_SUB_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 0) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 33) + return OPCODE_ADD_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 161) + return OPCODE_SUB_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 321) + return OPCODE_MIN_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 385) + return OPCODE_MAX_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_get (insn) == 386 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CLSFY_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 193) + return OPCODE_MINNUM_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 257) + return OPCODE_MAXNUM_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 9 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 8 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 449) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_FREXP_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_get (insn) == 386 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 33) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 65) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 129) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 1 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 7 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 5 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_get (insn) == 769 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 6 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 2 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_get (insn) == 768 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 4 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae9_slot2_33_9_Slot_ae9_slot2_get (insn) == 6316160 && + Field_fld_ae9_slot2_8_0_Slot_ae9_slot2_get (insn) == 65) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae9_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get (insn) == 28696) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get (insn) == 28697) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get (insn) == 29846 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CONST_H; + if (Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get (insn) == 29847 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CONST_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14347 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CLSFY_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14379 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_DIV0_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14411 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14443 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_MKSADJ_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14475 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_NEXP01_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14507 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_RECIP0_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14539 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_RSQRT0_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14571 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_SQRT0_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14603 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_ABS_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14635 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CONJC_H; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14667 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CONJC_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14699 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_MULJC_H; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14731 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_MULJC_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14763 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_NEG_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14795 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_ABS_H; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14827 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CLSFY_H; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14859 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_NEG_H; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14891 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_AE_MOV; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 576 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_DIVN_S; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 608 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MADDN_S; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 640 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MADD_S; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 672 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MSUBN_S; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 704 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MSUB_S; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 736 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MUL_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 10) + return OPCODE_MADDQ_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 11) + return OPCODE_MSUBQ_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 12) + return OPCODE_MULQ_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 13) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_4_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_AE_SEL16I; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 27) + return OPCODE_MIN_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 25) + return OPCODE_MAX_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 26) + return OPCODE_MINNUM_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 25) + return OPCODE_MAXNUM_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 9) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 8) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 24) + return OPCODE_FREXP_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 26) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 24) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_BMAXNUM_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get (insn) == 2) + return OPCODE_BMINNUM_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_BMAXNUMABS_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get (insn) == 2) + return OPCODE_BMINNUMABS_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 7) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 3) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 5) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_MIN_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 28) + return OPCODE_MAX_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 28) + return OPCODE_MINNUM_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 27) + return OPCODE_MAXNUM_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 6) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 2) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 4) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 5) + return OPCODE_ADD_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 6) + return OPCODE_SUB_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 226) + return OPCODE_MKDADJ_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 225) + return OPCODE_ADDEXP_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 224) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 4) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_MADDA_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 228) + return OPCODE_ADDEXP_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 227) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 64) + return OPCODE_ADD_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 98) + return OPCODE_SUB_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 66) + return OPCODE_MUL_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 96) + return OPCODE_MADD_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 97) + return OPCODE_MSUB_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 65) + return OPCODE_MSUBN_H; + if (Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_get (insn) == 4) + return OPCODE_MULMUXQ_S; + if (Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_get (insn) == 8 && + Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MULMUX_S; + if (Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_MADDMUXQ_S; + if (Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_get (insn) == 2 && + Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae9_slot3_31_7_Slot_ae9_slot3_get (insn) == 3828480 && + Field_fld_ae9_slot3_6_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4096) + return OPCODE_AE_EXPADD16_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4097) + return OPCODE_AE_EXPADD16_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4098) + return OPCODE_AE_EXPSUB16_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4099) + return OPCODE_AE_EXPSUB16_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4100) + return OPCODE_AE_ADD16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4101) + return OPCODE_AE_ADD16S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4102) + return OPCODE_AE_ADD24S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4103) + return OPCODE_AE_ADD32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4104) + return OPCODE_AE_ADD32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4105) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4106) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4107) + return OPCODE_AE_ADD64; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4108) + return OPCODE_AE_ADD64S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4109) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4110) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4111) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4112) + return OPCODE_AE_ADDSUB32S_HL_LH; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4113) + return OPCODE_AE_ADDSUB32_HL_LH; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4114) + return OPCODE_AE_MAX16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4115) + return OPCODE_AE_MAX32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4116) + return OPCODE_AE_MAX8; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4117) + return OPCODE_AE_MIN16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4118) + return OPCODE_AE_MIN32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4119) + return OPCODE_AE_MIN8; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4120) + return OPCODE_AE_MINMAX16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4121) + return OPCODE_AE_MINMAX32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4122) + return OPCODE_AE_MOVNEG32S_T; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4123) + return OPCODE_AE_ROUND16X4F32SASYM; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4124) + return OPCODE_AE_ROUND16X4F32SSYM; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4125) + return OPCODE_AE_ROUND32X2F64SASYM; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4126) + return OPCODE_AE_ROUND32X2F64SSYM; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4127) + return OPCODE_AE_SUB16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4128) + return OPCODE_AE_SUB16S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4129) + return OPCODE_AE_SUB24S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4130) + return OPCODE_AE_SUB32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4131) + return OPCODE_AE_SUB32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4132) + return OPCODE_AE_SUB64; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4133) + return OPCODE_AE_SUB64S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4134) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4135) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4136) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4137) + return OPCODE_ADD_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4138) + return OPCODE_DIVN_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4139) + return OPCODE_MADDN_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4140) + return OPCODE_MADD_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4141) + return OPCODE_MSUB_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4142) + return OPCODE_MUL_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4143) + return OPCODE_SUB_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5131 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5163 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SAT48S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5195 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5208 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5209 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG16S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5210 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG24S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5211 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5212 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5213 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG32_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5214 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG64; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5215 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG64S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5227 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ADDEXP_S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5233 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5234 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5235 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS64; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5237 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS16S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5238 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS64S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5239 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5241 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS24S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5242 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5243 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5245 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5246 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_DIV64D32_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5247 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5259 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MKDADJ_S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5291 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADD16X4; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5323 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADD8X8_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5355 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADD8X8_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5387 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADDA16X4; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5419 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADDA8X8_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5451 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADDA8X8_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5483 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RMAX16X4; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5515 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RMAX8X8; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5547 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RMIN16X4; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5579 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RMIN8X8; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5611 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ABS_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5643 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_CLSFY_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5675 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_NEG_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5707 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MKDADJ_H; + if (Field_fld_ae_slot2_28_17_Slot_ae_slot2_get (insn) == 1300 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ADD72X64; + if (Field_fld_ae_slot2_28_17_Slot_ae_slot2_get (insn) == 1301 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SUB72X64; + if (Field_fld_ae_slot2_28_17_Slot_ae_slot2_get (insn) == 1316 && + Field_fld_ae_slot2_14_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SEXT72; + if (Field_fld_ae_slot2_28_19_Slot_ae_slot2_get (insn) == 321 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ADD72; + if (Field_fld_ae_slot2_28_19_Slot_ae_slot2_get (insn) == 323 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SUB72; + if (Field_fld_ae_slot2_28_19_Slot_ae_slot2_get (insn) == 327 && + Field_fld_ae_slot2_16_15_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SAT64S; + if (Field_fld_ae_slot2_28_19_Slot_ae_slot2_get (insn) == 342 && + Field_fld_ae_slot2_14_0_Slot_ae_slot2_get (insn) == 1062) + return OPCODE_AE_MOVEEP; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 64) + return OPCODE_AE_MUL16X4; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 65) + return OPCODE_AE_MUL16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 66) + return OPCODE_AE_MULA16X4; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 67) + return OPCODE_AE_MULA16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 68) + return OPCODE_AE_MULAFC32RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 69) + return OPCODE_AE_MULAFC32X16W_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 70) + return OPCODE_AE_MULAFC32X16W_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 71) + return OPCODE_AE_MULAFP32X2S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 72) + return OPCODE_AE_MULAFP32X2S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 73) + return OPCODE_AE_MULFC32RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 74) + return OPCODE_AE_MULFC32X16W_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 75) + return OPCODE_AE_MULFC32X16W_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 76) + return OPCODE_AE_MULFP32X2S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 77) + return OPCODE_AE_MULFP32X2S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 78) + return OPCODE_AE_MULS16X4; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 79) + return OPCODE_AE_MULS16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 80) + return OPCODE_AE_MULSFP32X2S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 81) + return OPCODE_AE_MULSFP32X2S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 82) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 83) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 84) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 85) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 86) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 87) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 88) + return OPCODE_MADDA_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 89) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 90) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 91) + return OPCODE_AE_SEL8X8I; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 2) + return OPCODE_AE_MUL32EP_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 5) + return OPCODE_AE_MULA32EP_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 3) + return OPCODE_AE_MUL32USEP_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 6) + return OPCODE_AE_MULA32USEP_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 4) + return OPCODE_AE_MUL32USEP_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 7) + return OPCODE_AE_MULA32USEP_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_8_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 7) + return OPCODE_AE_SEL16I_N; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 2) + return OPCODE_AE_MULS32EP_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 4) + return OPCODE_AE_MULZAAD32EP_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 6) + return OPCODE_AE_MULZSSD32EP_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_MULAAD32EP_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 3) + return OPCODE_AE_MULSSD32EP_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 1) + return OPCODE_AE_MULAAD32USEP_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 5) + return OPCODE_AE_MULZAAD32USEP_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 8) + return OPCODE_AE_MUL32U_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULA32U_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 2) + return OPCODE_AE_MUL16S_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULA16S_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 10) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 3) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 4) + return OPCODE_AE_MUL32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULA32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 7) + return OPCODE_AE_MUL32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULA32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 5) + return OPCODE_AE_MUL32S_HL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULA32S_HL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 6) + return OPCODE_AE_MUL32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULA32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_6_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MULMUX_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULAC16JS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULAC16JS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 5) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 4) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 3) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 1) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 2) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 8) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_MULAAD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 10) + return OPCODE_AE_MULAAD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 6) + return OPCODE_AE_MULAA2D16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 7) + return OPCODE_AE_MULAA2D16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULAAFD16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULAAFD16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULSAD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULSAD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULSAD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULSAD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC16S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULSF32RA_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32RA_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32RA_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULSF16SS_33; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULSF16SS_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULSF16SS_32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULSF16SS_21; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULSF16SS_31; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULSF16SS_30; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULSF16SS_10; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULSF16SS_20; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULSF16SS_11; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC16S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAFC16RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAFCJ32RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAFCJ16RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULSFP32X2TS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULSP32X2T; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULSP16S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULSP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULSP16X16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC32X16_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULSSD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULSSD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULSS2D16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULSS2D16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULSSFD16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULSSFD16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAFP32X2TS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC32X16_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULZAAD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULZAAD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAP16S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULZAA2D16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULZAA2D16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULZASD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULZASD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULACJ32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAP16X16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULZAAFD16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULZAAFD16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULZSAD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULZSAD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAP32X2T; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULZSAD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULZSAD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_10; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULZSSD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULASD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULZSSD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULASD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULZSS2D16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULZSS2D16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULZSSFD16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULZSSFD16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_11; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_MUL_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_MADD_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_MSUB_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_MSUBN_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_MADDN_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_DIVN_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_MIN_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_MAX_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_MINNUM_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_MAXNUM_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 106 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_20; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 106 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 106 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 106 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 106 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 107 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULC16JS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 107 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULC16JS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 107 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_21; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 107 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 107 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 108 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 108 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULC32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 108 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULC16S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 108 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULC16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 108 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULC16S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 109 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 109 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_30; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 109 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULC32X16_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 109 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULC32X16_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 109 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULCJ32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 110 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF16SS_21; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 110 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF16SS_10; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 110 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF16SS_20; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 110 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF16SS_11; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 110 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_31; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 111 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF16SS_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 111 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF16SS_32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 111 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF16SS_31; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 111 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF16SS_30; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 111 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 112 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF32RA_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 112 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF32RA_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 112 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF32RA_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 112 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF16SS_33; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 112 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_33; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 113 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 113 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 113 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 113 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 113 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32RA_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 114 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 114 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 114 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32RA_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 114 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 114 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 115 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32RA_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 115 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 115 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 115 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 115 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 116 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 116 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 116 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 116 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 116 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 117 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 117 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 117 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 117 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 117 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFC16RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 118 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 118 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULFP16X4RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 118 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 118 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULFCJ32RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 118 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULFCJ16RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 119 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 119 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 119 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 119 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULFP16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 119 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFP16X4RS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 120 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 120 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 120 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 120 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 120 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 121 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 121 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 121 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 121 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 121 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 122 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 122 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFP32X2TS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 122 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULP16S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 122 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 122 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULP16X16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 123 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 123 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 123 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 123 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 123 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULP32X2T; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 124 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 124 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULS16S_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 124 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 124 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 124 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 125 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 125 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 125 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 125 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULS32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 125 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULS32S_HL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 126 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULS32U_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 126 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 126 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 126 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULS32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 126 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULS32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 127 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 127 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 127 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 127 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 127 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 130 && + Field_fld_ae_slot2_14_10_Slot_ae_slot2_get (insn) == 1) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 130 && + Field_fld_ae_slot2_14_10_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 160 && + Field_fld_ae_slot2_9_2_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_PKSR16; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 161 && + Field_fld_ae_slot2_9_2_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_PKSR24; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 162 && + Field_fld_ae_slot2_9_2_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_PKSR32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 163 && + Field_fld_ae_slot2_9_2_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 164 && + Field_fld_ae_slot2_9_1_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 164 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_ABS_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 164 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_CONJC_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 165 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_MKSADJ_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 165 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_DIV0_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 165 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_CONJC_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 165 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_MULJC_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 166 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_NEXP01_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 166 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_RECIP0_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 166 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_NEG_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 166 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_MULJC_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 167 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_SQRT0_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 167 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_RSQRT0_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 167 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_ADDEXP_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 167 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 168 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 168 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 168 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_AE_MOV; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 168 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_DIV0_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 169 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_MKSADJ_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 169 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_NEXP0_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 169 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_NEXP01_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 169 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_RECIP0_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 170 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 170 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 170 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_RSQRT0_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 170 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_SQRT0_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 171 && + Field_fld_ae_slot2_14_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_AE_MOVZBVCDR; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 171 && + Field_fld_ae_slot2_14_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_AE_MOVDRZBVC; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 171 && + Field_fld_ae_slot2_14_14_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_CONST_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 171 && + Field_fld_ae_slot2_14_14_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_CONST_H; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 1) + return OPCODE_AE_DSEL8X8; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 8) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 10) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 9) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 1) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 7) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 3) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 5) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 6) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 2) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 4) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 7 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SORT16X4; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 9 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ADD_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 10 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_SUB_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 6 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MIN_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MAX_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 33) + return OPCODE_CLSFY_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MINNUM_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 2 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MAXNUM_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 8 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_FREXP_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 1 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 33) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 4 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 1 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_14_14_Slot_ae_slot2_get (insn) == 1 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 32) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_14_14_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 32) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae_slot2_28_4_Slot_ae_slot2_get (insn) == 11206722 && + Field_fld_ae_slot2_3_0_Slot_ae_slot2_get (insn) == 7) + return OPCODE_NOP; + if (Field_fld_ae_slot2_28_5_Slot_ae_slot2_get (insn) == 5394432) + return OPCODE_AE_MOVFCRFSRV; + if (Field_fld_ae_slot2_28_5_Slot_ae_slot2_get (insn) == 5395456) + return OPCODE_AE_MOVVFCRFSR; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot3_36_12_Slot_ae_slot3_get (insn) == 15205414 && + Field_fld_ae_slot3_11_0_Slot_ae_slot3_get (insn) == 2146) + return OPCODE_NOP; + if (Field_fld_ae_slot3_36_16_Slot_ae_slot3_get (insn) == 934928 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot3_36_19_Slot_ae_slot3_get (insn) == 116864 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae_slot3_36_19_Slot_ae_slot3_get (insn) == 116868 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_CONST_H; + if (Field_fld_ae_slot3_36_19_Slot_ae_slot3_get (insn) == 116870 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_CONST_S; + if (Field_fld_ae_slot3_36_19_Slot_ae_slot3_get (insn) == 116928 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57632) + return OPCODE_AE_MUL16X4; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57633) + return OPCODE_AE_MUL16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57634) + return OPCODE_AE_MUL2C16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57635) + return OPCODE_AE_MUL32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57636) + return OPCODE_AE_MUL32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57637) + return OPCODE_AE_MULA16X4; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57638) + return OPCODE_AE_MULA16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57639) + return OPCODE_AE_MULA2C16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57640) + return OPCODE_AE_MULA32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57641) + return OPCODE_AE_MULA32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57642) + return OPCODE_AE_MULAA32X2_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57643) + return OPCODE_AE_MULAAAA2Q8; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57644) + return OPCODE_AE_MULAC16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57645) + return OPCODE_AE_MULAC16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57646) + return OPCODE_AE_MULAC32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57647) + return OPCODE_AE_MULAC32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57648) + return OPCODE_AE_MULAC32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57649) + return OPCODE_AE_MULACJ32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57650) + return OPCODE_AE_MULADDF32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57651) + return OPCODE_AE_MULADDF32RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57652) + return OPCODE_AE_MULAF16X4SS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57653) + return OPCODE_AE_MULAF32X2RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57654) + return OPCODE_AE_MULAF32X2RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57655) + return OPCODE_AE_MULAF32X2R_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57656) + return OPCODE_AE_MULAF32X2R_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57657) + return OPCODE_AE_MULAFC16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57658) + return OPCODE_AE_MULAFC32RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57659) + return OPCODE_AE_MULAFC32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57660) + return OPCODE_AE_MULAFC32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57661) + return OPCODE_AE_MULAFC32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57662) + return OPCODE_AE_MULAFCJ16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57663) + return OPCODE_AE_MULAFCJ32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57664) + return OPCODE_AE_MULAFCJ32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57665) + return OPCODE_AE_MULAFCJ32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57666) + return OPCODE_AE_MULAFP32X16_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57667) + return OPCODE_AE_MULAFP32X16_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57668) + return OPCODE_AE_MULC32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57669) + return OPCODE_AE_MULC32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57670) + return OPCODE_AE_MULC32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57671) + return OPCODE_AE_MULCJ32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57672) + return OPCODE_AE_MULF32X2R_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57673) + return OPCODE_AE_MULFC16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57674) + return OPCODE_AE_MULFC32RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57675) + return OPCODE_AE_MULFC32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57676) + return OPCODE_AE_MULFCJ32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57677) + return OPCODE_AE_MULFCJ32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57678) + return OPCODE_AE_MULFP32X16_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57679) + return OPCODE_AE_MULFP32X16_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57680) + return OPCODE_AE_MULS32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57681) + return OPCODE_AE_MULS32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57682) + return OPCODE_AE_MULSF16X4SS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57683) + return OPCODE_AE_MULSF32X2RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57684) + return OPCODE_AE_MULSFP32X16_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57685) + return OPCODE_AE_MULSFP32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57686) + return OPCODE_AE_MULSFP32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57687) + return OPCODE_AE_MULSS32X2_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57688) + return OPCODE_AE_MULZSS32X2_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULAC16JS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULAC16JS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULAAD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULAAD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULAA2D16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULAA2D16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULAAFD16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULAAFD16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULC16JS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULF32RA_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULF16SS_33; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULF16SS_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULF16SS_31; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULF16SS_10; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULF16SS_20; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULC16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULFC16RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULFCJ32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULCJ32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULC16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULC16JS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULF32RA_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULF32RA_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULF16SS_32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULF16SS_21; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULF16SS_30; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULF16SS_11; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULC32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULC16S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULFCJ16RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULFP16X4RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSS2D16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57693 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57693 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57693 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57693 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57693 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57694 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57694 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57694 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57694 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57694 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57695 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57695 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57695 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57695 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57695 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZSAD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57696) + return OPCODE_AE_MULAFP32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57697) + return OPCODE_AE_MULAFP32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57698) + return OPCODE_AE_MULC16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57699) + return OPCODE_AE_MULC16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57700) + return OPCODE_AE_MULF16X4SS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57701) + return OPCODE_AE_MULF32X2RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57702) + return OPCODE_AE_MULF32X2RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57703) + return OPCODE_AE_MULF32X2R_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57704) + return OPCODE_AE_MULFC32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57705) + return OPCODE_AE_MULFC32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57706) + return OPCODE_AE_MULFCJ16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57707) + return OPCODE_AE_MULFCJ32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57708) + return OPCODE_AE_MULFP32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57709) + return OPCODE_AE_MULFP32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57710) + return OPCODE_AE_MULS16X4; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57711) + return OPCODE_AE_MULS16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57712) + return OPCODE_AE_MULSF32X2RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57713) + return OPCODE_AE_MULSF32X2R_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57714) + return OPCODE_AE_MULSF32X2R_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57715) + return OPCODE_AE_MULSFP32X16_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57716) + return OPCODE_AE_MULSUBF32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57717) + return OPCODE_AE_MULSUBF32RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57718) + return OPCODE_AE_MULZAA32X2_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57719) + return OPCODE_AE_MULZAAAA2Q8; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULSF32RA_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULSF16SS_31; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULSF16SS_20; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULS32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULSAD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULP16S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULSP16S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULSS2D16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULZAAFD16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULSF32RA_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULSF16SS_32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULSF16SS_21; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULS16S_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULS32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULZAAD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULSSD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULSAD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULSP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULSS2D16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULZAAFD16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULSF16SS_33; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULSF16SS_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULSF16SS_10; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULSAD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULS32S_HL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULZAAD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULSSD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULP32X2S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULP16X16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULSP16X16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULZAA2D16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULSSFD16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULSF32RA_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULSF16SS_30; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULSF16SS_11; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULSAD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULS32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULZAA2D16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULSSFD16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57725 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57725 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57725 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57725 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57725 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57726 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57726 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57726 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57726 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57726 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57727 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57727 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57727 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57727 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZSAD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57727 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSS2D16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59532 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59533 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59534 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32S_HL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59535 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59536 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAC16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59537 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULACJ32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59538 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_20; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59539 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_31; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59540 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32RA_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59541 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59542 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59543 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59544 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59545 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59546 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFCJ32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59547 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59548 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59549 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59550 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59551 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59560 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL16S_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59561 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59562 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59563 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32S_HL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59564 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59565 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA16S_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59566 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59567 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59568 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAC16S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59569 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59570 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_21; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59571 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59572 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32RA_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59573 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59574 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59575 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59576 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59577 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59578 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59579 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59580 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59581 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP16X16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59582 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59583 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59592 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59593 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59594 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59595 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59596 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59597 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59598 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59599 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59600 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAC16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59601 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_10; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59602 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59603 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_33; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59604 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59605 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59606 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59607 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59608 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFC16RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59609 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59610 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59611 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59612 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59613 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59614 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59615 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULASD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59624 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59625 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59626 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59627 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59628 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59629 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59630 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59631 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59632 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAC32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59633 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_11; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59634 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_30; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59635 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32RA_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59636 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59637 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59638 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59639 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59640 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59641 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFCJ16RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59642 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59643 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59644 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP16S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59645 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59646 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59647 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULASD32S_HL_LH; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14849 && + Field_fld_ae_slot3_19_17_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26722) + return OPCODE_AE_MOVEEP; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14880 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32EP_HH; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14881 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULS32EP_HH; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14882 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSSD32EP_HH_LL; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14888 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32EP_HH; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14889 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULSSD32EP_HH_LL; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14896 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAAD32EP_HH_LL; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14897 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZAAD32EP_HH_LL; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14904 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAAD32USEP_HL_LH; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14905 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZAAD32USEP_HL_LH; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1760) + return OPCODE_AE_MULAAAA2Q16X8; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1761) + return OPCODE_AE_MULAF2P32X16X4RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1762) + return OPCODE_AE_MULAF2P32X16X4RS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1763) + return OPCODE_AE_MULAF2P32X16X4S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1764) + return OPCODE_AE_MULAFD32X16X2_FIR_HH; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1765) + return OPCODE_AE_MULAFD32X16X2_FIR_HL; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1766) + return OPCODE_AE_MULAFD32X16X2_FIR_LH; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1767) + return OPCODE_AE_MULAFD32X16X2_FIR_LL; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1768) + return OPCODE_AE_MULAFD32X2RA_FIR_H; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1769) + return OPCODE_AE_MULAFD32X2RA_FIR_L; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1770) + return OPCODE_AE_MULAFD32X2S_FIR_H; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1771) + return OPCODE_AE_MULAFD32X2S_FIR_L; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1772) + return OPCODE_AE_MULAFPC32X16X2RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1773) + return OPCODE_AE_MULAFPCJ32X16X2RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1774) + return OPCODE_AE_MULAFQ16X2_FIR_0; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1775) + return OPCODE_AE_MULAFQ16X2_FIR_1; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1776) + return OPCODE_AE_MULAFQ16X2_FIR_2; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1777) + return OPCODE_AE_MULAFQ16X2_FIR_3; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1778) + return OPCODE_AE_MULAPC32X16X2; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1779) + return OPCODE_AE_MULF2P32X16X4RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1780) + return OPCODE_AE_MULF2P32X16X4RS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1781) + return OPCODE_AE_MULF2P32X16X4S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1782) + return OPCODE_AE_MULFD32X16X2_FIR_HH; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1783) + return OPCODE_AE_MULFD32X16X2_FIR_HL; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1784) + return OPCODE_AE_MULFD32X16X2_FIR_LH; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1785) + return OPCODE_AE_MULFD32X16X2_FIR_LL; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1786) + return OPCODE_AE_MULFD32X2RA_FIR_H; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1787) + return OPCODE_AE_MULFD32X2RA_FIR_L; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1788) + return OPCODE_AE_MULFD32X2S_FIR_H; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1789) + return OPCODE_AE_MULFD32X2S_FIR_L; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1790) + return OPCODE_AE_MULFPC32X16X2RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1791) + return OPCODE_AE_MULFPCJ32X16X2RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1792) + return OPCODE_AE_MULFQ16X2_FIR_0; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1793) + return OPCODE_AE_MULFQ16X2_FIR_1; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1794) + return OPCODE_AE_MULFQ16X2_FIR_2; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1795) + return OPCODE_AE_MULFQ16X2_FIR_3; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1796) + return OPCODE_AE_MULPC32X16X2; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1797) + return OPCODE_AE_MULSF2P32X16X4RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1798) + return OPCODE_AE_MULSF2P32X16X4RS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1799) + return OPCODE_AE_MULSF2P32X16X4S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1800) + return OPCODE_AE_MULZAAAA2Q16X8; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 433250) + return OPCODE_AE_RNG32X2; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 24 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 29 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 26 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 30 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 31 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI32R; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 25 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI24S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 27 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI32S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLI64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (insn) == 13 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (insn) == 9 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAISQ56S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (insn) == 5 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI64S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_13_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI72; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 28 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI72; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLI24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 515 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 899 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLS24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 771 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAS24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_19_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI16; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_19_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI16R; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLI32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 579 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 931 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLS32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 803 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAS32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_19_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI16S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 547 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 611 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS32S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 707 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLASQ56; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 995 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLSQ56; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 867 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRASQ56; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 643 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 963 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLS64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 835 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAS64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 739 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLASSQ56S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 675 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS64S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1856 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAAAAFQ32X16; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1856 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 99) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1857 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAAAAQ32X16; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1857 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 99) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1858 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZAAAAFQ32X16; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1859 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZAAAAQ32X16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MUL2P32X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MUL2P32X4S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL2P32X4T; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MUL2Q32X16_FIR_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MUL2Q32X16_FIR_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULA2P32X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULA2P32X4T; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULA2Q32X16_FIR_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULA2Q32X16_FIR_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULAAAA2Q16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULAAAA2Q32X16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULAAF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULAAF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULAAF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULAAF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULAF2P32X4RAS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULAF2P32X4RS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULASF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULASF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULASF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULASF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULF2D32X2WS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULF2P32X4RAS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULF2P32X4RS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULFD16X16X4WS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULS2P32X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULS2P32X4T; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULSAF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULSAF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULSAF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULSAF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULSF2P32X4RAS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 32) + return OPCODE_AE_MULSF2P32X4RS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 33) + return OPCODE_AE_MULSSF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 34) + return OPCODE_AE_MULSSF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 35) + return OPCODE_AE_MULSSF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 36) + return OPCODE_AE_MULSSF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 37) + return OPCODE_AE_MULZAAAA2Q16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 38) + return OPCODE_AE_MULZAAAA2Q32X16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 39) + return OPCODE_AE_MULZAAF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 40) + return OPCODE_AE_MULZAAF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 41) + return OPCODE_AE_MULZAAF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 42) + return OPCODE_AE_MULZAAF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 43) + return OPCODE_AE_MULZASF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 44) + return OPCODE_AE_MULZASF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 45) + return OPCODE_AE_MULZASF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 46) + return OPCODE_AE_MULZASF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 47) + return OPCODE_AE_MULZSAF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 48) + return OPCODE_AE_MULZSAF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 49) + return OPCODE_AE_MULZSAF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 50) + return OPCODE_AE_MULZSAF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 51) + return OPCODE_AE_MULZSSF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 52) + return OPCODE_AE_MULZSSF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 53) + return OPCODE_AE_MULZSSF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 54) + return OPCODE_AE_MULZSSF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_19_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SEL16I; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1860 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SHORTSWAP; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1572 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1540 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1828 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1796 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 611 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_TRUNCP24Q48X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1892 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_TRUNCP16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1764 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MOV; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1732 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1700 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1668 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1636 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1604 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1924 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_TRUNCQ32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 515 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_AND; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 547 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_NAND; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 579 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_OR; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 643 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_XOR; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 431202) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 432226) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_19_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 4 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SEXT32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_DSEL8X8; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 13 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 34) + return OPCODE_ADD_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 13 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 66) + return OPCODE_SUB_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3588 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_NEXP01_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2564 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MKSADJ_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 428130) + return OPCODE_MKDADJ_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1988 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_DIV0_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2628 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_SQRT0_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2596 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_RECIP0_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3620 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_RSQRT0_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 427106) + return OPCODE_ADDEXP_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 426082) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 867 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MIN_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 771 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MAX_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3652 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ABS_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2724 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_NEG_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3684 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CONJC_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3716 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MULJC_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1956 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CLSFY_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 835 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MINNUM_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 739 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MAXNUM_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 9 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 12 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 13 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 675 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_FREXP_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2020 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 803 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 707 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_18_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_BMAXNUM_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_18_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_BMINNUM_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_18_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_BMAXNUMABS_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_18_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_BMINNUMABS_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 8 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3748 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ABS_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 430178) + return OPCODE_ADDEXP_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 429154) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2756 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CLSFY_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2660 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CONJC_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 995 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MIN_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 931 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MAX_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 963 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MINNUM_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 899 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MAXNUM_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2692 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MULJC_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3780 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_NEG_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 4 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 7 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 5 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 6 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 648290) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 38) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 37) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 39) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 40) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 41) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 30816) + return OPCODE_AE_ADDRNG32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 17506) + return OPCODE_AE_SUBRNG32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 31841) + return OPCODE_AE_SAT16X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 24673) + return OPCODE_AE_ROUND32X2F64SSYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 23649) + return OPCODE_AE_ROUND32X2F64SASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 22625) + return OPCODE_AE_ROUND32X2F48SSYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 21601) + return OPCODE_AE_ROUND32X2F48SASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 18529) + return OPCODE_AE_ROUND16X4F32SSYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 17505) + return OPCODE_AE_ROUND16X4F32SASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 20577) + return OPCODE_AE_ROUND24X2F48SSYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 19553) + return OPCODE_AE_ROUND24X2F48SASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 30817) + return OPCODE_AE_ROUNDSP16Q48X2SYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 29793) + return OPCODE_AE_ROUNDSP16Q48X2ASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 12385) + return OPCODE_AE_MINABS32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 7265) + return OPCODE_AE_MAXABS32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26722) + return OPCODE_AE_ROUNDSP16F24SYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26722) + return OPCODE_AE_ROUNDSP16F24ASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 1008738) + return OPCODE_AE_SAT48S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 1041506) + return OPCODE_AE_SATQ56S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 975970) + return OPCODE_AE_SAT24S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 13409) + return OPCODE_AE_MINABS64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 8289) + return OPCODE_AE_MAXABS64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26722) + return OPCODE_AE_ROUNDSQ32F48SYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26722) + return OPCODE_AE_ROUNDSQ32F48ASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 23648) + return OPCODE_AE_ADD32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 10338) + return OPCODE_AE_SUB32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 97) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 15458) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 20576) + return OPCODE_AE_ADD16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 7266) + return OPCODE_AE_SUB16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26720) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 3169) + return OPCODE_AE_ADDSUB32_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 746594) + return OPCODE_AE_NEG32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 255074) + return OPCODE_AE_ABS32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 812130) + return OPCODE_AE_NEG32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 22624) + return OPCODE_AE_ADD24S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 9314) + return OPCODE_AE_SUB24S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 24672) + return OPCODE_AE_ADD32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 11362) + return OPCODE_AE_SUB32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 1121) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 16482) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 21600) + return OPCODE_AE_ADD16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 8290) + return OPCODE_AE_SUB16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 25696) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 2145) + return OPCODE_AE_ADDSUB32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 713826) + return OPCODE_AE_NEG24S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 222306) + return OPCODE_AE_ABS24S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 779362) + return OPCODE_AE_NEG32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 287842) + return OPCODE_AE_ABS32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 681058) + return OPCODE_AE_NEG16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 189538) + return OPCODE_AE_ABS16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 156770) + return OPCODE_AE_ABS16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 10337) + return OPCODE_AE_MIN32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 5217) + return OPCODE_AE_MAX32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 15457) + return OPCODE_AE_MINMAX32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 14433) + return OPCODE_AE_MINMAX16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 9313) + return OPCODE_AE_MIN16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 4193) + return OPCODE_AE_MAX16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 27744) + return OPCODE_AE_ADD64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 12386) + return OPCODE_AE_SUB64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 844898) + return OPCODE_AE_NEG64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 320610) + return OPCODE_AE_ABS64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 31840) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 18530) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 28768) + return OPCODE_AE_ADD64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 13410) + return OPCODE_AE_SUB64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 943202) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 418914) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 877666) + return OPCODE_AE_NEG64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 353378) + return OPCODE_AE_ABS64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 6241) + return OPCODE_AE_MAX64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 11361) + return OPCODE_AE_MIN64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 615522) + return OPCODE_AE_MUL16JS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 517218) + return OPCODE_AE_CONJ16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 549986) + return OPCODE_AE_DIV64D32_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 582754) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_17_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 25698) + return OPCODE_AE_SAT64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 386146) + return OPCODE_AE_ABS8S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 910434) + return OPCODE_AE_NEG8S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 29792) + return OPCODE_AE_ADD8S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 14434) + return OPCODE_AE_SUB8S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 3170) + return OPCODE_AE_SATU16X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 98) + return OPCODE_AE_SAT32X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 4194) + return OPCODE_AE_SATU32X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 2146) + return OPCODE_AE_SAT8X8X16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 6242) + return OPCODE_AE_SATU8X8X16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 1122) + return OPCODE_AE_SAT8X4X32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 5218) + return OPCODE_AE_SATU8X4X32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 28769) + return OPCODE_AE_ROUND8X8F16SSYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 27745) + return OPCODE_AE_ROUND8X8F16SASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26721) + return OPCODE_AE_ROUND8X4F32SSYM_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 25697) + return OPCODE_AE_ROUND8X4F32SASYM_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 36) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 46) + return OPCODE_AE_ADDW8; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 44) + return OPCODE_AE_ADDW16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 45) + return OPCODE_AE_ADDW32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 50) + return OPCODE_AE_SUBW8; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 48) + return OPCODE_AE_SUBW16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 49) + return OPCODE_AE_SUBW32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 34) + return OPCODE_AE_ACCW8; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 32) + return OPCODE_AE_ACCW16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 33) + return OPCODE_AE_ACCW32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 47) + return OPCODE_AE_ADDW8U; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 51) + return OPCODE_AE_SUBW8U; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 35) + return OPCODE_AE_ACCW8U; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULFD16X16X4RAS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 54) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 53) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 55) + return OPCODE_AE_SEL8X8I; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_12_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 96) + return OPCODE_AE_BMAX8X8_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_12_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 96) + return OPCODE_AE_BMAX8X8_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_12_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 96) + return OPCODE_AE_BMIN8X8_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_12_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 96) + return OPCODE_AE_BMIN8X8_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 451682) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 484450) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 16481) + return OPCODE_AE_MOVNEG32S_T; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 16480) + return OPCODE_AE_EXPADD16_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 18528) + return OPCODE_AE_EXPSUB16_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 17504) + return OPCODE_AE_EXPADD16_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 19552) + return OPCODE_AE_EXPSUB16_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 42) + return OPCODE_AE_ADDCEXP32_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 43) + return OPCODE_AE_ADDCEXP32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 63) + return OPCODE_MUL_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 60) + return OPCODE_MADD_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 62) + return OPCODE_MSUB_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 61) + return OPCODE_MSUBN_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 59) + return OPCODE_MADDN_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 58) + return OPCODE_DIVN_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_1_Slot_ae_slot3_get (insn) == 28) + return OPCODE_MULMUX_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_9_3_Slot_ae_slot3_get (insn) == 7) + return OPCODE_MADDMUX_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 52) + return OPCODE_MADDA_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 19554) + return OPCODE_ADD_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 24674) + return OPCODE_SUB_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 23650) + return OPCODE_MUL_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 20578) + return OPCODE_MADD_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 22626) + return OPCODE_MSUB_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 21602) + return OPCODE_MSUBN_H; + return XTENSA_UNDEFINED; +} + + +/* Instruction slots. */ + +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = (insn[0] & 0xffffff); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_ae_format_Format_ae_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x300) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xc) | (((insn[0] & 0x18000000) >> 27) << 2); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf0) >> 4) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf000) >> 12) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | ((insn[1] & 0x1) << 12); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[0] & 0xc00) >> 10) << 13); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[1] & 0x6) >> 1) << 15); + slotbuf[0] = (slotbuf[0] & ~0x20000) | (((insn[2] & 0x1000000) >> 24) << 17); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x10000) >> 16) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[1] & 0x800000) >> 23) << 19); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[0] & 0x4000000) >> 26) << 20); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[1] & 0x1000000) >> 24) << 21); + slotbuf[0] = (slotbuf[0] & ~0xc00000) | (((insn[2] & 0x6000000) >> 25) << 22); + slotbuf[0] = (slotbuf[0] & ~0x7000000) | (((insn[2] & 0xe00000) >> 21) << 24); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x2000) >> 13) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x10000000) >> 28) << 28); +} + +static void +Slot_ae_format_Format_ae_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x300) | ((slotbuf[0] & 0x3) << 8); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0xc) >> 2) << 27); + insn[0] = (insn[0] & ~0xf0) | (((slotbuf[0] & 0xf0) >> 4) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0xf00) >> 8) << 12); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x1000) >> 12); + insn[0] = (insn[0] & ~0xc00) | (((slotbuf[0] & 0x6000) >> 13) << 10); + insn[1] = (insn[1] & ~0x6) | (((slotbuf[0] & 0x18000) >> 15) << 1); + insn[2] = (insn[2] & ~0x1000000) | (((slotbuf[0] & 0x20000) >> 17) << 24); + insn[2] = (insn[2] & ~0x10000) | (((slotbuf[0] & 0x40000) >> 18) << 16); + insn[1] = (insn[1] & ~0x800000) | (((slotbuf[0] & 0x80000) >> 19) << 23); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x100000) >> 20) << 26); + insn[1] = (insn[1] & ~0x1000000) | (((slotbuf[0] & 0x200000) >> 21) << 24); + insn[2] = (insn[2] & ~0x6000000) | (((slotbuf[0] & 0xc00000) >> 22) << 25); + insn[2] = (insn[2] & ~0xe00000) | (((slotbuf[0] & 0x7000000) >> 24) << 21); + insn[3] = (insn[3] & ~0x2000) | (((slotbuf[0] & 0x8000000) >> 27) << 13); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[0] & 0x10000000) >> 28) << 28); +} + +static void +Slot_ae_format_Format_ae_slot1_72_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[2] & 0xf8000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[2] & 0x60000) >> 17) << 18); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[3] & 0x7c000) >> 14) << 20); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x20000000) >> 29) << 25); +} + +static void +Slot_ae_format_Format_ae_slot1_72_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x1f00) >> 8) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[2] = (insn[2] & ~0x60000) | (((slotbuf[0] & 0xc0000) >> 18) << 17); + insn[3] = (insn[3] & ~0x7c000) | (((slotbuf[0] & 0x1f00000) >> 20) << 14); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x2000000) >> 25) << 29); +} + +static void +Slot_ae_format_Format_ae_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x1ff8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0xffc00) | (((insn[0] & 0x3ff0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[3] & 0x3e0) >> 5) << 20); + slotbuf[0] = (slotbuf[0] & ~0xe000000) | (((insn[3] & 0x380000) >> 19) << 25); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x40000000) >> 30) << 28); +} + +static void +Slot_ae_format_Format_ae_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x1ff8) | ((slotbuf[0] & 0x3ff) << 3); + insn[0] = (insn[0] & ~0x3ff0000) | (((slotbuf[0] & 0xffc00) >> 10) << 16); + insn[3] = (insn[3] & ~0x3e0) | (((slotbuf[0] & 0x1f00000) >> 20) << 5); + insn[3] = (insn[3] & ~0x380000) | (((slotbuf[0] & 0xe000000) >> 25) << 19); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x10000000) >> 28) << 30); +} + +static void +Slot_ae_format_Format_ae_slot3_45_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xfe000000) >> 25); + slotbuf[0] = (slotbuf[0] & ~0x7f80) | ((insn[2] & 0xff) << 7); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x180000) >> 19) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[3] & 0x1c00) >> 10) << 17); + slotbuf[0] = (slotbuf[0] & ~0x3ff00000) | (((insn[1] & 0x7fe000) >> 13) << 20); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0xc00000) >> 22) << 30); + slotbuf[1] = ((insn[3] & 0xf000000) >> 24); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x80000000) >> 31) << 4); +} + +static void +Slot_ae_format_Format_ae_slot3_45_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xfe000000) | ((slotbuf[0] & 0x7f) << 25); + insn[2] = (insn[2] & ~0xff) | ((slotbuf[0] & 0x7f80) >> 7); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x18000) >> 15) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0xe0000) >> 17) << 10); + insn[1] = (insn[1] & ~0x7fe000) | (((slotbuf[0] & 0x3ff00000) >> 20) << 13); + insn[3] = (insn[3] & ~0xc00000) | (((slotbuf[0] & 0xc0000000) >> 30) << 22); + insn[3] = (insn[3] & ~0xf000000) | ((slotbuf[1] & 0xf) << 24); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x10) >> 4) << 31); +} + +static void +Slot_ae_format_2_Format_ae2_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xff0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[0] & 0x18000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1c00) | ((insn[1] & 0x7) << 10); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x1000000) >> 24) << 13); + slotbuf[0] = (slotbuf[0] & ~0x1c000) | (((insn[0] & 0xe000) >> 13) << 14); + slotbuf[0] = (slotbuf[0] & ~0x20000) | (((insn[0] & 0x4000000) >> 26) << 17); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x800000) >> 23) << 18); + slotbuf[0] = (slotbuf[0] & ~0x180000) | (((insn[2] & 0x30000) >> 16) << 19); + slotbuf[0] = (slotbuf[0] & ~0xe00000) | (((insn[2] & 0x7000000) >> 24) << 21); + slotbuf[0] = (slotbuf[0] & ~0x7000000) | (((insn[1] & 0xe00000) >> 21) << 24); + slotbuf[0] = (slotbuf[0] & ~0x18000000) | (((insn[1] & 0x6000000) >> 25) << 27); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[2] & 0x100) >> 8) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[2] & 0x200) >> 9) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[2] & 0x400) >> 10) << 31); + slotbuf[1] = ((insn[2] & 0x800) >> 11); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[2] & 0x1000) >> 12) << 1); + slotbuf[1] = (slotbuf[1] & ~0x4) | (((insn[2] & 0x2000) >> 13) << 2); + slotbuf[1] = (slotbuf[1] & ~0x8) | (((insn[2] & 0x4000) >> 14) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[2] & 0x8000) >> 15) << 4); + slotbuf[1] = (slotbuf[1] & ~0x20) | (((insn[2] & 0x40000) >> 18) << 5); + slotbuf[1] = (slotbuf[1] & ~0x40) | (((insn[2] & 0x80000) >> 19) << 6); + slotbuf[1] = (slotbuf[1] & ~0x80) | (((insn[2] & 0x100000) >> 20) << 7); + slotbuf[1] = (slotbuf[1] & ~0x100) | (((insn[2] & 0x200000) >> 21) << 8); +} + +static void +Slot_ae_format_2_Format_ae2_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff0) | ((slotbuf[0] & 0xff) << 4); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x300) >> 8) << 27); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x1c00) >> 10); + insn[1] = (insn[1] & ~0x1000000) | (((slotbuf[0] & 0x2000) >> 13) << 24); + insn[0] = (insn[0] & ~0xe000) | (((slotbuf[0] & 0x1c000) >> 14) << 13); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x20000) >> 17) << 26); + insn[2] = (insn[2] & ~0x800000) | (((slotbuf[0] & 0x40000) >> 18) << 23); + insn[2] = (insn[2] & ~0x30000) | (((slotbuf[0] & 0x180000) >> 19) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0xe00000) >> 21) << 24); + insn[1] = (insn[1] & ~0xe00000) | (((slotbuf[0] & 0x7000000) >> 24) << 21); + insn[1] = (insn[1] & ~0x6000000) | (((slotbuf[0] & 0x18000000) >> 27) << 25); + insn[2] = (insn[2] & ~0x100) | (((slotbuf[0] & 0x20000000) >> 29) << 8); + insn[2] = (insn[2] & ~0x200) | (((slotbuf[0] & 0x40000000) >> 30) << 9); + insn[2] = (insn[2] & ~0x400) | (((slotbuf[0] & 0x80000000) >> 31) << 10); + insn[2] = (insn[2] & ~0x800) | ((slotbuf[1] & 0x1) << 11); + insn[2] = (insn[2] & ~0x1000) | (((slotbuf[1] & 0x2) >> 1) << 12); + insn[2] = (insn[2] & ~0x2000) | (((slotbuf[1] & 0x4) >> 2) << 13); + insn[2] = (insn[2] & ~0x4000) | (((slotbuf[1] & 0x8) >> 3) << 14); + insn[2] = (insn[2] & ~0x8000) | (((slotbuf[1] & 0x10) >> 4) << 15); + insn[2] = (insn[2] & ~0x40000) | (((slotbuf[1] & 0x20) >> 5) << 18); + insn[2] = (insn[2] & ~0x80000) | (((slotbuf[1] & 0x40) >> 6) << 19); + insn[2] = (insn[2] & ~0x100000) | (((slotbuf[1] & 0x80) >> 7) << 20); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[1] & 0x100) >> 8) << 21); +} + +static void +Slot_ae_format_2_Format_ae2_slot1_12_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x40000000) >> 30); + slotbuf[0] = (slotbuf[0] & ~0x2) | (((insn[1] & 0x20000000) >> 29) << 1); + slotbuf[0] = (slotbuf[0] & ~0xc) | (((insn[2] & 0x18000000) >> 27) << 2); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[1] & 0x80000000) >> 31) << 4); + slotbuf[0] = (slotbuf[0] & ~0xe0) | ((insn[2] & 0x7) << 5); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[2] & 0x60000000) >> 29) << 8); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | ((insn[3] & 0x1f) << 10); + slotbuf[0] = (slotbuf[0] & ~0x8000) | (((insn[0] & 0x1000) >> 12) << 15); + slotbuf[0] = (slotbuf[0] & ~0x70000) | (((insn[1] & 0xe000) >> 13) << 16); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[2] & 0x80000000) >> 31) << 19); + slotbuf[0] = (slotbuf[0] & ~0x300000) | (((insn[1] & 0x18000000) >> 27) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1c00000) | (((insn[2] & 0x38) >> 3) << 22); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[2] & 0x400000) >> 22) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x400) >> 10) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x800) >> 11) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x1000) >> 12) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x2000) >> 13) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x4000) >> 14) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x8000) >> 15) << 31); + slotbuf[1] = ((insn[3] & 0x10000) >> 16); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[3] & 0x20000) >> 17) << 1); + slotbuf[1] = (slotbuf[1] & ~0x4) | (((insn[3] & 0x40000) >> 18) << 2); + slotbuf[1] = (slotbuf[1] & ~0x8) | (((insn[3] & 0x80000) >> 19) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x100000) >> 20) << 4); +} + +static void +Slot_ae_format_2_Format_ae2_slot1_12_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x40000000) | ((slotbuf[0] & 0x1) << 30); + insn[1] = (insn[1] & ~0x20000000) | (((slotbuf[0] & 0x2) >> 1) << 29); + insn[2] = (insn[2] & ~0x18000000) | (((slotbuf[0] & 0xc) >> 2) << 27); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x10) >> 4) << 31); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0xe0) >> 5); + insn[2] = (insn[2] & ~0x60000000) | (((slotbuf[0] & 0x300) >> 8) << 29); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x7c00) >> 10); + insn[0] = (insn[0] & ~0x1000) | (((slotbuf[0] & 0x8000) >> 15) << 12); + insn[1] = (insn[1] & ~0xe000) | (((slotbuf[0] & 0x70000) >> 16) << 13); + insn[2] = (insn[2] & ~0x80000000) | (((slotbuf[0] & 0x80000) >> 19) << 31); + insn[1] = (insn[1] & ~0x18000000) | (((slotbuf[0] & 0x300000) >> 20) << 27); + insn[2] = (insn[2] & ~0x38) | (((slotbuf[0] & 0x1c00000) >> 22) << 3); + insn[2] = (insn[2] & ~0x400000) | (((slotbuf[0] & 0x2000000) >> 25) << 22); + insn[3] = (insn[3] & ~0x400) | (((slotbuf[0] & 0x4000000) >> 26) << 10); + insn[3] = (insn[3] & ~0x800) | (((slotbuf[0] & 0x8000000) >> 27) << 11); + insn[3] = (insn[3] & ~0x1000) | (((slotbuf[0] & 0x10000000) >> 28) << 12); + insn[3] = (insn[3] & ~0x2000) | (((slotbuf[0] & 0x20000000) >> 29) << 13); + insn[3] = (insn[3] & ~0x4000) | (((slotbuf[0] & 0x40000000) >> 30) << 14); + insn[3] = (insn[3] & ~0x8000) | (((slotbuf[0] & 0x80000000) >> 31) << 15); + insn[3] = (insn[3] & ~0x10000) | ((slotbuf[1] & 0x1) << 16); + insn[3] = (insn[3] & ~0x20000) | (((slotbuf[1] & 0x2) >> 1) << 17); + insn[3] = (insn[3] & ~0x40000) | (((slotbuf[1] & 0x4) >> 2) << 18); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[1] & 0x8) >> 3) << 19); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[1] & 0x10) >> 4) << 20); +} + +static void +Slot_ae_format_2_Format_ae2_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xf8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0x3e0) | (((insn[0] & 0x1f0000) >> 16) << 5); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[1] & 0x1f00) >> 8) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[3] & 0x3e0) >> 5) << 15); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[0] & 0x3e00000) >> 21) << 20); + slotbuf[0] = (slotbuf[0] & ~0x3e000000) | (((insn[1] & 0x1f0000) >> 16) << 25); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[2] & 0xc0) >> 6) << 30); + slotbuf[1] = ((insn[3] & 0x200000) >> 21); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[3] & 0x400000) >> 22) << 1); + slotbuf[1] = (slotbuf[1] & ~0x4) | (((insn[3] & 0x800000) >> 23) << 2); + slotbuf[1] = (slotbuf[1] & ~0x8) | (((insn[3] & 0x1000000) >> 24) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x2000000) >> 25) << 4); + slotbuf[1] = (slotbuf[1] & ~0x20) | (((insn[3] & 0x4000000) >> 26) << 5); + slotbuf[1] = (slotbuf[1] & ~0x40) | (((insn[3] & 0x8000000) >> 27) << 6); + slotbuf[1] = (slotbuf[1] & ~0x80) | (((insn[3] & 0x10000000) >> 28) << 7); + slotbuf[1] = (slotbuf[1] & ~0x100) | (((insn[3] & 0x20000000) >> 29) << 8); + slotbuf[1] = (slotbuf[1] & ~0x200) | (((insn[3] & 0x40000000) >> 30) << 9); + slotbuf[1] = (slotbuf[1] & ~0x400) | (((insn[3] & 0x80000000) >> 31) << 10); +} + +static void +Slot_ae_format_2_Format_ae2_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xf8) | ((slotbuf[0] & 0x1f) << 3); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0x3e0) >> 5) << 16); + insn[1] = (insn[1] & ~0x1f00) | (((slotbuf[0] & 0x7c00) >> 10) << 8); + insn[3] = (insn[3] & ~0x3e0) | (((slotbuf[0] & 0xf8000) >> 15) << 5); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x1f00000) >> 20) << 21); + insn[1] = (insn[1] & ~0x1f0000) | (((slotbuf[0] & 0x3e000000) >> 25) << 16); + insn[2] = (insn[2] & ~0xc0) | (((slotbuf[0] & 0xc0000000) >> 30) << 6); + insn[3] = (insn[3] & ~0x200000) | ((slotbuf[1] & 0x1) << 21); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[1] & 0x2) >> 1) << 22); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[1] & 0x4) >> 2) << 23); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[1] & 0x8) >> 3) << 24); + insn[3] = (insn[3] & ~0x2000000) | (((slotbuf[1] & 0x10) >> 4) << 25); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[1] & 0x20) >> 5) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[1] & 0x40) >> 6) << 27); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[1] & 0x80) >> 7) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[1] & 0x100) >> 8) << 29); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[1] & 0x200) >> 9) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x400) >> 10) << 31); +} + +static void +Slot_ae_format_3_Format_ae3_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xf00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf0) >> 4) << 4); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[0] & 0x18000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1c00) | ((insn[1] & 0x7) << 10); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x1000000) >> 24) << 13); + slotbuf[0] = (slotbuf[0] & ~0x1c000) | (((insn[0] & 0xe000) >> 13) << 14); + slotbuf[0] = (slotbuf[0] & ~0x20000) | (((insn[0] & 0x4000000) >> 26) << 17); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[1] & 0x6000) >> 13) << 18); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[0] & 0x3e00000) >> 21) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1e000000) | (((insn[1] & 0x78) >> 3) << 25); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[1] & 0x80000) >> 19) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[1] & 0x100000) >> 20) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[1] & 0x200000) >> 21) << 31); + slotbuf[1] = ((insn[1] & 0x400000) >> 22); +} + +static void +Slot_ae_format_3_Format_ae3_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf00) | ((slotbuf[0] & 0xf) << 8); + insn[0] = (insn[0] & ~0xf0) | (((slotbuf[0] & 0xf0) >> 4) << 4); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x300) >> 8) << 27); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x1c00) >> 10); + insn[1] = (insn[1] & ~0x1000000) | (((slotbuf[0] & 0x2000) >> 13) << 24); + insn[0] = (insn[0] & ~0xe000) | (((slotbuf[0] & 0x1c000) >> 14) << 13); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x20000) >> 17) << 26); + insn[1] = (insn[1] & ~0x6000) | (((slotbuf[0] & 0xc0000) >> 18) << 13); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x1f00000) >> 20) << 21); + insn[1] = (insn[1] & ~0x78) | (((slotbuf[0] & 0x1e000000) >> 25) << 3); + insn[1] = (insn[1] & ~0x80000) | (((slotbuf[0] & 0x20000000) >> 29) << 19); + insn[1] = (insn[1] & ~0x100000) | (((slotbuf[0] & 0x40000000) >> 30) << 20); + insn[1] = (insn[1] & ~0x200000) | (((slotbuf[0] & 0x80000000) >> 31) << 21); + insn[1] = (insn[1] & ~0x400000) | ((slotbuf[1] & 0x1) << 22); +} + +static void +Slot_ae_format_3_Format_ae3_slot1_12_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x1000) >> 12); + slotbuf[0] = (slotbuf[0] & ~0xe) | (((insn[1] & 0xe000000) >> 25) << 1); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[1] & 0xf00) >> 8) << 4); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[1] & 0x30000000) >> 28) << 8); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x1f0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x8000) | (((insn[1] & 0x80) >> 7) << 15); + slotbuf[0] = (slotbuf[0] & ~0x10000) | (((insn[1] & 0x1000) >> 12) << 16); + slotbuf[0] = (slotbuf[0] & ~0x1e0000) | (((insn[1] & 0x78000) >> 15) << 17); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[1] & 0x800000) >> 23) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[1] & 0x40000000) >> 30) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[1] & 0x80000000) >> 31) << 23); +} + +static void +Slot_ae_format_3_Format_ae3_slot1_12_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x1000) | ((slotbuf[0] & 0x1) << 12); + insn[1] = (insn[1] & ~0xe000000) | (((slotbuf[0] & 0xe) >> 1) << 25); + insn[1] = (insn[1] & ~0xf00) | (((slotbuf[0] & 0xf0) >> 4) << 8); + insn[1] = (insn[1] & ~0x30000000) | (((slotbuf[0] & 0x300) >> 8) << 28); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0x7c00) >> 10) << 16); + insn[1] = (insn[1] & ~0x80) | (((slotbuf[0] & 0x8000) >> 15) << 7); + insn[1] = (insn[1] & ~0x1000) | (((slotbuf[0] & 0x10000) >> 16) << 12); + insn[1] = (insn[1] & ~0x78000) | (((slotbuf[0] & 0x1e0000) >> 17) << 15); + insn[1] = (insn[1] & ~0x800000) | (((slotbuf[0] & 0x200000) >> 21) << 23); + insn[1] = (insn[1] & ~0x40000000) | (((slotbuf[0] & 0x400000) >> 22) << 30); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x800000) >> 23) << 31); +} + +static void +Slot_ae_format_5_Format_ae5_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xf00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf0) >> 4) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf000) >> 12) << 8); + slotbuf[0] = (slotbuf[0] & ~0x7000) | (((insn[0] & 0x1c000000) >> 26) << 12); + slotbuf[0] = (slotbuf[0] & ~0x38000) | ((insn[1] & 0x7) << 15); + slotbuf[0] = (slotbuf[0] & ~0x1ffc0000) | (((insn[1] & 0xffe000) >> 13) << 18); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[1] & 0x40000000) >> 30) << 29); +} + +static void +Slot_ae_format_5_Format_ae5_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf00) | ((slotbuf[0] & 0xf) << 8); + insn[0] = (insn[0] & ~0xf0) | (((slotbuf[0] & 0xf0) >> 4) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0xf00) >> 8) << 12); + insn[0] = (insn[0] & ~0x1c000000) | (((slotbuf[0] & 0x7000) >> 12) << 26); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x38000) >> 15); + insn[1] = (insn[1] & ~0xffe000) | (((slotbuf[0] & 0x1ffc0000) >> 18) << 13); + insn[1] = (insn[1] & ~0x40000000) | (((slotbuf[0] & 0x20000000) >> 29) << 30); +} + +static void +Slot_ae_format_5_Format_ae5_slot1_56_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x1000000) >> 24); + slotbuf[0] = (slotbuf[0] & ~0x2) | (((insn[1] & 0x80000000) >> 31) << 1); +} + +static void +Slot_ae_format_5_Format_ae5_slot1_56_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x1000000) | ((slotbuf[0] & 0x1) << 24); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x2) >> 1) << 31); +} + +static void +Slot_ae_format_5_Format_ae5_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x1ff8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0xffc00) | (((insn[0] & 0x3ff0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[1] & 0x3e000000) >> 25) << 20); +} + +static void +Slot_ae_format_5_Format_ae5_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x1ff8) | ((slotbuf[0] & 0x3ff) << 3); + insn[0] = (insn[0] & ~0x3ff0000) | (((slotbuf[0] & 0xffc00) >> 10) << 16); + insn[1] = (insn[1] & ~0x3e000000) | (((slotbuf[0] & 0x1f00000) >> 20) << 25); +} + +static void +Slot_ae_format_6_Format_ae6_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xf0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[2] & 0x800000) >> 23) << 4); + slotbuf[0] = (slotbuf[0] & ~0x60) | (((insn[0] & 0x18000000) >> 27) << 5); + slotbuf[0] = (slotbuf[0] & ~0x380) | ((insn[1] & 0x7) << 7); + slotbuf[0] = (slotbuf[0] & ~0x3c00) | (((insn[0] & 0xf000) >> 12) << 10); + slotbuf[0] = (slotbuf[0] & ~0x4000) | (((insn[0] & 0x4000000) >> 26) << 14); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x30000) >> 16) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[2] & 0x7000000) >> 24) << 17); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[1] & 0x1000) >> 12) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1e00000) | (((insn[2] & 0xf00) >> 8) << 21); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x8000) >> 15) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x10000) >> 16) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x20000) >> 17) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x40000) >> 18) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x80000) >> 19) << 29); +} + +static void +Slot_ae_format_6_Format_ae6_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0) | ((slotbuf[0] & 0xf) << 4); + insn[2] = (insn[2] & ~0x800000) | (((slotbuf[0] & 0x10) >> 4) << 23); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x60) >> 5) << 27); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x380) >> 7); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0x3c00) >> 10) << 12); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x4000) >> 14) << 26); + insn[2] = (insn[2] & ~0x30000) | (((slotbuf[0] & 0x18000) >> 15) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0xe0000) >> 17) << 24); + insn[1] = (insn[1] & ~0x1000) | (((slotbuf[0] & 0x100000) >> 20) << 12); + insn[2] = (insn[2] & ~0xf00) | (((slotbuf[0] & 0x1e00000) >> 21) << 8); + insn[3] = (insn[3] & ~0x8000) | (((slotbuf[0] & 0x2000000) >> 25) << 15); + insn[3] = (insn[3] & ~0x10000) | (((slotbuf[0] & 0x4000000) >> 26) << 16); + insn[3] = (insn[3] & ~0x20000) | (((slotbuf[0] & 0x8000000) >> 27) << 17); + insn[3] = (insn[3] & ~0x40000) | (((slotbuf[0] & 0x10000000) >> 28) << 18); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[0] & 0x20000000) >> 29) << 19); +} + +static void +Slot_ae_format_6_Format_ae6_slot1_57_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xc0000000) >> 30); + slotbuf[0] = (slotbuf[0] & ~0x1c) | ((insn[2] & 0x7) << 2); + slotbuf[0] = (slotbuf[0] & ~0x3e0) | (((insn[1] & 0x3e000000) >> 25) << 5); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[2] & 0xf8000000) >> 27) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | ((insn[3] & 0x1f) << 15); + slotbuf[0] = (slotbuf[0] & ~0xf00000) | (((insn[2] & 0xf000) >> 12) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x100000) >> 20) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x200000) >> 21) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x400000) >> 22) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x800000) >> 23) << 27); +} + +static void +Slot_ae_format_6_Format_ae6_slot1_57_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xc0000000) | ((slotbuf[0] & 0x3) << 30); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0x1c) >> 2); + insn[1] = (insn[1] & ~0x3e000000) | (((slotbuf[0] & 0x3e0) >> 5) << 25); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x7c00) >> 10) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0xf8000) >> 15); + insn[2] = (insn[2] & ~0xf000) | (((slotbuf[0] & 0xf00000) >> 20) << 12); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[0] & 0x1000000) >> 24) << 20); + insn[3] = (insn[3] & ~0x200000) | (((slotbuf[0] & 0x2000000) >> 25) << 21); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[0] & 0x4000000) >> 26) << 22); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[0] & 0x8000000) >> 27) << 23); +} + +static void +Slot_ae_format_6_Format_ae6_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xf8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0x7fe0) | (((insn[0] & 0x3ff0000) >> 16) << 5); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[3] & 0x3e0) >> 5) << 15); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[2] & 0x40000) >> 18) << 20); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x1000000) >> 24) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x2000000) >> 25) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x4000000) >> 26) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x8000000) >> 27) << 24); +} + +static void +Slot_ae_format_6_Format_ae6_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xf8) | ((slotbuf[0] & 0x1f) << 3); + insn[0] = (insn[0] & ~0x3ff0000) | (((slotbuf[0] & 0x7fe0) >> 5) << 16); + insn[3] = (insn[3] & ~0x3e0) | (((slotbuf[0] & 0xf8000) >> 15) << 5); + insn[2] = (insn[2] & ~0x40000) | (((slotbuf[0] & 0x100000) >> 20) << 18); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x200000) >> 21) << 24); + insn[3] = (insn[3] & ~0x2000000) | (((slotbuf[0] & 0x400000) >> 22) << 25); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x800000) >> 23) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x1000000) >> 24) << 27); +} + +static void +Slot_ae_format_6_Format_ae6_slot3_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x3e000) >> 13); + slotbuf[0] = (slotbuf[0] & ~0x60) | (((insn[2] & 0x180000) >> 19) << 5); + slotbuf[0] = (slotbuf[0] & ~0x380) | (((insn[3] & 0x1c00) >> 10) << 7); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[2] & 0xf8) >> 3) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[1] & 0x7c0000) >> 18) << 15); + slotbuf[0] = (slotbuf[0] & ~0x700000) | (((insn[0] & 0x700) >> 8) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1800000) | (((insn[1] & 0x1800000) >> 23) << 23); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[0] & 0x800) >> 11) << 25); + slotbuf[0] = (slotbuf[0] & ~0x3c000000) | (((insn[1] & 0xf00) >> 8) << 26); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[2] & 0x600000) >> 21) << 30); + slotbuf[1] = ((insn[3] & 0x6000) >> 13); + slotbuf[1] = (slotbuf[1] & ~0x4) | (((insn[3] & 0x10000000) >> 28) << 2); + slotbuf[1] = (slotbuf[1] & ~0x8) | (((insn[3] & 0x20000000) >> 29) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x40000000) >> 30) << 4); + slotbuf[1] = (slotbuf[1] & ~0x20) | (((insn[3] & 0x80000000) >> 31) << 5); +} + +static void +Slot_ae_format_6_Format_ae6_slot3_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x3e000) | ((slotbuf[0] & 0x1f) << 13); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x60) >> 5) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0x380) >> 7) << 10); + insn[2] = (insn[2] & ~0xf8) | (((slotbuf[0] & 0x7c00) >> 10) << 3); + insn[1] = (insn[1] & ~0x7c0000) | (((slotbuf[0] & 0xf8000) >> 15) << 18); + insn[0] = (insn[0] & ~0x700) | (((slotbuf[0] & 0x700000) >> 20) << 8); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x1800000) >> 23) << 23); + insn[0] = (insn[0] & ~0x800) | (((slotbuf[0] & 0x2000000) >> 25) << 11); + insn[1] = (insn[1] & ~0xf00) | (((slotbuf[0] & 0x3c000000) >> 26) << 8); + insn[2] = (insn[2] & ~0x600000) | (((slotbuf[0] & 0xc0000000) >> 30) << 21); + insn[3] = (insn[3] & ~0x6000) | ((slotbuf[1] & 0x3) << 13); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[1] & 0x4) >> 2) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[1] & 0x8) >> 3) << 29); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[1] & 0x10) >> 4) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x20) >> 5) << 31); +} + +static void +Slot_ae_format_7_Format_ae7_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x3f0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x3c0) | (((insn[0] & 0xf000) >> 12) << 6); + slotbuf[0] = (slotbuf[0] & ~0x1c00) | (((insn[2] & 0xe00000) >> 21) << 10); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[2] & 0x30000) >> 16) << 13); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[2] & 0x7000000) >> 24) << 15); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[0] & 0xc00) >> 10) << 18); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[0] & 0x4000000) >> 26) << 20); + slotbuf[0] = (slotbuf[0] & ~0x600000) | (((insn[1] & 0x1800000) >> 23) << 21); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x20000000) >> 29) << 23); +} + +static void +Slot_ae_format_7_Format_ae7_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3f0) | ((slotbuf[0] & 0x3f) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0x3c0) >> 6) << 12); + insn[2] = (insn[2] & ~0xe00000) | (((slotbuf[0] & 0x1c00) >> 10) << 21); + insn[2] = (insn[2] & ~0x30000) | (((slotbuf[0] & 0x6000) >> 13) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0x38000) >> 15) << 24); + insn[0] = (insn[0] & ~0xc00) | (((slotbuf[0] & 0xc0000) >> 18) << 10); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x100000) >> 20) << 26); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x600000) >> 21) << 23); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x800000) >> 23) << 29); +} + +static void +Slot_ae_format_7_Format_ae7_slot1_72_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xf000) >> 12); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[2] & 0xf00) >> 8) << 4); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[2] & 0xf8000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x40000) >> 18) << 18); + slotbuf[0] = (slotbuf[0] & ~0x780000) | (((insn[3] & 0x1e000) >> 13) << 19); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x40000000) >> 30) << 23); +} + +static void +Slot_ae_format_7_Format_ae7_slot1_72_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xf000) | ((slotbuf[0] & 0xf) << 12); + insn[2] = (insn[2] & ~0xf00) | (((slotbuf[0] & 0xf0) >> 4) << 8); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x1f00) >> 8) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[2] = (insn[2] & ~0x40000) | (((slotbuf[0] & 0x40000) >> 18) << 18); + insn[3] = (insn[3] & ~0x1e000) | (((slotbuf[0] & 0x780000) >> 19) << 13); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x800000) >> 23) << 30); +} + +static void +Slot_ae_format_7_Format_ae7_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x1ff8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x3e00000) >> 21) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[0] & 0x1f0000) >> 16) << 15); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[3] & 0x3e0) >> 5) << 20); + slotbuf[0] = (slotbuf[0] & ~0x6000000) | (((insn[0] & 0x18000000) >> 27) << 25); + slotbuf[0] = (slotbuf[0] & ~0x38000000) | ((insn[1] & 0x7) << 27); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0x60000) >> 17) << 30); + slotbuf[1] = ((insn[3] & 0x780000) >> 19); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x80000000) >> 31) << 4); +} + +static void +Slot_ae_format_7_Format_ae7_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x1ff8) | ((slotbuf[0] & 0x3ff) << 3); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x7c00) >> 10) << 21); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0xf8000) >> 15) << 16); + insn[3] = (insn[3] & ~0x3e0) | (((slotbuf[0] & 0x1f00000) >> 20) << 5); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x6000000) >> 25) << 27); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x38000000) >> 27); + insn[3] = (insn[3] & ~0x60000) | (((slotbuf[0] & 0xc0000000) >> 30) << 17); + insn[3] = (insn[3] & ~0x780000) | ((slotbuf[1] & 0xf) << 19); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x10) >> 4) << 31); +} + +static void +Slot_ae_format_7_Format_ae7_slot3_45_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xfe000000) >> 25); + slotbuf[0] = (slotbuf[0] & ~0x7f80) | ((insn[2] & 0xff) << 7); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x180000) >> 19) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[3] & 0x1c00) >> 10) << 17); + slotbuf[0] = (slotbuf[0] & ~0x3ff00000) | (((insn[1] & 0x7fe000) >> 13) << 20); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0x1800000) >> 23) << 30); + slotbuf[1] = ((insn[3] & 0x1e000000) >> 25); +} + +static void +Slot_ae_format_7_Format_ae7_slot3_45_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xfe000000) | ((slotbuf[0] & 0x7f) << 25); + insn[2] = (insn[2] & ~0xff) | ((slotbuf[0] & 0x7f80) >> 7); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x18000) >> 15) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0xe0000) >> 17) << 10); + insn[1] = (insn[1] & ~0x7fe000) | (((slotbuf[0] & 0x3ff00000) >> 20) << 13); + insn[3] = (insn[3] & ~0x1800000) | (((slotbuf[0] & 0xc0000000) >> 30) << 23); + insn[3] = (insn[3] & ~0x1e000000) | ((slotbuf[1] & 0xf) << 25); +} + +static void +Slot_ae_format_8_Format_ae8_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xf0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x70) | (((insn[2] & 0x3800000) >> 23) << 4); + slotbuf[0] = (slotbuf[0] & ~0x80) | (((insn[0] & 0x2000) >> 13) << 7); + slotbuf[0] = (slotbuf[0] & ~0x100) | (((insn[0] & 0x100) >> 8) << 8); + slotbuf[0] = (slotbuf[0] & ~0x600) | (((insn[0] & 0x18000000) >> 27) << 9); + slotbuf[0] = (slotbuf[0] & ~0x800) | ((insn[1] & 0x1) << 11); + slotbuf[0] = (slotbuf[0] & ~0x3000) | (((insn[1] & 0x1800000) >> 23) << 12); + slotbuf[0] = (slotbuf[0] & ~0x4000) | (((insn[0] & 0x200) >> 9) << 14); + slotbuf[0] = (slotbuf[0] & ~0x8000) | (((insn[0] & 0x1000) >> 12) << 15); + slotbuf[0] = (slotbuf[0] & ~0x30000) | (((insn[0] & 0xc00) >> 10) << 16); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x10000) >> 16) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[2] & 0x200000) >> 21) << 19); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[1] & 0x1000) >> 12) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1e00000) | (((insn[1] & 0x1e000000) >> 25) << 21); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[2] & 0x400000) >> 22) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x10000) >> 16) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x20000) >> 17) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x40000) >> 18) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x80000) >> 19) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x100000) >> 20) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x200000) >> 21) << 31); +} + +static void +Slot_ae_format_8_Format_ae8_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0) | ((slotbuf[0] & 0xf) << 4); + insn[2] = (insn[2] & ~0x3800000) | (((slotbuf[0] & 0x70) >> 4) << 23); + insn[0] = (insn[0] & ~0x2000) | (((slotbuf[0] & 0x80) >> 7) << 13); + insn[0] = (insn[0] & ~0x100) | (((slotbuf[0] & 0x100) >> 8) << 8); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x600) >> 9) << 27); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x800) >> 11); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x3000) >> 12) << 23); + insn[0] = (insn[0] & ~0x200) | (((slotbuf[0] & 0x4000) >> 14) << 9); + insn[0] = (insn[0] & ~0x1000) | (((slotbuf[0] & 0x8000) >> 15) << 12); + insn[0] = (insn[0] & ~0xc00) | (((slotbuf[0] & 0x30000) >> 16) << 10); + insn[2] = (insn[2] & ~0x10000) | (((slotbuf[0] & 0x40000) >> 18) << 16); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[0] & 0x80000) >> 19) << 21); + insn[1] = (insn[1] & ~0x1000) | (((slotbuf[0] & 0x100000) >> 20) << 12); + insn[1] = (insn[1] & ~0x1e000000) | (((slotbuf[0] & 0x1e00000) >> 21) << 25); + insn[2] = (insn[2] & ~0x400000) | (((slotbuf[0] & 0x2000000) >> 25) << 22); + insn[3] = (insn[3] & ~0x10000) | (((slotbuf[0] & 0x4000000) >> 26) << 16); + insn[3] = (insn[3] & ~0x20000) | (((slotbuf[0] & 0x8000000) >> 27) << 17); + insn[3] = (insn[3] & ~0x40000) | (((slotbuf[0] & 0x10000000) >> 28) << 18); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[0] & 0x20000000) >> 29) << 19); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[0] & 0x40000000) >> 30) << 20); + insn[3] = (insn[3] & ~0x200000) | (((slotbuf[0] & 0x80000000) >> 31) << 21); +} + +static void +Slot_ae_format_8_Format_ae8_slot1_14_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[0] & 0xc000) >> 14) << 8); + slotbuf[0] = (slotbuf[0] & ~0x400) | (((insn[1] & 0x2) >> 1) << 10); + slotbuf[0] = (slotbuf[0] & ~0x800) | (((insn[1] & 0x8) >> 3) << 11); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[2] & 0x80000000) >> 31) << 12); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[2] & 0x60000) >> 17) << 18); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[2] & 0x4000000) >> 26) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1e00000) | (((insn[3] & 0x1e0) >> 5) << 21); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x400000) >> 22) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x800000) >> 23) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x1000000) >> 24) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x2000000) >> 25) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x4000000) >> 26) << 29); +} + +static void +Slot_ae_format_8_Format_ae8_slot1_14_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[0] = (insn[0] & ~0xc000) | (((slotbuf[0] & 0x300) >> 8) << 14); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x400) >> 10) << 1); + insn[1] = (insn[1] & ~0x8) | (((slotbuf[0] & 0x800) >> 11) << 3); + insn[2] = (insn[2] & ~0x80000000) | (((slotbuf[0] & 0x1000) >> 12) << 31); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[2] = (insn[2] & ~0x60000) | (((slotbuf[0] & 0xc0000) >> 18) << 17); + insn[2] = (insn[2] & ~0x4000000) | (((slotbuf[0] & 0x100000) >> 20) << 26); + insn[3] = (insn[3] & ~0x1e0) | (((slotbuf[0] & 0x1e00000) >> 21) << 5); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[0] & 0x2000000) >> 25) << 22); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[0] & 0x4000000) >> 26) << 23); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x8000000) >> 27) << 24); + insn[3] = (insn[3] & ~0x2000000) | (((slotbuf[0] & 0x10000000) >> 28) << 25); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x20000000) >> 29) << 26); +} + +static void +Slot_ae_format_8_Format_ae8_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xc0000000) >> 30); + slotbuf[0] = (slotbuf[0] & ~0x3fc) | ((insn[2] & 0xff) << 2); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x3e00000) >> 21) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[0] & 0x1f0000) >> 16) << 15); + slotbuf[0] = (slotbuf[0] & ~0xf00000) | (((insn[1] & 0xf0) >> 4) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[1] & 0x800) >> 11) << 24); + slotbuf[0] = (slotbuf[0] & ~0x6000000) | (((insn[2] & 0x180000) >> 19) << 25); + slotbuf[0] = (slotbuf[0] & ~0x38000000) | (((insn[3] & 0x1c00) >> 10) << 27); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[1] & 0xc0000) >> 18) << 30); + slotbuf[1] = ((insn[1] & 0x700000) >> 20); + slotbuf[1] = (slotbuf[1] & ~0x8) | (((insn[0] & 0x4000000) >> 26) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[1] & 0x4) >> 2) << 4); + slotbuf[1] = (slotbuf[1] & ~0xe0) | (((insn[1] & 0x700) >> 8) << 5); + slotbuf[1] = (slotbuf[1] & ~0x1f00) | (((insn[1] & 0x3e000) >> 13) << 8); + slotbuf[1] = (slotbuf[1] & ~0x2000) | (((insn[1] & 0x20000000) >> 29) << 13); + slotbuf[1] = (slotbuf[1] & ~0x3c000) | (((insn[2] & 0x78000000) >> 27) << 14); + slotbuf[1] = (slotbuf[1] & ~0x40000) | (((insn[3] & 0x200) >> 9) << 18); + slotbuf[1] = (slotbuf[1] & ~0x380000) | (((insn[3] & 0xe000) >> 13) << 19); + slotbuf[1] = (slotbuf[1] & ~0x400000) | (((insn[3] & 0x8000000) >> 27) << 22); + slotbuf[1] = (slotbuf[1] & ~0x800000) | (((insn[3] & 0x10000000) >> 28) << 23); + slotbuf[1] = (slotbuf[1] & ~0x1000000) | (((insn[3] & 0x20000000) >> 29) << 24); + slotbuf[1] = (slotbuf[1] & ~0x2000000) | (((insn[3] & 0x40000000) >> 30) << 25); + slotbuf[1] = (slotbuf[1] & ~0x4000000) | (((insn[3] & 0x80000000) >> 31) << 26); +} + +static void +Slot_ae_format_8_Format_ae8_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xc0000000) | ((slotbuf[0] & 0x3) << 30); + insn[2] = (insn[2] & ~0xff) | ((slotbuf[0] & 0x3fc) >> 2); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x7c00) >> 10) << 21); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0xf8000) >> 15) << 16); + insn[1] = (insn[1] & ~0xf0) | (((slotbuf[0] & 0xf00000) >> 20) << 4); + insn[1] = (insn[1] & ~0x800) | (((slotbuf[0] & 0x1000000) >> 24) << 11); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x6000000) >> 25) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0x38000000) >> 27) << 10); + insn[1] = (insn[1] & ~0xc0000) | (((slotbuf[0] & 0xc0000000) >> 30) << 18); + insn[1] = (insn[1] & ~0x700000) | ((slotbuf[1] & 0x7) << 20); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[1] & 0x8) >> 3) << 26); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[1] & 0x10) >> 4) << 2); + insn[1] = (insn[1] & ~0x700) | (((slotbuf[1] & 0xe0) >> 5) << 8); + insn[1] = (insn[1] & ~0x3e000) | (((slotbuf[1] & 0x1f00) >> 8) << 13); + insn[1] = (insn[1] & ~0x20000000) | (((slotbuf[1] & 0x2000) >> 13) << 29); + insn[2] = (insn[2] & ~0x78000000) | (((slotbuf[1] & 0x3c000) >> 14) << 27); + insn[3] = (insn[3] & ~0x200) | (((slotbuf[1] & 0x40000) >> 18) << 9); + insn[3] = (insn[3] & ~0xe000) | (((slotbuf[1] & 0x380000) >> 19) << 13); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[1] & 0x400000) >> 22) << 27); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[1] & 0x800000) >> 23) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[1] & 0x1000000) >> 24) << 29); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[1] & 0x2000000) >> 25) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x4000000) >> 26) << 31); +} + +static void +Slot_ae_format_9_Format_ae9_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xfff0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x7000) | (((insn[0] & 0x1c000000) >> 26) << 12); + slotbuf[0] = (slotbuf[0] & ~0x38000) | ((insn[1] & 0x7) << 15); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x10000) >> 16) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[2] & 0x200000) >> 21) << 19); + slotbuf[0] = (slotbuf[0] & ~0x300000) | (((insn[1] & 0x1800000) >> 23) << 20); + slotbuf[0] = (slotbuf[0] & ~0x3c00000) | (((insn[2] & 0x3c00000) >> 22) << 22); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x1000000) >> 24) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x2000000) >> 25) << 27); +} + +static void +Slot_ae_format_9_Format_ae9_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xfff0) | ((slotbuf[0] & 0xfff) << 4); + insn[0] = (insn[0] & ~0x1c000000) | (((slotbuf[0] & 0x7000) >> 12) << 26); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x38000) >> 15); + insn[2] = (insn[2] & ~0x10000) | (((slotbuf[0] & 0x40000) >> 18) << 16); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[0] & 0x80000) >> 19) << 21); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x300000) >> 20) << 23); + insn[2] = (insn[2] & ~0x3c00000) | (((slotbuf[0] & 0x3c00000) >> 22) << 22); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x4000000) >> 26) << 24); + insn[3] = (insn[3] & ~0x2000000) | (((slotbuf[0] & 0x8000000) >> 27) << 25); +} + +static void +Slot_ae_format_9_Format_ae9_slot1_72_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[2] & 0xf8000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[2] & 0x60000) >> 17) << 18); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[2] & 0x4000000) >> 26) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1e00000) | (((insn[3] & 0x1e000) >> 13) << 21); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x4000000) >> 26) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x8000000) >> 27) << 26); +} + +static void +Slot_ae_format_9_Format_ae9_slot1_72_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x1f00) >> 8) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[2] = (insn[2] & ~0x60000) | (((slotbuf[0] & 0xc0000) >> 18) << 17); + insn[2] = (insn[2] & ~0x4000000) | (((slotbuf[0] & 0x100000) >> 20) << 26); + insn[3] = (insn[3] & ~0x1e000) | (((slotbuf[0] & 0x1e00000) >> 21) << 13); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x2000000) >> 25) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x4000000) >> 26) << 27); +} + +static void +Slot_ae_format_9_Format_ae9_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[3] & 0x3e0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x60) | (((insn[1] & 0xc0000000) >> 30) << 5); + slotbuf[0] = (slotbuf[0] & ~0x380) | ((insn[2] & 0x7) << 7); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x1f0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1ff8000) | (((insn[1] & 0x1ff8) >> 3) << 15); + slotbuf[0] = (slotbuf[0] & ~0x3e000000) | (((insn[0] & 0x3e00000) >> 21) << 25); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0x60000) >> 17) << 30); + slotbuf[1] = ((insn[3] & 0x10000000) >> 28); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[3] & 0x20000000) >> 29) << 1); +} + +static void +Slot_ae_format_9_Format_ae9_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[3] = (insn[3] & ~0x3e0) | ((slotbuf[0] & 0x1f) << 5); + insn[1] = (insn[1] & ~0xc0000000) | (((slotbuf[0] & 0x60) >> 5) << 30); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0x380) >> 7); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0x7c00) >> 10) << 16); + insn[1] = (insn[1] & ~0x1ff8) | (((slotbuf[0] & 0x1ff8000) >> 15) << 3); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x3e000000) >> 25) << 21); + insn[3] = (insn[3] & ~0x60000) | (((slotbuf[0] & 0xc0000000) >> 30) << 17); + insn[3] = (insn[3] & ~0x10000000) | ((slotbuf[1] & 0x1) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[1] & 0x2) >> 1) << 29); +} + +static void +Slot_ae_format_9_Format_ae9_slot3_45_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xf8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0x3e0) | (((insn[1] & 0x3e000000) >> 25) << 5); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[1] & 0x7c0000) >> 18) << 10); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x180000) >> 19) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[3] & 0x1c00) >> 10) << 17); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[1] & 0x3e000) >> 13) << 20); + slotbuf[0] = (slotbuf[0] & ~0x3e000000) | (((insn[3] & 0xf80000) >> 19) << 25); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x40000000) >> 30) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x80000000) >> 31) << 31); +} + +static void +Slot_ae_format_9_Format_ae9_slot3_45_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xf8) | ((slotbuf[0] & 0x1f) << 3); + insn[1] = (insn[1] & ~0x3e000000) | (((slotbuf[0] & 0x3e0) >> 5) << 25); + insn[1] = (insn[1] & ~0x7c0000) | (((slotbuf[0] & 0x7c00) >> 10) << 18); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x18000) >> 15) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0xe0000) >> 17) << 10); + insn[1] = (insn[1] & ~0x3e000) | (((slotbuf[0] & 0x1f00000) >> 20) << 13); + insn[3] = (insn[3] & ~0xf80000) | (((slotbuf[0] & 0x3e000000) >> 25) << 19); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x40000000) >> 30) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x80000000) >> 31) << 31); +} + +static void +Slot_ae_format_10_Format_ae10_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x3f0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x3c0) | (((insn[0] & 0xf000) >> 12) << 6); + slotbuf[0] = (slotbuf[0] & ~0xc00) | (((insn[0] & 0xc00) >> 10) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[2] & 0x800000) >> 23) << 12); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[2] & 0x30000) >> 16) << 13); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[2] & 0x7000000) >> 24) << 15); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[1] & 0x2) >> 1) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[0] & 0x4000000) >> 26) << 19); + slotbuf[0] = (slotbuf[0] & ~0x300000) | (((insn[2] & 0x600000) >> 21) << 20); + slotbuf[0] = (slotbuf[0] & ~0xc00000) | (((insn[3] & 0x6000) >> 13) << 22); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x40000000) >> 30) << 24); +} + +static void +Slot_ae_format_10_Format_ae10_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3f0) | ((slotbuf[0] & 0x3f) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0x3c0) >> 6) << 12); + insn[0] = (insn[0] & ~0xc00) | (((slotbuf[0] & 0xc00) >> 10) << 10); + insn[2] = (insn[2] & ~0x800000) | (((slotbuf[0] & 0x1000) >> 12) << 23); + insn[2] = (insn[2] & ~0x30000) | (((slotbuf[0] & 0x6000) >> 13) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0x38000) >> 15) << 24); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x40000) >> 18) << 1); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x80000) >> 19) << 26); + insn[2] = (insn[2] & ~0x600000) | (((slotbuf[0] & 0x300000) >> 20) << 21); + insn[3] = (insn[3] & ~0x6000) | (((slotbuf[0] & 0xc00000) >> 22) << 13); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x1000000) >> 24) << 30); +} + +static void +Slot_ae_format_10_Format_ae10_slot1_34_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[2] & 0xf8000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[1] & 0x4) >> 2) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[2] & 0x40000) >> 18) << 19); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[3] & 0xf8000) >> 15) << 20); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x80000000) >> 31) << 25); +} + +static void +Slot_ae_format_10_Format_ae10_slot1_34_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x1f00) >> 8) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[0] & 0x40000) >> 18) << 2); + insn[2] = (insn[2] & ~0x40000) | (((slotbuf[0] & 0x80000) >> 19) << 18); + insn[3] = (insn[3] & ~0xf8000) | (((slotbuf[0] & 0x1f00000) >> 20) << 15); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x2000000) >> 25) << 31); +} + +static void +Slot_ae_format_10_Format_ae10_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[3] & 0x3e0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x60) | (((insn[1] & 0xc0000000) >> 30) << 5); + slotbuf[0] = (slotbuf[0] & ~0x380) | ((insn[2] & 0x7) << 7); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x1f0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1ff8000) | (((insn[1] & 0x1ff8) >> 3) << 15); + slotbuf[0] = (slotbuf[0] & ~0x3e000000) | (((insn[0] & 0x3e00000) >> 21) << 25); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0x300000) >> 20) << 30); + slotbuf[1] = ((insn[3] & 0x1c00000) >> 22); +} + +static void +Slot_ae_format_10_Format_ae10_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[3] = (insn[3] & ~0x3e0) | ((slotbuf[0] & 0x1f) << 5); + insn[1] = (insn[1] & ~0xc0000000) | (((slotbuf[0] & 0x60) >> 5) << 30); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0x380) >> 7); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0x7c00) >> 10) << 16); + insn[1] = (insn[1] & ~0x1ff8) | (((slotbuf[0] & 0x1ff8000) >> 15) << 3); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x3e000000) >> 25) << 21); + insn[3] = (insn[3] & ~0x300000) | (((slotbuf[0] & 0xc0000000) >> 30) << 20); + insn[3] = (insn[3] & ~0x1c00000) | ((slotbuf[1] & 0x7) << 22); +} + +static void +Slot_ae_format_10_Format_ae10_slot3_27_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xf8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0x3e0) | (((insn[1] & 0x3e000000) >> 25) << 5); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[1] & 0x7c0000) >> 18) << 10); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x180000) >> 19) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[3] & 0x1c00) >> 10) << 17); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[1] & 0x3e000) >> 13) << 20); + slotbuf[0] = (slotbuf[0] & ~0x6000000) | (((insn[0] & 0x18000000) >> 27) << 25); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | ((insn[1] & 0x1) << 27); + slotbuf[0] = (slotbuf[0] & ~0x30000000) | (((insn[1] & 0x1800000) >> 23) << 28); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0x6000000) >> 25) << 30); + slotbuf[1] = ((insn[3] & 0x38000000) >> 27); +} + +static void +Slot_ae_format_10_Format_ae10_slot3_27_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xf8) | ((slotbuf[0] & 0x1f) << 3); + insn[1] = (insn[1] & ~0x3e000000) | (((slotbuf[0] & 0x3e0) >> 5) << 25); + insn[1] = (insn[1] & ~0x7c0000) | (((slotbuf[0] & 0x7c00) >> 10) << 18); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x18000) >> 15) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0xe0000) >> 17) << 10); + insn[1] = (insn[1] & ~0x3e000) | (((slotbuf[0] & 0x1f00000) >> 20) << 13); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x6000000) >> 25) << 27); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x8000000) >> 27); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x30000000) >> 28) << 23); + insn[3] = (insn[3] & ~0x6000000) | (((slotbuf[0] & 0xc0000000) >> 30) << 25); + insn[3] = (insn[3] & ~0x38000000) | ((slotbuf[1] & 0x7) << 27); +} + +static void +Slot_ae_format_4_Format_ae4_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x3f0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x3c0) | (((insn[0] & 0xf000) >> 12) << 6); + slotbuf[0] = (slotbuf[0] & ~0xc00) | (((insn[0] & 0xc00) >> 10) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x2) >> 1) << 12); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[0] & 0x18000000) >> 27) << 13); + slotbuf[0] = (slotbuf[0] & ~0x8000) | ((insn[1] & 0x1) << 15); + slotbuf[0] = (slotbuf[0] & ~0x30000) | (((insn[1] & 0x1800000) >> 23) << 16); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x40000) >> 18) << 18); + slotbuf[0] = (slotbuf[0] & ~0x380000) | (((insn[3] & 0xe000) >> 13) << 19); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x10000000) >> 28) << 22); +} + +static void +Slot_ae_format_4_Format_ae4_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3f0) | ((slotbuf[0] & 0x3f) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0x3c0) >> 6) << 12); + insn[0] = (insn[0] & ~0xc00) | (((slotbuf[0] & 0xc00) >> 10) << 10); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x1000) >> 12) << 1); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x6000) >> 13) << 27); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x8000) >> 15); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x30000) >> 16) << 23); + insn[2] = (insn[2] & ~0x40000) | (((slotbuf[0] & 0x40000) >> 18) << 18); + insn[3] = (insn[3] & ~0xe000) | (((slotbuf[0] & 0x380000) >> 19) << 13); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[0] & 0x400000) >> 22) << 28); +} + +static void +Slot_ae_format_4_Format_ae4_slot1_72_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[2] & 0xf8000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0x3c0000) | (((insn[3] & 0xf0000) >> 16) << 18); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x20000000) >> 29) << 22); +} + +static void +Slot_ae_format_4_Format_ae4_slot1_72_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x1f00) >> 8) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[3] = (insn[3] & ~0xf0000) | (((slotbuf[0] & 0x3c0000) >> 18) << 16); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x400000) >> 22) << 29); +} + +static void +Slot_ae_format_4_Format_ae4_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x3e00000) >> 21); + slotbuf[0] = (slotbuf[0] & ~0x3e0) | (((insn[0] & 0x1f0000) >> 16) << 5); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[1] & 0xf8) >> 3) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[3] & 0x3e0) >> 5) << 15); + slotbuf[0] = (slotbuf[0] & ~0x700000) | (((insn[3] & 0x700000) >> 20) << 20); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x40000000) >> 30) << 23); +} + +static void +Slot_ae_format_4_Format_ae4_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3e00000) | ((slotbuf[0] & 0x1f) << 21); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0x3e0) >> 5) << 16); + insn[1] = (insn[1] & ~0xf8) | (((slotbuf[0] & 0x7c00) >> 10) << 3); + insn[3] = (insn[3] & ~0x3e0) | (((slotbuf[0] & 0xf8000) >> 15) << 5); + insn[3] = (insn[3] & ~0x700000) | (((slotbuf[0] & 0x700000) >> 20) << 20); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x800000) >> 23) << 30); +} + +static void +Slot_ae_format_4_Format_ae4_slot3_26_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0x180000) >> 19); + slotbuf[0] = (slotbuf[0] & ~0x1c) | (((insn[3] & 0x1c00) >> 10) << 2); + slotbuf[0] = (slotbuf[0] & ~0x20) | (((insn[0] & 0x4000000) >> 26) << 5); + slotbuf[0] = (slotbuf[0] & ~0x40) | (((insn[1] & 0x4) >> 2) << 6); + slotbuf[0] = (slotbuf[0] & ~0x380) | (((insn[1] & 0x700) >> 8) << 7); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[1] & 0x3e000) >> 13) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[2] & 0xf8) >> 3) << 15); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[1] & 0x7c0000) >> 18) << 20); + slotbuf[0] = (slotbuf[0] & ~0x6000000) | (((insn[3] & 0x1800000) >> 23) << 25); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x80000000) >> 31) << 27); +} + +static void +Slot_ae_format_4_Format_ae4_slot3_26_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0x180000) | ((slotbuf[0] & 0x3) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0x1c) >> 2) << 10); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x20) >> 5) << 26); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[0] & 0x40) >> 6) << 2); + insn[1] = (insn[1] & ~0x700) | (((slotbuf[0] & 0x380) >> 7) << 8); + insn[1] = (insn[1] & ~0x3e000) | (((slotbuf[0] & 0x7c00) >> 10) << 13); + insn[2] = (insn[2] & ~0xf8) | (((slotbuf[0] & 0xf8000) >> 15) << 3); + insn[1] = (insn[1] & ~0x7c0000) | (((slotbuf[0] & 0x1f00000) >> 20) << 18); + insn[3] = (insn[3] & ~0x1800000) | (((slotbuf[0] & 0x6000000) >> 25) << 23); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x8000000) >> 27) << 31); +} + +static void +Slot_ae_format_4_Format_ae4_slot4_43_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xfe000000) >> 25); + slotbuf[0] = (slotbuf[0] & ~0x380) | ((insn[2] & 0x7) << 7); + slotbuf[0] = (slotbuf[0] & ~0xc00) | (((insn[1] & 0x1800) >> 11) << 10); + slotbuf[0] = (slotbuf[0] & ~0x7000) | (((insn[2] & 0xe00000) >> 21) << 12); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x30000) >> 16) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[2] & 0x7000000) >> 24) << 17); + slotbuf[0] = (slotbuf[0] & ~0x700000) | (((insn[3] & 0xe000000) >> 25) << 20); +} + +static void +Slot_ae_format_4_Format_ae4_slot4_43_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xfe000000) | ((slotbuf[0] & 0x7f) << 25); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0x380) >> 7); + insn[1] = (insn[1] & ~0x1800) | (((slotbuf[0] & 0xc00) >> 10) << 11); + insn[2] = (insn[2] & ~0xe00000) | (((slotbuf[0] & 0x7000) >> 12) << 21); + insn[2] = (insn[2] & ~0x30000) | (((slotbuf[0] & 0x18000) >> 15) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0xe0000) >> 17) << 24); + insn[3] = (insn[3] & ~0xe000000) | (((slotbuf[0] & 0x700000) >> 20) << 25); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_s8_Slot_inst_get, + Field_imms8_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_r_disp_Slot_inst_get, + Field_r_3_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst_get, + Field_s2_Slot_inst_get, + Field_r2_Slot_inst_get, + Field_t4_Slot_inst_get, + Field_s4_Slot_inst_get, + Field_r4_Slot_inst_get, + Field_t8_Slot_inst_get, + Field_r8_Slot_inst_get, + Field_xt_wbr15_imm_Slot_inst_get, + Field_xt_wbr18_imm_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_inst_11_8_Slot_inst_get, + Field_fld_inst_12_12_Slot_inst_get, + Field_fld_inst_12_8_Slot_inst_get, + Field_fld_inst_13_8_Slot_inst_get, + Field_fld_inst_15_12_Slot_inst_get, + Field_fld_inst_19_17_Slot_inst_get, + Field_fld_inst_19_18_Slot_inst_get, + Field_fld_inst_23_12_Slot_inst_get, + Field_fld_inst_23_16_Slot_inst_get, + Field_fld_inst_4_4_Slot_inst_get, + Field_fld_inst_5_4_Slot_inst_get, + Field_fld_inst_7_4_Slot_inst_get, + Field_fld_inst_7_6_Slot_inst_get, + Field_fld_inst_7_7_Slot_inst_get, + Field_fld_inst_9_8_Slot_inst_get, + Field_bitindex_Slot_inst_get, + Field_s3to1_Slot_inst_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_s8_Slot_inst_set, + Field_imms8_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_r_disp_Slot_inst_set, + Field_r_3_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst_set, + Field_s2_Slot_inst_set, + Field_r2_Slot_inst_set, + Field_t4_Slot_inst_set, + Field_s4_Slot_inst_set, + Field_r4_Slot_inst_set, + Field_t8_Slot_inst_set, + Field_r8_Slot_inst_set, + Field_xt_wbr15_imm_Slot_inst_set, + Field_xt_wbr18_imm_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_inst_11_8_Slot_inst_set, + Field_fld_inst_12_12_Slot_inst_set, + Field_fld_inst_12_8_Slot_inst_set, + Field_fld_inst_13_8_Slot_inst_set, + Field_fld_inst_15_12_Slot_inst_set, + Field_fld_inst_19_17_Slot_inst_set, + Field_fld_inst_19_18_Slot_inst_set, + Field_fld_inst_23_12_Slot_inst_set, + Field_fld_inst_23_16_Slot_inst_set, + Field_fld_inst_4_4_Slot_inst_set, + Field_fld_inst_5_4_Slot_inst_set, + Field_fld_inst_7_4_Slot_inst_set, + Field_fld_inst_7_6_Slot_inst_set, + Field_fld_inst_7_7_Slot_inst_set, + Field_fld_inst_9_8_Slot_inst_set, + Field_bitindex_Slot_inst_set, + Field_s3to1_Slot_inst_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_get, + 0, + 0, + Field_r_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_set, + 0, + 0, + Field_r_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, 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+ 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_get, + 0, + 0, + Field_r_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_inst16b_12_Slot_inst16b_get, + Field_ae_fld_inst16b_15_13_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_set, + 0, + 0, + Field_r_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_inst16b_12_Slot_inst16b_set, + Field_ae_fld_inst16b_15_13_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot0_get_field_fns[] = { + Field_t_Slot_ae_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot0_get, + Field_s_Slot_ae_slot0_get, + Field_s8_Slot_ae_slot0_get, + 0, + Field_imm12b_Slot_ae_slot0_get, + Field_imm16_Slot_ae_slot0_get, + 0, + 0, + Field_offset_Slot_ae_slot0_get, + 0, + 0, + Field_op2_Slot_ae_slot0_get, + Field_r_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae_slot0_get, + Field_sal_Slot_ae_slot0_get, + Field_sargt_Slot_ae_slot0_get, + 0, + Field_sas_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae_slot0_get, + 0, + Field_r2_Slot_ae_slot0_get, + Field_t4_Slot_ae_slot0_get, + Field_s4_Slot_ae_slot0_get, + Field_r4_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_art_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_d1_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcmp_br4t_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcnv_arr_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcnv_art_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot0_get, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae_slot0_get, + Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_a_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_su_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_vu_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_x_Slot_ae_slot0_get, + Field_fld_ae_sem_pks_d_Slot_ae_slot0_get, + Field_fld_ae_sem_pks_pos_Slot_ae_slot0_get, + Field_fld_ae_sem_pks_s_Slot_ae_slot0_get, + Field_fld_ae_sem_rng_v0_Slot_ae_slot0_get, + Field_fld_ae_sem_rng_v1_Slot_ae_slot0_get, + Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_a_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_a0_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_d_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_d0_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_d1_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_da_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_i16_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_i32_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_i64_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_imm32_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_imm8_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_sd_Slot_ae_slot0_get, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae_slot0_get, + Field_fld_ae_sem_sp32cvt_art_Slot_ae_slot0_get, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae_slot0_get, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae_slot0_get, + Field_fld_ae_sem_spmisc_brt_Slot_ae_slot0_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot0_get, + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get, + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get, + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_10_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_6_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_9_Slot_ae_slot0_get, + Field_fld_ae_slot0_14_12_Slot_ae_slot0_get, + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_10_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_13_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get, + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get, + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get, + Field_fld_ae_slot0_18_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_19_12_Slot_ae_slot0_get, + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get, + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get, + Field_fld_ae_slot0_19_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_1_1_Slot_ae_slot0_get, + Field_fld_ae_slot0_20_16_Slot_ae_slot0_get, + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get, + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get, + Field_fld_ae_slot0_23_17_Slot_ae_slot0_get, + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get, + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_10_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_12_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_14_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_15_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_16_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_17_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_19_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_21_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_22_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_24_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_26_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_27_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_4_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get, + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get, + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get, + Field_fld_ae_slot0_4_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get, + Field_fld_ae_slot0_5_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get, + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get, + Field_fld_ae_slot0_7_3_Slot_ae_slot0_get, + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get, + Field_fld_ae_slot0_8_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_9_4_Slot_ae_slot0_get, + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot0_set_field_fns[] = { + Field_t_Slot_ae_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot0_set, + Field_s_Slot_ae_slot0_set, + Field_s8_Slot_ae_slot0_set, + 0, + Field_imm12b_Slot_ae_slot0_set, + Field_imm16_Slot_ae_slot0_set, + 0, + 0, + Field_offset_Slot_ae_slot0_set, + 0, + 0, + Field_op2_Slot_ae_slot0_set, + Field_r_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae_slot0_set, + Field_sal_Slot_ae_slot0_set, + Field_sargt_Slot_ae_slot0_set, + 0, + Field_sas_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae_slot0_set, + 0, + Field_r2_Slot_ae_slot0_set, + Field_t4_Slot_ae_slot0_set, + Field_s4_Slot_ae_slot0_set, + Field_r4_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_art_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_d1_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcmp_br4t_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcnv_arr_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcnv_art_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot0_set, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae_slot0_set, + Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_a_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_su_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_vu_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_x_Slot_ae_slot0_set, + Field_fld_ae_sem_pks_d_Slot_ae_slot0_set, + Field_fld_ae_sem_pks_pos_Slot_ae_slot0_set, + Field_fld_ae_sem_pks_s_Slot_ae_slot0_set, + Field_fld_ae_sem_rng_v0_Slot_ae_slot0_set, + Field_fld_ae_sem_rng_v1_Slot_ae_slot0_set, + Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_a_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_a0_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_d_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_d0_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_d1_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_da_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_i16_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_i32_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_i64_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_imm32_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_imm8_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_sd_Slot_ae_slot0_set, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae_slot0_set, + Field_fld_ae_sem_sp32cvt_art_Slot_ae_slot0_set, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae_slot0_set, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae_slot0_set, + Field_fld_ae_sem_spmisc_brt_Slot_ae_slot0_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot0_set, + Field_fld_ae_slot0_11_10_Slot_ae_slot0_set, + Field_fld_ae_slot0_11_11_Slot_ae_slot0_set, + Field_fld_ae_slot0_11_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_11_9_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_10_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_12_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_2_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_6_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_9_Slot_ae_slot0_set, + Field_fld_ae_slot0_14_12_Slot_ae_slot0_set, + Field_fld_ae_slot0_14_13_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_10_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_12_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_13_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_14_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_15_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_16_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_17_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_18_13_Slot_ae_slot0_set, + Field_fld_ae_slot0_18_15_Slot_ae_slot0_set, + Field_fld_ae_slot0_18_16_Slot_ae_slot0_set, + Field_fld_ae_slot0_18_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_19_12_Slot_ae_slot0_set, + Field_fld_ae_slot0_19_15_Slot_ae_slot0_set, + Field_fld_ae_slot0_19_19_Slot_ae_slot0_set, + Field_fld_ae_slot0_19_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_1_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_1_1_Slot_ae_slot0_set, + Field_fld_ae_slot0_20_16_Slot_ae_slot0_set, + Field_fld_ae_slot0_20_20_Slot_ae_slot0_set, + Field_fld_ae_slot0_23_15_Slot_ae_slot0_set, + Field_fld_ae_slot0_23_17_Slot_ae_slot0_set, + Field_fld_ae_slot0_23_19_Slot_ae_slot0_set, + Field_fld_ae_slot0_23_22_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_10_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_12_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_14_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_15_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_16_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_17_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_19_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_21_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_22_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_24_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_26_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_27_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_4_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_3_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_3_1_Slot_ae_slot0_set, + Field_fld_ae_slot0_3_2_Slot_ae_slot0_set, + Field_fld_ae_slot0_3_3_Slot_ae_slot0_set, + Field_fld_ae_slot0_4_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_4_4_Slot_ae_slot0_set, + Field_fld_ae_slot0_5_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_5_4_Slot_ae_slot0_set, + Field_fld_ae_slot0_7_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_7_2_Slot_ae_slot0_set, + Field_fld_ae_slot0_7_3_Slot_ae_slot0_set, + Field_fld_ae_slot0_7_4_Slot_ae_slot0_set, + Field_fld_ae_slot0_8_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_9_4_Slot_ae_slot0_set, + Field_fld_ae_slot0_9_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_9_9_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot1_get_field_fns[] = { + Field_t_Slot_ae_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot1_get, + Field_s_Slot_ae_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae_slot1_get, + Field_r_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae_slot1_get, + Field_sal_Slot_ae_slot1_get, + Field_sargt_Slot_ae_slot1_get, + 0, + Field_sas_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot1_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot1_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot1_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_a_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_0_0_Slot_ae_slot1_get, + Field_fld_ae_slot1_12_8_Slot_ae_slot1_get, + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get, + Field_fld_ae_slot1_17_17_Slot_ae_slot1_get, + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_1_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_12_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_13_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_16_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_17_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_18_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_20_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_22_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_23_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_8_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_9_Slot_ae_slot1_get, + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get, + Field_fld_ae_slot1_3_2_Slot_ae_slot1_get, + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get, + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot1_set_field_fns[] = { + Field_t_Slot_ae_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot1_set, + Field_s_Slot_ae_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae_slot1_set, + Field_r_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae_slot1_set, + Field_sal_Slot_ae_slot1_set, + Field_sargt_Slot_ae_slot1_set, + 0, + Field_sas_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot1_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot1_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot1_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_a_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_0_0_Slot_ae_slot1_set, + Field_fld_ae_slot1_12_8_Slot_ae_slot1_set, + Field_fld_ae_slot1_17_13_Slot_ae_slot1_set, + Field_fld_ae_slot1_17_17_Slot_ae_slot1_set, + Field_fld_ae_slot1_17_8_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_1_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_12_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_13_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_16_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_17_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_18_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_20_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_22_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_23_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_8_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_9_Slot_ae_slot1_set, + Field_fld_ae_slot1_3_0_Slot_ae_slot1_set, + Field_fld_ae_slot1_3_2_Slot_ae_slot1_set, + Field_fld_ae_slot1_3_3_Slot_ae_slot1_set, + Field_fld_ae_slot1_7_4_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot2_get, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot2_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae_slot2_get, + Field_fld_ae_sem_pks_pos_Slot_ae_slot2_get, + Field_fld_ae_sem_pks_s_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae_slot2_get, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot2_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae_slot2_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_hpcnv_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_hpfma_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_get, + Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot2_get, + Field_fld_ae_sem_multiply_d0_Slot_ae_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae_slot2_get, + Field_fld_ae_sem_multiply_q1_Slot_ae_slot2_get, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae_slot2_get, + Field_fld_ae_sem_reduction_sort_v_Slot_ae_slot2_get, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae_slot2_get, + Field_fld_ae_sem_select_isel_Slot_ae_slot2_get, + Field_fld_ae_sem_select_ss_Slot_ae_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_select_vu_Slot_ae_slot2_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_vp_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot2_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot2_get, + Field_fld_ae_slot2_14_0_Slot_ae_slot2_get, + Field_fld_ae_slot2_14_10_Slot_ae_slot2_get, + Field_fld_ae_slot2_14_14_Slot_ae_slot2_get, + Field_fld_ae_slot2_14_5_Slot_ae_slot2_get, + Field_fld_ae_slot2_16_15_Slot_ae_slot2_get, + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_15_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_17_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_19_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_20_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_25_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_4_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_5_Slot_ae_slot2_get, + Field_fld_ae_slot2_3_0_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_1_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_2_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_6_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_8_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot2_set, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot2_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae_slot2_set, + Field_fld_ae_sem_pks_pos_Slot_ae_slot2_set, + Field_fld_ae_sem_pks_s_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae_slot2_set, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot2_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae_slot2_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_hpcnv_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_hpfma_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_set, + Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot2_set, + Field_fld_ae_sem_multiply_d0_Slot_ae_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae_slot2_set, + Field_fld_ae_sem_multiply_q1_Slot_ae_slot2_set, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae_slot2_set, + Field_fld_ae_sem_reduction_sort_v_Slot_ae_slot2_set, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae_slot2_set, + Field_fld_ae_sem_select_isel_Slot_ae_slot2_set, + Field_fld_ae_sem_select_ss_Slot_ae_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_select_vu_Slot_ae_slot2_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_vp_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot2_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot2_set, + Field_fld_ae_slot2_14_0_Slot_ae_slot2_set, + Field_fld_ae_slot2_14_10_Slot_ae_slot2_set, + Field_fld_ae_slot2_14_14_Slot_ae_slot2_set, + Field_fld_ae_slot2_14_5_Slot_ae_slot2_set, + Field_fld_ae_slot2_16_15_Slot_ae_slot2_set, + Field_fld_ae_slot2_19_15_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_15_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_17_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_19_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_20_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_25_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_4_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_5_Slot_ae_slot2_set, + Field_fld_ae_slot2_3_0_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_0_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_1_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_2_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_5_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_6_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_7_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_8_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r4_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot3_get, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot3_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot3_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_d_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_d0_Slot_ae_slot3_get, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_i32_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_i64_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae_slot3_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_get, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot3_get, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot3_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae_slot3_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae_slot3_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae_slot3_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae_slot3_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_d0_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_d2_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_q0_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_q1_Slot_ae_slot3_get, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae_slot3_get, + Field_fld_ae_sem_select_ss_Slot_ae_slot3_get, + Field_fld_ae_sem_select_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_select_vs_Slot_ae_slot3_get, + Field_fld_ae_sem_select_vt_Slot_ae_slot3_get, + Field_fld_ae_sem_select_vu_Slot_ae_slot3_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot3_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot3_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_vp_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_vs_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_vt_Slot_ae_slot3_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot3_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae_slot3_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_imm_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_d1_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_d3_Slot_ae_slot3_get, + Field_fld_ae_sem_rng_d_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_e_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_i8_Slot_ae_slot3_get, + Field_fld_ae_slot3_11_0_Slot_ae_slot3_get, + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get, + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get, + Field_fld_ae_slot3_14_12_Slot_ae_slot3_get, + Field_fld_ae_slot3_14_13_Slot_ae_slot3_get, + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_17_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_18_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_19_Slot_ae_slot3_get, + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get, + Field_fld_ae_slot3_24_19_Slot_ae_slot3_get, + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_12_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_16_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_19_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_20_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_22_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_25_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_30_Slot_ae_slot3_get, + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get, + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get, + Field_fld_ae_slot3_9_1_Slot_ae_slot3_get, + Field_fld_ae_slot3_9_3_Slot_ae_slot3_get, + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r4_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot3_set, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot3_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot3_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_d_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_d0_Slot_ae_slot3_set, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_i32_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_i64_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae_slot3_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_set, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot3_set, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot3_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae_slot3_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae_slot3_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae_slot3_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae_slot3_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_d0_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_d2_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_q0_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_q1_Slot_ae_slot3_set, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae_slot3_set, + Field_fld_ae_sem_select_ss_Slot_ae_slot3_set, + Field_fld_ae_sem_select_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_select_vs_Slot_ae_slot3_set, + Field_fld_ae_sem_select_vt_Slot_ae_slot3_set, + Field_fld_ae_sem_select_vu_Slot_ae_slot3_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot3_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot3_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_vp_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_vs_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_vt_Slot_ae_slot3_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot3_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae_slot3_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_imm_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_d1_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_d3_Slot_ae_slot3_set, + Field_fld_ae_sem_rng_d_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_e_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_i8_Slot_ae_slot3_set, + Field_fld_ae_slot3_11_0_Slot_ae_slot3_set, + Field_fld_ae_slot3_14_0_Slot_ae_slot3_set, + Field_fld_ae_slot3_14_10_Slot_ae_slot3_set, + Field_fld_ae_slot3_14_12_Slot_ae_slot3_set, + Field_fld_ae_slot3_14_13_Slot_ae_slot3_set, + Field_fld_ae_slot3_16_13_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_0_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_10_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_15_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_17_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_18_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_19_Slot_ae_slot3_set, + Field_fld_ae_slot3_24_10_Slot_ae_slot3_set, + Field_fld_ae_slot3_24_19_Slot_ae_slot3_set, + Field_fld_ae_slot3_24_20_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_12_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_16_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_19_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_20_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_22_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_25_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_30_Slot_ae_slot3_set, + Field_fld_ae_slot3_4_0_Slot_ae_slot3_set, + Field_fld_ae_slot3_9_0_Slot_ae_slot3_set, + Field_fld_ae_slot3_9_1_Slot_ae_slot3_set, + Field_fld_ae_slot3_9_3_Slot_ae_slot3_set, + Field_fld_ae_slot3_9_5_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae2_slot0_get_field_fns[] = { + Field_t_Slot_ae2_slot0_get, + 0, + Field_bbi_Slot_ae2_slot0_get, + 0, + Field_imm8_Slot_ae2_slot0_get, + Field_s_Slot_ae2_slot0_get, + Field_s8_Slot_ae2_slot0_get, + 0, + Field_imm12b_Slot_ae2_slot0_get, + Field_imm16_Slot_ae2_slot0_get, + 0, + 0, + Field_offset_Slot_ae2_slot0_get, + 0, + 0, + Field_op2_Slot_ae2_slot0_get, + Field_r_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot0_get, + Field_sal_Slot_ae2_slot0_get, + Field_sargt_Slot_ae2_slot0_get, + 0, + Field_sas_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae2_slot0_get, + 0, + Field_r2_Slot_ae2_slot0_get, + Field_t4_Slot_ae2_slot0_get, + Field_s4_Slot_ae2_slot0_get, + Field_r4_Slot_ae2_slot0_get, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae2_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_art_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_ds_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_d1_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_hpcnv_arr_Slot_ae2_slot0_get, + Field_fld_ae_sem_hpcnv_art_Slot_ae2_slot0_get, + Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae2_slot0_get, + Field_fld_ae_sem_hpcnv_vr_Slot_ae2_slot0_get, + Field_fld_ae_sem_hpcnv_vt_Slot_ae2_slot0_get, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae2_slot0_get, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae2_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_su_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_vu_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot0_get, + Field_fld_ae_sem_pks_d_Slot_ae2_slot0_get, + Field_fld_ae_sem_pks_pos_Slot_ae2_slot0_get, + Field_fld_ae_sem_pks_s_Slot_ae2_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_a0_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_d_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_d0_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_d1_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_da_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_i16_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_i32_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_i64_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_imm32_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_imm8_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_sd_Slot_ae2_slot0_get, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae2_slot0_get, + Field_fld_ae_sem_sp32cvt_art_Slot_ae2_slot0_get, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae2_slot0_get, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae2_slot0_get, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae2_slot0_get, + Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot0_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot0_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_12_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_12_2_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_14_8_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_4_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_18_17_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_26_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae2_slot0_set_field_fns[] = { + Field_t_Slot_ae2_slot0_set, + 0, + Field_bbi_Slot_ae2_slot0_set, + 0, + Field_imm8_Slot_ae2_slot0_set, + Field_s_Slot_ae2_slot0_set, + Field_s8_Slot_ae2_slot0_set, + 0, + Field_imm12b_Slot_ae2_slot0_set, + Field_imm16_Slot_ae2_slot0_set, + 0, + 0, + Field_offset_Slot_ae2_slot0_set, + 0, + 0, + Field_op2_Slot_ae2_slot0_set, + Field_r_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot0_set, + Field_sal_Slot_ae2_slot0_set, + Field_sargt_Slot_ae2_slot0_set, + 0, + Field_sas_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae2_slot0_set, + 0, + Field_r2_Slot_ae2_slot0_set, + Field_t4_Slot_ae2_slot0_set, + Field_s4_Slot_ae2_slot0_set, + Field_r4_Slot_ae2_slot0_set, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae2_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_art_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_ds_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_d1_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_hpcnv_arr_Slot_ae2_slot0_set, + Field_fld_ae_sem_hpcnv_art_Slot_ae2_slot0_set, + Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae2_slot0_set, + Field_fld_ae_sem_hpcnv_vr_Slot_ae2_slot0_set, + Field_fld_ae_sem_hpcnv_vt_Slot_ae2_slot0_set, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae2_slot0_set, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae2_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_su_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_vu_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot0_set, + Field_fld_ae_sem_pks_d_Slot_ae2_slot0_set, + Field_fld_ae_sem_pks_pos_Slot_ae2_slot0_set, + Field_fld_ae_sem_pks_s_Slot_ae2_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_a0_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_d_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_d0_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_d1_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_da_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_i16_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_i32_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_i64_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_imm32_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_imm8_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_sd_Slot_ae2_slot0_set, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae2_slot0_set, + Field_fld_ae_sem_sp32cvt_art_Slot_ae2_slot0_set, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae2_slot0_set, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae2_slot0_set, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae2_slot0_set, + Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot0_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot0_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_12_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_12_2_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_14_8_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_4_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_18_17_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_26_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae2_slot1_get_field_fns[] = { + Field_t_Slot_ae2_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae2_slot1_get, + Field_s_Slot_ae2_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae2_slot1_get, + Field_r_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot1_get, + Field_sal_Slot_ae2_slot1_get, + Field_sargt_Slot_ae2_slot1_get, + 0, + Field_sas_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot1_get, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot1_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot1_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot1_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot1_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot1_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_11_0_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_17_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_18_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_22_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_23_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_3_2_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_3_3_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae2_slot1_set_field_fns[] = { + Field_t_Slot_ae2_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae2_slot1_set, + Field_s_Slot_ae2_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae2_slot1_set, + Field_r_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot1_set, + Field_sal_Slot_ae2_slot1_set, + Field_sargt_Slot_ae2_slot1_set, + 0, + Field_sas_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot1_set, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot1_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot1_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot1_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot1_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot1_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_11_0_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_17_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_18_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_22_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_23_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_3_2_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_3_3_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae2_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot2_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot2_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot2_get, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae2_slot2_get, + Field_fld_ae_sem_pks_pos_Slot_ae2_slot2_get, + Field_fld_ae_sem_pks_s_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot2_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot2_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot2_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot2_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot2_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot2_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae2_slot2_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae2_slot2_get, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae2_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae2_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae2_slot2_get, + Field_fld_ae_sem_multiply_q1_Slot_ae2_slot2_get, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae2_slot2_get, + Field_fld_ae_sem_reduction_sort_v_Slot_ae2_slot2_get, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_isel_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_ss_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_vu_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_vp_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_vs_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_vt_Slot_ae2_slot2_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae2_slot2_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae2_slot2_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_17_0_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_26_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_28_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vp_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vq_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae2_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot2_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot2_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot2_set, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae2_slot2_set, + Field_fld_ae_sem_pks_pos_Slot_ae2_slot2_set, + Field_fld_ae_sem_pks_s_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot2_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot2_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot2_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot2_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot2_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot2_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae2_slot2_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae2_slot2_set, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae2_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae2_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae2_slot2_set, + Field_fld_ae_sem_multiply_q1_Slot_ae2_slot2_set, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae2_slot2_set, + Field_fld_ae_sem_reduction_sort_v_Slot_ae2_slot2_set, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_isel_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_ss_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_vu_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_vp_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_vs_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_vt_Slot_ae2_slot2_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae2_slot2_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae2_slot2_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_17_0_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_26_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_28_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vp_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vq_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae3_slot0_get_field_fns[] = { + Field_t_Slot_ae3_slot0_get, + 0, + Field_bbi_Slot_ae3_slot0_get, + 0, + Field_imm8_Slot_ae3_slot0_get, + Field_s_Slot_ae3_slot0_get, + Field_s8_Slot_ae3_slot0_get, + 0, + Field_imm12b_Slot_ae3_slot0_get, + Field_imm16_Slot_ae3_slot0_get, + 0, + 0, + Field_offset_Slot_ae3_slot0_get, + 0, + 0, + Field_op2_Slot_ae3_slot0_get, + Field_r_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot0_get, + Field_sal_Slot_ae3_slot0_get, + Field_sargt_Slot_ae3_slot0_get, + 0, + Field_sas_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae3_slot0_get, + 0, + Field_r2_Slot_ae3_slot0_get, + Field_t4_Slot_ae3_slot0_get, + Field_s4_Slot_ae3_slot0_get, + Field_r4_Slot_ae3_slot0_get, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae3_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae3_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae3_slot0_get, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae3_slot0_get, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_su_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_vu_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae3_slot0_get, + Field_fld_ae_sem_shift_d_Slot_ae3_slot0_get, + Field_fld_ae_sem_shift_d0_Slot_ae3_slot0_get, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_16_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_7_2_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_9_4_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot0_get, + Field_fld_ae_sem_sb_loads_stores_iba2_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae3_slot0_set_field_fns[] = { + Field_t_Slot_ae3_slot0_set, + 0, + Field_bbi_Slot_ae3_slot0_set, + 0, + Field_imm8_Slot_ae3_slot0_set, + Field_s_Slot_ae3_slot0_set, + Field_s8_Slot_ae3_slot0_set, + 0, + Field_imm12b_Slot_ae3_slot0_set, + Field_imm16_Slot_ae3_slot0_set, + 0, + 0, + Field_offset_Slot_ae3_slot0_set, + 0, + 0, + Field_op2_Slot_ae3_slot0_set, + Field_r_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot0_set, + Field_sal_Slot_ae3_slot0_set, + Field_sargt_Slot_ae3_slot0_set, + 0, + Field_sas_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae3_slot0_set, + 0, + Field_r2_Slot_ae3_slot0_set, + Field_t4_Slot_ae3_slot0_set, + Field_s4_Slot_ae3_slot0_set, + Field_r4_Slot_ae3_slot0_set, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae3_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae3_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae3_slot0_set, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae3_slot0_set, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_su_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_vu_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae3_slot0_set, + Field_fld_ae_sem_shift_d_Slot_ae3_slot0_set, + Field_fld_ae_sem_shift_d0_Slot_ae3_slot0_set, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_16_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_7_2_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_9_4_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot0_set, + Field_fld_ae_sem_sb_loads_stores_iba2_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae3_slot1_get_field_fns[] = { + Field_t_Slot_ae3_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae3_slot1_get, + Field_s_Slot_ae3_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae3_slot1_get, + Field_r_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot1_get, + Field_sal_Slot_ae3_slot1_get, + Field_sargt_Slot_ae3_slot1_get, + 0, + Field_sas_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot1_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot1_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot1_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot1_get, + 0, + Field_fld_ae3_slot1_23_0_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_11_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_17_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_19_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_9_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_3_1_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae3_slot1_set_field_fns[] = { + Field_t_Slot_ae3_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae3_slot1_set, + Field_s_Slot_ae3_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae3_slot1_set, + Field_r_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot1_set, + Field_sal_Slot_ae3_slot1_set, + Field_sargt_Slot_ae3_slot1_set, + 0, + Field_sas_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot1_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot1_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot1_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot1_set, + 0, + Field_fld_ae3_slot1_23_0_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_11_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_17_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_19_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_9_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_3_1_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae5_slot0_get_field_fns[] = { + Field_t_Slot_ae5_slot0_get, + 0, + Field_bbi_Slot_ae5_slot0_get, + 0, + Field_imm8_Slot_ae5_slot0_get, + Field_s_Slot_ae5_slot0_get, + Field_s8_Slot_ae5_slot0_get, + 0, + Field_imm12b_Slot_ae5_slot0_get, + Field_imm16_Slot_ae5_slot0_get, + 0, + 0, + Field_offset_Slot_ae5_slot0_get, + 0, + 0, + Field_op2_Slot_ae5_slot0_get, + Field_r_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae5_slot0_get, + Field_sal_Slot_ae5_slot0_get, + Field_sargt_Slot_ae5_slot0_get, + 0, + Field_sas_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae5_slot0_get, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae5_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot0_get, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae5_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae5_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae5_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae5_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae5_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae5_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_su_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_vu_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_x_Slot_ae5_slot0_get, + Field_fld_ae_sem_pks_d_Slot_ae5_slot0_get, + Field_fld_ae_sem_pks_pos_Slot_ae5_slot0_get, + Field_fld_ae_sem_pks_s_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae5_slot0_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot0_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_ardecnorm16_ar_u_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_12_6_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_17_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_19_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_6_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_7_0_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get, + Field_fld_ae_sem_lb_db_ops_ar_u_Slot_ae5_slot0_get, + Field_fld_ae_sem_lb_db_ops_iba_Slot_ae5_slot0_get, + Field_fld_ae_sem_rng_a_Slot_ae5_slot0_get, + Field_fld_ae_sem_rng_art_Slot_ae5_slot0_get, + Field_fld_ae_sem_rng_i2_Slot_ae5_slot0_get, + Field_fld_ae_sem_rng_imm2_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae5_slot0_set_field_fns[] = { + Field_t_Slot_ae5_slot0_set, + 0, + Field_bbi_Slot_ae5_slot0_set, + 0, + Field_imm8_Slot_ae5_slot0_set, + Field_s_Slot_ae5_slot0_set, + Field_s8_Slot_ae5_slot0_set, + 0, + Field_imm12b_Slot_ae5_slot0_set, + Field_imm16_Slot_ae5_slot0_set, + 0, + 0, + Field_offset_Slot_ae5_slot0_set, + 0, + 0, + Field_op2_Slot_ae5_slot0_set, + Field_r_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae5_slot0_set, + Field_sal_Slot_ae5_slot0_set, + Field_sargt_Slot_ae5_slot0_set, + 0, + Field_sas_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae5_slot0_set, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae5_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot0_set, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae5_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae5_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae5_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae5_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae5_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae5_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_su_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_vu_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_x_Slot_ae5_slot0_set, + Field_fld_ae_sem_pks_d_Slot_ae5_slot0_set, + Field_fld_ae_sem_pks_pos_Slot_ae5_slot0_set, + Field_fld_ae_sem_pks_s_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae5_slot0_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot0_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_ardecnorm16_ar_u_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_12_6_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_17_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_19_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_6_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_7_0_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_set, + Field_fld_ae_sem_lb_db_ops_ar_u_Slot_ae5_slot0_set, + Field_fld_ae_sem_lb_db_ops_iba_Slot_ae5_slot0_set, + Field_fld_ae_sem_rng_a_Slot_ae5_slot0_set, + Field_fld_ae_sem_rng_art_Slot_ae5_slot0_set, + Field_fld_ae_sem_rng_i2_Slot_ae5_slot0_set, + Field_fld_ae_sem_rng_imm2_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae5_slot1_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot1_1_0_Slot_ae5_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae5_slot1_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot1_1_0_Slot_ae5_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae5_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot2_get, + 0, + Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot2_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot2_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae5_slot2_get, + Field_fld_ae_sem_pks_pos_Slot_ae5_slot2_get, + Field_fld_ae_sem_pks_s_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae5_slot2_get, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae5_slot2_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae5_slot2_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae5_slot2_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae5_slot2_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae5_slot2_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae5_slot2_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae5_slot2_get, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae5_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae5_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae5_slot2_get, + Field_fld_ae_sem_multiply_q1_Slot_ae5_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae5_slot2_get, + Field_fld_ae_sem_select_ss_Slot_ae5_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae5_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae5_slot2_get, + 0, + Field_fld_ae_sem_spaddsub_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae5_slot2_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae5_slot2_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae5_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_spfma_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_spfma_vs_Slot_ae5_slot2_get, + Field_fld_ae_sem_spfma_vt_Slot_ae5_slot2_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae5_slot2_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae5_slot2_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_14_5_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_24_0_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_9_7_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae5_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot2_set, + 0, + Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot2_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot2_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae5_slot2_set, + Field_fld_ae_sem_pks_pos_Slot_ae5_slot2_set, + Field_fld_ae_sem_pks_s_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae5_slot2_set, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae5_slot2_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae5_slot2_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae5_slot2_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae5_slot2_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae5_slot2_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae5_slot2_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae5_slot2_set, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae5_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae5_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae5_slot2_set, + Field_fld_ae_sem_multiply_q1_Slot_ae5_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae5_slot2_set, + Field_fld_ae_sem_select_ss_Slot_ae5_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae5_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae5_slot2_set, + 0, + Field_fld_ae_sem_spaddsub_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae5_slot2_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae5_slot2_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae5_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_spfma_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_spfma_vs_Slot_ae5_slot2_set, + Field_fld_ae_sem_spfma_vt_Slot_ae5_slot2_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae5_slot2_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae5_slot2_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_14_5_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_24_0_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_9_7_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot0_get_field_fns[] = { + Field_t_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae6_slot0_get, + 0, + Field_r2_Slot_ae6_slot0_get, + Field_t4_Slot_ae6_slot0_get, + 0, + Field_r4_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot0_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot0_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot0_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot0_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot0_get, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot0_get, + Field_fld_ae_sem_pks_d_Slot_ae6_slot0_get, + Field_fld_ae_sem_pks_pos_Slot_ae6_slot0_get, + Field_fld_ae_sem_pks_s_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_5_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_7_4_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot0_set_field_fns[] = { + Field_t_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae6_slot0_set, + 0, + Field_r2_Slot_ae6_slot0_set, + Field_t4_Slot_ae6_slot0_set, + 0, + Field_r4_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot0_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot0_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot0_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot0_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot0_set, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot0_set, + Field_fld_ae_sem_pks_d_Slot_ae6_slot0_set, + Field_fld_ae_sem_pks_pos_Slot_ae6_slot0_set, + Field_fld_ae_sem_pks_s_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_5_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_7_4_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot1_get_field_fns[] = { + Field_t_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + Field_s_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae6_slot1_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae6_slot1_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot1_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot1_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot1_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae6_slot1_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae6_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae6_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot1_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae6_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae6_slot1_get, + Field_fld_ae_sem_shift_d_Slot_ae6_slot1_get, + Field_fld_ae_sem_shift_d0_Slot_ae6_slot1_get, + 0, + Field_fld_ae_sem_shift_da_Slot_ae6_slot1_get, + Field_fld_ae_sem_shift_i16_Slot_ae6_slot1_get, + Field_fld_ae_sem_shift_i32_Slot_ae6_slot1_get, + Field_fld_ae_sem_shift_i64_Slot_ae6_slot1_get, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_21_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_3_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_2_0_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_9_5_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot1_set_field_fns[] = { + Field_t_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + Field_s_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae6_slot1_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae6_slot1_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot1_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot1_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot1_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae6_slot1_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae6_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae6_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot1_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae6_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae6_slot1_set, + Field_fld_ae_sem_shift_d_Slot_ae6_slot1_set, + Field_fld_ae_sem_shift_d0_Slot_ae6_slot1_set, + 0, + Field_fld_ae_sem_shift_da_Slot_ae6_slot1_set, + Field_fld_ae_sem_shift_i16_Slot_ae6_slot1_set, + Field_fld_ae_sem_shift_i32_Slot_ae6_slot1_set, + Field_fld_ae_sem_shift_i64_Slot_ae6_slot1_set, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_21_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_3_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_2_0_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_9_5_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot2_get_field_fns[] = { + Field_t_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae6_slot2_get, + 0, + 0, + Field_t4_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot2_get, + 0, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot2_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae6_slot2_get, + Field_fld_ae_sem_pks_pos_Slot_ae6_slot2_get, + Field_fld_ae_sem_pks_s_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae6_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae6_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_24_0_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_24_10_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_24_20_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot2_set_field_fns[] = { + Field_t_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae6_slot2_set, + 0, + 0, + Field_t4_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot2_set, + 0, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot2_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae6_slot2_set, + Field_fld_ae_sem_pks_pos_Slot_ae6_slot2_set, + Field_fld_ae_sem_pks_s_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae6_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae6_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_24_0_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_24_10_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_24_20_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r2_Slot_ae6_slot3_get, + 0, + 0, + Field_r4_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot3_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot3_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot3_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot3_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot3_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot3_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae6_slot3_get, + Field_fld_ae_sem_multiply_d2_Slot_ae6_slot3_get, + Field_fld_ae_sem_multiply_q0_Slot_ae6_slot3_get, + Field_fld_ae_sem_multiply_q1_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae6_slot3_get, + Field_fld_ae_sem_multiply_d3_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_12_0_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_14_0_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_24_20_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_37_13_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r2_Slot_ae6_slot3_set, + 0, + 0, + Field_r4_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot3_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot3_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot3_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot3_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot3_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot3_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae6_slot3_set, + Field_fld_ae_sem_multiply_d2_Slot_ae6_slot3_set, + Field_fld_ae_sem_multiply_q0_Slot_ae6_slot3_set, + Field_fld_ae_sem_multiply_q1_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae6_slot3_set, + Field_fld_ae_sem_multiply_d3_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_12_0_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_14_0_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_24_20_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_37_13_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot0_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_12_6_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_23_0_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot0_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_12_6_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_23_0_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot1_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_12_6_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_23_0_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot1_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_12_6_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_23_0_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae7_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae7_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae7_slot2_get, + Field_fld_ae_sem_multiply_q1_Slot_ae7_slot2_get, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae7_slot2_get, + Field_fld_ae_sem_reduction_sort_v_Slot_ae7_slot2_get, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_isel_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_ss_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_vu_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae7_slot2_get, + Field_fld_ae_sem_multiply_d3_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot2_11_0_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_14_10_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_36_12_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae7_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae7_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae7_slot2_set, + Field_fld_ae_sem_multiply_q1_Slot_ae7_slot2_set, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae7_slot2_set, + Field_fld_ae_sem_reduction_sort_v_Slot_ae7_slot2_set, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_isel_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_ss_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_vu_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae7_slot2_set, + Field_fld_ae_sem_multiply_d3_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot2_11_0_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_14_10_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_36_12_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae7_slot3_get, + Field_fld_ae_sem_multiply_d2_Slot_ae7_slot3_get, + Field_fld_ae_sem_multiply_q0_Slot_ae7_slot3_get, + Field_fld_ae_sem_multiply_q1_Slot_ae7_slot3_get, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae7_slot3_get, + Field_fld_ae_sem_select_ss_Slot_ae7_slot3_get, + Field_fld_ae_sem_select_vr_Slot_ae7_slot3_get, + Field_fld_ae_sem_select_vs_Slot_ae7_slot3_get, + Field_fld_ae_sem_select_vt_Slot_ae7_slot3_get, + Field_fld_ae_sem_select_vu_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae7_slot3_get, + Field_fld_ae_sem_multiply_d3_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot3_10_0_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_24_10_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_35_11_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_4_0_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae7_slot3_set, + Field_fld_ae_sem_multiply_d2_Slot_ae7_slot3_set, + Field_fld_ae_sem_multiply_q0_Slot_ae7_slot3_set, + Field_fld_ae_sem_multiply_q1_Slot_ae7_slot3_set, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae7_slot3_set, + Field_fld_ae_sem_select_ss_Slot_ae7_slot3_set, + Field_fld_ae_sem_select_vr_Slot_ae7_slot3_set, + Field_fld_ae_sem_select_vs_Slot_ae7_slot3_set, + Field_fld_ae_sem_select_vt_Slot_ae7_slot3_set, + Field_fld_ae_sem_select_vu_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae7_slot3_set, + Field_fld_ae_sem_multiply_d3_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot3_10_0_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_24_10_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_35_11_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_4_0_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae8_slot0_get_field_fns[] = { + Field_t_Slot_ae8_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae8_slot0_get, + Field_s_Slot_ae8_slot0_get, + Field_s8_Slot_ae8_slot0_get, + 0, + Field_imm12b_Slot_ae8_slot0_get, + Field_imm16_Slot_ae8_slot0_get, + 0, + 0, + Field_offset_Slot_ae8_slot0_get, + 0, + 0, + Field_op2_Slot_ae8_slot0_get, + Field_r_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae8_slot0_get, + Field_sal_Slot_ae8_slot0_get, + Field_sargt_Slot_ae8_slot0_get, + 0, + Field_sas_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae8_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae8_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae8_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot0_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_su_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae8_slot0_get, + Field_fld_ae_sem_shift_d_Slot_ae8_slot0_get, + Field_fld_ae_sem_shift_d0_Slot_ae8_slot0_get, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae8_slot0_get, + Field_fld_ae_sem_shift_i32_Slot_ae8_slot0_get, + Field_fld_ae_sem_shift_i64_Slot_ae8_slot0_get, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_13_13_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_17_8_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_21_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_22_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_23_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_7_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_9_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_6_0_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_7_5_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_8_0_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae8_slot0_set_field_fns[] = { + Field_t_Slot_ae8_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae8_slot0_set, + Field_s_Slot_ae8_slot0_set, + Field_s8_Slot_ae8_slot0_set, + 0, + Field_imm12b_Slot_ae8_slot0_set, + Field_imm16_Slot_ae8_slot0_set, + 0, + 0, + Field_offset_Slot_ae8_slot0_set, + 0, + 0, + Field_op2_Slot_ae8_slot0_set, + Field_r_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae8_slot0_set, + Field_sal_Slot_ae8_slot0_set, + Field_sargt_Slot_ae8_slot0_set, + 0, + Field_sas_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae8_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae8_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae8_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot0_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_su_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae8_slot0_set, + Field_fld_ae_sem_shift_d_Slot_ae8_slot0_set, + Field_fld_ae_sem_shift_d0_Slot_ae8_slot0_set, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae8_slot0_set, + Field_fld_ae_sem_shift_i32_Slot_ae8_slot0_set, + Field_fld_ae_sem_shift_i64_Slot_ae8_slot0_set, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_13_13_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_17_8_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_21_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_22_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_23_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_7_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_9_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_6_0_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_7_5_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_8_0_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae8_slot1_get_field_fns[] = { + Field_t_Slot_ae8_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae8_slot1_get, + Field_s_Slot_ae8_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae8_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae8_slot1_get, + Field_r_Slot_ae8_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae8_slot1_get, + Field_sal_Slot_ae8_slot1_get, + Field_sargt_Slot_ae8_slot1_get, + 0, + Field_sas_Slot_ae8_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot1_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_17_15_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_22_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_23_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_5_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_9_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_4_0_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae8_slot1_set_field_fns[] = { + Field_t_Slot_ae8_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae8_slot1_set, + Field_s_Slot_ae8_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae8_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae8_slot1_set, + Field_r_Slot_ae8_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae8_slot1_set, + Field_sal_Slot_ae8_slot1_set, + Field_sargt_Slot_ae8_slot1_set, + 0, + Field_sas_Slot_ae8_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot1_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_17_15_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_22_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_23_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_5_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_9_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_4_0_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae8_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_19_15_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_33_25_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_33_9_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_8_0_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_c0_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_c1_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_c2_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_c3_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_q0_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_q1_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_q2_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_q3_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_v0_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_v1_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_v2_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_v3_Slot_ae8_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae8_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_19_15_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_33_25_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_33_9_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_8_0_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_c0_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_c1_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_c2_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_c3_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_q0_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_q1_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_q2_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_q3_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_v0_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_v1_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_v2_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_v3_Slot_ae8_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae9_slot0_get_field_fns[] = { + Field_t_Slot_ae9_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae9_slot0_get, + Field_s_Slot_ae9_slot0_get, + Field_s8_Slot_ae9_slot0_get, + 0, + Field_imm12b_Slot_ae9_slot0_get, + Field_imm16_Slot_ae9_slot0_get, + 0, + 0, + Field_offset_Slot_ae9_slot0_get, + 0, + 0, + Field_op2_Slot_ae9_slot0_get, + Field_r_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae9_slot0_get, + Field_sal_Slot_ae9_slot0_get, + Field_sargt_Slot_ae9_slot0_get, + 0, + Field_sas_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r2_Slot_ae9_slot0_get, + 0, + Field_s4_Slot_ae9_slot0_get, + Field_r4_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v0_Slot_ae9_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae9_slot0_get, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae9_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae9_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae9_slot0_get, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae9_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_su_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae9_slot0_get, + Field_fld_ae_sem_sp32cvt_art_Slot_ae9_slot0_get, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae9_slot0_get, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae9_slot0_get, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae9_slot0_get, + Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot0_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot0_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_17_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_19_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_22_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_3_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_2_0_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_7_6_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae9_slot0_set_field_fns[] = { + Field_t_Slot_ae9_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae9_slot0_set, + Field_s_Slot_ae9_slot0_set, + Field_s8_Slot_ae9_slot0_set, + 0, + Field_imm12b_Slot_ae9_slot0_set, + Field_imm16_Slot_ae9_slot0_set, + 0, + 0, + Field_offset_Slot_ae9_slot0_set, + 0, + 0, + Field_op2_Slot_ae9_slot0_set, + Field_r_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae9_slot0_set, + Field_sal_Slot_ae9_slot0_set, + Field_sargt_Slot_ae9_slot0_set, + 0, + Field_sas_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r2_Slot_ae9_slot0_set, + 0, + Field_s4_Slot_ae9_slot0_set, + Field_r4_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v0_Slot_ae9_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae9_slot0_set, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae9_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae9_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae9_slot0_set, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae9_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_su_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae9_slot0_set, + Field_fld_ae_sem_sp32cvt_art_Slot_ae9_slot0_set, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae9_slot0_set, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae9_slot0_set, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae9_slot0_set, + Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot0_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot0_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_17_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_19_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_22_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_3_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_2_0_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_7_6_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae9_slot1_get_field_fns[] = { + Field_t_Slot_ae9_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae9_slot1_get, + Field_s_Slot_ae9_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae9_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae9_slot1_get, + Field_r_Slot_ae9_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae9_slot1_get, + Field_sal_Slot_ae9_slot1_get, + Field_sargt_Slot_ae9_slot1_get, + 0, + Field_sas_Slot_ae9_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_1_0_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_17_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_2_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_22_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_23_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_9_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_3_2_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae9_slot1_set_field_fns[] = { + Field_t_Slot_ae9_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae9_slot1_set, + Field_s_Slot_ae9_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae9_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae9_slot1_set, + Field_r_Slot_ae9_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae9_slot1_set, + Field_sal_Slot_ae9_slot1_set, + Field_sargt_Slot_ae9_slot1_set, + 0, + Field_sas_Slot_ae9_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_1_0_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_17_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_2_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_22_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_23_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_9_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_3_2_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae9_slot2_get_field_fns[] = { + Field_t_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae9_slot2_get, + 0, + 0, + Field_t4_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot2_get, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot2_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot2_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot2_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot2_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae9_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae9_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae9_slot2_get, + Field_fld_ae_sem_select_vu_Slot_ae9_slot2_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot2_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot2_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_vp_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_vs_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_vt_Slot_ae9_slot2_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot2_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot2_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spaddsub_vp_Slot_ae9_slot2_get, + Field_fld_ae_sem_spaddsub_vq_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_9_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_8_0_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpfma_vp_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpfma_vu_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_vu_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae9_slot2_set_field_fns[] = { + Field_t_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae9_slot2_set, + 0, + 0, + Field_t4_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot2_set, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot2_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot2_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot2_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot2_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae9_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae9_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae9_slot2_set, + Field_fld_ae_sem_select_vu_Slot_ae9_slot2_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot2_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot2_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_vp_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_vs_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_vt_Slot_ae9_slot2_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot2_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot2_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spaddsub_vp_Slot_ae9_slot2_set, + Field_fld_ae_sem_spaddsub_vq_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_9_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_8_0_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpfma_vp_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpfma_vu_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_vu_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae9_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot3_get, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot3_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot3_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot3_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot3_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot3_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot3_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot3_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot3_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot3_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae9_slot3_get, + Field_fld_ae_sem_select_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_select_vs_Slot_ae9_slot3_get, + Field_fld_ae_sem_select_vt_Slot_ae9_slot3_get, + Field_fld_ae_sem_select_vu_Slot_ae9_slot3_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot3_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot3_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_vp_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_vs_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_vt_Slot_ae9_slot3_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot3_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot3_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spfma_vu_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_7_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_4_4_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_6_0_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae9_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot3_set, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot3_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot3_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot3_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot3_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot3_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot3_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot3_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot3_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot3_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae9_slot3_set, + Field_fld_ae_sem_select_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_select_vs_Slot_ae9_slot3_set, + Field_fld_ae_sem_select_vt_Slot_ae9_slot3_set, + Field_fld_ae_sem_select_vu_Slot_ae9_slot3_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot3_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot3_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_vp_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_vs_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_vt_Slot_ae9_slot3_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot3_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot3_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spfma_vu_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_7_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_4_4_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_6_0_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae10_slot0_get_field_fns[] = { + Field_t_Slot_ae10_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae10_slot0_get, + Field_s_Slot_ae10_slot0_get, + Field_s8_Slot_ae10_slot0_get, + 0, + Field_imm12b_Slot_ae10_slot0_get, + Field_imm16_Slot_ae10_slot0_get, + 0, + 0, + Field_offset_Slot_ae10_slot0_get, + 0, + 0, + Field_op2_Slot_ae10_slot0_get, + Field_r_Slot_ae10_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae10_slot0_get, + Field_sal_Slot_ae10_slot0_get, + Field_sargt_Slot_ae10_slot0_get, + 0, + Field_sas_Slot_ae10_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae10_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot0_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_17_8_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_0_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_17_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_7_6_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae10_slot0_set_field_fns[] = { + Field_t_Slot_ae10_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae10_slot0_set, + Field_s_Slot_ae10_slot0_set, + Field_s8_Slot_ae10_slot0_set, + 0, + Field_imm12b_Slot_ae10_slot0_set, + Field_imm16_Slot_ae10_slot0_set, + 0, + 0, + Field_offset_Slot_ae10_slot0_set, + 0, + 0, + Field_op2_Slot_ae10_slot0_set, + Field_r_Slot_ae10_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae10_slot0_set, + Field_sal_Slot_ae10_slot0_set, + Field_sargt_Slot_ae10_slot0_set, + 0, + Field_sas_Slot_ae10_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae10_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot0_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_17_8_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_0_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_17_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_7_6_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae10_slot1_get_field_fns[] = { + Field_t_Slot_ae10_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae10_slot1_get, + Field_s_Slot_ae10_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae10_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae10_slot1_get, + Field_r_Slot_ae10_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae10_slot1_get, + Field_sal_Slot_ae10_slot1_get, + Field_sargt_Slot_ae10_slot1_get, + 0, + Field_sas_Slot_ae10_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae10_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot1_0_0_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_1_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_17_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_22_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_23_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_9_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_3_2_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae10_slot1_set_field_fns[] = { + Field_t_Slot_ae10_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae10_slot1_set, + Field_s_Slot_ae10_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae10_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae10_slot1_set, + Field_r_Slot_ae10_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae10_slot1_set, + Field_sal_Slot_ae10_slot1_set, + Field_sargt_Slot_ae10_slot1_set, + 0, + Field_sas_Slot_ae10_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae10_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot1_0_0_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_1_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_17_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_22_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_23_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_9_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_3_2_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae10_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot2_get, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot2_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot2_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot2_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot2_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae10_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae10_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae10_slot2_get, + Field_fld_ae_sem_select_vu_Slot_ae10_slot2_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot2_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot2_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vp_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vs_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vt_Slot_ae10_slot2_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot2_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot2_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spaddsub_vp_Slot_ae10_slot2_get, + Field_fld_ae_sem_spaddsub_vq_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vu_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_10_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vq_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae10_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot2_set, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot2_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot2_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot2_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot2_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae10_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae10_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae10_slot2_set, + Field_fld_ae_sem_select_vu_Slot_ae10_slot2_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot2_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot2_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vp_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vs_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vt_Slot_ae10_slot2_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot2_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot2_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spaddsub_vp_Slot_ae10_slot2_set, + Field_fld_ae_sem_spaddsub_vq_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vu_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_10_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vq_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae10_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae10_slot3_get, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot3_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae10_slot3_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae10_slot3_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot3_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot3_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot3_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot3_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot3_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot3_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae10_slot3_get, + Field_fld_ae_sem_select_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_select_vs_Slot_ae10_slot3_get, + Field_fld_ae_sem_select_vt_Slot_ae10_slot3_get, + Field_fld_ae_sem_select_vu_Slot_ae10_slot3_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot3_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot3_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vp_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vs_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vt_Slot_ae10_slot3_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot3_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot3_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot3_get, + Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vu_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vq_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_10_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_4_4_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae10_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae10_slot3_set, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot3_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae10_slot3_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae10_slot3_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot3_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot3_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot3_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot3_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot3_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot3_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae10_slot3_set, + Field_fld_ae_sem_select_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_select_vs_Slot_ae10_slot3_set, + Field_fld_ae_sem_select_vt_Slot_ae10_slot3_set, + Field_fld_ae_sem_select_vu_Slot_ae10_slot3_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot3_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot3_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vp_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vs_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vt_Slot_ae10_slot3_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot3_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot3_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot3_set, + Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vu_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vq_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_10_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_4_4_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot0_get_field_fns[] = { + Field_t_Slot_ae4_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae4_slot0_get, + Field_s_Slot_ae4_slot0_get, + Field_s8_Slot_ae4_slot0_get, + 0, + Field_imm12b_Slot_ae4_slot0_get, + Field_imm16_Slot_ae4_slot0_get, + 0, + 0, + Field_offset_Slot_ae4_slot0_get, + 0, + 0, + Field_op2_Slot_ae4_slot0_get, + Field_r_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae4_slot0_get, + Field_sal_Slot_ae4_slot0_get, + Field_sargt_Slot_ae4_slot0_get, + 0, + Field_sas_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot0_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot0_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot0_22_0_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_17_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_20_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_3_1_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot0_set_field_fns[] = { + Field_t_Slot_ae4_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae4_slot0_set, + Field_s_Slot_ae4_slot0_set, + Field_s8_Slot_ae4_slot0_set, + 0, + Field_imm12b_Slot_ae4_slot0_set, + Field_imm16_Slot_ae4_slot0_set, + 0, + 0, + Field_offset_Slot_ae4_slot0_set, + 0, + 0, + Field_op2_Slot_ae4_slot0_set, + Field_r_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae4_slot0_set, + Field_sal_Slot_ae4_slot0_set, + Field_sargt_Slot_ae4_slot0_set, + 0, + Field_sas_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot0_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot0_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot0_22_0_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_17_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_20_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_3_1_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot1_get_field_fns[] = { + Field_t_Slot_ae4_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae4_slot1_get, + Field_s_Slot_ae4_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae4_slot1_get, + Field_r_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae4_slot1_get, + Field_sal_Slot_ae4_slot1_get, + Field_sargt_Slot_ae4_slot1_get, + 0, + Field_sas_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot1_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot1_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot1_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot1_22_0_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_17_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_3_1_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot1_set_field_fns[] = { + Field_t_Slot_ae4_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae4_slot1_set, + Field_s_Slot_ae4_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae4_slot1_set, + Field_r_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae4_slot1_set, + Field_sal_Slot_ae4_slot1_set, + Field_sargt_Slot_ae4_slot1_set, + 0, + Field_sas_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot1_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot1_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot1_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot1_22_0_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_17_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_3_1_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot2_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot2_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot2_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot2_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae4_slot2_get, + Field_fld_ae_sem_pks_pos_Slot_ae4_slot2_get, + Field_fld_ae_sem_pks_s_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae4_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae4_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot2_23_0_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_23_17_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_4_0_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot2_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot2_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot2_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot2_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae4_slot2_set, + Field_fld_ae_sem_pks_pos_Slot_ae4_slot2_set, + Field_fld_ae_sem_pks_s_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae4_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae4_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot2_23_0_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_23_17_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_4_0_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot3_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot3_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot3_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae4_slot3_get, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot3_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae4_slot3_get, + Field_fld_ae_sem_multiply_d2_Slot_ae4_slot3_get, + Field_fld_ae_sem_multiply_q0_Slot_ae4_slot3_get, + Field_fld_ae_sem_multiply_q1_Slot_ae4_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae4_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot3_14_10_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_19_19_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_19_5_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_27_20_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_27_3_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_2_0_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot3_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot3_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot3_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae4_slot3_set, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot3_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae4_slot3_set, + Field_fld_ae_sem_multiply_d2_Slot_ae4_slot3_set, + Field_fld_ae_sem_multiply_q0_Slot_ae4_slot3_set, + Field_fld_ae_sem_multiply_q1_Slot_ae4_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae4_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot3_14_10_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_19_19_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_19_5_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_27_20_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_27_3_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_2_0_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot4_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot4_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot4_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot4_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot4_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot4_22_0_Slot_ae4_slot4_get, + Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get, + Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get, + Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot4_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot4_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot4_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot4_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot4_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot4_22_0_Slot_ae4_slot4_set, + Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_set, + Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_set, + Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_slot_internal slots[] = { + { "Inst", "x24", 0, + Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, + Slot_inst_get_field_fns, Slot_inst_set_field_fns, + Slot_inst_decode, "nop" }, + { "Inst16a", "x16a", 0, + Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, + Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, + Slot_inst16a_decode, "" }, + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, + Slot_inst16b_decode, "nop.n" }, + { "ae_slot0", "ae_format", 0, + Slot_ae_format_Format_ae_slot0_4_get, Slot_ae_format_Format_ae_slot0_4_set, + Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns, + Slot_ae_slot0_decode, "nop" }, + { "ae_slot1", "ae_format", 1, + Slot_ae_format_Format_ae_slot1_72_get, Slot_ae_format_Format_ae_slot1_72_set, + Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns, + Slot_ae_slot1_decode, "nop" }, + { "ae_slot2", "ae_format", 2, + Slot_ae_format_Format_ae_slot2_16_get, Slot_ae_format_Format_ae_slot2_16_set, + Slot_ae_slot2_get_field_fns, Slot_ae_slot2_set_field_fns, + Slot_ae_slot2_decode, "nop" }, + { "ae_slot3", "ae_format", 3, + Slot_ae_format_Format_ae_slot3_45_get, Slot_ae_format_Format_ae_slot3_45_set, + Slot_ae_slot3_get_field_fns, Slot_ae_slot3_set_field_fns, + Slot_ae_slot3_decode, "nop" }, + { "ae2_slot0", "ae_format_2", 0, + Slot_ae_format_2_Format_ae2_slot0_4_get, Slot_ae_format_2_Format_ae2_slot0_4_set, + Slot_ae2_slot0_get_field_fns, Slot_ae2_slot0_set_field_fns, + Slot_ae2_slot0_decode, "nop" }, + { "ae2_slot1", "ae_format_2", 1, + Slot_ae_format_2_Format_ae2_slot1_12_get, Slot_ae_format_2_Format_ae2_slot1_12_set, + Slot_ae2_slot1_get_field_fns, Slot_ae2_slot1_set_field_fns, + Slot_ae2_slot1_decode, "nop" }, + { "ae2_slot2", "ae_format_2", 2, + Slot_ae_format_2_Format_ae2_slot2_16_get, Slot_ae_format_2_Format_ae2_slot2_16_set, + Slot_ae2_slot2_get_field_fns, Slot_ae2_slot2_set_field_fns, + Slot_ae2_slot2_decode, "nop" }, + { "ae3_slot0", "ae_format_3", 0, + Slot_ae_format_3_Format_ae3_slot0_4_get, Slot_ae_format_3_Format_ae3_slot0_4_set, + Slot_ae3_slot0_get_field_fns, Slot_ae3_slot0_set_field_fns, + Slot_ae3_slot0_decode, "nop" }, + { "ae3_slot1", "ae_format_3", 1, + Slot_ae_format_3_Format_ae3_slot1_12_get, Slot_ae_format_3_Format_ae3_slot1_12_set, + Slot_ae3_slot1_get_field_fns, Slot_ae3_slot1_set_field_fns, + Slot_ae3_slot1_decode, "nop" }, + { "ae5_slot0", "ae_format_5", 0, + Slot_ae_format_5_Format_ae5_slot0_4_get, Slot_ae_format_5_Format_ae5_slot0_4_set, + Slot_ae5_slot0_get_field_fns, Slot_ae5_slot0_set_field_fns, + Slot_ae5_slot0_decode, "nop" }, + { "ae5_slot1", "ae_format_5", 1, + Slot_ae_format_5_Format_ae5_slot1_56_get, Slot_ae_format_5_Format_ae5_slot1_56_set, + Slot_ae5_slot1_get_field_fns, Slot_ae5_slot1_set_field_fns, + Slot_ae5_slot1_decode, "nop" }, + { "ae5_slot2", "ae_format_5", 2, + Slot_ae_format_5_Format_ae5_slot2_16_get, Slot_ae_format_5_Format_ae5_slot2_16_set, + Slot_ae5_slot2_get_field_fns, Slot_ae5_slot2_set_field_fns, + Slot_ae5_slot2_decode, "nop" }, + { "ae6_slot0", "ae_format_6", 0, + Slot_ae_format_6_Format_ae6_slot0_4_get, Slot_ae_format_6_Format_ae6_slot0_4_set, + Slot_ae6_slot0_get_field_fns, Slot_ae6_slot0_set_field_fns, + Slot_ae6_slot0_decode, "nop" }, + { "ae6_slot1", "ae_format_6", 1, + Slot_ae_format_6_Format_ae6_slot1_57_get, Slot_ae_format_6_Format_ae6_slot1_57_set, + Slot_ae6_slot1_get_field_fns, Slot_ae6_slot1_set_field_fns, + Slot_ae6_slot1_decode, "nop" }, + { "ae6_slot2", "ae_format_6", 2, + Slot_ae_format_6_Format_ae6_slot2_16_get, Slot_ae_format_6_Format_ae6_slot2_16_set, + Slot_ae6_slot2_get_field_fns, Slot_ae6_slot2_set_field_fns, + Slot_ae6_slot2_decode, "nop" }, + { "ae6_slot3", "ae_format_6", 3, + Slot_ae_format_6_Format_ae6_slot3_8_get, Slot_ae_format_6_Format_ae6_slot3_8_set, + Slot_ae6_slot3_get_field_fns, Slot_ae6_slot3_set_field_fns, + Slot_ae6_slot3_decode, "nop" }, + { "ae7_slot0", "ae_format_7", 0, + Slot_ae_format_7_Format_ae7_slot0_4_get, Slot_ae_format_7_Format_ae7_slot0_4_set, + Slot_ae7_slot0_get_field_fns, Slot_ae7_slot0_set_field_fns, + Slot_ae7_slot0_decode, "nop" }, + { "ae7_slot1", "ae_format_7", 1, + Slot_ae_format_7_Format_ae7_slot1_72_get, Slot_ae_format_7_Format_ae7_slot1_72_set, + Slot_ae7_slot1_get_field_fns, Slot_ae7_slot1_set_field_fns, + Slot_ae7_slot1_decode, "nop" }, + { "ae7_slot2", "ae_format_7", 2, + Slot_ae_format_7_Format_ae7_slot2_16_get, Slot_ae_format_7_Format_ae7_slot2_16_set, + Slot_ae7_slot2_get_field_fns, Slot_ae7_slot2_set_field_fns, + Slot_ae7_slot2_decode, "nop" }, + { "ae7_slot3", "ae_format_7", 3, + Slot_ae_format_7_Format_ae7_slot3_45_get, Slot_ae_format_7_Format_ae7_slot3_45_set, + Slot_ae7_slot3_get_field_fns, Slot_ae7_slot3_set_field_fns, + Slot_ae7_slot3_decode, "nop" }, + { "ae8_slot0", "ae_format_8", 0, + Slot_ae_format_8_Format_ae8_slot0_4_get, Slot_ae_format_8_Format_ae8_slot0_4_set, + Slot_ae8_slot0_get_field_fns, Slot_ae8_slot0_set_field_fns, + Slot_ae8_slot0_decode, "nop" }, + { "ae8_slot1", "ae_format_8", 1, + Slot_ae_format_8_Format_ae8_slot1_14_get, Slot_ae_format_8_Format_ae8_slot1_14_set, + Slot_ae8_slot1_get_field_fns, Slot_ae8_slot1_set_field_fns, + Slot_ae8_slot1_decode, "nop" }, + { "ae8_slot2", "ae_format_8", 2, + Slot_ae_format_8_Format_ae8_slot2_16_get, Slot_ae_format_8_Format_ae8_slot2_16_set, + Slot_ae8_slot2_get_field_fns, Slot_ae8_slot2_set_field_fns, + Slot_ae8_slot2_decode, "nop" }, + { "ae9_slot0", "ae_format_9", 0, + Slot_ae_format_9_Format_ae9_slot0_4_get, Slot_ae_format_9_Format_ae9_slot0_4_set, + Slot_ae9_slot0_get_field_fns, Slot_ae9_slot0_set_field_fns, + Slot_ae9_slot0_decode, "nop" }, + { "ae9_slot1", "ae_format_9", 1, + Slot_ae_format_9_Format_ae9_slot1_72_get, Slot_ae_format_9_Format_ae9_slot1_72_set, + Slot_ae9_slot1_get_field_fns, Slot_ae9_slot1_set_field_fns, + Slot_ae9_slot1_decode, "nop" }, + { "ae9_slot2", "ae_format_9", 2, + Slot_ae_format_9_Format_ae9_slot2_16_get, Slot_ae_format_9_Format_ae9_slot2_16_set, + Slot_ae9_slot2_get_field_fns, Slot_ae9_slot2_set_field_fns, + Slot_ae9_slot2_decode, "nop" }, + { "ae9_slot3", "ae_format_9", 3, + Slot_ae_format_9_Format_ae9_slot3_45_get, Slot_ae_format_9_Format_ae9_slot3_45_set, + Slot_ae9_slot3_get_field_fns, Slot_ae9_slot3_set_field_fns, + Slot_ae9_slot3_decode, "nop" }, + { "ae10_slot0", "ae_format_10", 0, + Slot_ae_format_10_Format_ae10_slot0_4_get, Slot_ae_format_10_Format_ae10_slot0_4_set, + Slot_ae10_slot0_get_field_fns, Slot_ae10_slot0_set_field_fns, + Slot_ae10_slot0_decode, "nop" }, + { "ae10_slot1", "ae_format_10", 1, + Slot_ae_format_10_Format_ae10_slot1_34_get, Slot_ae_format_10_Format_ae10_slot1_34_set, + Slot_ae10_slot1_get_field_fns, Slot_ae10_slot1_set_field_fns, + Slot_ae10_slot1_decode, "nop" }, + { "ae10_slot2", "ae_format_10", 2, + Slot_ae_format_10_Format_ae10_slot2_16_get, Slot_ae_format_10_Format_ae10_slot2_16_set, + Slot_ae10_slot2_get_field_fns, Slot_ae10_slot2_set_field_fns, + Slot_ae10_slot2_decode, "nop" }, + { "ae10_slot3", "ae_format_10", 3, + Slot_ae_format_10_Format_ae10_slot3_27_get, Slot_ae_format_10_Format_ae10_slot3_27_set, + Slot_ae10_slot3_get_field_fns, Slot_ae10_slot3_set_field_fns, + Slot_ae10_slot3_decode, "nop" }, + { "ae4_slot0", "ae_format_4", 0, + Slot_ae_format_4_Format_ae4_slot0_4_get, Slot_ae_format_4_Format_ae4_slot0_4_set, + Slot_ae4_slot0_get_field_fns, Slot_ae4_slot0_set_field_fns, + Slot_ae4_slot0_decode, "nop" }, + { "ae4_slot1", "ae_format_4", 1, + Slot_ae_format_4_Format_ae4_slot1_72_get, Slot_ae_format_4_Format_ae4_slot1_72_set, + Slot_ae4_slot1_get_field_fns, Slot_ae4_slot1_set_field_fns, + Slot_ae4_slot1_decode, "nop" }, + { "ae4_slot2", "ae_format_4", 2, + Slot_ae_format_4_Format_ae4_slot2_16_get, Slot_ae_format_4_Format_ae4_slot2_16_set, + Slot_ae4_slot2_get_field_fns, Slot_ae4_slot2_set_field_fns, + Slot_ae4_slot2_decode, "nop" }, + { "ae4_slot3", "ae_format_4", 3, + Slot_ae_format_4_Format_ae4_slot3_26_get, Slot_ae_format_4_Format_ae4_slot3_26_set, + Slot_ae4_slot3_get_field_fns, Slot_ae4_slot3_set_field_fns, + Slot_ae4_slot3_decode, "nop" }, + { "ae4_slot4", "ae_format_4", 4, + Slot_ae_format_4_Format_ae4_slot4_43_get, Slot_ae_format_4_Format_ae4_slot4_43_set, + Slot_ae4_slot4_get_field_fns, Slot_ae4_slot4_set_field_fns, + Slot_ae4_slot4_decode, "nop" } +}; + + +/* Instruction formats. */ + +static void +Format_x24_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_x16a_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_x16b_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xf; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_2_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x2000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_3_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_5_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x2000000e; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_6_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x6000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_7_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_8_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xa000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_9_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_10_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_4_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x4000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static int Format_x24_slots[] = { 0 }; + +static int Format_x16a_slots[] = { 1 }; + +static int Format_x16b_slots[] = { 2 }; + +static int Format_ae_format_slots[] = { 3, 5, 6, 4 }; + +static int Format_ae_format_2_slots[] = { 7, 8, 9 }; + +static int Format_ae_format_3_slots[] = { 10, 11 }; + +static int Format_ae_format_5_slots[] = { 12, 14, 13 }; + +static int Format_ae_format_6_slots[] = { 15, 18, 17, 16 }; + +static int Format_ae_format_7_slots[] = { 19, 21, 22, 20 }; + +static int Format_ae_format_8_slots[] = { 23, 24, 25 }; + +static int Format_ae_format_9_slots[] = { 26, 28, 29, 27 }; + +static int Format_ae_format_10_slots[] = { 30, 32, 33, 31 }; + +static int Format_ae_format_4_slots[] = { 34, 36, 37, 38, 35 }; + +static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }, + { "ae_format", 16, Format_ae_format_encode, 4, Format_ae_format_slots }, + { "ae_format_2", 16, Format_ae_format_2_encode, 3, Format_ae_format_2_slots }, + { "ae_format_3", 8, Format_ae_format_3_encode, 2, Format_ae_format_3_slots }, + { "ae_format_5", 8, Format_ae_format_5_encode, 3, Format_ae_format_5_slots }, + { "ae_format_6", 16, Format_ae_format_6_encode, 4, Format_ae_format_6_slots }, + { "ae_format_7", 16, Format_ae_format_7_encode, 4, Format_ae_format_7_slots }, + { "ae_format_8", 16, Format_ae_format_8_encode, 3, Format_ae_format_8_slots }, + { "ae_format_9", 16, Format_ae_format_9_encode, 4, Format_ae_format_9_slots }, + { "ae_format_10", 16, Format_ae_format_10_encode, 4, Format_ae_format_10_slots }, + { "ae_format_4", 16, Format_ae_format_4_encode, 5, Format_ae_format_4_slots } +}; + + +static int +format_decoder (const xtensa_insnbuf insn) +{ + if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 0; /* x24 */ + if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 1; /* x16a */ + if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 2; /* x16b */ + if ((insn[0] & 0xe000000f) == 0xf && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 3; /* ae_format */ + if ((insn[0] & 0xe000000f) == 0x2000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 4; /* ae_format_2 */ + if ((insn[0] & 0xe000000f) == 0xe && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 5; /* ae_format_3 */ + if ((insn[0] & 0xe000000f) == 0x2000000e && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 6; /* ae_format_5 */ + if ((insn[0] & 0xe000000f) == 0x6000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 7; /* ae_format_6 */ + if ((insn[0] & 0xe000000f) == 0x8000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 8; /* ae_format_7 */ + if ((insn[0] & 0xe000000f) == 0xa000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 9; /* ae_format_8 */ + if ((insn[0] & 0xe000000f) == 0xc000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 10; /* ae_format_9 */ + if ((insn[0] & 0xe000000f) == 0xe000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 11; /* ae_format_10 */ + if ((insn[0] & 0xe000000f) == 0x4000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 12; /* ae_format_4 */ + return -1; +} + +static int length_table[256] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16 +}; + +static int +length_decoder (const unsigned char *insn) +{ + int l = insn[0]; + return length_table[l]; +} + + +/* Top-level ISA structure. */ + +xtensa_isa_internal xtensa_modules = { + 0 /* little-endian */, + 16 /* insn_size */, 0, + 13, formats, format_decoder, length_decoder, + 39, slots, + 886 /* num_fields */, + 1098, operands, + 2115, iclasses, + 2217, opcodes, 0, + 9, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, + 6, interfaces, 0, + 7, funcUnits, 0 +}; diff --git a/overlays/xtensa_mtk_mt818x_adsp/gdb/xtensa-regmap.c b/overlays/xtensa_mtk_mt818x_adsp/gdb/xtensa-regmap.c new file mode 100644 index 00000000..a1086beb --- /dev/null +++ b/overlays/xtensa_mtk_mt818x_adsp/gdb/xtensa-regmap.c @@ -0,0 +1,95 @@ +/* Customized table mapping between kernel xtregset and GDB register cache. + + Copyright (c) 2007-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +typedef struct { + int gdb_regnum; + int gdb_offset; + int ptrace_cp_offset; + int ptrace_offset; + int size; + int coproc; + int dbnum; + char* name +;} xtensa_regtable_t; + +#define XTENSA_ELF_XTREG_SIZE 404 + +const xtensa_regtable_t xtensa_regmap_table[] = { + /* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */ + { 76, 304, 0, 0, 4, -1, 0x0204, "br" }, + { 78, 312, 16, 32, 4, 1, 0x03f0, "ae_ovf_sar" }, + { 79, 316, 20, 36, 4, 1, 0x03f1, "ae_bithead" }, + { 80, 320, 24, 40, 4, 1, 0x03f2, "ae_ts_fts_bu_bp" }, + { 81, 324, 28, 44, 4, 1, 0x03f3, "ae_cw_sd_no" }, + { 82, 328, 32, 48, 4, 1, 0x03f6, "ae_cbegin0" }, + { 83, 332, 36, 52, 4, 1, 0x03f7, "ae_cend0" }, + { 84, 336, 40, 56, 4, 1, 0x03f8, "ae_cbegin1" }, + { 85, 340, 44, 60, 4, 1, 0x03f9, "ae_cend1" }, + { 86, 344, 48, 64, 4, 1, 0x03fa, "ae_cbegin2" }, + { 87, 348, 52, 68, 4, 1, 0x03fb, "ae_cend2" }, + { 88, 352, 128, 144, 8, 1, 0x1000, "aed0" }, + { 89, 360, 136, 152, 8, 1, 0x1001, "aed1" }, + { 90, 368, 144, 160, 8, 1, 0x1002, "aed2" }, + { 91, 376, 152, 168, 8, 1, 0x1003, "aed3" }, + { 92, 384, 160, 176, 8, 1, 0x1004, "aed4" }, + { 93, 392, 168, 184, 8, 1, 0x1005, "aed5" }, + { 94, 400, 176, 192, 8, 1, 0x1006, "aed6" }, + { 95, 408, 184, 200, 8, 1, 0x1007, "aed7" }, + { 96, 416, 192, 208, 8, 1, 0x1008, "aed8" }, + { 97, 424, 200, 216, 8, 1, 0x1009, "aed9" }, + { 98, 432, 208, 224, 8, 1, 0x100a, "aed10" }, + { 99, 440, 216, 232, 8, 1, 0x100b, "aed11" }, + { 100, 448, 224, 240, 8, 1, 0x100c, "aed12" }, + { 101, 456, 232, 248, 8, 1, 0x100d, "aed13" }, + { 102, 464, 240, 256, 8, 1, 0x100e, "aed14" }, + { 103, 472, 248, 264, 8, 1, 0x100f, "aed15" }, + { 104, 480, 256, 272, 8, 1, 0x1010, "aed16" }, + { 105, 488, 264, 280, 8, 1, 0x1011, "aed17" }, + { 106, 496, 272, 288, 8, 1, 0x1012, "aed18" }, + { 107, 504, 280, 296, 8, 1, 0x1013, "aed19" }, + { 108, 512, 288, 304, 8, 1, 0x1014, "aed20" }, + { 109, 520, 296, 312, 8, 1, 0x1015, "aed21" }, + { 110, 528, 304, 320, 8, 1, 0x1016, "aed22" }, + { 111, 536, 312, 328, 8, 1, 0x1017, "aed23" }, + { 112, 544, 320, 336, 8, 1, 0x1018, "aed24" }, + { 113, 552, 328, 344, 8, 1, 0x1019, "aed25" }, + { 114, 560, 336, 352, 8, 1, 0x101a, "aed26" }, + { 115, 568, 344, 360, 8, 1, 0x101b, "aed27" }, + { 116, 576, 352, 368, 8, 1, 0x101c, "aed28" }, + { 117, 584, 360, 376, 8, 1, 0x101d, "aed29" }, + { 118, 592, 368, 384, 8, 1, 0x101e, "aed30" }, + { 119, 600, 376, 392, 8, 1, 0x101f, "aed31" }, + { 120, 608, 64, 80, 16, 1, 0x1020, "u0" }, + { 121, 624, 80, 96, 16, 1, 0x1021, "u1" }, + { 122, 640, 96, 112, 16, 1, 0x1022, "u2" }, + { 123, 656, 112, 128, 16, 1, 0x1023, "u3" }, + { 124, 672, 384, 400, 1, 1, 0x1024, "aep0" }, + { 125, 673, 385, 401, 1, 1, 0x1025, "aep1" }, + { 126, 674, 386, 402, 1, 1, 0x1026, "aep2" }, + { 127, 675, 387, 403, 1, 1, 0x1027, "aep3" }, + { 128, 676, 0, 16, 4, 1, 0x1029, "ae_zbiasv8c" }, + { 129, 680, 8, 24, 4, 1, 0x102a, "fcr_fsr" }, + { 0 } +}; + diff --git a/overlays/xtensa_mtk_mt818x_adsp/gdb/xtensa-xtregs.c b/overlays/xtensa_mtk_mt818x_adsp/gdb/xtensa-xtregs.c new file mode 100644 index 00000000..a1086beb --- /dev/null +++ b/overlays/xtensa_mtk_mt818x_adsp/gdb/xtensa-xtregs.c @@ -0,0 +1,95 @@ +/* Customized table mapping between kernel xtregset and GDB register cache. + + Copyright (c) 2007-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +typedef struct { + int gdb_regnum; + int gdb_offset; + int ptrace_cp_offset; + int ptrace_offset; + int size; + int coproc; + int dbnum; + char* name +;} xtensa_regtable_t; + +#define XTENSA_ELF_XTREG_SIZE 404 + +const xtensa_regtable_t xtensa_regmap_table[] = { + /* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */ + { 76, 304, 0, 0, 4, -1, 0x0204, "br" }, + { 78, 312, 16, 32, 4, 1, 0x03f0, "ae_ovf_sar" }, + { 79, 316, 20, 36, 4, 1, 0x03f1, "ae_bithead" }, + { 80, 320, 24, 40, 4, 1, 0x03f2, "ae_ts_fts_bu_bp" }, + { 81, 324, 28, 44, 4, 1, 0x03f3, "ae_cw_sd_no" }, + { 82, 328, 32, 48, 4, 1, 0x03f6, "ae_cbegin0" }, + { 83, 332, 36, 52, 4, 1, 0x03f7, "ae_cend0" }, + { 84, 336, 40, 56, 4, 1, 0x03f8, "ae_cbegin1" }, + { 85, 340, 44, 60, 4, 1, 0x03f9, "ae_cend1" }, + { 86, 344, 48, 64, 4, 1, 0x03fa, "ae_cbegin2" }, + { 87, 348, 52, 68, 4, 1, 0x03fb, "ae_cend2" }, + { 88, 352, 128, 144, 8, 1, 0x1000, "aed0" }, + { 89, 360, 136, 152, 8, 1, 0x1001, "aed1" }, + { 90, 368, 144, 160, 8, 1, 0x1002, "aed2" }, + { 91, 376, 152, 168, 8, 1, 0x1003, "aed3" }, + { 92, 384, 160, 176, 8, 1, 0x1004, "aed4" }, + { 93, 392, 168, 184, 8, 1, 0x1005, "aed5" }, + { 94, 400, 176, 192, 8, 1, 0x1006, "aed6" }, + { 95, 408, 184, 200, 8, 1, 0x1007, "aed7" }, + { 96, 416, 192, 208, 8, 1, 0x1008, "aed8" }, + { 97, 424, 200, 216, 8, 1, 0x1009, "aed9" }, + { 98, 432, 208, 224, 8, 1, 0x100a, "aed10" }, + { 99, 440, 216, 232, 8, 1, 0x100b, "aed11" }, + { 100, 448, 224, 240, 8, 1, 0x100c, "aed12" }, + { 101, 456, 232, 248, 8, 1, 0x100d, "aed13" }, + { 102, 464, 240, 256, 8, 1, 0x100e, "aed14" }, + { 103, 472, 248, 264, 8, 1, 0x100f, "aed15" }, + { 104, 480, 256, 272, 8, 1, 0x1010, "aed16" }, + { 105, 488, 264, 280, 8, 1, 0x1011, "aed17" }, + { 106, 496, 272, 288, 8, 1, 0x1012, "aed18" }, + { 107, 504, 280, 296, 8, 1, 0x1013, "aed19" }, + { 108, 512, 288, 304, 8, 1, 0x1014, "aed20" }, + { 109, 520, 296, 312, 8, 1, 0x1015, "aed21" }, + { 110, 528, 304, 320, 8, 1, 0x1016, "aed22" }, + { 111, 536, 312, 328, 8, 1, 0x1017, "aed23" }, + { 112, 544, 320, 336, 8, 1, 0x1018, "aed24" }, + { 113, 552, 328, 344, 8, 1, 0x1019, "aed25" }, + { 114, 560, 336, 352, 8, 1, 0x101a, "aed26" }, + { 115, 568, 344, 360, 8, 1, 0x101b, "aed27" }, + { 116, 576, 352, 368, 8, 1, 0x101c, "aed28" }, + { 117, 584, 360, 376, 8, 1, 0x101d, "aed29" }, + { 118, 592, 368, 384, 8, 1, 0x101e, "aed30" }, + { 119, 600, 376, 392, 8, 1, 0x101f, "aed31" }, + { 120, 608, 64, 80, 16, 1, 0x1020, "u0" }, + { 121, 624, 80, 96, 16, 1, 0x1021, "u1" }, + { 122, 640, 96, 112, 16, 1, 0x1022, "u2" }, + { 123, 656, 112, 128, 16, 1, 0x1023, "u3" }, + { 124, 672, 384, 400, 1, 1, 0x1024, "aep0" }, + { 125, 673, 385, 401, 1, 1, 0x1025, "aep1" }, + { 126, 674, 386, 402, 1, 1, 0x1026, "aep2" }, + { 127, 675, 387, 403, 1, 1, 0x1027, "aep3" }, + { 128, 676, 0, 16, 4, 1, 0x1029, "ae_zbiasv8c" }, + { 129, 680, 8, 24, 4, 1, 0x102a, "fcr_fsr" }, + { 0 } +}; + diff --git a/overlays/xtensa_mtk_mt818x_adsp/xtensa/config/core-isa.h b/overlays/xtensa_mtk_mt818x_adsp/xtensa/config/core-isa.h new file mode 100644 index 00000000..c2104754 --- /dev/null +++ b/overlays/xtensa_mtk_mt818x_adsp/xtensa/config/core-isa.h @@ -0,0 +1,843 @@ +/* + * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa + * processor CORE configuration + * + * See , which includes this file, for more details. + */ + +/* Xtensa processor core configuration information. + + Copyright (c) 1999-2024 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef XTENSA_CORE_CONFIGURATION_H_ +#define XTENSA_CORE_CONFIGURATION_H_ + + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 16 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_EXCLUSIVE 1 /* L32EX/S32EX instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ +#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ +#define XCHAL_HAVE_LX 1 /* LX core */ +#define XCHAL_HAVE_NX 0 /* NX core (starting RH) */ +#define XCHAL_HAVE_RNX 0 /* RNX core (starting RJ) */ + +#define XCHAL_HAVE_SUPERGATHER 0 /* SuperGather */ + +#define XCHAL_HAVE_FUSION 0 /* Fusion */ +#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ +#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ +#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ +#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ +#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ +#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ +#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ +#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ +#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ +#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI5S 0 /* HiFi5s Audio Engine pkg */ +#define XCHAL_HAVE_HIFI5S_NN_MAC 0 /* HiFi5s Audio Engine NN-MAC option */ +#define XCHAL_HAVE_HIFI5S_VFPU 0 /* HiFi5s Audio Engine Single-Precision VFPU option */ +#define XCHAL_HAVE_HIFI5S_HP_VFPU 0 /* HiFi5s Audio Engine Half-Precision VFPU option */ +#define XCHAL_HAVE_HIFI5S_DP_FPU 0 /* HiFi5s Audio Engine Double-Precision FPU option */ +#define XCHAL_HAVE_HIFI5 1 /* HiFi5 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI5_NN_MAC 1 /* HiFi5 Audio Engine NN-MAC option */ +#define XCHAL_HAVE_HIFI5_VFPU 1 /* HiFi5 Audio Engine Single-Precision VFPU option */ +#define XCHAL_HAVE_HIFI5_HP_VFPU 1 /* HiFi5 Audio Engine Half-Precision VFPU option */ +#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4_VFPU 1 /* HiFi4 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3 1 /* HiFi3 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3_VFPU 1 /* HiFi3 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI1S 0 /* HiFi1s */ +#define XCHAL_HAVE_HIFI1S_VFPU 0 /* HiFi1s SP-VFPU option */ +#define XCHAL_HAVE_HIFI1S_DP_FPU 0 /* HiFi1s DP-FPU option */ +#define XCHAL_HAVE_HIFI1S_LOW_LATENCY_MAC_FMA 0 /* HiFi1s Low-latency MAC/FMA option */ +#define XCHAL_HAVE_HIFI1 0 /* HiFi1 */ +#define XCHAL_HAVE_HIFI1_VFPU 0 /* HiFi1 VFPU option */ +#define XCHAL_HAVE_HIFI1_LOW_LATENCY_MAC_FMA 0 /* HiFi1 Low-latency MAC/FMA option */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ +#define XCHAL_HAVE_HIFI_MINI 0 + + + +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ +#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_USER_SPFPU 1 /* user SP floating-point pkg */ +#define XCHAL_HAVE_FP 1 /* single prec floating point */ +#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */ +#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */ +#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ +#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */ +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ +#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ +#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ +#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ +#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ + +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ + +#define XCHAL_HAVE_FUSIONG 0 /* FusionG */ +#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */ +#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */ +#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */ +#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */ +#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ + +#define XCHAL_HAVE_FUSIONJ 0 /* FusionJ */ +#define XCHAL_HAVE_FUSIONJ6 0 /* FusionJ6 */ +#define XCHAL_HAVE_FUSIONJ_SP_VFPU 0 /* sp_vfpu option on FusionJ */ +#define XCHAL_HAVE_FUSIONJ_DP_VFPU 0 /* dp_vfpu option on FusionJ */ +#define XCHAL_FUSIONJ_SIMD32 0 /* simd32 for FusionJ */ + +#define XCHAL_HAVE_PDX 0 /* PDX-LX */ +#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */ +#define XCHAL_HAVE_PDX4 0 /* PDX4-LX */ +#define XCHAL_HAVE_PDX8 0 /* PDX8-LX */ +#define XCHAL_HAVE_PDX16 0 /* PDX16-LX */ +#define XCHAL_HAVE_PDXNX 0 /* PDX-NX */ + +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ +#define XCHAL_HAVE_BALL 0 +#define XCHAL_HAVE_BALLAP 0 +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_CONNX_B10 0 /* ConnX B10 pkg*/ +#define XCHAL_HAVE_CONNX_B20 0 /* ConnX B20 pkg*/ +#define XCHAL_HAVE_CONNX_B_DP_VFPU 0 /* Double-precision Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_DPX_VFPU 0 /* Double-precision Vector Floating-point option on FP Machine*/ +#define XCHAL_HAVE_CONNX_B_SP_VFPU 0 /* Single-precision Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_SPX_VFPU 0 /* Single-precision Extended Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_HP_VFPU 0 /* Half-precision Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_HPX_VFPU 0 /* Half-precision Extended Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_32B_MAC 0 /* 32-bit vector MAC (real and complex), FIR & FFT option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_VITERBI 0 /* Viterbi option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_TURBO 0 /* Turbo option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_LDPC 0 /* LDPC option on ConnX B10 & B20 */ +#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */ +#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ + +#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */ +#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ +#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, Q6, Q7, Q8 or v331/v341 */ +#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */ +#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */ +#define XCHAL_HAVE_VISION_DP_VFPU 0 /* dp_vfpu option on Vision Q7/Q8 */ +#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6/Q6/Q7 */ +#define XCHAL_HAVE_VISION_SP_VFPU_2XFMAC 0 /* sp_vfpu_2xfma option on Vision Q7 */ +#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6/Q6 */ +#define XCHAL_HAVE_VISION_HP_VFPU_2XFMAC 0 /* hp_vfpu_2xfma option on Vision Q7 */ + +#define XCHAL_HAVE_VISIONC 0 /* Vision C */ + +#define XCHAL_HAVE_XNNE 0 /* XNNE */ + +/* Radar FFT */ +#define XCHAL_HAVE_RADAR_FFT 0 /* Radar FFT eTIE module */ + + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_LOADSTORE_UNITS 2 /* load/store units */ +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 32 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 16 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 16 /* data width in bytes */ +#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay + (1 = 5-stage, 2 = 7-stage) */ +#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ +#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ +#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ + +#define XCHAL_UNIFIED_LOADSTORE 0 + +#define XCHAL_SW_VERSION 1503000 /* sw version of this header */ +#define XCHAL_SW_VERSION_MAJOR 15000 /* major ver# of sw */ +#define XCHAL_SW_VERSION_MINOR 3 /* minor ver# of sw */ +#define XCHAL_SW_VERSION_MICRO 0 /* micro ver# of sw */ +#define XCHAL_SW_MINOR_VERSION 1503000 /* with zeroed micro */ +#define XCHAL_SW_MICRO_VERSION 1503000 + +#define XCHAL_CORE_ID "hifi5_7stg_I64D128" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_BUILD_UNIQUE_ID 0x000B6AC7 /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC003B286 /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x294904D8 /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX7.1.5" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2810 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 5 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION_MICRO 0 /* subdot ver# of targeted hw */ +#define XCHAL_HW_VERSION 281050 /* major*100+(major<2810 ? minor : minor*10+micro) */ +#define XCHAL_HW_REL_LX7 1 +#define XCHAL_HW_REL_LX7_1 1 +#define XCHAL_HW_REL_LX7_1_5 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2810 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 5 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MICRO 0 /* micro v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 281050 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2810 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 5 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MICRO 0 /* micro v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 281050 /* latest targeted hw */ + +/* Config is enabled for functional safety: */ +#define XCHAL_HAVE_FUNC_SAFETY 0 + +/* Config is enabled for secure operation: */ +#define XCHAL_HAVE_SECURE 0 + +#define XCHAL_HAVE_APB 0 + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 7 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 7 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 65536 /* I-cache size in bytes or 0 */ +#define XCHAL_ICACHE_SIZE_LOG2 16 +#define XCHAL_DCACHE_SIZE 131072 /* D-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE_LOG2 17 + +#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + + +#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ + +#define XCHAL_HAVE_PREFETCH_L1 1 /* prefetch to L1 cache */ +#define XCHAL_PREFETCH_CASTOUT_LINES 2 /* dcache pref. castout bufsz */ +#define XCHAL_PREFETCH_ENTRIES 16 /* cache prefetch entries */ + + +#define XCHAL_HAVE_DCACHE_PREFETCH 1 +#define XCHAL_HAVE_DCACHE_PREFETCH_L1 1 /* prefetch to L1 cache */ +#define XCHAL_DCACHE_PREFETCH_ENTRIES 16 /* cache prefetch entries */ + +#define XCHAL_HAVE_ICACHE_PREFETCH 0 +#define XCHAL_HAVE_ICACHE_PREFETCH_L1 0 /* prefetch to L1 cache */ +#define XCHAL_ICACHE_PREFETCH_ENTRIES 0 /* cache prefetch entries */ + +#define XCHAL_PREFETCH_BLOCK_ENTRIES 8 /* prefetch block streams */ +#define XCHAL_HAVE_CACHE_BLOCKOPS 1 /* block prefetch for caches */ +#define XCHAL_HAVE_CME_DOWNGRADES 0 +#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ +#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ +#define XCHAL_HAVE_ICACHE_DYN_WAYS 1 /* Icache dynamic way support */ +#define XCHAL_HAVE_DCACHE_DYN_WAYS 1 /* Dcache dynamic way support */ +#define XCHAL_HAVE_ICACHE_DYN_ENABLE 1 /* Icache enabled via MEMCTL */ +#define XCHAL_HAVE_DCACHE_DYN_ENABLE 1 /* Dcache enabled via MEMCTL */ + +#define XCHAL_L1SCACHE_SIZE 0 +#define XCHAL_L1SCACHE_SIZE_LOG2 0 +#define XCHAL_L1SCACHE_WAYS 1 +#define XCHAL_L1SCACHE_WAYS_LOG2 0 +#define XCHAL_L1SCACHE_ACCESS_SIZE 0 +#define XCHAL_L1SCACHE_BANKS 1 + +#define XCHAL_L1VCACHE_SIZE 0 + +#define XCHAL_HAVE_L2 0 /* L2 memory controller */ +#define XCHAL_HAVE_L2_CACHE 0 /* L2 cache configured */ +#define XCHAL_HAVE_L2_RAM 0 /* L2 cache configured */ +#define XCHAL_NUM_CORES_IN_CLUSTER 0 + +/* PRID_ID macros are for internal use only ... subject to removal */ +#define PRID_ID_SHIFT 0 +#define PRID_ID_BITS 4 +#define PRID_ID_MASK 0x0000000F + +/* This one is a form of caching, though not architecturally visible: */ +#define XCHAL_HAVE_BRANCH_PREDICTION 0 /* branch [target] prediction */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound bus present */ + +#define XCHAL_HAVE_AXI 1 /* AXI bus */ +#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */ +#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ + +#define XCHAL_HAVE_PIF_WR_RESP 1 /* pif write response */ +#define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 7 +#define XCHAL_DCACHE_SETWIDTH 8 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 4 +#define XCHAL_ICACHE_WAYS_LOG2 2 +#define XCHAL_DCACHE_WAYS 4 +#define XCHAL_DCACHE_WAYS_LOG2 2 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 1 +#define XCHAL_DCACHE_LINE_LOCKABLE 1 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 +#define XCHAL_ICACHE_ECC_WIDTH 4 +#define XCHAL_DCACHE_ECC_WIDTH 1 + +/* Cache access size in bytes (affects operation of SICW instruction): */ +#define XCHAL_ICACHE_ACCESS_SIZE 16 +#define XCHAL_DCACHE_ACCESS_SIZE 16 + +#define XCHAL_DCACHE_BANKS 2 /* number of banks */ + +/* The number of Cache lines associated with a single cache tag */ +#define XCHAL_DCACHE_LINES_PER_TAG_LOG2 0 + +/* Number of encoded cache attr bits (see for decoded bits): */ + +/* Extended memory attributes supported. */ +#define XCHAL_HAVE_EXT_CA 0 + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ +#define XCHAL_HAVE_IRAMCFG 0 /* IRAMxCFG register present */ +#define XCHAL_HAVE_DRAMCFG 0 /* DRAMxCFG register present */ + +/* Instruction RAM 0: */ +#define XCHAL_INSTRAM0_VADDR 0x3FFF0000 /* virtual address */ +#define XCHAL_INSTRAM0_PADDR 0x3FFF0000 /* physical address */ +#define XCHAL_INSTRAM0_SIZE 32768 /* size in bytes */ +#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_HAVE_INSTRAM0 1 +#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* Instruction RAM 1: */ +#define XCHAL_INSTRAM1_VADDR 0x3FFF8000 /* virtual address */ +#define XCHAL_INSTRAM1_PADDR 0x3FFF8000 /* physical address */ +#define XCHAL_INSTRAM1_SIZE 4096 /* size in bytes */ +#define XCHAL_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_HAVE_INSTRAM1 1 +#define XCHAL_INSTRAM1_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* Data RAM 0: */ +#define XCHAL_DATARAM0_VADDR 0x3FFE8000 /* virtual address */ +#define XCHAL_DATARAM0_PADDR 0x3FFE8000 /* physical address */ +#define XCHAL_DATARAM0_SIZE 32768 /* size in bytes */ +#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM0_BANKS 2 /* number of banks */ +#define XCHAL_HAVE_DATARAM0 1 +#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */ + +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ + + +/*---------------------------------------------------------------------- + IDMA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_IDMA 0 + + + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 5 /* number of interrupt levels + (not including level zero) */ +#define XCHAL_INTERRUPT_RANGE 32 /* range of interrupt numbers */ + + +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x040000FF +#define XCHAL_INTLEVEL2_MASK 0xA800FF00 +#define XCHAL_INTLEVEL3_MASK 0x518F0000 +#define XCHAL_INTLEVEL4_MASK 0x00700000 +#define XCHAL_INTLEVEL5_MASK 0x00000000 +#define XCHAL_INTLEVEL6_MASK 0x02000000 +#define XCHAL_INTLEVEL7_MASK 0x00000000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x040000FF +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0xAC00FFFF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0xFD8FFFFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0xFDFFFFFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFDFFFFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFFFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 1 +#define XCHAL_INT2_LEVEL 1 +#define XCHAL_INT3_LEVEL 1 +#define XCHAL_INT4_LEVEL 1 +#define XCHAL_INT5_LEVEL 1 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 1 +#define XCHAL_INT8_LEVEL 2 +#define XCHAL_INT9_LEVEL 2 +#define XCHAL_INT10_LEVEL 2 +#define XCHAL_INT11_LEVEL 2 +#define XCHAL_INT12_LEVEL 2 +#define XCHAL_INT13_LEVEL 2 +#define XCHAL_INT14_LEVEL 2 +#define XCHAL_INT15_LEVEL 2 +#define XCHAL_INT16_LEVEL 3 +#define XCHAL_INT17_LEVEL 3 +#define XCHAL_INT18_LEVEL 3 +#define XCHAL_INT19_LEVEL 3 +#define XCHAL_INT20_LEVEL 4 +#define XCHAL_INT21_LEVEL 4 +#define XCHAL_INT22_LEVEL 4 +#define XCHAL_INT23_LEVEL 3 +#define XCHAL_INT24_LEVEL 3 +#define XCHAL_INT25_LEVEL 6 +#define XCHAL_INT26_LEVEL 1 +#define XCHAL_INT27_LEVEL 2 +#define XCHAL_INT28_LEVEL 3 +#define XCHAL_INT29_LEVEL 2 +#define XCHAL_INT30_LEVEL 3 +#define XCHAL_INT31_LEVEL 2 +#define XCHAL_DEBUGLEVEL 5 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 6 /* NMI "level" (for use with + EXCSAVE/EPS/EPC_n, RFI n) */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT25_TYPE XTHAL_INTTYPE_NMI +#define XCHAL_INT26_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT27_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT28_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT29_TYPE XTHAL_INTTYPE_PROFILING +#define XCHAL_INT30_TYPE XTHAL_INTTYPE_WRITE_ERROR +#define XCHAL_INT31_TYPE XTHAL_INTTYPE_SOFTWARE + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x007FFFFF +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x01800000 +#define XCHAL_INTTYPE_MASK_NMI 0x02000000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x80000000 +#define XCHAL_INTTYPE_MASK_TIMER 0x1C000000 +#define XCHAL_INTTYPE_MASK_ETIE 0x00000000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x40000000 +#define XCHAL_INTTYPE_MASK_DBG_REQUEST 0x00000000 +#define XCHAL_INTTYPE_MASK_BREAKIN 0x00000000 +#define XCHAL_INTTYPE_MASK_TRAX 0x00000000 +#define XCHAL_INTTYPE_MASK_PROFILING 0x20000000 +#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000 +#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_L2_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_L2_STATUS 0x00000000 +#define XCHAL_INTTYPE_MASK_COR_ECC_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_WWDT 0x00000000 +#define XCHAL_INTTYPE_MASK_FXLK 0x00000000 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 26 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 27 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT 28 /* CCOMPARE2 */ +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 25 +#define XCHAL_WRITE_ERROR_INTERRUPT 30 +#define XCHAL_PROFILING_INTERRUPT 29 + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +#define XCHAL_INTLEVEL6_NUM 25 +/* (There are many interrupts each at level(s) 1, 2, 3, 4.) */ + + +/* + * External interrupt mapping. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ +#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ +#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ +#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ +#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 6 /* (intlevel 1) */ +#define XCHAL_EXTINT7_NUM 7 /* (intlevel 1) */ +#define XCHAL_EXTINT8_NUM 8 /* (intlevel 2) */ +#define XCHAL_EXTINT9_NUM 9 /* (intlevel 2) */ +#define XCHAL_EXTINT10_NUM 10 /* (intlevel 2) */ +#define XCHAL_EXTINT11_NUM 11 /* (intlevel 2) */ +#define XCHAL_EXTINT12_NUM 12 /* (intlevel 2) */ +#define XCHAL_EXTINT13_NUM 13 /* (intlevel 2) */ +#define XCHAL_EXTINT14_NUM 14 /* (intlevel 2) */ +#define XCHAL_EXTINT15_NUM 15 /* (intlevel 2) */ +#define XCHAL_EXTINT16_NUM 16 /* (intlevel 3) */ +#define XCHAL_EXTINT17_NUM 17 /* (intlevel 3) */ +#define XCHAL_EXTINT18_NUM 18 /* (intlevel 3) */ +#define XCHAL_EXTINT19_NUM 19 /* (intlevel 3) */ +#define XCHAL_EXTINT20_NUM 20 /* (intlevel 4) */ +#define XCHAL_EXTINT21_NUM 21 /* (intlevel 4) */ +#define XCHAL_EXTINT22_NUM 22 /* (intlevel 4) */ +#define XCHAL_EXTINT23_NUM 23 /* (intlevel 3) */ +#define XCHAL_EXTINT24_NUM 24 /* (intlevel 3) */ +#define XCHAL_EXTINT25_NUM 25 /* (intlevel 6) */ +/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ +#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ +#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ +#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ +#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ +#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ +#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ +#define XCHAL_INT6_EXTNUM 6 /* (intlevel 1) */ +#define XCHAL_INT7_EXTNUM 7 /* (intlevel 1) */ +#define XCHAL_INT8_EXTNUM 8 /* (intlevel 2) */ +#define XCHAL_INT9_EXTNUM 9 /* (intlevel 2) */ +#define XCHAL_INT10_EXTNUM 10 /* (intlevel 2) */ +#define XCHAL_INT11_EXTNUM 11 /* (intlevel 2) */ +#define XCHAL_INT12_EXTNUM 12 /* (intlevel 2) */ +#define XCHAL_INT13_EXTNUM 13 /* (intlevel 2) */ +#define XCHAL_INT14_EXTNUM 14 /* (intlevel 2) */ +#define XCHAL_INT15_EXTNUM 15 /* (intlevel 2) */ +#define XCHAL_INT16_EXTNUM 16 /* (intlevel 3) */ +#define XCHAL_INT17_EXTNUM 17 /* (intlevel 3) */ +#define XCHAL_INT18_EXTNUM 18 /* (intlevel 3) */ +#define XCHAL_INT19_EXTNUM 19 /* (intlevel 3) */ +#define XCHAL_INT20_EXTNUM 20 /* (intlevel 4) */ +#define XCHAL_INT21_EXTNUM 21 /* (intlevel 4) */ +#define XCHAL_INT22_EXTNUM 22 /* (intlevel 4) */ +#define XCHAL_INT23_EXTNUM 23 /* (intlevel 3) */ +#define XCHAL_INT24_EXTNUM 24 /* (intlevel 3) */ +#define XCHAL_INT25_EXTNUM 25 /* (intlevel 6) */ + +#define XCHAL_HAVE_ISB 0 /* No ISB */ +#define XCHAL_ISB_VADDR 0 /* N/A */ +#define XCHAL_HAVE_ITB 0 /* No ITB */ +#define XCHAL_ITB_VADDR 0 /* N/A */ + +#define XCHAL_HAVE_KSL 0 /* Kernel Stack Limit */ +#define XCHAL_HAVE_ISL 0 /* Interrupt Stack Limit */ +#define XCHAL_HAVE_PSL 0 /* Pageable Stack Limit */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (until T1050) + 2 == XEA2 (LX) + 3 == XEA3 (NX) + 0 == XEA5 (RNX) */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEA3 0 /* Exception Architecture 3 */ +#define XCHAL_HAVE_XEA5 0 /* Exception Architecture 5 */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_IMPRECISE_EXCEPTIONS 0 /* imprecise exception option */ +#define XCHAL_EXCCAUSE_NUM 64 /* Number of exceptions */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0x40000400 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x40000400 +#define XCHAL_RESET_VECBASE_OVERLAP 0 /* UNUSED */ + +#define XCHAL_RESET_VECTOR0_VADDR 0x40000000 +#define XCHAL_RESET_VECTOR0_PADDR 0x40000000 +#define XCHAL_RESET_VECTOR1_VADDR 0x40000800 +#define XCHAL_RESET_VECTOR1_PADDR 0x40000800 +#define XCHAL_RESET_VECTOR_VADDR XCHAL_RESET_VECTOR1_VADDR +#define XCHAL_RESET_VECTOR_PADDR XCHAL_RESET_VECTOR1_PADDR +#define XCHAL_USER_VECOFS 0x00000250 +#define XCHAL_USER_VECTOR_VADDR 0x40000650 +#define XCHAL_USER_VECTOR_PADDR 0x40000650 +#define XCHAL_KERNEL_VECOFS 0x00000230 +#define XCHAL_KERNEL_VECTOR_VADDR 0x40000630 +#define XCHAL_KERNEL_VECTOR_PADDR 0x40000630 +#define XCHAL_DOUBLEEXC_VECOFS 0x00000270 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x40000670 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x40000670 +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x40000400 +#define XCHAL_WINDOW_VECTORS_PADDR 0x40000400 +#define XCHAL_INTLEVEL2_VECOFS 0x00000180 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000580 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000580 +#define XCHAL_INTLEVEL3_VECOFS 0x000001A4 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400005A4 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400005A4 +#define XCHAL_INTLEVEL4_VECOFS 0x000001C8 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x400005C8 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x400005C8 +#define XCHAL_INTLEVEL5_VECOFS 0x000001EC +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x400005EC +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x400005EC +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL5_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL5_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL5_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x00000210 +#define XCHAL_NMI_VECTOR_VADDR 0x40000610 +#define XCHAL_NMI_VECTOR_PADDR 0x40000610 +#define XCHAL_INTLEVEL6_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL6_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL6_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG MODULE + ----------------------------------------------------------------------*/ + +/* Misc */ +#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ +#define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */ +#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ + +/* On-Chip Debug (OCD) */ +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ +#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ + +/* TRAX (in core) */ +#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ +#define XCHAL_TRAX_MEM_SIZE 4096 /* TRAX memory size in bytes */ +#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ +#define XCHAL_TRAX_ATB_WIDTH 32 /* ATB width (bits), 0=no ATB */ +#define XCHAL_TRAX_TIME_WIDTH 64 /* timestamp bitwidth, 0=none */ + +/* Perf counters */ +#define XCHAL_NUM_PERF_COUNTERS 8 /* performance counters */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 0 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */ +#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ + +/* If none of the above last 5 are set, it's a custom TLB configuration. */ + +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ + +/*---------------------------------------------------------------------- + MPU + ----------------------------------------------------------------------*/ +#define XCHAL_HAVE_MPU 1 +#define XCHAL_MPU_ENTRIES 32 +#define XCHAL_MPU_LOCK 0 + +#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ +#define XCHAL_MPU_BACKGROUND_ENTRIES 2 /* number of entries in bg map*/ +#define XCHAL_MPU_BG_CACHEADRDIS 0xFF /* default CACHEADRDIS for bg */ + +#define XCHAL_MPU_ALIGN_BITS 12 +#define XCHAL_MPU_ALIGN 4096 + +/*----------------------------------------------------------------------- + CSR Parity +------------------------------------------------------------------------*/ +#define XCHAL_HAVE_CSR_PARITY 0 + + +/*---------------------------------------------------------------------- + FLEX-LOCK +------------------------------------------------------------------------*/ + +#define XCHAL_HAVE_FXLK 0 + +/*---------------------------------------------------------------------- + WWDT (Windowed Watchdog Timer) +------------------------------------------------------------------------*/ +#define XCHAL_HAVE_WWDT 0 +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* XTENSA_CORE_CONFIGURATION_H_ */ + diff --git a/overlays/xtensa_mtk_mt8196_adsp/binutils/xtensa-config.h b/overlays/xtensa_mtk_mt8196_adsp/binutils/xtensa-config.h new file mode 100644 index 00000000..036261de --- /dev/null +++ b/overlays/xtensa_mtk_mt8196_adsp/binutils/xtensa-config.h @@ -0,0 +1,185 @@ +/* Xtensa configuration settings. + Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 + Free Software Foundation, Inc. + Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef XTENSA_CONFIG_H +#define XTENSA_CONFIG_H + +/* The macros defined here match those with the same names in the Xtensa + compile-time HAL (Hardware Abstraction Layer). Please refer to the + Xtensa System Software Reference Manual for documentation of these + macros. */ + +#undef XCHAL_HAVE_BE +#define XCHAL_HAVE_BE 0 + +#undef XCHAL_HAVE_DENSITY +#define XCHAL_HAVE_DENSITY 1 + +#undef XCHAL_HAVE_CONST16 +#define XCHAL_HAVE_CONST16 0 + +#undef XCHAL_HAVE_ABS +#define XCHAL_HAVE_ABS 1 + +#undef XCHAL_HAVE_ADDX +#define XCHAL_HAVE_ADDX 1 + +#undef XCHAL_HAVE_L32R +#define XCHAL_HAVE_L32R 1 + +#undef XSHAL_USE_ABSOLUTE_LITERALS +#define XSHAL_USE_ABSOLUTE_LITERALS 0 + +#undef XSHAL_HAVE_TEXT_SECTION_LITERALS +#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ + +#undef XCHAL_HAVE_MAC16 +#define XCHAL_HAVE_MAC16 0 + +#undef XCHAL_HAVE_MUL16 +#define XCHAL_HAVE_MUL16 1 + +#undef XCHAL_HAVE_MUL32 +#define XCHAL_HAVE_MUL32 1 + +#undef XCHAL_HAVE_MUL32_HIGH +#define XCHAL_HAVE_MUL32_HIGH 0 + +#undef XCHAL_HAVE_DIV32 +#define XCHAL_HAVE_DIV32 1 + +#undef XCHAL_HAVE_NSA +#define XCHAL_HAVE_NSA 1 + +#undef XCHAL_HAVE_MINMAX +#define XCHAL_HAVE_MINMAX 1 + +#undef XCHAL_HAVE_SEXT +#define XCHAL_HAVE_SEXT 1 + +#undef XCHAL_HAVE_LOOPS +#define XCHAL_HAVE_LOOPS 1 + +#undef XCHAL_HAVE_THREADPTR +#define XCHAL_HAVE_THREADPTR 1 + +#undef XCHAL_HAVE_RELEASE_SYNC +#define XCHAL_HAVE_RELEASE_SYNC 1 + +#undef XCHAL_HAVE_S32C1I +#define XCHAL_HAVE_S32C1I 0 + +#undef XCHAL_HAVE_BOOLEANS +#define XCHAL_HAVE_BOOLEANS 1 + +#undef XCHAL_HAVE_FP +#define XCHAL_HAVE_FP 0 + +#undef XCHAL_HAVE_FP_DIV +#define XCHAL_HAVE_FP_DIV 0 + +#undef XCHAL_HAVE_FP_RECIP +#define XCHAL_HAVE_FP_RECIP 0 + +#undef XCHAL_HAVE_FP_SQRT +#define XCHAL_HAVE_FP_SQRT 0 + +#undef XCHAL_HAVE_FP_RSQRT +#define XCHAL_HAVE_FP_RSQRT 0 + +#undef XCHAL_HAVE_DFP_ACCEL +#define XCHAL_HAVE_DFP_ACCEL 0 +/* For backward compatibility */ +#undef XCHAL_HAVE_DFP_accel +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL + +#undef XCHAL_HAVE_WINDOWED +#define XCHAL_HAVE_WINDOWED 1 + +#undef XCHAL_NUM_AREGS +#define XCHAL_NUM_AREGS 64 + +#undef XCHAL_HAVE_WIDE_BRANCHES +#define XCHAL_HAVE_WIDE_BRANCHES 0 + +#undef XCHAL_ICACHE_SIZE +#define XCHAL_ICACHE_SIZE 65536 + +#undef XCHAL_DCACHE_SIZE +#define XCHAL_DCACHE_SIZE 131072 + +#undef XCHAL_ICACHE_LINESIZE +#define XCHAL_ICACHE_LINESIZE 128 + +#undef XCHAL_DCACHE_LINESIZE +#define XCHAL_DCACHE_LINESIZE 128 + +#undef XCHAL_ICACHE_LINEWIDTH +#define XCHAL_ICACHE_LINEWIDTH 7 + +#undef XCHAL_DCACHE_LINEWIDTH +#define XCHAL_DCACHE_LINEWIDTH 7 + +#undef XCHAL_DCACHE_IS_WRITEBACK +#define XCHAL_DCACHE_IS_WRITEBACK 1 + + +#undef XCHAL_HAVE_MMU +#define XCHAL_HAVE_MMU 0 + + +#undef XCHAL_HAVE_DEBUG +#define XCHAL_HAVE_DEBUG 1 + +#undef XCHAL_NUM_IBREAK +#define XCHAL_NUM_IBREAK 2 + +#undef XCHAL_NUM_DBREAK +#define XCHAL_NUM_DBREAK 2 + +#undef XCHAL_DEBUGLEVEL +#define XCHAL_DEBUGLEVEL 5 + + +#undef XCHAL_MAX_INSTRUCTION_SIZE +#define XCHAL_MAX_INSTRUCTION_SIZE 16 + +#undef XCHAL_INST_FETCH_WIDTH +#define XCHAL_INST_FETCH_WIDTH 16 + + +#undef XSHAL_ABI +#undef XTHAL_ABI_WINDOWED +#undef XTHAL_ABI_CALL0 +#define XSHAL_ABI XTHAL_ABI_WINDOWED +#define XTHAL_ABI_WINDOWED 0 +#define XTHAL_ABI_CALL0 1 + + +#undef XCHAL_M_STAGE +#define XCHAL_M_STAGE 3 + +#undef XTENSA_MARCH_LATEST +#define XTENSA_MARCH_LATEST 281080 + +#undef XTENSA_MARCH_EARLIEST +#define XTENSA_MARCH_EARLIEST 281080 + + +#endif /* !XTENSA_CONFIG_H */ diff --git a/overlays/xtensa_mtk_mt8196_adsp/binutils/xtensa-modules.c b/overlays/xtensa_mtk_mt8196_adsp/binutils/xtensa-modules.c new file mode 100644 index 00000000..24233d0a --- /dev/null +++ b/overlays/xtensa_mtk_mt8196_adsp/binutils/xtensa-modules.c @@ -0,0 +1,244783 @@ +/* Xtensa configuration-specific ISA information. + + Copyright (c) 2003-2024 Cadence Design Systems, Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "ansidecl.h" +#include +#include "xtensa-isa-internal.h" + + +/* Sysregs. */ + +static xtensa_sysreg_internal sysregs[] = { + { "LBEG", 0, 0 }, + { "LEND", 1, 0 }, + { "LCOUNT", 2, 0 }, + { "BR", 4, 0 }, + { "MMID", 89, 0 }, + { "DDR", 104, 0 }, + { "CONFIGID0", 176, 0 }, + { "CONFIGID1", 208, 0 }, + { "INTERRUPT", 226, 0 }, + { "INTCLEAR", 227, 0 }, + { "CCOUNT", 234, 0 }, + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, + { "CCOMPARE1", 241, 0 }, + { "CCOMPARE2", 242, 0 }, + { "VECBASE", 231, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EPC3", 179, 0 }, + { "EPC4", 180, 0 }, + { "EPC5", 181, 0 }, + { "EPC6", 182, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EXCSAVE3", 211, 0 }, + { "EXCSAVE4", 212, 0 }, + { "EXCSAVE5", 213, 0 }, + { "EXCSAVE6", 214, 0 }, + { "EPS2", 194, 0 }, + { "EPS3", 195, 0 }, + { "EPS4", 196, 0 }, + { "EPS5", 197, 0 }, + { "EPS6", 198, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, + { "WINDOWBASE", 72, 0 }, + { "WINDOWSTART", 73, 0 }, + { "MEMCTL", 97, 0 }, + { "SAR", 3, 0 }, + { "PS", 230, 0 }, + { "MISC0", 244, 0 }, + { "MISC1", 245, 0 }, + { "MISC2", 246, 0 }, + { "MISC3", 247, 0 }, + { "MPUCFG", 92, 0 }, + { "OPMODE", 119, 0 }, + { "INTENABLE", 228, 0 }, + { "DBREAKA0", 144, 0 }, + { "DBREAKC0", 160, 0 }, + { "DBREAKA1", 145, 0 }, + { "DBREAKC1", 161, 0 }, + { "IBREAKA0", 128, 0 }, + { "IBREAKA1", 129, 0 }, + { "IBREAKENABLE", 96, 0 }, + { "ICOUNTLEVEL", 237, 0 }, + { "DEBUGCAUSE", 233, 0 }, + { "PREFCTL", 40, 0 }, + { "CACHEADRDIS", 98, 0 }, + { "MPUENB", 90, 0 }, + { "CPENABLE", 224, 0 }, + { "ATOMCTL", 99, 0 }, + { "ERACCESS", 95, 0 }, + { "THREADPTR", 231, 1 }, + { "AE_OVF_SAR", 240, 1 }, + { "AE_BITHEAD", 241, 1 }, + { "AE_TS_FTS_BU_BP", 242, 1 }, + { "AE_CW_SD_NO", 243, 1 }, + { "AE_CBEGIN0", 246, 1 }, + { "AE_CEND0", 247, 1 }, + { "AE_CBEGIN1", 248, 1 }, + { "AE_CEND1", 249, 1 }, + { "AE_CBEGIN2", 250, 1 }, + { "AE_CEND2", 251, 1 }, + { "AE_ZBIASV8C", -1, 1 }, + { "FCR_FSR", -1, 1 }, + { "EXPSTATE", 230, 1 } +}; + +#define NUM_SYSREGS 78 +#define MAX_SPECIAL_REG 247 +#define MAX_USER_REG 251 + + +/* Processor states. */ + +static xtensa_state_internal states[] = { + { "LCOUNT", 32, 0 }, + { "PC", 32, 0 }, + { "DDR", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "INTERRUPT", 32, 0 }, + { "CCOUNT", 32, 0 }, + { "XTSYNC", 1, 0 }, + { "VECBASE", 22, 0 }, + { "VECBASELOCK", 1, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EPC3", 32, 0 }, + { "EPC4", 32, 0 }, + { "EPC5", 32, 0 }, + { "EPC6", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EXCSAVE3", 32, 0 }, + { "EXCSAVE4", 32, 0 }, + { "EXCSAVE5", 32, 0 }, + { "EXCSAVE6", 32, 0 }, + { "EPS2", 15, 0 }, + { "EPS3", 15, 0 }, + { "EPS4", 15, 0 }, + { "EPS5", 15, 0 }, + { "EPS6", 15, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, + { "PSWOE", 1, 0 }, + { "PSRING", 2, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, + { "WindowBase", 4, 0 }, + { "WindowStart", 16, 0 }, + { "PSCALLINC", 2, 0 }, + { "PSOWB", 4, 0 }, + { "LBEG", 32, 0 }, + { "LEND", 32, 0 }, + { "MEMCTL", 24, 0 }, + { "SAR", 6, 0 }, + { "THREADPTR", 32, 0 }, + { "MISC0", 32, 0 }, + { "MISC1", 32, 0 }, + { "MISC2", 32, 0 }, + { "MISC3", 32, 0 }, + { "MPUNUMENTRIES", 6, 0 }, + { "OPMODEECCFENCE", 2, 0 }, + { "InOCDMode", 1, 0 }, + { "INTENABLE", 32, 0 }, + { "DBREAKA0", 32, 0 }, + { "DBREAKC0", 8, 0 }, + { "DBREAKA1", 32, 0 }, + { "DBREAKC1", 8, 0 }, + { "IBREAKA0", 32, 0 }, + { "IBREAKA1", 32, 0 }, + { "IBREAKENABLE", 2, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, + { "CCOMPARE0", 32, 0 }, + { "CCOMPARE1", 32, 0 }, + { "CCOMPARE2", 32, 0 }, + { "PREFCTL", 9, 0 }, + { "CACHEADRDIS", 8, 0 }, + { "MPUENB", 32, 0 }, + { "MPULOCK", 32, 0 }, + { "CPENABLE", 2, 0 }, + { "ATOMCTL", 9, 0 }, + { "ERI_RAW_INTERLOCK", 1, 0 }, + { "ERACCESS", 16, 0 }, + { "AE_OVERFLOW", 1, XTENSA_STATE_IS_SHARED_OR }, + { "AE_CBEGIN0", 32, 0 }, + { "AE_CEND0", 32, 0 }, + { "AE_CBEGIN1", 32, 0 }, + { "AE_CEND1", 32, 0 }, + { "AE_CBEGIN2", 32, 0 }, + { "AE_CEND2", 32, 0 }, + { "AE_SAR", 14, 0 }, + { "AE_CWRAP", 1, 0 }, + { "AE_BITHEAD", 32, 0 }, + { "AE_BITPTR", 4, 0 }, + { "AE_BITSUSED", 4, 0 }, + { "AE_TABLESIZE", 4, 0 }, + { "AE_FIRST_TS", 4, 0 }, + { "AE_NEXTOFFSET", 27, 0 }, + { "AE_SEARCHDONE", 1, 0 }, + { "AE_ZBIASV8", 8, 0 }, + { "AE_ZBIASC8", 8, 0 }, + { "RoundMode", 2, 0 }, + { "InvalidFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "DivZeroFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "OverflowFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "UnderflowFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "InexactFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } +}; + +#define NUM_STATES 97 + +enum xtensa_state_id { + STATE_LCOUNT, + STATE_PC, + STATE_DDR, + STATE_ICOUNT, + STATE_INTERRUPT, + STATE_CCOUNT, + STATE_XTSYNC, + STATE_VECBASE, + STATE_VECBASELOCK, + STATE_EPC1, + STATE_EPC2, + STATE_EPC3, + STATE_EPC4, + STATE_EPC5, + STATE_EPC6, + STATE_EXCSAVE1, + STATE_EXCSAVE2, + STATE_EXCSAVE3, + STATE_EXCSAVE4, + STATE_EXCSAVE5, + STATE_EXCSAVE6, + STATE_EPS2, + STATE_EPS3, + STATE_EPS4, + STATE_EPS5, + STATE_EPS6, + STATE_EXCCAUSE, + STATE_PSINTLEVEL, + STATE_PSUM, + STATE_PSWOE, + STATE_PSRING, + STATE_PSEXCM, + STATE_DEPC, + STATE_EXCVADDR, + STATE_WindowBase, + STATE_WindowStart, + STATE_PSCALLINC, + STATE_PSOWB, + STATE_LBEG, + STATE_LEND, + STATE_MEMCTL, + STATE_SAR, + STATE_THREADPTR, + STATE_MISC0, + STATE_MISC1, + STATE_MISC2, + STATE_MISC3, + STATE_MPUNUMENTRIES, + STATE_OPMODEECCFENCE, + STATE_InOCDMode, + STATE_INTENABLE, + STATE_DBREAKA0, + STATE_DBREAKC0, + STATE_DBREAKA1, + STATE_DBREAKC1, + STATE_IBREAKA0, + STATE_IBREAKA1, + STATE_IBREAKENABLE, + STATE_ICOUNTLEVEL, + STATE_DEBUGCAUSE, + STATE_DBNUM, + STATE_CCOMPARE0, + STATE_CCOMPARE1, + STATE_CCOMPARE2, + STATE_PREFCTL, + STATE_CACHEADRDIS, + STATE_MPUENB, + STATE_MPULOCK, + STATE_CPENABLE, + STATE_ATOMCTL, + STATE_ERI_RAW_INTERLOCK, + STATE_ERACCESS, + STATE_AE_OVERFLOW, + STATE_AE_CBEGIN0, + STATE_AE_CEND0, + STATE_AE_CBEGIN1, + STATE_AE_CEND1, + STATE_AE_CBEGIN2, + STATE_AE_CEND2, + STATE_AE_SAR, + STATE_AE_CWRAP, + STATE_AE_BITHEAD, + STATE_AE_BITPTR, + STATE_AE_BITSUSED, + STATE_AE_TABLESIZE, + STATE_AE_FIRST_TS, + STATE_AE_NEXTOFFSET, + STATE_AE_SEARCHDONE, + STATE_AE_ZBIASV8, + STATE_AE_ZBIASC8, + STATE_RoundMode, + STATE_InvalidFlag, + STATE_DivZeroFlag, + STATE_OverflowFlag, + STATE_UnderflowFlag, + STATE_InexactFlag, + STATE_EXPSTATE +}; + + +/* Field definitions. */ + +static unsigned +Field_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_n_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_m_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_inst_15_12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_inst_15_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_inst_11_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_inst_11_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_inst16b_15_13_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_ae_fld_inst16b_15_13_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_ae_fld_inst16b_12_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_ae_fld_inst16b_12_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 3) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_19_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 3) >> 18); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x1fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_3_2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_17_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 3) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_22_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 11) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 3) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_21_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe00000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_19_19_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_18_16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_3_3_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 3) >> 15); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_3_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_28_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 3) >> 7); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_28_14_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 3) >> 17); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_14_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 3) >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 3) >> 13); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x1ffffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot0_8_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_8_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_28_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 3) >> 11); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x1fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_3_1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_1_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_9_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_1_1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_1_1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_slot0_12_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_12_10_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot0_17_10_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 14) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot0_12_6_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_6_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 3) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_27_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000000) | (tie_t << 27); +} + +static unsigned +Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 8) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot0_23_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_18_13_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 3) >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_17_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_9_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_11_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae_slot0_5_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_5_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_4_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_4_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_18_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_19_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot0_19_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_18_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 13) >> 21); + return tie_t; +} + +static void +Field_fld_ae_slot0_18_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_5_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_4_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_19_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_19_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_19_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_23_19_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_14_13_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_17_13_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_13_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_23_22_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_28_24_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 3) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_24_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_14_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_slot0_28_26_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 3) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_26_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c000000) | (tie_t << 26); +} + +static unsigned +Field_fld_ae_slot0_23_17_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot0_23_17_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot0_9_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_9_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_9_9_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_slot0_7_3_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_3_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae_slot0_12_9_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 19) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_9_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_slot0_14_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_14_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 6) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_16_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 6) >> 18); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 6) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_17_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot1_7_4_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot1_25_1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 6) >> 7); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_slot1_0_0_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot1_0_0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot1_3_0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot1_25_9_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 6) >> 15); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_9_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 6) >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x3ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot1_3_3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae_slot1_3_2_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot1_3_2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 6) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_18_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 6) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot1_17_8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot1_17_13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot1_12_8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot1_12_8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot1_17_17_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot1_17_17_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot1_25_22_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 6) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_22_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae_slot1_25_23_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 6) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_23_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae_slot2_28_4_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 3) >> 7); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_4_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot2_3_0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot2_3_0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 3) >> 18); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_15_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x1fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_5_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 3) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_20_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_7_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_fld_ae_slot2_9_1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 22) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot2_9_2_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_2_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot2_28_19_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 3) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_19_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot2_14_0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 17) >> 17); + return tie_t; +} + +static void +Field_fld_ae_slot2_14_0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot2_28_17_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 3) >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_17_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot2_14_5_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot2_14_5_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_slot2_16_15_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot2_16_15_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 3) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_25_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_slot2_14_10_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot2_14_10_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot2_19_15_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot2_28_5_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 3) >> 8); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_5_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0x1fffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_slot2_9_6_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_6_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae_slot2_9_8_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_8_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot2_14_14_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot2_14_14_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_slot3_36_12_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 20) | (insn[0] >> 12); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_12_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 20); +} + +static unsigned +Field_fld_ae_slot3_11_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot3_11_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_30_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 12) >> 12); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot3_9_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 17) >> 17); + return tie_t; +} + +static void +Field_fld_ae_slot3_14_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_25_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae_slot3_19_19_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_19_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_14_10_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_4_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_ae_slot3_24_10_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot3_36_16_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 16) | (insn[0] >> 16); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_16_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 16); +} + +static unsigned +Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_10_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_24_20_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_20_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_9_5_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot3_16_13_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot3_24_19_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 7) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot3_24_19_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x1f80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 10) | (insn[0] >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_22_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xffc00000) | (tie_t << 22); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 10); +} + +static unsigned +Field_fld_ae_slot3_19_17_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_17_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot3_14_13_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot3_14_13_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_15_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot3_14_12_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot3_14_12_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot3_9_1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 22) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot3_9_1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_slot3_9_3_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 22) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot3_9_3_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae_slot3_36_19_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 13) | (insn[0] >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_19_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xfff80000) | (tie_t << 19); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 13); +} + +static unsigned +Field_fld_ae_slot3_19_18_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_18_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 16) | (insn[0] >> 16); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 16); +} + +static unsigned +Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 13) | (insn[0] >> 19); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xfff80000) | (tie_t << 19); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 13); +} + +static unsigned +Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 15) | (insn[0] >> 17); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xfffe0000) | (tie_t << 17); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 15); +} + +static unsigned +Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 11) | (insn[0] >> 21); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffe00000) | (tie_t << 21); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 11); +} + +static unsigned +Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_15_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 5) | (insn[0] >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 5); +} + +static unsigned +Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 14); +} + +static unsigned +Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae2_slot0_12_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_ae2_slot0_12_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_12_2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_ae2_slot0_12_2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae2_slot0_14_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_fld_ae2_slot0_14_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 8) | (insn[0] >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xff000000) | (tie_t << 24); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 8); +} + +static unsigned +Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_15_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae2_slot0_40_26_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 6) | (insn[0] >> 26); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_26_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 6); +} + +static unsigned +Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + return tie_t; +} + +static void +Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae2_slot0_18_17_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_18_17_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 9) | (insn[0] >> 23); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xff800000) | (tie_t << 23); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 9); +} + +static unsigned +Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 20) | (insn[0] >> 12); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 20); +} + +static unsigned +Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot1_11_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot1_11_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 16) | (insn[0] >> 16); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 16); +} + +static unsigned +Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot1_36_17_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 15) | (insn[0] >> 17); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_17_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffe0000) | (tie_t << 17); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 15); +} + +static unsigned +Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot1_3_3_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot1_3_3_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 18); +} + +static unsigned +Field_fld_ae2_slot1_3_2_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot1_3_2_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot1_36_18_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_18_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 14); +} + +static unsigned +Field_fld_ae2_slot1_36_22_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 10) | (insn[0] >> 22); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_22_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xffc00000) | (tie_t << 22); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 10); +} + +static unsigned +Field_fld_ae2_slot1_36_23_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 9) | (insn[0] >> 23); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_23_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xff800000) | (tie_t << 23); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 9); +} + +static unsigned +Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 14); +} + +static unsigned +Field_fld_ae2_slot2_17_0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_fld_ae2_slot2_17_0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 7) >> 12); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0x1ffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 7) >> 22); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 14) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + return tie_t; +} + +static void +Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot2_42_26_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 6) | (insn[0] >> 26); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_26_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 6); +} + +static unsigned +Field_fld_ae2_slot2_42_28_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 4) | (insn[0] >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_28_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xf0000000) | (tie_t << 28); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 4); +} + +static unsigned +Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 7) >> 16); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x1fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 12) >> 21); + return tie_t; +} + +static void +Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 15) | (insn[0] >> 17); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xfffe0000) | (tie_t << 17); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 15); +} + +static unsigned +Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 20) | (insn[0] >> 12); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 20); +} + +static unsigned +Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 14); +} + +static unsigned +Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 24) | (insn[0] >> 8); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff00) | (tie_t << 8); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 24); +} + +static unsigned +Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae3_slot0_32_16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 16) | (insn[0] >> 16); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 16); +} + +static unsigned +Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 21) | (insn[0] >> 11); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xfffff800) | (tie_t << 11); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 21); +} + +static unsigned +Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 19) | (insn[0] >> 13); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffffe000) | (tie_t << 13); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 19); +} + +static unsigned +Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 5) | (insn[0] >> 27); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 5); +} + +static unsigned +Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae3_slot0_7_2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_ae3_slot0_7_2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 18); +} + +static unsigned +Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_9_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ae3_slot0_9_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae3_slot1_23_17_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_17_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot1_23_0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot1_23_11_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 8) >> 19); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_11_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 8) >> 21); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 8) >> 23); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae3_slot1_23_19_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_19_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae3_slot1_3_1_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae3_slot1_3_1_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae3_slot1_23_9_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_9_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 2) >> 18); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 2) >> 14); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 2) >> 20); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 2) >> 7); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae5_slot0_29_17_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 2) >> 19); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_17_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x3ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 2) >> 10); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x3fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 2) >> 15); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 2) >> 29); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000000) | (tie_t << 27); +} + +static unsigned +Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2) | (tie_t << 1); +} + +static unsigned +Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 2) >> 17); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x3fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae5_slot0_29_6_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 2) >> 8); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_6_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0x3fffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 19) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae5_slot0_29_19_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 2) >> 21); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_19_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x3ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae5_slot0_7_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae5_slot0_7_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae5_slot0_12_6_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_fld_ae5_slot0_12_6_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae5_slot1_1_0_Slot_ae5_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot1_1_0_Slot_ae5_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot2_24_0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 7) >> 7); + return tie_t; +} + +static void +Field_fld_ae5_slot2_24_0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae5_slot2_14_5_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_ae5_slot2_14_5_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae5_slot2_9_7_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_fld_ae5_slot2_9_7_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 7) >> 24); + return tie_t; +} + +static void +Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 7) >> 22); + return tie_t; +} + +static void +Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot0_29_5_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 2) >> 7); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_5_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 2) >> 17); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x3fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 2) >> 20); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae6_slot0_7_4_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae6_slot0_7_4_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 2) >> 12); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0x3ffffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 2) >> 15); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 2) >> 16); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x3fffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 4) >> 16); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae6_slot1_27_3_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 4) >> 7); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_3_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae6_slot1_2_0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae6_slot1_2_0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 4) >> 19); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 4) >> 24); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 4) >> 10); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xfffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae6_slot1_9_5_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot1_9_5_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae6_slot1_27_21_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 4) >> 25); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_21_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe00000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae6_slot2_24_0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 7) >> 7); + return tie_t; +} + +static void +Field_fld_ae6_slot2_24_0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 7) >> 22); + return tie_t; +} + +static void +Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 7) >> 21); + return tie_t; +} + +static void +Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot2_24_10_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_ae6_slot2_24_10_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_fld_ae6_slot2_24_20_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot2_24_20_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae6_slot3_37_13_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | (insn[1] & 0x3f); + tie_t = (tie_t << 19) | (insn[0] >> 13); + return tie_t; +} + +static void +Field_fld_ae6_slot3_37_13_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffe000) | (tie_t << 13); + insn[1] = (insn[1] & ~0x3f) | (tie_t >> 19); +} + +static unsigned +Field_fld_ae6_slot3_12_0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_ae6_slot3_12_0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | (insn[1] & 0x3f); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x3f) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | (insn[1] & 0x3f); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x3f) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae6_slot3_24_20_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot3_24_20_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae6_slot3_14_0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 17) >> 17); + return tie_t; +} + +static void +Field_fld_ae6_slot3_14_0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | (insn[1] & 0x3f); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x3f) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_ae7_slot0_23_0_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_ae7_slot0_23_0_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 8) >> 21); + return tie_t; +} + +static void +Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + return tie_t; +} + +static void +Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot0_12_6_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot0_12_6_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot1_23_0_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_ae7_slot1_23_0_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 8) >> 21); + return tie_t; +} + +static void +Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + return tie_t; +} + +static void +Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot1_12_6_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot1_12_6_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot2_36_12_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 20) | (insn[0] >> 12); + return tie_t; +} + +static void +Field_fld_ae7_slot2_36_12_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 20); +} + +static unsigned +Field_fld_ae7_slot2_11_0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); + return tie_t; +} + +static void +Field_fld_ae7_slot2_11_0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae7_slot2_14_10_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae7_slot2_14_10_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae7_slot3_35_11_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | (insn[1] & 0xf); + tie_t = (tie_t << 21) | (insn[0] >> 11); + return tie_t; +} + +static void +Field_fld_ae7_slot3_35_11_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffff800) | (tie_t << 11); + insn[1] = (insn[1] & ~0xf) | (tie_t >> 21); +} + +static unsigned +Field_fld_ae7_slot3_10_0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 21) >> 21); + return tie_t; +} + +static void +Field_fld_ae7_slot3_10_0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | (insn[1] & 0xf); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0xf) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae7_slot3_24_10_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_ae7_slot3_24_10_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae7_slot3_4_0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae7_slot3_4_0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | (insn[1] & 0xf); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0xf) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | (insn[1] & 0xf); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0xf) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 0) >> 18); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 0) >> 12); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 0) >> 8); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot0_13_13_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_fld_ae8_slot0_13_13_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 0) >> 20); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae8_slot0_31_7_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 0) >> 7); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_7_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae8_slot0_6_0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ae8_slot0_6_0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot0_31_9_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 0) >> 9); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_9_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xfffffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 0) >> 15); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae8_slot0_7_5_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ae8_slot0_7_5_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 18) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 14) >> 18); + return tie_t; +} + +static void +Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 0) >> 19); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae8_slot0_8_0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_ae8_slot0_8_0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot0_17_8_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot0_17_8_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae8_slot0_31_21_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 0) >> 21); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_21_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe00000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae8_slot0_31_22_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 0) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_22_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae8_slot0_31_23_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 0) >> 23); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_23_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + return tie_t; +} + +static void +Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 2) >> 14); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae8_slot1_17_15_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae8_slot1_17_15_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae8_slot1_29_5_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 2) >> 7); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_5_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae8_slot1_4_0_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae8_slot1_4_0_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 2) >> 10); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x3fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot1_29_9_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 2) >> 11); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_9_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x3ffffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 2) >> 15); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 2) >> 20); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae8_slot1_29_22_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 2) >> 24); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_22_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae8_slot1_29_23_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 2) >> 25); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_23_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[1] << 5) >> 7); + return tie_t; +} + +static void +Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[1] = (insn[1] & ~0x7fffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae8_slot2_33_9_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 23) | (insn[0] >> 9); + return tie_t; +} + +static void +Field_fld_ae8_slot2_33_9_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffffe00) | (tie_t << 9); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 23); +} + +static unsigned +Field_fld_ae8_slot2_8_0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_ae8_slot2_8_0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot2_33_25_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae8_slot2_33_25_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae8_slot2_19_15_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae8_slot2_19_15_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[1] << 5) >> 23); + return tie_t; +} + +static void +Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[1] = (insn[1] & ~0x7fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[1] << 5) >> 13); + return tie_t; +} + +static void +Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[1] = (insn[1] & ~0x7ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[1] << 5) >> 8); + return tie_t; +} + +static void +Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[1] = (insn[1] & ~0x7fffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[1] << 19) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[1] = (insn[1] & ~0x1ff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 4) >> 20); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 4) >> 16); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 4) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 4) >> 12); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot0_27_17_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 4) >> 21); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_17_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 4) >> 24); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae9_slot0_27_3_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 4) >> 7); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_3_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae9_slot0_2_0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae9_slot0_2_0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 4) >> 14); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 4) >> 17); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae9_slot0_7_6_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae9_slot0_7_6_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 14) >> 18); + return tie_t; +} + +static void +Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae9_slot0_27_19_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 4) >> 23); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_19_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 19) >> 24); + return tie_t; +} + +static void +Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 23) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae9_slot0_27_22_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 4) >> 26); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_22_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 4) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 5) >> 21); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae9_slot1_26_17_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 5) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_17_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae9_slot1_26_2_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 5) >> 7); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_2_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae9_slot1_1_0_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae9_slot1_1_0_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 5) >> 13); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x7ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot1_26_9_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 5) >> 14); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_9_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x7fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 5) >> 18); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x7ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae9_slot1_3_2_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae9_slot1_3_2_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 5) >> 23); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae9_slot1_26_22_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 5) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_22_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae9_slot1_26_23_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_23_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae9_slot2_33_9_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 23) | (insn[0] >> 9); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_9_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffffe00) | (tie_t << 9); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 23); +} + +static unsigned +Field_fld_ae9_slot2_8_0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_ae9_slot2_8_0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 6) | (insn[0] >> 26); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 6); +} + +static unsigned +Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 4) | (insn[0] >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xf0000000) | (tie_t << 28); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 4); +} + +static unsigned +Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 18); +} + +static unsigned +Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 7) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 7) >> 21); + return tie_t; +} + +static void +Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae9_slot3_31_7_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 0) >> 7); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_7_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae9_slot3_6_0_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ae9_slot3_6_0_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 0) >> 25); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae9_slot3_4_4_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot3_4_4_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 0) >> 15); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 0) >> 20); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 0) >> 26); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); +} + +static unsigned +Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 0) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000000) | (tie_t << 28); +} + +static unsigned +Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 0) >> 14); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); +} + +static unsigned +Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 7) >> 23); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 7) >> 19); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 7) >> 25); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 7) >> 15); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot0_24_17_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 7) >> 24); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_17_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae10_slot0_24_0_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 7) >> 7); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_0_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 7) >> 20); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae10_slot0_7_6_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot0_7_6_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 14) >> 18); + return tie_t; +} + +static void +Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae10_slot0_17_8_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot0_17_8_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 6) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 6) >> 18); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae10_slot1_25_17_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 6) >> 23); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_17_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae10_slot1_25_1_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 6) >> 7); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_1_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae10_slot1_0_0_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot1_0_0_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot1_25_9_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 6) >> 15); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_9_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 6) >> 19); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x3ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae10_slot1_3_2_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot1_3_2_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 6) >> 24); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 6) >> 26); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae10_slot1_25_22_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 6) >> 28); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_22_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae10_slot1_25_23_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 6) >> 29); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_23_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae10_slot2_34_10_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 22) | (insn[0] >> 10); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_10_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffffc00) | (tie_t << 10); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 22); +} + +static unsigned +Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 1) | (insn[0] >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x80000000) | (tie_t << 31); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 1); +} + +static unsigned +Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[1] << 29) >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[1] = (insn[1] & ~0x6) | (tie_t << 1); +} + +static unsigned +Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 18); +} + +static unsigned +Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae10_slot3_34_10_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 22) | (insn[0] >> 10); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_10_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffffc00) | (tie_t << 10); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 22); +} + +static unsigned +Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae10_slot3_4_4_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot3_4_4_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 1) | (insn[0] >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x80000000) | (tie_t << 31); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 1); +} + +static unsigned +Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[1] << 29) >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[1] = (insn[1] & ~0x6) | (tie_t << 1); +} + +static unsigned +Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 18); +} + +static unsigned +Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); +} + +static unsigned +Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 9) >> 21); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 9) >> 17); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot0_22_17_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 9) >> 26); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_17_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae4_slot0_22_20_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_20_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae4_slot0_22_0_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 9) >> 9); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_0_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot0_3_1_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot0_3_1_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 9) >> 22); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 9) >> 15); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x7fffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 9) >> 21); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae4_slot1_22_17_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 9) >> 26); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_17_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae4_slot1_22_0_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 9) >> 9); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_0_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 9) >> 17); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot1_3_1_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot1_3_1_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 9) >> 22); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae4_slot2_23_0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_ae4_slot2_23_0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 8) >> 23); + return tie_t; +} + +static void +Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae4_slot2_23_17_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_ae4_slot2_23_17_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae4_slot2_4_0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot2_4_0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae4_slot3_27_3_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 4) >> 7); + return tie_t; +} + +static void +Field_fld_ae4_slot3_27_3_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae4_slot3_2_0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot3_2_0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae4_slot3_19_19_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_fld_ae4_slot3_19_19_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae4_slot3_19_5_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 12) >> 17); + return tie_t; +} + +static void +Field_fld_ae4_slot3_19_5_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae4_slot3_27_20_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 4) >> 24); + return tie_t; +} + +static void +Field_fld_ae4_slot3_27_20_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae4_slot3_14_10_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot3_14_10_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae4_slot4_22_0_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 9) >> 9); + return tie_t; +} + +static void +Field_fld_ae4_slot4_22_0_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 9) >> 24); + return tie_t; +} + +static void +Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_t_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_t_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 23) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e0) | (tie_t << 5); +} + +static unsigned +Field_t_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bbi_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_bbi_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_bbi_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 24) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_imm8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_imm8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_imm8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29); + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_imm8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); + tie_t = (val << 24) >> 29; + insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14); +} + +static unsigned +Field_imm8_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_imm8_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_imm8_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_imm8_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_imm8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_s_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_s8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_s8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_s8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_s8_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_s8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_s8_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_s8_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_imms8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_imms8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 22) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); + tie_t = (val << 21) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 20) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_imm12b_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_imm12b_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 20) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_imm12b_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_imm12b_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 10) | ((insn[0] << 18) >> 22); + return tie_t; +} + +static void +Field_imm12b_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0) | (tie_t << 4); + tie_t = (val << 20) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_imm12b_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 11) | ((insn[0] << 13) >> 21); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 17) >> 21; + insn[0] = (insn[0] & ~0x7ff00) | (tie_t << 8); + tie_t = (val << 16) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_imm16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 14) | ((insn[0] << 14) >> 18); + return tie_t; +} + +static void +Field_imm16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0) | (tie_t << 4); + tie_t = (val << 16) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_imm16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_imm16_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_imm16_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_imm16_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_offset_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 17) | ((insn[0] << 15) >> 15); + return tie_t; +} + +static void +Field_offset_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff) | (tie_t << 0); + tie_t = (val << 14) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_offset_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 17) | ((insn[0] << 15) >> 15); + return tie_t; +} + +static void +Field_offset_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff) | (tie_t << 0); + tie_t = (val << 14) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_offset_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_op2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_op2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_op2_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_op2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_op2_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_op2_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_op2_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_op2_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_r_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_disp_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_r_disp_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_r_3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r_3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_sae_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_sae_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_sae_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sae_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_sae_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_sal_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_sal_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_sal_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sal_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_sargt_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_sargt_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sargt_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_sargt_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_sas_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sas_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_sas_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_sas_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_sas_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_sas_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_sas_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_sas_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_sas_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_sas_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_sas_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_t2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_t2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_t2_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_t2_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); +} + +static unsigned +Field_s2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_r2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_r2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_r2_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_r2_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_t4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_t4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_t4_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_t4_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); +} + +static unsigned +Field_s4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_s4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_s4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_s4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_s4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_s4_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_s4_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_s4_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_s4_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_s4_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_r4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_r4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_r4_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_r4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_r4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_r4_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_r4_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_r4_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_t8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_r8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_xt_wbr15_imm_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_xt_wbr15_imm_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_xt_wbr15_imm_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_xt_wloop_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_xt_wloop_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_arithmetic_art_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_art_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_art_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_art_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 6) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 6) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 16) >> 26); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_br4t_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_br4t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpcnv_arr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_arr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_hpcnv_arr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_arr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_hpcnv_art_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_art_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_hpcnv_art_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_art_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 23) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_vu_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_vu_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_vu_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_vu_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_vu_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_vu_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_vu_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_vu_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_rng_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_rng_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_a_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_a_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_shift_a0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_a0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_a0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_shift_a0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_a0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_shift_d1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_d1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_da_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_da_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_da_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_da_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_shift_da_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_da_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_i32_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_shift_i32_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i32_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_i32_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 7) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i32_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_shift_i32_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i32_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_shift_i32_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i32_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_shift_i64_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i64_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_i64_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i64_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_sem_shift_i64_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i64_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_shift_i64_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i64_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_shift_i64_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i64_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_shift_imm32_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_imm32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_imm32_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_imm32_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_imm8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_imm8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_sd_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_sd_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_sd_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_sd_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_sd_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_sd_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_shift_sd_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_sd_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_shift_sd_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_sd_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_arr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_arr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_arr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_arr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_arr_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_arr_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_art_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_art_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_art_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_art_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_art_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_art_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vr_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vr_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vt_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vt_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 23) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_ds_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_ds_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_ds_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_ds_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_ds_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_ds_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 1) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000000) | (tie_t << 30); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 1) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000000) | (tie_t << 30); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_imm_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_imm_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_multiply_d1_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d1_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_d1_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d1_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_multiply_d1_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d1_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_multiply_d1_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d1_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d3_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d3_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_multiply_d3_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d3_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d3_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d3_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_multiply_d3_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d3_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_rng_d_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_d_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_shift_e_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_e_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_i8_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i8_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vp_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vp_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vp_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vp_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vp_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vp_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vq_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vq_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vq_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vq_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vq_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vq_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_sb_loads_stores_iba2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sb_loads_stores_iba2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_ardecnorm16_ar_u_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_ardecnorm16_ar_u_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_lb_db_ops_ar_u_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_db_ops_ar_u_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_lb_db_ops_iba_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_db_ops_iba_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_rng_a_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_a_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_rng_art_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_art_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_rng_i2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_i2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_rng_imm2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_imm2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_nn_c0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_c0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_mul_nn_c1_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_c1_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae_sem_mul_nn_c2_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_c2_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_mul_nn_c3_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_c3_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_nn_q0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_q0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_mul_nn_q1_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_q1_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_nn_q2_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_q2_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_mul_nn_q3_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_q3_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_mul_nn_v0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_v0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_mul_nn_v1_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_v1_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae_sem_mul_nn_v2_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_v2_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_mul_nn_v3_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_v3_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_hpfma_vp_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vp_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vu_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vu_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_vu_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vu_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vu_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vu_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vu_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vu_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vu_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vu_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vq_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vq_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_vq_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vq_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_inst_12_12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_inst_12_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_inst_12_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_inst_12_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_inst_13_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_fld_inst_13_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); +} + +static unsigned +Field_fld_inst_19_17_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_fld_inst_19_17_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_inst_19_18_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_inst_19_18_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_inst_23_12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_fld_inst_23_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_fld_inst_23_16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_fld_inst_23_16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_inst_4_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_inst_4_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_inst_5_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_inst_5_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_inst_7_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_inst_7_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_inst_7_6_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_inst_7_6_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_inst_7_7_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_inst_7_7_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_inst_9_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_inst_9_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) +{ + /* Do nothing. */ +} + +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 4; +} + +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 8; +} + +static unsigned +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 12; +} + +static unsigned +Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +enum xtensa_field_id { + FIELD_t, + FIELD_bbi4, + FIELD_bbi, + FIELD_imm12, + FIELD_imm8, + FIELD_s, + FIELD_s8, + FIELD_imms8, + FIELD_imm12b, + FIELD_imm16, + FIELD_m, + FIELD_n, + FIELD_offset, + FIELD_op0, + FIELD_op1, + FIELD_op2, + FIELD_r, + FIELD_r_disp, + FIELD_r_3, + FIELD_sa4, + FIELD_sae4, + FIELD_sae, + FIELD_sal, + FIELD_sargt, + FIELD_sas4, + FIELD_sas, + FIELD_sr, + FIELD_st, + FIELD_thi3, + FIELD_imm4, + FIELD_mn, + FIELD_i, + FIELD_imm6lo, + FIELD_imm6hi, + FIELD_imm7lo, + FIELD_imm7hi, + FIELD_z, + FIELD_imm6, + FIELD_imm7, + FIELD_t2, + FIELD_s2, + FIELD_r2, + FIELD_t4, + FIELD_s4, + FIELD_r4, + FIELD_t8, + FIELD_r8, + FIELD_xt_wbr15_imm, + FIELD_xt_wloop_imm, + FIELD_ae_fld_Inst16b_12, + FIELD_ae_fld_Inst16b_15_13, + FIELD_fld_ae_sem_arithmetic_art, + FIELD_fld_ae_sem_arithmetic_ds, + FIELD_fld_ae_sem_arithmetic_v, + FIELD_fld_ae_sem_arithmetic_v0, + FIELD_fld_ae_sem_arithmetic_v1, + FIELD_fld_ae_sem_arithmetic_va, + FIELD_fld_ae_sem_arithmetic_vs, + FIELD_fld_ae_sem_dr_to_ar_a, + FIELD_fld_ae_sem_dr_to_ar_ab, + FIELD_fld_ae_sem_dr_to_ar_ai, + FIELD_fld_ae_sem_dr_to_ar_aoe, + FIELD_fld_ae_sem_dr_to_ar_d, + FIELD_fld_ae_sem_dr_to_ar_d0, + FIELD_fld_ae_sem_dr_to_ar_d1, + FIELD_fld_ae_sem_dr_to_ar_imm8, + FIELD_fld_ae_sem_dr_to_ar_v0, + FIELD_fld_ae_sem_dr_to_ar_vr, + FIELD_fld_ae_sem_dr_to_dr_arr, + FIELD_fld_ae_sem_dr_to_dr_bt, + FIELD_fld_ae_sem_dr_to_dr_ds, + FIELD_fld_ae_sem_dr_to_dr_imm2, + FIELD_fld_ae_sem_dr_to_dr_immed, + FIELD_fld_ae_sem_dr_to_dr_movi_imm, + FIELD_fld_ae_sem_dr_to_dr_v, + FIELD_fld_ae_sem_dr_to_dr_v0, + FIELD_fld_ae_sem_dr_to_dr_v1, + FIELD_fld_ae_sem_hpcmp_br4t, + FIELD_fld_ae_sem_hpcmp_vr, + FIELD_fld_ae_sem_hpcmp_vs, + FIELD_fld_ae_sem_hpcnv_arr, + FIELD_fld_ae_sem_hpcnv_art, + FIELD_fld_ae_sem_hpcnv_i_imm4, + FIELD_fld_ae_sem_hpcnv_vr, + FIELD_fld_ae_sem_hpcnv_vt, + FIELD_fld_ae_sem_hprminmaxnum_vr, + FIELD_fld_ae_sem_hprminmaxnum_vt, + FIELD_fld_ae_sem_lb_ops_iba, + FIELD_fld_ae_sem_loads_stores_a, + FIELD_fld_ae_sem_loads_stores_a_0, + FIELD_fld_ae_sem_loads_stores_av, + FIELD_fld_ae_sem_loads_stores_av1, + FIELD_fld_ae_sem_loads_stores_end, + FIELD_fld_ae_sem_loads_stores_i128, + FIELD_fld_ae_sem_loads_stores_i16, + FIELD_fld_ae_sem_loads_stores_i3, + FIELD_fld_ae_sem_loads_stores_i32, + FIELD_fld_ae_sem_loads_stores_i32pos, + FIELD_fld_ae_sem_loads_stores_i64, + FIELD_fld_ae_sem_loads_stores_i64half, + FIELD_fld_ae_sem_loads_stores_i64neg, + FIELD_fld_ae_sem_loads_stores_i64pos, + FIELD_fld_ae_sem_loads_stores_i64x2, + FIELD_fld_ae_sem_loads_stores_i8, + FIELD_fld_ae_sem_loads_stores_imm2, + FIELD_fld_ae_sem_loads_stores_su, + FIELD_fld_ae_sem_loads_stores_uu, + FIELD_fld_ae_sem_loads_stores_v, + FIELD_fld_ae_sem_loads_stores_v1, + FIELD_fld_ae_sem_loads_stores_vu, + FIELD_fld_ae_sem_loads_stores_x, + FIELD_fld_ae_sem_pks_d, + FIELD_fld_ae_sem_pks_pos, + FIELD_fld_ae_sem_pks_s, + FIELD_fld_ae_sem_rng_v0, + FIELD_fld_ae_sem_rng_v1, + FIELD_fld_ae_sem_sb_loads_stores_iba, + FIELD_fld_ae_sem_shift_a, + FIELD_fld_ae_sem_shift_a0, + FIELD_fld_ae_sem_shift_d, + FIELD_fld_ae_sem_shift_d0, + FIELD_fld_ae_sem_shift_d1, + FIELD_fld_ae_sem_shift_da, + FIELD_fld_ae_sem_shift_i16, + FIELD_fld_ae_sem_shift_i32, + FIELD_fld_ae_sem_shift_i64, + FIELD_fld_ae_sem_shift_imm32, + FIELD_fld_ae_sem_shift_imm8, + FIELD_fld_ae_sem_shift_sd, + FIELD_fld_ae_sem_sp32cvt_arr, + FIELD_fld_ae_sem_sp32cvt_art, + FIELD_fld_ae_sem_sp32cvt_i_imm5, + FIELD_fld_ae_sem_sp32cvt_vr, + FIELD_fld_ae_sem_sp32cvt_vt, + FIELD_fld_ae_sem_spmisc_brt, + FIELD_fld_ae_sem_spmisc_vr, + FIELD_fld_ae_sem_spmisc_vs, + FIELD_fld_ae_slot0_11_10, + FIELD_fld_ae_slot0_11_11, + FIELD_fld_ae_slot0_11_8, + FIELD_fld_ae_slot0_11_9, + FIELD_fld_ae_slot0_12_0, + FIELD_fld_ae_slot0_12_10, + FIELD_fld_ae_slot0_12_12, + FIELD_fld_ae_slot0_12_2, + FIELD_fld_ae_slot0_12_6, + FIELD_fld_ae_slot0_12_8, + FIELD_fld_ae_slot0_12_9, + FIELD_fld_ae_slot0_14_12, + FIELD_fld_ae_slot0_14_13, + FIELD_fld_ae_slot0_17_10, + FIELD_fld_ae_slot0_17_12, + FIELD_fld_ae_slot0_17_13, + FIELD_fld_ae_slot0_17_14, + FIELD_fld_ae_slot0_17_15, + FIELD_fld_ae_slot0_17_16, + FIELD_fld_ae_slot0_17_17, + FIELD_fld_ae_slot0_17_8, + FIELD_fld_ae_slot0_18_13, + FIELD_fld_ae_slot0_18_15, + FIELD_fld_ae_slot0_18_16, + FIELD_fld_ae_slot0_18_8, + FIELD_fld_ae_slot0_19_12, + FIELD_fld_ae_slot0_19_15, + FIELD_fld_ae_slot0_19_19, + FIELD_fld_ae_slot0_19_8, + FIELD_fld_ae_slot0_1_0, + FIELD_fld_ae_slot0_1_1, + FIELD_fld_ae_slot0_20_16, + FIELD_fld_ae_slot0_20_20, + FIELD_fld_ae_slot0_23_15, + FIELD_fld_ae_slot0_23_17, + FIELD_fld_ae_slot0_23_19, + FIELD_fld_ae_slot0_23_22, + FIELD_fld_ae_slot0_28_10, + FIELD_fld_ae_slot0_28_12, + FIELD_fld_ae_slot0_28_14, + FIELD_fld_ae_slot0_28_15, + FIELD_fld_ae_slot0_28_16, + FIELD_fld_ae_slot0_28_17, + FIELD_fld_ae_slot0_28_19, + FIELD_fld_ae_slot0_28_21, + FIELD_fld_ae_slot0_28_22, + FIELD_fld_ae_slot0_28_24, + FIELD_fld_ae_slot0_28_26, + FIELD_fld_ae_slot0_28_27, + FIELD_fld_ae_slot0_28_4, + FIELD_fld_ae_slot0_28_8, + FIELD_fld_ae_slot0_3_0, + FIELD_fld_ae_slot0_3_1, + FIELD_fld_ae_slot0_3_2, + FIELD_fld_ae_slot0_3_3, + FIELD_fld_ae_slot0_4_0, + FIELD_fld_ae_slot0_4_4, + FIELD_fld_ae_slot0_5_0, + FIELD_fld_ae_slot0_5_4, + FIELD_fld_ae_slot0_7_0, + FIELD_fld_ae_slot0_7_2, + FIELD_fld_ae_slot0_7_3, + FIELD_fld_ae_slot0_7_4, + FIELD_fld_ae_slot0_8_8, + FIELD_fld_ae_slot0_9_4, + FIELD_fld_ae_slot0_9_8, + FIELD_fld_ae_slot0_9_9, + FIELD_fld_ae_slot1_0_0, + FIELD_fld_ae_slot1_12_8, + FIELD_fld_ae_slot1_17_13, + FIELD_fld_ae_slot1_17_17, + FIELD_fld_ae_slot1_17_8, + FIELD_fld_ae_slot1_25_1, + FIELD_fld_ae_slot1_25_12, + FIELD_fld_ae_slot1_25_13, + FIELD_fld_ae_slot1_25_16, + FIELD_fld_ae_slot1_25_17, + FIELD_fld_ae_slot1_25_18, + FIELD_fld_ae_slot1_25_20, + FIELD_fld_ae_slot1_25_22, + FIELD_fld_ae_slot1_25_23, + FIELD_fld_ae_slot1_25_8, + FIELD_fld_ae_slot1_25_9, + FIELD_fld_ae_slot1_3_0, + FIELD_fld_ae_slot1_3_2, + FIELD_fld_ae_slot1_3_3, + FIELD_fld_ae_slot1_7_4, + FIELD_fld_ae_sem_arithmetic_e, + FIELD_fld_ae_sem_arithmetic_ep, + FIELD_fld_ae_sem_arithmetic_ep1, + FIELD_fld_ae_sem_dr_to_ar_ei, + FIELD_fld_ae_sem_dr_to_ar_eo, + FIELD_fld_ae_sem_dr_to_dr_immed_N, + FIELD_fld_ae_sem_fpmov_i_imm4, + FIELD_fld_ae_sem_fpmov_vr, + FIELD_fld_ae_sem_fpmov_vs, + FIELD_fld_ae_sem_fpmov_vt, + FIELD_fld_ae_sem_fpmov_vu, + FIELD_fld_ae_sem_hpcmp_vt, + FIELD_fld_ae_sem_hpcnv_vs, + FIELD_fld_ae_sem_hpfma_vr, + FIELD_fld_ae_sem_hpfma_vs, + FIELD_fld_ae_sem_hpfma_vt, + FIELD_fld_ae_sem_movfpstate_v, + FIELD_fld_ae_sem_multiply_acc_ep, + FIELD_fld_ae_sem_multiply_d0, + FIELD_fld_ae_sem_multiply_d2, + FIELD_fld_ae_sem_multiply_q0, + FIELD_fld_ae_sem_multiply_q1, + FIELD_fld_ae_sem_reduction_sort_ds, + FIELD_fld_ae_sem_reduction_sort_v, + FIELD_fld_ae_sem_reduction_sort_v0, + FIELD_fld_ae_sem_select_isel, + FIELD_fld_ae_sem_select_ss, + FIELD_fld_ae_sem_select_vr, + FIELD_fld_ae_sem_select_vs, + FIELD_fld_ae_sem_select_vt, + FIELD_fld_ae_sem_select_vu, + FIELD_fld_ae_sem_spaddsub_vr, + FIELD_fld_ae_sem_spaddsub_vs, + FIELD_fld_ae_sem_spaddsub_vt, + FIELD_fld_ae_sem_spaddsub_vu, + FIELD_fld_ae_sem_spfma_i_imm1, + FIELD_fld_ae_sem_spfma_i_imm3, + FIELD_fld_ae_sem_spfma_vp, + FIELD_fld_ae_sem_spfma_vr, + FIELD_fld_ae_sem_spfma_vs, + FIELD_fld_ae_sem_spfma_vt, + FIELD_fld_ae_sem_spmisc_vsM, + FIELD_fld_ae_sem_spmisc_vt, + FIELD_fld_ae_sem_spmisc_vtM, + FIELD_fld_ae_slot2_14_0, + FIELD_fld_ae_slot2_14_10, + FIELD_fld_ae_slot2_14_14, + FIELD_fld_ae_slot2_14_5, + FIELD_fld_ae_slot2_16_15, + FIELD_fld_ae_slot2_19_15, + FIELD_fld_ae_slot2_28_15, + FIELD_fld_ae_slot2_28_17, + FIELD_fld_ae_slot2_28_19, + FIELD_fld_ae_slot2_28_20, + FIELD_fld_ae_slot2_28_25, + FIELD_fld_ae_slot2_28_4, + FIELD_fld_ae_slot2_28_5, + FIELD_fld_ae_slot2_3_0, + FIELD_fld_ae_slot2_9_0, + FIELD_fld_ae_slot2_9_1, + FIELD_fld_ae_slot2_9_2, + FIELD_fld_ae_slot2_9_5, + FIELD_fld_ae_slot2_9_6, + FIELD_fld_ae_slot2_9_7, + FIELD_fld_ae_slot2_9_8, + FIELD_fld_ae_sem_dr_to_dr_imm, + FIELD_fld_ae_sem_multiply_d1, + FIELD_fld_ae_sem_multiply_d3, + FIELD_fld_ae_sem_rng_d, + FIELD_fld_ae_sem_shift_e, + FIELD_fld_ae_sem_shift_i8, + FIELD_fld_ae_slot3_11_0, + FIELD_fld_ae_slot3_14_0, + FIELD_fld_ae_slot3_14_10, + FIELD_fld_ae_slot3_14_12, + FIELD_fld_ae_slot3_14_13, + FIELD_fld_ae_slot3_16_13, + FIELD_fld_ae_slot3_19_0, + FIELD_fld_ae_slot3_19_10, + FIELD_fld_ae_slot3_19_15, + FIELD_fld_ae_slot3_19_17, + FIELD_fld_ae_slot3_19_18, + FIELD_fld_ae_slot3_19_19, + FIELD_fld_ae_slot3_24_10, + FIELD_fld_ae_slot3_24_19, + FIELD_fld_ae_slot3_24_20, + FIELD_fld_ae_slot3_36_12, + FIELD_fld_ae_slot3_36_16, + FIELD_fld_ae_slot3_36_19, + FIELD_fld_ae_slot3_36_20, + FIELD_fld_ae_slot3_36_22, + FIELD_fld_ae_slot3_36_25, + FIELD_fld_ae_slot3_36_30, + FIELD_fld_ae_slot3_4_0, + FIELD_fld_ae_slot3_9_0, + FIELD_fld_ae_slot3_9_1, + FIELD_fld_ae_slot3_9_3, + FIELD_fld_ae_slot3_9_5, + FIELD_fld_ae2_slot0_0_0, + FIELD_fld_ae2_slot0_11_4, + FIELD_fld_ae2_slot0_11_8, + FIELD_fld_ae2_slot0_11_9, + FIELD_fld_ae2_slot0_12_0, + FIELD_fld_ae2_slot0_12_2, + FIELD_fld_ae2_slot0_12_4, + FIELD_fld_ae2_slot0_12_8, + FIELD_fld_ae2_slot0_14_13, + FIELD_fld_ae2_slot0_14_8, + FIELD_fld_ae2_slot0_15_0, + FIELD_fld_ae2_slot0_15_12, + FIELD_fld_ae2_slot0_15_13, + FIELD_fld_ae2_slot0_15_15, + FIELD_fld_ae2_slot0_15_4, + FIELD_fld_ae2_slot0_15_8, + FIELD_fld_ae2_slot0_17_13, + FIELD_fld_ae2_slot0_17_17, + FIELD_fld_ae2_slot0_18_15, + FIELD_fld_ae2_slot0_18_17, + FIELD_fld_ae2_slot0_18_18, + FIELD_fld_ae2_slot0_1_0, + FIELD_fld_ae2_slot0_23_18, + FIELD_fld_ae2_slot0_23_19, + FIELD_fld_ae2_slot0_3_0, + FIELD_fld_ae2_slot0_40_16, + FIELD_fld_ae2_slot0_40_17, + FIELD_fld_ae2_slot0_40_18, + FIELD_fld_ae2_slot0_40_19, + FIELD_fld_ae2_slot0_40_21, + FIELD_fld_ae2_slot0_40_23, + FIELD_fld_ae2_slot0_40_24, + FIELD_fld_ae2_slot0_40_25, + FIELD_fld_ae2_slot0_40_26, + FIELD_fld_ae2_slot0_40_27, + FIELD_fld_ae2_slot0_7_0, + FIELD_fld_ae2_slot0_7_4, + FIELD_fld_ae2_slot0_7_6, + FIELD_fld_ae2_slot0_7_7, + FIELD_fld_ae2_slot0_8_8, + FIELD_fld_ae2_slot0_9_8, + FIELD_fld_ae2_slot1_0_0, + FIELD_fld_ae2_slot1_11_0, + FIELD_fld_ae2_slot1_11_10, + FIELD_fld_ae2_slot1_11_8, + FIELD_fld_ae2_slot1_14_10, + FIELD_fld_ae2_slot1_14_11, + FIELD_fld_ae2_slot1_14_12, + FIELD_fld_ae2_slot1_14_14, + FIELD_fld_ae2_slot1_14_8, + FIELD_fld_ae2_slot1_36_12, + FIELD_fld_ae2_slot1_36_14, + FIELD_fld_ae2_slot1_36_15, + FIELD_fld_ae2_slot1_36_16, + FIELD_fld_ae2_slot1_36_17, + FIELD_fld_ae2_slot1_36_18, + FIELD_fld_ae2_slot1_36_20, + FIELD_fld_ae2_slot1_36_22, + FIELD_fld_ae2_slot1_36_23, + FIELD_fld_ae2_slot1_3_0, + FIELD_fld_ae2_slot1_3_1, + FIELD_fld_ae2_slot1_3_2, + FIELD_fld_ae2_slot1_3_3, + FIELD_fld_ae2_slot1_7_4, + FIELD_fld_ae2_slot1_9_8, + FIELD_fld_ae2_slot1_9_9, + FIELD_fld_ae2_slot2_14_10, + FIELD_fld_ae2_slot2_17_0, + FIELD_fld_ae2_slot2_17_10, + FIELD_fld_ae2_slot2_17_15, + FIELD_fld_ae2_slot2_17_17, + FIELD_fld_ae2_slot2_19_10, + FIELD_fld_ae2_slot2_19_15, + FIELD_fld_ae2_slot2_19_18, + FIELD_fld_ae2_slot2_19_9, + FIELD_fld_ae2_slot2_24_10, + FIELD_fld_ae2_slot2_24_15, + FIELD_fld_ae2_slot2_24_20, + FIELD_fld_ae2_slot2_24_5, + FIELD_fld_ae2_slot2_24_9, + FIELD_fld_ae2_slot2_42_18, + FIELD_fld_ae2_slot2_42_20, + FIELD_fld_ae2_slot2_42_25, + FIELD_fld_ae2_slot2_42_26, + FIELD_fld_ae2_slot2_42_28, + FIELD_fld_ae2_slot2_42_30, + FIELD_fld_ae2_slot2_4_0, + FIELD_fld_ae2_slot2_9_5, + FIELD_fld_ae_sem_spaddsub_vp, + FIELD_fld_ae_sem_spaddsub_vq, + FIELD_fld_ae3_slot0_11_11, + FIELD_fld_ae3_slot0_11_4, + FIELD_fld_ae3_slot0_11_8, + FIELD_fld_ae3_slot0_12_12, + FIELD_fld_ae3_slot0_12_8, + FIELD_fld_ae3_slot0_13_13, + FIELD_fld_ae3_slot0_13_8, + FIELD_fld_ae3_slot0_1_0, + FIELD_fld_ae3_slot0_32_11, + FIELD_fld_ae3_slot0_32_12, + FIELD_fld_ae3_slot0_32_13, + FIELD_fld_ae3_slot0_32_14, + FIELD_fld_ae3_slot0_32_15, + FIELD_fld_ae3_slot0_32_16, + FIELD_fld_ae3_slot0_32_17, + FIELD_fld_ae3_slot0_32_18, + FIELD_fld_ae3_slot0_32_20, + FIELD_fld_ae3_slot0_32_27, + FIELD_fld_ae3_slot0_32_8, + FIELD_fld_ae3_slot0_3_0, + FIELD_fld_ae3_slot0_3_2, + FIELD_fld_ae3_slot0_3_3, + FIELD_fld_ae3_slot0_4_0, + FIELD_fld_ae3_slot0_4_4, + FIELD_fld_ae3_slot0_5_0, + FIELD_fld_ae3_slot0_5_4, + FIELD_fld_ae3_slot0_7_0, + FIELD_fld_ae3_slot0_7_2, + FIELD_fld_ae3_slot0_7_4, + FIELD_fld_ae3_slot0_7_6, + FIELD_fld_ae3_slot0_8_8, + FIELD_fld_ae3_slot0_9_4, + FIELD_fld_ae3_slot0_9_8, + FIELD_fld_ae_sem_dr_to_ar_ar_s, + FIELD_fld_ae_sem_sb_loads_stores_iba2, + FIELD_fld_ae3_slot1_23_0, + FIELD_fld_ae3_slot1_23_11, + FIELD_fld_ae3_slot1_23_12, + FIELD_fld_ae3_slot1_23_13, + FIELD_fld_ae3_slot1_23_15, + FIELD_fld_ae3_slot1_23_16, + FIELD_fld_ae3_slot1_23_17, + FIELD_fld_ae3_slot1_23_19, + FIELD_fld_ae3_slot1_23_6, + FIELD_fld_ae3_slot1_23_8, + FIELD_fld_ae3_slot1_23_9, + FIELD_fld_ae3_slot1_3_0, + FIELD_fld_ae3_slot1_3_1, + FIELD_fld_ae3_slot1_3_2, + FIELD_fld_ae3_slot1_3_3, + FIELD_fld_ae3_slot1_7_4, + FIELD_fld_ae3_slot1_9_8, + FIELD_fld_AE_ARDECNORM16_ar_u, + FIELD_fld_ae5_slot0_11_10, + FIELD_fld_ae5_slot0_11_4, + FIELD_fld_ae5_slot0_11_8, + FIELD_fld_ae5_slot0_11_9, + FIELD_fld_ae5_slot0_12_10, + FIELD_fld_ae5_slot0_12_4, + FIELD_fld_ae5_slot0_12_6, + FIELD_fld_ae5_slot0_12_8, + FIELD_fld_ae5_slot0_12_9, + FIELD_fld_ae5_slot0_1_0, + FIELD_fld_ae5_slot0_1_1, + FIELD_fld_ae5_slot0_29_12, + FIELD_fld_ae5_slot0_29_13, + FIELD_fld_ae5_slot0_29_15, + FIELD_fld_ae5_slot0_29_16, + FIELD_fld_ae5_slot0_29_17, + FIELD_fld_ae5_slot0_29_18, + FIELD_fld_ae5_slot0_29_19, + FIELD_fld_ae5_slot0_29_20, + FIELD_fld_ae5_slot0_29_27, + FIELD_fld_ae5_slot0_29_5, + FIELD_fld_ae5_slot0_29_6, + FIELD_fld_ae5_slot0_29_8, + FIELD_fld_ae5_slot0_2_0, + FIELD_fld_ae5_slot0_3_0, + FIELD_fld_ae5_slot0_3_2, + FIELD_fld_ae5_slot0_4_0, + FIELD_fld_ae5_slot0_4_4, + FIELD_fld_ae5_slot0_7_0, + FIELD_fld_ae5_slot0_7_4, + FIELD_fld_ae5_slot0_7_7, + FIELD_fld_ae5_slot0_8_8, + FIELD_fld_ae_sem_lb_db_ops_ar_u, + FIELD_fld_ae_sem_lb_db_ops_iba, + FIELD_fld_ae_sem_rng_a, + FIELD_fld_ae_sem_rng_art, + FIELD_fld_ae_sem_rng_i2, + FIELD_fld_ae_sem_rng_imm2, + FIELD_fld_ae5_slot1_1_0, + FIELD_fld_ae5_slot2_14_10, + FIELD_fld_ae5_slot2_14_14, + FIELD_fld_ae5_slot2_14_5, + FIELD_fld_ae5_slot2_24_0, + FIELD_fld_ae5_slot2_24_15, + FIELD_fld_ae5_slot2_24_17, + FIELD_fld_ae5_slot2_24_20, + FIELD_fld_ae5_slot2_4_0, + FIELD_fld_ae5_slot2_9_0, + FIELD_fld_ae5_slot2_9_5, + FIELD_fld_ae5_slot2_9_7, + FIELD_fld_ae6_slot0_10_10, + FIELD_fld_ae6_slot0_15_15, + FIELD_fld_ae6_slot0_29_10, + FIELD_fld_ae6_slot0_29_13, + FIELD_fld_ae6_slot0_29_14, + FIELD_fld_ae6_slot0_29_15, + FIELD_fld_ae6_slot0_29_18, + FIELD_fld_ae6_slot0_29_20, + FIELD_fld_ae6_slot0_29_5, + FIELD_fld_ae6_slot0_4_0, + FIELD_fld_ae6_slot0_4_4, + FIELD_fld_ae6_slot0_7_4, + FIELD_fld_ae6_slot0_7_7, + FIELD_fld_ae6_slot0_9_8, + FIELD_fld_ae6_slot0_9_9, + FIELD_fld_ae6_slot1_14_14, + FIELD_fld_ae6_slot1_27_12, + FIELD_fld_ae6_slot1_27_15, + FIELD_fld_ae6_slot1_27_20, + FIELD_fld_ae6_slot1_27_21, + FIELD_fld_ae6_slot1_27_3, + FIELD_fld_ae6_slot1_27_6, + FIELD_fld_ae6_slot1_2_0, + FIELD_fld_ae6_slot1_9_5, + FIELD_fld_ae6_slot1_9_6, + FIELD_fld_ae6_slot1_9_7, + FIELD_fld_ae6_slot1_9_8, + FIELD_fld_ae6_slot1_9_9, + FIELD_fld_ae6_slot2_10_10, + FIELD_fld_ae6_slot2_11_10, + FIELD_fld_ae6_slot2_24_0, + FIELD_fld_ae6_slot2_24_10, + FIELD_fld_ae6_slot2_24_14, + FIELD_fld_ae6_slot2_24_15, + FIELD_fld_ae6_slot2_24_20, + FIELD_fld_ae6_slot2_4_2, + FIELD_fld_ae6_slot2_9_5, + FIELD_fld_ae6_slot3_10_10, + FIELD_fld_ae6_slot3_12_0, + FIELD_fld_ae6_slot3_14_0, + FIELD_fld_ae6_slot3_14_10, + FIELD_fld_ae6_slot3_14_13, + FIELD_fld_ae6_slot3_14_5, + FIELD_fld_ae6_slot3_24_20, + FIELD_fld_ae6_slot3_37_13, + FIELD_fld_ae6_slot3_37_15, + FIELD_fld_ae6_slot3_37_20, + FIELD_fld_ae6_slot3_37_30, + FIELD_fld_ae6_slot3_9_5, + FIELD_fld_ae7_slot0_12_6, + FIELD_fld_ae7_slot0_23_0, + FIELD_fld_ae7_slot0_23_13, + FIELD_fld_ae7_slot0_23_17, + FIELD_fld_ae7_slot0_23_18, + FIELD_fld_ae7_slot0_23_6, + FIELD_fld_ae7_slot0_7_4, + FIELD_fld_ae7_slot0_7_6, + FIELD_fld_ae7_slot0_7_7, + FIELD_fld_ae7_slot1_12_6, + FIELD_fld_ae7_slot1_23_0, + FIELD_fld_ae7_slot1_23_13, + FIELD_fld_ae7_slot1_23_17, + FIELD_fld_ae7_slot1_23_18, + FIELD_fld_ae7_slot1_23_6, + FIELD_fld_ae7_slot1_7_4, + FIELD_fld_ae7_slot1_7_6, + FIELD_fld_ae7_slot1_7_7, + FIELD_fld_ae7_slot2_11_0, + FIELD_fld_ae7_slot2_14_10, + FIELD_fld_ae7_slot2_14_5, + FIELD_fld_ae7_slot2_36_12, + FIELD_fld_ae7_slot2_36_15, + FIELD_fld_ae7_slot2_36_20, + FIELD_fld_ae7_slot2_36_25, + FIELD_fld_ae7_slot2_36_30, + FIELD_fld_ae7_slot2_9_5, + FIELD_fld_ae7_slot3_10_0, + FIELD_fld_ae7_slot3_14_10, + FIELD_fld_ae7_slot3_14_5, + FIELD_fld_ae7_slot3_24_10, + FIELD_fld_ae7_slot3_35_11, + FIELD_fld_ae7_slot3_35_20, + FIELD_fld_ae7_slot3_35_25, + FIELD_fld_ae7_slot3_35_30, + FIELD_fld_ae7_slot3_4_0, + FIELD_fld_ae7_slot3_9_5, + FIELD_fld_ae8_slot0_13_12, + FIELD_fld_ae8_slot0_13_13, + FIELD_fld_ae8_slot0_13_4, + FIELD_fld_ae8_slot0_13_9, + FIELD_fld_ae8_slot0_17_4, + FIELD_fld_ae8_slot0_17_8, + FIELD_fld_ae8_slot0_31_12, + FIELD_fld_ae8_slot0_31_15, + FIELD_fld_ae8_slot0_31_18, + FIELD_fld_ae8_slot0_31_19, + FIELD_fld_ae8_slot0_31_20, + FIELD_fld_ae8_slot0_31_21, + FIELD_fld_ae8_slot0_31_22, + FIELD_fld_ae8_slot0_31_23, + FIELD_fld_ae8_slot0_31_7, + FIELD_fld_ae8_slot0_31_8, + FIELD_fld_ae8_slot0_31_9, + FIELD_fld_ae8_slot0_3_0, + FIELD_fld_ae8_slot0_6_0, + FIELD_fld_ae8_slot0_7_4, + FIELD_fld_ae8_slot0_7_5, + FIELD_fld_ae8_slot0_7_7, + FIELD_fld_ae8_slot0_8_0, + FIELD_fld_ae8_slot1_17_13, + FIELD_fld_ae8_slot1_17_14, + FIELD_fld_ae8_slot1_17_15, + FIELD_fld_ae8_slot1_17_8, + FIELD_fld_ae8_slot1_29_12, + FIELD_fld_ae8_slot1_29_13, + FIELD_fld_ae8_slot1_29_18, + FIELD_fld_ae8_slot1_29_20, + FIELD_fld_ae8_slot1_29_22, + FIELD_fld_ae8_slot1_29_23, + FIELD_fld_ae8_slot1_29_5, + FIELD_fld_ae8_slot1_29_8, + FIELD_fld_ae8_slot1_29_9, + FIELD_fld_ae8_slot1_3_0, + FIELD_fld_ae8_slot1_3_3, + FIELD_fld_ae8_slot1_4_0, + FIELD_fld_ae8_slot1_7_4, + FIELD_fld_ae8_slot2_19_10, + FIELD_fld_ae8_slot2_19_15, + FIELD_fld_ae8_slot2_33_15, + FIELD_fld_ae8_slot2_33_25, + FIELD_fld_ae8_slot2_33_9, + FIELD_fld_ae8_slot2_34_30, + FIELD_fld_ae8_slot2_39_35, + FIELD_fld_ae8_slot2_44_35, + FIELD_fld_ae8_slot2_58_34, + FIELD_fld_ae8_slot2_58_35, + FIELD_fld_ae8_slot2_58_40, + FIELD_fld_ae8_slot2_58_50, + FIELD_fld_ae8_slot2_8_0, + FIELD_fld_ae8_slot2_9_0, + FIELD_fld_ae_sem_mul_nn_c0, + FIELD_fld_ae_sem_mul_nn_c1, + FIELD_fld_ae_sem_mul_nn_c2, + FIELD_fld_ae_sem_mul_nn_c3, + FIELD_fld_ae_sem_mul_nn_q0, + FIELD_fld_ae_sem_mul_nn_q1, + FIELD_fld_ae_sem_mul_nn_q2, + FIELD_fld_ae_sem_mul_nn_q3, + FIELD_fld_ae_sem_mul_nn_v0, + FIELD_fld_ae_sem_mul_nn_v1, + FIELD_fld_ae_sem_mul_nn_v2, + FIELD_fld_ae_sem_mul_nn_v3, + FIELD_fld_ae9_slot0_0_0, + FIELD_fld_ae9_slot0_12_12, + FIELD_fld_ae9_slot0_12_5, + FIELD_fld_ae9_slot0_12_8, + FIELD_fld_ae9_slot0_17_13, + FIELD_fld_ae9_slot0_17_4, + FIELD_fld_ae9_slot0_17_8, + FIELD_fld_ae9_slot0_27_10, + FIELD_fld_ae9_slot0_27_12, + FIELD_fld_ae9_slot0_27_13, + FIELD_fld_ae9_slot0_27_16, + FIELD_fld_ae9_slot0_27_17, + FIELD_fld_ae9_slot0_27_18, + FIELD_fld_ae9_slot0_27_19, + FIELD_fld_ae9_slot0_27_20, + FIELD_fld_ae9_slot0_27_22, + FIELD_fld_ae9_slot0_27_23, + FIELD_fld_ae9_slot0_27_3, + FIELD_fld_ae9_slot0_27_8, + FIELD_fld_ae9_slot0_2_0, + FIELD_fld_ae9_slot0_3_0, + FIELD_fld_ae9_slot0_7_0, + FIELD_fld_ae9_slot0_7_4, + FIELD_fld_ae9_slot0_7_5, + FIELD_fld_ae9_slot0_7_6, + FIELD_fld_ae9_slot0_7_7, + FIELD_fld_ae9_slot0_8_4, + FIELD_fld_ae9_slot0_8_5, + FIELD_fld_ae9_slot0_9_5, + FIELD_fld_ae9_slot1_17_13, + FIELD_fld_ae9_slot1_17_8, + FIELD_fld_ae9_slot1_1_0, + FIELD_fld_ae9_slot1_26_12, + FIELD_fld_ae9_slot1_26_13, + FIELD_fld_ae9_slot1_26_16, + FIELD_fld_ae9_slot1_26_17, + FIELD_fld_ae9_slot1_26_18, + FIELD_fld_ae9_slot1_26_2, + FIELD_fld_ae9_slot1_26_20, + FIELD_fld_ae9_slot1_26_22, + FIELD_fld_ae9_slot1_26_23, + FIELD_fld_ae9_slot1_26_8, + FIELD_fld_ae9_slot1_26_9, + FIELD_fld_ae9_slot1_3_0, + FIELD_fld_ae9_slot1_3_2, + FIELD_fld_ae9_slot1_3_3, + FIELD_fld_ae9_slot1_7_4, + FIELD_fld_ae9_slot2_24_14, + FIELD_fld_ae9_slot2_24_15, + FIELD_fld_ae9_slot2_24_20, + FIELD_fld_ae9_slot2_33_14, + FIELD_fld_ae9_slot2_33_15, + FIELD_fld_ae9_slot2_33_20, + FIELD_fld_ae9_slot2_33_25, + FIELD_fld_ae9_slot2_33_26, + FIELD_fld_ae9_slot2_33_28, + FIELD_fld_ae9_slot2_33_30, + FIELD_fld_ae9_slot2_33_9, + FIELD_fld_ae9_slot2_4_0, + FIELD_fld_ae9_slot2_5_0, + FIELD_fld_ae9_slot2_6_0, + FIELD_fld_ae9_slot2_8_0, + FIELD_fld_ae9_slot2_9_0, + FIELD_fld_ae9_slot2_9_5, + FIELD_fld_ae9_slot2_9_9, + FIELD_fld_ae_sem_hpfma_vp, + FIELD_fld_ae_sem_hpfma_vu, + FIELD_fld_ae_sem_spfma_vu, + FIELD_fld_ae9_slot3_19_15, + FIELD_fld_ae9_slot3_24_20, + FIELD_fld_ae9_slot3_31_14, + FIELD_fld_ae9_slot3_31_15, + FIELD_fld_ae9_slot3_31_20, + FIELD_fld_ae9_slot3_31_25, + FIELD_fld_ae9_slot3_31_26, + FIELD_fld_ae9_slot3_31_28, + FIELD_fld_ae9_slot3_31_7, + FIELD_fld_ae9_slot3_4_0, + FIELD_fld_ae9_slot3_4_3, + FIELD_fld_ae9_slot3_4_4, + FIELD_fld_ae9_slot3_6_0, + FIELD_fld_ae9_slot3_9_0, + FIELD_fld_ae9_slot3_9_5, + FIELD_fld_ae10_slot0_17_13, + FIELD_fld_ae10_slot0_17_4, + FIELD_fld_ae10_slot0_17_8, + FIELD_fld_ae10_slot0_24_0, + FIELD_fld_ae10_slot0_24_10, + FIELD_fld_ae10_slot0_24_12, + FIELD_fld_ae10_slot0_24_13, + FIELD_fld_ae10_slot0_24_16, + FIELD_fld_ae10_slot0_24_17, + FIELD_fld_ae10_slot0_24_18, + FIELD_fld_ae10_slot0_24_20, + FIELD_fld_ae10_slot0_24_8, + FIELD_fld_ae10_slot0_3_0, + FIELD_fld_ae10_slot0_7_4, + FIELD_fld_ae10_slot0_7_6, + FIELD_fld_ae10_slot0_7_7, + FIELD_fld_ae10_slot0_8_4, + FIELD_fld_ae10_slot1_0_0, + FIELD_fld_ae10_slot1_17_13, + FIELD_fld_ae10_slot1_17_8, + FIELD_fld_ae10_slot1_25_1, + FIELD_fld_ae10_slot1_25_12, + FIELD_fld_ae10_slot1_25_13, + FIELD_fld_ae10_slot1_25_16, + FIELD_fld_ae10_slot1_25_17, + FIELD_fld_ae10_slot1_25_18, + FIELD_fld_ae10_slot1_25_20, + FIELD_fld_ae10_slot1_25_22, + FIELD_fld_ae10_slot1_25_23, + FIELD_fld_ae10_slot1_25_8, + FIELD_fld_ae10_slot1_25_9, + FIELD_fld_ae10_slot1_3_0, + FIELD_fld_ae10_slot1_3_2, + FIELD_fld_ae10_slot1_3_3, + FIELD_fld_ae10_slot1_7_4, + FIELD_fld_ae10_slot2_24_20, + FIELD_fld_ae10_slot2_29_20, + FIELD_fld_ae10_slot2_29_25, + FIELD_fld_ae10_slot2_34_10, + FIELD_fld_ae10_slot2_34_14, + FIELD_fld_ae10_slot2_34_15, + FIELD_fld_ae10_slot2_34_20, + FIELD_fld_ae10_slot2_34_25, + FIELD_fld_ae10_slot2_34_30, + FIELD_fld_ae10_slot2_34_31, + FIELD_fld_ae10_slot2_34_33, + FIELD_fld_ae10_slot2_4_0, + FIELD_fld_ae10_slot2_9_0, + FIELD_fld_ae10_slot2_9_5, + FIELD_fld_ae_sem_hpfma_vq, + FIELD_fld_ae_sem_spfma_vq, + FIELD_fld_ae10_slot3_19_15, + FIELD_fld_ae10_slot3_29_20, + FIELD_fld_ae10_slot3_29_25, + FIELD_fld_ae10_slot3_34_10, + FIELD_fld_ae10_slot3_34_14, + FIELD_fld_ae10_slot3_34_15, + FIELD_fld_ae10_slot3_34_20, + FIELD_fld_ae10_slot3_34_25, + FIELD_fld_ae10_slot3_34_30, + FIELD_fld_ae10_slot3_34_31, + FIELD_fld_ae10_slot3_34_33, + FIELD_fld_ae10_slot3_4_0, + FIELD_fld_ae10_slot3_4_3, + FIELD_fld_ae10_slot3_4_4, + FIELD_fld_ae10_slot3_9_0, + FIELD_fld_ae10_slot3_9_5, + FIELD_fld_ae4_slot0_22_0, + FIELD_fld_ae4_slot0_22_12, + FIELD_fld_ae4_slot0_22_13, + FIELD_fld_ae4_slot0_22_16, + FIELD_fld_ae4_slot0_22_17, + FIELD_fld_ae4_slot0_22_18, + FIELD_fld_ae4_slot0_22_20, + FIELD_fld_ae4_slot0_22_6, + FIELD_fld_ae4_slot0_22_8, + FIELD_fld_ae4_slot0_3_0, + FIELD_fld_ae4_slot0_3_1, + FIELD_fld_ae4_slot0_4_4, + FIELD_fld_ae4_slot0_7_4, + FIELD_fld_ae4_slot1_22_0, + FIELD_fld_ae4_slot1_22_12, + FIELD_fld_ae4_slot1_22_13, + FIELD_fld_ae4_slot1_22_16, + FIELD_fld_ae4_slot1_22_17, + FIELD_fld_ae4_slot1_22_18, + FIELD_fld_ae4_slot1_22_8, + FIELD_fld_ae4_slot1_3_0, + FIELD_fld_ae4_slot1_3_1, + FIELD_fld_ae4_slot1_7_4, + FIELD_fld_ae4_slot2_23_0, + FIELD_fld_ae4_slot2_23_12, + FIELD_fld_ae4_slot2_23_15, + FIELD_fld_ae4_slot2_23_17, + FIELD_fld_ae4_slot2_23_20, + FIELD_fld_ae4_slot2_4_0, + FIELD_fld_ae4_slot2_9_5, + FIELD_fld_ae4_slot3_14_10, + FIELD_fld_ae4_slot3_19_15, + FIELD_fld_ae4_slot3_19_19, + FIELD_fld_ae4_slot3_19_5, + FIELD_fld_ae4_slot3_27_20, + FIELD_fld_ae4_slot3_27_25, + FIELD_fld_ae4_slot3_27_3, + FIELD_fld_ae4_slot3_2_0, + FIELD_fld_ae4_slot3_9_0, + FIELD_fld_ae4_slot3_9_5, + FIELD_fld_ae4_slot4_22_0, + FIELD_fld_ae4_slot4_22_15, + FIELD_fld_ae4_slot4_22_20, + FIELD_fld_ae4_slot4_9_5, + FIELD_fld_Inst_11_8, + FIELD_fld_Inst_12_12, + FIELD_fld_Inst_12_8, + FIELD_fld_Inst_13_8, + FIELD_fld_Inst_15_12, + FIELD_fld_Inst_19_17, + FIELD_fld_Inst_19_18, + FIELD_fld_Inst_23_12, + FIELD_fld_Inst_23_16, + FIELD_fld_Inst_4_4, + FIELD_fld_Inst_5_4, + FIELD_fld_Inst_7_4, + FIELD_fld_Inst_7_6, + FIELD_fld_Inst_7_7, + FIELD_fld_Inst_9_8, + FIELD_bitindex, + FIELD_s3to1, + FIELD__ar0, + FIELD__ar4, + FIELD__ar8, + FIELD__ar12, + FIELD__bt16, + FIELD__bs16, + FIELD__br16, + FIELD__brall +}; + + +/* Functional units. */ + +static xtensa_funcUnit_internal funcUnits[] = { + {"XT_LOADSTORE_UNIT", 2}, + { "mul_function", 1 }, + { "mul_S2_function", 1 }, + { "ae_add32x27", 1 }, + { "ae_shift32x4", 1 }, + { "ae_shift32x5", 1 }, + { "ae_leftshift32x5", 2 } +}; + +enum xtensa_funcUnit_id { + FUNCUNIT_XT_LOADSTORE_UNIT, + FUNCUNIT_mul_function, + FUNCUNIT_mul_S2_function, + FUNCUNIT_ae_add32x27, + FUNCUNIT_ae_shift32x4, + FUNCUNIT_ae_shift32x5, + FUNCUNIT_ae_leftshift32x5 +}; + + +/* Register files. */ + +enum xtensa_regfile_id { + REGFILE_AR, + REGFILE_BR, + REGFILE_AE_DR, + REGFILE_AE_VALIGN, + REGFILE_AE_EP, + REGFILE_BR2, + REGFILE_BR4, + REGFILE_BR8, + REGFILE_BR16 +}; + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", REGFILE_AR, 32, 64 }, + { "BR", "b", REGFILE_BR, 1, 16 }, + { "AE_DR", "aed", REGFILE_AE_DR, 64, 32 }, + { "AE_VALIGN", "u", REGFILE_AE_VALIGN, 128, 4 }, + { "AE_EP", "aep", REGFILE_AE_EP, 8, 4 }, + { "BR2", "b", REGFILE_BR, 2, 8 }, + { "BR4", "b", REGFILE_BR, 4, 4 }, + { "BR8", "b", REGFILE_BR, 8, 2 }, + { "BR16", "b", REGFILE_BR, 16, 1 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + { "IMPWIRE", 32, 0, 0, 'i' }, + { "ERI_RD_Rdy", 1, 0, 1, 'i' }, + { "ERI_RD_Out", 14, 0, 1, 'o' }, + { "ERI_RD_In", 32, 0, 2, 'i' }, + { "ERI_WR_Out", 46, 0, 3, 'o' }, + { "ERI_WR_In", 1, 0, 4, 'i' } +}; + +enum xtensa_interface_id { + INTERFACE_IMPWIRE, + INTERFACE_ERI_RD_Rdy, + INTERFACE_ERI_RD_Out, + INTERFACE_ERI_RD_In, + INTERFACE_ERI_WR_Out, + INTERFACE_ERI_WR_In +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table bitmask8 */ +static const unsigned CONST_TBL_bitmask8_0[] = { + 0 & 0xff, + 0x1 & 0xff, + 0x3 & 0xff, + 0x7 & 0xff, + 0xf & 0xff, + 0x1f & 0xff, + 0x3f & 0xff, + 0x7f & 0xff, + 0 +}; + +/* constant table bitmask16 */ +static const unsigned CONST_TBL_bitmask16_0[] = { + 0 & 0xffff, + 0x1 & 0xffff, + 0x3 & 0xffff, + 0x7 & 0xffff, + 0xf & 0xffff, + 0x1f & 0xffff, + 0x3f & 0xffff, + 0x7f & 0xffff, + 0xff & 0xffff, + 0x1ff & 0xffff, + 0x3ff & 0xffff, + 0x7ff & 0xffff, + 0xfff & 0xffff, + 0x1fff & 0xffff, + 0x3fff & 0xffff, + 0x7fff & 0xffff, + 0 +}; + +/* constant table ae_ltr4_table */ +static const unsigned CONST_TBL_ae_ltr4_table_0[] = { + 0 & 0xf, + 0x8 & 0xf, + 0xc & 0xf, + 0xe & 0xf, + 0 +}; + +/* constant table ae_ltr8_table */ +static const unsigned CONST_TBL_ae_ltr8_table_0[] = { + 0 & 0xff, + 0x80 & 0xff, + 0xc0 & 0xff, + 0xe0 & 0xff, + 0xf0 & 0xff, + 0xf8 & 0xff, + 0xfc & 0xff, + 0xfe & 0xff, + 0 +}; + +/* constant table ae_immls64neg */ +static const unsigned CONST_TBL_ae_immls64neg_0[] = { + 0xffffffe0, + 0xffffffe8, + 0xfffffff0, + 0xfffffff8, + 0 +}; + +/* constant table ae_slai72table */ +static const unsigned CONST_TBL_ae_slai72table_0[] = { + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0 +}; + +/* constant table ae_seliencode */ +static const unsigned CONST_TBL_ae_seliencode_0[] = { + 0x4e5 & 0xfff, + 0x65 & 0xfff, + 0x77 & 0xfff, + 0x4f7 & 0xfff, + 0x72e & 0xfff, + 0x29c & 0xfff, + 0xaf & 0xfff, + 0xa6 & 0xfff, + 0x2ef & 0xfff, + 0x10d & 0xfff, + 0x599 & 0xfff, + 0x59f & 0xfff, + 0xb3e & 0xfff, + 0x18f & 0xfff, + 0x51d & 0xfff, + 0xa6 & 0xfff, + 0 +}; + +/* constant table ae_ohba */ +static const unsigned CONST_TBL_ae_ohba_0[] = { + 0x1 & 0x1f, + 0x2 & 0x1f, + 0x3 & 0x1f, + 0x4 & 0x1f, + 0x5 & 0x1f, + 0x6 & 0x1f, + 0x7 & 0x1f, + 0x8 & 0x1f, + 0x9 & 0x1f, + 0xa & 0x1f, + 0xb & 0x1f, + 0xc & 0x1f, + 0xd & 0x1f, + 0xe & 0x1f, + 0xf & 0x1f, + 0x10 & 0x1f, + 0 +}; + +/* constant table ae_ohba2 */ +static const unsigned CONST_TBL_ae_ohba2_0[] = { + 0x1 & 0x1f, + 0x2 & 0x1f, + 0x3 & 0x1f, + 0x4 & 0x1f, + 0x5 & 0x1f, + 0x6 & 0x1f, + 0x7 & 0x1f, + 0x8 & 0x1f, + 0x9 & 0x1f, + 0xa & 0x1f, + 0xb & 0x1f, + 0xc & 0x1f, + 0xd & 0x1f, + 0xe & 0x1f, + 0xf & 0x1f, + 0x10 & 0x1f, + 0 +}; + +/* constant table ae_opnd_tp7 */ +static const unsigned CONST_TBL_ae_opnd_tp7_0[] = { + 0x7 & 0x1f, + 0x8 & 0x1f, + 0x9 & 0x1f, + 0xa & 0x1f, + 0xb & 0x1f, + 0xc & 0x1f, + 0xd & 0x1f, + 0xe & 0x1f, + 0xf & 0x1f, + 0x10 & 0x1f, + 0x11 & 0x1f, + 0x12 & 0x1f, + 0x13 & 0x1f, + 0x14 & 0x1f, + 0x15 & 0x1f, + 0x16 & 0x1f, + 0 +}; + +/* constant table xd_seli_8x8_table0 */ +static const unsigned CONST_TBL_xd_seli_8x8_table0_0[] = { + 0xba987654, + 0xfedc7654, + 0xfedc3210, + 0xba983210, + 0x98765432, + 0xdcba9876, + 0xfeba5410, + 0xfeba7632, + 0xdc985410, + 0xfe76dc54, + 0xba3298dc, + 0xba329810, + 0x54761032, + 0xfe32dc10, + 0xba769854, + 0xfeba7632, + 0xedcba987, + 0xcba98765, + 0xa9876543, + 0x87654321, + 0xf7e6d5c4, + 0xb3a29180, + 0xf3e2d1c0, + 0xb7a69584, + 0xfe76ba32, + 0xeca86420, + 0xfdb97531, + 0xeca87531, + 0xfdb96420, + 0xdc987632, + 0xefcdab89, + 0x32107654, + 0 +}; + +/* constant table xd_seli_8x8_table0_be */ +static const unsigned CONST_TBL_xd_seli_8x8_table0_be_0[] = { + 0x456789ab, + 0x12389ab, + 0x123cdef, + 0x4567cdef, + 0x6789abcd, + 0x23456789, + 0x145abef, + 0x14589cd, + 0x2367abef, + 0x18923ab, + 0x45cd6723, + 0x45cd67ef, + 0xab89efcd, + 0x1cd23ef, + 0x458967ab, + 0x14589cd, + 0x12345678, + 0x3456789a, + 0x56789abc, + 0x789abcde, + 0x8192a3b, + 0x4c5d6e7f, + 0xc1d2e3f, + 0x48596a7b, + 0x18945cd, + 0x13579bdf, + 0x2468ace, + 0x13578ace, + 0x2469bdf, + 0x236789cd, + 0x10325476, + 0xcdef89ab, + 0 +}; + +/* constant table tab_lavunqz_8x8 */ +static const unsigned CONST_TBL_tab_lavunqz_8x8_0[] = { + 0, + 0x7, + 0x70, + 0x76, + 0x700, + 0x706, + 0x760, + 0x765, + 0x7000, + 0x7006, + 0x7060, + 0x7065, + 0x7600, + 0x7605, + 0x7650, + 0x7654, + 0x70000, + 0x70006, + 0x70060, + 0x70065, + 0x70600, + 0x70605, + 0x70650, + 0x70654, + 0x76000, + 0x76005, + 0x76050, + 0x76054, + 0x76500, + 0x76504, + 0x76540, + 0x76543, + 0x700000, + 0x700006, + 0x700060, + 0x700065, + 0x700600, + 0x700605, + 0x700650, + 0x700654, + 0x706000, + 0x706005, + 0x706050, + 0x706054, + 0x706500, + 0x706504, + 0x706540, + 0x706543, + 0x760000, + 0x760005, + 0x760050, + 0x760054, + 0x760500, + 0x760504, + 0x760540, + 0x760543, + 0x765000, + 0x765004, + 0x765040, + 0x765043, + 0x765400, + 0x765403, + 0x765430, + 0x765432, + 0x7000000, + 0x7000006, + 0x7000060, + 0x7000065, + 0x7000600, + 0x7000605, + 0x7000650, + 0x7000654, + 0x7006000, + 0x7006005, + 0x7006050, + 0x7006054, + 0x7006500, + 0x7006504, + 0x7006540, + 0x7006543, + 0x7060000, + 0x7060005, + 0x7060050, + 0x7060054, + 0x7060500, + 0x7060504, + 0x7060540, + 0x7060543, + 0x7065000, + 0x7065004, + 0x7065040, + 0x7065043, + 0x7065400, + 0x7065403, + 0x7065430, + 0x7065432, + 0x7600000, + 0x7600005, + 0x7600050, + 0x7600054, + 0x7600500, + 0x7600504, + 0x7600540, + 0x7600543, + 0x7605000, + 0x7605004, + 0x7605040, + 0x7605043, + 0x7605400, + 0x7605403, + 0x7605430, + 0x7605432, + 0x7650000, + 0x7650004, + 0x7650040, + 0x7650043, + 0x7650400, + 0x7650403, + 0x7650430, + 0x7650432, + 0x7654000, + 0x7654003, + 0x7654030, + 0x7654032, + 0x7654300, + 0x7654302, + 0x7654320, + 0x7654321, + 0x70000000, + 0x70000006, + 0x70000060, + 0x70000065, + 0x70000600, + 0x70000605, + 0x70000650, + 0x70000654, + 0x70006000, + 0x70006005, + 0x70006050, + 0x70006054, + 0x70006500, + 0x70006504, + 0x70006540, + 0x70006543, + 0x70060000, + 0x70060005, + 0x70060050, + 0x70060054, + 0x70060500, + 0x70060504, + 0x70060540, + 0x70060543, + 0x70065000, + 0x70065004, + 0x70065040, + 0x70065043, + 0x70065400, + 0x70065403, + 0x70065430, + 0x70065432, + 0x70600000, + 0x70600005, + 0x70600050, + 0x70600054, + 0x70600500, + 0x70600504, + 0x70600540, + 0x70600543, + 0x70605000, + 0x70605004, + 0x70605040, + 0x70605043, + 0x70605400, + 0x70605403, + 0x70605430, + 0x70605432, + 0x70650000, + 0x70650004, + 0x70650040, + 0x70650043, + 0x70650400, + 0x70650403, + 0x70650430, + 0x70650432, + 0x70654000, + 0x70654003, + 0x70654030, + 0x70654032, + 0x70654300, + 0x70654302, + 0x70654320, + 0x70654321, + 0x76000000, + 0x76000005, + 0x76000050, + 0x76000054, + 0x76000500, + 0x76000504, + 0x76000540, + 0x76000543, + 0x76005000, + 0x76005004, + 0x76005040, + 0x76005043, + 0x76005400, + 0x76005403, + 0x76005430, + 0x76005432, + 0x76050000, + 0x76050004, + 0x76050040, + 0x76050043, + 0x76050400, + 0x76050403, + 0x76050430, + 0x76050432, + 0x76054000, + 0x76054003, + 0x76054030, + 0x76054032, + 0x76054300, + 0x76054302, + 0x76054320, + 0x76054321, + 0x76500000, + 0x76500004, + 0x76500040, + 0x76500043, + 0x76500400, + 0x76500403, + 0x76500430, + 0x76500432, + 0x76504000, + 0x76504003, + 0x76504030, + 0x76504032, + 0x76504300, + 0x76504302, + 0x76504320, + 0x76504321, + 0x76540000, + 0x76540003, + 0x76540030, + 0x76540032, + 0x76540300, + 0x76540302, + 0x76540320, + 0x76540321, + 0x76543000, + 0x76543002, + 0x76543020, + 0x76543021, + 0x76543200, + 0x76543201, + 0x76543210, + 0x76543210, + 0 +}; + +/* constant table tab_lavunqz_16x4 */ +static const unsigned CONST_TBL_tab_lavunqz_16x4_0[] = { + 0 & 0xff, + 0x3 & 0xff, + 0xc & 0xff, + 0xe & 0xff, + 0x30 & 0xff, + 0x32 & 0xff, + 0x38 & 0xff, + 0x39 & 0xff, + 0xc0 & 0xff, + 0xc2 & 0xff, + 0xc8 & 0xff, + 0xc9 & 0xff, + 0xe0 & 0xff, + 0xe1 & 0xff, + 0xe4 & 0xff, + 0xe4 & 0xff, + 0 +}; + +/* constant table xd_recip0_table128_8 */ +static const unsigned CONST_TBL_xd_recip0_table128_8_0[] = { + 0xff & 0xff, + 0xfd & 0xff, + 0xfb & 0xff, + 0xf9 & 0xff, + 0xf7 & 0xff, + 0xf5 & 0xff, + 0xf4 & 0xff, + 0xf2 & 0xff, + 0xf0 & 0xff, + 0xee & 0xff, + 0xed & 0xff, + 0xeb & 0xff, + 0xe9 & 0xff, + 0xe8 & 0xff, + 0xe6 & 0xff, + 0xe4 & 0xff, + 0xe3 & 0xff, + 0xe1 & 0xff, + 0xe0 & 0xff, + 0xde & 0xff, + 0xdd & 0xff, + 0xdb & 0xff, + 0xda & 0xff, + 0xd8 & 0xff, + 0xd7 & 0xff, + 0xd5 & 0xff, + 0xd4 & 0xff, + 0xd3 & 0xff, + 0xd1 & 0xff, + 0xd0 & 0xff, + 0xcf & 0xff, + 0xcd & 0xff, + 0xcc & 0xff, + 0xcb & 0xff, + 0xca & 0xff, + 0xc8 & 0xff, + 0xc7 & 0xff, + 0xc6 & 0xff, + 0xc5 & 0xff, + 0xc4 & 0xff, + 0xc2 & 0xff, + 0xc1 & 0xff, + 0xc0 & 0xff, + 0xbf & 0xff, + 0xbe & 0xff, + 0xbd & 0xff, + 0xbc & 0xff, + 0xbb & 0xff, + 0xba & 0xff, + 0xb9 & 0xff, + 0xb8 & 0xff, + 0xb7 & 0xff, + 0xb6 & 0xff, + 0xb5 & 0xff, + 0xb4 & 0xff, + 0xb3 & 0xff, + 0xb2 & 0xff, + 0xb1 & 0xff, + 0xb0 & 0xff, + 0xaf & 0xff, + 0xae & 0xff, + 0xad & 0xff, + 0xac & 0xff, + 0xab & 0xff, + 0xaa & 0xff, + 0xa9 & 0xff, + 0xa8 & 0xff, + 0xa8 & 0xff, + 0xa7 & 0xff, + 0xa6 & 0xff, + 0xa5 & 0xff, + 0xa4 & 0xff, + 0xa3 & 0xff, + 0xa3 & 0xff, + 0xa2 & 0xff, + 0xa1 & 0xff, + 0xa0 & 0xff, + 0x9f & 0xff, + 0x9f & 0xff, + 0x9e & 0xff, + 0x9d & 0xff, + 0x9c & 0xff, + 0x9c & 0xff, + 0x9b & 0xff, + 0x9a & 0xff, + 0x99 & 0xff, + 0x99 & 0xff, + 0x98 & 0xff, + 0x97 & 0xff, + 0x97 & 0xff, + 0x96 & 0xff, + 0x95 & 0xff, + 0x95 & 0xff, + 0x94 & 0xff, + 0x93 & 0xff, + 0x93 & 0xff, + 0x92 & 0xff, + 0x91 & 0xff, + 0x91 & 0xff, + 0x90 & 0xff, + 0x8f & 0xff, + 0x8f & 0xff, + 0x8e & 0xff, + 0x8e & 0xff, + 0x8d & 0xff, + 0x8c & 0xff, + 0x8c & 0xff, + 0x8b & 0xff, + 0x8b & 0xff, + 0x8a & 0xff, + 0x89 & 0xff, + 0x89 & 0xff, + 0x88 & 0xff, + 0x88 & 0xff, + 0x87 & 0xff, + 0x87 & 0xff, + 0x86 & 0xff, + 0x85 & 0xff, + 0x85 & 0xff, + 0x84 & 0xff, + 0x84 & 0xff, + 0x83 & 0xff, + 0x83 & 0xff, + 0x82 & 0xff, + 0x82 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0 +}; + +/* constant table xd_rsqrt0_table128_8 */ +static const unsigned CONST_TBL_xd_rsqrt0_table128_8_0[] = { + 0xb4 & 0xff, + 0xb3 & 0xff, + 0xb2 & 0xff, + 0xb0 & 0xff, + 0xaf & 0xff, + 0xae & 0xff, + 0xac & 0xff, + 0xab & 0xff, + 0xaa & 0xff, + 0xa9 & 0xff, + 0xa8 & 0xff, + 0xa7 & 0xff, + 0xa6 & 0xff, + 0xa5 & 0xff, + 0xa3 & 0xff, + 0xa2 & 0xff, + 0xa1 & 0xff, + 0xa0 & 0xff, + 0x9f & 0xff, + 0x9e & 0xff, + 0x9e & 0xff, + 0x9d & 0xff, + 0x9c & 0xff, + 0x9b & 0xff, + 0x9a & 0xff, + 0x99 & 0xff, + 0x98 & 0xff, + 0x97 & 0xff, + 0x97 & 0xff, + 0x96 & 0xff, + 0x95 & 0xff, + 0x94 & 0xff, + 0x93 & 0xff, + 0x93 & 0xff, + 0x92 & 0xff, + 0x91 & 0xff, + 0x90 & 0xff, + 0x90 & 0xff, + 0x8f & 0xff, + 0x8e & 0xff, + 0x8e & 0xff, + 0x8d & 0xff, + 0x8c & 0xff, + 0x8c & 0xff, + 0x8b & 0xff, + 0x8a & 0xff, + 0x8a & 0xff, + 0x89 & 0xff, + 0x89 & 0xff, + 0x88 & 0xff, + 0x87 & 0xff, + 0x87 & 0xff, + 0x86 & 0xff, + 0x86 & 0xff, + 0x85 & 0xff, + 0x84 & 0xff, + 0x84 & 0xff, + 0x83 & 0xff, + 0x83 & 0xff, + 0x82 & 0xff, + 0x82 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0x80 & 0xff, + 0xff & 0xff, + 0xfd & 0xff, + 0xfb & 0xff, + 0xf9 & 0xff, + 0xf7 & 0xff, + 0xf6 & 0xff, + 0xf4 & 0xff, + 0xf2 & 0xff, + 0xf1 & 0xff, + 0xef & 0xff, + 0xed & 0xff, + 0xec & 0xff, + 0xea & 0xff, + 0xe9 & 0xff, + 0xe7 & 0xff, + 0xe6 & 0xff, + 0xe4 & 0xff, + 0xe3 & 0xff, + 0xe1 & 0xff, + 0xe0 & 0xff, + 0xdf & 0xff, + 0xdd & 0xff, + 0xdc & 0xff, + 0xdb & 0xff, + 0xda & 0xff, + 0xd8 & 0xff, + 0xd7 & 0xff, + 0xd6 & 0xff, + 0xd5 & 0xff, + 0xd4 & 0xff, + 0xd3 & 0xff, + 0xd2 & 0xff, + 0xd0 & 0xff, + 0xcf & 0xff, + 0xce & 0xff, + 0xcd & 0xff, + 0xcc & 0xff, + 0xcb & 0xff, + 0xca & 0xff, + 0xc9 & 0xff, + 0xc8 & 0xff, + 0xc7 & 0xff, + 0xc6 & 0xff, + 0xc6 & 0xff, + 0xc5 & 0xff, + 0xc4 & 0xff, + 0xc3 & 0xff, + 0xc2 & 0xff, + 0xc1 & 0xff, + 0xc0 & 0xff, + 0xbf & 0xff, + 0xbf & 0xff, + 0xbe & 0xff, + 0xbd & 0xff, + 0xbc & 0xff, + 0xbb & 0xff, + 0xbb & 0xff, + 0xba & 0xff, + 0xb9 & 0xff, + 0xb8 & 0xff, + 0xb8 & 0xff, + 0xb7 & 0xff, + 0xb6 & 0xff, + 0xb5 & 0xff, + 0 +}; + +/* constant table vfpu2_table_mulmux */ +static const unsigned CONST_TBL_vfpu2_table_mulmux_0[] = { + 0xe & 0x3f, + 0x1e & 0x3f, + 0 +}; + +/* constant table vfpu2_table_maddmux */ +static const unsigned CONST_TBL_vfpu2_table_maddmux_0[] = { + 0xe & 0x3f, + 0x21 & 0x3f, + 0x3e & 0x3f, + 0x11 & 0x3f, + 0x1e & 0x3f, + 0x1 & 0x3f, + 0x2e & 0x3f, + 0x31 & 0x3f, + 0 +}; + +/* constant table xdsem_tab_la_default */ +static const unsigned CONST_TBL_xdsem_tab_la_default_0[] = { + 0xffff & 0xffff, + 0xfffe & 0xffff, + 0xfffc & 0xffff, + 0xfff8 & 0xffff, + 0xfff0 & 0xffff, + 0xffe0 & 0xffff, + 0xffc0 & 0xffff, + 0xff80 & 0xffff, + 0xff00 & 0xffff, + 0xfe00 & 0xffff, + 0xfc00 & 0xffff, + 0xf800 & 0xffff, + 0xf000 & 0xffff, + 0xe000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_lahr */ +static const unsigned CONST_TBL_xdsem_tab_lahr_0[] = { + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0 +}; + +/* constant table xdsem_tab_lahs */ +static const unsigned CONST_TBL_xdsem_tab_lahs_0[] = { + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev8_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev8_m64_0[] = { + 0x100 & 0xffff, + 0x200 & 0xffff, + 0x400 & 0xffff, + 0x800 & 0xffff, + 0x1000 & 0xffff, + 0x2000 & 0xffff, + 0x4000 & 0xffff, + 0x8000 & 0xffff, + 0x1 & 0xffff, + 0x2 & 0xffff, + 0x4 & 0xffff, + 0x8 & 0xffff, + 0x10 & 0xffff, + 0x20 & 0xffff, + 0x40 & 0xffff, + 0x80 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev8_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev8_m32_0[] = { + 0x1010 & 0xffff, + 0x2020 & 0xffff, + 0x4040 & 0xffff, + 0x8080 & 0xffff, + 0x101 & 0xffff, + 0x202 & 0xffff, + 0x404 & 0xffff, + 0x808 & 0xffff, + 0x1010 & 0xffff, + 0x2020 & 0xffff, + 0x4040 & 0xffff, + 0x8080 & 0xffff, + 0x101 & 0xffff, + 0x202 & 0xffff, + 0x404 & 0xffff, + 0x808 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev8_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev8_m16_0[] = { + 0x4444 & 0xffff, + 0x8888 & 0xffff, + 0x1111 & 0xffff, + 0x2222 & 0xffff, + 0x4444 & 0xffff, + 0x8888 & 0xffff, + 0x1111 & 0xffff, + 0x2222 & 0xffff, + 0x4444 & 0xffff, + 0x8888 & 0xffff, + 0x1111 & 0xffff, + 0x2222 & 0xffff, + 0x4444 & 0xffff, + 0x8888 & 0xffff, + 0x1111 & 0xffff, + 0x2222 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev8_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev8_m8_0[] = { + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev16_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev16_m64_0[] = { + 0 & 0xffff, + 0 & 0xffff, + 0x3 & 0xffff, + 0x3 & 0xffff, + 0xf & 0xffff, + 0xf & 0xffff, + 0x3f & 0xffff, + 0x3f & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xfc & 0xffff, + 0xfc & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0xc0 & 0xffff, + 0xc0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev16_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev16_m32_0[] = { + 0xff & 0xffff, + 0xff & 0xffff, + 0xcc & 0xffff, + 0xcc & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0x33 & 0xffff, + 0x33 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xcc & 0xffff, + 0xcc & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev16_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev16_m16_0[] = { + 0xff & 0xffff, + 0xff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev16_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev16_m8_0[] = { + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_128rev16_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_128rev16_m32_0[] = { + 0xffff & 0xffff, + 0xffff & 0xffff, + 0xcccc & 0xffff, + 0xcccc & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0x33 & 0xffff, + 0x33 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xcc & 0xffff, + 0xcc & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_128rev16_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_128rev16_m16_0[] = { + 0xffff & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xf0ff & 0xffff, + 0xf0ff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev32_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev32_m64_0[] = { + 0xf00 & 0xffff, + 0xf00 & 0xffff, + 0xf00 & 0xffff, + 0xf00 & 0xffff, + 0xf000 & 0xffff, + 0xf000 & 0xffff, + 0xf000 & 0xffff, + 0xf000 & 0xffff, + 0xf & 0xffff, + 0xf & 0xffff, + 0xf & 0xffff, + 0xf & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev32_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev32_m32_0[] = { + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev64_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev64_m64_0[] = { + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_r16_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_r16_m64_0[] = { + 0x300 & 0xffff, + 0x300 & 0xffff, + 0xc00 & 0xffff, + 0xc00 & 0xffff, + 0x3000 & 0xffff, + 0x3000 & 0xffff, + 0xc000 & 0xffff, + 0xc000 & 0xffff, + 0x3 & 0xffff, + 0x3 & 0xffff, + 0xc & 0xffff, + 0xc & 0xffff, + 0x30 & 0xffff, + 0x30 & 0xffff, + 0xc0 & 0xffff, + 0xc0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_r16_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_r16_m32_0[] = { + 0x3030 & 0xffff, + 0x3030 & 0xffff, + 0xc0c0 & 0xffff, + 0xc0c0 & 0xffff, + 0x303 & 0xffff, + 0x303 & 0xffff, + 0xc0c & 0xffff, + 0xc0c & 0xffff, + 0x3030 & 0xffff, + 0x3030 & 0xffff, + 0xc0c0 & 0xffff, + 0xc0c0 & 0xffff, + 0x303 & 0xffff, + 0x303 & 0xffff, + 0xc0c & 0xffff, + 0xc0c & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_r16_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_r16_m16_0[] = { + 0xcccc & 0xffff, + 0xcccc & 0xffff, + 0x3333 & 0xffff, + 0x3333 & 0xffff, + 0xcccc & 0xffff, + 0xcccc & 0xffff, + 0x3333 & 0xffff, + 0x3333 & 0xffff, + 0xcccc & 0xffff, + 0xcccc & 0xffff, + 0x3333 & 0xffff, + 0x3333 & 0xffff, + 0xcccc & 0xffff, + 0xcccc & 0xffff, + 0x3333 & 0xffff, + 0x3333 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_shiftrot_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_shiftrot_m64_0[] = { + 0 & 0xffff, + 0x101 & 0xffff, + 0x303 & 0xffff, + 0x707 & 0xffff, + 0xf0f & 0xffff, + 0x1f1f & 0xffff, + 0x3f3f & 0xffff, + 0x7f7f & 0xffff, + 0xffff & 0xffff, + 0xfefe & 0xffff, + 0xfcfc & 0xffff, + 0xf8f8 & 0xffff, + 0xf0f0 & 0xffff, + 0xe0e0 & 0xffff, + 0xc0c0 & 0xffff, + 0x8080 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_shiftrot_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_shiftrot_m32_0[] = { + 0 & 0xffff, + 0x1111 & 0xffff, + 0x3333 & 0xffff, + 0x7777 & 0xffff, + 0xffff & 0xffff, + 0xeeee & 0xffff, + 0xcccc & 0xffff, + 0x8888 & 0xffff, + 0 & 0xffff, + 0x1111 & 0xffff, + 0x3333 & 0xffff, + 0x7777 & 0xffff, + 0xffff & 0xffff, + 0xeeee & 0xffff, + 0xcccc & 0xffff, + 0x8888 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_shiftrot_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_shiftrot_m16_0[] = { + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_shiftrot_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_shiftrot_m8_0[] = { + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to16_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to16_m64_0[] = { + 0xf000 & 0xffff, + 0xe000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 & 0xffff, + 0x1 & 0xffff, + 0x3 & 0xffff, + 0x7 & 0xffff, + 0xf & 0xffff, + 0x11e & 0xffff, + 0x33c & 0xffff, + 0x778 & 0xffff, + 0xff0 & 0xffff, + 0x1ee0 & 0xffff, + 0x3cc0 & 0xffff, + 0x7880 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to16_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to16_m32_0[] = { + 0x3c0 & 0xffff, + 0x1680 & 0xffff, + 0x3c00 & 0xffff, + 0x6801 & 0xffff, + 0xc003 & 0xffff, + 0x8016 & 0xffff, + 0x3c & 0xffff, + 0x168 & 0xffff, + 0x3c0 & 0xffff, + 0x1680 & 0xffff, + 0x3c00 & 0xffff, + 0x6801 & 0xffff, + 0xc003 & 0xffff, + 0x8016 & 0xffff, + 0x3c & 0xffff, + 0x168 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to16_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to16_m16_0[] = { + 0x1818 & 0xffff, + 0x6060 & 0xffff, + 0x8181 & 0xffff, + 0x606 & 0xffff, + 0x1818 & 0xffff, + 0x6060 & 0xffff, + 0x8181 & 0xffff, + 0x606 & 0xffff, + 0x1818 & 0xffff, + 0x6060 & 0xffff, + 0x8181 & 0xffff, + 0x606 & 0xffff, + 0x1818 & 0xffff, + 0x6060 & 0xffff, + 0x8181 & 0xffff, + 0x606 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to16_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to16_m8_0[] = { + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp16to32_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp16to32_m16_0[] = { + 0x3838 & 0xffff, + 0x6161 & 0xffff, + 0x8383 & 0xffff, + 0x1616 & 0xffff, + 0x3838 & 0xffff, + 0x6161 & 0xffff, + 0x8383 & 0xffff, + 0x1616 & 0xffff, + 0x3838 & 0xffff, + 0x6161 & 0xffff, + 0x8383 & 0xffff, + 0x1616 & 0xffff, + 0x3838 & 0xffff, + 0x6161 & 0xffff, + 0x8383 & 0xffff, + 0x1616 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp16to32_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp16to32_m8_0[] = { + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to32_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to32_m64_0[] = { + 0xc00 & 0xffff, + 0x1800 & 0xffff, + 0x3000 & 0xffff, + 0x6000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 & 0xffff, + 0x1 & 0xffff, + 0x3 & 0xffff, + 0x6 & 0xffff, + 0xc & 0xffff, + 0x18 & 0xffff, + 0x30 & 0xffff, + 0x160 & 0xffff, + 0x3c0 & 0xffff, + 0x680 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to32_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to32_m32_0[] = { + 0x8020 & 0xffff, + 0x40 & 0xffff, + 0x180 & 0xffff, + 0x200 & 0xffff, + 0x401 & 0xffff, + 0x1802 & 0xffff, + 0x2004 & 0xffff, + 0x4018 & 0xffff, + 0x8020 & 0xffff, + 0x40 & 0xffff, + 0x180 & 0xffff, + 0x200 & 0xffff, + 0x401 & 0xffff, + 0x1802 & 0xffff, + 0x2004 & 0xffff, + 0x4018 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to32_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to32_m16_0[] = { + 0x2184 & 0xffff, + 0x4218 & 0xffff, + 0x8421 & 0xffff, + 0x1842 & 0xffff, + 0x2184 & 0xffff, + 0x4218 & 0xffff, + 0x8421 & 0xffff, + 0x1842 & 0xffff, + 0x2184 & 0xffff, + 0x4218 & 0xffff, + 0x8421 & 0xffff, + 0x1842 & 0xffff, + 0x2184 & 0xffff, + 0x4218 & 0xffff, + 0x8421 & 0xffff, + 0x1842 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to32_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to32_m8_0[] = { + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp16to32h_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp16to32h_m16_0[] = { + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr16to8_m8 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr16to8_m8_0[] = { + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr16to8_m16 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr16to8_m16_0[] = { + 0x4242 & 0xffff, + 0x9090 & 0xffff, + 0x2424 & 0xffff, + 0x909 & 0xffff, + 0x4242 & 0xffff, + 0x9090 & 0xffff, + 0x2424 & 0xffff, + 0x909 & 0xffff, + 0x4242 & 0xffff, + 0x9090 & 0xffff, + 0x2424 & 0xffff, + 0x909 & 0xffff, + 0x4242 & 0xffff, + 0x9090 & 0xffff, + 0x2424 & 0xffff, + 0x909 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr16to8_m32 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr16to8_m32_0[] = { + 0x300c & 0xffff, + 0x6108 & 0xffff, + 0xc300 & 0xffff, + 0x8610 & 0xffff, + 0xc30 & 0xffff, + 0x861 & 0xffff, + 0xc3 & 0xffff, + 0x1086 & 0xffff, + 0x300c & 0xffff, + 0x6108 & 0xffff, + 0xc300 & 0xffff, + 0x8610 & 0xffff, + 0xc30 & 0xffff, + 0x861 & 0xffff, + 0xc3 & 0xffff, + 0x1086 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr16to8_m64 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr16to8_m64_0[] = { + 0xf0 & 0xffff, + 0xe0 & 0xffff, + 0xc0 & 0xffff, + 0x80 & 0xffff, + 0 & 0xffff, + 0x100 & 0xffff, + 0x300 & 0xffff, + 0x700 & 0xffff, + 0xf00 & 0xffff, + 0x1e01 & 0xffff, + 0x3c03 & 0xffff, + 0x7807 & 0xffff, + 0xf00f & 0xffff, + 0xe01e & 0xffff, + 0xc03c & 0xffff, + 0x8078 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to8_m8 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to8_m8_0[] = { + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to8_m16 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to8_m16_0[] = { + 0x8400 & 0xffff, + 0x840 & 0xffff, + 0x84 & 0xffff, + 0x4008 & 0xffff, + 0x8400 & 0xffff, + 0x840 & 0xffff, + 0x84 & 0xffff, + 0x4008 & 0xffff, + 0x8400 & 0xffff, + 0x840 & 0xffff, + 0x84 & 0xffff, + 0x4008 & 0xffff, + 0x8400 & 0xffff, + 0x840 & 0xffff, + 0x84 & 0xffff, + 0x4008 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to8_m32 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to8_m32_0[] = { + 0x802 & 0xffff, + 0x4 & 0xffff, + 0x1008 & 0xffff, + 0x2000 & 0xffff, + 0x4010 & 0xffff, + 0x8120 & 0xffff, + 0x240 & 0xffff, + 0x481 & 0xffff, + 0x802 & 0xffff, + 0x4 & 0xffff, + 0x1008 & 0xffff, + 0x2000 & 0xffff, + 0x4010 & 0xffff, + 0x8120 & 0xffff, + 0x240 & 0xffff, + 0x481 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to8_m64 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to8_m64_0[] = { + 0xc & 0xffff, + 0x18 & 0xffff, + 0x30 & 0xffff, + 0x60 & 0xffff, + 0xc0 & 0xffff, + 0x80 & 0xffff, + 0 & 0xffff, + 0x100 & 0xffff, + 0x300 & 0xffff, + 0x600 & 0xffff, + 0xc00 & 0xffff, + 0x1800 & 0xffff, + 0x3000 & 0xffff, + 0x6001 & 0xffff, + 0xc003 & 0xffff, + 0x8006 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to16_m8 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to16_m8_0[] = { + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to16_m16 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to16_m16_0[] = { + 0xc0c0 & 0xffff, + 0x8484 & 0xffff, + 0xc0c & 0xffff, + 0x4848 & 0xffff, + 0xc0c0 & 0xffff, + 0x8484 & 0xffff, + 0xc0c & 0xffff, + 0x4848 & 0xffff, + 0xc0c0 & 0xffff, + 0x8484 & 0xffff, + 0xc0c & 0xffff, + 0x4848 & 0xffff, + 0xc0c0 & 0xffff, + 0x8484 & 0xffff, + 0xc0c & 0xffff, + 0x4848 & 0xffff, + 0 +}; + +/* constant table bitmask16rev */ +static const unsigned CONST_TBL_bitmask16rev_0[] = { + 0xffff & 0xffff, + 0xfffe & 0xffff, + 0xfffc & 0xffff, + 0xfff8 & 0xffff, + 0xfff0 & 0xffff, + 0xffe0 & 0xffff, + 0xffc0 & 0xffff, + 0xff80 & 0xffff, + 0xff00 & 0xffff, + 0xfe00 & 0xffff, + 0xfc00 & 0xffff, + 0xf800 & 0xffff, + 0xf000 & 0xffff, + 0xe000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 +}; + +/* constant table bitmask16sbe */ +static const unsigned CONST_TBL_bitmask16sbe_0[] = { + 0xfffe & 0xffff, + 0xfffc & 0xffff, + 0xfff8 & 0xffff, + 0xfff0 & 0xffff, + 0xffe0 & 0xffff, + 0xffc0 & 0xffff, + 0xff80 & 0xffff, + 0xff00 & 0xffff, + 0xfe00 & 0xffff, + 0xfc00 & 0xffff, + 0xf800 & 0xffff, + 0xf000 & 0xffff, + 0xe000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table bitmask16rxp */ +static const unsigned CONST_TBL_bitmask16rxp_0[] = { + 0 & 0xffff, + 0x8000 & 0xffff, + 0xc000 & 0xffff, + 0xe000 & 0xffff, + 0xf000 & 0xffff, + 0xf800 & 0xffff, + 0xfc00 & 0xffff, + 0xfe00 & 0xffff, + 0xff00 & 0xffff, + 0xff80 & 0xffff, + 0xffc0 & 0xffff, + 0xffe0 & 0xffff, + 0xfff0 & 0xffff, + 0xfff8 & 0xffff, + 0xfffc & 0xffff, + 0xfffe & 0xffff, + 0 +}; + + +/* Instruction operands. */ + +static int +OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) +{ + unsigned soffsetx4_out_0; + unsigned soffsetx4_in_0; + soffsetx4_in_0 = *valp & 0x3ffff; + soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); + *valp = soffsetx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) +{ + unsigned soffsetx4_in_0; + unsigned soffsetx4_out_0; + soffsetx4_out_0 = *valp; + soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; + *valp = soffsetx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_immr_decode (uint32 *valp) +{ + unsigned immr_out_0; + unsigned immr_in_0; + immr_in_0 = *valp & 0xf; + immr_out_0 = immr_in_0; + *valp = immr_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immr_encode (uint32 *valp) +{ + unsigned immr_in_0; + unsigned immr_out_0; + immr_out_0 = *valp; + immr_in_0 = (immr_out_0 & 0xf); + *valp = immr_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) +{ + unsigned uimm12x8_out_0; + unsigned uimm12x8_in_0; + uimm12x8_in_0 = *valp & 0xfff; + uimm12x8_out_0 = uimm12x8_in_0 << 3; + *valp = uimm12x8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) +{ + unsigned uimm12x8_in_0; + unsigned uimm12x8_out_0; + uimm12x8_out_0 = *valp; + uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); + *valp = uimm12x8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_decode (uint32 *valp) +{ + unsigned simm4_out_0; + unsigned simm4_in_0; + simm4_in_0 = *valp & 0xf; + simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; + *valp = simm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_encode (uint32 *valp) +{ + unsigned simm4_in_0; + unsigned simm4_out_0; + simm4_out_0 = *valp; + simm4_in_0 = (simm4_out_0 & 0xf); + *valp = simm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_0_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_4_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_8_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_8_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_12_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_12_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_entry_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_immrx4_decode (uint32 *valp) +{ + unsigned immrx4_out_0; + unsigned immrx4_in_0; + immrx4_in_0 = *valp & 0xf; + immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; + *valp = immrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immrx4_encode (uint32 *valp) +{ + unsigned immrx4_in_0; + unsigned immrx4_out_0; + immrx4_out_0 = *valp; + immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); + *valp = immrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) +{ + unsigned lsi4x4_out_0; + unsigned lsi4x4_in_0; + lsi4x4_in_0 = *valp & 0xf; + lsi4x4_out_0 = lsi4x4_in_0 << 2; + *valp = lsi4x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) +{ + unsigned lsi4x4_in_0; + unsigned lsi4x4_out_0; + lsi4x4_out_0 = *valp; + lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); + *valp = lsi4x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_decode (uint32 *valp) +{ + unsigned simm7_out_0; + unsigned simm7_in_0; + simm7_in_0 = *valp & 0x7f; + simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; + *valp = simm7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_encode (uint32 *valp) +{ + unsigned simm7_in_0; + unsigned simm7_out_0; + simm7_out_0 = *valp; + simm7_in_0 = (simm7_out_0 & 0x7f); + *valp = simm7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_decode (uint32 *valp) +{ + unsigned uimm6_out_0; + unsigned uimm6_in_0; + uimm6_in_0 = *valp & 0x3f; + uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); + *valp = uimm6_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_encode (uint32 *valp) +{ + unsigned uimm6_in_0; + unsigned uimm6_out_0; + uimm6_out_0 = *valp; + uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; + *valp = uimm6_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_decode (uint32 *valp) +{ + unsigned ai4const_out_0; + unsigned ai4const_in_0; + ai4const_in_0 = *valp & 0xf; + ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; + *valp = ai4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_encode (uint32 *valp) +{ + unsigned ai4const_in_0; + unsigned ai4const_out_0; + ai4const_out_0 = *valp; + switch (ai4const_out_0) + { + case 0xffffffff: ai4const_in_0 = 0; break; + case 0x1: ai4const_in_0 = 0x1; break; + case 0x2: ai4const_in_0 = 0x2; break; + case 0x3: ai4const_in_0 = 0x3; break; + case 0x4: ai4const_in_0 = 0x4; break; + case 0x5: ai4const_in_0 = 0x5; break; + case 0x6: ai4const_in_0 = 0x6; break; + case 0x7: ai4const_in_0 = 0x7; break; + case 0x8: ai4const_in_0 = 0x8; break; + case 0x9: ai4const_in_0 = 0x9; break; + case 0xa: ai4const_in_0 = 0xa; break; + case 0xb: ai4const_in_0 = 0xb; break; + case 0xc: ai4const_in_0 = 0xc; break; + case 0xd: ai4const_in_0 = 0xd; break; + case 0xe: ai4const_in_0 = 0xe; break; + default: ai4const_in_0 = 0xf; break; + } + *valp = ai4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_decode (uint32 *valp) +{ + unsigned b4const_out_0; + unsigned b4const_in_0; + b4const_in_0 = *valp & 0xf; + b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; + *valp = b4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_encode (uint32 *valp) +{ + unsigned b4const_in_0; + unsigned b4const_out_0; + b4const_out_0 = *valp; + switch (b4const_out_0) + { + case 0xffffffff: b4const_in_0 = 0; break; + case 0x1: b4const_in_0 = 0x1; break; + case 0x2: b4const_in_0 = 0x2; break; + case 0x3: b4const_in_0 = 0x3; break; + case 0x4: b4const_in_0 = 0x4; break; + case 0x5: b4const_in_0 = 0x5; break; + case 0x6: b4const_in_0 = 0x6; break; + case 0x7: b4const_in_0 = 0x7; break; + case 0x8: b4const_in_0 = 0x8; break; + case 0xa: b4const_in_0 = 0x9; break; + case 0xc: b4const_in_0 = 0xa; break; + case 0x10: b4const_in_0 = 0xb; break; + case 0x20: b4const_in_0 = 0xc; break; + case 0x40: b4const_in_0 = 0xd; break; + case 0x80: b4const_in_0 = 0xe; break; + default: b4const_in_0 = 0xf; break; + } + *valp = b4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_decode (uint32 *valp) +{ + unsigned b4constu_out_0; + unsigned b4constu_in_0; + b4constu_in_0 = *valp & 0xf; + b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; + *valp = b4constu_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_encode (uint32 *valp) +{ + unsigned b4constu_in_0; + unsigned b4constu_out_0; + b4constu_out_0 = *valp; + switch (b4constu_out_0) + { + case 0x8000: b4constu_in_0 = 0; break; + case 0x10000: b4constu_in_0 = 0x1; break; + case 0x2: b4constu_in_0 = 0x2; break; + case 0x3: b4constu_in_0 = 0x3; break; + case 0x4: b4constu_in_0 = 0x4; break; + case 0x5: b4constu_in_0 = 0x5; break; + case 0x6: b4constu_in_0 = 0x6; break; + case 0x7: b4constu_in_0 = 0x7; break; + case 0x8: b4constu_in_0 = 0x8; break; + case 0xa: b4constu_in_0 = 0x9; break; + case 0xc: b4constu_in_0 = 0xa; break; + case 0x10: b4constu_in_0 = 0xb; break; + case 0x20: b4constu_in_0 = 0xc; break; + case 0x40: b4constu_in_0 = 0xd; break; + case 0x80: b4constu_in_0 = 0xe; break; + default: b4constu_in_0 = 0xf; break; + } + *valp = b4constu_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_decode (uint32 *valp) +{ + unsigned immt_out_0; + unsigned immt_in_0; + immt_in_0 = *valp & 0xf; + immt_out_0 = immt_in_0; + *valp = immt_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_encode (uint32 *valp) +{ + unsigned immt_in_0; + unsigned immt_out_0; + immt_out_0 = *valp; + immt_in_0 = immt_out_0 & 0xf; + *valp = immt_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimms8_decode (uint32 *valp) +{ + unsigned uimms8_out_0; + unsigned uimms8_in_0; + uimms8_in_0 = *valp & 0x7; + uimms8_out_0 = uimms8_in_0; + *valp = uimms8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimms8_encode (uint32 *valp) +{ + unsigned uimms8_in_0; + unsigned uimms8_out_0; + uimms8_out_0 = *valp; + uimms8_in_0 = uimms8_out_0 & 0x7; + *valp = uimms8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_decode (uint32 *valp) +{ + unsigned uimm8_out_0; + unsigned uimm8_in_0; + uimm8_in_0 = *valp & 0xff; + uimm8_out_0 = uimm8_in_0; + *valp = uimm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_encode (uint32 *valp) +{ + unsigned uimm8_in_0; + unsigned uimm8_out_0; + uimm8_out_0 = *valp; + uimm8_in_0 = (uimm8_out_0 & 0xff); + *valp = uimm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) +{ + unsigned uimm8x2_out_0; + unsigned uimm8x2_in_0; + uimm8x2_in_0 = *valp & 0xff; + uimm8x2_out_0 = uimm8x2_in_0 << 1; + *valp = uimm8x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) +{ + unsigned uimm8x2_in_0; + unsigned uimm8x2_out_0; + uimm8x2_out_0 = *valp; + uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); + *valp = uimm8x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) +{ + unsigned uimm8x4_out_0; + unsigned uimm8x4_in_0; + uimm8x4_in_0 = *valp & 0xff; + uimm8x4_out_0 = uimm8x4_in_0 << 2; + *valp = uimm8x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) +{ + unsigned uimm8x4_in_0; + unsigned uimm8x4_out_0; + uimm8x4_out_0 = *valp; + uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); + *valp = uimm8x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) +{ + unsigned uimm4x16_out_0; + unsigned uimm4x16_in_0; + uimm4x16_in_0 = *valp & 0xf; + uimm4x16_out_0 = ((0 << 4) | uimm4x16_in_0) << 4; + *valp = uimm4x16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) +{ + unsigned uimm4x16_in_0; + unsigned uimm4x16_out_0; + uimm4x16_out_0 = *valp; + uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); + *valp = uimm4x16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp) +{ + unsigned uimmrx4_out_0; + unsigned uimmrx4_in_0; + uimmrx4_in_0 = *valp & 0xf; + uimmrx4_out_0 = ((0 << 4) | uimmrx4_in_0) << 2; + *valp = uimmrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp) +{ + unsigned uimmrx4_in_0; + unsigned uimmrx4_out_0; + uimmrx4_out_0 = *valp; + uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf); + *valp = uimmrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_decode (uint32 *valp) +{ + unsigned simm8_out_0; + unsigned simm8_in_0; + simm8_in_0 = *valp & 0xff; + simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; + *valp = simm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_encode (uint32 *valp) +{ + unsigned simm8_in_0; + unsigned simm8_out_0; + simm8_out_0 = *valp; + simm8_in_0 = (simm8_out_0 & 0xff); + *valp = simm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) +{ + unsigned simm8x256_out_0; + unsigned simm8x256_in_0; + simm8x256_in_0 = *valp & 0xff; + simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; + *valp = simm8x256_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) +{ + unsigned simm8x256_in_0; + unsigned simm8x256_out_0; + simm8x256_out_0 = *valp; + simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); + *valp = simm8x256_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_decode (uint32 *valp) +{ + unsigned simm12b_out_0; + unsigned simm12b_in_0; + simm12b_in_0 = *valp & 0xfff; + simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; + *valp = simm12b_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_encode (uint32 *valp) +{ + unsigned simm12b_in_0; + unsigned simm12b_out_0; + simm12b_out_0 = *valp; + simm12b_in_0 = (simm12b_out_0 & 0xfff); + *valp = simm12b_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_decode (uint32 *valp) +{ + unsigned msalp32_out_0; + unsigned msalp32_in_0; + msalp32_in_0 = *valp & 0x1f; + msalp32_out_0 = 0x20 - msalp32_in_0; + *valp = msalp32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_encode (uint32 *valp) +{ + unsigned msalp32_in_0; + unsigned msalp32_out_0; + msalp32_out_0 = *valp; + msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; + *valp = msalp32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_out_0; + unsigned op2p1_in_0; + op2p1_in_0 = *valp & 0xf; + op2p1_out_0 = op2p1_in_0 + 0x1; + *valp = op2p1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_encode (uint32 *valp) +{ + unsigned op2p1_in_0; + unsigned op2p1_out_0; + op2p1_out_0 = *valp; + op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; + *valp = op2p1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_decode (uint32 *valp) +{ + unsigned label8_out_0; + unsigned label8_in_0; + label8_in_0 = *valp & 0xff; + label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); + *valp = label8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_encode (uint32 *valp) +{ + unsigned label8_in_0; + unsigned label8_out_0; + label8_out_0 = *valp; + label8_in_0 = (label8_out_0 - 0x4) & 0xff; + *valp = label8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_decode (uint32 *valp) +{ + unsigned ulabel8_out_0; + unsigned ulabel8_in_0; + ulabel8_in_0 = *valp & 0xff; + ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0); + *valp = ulabel8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_encode (uint32 *valp) +{ + unsigned ulabel8_in_0; + unsigned ulabel8_out_0; + ulabel8_out_0 = *valp; + ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff; + *valp = ulabel8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_decode (uint32 *valp) +{ + unsigned label12_out_0; + unsigned label12_in_0; + label12_in_0 = *valp & 0xfff; + label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); + *valp = label12_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_encode (uint32 *valp) +{ + unsigned label12_in_0; + unsigned label12_out_0; + label12_out_0 = *valp; + label12_in_0 = (label12_out_0 - 0x4) & 0xfff; + *valp = label12_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_decode (uint32 *valp) +{ + unsigned soffset_out_0; + unsigned soffset_in_0; + soffset_in_0 = *valp & 0x3ffff; + soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); + *valp = soffset_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_encode (uint32 *valp) +{ + unsigned soffset_in_0; + unsigned soffset_out_0; + soffset_out_0 = *valp; + soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; + *valp = soffset_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) +{ + unsigned uimm16x4_out_0; + unsigned uimm16x4_in_0; + uimm16x4_in_0 = *valp & 0xffff; + uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; + *valp = uimm16x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) +{ + unsigned uimm16x4_in_0; + unsigned uimm16x4_out_0; + uimm16x4_out_0 = *valp; + uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; + *valp = uimm16x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_imms_decode (uint32 *valp) +{ + unsigned imms_out_0; + unsigned imms_in_0; + imms_in_0 = *valp & 0xf; + imms_out_0 = imms_in_0; + *valp = imms_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_imms_encode (uint32 *valp) +{ + unsigned imms_in_0; + unsigned imms_out_0; + imms_out_0 = *valp; + imms_in_0 = imms_out_0 & 0xf; + *valp = imms_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_BR_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16); + return error; +} + +static int +OperandSem_opnd_sem_BR2_decode (uint32 *valp) +{ + *valp = *valp << 1; + return 0; +} + +static int +OperandSem_opnd_sem_BR2_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 1) != 0); + *valp = *valp >> 1; + return error; +} + +static int +OperandSem_opnd_sem_BR4_decode (uint32 *valp) +{ + *valp = *valp << 2; + return 0; +} + +static int +OperandSem_opnd_sem_BR4_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 3) != 0); + *valp = *valp >> 2; + return error; +} + +static int +OperandSem_opnd_sem_BR8_decode (uint32 *valp) +{ + *valp = *valp << 3; + return 0; +} + +static int +OperandSem_opnd_sem_BR8_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 7) != 0); + *valp = *valp >> 3; + return error; +} + +static int +OperandSem_opnd_sem_BR16_decode (uint32 *valp) +{ + *valp = *valp << 4; + return 0; +} + +static int +OperandSem_opnd_sem_BR16_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 15) != 0); + *valp = *valp >> 4; + return error; +} + +static int +OperandSem_opnd_sem_tp7_decode (uint32 *valp) +{ + unsigned tp7_out_0; + unsigned tp7_in_0; + tp7_in_0 = *valp & 0xf; + tp7_out_0 = tp7_in_0 + 0x7; + *valp = tp7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_tp7_encode (uint32 *valp) +{ + unsigned tp7_in_0; + unsigned tp7_out_0; + tp7_out_0 = *valp; + tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; + *valp = tp7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) +{ + unsigned xt_wbr15_label_out_0; + unsigned xt_wbr15_label_in_0; + xt_wbr15_label_in_0 = *valp & 0x7fff; + xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); + *valp = xt_wbr15_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) +{ + unsigned xt_wbr15_label_in_0; + unsigned xt_wbr15_label_out_0; + xt_wbr15_label_out_0 = *valp; + xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; + *valp = xt_wbr15_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wloop_label_decode (uint32 *valp) +{ + unsigned xt_wloop_label_out_0; + unsigned xt_wloop_label_in_0; + xt_wloop_label_in_0 = *valp & 0x7fff; + xt_wloop_label_out_0 = 0x4 + (((0) << 15) | xt_wloop_label_in_0); + *valp = xt_wloop_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wloop_label_encode (uint32 *valp) +{ + unsigned xt_wloop_label_in_0; + unsigned xt_wloop_label_out_0; + xt_wloop_label_out_0 = *valp; + xt_wloop_label_in_0 = (xt_wloop_label_out_0 - 0x4) & 0x7fff; + *valp = xt_wloop_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_uimm2x2_decode (uint32 *valp) +{ + unsigned ae_uimm2x2_out_0; + unsigned ae_uimm2x2_in_0; + ae_uimm2x2_in_0 = *valp & 0x1; + ae_uimm2x2_out_0 = (0 << 2) | (ae_uimm2x2_in_0 << 1) | 0; + *valp = ae_uimm2x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_uimm2x2_encode (uint32 *valp) +{ + unsigned ae_uimm2x2_in_0; + unsigned ae_uimm2x2_out_0; + ae_uimm2x2_out_0 = *valp; + ae_uimm2x2_in_0 = (((ae_uimm2x2_out_0 >> 1) & 1)) & 0x1; + *valp = ae_uimm2x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AE_DR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_DR_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64_out_0; + unsigned opnd_ae_sem_loads_stores_i64_in_0; + opnd_ae_sem_loads_stores_i64_in_0 = *valp & 0xf; + opnd_ae_sem_loads_stores_i64_out_0 = (((int) opnd_ae_sem_loads_stores_i64_in_0 << 28) >> 28) << 3; + *valp = opnd_ae_sem_loads_stores_i64_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64_in_0; + unsigned opnd_ae_sem_loads_stores_i64_out_0; + opnd_ae_sem_loads_stores_i64_out_0 = *valp; + opnd_ae_sem_loads_stores_i64_in_0 = ((opnd_ae_sem_loads_stores_i64_out_0 >> 3) & 0xf); + *valp = opnd_ae_sem_loads_stores_i64_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_sb_loads_stores_iba_out_0; + unsigned opnd_ae_sem_sb_loads_stores_iba_in_0; + opnd_ae_sem_sb_loads_stores_iba_in_0 = *valp & 0xf; + opnd_ae_sem_sb_loads_stores_iba_out_0 = CONST_TBL_ae_ohba_0[opnd_ae_sem_sb_loads_stores_iba_in_0 & 0xf]; + *valp = opnd_ae_sem_sb_loads_stores_iba_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_sb_loads_stores_iba_in_0; + unsigned opnd_ae_sem_sb_loads_stores_iba_out_0; + opnd_ae_sem_sb_loads_stores_iba_out_0 = *valp; + switch (opnd_ae_sem_sb_loads_stores_iba_out_0) + { + case 0x1: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0; break; + case 0x2: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x1; break; + case 0x3: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x2; break; + case 0x4: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x3; break; + case 0x5: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x4; break; + case 0x6: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x5; break; + case 0x7: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x6; break; + case 0x8: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x7; break; + case 0x9: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x8; break; + case 0xa: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x9; break; + case 0xb: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xa; break; + case 0xc: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xb; break; + case 0xd: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xc; break; + case 0xe: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xd; break; + case 0xf: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xe; break; + default: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xf; break; + } + *valp = opnd_ae_sem_sb_loads_stores_iba_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_imm2_out_0; + unsigned opnd_ae_sem_loads_stores_imm2_in_0; + opnd_ae_sem_loads_stores_imm2_in_0 = *valp & 0x3; + opnd_ae_sem_loads_stores_imm2_out_0 = (0 << 2) | opnd_ae_sem_loads_stores_imm2_in_0; + *valp = opnd_ae_sem_loads_stores_imm2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_imm2_in_0; + unsigned opnd_ae_sem_loads_stores_imm2_out_0; + opnd_ae_sem_loads_stores_imm2_out_0 = *valp; + opnd_ae_sem_loads_stores_imm2_in_0 = (opnd_ae_sem_loads_stores_imm2_out_0 & 0x3); + *valp = opnd_ae_sem_loads_stores_imm2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_movi_imm_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_dr_to_dr_movi_imm_out_0; + unsigned opnd_ae_sem_dr_to_dr_movi_imm_in_0; + opnd_ae_sem_dr_to_dr_movi_imm_in_0 = *valp & 0x3f; + opnd_ae_sem_dr_to_dr_movi_imm_out_0 = (((-(( ( ((((opnd_ae_sem_dr_to_dr_movi_imm_in_0 >> 4) & 0x3)) | 0xfffffffc)) == 0xffffffff))) & 0x3ffffff) << 6) | opnd_ae_sem_dr_to_dr_movi_imm_in_0; + *valp = opnd_ae_sem_dr_to_dr_movi_imm_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_movi_imm_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_dr_to_dr_movi_imm_in_0; + unsigned opnd_ae_sem_dr_to_dr_movi_imm_out_0; + opnd_ae_sem_dr_to_dr_movi_imm_out_0 = *valp; + opnd_ae_sem_dr_to_dr_movi_imm_in_0 = (opnd_ae_sem_dr_to_dr_movi_imm_out_0 & 0x3f); + *valp = opnd_ae_sem_dr_to_dr_movi_imm_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_spfma_i_imm3_out_0; + unsigned opnd_ae_sem_spfma_i_imm3_in_0; + opnd_ae_sem_spfma_i_imm3_in_0 = *valp & 0x7; + opnd_ae_sem_spfma_i_imm3_out_0 = (0 << 3) | opnd_ae_sem_spfma_i_imm3_in_0; + *valp = opnd_ae_sem_spfma_i_imm3_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_spfma_i_imm3_in_0; + unsigned opnd_ae_sem_spfma_i_imm3_out_0; + opnd_ae_sem_spfma_i_imm3_out_0 = *valp; + opnd_ae_sem_spfma_i_imm3_in_0 = (opnd_ae_sem_spfma_i_imm3_out_0 & 0x7); + *valp = opnd_ae_sem_spfma_i_imm3_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AE_VALIGN_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_VALIGN_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i32_out_0; + unsigned opnd_ae_sem_loads_stores_i32_in_0; + opnd_ae_sem_loads_stores_i32_in_0 = *valp & 0xf; + opnd_ae_sem_loads_stores_i32_out_0 = (((int) opnd_ae_sem_loads_stores_i32_in_0 << 28) >> 28) << 2; + *valp = opnd_ae_sem_loads_stores_i32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i32_in_0; + unsigned opnd_ae_sem_loads_stores_i32_out_0; + opnd_ae_sem_loads_stores_i32_out_0 = *valp; + opnd_ae_sem_loads_stores_i32_in_0 = ((opnd_ae_sem_loads_stores_i32_out_0 >> 2) & 0xf); + *valp = opnd_ae_sem_loads_stores_i32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32pos_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i32pos_out_0; + unsigned opnd_ae_sem_loads_stores_i32pos_in_0; + opnd_ae_sem_loads_stores_i32pos_in_0 = *valp & 0x7; + opnd_ae_sem_loads_stores_i32pos_out_0 = ((0 << 3) | opnd_ae_sem_loads_stores_i32pos_in_0) << 2; + *valp = opnd_ae_sem_loads_stores_i32pos_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32pos_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i32pos_in_0; + unsigned opnd_ae_sem_loads_stores_i32pos_out_0; + opnd_ae_sem_loads_stores_i32pos_out_0 = *valp; + opnd_ae_sem_loads_stores_i32pos_in_0 = ((opnd_ae_sem_loads_stores_i32pos_out_0 >> 2) & 0x7); + *valp = opnd_ae_sem_loads_stores_i32pos_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i16_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i16_out_0; + unsigned opnd_ae_sem_loads_stores_i16_in_0; + opnd_ae_sem_loads_stores_i16_in_0 = *valp & 0xf; + opnd_ae_sem_loads_stores_i16_out_0 = (((int) opnd_ae_sem_loads_stores_i16_in_0 << 28) >> 28) << 1; + *valp = opnd_ae_sem_loads_stores_i16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i16_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i16_in_0; + unsigned opnd_ae_sem_loads_stores_i16_out_0; + opnd_ae_sem_loads_stores_i16_out_0 = *valp; + opnd_ae_sem_loads_stores_i16_in_0 = ((opnd_ae_sem_loads_stores_i16_out_0 >> 1) & 0xf); + *valp = opnd_ae_sem_loads_stores_i16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i8_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i8_out_0; + unsigned opnd_ae_sem_loads_stores_i8_in_0; + opnd_ae_sem_loads_stores_i8_in_0 = *valp & 0xf; + opnd_ae_sem_loads_stores_i8_out_0 = ((int) opnd_ae_sem_loads_stores_i8_in_0 << 28) >> 28; + *valp = opnd_ae_sem_loads_stores_i8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i8_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i8_in_0; + unsigned opnd_ae_sem_loads_stores_i8_out_0; + opnd_ae_sem_loads_stores_i8_out_0 = *valp; + opnd_ae_sem_loads_stores_i8_in_0 = (opnd_ae_sem_loads_stores_i8_out_0 & 0xf); + *valp = opnd_ae_sem_loads_stores_i8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64pos_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64pos_out_0; + unsigned opnd_ae_sem_loads_stores_i64pos_in_0; + opnd_ae_sem_loads_stores_i64pos_in_0 = *valp & 0x7; + opnd_ae_sem_loads_stores_i64pos_out_0 = ((0 << 3) | opnd_ae_sem_loads_stores_i64pos_in_0) << 3; + *valp = opnd_ae_sem_loads_stores_i64pos_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64pos_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64pos_in_0; + unsigned opnd_ae_sem_loads_stores_i64pos_out_0; + opnd_ae_sem_loads_stores_i64pos_out_0 = *valp; + opnd_ae_sem_loads_stores_i64pos_in_0 = ((opnd_ae_sem_loads_stores_i64pos_out_0 >> 3) & 0x7); + *valp = opnd_ae_sem_loads_stores_i64pos_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64neg_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64neg_out_0; + unsigned opnd_ae_sem_loads_stores_i64neg_in_0; + opnd_ae_sem_loads_stores_i64neg_in_0 = *valp & 0x3; + opnd_ae_sem_loads_stores_i64neg_out_0 = CONST_TBL_ae_immls64neg_0[opnd_ae_sem_loads_stores_i64neg_in_0 & 0x3]; + *valp = opnd_ae_sem_loads_stores_i64neg_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64neg_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64neg_in_0; + unsigned opnd_ae_sem_loads_stores_i64neg_out_0; + opnd_ae_sem_loads_stores_i64neg_out_0 = *valp; + opnd_ae_sem_loads_stores_i64neg_in_0 = (((opnd_ae_sem_loads_stores_i64neg_out_0 == (CONST_TBL_ae_immls64neg_0[0]))) ? 0 : (((opnd_ae_sem_loads_stores_i64neg_out_0 == (CONST_TBL_ae_immls64neg_0[1]))) ? 0x1 : (((opnd_ae_sem_loads_stores_i64neg_out_0 == (CONST_TBL_ae_immls64neg_0[2]))) ? 0x2 : 0x3))) & 0x3; + *valp = opnd_ae_sem_loads_stores_i64neg_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64half_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64half_out_0; + unsigned opnd_ae_sem_loads_stores_i64half_in_0; + opnd_ae_sem_loads_stores_i64half_in_0 = *valp & 0x7; + opnd_ae_sem_loads_stores_i64half_out_0 = (((int) opnd_ae_sem_loads_stores_i64half_in_0 << 29) >> 29) << 3; + *valp = opnd_ae_sem_loads_stores_i64half_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64half_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64half_in_0; + unsigned opnd_ae_sem_loads_stores_i64half_out_0; + opnd_ae_sem_loads_stores_i64half_out_0 = *valp; + opnd_ae_sem_loads_stores_i64half_in_0 = ((opnd_ae_sem_loads_stores_i64half_out_0 >> 3) & 0x7); + *valp = opnd_ae_sem_loads_stores_i64half_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_hpcnv_i_imm4_out_0; + unsigned opnd_ae_sem_hpcnv_i_imm4_in_0; + opnd_ae_sem_hpcnv_i_imm4_in_0 = *valp & 0xf; + opnd_ae_sem_hpcnv_i_imm4_out_0 = (0 << 4) | opnd_ae_sem_hpcnv_i_imm4_in_0; + *valp = opnd_ae_sem_hpcnv_i_imm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_hpcnv_i_imm4_in_0; + unsigned opnd_ae_sem_hpcnv_i_imm4_out_0; + opnd_ae_sem_hpcnv_i_imm4_out_0 = *valp; + opnd_ae_sem_hpcnv_i_imm4_in_0 = (opnd_ae_sem_hpcnv_i_imm4_out_0 & 0xf); + *valp = opnd_ae_sem_hpcnv_i_imm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_sp32cvt_i_imm5_out_0; + unsigned opnd_ae_sem_sp32cvt_i_imm5_in_0; + opnd_ae_sem_sp32cvt_i_imm5_in_0 = *valp & 0x1f; + opnd_ae_sem_sp32cvt_i_imm5_out_0 = (0 << 5) | opnd_ae_sem_sp32cvt_i_imm5_in_0; + *valp = opnd_ae_sem_sp32cvt_i_imm5_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_sp32cvt_i_imm5_in_0; + unsigned opnd_ae_sem_sp32cvt_i_imm5_out_0; + opnd_ae_sem_sp32cvt_i_imm5_out_0 = *valp; + opnd_ae_sem_sp32cvt_i_imm5_in_0 = (opnd_ae_sem_sp32cvt_i_imm5_out_0 & 0x1f); + *valp = opnd_ae_sem_sp32cvt_i_imm5_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_shift_i64_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_shift_i64_out_0; + unsigned opnd_ae_sem_shift_i64_in_0; + opnd_ae_sem_shift_i64_in_0 = *valp & 0x3f; + opnd_ae_sem_shift_i64_out_0 = (0 << 6) | opnd_ae_sem_shift_i64_in_0; + *valp = opnd_ae_sem_shift_i64_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_shift_i64_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_shift_i64_in_0; + unsigned opnd_ae_sem_shift_i64_out_0; + opnd_ae_sem_shift_i64_out_0 = *valp; + opnd_ae_sem_shift_i64_in_0 = (opnd_ae_sem_shift_i64_out_0 & 0x3f); + *valp = opnd_ae_sem_shift_i64_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i128_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i128_out_0; + unsigned opnd_ae_sem_loads_stores_i128_in_0; + opnd_ae_sem_loads_stores_i128_in_0 = *valp & 0xf; + opnd_ae_sem_loads_stores_i128_out_0 = (((int) opnd_ae_sem_loads_stores_i128_in_0 << 28) >> 28) << 4; + *valp = opnd_ae_sem_loads_stores_i128_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i128_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i128_in_0; + unsigned opnd_ae_sem_loads_stores_i128_out_0; + opnd_ae_sem_loads_stores_i128_out_0 = *valp; + opnd_ae_sem_loads_stores_i128_in_0 = ((opnd_ae_sem_loads_stores_i128_out_0 >> 4) & 0xf); + *valp = opnd_ae_sem_loads_stores_i128_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64x2_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64x2_out_0; + unsigned opnd_ae_sem_loads_stores_i64x2_in_0; + opnd_ae_sem_loads_stores_i64x2_in_0 = *valp & 0x7; + opnd_ae_sem_loads_stores_i64x2_out_0 = ((0 << 3) | opnd_ae_sem_loads_stores_i64x2_in_0) << 3; + *valp = opnd_ae_sem_loads_stores_i64x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64x2_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64x2_in_0; + unsigned opnd_ae_sem_loads_stores_i64x2_out_0; + opnd_ae_sem_loads_stores_i64x2_out_0 = *valp; + opnd_ae_sem_loads_stores_i64x2_in_0 = (((opnd_ae_sem_loads_stores_i64x2_out_0 >> 3) & 0xf)) & 0x7; + *valp = opnd_ae_sem_loads_stores_i64x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AE_EP_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_EP_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_shift_i8_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_shift_i8_out_0; + unsigned opnd_ae_sem_shift_i8_in_0; + opnd_ae_sem_shift_i8_in_0 = *valp & 0x7; + opnd_ae_sem_shift_i8_out_0 = CONST_TBL_ae_slai72table_0[opnd_ae_sem_shift_i8_in_0 & 0x7]; + *valp = opnd_ae_sem_shift_i8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_shift_i8_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_shift_i8_in_0; + unsigned opnd_ae_sem_shift_i8_out_0; + opnd_ae_sem_shift_i8_out_0 = *valp; + switch (opnd_ae_sem_shift_i8_out_0) + { + case 0x1: opnd_ae_sem_shift_i8_in_0 = 0; break; + case 0x2: opnd_ae_sem_shift_i8_in_0 = 0x1; break; + case 0x3: opnd_ae_sem_shift_i8_in_0 = 0x2; break; + case 0x4: opnd_ae_sem_shift_i8_in_0 = 0x3; break; + case 0x5: opnd_ae_sem_shift_i8_in_0 = 0x4; break; + case 0x6: opnd_ae_sem_shift_i8_in_0 = 0x5; break; + case 0x7: opnd_ae_sem_shift_i8_in_0 = 0x6; break; + default: opnd_ae_sem_shift_i8_in_0 = 0x7; break; + } + *valp = opnd_ae_sem_shift_i8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_imm_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_dr_to_dr_imm_out_0; + unsigned opnd_ae_sem_dr_to_dr_imm_in_0; + opnd_ae_sem_dr_to_dr_imm_in_0 = *valp & 0xf; + opnd_ae_sem_dr_to_dr_imm_out_0 = CONST_TBL_ae_opnd_tp7_0[opnd_ae_sem_dr_to_dr_imm_in_0 & 0xf]; + *valp = opnd_ae_sem_dr_to_dr_imm_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_imm_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_dr_to_dr_imm_in_0; + unsigned opnd_ae_sem_dr_to_dr_imm_out_0; + opnd_ae_sem_dr_to_dr_imm_out_0 = *valp; + switch (opnd_ae_sem_dr_to_dr_imm_out_0) + { + case 0x7: opnd_ae_sem_dr_to_dr_imm_in_0 = 0; break; + case 0x8: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x1; break; + case 0x9: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x2; break; + case 0xa: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x3; break; + case 0xb: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x4; break; + case 0xc: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x5; break; + case 0xd: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x6; break; + case 0xe: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x7; break; + case 0xf: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x8; break; + case 0x10: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x9; break; + case 0x11: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xa; break; + case 0x12: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xb; break; + case 0x13: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xc; break; + case 0x14: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xd; break; + case 0x15: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xe; break; + default: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xf; break; + } + *valp = opnd_ae_sem_dr_to_dr_imm_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba2_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_sb_loads_stores_iba2_out_0; + unsigned opnd_ae_sem_sb_loads_stores_iba2_in_0; + opnd_ae_sem_sb_loads_stores_iba2_in_0 = *valp & 0xf; + opnd_ae_sem_sb_loads_stores_iba2_out_0 = CONST_TBL_ae_ohba2_0[opnd_ae_sem_sb_loads_stores_iba2_in_0 & 0xf]; + *valp = opnd_ae_sem_sb_loads_stores_iba2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba2_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_sb_loads_stores_iba2_in_0; + unsigned opnd_ae_sem_sb_loads_stores_iba2_out_0; + opnd_ae_sem_sb_loads_stores_iba2_out_0 = *valp; + switch (opnd_ae_sem_sb_loads_stores_iba2_out_0) + { + case 0x1: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0; break; + case 0x2: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x1; break; + case 0x3: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x2; break; + case 0x4: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x3; break; + case 0x5: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x4; break; + case 0x6: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x5; break; + case 0x7: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x6; break; + case 0x8: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x7; break; + case 0x9: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x8; break; + case 0xa: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x9; break; + case 0xb: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xa; break; + case 0xc: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xb; break; + case 0xd: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xc; break; + case 0xe: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xd; break; + case 0xf: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xe; break; + default: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xf; break; + } + *valp = opnd_ae_sem_sb_loads_stores_iba2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm1_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_spfma_i_imm1_out_0; + unsigned opnd_ae_sem_spfma_i_imm1_in_0; + opnd_ae_sem_spfma_i_imm1_in_0 = *valp & 0x1; + opnd_ae_sem_spfma_i_imm1_out_0 = (0 << 1) | opnd_ae_sem_spfma_i_imm1_in_0; + *valp = opnd_ae_sem_spfma_i_imm1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm1_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_spfma_i_imm1_in_0; + unsigned opnd_ae_sem_spfma_i_imm1_out_0; + opnd_ae_sem_spfma_i_imm1_out_0 = *valp; + opnd_ae_sem_spfma_i_imm1_in_0 = (((opnd_ae_sem_spfma_i_imm1_out_0 >> 0) & 1)) & 0x1; + *valp = opnd_ae_sem_spfma_i_imm1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_decode (uint32 *valp) +{ + unsigned bbi_out_0; + unsigned bbi_in_0; + bbi_in_0 = *valp & 0x1f; + bbi_out_0 = (0 << 5) | bbi_in_0; + *valp = bbi_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_encode (uint32 *valp) +{ + unsigned bbi_in_0; + unsigned bbi_out_0; + bbi_out_0 = *valp; + bbi_in_0 = (bbi_out_0 & 0x1f); + *valp = bbi_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_decode (uint32 *valp) +{ + unsigned s_out_0; + unsigned s_in_0; + s_in_0 = *valp & 0xf; + s_out_0 = (0 << 4) | s_in_0; + *valp = s_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_encode (uint32 *valp) +{ + unsigned s_in_0; + unsigned s_out_0; + s_out_0 = *valp; + s_in_0 = (s_out_0 & 0xf); + *valp = s_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bitindex_decode (uint32 *valp) +{ + unsigned bitindex_out_0; + unsigned bitindex_in_0; + bitindex_in_0 = *valp & 0x1f; + bitindex_out_0 = (0 << 5) | bitindex_in_0; + *valp = bitindex_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bitindex_encode (uint32 *valp) +{ + unsigned bitindex_in_0; + unsigned bitindex_out_0; + bitindex_out_0 = *valp; + bitindex_in_0 = (bitindex_out_0 & 0x1f); + *valp = bitindex_in_0; + return 0; +} + +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +{ + *valp -= (pc & ~0x3); + return 0; +} + +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += (pc & ~0x3); + return 0; +} + +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ulabel8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label12_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +{ + *valp -= ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_xt_wloop_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wloop_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static xtensa_operand_internal operands[] = { + { "soffsetx4", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa, + -1, 0 }, + { "immr", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_immr_encode, OperandSem_opnd_sem_immr_decode, + 0, 0, + -1, 0 }, + { "uimm12x8", FIELD_imm12, -1, 0, + 0, + OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, + 0, 0, + -1, 0 }, + { "simm4", FIELD_mn, -1, 0, + 0, + OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, + 0, 0, + -1, 0 }, + { "arr", FIELD_r, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "ars", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "*ars_invisible", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "art", FIELD_t, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "ar0", FIELD__ar0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, + 0, 0, + 0, 63 }, + { "ar4", FIELD__ar4, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, + 0, 0, + 0, 63 }, + { "ar8", FIELD__ar8, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_8_encode, OperandSem_opnd_sem_AR_8_decode, + 0, 0, + 0, 63 }, + { "ar12", FIELD__ar12, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_12_encode, OperandSem_opnd_sem_AR_12_decode, + 0, 0, + 0, 63 }, + { "ars_entry", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_entry_encode, OperandSem_opnd_sem_AR_entry_decode, + 0, 0, + 0, 63 }, + { "immrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, + 0, 0, + -1, 0 }, + { "lsi4x4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, + 0, 0, + -1, 0 }, + { "simm7", FIELD_imm7, -1, 0, + 0, + OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, + 0, 0, + -1, 0 }, + { "uimm6", FIELD_imm6, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa, + -1, 0 }, + { "ai4const", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, + 0, 0, + -1, 0 }, + { "b4const", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, + 0, 0, + -1, 0 }, + { "b4constu", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, + 0, 0, + -1, 0 }, + { "immt", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, + 0, 0, + -1, 0 }, + { "uimms8", FIELD_imms8, -1, 0, + 0, + OperandSem_opnd_sem_uimms8_encode, OperandSem_opnd_sem_uimms8_decode, + 0, 0, + -1, 0 }, + { "uimm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, + 0, 0, + -1, 0 }, + { "uimm8x2", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, + 0, 0, + -1, 0 }, + { "uimm8x4", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, + 0, 0, + -1, 0 }, + { "uimm4x16", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, + 0, 0, + -1, 0 }, + { "uimmrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode, + 0, 0, + -1, 0 }, + { "simm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, + 0, 0, + -1, 0 }, + { "simm8x256", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, + 0, 0, + -1, 0 }, + { "simm12b", FIELD_imm12b, -1, 0, + 0, + OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, + 0, 0, + -1, 0 }, + { "msalp32", FIELD_sal, -1, 0, + 0, + OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, + 0, 0, + -1, 0 }, + { "op2p1", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, + 0, 0, + -1, 0 }, + { "label8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, + Operand_label8_ator, Operand_label8_rtoa, + -1, 0 }, + { "ulabel8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode, + Operand_ulabel8_ator, Operand_ulabel8_rtoa, + -1, 0 }, + { "label12", FIELD_imm12, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, + Operand_label12_ator, Operand_label12_rtoa, + -1, 0 }, + { "soffset", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa, + -1, 0 }, + { "uimm16x4", FIELD_imm16, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa, + -1, 0 }, + { "imms", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_imms_encode, OperandSem_opnd_sem_imms_decode, + 0, 0, + -1, 0 }, + { "imms1", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_imms_encode, OperandSem_opnd_sem_imms_decode, + 0, 0, + -1, 0 }, + { "bt", FIELD_t, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "bs", FIELD_s, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "br", FIELD_r, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "bt2", FIELD_t2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "bs2", FIELD_s2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "br2", FIELD_r2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "bt4", FIELD_t4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "bs4", FIELD_s4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "br4", FIELD_r4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "bt8", FIELD_t8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0, + 0, 15 }, + { "bs8", FIELD_s8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0, + 0, 15 }, + { "br8", FIELD_r8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0, + 0, 15 }, + { "bt16", FIELD__bt16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "bs16", FIELD__bs16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "br16", FIELD__br16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "brall", FIELD__brall, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "tp7", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, + 0, 0, + -1, 0 }, + { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa, + -1, 0 }, + { "xt_wloop_label", FIELD_xt_wloop_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wloop_label_encode, OperandSem_opnd_sem_xt_wloop_label_decode, + Operand_xt_wloop_label_ator, Operand_xt_wloop_label_rtoa, + -1, 0 }, + { "ae_uimm2x2", FIELD_ae_fld_Inst16b_12, -1, 0, + 0, + OperandSem_opnd_sem_ae_uimm2x2_encode, OperandSem_opnd_sem_ae_uimm2x2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_dr_v", FIELD_fld_ae_sem_dr_to_dr_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_arithmetic_v", FIELD_fld_ae_sem_arithmetic_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_arithmetic_v0", FIELD_fld_ae_sem_arithmetic_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_arithmetic_v1", FIELD_fld_ae_sem_arithmetic_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_a.0", FIELD_fld_ae_sem_loads_stores_a_0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_loads_stores_x", FIELD_fld_ae_sem_loads_stores_x, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_loads_stores_end", FIELD_fld_ae_sem_loads_stores_end, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_loads_stores_i64", FIELD_fld_ae_sem_loads_stores_i64, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_lb_ops_iba", FIELD_fld_ae_sem_lb_ops_iba, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_encode, OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_sb_loads_stores_iba", FIELD_fld_ae_sem_sb_loads_stores_iba, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_encode, OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_pks_d", FIELD_fld_ae_sem_pks_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_pks_pos", FIELD_fld_ae_sem_pks_pos, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_pks_s", FIELD_fld_ae_sem_pks_s, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_a", FIELD_fld_ae_sem_dr_to_ar_a, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_dr_to_ar_v0", FIELD_fld_ae_sem_dr_to_ar_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_v0", FIELD_fld_ae_sem_dr_to_dr_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_ab", FIELD_fld_ae_sem_dr_to_ar_ab, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_dr_to_ar_ai", FIELD_fld_ae_sem_dr_to_ar_ai, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_dr_to_ar_aoe", FIELD_fld_ae_sem_dr_to_ar_aoe, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_dr_to_dr_movi_imm", FIELD_fld_ae_sem_dr_to_dr_movi_imm, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_movi_imm_encode, OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_movi_imm_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_dr_ds", FIELD_fld_ae_sem_dr_to_dr_ds, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_v1", FIELD_fld_ae_sem_dr_to_dr_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_imm8", FIELD_fld_ae_sem_dr_to_ar_imm8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_encode, OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_a0", FIELD_fld_ae_sem_shift_a0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_shift_d", FIELD_fld_ae_sem_shift_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_shift_d0", FIELD_fld_ae_sem_shift_d0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_d", FIELD_fld_ae_sem_dr_to_ar_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_d0", FIELD_fld_ae_sem_dr_to_ar_d0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_d1", FIELD_fld_ae_sem_dr_to_ar_d1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_imm2", FIELD_fld_ae_sem_dr_to_dr_imm2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_arithmetic_ds", FIELD_fld_ae_sem_arithmetic_ds, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_uu", FIELD_fld_ae_sem_loads_stores_uu, REGFILE_AE_VALIGN, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_VALIGN_encode, OperandSem_opnd_sem_AE_VALIGN_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_loads_stores_vu", FIELD_fld_ae_sem_loads_stores_vu, REGFILE_AE_VALIGN, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_VALIGN_encode, OperandSem_opnd_sem_AE_VALIGN_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_loads_stores_i32", FIELD_fld_ae_sem_loads_stores_i32, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_v", FIELD_fld_ae_sem_loads_stores_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_i32pos", FIELD_fld_ae_sem_loads_stores_i32pos, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32pos_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32pos_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i16", FIELD_fld_ae_sem_loads_stores_i16, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i16_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i16_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i8", FIELD_fld_ae_sem_loads_stores_i8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i8_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i8_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i64pos", FIELD_fld_ae_sem_loads_stores_i64pos, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64pos_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64pos_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i64neg", FIELD_fld_ae_sem_loads_stores_i64neg, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64neg_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64neg_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i64half", FIELD_fld_ae_sem_loads_stores_i64half, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64half_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64half_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_su", FIELD_fld_ae_sem_loads_stores_su, REGFILE_AE_VALIGN, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_VALIGN_encode, OperandSem_opnd_sem_AE_VALIGN_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_loads_stores_v1", FIELD_fld_ae_sem_loads_stores_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_av", FIELD_fld_ae_sem_loads_stores_av, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_shift_i16", FIELD_fld_ae_sem_shift_i16, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_encode, OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_i32", FIELD_fld_ae_sem_shift_i32, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_encode, OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_d1", FIELD_fld_ae_sem_shift_d1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_shift_da", FIELD_fld_ae_sem_shift_da, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_shift_imm32", FIELD_fld_ae_sem_shift_imm32, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_encode, OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_a", FIELD_fld_ae_sem_shift_a, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_shift_sd", FIELD_fld_ae_sem_shift_sd, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_shift_i64", FIELD_fld_ae_sem_shift_i64, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_shift_i64_encode, OperandSem_opnd_sem_opnd_ae_sem_shift_i64_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_imm8", FIELD_fld_ae_sem_shift_imm8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_encode, OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_dr_immed", FIELD_fld_ae_sem_dr_to_dr_immed, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_encode, OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_arithmetic_art", FIELD_fld_ae_sem_arithmetic_art, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_arithmetic_va", FIELD_fld_ae_sem_arithmetic_va, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_arithmetic_vs", FIELD_fld_ae_sem_arithmetic_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_i128", FIELD_fld_ae_sem_loads_stores_i128, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i128_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i128_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i64x2", FIELD_fld_ae_sem_loads_stores_i64x2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64x2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64x2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_av1", FIELD_fld_ae_sem_loads_stores_av1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_imm2", FIELD_fld_ae_sem_loads_stores_imm2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i3", FIELD_fld_ae_sem_loads_stores_i3, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_encode, OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_rng_v0", FIELD_fld_ae_sem_rng_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_rng_v1", FIELD_fld_ae_sem_rng_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_reduction_sort_v", FIELD_fld_ae_sem_reduction_sort_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_reduction_sort_v0", FIELD_fld_ae_sem_reduction_sort_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_reduction_sort_ds", FIELD_fld_ae_sem_reduction_sort_ds, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_multiply_d0", FIELD_fld_ae_sem_multiply_d0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_multiply_d2", FIELD_fld_ae_sem_multiply_d2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_multiply_q0", FIELD_fld_ae_sem_multiply_q0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_multiply_q1", FIELD_fld_ae_sem_multiply_q1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_immed.N", FIELD_fld_ae_sem_dr_to_dr_immed_N, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_ar_ei", FIELD_fld_ae_sem_dr_to_ar_ei, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_dr_to_ar_eo", FIELD_fld_ae_sem_dr_to_ar_eo, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_multiply_acc_ep", FIELD_fld_ae_sem_multiply_acc_ep, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_arithmetic_e", FIELD_fld_ae_sem_arithmetic_e, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_arithmetic_ep", FIELD_fld_ae_sem_arithmetic_ep, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_arithmetic_ep1", FIELD_fld_ae_sem_arithmetic_ep1, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_select_ss", FIELD_fld_ae_sem_select_ss, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_select_vr", FIELD_fld_ae_sem_select_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_select_vs", FIELD_fld_ae_sem_select_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_select_vt", FIELD_fld_ae_sem_select_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_select_vu", FIELD_fld_ae_sem_select_vu, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_select_isel", FIELD_fld_ae_sem_select_isel, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_encode, OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_e", FIELD_fld_ae_sem_shift_e, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_shift_i8", FIELD_fld_ae_sem_shift_i8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_shift_i8_encode, OperandSem_opnd_sem_opnd_ae_sem_shift_i8_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_multiply_d1", FIELD_fld_ae_sem_multiply_d1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_multiply_d3", FIELD_fld_ae_sem_multiply_d3, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_imm", FIELD_fld_ae_sem_dr_to_dr_imm, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_imm_encode, OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_imm_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_rng_d", FIELD_fld_ae_sem_rng_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_sb_loads_stores_iba2", FIELD_fld_ae_sem_sb_loads_stores_iba2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba2_encode, OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_ar_ar_s", FIELD_fld_ae_sem_dr_to_ar_ar_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_AE_ARDECNORM16_ar_u", FIELD_fld_AE_ARDECNORM16_ar_u, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_rng_a", FIELD_fld_ae_sem_rng_a, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_rng_art", FIELD_fld_ae_sem_rng_art, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_rng_i2", FIELD_fld_ae_sem_rng_i2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_rng_imm2", FIELD_fld_ae_sem_rng_imm2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_lb_db_ops_ar_u", FIELD_fld_ae_sem_lb_db_ops_ar_u, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_lb_db_ops_iba", FIELD_fld_ae_sem_lb_db_ops_iba, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_encode, OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_ar_vr", FIELD_fld_ae_sem_dr_to_ar_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spmisc_brt", FIELD_fld_ae_sem_spmisc_brt, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_spmisc_vr", FIELD_fld_ae_sem_spmisc_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spmisc_vs", FIELD_fld_ae_sem_spmisc_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_arr", FIELD_fld_ae_sem_dr_to_dr_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_dr_to_dr_bt", FIELD_fld_ae_sem_dr_to_dr_bt, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_sp32cvt_art", FIELD_fld_ae_sem_sp32cvt_art, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_sp32cvt_i_imm5", FIELD_fld_ae_sem_sp32cvt_i_imm5, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_encode, OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_sp32cvt_vr", FIELD_fld_ae_sem_sp32cvt_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_sp32cvt_vt", FIELD_fld_ae_sem_sp32cvt_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_sp32cvt_arr", FIELD_fld_ae_sem_sp32cvt_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_movfpstate_v", FIELD_fld_ae_sem_movfpstate_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_fpmov_vr", FIELD_fld_ae_sem_fpmov_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_fpmov_vt", FIELD_fld_ae_sem_fpmov_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_fpmov_i_imm4", FIELD_fld_ae_sem_fpmov_i_imm4, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_encode, OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_fpmov_vs", FIELD_fld_ae_sem_fpmov_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_fpmov_vu", FIELD_fld_ae_sem_fpmov_vu, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spmisc_vsM", FIELD_fld_ae_sem_spmisc_vsM, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spmisc_vtM", FIELD_fld_ae_sem_spmisc_vtM, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spmisc_vt", FIELD_fld_ae_sem_spmisc_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spaddsub_vr", FIELD_fld_ae_sem_spaddsub_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spaddsub_vs", FIELD_fld_ae_sem_spaddsub_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spaddsub_vt", FIELD_fld_ae_sem_spaddsub_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spaddsub_vu", FIELD_fld_ae_sem_spaddsub_vu, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vr", FIELD_fld_ae_sem_spfma_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vs", FIELD_fld_ae_sem_spfma_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vt", FIELD_fld_ae_sem_spfma_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vp", FIELD_fld_ae_sem_spfma_vp, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_i_imm1", FIELD_fld_ae_sem_spfma_i_imm1, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm1_encode, OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm1_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_spfma_i_imm3", FIELD_fld_ae_sem_spfma_i_imm3, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_encode, OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_spaddsub_vp", FIELD_fld_ae_sem_spaddsub_vp, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spaddsub_vq", FIELD_fld_ae_sem_spaddsub_vq, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vu", FIELD_fld_ae_sem_spfma_vu, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vq", FIELD_fld_ae_sem_spfma_vq, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hprminmaxnum_vr", FIELD_fld_ae_sem_hprminmaxnum_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hprminmaxnum_vt", FIELD_fld_ae_sem_hprminmaxnum_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcmp_br4t", FIELD_fld_ae_sem_hpcmp_br4t, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_hpcmp_vr", FIELD_fld_ae_sem_hpcmp_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcmp_vs", FIELD_fld_ae_sem_hpcmp_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcnv_art", FIELD_fld_ae_sem_hpcnv_art, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_hpcnv_i_imm4", FIELD_fld_ae_sem_hpcnv_i_imm4, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_encode, OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_hpcnv_vr", FIELD_fld_ae_sem_hpcnv_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcnv_arr", FIELD_fld_ae_sem_hpcnv_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_hpcnv_vt", FIELD_fld_ae_sem_hpcnv_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcmp_vt", FIELD_fld_ae_sem_hpcmp_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcnv_vs", FIELD_fld_ae_sem_hpcnv_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vr", FIELD_fld_ae_sem_hpfma_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vs", FIELD_fld_ae_sem_hpfma_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vt", FIELD_fld_ae_sem_hpfma_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vp", FIELD_fld_ae_sem_hpfma_vp, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vu", FIELD_fld_ae_sem_hpfma_vu, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vq", FIELD_fld_ae_sem_hpfma_vq, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_c0", FIELD_fld_ae_sem_mul_nn_c0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_c1", FIELD_fld_ae_sem_mul_nn_c1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_c2", FIELD_fld_ae_sem_mul_nn_c2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_c3", FIELD_fld_ae_sem_mul_nn_c3, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_q0", FIELD_fld_ae_sem_mul_nn_q0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_q1", FIELD_fld_ae_sem_mul_nn_q1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_v0", FIELD_fld_ae_sem_mul_nn_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_v1", FIELD_fld_ae_sem_mul_nn_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_q2", FIELD_fld_ae_sem_mul_nn_q2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_q3", FIELD_fld_ae_sem_mul_nn_q3, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_v2", FIELD_fld_ae_sem_mul_nn_v2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_v3", FIELD_fld_ae_sem_mul_nn_v3, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "bbi", FIELD_bbi, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "sae", FIELD_sae, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "sas", FIELD_sas, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "sargt", FIELD_sargt, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "s", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, + 0, 0, + -1, 0 }, + { "bitindex", FIELD_bitindex, -1, 0, + 0, + OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode, + 0, 0, + -1, 0 }, + { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 }, + { "imms8", FIELD_imms8, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, + { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, + { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, + { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, + { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, + { "r_disp", FIELD_r_disp, -1, 0, 0, 0, 0, 0, 0 }, + { "r_3", FIELD_r_3, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, + { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, + { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, + { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, + { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 }, + { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 }, + { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 }, + { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 }, + { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 }, + { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 }, + { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 }, + { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wloop_imm", FIELD_xt_wloop_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_Inst16b_12", FIELD_ae_fld_Inst16b_12, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_Inst16b_15_13", FIELD_ae_fld_Inst16b_15_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_art", FIELD_fld_ae_sem_arithmetic_art, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_ds", FIELD_fld_ae_sem_arithmetic_ds, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_v", FIELD_fld_ae_sem_arithmetic_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_v0", FIELD_fld_ae_sem_arithmetic_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_v1", FIELD_fld_ae_sem_arithmetic_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_va", FIELD_fld_ae_sem_arithmetic_va, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_vs", FIELD_fld_ae_sem_arithmetic_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_a", FIELD_fld_ae_sem_dr_to_ar_a, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_ab", FIELD_fld_ae_sem_dr_to_ar_ab, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_ai", FIELD_fld_ae_sem_dr_to_ar_ai, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_aoe", FIELD_fld_ae_sem_dr_to_ar_aoe, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_d", FIELD_fld_ae_sem_dr_to_ar_d, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_d0", FIELD_fld_ae_sem_dr_to_ar_d0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_d1", FIELD_fld_ae_sem_dr_to_ar_d1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_imm8", FIELD_fld_ae_sem_dr_to_ar_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_v0", FIELD_fld_ae_sem_dr_to_ar_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_vr", FIELD_fld_ae_sem_dr_to_ar_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_arr", FIELD_fld_ae_sem_dr_to_dr_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_bt", FIELD_fld_ae_sem_dr_to_dr_bt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_ds", FIELD_fld_ae_sem_dr_to_dr_ds, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_imm2", FIELD_fld_ae_sem_dr_to_dr_imm2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_immed", FIELD_fld_ae_sem_dr_to_dr_immed, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_movi_imm", FIELD_fld_ae_sem_dr_to_dr_movi_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_v", FIELD_fld_ae_sem_dr_to_dr_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_v0", FIELD_fld_ae_sem_dr_to_dr_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_v1", FIELD_fld_ae_sem_dr_to_dr_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcmp_br4t", FIELD_fld_ae_sem_hpcmp_br4t, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcmp_vr", FIELD_fld_ae_sem_hpcmp_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcmp_vs", FIELD_fld_ae_sem_hpcmp_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_arr", FIELD_fld_ae_sem_hpcnv_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_art", FIELD_fld_ae_sem_hpcnv_art, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_i_imm4", FIELD_fld_ae_sem_hpcnv_i_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_vr", FIELD_fld_ae_sem_hpcnv_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_vt", FIELD_fld_ae_sem_hpcnv_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hprminmaxnum_vr", FIELD_fld_ae_sem_hprminmaxnum_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hprminmaxnum_vt", FIELD_fld_ae_sem_hprminmaxnum_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_lb_ops_iba", FIELD_fld_ae_sem_lb_ops_iba, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_a", FIELD_fld_ae_sem_loads_stores_a, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_a.0", FIELD_fld_ae_sem_loads_stores_a_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_av", FIELD_fld_ae_sem_loads_stores_av, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_av1", FIELD_fld_ae_sem_loads_stores_av1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_end", FIELD_fld_ae_sem_loads_stores_end, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i128", FIELD_fld_ae_sem_loads_stores_i128, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i16", FIELD_fld_ae_sem_loads_stores_i16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i3", FIELD_fld_ae_sem_loads_stores_i3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i32", FIELD_fld_ae_sem_loads_stores_i32, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i32pos", FIELD_fld_ae_sem_loads_stores_i32pos, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i64", FIELD_fld_ae_sem_loads_stores_i64, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i64half", FIELD_fld_ae_sem_loads_stores_i64half, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i64neg", FIELD_fld_ae_sem_loads_stores_i64neg, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i64pos", FIELD_fld_ae_sem_loads_stores_i64pos, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i64x2", FIELD_fld_ae_sem_loads_stores_i64x2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i8", FIELD_fld_ae_sem_loads_stores_i8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_imm2", FIELD_fld_ae_sem_loads_stores_imm2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_su", FIELD_fld_ae_sem_loads_stores_su, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_uu", FIELD_fld_ae_sem_loads_stores_uu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_v", FIELD_fld_ae_sem_loads_stores_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_v1", FIELD_fld_ae_sem_loads_stores_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_vu", FIELD_fld_ae_sem_loads_stores_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_x", FIELD_fld_ae_sem_loads_stores_x, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_pks_d", FIELD_fld_ae_sem_pks_d, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_pks_pos", FIELD_fld_ae_sem_pks_pos, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_pks_s", FIELD_fld_ae_sem_pks_s, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_v0", FIELD_fld_ae_sem_rng_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_v1", FIELD_fld_ae_sem_rng_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sb_loads_stores_iba", FIELD_fld_ae_sem_sb_loads_stores_iba, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_a", FIELD_fld_ae_sem_shift_a, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_a0", FIELD_fld_ae_sem_shift_a0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_d", FIELD_fld_ae_sem_shift_d, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_d0", FIELD_fld_ae_sem_shift_d0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_d1", FIELD_fld_ae_sem_shift_d1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_da", FIELD_fld_ae_sem_shift_da, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_i16", FIELD_fld_ae_sem_shift_i16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_i32", FIELD_fld_ae_sem_shift_i32, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_i64", FIELD_fld_ae_sem_shift_i64, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_imm32", FIELD_fld_ae_sem_shift_imm32, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_imm8", FIELD_fld_ae_sem_shift_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_sd", FIELD_fld_ae_sem_shift_sd, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sp32cvt_arr", FIELD_fld_ae_sem_sp32cvt_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sp32cvt_art", FIELD_fld_ae_sem_sp32cvt_art, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sp32cvt_i_imm5", FIELD_fld_ae_sem_sp32cvt_i_imm5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sp32cvt_vr", FIELD_fld_ae_sem_sp32cvt_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sp32cvt_vt", FIELD_fld_ae_sem_sp32cvt_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_brt", FIELD_fld_ae_sem_spmisc_brt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_vr", FIELD_fld_ae_sem_spmisc_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_vs", FIELD_fld_ae_sem_spmisc_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_10", FIELD_fld_ae_slot0_11_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_11", FIELD_fld_ae_slot0_11_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_8", FIELD_fld_ae_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_9", FIELD_fld_ae_slot0_11_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_0", FIELD_fld_ae_slot0_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_10", FIELD_fld_ae_slot0_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_12", FIELD_fld_ae_slot0_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_2", FIELD_fld_ae_slot0_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_6", FIELD_fld_ae_slot0_12_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_8", FIELD_fld_ae_slot0_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_9", FIELD_fld_ae_slot0_12_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_14_12", FIELD_fld_ae_slot0_14_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_14_13", FIELD_fld_ae_slot0_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_10", FIELD_fld_ae_slot0_17_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_12", FIELD_fld_ae_slot0_17_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_13", FIELD_fld_ae_slot0_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_14", FIELD_fld_ae_slot0_17_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_15", FIELD_fld_ae_slot0_17_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_16", FIELD_fld_ae_slot0_17_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_17", FIELD_fld_ae_slot0_17_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_8", FIELD_fld_ae_slot0_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_18_13", FIELD_fld_ae_slot0_18_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_18_15", FIELD_fld_ae_slot0_18_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_18_16", FIELD_fld_ae_slot0_18_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_18_8", FIELD_fld_ae_slot0_18_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_19_12", FIELD_fld_ae_slot0_19_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_19_15", FIELD_fld_ae_slot0_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_19_19", FIELD_fld_ae_slot0_19_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_19_8", FIELD_fld_ae_slot0_19_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_1_0", FIELD_fld_ae_slot0_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_1_1", FIELD_fld_ae_slot0_1_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_16", FIELD_fld_ae_slot0_20_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_20", FIELD_fld_ae_slot0_20_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_23_15", FIELD_fld_ae_slot0_23_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_23_17", FIELD_fld_ae_slot0_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_23_19", FIELD_fld_ae_slot0_23_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_23_22", FIELD_fld_ae_slot0_23_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_10", FIELD_fld_ae_slot0_28_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_12", FIELD_fld_ae_slot0_28_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_14", FIELD_fld_ae_slot0_28_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_15", FIELD_fld_ae_slot0_28_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_16", FIELD_fld_ae_slot0_28_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_17", FIELD_fld_ae_slot0_28_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_19", FIELD_fld_ae_slot0_28_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_21", FIELD_fld_ae_slot0_28_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_22", FIELD_fld_ae_slot0_28_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_24", FIELD_fld_ae_slot0_28_24, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_26", FIELD_fld_ae_slot0_28_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_27", FIELD_fld_ae_slot0_28_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_4", FIELD_fld_ae_slot0_28_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_8", FIELD_fld_ae_slot0_28_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_3_0", FIELD_fld_ae_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_3_1", FIELD_fld_ae_slot0_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_3_2", FIELD_fld_ae_slot0_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_3_3", FIELD_fld_ae_slot0_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_4_0", FIELD_fld_ae_slot0_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_4_4", FIELD_fld_ae_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_5_0", FIELD_fld_ae_slot0_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_5_4", FIELD_fld_ae_slot0_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_0", FIELD_fld_ae_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_2", FIELD_fld_ae_slot0_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_3", FIELD_fld_ae_slot0_7_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_4", FIELD_fld_ae_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_8_8", FIELD_fld_ae_slot0_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_9_4", FIELD_fld_ae_slot0_9_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_9_8", FIELD_fld_ae_slot0_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_9_9", FIELD_fld_ae_slot0_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_0_0", FIELD_fld_ae_slot1_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_12_8", FIELD_fld_ae_slot1_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_17_13", FIELD_fld_ae_slot1_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_17_17", FIELD_fld_ae_slot1_17_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_17_8", FIELD_fld_ae_slot1_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_1", FIELD_fld_ae_slot1_25_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_12", FIELD_fld_ae_slot1_25_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_13", FIELD_fld_ae_slot1_25_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_16", FIELD_fld_ae_slot1_25_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_17", FIELD_fld_ae_slot1_25_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_18", FIELD_fld_ae_slot1_25_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_20", FIELD_fld_ae_slot1_25_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_22", FIELD_fld_ae_slot1_25_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_23", FIELD_fld_ae_slot1_25_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_8", FIELD_fld_ae_slot1_25_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_9", FIELD_fld_ae_slot1_25_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_3_0", FIELD_fld_ae_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_3_2", FIELD_fld_ae_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_3_3", FIELD_fld_ae_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_7_4", FIELD_fld_ae_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_e", FIELD_fld_ae_sem_arithmetic_e, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_ep", FIELD_fld_ae_sem_arithmetic_ep, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_ep1", FIELD_fld_ae_sem_arithmetic_ep1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_ei", FIELD_fld_ae_sem_dr_to_ar_ei, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_eo", FIELD_fld_ae_sem_dr_to_ar_eo, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_immed.N", FIELD_fld_ae_sem_dr_to_dr_immed_N, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_fpmov_i_imm4", FIELD_fld_ae_sem_fpmov_i_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_fpmov_vr", FIELD_fld_ae_sem_fpmov_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_fpmov_vs", FIELD_fld_ae_sem_fpmov_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_fpmov_vt", FIELD_fld_ae_sem_fpmov_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_fpmov_vu", FIELD_fld_ae_sem_fpmov_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcmp_vt", FIELD_fld_ae_sem_hpcmp_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_vs", FIELD_fld_ae_sem_hpcnv_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vr", FIELD_fld_ae_sem_hpfma_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vs", FIELD_fld_ae_sem_hpfma_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vt", FIELD_fld_ae_sem_hpfma_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_movfpstate_v", FIELD_fld_ae_sem_movfpstate_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_acc_ep", FIELD_fld_ae_sem_multiply_acc_ep, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_d0", FIELD_fld_ae_sem_multiply_d0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_d2", FIELD_fld_ae_sem_multiply_d2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_q0", FIELD_fld_ae_sem_multiply_q0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_q1", FIELD_fld_ae_sem_multiply_q1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_reduction_sort_ds", FIELD_fld_ae_sem_reduction_sort_ds, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_reduction_sort_v", FIELD_fld_ae_sem_reduction_sort_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_reduction_sort_v0", FIELD_fld_ae_sem_reduction_sort_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_isel", FIELD_fld_ae_sem_select_isel, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_ss", FIELD_fld_ae_sem_select_ss, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_vr", FIELD_fld_ae_sem_select_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_vs", FIELD_fld_ae_sem_select_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_vt", FIELD_fld_ae_sem_select_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_vu", FIELD_fld_ae_sem_select_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vr", FIELD_fld_ae_sem_spaddsub_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vs", FIELD_fld_ae_sem_spaddsub_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vt", FIELD_fld_ae_sem_spaddsub_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vu", FIELD_fld_ae_sem_spaddsub_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_i_imm1", FIELD_fld_ae_sem_spfma_i_imm1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_i_imm3", FIELD_fld_ae_sem_spfma_i_imm3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vp", FIELD_fld_ae_sem_spfma_vp, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vr", FIELD_fld_ae_sem_spfma_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vs", FIELD_fld_ae_sem_spfma_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vt", FIELD_fld_ae_sem_spfma_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_vsM", FIELD_fld_ae_sem_spmisc_vsM, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_vt", FIELD_fld_ae_sem_spmisc_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_vtM", FIELD_fld_ae_sem_spmisc_vtM, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_14_0", FIELD_fld_ae_slot2_14_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_14_10", FIELD_fld_ae_slot2_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_14_14", FIELD_fld_ae_slot2_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_14_5", FIELD_fld_ae_slot2_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_16_15", FIELD_fld_ae_slot2_16_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_19_15", FIELD_fld_ae_slot2_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_15", FIELD_fld_ae_slot2_28_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_17", FIELD_fld_ae_slot2_28_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_19", FIELD_fld_ae_slot2_28_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_20", FIELD_fld_ae_slot2_28_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_25", FIELD_fld_ae_slot2_28_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_4", FIELD_fld_ae_slot2_28_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_5", FIELD_fld_ae_slot2_28_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_3_0", FIELD_fld_ae_slot2_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_0", FIELD_fld_ae_slot2_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_1", FIELD_fld_ae_slot2_9_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_2", FIELD_fld_ae_slot2_9_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_5", FIELD_fld_ae_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_6", FIELD_fld_ae_slot2_9_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_7", FIELD_fld_ae_slot2_9_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_8", FIELD_fld_ae_slot2_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_imm", FIELD_fld_ae_sem_dr_to_dr_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_d1", FIELD_fld_ae_sem_multiply_d1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_d3", FIELD_fld_ae_sem_multiply_d3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_d", FIELD_fld_ae_sem_rng_d, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_e", FIELD_fld_ae_sem_shift_e, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_i8", FIELD_fld_ae_sem_shift_i8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_11_0", FIELD_fld_ae_slot3_11_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_14_0", FIELD_fld_ae_slot3_14_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_14_10", FIELD_fld_ae_slot3_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_14_12", FIELD_fld_ae_slot3_14_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_14_13", FIELD_fld_ae_slot3_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_16_13", FIELD_fld_ae_slot3_16_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_0", FIELD_fld_ae_slot3_19_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_10", FIELD_fld_ae_slot3_19_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_15", FIELD_fld_ae_slot3_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_17", FIELD_fld_ae_slot3_19_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_18", FIELD_fld_ae_slot3_19_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_19", FIELD_fld_ae_slot3_19_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_24_10", FIELD_fld_ae_slot3_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_24_19", FIELD_fld_ae_slot3_24_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_24_20", FIELD_fld_ae_slot3_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_12", FIELD_fld_ae_slot3_36_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_16", FIELD_fld_ae_slot3_36_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_19", FIELD_fld_ae_slot3_36_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_20", FIELD_fld_ae_slot3_36_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_22", FIELD_fld_ae_slot3_36_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_25", FIELD_fld_ae_slot3_36_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_30", FIELD_fld_ae_slot3_36_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_4_0", FIELD_fld_ae_slot3_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_9_0", FIELD_fld_ae_slot3_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_9_1", FIELD_fld_ae_slot3_9_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_9_3", FIELD_fld_ae_slot3_9_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_9_5", FIELD_fld_ae_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_0_0", FIELD_fld_ae2_slot0_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_11_4", FIELD_fld_ae2_slot0_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_11_8", FIELD_fld_ae2_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_11_9", FIELD_fld_ae2_slot0_11_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_12_0", FIELD_fld_ae2_slot0_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_12_2", FIELD_fld_ae2_slot0_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_12_4", FIELD_fld_ae2_slot0_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_12_8", FIELD_fld_ae2_slot0_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_14_13", FIELD_fld_ae2_slot0_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_14_8", FIELD_fld_ae2_slot0_14_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_0", FIELD_fld_ae2_slot0_15_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_12", FIELD_fld_ae2_slot0_15_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_13", FIELD_fld_ae2_slot0_15_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_15", FIELD_fld_ae2_slot0_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_4", FIELD_fld_ae2_slot0_15_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_8", FIELD_fld_ae2_slot0_15_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_17_13", FIELD_fld_ae2_slot0_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_17_17", FIELD_fld_ae2_slot0_17_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_18_15", FIELD_fld_ae2_slot0_18_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_18_17", FIELD_fld_ae2_slot0_18_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_18_18", FIELD_fld_ae2_slot0_18_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_1_0", FIELD_fld_ae2_slot0_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_23_18", FIELD_fld_ae2_slot0_23_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_23_19", FIELD_fld_ae2_slot0_23_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_3_0", FIELD_fld_ae2_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_16", FIELD_fld_ae2_slot0_40_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_17", FIELD_fld_ae2_slot0_40_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_18", FIELD_fld_ae2_slot0_40_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_19", FIELD_fld_ae2_slot0_40_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_21", FIELD_fld_ae2_slot0_40_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_23", FIELD_fld_ae2_slot0_40_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_24", FIELD_fld_ae2_slot0_40_24, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_25", FIELD_fld_ae2_slot0_40_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_26", FIELD_fld_ae2_slot0_40_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_27", FIELD_fld_ae2_slot0_40_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_0", FIELD_fld_ae2_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_4", FIELD_fld_ae2_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_6", FIELD_fld_ae2_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_7", FIELD_fld_ae2_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_8_8", FIELD_fld_ae2_slot0_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_9_8", FIELD_fld_ae2_slot0_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_0_0", FIELD_fld_ae2_slot1_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_11_0", FIELD_fld_ae2_slot1_11_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_11_10", FIELD_fld_ae2_slot1_11_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_11_8", FIELD_fld_ae2_slot1_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_14_10", FIELD_fld_ae2_slot1_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_14_11", FIELD_fld_ae2_slot1_14_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_14_12", FIELD_fld_ae2_slot1_14_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_14_14", FIELD_fld_ae2_slot1_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_14_8", FIELD_fld_ae2_slot1_14_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_12", FIELD_fld_ae2_slot1_36_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_14", FIELD_fld_ae2_slot1_36_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_15", FIELD_fld_ae2_slot1_36_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_16", FIELD_fld_ae2_slot1_36_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_17", FIELD_fld_ae2_slot1_36_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_18", FIELD_fld_ae2_slot1_36_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_20", FIELD_fld_ae2_slot1_36_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_22", FIELD_fld_ae2_slot1_36_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_23", FIELD_fld_ae2_slot1_36_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_3_0", FIELD_fld_ae2_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_3_1", FIELD_fld_ae2_slot1_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_3_2", FIELD_fld_ae2_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_3_3", FIELD_fld_ae2_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_7_4", FIELD_fld_ae2_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_9_8", FIELD_fld_ae2_slot1_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_9_9", FIELD_fld_ae2_slot1_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_14_10", FIELD_fld_ae2_slot2_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_17_0", FIELD_fld_ae2_slot2_17_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_17_10", FIELD_fld_ae2_slot2_17_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_17_15", FIELD_fld_ae2_slot2_17_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_17_17", FIELD_fld_ae2_slot2_17_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_19_10", FIELD_fld_ae2_slot2_19_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_19_15", FIELD_fld_ae2_slot2_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_19_18", FIELD_fld_ae2_slot2_19_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_19_9", FIELD_fld_ae2_slot2_19_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_10", FIELD_fld_ae2_slot2_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_15", FIELD_fld_ae2_slot2_24_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_20", FIELD_fld_ae2_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_5", FIELD_fld_ae2_slot2_24_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_9", FIELD_fld_ae2_slot2_24_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_18", FIELD_fld_ae2_slot2_42_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_20", FIELD_fld_ae2_slot2_42_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_25", FIELD_fld_ae2_slot2_42_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_26", FIELD_fld_ae2_slot2_42_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_28", FIELD_fld_ae2_slot2_42_28, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_30", FIELD_fld_ae2_slot2_42_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_4_0", FIELD_fld_ae2_slot2_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_9_5", FIELD_fld_ae2_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vp", FIELD_fld_ae_sem_spaddsub_vp, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vq", FIELD_fld_ae_sem_spaddsub_vq, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_11_11", FIELD_fld_ae3_slot0_11_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_11_4", FIELD_fld_ae3_slot0_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_11_8", FIELD_fld_ae3_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_12_12", FIELD_fld_ae3_slot0_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_12_8", FIELD_fld_ae3_slot0_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_13_13", FIELD_fld_ae3_slot0_13_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_13_8", FIELD_fld_ae3_slot0_13_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_1_0", FIELD_fld_ae3_slot0_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_11", FIELD_fld_ae3_slot0_32_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_12", FIELD_fld_ae3_slot0_32_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_13", FIELD_fld_ae3_slot0_32_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_14", FIELD_fld_ae3_slot0_32_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_15", FIELD_fld_ae3_slot0_32_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_16", FIELD_fld_ae3_slot0_32_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_17", FIELD_fld_ae3_slot0_32_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_18", FIELD_fld_ae3_slot0_32_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_20", FIELD_fld_ae3_slot0_32_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_27", FIELD_fld_ae3_slot0_32_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_8", FIELD_fld_ae3_slot0_32_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_3_0", FIELD_fld_ae3_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_3_2", FIELD_fld_ae3_slot0_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_3_3", FIELD_fld_ae3_slot0_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_4_0", FIELD_fld_ae3_slot0_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_4_4", FIELD_fld_ae3_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_5_0", FIELD_fld_ae3_slot0_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_5_4", FIELD_fld_ae3_slot0_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_7_0", FIELD_fld_ae3_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_7_2", FIELD_fld_ae3_slot0_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_7_4", FIELD_fld_ae3_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_7_6", FIELD_fld_ae3_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_8_8", FIELD_fld_ae3_slot0_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_9_4", FIELD_fld_ae3_slot0_9_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_9_8", FIELD_fld_ae3_slot0_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_ar_s", FIELD_fld_ae_sem_dr_to_ar_ar_s, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sb_loads_stores_iba2", FIELD_fld_ae_sem_sb_loads_stores_iba2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_0", FIELD_fld_ae3_slot1_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_11", FIELD_fld_ae3_slot1_23_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_12", FIELD_fld_ae3_slot1_23_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_13", FIELD_fld_ae3_slot1_23_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_15", FIELD_fld_ae3_slot1_23_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_16", FIELD_fld_ae3_slot1_23_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_17", FIELD_fld_ae3_slot1_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_19", FIELD_fld_ae3_slot1_23_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_6", FIELD_fld_ae3_slot1_23_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_8", FIELD_fld_ae3_slot1_23_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_9", FIELD_fld_ae3_slot1_23_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_3_0", FIELD_fld_ae3_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_3_1", FIELD_fld_ae3_slot1_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_3_2", FIELD_fld_ae3_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_3_3", FIELD_fld_ae3_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_7_4", FIELD_fld_ae3_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_9_8", FIELD_fld_ae3_slot1_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_AE_ARDECNORM16_ar_u", FIELD_fld_AE_ARDECNORM16_ar_u, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_11_10", FIELD_fld_ae5_slot0_11_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_11_4", FIELD_fld_ae5_slot0_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_11_8", FIELD_fld_ae5_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_11_9", FIELD_fld_ae5_slot0_11_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_12_10", FIELD_fld_ae5_slot0_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_12_4", FIELD_fld_ae5_slot0_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_12_6", FIELD_fld_ae5_slot0_12_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_12_8", FIELD_fld_ae5_slot0_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_12_9", FIELD_fld_ae5_slot0_12_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_1_0", FIELD_fld_ae5_slot0_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_1_1", FIELD_fld_ae5_slot0_1_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_12", FIELD_fld_ae5_slot0_29_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_13", FIELD_fld_ae5_slot0_29_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_15", FIELD_fld_ae5_slot0_29_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_16", FIELD_fld_ae5_slot0_29_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_17", FIELD_fld_ae5_slot0_29_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_18", FIELD_fld_ae5_slot0_29_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_19", FIELD_fld_ae5_slot0_29_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_20", FIELD_fld_ae5_slot0_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_27", FIELD_fld_ae5_slot0_29_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_5", FIELD_fld_ae5_slot0_29_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_6", FIELD_fld_ae5_slot0_29_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_8", FIELD_fld_ae5_slot0_29_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_2_0", FIELD_fld_ae5_slot0_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_3_0", FIELD_fld_ae5_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_3_2", FIELD_fld_ae5_slot0_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_4_0", FIELD_fld_ae5_slot0_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_4_4", FIELD_fld_ae5_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_7_0", FIELD_fld_ae5_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_7_4", FIELD_fld_ae5_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_7_7", FIELD_fld_ae5_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_8_8", FIELD_fld_ae5_slot0_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_lb_db_ops_ar_u", FIELD_fld_ae_sem_lb_db_ops_ar_u, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_lb_db_ops_iba", FIELD_fld_ae_sem_lb_db_ops_iba, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_a", FIELD_fld_ae_sem_rng_a, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_art", FIELD_fld_ae_sem_rng_art, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_i2", FIELD_fld_ae_sem_rng_i2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_imm2", FIELD_fld_ae_sem_rng_imm2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot1_1_0", FIELD_fld_ae5_slot1_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_14_10", FIELD_fld_ae5_slot2_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_14_14", FIELD_fld_ae5_slot2_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_14_5", FIELD_fld_ae5_slot2_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_24_0", FIELD_fld_ae5_slot2_24_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_24_15", FIELD_fld_ae5_slot2_24_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_24_17", FIELD_fld_ae5_slot2_24_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_24_20", FIELD_fld_ae5_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_4_0", FIELD_fld_ae5_slot2_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_9_0", FIELD_fld_ae5_slot2_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_9_5", FIELD_fld_ae5_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_9_7", FIELD_fld_ae5_slot2_9_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_10_10", FIELD_fld_ae6_slot0_10_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_15_15", FIELD_fld_ae6_slot0_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_10", FIELD_fld_ae6_slot0_29_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_13", FIELD_fld_ae6_slot0_29_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_14", FIELD_fld_ae6_slot0_29_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_15", FIELD_fld_ae6_slot0_29_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_18", FIELD_fld_ae6_slot0_29_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_20", FIELD_fld_ae6_slot0_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_5", FIELD_fld_ae6_slot0_29_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_4_0", FIELD_fld_ae6_slot0_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_4_4", FIELD_fld_ae6_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_7_4", FIELD_fld_ae6_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_7_7", FIELD_fld_ae6_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_9_8", FIELD_fld_ae6_slot0_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_9_9", FIELD_fld_ae6_slot0_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_14_14", FIELD_fld_ae6_slot1_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_12", FIELD_fld_ae6_slot1_27_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_15", FIELD_fld_ae6_slot1_27_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_20", FIELD_fld_ae6_slot1_27_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_21", FIELD_fld_ae6_slot1_27_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_3", FIELD_fld_ae6_slot1_27_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_6", FIELD_fld_ae6_slot1_27_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_2_0", FIELD_fld_ae6_slot1_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_9_5", FIELD_fld_ae6_slot1_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_9_6", FIELD_fld_ae6_slot1_9_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_9_7", FIELD_fld_ae6_slot1_9_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_9_8", FIELD_fld_ae6_slot1_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_9_9", FIELD_fld_ae6_slot1_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_10_10", FIELD_fld_ae6_slot2_10_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_11_10", FIELD_fld_ae6_slot2_11_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_24_0", FIELD_fld_ae6_slot2_24_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_24_10", FIELD_fld_ae6_slot2_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_24_14", FIELD_fld_ae6_slot2_24_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_24_15", FIELD_fld_ae6_slot2_24_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_24_20", FIELD_fld_ae6_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_4_2", FIELD_fld_ae6_slot2_4_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_9_5", FIELD_fld_ae6_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_10_10", FIELD_fld_ae6_slot3_10_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_12_0", FIELD_fld_ae6_slot3_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_14_0", FIELD_fld_ae6_slot3_14_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_14_10", FIELD_fld_ae6_slot3_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_14_13", FIELD_fld_ae6_slot3_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_14_5", FIELD_fld_ae6_slot3_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_24_20", FIELD_fld_ae6_slot3_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_37_13", FIELD_fld_ae6_slot3_37_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_37_15", FIELD_fld_ae6_slot3_37_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_37_20", FIELD_fld_ae6_slot3_37_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_37_30", FIELD_fld_ae6_slot3_37_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_9_5", FIELD_fld_ae6_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_12_6", FIELD_fld_ae7_slot0_12_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_23_0", FIELD_fld_ae7_slot0_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_23_13", FIELD_fld_ae7_slot0_23_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_23_17", FIELD_fld_ae7_slot0_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_23_18", FIELD_fld_ae7_slot0_23_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_23_6", FIELD_fld_ae7_slot0_23_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_7_4", FIELD_fld_ae7_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_7_6", FIELD_fld_ae7_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_7_7", FIELD_fld_ae7_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_12_6", FIELD_fld_ae7_slot1_12_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_23_0", FIELD_fld_ae7_slot1_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_23_13", FIELD_fld_ae7_slot1_23_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_23_17", FIELD_fld_ae7_slot1_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_23_18", FIELD_fld_ae7_slot1_23_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_23_6", FIELD_fld_ae7_slot1_23_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_7_4", FIELD_fld_ae7_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_7_6", FIELD_fld_ae7_slot1_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_7_7", FIELD_fld_ae7_slot1_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_11_0", FIELD_fld_ae7_slot2_11_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_14_10", FIELD_fld_ae7_slot2_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_14_5", FIELD_fld_ae7_slot2_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_36_12", FIELD_fld_ae7_slot2_36_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_36_15", FIELD_fld_ae7_slot2_36_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_36_20", FIELD_fld_ae7_slot2_36_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_36_25", FIELD_fld_ae7_slot2_36_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_36_30", FIELD_fld_ae7_slot2_36_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_9_5", FIELD_fld_ae7_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_10_0", FIELD_fld_ae7_slot3_10_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_14_10", FIELD_fld_ae7_slot3_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_14_5", FIELD_fld_ae7_slot3_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_24_10", FIELD_fld_ae7_slot3_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_35_11", FIELD_fld_ae7_slot3_35_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_35_20", FIELD_fld_ae7_slot3_35_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_35_25", FIELD_fld_ae7_slot3_35_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_35_30", FIELD_fld_ae7_slot3_35_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_4_0", FIELD_fld_ae7_slot3_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_9_5", FIELD_fld_ae7_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_13_12", FIELD_fld_ae8_slot0_13_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_13_13", FIELD_fld_ae8_slot0_13_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_13_4", FIELD_fld_ae8_slot0_13_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_13_9", FIELD_fld_ae8_slot0_13_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_17_4", FIELD_fld_ae8_slot0_17_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_17_8", FIELD_fld_ae8_slot0_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_12", FIELD_fld_ae8_slot0_31_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_15", FIELD_fld_ae8_slot0_31_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_18", FIELD_fld_ae8_slot0_31_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_19", FIELD_fld_ae8_slot0_31_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_20", FIELD_fld_ae8_slot0_31_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_21", FIELD_fld_ae8_slot0_31_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_22", FIELD_fld_ae8_slot0_31_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_23", FIELD_fld_ae8_slot0_31_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_7", FIELD_fld_ae8_slot0_31_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_8", FIELD_fld_ae8_slot0_31_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_9", FIELD_fld_ae8_slot0_31_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_3_0", FIELD_fld_ae8_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_6_0", FIELD_fld_ae8_slot0_6_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_7_4", FIELD_fld_ae8_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_7_5", FIELD_fld_ae8_slot0_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_7_7", FIELD_fld_ae8_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_8_0", FIELD_fld_ae8_slot0_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_17_13", FIELD_fld_ae8_slot1_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_17_14", FIELD_fld_ae8_slot1_17_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_17_15", FIELD_fld_ae8_slot1_17_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_17_8", FIELD_fld_ae8_slot1_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_12", FIELD_fld_ae8_slot1_29_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_13", FIELD_fld_ae8_slot1_29_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_18", FIELD_fld_ae8_slot1_29_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_20", FIELD_fld_ae8_slot1_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_22", FIELD_fld_ae8_slot1_29_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_23", FIELD_fld_ae8_slot1_29_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_5", FIELD_fld_ae8_slot1_29_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_8", FIELD_fld_ae8_slot1_29_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_9", FIELD_fld_ae8_slot1_29_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_3_0", FIELD_fld_ae8_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_3_3", FIELD_fld_ae8_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_4_0", FIELD_fld_ae8_slot1_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_7_4", FIELD_fld_ae8_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_19_10", FIELD_fld_ae8_slot2_19_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_19_15", FIELD_fld_ae8_slot2_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_33_15", FIELD_fld_ae8_slot2_33_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_33_25", FIELD_fld_ae8_slot2_33_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_33_9", FIELD_fld_ae8_slot2_33_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_34_30", FIELD_fld_ae8_slot2_34_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_39_35", FIELD_fld_ae8_slot2_39_35, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_44_35", FIELD_fld_ae8_slot2_44_35, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_58_34", FIELD_fld_ae8_slot2_58_34, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_58_35", FIELD_fld_ae8_slot2_58_35, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_58_40", FIELD_fld_ae8_slot2_58_40, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_58_50", FIELD_fld_ae8_slot2_58_50, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_8_0", FIELD_fld_ae8_slot2_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_9_0", FIELD_fld_ae8_slot2_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_c0", FIELD_fld_ae_sem_mul_nn_c0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_c1", FIELD_fld_ae_sem_mul_nn_c1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_c2", FIELD_fld_ae_sem_mul_nn_c2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_c3", FIELD_fld_ae_sem_mul_nn_c3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_q0", FIELD_fld_ae_sem_mul_nn_q0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_q1", FIELD_fld_ae_sem_mul_nn_q1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_q2", FIELD_fld_ae_sem_mul_nn_q2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_q3", FIELD_fld_ae_sem_mul_nn_q3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_v0", FIELD_fld_ae_sem_mul_nn_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_v1", FIELD_fld_ae_sem_mul_nn_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_v2", FIELD_fld_ae_sem_mul_nn_v2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_v3", FIELD_fld_ae_sem_mul_nn_v3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_0_0", FIELD_fld_ae9_slot0_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_12_12", FIELD_fld_ae9_slot0_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_12_5", FIELD_fld_ae9_slot0_12_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_12_8", FIELD_fld_ae9_slot0_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_17_13", FIELD_fld_ae9_slot0_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_17_4", FIELD_fld_ae9_slot0_17_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_17_8", FIELD_fld_ae9_slot0_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_10", FIELD_fld_ae9_slot0_27_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_12", FIELD_fld_ae9_slot0_27_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_13", FIELD_fld_ae9_slot0_27_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_16", FIELD_fld_ae9_slot0_27_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_17", FIELD_fld_ae9_slot0_27_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_18", FIELD_fld_ae9_slot0_27_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_19", FIELD_fld_ae9_slot0_27_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_20", FIELD_fld_ae9_slot0_27_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_22", FIELD_fld_ae9_slot0_27_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_23", FIELD_fld_ae9_slot0_27_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_3", FIELD_fld_ae9_slot0_27_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_8", FIELD_fld_ae9_slot0_27_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_2_0", FIELD_fld_ae9_slot0_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_3_0", FIELD_fld_ae9_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_7_0", FIELD_fld_ae9_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_7_4", FIELD_fld_ae9_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_7_5", FIELD_fld_ae9_slot0_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_7_6", FIELD_fld_ae9_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_7_7", FIELD_fld_ae9_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_8_4", FIELD_fld_ae9_slot0_8_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_8_5", FIELD_fld_ae9_slot0_8_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_9_5", FIELD_fld_ae9_slot0_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_17_13", FIELD_fld_ae9_slot1_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_17_8", FIELD_fld_ae9_slot1_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_1_0", FIELD_fld_ae9_slot1_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_12", FIELD_fld_ae9_slot1_26_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_13", FIELD_fld_ae9_slot1_26_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_16", FIELD_fld_ae9_slot1_26_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_17", FIELD_fld_ae9_slot1_26_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_18", FIELD_fld_ae9_slot1_26_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_2", FIELD_fld_ae9_slot1_26_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_20", FIELD_fld_ae9_slot1_26_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_22", FIELD_fld_ae9_slot1_26_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_23", FIELD_fld_ae9_slot1_26_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_8", FIELD_fld_ae9_slot1_26_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_9", FIELD_fld_ae9_slot1_26_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_3_0", FIELD_fld_ae9_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_3_2", FIELD_fld_ae9_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_3_3", FIELD_fld_ae9_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_7_4", FIELD_fld_ae9_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_24_14", FIELD_fld_ae9_slot2_24_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_24_15", FIELD_fld_ae9_slot2_24_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_24_20", FIELD_fld_ae9_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_14", FIELD_fld_ae9_slot2_33_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_15", FIELD_fld_ae9_slot2_33_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_20", FIELD_fld_ae9_slot2_33_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_25", FIELD_fld_ae9_slot2_33_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_26", FIELD_fld_ae9_slot2_33_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_28", FIELD_fld_ae9_slot2_33_28, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_30", FIELD_fld_ae9_slot2_33_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_9", FIELD_fld_ae9_slot2_33_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_4_0", FIELD_fld_ae9_slot2_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_5_0", FIELD_fld_ae9_slot2_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_6_0", FIELD_fld_ae9_slot2_6_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_8_0", FIELD_fld_ae9_slot2_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_9_0", FIELD_fld_ae9_slot2_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_9_5", FIELD_fld_ae9_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_9_9", FIELD_fld_ae9_slot2_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vp", FIELD_fld_ae_sem_hpfma_vp, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vu", FIELD_fld_ae_sem_hpfma_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vu", FIELD_fld_ae_sem_spfma_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_19_15", FIELD_fld_ae9_slot3_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_24_20", FIELD_fld_ae9_slot3_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_14", FIELD_fld_ae9_slot3_31_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_15", FIELD_fld_ae9_slot3_31_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_20", FIELD_fld_ae9_slot3_31_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_25", FIELD_fld_ae9_slot3_31_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_26", FIELD_fld_ae9_slot3_31_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_28", FIELD_fld_ae9_slot3_31_28, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_7", FIELD_fld_ae9_slot3_31_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_4_0", FIELD_fld_ae9_slot3_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_4_3", FIELD_fld_ae9_slot3_4_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_4_4", FIELD_fld_ae9_slot3_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_6_0", FIELD_fld_ae9_slot3_6_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_9_0", FIELD_fld_ae9_slot3_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_9_5", FIELD_fld_ae9_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_17_13", FIELD_fld_ae10_slot0_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_17_4", FIELD_fld_ae10_slot0_17_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_17_8", FIELD_fld_ae10_slot0_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_0", FIELD_fld_ae10_slot0_24_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_10", FIELD_fld_ae10_slot0_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_12", FIELD_fld_ae10_slot0_24_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_13", FIELD_fld_ae10_slot0_24_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_16", FIELD_fld_ae10_slot0_24_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_17", FIELD_fld_ae10_slot0_24_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_18", FIELD_fld_ae10_slot0_24_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_20", FIELD_fld_ae10_slot0_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_8", FIELD_fld_ae10_slot0_24_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_3_0", FIELD_fld_ae10_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_7_4", FIELD_fld_ae10_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_7_6", FIELD_fld_ae10_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_7_7", FIELD_fld_ae10_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_8_4", FIELD_fld_ae10_slot0_8_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_0_0", FIELD_fld_ae10_slot1_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_17_13", FIELD_fld_ae10_slot1_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_17_8", FIELD_fld_ae10_slot1_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_1", FIELD_fld_ae10_slot1_25_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_12", FIELD_fld_ae10_slot1_25_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_13", FIELD_fld_ae10_slot1_25_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_16", FIELD_fld_ae10_slot1_25_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_17", FIELD_fld_ae10_slot1_25_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_18", FIELD_fld_ae10_slot1_25_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_20", FIELD_fld_ae10_slot1_25_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_22", FIELD_fld_ae10_slot1_25_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_23", FIELD_fld_ae10_slot1_25_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_8", FIELD_fld_ae10_slot1_25_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_9", FIELD_fld_ae10_slot1_25_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_3_0", FIELD_fld_ae10_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_3_2", FIELD_fld_ae10_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_3_3", FIELD_fld_ae10_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_7_4", FIELD_fld_ae10_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_24_20", FIELD_fld_ae10_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_29_20", FIELD_fld_ae10_slot2_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_29_25", FIELD_fld_ae10_slot2_29_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_10", FIELD_fld_ae10_slot2_34_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_14", FIELD_fld_ae10_slot2_34_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_15", FIELD_fld_ae10_slot2_34_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_20", FIELD_fld_ae10_slot2_34_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_25", FIELD_fld_ae10_slot2_34_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_30", FIELD_fld_ae10_slot2_34_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_31", FIELD_fld_ae10_slot2_34_31, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_33", FIELD_fld_ae10_slot2_34_33, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_4_0", FIELD_fld_ae10_slot2_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_9_0", FIELD_fld_ae10_slot2_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_9_5", FIELD_fld_ae10_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vq", FIELD_fld_ae_sem_hpfma_vq, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vq", FIELD_fld_ae_sem_spfma_vq, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_19_15", FIELD_fld_ae10_slot3_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_29_20", FIELD_fld_ae10_slot3_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_29_25", FIELD_fld_ae10_slot3_29_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_10", FIELD_fld_ae10_slot3_34_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_14", FIELD_fld_ae10_slot3_34_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_15", FIELD_fld_ae10_slot3_34_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_20", FIELD_fld_ae10_slot3_34_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_25", FIELD_fld_ae10_slot3_34_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_30", FIELD_fld_ae10_slot3_34_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_31", FIELD_fld_ae10_slot3_34_31, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_33", FIELD_fld_ae10_slot3_34_33, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_4_0", FIELD_fld_ae10_slot3_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_4_3", FIELD_fld_ae10_slot3_4_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_4_4", FIELD_fld_ae10_slot3_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_9_0", FIELD_fld_ae10_slot3_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_9_5", FIELD_fld_ae10_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_0", FIELD_fld_ae4_slot0_22_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_12", FIELD_fld_ae4_slot0_22_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_13", FIELD_fld_ae4_slot0_22_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_16", FIELD_fld_ae4_slot0_22_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_17", FIELD_fld_ae4_slot0_22_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_18", FIELD_fld_ae4_slot0_22_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_20", FIELD_fld_ae4_slot0_22_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_6", FIELD_fld_ae4_slot0_22_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_8", FIELD_fld_ae4_slot0_22_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_3_0", FIELD_fld_ae4_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_3_1", FIELD_fld_ae4_slot0_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_4_4", FIELD_fld_ae4_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_7_4", FIELD_fld_ae4_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_0", FIELD_fld_ae4_slot1_22_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_12", FIELD_fld_ae4_slot1_22_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_13", FIELD_fld_ae4_slot1_22_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_16", FIELD_fld_ae4_slot1_22_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_17", FIELD_fld_ae4_slot1_22_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_18", FIELD_fld_ae4_slot1_22_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_8", FIELD_fld_ae4_slot1_22_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_3_0", FIELD_fld_ae4_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_3_1", FIELD_fld_ae4_slot1_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_7_4", FIELD_fld_ae4_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_23_0", FIELD_fld_ae4_slot2_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_23_12", FIELD_fld_ae4_slot2_23_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_23_15", FIELD_fld_ae4_slot2_23_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_23_17", FIELD_fld_ae4_slot2_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_23_20", FIELD_fld_ae4_slot2_23_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_4_0", FIELD_fld_ae4_slot2_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_9_5", FIELD_fld_ae4_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_14_10", FIELD_fld_ae4_slot3_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_19_15", FIELD_fld_ae4_slot3_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_19_19", FIELD_fld_ae4_slot3_19_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_19_5", FIELD_fld_ae4_slot3_19_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_27_20", FIELD_fld_ae4_slot3_27_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_27_25", FIELD_fld_ae4_slot3_27_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_27_3", FIELD_fld_ae4_slot3_27_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_2_0", FIELD_fld_ae4_slot3_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_9_0", FIELD_fld_ae4_slot3_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_9_5", FIELD_fld_ae4_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot4_22_0", FIELD_fld_ae4_slot4_22_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot4_22_15", FIELD_fld_ae4_slot4_22_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot4_22_20", FIELD_fld_ae4_slot4_22_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot4_9_5", FIELD_fld_ae4_slot4_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_11_8", FIELD_fld_Inst_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_12_12", FIELD_fld_Inst_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_12_8", FIELD_fld_Inst_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_13_8", FIELD_fld_Inst_13_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_15_12", FIELD_fld_Inst_15_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_19_17", FIELD_fld_Inst_19_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_19_18", FIELD_fld_Inst_19_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_23_12", FIELD_fld_Inst_23_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_23_16", FIELD_fld_Inst_23_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_4_4", FIELD_fld_Inst_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_5_4", FIELD_fld_Inst_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_7_4", FIELD_fld_Inst_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_7_6", FIELD_fld_Inst_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_7_7", FIELD_fld_Inst_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_9_8", FIELD_fld_Inst_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 } +}; + +enum xtensa_operand_id { + OPERAND_soffsetx4, + OPERAND_immr, + OPERAND_uimm12x8, + OPERAND_simm4, + OPERAND_arr, + OPERAND_ars, + OPERAND__ars_invisible, + OPERAND_art, + OPERAND_ar0, + OPERAND_ar4, + OPERAND_ar8, + OPERAND_ar12, + OPERAND_ars_entry, + OPERAND_immrx4, + OPERAND_lsi4x4, + OPERAND_simm7, + OPERAND_uimm6, + OPERAND_ai4const, + OPERAND_b4const, + OPERAND_b4constu, + OPERAND_immt, + OPERAND_uimms8, + OPERAND_uimm8, + OPERAND_uimm8x2, + OPERAND_uimm8x4, + OPERAND_uimm4x16, + OPERAND_uimmrx4, + OPERAND_simm8, + OPERAND_simm8x256, + OPERAND_simm12b, + OPERAND_msalp32, + OPERAND_op2p1, + OPERAND_label8, + OPERAND_ulabel8, + OPERAND_label12, + OPERAND_soffset, + OPERAND_uimm16x4, + OPERAND_imms, + OPERAND_imms1, + OPERAND_bt, + OPERAND_bs, + OPERAND_br, + OPERAND_bt2, + OPERAND_bs2, + OPERAND_br2, + OPERAND_bt4, + OPERAND_bs4, + OPERAND_br4, + OPERAND_bt8, + OPERAND_bs8, + OPERAND_br8, + OPERAND_bt16, + OPERAND_bs16, + OPERAND_br16, + OPERAND_brall, + OPERAND_tp7, + OPERAND_xt_wbr15_label, + OPERAND_xt_wloop_label, + OPERAND_ae_uimm2x2, + OPERAND_opnd_ae_sem_dr_to_dr_v, + OPERAND_opnd_ae_sem_arithmetic_v, + OPERAND_opnd_ae_sem_arithmetic_v0, + OPERAND_opnd_ae_sem_arithmetic_v1, + OPERAND_opnd_ae_sem_loads_stores_a_0, + OPERAND_opnd_ae_sem_loads_stores_x, + OPERAND_opnd_ae_sem_loads_stores_end, + OPERAND_opnd_ae_sem_loads_stores_i64, + OPERAND_opnd_ae_sem_lb_ops_iba, + OPERAND_opnd_ae_sem_sb_loads_stores_iba, + OPERAND_opnd_ae_sem_pks_d, + OPERAND_opnd_ae_sem_pks_pos, + OPERAND_opnd_ae_sem_pks_s, + OPERAND_opnd_ae_sem_dr_to_ar_a, + OPERAND_opnd_ae_sem_dr_to_ar_v0, + OPERAND_opnd_ae_sem_dr_to_dr_v0, + OPERAND_opnd_ae_sem_dr_to_ar_ab, + OPERAND_opnd_ae_sem_dr_to_ar_ai, + OPERAND_opnd_ae_sem_dr_to_ar_aoe, + OPERAND_opnd_ae_sem_dr_to_dr_movi_imm, + OPERAND_opnd_ae_sem_dr_to_dr_ds, + OPERAND_opnd_ae_sem_dr_to_dr_v1, + OPERAND_opnd_ae_sem_dr_to_ar_imm8, + OPERAND_opnd_ae_sem_shift_a0, + OPERAND_opnd_ae_sem_shift_d, + OPERAND_opnd_ae_sem_shift_d0, + OPERAND_opnd_ae_sem_dr_to_ar_d, + OPERAND_opnd_ae_sem_dr_to_ar_d0, + OPERAND_opnd_ae_sem_dr_to_ar_d1, + OPERAND_opnd_ae_sem_dr_to_dr_imm2, + OPERAND_opnd_ae_sem_arithmetic_ds, + OPERAND_opnd_ae_sem_loads_stores_uu, + OPERAND_opnd_ae_sem_loads_stores_vu, + OPERAND_opnd_ae_sem_loads_stores_i32, + OPERAND_opnd_ae_sem_loads_stores_v, + OPERAND_opnd_ae_sem_loads_stores_i32pos, + OPERAND_opnd_ae_sem_loads_stores_i16, + OPERAND_opnd_ae_sem_loads_stores_i8, + OPERAND_opnd_ae_sem_loads_stores_i64pos, + OPERAND_opnd_ae_sem_loads_stores_i64neg, + OPERAND_opnd_ae_sem_loads_stores_i64half, + OPERAND_opnd_ae_sem_loads_stores_su, + OPERAND_opnd_ae_sem_loads_stores_v1, + OPERAND_opnd_ae_sem_loads_stores_av, + OPERAND_opnd_ae_sem_shift_i16, + OPERAND_opnd_ae_sem_shift_i32, + OPERAND_opnd_ae_sem_shift_d1, + OPERAND_opnd_ae_sem_shift_da, + OPERAND_opnd_ae_sem_shift_imm32, + OPERAND_opnd_ae_sem_shift_a, + OPERAND_opnd_ae_sem_shift_sd, + OPERAND_opnd_ae_sem_shift_i64, + OPERAND_opnd_ae_sem_shift_imm8, + OPERAND_opnd_ae_sem_dr_to_dr_immed, + OPERAND_opnd_ae_sem_arithmetic_art, + OPERAND_opnd_ae_sem_arithmetic_va, + OPERAND_opnd_ae_sem_arithmetic_vs, + OPERAND_opnd_ae_sem_loads_stores_i128, + OPERAND_opnd_ae_sem_loads_stores_i64x2, + OPERAND_opnd_ae_sem_loads_stores_av1, + OPERAND_opnd_ae_sem_loads_stores_imm2, + OPERAND_opnd_ae_sem_loads_stores_i3, + OPERAND_opnd_ae_sem_rng_v0, + OPERAND_opnd_ae_sem_rng_v1, + OPERAND_opnd_ae_sem_reduction_sort_v, + OPERAND_opnd_ae_sem_reduction_sort_v0, + OPERAND_opnd_ae_sem_reduction_sort_ds, + OPERAND_opnd_ae_sem_multiply_d0, + OPERAND_opnd_ae_sem_multiply_d2, + OPERAND_opnd_ae_sem_multiply_q0, + OPERAND_opnd_ae_sem_multiply_q1, + OPERAND_opnd_ae_sem_dr_to_dr_immed_N, + OPERAND_opnd_ae_sem_dr_to_ar_ei, + OPERAND_opnd_ae_sem_dr_to_ar_eo, + OPERAND_opnd_ae_sem_multiply_acc_ep, + OPERAND_opnd_ae_sem_arithmetic_e, + OPERAND_opnd_ae_sem_arithmetic_ep, + OPERAND_opnd_ae_sem_arithmetic_ep1, + OPERAND_opnd_ae_sem_select_ss, + OPERAND_opnd_ae_sem_select_vr, + OPERAND_opnd_ae_sem_select_vs, + OPERAND_opnd_ae_sem_select_vt, + OPERAND_opnd_ae_sem_select_vu, + OPERAND_opnd_ae_sem_select_isel, + OPERAND_opnd_ae_sem_shift_e, + OPERAND_opnd_ae_sem_shift_i8, + OPERAND_opnd_ae_sem_multiply_d1, + OPERAND_opnd_ae_sem_multiply_d3, + OPERAND_opnd_ae_sem_dr_to_dr_imm, + OPERAND_opnd_ae_sem_rng_d, + OPERAND_opnd_ae_sem_sb_loads_stores_iba2, + OPERAND_opnd_ae_sem_dr_to_ar_ar_s, + OPERAND_opnd_AE_ARDECNORM16_ar_u, + OPERAND_opnd_ae_sem_rng_a, + OPERAND_opnd_ae_sem_rng_art, + OPERAND_opnd_ae_sem_rng_i2, + OPERAND_opnd_ae_sem_rng_imm2, + OPERAND_opnd_ae_sem_lb_db_ops_ar_u, + OPERAND_opnd_ae_sem_lb_db_ops_iba, + OPERAND_opnd_ae_sem_dr_to_ar_vr, + OPERAND_opnd_ae_sem_spmisc_brt, + OPERAND_opnd_ae_sem_spmisc_vr, + OPERAND_opnd_ae_sem_spmisc_vs, + OPERAND_opnd_ae_sem_dr_to_dr_arr, + OPERAND_opnd_ae_sem_dr_to_dr_bt, + OPERAND_opnd_ae_sem_sp32cvt_art, + OPERAND_opnd_ae_sem_sp32cvt_i_imm5, + OPERAND_opnd_ae_sem_sp32cvt_vr, + OPERAND_opnd_ae_sem_sp32cvt_vt, + OPERAND_opnd_ae_sem_sp32cvt_arr, + OPERAND_opnd_ae_sem_movfpstate_v, + OPERAND_opnd_ae_sem_fpmov_vr, + OPERAND_opnd_ae_sem_fpmov_vt, + OPERAND_opnd_ae_sem_fpmov_i_imm4, + OPERAND_opnd_ae_sem_fpmov_vs, + OPERAND_opnd_ae_sem_fpmov_vu, + OPERAND_opnd_ae_sem_spmisc_vsM, + OPERAND_opnd_ae_sem_spmisc_vtM, + OPERAND_opnd_ae_sem_spmisc_vt, + OPERAND_opnd_ae_sem_spaddsub_vr, + OPERAND_opnd_ae_sem_spaddsub_vs, + OPERAND_opnd_ae_sem_spaddsub_vt, + OPERAND_opnd_ae_sem_spaddsub_vu, + OPERAND_opnd_ae_sem_spfma_vr, + OPERAND_opnd_ae_sem_spfma_vs, + OPERAND_opnd_ae_sem_spfma_vt, + OPERAND_opnd_ae_sem_spfma_vp, + OPERAND_opnd_ae_sem_spfma_i_imm1, + OPERAND_opnd_ae_sem_spfma_i_imm3, + OPERAND_opnd_ae_sem_spaddsub_vp, + OPERAND_opnd_ae_sem_spaddsub_vq, + OPERAND_opnd_ae_sem_spfma_vu, + OPERAND_opnd_ae_sem_spfma_vq, + OPERAND_opnd_ae_sem_hprminmaxnum_vr, + OPERAND_opnd_ae_sem_hprminmaxnum_vt, + OPERAND_opnd_ae_sem_hpcmp_br4t, + OPERAND_opnd_ae_sem_hpcmp_vr, + OPERAND_opnd_ae_sem_hpcmp_vs, + OPERAND_opnd_ae_sem_hpcnv_art, + OPERAND_opnd_ae_sem_hpcnv_i_imm4, + OPERAND_opnd_ae_sem_hpcnv_vr, + OPERAND_opnd_ae_sem_hpcnv_arr, + OPERAND_opnd_ae_sem_hpcnv_vt, + OPERAND_opnd_ae_sem_hpcmp_vt, + OPERAND_opnd_ae_sem_hpcnv_vs, + OPERAND_opnd_ae_sem_hpfma_vr, + OPERAND_opnd_ae_sem_hpfma_vs, + OPERAND_opnd_ae_sem_hpfma_vt, + OPERAND_opnd_ae_sem_hpfma_vp, + OPERAND_opnd_ae_sem_hpfma_vu, + OPERAND_opnd_ae_sem_hpfma_vq, + OPERAND_opnd_ae_sem_mul_nn_c0, + OPERAND_opnd_ae_sem_mul_nn_c1, + OPERAND_opnd_ae_sem_mul_nn_c2, + OPERAND_opnd_ae_sem_mul_nn_c3, + OPERAND_opnd_ae_sem_mul_nn_q0, + OPERAND_opnd_ae_sem_mul_nn_q1, + OPERAND_opnd_ae_sem_mul_nn_v0, + OPERAND_opnd_ae_sem_mul_nn_v1, + OPERAND_opnd_ae_sem_mul_nn_q2, + OPERAND_opnd_ae_sem_mul_nn_q3, + OPERAND_opnd_ae_sem_mul_nn_v2, + OPERAND_opnd_ae_sem_mul_nn_v3, + OPERAND_bbi, + OPERAND_sae, + OPERAND_sas, + OPERAND_sargt, + OPERAND_s, + OPERAND_bitindex, + OPERAND_t, + OPERAND_bbi4, + OPERAND_imm12, + OPERAND_imm8, + OPERAND_s8, + OPERAND_imms8, + OPERAND_imm12b, + OPERAND_imm16, + OPERAND_m, + OPERAND_n, + OPERAND_offset, + OPERAND_op0, + OPERAND_op1, + OPERAND_op2, + OPERAND_r, + OPERAND_r_disp, + OPERAND_r_3, + OPERAND_sa4, + OPERAND_sae4, + OPERAND_sal, + OPERAND_sas4, + OPERAND_sr, + OPERAND_st, + OPERAND_thi3, + OPERAND_imm4, + OPERAND_mn, + OPERAND_i, + OPERAND_imm6lo, + OPERAND_imm6hi, + OPERAND_imm7lo, + OPERAND_imm7hi, + OPERAND_z, + OPERAND_imm6, + OPERAND_imm7, + OPERAND_t2, + OPERAND_s2, + OPERAND_r2, + OPERAND_t4, + OPERAND_s4, + OPERAND_r4, + OPERAND_t8, + OPERAND_r8, + OPERAND_xt_wbr15_imm, + OPERAND_xt_wloop_imm, + OPERAND_ae_fld_Inst16b_12, + OPERAND_ae_fld_Inst16b_15_13, + OPERAND_fld_ae_sem_arithmetic_art, + OPERAND_fld_ae_sem_arithmetic_ds, + OPERAND_fld_ae_sem_arithmetic_v, + OPERAND_fld_ae_sem_arithmetic_v0, + OPERAND_fld_ae_sem_arithmetic_v1, + OPERAND_fld_ae_sem_arithmetic_va, + OPERAND_fld_ae_sem_arithmetic_vs, + OPERAND_fld_ae_sem_dr_to_ar_a, + OPERAND_fld_ae_sem_dr_to_ar_ab, + OPERAND_fld_ae_sem_dr_to_ar_ai, + OPERAND_fld_ae_sem_dr_to_ar_aoe, + OPERAND_fld_ae_sem_dr_to_ar_d, + OPERAND_fld_ae_sem_dr_to_ar_d0, + OPERAND_fld_ae_sem_dr_to_ar_d1, + OPERAND_fld_ae_sem_dr_to_ar_imm8, + OPERAND_fld_ae_sem_dr_to_ar_v0, + OPERAND_fld_ae_sem_dr_to_ar_vr, + OPERAND_fld_ae_sem_dr_to_dr_arr, + OPERAND_fld_ae_sem_dr_to_dr_bt, + OPERAND_fld_ae_sem_dr_to_dr_ds, + OPERAND_fld_ae_sem_dr_to_dr_imm2, + OPERAND_fld_ae_sem_dr_to_dr_immed, + OPERAND_fld_ae_sem_dr_to_dr_movi_imm, + OPERAND_fld_ae_sem_dr_to_dr_v, + OPERAND_fld_ae_sem_dr_to_dr_v0, + OPERAND_fld_ae_sem_dr_to_dr_v1, + OPERAND_fld_ae_sem_hpcmp_br4t, + OPERAND_fld_ae_sem_hpcmp_vr, + OPERAND_fld_ae_sem_hpcmp_vs, + OPERAND_fld_ae_sem_hpcnv_arr, + OPERAND_fld_ae_sem_hpcnv_art, + OPERAND_fld_ae_sem_hpcnv_i_imm4, + OPERAND_fld_ae_sem_hpcnv_vr, + OPERAND_fld_ae_sem_hpcnv_vt, + OPERAND_fld_ae_sem_hprminmaxnum_vr, + OPERAND_fld_ae_sem_hprminmaxnum_vt, + OPERAND_fld_ae_sem_lb_ops_iba, + OPERAND_fld_ae_sem_loads_stores_a, + OPERAND_fld_ae_sem_loads_stores_a_0, + OPERAND_fld_ae_sem_loads_stores_av, + OPERAND_fld_ae_sem_loads_stores_av1, + OPERAND_fld_ae_sem_loads_stores_end, + OPERAND_fld_ae_sem_loads_stores_i128, + OPERAND_fld_ae_sem_loads_stores_i16, + OPERAND_fld_ae_sem_loads_stores_i3, + OPERAND_fld_ae_sem_loads_stores_i32, + OPERAND_fld_ae_sem_loads_stores_i32pos, + OPERAND_fld_ae_sem_loads_stores_i64, + OPERAND_fld_ae_sem_loads_stores_i64half, + OPERAND_fld_ae_sem_loads_stores_i64neg, + OPERAND_fld_ae_sem_loads_stores_i64pos, + OPERAND_fld_ae_sem_loads_stores_i64x2, + OPERAND_fld_ae_sem_loads_stores_i8, + OPERAND_fld_ae_sem_loads_stores_imm2, + OPERAND_fld_ae_sem_loads_stores_su, + OPERAND_fld_ae_sem_loads_stores_uu, + OPERAND_fld_ae_sem_loads_stores_v, + OPERAND_fld_ae_sem_loads_stores_v1, + OPERAND_fld_ae_sem_loads_stores_vu, + OPERAND_fld_ae_sem_loads_stores_x, + OPERAND_fld_ae_sem_pks_d, + OPERAND_fld_ae_sem_pks_pos, + OPERAND_fld_ae_sem_pks_s, + OPERAND_fld_ae_sem_rng_v0, + OPERAND_fld_ae_sem_rng_v1, + OPERAND_fld_ae_sem_sb_loads_stores_iba, + OPERAND_fld_ae_sem_shift_a, + OPERAND_fld_ae_sem_shift_a0, + OPERAND_fld_ae_sem_shift_d, + OPERAND_fld_ae_sem_shift_d0, + OPERAND_fld_ae_sem_shift_d1, + OPERAND_fld_ae_sem_shift_da, + OPERAND_fld_ae_sem_shift_i16, + OPERAND_fld_ae_sem_shift_i32, + OPERAND_fld_ae_sem_shift_i64, + OPERAND_fld_ae_sem_shift_imm32, + OPERAND_fld_ae_sem_shift_imm8, + OPERAND_fld_ae_sem_shift_sd, + OPERAND_fld_ae_sem_sp32cvt_arr, + OPERAND_fld_ae_sem_sp32cvt_art, + OPERAND_fld_ae_sem_sp32cvt_i_imm5, + OPERAND_fld_ae_sem_sp32cvt_vr, + OPERAND_fld_ae_sem_sp32cvt_vt, + OPERAND_fld_ae_sem_spmisc_brt, + OPERAND_fld_ae_sem_spmisc_vr, + OPERAND_fld_ae_sem_spmisc_vs, + OPERAND_fld_ae_slot0_11_10, + OPERAND_fld_ae_slot0_11_11, + OPERAND_fld_ae_slot0_11_8, + OPERAND_fld_ae_slot0_11_9, + OPERAND_fld_ae_slot0_12_0, + OPERAND_fld_ae_slot0_12_10, + OPERAND_fld_ae_slot0_12_12, + OPERAND_fld_ae_slot0_12_2, + OPERAND_fld_ae_slot0_12_6, + OPERAND_fld_ae_slot0_12_8, + OPERAND_fld_ae_slot0_12_9, + OPERAND_fld_ae_slot0_14_12, + OPERAND_fld_ae_slot0_14_13, + OPERAND_fld_ae_slot0_17_10, + OPERAND_fld_ae_slot0_17_12, + OPERAND_fld_ae_slot0_17_13, + OPERAND_fld_ae_slot0_17_14, + OPERAND_fld_ae_slot0_17_15, + OPERAND_fld_ae_slot0_17_16, + OPERAND_fld_ae_slot0_17_17, + OPERAND_fld_ae_slot0_17_8, + OPERAND_fld_ae_slot0_18_13, + OPERAND_fld_ae_slot0_18_15, + OPERAND_fld_ae_slot0_18_16, + OPERAND_fld_ae_slot0_18_8, + OPERAND_fld_ae_slot0_19_12, + OPERAND_fld_ae_slot0_19_15, + OPERAND_fld_ae_slot0_19_19, + OPERAND_fld_ae_slot0_19_8, + OPERAND_fld_ae_slot0_1_0, + OPERAND_fld_ae_slot0_1_1, + OPERAND_fld_ae_slot0_20_16, + OPERAND_fld_ae_slot0_20_20, + OPERAND_fld_ae_slot0_23_15, + OPERAND_fld_ae_slot0_23_17, + OPERAND_fld_ae_slot0_23_19, + OPERAND_fld_ae_slot0_23_22, + OPERAND_fld_ae_slot0_28_10, + OPERAND_fld_ae_slot0_28_12, + OPERAND_fld_ae_slot0_28_14, + OPERAND_fld_ae_slot0_28_15, + OPERAND_fld_ae_slot0_28_16, + OPERAND_fld_ae_slot0_28_17, + OPERAND_fld_ae_slot0_28_19, + OPERAND_fld_ae_slot0_28_21, + OPERAND_fld_ae_slot0_28_22, + OPERAND_fld_ae_slot0_28_24, + OPERAND_fld_ae_slot0_28_26, + OPERAND_fld_ae_slot0_28_27, + OPERAND_fld_ae_slot0_28_4, + OPERAND_fld_ae_slot0_28_8, + OPERAND_fld_ae_slot0_3_0, + OPERAND_fld_ae_slot0_3_1, + OPERAND_fld_ae_slot0_3_2, + OPERAND_fld_ae_slot0_3_3, + OPERAND_fld_ae_slot0_4_0, + OPERAND_fld_ae_slot0_4_4, + OPERAND_fld_ae_slot0_5_0, + OPERAND_fld_ae_slot0_5_4, + OPERAND_fld_ae_slot0_7_0, + OPERAND_fld_ae_slot0_7_2, + OPERAND_fld_ae_slot0_7_3, + OPERAND_fld_ae_slot0_7_4, + OPERAND_fld_ae_slot0_8_8, + OPERAND_fld_ae_slot0_9_4, + OPERAND_fld_ae_slot0_9_8, + OPERAND_fld_ae_slot0_9_9, + OPERAND_fld_ae_slot1_0_0, + OPERAND_fld_ae_slot1_12_8, + OPERAND_fld_ae_slot1_17_13, + OPERAND_fld_ae_slot1_17_17, + OPERAND_fld_ae_slot1_17_8, + OPERAND_fld_ae_slot1_25_1, + OPERAND_fld_ae_slot1_25_12, + OPERAND_fld_ae_slot1_25_13, + OPERAND_fld_ae_slot1_25_16, + OPERAND_fld_ae_slot1_25_17, + OPERAND_fld_ae_slot1_25_18, + OPERAND_fld_ae_slot1_25_20, + OPERAND_fld_ae_slot1_25_22, + OPERAND_fld_ae_slot1_25_23, + OPERAND_fld_ae_slot1_25_8, + OPERAND_fld_ae_slot1_25_9, + OPERAND_fld_ae_slot1_3_0, + OPERAND_fld_ae_slot1_3_2, + OPERAND_fld_ae_slot1_3_3, + OPERAND_fld_ae_slot1_7_4, + OPERAND_fld_ae_sem_arithmetic_e, + OPERAND_fld_ae_sem_arithmetic_ep, + OPERAND_fld_ae_sem_arithmetic_ep1, + OPERAND_fld_ae_sem_dr_to_ar_ei, + OPERAND_fld_ae_sem_dr_to_ar_eo, + OPERAND_fld_ae_sem_dr_to_dr_immed_N, + OPERAND_fld_ae_sem_fpmov_i_imm4, + OPERAND_fld_ae_sem_fpmov_vr, + OPERAND_fld_ae_sem_fpmov_vs, + OPERAND_fld_ae_sem_fpmov_vt, + OPERAND_fld_ae_sem_fpmov_vu, + OPERAND_fld_ae_sem_hpcmp_vt, + OPERAND_fld_ae_sem_hpcnv_vs, + OPERAND_fld_ae_sem_hpfma_vr, + OPERAND_fld_ae_sem_hpfma_vs, + OPERAND_fld_ae_sem_hpfma_vt, + OPERAND_fld_ae_sem_movfpstate_v, + OPERAND_fld_ae_sem_multiply_acc_ep, + OPERAND_fld_ae_sem_multiply_d0, + OPERAND_fld_ae_sem_multiply_d2, + OPERAND_fld_ae_sem_multiply_q0, + OPERAND_fld_ae_sem_multiply_q1, + OPERAND_fld_ae_sem_reduction_sort_ds, + OPERAND_fld_ae_sem_reduction_sort_v, + OPERAND_fld_ae_sem_reduction_sort_v0, + OPERAND_fld_ae_sem_select_isel, + OPERAND_fld_ae_sem_select_ss, + OPERAND_fld_ae_sem_select_vr, + OPERAND_fld_ae_sem_select_vs, + OPERAND_fld_ae_sem_select_vt, + OPERAND_fld_ae_sem_select_vu, + OPERAND_fld_ae_sem_spaddsub_vr, + OPERAND_fld_ae_sem_spaddsub_vs, + OPERAND_fld_ae_sem_spaddsub_vt, + OPERAND_fld_ae_sem_spaddsub_vu, + OPERAND_fld_ae_sem_spfma_i_imm1, + OPERAND_fld_ae_sem_spfma_i_imm3, + OPERAND_fld_ae_sem_spfma_vp, + OPERAND_fld_ae_sem_spfma_vr, + OPERAND_fld_ae_sem_spfma_vs, + OPERAND_fld_ae_sem_spfma_vt, + OPERAND_fld_ae_sem_spmisc_vsM, + OPERAND_fld_ae_sem_spmisc_vt, + OPERAND_fld_ae_sem_spmisc_vtM, + OPERAND_fld_ae_slot2_14_0, + OPERAND_fld_ae_slot2_14_10, + OPERAND_fld_ae_slot2_14_14, + OPERAND_fld_ae_slot2_14_5, + OPERAND_fld_ae_slot2_16_15, + OPERAND_fld_ae_slot2_19_15, + OPERAND_fld_ae_slot2_28_15, + OPERAND_fld_ae_slot2_28_17, + OPERAND_fld_ae_slot2_28_19, + OPERAND_fld_ae_slot2_28_20, + OPERAND_fld_ae_slot2_28_25, + OPERAND_fld_ae_slot2_28_4, + OPERAND_fld_ae_slot2_28_5, + OPERAND_fld_ae_slot2_3_0, + OPERAND_fld_ae_slot2_9_0, + OPERAND_fld_ae_slot2_9_1, + OPERAND_fld_ae_slot2_9_2, + OPERAND_fld_ae_slot2_9_5, + OPERAND_fld_ae_slot2_9_6, + OPERAND_fld_ae_slot2_9_7, + OPERAND_fld_ae_slot2_9_8, + OPERAND_fld_ae_sem_dr_to_dr_imm, + OPERAND_fld_ae_sem_multiply_d1, + OPERAND_fld_ae_sem_multiply_d3, + OPERAND_fld_ae_sem_rng_d, + OPERAND_fld_ae_sem_shift_e, + OPERAND_fld_ae_sem_shift_i8, + OPERAND_fld_ae_slot3_11_0, + OPERAND_fld_ae_slot3_14_0, + OPERAND_fld_ae_slot3_14_10, + OPERAND_fld_ae_slot3_14_12, + OPERAND_fld_ae_slot3_14_13, + OPERAND_fld_ae_slot3_16_13, + OPERAND_fld_ae_slot3_19_0, + OPERAND_fld_ae_slot3_19_10, + OPERAND_fld_ae_slot3_19_15, + OPERAND_fld_ae_slot3_19_17, + OPERAND_fld_ae_slot3_19_18, + OPERAND_fld_ae_slot3_19_19, + OPERAND_fld_ae_slot3_24_10, + OPERAND_fld_ae_slot3_24_19, + OPERAND_fld_ae_slot3_24_20, + OPERAND_fld_ae_slot3_36_12, + OPERAND_fld_ae_slot3_36_16, + OPERAND_fld_ae_slot3_36_19, + OPERAND_fld_ae_slot3_36_20, + OPERAND_fld_ae_slot3_36_22, + OPERAND_fld_ae_slot3_36_25, + OPERAND_fld_ae_slot3_36_30, + OPERAND_fld_ae_slot3_4_0, + OPERAND_fld_ae_slot3_9_0, + OPERAND_fld_ae_slot3_9_1, + OPERAND_fld_ae_slot3_9_3, + OPERAND_fld_ae_slot3_9_5, + OPERAND_fld_ae2_slot0_0_0, + OPERAND_fld_ae2_slot0_11_4, + OPERAND_fld_ae2_slot0_11_8, + OPERAND_fld_ae2_slot0_11_9, + OPERAND_fld_ae2_slot0_12_0, + OPERAND_fld_ae2_slot0_12_2, + OPERAND_fld_ae2_slot0_12_4, + OPERAND_fld_ae2_slot0_12_8, + OPERAND_fld_ae2_slot0_14_13, + OPERAND_fld_ae2_slot0_14_8, + OPERAND_fld_ae2_slot0_15_0, + OPERAND_fld_ae2_slot0_15_12, + OPERAND_fld_ae2_slot0_15_13, + OPERAND_fld_ae2_slot0_15_15, + OPERAND_fld_ae2_slot0_15_4, + OPERAND_fld_ae2_slot0_15_8, + OPERAND_fld_ae2_slot0_17_13, + OPERAND_fld_ae2_slot0_17_17, + OPERAND_fld_ae2_slot0_18_15, + OPERAND_fld_ae2_slot0_18_17, + OPERAND_fld_ae2_slot0_18_18, + OPERAND_fld_ae2_slot0_1_0, + OPERAND_fld_ae2_slot0_23_18, + OPERAND_fld_ae2_slot0_23_19, + OPERAND_fld_ae2_slot0_3_0, + OPERAND_fld_ae2_slot0_40_16, + OPERAND_fld_ae2_slot0_40_17, + OPERAND_fld_ae2_slot0_40_18, + OPERAND_fld_ae2_slot0_40_19, + OPERAND_fld_ae2_slot0_40_21, + OPERAND_fld_ae2_slot0_40_23, + OPERAND_fld_ae2_slot0_40_24, + OPERAND_fld_ae2_slot0_40_25, + OPERAND_fld_ae2_slot0_40_26, + OPERAND_fld_ae2_slot0_40_27, + OPERAND_fld_ae2_slot0_7_0, + OPERAND_fld_ae2_slot0_7_4, + OPERAND_fld_ae2_slot0_7_6, + OPERAND_fld_ae2_slot0_7_7, + OPERAND_fld_ae2_slot0_8_8, + OPERAND_fld_ae2_slot0_9_8, + OPERAND_fld_ae2_slot1_0_0, + OPERAND_fld_ae2_slot1_11_0, + OPERAND_fld_ae2_slot1_11_10, + OPERAND_fld_ae2_slot1_11_8, + OPERAND_fld_ae2_slot1_14_10, + OPERAND_fld_ae2_slot1_14_11, + OPERAND_fld_ae2_slot1_14_12, + OPERAND_fld_ae2_slot1_14_14, + OPERAND_fld_ae2_slot1_14_8, + OPERAND_fld_ae2_slot1_36_12, + OPERAND_fld_ae2_slot1_36_14, + OPERAND_fld_ae2_slot1_36_15, + OPERAND_fld_ae2_slot1_36_16, + OPERAND_fld_ae2_slot1_36_17, + OPERAND_fld_ae2_slot1_36_18, + OPERAND_fld_ae2_slot1_36_20, + OPERAND_fld_ae2_slot1_36_22, + OPERAND_fld_ae2_slot1_36_23, + OPERAND_fld_ae2_slot1_3_0, + OPERAND_fld_ae2_slot1_3_1, + OPERAND_fld_ae2_slot1_3_2, + OPERAND_fld_ae2_slot1_3_3, + OPERAND_fld_ae2_slot1_7_4, + OPERAND_fld_ae2_slot1_9_8, + OPERAND_fld_ae2_slot1_9_9, + OPERAND_fld_ae2_slot2_14_10, + OPERAND_fld_ae2_slot2_17_0, + OPERAND_fld_ae2_slot2_17_10, + OPERAND_fld_ae2_slot2_17_15, + OPERAND_fld_ae2_slot2_17_17, + OPERAND_fld_ae2_slot2_19_10, + OPERAND_fld_ae2_slot2_19_15, + OPERAND_fld_ae2_slot2_19_18, + OPERAND_fld_ae2_slot2_19_9, + OPERAND_fld_ae2_slot2_24_10, + OPERAND_fld_ae2_slot2_24_15, + OPERAND_fld_ae2_slot2_24_20, + OPERAND_fld_ae2_slot2_24_5, + OPERAND_fld_ae2_slot2_24_9, + OPERAND_fld_ae2_slot2_42_18, + OPERAND_fld_ae2_slot2_42_20, + OPERAND_fld_ae2_slot2_42_25, + OPERAND_fld_ae2_slot2_42_26, + OPERAND_fld_ae2_slot2_42_28, + OPERAND_fld_ae2_slot2_42_30, + OPERAND_fld_ae2_slot2_4_0, + OPERAND_fld_ae2_slot2_9_5, + OPERAND_fld_ae_sem_spaddsub_vp, + OPERAND_fld_ae_sem_spaddsub_vq, + OPERAND_fld_ae3_slot0_11_11, + OPERAND_fld_ae3_slot0_11_4, + OPERAND_fld_ae3_slot0_11_8, + OPERAND_fld_ae3_slot0_12_12, + OPERAND_fld_ae3_slot0_12_8, + OPERAND_fld_ae3_slot0_13_13, + OPERAND_fld_ae3_slot0_13_8, + OPERAND_fld_ae3_slot0_1_0, + OPERAND_fld_ae3_slot0_32_11, + OPERAND_fld_ae3_slot0_32_12, + OPERAND_fld_ae3_slot0_32_13, + OPERAND_fld_ae3_slot0_32_14, + OPERAND_fld_ae3_slot0_32_15, + OPERAND_fld_ae3_slot0_32_16, + OPERAND_fld_ae3_slot0_32_17, + OPERAND_fld_ae3_slot0_32_18, + OPERAND_fld_ae3_slot0_32_20, + OPERAND_fld_ae3_slot0_32_27, + OPERAND_fld_ae3_slot0_32_8, + OPERAND_fld_ae3_slot0_3_0, + OPERAND_fld_ae3_slot0_3_2, + OPERAND_fld_ae3_slot0_3_3, + OPERAND_fld_ae3_slot0_4_0, + OPERAND_fld_ae3_slot0_4_4, + OPERAND_fld_ae3_slot0_5_0, + OPERAND_fld_ae3_slot0_5_4, + OPERAND_fld_ae3_slot0_7_0, + OPERAND_fld_ae3_slot0_7_2, + OPERAND_fld_ae3_slot0_7_4, + OPERAND_fld_ae3_slot0_7_6, + OPERAND_fld_ae3_slot0_8_8, + OPERAND_fld_ae3_slot0_9_4, + OPERAND_fld_ae3_slot0_9_8, + OPERAND_fld_ae_sem_dr_to_ar_ar_s, + OPERAND_fld_ae_sem_sb_loads_stores_iba2, + OPERAND_fld_ae3_slot1_23_0, + OPERAND_fld_ae3_slot1_23_11, + OPERAND_fld_ae3_slot1_23_12, + OPERAND_fld_ae3_slot1_23_13, + OPERAND_fld_ae3_slot1_23_15, + OPERAND_fld_ae3_slot1_23_16, + OPERAND_fld_ae3_slot1_23_17, + OPERAND_fld_ae3_slot1_23_19, + OPERAND_fld_ae3_slot1_23_6, + OPERAND_fld_ae3_slot1_23_8, + OPERAND_fld_ae3_slot1_23_9, + OPERAND_fld_ae3_slot1_3_0, + OPERAND_fld_ae3_slot1_3_1, + OPERAND_fld_ae3_slot1_3_2, + OPERAND_fld_ae3_slot1_3_3, + OPERAND_fld_ae3_slot1_7_4, + OPERAND_fld_ae3_slot1_9_8, + OPERAND_fld_AE_ARDECNORM16_ar_u, + OPERAND_fld_ae5_slot0_11_10, + OPERAND_fld_ae5_slot0_11_4, + OPERAND_fld_ae5_slot0_11_8, + OPERAND_fld_ae5_slot0_11_9, + OPERAND_fld_ae5_slot0_12_10, + OPERAND_fld_ae5_slot0_12_4, + OPERAND_fld_ae5_slot0_12_6, + OPERAND_fld_ae5_slot0_12_8, + OPERAND_fld_ae5_slot0_12_9, + OPERAND_fld_ae5_slot0_1_0, + OPERAND_fld_ae5_slot0_1_1, + OPERAND_fld_ae5_slot0_29_12, + OPERAND_fld_ae5_slot0_29_13, + OPERAND_fld_ae5_slot0_29_15, + OPERAND_fld_ae5_slot0_29_16, + OPERAND_fld_ae5_slot0_29_17, + OPERAND_fld_ae5_slot0_29_18, + OPERAND_fld_ae5_slot0_29_19, + OPERAND_fld_ae5_slot0_29_20, + OPERAND_fld_ae5_slot0_29_27, + OPERAND_fld_ae5_slot0_29_5, + OPERAND_fld_ae5_slot0_29_6, + OPERAND_fld_ae5_slot0_29_8, + OPERAND_fld_ae5_slot0_2_0, + OPERAND_fld_ae5_slot0_3_0, + OPERAND_fld_ae5_slot0_3_2, + OPERAND_fld_ae5_slot0_4_0, + OPERAND_fld_ae5_slot0_4_4, + OPERAND_fld_ae5_slot0_7_0, + OPERAND_fld_ae5_slot0_7_4, + OPERAND_fld_ae5_slot0_7_7, + OPERAND_fld_ae5_slot0_8_8, + OPERAND_fld_ae_sem_lb_db_ops_ar_u, + OPERAND_fld_ae_sem_lb_db_ops_iba, + OPERAND_fld_ae_sem_rng_a, + OPERAND_fld_ae_sem_rng_art, + OPERAND_fld_ae_sem_rng_i2, + OPERAND_fld_ae_sem_rng_imm2, + OPERAND_fld_ae5_slot1_1_0, + OPERAND_fld_ae5_slot2_14_10, + OPERAND_fld_ae5_slot2_14_14, + OPERAND_fld_ae5_slot2_14_5, + OPERAND_fld_ae5_slot2_24_0, + OPERAND_fld_ae5_slot2_24_15, + OPERAND_fld_ae5_slot2_24_17, + OPERAND_fld_ae5_slot2_24_20, + OPERAND_fld_ae5_slot2_4_0, + OPERAND_fld_ae5_slot2_9_0, + OPERAND_fld_ae5_slot2_9_5, + OPERAND_fld_ae5_slot2_9_7, + OPERAND_fld_ae6_slot0_10_10, + OPERAND_fld_ae6_slot0_15_15, + OPERAND_fld_ae6_slot0_29_10, + OPERAND_fld_ae6_slot0_29_13, + OPERAND_fld_ae6_slot0_29_14, + OPERAND_fld_ae6_slot0_29_15, + OPERAND_fld_ae6_slot0_29_18, + OPERAND_fld_ae6_slot0_29_20, + OPERAND_fld_ae6_slot0_29_5, + OPERAND_fld_ae6_slot0_4_0, + OPERAND_fld_ae6_slot0_4_4, + OPERAND_fld_ae6_slot0_7_4, + OPERAND_fld_ae6_slot0_7_7, + OPERAND_fld_ae6_slot0_9_8, + OPERAND_fld_ae6_slot0_9_9, + OPERAND_fld_ae6_slot1_14_14, + OPERAND_fld_ae6_slot1_27_12, + OPERAND_fld_ae6_slot1_27_15, + OPERAND_fld_ae6_slot1_27_20, + OPERAND_fld_ae6_slot1_27_21, + OPERAND_fld_ae6_slot1_27_3, + OPERAND_fld_ae6_slot1_27_6, + OPERAND_fld_ae6_slot1_2_0, + OPERAND_fld_ae6_slot1_9_5, + OPERAND_fld_ae6_slot1_9_6, + OPERAND_fld_ae6_slot1_9_7, + OPERAND_fld_ae6_slot1_9_8, + OPERAND_fld_ae6_slot1_9_9, + OPERAND_fld_ae6_slot2_10_10, + OPERAND_fld_ae6_slot2_11_10, + OPERAND_fld_ae6_slot2_24_0, + OPERAND_fld_ae6_slot2_24_10, + OPERAND_fld_ae6_slot2_24_14, + OPERAND_fld_ae6_slot2_24_15, + OPERAND_fld_ae6_slot2_24_20, + OPERAND_fld_ae6_slot2_4_2, + OPERAND_fld_ae6_slot2_9_5, + OPERAND_fld_ae6_slot3_10_10, + OPERAND_fld_ae6_slot3_12_0, + OPERAND_fld_ae6_slot3_14_0, + OPERAND_fld_ae6_slot3_14_10, + OPERAND_fld_ae6_slot3_14_13, + OPERAND_fld_ae6_slot3_14_5, + OPERAND_fld_ae6_slot3_24_20, + OPERAND_fld_ae6_slot3_37_13, + OPERAND_fld_ae6_slot3_37_15, + OPERAND_fld_ae6_slot3_37_20, + OPERAND_fld_ae6_slot3_37_30, + OPERAND_fld_ae6_slot3_9_5, + OPERAND_fld_ae7_slot0_12_6, + OPERAND_fld_ae7_slot0_23_0, + OPERAND_fld_ae7_slot0_23_13, + OPERAND_fld_ae7_slot0_23_17, + OPERAND_fld_ae7_slot0_23_18, + OPERAND_fld_ae7_slot0_23_6, + OPERAND_fld_ae7_slot0_7_4, + OPERAND_fld_ae7_slot0_7_6, + OPERAND_fld_ae7_slot0_7_7, + OPERAND_fld_ae7_slot1_12_6, + OPERAND_fld_ae7_slot1_23_0, + OPERAND_fld_ae7_slot1_23_13, + OPERAND_fld_ae7_slot1_23_17, + OPERAND_fld_ae7_slot1_23_18, + OPERAND_fld_ae7_slot1_23_6, + OPERAND_fld_ae7_slot1_7_4, + OPERAND_fld_ae7_slot1_7_6, + OPERAND_fld_ae7_slot1_7_7, + OPERAND_fld_ae7_slot2_11_0, + OPERAND_fld_ae7_slot2_14_10, + OPERAND_fld_ae7_slot2_14_5, + OPERAND_fld_ae7_slot2_36_12, + OPERAND_fld_ae7_slot2_36_15, + OPERAND_fld_ae7_slot2_36_20, + OPERAND_fld_ae7_slot2_36_25, + OPERAND_fld_ae7_slot2_36_30, + OPERAND_fld_ae7_slot2_9_5, + OPERAND_fld_ae7_slot3_10_0, + OPERAND_fld_ae7_slot3_14_10, + OPERAND_fld_ae7_slot3_14_5, + OPERAND_fld_ae7_slot3_24_10, + OPERAND_fld_ae7_slot3_35_11, + OPERAND_fld_ae7_slot3_35_20, + OPERAND_fld_ae7_slot3_35_25, + OPERAND_fld_ae7_slot3_35_30, + OPERAND_fld_ae7_slot3_4_0, + OPERAND_fld_ae7_slot3_9_5, + OPERAND_fld_ae8_slot0_13_12, + OPERAND_fld_ae8_slot0_13_13, + OPERAND_fld_ae8_slot0_13_4, + OPERAND_fld_ae8_slot0_13_9, + OPERAND_fld_ae8_slot0_17_4, + OPERAND_fld_ae8_slot0_17_8, + OPERAND_fld_ae8_slot0_31_12, + OPERAND_fld_ae8_slot0_31_15, + OPERAND_fld_ae8_slot0_31_18, + OPERAND_fld_ae8_slot0_31_19, + OPERAND_fld_ae8_slot0_31_20, + OPERAND_fld_ae8_slot0_31_21, + OPERAND_fld_ae8_slot0_31_22, + OPERAND_fld_ae8_slot0_31_23, + OPERAND_fld_ae8_slot0_31_7, + OPERAND_fld_ae8_slot0_31_8, + OPERAND_fld_ae8_slot0_31_9, + OPERAND_fld_ae8_slot0_3_0, + OPERAND_fld_ae8_slot0_6_0, + OPERAND_fld_ae8_slot0_7_4, + OPERAND_fld_ae8_slot0_7_5, + OPERAND_fld_ae8_slot0_7_7, + OPERAND_fld_ae8_slot0_8_0, + OPERAND_fld_ae8_slot1_17_13, + OPERAND_fld_ae8_slot1_17_14, + OPERAND_fld_ae8_slot1_17_15, + OPERAND_fld_ae8_slot1_17_8, + OPERAND_fld_ae8_slot1_29_12, + OPERAND_fld_ae8_slot1_29_13, + OPERAND_fld_ae8_slot1_29_18, + OPERAND_fld_ae8_slot1_29_20, + OPERAND_fld_ae8_slot1_29_22, + OPERAND_fld_ae8_slot1_29_23, + OPERAND_fld_ae8_slot1_29_5, + OPERAND_fld_ae8_slot1_29_8, + OPERAND_fld_ae8_slot1_29_9, + OPERAND_fld_ae8_slot1_3_0, + OPERAND_fld_ae8_slot1_3_3, + OPERAND_fld_ae8_slot1_4_0, + OPERAND_fld_ae8_slot1_7_4, + OPERAND_fld_ae8_slot2_19_10, + OPERAND_fld_ae8_slot2_19_15, + OPERAND_fld_ae8_slot2_33_15, + OPERAND_fld_ae8_slot2_33_25, + OPERAND_fld_ae8_slot2_33_9, + OPERAND_fld_ae8_slot2_34_30, + OPERAND_fld_ae8_slot2_39_35, + OPERAND_fld_ae8_slot2_44_35, + OPERAND_fld_ae8_slot2_58_34, + OPERAND_fld_ae8_slot2_58_35, + OPERAND_fld_ae8_slot2_58_40, + OPERAND_fld_ae8_slot2_58_50, + OPERAND_fld_ae8_slot2_8_0, + OPERAND_fld_ae8_slot2_9_0, + OPERAND_fld_ae_sem_mul_nn_c0, + OPERAND_fld_ae_sem_mul_nn_c1, + OPERAND_fld_ae_sem_mul_nn_c2, + OPERAND_fld_ae_sem_mul_nn_c3, + OPERAND_fld_ae_sem_mul_nn_q0, + OPERAND_fld_ae_sem_mul_nn_q1, + OPERAND_fld_ae_sem_mul_nn_q2, + OPERAND_fld_ae_sem_mul_nn_q3, + OPERAND_fld_ae_sem_mul_nn_v0, + OPERAND_fld_ae_sem_mul_nn_v1, + OPERAND_fld_ae_sem_mul_nn_v2, + OPERAND_fld_ae_sem_mul_nn_v3, + OPERAND_fld_ae9_slot0_0_0, + OPERAND_fld_ae9_slot0_12_12, + OPERAND_fld_ae9_slot0_12_5, + OPERAND_fld_ae9_slot0_12_8, + OPERAND_fld_ae9_slot0_17_13, + OPERAND_fld_ae9_slot0_17_4, + OPERAND_fld_ae9_slot0_17_8, + OPERAND_fld_ae9_slot0_27_10, + OPERAND_fld_ae9_slot0_27_12, + OPERAND_fld_ae9_slot0_27_13, + OPERAND_fld_ae9_slot0_27_16, + OPERAND_fld_ae9_slot0_27_17, + OPERAND_fld_ae9_slot0_27_18, + OPERAND_fld_ae9_slot0_27_19, + OPERAND_fld_ae9_slot0_27_20, + OPERAND_fld_ae9_slot0_27_22, + OPERAND_fld_ae9_slot0_27_23, + OPERAND_fld_ae9_slot0_27_3, + OPERAND_fld_ae9_slot0_27_8, + OPERAND_fld_ae9_slot0_2_0, + OPERAND_fld_ae9_slot0_3_0, + OPERAND_fld_ae9_slot0_7_0, + OPERAND_fld_ae9_slot0_7_4, + OPERAND_fld_ae9_slot0_7_5, + OPERAND_fld_ae9_slot0_7_6, + OPERAND_fld_ae9_slot0_7_7, + OPERAND_fld_ae9_slot0_8_4, + OPERAND_fld_ae9_slot0_8_5, + OPERAND_fld_ae9_slot0_9_5, + OPERAND_fld_ae9_slot1_17_13, + OPERAND_fld_ae9_slot1_17_8, + OPERAND_fld_ae9_slot1_1_0, + OPERAND_fld_ae9_slot1_26_12, + OPERAND_fld_ae9_slot1_26_13, + OPERAND_fld_ae9_slot1_26_16, + OPERAND_fld_ae9_slot1_26_17, + OPERAND_fld_ae9_slot1_26_18, + OPERAND_fld_ae9_slot1_26_2, + OPERAND_fld_ae9_slot1_26_20, + OPERAND_fld_ae9_slot1_26_22, + OPERAND_fld_ae9_slot1_26_23, + OPERAND_fld_ae9_slot1_26_8, + OPERAND_fld_ae9_slot1_26_9, + OPERAND_fld_ae9_slot1_3_0, + OPERAND_fld_ae9_slot1_3_2, + OPERAND_fld_ae9_slot1_3_3, + OPERAND_fld_ae9_slot1_7_4, + OPERAND_fld_ae9_slot2_24_14, + OPERAND_fld_ae9_slot2_24_15, + OPERAND_fld_ae9_slot2_24_20, + OPERAND_fld_ae9_slot2_33_14, + OPERAND_fld_ae9_slot2_33_15, + OPERAND_fld_ae9_slot2_33_20, + OPERAND_fld_ae9_slot2_33_25, + OPERAND_fld_ae9_slot2_33_26, + OPERAND_fld_ae9_slot2_33_28, + OPERAND_fld_ae9_slot2_33_30, + OPERAND_fld_ae9_slot2_33_9, + OPERAND_fld_ae9_slot2_4_0, + OPERAND_fld_ae9_slot2_5_0, + OPERAND_fld_ae9_slot2_6_0, + OPERAND_fld_ae9_slot2_8_0, + OPERAND_fld_ae9_slot2_9_0, + OPERAND_fld_ae9_slot2_9_5, + OPERAND_fld_ae9_slot2_9_9, + OPERAND_fld_ae_sem_hpfma_vp, + OPERAND_fld_ae_sem_hpfma_vu, + OPERAND_fld_ae_sem_spfma_vu, + OPERAND_fld_ae9_slot3_19_15, + OPERAND_fld_ae9_slot3_24_20, + OPERAND_fld_ae9_slot3_31_14, + OPERAND_fld_ae9_slot3_31_15, + OPERAND_fld_ae9_slot3_31_20, + OPERAND_fld_ae9_slot3_31_25, + OPERAND_fld_ae9_slot3_31_26, + OPERAND_fld_ae9_slot3_31_28, + OPERAND_fld_ae9_slot3_31_7, + OPERAND_fld_ae9_slot3_4_0, + OPERAND_fld_ae9_slot3_4_3, + OPERAND_fld_ae9_slot3_4_4, + OPERAND_fld_ae9_slot3_6_0, + OPERAND_fld_ae9_slot3_9_0, + OPERAND_fld_ae9_slot3_9_5, + OPERAND_fld_ae10_slot0_17_13, + OPERAND_fld_ae10_slot0_17_4, + OPERAND_fld_ae10_slot0_17_8, + OPERAND_fld_ae10_slot0_24_0, + OPERAND_fld_ae10_slot0_24_10, + OPERAND_fld_ae10_slot0_24_12, + OPERAND_fld_ae10_slot0_24_13, + OPERAND_fld_ae10_slot0_24_16, + OPERAND_fld_ae10_slot0_24_17, + OPERAND_fld_ae10_slot0_24_18, + OPERAND_fld_ae10_slot0_24_20, + OPERAND_fld_ae10_slot0_24_8, + OPERAND_fld_ae10_slot0_3_0, + OPERAND_fld_ae10_slot0_7_4, + OPERAND_fld_ae10_slot0_7_6, + OPERAND_fld_ae10_slot0_7_7, + OPERAND_fld_ae10_slot0_8_4, + OPERAND_fld_ae10_slot1_0_0, + OPERAND_fld_ae10_slot1_17_13, + OPERAND_fld_ae10_slot1_17_8, + OPERAND_fld_ae10_slot1_25_1, + OPERAND_fld_ae10_slot1_25_12, + OPERAND_fld_ae10_slot1_25_13, + OPERAND_fld_ae10_slot1_25_16, + OPERAND_fld_ae10_slot1_25_17, + OPERAND_fld_ae10_slot1_25_18, + OPERAND_fld_ae10_slot1_25_20, + OPERAND_fld_ae10_slot1_25_22, + OPERAND_fld_ae10_slot1_25_23, + OPERAND_fld_ae10_slot1_25_8, + OPERAND_fld_ae10_slot1_25_9, + OPERAND_fld_ae10_slot1_3_0, + OPERAND_fld_ae10_slot1_3_2, + OPERAND_fld_ae10_slot1_3_3, + OPERAND_fld_ae10_slot1_7_4, + OPERAND_fld_ae10_slot2_24_20, + OPERAND_fld_ae10_slot2_29_20, + OPERAND_fld_ae10_slot2_29_25, + OPERAND_fld_ae10_slot2_34_10, + OPERAND_fld_ae10_slot2_34_14, + OPERAND_fld_ae10_slot2_34_15, + OPERAND_fld_ae10_slot2_34_20, + OPERAND_fld_ae10_slot2_34_25, + OPERAND_fld_ae10_slot2_34_30, + OPERAND_fld_ae10_slot2_34_31, + OPERAND_fld_ae10_slot2_34_33, + OPERAND_fld_ae10_slot2_4_0, + OPERAND_fld_ae10_slot2_9_0, + OPERAND_fld_ae10_slot2_9_5, + OPERAND_fld_ae_sem_hpfma_vq, + OPERAND_fld_ae_sem_spfma_vq, + OPERAND_fld_ae10_slot3_19_15, + OPERAND_fld_ae10_slot3_29_20, + OPERAND_fld_ae10_slot3_29_25, + OPERAND_fld_ae10_slot3_34_10, + OPERAND_fld_ae10_slot3_34_14, + OPERAND_fld_ae10_slot3_34_15, + OPERAND_fld_ae10_slot3_34_20, + OPERAND_fld_ae10_slot3_34_25, + OPERAND_fld_ae10_slot3_34_30, + OPERAND_fld_ae10_slot3_34_31, + OPERAND_fld_ae10_slot3_34_33, + OPERAND_fld_ae10_slot3_4_0, + OPERAND_fld_ae10_slot3_4_3, + OPERAND_fld_ae10_slot3_4_4, + OPERAND_fld_ae10_slot3_9_0, + OPERAND_fld_ae10_slot3_9_5, + OPERAND_fld_ae4_slot0_22_0, + OPERAND_fld_ae4_slot0_22_12, + OPERAND_fld_ae4_slot0_22_13, + OPERAND_fld_ae4_slot0_22_16, + OPERAND_fld_ae4_slot0_22_17, + OPERAND_fld_ae4_slot0_22_18, + OPERAND_fld_ae4_slot0_22_20, + OPERAND_fld_ae4_slot0_22_6, + OPERAND_fld_ae4_slot0_22_8, + OPERAND_fld_ae4_slot0_3_0, + OPERAND_fld_ae4_slot0_3_1, + OPERAND_fld_ae4_slot0_4_4, + OPERAND_fld_ae4_slot0_7_4, + OPERAND_fld_ae4_slot1_22_0, + OPERAND_fld_ae4_slot1_22_12, + OPERAND_fld_ae4_slot1_22_13, + OPERAND_fld_ae4_slot1_22_16, + OPERAND_fld_ae4_slot1_22_17, + OPERAND_fld_ae4_slot1_22_18, + OPERAND_fld_ae4_slot1_22_8, + OPERAND_fld_ae4_slot1_3_0, + OPERAND_fld_ae4_slot1_3_1, + OPERAND_fld_ae4_slot1_7_4, + OPERAND_fld_ae4_slot2_23_0, + OPERAND_fld_ae4_slot2_23_12, + OPERAND_fld_ae4_slot2_23_15, + OPERAND_fld_ae4_slot2_23_17, + OPERAND_fld_ae4_slot2_23_20, + OPERAND_fld_ae4_slot2_4_0, + OPERAND_fld_ae4_slot2_9_5, + OPERAND_fld_ae4_slot3_14_10, + OPERAND_fld_ae4_slot3_19_15, + OPERAND_fld_ae4_slot3_19_19, + OPERAND_fld_ae4_slot3_19_5, + OPERAND_fld_ae4_slot3_27_20, + OPERAND_fld_ae4_slot3_27_25, + OPERAND_fld_ae4_slot3_27_3, + OPERAND_fld_ae4_slot3_2_0, + OPERAND_fld_ae4_slot3_9_0, + OPERAND_fld_ae4_slot3_9_5, + OPERAND_fld_ae4_slot4_22_0, + OPERAND_fld_ae4_slot4_22_15, + OPERAND_fld_ae4_slot4_22_20, + OPERAND_fld_ae4_slot4_9_5, + OPERAND_fld_Inst_11_8, + OPERAND_fld_Inst_12_12, + OPERAND_fld_Inst_12_8, + OPERAND_fld_Inst_13_8, + OPERAND_fld_Inst_15_12, + OPERAND_fld_Inst_19_17, + OPERAND_fld_Inst_19_18, + OPERAND_fld_Inst_23_12, + OPERAND_fld_Inst_23_16, + OPERAND_fld_Inst_4_4, + OPERAND_fld_Inst_5_4, + OPERAND_fld_Inst_7_4, + OPERAND_fld_Inst_7_6, + OPERAND_fld_Inst_7_7, + OPERAND_fld_Inst_9_8, + OPERAND_s3to1 +}; + + +/* Iclass table. */ + +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSRING }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { OPERAND_ars_entry }, 's' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm12x8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { OPERAND_simm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ai4const }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_simm7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8x256 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_label12 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sae }, 'i' }, + { { OPERAND_op2p1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { OPERAND_soffset }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_uimm16x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_simm12b }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ex_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ex_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_getex_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_getex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clrex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_simcall_args[] = { + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimmrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { OPERAND_sas }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_msalp32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sargt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { + { { STATE_LEND }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { + { { STATE_LEND }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { + { { STATE_LEND }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { + { { STATE_LCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MEMCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MEMCTL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MEMCTL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'i' }, + { { STATE_VECBASELOCK }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'm' }, + { { STATE_VECBASELOCK }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'm' }, + { { STATE_VECBASELOCK }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpucfg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpucfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUNUMENTRIES }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpucfg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpucfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUNUMENTRIES }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_salt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_opmode_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_opmode_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_OPMODEECCFENCE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_opmode_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_opmode_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_OPMODEECCFENCE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_opmode_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_opmode_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_OPMODEECCFENCE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_mul16_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_EPC5 }, 'i' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_EPS3 }, 'i' }, + { { STATE_EPS4 }, 'i' }, + { { STATE_EPS5 }, 'i' }, + { { STATE_EPS6 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTERRUPT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { OPERAND_imms }, 'i' }, + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC5 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_VECBASE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_bs }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { + { { OPERAND_bs }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_brall }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_brall }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_brall }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdcw_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdcw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldcw_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldcw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_stateArgs[] = { + { { STATE_PREFCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_stateArgs[] = { + { { STATE_PREFCTL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_stateArgs[] = { + { { STATE_PREFCTL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cacheadrdis_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cacheadrdis_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CACHEADRDIS }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cacheadrdis_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cacheadrdis_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CACHEADRDIS }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cacheadrdis_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cacheadrdis_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CACHEADRDIS }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb0_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wptlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wptlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'm' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_MPULOCK }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpuenb_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpuenb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpuenb_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpuenb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'm' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_MPULOCK }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_mpuenb_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_mpuenb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'm' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_MPULOCK }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ERACCESS }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ERACCESS }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ERACCESS }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { + { { STATE_ERACCESS }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_ERI_RAW_INTERLOCK }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = { + INTERFACE_ERI_RD_In, + INTERFACE_ERI_RD_Out +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { + { { STATE_ERACCESS }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_ERI_RAW_INTERLOCK }, 'o' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = { + INTERFACE_ERI_WR_In, + INTERFACE_ERI_WR_Out +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_1_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_2_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_3_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_sext16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_zext16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_zext8_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_clamps16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_fcr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fcr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = { + { { STATE_RoundMode }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_fsr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = { + { { STATE_InvalidFlag }, 'i' }, + { { STATE_DivZeroFlag }, 'i' }, + { { STATE_OverflowFlag }, 'i' }, + { { STATE_UnderflowFlag }, 'i' }, + { { STATE_InexactFlag }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fsr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = { + { { STATE_InvalidFlag }, 'o' }, + { { STATE_DivZeroFlag }, 'o' }, + { { STATE_OverflowFlag }, 'o' }, + { { STATE_UnderflowFlag }, 'o' }, + { { STATE_InexactFlag }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { + INTERFACE_IMPWIRE +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'i' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'o' }, + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = { + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = { + { { STATE_AE_BITHEAD }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_TABLESIZE }, 'i' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = { + { { STATE_AE_BITPTR }, 'o' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cw_sd_no_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cw_sd_no_stateArgs[] = { + { { STATE_AE_CWRAP }, 'i' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cw_sd_no_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cw_sd_no_stateArgs[] = { + { { STATE_AE_CWRAP }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin0_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin0_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend0_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend0_stateArgs[] = { + { { STATE_AE_CEND0 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin1_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend1_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin2_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend2_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_OVERFLOW_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_OVERFLOW_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_OVERFLOW_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_OVERFLOW_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SAR_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SAR_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SAR_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SAR_stateArgs[] = { + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITPTR_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITPTR_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITPTR_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITPTR_stateArgs[] = { + { { STATE_AE_BITPTR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITSUSED_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITSUSED_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITSUSED_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITSUSED_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_TABLESIZE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_TABLESIZE_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_TABLESIZE_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_TABLESIZE_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_FIRST_TS_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_FIRST_TS_stateArgs[] = { + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_FIRST_TS_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_FIRST_TS_stateArgs[] = { + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_NEXTOFFSET_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_NEXTOFFSET_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_NEXTOFFSET_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_NEXTOFFSET_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SEARCHDONE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SEARCHDONE_stateArgs[] = { + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SEARCHDONE_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SEARCHDONE_stateArgs[] = { + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_CWRAP_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_CWRAP_stateArgs[] = { + { { STATE_AE_CWRAP }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_CWRAP_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_CWRAP_stateArgs[] = { + { { STATE_AE_CWRAP }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4U_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4U_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4U_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4U_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4U_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4U_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64neg }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RI_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64half }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_I_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_IP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_X_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_XP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_I_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_IP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_X_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_XP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_I_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_IP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_X_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_XP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4UX2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4UX2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4UX2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4UX2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4UX2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4UX2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4UX2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4UX2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_I_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_IP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_X_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_XP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ZALIGN64_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_ZALIGN64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LALIGN64_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LALIGN64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SALIGN64_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SALIGN64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVALIGN_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_vu }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVALIGN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA64_PP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA64_PP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8NEG_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8NEG_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64POS_FP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64POS_FP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64NEG_FP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64NEG_FP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDICIRC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_end }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_I_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_X_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_I_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_X_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RA64S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24X2RA64S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S24X2RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RA32S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RA32S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDBRBA32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_aoe }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ab }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ai }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_L_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BITSWAP_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_aoe }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ab }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32JS_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32JS_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32JS_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32JS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_H_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_H_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_L_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDRNG32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBRNG32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RNG32X2_args[] = { + { { OPERAND_opnd_ae_sem_rng_d }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RNG32X2_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_immed }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_N_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_immed_N }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_N_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHORTSWAP_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHORTSWAP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAB4_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAB2_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAB_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA1X2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVB2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVB4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT16X4_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF16X4_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT32X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF32X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARA7X2_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARA7X2_stateArgs[] = { + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARD7_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARD7_stateArgs[] = { + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVASAR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_MOVASAR_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVI_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_movi_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24A32X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24A32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT16X4_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT16X4_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_10_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_10_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_10_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_10_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LL_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LH_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HL_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HH_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24Q48X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24Q48X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32X2F64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32X2F64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32X2F64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32X2F64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32F64S_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32F64S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32F64S_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32F64S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP16_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SSYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SSYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SSYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SSYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2SYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2SYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2ASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2ASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24SYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24SYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24ASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24ASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOV_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT64_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF64_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56A32S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56A32S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48A32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48A32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64A32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64A32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64F32_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64F32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT48S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT48S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATQ56S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT24S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCQ32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCQ32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48SYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48SYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48ASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48ASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32Q48_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32Q48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_3_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_1_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_0_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRA64_32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRA64_32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR32_args[] = { + { { OPERAND_opnd_ae_sem_pks_d }, 'm' }, + { { OPERAND_opnd_ae_sem_pks_s }, 'i' }, + { { OPERAND_opnd_ae_sem_pks_pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR24_args[] = { + { { OPERAND_opnd_ae_sem_pks_d }, 'm' }, + { { OPERAND_opnd_ae_sem_pks_s }, 'i' }, + { { OPERAND_opnd_ae_sem_pks_pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR24_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSRF32_args[] = { + { { OPERAND_opnd_ae_sem_pks_d }, 'm' }, + { { OPERAND_opnd_ae_sem_pks_s }, 'i' }, + { { OPERAND_opnd_ae_sem_pks_pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSRF32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR16_args[] = { + { { OPERAND_opnd_ae_sem_pks_d }, 'm' }, + { { OPERAND_opnd_ae_sem_pks_s }, 'i' }, + { { OPERAND_opnd_ae_sem_pks_pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR16_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD24S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB24S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG24S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS24S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG16S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS16S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16JS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16JS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16JS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16JS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16JS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16JS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16JS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16JS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT16_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE16_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ16_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINMAX32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINMAX32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINMAX16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINMAX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSQ56S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBSQ56S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEGSQ56S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEGSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABSSQ56S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABSSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_AND_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_AND_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NAND_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NAND_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_OR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_OR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_XOR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_XOR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16R_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32R_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI16S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA16S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16RS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32RS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASQ56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLSQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLSQ56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRASQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRASQ56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAAQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAAQ56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLAQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLAQ56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAAQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAAQ56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS64_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS64_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAISQ56S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAISQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASSQ56S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAASQ56S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAASQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT64_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE64_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ64_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA64_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ16_0_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ16_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ32_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32U_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32U_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32U_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32U_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32U_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32U_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_33_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_33_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_21_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_21_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_31_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_31_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_30_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_30_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_10_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_10_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_20_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_20_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_11_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_11_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_33_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_33_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_21_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_21_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_31_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_31_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_30_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_30_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_10_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_10_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_20_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_20_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_11_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_11_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_33_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_33_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_21_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_21_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_31_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_31_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_30_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_30_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_10_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_10_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_20_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_20_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_11_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_11_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16S_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16S_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16S_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16S_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16S_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16S_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2R_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2R_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2R_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2TS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2TS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2TS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2TS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2TS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2TS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC24RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC24RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC24RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC24RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16X4SS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16X4SS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16X4SS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16X4SS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16X4SS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16X4SS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC16RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC16RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC16RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC16RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16JS_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16JS_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG16RAS_S1_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_vs }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG16RAS_S1_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG16RAS_S2_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_vs }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG16RAS_S2_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CONJ16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CONJ16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAFQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAFQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAFQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAFQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16_00_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16_00_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_H_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHA32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_aoe }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ai }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL32T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL32T_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16T_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IP_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IP_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC1_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDSHT_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDSHT_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_opnd_ae_sem_lb_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ae_sem_lb_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBS_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBS_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBSI_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_opnd_ae_sem_lb_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBSI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ARDECNORM16_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_opnd_AE_ARDECNORM16_ar_u }, 'm' }, + { { OPERAND_arr }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL32T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL32T_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL16T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL16T_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC1_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC1_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IP_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IP_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IP_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAE_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ei }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAE_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEA_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_eo }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ar_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEEP_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_eo }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ei }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEEP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT72_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ep1 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ep1 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72X64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72X64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72X64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72X64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32EP_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32EP_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32EP_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32EP_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32EP_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32EP_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32USEP_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32USEP_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32USEP_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32USEP_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI72_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_e }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI72_args[] = { + { { OPERAND_opnd_ae_sem_shift_e }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_e }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16SI_N_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_uimm2x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16UI_N_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_uimm2x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16I_N_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_uimm2x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LALIGN128_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LALIGN128_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SALIGN128_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SALIGN128_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA128_PP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA128_PP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA128POS_FP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA128POS_FP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X4S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X4S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X4U_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X4U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS8S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG8S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD8S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB8S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_art }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_art }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_art }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU16X4_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU16X4_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT32X2_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT32X2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU32X2_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU32X2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT8X8X16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT8X8X16_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU8X8X16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU8X8X16_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT8X4X32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT8X4X32_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU8X4X32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU8X4X32_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X8F16SSYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X8F16SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X8F16SASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X8F16SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X4F32SSYM_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X4F32SSYM_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X4F32SASYM_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X4F32SASYM_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA8_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD8_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDX2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDX2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32J_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32J_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW8U_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW8U_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW8U_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_HL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_HL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_HL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_HL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_HL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_HL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2R_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2R_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2R_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2R_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2R_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2R_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2R_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2R_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2R_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2R_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2R_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2R_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2P32X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2P32X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS2P32X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS2P32X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2P32X4T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2P32X4T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS2P32X4T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS2P32X4T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA32X2_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA32X2_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS32X2_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS32X2_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA32X2_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA32X2_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32X2_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32X2_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULCJ32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULCJ32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULACJ32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULACJ32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULADDF32RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULADDF32RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULADDF32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULADDF32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSUBF32RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSUBF32RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSUBF32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSUBF32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULCJ32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULCJ32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULACJ32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULACJ32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2D32X2WS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2D32X2WS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2C16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2C16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2C16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2C16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ16RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ16RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ16RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ16RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD16X16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD16X16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA2D16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA2D16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA2D16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA2D16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS2D16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS2D16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS2D16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS2D16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA2D16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA2D16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA2D16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA2D16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS2D16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS2D16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS2D16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS2D16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD16X16X4WS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD16X16X4WS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q16X8_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q16X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q16X8_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q16X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q8_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q8_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULPC32X16X2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULPC32X16X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAPC32X16X2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAPC32X16X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFPC32X16X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFPC32X16X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFPC32X16X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFPC32X16X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFPCJ32X16X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFPCJ32X16X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFPCJ32X16X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFPCJ32X16X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2Q32X16_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2Q32X16_FIR_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2Q32X16_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2Q32X16_FIR_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2Q32X16_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2Q32X16_FIR_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2Q32X16_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2Q32X16_FIR_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI8_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI8R_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI8R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI8_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI8_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI8S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA8_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA8_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA8S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA8RS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA8RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA8S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI16_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI16_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA16_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA16_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16SYM_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16SYM_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16SYMS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16SYMS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32SYM_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32SYM_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32SYMS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32SYMS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAV16RS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAV16RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAV32RS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAV32RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8S_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8S_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8S_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8S_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8U_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8U_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8U_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8US_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8US_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8US_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8US_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8U_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8U_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8U_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8US_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8US_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8US_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8US_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16S_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16S_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16U_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16US_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16US_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16U_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16US_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16US_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8S_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8S_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8U_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8US_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8US_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8U_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8US_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8US_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL8X8_args[] = { + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHFL8X8_args[] = { + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHFL8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16X4_args[] = { + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHFL16X4_args[] = { + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHFL16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DSEL8X8_args[] = { + { { OPERAND_opnd_ae_sem_select_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DSEL8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DSEL16X4_args[] = { + { { OPERAND_opnd_ae_sem_select_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DSEL16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL8X8I_args[] = { + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_isel }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL8X8I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMAX8X8_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMAX8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMIN8X8_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMIN8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMAX16X4_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMAX16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMIN16X4_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMIN16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SORT16X4_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SORT16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD8X8_H_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD8X8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA8X8_H_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'm' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA8X8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD8X8_L_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD8X8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA8X8_L_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'm' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA8X8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD16X4_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA16X4_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'm' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX8X8_H_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX8X8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX8X8_L_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX8X8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN8X8_H_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN8X8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN8X8_L_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN8X8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX16X4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN16X4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX32X2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN32X2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDINV16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDINV16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDINV32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDINV32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT16X8_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT16X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT8X16_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT8X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT8X16_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT8X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBD1X4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBD1X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBD1X2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBD1X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVNEG32S_T_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVNEG32S_T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDEXT_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDEXT_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVADEXT_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_a }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVADEXT_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVADEXT_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_a }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVADEXT_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA16X4_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_d }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ32X4_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_d }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ32X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA32X4_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_d }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA32X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI16X4F32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI16X4F32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI16X4F64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI16X4F64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16X4F32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16X4F32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16X4F64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16X4F64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDC32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDC32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBC32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBC32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDC32U_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDC32U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBC32U_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBC32U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPADD16_H_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPADD16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPSUB16_H_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPSUB16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPADD16_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPADD16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPSUB16_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPSUB16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCEXP32_H_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCEXP32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCEXP32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCEXP32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG16_args[] = { + { { OPERAND_opnd_ae_sem_rng_a }, 'o' }, + { { OPERAND_opnd_ae_sem_rng_art }, 'o' }, + { { OPERAND_opnd_ae_sem_rng_i2 }, 'i' }, + { { OPERAND_opnd_ae_sem_rng_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG16_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG32_args[] = { + { { OPERAND_opnd_ae_sem_rng_a }, 'o' }, + { { OPERAND_opnd_ae_sem_rng_art }, 'o' }, + { { OPERAND_opnd_ae_sem_rng_i2 }, 'i' }, + { { OPERAND_opnd_ae_sem_rng_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RNG32X4_args[] = { + { { OPERAND_opnd_ae_sem_rng_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_rng_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RNG32X4_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAV8X8X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAV8X8X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAV16X4X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAV16X4X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAV8X8X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAV8X8X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAV16X4X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAV16X4X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVZBVCDR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVZBVCDR_stateArgs[] = { + { { STATE_AE_ZBIASV8 }, 'o' }, + { { STATE_AE_ZBIASC8 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDRZBVC_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDRZBVC_stateArgs[] = { + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAVUNSQZ8X8_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAVUNSQZ8X8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAVUNSQZ16X4_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAVUNSQZ16X4_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_HL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_HL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_HL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_HL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB3X3O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB3X3O8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB3X3O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB3X3O8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB8Q8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB8Q8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB4O8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB4O8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB8Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB8Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB8Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB8Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB4O8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB4O8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB4O8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB4O8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB3X3O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB3X3O8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB3X3O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB3X3O8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_L_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_L_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_H_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_L_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_L_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_H_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVFCRFSRV_args[] = { + { { OPERAND_opnd_ae_sem_movfpstate_v }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVFCRFSRV_stateArgs[] = { + { { STATE_RoundMode }, 'o' }, + { { STATE_InvalidFlag }, 'o' }, + { { STATE_DivZeroFlag }, 'o' }, + { { STATE_OverflowFlag }, 'o' }, + { { STATE_UnderflowFlag }, 'o' }, + { { STATE_InexactFlag }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVVFCRFSR_args[] = { + { { OPERAND_opnd_ae_sem_movfpstate_v }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_MOVVFCRFSR_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_InvalidFlag }, 'i' }, + { { STATE_DivZeroFlag }, 'i' }, + { { STATE_OverflowFlag }, 'i' }, + { { STATE_UnderflowFlag }, 'i' }, + { { STATE_InexactFlag }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVT_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVT_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVF_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVF_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVEQZ_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVEQZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVNEZ_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVNEZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVGEZ_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVGEZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVLTZ_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVLTZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RFR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RFR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WFR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_WFR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBN_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBN_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_S_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_S_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'm' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_S_stateArgs[] = { + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vsM }, 'm' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vsM }, 'm' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MIN_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MIN_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAX_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAX_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUX_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUX_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUX_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUX_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_art }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_art }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_SX2_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_SX2_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_SX2_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_SX2_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FICEIL_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FICEIL_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIFLOOR_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIFLOOR_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIRINT_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIRINT_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIROUND_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIROUND_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FITRUNC_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FITRUNC_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_SX2_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_SX2_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_SX2_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_SX2_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_S_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_S_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_S_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_S_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_S_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CLSFY_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CLSFY_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUM_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUM_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUM_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUM_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDANDSUB_S_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDANDSUB_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDANDSUBJC_S_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDANDSUBJC_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_HL_LH_S_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_HL_LH_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDA_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDA_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FREXP_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vsM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FREXP_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOATEXP_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOATEXP_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUMABS_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUMABS_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUMABS_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUMABS_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUXQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUXQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUXQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUXQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMAXNUM_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMAXNUM_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMINNUM_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMINNUM_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMAXNUMABS_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMAXNUMABS_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMINNUMABS_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMINNUMABS_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_SX2X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_SX2X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_SX2X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_SX2X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_SX2X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUX_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUX_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUX_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUX_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'm' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'm' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CLSFY_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CLSFY_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_H_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_H_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MIN_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MIN_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAX_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAX_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUM_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUM_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUM_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUM_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_H_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FICEIL_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FICEIL_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIFLOOR_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIFLOOR_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIRINT_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIRINT_H_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIROUND_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIROUND_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FITRUNC_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FITRUNC_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vs }, 'm' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP0_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP0_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT16_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT16_H_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT16_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT16_H_stateArgs[] = { + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC16_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_art }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC16_H_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC16_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_art }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC16_H_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT16_HX4_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT16_HX4_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT16_HX4_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT16_HX4_stateArgs[] = { + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC16_HX4_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC16_HX4_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC16_HX4_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC16_HX4_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBN_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBN_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_H_stateArgs[] = { + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RMINNUM_H_args[] = { + { { OPERAND_opnd_ae_sem_hprminmaxnum_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hprminmaxnum_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RMINNUM_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RMAXNUM_H_args[] = { + { { OPERAND_opnd_ae_sem_hprminmaxnum_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hprminmaxnum_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RMAXNUM_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_HX4X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_HX4X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_HX4X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_HX4X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_HX4X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULQ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULQ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDQ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDQ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULCNVH_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULCNVH_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULACNVH_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULACNVH_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULCNVL_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULCNVL_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULACNVL_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULACNVL_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_iclass_internal iclasses[] = { + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_threadptr_args, + 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, + { 1, Iclass_wur_threadptr_args, + 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_loop_args, + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_loopz_args, + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32ex_args, + 1, Iclass_xt_iclass_l32ex_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_s32ex_args, + 1, Iclass_xt_iclass_s32ex_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_getex_args, + 1, Iclass_xt_iclass_getex_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_clrex */, + 1, Iclass_xt_iclass_clrex_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_simcall_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32nb_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lend_args, + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lend_args, + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lend_args, + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lcount_args, + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lcount_args, + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lcount_args, + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lbeg_args, + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lbeg_args, + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lbeg_args, + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_memctl_args, + 3, Iclass_xt_iclass_rsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_memctl_args, + 3, Iclass_xt_iclass_wsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_memctl_args, + 3, Iclass_xt_iclass_xsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid0_args, + 2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_configid0_args, + 2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid1_args, + 2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc3_args, + 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc3_args, + 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc3_args, + 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave3_args, + 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave3_args, + 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave3_args, + 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc4_args, + 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc4_args, + 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc4_args, + 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave4_args, + 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave4_args, + 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave4_args, + 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc5_args, + 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc5_args, + 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc5_args, + 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave5_args, + 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave5_args, + 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave5_args, + 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc6_args, + 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc6_args, + 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc6_args, + 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave6_args, + 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave6_args, + 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave6_args, + 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps3_args, + 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps3_args, + 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps3_args, + 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps4_args, + 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps4_args, + 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps4_args, + 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps5_args, + 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps5_args, + 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps5_args, + 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps6_args, + 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps6_args, + 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps6_args, + 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc0_args, + 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc0_args, + 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc0_args, + 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc1_args, + 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc1_args, + 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc1_args, + 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc2_args, + 3, Iclass_xt_iclass_rsr_misc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc2_args, + 3, Iclass_xt_iclass_wsr_misc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc2_args, + 3, Iclass_xt_iclass_xsr_misc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc3_args, + 3, Iclass_xt_iclass_rsr_misc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc3_args, + 3, Iclass_xt_iclass_wsr_misc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc3_args, + 3, Iclass_xt_iclass_xsr_misc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_vecbase_args, + 4, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_vecbase_args, + 4, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_vecbase_args, + 4, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_mpucfg_args, + 3, Iclass_xt_iclass_rsr_mpucfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mpucfg_args, + 3, Iclass_xt_iclass_wsr_mpucfg_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_salt_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_opmode_args, + 3, Iclass_xt_iclass_rsr_opmode_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_opmode_args, + 3, Iclass_xt_iclass_wsr_opmode_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_opmode_args, + 3, Iclass_xt_iclass_xsr_opmode_stateArgs, 0, 0 }, + { 3, Iclass_xt_mul16_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 19, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka0_args, + 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka0_args, + 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka0_args, + 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc0_args, + 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc0_args, + 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc0_args, + 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka1_args, + 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka1_args, + 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka1_args, + 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc1_args, + 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc1_args, + 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc1_args, + 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka0_args, + 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka0_args, + 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka0_args, + 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka1_args, + 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka1_args, + 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka1_args, + 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreakenable_args, + 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreakenable_args, + 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreakenable_args, + 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_lddr32_p_args, + 5, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sddr32_p_args, + 4, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfdo_args, + 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 2, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mmid_args, + 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_bbool1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbranch_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bmove_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_RSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_WSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_XSR_BR_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare1_args, + 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare1_args, + 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare1_args, + 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare2_args, + 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare2_args, + 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare2_args, + 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_lock_args, + 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_inv_args, + 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_licx_args, + 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sicx_args, + 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_dcache_dyn_args, + 2, Iclass_xt_iclass_dcache_dyn_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_ind_args, + 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_inv_args, + 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dpf_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_lock_args, + 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sdct_args, + 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ldct_args, + 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sdcw_args, + 2, Iclass_xt_iclass_sdcw_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ldcw_args, + 2, Iclass_xt_iclass_ldcw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prefctl_args, + 1, Iclass_xt_iclass_rsr_prefctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_prefctl_args, + 1, Iclass_xt_iclass_wsr_prefctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_prefctl_args, + 1, Iclass_xt_iclass_xsr_prefctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cacheadrdis_args, + 4, Iclass_xt_iclass_wsr_cacheadrdis_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cacheadrdis_args, + 3, Iclass_xt_iclass_rsr_cacheadrdis_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cacheadrdis_args, + 4, Iclass_xt_iclass_xsr_cacheadrdis_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rptlb0_args, + 3, Iclass_xt_iclass_rptlb0_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rptlb_args, + 2, Iclass_xt_iclass_rptlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_wptlb_args, + 5, Iclass_xt_iclass_wptlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_mpuenb_args, + 3, Iclass_xt_iclass_rsr_mpuenb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mpuenb_args, + 5, Iclass_xt_iclass_wsr_mpuenb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_mpuenb_args, + 5, Iclass_xt_iclass_xsr_mpuenb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cpenable_args, + 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cpenable_args, + 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cpenable_args, + 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_clamp_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_minmax_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_sx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32ai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32ri_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_atomctl_args, + 4, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_atomctl_args, + 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_atomctl_args, + 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_div_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eraccess_args, + 3, Iclass_xt_iclass_rsr_eraccess_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eraccess_args, + 3, Iclass_xt_iclass_wsr_eraccess_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eraccess_args, + 3, Iclass_xt_iclass_xsr_eraccess_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rer_args, + 4, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs }, + { 2, Iclass_xt_iclass_wer_args, + 4, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs }, + { 2, Iclass_xt_iclass_wb15_0_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_1_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_2_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_3_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_4_args, + 0, 0, 0, 0 }, + { 2, Iclass_ic_sext16_args, + 0, 0, 0, 0 }, + { 2, Iclass_ic_zext16_args, + 0, 0, 0, 0 }, + { 2, Iclass_ic_zext8_args, + 0, 0, 0, 0 }, + { 2, Iclass_ic_clamps16_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_fcr_args, + 2, Iclass_rur_fcr_stateArgs, 0, 0 }, + { 1, Iclass_wur_fcr_args, + 2, Iclass_wur_fcr_stateArgs, 0, 0 }, + { 1, Iclass_rur_fsr_args, + 6, Iclass_rur_fsr_stateArgs, 0, 0 }, + { 1, Iclass_wur_fsr_args, + 6, Iclass_wur_fsr_stateArgs, 0, 0 }, + { 1, Iclass_iclass_READ_IMPWIRE_args, + 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, + { 1, Iclass_iclass_SETB_EXPSTATE_args, + 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, + { 1, Iclass_iclass_CLRB_EXPSTATE_args, + 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, + { 2, Iclass_iclass_WRMSK_EXPSTATE_args, + 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_ovf_sar_args, + 3, Iclass_rur_ae_ovf_sar_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_ovf_sar_args, + 3, Iclass_wur_ae_ovf_sar_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_bithead_args, + 2, Iclass_rur_ae_bithead_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_bithead_args, + 2, Iclass_wur_ae_bithead_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_ts_fts_bu_bp_args, + 5, Iclass_rur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_ts_fts_bu_bp_args, + 5, Iclass_wur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cw_sd_no_args, + 4, Iclass_rur_ae_cw_sd_no_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cw_sd_no_args, + 4, Iclass_wur_ae_cw_sd_no_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cbegin0_args, + 2, Iclass_rur_ae_cbegin0_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cbegin0_args, + 2, Iclass_wur_ae_cbegin0_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cend0_args, + 2, Iclass_rur_ae_cend0_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cend0_args, + 2, Iclass_wur_ae_cend0_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cbegin1_args, + 2, Iclass_rur_ae_cbegin1_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cbegin1_args, + 2, Iclass_wur_ae_cbegin1_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cend1_args, + 2, Iclass_rur_ae_cend1_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cend1_args, + 2, Iclass_wur_ae_cend1_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cbegin2_args, + 2, Iclass_rur_ae_cbegin2_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cbegin2_args, + 2, Iclass_wur_ae_cbegin2_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cend2_args, + 2, Iclass_rur_ae_cend2_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cend2_args, + 2, Iclass_wur_ae_cend2_stateArgs, 0, 0 }, + { 1, Iclass_rur_expstate_args, + 1, Iclass_rur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_wur_expstate_args, + 1, Iclass_wur_expstate_stateArgs, 0, 0 }, + { 1, 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0, 0 }, + { 3, Iclass_AE_S8_0_IP_args, + 1, Iclass_AE_S8_0_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S8_0_X_args, + 1, Iclass_AE_S8_0_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S8_0_XP_args, + 1, Iclass_AE_S8_0_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S64_XC_args, + 3, Iclass_AE_S64_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S64_XC1_args, + 3, Iclass_AE_S64_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S64_I_args, + 1, Iclass_AE_S64_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S64_IP_args, + 1, Iclass_AE_S64_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S64_X_args, + 1, Iclass_AE_S64_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S64_XP_args, + 1, Iclass_AE_S64_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32M_XC_args, + 3, Iclass_AE_S32M_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32M_I_args, + 1, Iclass_AE_S32M_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32M_IU_args, + 1, Iclass_AE_S32M_IU_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32M_X_args, + 1, Iclass_AE_S32M_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32M_XU_args, + 1, Iclass_AE_S32M_XU_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2_XC2_args, + 3, Iclass_AE_L32X2_XC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X4_XC2_args, + 3, Iclass_AE_L16X4_XC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8X8_XC2_args, + 3, Iclass_AE_L8X8_XC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_L64_XC2_args, + 3, Iclass_AE_L64_XC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2_XC2_args, + 3, Iclass_AE_S32X2_XC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_XC2_args, + 3, Iclass_AE_S16X4_XC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_S8X8_XC2_args, + 3, Iclass_AE_S8X8_XC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_S64_XC2_args, + 3, Iclass_AE_S64_XC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4RNG_I_args, + 2, Iclass_AE_S16X4RNG_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4RNG_IP_args, + 2, Iclass_AE_S16X4RNG_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4RNG_X_args, + 2, Iclass_AE_S16X4RNG_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4RNG_XP_args, + 2, Iclass_AE_S16X4RNG_XP_stateArgs, 0, 0 }, + { 4, Iclass_AE_L32X2X2_XC_args, + 3, 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Iclass_AE_S16X4X2RNG_I_args, + 2, Iclass_AE_S16X4X2RNG_I_stateArgs, 0, 0 }, + { 4, Iclass_AE_S16X4X2RNG_IP_args, + 2, Iclass_AE_S16X4X2RNG_IP_stateArgs, 0, 0 }, + { 4, Iclass_AE_S16X4X2RNG_X_args, + 2, Iclass_AE_S16X4X2RNG_X_stateArgs, 0, 0 }, + { 4, Iclass_AE_S16X4X2RNG_XP_args, + 2, Iclass_AE_S16X4X2RNG_XP_stateArgs, 0, 0 }, + { 1, Iclass_AE_ZALIGN64_args, + 1, Iclass_AE_ZALIGN64_stateArgs, 0, 0 }, + { 3, Iclass_AE_LALIGN64_I_args, + 1, Iclass_AE_LALIGN64_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_SALIGN64_I_args, + 1, Iclass_AE_SALIGN64_I_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVALIGN_args, + 1, Iclass_AE_MOVALIGN_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA64_PP_args, + 1, Iclass_AE_LA64_PP_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24POS_PC_args, + 3, Iclass_AE_LA24POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24NEG_PC_args, + 3, Iclass_AE_LA24NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24POS_PC1_args, + 3, Iclass_AE_LA24POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24NEG_PC1_args, + 3, Iclass_AE_LA24NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24X2POS_PC_args, + 3, Iclass_AE_LA24X2POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24X2NEG_PC_args, + 3, Iclass_AE_LA24X2NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24X2POS_PC1_args, + 3, Iclass_AE_LA24X2POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24X2NEG_PC1_args, + 3, Iclass_AE_LA24X2NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2POS_PC_args, + 3, Iclass_AE_LA32X2POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2NEG_PC_args, + 3, Iclass_AE_LA32X2NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2POS_PC1_args, + 3, Iclass_AE_LA32X2POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2NEG_PC1_args, + 3, Iclass_AE_LA32X2NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2POS_PC2_args, + 3, Iclass_AE_LA32X2POS_PC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4POS_PC_args, + 3, Iclass_AE_LA16X4POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4NEG_PC_args, + 3, Iclass_AE_LA16X4NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4POS_PC1_args, + 3, Iclass_AE_LA16X4POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4NEG_PC1_args, + 3, Iclass_AE_LA16X4NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4POS_PC2_args, + 3, Iclass_AE_LA16X4POS_PC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8POS_PC_args, + 3, Iclass_AE_LA8X8POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8NEG_PC_args, + 3, Iclass_AE_LA8X8NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8POS_PC1_args, + 3, Iclass_AE_LA8X8POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8NEG_PC1_args, + 3, Iclass_AE_LA8X8NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8POS_PC2_args, + 3, Iclass_AE_LA8X8POS_PC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2X2POS_PC_args, + 3, Iclass_AE_LA32X2X2POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2X2POS_PC1_args, + 3, Iclass_AE_LA32X2X2POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2X2POS_PC2_args, + 3, Iclass_AE_LA32X2X2POS_PC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4X2POS_PC_args, + 3, Iclass_AE_LA16X4X2POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4X2POS_PC1_args, + 3, Iclass_AE_LA16X4X2POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4X2POS_PC2_args, + 3, Iclass_AE_LA16X4X2POS_PC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8X2POS_PC_args, + 3, Iclass_AE_LA8X8X2POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8X2POS_PC1_args, + 3, Iclass_AE_LA8X8X2POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8X2POS_PC2_args, + 3, Iclass_AE_LA8X8X2POS_PC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_SA64POS_FP_args, + 1, Iclass_AE_SA64POS_FP_stateArgs, 0, 0 }, + { 2, Iclass_AE_SA64NEG_FP_args, + 1, Iclass_AE_SA64NEG_FP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IC_args, + 3, Iclass_AE_LA32X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IC1_args, + 3, Iclass_AE_LA32X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IC2_args, + 3, Iclass_AE_LA32X2_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IP_args, + 1, Iclass_AE_LA32X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_RIP_args, + 1, Iclass_AE_LA32X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_RIC_args, + 3, Iclass_AE_LA32X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_RIC1_args, + 3, Iclass_AE_LA32X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IC_args, + 3, Iclass_AE_LA16X4_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IC1_args, + 3, Iclass_AE_LA16X4_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IC2_args, + 3, Iclass_AE_LA16X4_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IP_args, + 1, Iclass_AE_LA16X4_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_RIP_args, + 1, Iclass_AE_LA16X4_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_RIC_args, + 3, Iclass_AE_LA16X4_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_RIC1_args, + 3, Iclass_AE_LA16X4_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_IC_args, + 3, Iclass_AE_LA8X8_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_IC1_args, + 3, Iclass_AE_LA8X8_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_IC2_args, + 3, Iclass_AE_LA8X8_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_IP_args, + 1, Iclass_AE_LA8X8_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_RIP_args, + 1, Iclass_AE_LA8X8_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_RIC_args, + 3, Iclass_AE_LA8X8_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_RIC1_args, + 3, Iclass_AE_LA8X8_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_IC_args, + 3, Iclass_AE_LA32X2F24_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_IC1_args, + 3, Iclass_AE_LA32X2F24_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_IP_args, + 1, Iclass_AE_LA32X2F24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_RIP_args, + 1, Iclass_AE_LA32X2F24_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_RIC_args, + 3, Iclass_AE_LA32X2F24_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_RIC1_args, + 3, Iclass_AE_LA32X2F24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_IC_args, + 3, Iclass_AE_LA24_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_IC1_args, + 3, Iclass_AE_LA24_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_IP_args, + 1, Iclass_AE_LA24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_RIP_args, + 1, Iclass_AE_LA24_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_RIC_args, + 3, Iclass_AE_LA24_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_RIC1_args, + 3, Iclass_AE_LA24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_IC_args, + 3, Iclass_AE_LA24X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_IC1_args, + 3, Iclass_AE_LA24X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_IP_args, + 1, Iclass_AE_LA24X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_RIP_args, + 1, Iclass_AE_LA24X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_RIC_args, + 3, Iclass_AE_LA24X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_RIC1_args, + 3, Iclass_AE_LA24X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IC_args, + 3, Iclass_AE_SA32X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IC1_args, + 3, Iclass_AE_SA32X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IC2_args, + 3, Iclass_AE_SA32X2_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IP_args, + 1, Iclass_AE_SA32X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_RIP_args, + 1, Iclass_AE_SA32X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_RIC_args, + 3, Iclass_AE_SA32X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_RIC1_args, + 3, Iclass_AE_SA32X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IC_args, + 3, Iclass_AE_SA16X4_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IC1_args, + 3, Iclass_AE_SA16X4_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IC2_args, + 3, Iclass_AE_SA16X4_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IP_args, + 1, Iclass_AE_SA16X4_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_RIP_args, + 1, Iclass_AE_SA16X4_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_RIC_args, + 3, Iclass_AE_SA16X4_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_RIC1_args, + 3, Iclass_AE_SA16X4_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_IC_args, + 3, Iclass_AE_SA8X8_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_IC1_args, + 3, Iclass_AE_SA8X8_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_IC2_args, + 3, Iclass_AE_SA8X8_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_IP_args, + 1, Iclass_AE_SA8X8_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_RIP_args, + 1, Iclass_AE_SA8X8_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_RIC_args, + 3, Iclass_AE_SA8X8_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_RIC1_args, + 3, Iclass_AE_SA8X8_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_IC_args, + 3, Iclass_AE_SA32X2F24_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_IC1_args, + 3, Iclass_AE_SA32X2F24_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_IP_args, + 1, Iclass_AE_SA32X2F24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_RIP_args, + 1, Iclass_AE_SA32X2F24_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_RIC_args, + 3, Iclass_AE_SA32X2F24_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_RIC1_args, + 3, Iclass_AE_SA32X2F24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_IC_args, + 3, Iclass_AE_SA24_L_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_IC1_args, + 3, Iclass_AE_SA24_L_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_IP_args, + 1, Iclass_AE_SA24_L_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_RIP_args, + 1, Iclass_AE_SA24_L_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_RIC_args, + 3, Iclass_AE_SA24_L_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_RIC1_args, + 3, Iclass_AE_SA24_L_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_IC_args, + 3, Iclass_AE_SA24X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_IC1_args, + 3, Iclass_AE_SA24X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_IP_args, + 1, Iclass_AE_SA24X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_RIP_args, + 1, Iclass_AE_SA24X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_RIC_args, + 3, Iclass_AE_SA24X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_RIC1_args, + 3, Iclass_AE_SA24X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDICIRC_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_ADDCIRC_XC2_args, + 3, Iclass_AE_ADDCIRC_XC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_ADDCIRC_XC1_args, + 3, Iclass_AE_ADDCIRC_XC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_ADDCIRC_XC_args, + 3, Iclass_AE_ADDCIRC_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_I_args, + 2, Iclass_AE_S32RA64S_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_IP_args, + 2, Iclass_AE_S32RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_X_args, + 2, Iclass_AE_S32RA64S_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_XP_args, + 2, Iclass_AE_S32RA64S_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_XC_args, + 4, Iclass_AE_S32RA64S_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_XC1_args, + 4, Iclass_AE_S32RA64S_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_I_args, + 2, Iclass_AE_S24RA64S_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_IP_args, + 2, Iclass_AE_S24RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_X_args, + 2, Iclass_AE_S24RA64S_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_XP_args, + 2, Iclass_AE_S24RA64S_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_XC_args, + 4, Iclass_AE_S24RA64S_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_XC1_args, + 4, Iclass_AE_S24RA64S_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2RA64S_IP_args, + 2, Iclass_AE_S32X2RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24X2RA64S_IP_args, + 2, Iclass_AE_S24X2RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4RA32S_IP_args, + 2, Iclass_AE_S16X4RA32S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDBRBA32_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_S32X2_L_IP_args, + 1, Iclass_AE_S32X2_L_IP_stateArgs, 0, 0 }, + { 2, Iclass_AE_BITSWAP_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MUL32JS_args, + 1, Iclass_AE_MUL32JS_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUB32S_args, + 2, Iclass_AE_ADDANDSUB32S_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUB32JS_args, + 2, Iclass_AE_ADDANDSUB32JS_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUBRNG32_args, + 2, Iclass_AE_ADDANDSUBRNG32_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUBRNG32_H_args, + 2, Iclass_AE_ADDANDSUBRNG32_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUBRNG32_L_args, + 2, Iclass_AE_ADDANDSUBRNG32_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDRNG32_args, + 2, Iclass_AE_ADDRNG32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUBRNG32_args, + 2, Iclass_AE_SUBRNG32_stateArgs, 0, 0 }, + { 1, Iclass_AE_RNG32X2_args, + 2, Iclass_AE_RNG32X2_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL16I_args, + 1, Iclass_AE_SEL16I_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL16I_N_args, + 1, Iclass_AE_SEL16I_N_stateArgs, 0, 0 }, + { 2, Iclass_AE_SHORTSWAP_args, + 1, Iclass_AE_SHORTSWAP_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAB4_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVAB2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVAB_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVBA_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_MOVBA1X2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVBA4_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVBA2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVB2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVB4_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_MOVT16X4_args, + 1, Iclass_AE_MOVT16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVF16X4_args, + 1, Iclass_AE_MOVF16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVT32X2_args, + 1, Iclass_AE_MOVT32X2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVF32X2_args, + 1, Iclass_AE_MOVF32X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVSARA7X2_args, + 2, Iclass_AE_MOVSARA7X2_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVSARD7_args, + 2, Iclass_AE_MOVSARD7_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVASAR_args, + 2, Iclass_AE_MOVASAR_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVDA32X2_args, + 1, Iclass_AE_MOVDA32X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVDA32_args, + 1, Iclass_AE_MOVDA32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVDA16X2_args, + 1, Iclass_AE_MOVDA16X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVDA16_args, + 1, Iclass_AE_MOVDA16_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVI_args, + 1, Iclass_AE_MOVI_stateArgs, 0, 0 }, + { 3, Iclass_AE_TRUNCP24A32X2_args, + 1, Iclass_AE_TRUNCP24A32X2_stateArgs, 0, 0 }, + { 3, Iclass_AE_SAT16X4_args, + 2, Iclass_AE_SAT16X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT32X2F16_32_args, + 1, Iclass_AE_CVT32X2F16_32_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT32X2F16_10_args, + 1, Iclass_AE_CVT32X2F16_10_stateArgs, 0, 0 }, + { 2, Iclass_AE_SEXT32X2D16_32_args, + 1, Iclass_AE_SEXT32X2D16_32_stateArgs, 0, 0 }, + { 2, Iclass_AE_SEXT32X2D16_10_args, + 1, Iclass_AE_SEXT32X2D16_10_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTA32F24S_L_args, + 1, Iclass_AE_CVTA32F24S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTA32F24S_H_args, + 1, Iclass_AE_CVTA32F24S_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_LL_args, + 1, Iclass_AE_CVTP24A16X2_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_LH_args, + 1, Iclass_AE_CVTP24A16X2_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_HL_args, + 1, Iclass_AE_CVTP24A16X2_HL_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_HH_args, + 1, Iclass_AE_CVTP24A16X2_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_TRUNCP24Q48X2_args, + 1, Iclass_AE_TRUNCP24Q48X2_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCA32X2F64S_args, + 2, Iclass_AE_TRUNCA32X2F64S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCI32X2F64S_args, + 2, Iclass_AE_TRUNCI32X2F64S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCA32F64S_L_args, + 2, Iclass_AE_TRUNCA32F64S_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCI32F64S_L_args, + 2, Iclass_AE_TRUNCI32F64S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCP16_args, + 1, Iclass_AE_TRUNCP16_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F64SSYM_args, + 2, Iclass_AE_ROUND32X2F64SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F64SASYM_args, + 2, Iclass_AE_ROUND32X2F64SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F48SSYM_args, + 2, Iclass_AE_ROUND32X2F48SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F48SASYM_args, + 2, Iclass_AE_ROUND32X2F48SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND16X4F32SSYM_args, + 2, Iclass_AE_ROUND16X4F32SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND16X4F32SASYM_args, + 2, Iclass_AE_ROUND16X4F32SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND24X2F48SSYM_args, + 2, Iclass_AE_ROUND24X2F48SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND24X2F48SASYM_args, + 2, Iclass_AE_ROUND24X2F48SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUNDSP16Q48X2SYM_args, + 2, Iclass_AE_ROUNDSP16Q48X2SYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUNDSP16Q48X2ASYM_args, + 2, Iclass_AE_ROUNDSP16Q48X2ASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_MINABS32S_args, + 2, Iclass_AE_MINABS32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAXABS32S_args, + 2, Iclass_AE_MAXABS32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSP16F24SYM_args, + 2, Iclass_AE_ROUNDSP16F24SYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSP16F24ASYM_args, + 2, Iclass_AE_ROUNDSP16F24ASYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOV_args, + 1, Iclass_AE_MOV_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVT64_args, + 1, Iclass_AE_MOVT64_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVF64_args, + 1, Iclass_AE_MOVF64_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTQ56A32S_args, + 1, Iclass_AE_CVTQ56A32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT48A32_args, + 1, Iclass_AE_CVT48A32_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT64A32_args, + 1, Iclass_AE_CVT64A32_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTQ56P32S_L_args, + 1, Iclass_AE_CVTQ56P32S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTQ56P32S_H_args, + 1, Iclass_AE_CVTQ56P32S_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT64F32_H_args, + 1, Iclass_AE_CVT64F32_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT48F32_L_args, + 1, Iclass_AE_CVT48F32_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT48F32_H_args, + 1, Iclass_AE_CVT48F32_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_SAT48S_args, + 2, Iclass_AE_SAT48S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SATQ56S_args, + 2, Iclass_AE_SATQ56S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SAT24S_args, + 2, Iclass_AE_SAT24S_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCQ32_args, + 1, Iclass_AE_TRUNCQ32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MINABS64S_args, + 2, Iclass_AE_MINABS64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAXABS64S_args, + 2, Iclass_AE_MAXABS64S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSQ32F48SYM_args, + 2, Iclass_AE_ROUNDSQ32F48SYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSQ32F48ASYM_args, + 2, Iclass_AE_ROUNDSQ32F48ASYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCA32Q48_args, + 1, Iclass_AE_TRUNCA32Q48_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD32_L_args, + 1, Iclass_AE_MOVAD32_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD32_H_args, + 1, Iclass_AE_MOVAD32_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_3_args, + 1, Iclass_AE_MOVAD16_3_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_2_args, + 1, Iclass_AE_MOVAD16_2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_1_args, + 1, Iclass_AE_MOVAD16_1_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_0_args, + 1, Iclass_AE_MOVAD16_0_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRA64_32_args, + 1, Iclass_AE_SRA64_32_stateArgs, 0, 0 }, + { 3, Iclass_AE_PKSR32_args, + 2, Iclass_AE_PKSR32_stateArgs, 0, 0 }, + { 3, Iclass_AE_PKSR24_args, + 2, Iclass_AE_PKSR24_stateArgs, 0, 0 }, + { 3, Iclass_AE_PKSRF32_args, + 2, Iclass_AE_PKSRF32_stateArgs, 0, 0 }, + { 3, Iclass_AE_PKSR16_args, + 2, Iclass_AE_PKSR16_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCA16P24S_L_args, + 1, Iclass_AE_TRUNCA16P24S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCA16P24S_H_args, + 1, Iclass_AE_TRUNCA16P24S_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD32_args, + 1, Iclass_AE_ADD32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB32_args, + 1, Iclass_AE_SUB32_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDSUB32_args, + 1, Iclass_AE_ADDSUB32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUBADD32_args, + 1, Iclass_AE_SUBADD32_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD16_args, + 1, Iclass_AE_ADD16_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB16_args, + 1, Iclass_AE_SUB16_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD32_HL_LH_args, + 1, Iclass_AE_ADD32_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDSUB32_HL_LH_args, + 1, Iclass_AE_ADDSUB32_HL_LH_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG32_args, + 1, Iclass_AE_NEG32_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS32_args, + 1, Iclass_AE_ABS32_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG32_L_args, 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0, 0 }, + { 2, Iclass_AE_ABS32S_args, + 1, Iclass_AE_ABS32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG16S_args, + 1, Iclass_AE_NEG16S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS16S_args, + 1, Iclass_AE_ABS16S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS16_args, + 1, Iclass_AE_ABS16_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULC16JS_H_args, + 2, Iclass_AE_MULC16JS_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULC16JS_L_args, + 2, Iclass_AE_MULC16JS_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAC16JS_H_args, + 2, Iclass_AE_MULAC16JS_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAC16JS_L_args, + 2, Iclass_AE_MULAC16JS_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_LT16_args, + 1, Iclass_AE_LT16_stateArgs, 0, 0 }, + { 3, Iclass_AE_LE16_args, + 1, Iclass_AE_LE16_stateArgs, 0, 0 }, + { 3, Iclass_AE_EQ16_args, + 1, Iclass_AE_EQ16_stateArgs, 0, 0 }, + { 3, Iclass_AE_LT32_args, + 1, Iclass_AE_LT32_stateArgs, 0, 0 }, + { 3, Iclass_AE_LE32_args, + 1, Iclass_AE_LE32_stateArgs, 0, 0 }, + { 3, Iclass_AE_EQ32_args, + 1, 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Iclass_AE_SUBW16_args, + 1, Iclass_AE_SUBW16_stateArgs, 0, 0 }, + { 4, Iclass_AE_SUBW32_args, + 1, Iclass_AE_SUBW32_stateArgs, 0, 0 }, + { 4, Iclass_AE_ACCW8_args, + 1, Iclass_AE_ACCW8_stateArgs, 0, 0 }, + { 4, Iclass_AE_ACCW16_args, + 1, Iclass_AE_ACCW16_stateArgs, 0, 0 }, + { 4, Iclass_AE_ACCW32_args, + 1, Iclass_AE_ACCW32_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDW8U_args, + 1, Iclass_AE_ADDW8U_stateArgs, 0, 0 }, + { 4, Iclass_AE_SUBW8U_args, + 1, Iclass_AE_SUBW8U_stateArgs, 0, 0 }, + { 4, Iclass_AE_ACCW8U_args, + 1, Iclass_AE_ACCW8U_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULFP32X2S_HH_LL_args, + 2, Iclass_AE_MULFP32X2S_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAFP32X2S_HH_LL_args, + 2, Iclass_AE_MULAFP32X2S_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSFP32X2S_HH_LL_args, + 2, Iclass_AE_MULSFP32X2S_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULFP32X2S_HL_LH_args, + 2, Iclass_AE_MULFP32X2S_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAFP32X2S_HL_LH_args, + 2, Iclass_AE_MULAFP32X2S_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSFP32X2S_HL_LH_args, + 2, Iclass_AE_MULSFP32X2S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZAAF2D32S_HH_LL_args, + 2, Iclass_AE_MULZAAF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZASF2D32S_HH_LL_args, + 2, Iclass_AE_MULZASF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSAF2D32S_HH_LL_args, + 2, Iclass_AE_MULZSAF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSSF2D32S_HH_LL_args, + 2, Iclass_AE_MULZSSF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAAF2D32S_HH_LL_args, + 2, Iclass_AE_MULAAF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULASF2D32S_HH_LL_args, + 2, Iclass_AE_MULASF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSAF2D32S_HH_LL_args, + 2, Iclass_AE_MULSAF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSSF2D32S_HH_LL_args, + 2, Iclass_AE_MULSSF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZAAF2D32S_HL_LH_args, + 2, Iclass_AE_MULZAAF2D32S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZASF2D32S_HL_LH_args, + 2, Iclass_AE_MULZASF2D32S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSAF2D32S_HL_LH_args, + 2, Iclass_AE_MULZSAF2D32S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSSF2D32S_HL_LH_args, + 2, Iclass_AE_MULZSSF2D32S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAAF2D32S_HL_LH_args, + 2, Iclass_AE_MULAAF2D32S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULASF2D32S_HL_LH_args, + 2, Iclass_AE_MULASF2D32S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSAF2D32S_HL_LH_args, + 2, Iclass_AE_MULSAF2D32S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSSF2D32S_HL_LH_args, + 2, Iclass_AE_MULSSF2D32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32S_HH_args, + 2, Iclass_AE_MUL32S_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA32S_HH_args, + 2, Iclass_AE_MULA32S_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32S_HH_args, + 2, Iclass_AE_MULS32S_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32S_LL_args, + 2, Iclass_AE_MUL32S_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA32S_LL_args, + 2, Iclass_AE_MULA32S_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32S_LL_args, + 2, Iclass_AE_MULS32S_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32S_HL_args, + 2, Iclass_AE_MUL32S_HL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA32S_HL_args, + 2, Iclass_AE_MULA32S_HL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32S_HL_args, + 2, Iclass_AE_MULS32S_HL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32S_LH_args, + 2, Iclass_AE_MUL32S_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA32S_LH_args, + 2, Iclass_AE_MULA32S_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32S_LH_args, + 2, Iclass_AE_MULS32S_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MUL32X2S_HH_LL_args, + 2, Iclass_AE_MUL32X2S_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULA32X2S_HH_LL_args, + 2, Iclass_AE_MULA32X2S_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULS32X2S_HH_LL_args, + 2, Iclass_AE_MULS32X2S_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MUL32X2S_HL_LH_args, + 2, Iclass_AE_MUL32X2S_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULA32X2S_HL_LH_args, + 2, Iclass_AE_MULA32X2S_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULS32X2S_HL_LH_args, + 2, Iclass_AE_MULS32X2S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZAAD32S_HH_LL_args, + 2, Iclass_AE_MULZAAD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZASD32S_HH_LL_args, + 2, Iclass_AE_MULZASD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZSAD32S_HH_LL_args, + 2, Iclass_AE_MULZSAD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZSSD32S_HH_LL_args, + 2, Iclass_AE_MULZSSD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAAD32S_HH_LL_args, + 2, Iclass_AE_MULAAD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULASD32S_HH_LL_args, + 2, Iclass_AE_MULASD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSAD32S_HH_LL_args, + 2, Iclass_AE_MULSAD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSSD32S_HH_LL_args, + 2, Iclass_AE_MULSSD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZAAD32S_HL_LH_args, + 2, Iclass_AE_MULZAAD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZASD32S_HL_LH_args, + 2, Iclass_AE_MULZASD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZSAD32S_HL_LH_args, + 2, Iclass_AE_MULZSAD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZSSD32S_HL_LH_args, + 2, Iclass_AE_MULZSSD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAAD32S_HL_LH_args, + 2, Iclass_AE_MULAAD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULASD32S_HL_LH_args, + 2, Iclass_AE_MULASD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSAD32S_HL_LH_args, + 2, Iclass_AE_MULSAD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSSD32S_HL_LH_args, + 2, Iclass_AE_MULSSD32S_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULF32X2RA_HH_LL_args, + 1, Iclass_AE_MULF32X2RA_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAF32X2RA_HH_LL_args, + 1, Iclass_AE_MULAF32X2RA_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSF32X2RA_HH_LL_args, + 1, Iclass_AE_MULSF32X2RA_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULF32X2RA_HL_LH_args, + 1, Iclass_AE_MULF32X2RA_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAF32X2RA_HL_LH_args, + 1, Iclass_AE_MULAF32X2RA_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSF32X2RA_HL_LH_args, + 1, Iclass_AE_MULSF32X2RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZAAF2D32RA_HH_LL_args, + 1, Iclass_AE_MULZAAF2D32RA_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZASF2D32RA_HH_LL_args, + 1, Iclass_AE_MULZASF2D32RA_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSAF2D32RA_HH_LL_args, + 1, Iclass_AE_MULZSAF2D32RA_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSSF2D32RA_HH_LL_args, + 1, Iclass_AE_MULZSSF2D32RA_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAAF2D32RA_HH_LL_args, + 1, Iclass_AE_MULAAF2D32RA_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULASF2D32RA_HH_LL_args, + 1, Iclass_AE_MULASF2D32RA_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSAF2D32RA_HH_LL_args, + 1, Iclass_AE_MULSAF2D32RA_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSSF2D32RA_HH_LL_args, + 1, Iclass_AE_MULSSF2D32RA_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZAAF2D32RA_HL_LH_args, + 1, Iclass_AE_MULZAAF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZASF2D32RA_HL_LH_args, + 1, Iclass_AE_MULZASF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSAF2D32RA_HL_LH_args, + 1, Iclass_AE_MULZSAF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSSF2D32RA_HL_LH_args, + 1, Iclass_AE_MULZSSF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAAF2D32RA_HL_LH_args, + 1, Iclass_AE_MULAAF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULASF2D32RA_HL_LH_args, + 1, Iclass_AE_MULASF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSAF2D32RA_HL_LH_args, + 1, Iclass_AE_MULSAF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSSF2D32RA_HL_LH_args, + 1, Iclass_AE_MULSSF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULF32X2R_HH_LL_args, + 1, Iclass_AE_MULF32X2R_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAF32X2R_HH_LL_args, + 1, Iclass_AE_MULAF32X2R_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSF32X2R_HH_LL_args, + 1, Iclass_AE_MULSF32X2R_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULF32X2R_HL_LH_args, + 1, Iclass_AE_MULF32X2R_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAF32X2R_HL_LH_args, + 1, Iclass_AE_MULAF32X2R_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSF32X2R_HL_LH_args, + 1, Iclass_AE_MULSF32X2R_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULFC32W_args, + 1, Iclass_AE_MULFC32W_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAFC32W_args, + 1, Iclass_AE_MULAFC32W_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULFCJ32W_args, + 1, Iclass_AE_MULFCJ32W_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAFCJ32W_args, + 1, Iclass_AE_MULAFCJ32W_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULFCJ32RAS_args, + 2, Iclass_AE_MULFCJ32RAS_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAFCJ32RAS_args, + 2, Iclass_AE_MULAFCJ32RAS_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULF2P32X4RS_args, + 2, Iclass_AE_MULF2P32X4RS_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAF2P32X4RS_args, + 2, Iclass_AE_MULAF2P32X4RS_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSF2P32X4RS_args, + 2, Iclass_AE_MULSF2P32X4RS_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULF2P32X4RAS_args, + 2, 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Iclass_AE_MULZSS32X2_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAA32X2_HH_LL_args, + 1, Iclass_AE_MULAA32X2_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSS32X2_HH_LL_args, + 1, Iclass_AE_MULSS32X2_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULCJ32_args, + 1, Iclass_AE_MULCJ32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULACJ32_args, + 1, Iclass_AE_MULACJ32_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULADDF32RS_args, + 2, Iclass_AE_MULADDF32RS_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULADDF32RAS_args, + 2, Iclass_AE_MULADDF32RAS_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSUBF32RS_args, + 2, Iclass_AE_MULSUBF32RS_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSUBF32RAS_args, + 2, Iclass_AE_MULSUBF32RAS_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULFC32RA_args, + 1, Iclass_AE_MULFC32RA_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAFC32RA_args, + 1, Iclass_AE_MULAFC32RA_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULCJ32W_args, + 1, Iclass_AE_MULCJ32W_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULACJ32W_args, + 1, Iclass_AE_MULACJ32W_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULC32W_args, + 1, Iclass_AE_MULC32W_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAC32W_args, + 1, Iclass_AE_MULAC32W_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULF2D32X2WS_args, + 2, Iclass_AE_MULF2D32X2WS_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZAAAA2Q16_args, + 1, Iclass_AE_MULZAAAA2Q16_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAAAA2Q16_args, + 1, Iclass_AE_MULAAAA2Q16_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULP16S_H_args, + 2, Iclass_AE_MULP16S_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAP16S_H_args, + 2, Iclass_AE_MULAP16S_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSP16S_H_args, + 2, Iclass_AE_MULSP16S_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULP16S_L_args, + 2, Iclass_AE_MULP16S_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAP16S_L_args, + 2, Iclass_AE_MULAP16S_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSP16S_L_args, + 2, Iclass_AE_MULSP16S_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULC16W_H_args, + 1, Iclass_AE_MULC16W_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAC16W_H_args, + 1, Iclass_AE_MULAC16W_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULC16W_L_args, + 1, Iclass_AE_MULC16W_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAC16W_L_args, + 1, Iclass_AE_MULAC16W_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_MUL2C16S_args, + 2, Iclass_AE_MUL2C16S_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULA2C16S_args, + 2, Iclass_AE_MULA2C16S_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULFC16S_args, + 2, Iclass_AE_MULFC16S_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAFC16S_args, + 2, Iclass_AE_MULAFC16S_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULFCJ16S_args, + 2, Iclass_AE_MULFCJ16S_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAFCJ16S_args, + 2, Iclass_AE_MULAFCJ16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULFCJ16RAS_args, + 2, Iclass_AE_MULFCJ16RAS_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAFCJ16RAS_args, + 2, Iclass_AE_MULAFCJ16RAS_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULC16S_args, + 2, Iclass_AE_MULC16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAC16S_args, + 2, Iclass_AE_MULAC16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULFP16X4RS_args, + 2, Iclass_AE_MULFP16X4RS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFD16X16X4RAS_args, + 2, Iclass_AE_MULFD16X16X4RAS_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULP16X16X4S_args, + 2, Iclass_AE_MULP16X16X4S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAP16X16X4S_args, + 2, Iclass_AE_MULAP16X16X4S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSP16X16X4S_args, + 2, Iclass_AE_MULSP16X16X4S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZAA2D16SS_HH_LL_args, + 2, Iclass_AE_MULZAA2D16SS_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZAA2D16SS_HL_LH_args, + 2, Iclass_AE_MULZAA2D16SS_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZSS2D16SS_HH_LL_args, + 2, Iclass_AE_MULZSS2D16SS_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZSS2D16SS_HL_LH_args, + 2, Iclass_AE_MULZSS2D16SS_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAA2D16SS_HH_LL_args, + 2, Iclass_AE_MULAA2D16SS_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAA2D16SS_HL_LH_args, + 2, Iclass_AE_MULAA2D16SS_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSS2D16SS_HH_LL_args, + 2, Iclass_AE_MULSS2D16SS_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSS2D16SS_HL_LH_args, + 2, Iclass_AE_MULSS2D16SS_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZAAFD16SS_HH_LL_args, + 2, Iclass_AE_MULZAAFD16SS_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZAAFD16SS_HL_LH_args, + 2, Iclass_AE_MULZAAFD16SS_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZSSFD16SS_HH_LL_args, + 2, Iclass_AE_MULZSSFD16SS_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZSSFD16SS_HL_LH_args, + 2, Iclass_AE_MULZSSFD16SS_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAAFD16SS_HH_LL_args, + 2, Iclass_AE_MULAAFD16SS_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAAFD16SS_HL_LH_args, + 2, Iclass_AE_MULAAFD16SS_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSSFD16SS_HH_LL_args, + 2, Iclass_AE_MULSSFD16SS_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSSFD16SS_HL_LH_args, + 2, Iclass_AE_MULSSFD16SS_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULFD16X16X4WS_args, + 2, Iclass_AE_MULFD16X16X4WS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULZAAAA2Q16X8_args, + 1, Iclass_AE_MULZAAAA2Q16X8_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAAAA2Q16X8_args, + 1, Iclass_AE_MULAAAA2Q16X8_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAAAA2Q8_args, + 1, Iclass_AE_MULZAAAA2Q8_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAAA2Q8_args, + 1, Iclass_AE_MULAAAA2Q8_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULC32X16W_H_args, + 1, Iclass_AE_MULC32X16W_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAC32X16W_H_args, + 1, Iclass_AE_MULAC32X16W_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULC32X16W_L_args, + 1, Iclass_AE_MULC32X16W_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAC32X16W_L_args, + 1, Iclass_AE_MULAC32X16W_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULPC32X16X2_args, + 1, Iclass_AE_MULPC32X16X2_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAPC32X16X2_args, + 1, Iclass_AE_MULAPC32X16X2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULFP32X16_H_args, + 1, Iclass_AE_MULFP32X16_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAFP32X16_H_args, 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Iclass_AE_MULAFCJ32X16W_L_args, + 1, Iclass_AE_MULAFCJ32X16W_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULF2P32X16X4RAS_args, + 2, Iclass_AE_MULF2P32X16X4RAS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAF2P32X16X4RAS_args, + 2, Iclass_AE_MULAF2P32X16X4RAS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULSF2P32X16X4RAS_args, + 2, Iclass_AE_MULSF2P32X16X4RAS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULF2P32X16X4RS_args, + 2, Iclass_AE_MULF2P32X16X4RS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAF2P32X16X4RS_args, + 2, Iclass_AE_MULAF2P32X16X4RS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULSF2P32X16X4RS_args, + 2, Iclass_AE_MULSF2P32X16X4RS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULF2P32X16X4S_args, + 2, Iclass_AE_MULF2P32X16X4S_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAF2P32X16X4S_args, + 2, Iclass_AE_MULAF2P32X16X4S_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULSF2P32X16X4S_args, + 2, Iclass_AE_MULSF2P32X16X4S_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFPC32X16X2RAS_args, + 2, Iclass_AE_MULFPC32X16X2RAS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFPC32X16X2RAS_args, + 2, Iclass_AE_MULAFPC32X16X2RAS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFPCJ32X16X2RAS_args, + 2, Iclass_AE_MULFPCJ32X16X2RAS_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFPCJ32X16X2RAS_args, + 2, Iclass_AE_MULAFPCJ32X16X2RAS_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZAAAA2Q32X16_args, + 1, Iclass_AE_MULZAAAA2Q32X16_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAAAA2Q32X16_args, + 1, Iclass_AE_MULAAAA2Q32X16_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL2Q32X16_FIR_H_args, + 1, Iclass_AE_MUL2Q32X16_FIR_H_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA2Q32X16_FIR_H_args, + 1, Iclass_AE_MULA2Q32X16_FIR_H_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL2Q32X16_FIR_L_args, + 1, Iclass_AE_MUL2Q32X16_FIR_L_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA2Q32X16_FIR_L_args, + 1, Iclass_AE_MULA2Q32X16_FIR_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI8_args, + 1, Iclass_AE_SRAI8_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI8R_args, + 1, Iclass_AE_SRAI8R_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLI8_args, + 1, Iclass_AE_SRLI8_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI8_args, + 1, Iclass_AE_SLAI8_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI8S_args, + 2, Iclass_AE_SLAI8S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA8_args, + 1, Iclass_AE_SLAA8_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLA8_args, + 1, Iclass_AE_SRLA8_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA8S_args, + 2, Iclass_AE_SLAA8S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA8RS_args, + 2, Iclass_AE_SRAA8RS_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA8S_args, + 2, Iclass_AE_SRAA8S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLI16_args, + 1, Iclass_AE_SRLI16_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI16_args, + 1, Iclass_AE_SLAI16_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA16_args, + 1, Iclass_AE_SLAA16_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLA16_args, + 1, Iclass_AE_SRLA16_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI16SYM_args, + 1, Iclass_AE_SRAI16SYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA16SYMS_args, + 2, Iclass_AE_SRAA16SYMS_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI32SYM_args, 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Iclass_AE_CVTI32X4F8U_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTI32X4F8U_L_args, + 1, Iclass_AE_CVTI32X4F8U_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTI32X4F8US_H_args, + 2, Iclass_AE_CVTI32X4F8US_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTI32X4F8US_L_args, + 2, Iclass_AE_CVTI32X4F8US_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA32X4F8U_H_args, + 1, Iclass_AE_CVTA32X4F8U_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA32X4F8U_L_args, + 1, Iclass_AE_CVTA32X4F8U_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA32X4F8US_H_args, + 2, Iclass_AE_CVTA32X4F8US_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA32X4F8US_L_args, + 2, Iclass_AE_CVTA32X4F8US_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTI32X4F16_args, + 1, Iclass_AE_CVTI32X4F16_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTI32X4F16S_args, + 2, Iclass_AE_CVTI32X4F16S_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA32X4F16_args, + 1, Iclass_AE_CVTA32X4F16_stateArgs, 0, 0 }, + { 4, Iclass_AE_CVTA32X4F16S_args, + 2, Iclass_AE_CVTA32X4F16S_stateArgs, 0, 0 }, + { 4, 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0, 0 }, + { 4, Iclass_AE_SEL8X8_args, + 1, Iclass_AE_SEL8X8_stateArgs, 0, 0 }, + { 3, Iclass_AE_SHFL8X8_args, + 1, Iclass_AE_SHFL8X8_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL16X4_args, + 1, Iclass_AE_SEL16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_SHFL16X4_args, + 1, Iclass_AE_SHFL16X4_stateArgs, 0, 0 }, + { 5, Iclass_AE_DSEL8X8_args, + 1, Iclass_AE_DSEL8X8_stateArgs, 0, 0 }, + { 5, Iclass_AE_DSEL16X4_args, + 1, Iclass_AE_DSEL16X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL8X8I_args, + 1, Iclass_AE_SEL8X8I_stateArgs, 0, 0 }, + { 2, Iclass_AE_RMAX8X8_args, + 1, Iclass_AE_RMAX8X8_stateArgs, 0, 0 }, + { 2, Iclass_AE_RMIN8X8_args, + 1, Iclass_AE_RMIN8X8_stateArgs, 0, 0 }, + { 2, Iclass_AE_RMAX16X4_args, + 1, Iclass_AE_RMAX16X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_RMIN16X4_args, + 1, Iclass_AE_RMIN16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_SORT16X4_args, + 1, Iclass_AE_SORT16X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADD8X8_H_args, + 1, Iclass_AE_RADD8X8_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADDA8X8_H_args, + 1, Iclass_AE_RADDA8X8_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADD8X8_L_args, + 1, Iclass_AE_RADD8X8_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADDA8X8_L_args, + 1, Iclass_AE_RADDA8X8_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADD16X4_args, + 1, Iclass_AE_RADD16X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADDA16X4_args, + 1, Iclass_AE_RADDA16X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMAX8X8_H_args, + 1, Iclass_AE_BMAX8X8_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMAX8X8_L_args, + 1, Iclass_AE_BMAX8X8_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMIN8X8_H_args, + 1, Iclass_AE_BMIN8X8_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMIN8X8_L_args, + 1, Iclass_AE_BMIN8X8_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMAX16X4_args, + 1, Iclass_AE_BMAX16X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMIN16X4_args, + 1, Iclass_AE_BMIN16X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMAX32X2_args, + 1, Iclass_AE_BMAX32X2_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMIN32X2_args, + 1, Iclass_AE_BMIN32X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_ADDINV16S_args, + 2, Iclass_AE_ADDINV16S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ADDINV32S_args, + 2, Iclass_AE_ADDINV32S_stateArgs, 0, 0 }, + { 6, Iclass_AE_MOVT16X8_args, + 1, Iclass_AE_MOVT16X8_stateArgs, 0, 0 }, + { 5, Iclass_AE_MOVT8X16_H_args, + 1, Iclass_AE_MOVT8X16_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MOVT8X16_L_args, + 1, Iclass_AE_MOVT8X16_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVBD1X4_args, + 1, Iclass_AE_MOVBD1X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVBD1X2_args, + 1, Iclass_AE_MOVBD1X2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVNEG32S_T_args, + 1, Iclass_AE_MOVNEG32S_T_stateArgs, 0, 0 }, + { 4, Iclass_AE_MOVDEXT_args, + 1, Iclass_AE_MOVDEXT_stateArgs, 0, 0 }, + { 4, Iclass_AE_MOVADEXT_H_args, + 1, Iclass_AE_MOVADEXT_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_MOVADEXT_L_args, + 1, Iclass_AE_MOVADEXT_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_NSA16X4_args, + 1, Iclass_AE_NSA16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_NSAZ32X4_args, + 1, Iclass_AE_NSAZ32X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_NSA32X4_args, + 1, Iclass_AE_NSA32X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCI16X4F32S_args, + 2, Iclass_AE_TRUNCI16X4F32S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCI16X4F64S_args, + 2, Iclass_AE_TRUNCI16X4F64S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCA16X4F32S_args, + 2, Iclass_AE_TRUNCA16X4F32S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCA16X4F64S_args, + 2, Iclass_AE_TRUNCA16X4F64S_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDC32_args, + 1, Iclass_AE_ADDC32_stateArgs, 0, 0 }, + { 4, Iclass_AE_SUBC32_args, + 1, Iclass_AE_SUBC32_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDC32U_args, + 1, Iclass_AE_ADDC32U_stateArgs, 0, 0 }, + { 4, Iclass_AE_SUBC32U_args, + 1, Iclass_AE_SUBC32U_stateArgs, 0, 0 }, + { 3, Iclass_AE_EXPADD16_H_args, + 1, Iclass_AE_EXPADD16_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_EXPSUB16_H_args, + 1, Iclass_AE_EXPSUB16_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_EXPADD16_L_args, + 1, Iclass_AE_EXPADD16_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_EXPSUB16_L_args, + 1, Iclass_AE_EXPSUB16_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDCEXP32_H_args, + 1, Iclass_AE_ADDCEXP32_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDCEXP32_L_args, + 1, Iclass_AE_ADDCEXP32_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_CALCRNG16_args, + 2, Iclass_AE_CALCRNG16_stateArgs, 0, 0 }, + { 4, Iclass_AE_CALCRNG32_args, + 2, Iclass_AE_CALCRNG32_stateArgs, 0, 0 }, + { 2, Iclass_AE_RNG32X4_args, + 2, Iclass_AE_RNG32X4_stateArgs, 0, 0 }, + { 5, Iclass_AE_LAV8X8X2_XP_args, + 1, Iclass_AE_LAV8X8X2_XP_stateArgs, 0, 0 }, + { 5, Iclass_AE_LAV16X4X2_XP_args, + 1, Iclass_AE_LAV16X4X2_XP_stateArgs, 0, 0 }, + { 5, Iclass_AE_SAV8X8X2_XP_args, + 1, Iclass_AE_SAV8X8X2_XP_stateArgs, 0, 0 }, + { 5, Iclass_AE_SAV16X4X2_XP_args, + 1, Iclass_AE_SAV16X4X2_XP_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVZBVCDR_args, + 3, Iclass_AE_MOVZBVCDR_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVDRZBVC_args, + 3, Iclass_AE_MOVDRZBVC_stateArgs, 0, 0 }, + { 6, Iclass_AE_LAVUNSQZ8X8_XP_args, + 1, Iclass_AE_LAVUNSQZ8X8_XP_stateArgs, 0, 0 }, + { 6, Iclass_AE_LAVUNSQZ16X4_XP_args, + 1, Iclass_AE_LAVUNSQZ16X4_XP_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL8Q8X8_args, + 1, Iclass_AE_MUL8Q8X8_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA8Q8X8_args, + 1, Iclass_AE_MULA8Q8X8_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL8Q4X16_args, + 1, Iclass_AE_MUL8Q4X16_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA8Q4X16_args, + 1, Iclass_AE_MULA8Q4X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL8Q8X16_args, + 1, Iclass_AE_MUL8Q8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA8Q8X16_args, + 1, Iclass_AE_MULA8Q8X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MUL8QW8X16_args, + 1, Iclass_AE_MUL8QW8X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MULA8QW8X16_args, + 1, Iclass_AE_MULA8QW8X16_stateArgs, 0, 0 }, + { 9, Iclass_AE_MUL4O8X8_args, + 1, Iclass_AE_MUL4O8X8_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULA4O8X8_args, + 1, Iclass_AE_MULA4O8X8_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O4X16_args, + 1, Iclass_AE_MUL4O4X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O4X16_args, + 1, Iclass_AE_MULA4O4X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MUL4O8X16_args, + 1, Iclass_AE_MUL4O8X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MULA4O8X16_args, + 1, Iclass_AE_MULA4O8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4QW8X16_args, + 1, Iclass_AE_MUL4QW8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4QW8X16_args, + 1, Iclass_AE_MULA4QW8X16_stateArgs, 0, 0 }, + { 5, Iclass_AE_MUL8Q8X8CNV_L_args, + 1, Iclass_AE_MUL8Q8X8CNV_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MUL8Q8X8CNV_H_args, + 1, Iclass_AE_MUL8Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULA8Q8X8CNV_L_args, + 1, Iclass_AE_MULA8Q8X8CNV_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULA8Q8X8CNV_H_args, + 1, Iclass_AE_MULA8Q8X8CNV_H_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL8Q8X16CNV_args, + 1, Iclass_AE_MUL8Q8X16CNV_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA8Q8X16CNV_args, + 1, Iclass_AE_MULA8Q8X16CNV_stateArgs, 0, 0 }, + { 5, Iclass_AE_MUL2X4Q8X8CNV_H_args, + 1, Iclass_AE_MUL2X4Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULA2X4Q8X8CNV_H_args, + 1, Iclass_AE_MULA2X4Q8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL2X4Q8X8CNV_L_args, + 1, Iclass_AE_MUL2X4Q8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA2X4Q8X8CNV_L_args, + 1, Iclass_AE_MULA2X4Q8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL2X4Q8X16CNV_args, + 1, Iclass_AE_MUL2X4Q8X16CNV_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA2X4Q8X16CNV_args, + 1, Iclass_AE_MULA2X4Q8X16CNV_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULQQ8X16CNV_args, + 1, Iclass_AE_MULQQ8X16CNV_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAQQ8X16CNV_args, + 1, Iclass_AE_MULAQQ8X16CNV_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL4O8X8CNV_H_args, + 1, Iclass_AE_MUL4O8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA4O8X8CNV_H_args, + 1, Iclass_AE_MULA4O8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL4O8X8CNV_L_args, + 1, Iclass_AE_MUL4O8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA4O8X8CNV_L_args, + 1, Iclass_AE_MULA4O8X8CNV_L_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O8X16CNV_H_args, + 1, Iclass_AE_MUL4O8X16CNV_H_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O8X16CNV_H_args, + 1, Iclass_AE_MULA4O8X16CNV_H_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O8X16CNV_L_args, + 1, Iclass_AE_MUL4O8X16CNV_L_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O8X16CNV_L_args, + 1, Iclass_AE_MULA4O8X16CNV_L_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL8Q4X16CNV_H_args, + 1, Iclass_AE_MUL8Q4X16CNV_H_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA8Q4X16CNV_H_args, + 1, Iclass_AE_MULA8Q4X16CNV_H_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL8Q4X16CNV_L_args, + 1, Iclass_AE_MUL8Q4X16CNV_L_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA8Q4X16CNV_L_args, + 1, Iclass_AE_MULA8Q4X16CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL2X4Q4X16CNV_H_args, + 1, Iclass_AE_MUL2X4Q4X16CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA2X4Q4X16CNV_H_args, + 1, Iclass_AE_MULA2X4Q4X16CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL2X4Q4X16CNV_L_args, + 1, Iclass_AE_MUL2X4Q4X16CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA2X4Q4X16CNV_L_args, + 1, Iclass_AE_MULA2X4Q4X16CNV_L_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULQQ4X16CNV_H_args, + 1, Iclass_AE_MULQQ4X16CNV_H_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAQQ4X16CNV_H_args, + 1, Iclass_AE_MULAQQ4X16CNV_H_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULQQ4X16CNV_L_args, + 1, Iclass_AE_MULQQ4X16CNV_L_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAQQ4X16CNV_L_args, + 1, Iclass_AE_MULAQQ4X16CNV_L_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O4X16CNV_HH_args, + 1, Iclass_AE_MUL4O4X16CNV_HH_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O4X16CNV_HL_args, + 1, Iclass_AE_MUL4O4X16CNV_HL_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O4X16CNV_LH_args, + 1, Iclass_AE_MUL4O4X16CNV_LH_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O4X16CNV_LL_args, + 1, Iclass_AE_MUL4O4X16CNV_LL_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O4X16CNV_HH_args, + 1, Iclass_AE_MULA4O4X16CNV_HH_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O4X16CNV_HL_args, + 1, Iclass_AE_MULA4O4X16CNV_HL_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O4X16CNV_LH_args, + 1, Iclass_AE_MULA4O4X16CNV_LH_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O4X16CNV_LL_args, + 1, Iclass_AE_MULA4O4X16CNV_LL_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUU8Q8X8_args, + 1, Iclass_AE_MULUU8Q8X8_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUU8Q8X8_args, + 1, Iclass_AE_MULAUU8Q8X8_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULUU4O8X8_args, + 1, Iclass_AE_MULUU4O8X8_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAUU4O8X8_args, + 1, Iclass_AE_MULAUU4O8X8_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULUU8Q8X8CNV_L_args, + 1, Iclass_AE_MULUU8Q8X8CNV_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAUU8Q8X8CNV_L_args, + 1, Iclass_AE_MULAUU8Q8X8CNV_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULUU8Q8X8CNV_H_args, + 1, Iclass_AE_MULUU8Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAUU8Q8X8CNV_H_args, + 1, Iclass_AE_MULAUU8Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULUU2X4Q8X8CNV_H_args, + 1, Iclass_AE_MULUU2X4Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAUU2X4Q8X8CNV_H_args, + 1, Iclass_AE_MULAUU2X4Q8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUU2X4Q8X8CNV_L_args, + 1, Iclass_AE_MULUU2X4Q8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUU2X4Q8X8CNV_L_args, + 1, Iclass_AE_MULAUU2X4Q8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUU4O8X8CNV_H_args, + 1, Iclass_AE_MULUU4O8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUU4O8X8CNV_H_args, + 1, Iclass_AE_MULAUU4O8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUU4O8X8CNV_L_args, + 1, Iclass_AE_MULUU4O8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUU4O8X8CNV_L_args, + 1, Iclass_AE_MULAUU4O8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUS8Q8X8_args, + 1, Iclass_AE_MULUS8Q8X8_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUS8Q8X8_args, + 1, Iclass_AE_MULAUS8Q8X8_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULUS8Q4X16_args, + 1, Iclass_AE_MULUS8Q4X16_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAUS8Q4X16_args, + 1, Iclass_AE_MULAUS8Q4X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULUS8Q8X16_args, + 1, Iclass_AE_MULUS8Q8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULAUS8Q8X16_args, + 1, Iclass_AE_MULAUS8Q8X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MULUS8QW8X16_args, + 1, Iclass_AE_MULUS8QW8X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MULAUS8QW8X16_args, + 1, Iclass_AE_MULAUS8QW8X16_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULUS4O8X8_args, + 1, Iclass_AE_MULUS4O8X8_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAUS4O8X8_args, + 1, Iclass_AE_MULAUS4O8X8_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULUS4O4X16_args, + 1, Iclass_AE_MULUS4O4X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULAUS4O4X16_args, + 1, Iclass_AE_MULAUS4O4X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MULUS4O8X16_args, + 1, Iclass_AE_MULUS4O8X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MULAUS4O8X16_args, + 1, Iclass_AE_MULAUS4O8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULUS4QW8X16_args, + 1, Iclass_AE_MULUS4QW8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULAUS4QW8X16_args, + 1, Iclass_AE_MULAUS4QW8X16_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULUS8Q8X8CNV_L_args, + 1, Iclass_AE_MULUS8Q8X8CNV_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAUS8Q8X8CNV_L_args, + 1, Iclass_AE_MULAUS8Q8X8CNV_L_stateArgs, 0, 0 }, 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}, + { 9, Iclass_AE_MULAUSQQ8X16CNV_args, + 1, Iclass_AE_MULAUSQQ8X16CNV_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUS4O8X8CNV_H_args, + 1, Iclass_AE_MULUS4O8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUS4O8X8CNV_H_args, + 1, Iclass_AE_MULAUS4O8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUS4O8X8CNV_L_args, + 1, Iclass_AE_MULUS4O8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUS4O8X8CNV_L_args, + 1, Iclass_AE_MULAUS4O8X8CNV_L_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULUS4O8X16CNV_H_args, + 1, Iclass_AE_MULUS4O8X16CNV_H_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULAUS4O8X16CNV_H_args, + 1, Iclass_AE_MULAUS4O8X16CNV_H_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULUS4O8X16CNV_L_args, + 1, Iclass_AE_MULUS4O8X16CNV_L_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULAUS4O8X16CNV_L_args, + 1, Iclass_AE_MULAUS4O8X16CNV_L_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULUS8Q4X16CNV_H_args, + 1, Iclass_AE_MULUS8Q4X16CNV_H_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAUS8Q4X16CNV_H_args, + 1, Iclass_AE_MULAUS8Q4X16CNV_H_stateArgs, 0, 0 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0 }, + { 3, Iclass_UN_S_args, + 2, Iclass_UN_S_stateArgs, 0, 0 }, + { 3, Iclass_ULE_S_args, + 2, Iclass_ULE_S_stateArgs, 0, 0 }, + { 3, Iclass_ULT_S_args, + 2, Iclass_ULT_S_stateArgs, 0, 0 }, + { 3, Iclass_UEQ_S_args, + 2, Iclass_UEQ_S_stateArgs, 0, 0 }, + { 2, Iclass_NEXP01_S_args, + 1, Iclass_NEXP01_S_stateArgs, 0, 0 }, + { 2, Iclass_MKSADJ_S_args, + 2, Iclass_MKSADJ_S_stateArgs, 0, 0 }, + { 2, Iclass_MKDADJ_S_args, + 3, Iclass_MKDADJ_S_stateArgs, 0, 0 }, + { 2, Iclass_DIV0_S_args, + 1, Iclass_DIV0_S_stateArgs, 0, 0 }, + { 2, Iclass_SQRT0_S_args, + 1, Iclass_SQRT0_S_stateArgs, 0, 0 }, + { 2, Iclass_RECIP0_S_args, + 3, Iclass_RECIP0_S_stateArgs, 0, 0 }, + { 2, Iclass_RSQRT0_S_args, + 3, Iclass_RSQRT0_S_stateArgs, 0, 0 }, + { 3, Iclass_DIVN_S_args, + 5, Iclass_DIVN_S_stateArgs, 0, 0 }, + { 2, Iclass_ADDEXP_S_args, + 1, Iclass_ADDEXP_S_stateArgs, 0, 0 }, + { 2, Iclass_ADDEXPM_S_args, + 1, Iclass_ADDEXPM_S_stateArgs, 0, 0 }, + { 3, Iclass_MIN_S_args, + 2, Iclass_MIN_S_stateArgs, 0, 0 }, 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+ 3, Iclass_FLOAT_SX2_stateArgs, 0, 0 }, + { 3, Iclass_UFLOAT_SX2_args, + 3, Iclass_UFLOAT_SX2_stateArgs, 0, 0 }, + { 2, Iclass_ABS_S_args, + 1, Iclass_ABS_S_stateArgs, 0, 0 }, + { 2, Iclass_NEG_S_args, + 1, Iclass_NEG_S_stateArgs, 0, 0 }, + { 2, Iclass_CONJC_S_args, + 1, Iclass_CONJC_S_stateArgs, 0, 0 }, + { 2, Iclass_MULJC_S_args, + 1, Iclass_MULJC_S_stateArgs, 0, 0 }, + { 2, Iclass_CONST_S_args, + 1, Iclass_CONST_S_stateArgs, 0, 0 }, + { 2, Iclass_CLSFY_S_args, + 1, Iclass_CLSFY_S_stateArgs, 0, 0 }, + { 3, Iclass_MINNUM_S_args, + 2, Iclass_MINNUM_S_stateArgs, 0, 0 }, + { 3, Iclass_MAXNUM_S_args, + 2, Iclass_MAXNUM_S_stateArgs, 0, 0 }, + { 4, Iclass_ADDANDSUB_S_args, + 5, Iclass_ADDANDSUB_S_stateArgs, 0, 0 }, + { 4, Iclass_ADDANDSUBJC_S_args, + 5, Iclass_ADDANDSUBJC_S_stateArgs, 0, 0 }, + { 3, Iclass_ADD_HL_LH_S_args, + 5, Iclass_ADD_HL_LH_S_stateArgs, 0, 0 }, + { 4, Iclass_MADDA_S_args, + 6, Iclass_MADDA_S_stateArgs, 0, 0 }, + { 3, Iclass_FREXP_S_args, + 1, Iclass_FREXP_S_stateArgs, 0, 0 }, + { 2, Iclass_FLOATEXP_S_args, + 1, Iclass_FLOATEXP_S_stateArgs, 0, 0 }, + { 3, Iclass_MINNUMABS_S_args, + 2, Iclass_MINNUMABS_S_stateArgs, 0, 0 }, + { 3, Iclass_MAXNUMABS_S_args, + 2, Iclass_MAXNUMABS_S_stateArgs, 0, 0 }, + { 5, Iclass_MULQ_S_args, + 6, Iclass_MULQ_S_stateArgs, 0, 0 }, + { 5, Iclass_MADDQ_S_args, + 6, Iclass_MADDQ_S_stateArgs, 0, 0 }, + { 5, Iclass_MSUBQ_S_args, + 6, Iclass_MSUBQ_S_stateArgs, 0, 0 }, + { 6, Iclass_MULMUXQ_S_args, + 6, Iclass_MULMUXQ_S_stateArgs, 0, 0 }, + { 6, Iclass_MADDMUXQ_S_args, + 6, Iclass_MADDMUXQ_S_stateArgs, 0, 0 }, + { 4, Iclass_BMAXNUM_S_args, + 2, Iclass_BMAXNUM_S_stateArgs, 0, 0 }, + { 4, Iclass_BMINNUM_S_args, + 2, Iclass_BMINNUM_S_stateArgs, 0, 0 }, + { 4, Iclass_BMAXNUMABS_S_args, + 2, Iclass_BMAXNUMABS_S_stateArgs, 0, 0 }, + { 4, Iclass_BMINNUMABS_S_args, + 2, Iclass_BMINNUMABS_S_stateArgs, 0, 0 }, + { 4, Iclass_ABS_SX2X2_args, + 1, Iclass_ABS_SX2X2_stateArgs, 0, 0 }, + { 4, Iclass_NEG_SX2X2_args, + 1, Iclass_NEG_SX2X2_stateArgs, 0, 0 }, + { 4, Iclass_CONJC_SX2X2_args, + 1, Iclass_CONJC_SX2X2_stateArgs, 0, 0 }, + { 4, Iclass_MULJC_SX2X2_args, + 1, Iclass_MULJC_SX2X2_stateArgs, 0, 0 }, + { 3, Iclass_CONST_SX2X2_args, + 1, Iclass_CONST_SX2X2_stateArgs, 0, 0 }, + { 6, Iclass_ADD_SX2X2_args, + 5, Iclass_ADD_SX2X2_stateArgs, 0, 0 }, + { 6, Iclass_SUB_SX2X2_args, + 5, Iclass_SUB_SX2X2_stateArgs, 0, 0 }, + { 6, Iclass_MUL_SX2X2_args, + 6, Iclass_MUL_SX2X2_stateArgs, 0, 0 }, + { 6, Iclass_MADD_SX2X2_args, + 6, Iclass_MADD_SX2X2_stateArgs, 0, 0 }, + { 6, Iclass_MSUB_SX2X2_args, + 6, Iclass_MSUB_SX2X2_stateArgs, 0, 0 }, + { 7, Iclass_MULMUX_SX2X2_args, + 6, Iclass_MULMUX_SX2X2_stateArgs, 0, 0 }, + { 7, Iclass_MADDMUX_SX2X2_args, + 6, Iclass_MADDMUX_SX2X2_stateArgs, 0, 0 }, + { 2, Iclass_ABS_H_args, + 1, Iclass_ABS_H_stateArgs, 0, 0 }, + { 2, Iclass_ADDEXP_H_args, + 1, Iclass_ADDEXP_H_stateArgs, 0, 0 }, + { 2, Iclass_ADDEXPM_H_args, + 1, Iclass_ADDEXPM_H_stateArgs, 0, 0 }, + { 2, Iclass_CLSFY_H_args, + 1, Iclass_CLSFY_H_stateArgs, 0, 0 }, + { 2, Iclass_CONJC_H_args, + 1, Iclass_CONJC_H_stateArgs, 0, 0 }, + { 2, Iclass_CONST_H_args, + 1, Iclass_CONST_H_stateArgs, 0, 0 }, + { 3, Iclass_MIN_H_args, + 2, Iclass_MIN_H_stateArgs, 0, 0 }, + { 3, Iclass_MAX_H_args, + 2, Iclass_MAX_H_stateArgs, 0, 0 }, + { 3, Iclass_MINNUM_H_args, + 2, Iclass_MINNUM_H_stateArgs, 0, 0 }, + { 3, Iclass_MAXNUM_H_args, + 2, Iclass_MAXNUM_H_stateArgs, 0, 0 }, + { 2, Iclass_MULJC_H_args, + 1, Iclass_MULJC_H_stateArgs, 0, 0 }, + { 2, Iclass_NEG_H_args, + 1, Iclass_NEG_H_stateArgs, 0, 0 }, + { 3, Iclass_OEQ_H_args, + 2, Iclass_OEQ_H_stateArgs, 0, 0 }, + { 3, Iclass_OLE_H_args, + 2, Iclass_OLE_H_stateArgs, 0, 0 }, + { 3, Iclass_OLT_H_args, + 2, Iclass_OLT_H_stateArgs, 0, 0 }, + { 3, Iclass_UEQ_H_args, + 2, Iclass_UEQ_H_stateArgs, 0, 0 }, + { 3, Iclass_ULE_H_args, + 2, Iclass_ULE_H_stateArgs, 0, 0 }, + { 3, Iclass_ULT_H_args, + 2, Iclass_ULT_H_stateArgs, 0, 0 }, + { 3, Iclass_UN_H_args, + 2, Iclass_UN_H_stateArgs, 0, 0 }, + { 2, Iclass_DIV0_H_args, + 1, Iclass_DIV0_H_stateArgs, 0, 0 }, + { 2, Iclass_FICEIL_H_args, + 2, Iclass_FICEIL_H_stateArgs, 0, 0 }, + { 2, Iclass_FIFLOOR_H_args, + 2, Iclass_FIFLOOR_H_stateArgs, 0, 0 }, + { 2, Iclass_FIRINT_H_args, + 4, Iclass_FIRINT_H_stateArgs, 0, 0 }, + { 2, Iclass_FIROUND_H_args, + 2, Iclass_FIROUND_H_stateArgs, 0, 0 }, + { 2, Iclass_FITRUNC_H_args, + 2, Iclass_FITRUNC_H_stateArgs, 0, 0 }, + { 2, Iclass_MKDADJ_H_args, + 3, Iclass_MKDADJ_H_stateArgs, 0, 0 }, + { 2, Iclass_MKSADJ_H_args, + 2, Iclass_MKSADJ_H_stateArgs, 0, 0 }, + { 2, Iclass_NEXP0_H_args, + 1, Iclass_NEXP0_H_stateArgs, 0, 0 }, + { 2, Iclass_NEXP01_H_args, + 1, Iclass_NEXP01_H_stateArgs, 0, 0 }, + { 2, Iclass_RECIP0_H_args, + 3, Iclass_RECIP0_H_stateArgs, 0, 0 }, + { 2, Iclass_RSQRT0_H_args, + 3, Iclass_RSQRT0_H_stateArgs, 0, 0 }, + { 2, Iclass_SQRT0_H_args, + 1, Iclass_SQRT0_H_stateArgs, 0, 0 }, + { 3, Iclass_FLOAT16_H_args, + 3, Iclass_FLOAT16_H_stateArgs, 0, 0 }, + { 3, Iclass_UFLOAT16_H_args, + 4, Iclass_UFLOAT16_H_stateArgs, 0, 0 }, + { 3, Iclass_TRUNC16_H_args, + 3, Iclass_TRUNC16_H_stateArgs, 0, 0 }, + { 3, Iclass_UTRUNC16_H_args, + 3, Iclass_UTRUNC16_H_stateArgs, 0, 0 }, + { 3, Iclass_FLOAT16_HX4_args, + 3, Iclass_FLOAT16_HX4_stateArgs, 0, 0 }, + { 3, Iclass_UFLOAT16_HX4_args, + 4, Iclass_UFLOAT16_HX4_stateArgs, 0, 0 }, + { 3, Iclass_TRUNC16_HX4_args, + 3, Iclass_TRUNC16_HX4_stateArgs, 0, 0 }, + { 3, Iclass_UTRUNC16_HX4_args, + 3, Iclass_UTRUNC16_HX4_stateArgs, 0, 0 }, + { 3, Iclass_ADD_H_args, + 5, Iclass_ADD_H_stateArgs, 0, 0 }, + { 3, Iclass_SUB_H_args, + 5, Iclass_SUB_H_stateArgs, 0, 0 }, + { 3, Iclass_MUL_H_args, + 6, Iclass_MUL_H_stateArgs, 0, 0 }, + { 3, Iclass_MADD_H_args, + 6, Iclass_MADD_H_stateArgs, 0, 0 }, + { 3, Iclass_MSUB_H_args, + 6, Iclass_MSUB_H_stateArgs, 0, 0 }, + { 3, Iclass_MADDN_H_args, + 1, Iclass_MADDN_H_stateArgs, 0, 0 }, + { 3, Iclass_MSUBN_H_args, + 1, Iclass_MSUBN_H_stateArgs, 0, 0 }, + { 3, Iclass_DIVN_H_args, + 5, Iclass_DIVN_H_stateArgs, 0, 0 }, + { 2, Iclass_RMINNUM_H_args, + 2, Iclass_RMINNUM_H_stateArgs, 0, 0 }, + { 2, Iclass_RMAXNUM_H_args, + 2, Iclass_RMAXNUM_H_stateArgs, 0, 0 }, + { 4, Iclass_ABS_HX4X2_args, + 1, Iclass_ABS_HX4X2_stateArgs, 0, 0 }, + { 4, Iclass_NEG_HX4X2_args, + 1, Iclass_NEG_HX4X2_stateArgs, 0, 0 }, + { 4, Iclass_CONJC_HX4X2_args, + 1, Iclass_CONJC_HX4X2_stateArgs, 0, 0 }, + { 3, Iclass_CONST_HX4X2_args, + 1, Iclass_CONST_HX4X2_stateArgs, 0, 0 }, + { 4, Iclass_MULJC_HX4X2_args, + 1, Iclass_MULJC_HX4X2_stateArgs, 0, 0 }, + { 6, Iclass_ADD_HX4X2_args, + 5, Iclass_ADD_HX4X2_stateArgs, 0, 0 }, + { 6, Iclass_SUB_HX4X2_args, + 5, Iclass_SUB_HX4X2_stateArgs, 0, 0 }, + { 6, Iclass_MUL_HX4X2_args, + 6, Iclass_MUL_HX4X2_stateArgs, 0, 0 }, + { 6, Iclass_MADD_HX4X2_args, + 6, Iclass_MADD_HX4X2_stateArgs, 0, 0 }, + { 6, Iclass_MSUB_HX4X2_args, + 6, Iclass_MSUB_HX4X2_stateArgs, 0, 0 }, + { 5, Iclass_MULQ_H_args, + 6, Iclass_MULQ_H_stateArgs, 0, 0 }, + { 5, Iclass_MADDQ_H_args, + 6, Iclass_MADDQ_H_stateArgs, 0, 0 }, + { 5, Iclass_MULCNVH_HX4X2_args, + 6, Iclass_MULCNVH_HX4X2_stateArgs, 0, 0 }, + { 5, Iclass_MULACNVH_HX4X2_args, + 6, Iclass_MULACNVH_HX4X2_stateArgs, 0, 0 }, + { 5, Iclass_MULCNVL_HX4X2_args, + 6, Iclass_MULCNVL_HX4X2_stateArgs, 0, 0 }, + { 5, Iclass_MULACNVL_HX4X2_args, + 6, Iclass_MULACNVL_HX4X2_stateArgs, 0, 0 } +}; + +enum xtensa_iclass_id { + ICLASS_xt_iclass_excw, + ICLASS_xt_iclass_rfe, + ICLASS_xt_iclass_rfde, + ICLASS_xt_iclass_syscall, + ICLASS_xt_iclass_call12, + ICLASS_xt_iclass_call8, + ICLASS_xt_iclass_call4, + ICLASS_xt_iclass_callx12, + ICLASS_xt_iclass_callx8, + ICLASS_xt_iclass_callx4, + ICLASS_xt_iclass_entry, + ICLASS_xt_iclass_movsp, + ICLASS_xt_iclass_rotw, + ICLASS_xt_iclass_retw, + ICLASS_xt_iclass_rfwou, + ICLASS_xt_iclass_l32e, + ICLASS_xt_iclass_s32e, + ICLASS_xt_iclass_rsr_windowbase, + ICLASS_xt_iclass_wsr_windowbase, + ICLASS_xt_iclass_xsr_windowbase, + ICLASS_xt_iclass_rsr_windowstart, + ICLASS_xt_iclass_wsr_windowstart, + ICLASS_xt_iclass_xsr_windowstart, + ICLASS_xt_iclass_add_n, + ICLASS_xt_iclass_addi_n, + ICLASS_xt_iclass_bz6, + ICLASS_xt_iclass_ill_n, + ICLASS_xt_iclass_loadi4, + ICLASS_xt_iclass_mov_n, + ICLASS_xt_iclass_movi_n, + ICLASS_xt_iclass_nopn, + ICLASS_xt_iclass_retn, + ICLASS_xt_iclass_storei4, + ICLASS_rur_threadptr, + ICLASS_wur_threadptr, + ICLASS_xt_iclass_addi, + ICLASS_xt_iclass_addmi, + ICLASS_xt_iclass_addsub, + ICLASS_xt_iclass_bit, + ICLASS_xt_iclass_bsi8, + ICLASS_xt_iclass_bsi8b, + ICLASS_xt_iclass_bsi8u, + ICLASS_xt_iclass_bst8, + ICLASS_xt_iclass_bsz12, + ICLASS_xt_iclass_call0, + ICLASS_xt_iclass_callx0, + ICLASS_xt_iclass_exti, + ICLASS_xt_iclass_ill, + ICLASS_xt_iclass_jump, + ICLASS_xt_iclass_jumpx, + ICLASS_xt_iclass_l16ui, + ICLASS_xt_iclass_l16si, + ICLASS_xt_iclass_l32i, + ICLASS_xt_iclass_l32r, + ICLASS_xt_iclass_l8i, + ICLASS_xt_iclass_loop, + ICLASS_xt_iclass_loopz, + ICLASS_xt_iclass_movi, + ICLASS_xt_iclass_movz, + ICLASS_xt_iclass_neg, + ICLASS_xt_iclass_nop, + ICLASS_xt_iclass_l32ex, + ICLASS_xt_iclass_s32ex, + ICLASS_xt_iclass_getex, + ICLASS_xt_iclass_clrex, + ICLASS_xt_iclass_return, + ICLASS_xt_iclass_simcall, + ICLASS_xt_iclass_s16i, + ICLASS_xt_iclass_s32i, + ICLASS_xt_iclass_s32nb, + ICLASS_xt_iclass_s8i, + ICLASS_xt_iclass_sar, + ICLASS_xt_iclass_sari, + ICLASS_xt_iclass_shifts, + ICLASS_xt_iclass_shiftst, + ICLASS_xt_iclass_shiftt, + ICLASS_xt_iclass_slli, + ICLASS_xt_iclass_srai, + ICLASS_xt_iclass_srli, + ICLASS_xt_iclass_memw, + ICLASS_xt_iclass_extw, + ICLASS_xt_iclass_isync, + ICLASS_xt_iclass_sync, + ICLASS_xt_iclass_rsil, + ICLASS_xt_iclass_rsr_lend, + ICLASS_xt_iclass_wsr_lend, + ICLASS_xt_iclass_xsr_lend, + ICLASS_xt_iclass_rsr_lcount, + ICLASS_xt_iclass_wsr_lcount, + ICLASS_xt_iclass_xsr_lcount, + ICLASS_xt_iclass_rsr_lbeg, + ICLASS_xt_iclass_wsr_lbeg, + ICLASS_xt_iclass_xsr_lbeg, + ICLASS_xt_iclass_rsr_sar, + ICLASS_xt_iclass_wsr_sar, + ICLASS_xt_iclass_xsr_sar, + ICLASS_xt_iclass_rsr_memctl, + ICLASS_xt_iclass_wsr_memctl, + ICLASS_xt_iclass_xsr_memctl, + ICLASS_xt_iclass_rsr_configid0, + ICLASS_xt_iclass_wsr_configid0, + ICLASS_xt_iclass_rsr_configid1, + ICLASS_xt_iclass_rsr_ps, + ICLASS_xt_iclass_wsr_ps, + ICLASS_xt_iclass_xsr_ps, + ICLASS_xt_iclass_rsr_epc1, + ICLASS_xt_iclass_wsr_epc1, + ICLASS_xt_iclass_xsr_epc1, + ICLASS_xt_iclass_rsr_excsave1, + ICLASS_xt_iclass_wsr_excsave1, + ICLASS_xt_iclass_xsr_excsave1, + ICLASS_xt_iclass_rsr_epc2, + ICLASS_xt_iclass_wsr_epc2, + ICLASS_xt_iclass_xsr_epc2, + ICLASS_xt_iclass_rsr_excsave2, + ICLASS_xt_iclass_wsr_excsave2, + ICLASS_xt_iclass_xsr_excsave2, + ICLASS_xt_iclass_rsr_epc3, + ICLASS_xt_iclass_wsr_epc3, + ICLASS_xt_iclass_xsr_epc3, + ICLASS_xt_iclass_rsr_excsave3, + ICLASS_xt_iclass_wsr_excsave3, + ICLASS_xt_iclass_xsr_excsave3, + ICLASS_xt_iclass_rsr_epc4, + ICLASS_xt_iclass_wsr_epc4, + ICLASS_xt_iclass_xsr_epc4, + ICLASS_xt_iclass_rsr_excsave4, + ICLASS_xt_iclass_wsr_excsave4, + ICLASS_xt_iclass_xsr_excsave4, + ICLASS_xt_iclass_rsr_epc5, + ICLASS_xt_iclass_wsr_epc5, + ICLASS_xt_iclass_xsr_epc5, + ICLASS_xt_iclass_rsr_excsave5, + ICLASS_xt_iclass_wsr_excsave5, + ICLASS_xt_iclass_xsr_excsave5, + ICLASS_xt_iclass_rsr_epc6, + ICLASS_xt_iclass_wsr_epc6, + ICLASS_xt_iclass_xsr_epc6, + ICLASS_xt_iclass_rsr_excsave6, + ICLASS_xt_iclass_wsr_excsave6, + ICLASS_xt_iclass_xsr_excsave6, + ICLASS_xt_iclass_rsr_eps2, + ICLASS_xt_iclass_wsr_eps2, + ICLASS_xt_iclass_xsr_eps2, + ICLASS_xt_iclass_rsr_eps3, + ICLASS_xt_iclass_wsr_eps3, + ICLASS_xt_iclass_xsr_eps3, + ICLASS_xt_iclass_rsr_eps4, + ICLASS_xt_iclass_wsr_eps4, + ICLASS_xt_iclass_xsr_eps4, + ICLASS_xt_iclass_rsr_eps5, + ICLASS_xt_iclass_wsr_eps5, + ICLASS_xt_iclass_xsr_eps5, + ICLASS_xt_iclass_rsr_eps6, + ICLASS_xt_iclass_wsr_eps6, + ICLASS_xt_iclass_xsr_eps6, + ICLASS_xt_iclass_rsr_excvaddr, + ICLASS_xt_iclass_wsr_excvaddr, + ICLASS_xt_iclass_xsr_excvaddr, + ICLASS_xt_iclass_rsr_depc, + ICLASS_xt_iclass_wsr_depc, + ICLASS_xt_iclass_xsr_depc, + ICLASS_xt_iclass_rsr_exccause, + ICLASS_xt_iclass_wsr_exccause, + ICLASS_xt_iclass_xsr_exccause, + ICLASS_xt_iclass_rsr_misc0, + ICLASS_xt_iclass_wsr_misc0, + ICLASS_xt_iclass_xsr_misc0, + ICLASS_xt_iclass_rsr_misc1, + ICLASS_xt_iclass_wsr_misc1, + ICLASS_xt_iclass_xsr_misc1, + ICLASS_xt_iclass_rsr_misc2, + ICLASS_xt_iclass_wsr_misc2, + ICLASS_xt_iclass_xsr_misc2, + ICLASS_xt_iclass_rsr_misc3, + ICLASS_xt_iclass_wsr_misc3, + ICLASS_xt_iclass_xsr_misc3, + ICLASS_xt_iclass_rsr_prid, + ICLASS_xt_iclass_rsr_vecbase, + ICLASS_xt_iclass_wsr_vecbase, + ICLASS_xt_iclass_xsr_vecbase, + ICLASS_xt_iclass_rsr_mpucfg, + ICLASS_xt_iclass_wsr_mpucfg, + ICLASS_xt_iclass_salt, + ICLASS_xt_iclass_rsr_opmode, + ICLASS_xt_iclass_wsr_opmode, + ICLASS_xt_iclass_xsr_opmode, + ICLASS_xt_mul16, + ICLASS_xt_mul32, + ICLASS_xt_iclass_rfi, + ICLASS_xt_iclass_wait, + ICLASS_xt_iclass_rsr_interrupt, + ICLASS_xt_iclass_wsr_intset, + ICLASS_xt_iclass_wsr_intclear, + ICLASS_xt_iclass_rsr_intenable, + ICLASS_xt_iclass_wsr_intenable, + ICLASS_xt_iclass_xsr_intenable, + ICLASS_xt_iclass_break, + ICLASS_xt_iclass_break_n, + ICLASS_xt_iclass_rsr_dbreaka0, + ICLASS_xt_iclass_wsr_dbreaka0, + ICLASS_xt_iclass_xsr_dbreaka0, + ICLASS_xt_iclass_rsr_dbreakc0, + ICLASS_xt_iclass_wsr_dbreakc0, + ICLASS_xt_iclass_xsr_dbreakc0, + ICLASS_xt_iclass_rsr_dbreaka1, + ICLASS_xt_iclass_wsr_dbreaka1, + ICLASS_xt_iclass_xsr_dbreaka1, + ICLASS_xt_iclass_rsr_dbreakc1, + ICLASS_xt_iclass_wsr_dbreakc1, + ICLASS_xt_iclass_xsr_dbreakc1, + ICLASS_xt_iclass_rsr_ibreaka0, + ICLASS_xt_iclass_wsr_ibreaka0, + ICLASS_xt_iclass_xsr_ibreaka0, + ICLASS_xt_iclass_rsr_ibreaka1, + ICLASS_xt_iclass_wsr_ibreaka1, + ICLASS_xt_iclass_xsr_ibreaka1, + ICLASS_xt_iclass_rsr_ibreakenable, + ICLASS_xt_iclass_wsr_ibreakenable, + ICLASS_xt_iclass_xsr_ibreakenable, + ICLASS_xt_iclass_rsr_debugcause, + ICLASS_xt_iclass_wsr_debugcause, + ICLASS_xt_iclass_xsr_debugcause, + ICLASS_xt_iclass_rsr_icount, + ICLASS_xt_iclass_wsr_icount, + ICLASS_xt_iclass_xsr_icount, + ICLASS_xt_iclass_rsr_icountlevel, + ICLASS_xt_iclass_wsr_icountlevel, + ICLASS_xt_iclass_xsr_icountlevel, + ICLASS_xt_iclass_rsr_ddr, + ICLASS_xt_iclass_wsr_ddr, + ICLASS_xt_iclass_xsr_ddr, + ICLASS_xt_iclass_lddr32_p, + ICLASS_xt_iclass_sddr32_p, + ICLASS_xt_iclass_rfdo, + ICLASS_xt_iclass_rfdd, + ICLASS_xt_iclass_wsr_mmid, + ICLASS_xt_iclass_bbool1, + ICLASS_xt_iclass_bbool4, + ICLASS_xt_iclass_bbool8, + ICLASS_xt_iclass_bbranch, + ICLASS_xt_iclass_bmove, + ICLASS_xt_iclass_RSR_BR, + ICLASS_xt_iclass_WSR_BR, + ICLASS_xt_iclass_XSR_BR, + ICLASS_xt_iclass_rsr_ccount, + ICLASS_xt_iclass_wsr_ccount, + ICLASS_xt_iclass_xsr_ccount, + ICLASS_xt_iclass_rsr_ccompare0, + ICLASS_xt_iclass_wsr_ccompare0, + ICLASS_xt_iclass_xsr_ccompare0, + ICLASS_xt_iclass_rsr_ccompare1, + ICLASS_xt_iclass_wsr_ccompare1, + ICLASS_xt_iclass_xsr_ccompare1, + ICLASS_xt_iclass_rsr_ccompare2, + ICLASS_xt_iclass_wsr_ccompare2, + ICLASS_xt_iclass_xsr_ccompare2, + ICLASS_xt_iclass_icache, + ICLASS_xt_iclass_icache_lock, + ICLASS_xt_iclass_icache_inv, + ICLASS_xt_iclass_licx, + ICLASS_xt_iclass_sicx, + ICLASS_xt_iclass_dcache, + ICLASS_xt_iclass_dcache_dyn, + ICLASS_xt_iclass_dcache_ind, + ICLASS_xt_iclass_dcache_inv, + ICLASS_xt_iclass_dpf, + ICLASS_xt_iclass_dcache_lock, + ICLASS_xt_iclass_sdct, + ICLASS_xt_iclass_ldct, + ICLASS_xt_iclass_sdcw, + ICLASS_xt_iclass_ldcw, + ICLASS_xt_iclass_rsr_prefctl, + ICLASS_xt_iclass_wsr_prefctl, + ICLASS_xt_iclass_xsr_prefctl, + ICLASS_xt_iclass_wsr_cacheadrdis, + ICLASS_xt_iclass_rsr_cacheadrdis, + ICLASS_xt_iclass_xsr_cacheadrdis, + ICLASS_xt_iclass_rptlb0, + ICLASS_xt_iclass_rptlb, + ICLASS_xt_iclass_wptlb, + ICLASS_xt_iclass_rsr_mpuenb, + ICLASS_xt_iclass_wsr_mpuenb, + ICLASS_xt_iclass_xsr_mpuenb, + ICLASS_xt_iclass_rsr_cpenable, + ICLASS_xt_iclass_wsr_cpenable, + ICLASS_xt_iclass_xsr_cpenable, + ICLASS_xt_iclass_clamp, + ICLASS_xt_iclass_minmax, + ICLASS_xt_iclass_nsa, + ICLASS_xt_iclass_sx, + ICLASS_xt_iclass_l32ai, + ICLASS_xt_iclass_s32ri, + ICLASS_xt_iclass_rsr_atomctl, + ICLASS_xt_iclass_wsr_atomctl, + ICLASS_xt_iclass_xsr_atomctl, + ICLASS_xt_iclass_div, + ICLASS_xt_iclass_rsr_eraccess, + ICLASS_xt_iclass_wsr_eraccess, + ICLASS_xt_iclass_xsr_eraccess, + ICLASS_xt_iclass_rer, + ICLASS_xt_iclass_wer, + ICLASS_xt_iclass_wb15_0, + ICLASS_xt_iclass_wb15_1, + ICLASS_xt_iclass_wb15_2, + ICLASS_xt_iclass_wb15_3, + ICLASS_xt_iclass_wb15_4, + ICLASS_ic_sext16, + ICLASS_ic_zext16, + ICLASS_ic_zext8, + ICLASS_ic_clamps16, + ICLASS_rur_fcr, + ICLASS_wur_fcr, + ICLASS_rur_fsr, + ICLASS_wur_fsr, + ICLASS_iclass_READ_IMPWIRE, + ICLASS_iclass_SETB_EXPSTATE, + ICLASS_iclass_CLRB_EXPSTATE, + ICLASS_iclass_WRMSK_EXPSTATE, + ICLASS_rur_ae_ovf_sar, + ICLASS_wur_ae_ovf_sar, + ICLASS_rur_ae_bithead, + ICLASS_wur_ae_bithead, + ICLASS_rur_ae_ts_fts_bu_bp, + ICLASS_wur_ae_ts_fts_bu_bp, + ICLASS_rur_ae_cw_sd_no, + ICLASS_wur_ae_cw_sd_no, + ICLASS_rur_ae_cbegin0, + ICLASS_wur_ae_cbegin0, + ICLASS_rur_ae_cend0, + ICLASS_wur_ae_cend0, + ICLASS_rur_ae_cbegin1, + ICLASS_wur_ae_cbegin1, + ICLASS_rur_ae_cend1, + ICLASS_wur_ae_cend1, + ICLASS_rur_ae_cbegin2, + ICLASS_wur_ae_cbegin2, + ICLASS_rur_ae_cend2, + ICLASS_wur_ae_cend2, + ICLASS_rur_expstate, + ICLASS_wur_expstate, + ICLASS_RUR_AE_OVERFLOW, + ICLASS_WUR_AE_OVERFLOW, + ICLASS_RUR_AE_SAR, + ICLASS_WUR_AE_SAR, + ICLASS_RUR_AE_BITPTR, + ICLASS_WUR_AE_BITPTR, + ICLASS_RUR_AE_BITSUSED, + ICLASS_WUR_AE_BITSUSED, + ICLASS_RUR_AE_TABLESIZE, + ICLASS_WUR_AE_TABLESIZE, + ICLASS_RUR_AE_FIRST_TS, + ICLASS_WUR_AE_FIRST_TS, + ICLASS_RUR_AE_NEXTOFFSET, + ICLASS_WUR_AE_NEXTOFFSET, + ICLASS_RUR_AE_SEARCHDONE, + ICLASS_WUR_AE_SEARCHDONE, + ICLASS_RUR_AE_CWRAP, + ICLASS_WUR_AE_CWRAP, + ICLASS_AE_L8X4F_I, + ICLASS_AE_L8X4F_IP, + ICLASS_AE_L8X4F_X, + ICLASS_AE_L8X4F_XP, + ICLASS_AE_L8X4S_I, + ICLASS_AE_L8X4S_IP, + ICLASS_AE_L8X4S_X, + ICLASS_AE_L8X4S_XP, + ICLASS_AE_L8X4U_I, + ICLASS_AE_L8X4U_IP, + ICLASS_AE_L8X4U_X, + ICLASS_AE_L8X4U_XP, + ICLASS_AE_S8X4U_I, + ICLASS_AE_S8X4U_IP, + ICLASS_AE_S8X4U_X, + ICLASS_AE_S8X4U_XP, + ICLASS_AE_L16M_XC, + ICLASS_AE_L16M_XC1, + ICLASS_AE_L16M_I, + ICLASS_AE_L16M_IU, + ICLASS_AE_L16M_X, + ICLASS_AE_L16M_XU, + ICLASS_AE_L16_XC, + ICLASS_AE_L16_XC1, + ICLASS_AE_L16_I, + ICLASS_AE_L16_IP, + ICLASS_AE_L16_X, + ICLASS_AE_L16_XP, + ICLASS_AE_L8_XC, + ICLASS_AE_L8_XC1, + ICLASS_AE_L8_I, + ICLASS_AE_L8_IP, + ICLASS_AE_L8_X, + ICLASS_AE_L8_XP, + ICLASS_AE_L32F24_XC, + ICLASS_AE_L32F24_XC1, + ICLASS_AE_L32F24_I, + ICLASS_AE_L32F24_IP, + ICLASS_AE_L32F24_X, + ICLASS_AE_L32F24_XP, + ICLASS_AE_L32_XC, + ICLASS_AE_L32_XC1, + ICLASS_AE_L32_I, + ICLASS_AE_L32_IP, + ICLASS_AE_L32_X, + ICLASS_AE_L32_XP, + ICLASS_AE_L32M_XC, + ICLASS_AE_L32M_I, + ICLASS_AE_L32M_IU, + ICLASS_AE_L32M_X, + ICLASS_AE_L32M_XU, + ICLASS_AE_L16X2M_XC, + ICLASS_AE_L16X2M_XC1, + ICLASS_AE_L16X2M_I, + ICLASS_AE_L16X2M_IU, + ICLASS_AE_L16X2M_X, + ICLASS_AE_L16X2M_XU, + ICLASS_AE_L32X2F24_XC, + ICLASS_AE_L32X2F24_XC1, + ICLASS_AE_L32X2F24_I, + ICLASS_AE_L32X2F24_IP, + ICLASS_AE_L32X2F24_RIP, + ICLASS_AE_L32X2F24_RI, + ICLASS_AE_L32X2F24_RIC, + ICLASS_AE_L32X2F24_RIC1, + ICLASS_AE_L32X2F24_X, + ICLASS_AE_L32X2F24_XP, + ICLASS_AE_L32X2_XC, + ICLASS_AE_L32X2_XC1, + ICLASS_AE_L32X2_I, + ICLASS_AE_L32X2_IP, + ICLASS_AE_L32X2_RIC, + ICLASS_AE_L32X2_RIC1, + ICLASS_AE_L32X2_X, + ICLASS_AE_L32X2_XP, + ICLASS_AE_L16X4_XC, + ICLASS_AE_L16X4_XC1, + ICLASS_AE_L16X4_I, + ICLASS_AE_L16X4_IP, + ICLASS_AE_L16X4_X, + ICLASS_AE_L16X4_XP, + ICLASS_AE_L8X8_XC, + ICLASS_AE_L8X8_XC1, + ICLASS_AE_L8X8_I, + ICLASS_AE_L8X8_IP, + ICLASS_AE_L8X8_X, + ICLASS_AE_L8X8_XP, + ICLASS_AE_L64_XC, + ICLASS_AE_L64_XC1, + ICLASS_AE_L64_I, + ICLASS_AE_L64_IP, + ICLASS_AE_L64_X, + ICLASS_AE_L64_XP, + ICLASS_AE_S16X2M_XC, + ICLASS_AE_S16X2M_XC1, + ICLASS_AE_S16X2M_I, + ICLASS_AE_S16X2M_IU, + ICLASS_AE_S16X2M_X, + ICLASS_AE_S16X2M_XU, + ICLASS_AE_S32X2F24_XC, + ICLASS_AE_S32X2F24_XC1, + ICLASS_AE_S32X2F24_I, + ICLASS_AE_S32X2F24_IP, + ICLASS_AE_S32X2F24_RIP, + ICLASS_AE_S32X2F24_RIC, + ICLASS_AE_S32X2F24_RIC1, + ICLASS_AE_S32X2F24_X, + ICLASS_AE_S32X2F24_XP, + ICLASS_AE_S32X2_XC, + ICLASS_AE_S32X2_XC1, + ICLASS_AE_S32X2_I, + ICLASS_AE_S32X2_IP, + ICLASS_AE_S32X2_RIC, + ICLASS_AE_S32X2_RIC1, + ICLASS_AE_S32X2_X, + ICLASS_AE_S32X2_XP, + ICLASS_AE_S32X2RNG_I, + ICLASS_AE_S32X2RNG_IP, + ICLASS_AE_S32X2RNG_X, + ICLASS_AE_S32X2RNG_XP, + ICLASS_AE_S16X4_XC, + ICLASS_AE_S16X4_XC1, + ICLASS_AE_S16X4_I, + ICLASS_AE_S16X4_IP, + ICLASS_AE_S16X4_X, + ICLASS_AE_S16X4_XP, + ICLASS_AE_S8X8_XC, + ICLASS_AE_S8X8_XC1, + ICLASS_AE_S8X8_I, + ICLASS_AE_S8X8_IP, + ICLASS_AE_S8X8_X, + ICLASS_AE_S8X8_XP, + ICLASS_AE_S16M_L_XC, + ICLASS_AE_S16M_L_XC1, + ICLASS_AE_S16M_L_I, + ICLASS_AE_S16M_L_IU, + ICLASS_AE_S16M_L_X, + ICLASS_AE_S16M_L_XU, + ICLASS_AE_S32F24_L_XC, + ICLASS_AE_S32F24_L_XC1, + ICLASS_AE_S32F24_L_I, + ICLASS_AE_S32F24_L_IP, + ICLASS_AE_S32F24_L_X, + ICLASS_AE_S32F24_L_XP, + ICLASS_AE_S32_L_XC, + ICLASS_AE_S32_L_XC1, + ICLASS_AE_S32_L_I, + ICLASS_AE_S32_L_IP, + ICLASS_AE_S32_L_X, + ICLASS_AE_S32_L_XP, + ICLASS_AE_S32_H_XC, + ICLASS_AE_S32_H_XC1, + ICLASS_AE_S32_H_I, + ICLASS_AE_S32_H_IP, + ICLASS_AE_S32_H_X, + ICLASS_AE_S32_H_XP, + ICLASS_AE_S16_0_XC, + ICLASS_AE_S16_0_XC1, + ICLASS_AE_S16_0_I, + ICLASS_AE_S16_0_IP, + ICLASS_AE_S16_0_X, + ICLASS_AE_S16_0_XP, + ICLASS_AE_S8_0_XC, + ICLASS_AE_S8_0_XC1, + ICLASS_AE_S8_0_I, + ICLASS_AE_S8_0_IP, + ICLASS_AE_S8_0_X, + ICLASS_AE_S8_0_XP, + ICLASS_AE_S64_XC, + ICLASS_AE_S64_XC1, + ICLASS_AE_S64_I, + ICLASS_AE_S64_IP, + ICLASS_AE_S64_X, + ICLASS_AE_S64_XP, + ICLASS_AE_S32M_XC, + ICLASS_AE_S32M_I, + ICLASS_AE_S32M_IU, + ICLASS_AE_S32M_X, + ICLASS_AE_S32M_XU, + ICLASS_AE_L32X2_XC2, + ICLASS_AE_L16X4_XC2, + ICLASS_AE_L8X8_XC2, + ICLASS_AE_L64_XC2, + ICLASS_AE_S32X2_XC2, + ICLASS_AE_S16X4_XC2, + ICLASS_AE_S8X8_XC2, + ICLASS_AE_S64_XC2, + ICLASS_AE_S16X4RNG_I, + ICLASS_AE_S16X4RNG_IP, + ICLASS_AE_S16X4RNG_X, + ICLASS_AE_S16X4RNG_XP, + ICLASS_AE_L32X2X2_XC, + ICLASS_AE_L32X2X2_XC1, + ICLASS_AE_L32X2X2_I, + ICLASS_AE_L32X2X2_IP, + ICLASS_AE_L32X2X2_X, + ICLASS_AE_L32X2X2_XP, + ICLASS_AE_L16X4X2_XC, + ICLASS_AE_L16X4X2_XC1, + ICLASS_AE_L16X4X2_I, + ICLASS_AE_L16X4X2_IP, + ICLASS_AE_L16X4X2_X, + ICLASS_AE_L16X4X2_XP, + ICLASS_AE_L8X8X2_XC, + ICLASS_AE_L8X8X2_XC1, + ICLASS_AE_L8X8X2_I, + ICLASS_AE_L8X8X2_IP, + ICLASS_AE_L8X8X2_X, + ICLASS_AE_L8X8X2_XP, + ICLASS_AE_L64X2_XC, + ICLASS_AE_L64X2_XC1, + ICLASS_AE_L64X2_I, + ICLASS_AE_L64X2_IP, + ICLASS_AE_L64X2_X, + ICLASS_AE_L64X2_XP, + ICLASS_AE_S32X2X2_XC, + ICLASS_AE_S32X2X2_XC1, + ICLASS_AE_S32X2X2_I, + ICLASS_AE_S32X2X2_IP, + ICLASS_AE_S32X2X2_X, + ICLASS_AE_S32X2X2_XP, + ICLASS_AE_S32X2X2RNG_I, + ICLASS_AE_S32X2X2RNG_IP, + ICLASS_AE_S32X2X2RNG_X, + ICLASS_AE_S32X2X2RNG_XP, + ICLASS_AE_S16X4X2_XC, + ICLASS_AE_S16X4X2_XC1, + ICLASS_AE_S16X4X2_I, + ICLASS_AE_S16X4X2_IP, + ICLASS_AE_S16X4X2_X, + ICLASS_AE_S16X4X2_XP, + ICLASS_AE_S8X8X2_XC, + ICLASS_AE_S8X8X2_XC1, + ICLASS_AE_S8X8X2_I, + ICLASS_AE_S8X8X2_IP, + ICLASS_AE_S8X8X2_X, + ICLASS_AE_S8X8X2_XP, + ICLASS_AE_S8X4UX2_I, + ICLASS_AE_S8X4UX2_IP, + ICLASS_AE_S8X4UX2_X, + ICLASS_AE_S8X4UX2_XP, + ICLASS_AE_S64X2_XC, + ICLASS_AE_S64X2_XC1, + ICLASS_AE_S64X2_I, + ICLASS_AE_S64X2_IP, + ICLASS_AE_S64X2_X, + ICLASS_AE_S64X2_XP, + ICLASS_AE_L32X2X2_XC2, + ICLASS_AE_L16X4X2_XC2, + ICLASS_AE_L8X8X2_XC2, + ICLASS_AE_L64X2_XC2, + ICLASS_AE_S32X2X2_XC2, + ICLASS_AE_S16X4X2_XC2, + ICLASS_AE_S8X8X2_XC2, + ICLASS_AE_S64X2_XC2, + ICLASS_AE_S16X4X2RNG_I, + ICLASS_AE_S16X4X2RNG_IP, + ICLASS_AE_S16X4X2RNG_X, + ICLASS_AE_S16X4X2RNG_XP, + ICLASS_AE_ZALIGN64, + ICLASS_AE_LALIGN64_I, + ICLASS_AE_SALIGN64_I, + ICLASS_AE_MOVALIGN, + ICLASS_AE_LA64_PP, + ICLASS_AE_LA24POS_PC, + ICLASS_AE_LA24NEG_PC, + ICLASS_AE_LA24POS_PC1, + ICLASS_AE_LA24NEG_PC1, + ICLASS_AE_LA24X2POS_PC, + ICLASS_AE_LA24X2NEG_PC, + ICLASS_AE_LA24X2POS_PC1, + ICLASS_AE_LA24X2NEG_PC1, + ICLASS_AE_LA32X2POS_PC, + ICLASS_AE_LA32X2NEG_PC, + ICLASS_AE_LA32X2POS_PC1, + ICLASS_AE_LA32X2NEG_PC1, + ICLASS_AE_LA32X2POS_PC2, + ICLASS_AE_LA16X4POS_PC, + ICLASS_AE_LA16X4NEG_PC, + ICLASS_AE_LA16X4POS_PC1, + ICLASS_AE_LA16X4NEG_PC1, + ICLASS_AE_LA16X4POS_PC2, + ICLASS_AE_LA8X8POS_PC, + ICLASS_AE_LA8X8NEG_PC, + ICLASS_AE_LA8X8POS_PC1, + ICLASS_AE_LA8X8NEG_PC1, + ICLASS_AE_LA8X8POS_PC2, + ICLASS_AE_LA32X2X2POS_PC, + ICLASS_AE_LA32X2X2POS_PC1, + ICLASS_AE_LA32X2X2POS_PC2, + ICLASS_AE_LA16X4X2POS_PC, + ICLASS_AE_LA16X4X2POS_PC1, + ICLASS_AE_LA16X4X2POS_PC2, + ICLASS_AE_LA8X8X2POS_PC, + ICLASS_AE_LA8X8X2POS_PC1, + ICLASS_AE_LA8X8X2POS_PC2, + ICLASS_AE_SA64POS_FP, + ICLASS_AE_SA64NEG_FP, + ICLASS_AE_LA32X2_IC, + ICLASS_AE_LA32X2_IC1, + ICLASS_AE_LA32X2_IC2, + ICLASS_AE_LA32X2_IP, + ICLASS_AE_LA32X2_RIP, + ICLASS_AE_LA32X2_RIC, + ICLASS_AE_LA32X2_RIC1, + ICLASS_AE_LA16X4_IC, + ICLASS_AE_LA16X4_IC1, + ICLASS_AE_LA16X4_IC2, + ICLASS_AE_LA16X4_IP, + ICLASS_AE_LA16X4_RIP, + ICLASS_AE_LA16X4_RIC, + ICLASS_AE_LA16X4_RIC1, + ICLASS_AE_LA8X8_IC, + ICLASS_AE_LA8X8_IC1, + ICLASS_AE_LA8X8_IC2, + ICLASS_AE_LA8X8_IP, + ICLASS_AE_LA8X8_RIP, + ICLASS_AE_LA8X8_RIC, + ICLASS_AE_LA8X8_RIC1, + ICLASS_AE_LA32X2F24_IC, + ICLASS_AE_LA32X2F24_IC1, + ICLASS_AE_LA32X2F24_IP, + ICLASS_AE_LA32X2F24_RIP, + ICLASS_AE_LA32X2F24_RIC, + ICLASS_AE_LA32X2F24_RIC1, + ICLASS_AE_LA24_IC, + ICLASS_AE_LA24_IC1, + ICLASS_AE_LA24_IP, + ICLASS_AE_LA24_RIP, + ICLASS_AE_LA24_RIC, + ICLASS_AE_LA24_RIC1, + ICLASS_AE_LA24X2_IC, + ICLASS_AE_LA24X2_IC1, + ICLASS_AE_LA24X2_IP, + ICLASS_AE_LA24X2_RIP, + ICLASS_AE_LA24X2_RIC, + ICLASS_AE_LA24X2_RIC1, + ICLASS_AE_SA32X2_IC, + ICLASS_AE_SA32X2_IC1, + ICLASS_AE_SA32X2_IC2, + ICLASS_AE_SA32X2_IP, + ICLASS_AE_SA32X2_RIP, + ICLASS_AE_SA32X2_RIC, + ICLASS_AE_SA32X2_RIC1, + ICLASS_AE_SA16X4_IC, + ICLASS_AE_SA16X4_IC1, + ICLASS_AE_SA16X4_IC2, + ICLASS_AE_SA16X4_IP, + ICLASS_AE_SA16X4_RIP, + ICLASS_AE_SA16X4_RIC, + ICLASS_AE_SA16X4_RIC1, + ICLASS_AE_SA8X8_IC, + ICLASS_AE_SA8X8_IC1, + ICLASS_AE_SA8X8_IC2, + ICLASS_AE_SA8X8_IP, + ICLASS_AE_SA8X8_RIP, + ICLASS_AE_SA8X8_RIC, + ICLASS_AE_SA8X8_RIC1, + ICLASS_AE_SA32X2F24_IC, + ICLASS_AE_SA32X2F24_IC1, + ICLASS_AE_SA32X2F24_IP, + ICLASS_AE_SA32X2F24_RIP, + ICLASS_AE_SA32X2F24_RIC, + ICLASS_AE_SA32X2F24_RIC1, + ICLASS_AE_SA24_L_IC, + ICLASS_AE_SA24_L_IC1, + ICLASS_AE_SA24_L_IP, + ICLASS_AE_SA24_L_RIP, + ICLASS_AE_SA24_L_RIC, + ICLASS_AE_SA24_L_RIC1, + ICLASS_AE_SA24X2_IC, + ICLASS_AE_SA24X2_IC1, + ICLASS_AE_SA24X2_IP, + ICLASS_AE_SA24X2_RIP, + ICLASS_AE_SA24X2_RIC, + ICLASS_AE_SA24X2_RIC1, + ICLASS_AE_ADDICIRC, + ICLASS_AE_ADDCIRC_XC2, + ICLASS_AE_ADDCIRC_XC1, + ICLASS_AE_ADDCIRC_XC, + ICLASS_AE_S32RA64S_I, + ICLASS_AE_S32RA64S_IP, + ICLASS_AE_S32RA64S_X, + ICLASS_AE_S32RA64S_XP, + ICLASS_AE_S32RA64S_XC, + ICLASS_AE_S32RA64S_XC1, + ICLASS_AE_S24RA64S_I, + ICLASS_AE_S24RA64S_IP, + ICLASS_AE_S24RA64S_X, + ICLASS_AE_S24RA64S_XP, + ICLASS_AE_S24RA64S_XC, + ICLASS_AE_S24RA64S_XC1, + ICLASS_AE_S32X2RA64S_IP, + ICLASS_AE_S24X2RA64S_IP, + ICLASS_AE_S16X4RA32S_IP, + ICLASS_AE_ADDBRBA32, + ICLASS_AE_S32X2_L_IP, + ICLASS_AE_BITSWAP, + ICLASS_AE_MUL32JS, + ICLASS_AE_ADDANDSUB32S, + ICLASS_AE_ADDANDSUB32JS, + ICLASS_AE_ADDANDSUBRNG32, + ICLASS_AE_ADDANDSUBRNG32_H, + ICLASS_AE_ADDANDSUBRNG32_L, + ICLASS_AE_ADDRNG32, + ICLASS_AE_SUBRNG32, + ICLASS_AE_RNG32X2, + ICLASS_AE_SEL16I, + ICLASS_AE_SEL16I_N, + ICLASS_AE_SHORTSWAP, + ICLASS_AE_MOVAB4, + ICLASS_AE_MOVAB2, + ICLASS_AE_MOVAB, + ICLASS_AE_MOVBA, + ICLASS_AE_MOVBA1X2, + ICLASS_AE_MOVBA4, + ICLASS_AE_MOVBA2, + ICLASS_AE_MOVB2, + ICLASS_AE_MOVB4, + ICLASS_AE_MOVT16X4, + ICLASS_AE_MOVF16X4, + ICLASS_AE_MOVT32X2, + ICLASS_AE_MOVF32X2, + ICLASS_AE_MOVSARA7X2, + ICLASS_AE_MOVSARD7, + ICLASS_AE_MOVASAR, + ICLASS_AE_MOVDA32X2, + ICLASS_AE_MOVDA32, + ICLASS_AE_MOVDA16X2, + ICLASS_AE_MOVDA16, + ICLASS_AE_MOVI, + ICLASS_AE_TRUNCP24A32X2, + ICLASS_AE_SAT16X4, + ICLASS_AE_CVT32X2F16_32, + ICLASS_AE_CVT32X2F16_10, + ICLASS_AE_SEXT32X2D16_32, + ICLASS_AE_SEXT32X2D16_10, + ICLASS_AE_CVTA32F24S_L, + ICLASS_AE_CVTA32F24S_H, + ICLASS_AE_CVTP24A16X2_LL, + ICLASS_AE_CVTP24A16X2_LH, + ICLASS_AE_CVTP24A16X2_HL, + ICLASS_AE_CVTP24A16X2_HH, + ICLASS_AE_TRUNCP24Q48X2, + ICLASS_AE_TRUNCA32X2F64S, + ICLASS_AE_TRUNCI32X2F64S, + ICLASS_AE_TRUNCA32F64S_L, + ICLASS_AE_TRUNCI32F64S_L, + ICLASS_AE_TRUNCP16, + ICLASS_AE_ROUND32X2F64SSYM, + ICLASS_AE_ROUND32X2F64SASYM, + ICLASS_AE_ROUND32X2F48SSYM, + ICLASS_AE_ROUND32X2F48SASYM, + ICLASS_AE_ROUND16X4F32SSYM, + ICLASS_AE_ROUND16X4F32SASYM, + ICLASS_AE_ROUND24X2F48SSYM, + ICLASS_AE_ROUND24X2F48SASYM, + ICLASS_AE_ROUNDSP16Q48X2SYM, + ICLASS_AE_ROUNDSP16Q48X2ASYM, + ICLASS_AE_MINABS32S, + ICLASS_AE_MAXABS32S, + ICLASS_AE_ROUNDSP16F24SYM, + ICLASS_AE_ROUNDSP16F24ASYM, + ICLASS_AE_MOV, + ICLASS_AE_MOVT64, + ICLASS_AE_MOVF64, + ICLASS_AE_CVTQ56A32S, + ICLASS_AE_CVT48A32, + ICLASS_AE_CVT64A32, + ICLASS_AE_CVTQ56P32S_L, + ICLASS_AE_CVTQ56P32S_H, + ICLASS_AE_CVT64F32_H, + ICLASS_AE_CVT48F32_L, + ICLASS_AE_CVT48F32_H, + ICLASS_AE_SAT48S, + ICLASS_AE_SATQ56S, + ICLASS_AE_SAT24S, + ICLASS_AE_TRUNCQ32, + ICLASS_AE_MINABS64S, + ICLASS_AE_MAXABS64S, + ICLASS_AE_ROUNDSQ32F48SYM, + ICLASS_AE_ROUNDSQ32F48ASYM, + ICLASS_AE_TRUNCA32Q48, + ICLASS_AE_MOVAD32_L, + ICLASS_AE_MOVAD32_H, + ICLASS_AE_MOVAD16_3, + ICLASS_AE_MOVAD16_2, + ICLASS_AE_MOVAD16_1, + ICLASS_AE_MOVAD16_0, + ICLASS_AE_SRA64_32, + ICLASS_AE_PKSR32, + ICLASS_AE_PKSR24, + ICLASS_AE_PKSRF32, + ICLASS_AE_PKSR16, + ICLASS_AE_TRUNCA16P24S_L, + ICLASS_AE_TRUNCA16P24S_H, + ICLASS_AE_ADD32, + ICLASS_AE_SUB32, + ICLASS_AE_ADDSUB32, + ICLASS_AE_SUBADD32, + ICLASS_AE_ADD16, + ICLASS_AE_SUB16, + ICLASS_AE_ADD32_HL_LH, + ICLASS_AE_ADDSUB32_HL_LH, + ICLASS_AE_NEG32, + ICLASS_AE_ABS32, + ICLASS_AE_NEG32_L, + ICLASS_AE_ADD24S, + ICLASS_AE_SUB24S, + ICLASS_AE_ADD32S, + ICLASS_AE_SUB32S, + ICLASS_AE_ADDSUB32S, + ICLASS_AE_SUBADD32S, + ICLASS_AE_ADD16S, + ICLASS_AE_SUB16S, + ICLASS_AE_ADD32S_HL_LH, + ICLASS_AE_ADDSUB32S_HL_LH, + ICLASS_AE_NEG24S, + ICLASS_AE_ABS24S, + ICLASS_AE_NEG32S, + ICLASS_AE_ABS32S, + ICLASS_AE_NEG16S, + ICLASS_AE_ABS16S, + ICLASS_AE_ABS16, + ICLASS_AE_MULC16JS_H, + ICLASS_AE_MULC16JS_L, + ICLASS_AE_MULAC16JS_H, + ICLASS_AE_MULAC16JS_L, + ICLASS_AE_LT16, + ICLASS_AE_LE16, + ICLASS_AE_EQ16, + ICLASS_AE_LT32, + ICLASS_AE_LE32, + ICLASS_AE_EQ32, + ICLASS_AE_MIN32, + ICLASS_AE_MAX32, + ICLASS_AE_MINMAX32, + ICLASS_AE_MINMAX16, + ICLASS_AE_MIN16, + ICLASS_AE_MAX16, + ICLASS_AE_ADD64, + ICLASS_AE_SUB64, + ICLASS_AE_NEG64, + ICLASS_AE_ABS64, + ICLASS_AE_ADDSQ56S, + ICLASS_AE_SUBSQ56S, + ICLASS_AE_ADD64S, + ICLASS_AE_SUB64S, + ICLASS_AE_NEGSQ56S, + ICLASS_AE_ABSSQ56S, + ICLASS_AE_NEG64S, + ICLASS_AE_ABS64S, + ICLASS_AE_AND, + ICLASS_AE_NAND, + ICLASS_AE_OR, + ICLASS_AE_XOR, + ICLASS_AE_SLAI24, + ICLASS_AE_SRLI24, + ICLASS_AE_SRAI24, + ICLASS_AE_SLAS24, + ICLASS_AE_SRLS24, + ICLASS_AE_SRAS24, + ICLASS_AE_SRAI16, + ICLASS_AE_SRAI16R, + ICLASS_AE_SLAI32, + ICLASS_AE_SRLI32, + ICLASS_AE_SRAI32, + ICLASS_AE_SRAI32R, + ICLASS_AE_SLAS32, + ICLASS_AE_SRLS32, + ICLASS_AE_SRAS32, + ICLASS_AE_SLAA32, + ICLASS_AE_SRLA32, + ICLASS_AE_SRAA32, + ICLASS_AE_SLAI16S, + ICLASS_AE_SLAA16S, + ICLASS_AE_SRAA16S, + ICLASS_AE_SRAA16RS, + ICLASS_AE_SLAI24S, + ICLASS_AE_SLAS24S, + ICLASS_AE_SLAI32S, + ICLASS_AE_SLAS32S, + ICLASS_AE_SLAA32S, + ICLASS_AE_SRAA32S, + ICLASS_AE_SRAA32RS, + ICLASS_AE_SLASQ56, + ICLASS_AE_SRLSQ56, + ICLASS_AE_SRASQ56, + ICLASS_AE_SLAAQ56, + ICLASS_AE_SRLAQ56, + ICLASS_AE_SRAAQ56, + ICLASS_AE_SLAI64, + ICLASS_AE_SRLI64, + ICLASS_AE_SRAI64, + ICLASS_AE_SLAS64, + ICLASS_AE_SRLS64, + ICLASS_AE_SRAS64, + ICLASS_AE_SLAA64, + ICLASS_AE_SRLA64, + ICLASS_AE_SRAA64, + ICLASS_AE_SLAISQ56S, + ICLASS_AE_SLASSQ56S, + ICLASS_AE_SLAASQ56S, + ICLASS_AE_SLAI64S, + ICLASS_AE_SLAS64S, + ICLASS_AE_SLAA64S, + ICLASS_AE_LT64, + ICLASS_AE_LE64, + ICLASS_AE_EQ64, + ICLASS_AE_MAX64, + ICLASS_AE_MIN64, + ICLASS_AE_NSA64, + ICLASS_AE_NSAZ16_0, + ICLASS_AE_NSAZ32_L, + ICLASS_AE_MULS32F48P16S_LL, + ICLASS_AE_MULF32S_LL, + ICLASS_AE_MUL32_LL, + ICLASS_AE_MULF32R_LL, + ICLASS_AE_MULF32RA_LL, + ICLASS_AE_MULS32F48P16S_LH, + ICLASS_AE_MULF32S_LH, + ICLASS_AE_MUL32_LH, + ICLASS_AE_MULF32R_LH, + ICLASS_AE_MULF32RA_LH, + ICLASS_AE_MULS32F48P16S_HH, + ICLASS_AE_MULF32S_HH, + ICLASS_AE_MUL32_HH, + ICLASS_AE_MULF32R_HH, + ICLASS_AE_MULF32RA_HH, + ICLASS_AE_MULAS32F48P16S_LL, + ICLASS_AE_MULAF32S_LL, + ICLASS_AE_MULA32_LL, + ICLASS_AE_MULAF32R_LL, + ICLASS_AE_MULAF32RA_LL, + ICLASS_AE_MULAS32F48P16S_LH, + ICLASS_AE_MULAF32S_LH, + ICLASS_AE_MULA32_LH, + ICLASS_AE_MULAF32R_LH, + ICLASS_AE_MULAF32RA_LH, + ICLASS_AE_MULAS32F48P16S_HH, + ICLASS_AE_MULAF32S_HH, + ICLASS_AE_MULA32_HH, + ICLASS_AE_MULAF32R_HH, + ICLASS_AE_MULAF32RA_HH, + ICLASS_AE_MULSS32F48P16S_LL, + ICLASS_AE_MULSF32S_LL, + ICLASS_AE_MULS32_LL, + ICLASS_AE_MULSF32R_LL, + ICLASS_AE_MULSF32RA_LL, + ICLASS_AE_MULSS32F48P16S_LH, + ICLASS_AE_MULSF32S_LH, + ICLASS_AE_MULS32_LH, + ICLASS_AE_MULSF32R_LH, + ICLASS_AE_MULSF32RA_LH, + ICLASS_AE_MULSS32F48P16S_HH, + ICLASS_AE_MULSF32S_HH, + ICLASS_AE_MULS32_HH, + ICLASS_AE_MULSF32R_HH, + ICLASS_AE_MULSF32RA_HH, + ICLASS_AE_MUL32U_LL, + ICLASS_AE_MULA32U_LL, + ICLASS_AE_MULS32U_LL, + ICLASS_AE_MULF16SS_33, + ICLASS_AE_MULF16SS_22, + ICLASS_AE_MULF16SS_32, + ICLASS_AE_MULF16SS_21, + ICLASS_AE_MULF16SS_31, + ICLASS_AE_MULF16SS_30, + ICLASS_AE_MULF16SS_10, + ICLASS_AE_MULF16SS_20, + ICLASS_AE_MULF16SS_11, + ICLASS_AE_MULF16SS_00, + ICLASS_AE_MULSF16SS_33, + ICLASS_AE_MULSF16SS_22, + ICLASS_AE_MULSF16SS_32, + ICLASS_AE_MULSF16SS_21, + ICLASS_AE_MULSF16SS_31, + ICLASS_AE_MULSF16SS_30, + ICLASS_AE_MULSF16SS_10, + ICLASS_AE_MULSF16SS_20, + ICLASS_AE_MULSF16SS_11, + ICLASS_AE_MULSF16SS_00, + ICLASS_AE_MULAF16SS_33, + ICLASS_AE_MULAF16SS_22, + ICLASS_AE_MULAF16SS_32, + ICLASS_AE_MULAF16SS_21, + ICLASS_AE_MULAF16SS_31, + ICLASS_AE_MULAF16SS_30, + ICLASS_AE_MULAF16SS_10, + ICLASS_AE_MULAF16SS_20, + ICLASS_AE_MULAF16SS_11, + ICLASS_AE_MULAF16SS_00, + ICLASS_AE_MUL16S_00, + ICLASS_AE_MULA16S_00, + ICLASS_AE_MULS16S_00, + ICLASS_AE_MULAAFD16SS_33_22, + ICLASS_AE_MULAAFD16SS_13_02, + ICLASS_AE_MULAAFD16SS_11_00, + ICLASS_AE_MULSSFD16SS_33_22, + ICLASS_AE_MULSSFD16SS_13_02, + ICLASS_AE_MULSSFD16SS_11_00, + ICLASS_AE_MULZAAFD16SS_33_22, + ICLASS_AE_MULZAAFD16SS_13_02, + ICLASS_AE_MULZAAFD16SS_11_00, + ICLASS_AE_MULZSSFD16SS_33_22, + ICLASS_AE_MULZSSFD16SS_13_02, + ICLASS_AE_MULZSSFD16SS_11_00, + ICLASS_AE_MULF48Q32SP16S_L, + ICLASS_AE_MULF48Q32SP16U_L, + ICLASS_AE_MULQ32SP16S_L, + ICLASS_AE_MULQ32SP16U_L, + ICLASS_AE_MULAF48Q32SP16S_L, + ICLASS_AE_MULAF48Q32SP16U_L, + ICLASS_AE_MULAQ32SP16S_L, + ICLASS_AE_MULAQ32SP16U_L, + ICLASS_AE_MULSF48Q32SP16S_L, + ICLASS_AE_MULSF48Q32SP16U_L, + ICLASS_AE_MULSQ32SP16S_L, + ICLASS_AE_MULSQ32SP16U_L, + ICLASS_AE_MULFP24X2RA, + ICLASS_AE_MULFP24X2R, + ICLASS_AE_MULAFP24X2RA, + ICLASS_AE_MULAFP24X2R, + ICLASS_AE_MULSFP24X2RA, + ICLASS_AE_MULSFP24X2R, + ICLASS_AE_MULZAAFD32S_HH_LL, + ICLASS_AE_MULZAAFD32RA_HH_LL, + ICLASS_AE_MULZAAD32_HH_LL, + ICLASS_AE_MULZAAFD32S_HL_LH, + ICLASS_AE_MULZAAFD32RA_HL_LH, + ICLASS_AE_MULZAAD32_HL_LH, + ICLASS_AE_MULZASFD32S_HH_LL, + ICLASS_AE_MULZASFD32RA_HH_LL, + ICLASS_AE_MULZASD32_HH_LL, + ICLASS_AE_MULZASFD32S_HL_LH, + ICLASS_AE_MULZASFD32RA_HL_LH, + ICLASS_AE_MULZASD32_HL_LH, + ICLASS_AE_MULZSAFD32S_HH_LL, + ICLASS_AE_MULZSAFD32RA_HH_LL, + ICLASS_AE_MULZSAD32_HH_LL, + ICLASS_AE_MULZSSFD32S_HH_LL, + ICLASS_AE_MULZSSFD32RA_HH_LL, + ICLASS_AE_MULZSSD32_HH_LL, + ICLASS_AE_MULZSSFD32S_HL_LH, + ICLASS_AE_MULZSSFD32RA_HL_LH, + ICLASS_AE_MULZSSD32_HL_LH, + ICLASS_AE_MULAAFD32S_HH_LL, + ICLASS_AE_MULAAFD32RA_HH_LL, + ICLASS_AE_MULAAD32_HH_LL, + ICLASS_AE_MULAAFD32S_HL_LH, + ICLASS_AE_MULAAFD32RA_HL_LH, + ICLASS_AE_MULAAD32_HL_LH, + ICLASS_AE_MULASFD32S_HH_LL, + ICLASS_AE_MULASFD32RA_HH_LL, + ICLASS_AE_MULASD32_HH_LL, + ICLASS_AE_MULASFD32S_HL_LH, + ICLASS_AE_MULASFD32RA_HL_LH, + ICLASS_AE_MULASD32_HL_LH, + ICLASS_AE_MULSAFD32S_HH_LL, + ICLASS_AE_MULSAFD32RA_HH_LL, + ICLASS_AE_MULSAD32_HH_LL, + ICLASS_AE_MULSSFD32S_HH_LL, + ICLASS_AE_MULSSFD32RA_HH_LL, + ICLASS_AE_MULSSD32_HH_LL, + ICLASS_AE_MULSSFD32S_HL_LH, + ICLASS_AE_MULSSFD32RA_HL_LH, + ICLASS_AE_MULSSD32_HL_LH, + ICLASS_AE_MULF32X16_L0, + ICLASS_AE_MUL32X16_L0, + ICLASS_AE_MULF32X16_L1, + ICLASS_AE_MUL32X16_L1, + ICLASS_AE_MULF32X16_L2, + ICLASS_AE_MUL32X16_L2, + ICLASS_AE_MULF32X16_L3, + ICLASS_AE_MUL32X16_L3, + ICLASS_AE_MULF32X16_H0, + ICLASS_AE_MUL32X16_H0, + ICLASS_AE_MULF32X16_H1, + ICLASS_AE_MUL32X16_H1, + ICLASS_AE_MULF32X16_H2, + ICLASS_AE_MUL32X16_H2, + ICLASS_AE_MULF32X16_H3, + ICLASS_AE_MUL32X16_H3, + ICLASS_AE_MULAF32X16_L0, + ICLASS_AE_MULA32X16_L0, + ICLASS_AE_MULAF32X16_L1, + ICLASS_AE_MULA32X16_L1, + ICLASS_AE_MULAF32X16_L2, + ICLASS_AE_MULA32X16_L2, + ICLASS_AE_MULAF32X16_L3, + ICLASS_AE_MULA32X16_L3, + ICLASS_AE_MULAF32X16_H0, + ICLASS_AE_MULA32X16_H0, + ICLASS_AE_MULAF32X16_H1, + ICLASS_AE_MULA32X16_H1, + ICLASS_AE_MULAF32X16_H2, + ICLASS_AE_MULA32X16_H2, + ICLASS_AE_MULAF32X16_H3, + ICLASS_AE_MULA32X16_H3, + ICLASS_AE_MULSF32X16_L0, + ICLASS_AE_MULS32X16_L0, + ICLASS_AE_MULSF32X16_L1, + ICLASS_AE_MULS32X16_L1, + ICLASS_AE_MULSF32X16_L2, + ICLASS_AE_MULS32X16_L2, + ICLASS_AE_MULSF32X16_L3, + ICLASS_AE_MULS32X16_L3, + ICLASS_AE_MULSF32X16_H0, + ICLASS_AE_MULS32X16_H0, + ICLASS_AE_MULSF32X16_H1, + ICLASS_AE_MULS32X16_H1, + ICLASS_AE_MULSF32X16_H2, + ICLASS_AE_MULS32X16_H2, + ICLASS_AE_MULSF32X16_H3, + ICLASS_AE_MULS32X16_H3, + ICLASS_AE_MULAAFD32X16_H3_L2, + ICLASS_AE_MULAAD32X16_H3_L2, + ICLASS_AE_MULAAFD32X16_H1_L0, + ICLASS_AE_MULAAD32X16_H1_L0, + ICLASS_AE_MULASFD32X16_H3_L2, + ICLASS_AE_MULASD32X16_H3_L2, + ICLASS_AE_MULASFD32X16_H1_L0, + ICLASS_AE_MULASD32X16_H1_L0, + ICLASS_AE_MULSAFD32X16_H3_L2, + ICLASS_AE_MULSAD32X16_H3_L2, + ICLASS_AE_MULSAFD32X16_H1_L0, + ICLASS_AE_MULSAD32X16_H1_L0, + ICLASS_AE_MULSSFD32X16_H3_L2, + ICLASS_AE_MULSSD32X16_H3_L2, + ICLASS_AE_MULSSFD32X16_H1_L0, + ICLASS_AE_MULSSD32X16_H1_L0, + ICLASS_AE_MULZAAFD32X16_H3_L2, + ICLASS_AE_MULZAAD32X16_H3_L2, + ICLASS_AE_MULZAAFD32X16_H1_L0, + ICLASS_AE_MULZAAD32X16_H1_L0, + ICLASS_AE_MULZASFD32X16_H3_L2, + ICLASS_AE_MULZASD32X16_H3_L2, + ICLASS_AE_MULZASFD32X16_H1_L0, + ICLASS_AE_MULZASD32X16_H1_L0, + ICLASS_AE_MULZSAFD32X16_H3_L2, + ICLASS_AE_MULZSAD32X16_H3_L2, + ICLASS_AE_MULZSAFD32X16_H1_L0, + ICLASS_AE_MULZSAD32X16_H1_L0, + ICLASS_AE_MULZSSFD32X16_H3_L2, + ICLASS_AE_MULZSSD32X16_H3_L2, + ICLASS_AE_MULZSSFD32X16_H1_L0, + ICLASS_AE_MULZSSD32X16_H1_L0, + ICLASS_AE_MULZAAFD32X16_H2_L3, + ICLASS_AE_MULZAAFD32X16_H0_L1, + ICLASS_AE_MULAAFD32X16_H2_L3, + ICLASS_AE_MULAAFD32X16_H0_L1, + ICLASS_AE_MULZAAD32X16_H2_L3, + ICLASS_AE_MULZAAD32X16_H0_L1, + ICLASS_AE_MULAAD32X16_H2_L3, + ICLASS_AE_MULAAD32X16_H0_L1, + ICLASS_AE_MULP32X16X2_H, + ICLASS_AE_MULFP32X16X2RS_H, + ICLASS_AE_MULFP32X16X2RAS_H, + ICLASS_AE_MULFP32X16X2S_H, + ICLASS_AE_MULP32X16X2_L, + ICLASS_AE_MULFP32X16X2RS_L, + ICLASS_AE_MULFP32X16X2RAS_L, + ICLASS_AE_MULFP32X16X2S_L, + ICLASS_AE_MULAP32X16X2_H, + ICLASS_AE_MULAFP32X16X2RS_H, + ICLASS_AE_MULAFP32X16X2RAS_H, + ICLASS_AE_MULAFP32X16X2S_H, + ICLASS_AE_MULAP32X16X2_L, + ICLASS_AE_MULAFP32X16X2RS_L, + ICLASS_AE_MULAFP32X16X2RAS_L, + ICLASS_AE_MULAFP32X16X2S_L, + ICLASS_AE_MULSP32X16X2_H, + ICLASS_AE_MULSFP32X16X2RS_H, + ICLASS_AE_MULSFP32X16X2RAS_H, + ICLASS_AE_MULSFP32X16X2S_H, + ICLASS_AE_MULSP32X16X2_L, + ICLASS_AE_MULSFP32X16X2RS_L, + ICLASS_AE_MULSFP32X16X2RAS_L, + ICLASS_AE_MULSFP32X16X2S_L, + ICLASS_AE_MULP32X2, + ICLASS_AE_MULFP32X2RS, + ICLASS_AE_MULFP32X2RAS, + ICLASS_AE_MULFP32X2TS, + ICLASS_AE_MULP32X2T, + ICLASS_AE_MULAP32X2, + ICLASS_AE_MULAFP32X2RS, + ICLASS_AE_MULAFP32X2RAS, + ICLASS_AE_MULAFP32X2TS, + ICLASS_AE_MULAP32X2T, + ICLASS_AE_MULSP32X2, + ICLASS_AE_MULSFP32X2RS, + ICLASS_AE_MULSFP32X2RAS, + ICLASS_AE_MULSFP32X2TS, + ICLASS_AE_MULSP32X2T, + ICLASS_AE_MULFP16X4S, + ICLASS_AE_MULFP16X4RAS, + ICLASS_AE_MULC32, + ICLASS_AE_MULFC24RA, + ICLASS_AE_MULFC32RAS, + ICLASS_AE_MULC32X16_L, + ICLASS_AE_MULFC32X16RAS_L, + ICLASS_AE_MULC32X16_H, + ICLASS_AE_MULFC32X16RAS_H, + ICLASS_AE_MULAC32, + ICLASS_AE_MULAFC24RA, + ICLASS_AE_MULAFC32RAS, + ICLASS_AE_MULAC32X16_L, + ICLASS_AE_MULAFC32X16RAS_L, + ICLASS_AE_MULAC32X16_H, + ICLASS_AE_MULAFC32X16RAS_H, + ICLASS_AE_MULF16X4SS, + ICLASS_AE_MULAF16X4SS, + ICLASS_AE_MULSF16X4SS, + ICLASS_AE_MUL16X4S, + ICLASS_AE_MULA16X4S, + ICLASS_AE_MULS16X4S, + ICLASS_AE_MUL16X4, + ICLASS_AE_MULA16X4, + ICLASS_AE_MULS16X4, + ICLASS_AE_MULFD32X2S_FIR_H, + ICLASS_AE_MULFD32X2RA_FIR_H, + ICLASS_AE_MULFD32X2S_FIR_L, + ICLASS_AE_MULFD32X2RA_FIR_L, + ICLASS_AE_MULFD32X16X2_FIR_HH, + ICLASS_AE_MULFD32X16X2_FIR_HL, + ICLASS_AE_MULFD32X16X2_FIR_LH, + ICLASS_AE_MULFD32X16X2_FIR_LL, + ICLASS_AE_MULAFD32X2S_FIR_H, + ICLASS_AE_MULAFD32X2RA_FIR_H, + ICLASS_AE_MULAFD32X2S_FIR_L, + ICLASS_AE_MULAFD32X2RA_FIR_L, + ICLASS_AE_MULAFD32X16X2_FIR_HH, + ICLASS_AE_MULAFD32X16X2_FIR_HL, + ICLASS_AE_MULAFD32X16X2_FIR_LH, + ICLASS_AE_MULAFD32X16X2_FIR_LL, + ICLASS_AE_MULC16S_H, + ICLASS_AE_MULC16S_L, + ICLASS_AE_MULAC16S_H, + ICLASS_AE_MULAC16S_L, + ICLASS_AE_MULFC16RAS, + ICLASS_AE_MULAFC16RAS, + ICLASS_AE_MUL16JS, + ICLASS_AE_ADDANDSUBRNG16RAS_S1, + ICLASS_AE_ADDANDSUBRNG16RAS_S2, + ICLASS_AE_CONJ16S, + ICLASS_AE_MULFQ16X2_FIR_3, + ICLASS_AE_MULFQ16X2_FIR_2, + ICLASS_AE_MULFQ16X2_FIR_1, + ICLASS_AE_MULFQ16X2_FIR_0, + ICLASS_AE_MULAFQ16X2_FIR_3, + ICLASS_AE_MULAFQ16X2_FIR_2, + ICLASS_AE_MULAFQ16X2_FIR_1, + ICLASS_AE_MULAFQ16X2_FIR_0, + ICLASS_AE_MULZAAAAFQ32X16, + ICLASS_AE_MULAAAAFQ32X16, + ICLASS_AE_MULZAAAAQ32X16, + ICLASS_AE_MULAAAAQ32X16, + ICLASS_AE_MUL16_00, + ICLASS_AE_MULA16_00, + ICLASS_AE_MULZAAAAQ16, + ICLASS_AE_MULAAAAQ16, + ICLASS_AE_DIV64D32_H, + ICLASS_AE_DIV64D32_L, + ICLASS_AE_SHA32, + ICLASS_AE_VLDL32T, + ICLASS_AE_VLDL16T, + ICLASS_AE_VLDL16C, + ICLASS_AE_VLDL16C_IP, + ICLASS_AE_VLDL16C_IC, + ICLASS_AE_VLDL16C_IC1, + ICLASS_AE_VLDSHT, + ICLASS_AE_LB, + ICLASS_AE_LBI, + ICLASS_AE_LBK, + ICLASS_AE_LBKI, + ICLASS_AE_LBS, + ICLASS_AE_LBSI, + ICLASS_AE_DB, + ICLASS_AE_DBI, + ICLASS_AE_DB_IC, + ICLASS_AE_DBI_IC, + ICLASS_AE_DB_IC1, + ICLASS_AE_DBI_IC1, + ICLASS_AE_DB_IP, + ICLASS_AE_DBI_IP, + ICLASS_AE_ARDECNORM16, + ICLASS_AE_LBKI_DBI_IC, + ICLASS_AE_LBKI_DBI_IP, + ICLASS_AE_LBKI_DBI, + ICLASS_AE_LBI_DBI_IC, + ICLASS_AE_LBI_DBI_IP, + ICLASS_AE_LBI_DBI, + ICLASS_AE_LBK_DB_IC, + ICLASS_AE_LBK_DB_IP, + ICLASS_AE_LBK_DB, + ICLASS_AE_LB_DB_IC, + ICLASS_AE_LB_DB_IP, + ICLASS_AE_LB_DB, + ICLASS_AE_VLEL32T, + ICLASS_AE_VLEL16T, + ICLASS_AE_SB, + ICLASS_AE_SBI, + ICLASS_AE_VLES16C, + ICLASS_AE_SBF, + ICLASS_AE_SB_IC, + ICLASS_AE_SBI_IC, + ICLASS_AE_VLES16C_IC, + ICLASS_AE_SBF_IC, + ICLASS_AE_SB_IC1, + ICLASS_AE_SBI_IC1, + ICLASS_AE_VLES16C_IC1, + ICLASS_AE_SBF_IC1, + ICLASS_AE_SB_IP, + ICLASS_AE_SBI_IP, + ICLASS_AE_VLES16C_IP, + ICLASS_AE_SBF_IP, + ICLASS_AE_SEXT32, + ICLASS_AE_MOVAE, + ICLASS_AE_MOVEA, + ICLASS_AE_MOVEEP, + ICLASS_AE_SEXT72, + ICLASS_AE_ADD72, + ICLASS_AE_SUB72, + ICLASS_AE_ADD72X64, + ICLASS_AE_SUB72X64, + ICLASS_AE_MUL32EP_HH, + ICLASS_AE_MULA32EP_HH, + ICLASS_AE_MULS32EP_HH, + ICLASS_AE_MULZAAD32EP_HH_LL, + ICLASS_AE_MULZSSD32EP_HH_LL, + ICLASS_AE_MULAAD32EP_HH_LL, + ICLASS_AE_MULSSD32EP_HH_LL, + ICLASS_AE_MULAAD32USEP_HL_LH, + ICLASS_AE_MULZAAD32USEP_HL_LH, + ICLASS_AE_MUL32USEP_LH, + ICLASS_AE_MULA32USEP_LH, + ICLASS_AE_MUL32USEP_LL, + ICLASS_AE_MULA32USEP_LL, + ICLASS_AE_SRAI72, + ICLASS_AE_SLAI72, + ICLASS_AE_SAT64S, + ICLASS_AE_L16SI_N, + ICLASS_AE_L16UI_N, + ICLASS_AE_S16I_N, + ICLASS_AE_LALIGN128_I, + ICLASS_AE_SALIGN128_I, + ICLASS_AE_LA128_PP, + ICLASS_AE_SA128POS_FP, + ICLASS_AE_LA8X4S_IP, + ICLASS_AE_LA8X4U_IP, + ICLASS_AE_LA8X8X2_IP, + ICLASS_AE_LA16X4X2_IP, + ICLASS_AE_LA32X2X2_IP, + ICLASS_AE_LA8X8X2_IC, + ICLASS_AE_LA16X4X2_IC, + ICLASS_AE_LA32X2X2_IC, + ICLASS_AE_LA8X8X2_IC1, + ICLASS_AE_LA16X4X2_IC1, + ICLASS_AE_LA32X2X2_IC1, + ICLASS_AE_LA8X8X2_IC2, + ICLASS_AE_LA16X4X2_IC2, + ICLASS_AE_LA32X2X2_IC2, + ICLASS_AE_SA8X8X2_IP, + ICLASS_AE_SA16X4X2_IP, + ICLASS_AE_SA32X2X2_IP, + ICLASS_AE_SA8X8X2_IC, + ICLASS_AE_SA16X4X2_IC, + ICLASS_AE_SA32X2X2_IC, + ICLASS_AE_SA8X8X2_IC1, + ICLASS_AE_SA16X4X2_IC1, + ICLASS_AE_SA32X2X2_IC1, + ICLASS_AE_SA8X8X2_IC2, + ICLASS_AE_SA16X4X2_IC2, + ICLASS_AE_SA32X2X2_IC2, + ICLASS_AE_ABS8, + ICLASS_AE_ABS8S, + ICLASS_AE_NEG8S, + ICLASS_AE_ADD8, + ICLASS_AE_SUB8, + ICLASS_AE_MAX8, + ICLASS_AE_MIN8, + ICLASS_AE_ADD8S, + ICLASS_AE_SUB8S, + ICLASS_AE_LE8, + ICLASS_AE_LT8, + ICLASS_AE_EQ8, + ICLASS_AE_SATU16X4, + ICLASS_AE_SAT32X2, + ICLASS_AE_SATU32X2, + ICLASS_AE_SAT8X8X16, + ICLASS_AE_SATU8X8X16, + ICLASS_AE_SAT8X4X32_L, + ICLASS_AE_SATU8X4X32_L, + ICLASS_AE_ROUND8X8F16SSYM, + ICLASS_AE_ROUND8X8F16SASYM, + ICLASS_AE_ROUND8X4F32SSYM_L, + ICLASS_AE_ROUND8X4F32SASYM_L, + ICLASS_AE_MOVDA8, + ICLASS_AE_MOVAD8, + ICLASS_AE_MOVDX2, + ICLASS_AE_ADDANDSUB32J, + ICLASS_AE_ADDW8, + ICLASS_AE_ADDW16, + ICLASS_AE_ADDW32, + ICLASS_AE_SUBW8, + ICLASS_AE_SUBW16, + ICLASS_AE_SUBW32, + ICLASS_AE_ACCW8, + ICLASS_AE_ACCW16, + ICLASS_AE_ACCW32, + ICLASS_AE_ADDW8U, + ICLASS_AE_SUBW8U, + ICLASS_AE_ACCW8U, + ICLASS_AE_MULFP32X2S_HH_LL, + ICLASS_AE_MULAFP32X2S_HH_LL, + ICLASS_AE_MULSFP32X2S_HH_LL, + ICLASS_AE_MULFP32X2S_HL_LH, + ICLASS_AE_MULAFP32X2S_HL_LH, + ICLASS_AE_MULSFP32X2S_HL_LH, + ICLASS_AE_MULZAAF2D32S_HH_LL, + ICLASS_AE_MULZASF2D32S_HH_LL, + ICLASS_AE_MULZSAF2D32S_HH_LL, + ICLASS_AE_MULZSSF2D32S_HH_LL, + ICLASS_AE_MULAAF2D32S_HH_LL, + ICLASS_AE_MULASF2D32S_HH_LL, + ICLASS_AE_MULSAF2D32S_HH_LL, + ICLASS_AE_MULSSF2D32S_HH_LL, + ICLASS_AE_MULZAAF2D32S_HL_LH, + ICLASS_AE_MULZASF2D32S_HL_LH, + ICLASS_AE_MULZSAF2D32S_HL_LH, + ICLASS_AE_MULZSSF2D32S_HL_LH, + ICLASS_AE_MULAAF2D32S_HL_LH, + ICLASS_AE_MULASF2D32S_HL_LH, + ICLASS_AE_MULSAF2D32S_HL_LH, + ICLASS_AE_MULSSF2D32S_HL_LH, + ICLASS_AE_MUL32S_HH, + ICLASS_AE_MULA32S_HH, + ICLASS_AE_MULS32S_HH, + ICLASS_AE_MUL32S_LL, + ICLASS_AE_MULA32S_LL, + ICLASS_AE_MULS32S_LL, + ICLASS_AE_MUL32S_HL, + ICLASS_AE_MULA32S_HL, + ICLASS_AE_MULS32S_HL, + ICLASS_AE_MUL32S_LH, + ICLASS_AE_MULA32S_LH, + ICLASS_AE_MULS32S_LH, + ICLASS_AE_MUL32X2S_HH_LL, + ICLASS_AE_MULA32X2S_HH_LL, + ICLASS_AE_MULS32X2S_HH_LL, + ICLASS_AE_MUL32X2S_HL_LH, + ICLASS_AE_MULA32X2S_HL_LH, + ICLASS_AE_MULS32X2S_HL_LH, + ICLASS_AE_MULZAAD32S_HH_LL, + ICLASS_AE_MULZASD32S_HH_LL, + ICLASS_AE_MULZSAD32S_HH_LL, + ICLASS_AE_MULZSSD32S_HH_LL, + ICLASS_AE_MULAAD32S_HH_LL, + ICLASS_AE_MULASD32S_HH_LL, + ICLASS_AE_MULSAD32S_HH_LL, + ICLASS_AE_MULSSD32S_HH_LL, + ICLASS_AE_MULZAAD32S_HL_LH, + ICLASS_AE_MULZASD32S_HL_LH, + ICLASS_AE_MULZSAD32S_HL_LH, + ICLASS_AE_MULZSSD32S_HL_LH, + ICLASS_AE_MULAAD32S_HL_LH, + ICLASS_AE_MULASD32S_HL_LH, + ICLASS_AE_MULSAD32S_HL_LH, + ICLASS_AE_MULSSD32S_HL_LH, + ICLASS_AE_MULF32X2RA_HH_LL, + ICLASS_AE_MULAF32X2RA_HH_LL, + ICLASS_AE_MULSF32X2RA_HH_LL, + ICLASS_AE_MULF32X2RA_HL_LH, + ICLASS_AE_MULAF32X2RA_HL_LH, + ICLASS_AE_MULSF32X2RA_HL_LH, + ICLASS_AE_MULZAAF2D32RA_HH_LL, + ICLASS_AE_MULZASF2D32RA_HH_LL, + ICLASS_AE_MULZSAF2D32RA_HH_LL, + ICLASS_AE_MULZSSF2D32RA_HH_LL, + ICLASS_AE_MULAAF2D32RA_HH_LL, + ICLASS_AE_MULASF2D32RA_HH_LL, + ICLASS_AE_MULSAF2D32RA_HH_LL, + ICLASS_AE_MULSSF2D32RA_HH_LL, + ICLASS_AE_MULZAAF2D32RA_HL_LH, + ICLASS_AE_MULZASF2D32RA_HL_LH, + ICLASS_AE_MULZSAF2D32RA_HL_LH, + ICLASS_AE_MULZSSF2D32RA_HL_LH, + ICLASS_AE_MULAAF2D32RA_HL_LH, + ICLASS_AE_MULASF2D32RA_HL_LH, + ICLASS_AE_MULSAF2D32RA_HL_LH, + ICLASS_AE_MULSSF2D32RA_HL_LH, + ICLASS_AE_MULF32X2R_HH_LL, + ICLASS_AE_MULAF32X2R_HH_LL, + ICLASS_AE_MULSF32X2R_HH_LL, + ICLASS_AE_MULF32X2R_HL_LH, + ICLASS_AE_MULAF32X2R_HL_LH, + ICLASS_AE_MULSF32X2R_HL_LH, + ICLASS_AE_MULFC32W, + ICLASS_AE_MULAFC32W, + ICLASS_AE_MULFCJ32W, + ICLASS_AE_MULAFCJ32W, + ICLASS_AE_MULFCJ32RAS, + ICLASS_AE_MULAFCJ32RAS, + ICLASS_AE_MULF2P32X4RS, + ICLASS_AE_MULAF2P32X4RS, + ICLASS_AE_MULSF2P32X4RS, + ICLASS_AE_MULF2P32X4RAS, + ICLASS_AE_MULAF2P32X4RAS, + ICLASS_AE_MULSF2P32X4RAS, + ICLASS_AE_MULP32X2S, + ICLASS_AE_MUL2P32X4S, + ICLASS_AE_MUL2P32X4, + ICLASS_AE_MULA2P32X4, + ICLASS_AE_MULS2P32X4, + ICLASS_AE_MUL2P32X4T, + ICLASS_AE_MULA2P32X4T, + ICLASS_AE_MULS2P32X4T, + ICLASS_AE_MULZAA32X2_HH_LL, + ICLASS_AE_MULZSS32X2_HH_LL, + ICLASS_AE_MULAA32X2_HH_LL, + ICLASS_AE_MULSS32X2_HH_LL, + ICLASS_AE_MULCJ32, + ICLASS_AE_MULACJ32, + ICLASS_AE_MULADDF32RS, + ICLASS_AE_MULADDF32RAS, + ICLASS_AE_MULSUBF32RS, + ICLASS_AE_MULSUBF32RAS, + ICLASS_AE_MULFC32RA, + ICLASS_AE_MULAFC32RA, + ICLASS_AE_MULCJ32W, + ICLASS_AE_MULACJ32W, + ICLASS_AE_MULC32W, + ICLASS_AE_MULAC32W, + ICLASS_AE_MULF2D32X2WS, + ICLASS_AE_MULZAAAA2Q16, + ICLASS_AE_MULAAAA2Q16, + ICLASS_AE_MULP16S_H, + ICLASS_AE_MULAP16S_H, + ICLASS_AE_MULSP16S_H, + ICLASS_AE_MULP16S_L, + ICLASS_AE_MULAP16S_L, + ICLASS_AE_MULSP16S_L, + ICLASS_AE_MULC16W_H, + ICLASS_AE_MULAC16W_H, + ICLASS_AE_MULC16W_L, + ICLASS_AE_MULAC16W_L, + ICLASS_AE_MUL2C16S, + ICLASS_AE_MULA2C16S, + ICLASS_AE_MULFC16S, + ICLASS_AE_MULAFC16S, + ICLASS_AE_MULFCJ16S, + ICLASS_AE_MULAFCJ16S, + ICLASS_AE_MULFCJ16RAS, + ICLASS_AE_MULAFCJ16RAS, + ICLASS_AE_MULC16S, + ICLASS_AE_MULAC16S, + ICLASS_AE_MULFP16X4RS, + ICLASS_AE_MULFD16X16X4RAS, + ICLASS_AE_MULP16X16X4S, + ICLASS_AE_MULAP16X16X4S, + ICLASS_AE_MULSP16X16X4S, + ICLASS_AE_MULZAA2D16SS_HH_LL, + ICLASS_AE_MULZAA2D16SS_HL_LH, + ICLASS_AE_MULZSS2D16SS_HH_LL, + ICLASS_AE_MULZSS2D16SS_HL_LH, + ICLASS_AE_MULAA2D16SS_HH_LL, + ICLASS_AE_MULAA2D16SS_HL_LH, + ICLASS_AE_MULSS2D16SS_HH_LL, + ICLASS_AE_MULSS2D16SS_HL_LH, + ICLASS_AE_MULZAAFD16SS_HH_LL, + ICLASS_AE_MULZAAFD16SS_HL_LH, + ICLASS_AE_MULZSSFD16SS_HH_LL, + ICLASS_AE_MULZSSFD16SS_HL_LH, + ICLASS_AE_MULAAFD16SS_HH_LL, + ICLASS_AE_MULAAFD16SS_HL_LH, + ICLASS_AE_MULSSFD16SS_HH_LL, + ICLASS_AE_MULSSFD16SS_HL_LH, + ICLASS_AE_MULFD16X16X4WS, + ICLASS_AE_MULZAAAA2Q16X8, + ICLASS_AE_MULAAAA2Q16X8, + ICLASS_AE_MULZAAAA2Q8, + ICLASS_AE_MULAAAA2Q8, + ICLASS_AE_MULC32X16W_H, + ICLASS_AE_MULAC32X16W_H, + ICLASS_AE_MULC32X16W_L, + ICLASS_AE_MULAC32X16W_L, + ICLASS_AE_MULPC32X16X2, + ICLASS_AE_MULAPC32X16X2, + ICLASS_AE_MULFP32X16_H, + ICLASS_AE_MULAFP32X16_H, + ICLASS_AE_MULSFP32X16_H, + ICLASS_AE_MULFP32X16_L, + ICLASS_AE_MULAFP32X16_L, + ICLASS_AE_MULSFP32X16_L, + ICLASS_AE_MULFC32X16W_H, + ICLASS_AE_MULAFC32X16W_H, + ICLASS_AE_MULFC32X16W_L, + ICLASS_AE_MULAFC32X16W_L, + ICLASS_AE_MULFCJ32X16W_H, + ICLASS_AE_MULAFCJ32X16W_H, + ICLASS_AE_MULFCJ32X16W_L, + ICLASS_AE_MULAFCJ32X16W_L, + ICLASS_AE_MULF2P32X16X4RAS, + ICLASS_AE_MULAF2P32X16X4RAS, + ICLASS_AE_MULSF2P32X16X4RAS, + ICLASS_AE_MULF2P32X16X4RS, + ICLASS_AE_MULAF2P32X16X4RS, + ICLASS_AE_MULSF2P32X16X4RS, + ICLASS_AE_MULF2P32X16X4S, + ICLASS_AE_MULAF2P32X16X4S, + ICLASS_AE_MULSF2P32X16X4S, + ICLASS_AE_MULFPC32X16X2RAS, + ICLASS_AE_MULAFPC32X16X2RAS, + ICLASS_AE_MULFPCJ32X16X2RAS, + ICLASS_AE_MULAFPCJ32X16X2RAS, + ICLASS_AE_MULZAAAA2Q32X16, + ICLASS_AE_MULAAAA2Q32X16, + ICLASS_AE_MUL2Q32X16_FIR_H, + ICLASS_AE_MULA2Q32X16_FIR_H, + ICLASS_AE_MUL2Q32X16_FIR_L, + ICLASS_AE_MULA2Q32X16_FIR_L, + ICLASS_AE_SRAI8, + ICLASS_AE_SRAI8R, + ICLASS_AE_SRLI8, + ICLASS_AE_SLAI8, + ICLASS_AE_SLAI8S, + ICLASS_AE_SLAA8, + ICLASS_AE_SRLA8, + ICLASS_AE_SLAA8S, + ICLASS_AE_SRAA8RS, + ICLASS_AE_SRAA8S, + ICLASS_AE_SRLI16, + ICLASS_AE_SLAI16, + ICLASS_AE_SLAA16, + ICLASS_AE_SRLA16, + ICLASS_AE_SRAI16SYM, + ICLASS_AE_SRAA16SYMS, + ICLASS_AE_SRAI32SYM, + ICLASS_AE_SRAA32SYMS, + ICLASS_AE_SRAV16RS, + ICLASS_AE_SRAV32RS, + ICLASS_AE_CVTI32X4F8_H, + ICLASS_AE_CVTI32X4F8_L, + ICLASS_AE_CVTI32X4F8S_H, + ICLASS_AE_CVTI32X4F8S_L, + ICLASS_AE_CVTA32X4F8_H, + ICLASS_AE_CVTA32X4F8_L, + ICLASS_AE_CVTA32X4F8S_H, + ICLASS_AE_CVTA32X4F8S_L, + ICLASS_AE_CVTI32X4F8U_H, + ICLASS_AE_CVTI32X4F8U_L, + ICLASS_AE_CVTI32X4F8US_H, + ICLASS_AE_CVTI32X4F8US_L, + ICLASS_AE_CVTA32X4F8U_H, + ICLASS_AE_CVTA32X4F8U_L, + ICLASS_AE_CVTA32X4F8US_H, + ICLASS_AE_CVTA32X4F8US_L, + ICLASS_AE_CVTI32X4F16, + ICLASS_AE_CVTI32X4F16S, + ICLASS_AE_CVTA32X4F16, + ICLASS_AE_CVTA32X4F16S, + ICLASS_AE_CVTI32X4F16U, + ICLASS_AE_CVTI32X4F16US, + ICLASS_AE_CVTA32X4F16U, + ICLASS_AE_CVTA32X4F16US, + ICLASS_AE_CVTI16X4X2F8, + ICLASS_AE_CVTI16X4X2F8S, + ICLASS_AE_CVTA16X4X2F8, + ICLASS_AE_CVTA16X4X2F8S, + ICLASS_AE_CVTI16X4X2F8U, + ICLASS_AE_CVTI16X4X2F8US, + ICLASS_AE_CVTA16X4X2F8U, + ICLASS_AE_CVTA16X4X2F8US, + ICLASS_AE_SEL8X8, + ICLASS_AE_SHFL8X8, + ICLASS_AE_SEL16X4, + ICLASS_AE_SHFL16X4, + ICLASS_AE_DSEL8X8, + ICLASS_AE_DSEL16X4, + ICLASS_AE_SEL8X8I, + ICLASS_AE_RMAX8X8, + ICLASS_AE_RMIN8X8, + ICLASS_AE_RMAX16X4, + ICLASS_AE_RMIN16X4, + ICLASS_AE_SORT16X4, + ICLASS_AE_RADD8X8_H, + ICLASS_AE_RADDA8X8_H, + ICLASS_AE_RADD8X8_L, + ICLASS_AE_RADDA8X8_L, + ICLASS_AE_RADD16X4, + ICLASS_AE_RADDA16X4, + ICLASS_AE_BMAX8X8_H, + ICLASS_AE_BMAX8X8_L, + ICLASS_AE_BMIN8X8_H, + ICLASS_AE_BMIN8X8_L, + ICLASS_AE_BMAX16X4, + ICLASS_AE_BMIN16X4, + ICLASS_AE_BMAX32X2, + ICLASS_AE_BMIN32X2, + ICLASS_AE_ADDINV16S, + ICLASS_AE_ADDINV32S, + ICLASS_AE_MOVT16X8, + ICLASS_AE_MOVT8X16_H, + ICLASS_AE_MOVT8X16_L, + ICLASS_AE_MOVBD1X4, + ICLASS_AE_MOVBD1X2, + ICLASS_AE_MOVNEG32S_T, + ICLASS_AE_MOVDEXT, + ICLASS_AE_MOVADEXT_H, + ICLASS_AE_MOVADEXT_L, + ICLASS_AE_NSA16X4, + ICLASS_AE_NSAZ32X4, + ICLASS_AE_NSA32X4, + ICLASS_AE_TRUNCI16X4F32S, + ICLASS_AE_TRUNCI16X4F64S, + ICLASS_AE_TRUNCA16X4F32S, + ICLASS_AE_TRUNCA16X4F64S, + ICLASS_AE_ADDC32, + ICLASS_AE_SUBC32, + ICLASS_AE_ADDC32U, + ICLASS_AE_SUBC32U, + ICLASS_AE_EXPADD16_H, + ICLASS_AE_EXPSUB16_H, + ICLASS_AE_EXPADD16_L, + ICLASS_AE_EXPSUB16_L, + ICLASS_AE_ADDCEXP32_H, + ICLASS_AE_ADDCEXP32_L, + ICLASS_AE_CALCRNG16, + ICLASS_AE_CALCRNG32, + ICLASS_AE_RNG32X4, + ICLASS_AE_LAV8X8X2_XP, + ICLASS_AE_LAV16X4X2_XP, + ICLASS_AE_SAV8X8X2_XP, + ICLASS_AE_SAV16X4X2_XP, + ICLASS_AE_MOVZBVCDR, + ICLASS_AE_MOVDRZBVC, + ICLASS_AE_LAVUNSQZ8X8_XP, + ICLASS_AE_LAVUNSQZ16X4_XP, + ICLASS_AE_MUL8Q8X8, + ICLASS_AE_MULA8Q8X8, + ICLASS_AE_MUL8Q4X16, + ICLASS_AE_MULA8Q4X16, + ICLASS_AE_MUL8Q8X16, + ICLASS_AE_MULA8Q8X16, + ICLASS_AE_MUL8QW8X16, + ICLASS_AE_MULA8QW8X16, + ICLASS_AE_MUL4O8X8, + ICLASS_AE_MULA4O8X8, + ICLASS_AE_MUL4O4X16, + ICLASS_AE_MULA4O4X16, + ICLASS_AE_MUL4O8X16, + ICLASS_AE_MULA4O8X16, + ICLASS_AE_MUL4QW8X16, + ICLASS_AE_MULA4QW8X16, + ICLASS_AE_MUL8Q8X8CNV_L, + ICLASS_AE_MUL8Q8X8CNV_H, + ICLASS_AE_MULA8Q8X8CNV_L, + ICLASS_AE_MULA8Q8X8CNV_H, + ICLASS_AE_MUL8Q8X16CNV, + ICLASS_AE_MULA8Q8X16CNV, + ICLASS_AE_MUL2X4Q8X8CNV_H, + ICLASS_AE_MULA2X4Q8X8CNV_H, + ICLASS_AE_MUL2X4Q8X8CNV_L, + ICLASS_AE_MULA2X4Q8X8CNV_L, + ICLASS_AE_MUL2X4Q8X16CNV, + ICLASS_AE_MULA2X4Q8X16CNV, + ICLASS_AE_MULQQ8X16CNV, + ICLASS_AE_MULAQQ8X16CNV, + ICLASS_AE_MUL4O8X8CNV_H, + ICLASS_AE_MULA4O8X8CNV_H, + ICLASS_AE_MUL4O8X8CNV_L, + ICLASS_AE_MULA4O8X8CNV_L, + ICLASS_AE_MUL4O8X16CNV_H, + ICLASS_AE_MULA4O8X16CNV_H, + ICLASS_AE_MUL4O8X16CNV_L, + ICLASS_AE_MULA4O8X16CNV_L, + ICLASS_AE_MUL8Q4X16CNV_H, + ICLASS_AE_MULA8Q4X16CNV_H, + ICLASS_AE_MUL8Q4X16CNV_L, + ICLASS_AE_MULA8Q4X16CNV_L, + ICLASS_AE_MUL2X4Q4X16CNV_H, + ICLASS_AE_MULA2X4Q4X16CNV_H, + ICLASS_AE_MUL2X4Q4X16CNV_L, + ICLASS_AE_MULA2X4Q4X16CNV_L, + ICLASS_AE_MULQQ4X16CNV_H, + ICLASS_AE_MULAQQ4X16CNV_H, + ICLASS_AE_MULQQ4X16CNV_L, + ICLASS_AE_MULAQQ4X16CNV_L, + ICLASS_AE_MUL4O4X16CNV_HH, + ICLASS_AE_MUL4O4X16CNV_HL, + ICLASS_AE_MUL4O4X16CNV_LH, + ICLASS_AE_MUL4O4X16CNV_LL, + ICLASS_AE_MULA4O4X16CNV_HH, + ICLASS_AE_MULA4O4X16CNV_HL, + ICLASS_AE_MULA4O4X16CNV_LH, + ICLASS_AE_MULA4O4X16CNV_LL, + ICLASS_AE_MULUU8Q8X8, + ICLASS_AE_MULAUU8Q8X8, + ICLASS_AE_MULUU4O8X8, + ICLASS_AE_MULAUU4O8X8, + ICLASS_AE_MULUU8Q8X8CNV_L, + ICLASS_AE_MULAUU8Q8X8CNV_L, + ICLASS_AE_MULUU8Q8X8CNV_H, + ICLASS_AE_MULAUU8Q8X8CNV_H, + ICLASS_AE_MULUU2X4Q8X8CNV_H, + ICLASS_AE_MULAUU2X4Q8X8CNV_H, + ICLASS_AE_MULUU2X4Q8X8CNV_L, + ICLASS_AE_MULAUU2X4Q8X8CNV_L, + ICLASS_AE_MULUU4O8X8CNV_H, + ICLASS_AE_MULAUU4O8X8CNV_H, + ICLASS_AE_MULUU4O8X8CNV_L, + ICLASS_AE_MULAUU4O8X8CNV_L, + ICLASS_AE_MULUS8Q8X8, + ICLASS_AE_MULAUS8Q8X8, + ICLASS_AE_MULUS8Q4X16, + ICLASS_AE_MULAUS8Q4X16, + ICLASS_AE_MULUS8Q8X16, + ICLASS_AE_MULAUS8Q8X16, + ICLASS_AE_MULUS8QW8X16, + ICLASS_AE_MULAUS8QW8X16, + ICLASS_AE_MULUS4O8X8, + ICLASS_AE_MULAUS4O8X8, + ICLASS_AE_MULUS4O4X16, + ICLASS_AE_MULAUS4O4X16, + ICLASS_AE_MULUS4O8X16, + ICLASS_AE_MULAUS4O8X16, + ICLASS_AE_MULUS4QW8X16, + ICLASS_AE_MULAUS4QW8X16, + ICLASS_AE_MULUS8Q8X8CNV_L, + ICLASS_AE_MULAUS8Q8X8CNV_L, + ICLASS_AE_MULUS8Q8X8CNV_H, + ICLASS_AE_MULAUS8Q8X8CNV_H, + ICLASS_AE_MULUS8Q8X16CNV, + ICLASS_AE_MULAUS8Q8X16CNV, + ICLASS_AE_MULUS2X4Q8X8CNV_H, + ICLASS_AE_MULAUS2X4Q8X8CNV_H, + ICLASS_AE_MULUS2X4Q8X8CNV_L, + ICLASS_AE_MULAUS2X4Q8X8CNV_L, + ICLASS_AE_MULUS2X4Q8X16CNV, + ICLASS_AE_MULAUS2X4Q8X16CNV, + ICLASS_AE_MULUSQQ8X16CNV, + ICLASS_AE_MULAUSQQ8X16CNV, + ICLASS_AE_MULUS4O8X8CNV_H, + ICLASS_AE_MULAUS4O8X8CNV_H, + ICLASS_AE_MULUS4O8X8CNV_L, + ICLASS_AE_MULAUS4O8X8CNV_L, + ICLASS_AE_MULUS4O8X16CNV_H, + ICLASS_AE_MULAUS4O8X16CNV_H, + ICLASS_AE_MULUS4O8X16CNV_L, + ICLASS_AE_MULAUS4O8X16CNV_L, + ICLASS_AE_MULUS8Q4X16CNV_H, + ICLASS_AE_MULAUS8Q4X16CNV_H, + ICLASS_AE_MULUS8Q4X16CNV_L, + ICLASS_AE_MULAUS8Q4X16CNV_L, + ICLASS_AE_MULUS2X4Q4X16CNV_H, + ICLASS_AE_MULAUS2X4Q4X16CNV_H, + ICLASS_AE_MULUS2X4Q4X16CNV_L, + ICLASS_AE_MULAUS2X4Q4X16CNV_L, + ICLASS_AE_MULUSQQ4X16CNV_H, + ICLASS_AE_MULAUSQQ4X16CNV_H, + ICLASS_AE_MULUSQQ4X16CNV_L, + ICLASS_AE_MULAUSQQ4X16CNV_L, + ICLASS_AE_MULUS4O4X16CNV_HH, + ICLASS_AE_MULUS4O4X16CNV_HL, + ICLASS_AE_MULUS4O4X16CNV_LH, + ICLASS_AE_MULUS4O4X16CNV_LL, + ICLASS_AE_MULAUS4O4X16CNV_HH, + ICLASS_AE_MULAUS4O4X16CNV_HL, + ICLASS_AE_MULAUS4O4X16CNV_LH, + ICLASS_AE_MULAUS4O4X16CNV_LL, + ICLASS_AE_MULSU8Q8X8, + ICLASS_AE_MULASU8Q8X8, + ICLASS_AE_MULSU4O8X8, + ICLASS_AE_MULASU4O8X8, + ICLASS_AE_MULSU8Q8X8CNV_L, + ICLASS_AE_MULASU8Q8X8CNV_L, + ICLASS_AE_MULSU8Q8X8CNV_H, + ICLASS_AE_MULASU8Q8X8CNV_H, + ICLASS_AE_MULSU2X4Q8X8CNV_H, + ICLASS_AE_MULASU2X4Q8X8CNV_H, + ICLASS_AE_MULSU2X4Q8X8CNV_L, + ICLASS_AE_MULASU2X4Q8X8CNV_L, + ICLASS_AE_MULSU4O8X8CNV_H, + ICLASS_AE_MULASU4O8X8CNV_H, + ICLASS_AE_MULSU4O8X8CNV_L, + ICLASS_AE_MULASU4O8X8CNV_L, + ICLASS_AE_MULUUZB8Q8X8, + ICLASS_AE_MULAUUZB8Q8X8, + ICLASS_AE_MULUUZB4O8X8, + ICLASS_AE_MULAUUZB4O8X8, + ICLASS_AE_MULUUZB8Q8X8CNV_L, + ICLASS_AE_MULAUUZB8Q8X8CNV_L, + ICLASS_AE_MULUUZB8Q8X8CNV_H, + ICLASS_AE_MULAUUZB8Q8X8CNV_H, + ICLASS_AE_MULUUZB2X4Q8X8CNV_H, + ICLASS_AE_MULAUUZB2X4Q8X8CNV_H, + ICLASS_AE_MULUUZB2X4Q8X8CNV_L, + ICLASS_AE_MULAUUZB2X4Q8X8CNV_L, + ICLASS_AE_MULUUZB4O8X8CNV_H, + ICLASS_AE_MULAUUZB4O8X8CNV_H, + ICLASS_AE_MULUUZB4O8X8CNV_L, + ICLASS_AE_MULAUUZB4O8X8CNV_L, + ICLASS_AE_MULUUZB3X3O8X8, + ICLASS_AE_MULAUUZB3X3O8X8, + ICLASS_AE_MULZB8Q8X8, + ICLASS_AE_MULAZB8Q8X8, + ICLASS_AE_MULZB4O8X8, + ICLASS_AE_MULAZB4O8X8, + ICLASS_AE_MULZB8Q8X8CNV_L, + ICLASS_AE_MULAZB8Q8X8CNV_L, + ICLASS_AE_MULZB8Q8X8CNV_H, + ICLASS_AE_MULAZB8Q8X8CNV_H, + ICLASS_AE_MULZB2X4Q8X8CNV_H, + ICLASS_AE_MULAZB2X4Q8X8CNV_H, + ICLASS_AE_MULZB2X4Q8X8CNV_L, + ICLASS_AE_MULAZB2X4Q8X8CNV_L, + ICLASS_AE_MULZB4O8X8CNV_H, + ICLASS_AE_MULAZB4O8X8CNV_H, + ICLASS_AE_MULZB4O8X8CNV_L, + ICLASS_AE_MULAZB4O8X8CNV_L, + ICLASS_AE_MULZB3X3O8X8, + ICLASS_AE_MULAZB3X3O8X8, + ICLASS_CVTSF16_L, + ICLASS_CVTSF16_H, + ICLASS_CVTF16S_L, + ICLASS_CVTF16S_H, + ICLASS_AE_MOVFCRFSRV, + ICLASS_AE_MOVVFCRFSR, + ICLASS_MOVT_S, + ICLASS_MOVF_S, + ICLASS_MOVEQZ_S, + ICLASS_MOVNEZ_S, + ICLASS_MOVGEZ_S, + ICLASS_MOVLTZ_S, + ICLASS_RFR, + ICLASS_WFR, + ICLASS_MUL_S, + ICLASS_MADD_S, + ICLASS_MSUB_S, + ICLASS_MSUBN_S, + ICLASS_MADDN_S, + ICLASS_ADD_S, + ICLASS_SUB_S, + ICLASS_OLE_S, + ICLASS_OLT_S, + ICLASS_OEQ_S, + ICLASS_UN_S, + ICLASS_ULE_S, + ICLASS_ULT_S, + ICLASS_UEQ_S, + ICLASS_NEXP01_S, + ICLASS_MKSADJ_S, + ICLASS_MKDADJ_S, + ICLASS_DIV0_S, + ICLASS_SQRT0_S, + ICLASS_RECIP0_S, + ICLASS_RSQRT0_S, + ICLASS_DIVN_S, + ICLASS_ADDEXP_S, + ICLASS_ADDEXPM_S, + ICLASS_MIN_S, + ICLASS_MAX_S, + ICLASS_MULMUX_S, + ICLASS_MADDMUX_S, + ICLASS_TRUNC_S, + ICLASS_UTRUNC_S, + ICLASS_TRUNC_SX2, + ICLASS_UTRUNC_SX2, + ICLASS_FICEIL_S, + ICLASS_FIFLOOR_S, + ICLASS_FIRINT_S, + ICLASS_FIROUND_S, + ICLASS_FITRUNC_S, + ICLASS_FLOAT_S, + ICLASS_UFLOAT_S, + ICLASS_FLOAT_SX2, + ICLASS_UFLOAT_SX2, + ICLASS_ABS_S, + ICLASS_NEG_S, + ICLASS_CONJC_S, + ICLASS_MULJC_S, + ICLASS_CONST_S, + ICLASS_CLSFY_S, + ICLASS_MINNUM_S, + ICLASS_MAXNUM_S, + ICLASS_ADDANDSUB_S, + ICLASS_ADDANDSUBJC_S, + ICLASS_ADD_HL_LH_S, + ICLASS_MADDA_S, + ICLASS_FREXP_S, + ICLASS_FLOATEXP_S, + ICLASS_MINNUMABS_S, + ICLASS_MAXNUMABS_S, + ICLASS_MULQ_S, + ICLASS_MADDQ_S, + ICLASS_MSUBQ_S, + ICLASS_MULMUXQ_S, + ICLASS_MADDMUXQ_S, + ICLASS_BMAXNUM_S, + ICLASS_BMINNUM_S, + ICLASS_BMAXNUMABS_S, + ICLASS_BMINNUMABS_S, + ICLASS_ABS_SX2X2, + ICLASS_NEG_SX2X2, + ICLASS_CONJC_SX2X2, + ICLASS_MULJC_SX2X2, + ICLASS_CONST_SX2X2, + ICLASS_ADD_SX2X2, + ICLASS_SUB_SX2X2, + ICLASS_MUL_SX2X2, + ICLASS_MADD_SX2X2, + ICLASS_MSUB_SX2X2, + ICLASS_MULMUX_SX2X2, + ICLASS_MADDMUX_SX2X2, + ICLASS_ABS_H, + ICLASS_ADDEXP_H, + ICLASS_ADDEXPM_H, + ICLASS_CLSFY_H, + ICLASS_CONJC_H, + ICLASS_CONST_H, + ICLASS_MIN_H, + ICLASS_MAX_H, + ICLASS_MINNUM_H, + ICLASS_MAXNUM_H, + ICLASS_MULJC_H, + ICLASS_NEG_H, + ICLASS_OEQ_H, + ICLASS_OLE_H, + ICLASS_OLT_H, + ICLASS_UEQ_H, + ICLASS_ULE_H, + ICLASS_ULT_H, + ICLASS_UN_H, + ICLASS_DIV0_H, + ICLASS_FICEIL_H, + ICLASS_FIFLOOR_H, + ICLASS_FIRINT_H, + ICLASS_FIROUND_H, + ICLASS_FITRUNC_H, + ICLASS_MKDADJ_H, + ICLASS_MKSADJ_H, + ICLASS_NEXP0_H, + ICLASS_NEXP01_H, + ICLASS_RECIP0_H, + ICLASS_RSQRT0_H, + ICLASS_SQRT0_H, + ICLASS_FLOAT16_H, + ICLASS_UFLOAT16_H, + ICLASS_TRUNC16_H, + ICLASS_UTRUNC16_H, + ICLASS_FLOAT16_HX4, + ICLASS_UFLOAT16_HX4, + ICLASS_TRUNC16_HX4, + ICLASS_UTRUNC16_HX4, + ICLASS_ADD_H, + ICLASS_SUB_H, + ICLASS_MUL_H, + ICLASS_MADD_H, + ICLASS_MSUB_H, + ICLASS_MADDN_H, + ICLASS_MSUBN_H, + ICLASS_DIVN_H, + ICLASS_RMINNUM_H, + ICLASS_RMAXNUM_H, + ICLASS_ABS_HX4X2, + ICLASS_NEG_HX4X2, + ICLASS_CONJC_HX4X2, + ICLASS_CONST_HX4X2, + ICLASS_MULJC_HX4X2, + ICLASS_ADD_HX4X2, + ICLASS_SUB_HX4X2, + ICLASS_MUL_HX4X2, + ICLASS_MADD_HX4X2, + ICLASS_MSUB_HX4X2, + ICLASS_MULQ_H, + ICLASS_MADDQ_H, + ICLASS_MULCNVH_HX4X2, + ICLASS_MULACNVH_HX4X2, + ICLASS_MULCNVL_HX4X2, + ICLASS_MULACNVL_HX4X2 +}; + + +/* Opcode encodings. */ + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408000; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf01d; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3400; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3500; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34800; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134800; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614800; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34900; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134900; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614900; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf06d; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03d; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00d; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e70; +} + +static void +Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e700; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_addi_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e0000; +} + +static void +Opcode_addi_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_addi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6e0000; + slotbuf[1] = 0; +} + +static void +Opcode_addi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01000; + slotbuf[1] = 0; +} + +static void +Opcode_addi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103e0000; + slotbuf[1] = 0; +} + +static void +Opcode_addi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_addi_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000; +} + +static void +Opcode_addi_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_addi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10360000; +} + +static void +Opcode_addi_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2642000; +} + +static void +Opcode_addi_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308000; +} + +static void +Opcode_addi_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2360000; +} + +static void +Opcode_addi_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340000; +} + +static void +Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb900000; +} + +static void +Opcode_addi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340000; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002; +} + +static void +Opcode_addmi_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f0000; +} + +static void +Opcode_addmi_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1250000; +} + +static void +Opcode_addmi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6f0000; + slotbuf[1] = 0; +} + +static void +Opcode_addmi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01200; + slotbuf[1] = 0; +} + +static void +Opcode_addmi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103e2000; + slotbuf[1] = 0; +} + +static void +Opcode_addmi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_addmi_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000; +} + +static void +Opcode_addmi_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_addmi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10370000; +} + +static void +Opcode_addmi_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2643000; +} + +static void +Opcode_addmi_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130c000; +} + +static void +Opcode_addmi_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2370000; +} + +static void +Opcode_addmi_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1350000; +} + +static void +Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb901000; +} + +static void +Opcode_addmi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1350000; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_add_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc48000; +} + +static void +Opcode_add_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144c000; +} + +static void +Opcode_add_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ba000; + slotbuf[1] = 0; +} + +static void +Opcode_add_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e12000; + slotbuf[1] = 0; +} + +static void +Opcode_add_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10724000; + slotbuf[1] = 0; +} + +static void +Opcode_add_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4000; +} + +static void +Opcode_add_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c4000; +} + +static void +Opcode_add_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c000; +} + +static void +Opcode_add_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10614000; +} + +static void +Opcode_add_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a09000; +} + +static void +Opcode_add_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1588000; +} + +static void +Opcode_add_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2750000; +} + +static void +Opcode_add_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154e000; +} + +static void +Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a79004; +} + +static void +Opcode_add_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154c000; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addx2_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc49000; +} + +static void +Opcode_addx2_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144d000; +} + +static void +Opcode_addx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74bb000; + slotbuf[1] = 0; +} + +static void +Opcode_addx2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1a000; + slotbuf[1] = 0; +} + +static void +Opcode_addx2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10725000; + slotbuf[1] = 0; +} + +static void +Opcode_addx2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a5000; +} + +static void +Opcode_addx2_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c5000; +} + +static void +Opcode_addx2_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29d000; +} + +static void +Opcode_addx2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10615000; +} + +static void +Opcode_addx2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0d000; +} + +static void +Opcode_addx2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c8000; +} + +static void +Opcode_addx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2751000; +} + +static void +Opcode_addx2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f000; +} + +static void +Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b79004; +} + +static void +Opcode_addx2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154d000; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_addx4_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc88000; +} + +static void +Opcode_addx4_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148c000; +} + +static void +Opcode_addx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74bc000; + slotbuf[1] = 0; +} + +static void +Opcode_addx4_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e42000; + slotbuf[1] = 0; +} + +static void +Opcode_addx4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10726000; + slotbuf[1] = 0; +} + +static void +Opcode_addx4_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6000; +} + +static void +Opcode_addx4_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c6000; +} + +static void +Opcode_addx4_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29e000; +} + +static void +Opcode_addx4_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10616000; +} + +static void +Opcode_addx4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a11000; +} + +static void +Opcode_addx4_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1589000; +} + +static void +Opcode_addx4_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2752000; +} + +static void +Opcode_addx4_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158e000; +} + +static void +Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9928000; +} + +static void +Opcode_addx4_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158c000; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_addx8_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc89000; +} + +static void +Opcode_addx8_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148d000; +} + +static void +Opcode_addx8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74bd000; + slotbuf[1] = 0; +} + +static void +Opcode_addx8_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e4a000; + slotbuf[1] = 0; +} + +static void +Opcode_addx8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10727000; + slotbuf[1] = 0; +} + +static void +Opcode_addx8_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a7000; +} + +static void +Opcode_addx8_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c7000; +} + +static void +Opcode_addx8_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29f000; +} + +static void +Opcode_addx8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10617000; +} + +static void +Opcode_addx8_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a15000; +} + +static void +Opcode_addx8_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c9000; +} + +static void +Opcode_addx8_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2753000; +} + +static void +Opcode_addx8_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158f000; +} + +static void +Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9968000; +} + +static void +Opcode_addx8_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158d000; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_sub_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4d000; +} + +static void +Opcode_sub_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1451000; +} + +static void +Opcode_sub_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74eb000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eba000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072a000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6000; +} + +static void +Opcode_sub_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d5000; +} + +static void +Opcode_sub_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ad000; +} + +static void +Opcode_sub_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064b000; +} + +static void +Opcode_sub_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a4d000; +} + +static void +Opcode_sub_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154d000; +} + +static void +Opcode_sub_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2761000; +} + +static void +Opcode_sub_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1553000; +} + +static void +Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a7900c; +} + +static void +Opcode_sub_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1551000; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_subx2_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8c000; +} + +static void +Opcode_subx2_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1490000; +} + +static void +Opcode_subx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ec000; + slotbuf[1] = 0; +} + +static void +Opcode_subx2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec2000; + slotbuf[1] = 0; +} + +static void +Opcode_subx2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072b000; + slotbuf[1] = 0; +} + +static void +Opcode_subx2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7000; +} + +static void +Opcode_subx2_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d6000; +} + +static void +Opcode_subx2_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ae000; +} + +static void +Opcode_subx2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064d000; +} + +static void +Opcode_subx2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a51000; +} + +static void +Opcode_subx2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158d000; +} + +static void +Opcode_subx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2762000; +} + +static void +Opcode_subx2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1592000; +} + +static void +Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b7100c; +} + +static void +Opcode_subx2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1590000; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_subx4_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8d000; +} + +static void +Opcode_subx4_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1491000; +} + +static void +Opcode_subx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ed000; + slotbuf[1] = 0; +} + +static void +Opcode_subx4_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eca000; + slotbuf[1] = 0; +} + +static void +Opcode_subx4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072c000; + slotbuf[1] = 0; +} + +static void +Opcode_subx4_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8000; +} + +static void +Opcode_subx4_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d7000; +} + +static void +Opcode_subx4_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2af000; +} + +static void +Opcode_subx4_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064f000; +} + +static void +Opcode_subx4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a55000; +} + +static void +Opcode_subx4_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cd000; +} + +static void +Opcode_subx4_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2763000; +} + +static void +Opcode_subx4_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1593000; +} + +static void +Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b7900c; +} + +static void +Opcode_subx4_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1591000; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_subx8_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xccc000; +} + +static void +Opcode_subx8_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d0000; +} + +static void +Opcode_subx8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ee000; + slotbuf[1] = 0; +} + +static void +Opcode_subx8_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ed2000; + slotbuf[1] = 0; +} + +static void +Opcode_subx8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072d000; + slotbuf[1] = 0; +} + +static void +Opcode_subx8_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b9000; +} + +static void +Opcode_subx8_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d8000; +} + +static void +Opcode_subx8_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0000; +} + +static void +Opcode_subx8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10651000; +} + +static void +Opcode_subx8_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a59000; +} + +static void +Opcode_subx8_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150e000; +} + +static void +Opcode_subx8_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2764000; +} + +static void +Opcode_subx8_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d2000; +} + +static void +Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9920008; +} + +static void +Opcode_subx8_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d0000; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_and_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc8000; +} + +static void +Opcode_and_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14cc000; +} + +static void +Opcode_and_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74be000; + slotbuf[1] = 0; +} + +static void +Opcode_and_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e52000; + slotbuf[1] = 0; +} + +static void +Opcode_and_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054b000; + slotbuf[1] = 0; +} + +static void +Opcode_and_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9000; +} + +static void +Opcode_and_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c8000; +} + +static void +Opcode_and_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0000; +} + +static void +Opcode_and_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10638000; +} + +static void +Opcode_and_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a19000; +} + +static void +Opcode_and_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150a000; +} + +static void +Opcode_and_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2754000; +} + +static void +Opcode_and_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ce000; +} + +static void +Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9920004; +} + +static void +Opcode_and_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cc000; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_or_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xccb000; +} + +static void +Opcode_or_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14cf000; +} + +static void +Opcode_or_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e7000; + slotbuf[1] = 0; +} + +static void +Opcode_or_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e9a000; + slotbuf[1] = 0; +} + +static void +Opcode_or_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1075d000; + slotbuf[1] = 0; +} + +static void +Opcode_or_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2000; +} + +static void +Opcode_or_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d1000; +} + +static void +Opcode_or_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a9000; +} + +static void +Opcode_or_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10643000; +} + +static void +Opcode_or_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_or_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a3d000; +} + +static void +Opcode_or_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154c000; +} + +static void +Opcode_or_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275d000; +} + +static void +Opcode_or_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d1000; +} + +static void +Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a79008; +} + +static void +Opcode_or_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cf000; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_xor_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xccd000; +} + +static void +Opcode_xor_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d1000; +} + +static void +Opcode_xor_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ef000; + slotbuf[1] = 0; +} + +static void +Opcode_xor_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eda000; + slotbuf[1] = 0; +} + +static void +Opcode_xor_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072e000; + slotbuf[1] = 0; +} + +static void +Opcode_xor_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba000; +} + +static void +Opcode_xor_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d9000; +} + +static void +Opcode_xor_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b1000; +} + +static void +Opcode_xor_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10653000; +} + +static void +Opcode_xor_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa01000; +} + +static void +Opcode_xor_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a5d000; +} + +static void +Opcode_xor_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154e000; +} + +static void +Opcode_xor_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2765000; +} + +static void +Opcode_xor_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d3000; +} + +static void +Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9960008; +} + +static void +Opcode_xor_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d1000; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6007; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe007; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4007; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5007; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd007; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1007; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa007; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb007; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2007; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3007; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc007; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9007; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_call0_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940000; +} + +static void +Opcode_call0_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d620000; + slotbuf[1] = 0; +} + +static void +Opcode_call0_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340000; + slotbuf[1] = 0; +} + +static void +Opcode_call0_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_call0_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0000; +} + +static void +Opcode_call0_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c0000; +} + +static void +Opcode_call0_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22c0000; +} + +static void +Opcode_call0_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7300000; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_callx0_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21003; +} + +static void +Opcode_callx0_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520205; + slotbuf[1] = 0; +} + +static void +Opcode_callx0_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10587bc0; + slotbuf[1] = 0; +} + +static void +Opcode_callx0_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6402; +} + +static void +Opcode_callx0_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d230; +} + +static void +Opcode_callx0_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d001; +} + +static void +Opcode_callx0_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781003; +} + +static void +Opcode_callx0_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e10e0; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_extui_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0000; +} + +static void +Opcode_extui_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_extui_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6a0000; + slotbuf[1] = 0; +} + +static void +Opcode_extui_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00000; + slotbuf[1] = 0; +} + +static void +Opcode_extui_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103c0000; + slotbuf[1] = 0; +} + +static void +Opcode_extui_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_extui_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_extui_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_extui_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340000; +} + +static void +Opcode_extui_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2640000; +} + +static void +Opcode_extui_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_extui_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2340000; +} + +static void +Opcode_extui_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_extui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa900000; +} + +static void +Opcode_extui_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_j_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_j_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d600000; + slotbuf[1] = 0; +} + +static void +Opcode_j_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300000; + slotbuf[1] = 0; +} + +static void +Opcode_j_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_j_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280000; +} + +static void +Opcode_j_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2580000; +} + +static void +Opcode_j_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2280000; +} + +static void +Opcode_j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7200000; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; +} + +static void +Opcode_jx_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21203; +} + +static void +Opcode_jx_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520a05; + slotbuf[1] = 0; +} + +static void +Opcode_jx_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef00; + slotbuf[1] = 0; +} + +static void +Opcode_jx_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6404; +} + +static void +Opcode_jx_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d430; +} + +static void +Opcode_jx_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d201; +} + +static void +Opcode_jx_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781203; +} + +static void +Opcode_jx_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e12e0; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1002; +} + +static void +Opcode_l16ui_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa40000; +} + +static void +Opcode_l16ui_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_l16ui_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7c0000; + slotbuf[1] = 0; +} + +static void +Opcode_l16ui_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c02200; + slotbuf[1] = 0; +} + +static void +Opcode_l16ui_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10402000; + slotbuf[1] = 0; +} + +static void +Opcode_l16ui_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_l16ui_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x350000; +} + +static void +Opcode_l16ui_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250000; +} + +static void +Opcode_l16ui_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103c0000; +} + +static void +Opcode_l16ui_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c0000; +} + +static void +Opcode_l16ui_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1314000; +} + +static void +Opcode_l16ui_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2390000; +} + +static void +Opcode_l16ui_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c0000; +} + +static void +Opcode_l16ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb01000; +} + +static void +Opcode_l16ui_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c0000; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9002; +} + +static void +Opcode_l16si_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_l16si_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_l16si_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d780000; + slotbuf[1] = 0; +} + +static void +Opcode_l16si_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c02000; + slotbuf[1] = 0; +} + +static void +Opcode_l16si_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10400000; + slotbuf[1] = 0; +} + +static void +Opcode_l16si_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_l16si_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_l16si_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_l16si_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103b0000; +} + +static void +Opcode_l16si_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2680000; +} + +static void +Opcode_l16si_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1310000; +} + +static void +Opcode_l16si_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2380000; +} + +static void +Opcode_l16si_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380000; +} + +static void +Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb00000; +} + +static void +Opcode_l16si_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380000; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2002; +} + +static void +Opcode_l32i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa80000; +} + +static void +Opcode_l32i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1290000; +} + +static void +Opcode_l32i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d790000; + slotbuf[1] = 0; +} + +static void +Opcode_l32i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c03000; + slotbuf[1] = 0; +} + +static void +Opcode_l32i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10420000; + slotbuf[1] = 0; +} + +static void +Opcode_l32i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_l32i_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360000; +} + +static void +Opcode_l32i_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260000; +} + +static void +Opcode_l32i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103d0000; +} + +static void +Opcode_l32i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2681000; +} + +static void +Opcode_l32i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318000; +} + +static void +Opcode_l32i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23a0000; +} + +static void +Opcode_l32i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1390000; +} + +static void +Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7320000; +} + +static void +Opcode_l32i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1390000; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_l32r_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_l32r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7200000; + slotbuf[1] = 0; +} + +static void +Opcode_l32r_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0; +} + +static void +Opcode_l32r_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_l32r_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; +} + +static void +Opcode_l32r_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_l32r_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_l32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000000; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_l8ui_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac0000; +} + +static void +Opcode_l8ui_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12d0000; +} + +static void +Opcode_l8ui_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7d0000; + slotbuf[1] = 0; +} + +static void +Opcode_l8ui_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c03200; + slotbuf[1] = 0; +} + +static void +Opcode_l8ui_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10422000; + slotbuf[1] = 0; +} + +static void +Opcode_l8ui_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_l8ui_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370000; +} + +static void +Opcode_l8ui_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270000; +} + +static void +Opcode_l8ui_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103e0000; +} + +static void +Opcode_l8ui_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c1000; +} + +static void +Opcode_l8ui_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131c000; +} + +static void +Opcode_l8ui_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23b0000; +} + +static void +Opcode_l8ui_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d0000; +} + +static void +Opcode_l8ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7321000; +} + +static void +Opcode_l8ui_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d0000; +} + +static void +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8076; +} + +static void +Opcode_loop_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_loop_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520000; + slotbuf[1] = 0; +} + +static void +Opcode_loop_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10582000; + slotbuf[1] = 0; +} + +static void +Opcode_loop_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0000; +} + +static void +Opcode_loop_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690000; +} + +static void +Opcode_loop_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac1000; +} + +static void +Opcode_loop_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2780000; +} + +static void +Opcode_loop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b20000; +} + +static void +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa076; +} + +static void +Opcode_loopgtz_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20001; +} + +static void +Opcode_loopgtz_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520001; + slotbuf[1] = 0; +} + +static void +Opcode_loopgtz_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10582040; + slotbuf[1] = 0; +} + +static void +Opcode_loopgtz_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0001; +} + +static void +Opcode_loopgtz_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690010; +} + +static void +Opcode_loopgtz_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac1001; +} + +static void +Opcode_loopgtz_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2780001; +} + +static void +Opcode_loopgtz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b20040; +} + +static void +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9076; +} + +static void +Opcode_loopnez_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20002; +} + +static void +Opcode_loopnez_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520002; + slotbuf[1] = 0; +} + +static void +Opcode_loopnez_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10582080; + slotbuf[1] = 0; +} + +static void +Opcode_loopnez_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0002; +} + +static void +Opcode_loopnez_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690020; +} + +static void +Opcode_loopnez_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac1002; +} + +static void +Opcode_loopnez_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2780002; +} + +static void +Opcode_loopnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b20080; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa002; +} + +static void +Opcode_movi_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad0000; +} + +static void +Opcode_movi_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1220000; +} + +static void +Opcode_movi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7f0000; + slotbuf[1] = 0; +} + +static void +Opcode_movi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04000; + slotbuf[1] = 0; +} + +static void +Opcode_movi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480000; + slotbuf[1] = 0; +} + +static void +Opcode_movi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_movi_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0000; +} + +static void +Opcode_movi_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_movi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10450000; +} + +static void +Opcode_movi_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c3000; +} + +static void +Opcode_movi_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1320000; +} + +static void +Opcode_movi_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23f0000; +} + +static void +Opcode_movi_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1320000; +} + +static void +Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9820000; +} + +static void +Opcode_movi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1320000; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830000; +} + +static void +Opcode_moveqz_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4b000; +} + +static void +Opcode_moveqz_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144f000; +} + +static void +Opcode_moveqz_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e3000; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e7a000; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10755000; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae000; +} + +static void +Opcode_moveqz_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3cd000; +} + +static void +Opcode_moveqz_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a5000; +} + +static void +Opcode_moveqz_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063d000; +} + +static void +Opcode_moveqz_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a2d000; +} + +static void +Opcode_moveqz_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154b000; +} + +static void +Opcode_moveqz_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2759000; +} + +static void +Opcode_moveqz_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1551000; +} + +static void +Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9978008; +} + +static void +Opcode_moveqz_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f000; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30000; +} + +static void +Opcode_movgez_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8a000; +} + +static void +Opcode_movgez_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148e000; +} + +static void +Opcode_movgez_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e4000; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e82000; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10757000; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1af000; +} + +static void +Opcode_movgez_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ce000; +} + +static void +Opcode_movgez_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a6000; +} + +static void +Opcode_movgez_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063e000; +} + +static void +Opcode_movgez_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a31000; +} + +static void +Opcode_movgez_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158b000; +} + +static void +Opcode_movgez_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275a000; +} + +static void +Opcode_movgez_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1590000; +} + +static void +Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x997000c; +} + +static void +Opcode_movgez_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158e000; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_movltz_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8b000; +} + +static void +Opcode_movltz_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148f000; +} + +static void +Opcode_movltz_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e5000; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e8a000; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10759000; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_movltz_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3cf000; +} + +static void +Opcode_movltz_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a7000; +} + +static void +Opcode_movltz_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063f000; +} + +static void +Opcode_movltz_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a35000; +} + +static void +Opcode_movltz_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cb000; +} + +static void +Opcode_movltz_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275b000; +} + +static void +Opcode_movltz_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1591000; +} + +static void +Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x997800c; +} + +static void +Opcode_movltz_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158f000; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_movnez_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcca000; +} + +static void +Opcode_movnez_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14ce000; +} + +static void +Opcode_movnez_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e6000; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e92000; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1075b000; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1000; +} + +static void +Opcode_movnez_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d0000; +} + +static void +Opcode_movnez_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8000; +} + +static void +Opcode_movnez_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10641000; +} + +static void +Opcode_movnez_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a39000; +} + +static void +Opcode_movnez_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150c000; +} + +static void +Opcode_movnez_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275c000; +} + +static void +Opcode_movnez_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d0000; +} + +static void +Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a71008; +} + +static void +Opcode_movnez_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ce000; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600100; +} + +static void +Opcode_abs_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc12020; +} + +static void +Opcode_abs_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1453000; +} + +static void +Opcode_abs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191f6030; + slotbuf[1] = 0; +} + +static void +Opcode_abs_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e14000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a00e; + slotbuf[1] = 0; +} + +static void +Opcode_abs_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8000; +} + +static void +Opcode_abs_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e5000; +} + +static void +Opcode_abs_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6000; +} + +static void +Opcode_abs_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a200b; +} + +static void +Opcode_abs_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a89000; +} + +static void +Opcode_abs_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f000; +} + +static void +Opcode_abs_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c6010; +} + +static void +Opcode_abs_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1555000; +} + +static void +Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a3000; +} + +static void +Opcode_abs_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1521000; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_neg_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc12030; +} + +static void +Opcode_neg_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1453010; +} + +static void +Opcode_neg_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191f7030; + slotbuf[1] = 0; +} + +static void +Opcode_neg_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e14010; + slotbuf[1] = 0; +} + +static void +Opcode_neg_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071b00f; + slotbuf[1] = 0; +} + +static void +Opcode_neg_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8020; +} + +static void +Opcode_neg_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e5020; +} + +static void +Opcode_neg_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6010; +} + +static void +Opcode_neg_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a300b; +} + +static void +Opcode_neg_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a89010; +} + +static void +Opcode_neg_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f010; +} + +static void +Opcode_neg_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c7010; +} + +static void +Opcode_neg_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1555010; +} + +static void +Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a3002; +} + +static void +Opcode_neg_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1521020; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f0; +} + +static void +Opcode_nop_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21903; +} + +static void +Opcode_nop_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1496109; +} + +static void +Opcode_nop_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000065; + slotbuf[1] = 0x6; +} + +static void +Opcode_nop_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82164012; + slotbuf[1] = 0x5; +} + +static void +Opcode_nop_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b48fb5; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c702; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63f8c00; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef74; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9603; +} + +static void +Opcode_nop_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e640b; +} + +static void +Opcode_nop_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7306; +} + +static void +Opcode_nop_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x568001; +} + +static void +Opcode_nop_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40b84a0; +} + +static void +Opcode_nop_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x510040; +} + +static void +Opcode_nop_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069db31; +} + +static void +Opcode_nop_Slot_ae5_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_nop_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700212; +} + +static void +Opcode_nop_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133b800; +} + +static void +Opcode_nop_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08940; +} + +static void +Opcode_nop_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130060; +} + +static void +Opcode_nop_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000021; + slotbuf[1] = 0x2; +} + +static void +Opcode_nop_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x692180; +} + +static void +Opcode_nop_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x692180; +} + +static void +Opcode_nop_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00560; + slotbuf[1] = 0xe; +} + +static void +Opcode_nop_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000801; + slotbuf[1] = 0xe; +} + +static void +Opcode_nop_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d901; +} + +static void +Opcode_nop_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d260f; +} + +static void +Opcode_nop_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200001; + slotbuf[1] = 0x229860; +} + +static void +Opcode_nop_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781903; +} + +static void +Opcode_nop_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159690b; +} + +static void +Opcode_nop_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c10041; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d35801d; +} + +static void +Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab20055; +} + +static void +Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14b610c; +} + +static void +Opcode_nop_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00427; +} + +static void +Opcode_nop_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80426862; + slotbuf[1] = 0xe; +} + +static void +Opcode_l32ex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf14000; +} + +static void +Opcode_s32ex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf15000; +} + +static void +Opcode_getex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40a000; +} + +static void +Opcode_clrex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3120; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_ret_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21303; +} + +static void +Opcode_ret_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520e05; + slotbuf[1] = 0; +} + +static void +Opcode_ret_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef10; + slotbuf[1] = 0; +} + +static void +Opcode_ret_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6405; +} + +static void +Opcode_ret_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d530; +} + +static void +Opcode_ret_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d301; +} + +static void +Opcode_ret_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781303; +} + +static void +Opcode_ret_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e13e0; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5002; +} + +static void +Opcode_s16i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_s16i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7a0000; + slotbuf[1] = 0; +} + +static void +Opcode_s16i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10440000; + slotbuf[1] = 0; +} + +static void +Opcode_s16i_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_s16i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103f0000; +} + +static void +Opcode_s16i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2682000; +} + +static void +Opcode_s16i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23c0000; +} + +static void +Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7330000; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002; +} + +static void +Opcode_s32i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa50000; +} + +static void +Opcode_s32i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7e0000; + slotbuf[1] = 0; +} + +static void +Opcode_s32i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10442000; + slotbuf[1] = 0; +} + +static void +Opcode_s32i_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x390000; +} + +static void +Opcode_s32i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10400000; +} + +static void +Opcode_s32i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c2000; +} + +static void +Opcode_s32i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23d0000; +} + +static void +Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7331000; +} + +static void +Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590000; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_s8i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa90000; +} + +static void +Opcode_s8i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7b0000; + slotbuf[1] = 0; +} + +static void +Opcode_s8i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10460000; + slotbuf[1] = 0; +} + +static void +Opcode_s8i_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0000; +} + +static void +Opcode_s8i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10410000; +} + +static void +Opcode_s8i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2683000; +} + +static void +Opcode_s8i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23e0000; +} + +static void +Opcode_s8i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa980000; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403000; +} + +static void +Opcode_ssa8b_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21503; +} + +static void +Opcode_ssa8b_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145420a; +} + +static void +Opcode_ssa8b_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7521605; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8b_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00c03; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8b_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef30; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8b_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9103; +} + +static void +Opcode_ssa8b_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6407; +} + +static void +Opcode_ssa8b_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7302; +} + +static void +Opcode_ssa8b_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d730; +} + +static void +Opcode_ssa8b_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d501; +} + +static void +Opcode_ssa8b_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d220f; +} + +static void +Opcode_ssa8b_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781503; +} + +static void +Opcode_ssa8b_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556a0b; +} + +static void +Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e15e0; +} + +static void +Opcode_ssa8b_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d7204; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402000; +} + +static void +Opcode_ssa8l_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21603; +} + +static void +Opcode_ssa8l_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145430a; +} + +static void +Opcode_ssa8l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7521a05; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f08c03; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef40; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8l_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9503; +} + +static void +Opcode_ssa8l_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6408; +} + +static void +Opcode_ssa8l_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7303; +} + +static void +Opcode_ssa8l_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d830; +} + +static void +Opcode_ssa8l_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d601; +} + +static void +Opcode_ssa8l_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d230f; +} + +static void +Opcode_ssa8l_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781603; +} + +static void +Opcode_ssa8l_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556b0b; +} + +static void +Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e16e0; +} + +static void +Opcode_ssa8l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d7304; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401000; +} + +static void +Opcode_ssl_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21703; +} + +static void +Opcode_ssl_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416109; +} + +static void +Opcode_ssl_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7521e05; + slotbuf[1] = 0; +} + +static void +Opcode_ssl_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c402; + slotbuf[1] = 0; +} + +static void +Opcode_ssl_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef50; + slotbuf[1] = 0; +} + +static void +Opcode_ssl_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9203; +} + +static void +Opcode_ssl_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6409; +} + +static void +Opcode_ssl_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7304; +} + +static void +Opcode_ssl_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d930; +} + +static void +Opcode_ssl_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d701; +} + +static void +Opcode_ssl_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d240f; +} + +static void +Opcode_ssl_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781703; +} + +static void +Opcode_ssl_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151690b; +} + +static void +Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e17e0; +} + +static void +Opcode_ssl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143610c; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ssr_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21803; +} + +static void +Opcode_ssr_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1456109; +} + +static void +Opcode_ssr_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a4af00; + slotbuf[1] = 0; +} + +static void +Opcode_ssr_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c502; + slotbuf[1] = 0; +} + +static void +Opcode_ssr_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef60; + slotbuf[1] = 0; +} + +static void +Opcode_ssr_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9303; +} + +static void +Opcode_ssr_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e640a; +} + +static void +Opcode_ssr_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7305; +} + +static void +Opcode_ssr_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069da30; +} + +static void +Opcode_ssr_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d801; +} + +static void +Opcode_ssr_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d250f; +} + +static void +Opcode_ssr_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781803; +} + +static void +Opcode_ssr_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x155690b; +} + +static void +Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e18e0; +} + +static void +Opcode_ssr_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x147610c; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404000; +} + +static void +Opcode_ssai_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc92520; +} + +static void +Opcode_ssai_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145400a; +} + +static void +Opcode_ssai_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19034310; + slotbuf[1] = 0; +} + +static void +Opcode_ssai_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00c01; + slotbuf[1] = 0; +} + +static void +Opcode_ssai_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afa0a; + slotbuf[1] = 0; +} + +static void +Opcode_ssai_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9003; +} + +static void +Opcode_ssai_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6400; +} + +static void +Opcode_ssai_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7300; +} + +static void +Opcode_ssai_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687701; +} + +static void +Opcode_ssai_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a88640; +} + +static void +Opcode_ssai_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d200f; +} + +static void +Opcode_ssai_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b520; +} + +static void +Opcode_ssai_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516a0b; +} + +static void +Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa60005; +} + +static void +Opcode_ssai_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d7004; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_sll_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20003; +} + +static void +Opcode_sll_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x141400a; +} + +static void +Opcode_sll_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x752c003; + slotbuf[1] = 0; +} + +static void +Opcode_sll_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0c002; + slotbuf[1] = 0; +} + +static void +Opcode_sll_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105860c0; + slotbuf[1] = 0; +} + +static void +Opcode_sll_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9000; +} + +static void +Opcode_sll_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0003; +} + +static void +Opcode_sll_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b8000; +} + +static void +Opcode_sll_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069c030; +} + +static void +Opcode_sll_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d000; +} + +static void +Opcode_sll_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159200f; +} + +static void +Opcode_sll_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2780003; +} + +static void +Opcode_sll_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151600a; +} + +static void +Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e10e0; +} + +static void +Opcode_sll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1596004; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_src_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4c000; +} + +static void +Opcode_src_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1450000; +} + +static void +Opcode_src_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ea000; + slotbuf[1] = 0; +} + +static void +Opcode_src_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eb2000; + slotbuf[1] = 0; +} + +static void +Opcode_src_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10729000; + slotbuf[1] = 0; +} + +static void +Opcode_src_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b5000; +} + +static void +Opcode_src_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d4000; +} + +static void +Opcode_src_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac000; +} + +static void +Opcode_src_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10649000; +} + +static void +Opcode_src_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a49000; +} + +static void +Opcode_src_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150d000; +} + +static void +Opcode_src_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2760000; +} + +static void +Opcode_src_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1552000; +} + +static void +Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a7100c; +} + +static void +Opcode_src_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1550000; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10000; +} + +static void +Opcode_sra_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc52020; +} + +static void +Opcode_sra_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1453020; +} + +static void +Opcode_sra_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191fc030; + slotbuf[1] = 0; +} + +static void +Opcode_sra_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e14020; + slotbuf[1] = 0; +} + +static void +Opcode_sra_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af000; + slotbuf[1] = 0; +} + +static void +Opcode_sra_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8030; +} + +static void +Opcode_sra_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e5010; +} + +static void +Opcode_sra_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6020; +} + +static void +Opcode_sra_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2007; +} + +static void +Opcode_sra_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a89020; +} + +static void +Opcode_sra_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f020; +} + +static void +Opcode_sra_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b000; +} + +static void +Opcode_sra_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1555020; +} + +static void +Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a3003; +} + +static void +Opcode_sra_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1521030; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_srl_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc52030; +} + +static void +Opcode_srl_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1453030; +} + +static void +Opcode_srl_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191fe030; + slotbuf[1] = 0; +} + +static void +Opcode_srl_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e14030; + slotbuf[1] = 0; +} + +static void +Opcode_srl_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af001; + slotbuf[1] = 0; +} + +static void +Opcode_srl_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8040; +} + +static void +Opcode_srl_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e5030; +} + +static void +Opcode_srl_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6030; +} + +static void +Opcode_srl_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a200f; +} + +static void +Opcode_srl_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a89030; +} + +static void +Opcode_srl_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f030; +} + +static void +Opcode_srl_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b010; +} + +static void +Opcode_srl_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1555030; +} + +static void +Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a3000; +} + +static void +Opcode_srl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1521040; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_slli_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc6000; +} + +static void +Opcode_slli_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14ca000; +} + +static void +Opcode_slli_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74b6000; + slotbuf[1] = 0; +} + +static void +Opcode_slli_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e22000; + slotbuf[1] = 0; +} + +static void +Opcode_slli_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10542000; + slotbuf[1] = 0; +} + +static void +Opcode_slli_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_slli_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_slli_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290000; +} + +static void +Opcode_slli_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10610000; +} + +static void +Opcode_slli_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a01000; +} + +static void +Opcode_slli_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1508000; +} + +static void +Opcode_slli_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x274c000; +} + +static void +Opcode_slli_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cc000; +} + +static void +Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9920000; +} + +static void +Opcode_slli_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ca000; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_srai_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc08000; +} + +static void +Opcode_srai_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140c000; +} + +static void +Opcode_srai_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74b8000; + slotbuf[1] = 0; +} + +static void +Opcode_srai_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e02000; + slotbuf[1] = 0; +} + +static void +Opcode_srai_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10546000; + slotbuf[1] = 0; +} + +static void +Opcode_srai_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2000; +} + +static void +Opcode_srai_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c2000; +} + +static void +Opcode_srai_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x292000; +} + +static void +Opcode_srai_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10612000; +} + +static void +Opcode_srai_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000e0; +} + +static void +Opcode_srai_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1548000; +} + +static void +Opcode_srai_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x274e000; +} + +static void +Opcode_srai_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150e000; +} + +static void +Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9970004; +} + +static void +Opcode_srai_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150c000; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_srli_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8e000; +} + +static void +Opcode_srli_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1452000; +} + +static void +Opcode_srli_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f4000; + slotbuf[1] = 0; +} + +static void +Opcode_srli_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ef2000; + slotbuf[1] = 0; +} + +static void +Opcode_srli_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056a000; + slotbuf[1] = 0; +} + +static void +Opcode_srli_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bd000; +} + +static void +Opcode_srli_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3de000; +} + +static void +Opcode_srli_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b4000; +} + +static void +Opcode_srli_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065d000; +} + +static void +Opcode_srli_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a71000; +} + +static void +Opcode_srli_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150f000; +} + +static void +Opcode_srli_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276a000; +} + +static void +Opcode_srli_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1554000; +} + +static void +Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x992800c; +} + +static void +Opcode_srli_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1552000; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d0; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2030; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2020; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2010; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30100; +} + +static void +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610100; +} + +static void +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200; +} + +static void +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610200; +} + +static void +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30300; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610300; +} + +static void +Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36100; +} + +static void +Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136100; +} + +static void +Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616100; +} + +static void +Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b000; +} + +static void +Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e600; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e600; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e600; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b100; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b100; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b100; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d100; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d100; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d100; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b200; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b200; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b200; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d200; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d200; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d200; +} + +static void +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b300; +} + +static void +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b300; +} + +static void +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b300; +} + +static void +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d300; +} + +static void +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d300; +} + +static void +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d300; +} + +static void +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b400; +} + +static void +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b400; +} + +static void +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b400; +} + +static void +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d400; +} + +static void +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d400; +} + +static void +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d400; +} + +static void +Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b500; +} + +static void +Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b500; +} + +static void +Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b500; +} + +static void +Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d500; +} + +static void +Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d500; +} + +static void +Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d500; +} + +static void +Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b600; +} + +static void +Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b600; +} + +static void +Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b600; +} + +static void +Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d600; +} + +static void +Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d600; +} + +static void +Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d600; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c200; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c200; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c200; +} + +static void +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c300; +} + +static void +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c300; +} + +static void +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c300; +} + +static void +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400; +} + +static void +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c400; +} + +static void +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c400; +} + +static void +Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c500; +} + +static void +Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c500; +} + +static void +Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c500; +} + +static void +Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c600; +} + +static void +Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c600; +} + +static void +Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c600; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ee00; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee00; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ee00; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c000; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e800; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e800; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e800; +} + +static void +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f400; +} + +static void +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f400; +} + +static void +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f400; +} + +static void +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f500; +} + +static void +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f500; +} + +static void +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f500; +} + +static void +Opcode_rsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f600; +} + +static void +Opcode_wsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f600; +} + +static void +Opcode_xsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f600; +} + +static void +Opcode_rsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f700; +} + +static void +Opcode_wsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f700; +} + +static void +Opcode_xsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f700; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3eb00; +} + +static void +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e700; +} + +static void +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e700; +} + +static void +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e700; +} + +static void +Opcode_rsr_mpucfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35c00; +} + +static void +Opcode_wsr_mpucfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135c00; +} + +static void +Opcode_salt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720000; +} + +static void +Opcode_salt_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c000; +} + +static void +Opcode_salt_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1410000; +} + +static void +Opcode_salt_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e8000; + slotbuf[1] = 0; +} + +static void +Opcode_salt_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea2000; + slotbuf[1] = 0; +} + +static void +Opcode_salt_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1075f000; + slotbuf[1] = 0; +} + +static void +Opcode_salt_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b3000; +} + +static void +Opcode_salt_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d2000; +} + +static void +Opcode_salt_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2aa000; +} + +static void +Opcode_salt_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10645000; +} + +static void +Opcode_salt_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a41000; +} + +static void +Opcode_salt_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158c000; +} + +static void +Opcode_salt_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275e000; +} + +static void +Opcode_salt_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512000; +} + +static void +Opcode_salt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b71008; +} + +static void +Opcode_salt_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510000; +} + +static void +Opcode_saltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x620000; +} + +static void +Opcode_saltu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0d000; +} + +static void +Opcode_saltu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1411000; +} + +static void +Opcode_saltu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e9000; + slotbuf[1] = 0; +} + +static void +Opcode_saltu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eaa000; + slotbuf[1] = 0; +} + +static void +Opcode_saltu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10728000; + slotbuf[1] = 0; +} + +static void +Opcode_saltu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b4000; +} + +static void +Opcode_saltu_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d3000; +} + +static void +Opcode_saltu_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ab000; +} + +static void +Opcode_saltu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10647000; +} + +static void +Opcode_saltu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a45000; +} + +static void +Opcode_saltu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cc000; +} + +static void +Opcode_saltu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275f000; +} + +static void +Opcode_saltu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1513000; +} + +static void +Opcode_saltu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b79008; +} + +static void +Opcode_saltu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1511000; +} + +static void +Opcode_rsr_opmode_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37700; +} + +static void +Opcode_wsr_opmode_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137700; +} + +static void +Opcode_xsr_opmode_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x617700; +} + +static void +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820000; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3010; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e200; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e200; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e300; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e400; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e400; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf02d; +} + +static void +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139000; +} + +static void +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619000; +} + +static void +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a000; +} + +static void +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a000; +} + +static void +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39100; +} + +static void +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139100; +} + +static void +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619100; +} + +static void +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a100; +} + +static void +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a100; +} + +static void +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a100; +} + +static void +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618000; +} + +static void +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38100; +} + +static void +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138100; +} + +static void +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618100; +} + +static void +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000; +} + +static void +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136000; +} + +static void +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616000; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e900; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e900; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e900; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ec00; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec00; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ec00; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ed00; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ed00; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ed00; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36800; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136800; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616800; +} + +static void +Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e0; +} + +static void +Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f0; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e000; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e010; +} + +static void +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135900; +} + +static void +Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_andb_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8f000; +} + +static void +Opcode_andb_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f5000; + slotbuf[1] = 0; +} + +static void +Opcode_andb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056b000; + slotbuf[1] = 0; +} + +static void +Opcode_andb_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3df000; +} + +static void +Opcode_andb_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10661000; +} + +static void +Opcode_andb_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a75000; +} + +static void +Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996800c; +} + +static void +Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_andbc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcce000; +} + +static void +Opcode_andbc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f6000; + slotbuf[1] = 0; +} + +static void +Opcode_andbc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056e000; + slotbuf[1] = 0; +} + +static void +Opcode_andbc_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0000; +} + +static void +Opcode_andbc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10663000; +} + +static void +Opcode_andbc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a79000; +} + +static void +Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9921000; +} + +static void +Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_orb_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xccf000; +} + +static void +Opcode_orb_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f7000; + slotbuf[1] = 0; +} + +static void +Opcode_orb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056f000; + slotbuf[1] = 0; +} + +static void +Opcode_orb_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e1000; +} + +static void +Opcode_orb_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10665000; +} + +static void +Opcode_orb_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a7d000; +} + +static void +Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9961000; +} + +static void +Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000; +} + +static void +Opcode_orbc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_orbc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f8000; + slotbuf[1] = 0; +} + +static void +Opcode_orbc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10572000; + slotbuf[1] = 0; +} + +static void +Opcode_orbc_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e2000; +} + +static void +Opcode_orbc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10667000; +} + +static void +Opcode_orbc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a81000; +} + +static void +Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929000; +} + +static void +Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420000; +} + +static void +Opcode_xorb_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc11000; +} + +static void +Opcode_xorb_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f9000; + slotbuf[1] = 0; +} + +static void +Opcode_xorb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10573000; + slotbuf[1] = 0; +} + +static void +Opcode_xorb_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e3000; +} + +static void +Opcode_xorb_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10669000; +} + +static void +Opcode_xorb_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a85000; +} + +static void +Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9969000; +} + +static void +Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_all4_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc92020; +} + +static void +Opcode_all4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19034010; + slotbuf[1] = 0; +} + +static void +Opcode_all4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af00a; + slotbuf[1] = 0; +} + +static void +Opcode_all4_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6300; +} + +static void +Opcode_all4_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687602; +} + +static void +Opcode_all4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80640; +} + +static void +Opcode_all4_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b020; +} + +static void +Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a7400; +} + +static void +Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_any4_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc92030; +} + +static void +Opcode_any4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19036010; + slotbuf[1] = 0; +} + +static void +Opcode_any4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af00b; + slotbuf[1] = 0; +} + +static void +Opcode_any4_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6340; +} + +static void +Opcode_any4_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687603; +} + +static void +Opcode_any4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80650; +} + +static void +Opcode_any4_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b030; +} + +static void +Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a7401; +} + +static void +Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000; +} + +static void +Opcode_all8_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc92420; +} + +static void +Opcode_all8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19034210; + slotbuf[1] = 0; +} + +static void +Opcode_all8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af80a; + slotbuf[1] = 0; +} + +static void +Opcode_all8_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6380; +} + +static void +Opcode_all8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687700; +} + +static void +Opcode_all8_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80660; +} + +static void +Opcode_all8_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b420; +} + +static void +Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a7402; +} + +static void +Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_any8_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc92430; +} + +static void +Opcode_any8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19036210; + slotbuf[1] = 0; +} + +static void +Opcode_any8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af80b; + slotbuf[1] = 0; +} + +static void +Opcode_any8_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6390; +} + +static void +Opcode_any8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687704; +} + +static void +Opcode_any8_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80670; +} + +static void +Opcode_any8_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b430; +} + +static void +Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a7403; +} + +static void +Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76; +} + +static void +Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1076; +} + +static void +Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc30000; +} + +static void +Opcode_movf_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0e000; +} + +static void +Opcode_movf_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f0000; + slotbuf[1] = 0; +} + +static void +Opcode_movf_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055f000; + slotbuf[1] = 0; +} + +static void +Opcode_movf_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3da000; +} + +static void +Opcode_movf_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10655000; +} + +static void +Opcode_movf_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a61000; +} + +static void +Opcode_movf_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2766000; +} + +static void +Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9928008; +} + +static void +Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30000; +} + +static void +Opcode_movt_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0f000; +} + +static void +Opcode_movt_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f1000; + slotbuf[1] = 0; +} + +static void +Opcode_movt_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10562000; + slotbuf[1] = 0; +} + +static void +Opcode_movt_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3db000; +} + +static void +Opcode_movt_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10657000; +} + +static void +Opcode_movt_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a65000; +} + +static void +Opcode_movt_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2767000; +} + +static void +Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9968008; +} + +static void +Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30400; +} + +static void +Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130400; +} + +static void +Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610400; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ea00; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea00; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ea00; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f000; +} + +static void +Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f100; +} + +static void +Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f100; +} + +static void +Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f100; +} + +static void +Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f200; +} + +static void +Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f200; +} + +static void +Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f200; +} + +static void +Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e2; +} + +static void +Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70c2; +} + +static void +Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270d2; +} + +static void +Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370d2; +} + +static void +Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70d2; +} + +static void +Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f2; +} + +static void +Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10000; +} + +static void +Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf12000; +} + +static void +Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf11000; +} + +static void +Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13000; +} + +static void +Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7042; +} + +static void +Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7052; +} + +static void +Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf7082; +} + +static void +Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x47082; +} + +static void +Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57082; +} + +static void +Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7062; +} + +static void +Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7072; +} + +static void +Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7002; +} + +static void +Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7022; +} + +static void +Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7012; +} + +static void +Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7032; +} + +static void +Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27082; +} + +static void +Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37082; +} + +static void +Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7082; +} + +static void +Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf19000; +} + +static void +Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf18000; +} + +static void +Opcode_sdcw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1b000; +} + +static void +Opcode_ldcw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1a000; +} + +static void +Opcode_rsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32800; +} + +static void +Opcode_wsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132800; +} + +static void +Opcode_xsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612800; +} + +static void +Opcode_wsr_cacheadrdis_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136200; +} + +static void +Opcode_rsr_cacheadrdis_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36200; +} + +static void +Opcode_xsr_cacheadrdis_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616200; +} + +static void +Opcode_rptlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50b000; +} + +static void +Opcode_pptlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50d000; +} + +static void +Opcode_rptlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50f000; +} + +static void +Opcode_wptlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50e000; +} + +static void +Opcode_rsr_mpuenb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35a00; +} + +static void +Opcode_wsr_mpuenb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135a00; +} + +static void +Opcode_xsr_mpuenb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615a00; +} + +static void +Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e000; +} + +static void +Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e000; +} + +static void +Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000; +} + +static void +Opcode_clamps_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4e000; +} + +static void +Opcode_clamps_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1412000; +} + +static void +Opcode_clamps_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f2000; + slotbuf[1] = 0; +} + +static void +Opcode_clamps_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee2000; + slotbuf[1] = 0; +} + +static void +Opcode_clamps_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10566000; + slotbuf[1] = 0; +} + +static void +Opcode_clamps_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb000; +} + +static void +Opcode_clamps_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3dc000; +} + +static void +Opcode_clamps_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b2000; +} + +static void +Opcode_clamps_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10659000; +} + +static void +Opcode_clamps_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a69000; +} + +static void +Opcode_clamps_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158e000; +} + +static void +Opcode_clamps_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2768000; +} + +static void +Opcode_clamps_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514000; +} + +static void +Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x992000c; +} + +static void +Opcode_clamps_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512000; +} + +static void +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_max_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc9000; +} + +static void +Opcode_max_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14cd000; +} + +static void +Opcode_max_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74bf000; + slotbuf[1] = 0; +} + +static void +Opcode_max_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e5a000; + slotbuf[1] = 0; +} + +static void +Opcode_max_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054e000; + slotbuf[1] = 0; +} + +static void +Opcode_max_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa000; +} + +static void +Opcode_max_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c9000; +} + +static void +Opcode_max_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a1000; +} + +static void +Opcode_max_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10639000; +} + +static void +Opcode_max_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a1d000; +} + +static void +Opcode_max_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154a000; +} + +static void +Opcode_max_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2755000; +} + +static void +Opcode_max_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cf000; +} + +static void +Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9960004; +} + +static void +Opcode_max_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cd000; +} + +static void +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_maxu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a000; +} + +static void +Opcode_maxu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140e000; +} + +static void +Opcode_maxu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e0000; + slotbuf[1] = 0; +} + +static void +Opcode_maxu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e62000; + slotbuf[1] = 0; +} + +static void +Opcode_maxu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054f000; + slotbuf[1] = 0; +} + +static void +Opcode_maxu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab000; +} + +static void +Opcode_maxu_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ca000; +} + +static void +Opcode_maxu_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a2000; +} + +static void +Opcode_maxu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063a000; +} + +static void +Opcode_maxu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a21000; +} + +static void +Opcode_maxu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158a000; +} + +static void +Opcode_maxu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2756000; +} + +static void +Opcode_maxu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510000; +} + +static void +Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9928004; +} + +static void +Opcode_maxu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150e000; +} + +static void +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_min_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0b000; +} + +static void +Opcode_min_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140f000; +} + +static void +Opcode_min_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e1000; + slotbuf[1] = 0; +} + +static void +Opcode_min_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6a000; + slotbuf[1] = 0; +} + +static void +Opcode_min_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10751000; + slotbuf[1] = 0; +} + +static void +Opcode_min_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac000; +} + +static void +Opcode_min_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3cb000; +} + +static void +Opcode_min_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a3000; +} + +static void +Opcode_min_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063b000; +} + +static void +Opcode_min_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a25000; +} + +static void +Opcode_min_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ca000; +} + +static void +Opcode_min_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2757000; +} + +static void +Opcode_min_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1511000; +} + +static void +Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9968004; +} + +static void +Opcode_min_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150f000; +} + +static void +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_minu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4a000; +} + +static void +Opcode_minu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144e000; +} + +static void +Opcode_minu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e2000; + slotbuf[1] = 0; +} + +static void +Opcode_minu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e72000; + slotbuf[1] = 0; +} + +static void +Opcode_minu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10753000; + slotbuf[1] = 0; +} + +static void +Opcode_minu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ad000; +} + +static void +Opcode_minu_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3cc000; +} + +static void +Opcode_minu_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a4000; +} + +static void +Opcode_minu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063c000; +} + +static void +Opcode_minu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a29000; +} + +static void +Opcode_minu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150b000; +} + +static void +Opcode_minu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2758000; +} + +static void +Opcode_minu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1550000; +} + +static void +Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9970008; +} + +static void +Opcode_minu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154e000; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40e000; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40f000; +} + +static void +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_sext_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4f000; +} + +static void +Opcode_sext_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1413000; +} + +static void +Opcode_sext_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f3000; + slotbuf[1] = 0; +} + +static void +Opcode_sext_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eea000; + slotbuf[1] = 0; +} + +static void +Opcode_sext_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10567000; + slotbuf[1] = 0; +} + +static void +Opcode_sext_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc000; +} + +static void +Opcode_sext_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3dd000; +} + +static void +Opcode_sext_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b3000; +} + +static void +Opcode_sext_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065b000; +} + +static void +Opcode_sext_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a6d000; +} + +static void +Opcode_sext_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ce000; +} + +static void +Opcode_sext_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2769000; +} + +static void +Opcode_sext_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1515000; +} + +static void +Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996000c; +} + +static void +Opcode_sext_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1513000; +} + +static void +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb002; +} + +static void +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002; +} + +static void +Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36300; +} + +static void +Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136300; +} + +static void +Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616300; +} + +static void +Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20000; +} + +static void +Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf20000; +} + +static void +Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe20000; +} + +static void +Opcode_rsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35f00; +} + +static void +Opcode_wsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135f00; +} + +static void +Opcode_xsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615f00; +} + +static void +Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x406000; +} + +static void +Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x407000; +} + +static void +Opcode_beqz_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000a; + slotbuf[1] = 0; +} + +static void +Opcode_beqz_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000a0; + slotbuf[1] = 0; +} + +static void +Opcode_beqz_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c0; +} + +static void +Opcode_bgez_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000e; + slotbuf[1] = 0; +} + +static void +Opcode_bgez_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000e0; + slotbuf[1] = 0; +} + +static void +Opcode_bgez_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000e0; +} + +static void +Opcode_bltz_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000040a; + slotbuf[1] = 0; +} + +static void +Opcode_bltz_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004a0; + slotbuf[1] = 0; +} + +static void +Opcode_bltz_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001c0; +} + +static void +Opcode_bnez_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000040e; + slotbuf[1] = 0; +} + +static void +Opcode_bnez_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004e0; + slotbuf[1] = 0; +} + +static void +Opcode_bnez_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001e0; +} + +static void +Opcode_beqi_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0; +} + +static void +Opcode_beqi_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0; +} + +static void +Opcode_beqi_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; +} + +static void +Opcode_bgei_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000004; + slotbuf[1] = 0; +} + +static void +Opcode_bgei_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000040; + slotbuf[1] = 0; +} + +static void +Opcode_bgei_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; +} + +static void +Opcode_blti_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000c; + slotbuf[1] = 0; +} + +static void +Opcode_blti_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c0; + slotbuf[1] = 0; +} + +static void +Opcode_blti_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000060; +} + +static void +Opcode_bnei_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000006; + slotbuf[1] = 0; +} + +static void +Opcode_bnei_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000060; + slotbuf[1] = 0; +} + +static void +Opcode_bnei_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000a0; +} + +static void +Opcode_bgeui_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000008; + slotbuf[1] = 0; +} + +static void +Opcode_bgeui_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000080; + slotbuf[1] = 0; +} + +static void +Opcode_bgeui_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000040; +} + +static void +Opcode_bltui_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000002; + slotbuf[1] = 0; +} + +static void +Opcode_bltui_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; + slotbuf[1] = 0; +} + +static void +Opcode_bltui_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000080; +} + +static void +Opcode_bbci_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0; +} + +static void +Opcode_bbci_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_bbci_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_bbsi_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000400; + slotbuf[1] = 0; +} + +static void +Opcode_bbsi_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; + slotbuf[1] = 0; +} + +static void +Opcode_bbsi_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; +} + +static void +Opcode_ball_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000800; + slotbuf[1] = 0; +} + +static void +Opcode_ball_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; + slotbuf[1] = 0; +} + +static void +Opcode_ball_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; +} + +static void +Opcode_bany_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000c00; + slotbuf[1] = 0; +} + +static void +Opcode_bany_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600; + slotbuf[1] = 0; +} + +static void +Opcode_bany_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500; +} + +static void +Opcode_bbc_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000900; + slotbuf[1] = 0; +} + +static void +Opcode_bbc_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00; + slotbuf[1] = 0; +} + +static void +Opcode_bbc_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600; +} + +static void +Opcode_bbs_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000d00; + slotbuf[1] = 0; +} + +static void +Opcode_bbs_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00; + slotbuf[1] = 0; +} + +static void +Opcode_bbs_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700; +} + +static void +Opcode_beq_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000200; + slotbuf[1] = 0; +} + +static void +Opcode_beq_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100; + slotbuf[1] = 0; +} + +static void +Opcode_beq_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; +} + +static void +Opcode_bgeu_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000600; + slotbuf[1] = 0; +} + +static void +Opcode_bgeu_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500; + slotbuf[1] = 0; +} + +static void +Opcode_bgeu_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900; +} + +static void +Opcode_bge_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000a00; + slotbuf[1] = 0; +} + +static void +Opcode_bge_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900; + slotbuf[1] = 0; +} + +static void +Opcode_bge_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00; +} + +static void +Opcode_bltu_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000e00; + slotbuf[1] = 0; +} + +static void +Opcode_bltu_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00; + slotbuf[1] = 0; +} + +static void +Opcode_bltu_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00; +} + +static void +Opcode_blt_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000300; + slotbuf[1] = 0; +} + +static void +Opcode_blt_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300; + slotbuf[1] = 0; +} + +static void +Opcode_blt_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00; +} + +static void +Opcode_bnall_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000700; + slotbuf[1] = 0; +} + +static void +Opcode_bnall_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700; + slotbuf[1] = 0; +} + +static void +Opcode_bnall_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00; +} + +static void +Opcode_bne_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000b00; + slotbuf[1] = 0; +} + +static void +Opcode_bne_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00; + slotbuf[1] = 0; +} + +static void +Opcode_bne_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00; +} + +static void +Opcode_bnone_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000f00; + slotbuf[1] = 0; +} + +static void +Opcode_bnone_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00; + slotbuf[1] = 0; +} + +static void +Opcode_bnone_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00; +} + +static void +Opcode_ae_sext16_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800d; +} + +static void +Opcode_ae_zext16_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900d; +} + +static void +Opcode_ae_zext8_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00d; +} + +static void +Opcode_ae_clamps16_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00d; +} + +static void +Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e80; +} + +static void +Opcode_rur_fcr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a7030; +} + +static void +Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e800; +} + +static void +Opcode_wur_fcr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa64005; +} + +static void +Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e90; +} + +static void +Opcode_rur_fsr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a7070; +} + +static void +Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e900; +} + +static void +Opcode_wur_fsr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa66005; +} + +static void +Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1200; +} + +static void +Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static void +Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f00; +} + +static void +Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f000; +} + +static void +Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f10; +} + +static void +Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f100; +} + +static void +Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f20; +} + +static void +Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f200; +} + +static void +Opcode_rur_ae_cw_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f30; +} + +static void +Opcode_wur_ae_cw_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f300; +} + +static void +Opcode_rur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f60; +} + +static void +Opcode_wur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f600; +} + +static void +Opcode_rur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f70; +} + +static void +Opcode_wur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f700; +} + +static void +Opcode_rur_ae_cbegin1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f80; +} + +static void +Opcode_wur_ae_cbegin1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f800; +} + +static void +Opcode_rur_ae_cend1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f90; +} + +static void +Opcode_wur_ae_cend1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f900; +} + +static void +Opcode_rur_ae_cbegin2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30fa0; +} + +static void +Opcode_wur_ae_cbegin2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3fa00; +} + +static void +Opcode_rur_ae_cend2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30fb0; +} + +static void +Opcode_wur_ae_cend2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3fb00; +} + +static void +Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e60; +} + +static void +Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e600; +} + +static void +Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ea04; +} + +static void +Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67eb04; +} + +static void +Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ec04; +} + +static void +Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ed04; +} + +static void +Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ee04; +} + +static void +Opcode_rur_ae_bitptr_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afe0b; + slotbuf[1] = 0; +} + +static void +Opcode_rur_ae_bitptr_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687705; +} + +static void +Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ef04; +} + +static void +Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f004; +} + +static void +Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f104; +} + +static void +Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f204; +} + +static void +Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f304; +} + +static void +Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f404; +} + +static void +Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f504; +} + +static void +Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f604; +} + +static void +Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f704; +} + +static void +Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f804; +} + +static void +Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f904; +} + +static void +Opcode_rur_ae_cwrap_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67fa04; +} + +static void +Opcode_wur_ae_cwrap_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67fb04; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3c000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7450000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10676000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168300; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054c000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901800; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133c000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2676000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c0000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb980008; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13be000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7c000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1440000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7452000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10678000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054e000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941800; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137c000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2678000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1502000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c0008; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fe000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1480000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7454000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1067a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170100; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10550000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981800; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13bc000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x267a000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1542000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb98000c; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xafc000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c0000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7456000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1067c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170200; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10552000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1800; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fc000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x267c000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1582000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c000c; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1540000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3e000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1402000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7458000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1067e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170300; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10554000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901a00; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133e000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x267e000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c2000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb981000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7e000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1442000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x745a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10556000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941a00; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137e000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2680000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1504000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c1000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c0000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabe000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1482000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x745c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10682000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178100; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10558000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981a00; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13be000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2682000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1544000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb981004; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1502000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xafe000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c2000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x745e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10684000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178200; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055a000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1a00; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fe000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2684000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1584000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c1004; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1542000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1404000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7490000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10686000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178300; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055c000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901c00; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2686000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c4000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb981008; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1582000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1444000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7492000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10688000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055e000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941c00; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1540000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2688000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1506000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c1008; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c2000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1484000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7494000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1068a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180100; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10560000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981c00; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268a000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1546000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb98100c; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1504000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c4000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7496000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1068c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180200; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10562000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1c00; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c0000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268c000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1586000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c100c; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1544000; +} + +static void +Opcode_ae_s8x4u_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7560000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x4u_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10784000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x4u_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a4000; +} + +static void +Opcode_ae_s8x4u_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2bc0000; +} + +static void +Opcode_ae_s8x4u_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2790000; +} + +static void +Opcode_ae_s8x4u_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b21000; +} + +static void +Opcode_ae_s8x4u_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7566000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x4u_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x4u_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106aa000; +} + +static void +Opcode_ae_s8x4u_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac0600; +} + +static void +Opcode_ae_s8x4u_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2796000; +} + +static void +Opcode_ae_s8x4u_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b2100c; +} + +static void +Opcode_ae_s8x4u_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7562000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x4u_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10786000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x4u_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a6000; +} + +static void +Opcode_ae_s8x4u_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2bc0200; +} + +static void +Opcode_ae_s8x4u_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2792000; +} + +static void +Opcode_ae_s8x4u_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b21004; +} + +static void +Opcode_ae_s8x4u_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7564000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x4u_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x4u_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a8000; +} + +static void +Opcode_ae_s8x4u_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2bc0400; +} + +static void +Opcode_ae_s8x4u_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2794000; +} + +static void +Opcode_ae_s8x4u_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b21008; +} + +static void +Opcode_ae_l16m_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae0000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1266000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c836000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110300; +} + +static void +Opcode_ae_l16m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10466000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e4000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2606000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1366000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a60004; +} + +static void +Opcode_ae_l16m_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1366000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa22000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1268000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c874000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10468000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900200; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1326000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2608000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1368000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1368000; +} + +static void +Opcode_ae_l16m_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa20000; +} + +static void +Opcode_ae_l16m_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1260000; +} + +static void +Opcode_ae_l16m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c832000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ec000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ae_l16m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10460000; +} + +static void +Opcode_ae_l16m_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900000; +} + +static void +Opcode_ae_l16m_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1324000; +} + +static void +Opcode_ae_l16m_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2600000; +} + +static void +Opcode_ae_l16m_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1360000; +} + +static void +Opcode_ae_l16m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9860000; +} + +static void +Opcode_ae_l16m_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1360000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1262000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c872000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_iu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ee000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_iu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110100; +} + +static void +Opcode_ae_l16m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10462000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1364000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2602000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1362000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9860004; +} + +static void +Opcode_ae_l16m_iu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1362000; +} + +static void +Opcode_ae_l16m_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa0000; +} + +static void +Opcode_ae_l16m_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1264000; +} + +static void +Opcode_ae_l16m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c834000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110200; +} + +static void +Opcode_ae_l16m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10464000; +} + +static void +Opcode_ae_l16m_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980000; +} + +static void +Opcode_ae_l16m_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a4000; +} + +static void +Opcode_ae_l16m_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2604000; +} + +static void +Opcode_ae_l16m_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1364000; +} + +static void +Opcode_ae_l16m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a60000; +} + +static void +Opcode_ae_l16m_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1364000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa62000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x126a000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c876000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1046a000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940200; +} + +static void +Opcode_ae_l16m_xu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1366000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260a000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136a000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e0000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136a000; +} + +static void +Opcode_ae_l16_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2a000; +} + +static void +Opcode_ae_l16_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ac000; +} + +static void +Opcode_ae_l16_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8cc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1047e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_ae_l16_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10508000; +} + +static void +Opcode_ae_l16_xc_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x920300; +} + +static void +Opcode_ae_l16_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940a00; +} + +static void +Opcode_ae_l16_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136e000; +} + +static void +Opcode_ae_l16_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262a000; +} + +static void +Opcode_ae_l16_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec000; +} + +static void +Opcode_ae_l16_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x982000c; +} + +static void +Opcode_ae_l16_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ac000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6a000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ec000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8ce000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050a000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980a00; +} + +static void +Opcode_ae_l16_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ae000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262c000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ae000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x986000c; +} + +static void +Opcode_ae_l16_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec000; +} + +static void +Opcode_ae_l16_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa68000; +} + +static void +Opcode_ae_l16_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e8000; +} + +static void +Opcode_ae_l16_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8c6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10472000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128200; +} + +static void +Opcode_ae_l16_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10502000; +} + +static void +Opcode_ae_l16_i_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x908300; +} + +static void +Opcode_ae_l16_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980800; +} + +static void +Opcode_ae_l16_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ac000; +} + +static void +Opcode_ae_l16_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2624000; +} + +static void +Opcode_ae_l16_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13aa000; +} + +static void +Opcode_ae_l16_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9c100c; +} + +static void +Opcode_ae_l16_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e8000; +} + +static void +Opcode_ae_l16_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa8000; +} + +static void +Opcode_ae_l16_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12aa000; +} + +static void +Opcode_ae_l16_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8c8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10476000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128300; +} + +static void +Opcode_ae_l16_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10504000; +} + +static void +Opcode_ae_l16_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910300; +} + +static void +Opcode_ae_l16_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0800; +} + +static void +Opcode_ae_l16_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec000; +} + +static void +Opcode_ae_l16_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2626000; +} + +static void +Opcode_ae_l16_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea000; +} + +static void +Opcode_ae_l16_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9820008; +} + +static void +Opcode_ae_l16_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13aa000; +} + +static void +Opcode_ae_l16_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae8000; +} + +static void +Opcode_ae_l16_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ea000; +} + +static void +Opcode_ae_l16_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8ca000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1047a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ae_l16_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10506000; +} + +static void +Opcode_ae_l16_x_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x918300; +} + +static void +Opcode_ae_l16_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900a00; +} + +static void +Opcode_ae_l16_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132e000; +} + +static void +Opcode_ae_l16_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2628000; +} + +static void +Opcode_ae_l16_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ac000; +} + +static void +Opcode_ae_l16_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9860008; +} + +static void +Opcode_ae_l16_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea000; +} + +static void +Opcode_ae_l16_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaaa000; +} + +static void +Opcode_ae_l16_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ae000; +} + +static void +Opcode_ae_l16_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_ae_l16_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050c000; +} + +static void +Opcode_ae_l16_xp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x928300; +} + +static void +Opcode_ae_l16_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0a00; +} + +static void +Opcode_ae_l16_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee000; +} + +static void +Opcode_ae_l16_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262e000; +} + +static void +Opcode_ae_l16_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee000; +} + +static void +Opcode_ae_l16_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a20008; +} + +static void +Opcode_ae_l16_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ae000; +} + +static void +Opcode_ae_l8_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc06000; +} + +static void +Opcode_ae_l8_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140a000; +} + +static void +Opcode_ae_l8_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74d8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190200; +} + +static void +Opcode_ae_l8_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10574000; +} + +static void +Opcode_ae_l8_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942200; +} + +static void +Opcode_ae_l8_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1546000; +} + +static void +Opcode_ae_l8_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a0000; +} + +static void +Opcode_ae_l8_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150c000; +} + +static void +Opcode_ae_l8_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab40000; +} + +static void +Opcode_ae_l8_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1588000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc46000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144a000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74da000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10576000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982200; +} + +static void +Opcode_ae_l8_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1586000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a2000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154c000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab40004; +} + +static void +Opcode_ae_l8_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c8000; +} + +static void +Opcode_ae_l8_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc44000; +} + +static void +Opcode_ae_l8_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1448000; +} + +static void +Opcode_ae_l8_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74d2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10696000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188300; +} + +static void +Opcode_ae_l8_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056e000; +} + +static void +Opcode_ae_l8_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982000; +} + +static void +Opcode_ae_l8_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1584000; +} + +static void +Opcode_ae_l8_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269a000; +} + +static void +Opcode_ae_l8_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154a000; +} + +static void +Opcode_ae_l8_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa941004; +} + +static void +Opcode_ae_l8_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c6000; +} + +static void +Opcode_ae_l8_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc84000; +} + +static void +Opcode_ae_l8_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1488000; +} + +static void +Opcode_ae_l8_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74d4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10698000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_ae_l8_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10570000; +} + +static void +Opcode_ae_l8_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2000; +} + +static void +Opcode_ae_l8_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c4000; +} + +static void +Opcode_ae_l8_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269c000; +} + +static void +Opcode_ae_l8_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158a000; +} + +static void +Opcode_ae_l8_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa941008; +} + +static void +Opcode_ae_l8_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1508000; +} + +static void +Opcode_ae_l8_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc4000; +} + +static void +Opcode_ae_l8_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c8000; +} + +static void +Opcode_ae_l8_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74d6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190100; +} + +static void +Opcode_ae_l8_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10572000; +} + +static void +Opcode_ae_l8_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902200; +} + +static void +Opcode_ae_l8_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1506000; +} + +static void +Opcode_ae_l8_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269e000; +} + +static void +Opcode_ae_l8_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ca000; +} + +static void +Opcode_ae_l8_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa94100c; +} + +static void +Opcode_ae_l8_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1548000; +} + +static void +Opcode_ae_l8_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc86000; +} + +static void +Opcode_ae_l8_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148a000; +} + +static void +Opcode_ae_l8_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74dc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190300; +} + +static void +Opcode_ae_l8_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10578000; +} + +static void +Opcode_ae_l8_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2200; +} + +static void +Opcode_ae_l8_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c6000; +} + +static void +Opcode_ae_l8_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a4000; +} + +static void +Opcode_ae_l8_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158c000; +} + +static void +Opcode_ae_l8_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab40008; +} + +static void +Opcode_ae_l8_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150a000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaac000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b0000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8d8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10648000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138200; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10514000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2636000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f0000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a0008; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b0000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaec000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f0000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8da000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10516000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2638000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1332000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e0008; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f0000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaea000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ee000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8d2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10642000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_ae_l32f24_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050e000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2630000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a60008; +} + +static void +Opcode_ae_l32f24_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2c000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1230000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8d4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10644000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10510000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2632000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1370000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a2000c; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6c000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1270000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8d6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10646000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138100; +} + +static void +Opcode_ae_l32f24_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10512000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2634000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b0000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a6000c; +} + +static void +Opcode_ae_l32f24_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1370000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2e000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1232000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8dc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138300; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10518000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263a000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1372000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a000c; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1332000; +} + +static void +Opcode_ae_l32_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf6000; +} + +static void +Opcode_ae_l32_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12fa000; +} + +static void +Opcode_ae_l32_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7410000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1066a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ae_l32_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1053c000; +} + +static void +Opcode_ae_l32_xc_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x960300; +} + +static void +Opcode_ae_l32_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981200; +} + +static void +Opcode_ae_l32_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b6000; +} + +static void +Opcode_ae_l32_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2662000; +} + +static void +Opcode_ae_l32_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137c000; +} + +static void +Opcode_ae_l32_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3a100c; +} + +static void +Opcode_ae_l32_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ba000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa38000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x123c000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7412000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1053e000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1200; +} + +static void +Opcode_ae_l32_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f6000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2664000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13bc000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3e100c; +} + +static void +Opcode_ae_l32_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fa000; +} + +static void +Opcode_ae_l32_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa36000; +} + +static void +Opcode_ae_l32_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x123a000; +} + +static void +Opcode_ae_l32_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8fa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10664000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158100; +} + +static void +Opcode_ae_l32_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10536000; +} + +static void +Opcode_ae_l32_i_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x948300; +} + +static void +Opcode_ae_l32_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1000; +} + +static void +Opcode_ae_l32_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f4000; +} + +static void +Opcode_ae_l32_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x265c000; +} + +static void +Opcode_ae_l32_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ba000; +} + +static void +Opcode_ae_l32_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3e100c; +} + +static void +Opcode_ae_l32_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f8000; +} + +static void +Opcode_ae_l32_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa76000; +} + +static void +Opcode_ae_l32_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x127a000; +} + +static void +Opcode_ae_l32_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8fc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10666000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158200; +} + +static void +Opcode_ae_l32_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10538000; +} + +static void +Opcode_ae_l32_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x950300; +} + +static void +Opcode_ae_l32_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901200; +} + +static void +Opcode_ae_l32_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1336000; +} + +static void +Opcode_ae_l32_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x265e000; +} + +static void +Opcode_ae_l32_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fa000; +} + +static void +Opcode_ae_l32_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3a100c; +} + +static void +Opcode_ae_l32_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a000; +} + +static void +Opcode_ae_l32_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab6000; +} + +static void +Opcode_ae_l32_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ba000; +} + +static void +Opcode_ae_l32_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8fe000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10668000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158300; +} + +static void +Opcode_ae_l32_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1053a000; +} + +static void +Opcode_ae_l32_x_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x958300; +} + +static void +Opcode_ae_l32_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941200; +} + +static void +Opcode_ae_l32_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1376000; +} + +static void +Opcode_ae_l32_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2660000; +} + +static void +Opcode_ae_l32_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133c000; +} + +static void +Opcode_ae_l32_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3e100c; +} + +static void +Opcode_ae_l32_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137a000; +} + +static void +Opcode_ae_l32_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa78000; +} + +static void +Opcode_ae_l32_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x127c000; +} + +static void +Opcode_ae_l32_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7414000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1066c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160100; +} + +static void +Opcode_ae_l32_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10540000; +} + +static void +Opcode_ae_l32_xp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x968300; +} + +static void +Opcode_ae_l32_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901400; +} + +static void +Opcode_ae_l32_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338000; +} + +static void +Opcode_ae_l32_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2666000; +} + +static void +Opcode_ae_l32_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fc000; +} + +static void +Opcode_ae_l32_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3a100c; +} + +static void +Opcode_ae_l32_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133c000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1234000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8e4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10652000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140300; +} + +static void +Opcode_ae_l32m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10520000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0c00; +} + +static void +Opcode_ae_l32m_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f0000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2642000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1374000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa000c; +} + +static void +Opcode_ae_l32m_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1334000; +} + +static void +Opcode_ae_l32m_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6e000; +} + +static void +Opcode_ae_l32m_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1272000; +} + +static void +Opcode_ae_l32m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8de000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_l32m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1051a000; +} + +static void +Opcode_ae_l32m_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900c00; +} + +static void +Opcode_ae_l32m_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330000; +} + +static void +Opcode_ae_l32m_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263c000; +} + +static void +Opcode_ae_l32m_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b2000; +} + +static void +Opcode_ae_l32m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e000c; +} + +static void +Opcode_ae_l32m_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1372000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaae000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b2000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_iu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_iu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140100; +} + +static void +Opcode_ae_l32m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1051c000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940c00; +} + +static void +Opcode_ae_l32m_iu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1370000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263e000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f2000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa0008; +} + +static void +Opcode_ae_l32m_iu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b2000; +} + +static void +Opcode_ae_l32m_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaee000; +} + +static void +Opcode_ae_l32m_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f2000; +} + +static void +Opcode_ae_l32m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8e2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10650000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140200; +} + +static void +Opcode_ae_l32m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1051e000; +} + +static void +Opcode_ae_l32m_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980c00; +} + +static void +Opcode_ae_l32m_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b0000; +} + +static void +Opcode_ae_l32m_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2640000; +} + +static void +Opcode_ae_l32m_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1334000; +} + +static void +Opcode_ae_l32m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae0008; +} + +static void +Opcode_ae_l32m_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f2000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa70000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1274000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8e6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10654000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10522000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900e00; +} + +static void +Opcode_ae_l32m_xu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1332000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2644000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b4000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae000c; +} + +static void +Opcode_ae_l32m_xu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1374000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa64000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e0000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c83e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10472000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940400; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1368000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2612000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e0000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa981000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e0000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa4000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a2000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c878000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10474000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980400; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a8000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2614000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a2000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a2000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa2000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x126c000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c838000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118100; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1046c000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980200; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a6000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260c000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136c000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e0004; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136c000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae2000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x126e000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c83a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118200; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1046e000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0200; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e6000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260e000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136e000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae0000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136e000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa24000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a0000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c83c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118300; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10470000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900400; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1328000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2610000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a0000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae0004; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a0000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae4000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e2000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c87a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fe000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120100; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10476000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0400; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e8000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2616000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e2000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9c1000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e2000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa32000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1236000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8ea000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10658000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148300; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10526000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ca000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ca000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264a000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1376000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83e100c; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f4000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa72000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1276000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8ec000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10528000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6cc000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6cc000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264c000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b6000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x93a100c; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1336000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab0000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b4000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19002030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00202; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148100; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10618008; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680050; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680050; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2646000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f4000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9871001; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000d; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc50080; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d2000; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d86a080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10576008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198300; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c2002; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea000; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea000; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276e000; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d4000; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b70006; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d2000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd0080; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1454000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d834080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1061e004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0100; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fc003; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea080; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea080; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277e000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996100e; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1554000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1492008; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74fc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01e01; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198208; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c4002; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276c080; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1594008; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b7000a; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1592008; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd00c0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1454004; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8340c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c010e; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2001; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6080; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6080; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277e040; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556004; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0303; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516002; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd00d0; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1454005; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8360c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00402; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2009; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6090; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6090; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277e050; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556005; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a0303; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556002; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf0000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f4000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8e8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10656000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148200; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10524000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c8000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c8000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2648000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1336000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a100c; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b4000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab2000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b6000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8ee000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1052a000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ce000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ce000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264e000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f6000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x93e100c; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1376000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa74000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1278000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8f2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150300; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1052e000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d2000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d2000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0e00; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f2000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2654000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b8000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3e100c; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f6000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab4000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b8000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8f4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10530000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d4000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d4000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1334000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2656000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f8000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3a100c; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf2000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f6000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19004030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04203; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150100; +} + +static void +Opcode_ae_l32x2_i_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x298000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10618004; +} + +static void +Opcode_ae_l32x2_i_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930300; +} + +static void +Opcode_ae_l32x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680060; +} + +static void +Opcode_ae_l32x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680060; +} + +static void +Opcode_ae_l32x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940e00; +} + +static void +Opcode_ae_l32x2_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1372000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2650000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9871002; +} + +static void +Opcode_ae_l32x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000e; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90080; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d2008; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74fe000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01f01; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057a008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198308; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c6002; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x970380; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee000; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee000; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac0400; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1550000; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276e080; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d4008; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b7000e; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d2008; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd00e0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1454006; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8340d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00401; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c010f; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2005; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f60a0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f60a0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80600; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200f; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277e060; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556006; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e0303; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1596002; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd00f0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1454007; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8360d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00403; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a200d; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f60b0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f60b0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80610; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x155200f; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277e070; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556007; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e0303; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d6002; +} + +static void +Opcode_ae_l32x2_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa34000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1238000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8f0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150200; +} + +static void +Opcode_ae_l32x2_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1052c000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x938300; +} + +static void +Opcode_ae_l32x2_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980e00; +} + +static void +Opcode_ae_l32x2_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b2000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2652000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1378000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3a100c; +} + +static void +Opcode_ae_l32x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b6000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf4000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f8000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8f8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10662000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29a000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10534000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940300; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d6000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d6000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b4000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x265a000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137a000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3a100c; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b8000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa6000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a6000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c87e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10466000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1047a000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c2000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c2000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980600; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13aa000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261c000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a6000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9c1004; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e4000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae6000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e6000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1047c000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c4000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c4000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0600; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261e000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e6000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa981008; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a6000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa26000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a4000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00203; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120200; +} + +static void +Opcode_ae_l16x4_i_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x294000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10618000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900300; +} + +static void +Opcode_ae_l16x4_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680040; +} + +static void +Opcode_ae_l16x4_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680040; +} + +static void +Opcode_ae_l16x4_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900600; +} + +static void +Opcode_ae_l16x4_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132a000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2618000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a4000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9871000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000c; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc50000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1492000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d82a080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10576000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198200; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0002; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x970300; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e8000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e8000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80400; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276c000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1594000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b70002; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1592000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa66000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e4000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c87c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10462000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120300; +} + +static void +Opcode_ae_l16x4_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10478000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940600; +} + +static void +Opcode_ae_l16x4_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136a000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261a000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e4000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa981004; +} + +static void +Opcode_ae_l16x4_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a4000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa28000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a8000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8c4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1046e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128100; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x296000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c6000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c6000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940800; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136c000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2622000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e8000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa98100c; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a8000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc82000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1486000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x749a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188100; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10566000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e2000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e2000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981e00; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1582000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2692000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1548000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa940004; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c4000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc2000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c6000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x749c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10568000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e4000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e4000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1e00; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c2000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2694000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1588000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa940008; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1506000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc02000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1406000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19082030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0420b; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10708001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180300; +} + +static void +Opcode_ae_l8x8_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10620008; +} + +static void +Opcode_ae_l8x8_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0050; +} + +static void +Opcode_ae_l8x8_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0050; +} + +static void +Opcode_ae_l8x8_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901e00; +} + +static void +Opcode_ae_l8x8_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1502000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268e000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c6000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9971001; +} + +static void +Opcode_ae_l8x8_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144000d; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd0000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1414000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74fc080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c8002; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e8080; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e8080; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80480; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1590000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2770000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9921008; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc42000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1446000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7498000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1068e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10564000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941e00; +} + +static void +Opcode_ae_l8x8_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1542000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2690000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1508000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa940000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1584000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc04000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1408000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10694000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188200; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056c000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e6000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e6000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1544000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2698000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150a000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa941000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1586000; +} + +static void +Opcode_ae_l64_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7a000; +} + +static void +Opcode_ae_l64_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x127e000; +} + +static void +Opcode_ae_l64_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7418000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10670000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168100; +} + +static void +Opcode_ae_l64_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10544000; +} + +static void +Opcode_ae_l64_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6da000; +} + +static void +Opcode_ae_l64_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6da000; +} + +static void +Opcode_ae_l64_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901600; +} + +static void +Opcode_ae_l64_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a000; +} + +static void +Opcode_ae_l64_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x266e000; +} + +static void +Opcode_ae_l64_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fe000; +} + +static void +Opcode_ae_l64_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb980000; +} + +static void +Opcode_ae_l64_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13bc000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaba000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12be000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x741a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10546000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6dc000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6dc000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941600; +} + +static void +Opcode_ae_l64_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137a000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2670000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c0000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fc000; +} + +static void +Opcode_ae_l64_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab8000; +} + +static void +Opcode_ae_l64_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12bc000; +} + +static void +Opcode_ae_l64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19006030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04202; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160200; +} + +static void +Opcode_ae_l64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1061800c; +} + +static void +Opcode_ae_l64_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680070; +} + +static void +Opcode_ae_l64_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680070; +} + +static void +Opcode_ae_l64_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941400; +} + +static void +Opcode_ae_l64_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1378000; +} + +static void +Opcode_ae_l64_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2668000; +} + +static void +Opcode_ae_l64_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133e000; +} + +static void +Opcode_ae_l64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9871003; +} + +static void +Opcode_ae_l64_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000f; +} + +static void +Opcode_ae_l64_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf8000; +} + +static void +Opcode_ae_l64_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12fc000; +} + +static void +Opcode_ae_l64_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19080030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0020b; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10708000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160300; +} + +static void +Opcode_ae_l64_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10620000; +} + +static void +Opcode_ae_l64_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0040; +} + +static void +Opcode_ae_l64_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0040; +} + +static void +Opcode_ae_l64_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981400; +} + +static void +Opcode_ae_l64_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b8000; +} + +static void +Opcode_ae_l64_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x266a000; +} + +static void +Opcode_ae_l64_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137e000; +} + +static void +Opcode_ae_l64_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9971000; +} + +static void +Opcode_ae_l64_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144000c; +} + +static void +Opcode_ae_l64_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3a000; +} + +static void +Opcode_ae_l64_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x123e000; +} + +static void +Opcode_ae_l64_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7416000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1066e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_ae_l64_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10542000; +} + +static void +Opcode_ae_l64_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d8000; +} + +static void +Opcode_ae_l64_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d8000; +} + +static void +Opcode_ae_l64_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1400; +} + +static void +Opcode_ae_l64_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f8000; +} + +static void +Opcode_ae_l64_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x266c000; +} + +static void +Opcode_ae_l64_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13be000; +} + +static void +Opcode_ae_l64_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e100c; +} + +static void +Opcode_ae_l64_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137c000; +} + +static void +Opcode_ae_l64_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xafa000; +} + +static void +Opcode_ae_l64_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12fe000; +} + +static void +Opcode_ae_l64_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x741e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10674000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168200; +} + +static void +Opcode_ae_l64_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054a000; +} + +static void +Opcode_ae_l64_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6de000; +} + +static void +Opcode_ae_l64_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6de000; +} + +static void +Opcode_ae_l64_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1600; +} + +static void +Opcode_ae_l64_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fa000; +} + +static void +Opcode_ae_l64_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2674000; +} + +static void +Opcode_ae_l64_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580000; +} + +static void +Opcode_ae_l64_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c0004; +} + +static void +Opcode_ae_l64_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137e000; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7550000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058c000; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942800; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b8000; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9821008; +} + +static void +Opcode_ae_s16x2m_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7552000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058e000; +} + +static void +Opcode_ae_s16x2m_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982800; +} + +static void +Opcode_ae_s16x2m_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ba000; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x751a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106aa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10586000; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982600; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b2000; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9861000; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x751c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ac000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10588000; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2600; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b4000; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9821004; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x751e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ae000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058a000; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902800; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b6000; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9861004; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7554000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10590000; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2800; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26bc000; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9861008; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7428000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c4000; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f6000; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae100c; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c6000; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f8000; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab80000; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19100030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10710000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10628000; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318000; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f2000; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a70000; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d82e080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10730008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ce002; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380000; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2776000; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996100a; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8340f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718007; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2006; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2984010; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996110f; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8340e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718006; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2002; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2904010; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996100f; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8360e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a200a; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2944010; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996120f; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7426000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106de000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c2000; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f4000; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa100c; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c8000; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26fa000; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc0000; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7434000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ea000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d0000; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3200; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2706000; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc0008; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7436000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d2000; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903400; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2708000; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab8000c; +} + +static void +Opcode_ae_s32x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19104030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10710002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10628004; +} + +static void +Opcode_ae_s32x2_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318010; +} + +static void +Opcode_ae_s32x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943200; +} + +static void +Opcode_ae_s32x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2702000; +} + +static void +Opcode_ae_s32x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a70002; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d86e080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10732008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d2002; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380200; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00600; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277a000; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996100c; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8360f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071800a; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a200e; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80620; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c4010; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996130f; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191a4030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2003; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80630; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2906010; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0120c; +} + +static void +Opcode_ae_s32x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7432000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ce000; +} + +static void +Opcode_ae_s32x2_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308200; +} + +static void +Opcode_ae_s32x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983200; +} + +static void +Opcode_ae_s32x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2704000; +} + +static void +Opcode_ae_s32x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab80008; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x743a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ee000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d6000; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308300; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983400; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270c000; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab81000; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19102030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10710001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10628008; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318200; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26fc000; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a70001; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d86c080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10732000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d0002; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380100; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2778000; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x992100c; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ca000; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308000; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26fe000; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab80004; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7430000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105cc000; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308100; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700000; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc0004; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x755c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ba000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10598000; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982a00; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c8000; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a61000; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x755e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1059a000; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2a00; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ca000; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a21004; +} + +static void +Opcode_ae_s16x4_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19086030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10708003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1062000c; +} + +static void +Opcode_ae_s16x4_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1310210; +} + +static void +Opcode_ae_s16x4_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902a00; +} + +static void +Opcode_ae_s16x4_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c4000; +} + +static void +Opcode_ae_s16x4_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9971003; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d82c080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10730000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104cc002; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318310; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac0480; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2774000; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x992100a; +} + +static void +Opcode_ae_s16x4_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x755a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10596000; +} + +static void +Opcode_ae_s16x4_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330200; +} + +static void +Opcode_ae_s16x4_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942a00; +} + +static void +Opcode_ae_s16x4_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c6000; +} + +static void +Opcode_ae_s16x4_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a21000; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7592000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106be000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1059e000; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330300; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942c00; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ce000; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a21008; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1051e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105fc000; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00000; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2738000; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc1004; +} + +static void +Opcode_ae_s8x8_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74a2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105fe000; +} + +static void +Opcode_ae_s8x8_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a40000; +} + +static void +Opcode_ae_s8x8_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x273a000; +} + +static void +Opcode_ae_s8x8_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb81008; +} + +static void +Opcode_ae_s8x8_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19182030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10630008; +} + +static void +Opcode_ae_s8x8_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983e00; +} + +static void +Opcode_ae_s8x8_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2734000; +} + +static void +Opcode_ae_s8x8_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b70001; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d830080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10734000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d4002; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a40600; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277c000; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x992100e; +} + +static void +Opcode_ae_s8x8_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x747e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1051a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105fa000; +} + +static void +Opcode_ae_s8x8_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3e00; +} + +static void +Opcode_ae_s8x8_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2736000; +} + +static void +Opcode_ae_s8x8_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb81004; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74a6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10526000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10602000; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac0000; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x273e000; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb8100c; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7514000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10580000; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2400; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ac000; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab41008; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7516000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10582000; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902600; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ae000; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab4100c; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74de000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057a000; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902400; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a6000; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab4000c; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7510000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057c000; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942400; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a8000; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab41000; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7512000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057e000; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982400; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26aa000; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab41004; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7518000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10584000; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942600; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b0000; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9821000; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75d6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b2000; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e2000; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a100c; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75d8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b4000; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e4000; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e100c; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ca000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ac000; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26dc000; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e1004; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75d2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106cc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae000; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26de000; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a1008; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75d4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ce000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b0000; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e0000; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e1008; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75da000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b6000; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e6000; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa1000; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x746e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10502000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ea000; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903a00; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2720000; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb80004; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7470000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ec000; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943a00; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2722000; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc0004; +} + +static void +Opcode_ae_s32_l_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7468000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106fa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e4000; +} + +static void +Opcode_ae_s32_l_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943800; +} + +static void +Opcode_ae_s32_l_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x271a000; +} + +static void +Opcode_ae_s32_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc100c; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x746a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106fc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e6000; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983800; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x271c000; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb80000; +} + +static void +Opcode_ae_s32_l_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x746c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106fe000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e8000; +} + +static void +Opcode_ae_s32_l_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3800; +} + +static void +Opcode_ae_s32_l_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x271e000; +} + +static void +Opcode_ae_s32_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc0000; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7472000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10506000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ee000; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983a00; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2724000; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb80008; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7462000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105de000; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983600; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2714000; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab81008; +} + +static void +Opcode_ae_s32_h_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7464000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e0000; +} + +static void +Opcode_ae_s32_h_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3600; +} + +static void +Opcode_ae_s32_h_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2716000; +} + +static void +Opcode_ae_s32_h_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc1008; +} + +static void +Opcode_ae_s32_h_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x743c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d8000; +} + +static void +Opcode_ae_s32_h_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3400; +} + +static void +Opcode_ae_s32_h_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270e000; +} + +static void +Opcode_ae_s32_h_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc1000; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x743e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105da000; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903600; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2710000; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab81004; +} + +static void +Opcode_ae_s32_h_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7460000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105dc000; +} + +static void +Opcode_ae_s32_h_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943600; +} + +static void +Opcode_ae_s32_h_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2712000; +} + +static void +Opcode_ae_s32_h_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc1004; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7466000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e2000; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903800; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2718000; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab8100c; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x759a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a6000; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942e00; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d6000; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a1000; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x759c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a8000; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982e00; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d8000; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e1000; +} + +static void +Opcode_ae_s16_0_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7594000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a0000; +} + +static void +Opcode_ae_s16_0_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982c00; +} + +static void +Opcode_ae_s16_0_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d0000; +} + +static void +Opcode_ae_s16_0_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a61008; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7596000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a2000; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2c00; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d2000; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a2100c; +} + +static void +Opcode_ae_s16_0_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7598000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a4000; +} + +static void +Opcode_ae_s16_0_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902e00; +} + +static void +Opcode_ae_s16_0_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d4000; +} + +static void +Opcode_ae_s16_0_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a6100c; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x759e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa000; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2e00; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26da000; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a1004; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ae000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10536000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060a000; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac0200; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2746000; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9870008; +} + +static void +Opcode_ae_s8_0_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74b0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060c000; +} + +static void +Opcode_ae_s8_0_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00400; +} + +static void +Opcode_ae_s8_0_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2748000; +} + +static void +Opcode_ae_s8_0_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x987000c; +} + +static void +Opcode_ae_s8_0_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74a8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1052a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10604000; +} + +static void +Opcode_ae_s8_0_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00200; +} + +static void +Opcode_ae_s8_0_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2740000; +} + +static void +Opcode_ae_s8_0_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc100c; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74aa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1052e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10606000; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a40200; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2742000; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9870000; +} + +static void +Opcode_ae_s8_0_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ac000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10532000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10608000; +} + +static void +Opcode_ae_s8_0_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80200; +} + +static void +Opcode_ae_s8_0_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2744000; +} + +static void +Opcode_ae_s8_0_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9870004; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74b2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1053a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060e000; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a40400; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x274a000; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9970000; +} + +static void +Opcode_ae_s64_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7476000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f2000; +} + +static void +Opcode_ae_s64_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983c00; +} + +static void +Opcode_ae_s64_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x272c000; +} + +static void +Opcode_ae_s64_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb8000c; +} + +static void +Opcode_ae_s64_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7478000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f4000; +} + +static void +Opcode_ae_s64_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3c00; +} + +static void +Opcode_ae_s64_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x272e000; +} + +static void +Opcode_ae_s64_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc000c; +} + +static void +Opcode_ae_s64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19106030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10710003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1062800c; +} + +static void +Opcode_ae_s64_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3a00; +} + +static void +Opcode_ae_s64_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2726000; +} + +static void +Opcode_ae_s64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a70003; +} + +static void +Opcode_ae_s64_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19180030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10630000; +} + +static void +Opcode_ae_s64_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903c00; +} + +static void +Opcode_ae_s64_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2728000; +} + +static void +Opcode_ae_s64_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b70000; +} + +static void +Opcode_ae_s64_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7474000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0000; +} + +static void +Opcode_ae_s64_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943c00; +} + +static void +Opcode_ae_s64_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x272a000; +} + +static void +Opcode_ae_s64_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc0008; +} + +static void +Opcode_ae_s64_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x747c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10516000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f8000; +} + +static void +Opcode_ae_s64_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943e00; +} + +static void +Opcode_ae_s64_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2732000; +} + +static void +Opcode_ae_s64_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc1000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7422000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106da000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105be000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ee000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa1008; +} + +static void +Opcode_ae_s32m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75dc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b8000; +} + +static void +Opcode_ae_s32m_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903000; +} + +static void +Opcode_ae_s32m_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e8000; +} + +static void +Opcode_ae_s32m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae1000; +} + +static void +Opcode_ae_s32m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75de000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ba000; +} + +static void +Opcode_ae_s32m_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943000; +} + +static void +Opcode_ae_s32m_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ea000; +} + +static void +Opcode_ae_s32m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa1004; +} + +static void +Opcode_ae_s32m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7420000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105bc000; +} + +static void +Opcode_ae_s32m_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983000; +} + +static void +Opcode_ae_s32m_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ec000; +} + +static void +Opcode_ae_s32m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae1004; +} + +static void +Opcode_ae_s32m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7424000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106dc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c0000; +} + +static void +Opcode_ae_s32m_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903200; +} + +static void +Opcode_ae_s32m_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f0000; +} + +static void +Opcode_ae_s32m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae1008; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8f6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10660000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10532000; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941000; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1374000; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2658000; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a000; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3e100c; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1378000; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8c2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1046a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1047e000; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900800; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132c000; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2620000; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a8000; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9c1008; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e6000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x749e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10692000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056a000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1504000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2696000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c8000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa94000c; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1546000; +} + +static void +Opcode_ae_l64_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x741c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10672000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10548000; +} + +static void +Opcode_ae_l64_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981600; +} + +static void +Opcode_ae_l64_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ba000; +} + +static void +Opcode_ae_l64_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2672000; +} + +static void +Opcode_ae_l64_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1540000; +} + +static void +Opcode_ae_l64_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb980004; +} + +static void +Opcode_ae_l64_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133e000; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7438000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ec000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d4000; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943400; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270a000; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc000c; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7590000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106bc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1059c000; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902c00; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26cc000; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a61004; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74a4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10522000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600000; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80000; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x273c000; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc1008; +} + +static void +Opcode_ae_s64_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x747a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10512000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f6000; +} + +static void +Opcode_ae_s64_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903e00; +} + +static void +Opcode_ae_s64_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2730000; +} + +static void +Opcode_ae_s64_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb81000; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19084030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10708002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10620004; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1310010; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26be000; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9971002; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74fe080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057e008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ca002; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318210; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2772000; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9961008; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7556000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10592000; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330000; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c0000; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x982100c; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7558000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10594000; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330100; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c2000; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x986100c; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c500000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe150000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c540000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a40000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1540000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf150000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1940000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1440000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb150000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7340000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900100; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1480000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc150000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19c0000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c0000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd150000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c5c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7840000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1840000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7570000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d480000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1880000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8150000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c380000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1780000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7430000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c3c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c0000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7470000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c480000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7240000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa150000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d380000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d80000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1880000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7830000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc0000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c0000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7870000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc0000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c0000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7860000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900200; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7920000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d340000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d40000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1840000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7960000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c640000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e40000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1940000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7970000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d5c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7850000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d200000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7910000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d500000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7900000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d540000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b40000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1640000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7940000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d580000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b80000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1680000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7810000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d280000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1780000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7820000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_s32x2x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2100000; +} + +static void +Opcode_ae_s32x2x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00000; +} + +static void +Opcode_ae_s32x2x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9800000; +} + +static void +Opcode_ae_s32x2x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2140000; +} + +static void +Opcode_ae_s32x2x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e40000; +} + +static void +Opcode_ae_s32x2x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9840000; +} + +static void +Opcode_ae_s32x2x2_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180000; +} + +static void +Opcode_ae_s32x2x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2040000; +} + +static void +Opcode_ae_s32x2x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d40000; +} + +static void +Opcode_ae_s32x2x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d70000; +} + +static void +Opcode_ae_s32x2x2_ip_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_s32x2x2_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0000; +} + +static void +Opcode_ae_s32x2x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080000; +} + +static void +Opcode_ae_s32x2x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d80000; +} + +static void +Opcode_ae_s32x2x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8800000; +} + +static void +Opcode_ae_s32x2x2_x_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_s32x2x2_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_s32x2x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0000; +} + +static void +Opcode_ae_s32x2x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc0000; +} + +static void +Opcode_ae_s32x2x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8840000; +} + +static void +Opcode_ae_s32x2x2_xp_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_s32x2x2_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_ae_s32x2x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21c0000; +} + +static void +Opcode_ae_s32x2x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec0000; +} + +static void +Opcode_ae_s32x2x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa840000; +} + +static void +Opcode_ae_s32x2x2rng_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c40000; +} + +static void +Opcode_ae_s32x2x2rng_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d60000; +} + +static void +Opcode_ae_s32x2x2rng_ip_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_s32x2x2rng_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80000; +} + +static void +Opcode_ae_s32x2x2rng_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c30000; +} + +static void +Opcode_ae_s32x2x2rng_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc0000; +} + +static void +Opcode_ae_s32x2x2rng_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c70000; +} + +static void +Opcode_ae_s32x2x2rng_xp_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_s32x2x2rng_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00000; +} + +static void +Opcode_ae_s32x2x2rng_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d30000; +} + +static void +Opcode_ae_s16x4x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f40000; +} + +static void +Opcode_ae_s16x4x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b40000; +} + +static void +Opcode_ae_s16x4x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d50000; +} + +static void +Opcode_ae_s16x4x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f80000; +} + +static void +Opcode_ae_s16x4x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b80000; +} + +static void +Opcode_ae_s16x4x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c20000; +} + +static void +Opcode_ae_s16x4x2_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_s16x4x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e80000; +} + +static void +Opcode_ae_s16x4x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a80000; +} + +static void +Opcode_ae_s16x4x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c10000; +} + +static void +Opcode_ae_s16x4x2_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_s16x4x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec0000; +} + +static void +Opcode_ae_s16x4x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac0000; +} + +static void +Opcode_ae_s16x4x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c50000; +} + +static void +Opcode_ae_s16x4x2_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_s16x4x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00000; +} + +static void +Opcode_ae_s16x4x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00000; +} + +static void +Opcode_ae_s16x4x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d10000; +} + +static void +Opcode_ae_s16x4x2_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140000; +} + +static void +Opcode_ae_s16x4x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ae_s16x4x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00000; +} + +static void +Opcode_ae_s16x4x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d20000; +} + +static void +Opcode_ae_s8x8x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2480000; +} + +static void +Opcode_ae_s8x8x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2180000; +} + +static void +Opcode_ae_s8x8x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8900000; +} + +static void +Opcode_ae_s8x8x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24c0000; +} + +static void +Opcode_ae_s8x8x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21c0000; +} + +static void +Opcode_ae_s8x8x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8940000; +} + +static void +Opcode_ae_s8x8x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23c0000; +} + +static void +Opcode_ae_s8x8x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0000; +} + +static void +Opcode_ae_s8x8x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe840000; +} + +static void +Opcode_ae_s8x8x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400000; +} + +static void +Opcode_ae_s8x8x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2100000; +} + +static void +Opcode_ae_s8x8x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf800000; +} + +static void +Opcode_ae_s8x8x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2440000; +} + +static void +Opcode_ae_s8x8x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2140000; +} + +static void +Opcode_ae_s8x8x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf840000; +} + +static void +Opcode_ae_s8x8x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540000; +} + +static void +Opcode_ae_s8x8x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2240000; +} + +static void +Opcode_ae_s8x8x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9940000; +} + +static void +Opcode_ae_s8x4ux2_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20e40000; +} + +static void +Opcode_ae_s8x4ux2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b80000; +} + +static void +Opcode_ae_s8x4ux2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2580080; +} + +static void +Opcode_ae_s8x4ux2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9910000; +} + +static void +Opcode_ae_s8x4ux2_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20e80000; +} + +static void +Opcode_ae_s8x4ux2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b80080; +} + +static void +Opcode_ae_s8x4ux2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c0080; +} + +static void +Opcode_ae_s8x4ux2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9910002; +} + +static void +Opcode_ae_s8x4ux2_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c0000; +} + +static void +Opcode_ae_s8x4ux2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b00000; +} + +static void +Opcode_ae_s8x4ux2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c0000; +} + +static void +Opcode_ae_s8x4ux2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8910000; +} + +static void +Opcode_ae_s8x4ux2_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20e00000; +} + +static void +Opcode_ae_s8x4ux2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b40000; +} + +static void +Opcode_ae_s8x4ux2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000000; +} + +static void +Opcode_ae_s8x4ux2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8950000; +} + +static void +Opcode_ae_s64x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22c0000; +} + +static void +Opcode_ae_s64x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fc0000; +} + +static void +Opcode_ae_s64x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc840000; +} + +static void +Opcode_ae_s64x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300000; +} + +static void +Opcode_ae_s64x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ae_s64x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd800000; +} + +static void +Opcode_ae_s64x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200000; +} + +static void +Opcode_ae_s64x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00000; +} + +static void +Opcode_ae_s64x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb800000; +} + +static void +Opcode_ae_s64x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2240000; +} + +static void +Opcode_ae_s64x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f40000; +} + +static void +Opcode_ae_s64x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb840000; +} + +static void +Opcode_ae_s64x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2280000; +} + +static void +Opcode_ae_s64x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f80000; +} + +static void +Opcode_ae_s64x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc800000; +} + +static void +Opcode_ae_s64x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2380000; +} + +static void +Opcode_ae_s64x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080000; +} + +static void +Opcode_ae_s64x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe800000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c580000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a80000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7800000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d4c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c0000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c0000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9150000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c600000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7930000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d240000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c40000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1740000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7950000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_s32x2x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2180000; +} + +static void +Opcode_ae_s32x2x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e80000; +} + +static void +Opcode_ae_s32x2x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800000; +} + +static void +Opcode_ae_s16x4x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fc0000; +} + +static void +Opcode_ae_s16x4x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc0000; +} + +static void +Opcode_ae_s16x4x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c60000; +} + +static void +Opcode_ae_s8x8x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500000; +} + +static void +Opcode_ae_s8x8x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200000; +} + +static void +Opcode_ae_s8x8x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9900000; +} + +static void +Opcode_ae_s64x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2340000; +} + +static void +Opcode_ae_s64x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2040000; +} + +static void +Opcode_ae_s64x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd840000; +} + +static void +Opcode_ae_s16x4x2rng_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980000; +} + +static void +Opcode_ae_s16x4x2rng_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c00000; +} + +static void +Opcode_ae_s16x4x2rng_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19c0000; +} + +static void +Opcode_ae_s16x4x2rng_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c40000; +} + +static void +Opcode_ae_s16x4x2rng_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00000; +} + +static void +Opcode_ae_s16x4x2rng_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d00000; +} + +static void +Opcode_ae_s16x4x2rng_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a40000; +} + +static void +Opcode_ae_s16x4x2rng_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d40000; +} + +static void +Opcode_ae_zalign64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b48fb4; + slotbuf[1] = 0; +} + +static void +Opcode_ae_zalign64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef70; + slotbuf[1] = 0; +} + +static void +Opcode_ae_zalign64_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069db30; +} + +static void +Opcode_ae_zalign64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab20045; +} + +static void +Opcode_ae_lalign64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f10; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lalign64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10748300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lalign64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680600; +} + +static void +Opcode_ae_lalign64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9839c01; +} + +static void +Opcode_ae_salign64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f20; + slotbuf[1] = 0; +} + +static void +Opcode_ae_salign64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10748700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_salign64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680700; +} + +static void +Opcode_ae_salign64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70ab000; +} + +static void +Opcode_ae_movalign_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b48fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movalign_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef80; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movalign_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687702; +} + +static void +Opcode_ae_movalign_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab20005; +} + +static void +Opcode_ae_la64_pp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b20fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la64_pp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afa0c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la64_pp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf500; +} + +static void +Opcode_ae_la64_pp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685602; +} + +static void +Opcode_ae_la64_pp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08540; +} + +static void +Opcode_ae_la64_pp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09a0e; +} + +static void +Opcode_ae_la64_pp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142e10c; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b50f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af00c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681703; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09a0d; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b40f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074cf0c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681701; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0920d; +} + +static void +Opcode_ae_la24pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b58f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683600; +} + +static void +Opcode_ae_la24pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09e0d; +} + +static void +Opcode_ae_la24neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b48f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681702; +} + +static void +Opcode_ae_la24neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0960d; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b70f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af80c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683603; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0160e; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b60f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af40c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683601; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0120e; +} + +static void +Opcode_ae_la24x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b78f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683700; +} + +static void +Opcode_ae_la24x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0160f; +} + +static void +Opcode_ae_la24x2neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b68f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683602; +} + +static void +Opcode_ae_la24x2neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0120f; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b08fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af20c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683703; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01e0e; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afc0c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683701; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01a0e; +} + +static void +Opcode_ae_la32x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b08fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685600; +} + +static void +Opcode_ae_la32x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01e0f; +} + +static void +Opcode_ae_la32x2neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683702; +} + +static void +Opcode_ae_la32x2neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01a0f; +} + +static void +Opcode_ae_la32x2pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b10fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2pos_pc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af60c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2pos_pc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685601; +} + +static void +Opcode_ae_la32x2pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0920e; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b10f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074cf04; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681602; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09f0e; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074cf00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681600; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09f0c; +} + +static void +Opcode_ae_la16x4pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b18f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681603; +} + +static void +Opcode_ae_la16x4pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09f0f; +} + +static void +Opcode_ae_la16x4neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b08f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681601; +} + +static void +Opcode_ae_la16x4neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09f0d; +} + +static void +Opcode_ae_la16x4pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b20f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4pos_pc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074cf08; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4pos_pc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681700; +} + +static void +Opcode_ae_la16x4pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0120d; +} + +static void +Opcode_ae_la8x8pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b28fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074eb00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685701; +} + +static void +Opcode_ae_la8x8pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09e0f; +} + +static void +Opcode_ae_la8x8neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b20fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afe0c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685603; +} + +static void +Opcode_ae_la8x8neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09a0f; +} + +static void +Opcode_ae_la8x8pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b30fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685702; +} + +static void +Opcode_ae_la8x8pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa820005; +} + +static void +Opcode_ae_la8x8neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b28fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685700; +} + +static void +Opcode_ae_la8x8neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09e0e; +} + +static void +Opcode_ae_la8x8pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b30fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8pos_pc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074eb04; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8pos_pc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685703; +} + +static void +Opcode_ae_la8x8pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa860005; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14230; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416103; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b10fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0ec02; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x686180; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x686180; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f30; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514103; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002430; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151630b; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0920f; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142810c; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14240; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416104; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b18fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0f002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x688180; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x688180; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f40; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514104; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002440; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151640b; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0960e; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142a10c; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14250; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416105; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b18fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0f402; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68a180; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68a180; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f50; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514105; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002450; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151650b; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0960f; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142c10c; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14200; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416100; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b28f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0e002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680180; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680180; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f00; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514100; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002400; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151600b; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0160d; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142210c; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14210; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416101; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b30f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0e402; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x682180; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x682180; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f10; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514101; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002410; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151610b; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01a0d; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142410c; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14220; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416102; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b38f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0e802; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x684180; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x684180; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f20; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514102; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002420; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151620b; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01e0d; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142610c; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14260; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416106; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b38fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0f802; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68c180; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68c180; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f60; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514106; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002460; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151660b; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa920005; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143010c; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14270; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416107; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b38fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0fc02; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68e180; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68e180; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f70; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514107; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002470; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151670b; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa960005; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143210c; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14280; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416108; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b40fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690180; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690180; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f80; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514108; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002480; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151680b; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa20005; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143410c; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b48fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074eb0c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687601; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8a4004; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b40fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074eb08; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687600; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa26004; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193c0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060a004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ee003; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fe000; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fe000; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006f0; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000f; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c40205; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19388030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f0002; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0040; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0040; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00800; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512000; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08205; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193c8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060c004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f0003; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00810; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512001; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48205; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19390030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060e004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0008; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f2002; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08000; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2040; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2040; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00820; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512002; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00305; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400c; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193d8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10612004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f4003; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08040; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f8040; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f8040; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00850; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512005; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48305; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400d; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193d0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10610004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f2003; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4040; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4040; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00830; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512003; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c40305; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19398030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f4002; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6040; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6040; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00840; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512004; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08305; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d838080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10736000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d6002; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea0c0; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea0c0; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00680; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510008; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08208; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d838090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d6003; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec080; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec080; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00690; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510009; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48208; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10736004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d8002; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006a0; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000a; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08209; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10736008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0104; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d8003; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x978300; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee080; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee080; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006b0; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000b; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48209; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514008; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104dc002; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x978340; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0000; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0000; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006e0; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000e; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0820b; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514009; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073600c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104da002; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec0c0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec0c0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006c0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000c; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0820a; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104da003; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee0c0; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee0c0; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006d0; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000d; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c4820a; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193a8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10614004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f6002; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fa040; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fa040; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00880; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512008; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c18201; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193e8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f6003; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fc040; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fc040; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00890; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512009; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c58201; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193b0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10616004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f8002; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008a0; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200a; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c10301; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193f0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10618004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0108; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f8003; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08080; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fe040; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fe040; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008b0; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200b; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c50301; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516000; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1061c004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fc002; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa080c0; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4080; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4080; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008e0; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200e; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c10205; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516001; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193b8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1061a004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fa002; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0080; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0080; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008c0; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200c; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c18301; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193f8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fa003; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2080; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2080; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008d0; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200d; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c58301; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10602004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e8003; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2000; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2000; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48201; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ea002; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4000; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4000; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00301; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10604004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ea003; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x978380; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6000; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6000; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c40301; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400a; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19380030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10608004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ee002; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9783c0; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fc000; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fc000; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00205; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400b; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10606004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ec002; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f8000; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f8000; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08301; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ec003; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fa000; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fa000; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48301; +} + +static void +Opcode_ae_la24_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073e004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e2003; +} + +static void +Opcode_ae_la24_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c4830a; +} + +static void +Opcode_ae_la24_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e4002; +} + +static void +Opcode_ae_la24_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0830b; +} + +static void +Opcode_ae_la24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073e008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e4003; +} + +static void +Opcode_ae_la24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c4830b; +} + +static void +Opcode_ae_la24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e8002; +} + +static void +Opcode_ae_la24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08201; +} + +static void +Opcode_ae_la24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073e00c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e6002; +} + +static void +Opcode_ae_la24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00201; +} + +static void +Opcode_ae_la24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e6003; +} + +static void +Opcode_ae_la24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c40201; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073c004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104dc003; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c4820b; +} + +static void +Opcode_ae_la24x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d870080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104de002; +} + +static void +Opcode_ae_la24x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08308; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d878080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073c008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104de003; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48308; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e2002; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0830a; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d870090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073c00c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e0002; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08309; +} + +static void +Opcode_ae_la24x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d878090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e0003; +} + +static void +Opcode_ae_la24x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48309; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a2004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ee001; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a60; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000d; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f0001; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a70; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000e; +} + +static void +Opcode_ae_sa32x2_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a2008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f2001; +} + +static void +Opcode_ae_sa32x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a80; +} + +static void +Opcode_ae_sa32x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000f; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a200c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f4001; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a90; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010c; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19038010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a6004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fa001; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00ac0; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010f; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f6001; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00aa0; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010d; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f8001; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00ab0; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010e; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10620004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fe002; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008f0; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0000; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fe003; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a00; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0001; +} + +static void +Opcode_ae_sa16x4_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10622004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0001; +} + +static void +Opcode_ae_sa16x4_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a10; +} + +static void +Opcode_ae_sa16x4_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0002; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10624004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c2001; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a20; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0003; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10628004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c8001; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a50; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0102; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10626004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c4001; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a30; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0100; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c6001; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a40; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0101; +} + +static void +Opcode_ae_sa8x8_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19078010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a6008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fc001; +} + +static void +Opcode_ae_sa8x8_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00ad0; +} + +static void +Opcode_ae_sa8x8_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0200; +} + +static void +Opcode_ae_sa8x8_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190b8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fe001; +} + +static void +Opcode_ae_sa8x8_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00ae0; +} + +static void +Opcode_ae_sa8x8_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0201; +} + +static void +Opcode_ae_sa8x8_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190f8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a600c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0000; +} + +static void +Opcode_ae_sa8x8_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00af0; +} + +static void +Opcode_ae_sa8x8_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0202; +} + +static void +Opcode_ae_sa8x8_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19138010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0001; +} + +static void +Opcode_ae_sa8x8_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00c00; +} + +static void +Opcode_ae_sa8x8_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0203; +} + +static void +Opcode_ae_sa8x8_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191f8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2000; +} + +static void +Opcode_ae_sa8x8_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00c30; +} + +static void +Opcode_ae_sa8x8_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0302; +} + +static void +Opcode_ae_sa8x8_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19178010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0002; +} + +static void +Opcode_ae_sa8x8_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00c10; +} + +static void +Opcode_ae_sa8x8_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0300; +} + +static void +Opcode_ae_sa8x8_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191b8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0003; +} + +static void +Opcode_ae_sa8x8_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00c20; +} + +static void +Opcode_ae_sa8x8_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0301; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063a004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e2001; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000b; +} + +static void +Opcode_ae_sa32x2f24_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e4001; +} + +static void +Opcode_ae_sa32x2f24_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0108; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063c004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e6001; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0109; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ec001; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000c; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063e004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e8001; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010a; +} + +static void +Opcode_ae_sa32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ea001; +} + +static void +Opcode_ae_sa32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010b; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530070; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10632004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d6001; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0105; +} + +static void +Opcode_ae_sa24_l_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538070; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d8001; +} + +static void +Opcode_ae_sa24_l_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0106; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10634004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104da001; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0107; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10638004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e0001; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000a; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10636004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104dc001; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0008; +} + +static void +Opcode_ae_sa24_l_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104de001; +} + +static void +Opcode_ae_sa24_l_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0009; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530040; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1062a004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ca001; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0103; +} + +static void +Opcode_ae_sa24x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538040; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104cc001; +} + +static void +Opcode_ae_sa24x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0004; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530050; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1062c004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ce001; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0005; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538060; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10630004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d4001; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0104; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538050; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1062e004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d0001; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0006; +} + +static void +Opcode_ae_sa24x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530060; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d2001; +} + +static void +Opcode_ae_sa24x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0007; +} + +static void +Opcode_ae_addicirc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a00f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addicirc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e04000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addicirc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9838c00; +} + +static void +Opcode_ae_addicirc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1520000; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a12f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6200; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7200; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a5400; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1523200; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a0af00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6100; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7100; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a7000; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1523100; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a02f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6000; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7000; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a5000; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1523000; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18800f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481900; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983c400; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18840f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481b00; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983e400; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18880f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481c00; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9838800; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18940f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481f00; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983e800; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188c0f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481e00; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983a800; +} + +static void +Opcode_ae_s32ra64s_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18900f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481d00; +} + +static void +Opcode_ae_s32ra64s_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983c800; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18780f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481400; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9838000; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18781f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481600; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983a000; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187c0b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481500; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983c000; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187c1f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481a00; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983a400; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187c0f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481700; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983e000; +} + +static void +Opcode_ae_s24ra64s_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187c1b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481800; +} + +static void +Opcode_ae_s24ra64s_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9838400; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0004; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830203; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0008; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830302; +} + +static void +Opcode_ae_s16x4ra32s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4ra32s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4ra32s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0000; +} + +static void +Opcode_ae_s16x4ra32s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830202; +} + +static void +Opcode_ae_addbrba32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74fa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addbrba32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1efa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addbrba32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1be000; +} + +static void +Opcode_ae_addbrba32_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e4000; +} + +static void +Opcode_ae_addbrba32_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b5000; +} + +static void +Opcode_ae_addbrba32_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa02000; +} + +static void +Opcode_ae_addbrba32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9921004; +} + +static void +Opcode_ae_addbrba32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1553000; +} + +static void +Opcode_ae_s32x2_l_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340000; +} + +static void +Opcode_ae_bitswap_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191fd030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bitswap_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0d002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bitswap_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9002; +} + +static void +Opcode_ae_bitswap_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a5000; +} + +static void +Opcode_ae_bitswap_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1597004; +} + +static void +Opcode_ae_mul32js_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32js_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80211420; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32js_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x560020; +} + +static void +Opcode_ae_mul32js_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40b00a1; +} + +static void +Opcode_ae_mul32js_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x510020; +} + +static void +Opcode_ae_mul32js_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c0008; +} + +static void +Opcode_ae_mul32js_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700220; +} + +static void +Opcode_ae_mul32js_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a800; +} + +static void +Opcode_ae_mul32js_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130040; +} + +static void +Opcode_ae_mul32js_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00d0; +} + +static void +Opcode_ae_mul32js_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2c0000; +} + +static void +Opcode_ae_mul32js_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8009e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsub32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsub32s_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000020; +} + +static void +Opcode_ae_addandsub32s_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsub32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9400000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5400000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000026; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsub32js_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsub32js_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_addandsub32js_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; +} + +static void +Opcode_ae_addandsub32js_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_addandsub32js_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_addandsub32js_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsub32js_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8400800; +} + +static void +Opcode_ae_addandsub32js_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5300000; +} + +static void +Opcode_ae_addandsub32js_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000025; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000040; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9400800; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5500000; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000027; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000060; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa400000; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5600000; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000028; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000080; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa400800; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5700000; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000029; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addrng32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007860; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subrng32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rng32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40069c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel16i_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82050000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_sel16i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sel16i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_sel16i_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000a0; +} + +static void +Opcode_ae_sel16i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200000; +} + +static void +Opcode_ae_sel16i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700000; +} + +static void +Opcode_ae_sel16i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_sel16i_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c050000; +} + +static void +Opcode_ae_sel16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7420000; +} + +static void +Opcode_ae_sel16i_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40080002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel16i_n_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_sel16i_n_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_sel16i_n_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00380; +} + +static void +Opcode_ae_shortswap_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401d1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movab4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af007; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movab4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a7010; +} + +static void +Opcode_ae_movab2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af006; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movab2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a7000; +} + +static void +Opcode_ae_movab_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movab_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a3002; +} + +static void +Opcode_ae_movba_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movba_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a3001; +} + +static void +Opcode_ae_movba1x2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movba1x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa820000; +} + +static void +Opcode_ae_movba4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af009; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movba4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa862004; +} + +static void +Opcode_ae_movba2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movba2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa822004; +} + +static void +Opcode_ae_movb2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af016; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movb4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af027; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192c0033; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt16x4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt16x4_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132c400; +} + +static void +Opcode_ae_movt16x4_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x124400; +} + +static void +Opcode_ae_movt16x4_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00221; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9832021; +} + +static void +Opcode_ae_movf16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192c0031; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf16x4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf16x4_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132c000; +} + +static void +Opcode_ae_movf16x4_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x124000; +} + +static void +Opcode_ae_movf16x4_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00201; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830021; +} + +static void +Opcode_ae_movt32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800f1; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt32x2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10720010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt32x2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132a000; +} + +static void +Opcode_ae_movt32x2_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120400; +} + +static void +Opcode_ae_movt32x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00021; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7468011; +} + +static void +Opcode_ae_movf32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf32x2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10720000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf32x2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1328000; +} + +static void +Opcode_ae_movf32x2_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ae_movf32x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7468001; +} + +static void +Opcode_ae_movsara7x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9969e04; +} + +static void +Opcode_ae_movsara7x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1523300; +} + +static void +Opcode_ae_movsard7_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19140026; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movsard7_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c401; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movsard7_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058a0c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movsard7_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069e030; +} + +static void +Opcode_ae_movsard7_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8a6004; +} + +static void +Opcode_ae_movasar_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19036310; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movasar_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c602; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movasar_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e19e0; +} + +static void +Opcode_ae_movda32x2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198000; +} + +static void +Opcode_ae_movda32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a79000; +} + +static void +Opcode_ae_movda32x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154a000; +} + +static void +Opcode_ae_movda32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7528003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00801; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107820e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0300; +} + +static void +Opcode_ae_movda32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640650; +} + +static void +Opcode_ae_movda32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e1080; +} + +static void +Opcode_ae_movda32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516004; +} + +static void +Opcode_ae_movda16x2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640400; +} + +static void +Opcode_ae_movda16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7526003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda16_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0310e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107800e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda16_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0203; +} + +static void +Opcode_ae_movda16_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640640; +} + +static void +Opcode_ae_movda16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e1060; +} + +static void +Opcode_ae_movda16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d6003; +} + +static void +Opcode_ae_movi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d836080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa00c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000c; +} + +static void +Opcode_ae_movi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640600; +} + +static void +Opcode_ae_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a1000; +} + +static void +Opcode_ae_movi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1554004; +} + +static void +Opcode_ae_movi_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa400024; +} + +static void +Opcode_ae_movi_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44100003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74b4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198100; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a71004; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158a000; +} + +static void +Opcode_ae_sat16x4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000a0; +} + +static void +Opcode_ae_sat16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000026; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03904; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98320e0; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40189002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000022; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03804; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107800c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98300e0; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40181002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19080026; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00802; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9836061; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800026; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401c9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19080022; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107800a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9836021; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800025; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401c1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvta32f24s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191ac030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32f24s_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e4b400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32f24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01708; +} + +static void +Opcode_ae_cvta32f24s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191a6030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32f24s_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e43400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32f24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01308; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1053e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640300; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a71000; +} + +static void +Opcode_ae_cvtp24a16x2_lh_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640100; +} + +static void +Opcode_ae_cvtp24a16x2_hl_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640200; +} + +static void +Opcode_ae_cvtp24a16x2_hh_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640000; +} + +static void +Opcode_ae_truncp24q48x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40098c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d180000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580000; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81a0300; +} + +static void +Opcode_ae_trunci32x2f64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c280000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunci32x2f64s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10202000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunci32x2f64s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x804000; +} + +static void +Opcode_ae_trunci32x2f64s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1680000; +} + +static void +Opcode_ae_trunca32f64s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d100000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca32f64s_l_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_trunca32f64s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81a0200; +} + +static void +Opcode_ae_trunci32f64s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c200000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunci32f64s_l_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600000; +} + +static void +Opcode_ae_truncp16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401d9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round32x2f64ssym_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80f0000; +} + +static void +Opcode_ae_round32x2f64ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round32x2f64sasym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280400; +} + +static void +Opcode_ae_round32x2f64sasym_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80e8000; +} + +static void +Opcode_ae_round32x2f64sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round32x2f48ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round32x2f48sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round16x4f32ssym_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800090; +} + +static void +Opcode_ae_round16x4f32ssym_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80e0000; +} + +static void +Opcode_ae_round16x4f32ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round16x4f32sasym_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104b0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_round16x4f32sasym_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800080; +} + +static void +Opcode_ae_round16x4f32sasym_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80d8000; +} + +static void +Opcode_ae_round16x4f32sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round24x2f48ssym_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104b8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_round24x2f48ssym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280000; +} + +static void +Opcode_ae_round24x2f48ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round24x2f48sasym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180e00; +} + +static void +Opcode_ae_round24x2f48sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsp16q48x2sym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsp16q48x2asym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_minabs32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_maxabs32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsp16f24sym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80106862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsp16f24asym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mov_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800f; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mov_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160011; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mov_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1904002e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mov_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03b06; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mov_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80f11801; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mov_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780060; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mov_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c010c; +} + +static void +Opcode_ae_mov_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x568000; +} + +static void +Opcode_ae_mov_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40b80a0; +} + +static void +Opcode_ae_mov_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c0000; +} + +static void +Opcode_ae_mov_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020f; +} + +static void +Opcode_ae_mov_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133ac00; +} + +static void +Opcode_ae_mov_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08100; +} + +static void +Opcode_ae_mov_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x124800; +} + +static void +Opcode_ae_mov_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000020; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mov_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00540; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mov_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000800; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mov_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2880080; +} + +static void +Opcode_ae_mov_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x229860; +} + +static void +Opcode_ae_mov_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25402e0; +} + +static void +Opcode_ae_mov_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00361; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mov_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d15801d; +} + +static void +Opcode_ae_mov_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98340e1; +} + +static void +Opcode_ae_mov_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800024; +} + +static void +Opcode_ae_mov_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401b9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movt64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt64_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1324000; +} + +static void +Opcode_ae_movt64_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c000; +} + +static void +Opcode_ae_movt64_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8b00201; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742a001; +} + +static void +Opcode_ae_movf64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf64_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1320000; +} + +static void +Opcode_ae_movf64_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118000; +} + +static void +Opcode_ae_movf64_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8b00001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7428001; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7524003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0310c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0202; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e1040; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1596003; +} + +static void +Opcode_ae_cvt48a32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48a32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03108; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48a32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0200; +} + +static void +Opcode_ae_cvt48a32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e1000; +} + +static void +Opcode_ae_cvt48a32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516003; +} + +static void +Opcode_ae_cvt64a32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7522003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt64a32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0310a; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt64a32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0201; +} + +static void +Opcode_ae_cvt64a32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e1020; +} + +static void +Opcode_ae_cvt64a32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556003; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1904002a; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03a06; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98340a1; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401b1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19040026; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03906; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9834061; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401a9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19040022; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03806; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9834021; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401a1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900002e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03b04; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98360e0; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40199002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900002a; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03a04; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98340e0; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40191002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat48s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa158000; +} + +static void +Opcode_ae_sat48s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800f6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_satq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800fe462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800ee462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_truncq32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98360a1; +} + +static void +Opcode_ae_truncq32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401e1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_minabs64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_maxabs64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsq32f48sym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80306862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsq32f48asym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80206862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_trunca32q48_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191f4030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca32q48_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0cc01; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929604; +} + +static void +Opcode_ae_movad32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191e4030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e7b400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a006; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_l_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf000; +} + +static void +Opcode_ae_movad32_l_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069a030; +} + +static void +Opcode_ae_movad32_l_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2986010; +} + +static void +Opcode_ae_movad32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09f08; +} + +static void +Opcode_ae_movad32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191be030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e73400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_h_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_h_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10698030; +} + +static void +Opcode_ae_movad32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09b08; +} + +static void +Opcode_ae_movad16_3_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191bc030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_3_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6b400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_3_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_3_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10696030; +} + +static void +Opcode_ae_movad16_3_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09708; +} + +static void +Opcode_ae_movad16_2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191b6030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e63400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071800f; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10694030; +} + +static void +Opcode_ae_movad16_2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09308; +} + +static void +Opcode_ae_movad16_1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191b4030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e5b400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071800e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10692030; +} + +static void +Opcode_ae_movad16_1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01f08; +} + +static void +Opcode_ae_movad16_0_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191ae030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_0_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e53400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_0_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071800b; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_0_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690030; +} + +static void +Opcode_ae_movad16_0_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2946010; +} + +static void +Opcode_ae_movad16_0_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01b08; +} + +static void +Opcode_ae_sra64_32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d818000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sra64_32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1000; +} + +static void +Opcode_ae_pksr32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19340032; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6340c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr32_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x55a000; +} + +static void +Opcode_ae_pksr32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c008c; +} + +static void +Opcode_ae_pksr32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17401e0; +} + +static void +Opcode_ae_pksr32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338000; +} + +static void +Opcode_ae_pksr32_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128008; +} + +static void +Opcode_ae_pksr32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830060; +} + +static void +Opcode_ae_pksr32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa200024; +} + +static void +Opcode_ae_pksr24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19340031; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr24_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6320c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr24_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x559000; +} + +static void +Opcode_ae_pksr24_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c001c; +} + +static void +Opcode_ae_pksr24_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17201e0; +} + +static void +Opcode_ae_pksr24_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132e400; +} + +static void +Opcode_ae_pksr24_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128004; +} + +static void +Opcode_ae_pksr24_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa100024; +} + +static void +Opcode_ae_pksrf32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19340033; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksrf32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6360c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksrf32_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x55b000; +} + +static void +Opcode_ae_pksrf32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c009c; +} + +static void +Opcode_ae_pksrf32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17601e0; +} + +static void +Opcode_ae_pksrf32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338400; +} + +static void +Opcode_ae_pksrf32_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12800c; +} + +static void +Opcode_ae_pksrf32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98300a0; +} + +static void +Opcode_ae_pksrf32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa300024; +} + +static void +Opcode_ae_pksr16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19340030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6300c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr16_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x558000; +} + +static void +Opcode_ae_pksr16_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c000c; +} + +static void +Opcode_ae_pksr16_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17001e0; +} + +static void +Opcode_ae_pksr16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132e000; +} + +static void +Opcode_ae_pksr16_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128000; +} + +static void +Opcode_ae_pksr16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830020; +} + +static void +Opcode_ae_pksr16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000024; +} + +static void +Opcode_ae_trunca16p24s_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a00b; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929204; +} + +static void +Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929c04; +} + +static void +Opcode_ae_add32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480000; +} + +static void +Opcode_ae_add32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89a0c00; +} + +static void +Opcode_ae_add32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8038000; +} + +static void +Opcode_ae_add32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005c60; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18500b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280600; +} + +static void +Opcode_ae_sub32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8110000; +} + +static void +Opcode_ae_sub32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addsub32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18100b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addsub32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080200; +} + +static void +Opcode_ae_addsub32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8070000; +} + +static void +Opcode_ae_addsub32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subadd32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18680b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subadd32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380c00; +} + +static void +Opcode_ae_subadd32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8130000; +} + +static void +Opcode_ae_subadd32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88a0800; +} + +static void +Opcode_ae_add16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8020000; +} + +static void +Opcode_ae_add16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18400f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280800; +} + +static void +Opcode_ae_sub16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80f8000; +} + +static void +Opcode_ae_sub16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ba0800; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8050000; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006860; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addsub32_hl_lh_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18180f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addsub32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8088000; +} + +static void +Opcode_ae_addsub32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f30; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0220; +} + +static void +Opcode_ae_neg32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2d8000; +} + +static void +Opcode_ae_neg32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800b6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f60; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0060; +} + +static void +Opcode_ae_abs32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3e8000; +} + +static void +Opcode_ae_abs32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8003e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg32_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2e8000; +} + +static void +Opcode_ae_neg32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800c6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89a0800; +} + +static void +Opcode_ae_add24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8030000; +} + +static void +Opcode_ae_add24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005860; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18480f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280200; +} + +static void +Opcode_ae_sub24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8108000; +} + +static void +Opcode_ae_sub24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10498000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add32s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480400; +} + +static void +Opcode_ae_add32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002400; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_add32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8aa0800; +} + +static void +Opcode_ae_add32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8040000; +} + +static void +Opcode_ae_add32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18500f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_sub32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280a00; +} + +static void +Opcode_ae_sub32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8118000; +} + +static void +Opcode_ae_sub32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addsub32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18100f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addsub32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080600; +} + +static void +Opcode_ae_addsub32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8078000; +} + +static void +Opcode_ae_addsub32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subadd32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18680f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subadd32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380200; +} + +static void +Opcode_ae_subadd32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8138000; +} + +static void +Opcode_ae_subadd32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004062; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10490000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add16s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_add16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88a0c00; +} + +static void +Opcode_ae_add16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8028000; +} + +static void +Opcode_ae_add16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005460; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18480b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub16s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002c00; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_sub16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280c00; +} + +static void +Opcode_ae_sub16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8100000; +} + +static void +Opcode_ae_sub16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002062; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8aa0c00; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8048000; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006460; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addsub32s_hl_lh_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18180b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addsub32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8080000; +} + +static void +Opcode_ae_addsub32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f20; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg24s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107380f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0200; +} + +static void +Opcode_ae_neg24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2d0000; +} + +static void +Opcode_ae_neg24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800ae462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f50; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs24s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738050; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0040; +} + +static void +Opcode_ae_abs24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3c8000; +} + +static void +Opcode_ae_abs24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80036462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f40; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780040; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003860; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_neg32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0240; +} + +static void +Opcode_ae_neg32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2e0000; +} + +static void +Opcode_ae_neg32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800be462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f70; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107380d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003c00; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_abs32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0080; +} + +static void +Opcode_ae_abs32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa390000; +} + +static void +Opcode_ae_abs32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80046462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f10; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107380b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg16s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003c40; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_neg16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00f0; +} + +static void +Opcode_ae_neg16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2c8000; +} + +static void +Opcode_ae_neg16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800a6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f40; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs16s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80211400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs16s_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x560000; +} + +static void +Opcode_ae_abs16s_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40b00a0; +} + +static void +Opcode_ae_abs16s_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x510000; +} + +static void +Opcode_ae_abs16s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003800; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_abs16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0020; +} + +static void +Opcode_ae_abs16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3a8000; +} + +static void +Opcode_ae_abs16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8002e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f30; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0000; +} + +static void +Opcode_ae_abs16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa388000; +} + +static void +Opcode_ae_abs16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80026462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16js_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc16js_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b001c0; +} + +static void +Opcode_ae_mulc16js_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16js_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc16js_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b001e0; +} + +static void +Opcode_ae_mulc16js_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16js_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac16js_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f003c0; +} + +static void +Opcode_ae_mulac16js_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16js_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac16js_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f003e0; +} + +static void +Opcode_ae_mulac16js_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_lt16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880009; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340014; +} + +static void +Opcode_ae_lt16_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400e0; +} + +static void +Opcode_ae_lt16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2a00; +} + +static void +Opcode_ae_le16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880205; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10749300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1348013; +} + +static void +Opcode_ae_le16_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25403c0; +} + +static void +Opcode_ae_le16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022e00; +} + +static void +Opcode_ae_eq16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880005; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10749100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340013; +} + +static void +Opcode_ae_eq16_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25401c0; +} + +static void +Opcode_ae_eq16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022a00; +} + +static void +Opcode_ae_lt32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10749000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340012; +} + +static void +Opcode_ae_lt32_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400c0; +} + +static void +Opcode_ae_lt32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022800; +} + +static void +Opcode_ae_le32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d88010e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10741100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340011; +} + +static void +Opcode_ae_le32_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25001e0; +} + +static void +Opcode_ae_le32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022400; +} + +static void +Opcode_ae_eq32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d88000e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10741000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340010; +} + +static void +Opcode_ae_eq32_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000e0; +} + +static void +Opcode_ae_eq32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022000; +} + +static void +Opcode_ae_min32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18300f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0110080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104a8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min32_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ae_min32_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40a00a0; +} + +static void +Opcode_ae_min32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180c00; +} + +static void +Opcode_ae_min32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80b0000; +} + +static void +Opcode_ae_min32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_max32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18200f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0110020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max32_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x528000; +} + +static void +Opcode_ae_max32_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40880a0; +} + +static void +Opcode_ae_max32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080e00; +} + +static void +Opcode_ae_max32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8098000; +} + +static void +Opcode_ae_max32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_minmax32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80c8000; +} + +static void +Opcode_ae_minmax32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_minmax16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80c0000; +} + +static void +Opcode_ae_minmax16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_min16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18300b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0110060; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min16_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x538000; +} + +static void +Opcode_ae_min16_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40980a0; +} + +static void +Opcode_ae_min16_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x508000; +} + +static void +Opcode_ae_min16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180800; +} + +static void +Opcode_ae_min16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a8000; +} + +static void +Opcode_ae_min16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_max16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18200b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0110000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max16_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x520000; +} + +static void +Opcode_ae_max16_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40800a0; +} + +static void +Opcode_ae_max16_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_max16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080a00; +} + +static void +Opcode_ae_max16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8090000; +} + +static void +Opcode_ae_max16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ba0c00; +} + +static void +Opcode_ae_add64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8058000; +} + +static void +Opcode_ae_add64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006c60; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18580b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280e00; +} + +static void +Opcode_ae_sub64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8120000; +} + +static void +Opcode_ae_sub64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003062; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f50; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0260; +} + +static void +Opcode_ae_neg64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2f0000; +} + +static void +Opcode_ae_neg64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800ce462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f80; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00a0; +} + +static void +Opcode_ae_abs64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa398000; +} + +static void +Opcode_ae_abs64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8004e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addsq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18080f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addsq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080c00; +} + +static void +Opcode_ae_addsq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8068000; +} + +static void +Opcode_ae_addsq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007c60; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subsq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18700b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subsq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380600; +} + +static void +Opcode_ae_subsq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8140000; +} + +static void +Opcode_ae_subsq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080000; +} + +static void +Opcode_ae_add64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8060000; +} + +static void +Opcode_ae_add64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18580f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380000; +} + +static void +Opcode_ae_sub64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8128000; +} + +static void +Opcode_ae_sub64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_negsq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f80; + slotbuf[1] = 0; +} + +static void +Opcode_ae_negsq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a02c0; +} + +static void +Opcode_ae_negsq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa058000; +} + +static void +Opcode_ae_negsq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800e6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abssq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80fc0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0030; +} + +static void +Opcode_ae_abssq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3b8000; +} + +static void +Opcode_ae_abssq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80066462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f60; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0280; +} + +static void +Opcode_ae_neg64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2f8000; +} + +static void +Opcode_ae_neg64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800d6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00c0; +} + +static void +Opcode_ae_abs64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3b0000; +} + +static void +Opcode_ae_abs64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80056462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_and_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_and_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7428000; +} + +static void +Opcode_ae_and_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40080c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_nand_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nand_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742a000; +} + +static void +Opcode_ae_nand_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40088c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_or_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880040; + slotbuf[1] = 0; +} + +static void +Opcode_ae_or_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742c000; +} + +static void +Opcode_ae_or_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40090c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_xor_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880050; + slotbuf[1] = 0; +} + +static void +Opcode_ae_xor_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742e000; +} + +static void +Opcode_ae_xor_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400a0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slai24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c800000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8424003; +} + +static void +Opcode_ae_slai24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40006003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srli24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c810000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srli24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842400b; +} + +static void +Opcode_ae_srli24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c808000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8424007; +} + +static void +Opcode_ae_srai24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40007403; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19238010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c18205; +} + +static void +Opcode_ae_slas24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42080c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srls24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193b8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srls24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04308; +} + +static void +Opcode_ae_srls24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420e0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sras24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19338010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sras24_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500d01; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sras24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c18305; +} + +static void +Opcode_ae_sras24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420c0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c820000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1204; +} + +static void +Opcode_ae_srai16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42080803; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai16r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c822000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai16r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1304; +} + +static void +Opcode_ae_srai16r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slai32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c804000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842c003; +} + +static void +Opcode_ae_slai32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40006803; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srli32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c812000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srli32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842600b; +} + +static void +Opcode_ae_srli32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000403; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8426007; +} + +static void +Opcode_ae_srai32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40007803; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai32r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842c007; +} + +static void +Opcode_ae_srai32r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40007c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1923c010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1c205; +} + +static void +Opcode_ae_slas32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42090c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srls32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193ba010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srls32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c06308; +} + +static void +Opcode_ae_srls32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420e8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sras32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1933a010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sras32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1a305; +} + +static void +Opcode_ae_sras32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420c8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaa32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d814000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8208; +} + +static void +Opcode_ae_srla32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c828000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1008; +} + +static void +Opcode_ae_sraa32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1200; +} + +static void +Opcode_ae_slai16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c81e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a830c; +} + +static void +Opcode_ae_slai16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000803; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaa16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c816000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8108; +} + +static void +Opcode_ae_sraa16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d81c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9000; +} + +static void +Opcode_ae_sraa16rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d81a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa16rs_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa16rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1100; +} + +static void +Opcode_ae_slai24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c802000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8426003; +} + +static void +Opcode_ae_slai24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40006403; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1923a010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas24s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1a205; +} + +static void +Opcode_ae_slas24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42088c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slai32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c806000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842e003; +} + +static void +Opcode_ae_slai32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40006c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1923e010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1e205; +} + +static void +Opcode_ae_slas32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42098c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaa32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d816000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8308; +} + +static void +Opcode_ae_sraa32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x748c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9200; +} + +static void +Opcode_ae_sraa32rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa32rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1300; +} + +static void +Opcode_ae_slasq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192bc010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c14305; +} + +static void +Opcode_ae_slasq56_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420b0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srlsq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193be010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c06309; +} + +static void +Opcode_ae_srlsq56_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420f8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srasq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1933e010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1e305; +} + +static void +Opcode_ae_srasq56_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420d8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaaq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c818000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaaq56_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a020c; +} + +static void +Opcode_ae_srlaq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c82e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9108; +} + +static void +Opcode_ae_sraaq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x758e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraaq56_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9104; +} + +static void +Opcode_ae_slai64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a0000; +} + +static void +Opcode_ae_slai64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srli64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7408000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srli64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a0008; +} + +static void +Opcode_ae_srli64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40004003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7406000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8004; +} + +static void +Opcode_ae_srai64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4001a003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192b8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c10305; +} + +static void +Opcode_ae_slas64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420a0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srls64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193bc010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srls64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04309; +} + +static void +Opcode_ae_srls64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420f0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sras64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1933c010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sras64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1c305; +} + +static void +Opcode_ae_sras64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420d0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaa64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a000c; +} + +static void +Opcode_ae_srla64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c82a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1108; +} + +static void +Opcode_ae_sraa64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1004; +} + +static void +Opcode_ae_slaisq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7404000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a0004; +} + +static void +Opcode_ae_slaisq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40012003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slassq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192be010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slassq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c16305; +} + +static void +Opcode_ae_slassq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420b8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaasq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c81a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaasq56s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a030c; +} + +static void +Opcode_ae_slai64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7402000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8000; +} + +static void +Opcode_ae_slai64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000a003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192ba010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c12305; +} + +static void +Opcode_ae_slas64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420a8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaa64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x748a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a010c; +} + +static void +Opcode_ae_lt64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt64_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1310000; +} + +static void +Opcode_ae_lt64_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000c0; +} + +static void +Opcode_ae_lt64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6202000; +} + +static void +Opcode_ae_le64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le64_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300010; +} + +static void +Opcode_ae_le64_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000a0; +} + +static void +Opcode_ae_le64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6102000; +} + +static void +Opcode_ae_eq64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq64_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ae_eq64_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500080; +} + +static void +Opcode_ae_eq64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002000; +} + +static void +Opcode_ae_max64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18280b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180000; +} + +static void +Opcode_ae_max64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_min64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18380b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180200; +} + +static void +Opcode_ae_min64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_nsa64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191e6030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsa64_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0c001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsa64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929004; +} + +static void +Opcode_ae_nsaz16_0_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191ec030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz16_0_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0c401; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz16_0_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a007; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz16_0_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929404; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191ee030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0c801; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a00a; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929804; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca004800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200280; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d001a0; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce001c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100140; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72001a0; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002a0; +} + +static void +Opcode_ae_mul32_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00260; +} + +static void +Opcode_ae_mul32_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88d00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8001c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000e0; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71001c0; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32ra_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca001800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32ra_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70001e0; +} + +static void +Opcode_ae_mulf32ra_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8004800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200260; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d00180; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc001c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100120; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7200180; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00280; +} + +static void +Opcode_ae_mul32_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00240; +} + +static void +Opcode_ae_mul32_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ec00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce001800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000c0; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71001a0; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32ra_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8001800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32ra_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70001c0; +} + +static void +Opcode_ae_mulf32ra_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce004400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200240; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c001e0; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca001c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100100; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71001e0; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00260; +} + +static void +Opcode_ae_mul32_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00220; +} + +static void +Opcode_ae_mul32_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8cc00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc001800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000a0; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7100180; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32ra_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce001400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32ra_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70001a0; +} + +static void +Opcode_ae_mulf32ra_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000240; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68001a0; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8bf00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00160; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7900160; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f500040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6003400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000e0; +} + +static void +Opcode_ae_mula32_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f000a0; +} + +static void +Opcode_ae_mula32_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00100; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7600160; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89500040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32ra_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32ra_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7300160; +} + +static void +Opcode_ae_mulaf32ra_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000220; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800180; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89f00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00140; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7800160; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d500040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6003000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000c0; +} + +static void +Opcode_ae_mula32_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00080; +} + +static void +Opcode_ae_mula32_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000e0; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7500160; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32ra_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32ra_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7200160; +} + +static void +Opcode_ae_mulaf32ra_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000200; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67001e0; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8fe00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00120; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7700160; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b500040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6002c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000a0; +} + +static void +Opcode_ae_mula32_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00060; +} + +static void +Opcode_ae_mula32_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000c0; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400160; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32ra_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32ra_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7100160; +} + +static void +Opcode_ae_mulaf32ra_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f300040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14002a0; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400280; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc006800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300240; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200220; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca005800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300080; +} + +static void +Opcode_ae_muls32_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60002a0; +} + +static void +Opcode_ae_muls32_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce006400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13001e0; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61003c0; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32ra_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8006400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32ra_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100360; +} + +static void +Opcode_ae_mulsf32ra_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400280; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400260; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca006800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300220; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200200; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8005800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300060; +} + +static void +Opcode_ae_muls32_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000280; +} + +static void +Opcode_ae_muls32_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc006400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13001c0; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61003a0; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32ra_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32ra_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100340; +} + +static void +Opcode_ae_mulsf32ra_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400260; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400240; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8006800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300200; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61003e0; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce005400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300040; +} + +static void +Opcode_ae_muls32_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000260; +} + +static void +Opcode_ae_muls32_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca006400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13001a0; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100380; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32ra_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32ra_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100320; +} + +static void +Opcode_ae_mulsf32ra_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32u_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32u_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00140; +} + +static void +Opcode_ae_mul32u_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00100; +} + +static void +Opcode_ae_mula32u_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32u_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00380; +} + +static void +Opcode_ae_mula32u_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00340; +} + +static void +Opcode_ae_muls32u_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc004c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32u_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200320; +} + +static void +Opcode_ae_muls32u_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e001c0; +} + +static void +Opcode_ae_mulf16ss_33_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000180; +} + +static void +Opcode_ae_mulf16ss_33_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f00180; +} + +static void +Opcode_ae_mulf16ss_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f001e0; +} + +static void +Opcode_ae_mulf16ss_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_21_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e001e0; +} + +static void +Opcode_ae_mulf16ss_21_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_31_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f001c0; +} + +static void +Opcode_ae_mulf16ss_31_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_30_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f001a0; +} + +static void +Opcode_ae_mulf16ss_30_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e00180; +} + +static void +Opcode_ae_mulf16ss_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_20_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e001c0; +} + +static void +Opcode_ae_mulf16ss_20_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_11_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e001a0; +} + +static void +Opcode_ae_mulf16ss_11_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc001400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100080; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d001e0; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_33_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100300; +} + +static void +Opcode_ae_mulsf16ss_33_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100280; +} + +static void +Opcode_ae_mulsf16ss_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61002e0; +} + +static void +Opcode_ae_mulsf16ss_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_21_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100260; +} + +static void +Opcode_ae_mulsf16ss_21_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_31_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61002c0; +} + +static void +Opcode_ae_mulsf16ss_31_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_30_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61002a0; +} + +static void +Opcode_ae_mulsf16ss_30_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100200; +} + +static void +Opcode_ae_mulsf16ss_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_20_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100240; +} + +static void +Opcode_ae_mulsf16ss_20_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_11_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100220; +} + +static void +Opcode_ae_mulsf16ss_11_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300180; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60003e0; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_33_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000160; +} + +static void +Opcode_ae_mulaf16ss_33_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d300040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c00160; +} + +static void +Opcode_ae_mulaf16ss_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d200040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f00160; +} + +static void +Opcode_ae_mulaf16ss_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b300040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_21_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b00160; +} + +static void +Opcode_ae_mulaf16ss_21_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b200040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_31_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e00160; +} + +static void +Opcode_ae_mulaf16ss_31_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89300040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_30_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d00160; +} + +static void +Opcode_ae_mulaf16ss_30_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f200040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800160; +} + +static void +Opcode_ae_mulaf16ss_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d100040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_20_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a00160; +} + +static void +Opcode_ae_mulaf16ss_20_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89200040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_11_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900160; +} + +static void +Opcode_ae_mulaf16ss_11_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f100040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000a0; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700160; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b100040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul16s_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul16s_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00080; +} + +static void +Opcode_ae_mul16s_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00040; +} + +static void +Opcode_ae_mul16s_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula16s_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula16s_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002c0; +} + +static void +Opcode_ae_mula16s_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00280; +} + +static void +Opcode_ae_mula16s_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ad00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls16s_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc004400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls16s_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200220; +} + +static void +Opcode_ae_muls16s_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c001c0; +} + +static void +Opcode_ae_muls16s_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6006c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002a0; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00260; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6006800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00280; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00240; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6006400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00260; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00220; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14003c0; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64003a0; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14003a0; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400380; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400380; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400360; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500280; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600260; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500260; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600240; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500240; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600220; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600380; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68003a0; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600360; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800380; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600340; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800360; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8002800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100260; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74001c0; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca002800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100280; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74001e0; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8004400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12001e0; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c00180; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca004400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200200; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c001a0; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00280; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60001c0; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002a0; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60001e0; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10001c0; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67001a0; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8be00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10001e0; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67001c0; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8de00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce007000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300360; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200340; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8007400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300380; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200360; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14001e0; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63003c0; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400200; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63003e0; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce003000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11003c0; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77001e0; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc003000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11003a0; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77001c0; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf003a0; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300180; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8da00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00380; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62001e0; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ba00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc007400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13003c0; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62003a0; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca007400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13003a0; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200380; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500320; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600300; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15002e0; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66002c0; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500200; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65003e0; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500340; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600320; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500300; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66002e0; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500220; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600200; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000e0; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67002c0; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000a0; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700280; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600060; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700240; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600100; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67002e0; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000c0; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67002a0; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600080; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700260; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16001e0; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800200; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16001c0; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67003e0; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16001a0; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67003c0; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700020; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900240; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003e0; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900200; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600300; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800320; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700040; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900260; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700000; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900220; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600320; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800340; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00340; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00300; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6007800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00300; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f002c0; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6005c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00220; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f001e0; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00360; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00320; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6007c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00320; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f002e0; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00240; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00200; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000360; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a001c0; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000320; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12600020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a00180; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10002e0; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69001c0; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000380; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a001e0; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000340; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12700020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a001a0; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000300; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69001e0; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc005c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300120; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000380; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca005c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300100; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12600040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000360; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8005c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000e0; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000340; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500060; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500240; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500020; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x169000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12700040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500200; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400340; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400320; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500080; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500260; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500040; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x169000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12600060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500220; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400360; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400340; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8002400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11001e0; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73001c0; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd001e0; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e001a0; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8cb00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca002400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100200; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73001e0; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00200; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e001c0; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8eb00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc002400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100220; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400180; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00220; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e001e0; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88c00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce002400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100240; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74001a0; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00240; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00200; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ac00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100160; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72001c0; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00160; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00120; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100180; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72001e0; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00180; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00140; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11001a0; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7300180; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd001a0; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00160; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ca00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11001c0; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73001a0; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd001c0; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00180; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ea00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00200; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e00160; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89700040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6001c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00020; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e003e0; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ef00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00220; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f00160; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b700040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00040; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00000; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00240; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000180; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d700040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6002400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00060; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00020; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00260; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60001a0; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f700040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6002800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00080; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00040; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00180; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a00160; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89600040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd003a0; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00360; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ee00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf001a0; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b00160; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b600040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6001000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd003c0; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00380; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88f00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf001c0; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c00160; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d600040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6001400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd003e0; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e003a0; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8af00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf001e0; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d00160; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f600040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6001800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e003c0; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8cf00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce006c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13002e0; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62002c0; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce005000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12003c0; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f001e0; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8007000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300300; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62002e0; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8005400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12003e0; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000200; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca007000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300320; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200300; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca005400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000220; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc007000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300340; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200320; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc005400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300020; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000240; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce006800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300260; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200240; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce004c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200340; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e001e0; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8006c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300280; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200260; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8005000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200360; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f00180; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca006c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13002a0; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200280; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca005000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200380; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f001a0; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc006c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13002c0; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62002a0; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc005000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12003a0; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f001c0; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe003e0; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f003a0; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6005800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00200; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f001c0; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe003a0; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00360; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6005000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe001c0; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00180; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10003c0; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b001a0; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10002c0; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69001a0; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10003a0; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b00180; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10002a0; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900180; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300160; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60003c0; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000320; +} + +static void +Opcode_ae_mulsad32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce005c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300140; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60003a0; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000300; +} + +static void +Opcode_ae_mulsad32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000c0; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65002a0; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400320; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400300; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000a0; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500280; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400300; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64002e0; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15003c0; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66003a0; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15001e0; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65003c0; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500380; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600360; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15001a0; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500380; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600140; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700320; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600040; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700220; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600120; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700300; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600020; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700200; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600220; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800240; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67003a0; +} + +static void +Opcode_ae_mulzsad32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600200; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800220; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700380; +} + +static void +Opcode_ae_mulzsad32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700080; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69002a0; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002e0; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800300; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700060; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900280; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002c0; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68002e0; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15003a0; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600380; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500360; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600340; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe003c0; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00380; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00380; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00340; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15001c0; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65003a0; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500180; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500360; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6005400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe001e0; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f001a0; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6004c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe001a0; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00160; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200160; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b00180; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc003400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200020; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78001c0; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8003400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11003e0; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7800180; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8003800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200060; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7900180; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200180; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b001a0; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce003400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200040; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78001e0; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca003400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78001a0; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca003800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200080; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x79001a0; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000140; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66001a0; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8dd00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63001e0; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8bb00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf003c0; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63001a0; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8fa00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000040; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64001a0; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8fb00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000160; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66001c0; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8fd00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000020; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400180; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8db00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf003e0; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63001c0; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89b00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000060; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64001c0; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89c00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400160; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300340; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca007800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400020; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300200; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce007400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13003e0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62003c0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce007800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400060; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300240; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400180; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300360; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc007800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400040; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300220; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8007800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62003e0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8007c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400080; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300260; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulp32x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp32x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12001a0; +} + +static void +Opcode_ae_mulp32x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b001c0; +} + +static void +Opcode_ae_mulp32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce003800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000c0; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x79001e0; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc003800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000a0; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x79001c0; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x2ts_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8003c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x2ts_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000e0; +} + +static void +Opcode_ae_mulfp32x2ts_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a00180; +} + +static void +Opcode_ae_mulp32x2t_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp32x2t_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12001c0; +} + +static void +Opcode_ae_mulp32x2t_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b001e0; +} + +static void +Opcode_ae_mulap32x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap32x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000180; +} + +static void +Opcode_ae_mulap32x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66001e0; +} + +static void +Opcode_ae_mulap32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89e00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000a0; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500180; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8dc00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000080; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64001e0; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8bc00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x2ts_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x2ts_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000c0; +} + +static void +Opcode_ae_mulafp32x2ts_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65001a0; +} + +static void +Opcode_ae_mulap32x2t_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap32x2t_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10001a0; +} + +static void +Opcode_ae_mulap32x2t_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700180; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14001a0; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300380; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc007c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000c0; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63002a0; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca007c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000a0; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300280; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x2ts_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce007c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x2ts_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000e0; +} + +static void +Opcode_ae_mulsfp32x2ts_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63002c0; +} + +static void +Opcode_ae_mulsp32x2t_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp32x2t_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14001c0; +} + +static void +Opcode_ae_mulsp32x2t_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63003a0; +} + +static void +Opcode_ae_mulfp16x4s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100380; +} + +static void +Opcode_ae_mulfp16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77001a0; +} + +static void +Opcode_ae_mulfp16x4ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76001e0; +} + +static void +Opcode_ae_mulc32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc001000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_mulc32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c001e0; +} + +static void +Opcode_ae_mulc32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce002800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11002a0; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75001a0; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8002c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x550000; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11002c0; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75001c0; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc32x16_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8001400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc32x16_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100040; +} + +static void +Opcode_ae_mulc32x16_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d001a0; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc002c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100300; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7600180; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc32x16_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce001000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc32x16_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100020; +} + +static void +Opcode_ae_mulc32x16_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d00180; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca002c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11002e0; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108000; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75001e0; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00020; +} + +static void +Opcode_ae_mulac32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300160; +} + +static void +Opcode_ae_mulac32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002c0; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61001a0; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002e0; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61001c0; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32x16_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac32x16_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00060; +} + +static void +Opcode_ae_mulac32x16_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500160; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00320; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200180; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32x16_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac32x16_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00040; +} + +static void +Opcode_ae_mulac32x16_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400160; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00300; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61001e0; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16x4ss_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16x4ss_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16x4ss_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul16x4s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_mul16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4100000; +} + +static void +Opcode_ae_mul16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4300000; +} + +static void +Opcode_ae_mula16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f00000; +} + +static void +Opcode_ae_muls16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul16x4_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mul16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; +} + +static void +Opcode_ae_mul16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4200000; +} + +static void +Opcode_ae_mula16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e00000; +} + +static void +Opcode_ae_muls16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfd32x2s_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2s_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2s_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2s_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2s_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2s_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulc16s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8001000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc16s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c001a0; +} + +static void +Opcode_ae_mulc16s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca001000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c001c0; +} + +static void +Opcode_ae_mulc16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac16s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100160; +} + +static void +Opcode_ae_mulac16s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200160; +} + +static void +Opcode_ae_mulac16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc16ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc002800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc16ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7500180; +} + +static void +Opcode_ae_mulfc16ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc16ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc16ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100180; +} + +static void +Opcode_ae_mulafc16ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul16js_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80ff0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul16js_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80096462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1910002e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133b000; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98360e1; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa00026; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40069462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19140022; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133b400; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18008000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x746a001; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa00027; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40069862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_conj16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_3_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_3_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_2_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_1_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_1_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_0_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_0_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafq16x2_fir_3_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_3_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_2_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_1_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_1_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_0_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_0_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzaaaafq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaafq32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaafq32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaafq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaafq32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaafq32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaaq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaaq32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaaq32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaaq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaaq32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaaq32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul16_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul16_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd000a0; +} + +static void +Opcode_ae_mul16_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00060; +} + +static void +Opcode_ae_mul16_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula16_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula16_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002e0; +} + +static void +Opcode_ae_mula16_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e002a0; +} + +static void +Opcode_ae_mula16_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8cd00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500120; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500300; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00140; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00100; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_div64d32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0090; +} + +static void +Opcode_ae_div64d32_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3f0000; +} + +static void +Opcode_ae_div64d32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80086462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_div64d32_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738070; + slotbuf[1] = 0; +} + +static void +Opcode_ae_div64d32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00b0; +} + +static void +Opcode_ae_div64d32_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3f8000; +} + +static void +Opcode_ae_div64d32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8008e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sha32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074cb00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl32t_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl16t_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10557000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl16c_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105872c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl16c_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10587ac0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl16c_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105876c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl16c_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d030; +} + +static void +Opcode_ae_vldsht_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afa0b; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a00f; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lb_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8010; +} + +static void +Opcode_ae_lb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a3001; +} + +static void +Opcode_ae_lb_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1521010; +} + +static void +Opcode_ae_lbi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lbi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9001; +} + +static void +Opcode_ae_lbi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a3003; +} + +static void +Opcode_ae_lbi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d6004; +} + +static void +Opcode_ae_lbk_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lbk_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8000; +} + +static void +Opcode_ae_lbki_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10563000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lbs_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071b00e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lbsi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af005; + slotbuf[1] = 0; +} + +static void +Opcode_ae_db_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_db_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929e04; +} + +static void +Opcode_ae_dbi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10748b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dbi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09b0c; +} + +static void +Opcode_ae_db_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dbi_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10748f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_db_ic1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dbi_ic1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ab00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_db_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aed00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dbi_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074af00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_ardecnorm16_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065f000; +} + +static void +Opcode_ae_lbki_dbi_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10430000; +} + +static void +Opcode_ae_lbki_dbi_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10440000; +} + +static void +Opcode_ae_lbki_dbi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10420000; +} + +static void +Opcode_ae_lbi_dbi_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680400; +} + +static void +Opcode_ae_lbi_dbi_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680500; +} + +static void +Opcode_ae_lbi_dbi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680300; +} + +static void +Opcode_ae_lbk_db_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10390000; +} + +static void +Opcode_ae_lbk_db_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103a0000; +} + +static void +Opcode_ae_lbk_db_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10380000; +} + +static void +Opcode_ae_lb_db_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680100; +} + +static void +Opcode_ae_lb_db_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680200; +} + +static void +Opcode_ae_lb_db_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680000; +} + +static void +Opcode_ae_vlel32t_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vlel16t_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055b000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072f000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vles16c_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10587ec0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbf_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105871c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sb_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbi_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10552000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vles16c_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105873c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbf_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105875c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sb_ic1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aeb00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbi_ic1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10553000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vles16c_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d130; +} + +static void +Opcode_ae_sbf_ic1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105879c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sb_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aef00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbi_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10556000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vles16c_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105877c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbf_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10587dc0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40081002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movae_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af209; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movae_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf400; +} + +static void +Opcode_ae_movea_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105870c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movea_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf440; +} + +static void +Opcode_ae_moveep_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00426; +} + +static void +Opcode_ae_moveep_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80406862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sext72_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa480000; +} + +static void +Opcode_ae_add72_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa080000; +} + +static void +Opcode_ae_sub72_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa180000; +} + +static void +Opcode_ae_add72x64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa280000; +} + +static void +Opcode_ae_sub72x64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2a0000; +} + +static void +Opcode_ae_mul32ep_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00100; +} + +static void +Opcode_ae_mul32ep_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32ep_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00280; +} + +static void +Opcode_ae_mula32ep_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32ep_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00100; +} + +static void +Opcode_ae_muls32ep_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00200; +} + +static void +Opcode_ae_mulzaad32ep_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00300; +} + +static void +Opcode_ae_mulzssd32ep_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00000; +} + +static void +Opcode_ae_mulaad32ep_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00180; +} + +static void +Opcode_ae_mulssd32ep_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32usep_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00080; +} + +static void +Opcode_ae_mulaad32usep_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32usep_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00280; +} + +static void +Opcode_ae_mulzaad32usep_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32usep_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00180; +} + +static void +Opcode_ae_mula32usep_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00300; +} + +static void +Opcode_ae_mul32usep_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00200; +} + +static void +Opcode_ae_mula32usep_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00380; +} + +static void +Opcode_ae_srai72_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slai72_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40007003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa380000; +} + +static void +Opcode_ae_sat64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_l16si_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200d; +} + +static void +Opcode_ae_l16ui_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400d; +} + +static void +Opcode_ae_s16i_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600d; +} + +static void +Opcode_ae_lalign128_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14000; +} + +static void +Opcode_ae_lalign128_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416000; +} + +static void +Opcode_ae_lalign128_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lalign128_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lalign128_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680080; +} + +static void +Opcode_ae_lalign128_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680080; +} + +static void +Opcode_ae_lalign128_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00e00; +} + +static void +Opcode_ae_lalign128_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514000; +} + +static void +Opcode_ae_lalign128_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000400; +} + +static void +Opcode_ae_lalign128_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1518000; +} + +static void +Opcode_ae_lalign128_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9839c00; +} + +static void +Opcode_ae_lalign128_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142000c; +} + +static void +Opcode_ae_salign128_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000600; +} + +static void +Opcode_ae_salign128_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a9000; +} + +static void +Opcode_ae_la128_pp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08140; +} + +static void +Opcode_ae_la128_pp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142010c; +} + +static void +Opcode_ae_sa128pos_fp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002490; +} + +static void +Opcode_ae_sa128pos_fp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa826004; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc12000; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1414008; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193a0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00860; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512006; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2804010; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516008; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c10201; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400e; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc12010; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1414009; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193e0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03802; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00870; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512007; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2806010; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516009; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c50201; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400f; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00080; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300008; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19068010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000d; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000b0; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000b; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000b0; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000b; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8818101; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000b; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00020; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300002; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19048010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00007; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600080; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600080; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700030; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400003; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400030; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400003; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810101; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400003; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00050; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300005; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19058010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000f; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640040; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640040; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700070; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400007; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400070; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400007; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810103; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400007; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00060; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300006; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19020010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640080; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640080; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700080; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400008; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400080; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400008; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8818000; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400008; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00030; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300003; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19010010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000c0; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000c0; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700040; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400004; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400040; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400004; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810002; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400004; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00070; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300007; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19028010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00009; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400c0; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400c0; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700090; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400009; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400090; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400009; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8818001; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400009; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00010; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300001; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19008010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00006; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600040; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600040; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700010; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400001; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400010; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400001; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810001; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400001; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00040; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300004; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19018010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700050; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400005; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400050; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400005; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810003; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400005; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19060010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00005; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000a0; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000a; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000a0; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000a; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8818100; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000a; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19040010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700020; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400002; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400020; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400002; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810100; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400002; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19050010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700060; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400006; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400060; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400006; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810102; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400006; +} + +static void +Opcode_ae_sa8x8x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800070; +} + +static void +Opcode_ae_sa8x8x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500070; +} + +static void +Opcode_ae_sa8x8x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830301; +} + +static void +Opcode_ae_sa16x4x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000f0; +} + +static void +Opcode_ae_sa16x4x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000f0; +} + +static void +Opcode_ae_sa16x4x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820301; +} + +static void +Opcode_ae_sa32x2x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800030; +} + +static void +Opcode_ae_sa32x2x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500030; +} + +static void +Opcode_ae_sa32x2x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820303; +} + +static void +Opcode_ae_sa8x8x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800040; +} + +static void +Opcode_ae_sa8x8x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500040; +} + +static void +Opcode_ae_sa8x8x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830200; +} + +static void +Opcode_ae_sa16x4x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000c0; +} + +static void +Opcode_ae_sa16x4x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000c0; +} + +static void +Opcode_ae_sa16x4x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820200; +} + +static void +Opcode_ae_sa32x2x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800000; +} + +static void +Opcode_ae_sa32x2x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500000; +} + +static void +Opcode_ae_sa32x2x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820202; +} + +static void +Opcode_ae_sa8x8x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800050; +} + +static void +Opcode_ae_sa8x8x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500050; +} + +static void +Opcode_ae_sa8x8x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830201; +} + +static void +Opcode_ae_sa16x4x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000d0; +} + +static void +Opcode_ae_sa16x4x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000d0; +} + +static void +Opcode_ae_sa16x4x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820201; +} + +static void +Opcode_ae_sa32x2x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800010; +} + +static void +Opcode_ae_sa32x2x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500010; +} + +static void +Opcode_ae_sa32x2x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820203; +} + +static void +Opcode_ae_sa8x8x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800060; +} + +static void +Opcode_ae_sa8x8x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500060; +} + +static void +Opcode_ae_sa8x8x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830300; +} + +static void +Opcode_ae_sa16x4x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000e0; +} + +static void +Opcode_ae_sa16x4x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000e0; +} + +static void +Opcode_ae_sa16x4x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820300; +} + +static void +Opcode_ae_sa32x2x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800020; +} + +static void +Opcode_ae_sa32x2x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500020; +} + +static void +Opcode_ae_sa32x2x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820302; +} + +static void +Opcode_ae_abs8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00e0; +} + +static void +Opcode_ae_abs8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs8s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003820; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_abs8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0010; +} + +static void +Opcode_ae_abs8s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8005e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f70; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg8s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003c60; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_neg8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a02a0; +} + +static void +Opcode_ae_neg8s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800de462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080400; +} + +static void +Opcode_ae_sub8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18600b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380400; +} + +static void +Opcode_ae_max8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18280f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0110040; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max8_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_ae_max8_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40900a0; +} + +static void +Opcode_ae_max8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180400; +} + +static void +Opcode_ae_max8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a0000; +} + +static void +Opcode_ae_min8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18380f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc01100a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min8_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x548000; +} + +static void +Opcode_ae_min8_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40a80a0; +} + +static void +Opcode_ae_min8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180600; +} + +static void +Opcode_ae_min8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80b8000; +} + +static void +Opcode_ae_add8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18080b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add8s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002800; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_add8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080800; +} + +static void +Opcode_ae_add8s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007460; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18600f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub8s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003400; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_sub8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380800; +} + +static void +Opcode_ae_sub8s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_le8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18740f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380e00; +} + +static void +Opcode_ae_lt8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18780b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380b00; +} + +static void +Opcode_ae_eq8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18700f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380a00; +} + +static void +Opcode_ae_satu16x4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000c0; +} + +static void +Opcode_ae_satu16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000062; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_satu32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001062; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat8x8x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_satu8x8x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat8x4x32_l_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000b0; +} + +static void +Opcode_ae_sat8x4x32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_satu8x4x32_l_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000d0; +} + +static void +Opcode_ae_satu8x4x32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round8x8f16ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round8x8f16sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round8x4f32ssym_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round8x4f32sasym_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movda8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x752a003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda8_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00803; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105820c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda8_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0301; +} + +static void +Opcode_ae_movda8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640660; +} + +static void +Opcode_ae_movda8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e10a0; +} + +static void +Opcode_ae_movda8_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556004; +} + +static void +Opcode_ae_movad8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d832080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad8_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10734008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690080; +} + +static void +Opcode_ae_movad8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01208; +} + +static void +Opcode_ae_movdx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movdx2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movdx2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10100000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movdx2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10100000; +} + +static void +Opcode_ae_movdx2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_movdx2_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_movdx2_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_movdx2_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_movdx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_movdx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; +} + +static void +Opcode_ae_movdx2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000100; +} + +static void +Opcode_ae_movdx2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsub32j_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsub32j_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_addandsub32j_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsub32j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8400000; +} + +static void +Opcode_ae_addandsub32j_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5200000; +} + +static void +Opcode_ae_addandsub32j_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000024; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addw8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addw8_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_addw8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc400000; +} + +static void +Opcode_ae_addw8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002e; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addw16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addw16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_addw16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb400000; +} + +static void +Opcode_ae_addw16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002c; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addw32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addw32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ae_addw32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb400800; +} + +static void +Opcode_ae_addw32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002d; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subw8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subw8_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_subw8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe400000; +} + +static void +Opcode_ae_subw8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000032; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subw16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subw16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_ae_subw16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd400000; +} + +static void +Opcode_ae_subw16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000030; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subw32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subw32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_ae_subw32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd400800; +} + +static void +Opcode_ae_subw32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000031; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_accw8_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_accw8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000022; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_accw16_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_accw16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_accw32_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_accw32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000021; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addw8u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addw8u_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_ae_addw8u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc400800; +} + +static void +Opcode_ae_addw8u_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002f; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subw8u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subw8u_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_subw8u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe400800; +} + +static void +Opcode_ae_subw8u_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000033; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_accw8u_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_accw8u_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000023; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x2s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c00000; +} + +static void +Opcode_ae_mulfp32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x2s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4700000; +} + +static void +Opcode_ae_mulafp32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x2s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000000; +} + +static void +Opcode_ae_mulsfp32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x2s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d00000; +} + +static void +Opcode_ae_mulfp32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x2s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4800000; +} + +static void +Opcode_ae_mulafp32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x2s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100000; +} + +static void +Opcode_ae_mulsfp32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulasf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulssf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulasf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulasf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulasf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulssf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulssf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulssf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mul32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd000c0; +} + +static void +Opcode_ae_mul32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00080; +} + +static void +Opcode_ae_mul32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8aa00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00300; +} + +static void +Opcode_ae_mula32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e002c0; +} + +static void +Opcode_ae_mula32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ed00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc004800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12002a0; +} + +static void +Opcode_ae_muls32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d001c0; +} + +static void +Opcode_ae_muls32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00120; +} + +static void +Opcode_ae_mul32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e000e0; +} + +static void +Opcode_ae_mul32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00360; +} + +static void +Opcode_ae_mula32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00320; +} + +static void +Opcode_ae_mula32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ce00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca004c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200300; +} + +static void +Opcode_ae_muls32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e001a0; +} + +static void +Opcode_ae_muls32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32s_hl_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32s_hl_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd000e0; +} + +static void +Opcode_ae_mul32s_hl_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e000a0; +} + +static void +Opcode_ae_mul32s_hl_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ab00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32s_hl_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32s_hl_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00320; +} + +static void +Opcode_ae_mula32s_hl_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e002e0; +} + +static void +Opcode_ae_mula32s_hl_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88e00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32s_hl_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce004800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32s_hl_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12002c0; +} + +static void +Opcode_ae_muls32s_hl_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d001e0; +} + +static void +Opcode_ae_muls32s_hl_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00100; +} + +static void +Opcode_ae_mul32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e000c0; +} + +static void +Opcode_ae_mul32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00340; +} + +static void +Opcode_ae_mula32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00300; +} + +static void +Opcode_ae_mula32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ae00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8004c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12002e0; +} + +static void +Opcode_ae_muls32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e00180; +} + +static void +Opcode_ae_muls32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500140; +} + +static void +Opcode_ae_mulzaad32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500320; +} + +static void +Opcode_ae_mulzaad32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15003e0; +} + +static void +Opcode_ae_mulzasd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66003c0; +} + +static void +Opcode_ae_mulzasd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsad32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsad32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600160; +} + +static void +Opcode_ae_mulzsad32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700340; +} + +static void +Opcode_ae_mulzsad32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600280; +} + +static void +Opcode_ae_mulzssd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68002a0; +} + +static void +Opcode_ae_mulzssd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6004400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00160; +} + +static void +Opcode_ae_mulaad32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00120; +} + +static void +Opcode_ae_mulaad32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000260; +} + +static void +Opcode_ae_mulasd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68001c0; +} + +static void +Opcode_ae_mulasd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8df00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsad32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc005800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsad32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000a0; +} + +static void +Opcode_ae_mulsad32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60002c0; +} + +static void +Opcode_ae_mulsad32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14002c0; +} + +static void +Opcode_ae_mulssd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64002a0; +} + +static void +Opcode_ae_mulssd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500160; +} + +static void +Opcode_ae_mulzaad32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500340; +} + +static void +Opcode_ae_mulzaad32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600000; +} + +static void +Opcode_ae_mulzasd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66003e0; +} + +static void +Opcode_ae_mulzasd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsad32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsad32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600180; +} + +static void +Opcode_ae_mulzsad32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700360; +} + +static void +Opcode_ae_mulzsad32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002a0; +} + +static void +Opcode_ae_mulzssd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68002c0; +} + +static void +Opcode_ae_mulzssd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6004800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00180; +} + +static void +Opcode_ae_mulaad32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00140; +} + +static void +Opcode_ae_mulaad32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000280; +} + +static void +Opcode_ae_mulasd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68001e0; +} + +static void +Opcode_ae_mulasd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ff00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsad32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce005800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsad32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000c0; +} + +static void +Opcode_ae_mulsad32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60002e0; +} + +static void +Opcode_ae_mulsad32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14002e0; +} + +static void +Opcode_ae_mulssd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64002c0; +} + +static void +Opcode_ae_mulssd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x2ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x2ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x2ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x2ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x2ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x2ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulf32x2r_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x2r_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x2r_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x2r_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x2r_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x2r_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj32ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8003000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfcj32ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100340; +} + +static void +Opcode_ae_mulfcj32ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76001c0; +} + +static void +Opcode_ae_mulfcj32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj32ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafcj32ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00360; +} + +static void +Opcode_ae_mulafcj32ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62001c0; +} + +static void +Opcode_ae_mulafcj32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89a00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf2p32x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2p32x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2p32x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulaf2p32x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulaf2p32x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulaf2p32x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulsf2p32x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulsf2p32x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulsf2p32x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulf2p32x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2p32x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2p32x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulaf2p32x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaf2p32x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaf2p32x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulsf2p32x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsf2p32x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsf2p32x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulp32x2s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul2p32x4s_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4s_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula2p32x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2p32x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2p32x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_muls2p32x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_muls2p32x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_muls2p32x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mul2p32x4t_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4t_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4t_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula2p32x4t_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2p32x4t_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2p32x4t_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_muls2p32x4t_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_muls2p32x4t_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_muls2p32x4t_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulzaa32x2_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzss32x2_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaa32x2_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss32x2_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulcj32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca001400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulcj32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100060; +} + +static void +Opcode_ae_mulcj32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d001c0; +} + +static void +Opcode_ae_mulcj32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulacj32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulacj32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00080; +} + +static void +Opcode_ae_mulacj32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600160; +} + +static void +Opcode_ae_mulacj32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89100040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc32ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc32ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_mulfc32ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4900000; +} + +static void +Opcode_ae_mulfc32ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc32ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc32ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_mulafc32ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4400000; +} + +static void +Opcode_ae_mulafc32ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulcj32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulacj32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf2d32x2ws_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2d32x2ws_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2d32x2ws_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulzaaaa2q16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaaa2q16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaaa2q16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulaaaa2q16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaaa2q16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaaa2q16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulp16s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca003c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp16s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200100; +} + +static void +Opcode_ae_mulp16s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a001a0; +} + +static void +Opcode_ae_mulp16s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulap16s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap16s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000e0; +} + +static void +Opcode_ae_mulap16s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65001c0; +} + +static void +Opcode_ae_mulap16s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8fc00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsp16s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp16s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400100; +} + +static void +Opcode_ae_mulsp16s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63002e0; +} + +static void +Opcode_ae_mulsp16s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc003c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200120; +} + +static void +Opcode_ae_mulp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a001c0; +} + +static void +Opcode_ae_mulp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulap16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000100; +} + +static void +Opcode_ae_mulap16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65001e0; +} + +static void +Opcode_ae_mulap16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89d00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400120; +} + +static void +Opcode_ae_mulsp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300300; +} + +static void +Opcode_ae_mulsp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul2c16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula2c16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj16ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce002c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfcj16ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100320; +} + +static void +Opcode_ae_mulfcj16ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76001a0; +} + +static void +Opcode_ae_mulfcj16ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj16ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafcj16ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00340; +} + +static void +Opcode_ae_mulafcj16ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62001a0; +} + +static void +Opcode_ae_mulafcj16ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc16s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10003e0; +} + +static void +Opcode_ae_mulc16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c00180; +} + +static void +Opcode_ae_mulc16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac16s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_mulac16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000160; +} + +static void +Opcode_ae_mulac16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp16x4rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca003000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp16x4rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100360; +} + +static void +Opcode_ae_mulfp16x4rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7700180; +} + +static void +Opcode_ae_mulfp16x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfd16x16x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfd16x16x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfd16x16x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulp16x16x4s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce003c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp16x16x4s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200140; +} + +static void +Opcode_ae_mulp16x16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a001e0; +} + +static void +Opcode_ae_mulp16x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulap16x16x4s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap16x16x4s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000120; +} + +static void +Opcode_ae_mulap16x16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600180; +} + +static void +Opcode_ae_mulap16x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8bd00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsp16x16x4s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp16x16x4s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400140; +} + +static void +Opcode_ae_mulsp16x16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300320; +} + +static void +Opcode_ae_mulsp16x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000e0; +} + +static void +Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65002c0; +} + +static void +Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500100; +} + +static void +Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65002e0; +} + +static void +Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600240; +} + +static void +Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800260; +} + +static void +Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600260; +} + +static void +Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800280; +} + +static void +Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6003800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00100; +} + +static void +Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f000c0; +} + +static void +Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6003c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00120; +} + +static void +Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f000e0; +} + +static void +Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss2d16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulss2d16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400220; +} + +static void +Opcode_ae_mulss2d16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400200; +} + +static void +Opcode_ae_mulss2d16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss2d16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulss2d16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400240; +} + +static void +Opcode_ae_mulss2d16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400220; +} + +static void +Opcode_ae_mulss2d16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15002a0; +} + +static void +Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600280; +} + +static void +Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15002c0; +} + +static void +Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66002a0; +} + +static void +Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003a0; +} + +static void +Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68003c0; +} + +static void +Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003c0; +} + +static void +Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68003e0; +} + +static void +Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6007000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002c0; +} + +static void +Opcode_ae_mulaafd16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00280; +} + +static void +Opcode_ae_mulaafd16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6007400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002e0; +} + +static void +Opcode_ae_mulaafd16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f002a0; +} + +static void +Opcode_ae_mulaafd16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14003e0; +} + +static void +Opcode_ae_mulssfd16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64003c0; +} + +static void +Opcode_ae_mulssfd16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_mulssfd16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64003e0; +} + +static void +Opcode_ae_mulssfd16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfd16x16x4ws_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulfd16x16x4ws_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulfd16x16x4ws_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulzaaaa2q16x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaa2q16x8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaa2q16x8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaa2q16x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaaaa2q16x8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaaaa2q16x8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzaaaa2q8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaa2q8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaa2q8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaa2q8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaa2q8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaa2q8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulpc32x16x2_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulpc32x16x2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulpc32x16x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulapc32x16x2_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulapc32x16x2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulapc32x16x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfp32x16_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc32x16w_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a00000; +} + +static void +Opcode_ae_mulfc32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc32x16w_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4500000; +} + +static void +Opcode_ae_mulafc32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc32x16w_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b00000; +} + +static void +Opcode_ae_mulfc32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc32x16w_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4600000; +} + +static void +Opcode_ae_mulafc32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf2p32x16x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulsf2p32x16x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf2p32x16x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulsf2p32x16x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf2p32x16x4s_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4s_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4s_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4s_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulsf2p32x16x4s_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4s_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfpc32x16x2ras_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mulfpc32x16x2ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfpc32x16x2ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfpc32x16x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpc32x16x2ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpc32x16x2ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpc32x16x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfpcj32x16x2ras_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ae_mulfpcj32x16x2ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfpcj32x16x2ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfpcj32x16x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpcj32x16x2ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpcj32x16x2ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpcj32x16x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzaaaa2q32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaaa2q32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaaa2q32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulaaaa2q32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaaa2q32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaaa2q32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mul2q32x16_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2q32x16_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2q32x16_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula2q32x16_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2q32x16_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2q32x16_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mul2q32x16_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mul2q32x16_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mul2q32x16_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2q32x16_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mula2q32x16_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mula2q32x16_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_srai8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d824080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00208; +} + +static void +Opcode_ae_srai8r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d826080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai8r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04208; +} + +static void +Opcode_ae_srli8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d828080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srli8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00308; +} + +static void +Opcode_ae_slai8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d820080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9308; +} + +static void +Opcode_ae_slai8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d822080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83ad308; +} + +static void +Opcode_ae_slaa8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a800c; +} + +static void +Opcode_ae_srla8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c82c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9008; +} + +static void +Opcode_ae_slaa8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x758a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a810c; +} + +static void +Opcode_ae_sraa8rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa8rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1104; +} + +static void +Opcode_ae_sraa8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x758c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9004; +} + +static void +Opcode_ae_srli16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c830000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srli16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1208; +} + +static void +Opcode_ae_slai16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c81c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a820c; +} + +static void +Opcode_ae_slaa16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c814000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8008; +} + +static void +Opcode_ae_srla16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c826000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9304; +} + +static void +Opcode_ae_srai16sym_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c824000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai16sym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9204; +} + +static void +Opcode_ae_sraa16syms_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d81e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa16syms_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9100; +} + +static void +Opcode_ae_srai32sym_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai32sym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842e007; +} + +static void +Opcode_ae_sraa32syms_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x748e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa32syms_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9300; +} + +static void +Opcode_ae_srav16rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srav16rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00000; +} + +static void +Opcode_ae_srav32rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srav32rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c02000; +} + +static void +Opcode_ae_cvti32x4f8_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a014000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8424002; +} + +static void +Opcode_ae_cvti32x4f8_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a016000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8426002; +} + +static void +Opcode_ae_cvti32x4f8s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a008000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8420001; +} + +static void +Opcode_ae_cvti32x4f8s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8422001; +} + +static void +Opcode_ae_cvta32x4f8_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a034000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8120200; +} + +static void +Opcode_ae_cvta32x4f8_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a036000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8120300; +} + +static void +Opcode_ae_cvta32x4f8s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a028000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82a0000; +} + +static void +Opcode_ae_cvta32x4f8s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a02a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82a0100; +} + +static void +Opcode_ae_cvti32x4f8u_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a010000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8u_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8420002; +} + +static void +Opcode_ae_cvti32x4f8u_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a012000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8u_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8422002; +} + +static void +Opcode_ae_cvti32x4f8us_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8us_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8424001; +} + +static void +Opcode_ae_cvti32x4f8us_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8us_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8426001; +} + +static void +Opcode_ae_cvta32x4f8u_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a030000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8u_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8120000; +} + +static void +Opcode_ae_cvta32x4f8u_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a032000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8u_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8120100; +} + +static void +Opcode_ae_cvta32x4f8us_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a02c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8us_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82a0200; +} + +static void +Opcode_ae_cvta32x4f8us_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a02e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8us_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82a0300; +} + +static void +Opcode_ae_cvti32x4f16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8420000; +} + +static void +Opcode_ae_cvti32x4f16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8422000; +} + +static void +Opcode_ae_cvta32x4f16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a020000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a0000; +} + +static void +Opcode_ae_cvta32x4f16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a022000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a0100; +} + +static void +Opcode_ae_cvti32x4f16u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f16u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8424000; +} + +static void +Opcode_ae_cvti32x4f16us_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f16us_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8426000; +} + +static void +Opcode_ae_cvta32x4f16u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a024000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f16u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a0200; +} + +static void +Opcode_ae_cvta32x4f16us_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a026000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f16us_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a0300; +} + +static void +Opcode_ae_cvti16x4x2f8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a038000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti16x4x2f8_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500200; +} + +static void +Opcode_ae_cvti16x4x2f8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8320000; +} + +static void +Opcode_ae_cvti16x4x2f8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a03a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti16x4x2f8s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_cvti16x4x2f8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8320100; +} + +static void +Opcode_ae_cvta16x4x2f8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b018000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta16x4x2f8_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_cvta16x4x2f8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220000; +} + +static void +Opcode_ae_cvta16x4x2f8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b01a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta16x4x2f8s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400200; +} + +static void +Opcode_ae_cvta16x4x2f8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220100; +} + +static void +Opcode_ae_cvti16x4x2f8u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a03c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti16x4x2f8u_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600200; +} + +static void +Opcode_ae_cvti16x4x2f8u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8320200; +} + +static void +Opcode_ae_cvti16x4x2f8us_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a03e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti16x4x2f8us_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8320300; +} + +static void +Opcode_ae_cvta16x4x2f8u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b01c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta16x4x2f8u_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_cvta16x4x2f8u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220200; +} + +static void +Opcode_ae_cvta16x4x2f8us_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b01e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta16x4x2f8us_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220300; +} + +static void +Opcode_ae_sel8x8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0108000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sel8x8_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_ae_sel8x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel8x8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000440; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel8x8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a00000; +} + +static void +Opcode_ae_sel8x8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000036; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl8x8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc01100e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_shfl8x8_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900400; +} + +static void +Opcode_ae_shfl8x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a08000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl8x8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000c40; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl8x8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8200400; +} + +static void +Opcode_ae_shfl8x8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000063; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel16x4_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_sel16x4_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000020; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_sel16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0100000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sel16x4_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_ae_sel16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel16x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel16x4_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sel16x4_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000020; +} + +static void +Opcode_ae_sel16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5900000; +} + +static void +Opcode_ae_sel16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000035; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc01100c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_shfl16x4_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900000; +} + +static void +Opcode_ae_shfl16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl16x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c40; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8200000; +} + +static void +Opcode_ae_shfl16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000063; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel8x8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80008000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dsel8x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel8x8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000400; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel8x8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ae_dsel8x8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000001; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel16x4_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_dsel16x4_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_dsel16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dsel16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel16x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel16x4_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dsel16x4_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000000; +} + +static void +Opcode_ae_dsel16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_dsel16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel8x8i_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sel8x8i_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_sel8x8i_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel8x8i_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000840; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel8x8i_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b00000; +} + +static void +Opcode_ae_sel8x8i_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000037; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rmax8x8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63d0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_rmax8x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b004e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rmax8x8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac58000; +} + +static void +Opcode_ae_rmin8x8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63e0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_rmin8x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00520; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rmin8x8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae58000; +} + +static void +Opcode_ae_rmax16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63c8c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_rmax16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b004c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rmax16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab58000; +} + +static void +Opcode_ae_rmin16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63d8c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_rmin16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00500; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rmin16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad58000; +} + +static void +Opcode_ae_sort16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e048000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sort16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sort16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa038000; +} + +static void +Opcode_ae_radd8x8_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63a0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radd8x8_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00420; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radd8x8_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa658000; +} + +static void +Opcode_ae_radda8x8_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63b8c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radda8x8_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00480; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radda8x8_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa958000; +} + +static void +Opcode_ae_radd8x8_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63a8c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radd8x8_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00440; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radd8x8_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa758000; +} + +static void +Opcode_ae_radda8x8_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63c0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radda8x8_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b004a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radda8x8_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa58000; +} + +static void +Opcode_ae_radd16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6398c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radd16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00400; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radd16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa558000; +} + +static void +Opcode_ae_radda16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63b0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radda16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00460; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radda16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa858000; +} + +static void +Opcode_ae_bmax8x8_h_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14004400; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmax8x8_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_bmax8x8_l_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1288000; +} + +static void +Opcode_ae_bmax8x8_l_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14006000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmax8x8_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_bmin8x8_h_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmin8x8_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_bmin8x8_l_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c8000; +} + +static void +Opcode_ae_bmin8x8_l_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000400; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmin8x8_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_bmax16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bmax16x4_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ae_bmax16x4_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14004000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmax16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820800; +} + +static void +Opcode_ae_bmin16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bmin16x4_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ae_bmin16x4_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14006400; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmin16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820c00; +} + +static void +Opcode_ae_bmax32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c700000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bmax32x2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ae_bmax32x2_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmax32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400a00; +} + +static void +Opcode_ae_bmin32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c700100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bmin32x2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ae_bmin32x2_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14002000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmin32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400e00; +} + +static void +Opcode_ae_addinv16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80fd0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addinv16s_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a000; +} + +static void +Opcode_ae_addinv16s_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ae_addinv16s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003c20; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addinv16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0050; +} + +static void +Opcode_ae_addinv16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3d0000; +} + +static void +Opcode_ae_addinv16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8006e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addinv32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80fe0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addinv32s_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a400; +} + +static void +Opcode_ae_addinv32s_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130020; +} + +static void +Opcode_ae_addinv32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003840; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addinv32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0070; +} + +static void +Opcode_ae_addinv32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3d8000; +} + +static void +Opcode_ae_addinv32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80076462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movt16x8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt16x8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_movt8x16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt8x16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; +} + +static void +Opcode_ae_movt8x16_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt8x16_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000000; +} + +static void +Opcode_ae_movbd1x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520005; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movbd1x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa824004; +} + +static void +Opcode_ae_movbd1x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movbd1x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa820004; +} + +static void +Opcode_ae_movneg32s_t_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18400b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movneg32s_t_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180a00; +} + +static void +Opcode_ae_movneg32s_t_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80d0000; +} + +static void +Opcode_ae_movneg32s_t_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movdext_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movdext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8420003; +} + +static void +Opcode_ae_movadext_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c400000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movadext_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400000; +} + +static void +Opcode_ae_movadext_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c440000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movadext_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400400; +} + +static void +Opcode_ae_nsa16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19196030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsa16x4_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03021; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsa16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0220c; +} + +static void +Opcode_ae_nsaz32x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880070; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz32x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c06001; +} + +static void +Opcode_ae_nsa32x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880060; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsa32x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04001; +} + +static void +Opcode_ae_trunci16x4f32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c080000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunci16x4f32s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_trunci16x4f32s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ae_trunci16x4f32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8422003; +} + +static void +Opcode_ae_trunci16x4f64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunci16x4f64s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_trunci16x4f64s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_trunci16x4f64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8020000; +} + +static void +Opcode_ae_trunca16x4f32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c100000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca16x4f32s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ae_trunca16x4f32s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_trunca16x4f32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81a0000; +} + +static void +Opcode_ae_trunca16x4f64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c180000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca16x4f64s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x704000; +} + +static void +Opcode_ae_trunca16x4f64s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1480000; +} + +static void +Opcode_ae_trunca16x4f64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81a0100; +} + +static void +Opcode_ae_addc32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c680000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addc32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_addc32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400800; +} + +static void +Opcode_ae_subc32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c780000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subc32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_subc32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820000; +} + +static void +Opcode_ae_addc32u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c680100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addc32u_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_ae_addc32u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400c00; +} + +static void +Opcode_ae_subc32u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c780100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subc32u_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_subc32u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820400; +} + +static void +Opcode_ae_expadd16_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; +} + +static void +Opcode_ae_expadd16_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_expsub16_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010000; +} + +static void +Opcode_ae_expsub16_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004860; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_expadd16_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8008000; +} + +static void +Opcode_ae_expadd16_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004460; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_expsub16_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8018000; +} + +static void +Opcode_ae_expsub16_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004c60; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addcexp32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002a; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addcexp32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002b; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_calcrng16_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680800; +} + +static void +Opcode_ae_calcrng32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680c00; +} + +static void +Opcode_ae_rng32x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7382f00; +} + +static void +Opcode_ae_lav8x8x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_lav8x8x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a058000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lav8x8x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_lav8x8x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_lav8x8x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8118000; +} + +static void +Opcode_ae_lav16x4x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lav16x4x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a018000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lav16x4x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_lav16x4x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_lav16x4x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8110000; +} + +static void +Opcode_ae_sav8x8x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_sav8x8x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_sav8x8x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf410000; +} + +static void +Opcode_ae_sav16x4x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_sav16x4x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_sav16x4x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf400000; +} + +static void +Opcode_ae_movzbvcdr_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100001; + slotbuf[1] = 0x229860; +} + +static void +Opcode_ae_movzbvcdr_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00027; +} + +static void +Opcode_ae_movdrzbvc_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; + slotbuf[1] = 0x229860; +} + +static void +Opcode_ae_movdrzbvc_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00026; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6040000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mul8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002000; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mul8q4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula8q4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400; + slotbuf[1] = 0x2c0100; +} + +static void +Opcode_ae_mul8q8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula8q8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mul8qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x40000; +} + +static void +Opcode_ae_mula8qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xc0000; +} + +static void +Opcode_ae_mul4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x240000; +} + +static void +Opcode_ae_mula4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x240000; +} + +static void +Opcode_ae_mul4o4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x280000; +} + +static void +Opcode_ae_mula4o4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x284000; +} + +static void +Opcode_ae_mul4o8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula4o8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x80000; +} + +static void +Opcode_ae_mul4qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x282000; +} + +static void +Opcode_ae_mula4qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x286000; +} + +static void +Opcode_ae_mul8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0728; +} + +static void +Opcode_ae_mul8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0628; +} + +static void +Opcode_ae_mula8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c2628; +} + +static void +Opcode_ae_mula8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c2628; +} + +static void +Opcode_ae_mul8q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0128; +} + +static void +Opcode_ae_mula8q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0228; +} + +static void +Opcode_ae_mul2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0628; +} + +static void +Opcode_ae_mula2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0728; +} + +static void +Opcode_ae_mul2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0008; +} + +static void +Opcode_ae_mul2x4q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula2x4q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0008; +} + +static void +Opcode_ae_mulqq8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200040; +} + +static void +Opcode_ae_mulaqq8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200010; +} + +static void +Opcode_ae_mul4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201860; +} + +static void +Opcode_ae_mula4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x205860; +} + +static void +Opcode_ae_mul4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x203860; +} + +static void +Opcode_ae_mula4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x207860; +} + +static void +Opcode_ae_mul4o8x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200460; +} + +static void +Opcode_ae_mula4o8x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200a60; +} + +static void +Opcode_ae_mul4o8x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200560; +} + +static void +Opcode_ae_mula4o8x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200b60; +} + +static void +Opcode_ae_mul8q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0028; +} + +static void +Opcode_ae_mula8q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0128; +} + +static void +Opcode_ae_mul8q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0028; +} + +static void +Opcode_ae_mula8q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0228; +} + +static void +Opcode_ae_mul2x4q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula2x4q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0008; +} + +static void +Opcode_ae_mul2x4q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula2x4q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0008; +} + +static void +Opcode_ae_mulqq4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200030; +} + +static void +Opcode_ae_mulaqq4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200000; +} + +static void +Opcode_ae_mulqq4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200038; +} + +static void +Opcode_ae_mulaqq4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200008; +} + +static void +Opcode_ae_mul4o4x16cnv_hh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200060; +} + +static void +Opcode_ae_mul4o4x16cnv_hl_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200160; +} + +static void +Opcode_ae_mul4o4x16cnv_lh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200260; +} + +static void +Opcode_ae_mul4o4x16cnv_ll_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200360; +} + +static void +Opcode_ae_mula4o4x16cnv_hh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200660; +} + +static void +Opcode_ae_mula4o4x16cnv_hl_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200760; +} + +static void +Opcode_ae_mula4o4x16cnv_lh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200860; +} + +static void +Opcode_ae_mula4o4x16cnv_ll_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200960; +} + +static void +Opcode_ae_muluu8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; + slotbuf[1] = 0x2c0002; +} + +static void +Opcode_ae_mulauu8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; + slotbuf[1] = 0x2c0001; +} + +static void +Opcode_ae_muluu4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x240002; +} + +static void +Opcode_ae_mulauu4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x240001; +} + +static void +Opcode_ae_muluu8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2cc728; +} + +static void +Opcode_ae_mulauu8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c6728; +} + +static void +Opcode_ae_muluu8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2cc628; +} + +static void +Opcode_ae_mulauu8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c6628; +} + +static void +Opcode_ae_muluu2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2cc628; +} + +static void +Opcode_ae_mulauu2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c6628; +} + +static void +Opcode_ae_muluu2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0028; +} + +static void +Opcode_ae_mulauu2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0018; +} + +static void +Opcode_ae_muluu4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x221860; +} + +static void +Opcode_ae_mulauu4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x211860; +} + +static void +Opcode_ae_muluu4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x223860; +} + +static void +Opcode_ae_mulauu4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x213860; +} + +static void +Opcode_ae_mulus8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0002000; + slotbuf[1] = 0x2c0001; +} + +static void +Opcode_ae_mulaus8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0002000; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mulus8q4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400; + slotbuf[1] = 0x2c0300; +} + +static void +Opcode_ae_mulaus8q4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400; + slotbuf[1] = 0x2c0200; +} + +static void +Opcode_ae_mulus8q8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mulaus8q8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mulus8qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x1c0000; +} + +static void +Opcode_ae_mulaus8qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x140000; +} + +static void +Opcode_ae_mulus4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x240001; +} + +static void +Opcode_ae_mulaus4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x240000; +} + +static void +Opcode_ae_mulus4o4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x28c000; +} + +static void +Opcode_ae_mulaus4o4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x288000; +} + +static void +Opcode_ae_mulus4o8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x180000; +} + +static void +Opcode_ae_mulaus4o8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x100000; +} + +static void +Opcode_ae_mulus4qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x28e000; +} + +static void +Opcode_ae_mulaus4qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x28a000; +} + +static void +Opcode_ae_mulus8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2ca728; +} + +static void +Opcode_ae_mulaus8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c4728; +} + +static void +Opcode_ae_mulus8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2ca728; +} + +static void +Opcode_ae_mulaus8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c4728; +} + +static void +Opcode_ae_mulus8q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0528; +} + +static void +Opcode_ae_mulaus8q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0428; +} + +static void +Opcode_ae_mulus2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2ca628; +} + +static void +Opcode_ae_mulaus2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c4628; +} + +static void +Opcode_ae_mulus2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0020; +} + +static void +Opcode_ae_mulaus2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0018; +} + +static void +Opcode_ae_mulus2x4q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0020; +} + +static void +Opcode_ae_mulaus2x4q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0010; +} + +static void +Opcode_ae_mulusqq8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200058; +} + +static void +Opcode_ae_mulausqq8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200028; +} + +static void +Opcode_ae_mulus4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x21d860; +} + +static void +Opcode_ae_mulaus4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x20d860; +} + +static void +Opcode_ae_mulus4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x21f860; +} + +static void +Opcode_ae_mulaus4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x20f860; +} + +static void +Opcode_ae_mulus4o8x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201660; +} + +static void +Opcode_ae_mulaus4o8x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201060; +} + +static void +Opcode_ae_mulus4o8x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201760; +} + +static void +Opcode_ae_mulaus4o8x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201160; +} + +static void +Opcode_ae_mulus8q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0428; +} + +static void +Opcode_ae_mulaus8q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0328; +} + +static void +Opcode_ae_mulus8q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0528; +} + +static void +Opcode_ae_mulaus8q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0328; +} + +static void +Opcode_ae_mulus2x4q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0020; +} + +static void +Opcode_ae_mulaus2x4q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0010; +} + +static void +Opcode_ae_mulus2x4q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0020; +} + +static void +Opcode_ae_mulaus2x4q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0010; +} + +static void +Opcode_ae_mulusqq4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200048; +} + +static void +Opcode_ae_mulausqq4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200018; +} + +static void +Opcode_ae_mulusqq4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200050; +} + +static void +Opcode_ae_mulausqq4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200020; +} + +static void +Opcode_ae_mulus4o4x16cnv_hh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201260; +} + +static void +Opcode_ae_mulus4o4x16cnv_hl_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201360; +} + +static void +Opcode_ae_mulus4o4x16cnv_lh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201460; +} + +static void +Opcode_ae_mulus4o4x16cnv_ll_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201560; +} + +static void +Opcode_ae_mulaus4o4x16cnv_hh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200c60; +} + +static void +Opcode_ae_mulaus4o4x16cnv_hl_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200d60; +} + +static void +Opcode_ae_mulaus4o4x16cnv_lh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200e60; +} + +static void +Opcode_ae_mulaus4o4x16cnv_ll_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200f60; +} + +static void +Opcode_ae_mulsu8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002000; + slotbuf[1] = 0x2c0001; +} + +static void +Opcode_ae_mulasu8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002000; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mulsu4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x240001; +} + +static void +Opcode_ae_mulasu4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x240000; +} + +static void +Opcode_ae_mulsu8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2ca628; +} + +static void +Opcode_ae_mulasu8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c4628; +} + +static void +Opcode_ae_mulsu8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c8728; +} + +static void +Opcode_ae_mulasu8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c2728; +} + +static void +Opcode_ae_mulsu2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c8728; +} + +static void +Opcode_ae_mulasu2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c2728; +} + +static void +Opcode_ae_mulsu2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0018; +} + +static void +Opcode_ae_mulasu2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0010; +} + +static void +Opcode_ae_mulsu4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x219860; +} + +static void +Opcode_ae_mulasu4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x209860; +} + +static void +Opcode_ae_mulsu4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x21b860; +} + +static void +Opcode_ae_mulasu4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x20b860; +} + +static void +Opcode_ae_muluuzb8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002000; + slotbuf[1] = 0x2c0002; +} + +static void +Opcode_ae_mulauuzb8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002000; + slotbuf[1] = 0x2c0001; +} + +static void +Opcode_ae_muluuzb4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x240002; +} + +static void +Opcode_ae_mulauuzb4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x240001; +} + +static void +Opcode_ae_muluuzb8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2ce628; +} + +static void +Opcode_ae_mulauuzb8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c8628; +} + +static void +Opcode_ae_muluuzb8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2ce628; +} + +static void +Opcode_ae_mulauuzb8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c8628; +} + +static void +Opcode_ae_muluuzb2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2cc728; +} + +static void +Opcode_ae_mulauuzb2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c6728; +} + +static void +Opcode_ae_muluuzb2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0028; +} + +static void +Opcode_ae_mulauuzb2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0018; +} + +static void +Opcode_ae_muluuzb4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x225860; +} + +static void +Opcode_ae_mulauuzb4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x215860; +} + +static void +Opcode_ae_muluuzb4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x227860; +} + +static void +Opcode_ae_mulauuzb4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x217860; +} + +static void +Opcode_ae_muluuzb3x3o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4280000; +} + +static void +Opcode_ae_mulauuzb3x3o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4180000; +} + +static void +Opcode_ae_mulzb8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002000; + slotbuf[1] = 0x2c0003; +} + +static void +Opcode_ae_mulazb8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002000; + slotbuf[1] = 0x2c0002; +} + +static void +Opcode_ae_mulzb4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x240003; +} + +static void +Opcode_ae_mulazb4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x240003; +} + +static void +Opcode_ae_mulzb8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2d8628; +} + +static void +Opcode_ae_mulazb8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2d2728; +} + +static void +Opcode_ae_mulzb8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2dc728; +} + +static void +Opcode_ae_mulazb8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2d6728; +} + +static void +Opcode_ae_mulzb2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2d0628; +} + +static void +Opcode_ae_mulazb2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2da728; +} + +static void +Opcode_ae_mulzb2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800; + slotbuf[1] = 0x2c0018; +} + +static void +Opcode_ae_mulazb2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; + slotbuf[1] = 0x2c0018; +} + +static void +Opcode_ae_mulzb4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x233860; +} + +static void +Opcode_ae_mulazb4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x231860; +} + +static void +Opcode_ae_mulzb4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x237860; +} + +static void +Opcode_ae_mulazb4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x235860; +} + +static void +Opcode_ae_mulzb3x3o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4000000; +} + +static void +Opcode_ae_mulazb3x3o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4040000; +} + +static void +Opcode_cvtsf16_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190c0026; + slotbuf[1] = 0; +} + +static void +Opcode_cvtsf16_l_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b7; +} + +static void +Opcode_cvtsf16_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a2f00; +} + +static void +Opcode_cvtsf16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190c0022; + slotbuf[1] = 0; +} + +static void +Opcode_cvtsf16_h_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b5; +} + +static void +Opcode_cvtsf16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a2b00; +} + +static void +Opcode_cvtf16s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1908002e; + slotbuf[1] = 0; +} + +static void +Opcode_cvtf16s_l_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b3; +} + +static void +Opcode_cvtf16s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2f00; +} + +static void +Opcode_cvtf16s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1908002a; + slotbuf[1] = 0; +} + +static void +Opcode_cvtf16s_h_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b1; +} + +static void +Opcode_cvtf16s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2b00; +} + +static void +Opcode_ae_movfcrfsrv_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4a0000; +} + +static void +Opcode_ae_movvfcrfsr_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4a8000; +} + +static void +Opcode_movt_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800e0; + slotbuf[1] = 0; +} + +static void +Opcode_movt_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481200; +} + +static void +Opcode_movt_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742e001; +} + +static void +Opcode_movf_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800d0; + slotbuf[1] = 0; +} + +static void +Opcode_movf_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480a00; +} + +static void +Opcode_movf_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742c001; +} + +static void +Opcode_moveqz_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d88000c; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04200; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480800; +} + +static void +Opcode_moveqz_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830000; +} + +static void +Opcode_movnez_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d88000a; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04b00; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481000; +} + +static void +Opcode_movnez_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98300c0; +} + +static void +Opcode_movgez_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880002; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04300; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480c00; +} + +static void +Opcode_movgez_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830040; +} + +static void +Opcode_movltz_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880006; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04a00; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480e00; +} + +static void +Opcode_movltz_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830080; +} + +static void +Opcode_rfr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929a04; +} + +static void +Opcode_wfr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e10c0; +} + +static void +Opcode_mul_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000020; + slotbuf[1] = 0x7; +} + +static void +Opcode_mul_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000020; + slotbuf[1] = 0x5; +} + +static void +Opcode_mul_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4300c00; + slotbuf[1] = 0; +} + +static void +Opcode_mul_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17001c0; +} + +static void +Opcode_mul_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae000080; + slotbuf[1] = 0; +} + +static void +Opcode_mul_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e000020; +} + +static void +Opcode_mul_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69003e0; +} + +static void +Opcode_mul_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003f; + slotbuf[1] = 0xe; +} + +static void +Opcode_madd_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; + slotbuf[1] = 0x7; +} + +static void +Opcode_madd_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000020; + slotbuf[1] = 0x5; +} + +static void +Opcode_madd_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe300800; + slotbuf[1] = 0; +} + +static void +Opcode_madd_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700160; +} + +static void +Opcode_madd_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8000080; + slotbuf[1] = 0; +} + +static void +Opcode_madd_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000020; +} + +static void +Opcode_madd_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900300; +} + +static void +Opcode_madd_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003c; + slotbuf[1] = 0xe; +} + +static void +Opcode_msub_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000020; + slotbuf[1] = 0x7; +} + +static void +Opcode_msub_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000020; + slotbuf[1] = 0x5; +} + +static void +Opcode_msub_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2300c00; + slotbuf[1] = 0; +} + +static void +Opcode_msub_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17001a0; +} + +static void +Opcode_msub_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac000080; + slotbuf[1] = 0; +} + +static void +Opcode_msub_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c000020; +} + +static void +Opcode_msub_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69003c0; +} + +static void +Opcode_msub_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003e; + slotbuf[1] = 0xe; +} + +static void +Opcode_msubn_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000020; + slotbuf[1] = 0x7; +} + +static void +Opcode_msubn_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44000020; + slotbuf[1] = 0x5; +} + +static void +Opcode_msubn_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0300c00; + slotbuf[1] = 0; +} + +static void +Opcode_msubn_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700180; +} + +static void +Opcode_msubn_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa000080; + slotbuf[1] = 0; +} + +static void +Opcode_msubn_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a000020; +} + +static void +Opcode_msubn_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69003a0; +} + +static void +Opcode_msubn_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003d; + slotbuf[1] = 0xe; +} + +static void +Opcode_maddn_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000020; + slotbuf[1] = 0x6; +} + +static void +Opcode_maddn_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000020; + slotbuf[1] = 0x4; +} + +static void +Opcode_maddn_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc300800; + slotbuf[1] = 0; +} + +static void +Opcode_maddn_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700140; +} + +static void +Opcode_maddn_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6000080; + slotbuf[1] = 0; +} + +static void +Opcode_maddn_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26000020; +} + +static void +Opcode_maddn_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69002e0; +} + +static void +Opcode_maddn_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003b; + slotbuf[1] = 0xe; +} + +static void +Opcode_add_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000022; + slotbuf[1] = 0x5; +} + +static void +Opcode_add_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000a0; + slotbuf[1] = 0x5; +} + +static void +Opcode_add_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a050000; + slotbuf[1] = 0; +} + +static void +Opcode_add_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1848000; +} + +static void +Opcode_add_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00021; + slotbuf[1] = 0; +} + +static void +Opcode_add_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000a0; +} + +static void +Opcode_add_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa048000; +} + +static void +Opcode_add_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068022; + slotbuf[1] = 0xe; +} + +static void +Opcode_sub_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000042; + slotbuf[1] = 0x5; +} + +static void +Opcode_sub_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000c0; + slotbuf[1] = 0x5; +} + +static void +Opcode_sub_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c050000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1870000; +} + +static void +Opcode_sub_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a000a1; + slotbuf[1] = 0; +} + +static void +Opcode_sub_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000c0; +} + +static void +Opcode_sub_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa050000; +} + +static void +Opcode_sub_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068042; + slotbuf[1] = 0xe; +} + +static void +Opcode_ole_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19200031; + slotbuf[1] = 0; +} + +static void +Opcode_ole_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640510; +} + +static void +Opcode_ole_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540081; +} + +static void +Opcode_ole_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022100; +} + +static void +Opcode_olt_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19240030; + slotbuf[1] = 0; +} + +static void +Opcode_olt_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640800; +} + +static void +Opcode_olt_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540090; +} + +static void +Opcode_olt_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022500; +} + +static void +Opcode_oeq_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19200030; + slotbuf[1] = 0; +} + +static void +Opcode_oeq_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640500; +} + +static void +Opcode_oeq_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540080; +} + +static void +Opcode_oeq_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022c00; +} + +static void +Opcode_un_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192c0030; + slotbuf[1] = 0; +} + +static void +Opcode_un_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640c00; +} + +static void +Opcode_un_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b0; +} + +static void +Opcode_un_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022600; +} + +static void +Opcode_ule_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19280030; + slotbuf[1] = 0; +} + +static void +Opcode_ule_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640900; +} + +static void +Opcode_ule_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400a0; +} + +static void +Opcode_ule_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022d00; +} + +static void +Opcode_ult_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19280031; + slotbuf[1] = 0; +} + +static void +Opcode_ult_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640910; +} + +static void +Opcode_ult_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400a1; +} + +static void +Opcode_ult_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022200; +} + +static void +Opcode_ueq_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19240031; + slotbuf[1] = 0; +} + +static void +Opcode_ueq_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640810; +} + +static void +Opcode_ueq_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540091; +} + +static void +Opcode_ueq_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022900; +} + +static void +Opcode_nexp01_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808008; + slotbuf[1] = 0x7; +} + +static void +Opcode_nexp01_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160004; + slotbuf[1] = 0x5; +} + +static void +Opcode_nexp01_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80211801; + slotbuf[1] = 0; +} + +static void +Opcode_nexp01_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700202; +} + +static void +Opcode_nexp01_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0c08001; + slotbuf[1] = 0; +} + +static void +Opcode_nexp01_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c45801d; +} + +static void +Opcode_nexp01_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa600026; +} + +static void +Opcode_nexp01_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40381002; + slotbuf[1] = 0xe; +} + +static void +Opcode_mksadj_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808004; + slotbuf[1] = 0x7; +} + +static void +Opcode_mksadj_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160003; + slotbuf[1] = 0x5; +} + +static void +Opcode_mksadj_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80111801; + slotbuf[1] = 0; +} + +static void +Opcode_mksadj_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700201; +} + +static void +Opcode_mksadj_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8c08001; + slotbuf[1] = 0; +} + +static void +Opcode_mksadj_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c35801d; +} + +static void +Opcode_mksadj_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa500026; +} + +static void +Opcode_mksadj_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40281002; + slotbuf[1] = 0xe; +} + +static void +Opcode_mkdadj_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000062; + slotbuf[1] = 0x6; +} + +static void +Opcode_mkdadj_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000e2; + slotbuf[1] = 0x5; +} + +static void +Opcode_mkdadj_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6390c00; + slotbuf[1] = 0; +} + +static void +Opcode_mkdadj_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17901e0; +} + +static void +Opcode_mkdadj_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab002c1; + slotbuf[1] = 0; +} + +static void +Opcode_mkdadj_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000e2; +} + +static void +Opcode_mkdadj_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa458000; +} + +static void +Opcode_mkdadj_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068862; + slotbuf[1] = 0xe; +} + +static void +Opcode_div0_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808003; + slotbuf[1] = 0x7; +} + +static void +Opcode_div0_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160001; + slotbuf[1] = 0x5; +} + +static void +Opcode_div0_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80011801; + slotbuf[1] = 0; +} + +static void +Opcode_div0_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700200; +} + +static void +Opcode_div0_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6c08001; + slotbuf[1] = 0; +} + +static void +Opcode_div0_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c15801d; +} + +static void +Opcode_div0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa500025; +} + +static void +Opcode_div0_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401f1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_sqrt0_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800b; + slotbuf[1] = 0x7; +} + +static void +Opcode_sqrt0_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160007; + slotbuf[1] = 0x5; +} + +static void +Opcode_sqrt0_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80511801; + slotbuf[1] = 0; +} + +static void +Opcode_sqrt0_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700205; +} + +static void +Opcode_sqrt0_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6c08001; + slotbuf[1] = 0; +} + +static void +Opcode_sqrt0_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c75801d; +} + +static void +Opcode_sqrt0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa700025; +} + +static void +Opcode_sqrt0_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40291002; + slotbuf[1] = 0xe; +} + +static void +Opcode_recip0_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808009; + slotbuf[1] = 0x7; +} + +static void +Opcode_recip0_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160005; + slotbuf[1] = 0x5; +} + +static void +Opcode_recip0_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80311801; + slotbuf[1] = 0; +} + +static void +Opcode_recip0_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700203; +} + +static void +Opcode_recip0_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2c08001; + slotbuf[1] = 0; +} + +static void +Opcode_recip0_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c55801d; +} + +static void +Opcode_recip0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa600027; +} + +static void +Opcode_recip0_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40289002; + slotbuf[1] = 0xe; +} + +static void +Opcode_rsqrt0_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800a; + slotbuf[1] = 0x7; +} + +static void +Opcode_rsqrt0_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160006; + slotbuf[1] = 0x5; +} + +static void +Opcode_rsqrt0_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80411801; + slotbuf[1] = 0; +} + +static void +Opcode_rsqrt0_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700204; +} + +static void +Opcode_rsqrt0_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4c08001; + slotbuf[1] = 0; +} + +static void +Opcode_rsqrt0_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c65801d; +} + +static void +Opcode_rsqrt0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa700024; +} + +static void +Opcode_rsqrt0_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40389002; + slotbuf[1] = 0xe; +} + +static void +Opcode_divn_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000020; + slotbuf[1] = 0x6; +} + +static void +Opcode_divn_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000020; + slotbuf[1] = 0x4; +} + +static void +Opcode_divn_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa300800; + slotbuf[1] = 0; +} + +static void +Opcode_divn_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700120; +} + +static void +Opcode_divn_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4000080; + slotbuf[1] = 0; +} + +static void +Opcode_divn_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000020; +} + +static void +Opcode_divn_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69002c0; +} + +static void +Opcode_divn_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003a; + slotbuf[1] = 0xe; +} + +static void +Opcode_addexp_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000061; + slotbuf[1] = 0x6; +} + +static void +Opcode_addexp_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000e1; + slotbuf[1] = 0x5; +} + +static void +Opcode_addexp_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6388c00; + slotbuf[1] = 0; +} + +static void +Opcode_addexp_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17881e0; +} + +static void +Opcode_addexp_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00261; + slotbuf[1] = 0; +} + +static void +Opcode_addexp_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000e1; +} + +static void +Opcode_addexp_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa358000; +} + +static void +Opcode_addexp_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068462; + slotbuf[1] = 0xe; +} + +static void +Opcode_addexpm_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000060; + slotbuf[1] = 0x6; +} + +static void +Opcode_addexpm_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000e0; + slotbuf[1] = 0x5; +} + +static void +Opcode_addexpm_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6380c00; + slotbuf[1] = 0; +} + +static void +Opcode_addexpm_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17801e0; +} + +static void +Opcode_addexpm_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00241; + slotbuf[1] = 0; +} + +static void +Opcode_addexpm_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000e0; +} + +static void +Opcode_addexpm_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa258000; +} + +static void +Opcode_addexpm_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068062; + slotbuf[1] = 0xe; +} + +static void +Opcode_min_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000040; + slotbuf[1] = 0x6; +} + +static void +Opcode_min_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205001b; + slotbuf[1] = 0x5; +} + +static void +Opcode_min_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c048000; + slotbuf[1] = 0; +} + +static void +Opcode_min_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1830000; +} + +static void +Opcode_min_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00141; + slotbuf[1] = 0; +} + +static void +Opcode_min_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05001b; +} + +static void +Opcode_min_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa030000; +} + +static void +Opcode_min_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400d8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_max_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000060; + slotbuf[1] = 0x6; +} + +static void +Opcode_max_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82058019; + slotbuf[1] = 0x5; +} + +static void +Opcode_max_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e040000; + slotbuf[1] = 0; +} + +static void +Opcode_max_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1818000; +} + +static void +Opcode_max_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00181; + slotbuf[1] = 0; +} + +static void +Opcode_max_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c058019; +} + +static void +Opcode_max_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa018000; +} + +static void +Opcode_max_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_mulmux_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulmux_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000020; + slotbuf[1] = 0x4; +} + +static void +Opcode_mulmux_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0300000; + slotbuf[1] = 0; +} + +static void +Opcode_mulmux_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000080; + slotbuf[1] = 0; +} + +static void +Opcode_mulmux_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000020; +} + +static void +Opcode_mulmux_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00000; +} + +static void +Opcode_mulmux_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80100038; + slotbuf[1] = 0xe; +} + +static void +Opcode_maddmux_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_maddmux_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_maddmux_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0300000; + slotbuf[1] = 0; +} + +static void +Opcode_maddmux_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000000; + slotbuf[1] = 0; +} + +static void +Opcode_maddmux_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000000; +} + +static void +Opcode_maddmux_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00000; +} + +static void +Opcode_maddmux_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000038; + slotbuf[1] = 0xe; +} + +static void +Opcode_trunc_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19030010; + slotbuf[1] = 0; +} + +static void +Opcode_trunc_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800010; +} + +static void +Opcode_trunc_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1308; +} + +static void +Opcode_utrunc_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19032010; + slotbuf[1] = 0; +} + +static void +Opcode_utrunc_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2802010; +} + +static void +Opcode_utrunc_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9208; +} + +static void +Opcode_trunc_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000024; + slotbuf[1] = 0; +} + +static void +Opcode_trunc_sx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800002; +} + +static void +Opcode_trunc_sx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c06000; +} + +static void +Opcode_utrunc_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900002c; + slotbuf[1] = 0; +} + +static void +Opcode_utrunc_sx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800006; +} + +static void +Opcode_utrunc_sx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c02001; +} + +static void +Opcode_ficeil_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190c002a; + slotbuf[1] = 0; +} + +static void +Opcode_ficeil_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b9; +} + +static void +Opcode_ficeil_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62a2b00; +} + +static void +Opcode_fifloor_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190c002e; + slotbuf[1] = 0; +} + +static void +Opcode_fifloor_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400bb; +} + +static void +Opcode_fifloor_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62a2f00; +} + +static void +Opcode_firint_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19100022; + slotbuf[1] = 0; +} + +static void +Opcode_firint_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400bd; +} + +static void +Opcode_firint_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63a2b00; +} + +static void +Opcode_firound_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19100026; + slotbuf[1] = 0; +} + +static void +Opcode_firound_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400bf; +} + +static void +Opcode_firound_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63a2f00; +} + +static void +Opcode_fitrunc_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1910002a; + slotbuf[1] = 0; +} + +static void +Opcode_fitrunc_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800008; +} + +static void +Opcode_fitrunc_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380f00; +} + +static void +Opcode_float_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18800b00; + slotbuf[1] = 0; +} + +static void +Opcode_float_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000000; +} + +static void +Opcode_float_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00100; +} + +static void +Opcode_ufloat_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18800b04; + slotbuf[1] = 0; +} + +static void +Opcode_ufloat_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000002; +} + +static void +Opcode_ufloat_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00140; +} + +static void +Opcode_float_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000020; + slotbuf[1] = 0; +} + +static void +Opcode_float_sx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800000; +} + +static void +Opcode_float_sx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04000; +} + +static void +Opcode_ufloat_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000028; + slotbuf[1] = 0; +} + +static void +Opcode_ufloat_sx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800004; +} + +static void +Opcode_ufloat_sx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00001; +} + +static void +Opcode_abs_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808000; + slotbuf[1] = 0x7; +} + +static void +Opcode_abs_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160008; + slotbuf[1] = 0x5; +} + +static void +Opcode_abs_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000a; + slotbuf[1] = 0; +} + +static void +Opcode_abs_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80611801; + slotbuf[1] = 0; +} + +static void +Opcode_abs_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700206; +} + +static void +Opcode_abs_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c08001; + slotbuf[1] = 0; +} + +static void +Opcode_abs_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c85801d; +} + +static void +Opcode_abs_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa400026; +} + +static void +Opcode_abs_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40391002; + slotbuf[1] = 0xe; +} + +static void +Opcode_neg_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808007; + slotbuf[1] = 0x7; +} + +static void +Opcode_neg_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000d; + slotbuf[1] = 0x5; +} + +static void +Opcode_neg_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2800a; + slotbuf[1] = 0; +} + +static void +Opcode_neg_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80b11801; + slotbuf[1] = 0; +} + +static void +Opcode_neg_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020b; +} + +static void +Opcode_neg_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcec08001; + slotbuf[1] = 0; +} + +static void +Opcode_neg_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cd5801d; +} + +static void +Opcode_neg_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa600025; +} + +static void +Opcode_neg_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402a9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_conjc_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808002; + slotbuf[1] = 0x7; +} + +static void +Opcode_conjc_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000a; + slotbuf[1] = 0x5; +} + +static void +Opcode_conjc_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d1000a; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80811801; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700208; +} + +static void +Opcode_conjc_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4c08001; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca5801d; +} + +static void +Opcode_conjc_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa500024; +} + +static void +Opcode_conjc_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40399002; + slotbuf[1] = 0xe; +} + +static void +Opcode_muljc_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808006; + slotbuf[1] = 0x7; +} + +static void +Opcode_muljc_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000c; + slotbuf[1] = 0x5; +} + +static void +Opcode_muljc_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2000a; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a11801; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020a; +} + +static void +Opcode_muljc_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xccc08001; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc5801d; +} + +static void +Opcode_muljc_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa600024; +} + +static void +Opcode_muljc_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403a1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_const_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808011; + slotbuf[1] = 0x7; +} + +static void +Opcode_const_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160013; + slotbuf[1] = 0x5; +} + +static void +Opcode_const_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3000b; + slotbuf[1] = 0; +} + +static void +Opcode_const_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81011a01; + slotbuf[1] = 0; +} + +static void +Opcode_const_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700211; +} + +static void +Opcode_const_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdec0c001; + slotbuf[1] = 0; +} + +static void +Opcode_const_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d25c01d; +} + +static void +Opcode_const_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00025; +} + +static void +Opcode_const_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44300003; + slotbuf[1] = 0xe; +} + +static void +Opcode_clsfy_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82810000; + slotbuf[1] = 0x7; +} + +static void +Opcode_clsfy_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160000; + slotbuf[1] = 0x5; +} + +static void +Opcode_clsfy_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e050000; + slotbuf[1] = 0; +} + +static void +Opcode_clsfy_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1878000; +} + +static void +Opcode_clsfy_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c10001; + slotbuf[1] = 0; +} + +static void +Opcode_clsfy_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05801d; +} + +static void +Opcode_clsfy_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000021; +} + +static void +Opcode_clsfy_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401e9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_minnum_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000060; + slotbuf[1] = 0x6; +} + +static void +Opcode_minnum_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205801a; + slotbuf[1] = 0x5; +} + +static void +Opcode_minnum_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a048000; + slotbuf[1] = 0; +} + +static void +Opcode_minnum_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1828000; +} + +static void +Opcode_minnum_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a000c1; + slotbuf[1] = 0; +} + +static void +Opcode_minnum_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05801a; +} + +static void +Opcode_minnum_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa028000; +} + +static void +Opcode_minnum_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400d0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_maxnum_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000040; + slotbuf[1] = 0x6; +} + +static void +Opcode_maxnum_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82050019; + slotbuf[1] = 0x5; +} + +static void +Opcode_maxnum_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c040000; + slotbuf[1] = 0; +} + +static void +Opcode_maxnum_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1810000; +} + +static void +Opcode_maxnum_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00101; + slotbuf[1] = 0; +} + +static void +Opcode_maxnum_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c050019; +} + +static void +Opcode_maxnum_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa010000; +} + +static void +Opcode_maxnum_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400b8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_addandsub_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000001; + slotbuf[1] = 0x5; +} + +static void +Opcode_addandsub_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82048000; + slotbuf[1] = 0x5; +} + +static void +Opcode_addandsub_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80019000; + slotbuf[1] = 0; +} + +static void +Opcode_addandsub_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addandsub_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0900001; + slotbuf[1] = 0; +} + +static void +Opcode_addandsub_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c048000; +} + +static void +Opcode_addandsub_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000140; +} + +static void +Opcode_addandsub_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40048002; + slotbuf[1] = 0xe; +} + +static void +Opcode_addandsubjc_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_addandsubjc_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82040000; + slotbuf[1] = 0x5; +} + +static void +Opcode_addandsubjc_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80011000; + slotbuf[1] = 0; +} + +static void +Opcode_addandsubjc_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_addandsubjc_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0800001; + slotbuf[1] = 0; +} + +static void +Opcode_addandsubjc_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c040000; +} + +static void +Opcode_addandsubjc_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000120; +} + +static void +Opcode_addandsubjc_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40060002; + slotbuf[1] = 0xe; +} + +static void +Opcode_add_hl_lh_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000002; + slotbuf[1] = 0x5; +} + +static void +Opcode_add_hl_lh_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000080; + slotbuf[1] = 0x5; +} + +static void +Opcode_add_hl_lh_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88050000; + slotbuf[1] = 0; +} + +static void +Opcode_add_hl_lh_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1840000; +} + +static void +Opcode_add_hl_lh_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a001c1; + slotbuf[1] = 0; +} + +static void +Opcode_add_hl_lh_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000080; +} + +static void +Opcode_add_hl_lh_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa040000; +} + +static void +Opcode_add_hl_lh_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068002; + slotbuf[1] = 0xe; +} + +static void +Opcode_madda_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_madda_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_madda_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000000; + slotbuf[1] = 0; +} + +static void +Opcode_madda_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000000; + slotbuf[1] = 0; +} + +static void +Opcode_madda_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000000; +} + +static void +Opcode_madda_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5800000; +} + +static void +Opcode_madda_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000034; + slotbuf[1] = 0xe; +} + +static void +Opcode_frexp_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000040; + slotbuf[1] = 0x6; +} + +static void +Opcode_frexp_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82050018; + slotbuf[1] = 0x5; +} + +static void +Opcode_frexp_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88040000; + slotbuf[1] = 0; +} + +static void +Opcode_frexp_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; +} + +static void +Opcode_frexp_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00001; + slotbuf[1] = 0; +} + +static void +Opcode_frexp_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c050018; +} + +static void +Opcode_frexp_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; +} + +static void +Opcode_frexp_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400a8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_floatexp_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82810020; + slotbuf[1] = 0x7; +} + +static void +Opcode_floatexp_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160002; + slotbuf[1] = 0x5; +} + +static void +Opcode_floatexp_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e050001; + slotbuf[1] = 0; +} + +static void +Opcode_floatexp_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1878001; +} + +static void +Opcode_floatexp_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c10021; + slotbuf[1] = 0; +} + +static void +Opcode_floatexp_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c25801d; +} + +static void +Opcode_floatexp_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa008021; +} + +static void +Opcode_floatexp_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401f9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_minnumabs_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000040; + slotbuf[1] = 0x6; +} + +static void +Opcode_minnumabs_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205001a; + slotbuf[1] = 0x5; +} + +static void +Opcode_minnumabs_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88048000; + slotbuf[1] = 0; +} + +static void +Opcode_minnumabs_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1820000; +} + +static void +Opcode_minnumabs_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00041; + slotbuf[1] = 0; +} + +static void +Opcode_minnumabs_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05001a; +} + +static void +Opcode_minnumabs_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa020000; +} + +static void +Opcode_minnumabs_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_maxnumabs_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000060; + slotbuf[1] = 0x6; +} + +static void +Opcode_maxnumabs_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82058018; + slotbuf[1] = 0x5; +} + +static void +Opcode_maxnumabs_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a040000; + slotbuf[1] = 0; +} + +static void +Opcode_maxnumabs_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1808000; +} + +static void +Opcode_maxnumabs_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00081; + slotbuf[1] = 0; +} + +static void +Opcode_maxnumabs_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c058018; +} + +static void +Opcode_maxnumabs_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa008000; +} + +static void +Opcode_maxnumabs_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400b0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_mulq_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_mulq_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulq_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98000000; + slotbuf[1] = 0; +} + +static void +Opcode_mulq_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000000; +} + +static void +Opcode_maddq_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_maddq_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_maddq_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94000000; + slotbuf[1] = 0; +} + +static void +Opcode_maddq_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000000; +} + +static void +Opcode_msubq_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_msubq_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_msubq_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96000000; + slotbuf[1] = 0; +} + +static void +Opcode_msubq_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000000; +} + +static void +Opcode_mulmuxq_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulmuxq_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_mulmuxq_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000000; + slotbuf[1] = 0; +} + +static void +Opcode_mulmuxq_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; +} + +static void +Opcode_maddmuxq_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x6; +} + +static void +Opcode_maddmuxq_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4; +} + +static void +Opcode_maddmuxq_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_maddmuxq_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_bmaxnum_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82058008; + slotbuf[1] = 0x5; +} + +static void +Opcode_bmaxnum_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82040000; + slotbuf[1] = 0; +} + +static void +Opcode_bmaxnum_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c058008; +} + +static void +Opcode_bmaxnum_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c0402; + slotbuf[1] = 0xe; +} + +static void +Opcode_bminnum_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82058010; + slotbuf[1] = 0x5; +} + +static void +Opcode_bminnum_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86040000; + slotbuf[1] = 0; +} + +static void +Opcode_bminnum_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c058010; +} + +static void +Opcode_bminnum_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c0802; + slotbuf[1] = 0xe; +} + +static void +Opcode_bmaxnumabs_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82058000; + slotbuf[1] = 0x5; +} + +static void +Opcode_bmaxnumabs_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80040000; + slotbuf[1] = 0; +} + +static void +Opcode_bmaxnumabs_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c058000; +} + +static void +Opcode_bmaxnumabs_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40080402; + slotbuf[1] = 0xe; +} + +static void +Opcode_bminnumabs_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82050010; + slotbuf[1] = 0x5; +} + +static void +Opcode_bminnumabs_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84040000; + slotbuf[1] = 0; +} + +static void +Opcode_bminnumabs_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c050010; +} + +static void +Opcode_bminnumabs_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40080802; + slotbuf[1] = 0xe; +} + +static void +Opcode_abs_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82100000; + slotbuf[1] = 0x7; +} + +static void +Opcode_abs_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82008000; + slotbuf[1] = 0x5; +} + +static void +Opcode_abs_sx2x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80018000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_sx2x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_abs_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0100001; + slotbuf[1] = 0; +} + +static void +Opcode_abs_sx2x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c008000; +} + +static void +Opcode_abs_sx2x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000020; +} + +static void +Opcode_abs_sx2x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40008002; + slotbuf[1] = 0xe; +} + +static void +Opcode_neg_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82700000; + slotbuf[1] = 0x7; +} + +static void +Opcode_neg_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82038000; + slotbuf[1] = 0x5; +} + +static void +Opcode_neg_sx2x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; + slotbuf[1] = 0; +} + +static void +Opcode_neg_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80018c00; + slotbuf[1] = 0; +} + +static void +Opcode_neg_sx2x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_neg_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0700001; + slotbuf[1] = 0; +} + +static void +Opcode_neg_sx2x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c038000; +} + +static void +Opcode_neg_sx2x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000e0; +} + +static void +Opcode_neg_sx2x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40040002; + slotbuf[1] = 0xe; +} + +static void +Opcode_conjc_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82300000; + slotbuf[1] = 0x7; +} + +static void +Opcode_conjc_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82018000; + slotbuf[1] = 0x5; +} + +static void +Opcode_conjc_sx2x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80018400; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_sx2x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_conjc_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0300001; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_sx2x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c018000; +} + +static void +Opcode_conjc_sx2x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000060; +} + +static void +Opcode_conjc_sx2x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40010002; + slotbuf[1] = 0xe; +} + +static void +Opcode_muljc_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82500000; + slotbuf[1] = 0x7; +} + +static void +Opcode_muljc_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82028000; + slotbuf[1] = 0x5; +} + +static void +Opcode_muljc_sx2x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80018800; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_sx2x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_muljc_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0500001; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_sx2x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c028000; +} + +static void +Opcode_muljc_sx2x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000a0; +} + +static void +Opcode_muljc_sx2x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40018002; + slotbuf[1] = 0xe; +} + +static void +Opcode_const_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82804000; + slotbuf[1] = 0x7; +} + +static void +Opcode_const_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82064000; + slotbuf[1] = 0x5; +} + +static void +Opcode_const_sx2x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00003; + slotbuf[1] = 0; +} + +static void +Opcode_const_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80011a00; + slotbuf[1] = 0; +} + +static void +Opcode_const_sx2x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1904001; +} + +static void +Opcode_const_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c04001; + slotbuf[1] = 0; +} + +static void +Opcode_const_sx2x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c064000; +} + +static void +Opcode_const_sx2x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa004020; +} + +static void +Opcode_const_sx2x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46000003; + slotbuf[1] = 0xe; +} + +static void +Opcode_add_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_add_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_add_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_sub_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_sub_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_mul_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x3; +} + +static void +Opcode_mul_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x3; +} + +static void +Opcode_madd_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_madd_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_msub_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_msub_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_mulmux_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_mulmux_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_maddmux_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_maddmux_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_abs_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800c; + slotbuf[1] = 0x7; +} + +static void +Opcode_abs_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000e; + slotbuf[1] = 0x5; +} + +static void +Opcode_abs_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03001; + slotbuf[1] = 0; +} + +static void +Opcode_abs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80c11801; + slotbuf[1] = 0; +} + +static void +Opcode_abs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020c; +} + +static void +Opcode_abs_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8c08001; + slotbuf[1] = 0; +} + +static void +Opcode_abs_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce5801d; +} + +static void +Opcode_abs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf58000; +} + +static void +Opcode_abs_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403a9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_addexp_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000064; + slotbuf[1] = 0x6; +} + +static void +Opcode_addexp_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000e4; + slotbuf[1] = 0x5; +} + +static void +Opcode_addexp_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63f0c00; + slotbuf[1] = 0; +} + +static void +Opcode_addexp_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a01e0; +} + +static void +Opcode_addexp_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00341; + slotbuf[1] = 0; +} + +static void +Opcode_addexp_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000e4; +} + +static void +Opcode_addexp_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa700027; +} + +static void +Opcode_addexp_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40069062; + slotbuf[1] = 0xe; +} + +static void +Opcode_addexpm_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000063; + slotbuf[1] = 0x6; +} + +static void +Opcode_addexpm_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000e3; + slotbuf[1] = 0x5; +} + +static void +Opcode_addexpm_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63e8c00; + slotbuf[1] = 0; +} + +static void +Opcode_addexpm_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17981e0; +} + +static void +Opcode_addexpm_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab002e1; + slotbuf[1] = 0; +} + +static void +Opcode_addexpm_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000e3; +} + +static void +Opcode_addexpm_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa700026; +} + +static void +Opcode_addexpm_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_clsfy_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800d; + slotbuf[1] = 0x7; +} + +static void +Opcode_clsfy_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000f; + slotbuf[1] = 0x5; +} + +static void +Opcode_clsfy_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80d11801; + slotbuf[1] = 0; +} + +static void +Opcode_clsfy_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020d; +} + +static void +Opcode_clsfy_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdac08001; + slotbuf[1] = 0; +} + +static void +Opcode_clsfy_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cf5801d; +} + +static void +Opcode_clsfy_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb058000; +} + +static void +Opcode_clsfy_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402b1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_conjc_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808001; + slotbuf[1] = 0x7; +} + +static void +Opcode_conjc_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160009; + slotbuf[1] = 0x5; +} + +static void +Opcode_conjc_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0800a; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80711801; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700207; +} + +static void +Opcode_conjc_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2c08001; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c95801d; +} + +static void +Opcode_conjc_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa400027; +} + +static void +Opcode_conjc_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40299002; + slotbuf[1] = 0xe; +} + +static void +Opcode_const_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808010; + slotbuf[1] = 0x7; +} + +static void +Opcode_const_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160012; + slotbuf[1] = 0x5; +} + +static void +Opcode_const_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3000a; + slotbuf[1] = 0; +} + +static void +Opcode_const_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81011801; + slotbuf[1] = 0; +} + +static void +Opcode_const_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700210; +} + +static void +Opcode_const_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdec08001; + slotbuf[1] = 0; +} + +static void +Opcode_const_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d25801d; +} + +static void +Opcode_const_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00024; +} + +static void +Opcode_const_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44200003; + slotbuf[1] = 0xe; +} + +static void +Opcode_min_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4100003; + slotbuf[1] = 0x6; +} + +static void +Opcode_min_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205001d; + slotbuf[1] = 0x5; +} + +static void +Opcode_min_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80119400; + slotbuf[1] = 0; +} + +static void +Opcode_min_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700100; +} + +static void +Opcode_min_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6b00001; + slotbuf[1] = 0; +} + +static void +Opcode_min_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05001d; +} + +static void +Opcode_min_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900380; +} + +static void +Opcode_min_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400f8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_max_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000003; + slotbuf[1] = 0x6; +} + +static void +Opcode_max_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205001c; + slotbuf[1] = 0x5; +} + +static void +Opcode_max_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80019400; + slotbuf[1] = 0; +} + +static void +Opcode_max_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000c0; +} + +static void +Opcode_max_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2b00001; + slotbuf[1] = 0; +} + +static void +Opcode_max_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05001c; +} + +static void +Opcode_max_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900340; +} + +static void +Opcode_max_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400e8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_minnum_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4100002; + slotbuf[1] = 0x6; +} + +static void +Opcode_minnum_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205801c; + slotbuf[1] = 0x5; +} + +static void +Opcode_minnum_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80111400; + slotbuf[1] = 0; +} + +static void +Opcode_minnum_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000e0; +} + +static void +Opcode_minnum_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4b00001; + slotbuf[1] = 0; +} + +static void +Opcode_minnum_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05801c; +} + +static void +Opcode_minnum_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900360; +} + +static void +Opcode_minnum_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400f0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_maxnum_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000002; + slotbuf[1] = 0x6; +} + +static void +Opcode_maxnum_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205801b; + slotbuf[1] = 0x5; +} + +static void +Opcode_maxnum_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80011400; + slotbuf[1] = 0; +} + +static void +Opcode_maxnum_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000a0; +} + +static void +Opcode_maxnum_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0b00001; + slotbuf[1] = 0; +} + +static void +Opcode_maxnum_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05801b; +} + +static void +Opcode_maxnum_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900320; +} + +static void +Opcode_maxnum_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400e0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_muljc_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808005; + slotbuf[1] = 0x7; +} + +static void +Opcode_muljc_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000b; + slotbuf[1] = 0x5; +} + +static void +Opcode_muljc_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d1800a; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80911801; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700209; +} + +static void +Opcode_muljc_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcac08001; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cb5801d; +} + +static void +Opcode_muljc_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa500027; +} + +static void +Opcode_muljc_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402a1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_neg_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800e; + slotbuf[1] = 0x7; +} + +static void +Opcode_neg_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160010; + slotbuf[1] = 0x5; +} + +static void +Opcode_neg_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03011; + slotbuf[1] = 0; +} + +static void +Opcode_neg_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80e11801; + slotbuf[1] = 0; +} + +static void +Opcode_neg_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020e; +} + +static void +Opcode_neg_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdcc08001; + slotbuf[1] = 0; +} + +static void +Opcode_neg_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d05801d; +} + +static void +Opcode_neg_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb158000; +} + +static void +Opcode_neg_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403b1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_oeq_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2e00; +} + +static void +Opcode_ole_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022300; +} + +static void +Opcode_olt_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022700; +} + +static void +Opcode_ueq_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022b00; +} + +static void +Opcode_ule_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022f00; +} + +static void +Opcode_ult_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2300; +} + +static void +Opcode_un_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2700; +} + +static void +Opcode_div0_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800027; +} + +static void +Opcode_ficeil_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19184030; + slotbuf[1] = 0; +} + +static void +Opcode_ficeil_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0430a; +} + +static void +Opcode_fifloor_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19186030; + slotbuf[1] = 0; +} + +static void +Opcode_fifloor_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0630a; +} + +static void +Opcode_firint_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1918c030; + slotbuf[1] = 0; +} + +static void +Opcode_firint_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0430b; +} + +static void +Opcode_firound_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1918e030; + slotbuf[1] = 0; +} + +static void +Opcode_firound_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0630b; +} + +static void +Opcode_fitrunc_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19194030; + slotbuf[1] = 0; +} + +static void +Opcode_fitrunc_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0020c; +} + +static void +Opcode_mkdadj_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb258000; +} + +static void +Opcode_mksadj_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa900024; +} + +static void +Opcode_nexp0_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa900026; +} + +static void +Opcode_nexp01_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa900025; +} + +static void +Opcode_recip0_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa900027; +} + +static void +Opcode_rsqrt0_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa00024; +} + +static void +Opcode_sqrt0_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa00025; +} + +static void +Opcode_float16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18980f00; + slotbuf[1] = 0; +} + +static void +Opcode_float16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c01200; +} + +static void +Opcode_ufloat16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x189a0f00; + slotbuf[1] = 0; +} + +static void +Opcode_ufloat16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c01240; +} + +static void +Opcode_trunc16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19300030; + slotbuf[1] = 0; +} + +static void +Opcode_trunc16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c01208; +} + +static void +Opcode_utrunc16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19320030; + slotbuf[1] = 0; +} + +static void +Opcode_utrunc16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c01608; +} + +static void +Opcode_float16_hx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d820000; + slotbuf[1] = 0; +} + +static void +Opcode_float16_hx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00200; +} + +static void +Opcode_ufloat16_hx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d820020; + slotbuf[1] = 0; +} + +static void +Opcode_ufloat16_hx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04200; +} + +static void +Opcode_trunc16_hx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d820010; + slotbuf[1] = 0; +} + +static void +Opcode_trunc16_hx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c02200; +} + +static void +Opcode_utrunc16_hx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d820030; + slotbuf[1] = 0; +} + +static void +Opcode_utrunc16_hx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c06200; +} + +static void +Opcode_add_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000001; + slotbuf[1] = 0x6; +} + +static void +Opcode_add_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000040; + slotbuf[1] = 0x5; +} + +static void +Opcode_add_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0118000; + slotbuf[1] = 0; +} + +static void +Opcode_add_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1838000; +} + +static void +Opcode_add_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000080; + slotbuf[1] = 0; +} + +static void +Opcode_add_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000040; +} + +static void +Opcode_add_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8148000; +} + +static void +Opcode_add_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_sub_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000a1; + slotbuf[1] = 0x6; +} + +static void +Opcode_sub_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000062; + slotbuf[1] = 0x5; +} + +static void +Opcode_sub_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc118000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1868000; +} + +static void +Opcode_sub_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000085; + slotbuf[1] = 0; +} + +static void +Opcode_sub_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000062; +} + +static void +Opcode_sub_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8178000; +} + +static void +Opcode_sub_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006062; + slotbuf[1] = 0xe; +} + +static void +Opcode_mul_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000081; + slotbuf[1] = 0x6; +} + +static void +Opcode_mul_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000042; + slotbuf[1] = 0x5; +} + +static void +Opcode_mul_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca118000; + slotbuf[1] = 0; +} + +static void +Opcode_mul_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1860000; +} + +static void +Opcode_mul_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000084; + slotbuf[1] = 0; +} + +static void +Opcode_mul_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000042; +} + +static void +Opcode_mul_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8170000; +} + +static void +Opcode_mul_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_madd_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000021; + slotbuf[1] = 0x6; +} + +static void +Opcode_madd_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000060; + slotbuf[1] = 0x5; +} + +static void +Opcode_madd_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6118000; + slotbuf[1] = 0; +} + +static void +Opcode_madd_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1850000; +} + +static void +Opcode_madd_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000081; + slotbuf[1] = 0; +} + +static void +Opcode_madd_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000060; +} + +static void +Opcode_madd_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8160000; +} + +static void +Opcode_madd_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005062; + slotbuf[1] = 0xe; +} + +static void +Opcode_msub_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000061; + slotbuf[1] = 0x6; +} + +static void +Opcode_msub_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000061; + slotbuf[1] = 0x5; +} + +static void +Opcode_msub_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8118000; + slotbuf[1] = 0; +} + +static void +Opcode_msub_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1858000; +} + +static void +Opcode_msub_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000083; + slotbuf[1] = 0; +} + +static void +Opcode_msub_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000061; +} + +static void +Opcode_msub_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8168000; +} + +static void +Opcode_msub_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005862; + slotbuf[1] = 0xe; +} + +static void +Opcode_maddn_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4118000; + slotbuf[1] = 0; +} + +static void +Opcode_maddn_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8158000; +} + +static void +Opcode_msubn_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000041; + slotbuf[1] = 0x6; +} + +static void +Opcode_msubn_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000041; + slotbuf[1] = 0x5; +} + +static void +Opcode_msubn_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000082; + slotbuf[1] = 0; +} + +static void +Opcode_msubn_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000041; +} + +static void +Opcode_msubn_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005462; + slotbuf[1] = 0xe; +} + +static void +Opcode_divn_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2118000; + slotbuf[1] = 0; +} + +static void +Opcode_divn_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8150000; +} + +static void +Opcode_rminnum_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1919e030; + slotbuf[1] = 0; +} + +static void +Opcode_rminnum_h_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540ae0; +} + +static void +Opcode_rminnum_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0620c; +} + +static void +Opcode_rmaxnum_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1919c030; + slotbuf[1] = 0; +} + +static void +Opcode_rmaxnum_h_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25406e0; +} + +static void +Opcode_rmaxnum_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0420c; +} + +static void +Opcode_abs_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_abs_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_abs_hx4x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_hx4x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80010000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_hx4x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000001; + slotbuf[1] = 0; +} + +static void +Opcode_abs_hx4x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000000; +} + +static void +Opcode_abs_hx4x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; +} + +static void +Opcode_abs_hx4x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40020002; + slotbuf[1] = 0xe; +} + +static void +Opcode_neg_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82600000; + slotbuf[1] = 0x7; +} + +static void +Opcode_neg_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82030000; + slotbuf[1] = 0x5; +} + +static void +Opcode_neg_hx4x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; + slotbuf[1] = 0; +} + +static void +Opcode_neg_hx4x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80010c00; + slotbuf[1] = 0; +} + +static void +Opcode_neg_hx4x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0600001; + slotbuf[1] = 0; +} + +static void +Opcode_neg_hx4x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c030000; +} + +static void +Opcode_neg_hx4x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000c0; +} + +static void +Opcode_neg_hx4x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40038002; + slotbuf[1] = 0xe; +} + +static void +Opcode_conjc_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82200000; + slotbuf[1] = 0x7; +} + +static void +Opcode_conjc_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82010000; + slotbuf[1] = 0x5; +} + +static void +Opcode_conjc_hx4x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_hx4x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80010400; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_hx4x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200001; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_hx4x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c010000; +} + +static void +Opcode_conjc_hx4x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000040; +} + +static void +Opcode_conjc_hx4x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40028002; + slotbuf[1] = 0xe; +} + +static void +Opcode_const_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82800000; + slotbuf[1] = 0x7; +} + +static void +Opcode_const_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82060000; + slotbuf[1] = 0x5; +} + +static void +Opcode_const_hx4x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00002; + slotbuf[1] = 0; +} + +static void +Opcode_const_hx4x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80011800; + slotbuf[1] = 0; +} + +static void +Opcode_const_hx4x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1904000; +} + +static void +Opcode_const_hx4x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c00001; + slotbuf[1] = 0; +} + +static void +Opcode_const_hx4x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c060000; +} + +static void +Opcode_const_hx4x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000020; +} + +static void +Opcode_const_hx4x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44000003; + slotbuf[1] = 0xe; +} + +static void +Opcode_muljc_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82400000; + slotbuf[1] = 0x7; +} + +static void +Opcode_muljc_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82020000; + slotbuf[1] = 0x5; +} + +static void +Opcode_muljc_hx4x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_hx4x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80010800; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_hx4x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0400001; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_hx4x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c020000; +} + +static void +Opcode_muljc_hx4x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000080; +} + +static void +Opcode_muljc_hx4x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40030002; + slotbuf[1] = 0xe; +} + +static void +Opcode_add_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_sub_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_mul_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4; +} + +static void +Opcode_mul_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_madd_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_madd_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_msub_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_msub_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_mulq_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulq_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulq_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a000000; + slotbuf[1] = 0; +} + +static void +Opcode_maddq_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x5; +} + +static void +Opcode_maddq_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulcnvh_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulcnvh_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulacnvh_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulacnvh_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulcnvl_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulcnvl_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulacnvl_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulacnvl_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40; + slotbuf[1] = 0x6; +} + +static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { + Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { + Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0, Opcode_addi_Slot_ae_slot0_encode, Opcode_addi_Slot_ae_slot1_encode, 0, 0, Opcode_addi_Slot_ae2_slot0_encode, Opcode_addi_Slot_ae2_slot1_encode, 0, Opcode_addi_Slot_ae3_slot0_encode, Opcode_addi_Slot_ae3_slot1_encode, Opcode_addi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addi_Slot_ae8_slot0_encode, Opcode_addi_Slot_ae8_slot1_encode, 0, Opcode_addi_Slot_ae9_slot0_encode, Opcode_addi_Slot_ae9_slot1_encode, 0, 0, Opcode_addi_Slot_ae10_slot0_encode, Opcode_addi_Slot_ae10_slot1_encode, 0, 0, Opcode_addi_Slot_ae4_slot0_encode, Opcode_addi_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0, Opcode_addmi_Slot_ae_slot0_encode, Opcode_addmi_Slot_ae_slot1_encode, 0, 0, Opcode_addmi_Slot_ae2_slot0_encode, Opcode_addmi_Slot_ae2_slot1_encode, 0, Opcode_addmi_Slot_ae3_slot0_encode, Opcode_addmi_Slot_ae3_slot1_encode, Opcode_addmi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addmi_Slot_ae8_slot0_encode, Opcode_addmi_Slot_ae8_slot1_encode, 0, Opcode_addmi_Slot_ae9_slot0_encode, Opcode_addmi_Slot_ae9_slot1_encode, 0, 0, Opcode_addmi_Slot_ae10_slot0_encode, Opcode_addmi_Slot_ae10_slot1_encode, 0, 0, Opcode_addmi_Slot_ae4_slot0_encode, Opcode_addmi_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0, Opcode_add_Slot_ae_slot0_encode, Opcode_add_Slot_ae_slot1_encode, 0, 0, Opcode_add_Slot_ae2_slot0_encode, Opcode_add_Slot_ae2_slot1_encode, 0, Opcode_add_Slot_ae3_slot0_encode, Opcode_add_Slot_ae3_slot1_encode, Opcode_add_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_Slot_ae8_slot0_encode, Opcode_add_Slot_ae8_slot1_encode, 0, Opcode_add_Slot_ae9_slot0_encode, Opcode_add_Slot_ae9_slot1_encode, 0, 0, Opcode_add_Slot_ae10_slot0_encode, Opcode_add_Slot_ae10_slot1_encode, 0, 0, Opcode_add_Slot_ae4_slot0_encode, Opcode_add_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0, Opcode_addx2_Slot_ae_slot0_encode, Opcode_addx2_Slot_ae_slot1_encode, 0, 0, Opcode_addx2_Slot_ae2_slot0_encode, Opcode_addx2_Slot_ae2_slot1_encode, 0, Opcode_addx2_Slot_ae3_slot0_encode, Opcode_addx2_Slot_ae3_slot1_encode, Opcode_addx2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addx2_Slot_ae8_slot0_encode, Opcode_addx2_Slot_ae8_slot1_encode, 0, Opcode_addx2_Slot_ae9_slot0_encode, Opcode_addx2_Slot_ae9_slot1_encode, 0, 0, Opcode_addx2_Slot_ae10_slot0_encode, Opcode_addx2_Slot_ae10_slot1_encode, 0, 0, Opcode_addx2_Slot_ae4_slot0_encode, Opcode_addx2_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0, Opcode_addx4_Slot_ae_slot0_encode, Opcode_addx4_Slot_ae_slot1_encode, 0, 0, Opcode_addx4_Slot_ae2_slot0_encode, Opcode_addx4_Slot_ae2_slot1_encode, 0, Opcode_addx4_Slot_ae3_slot0_encode, Opcode_addx4_Slot_ae3_slot1_encode, Opcode_addx4_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addx4_Slot_ae8_slot0_encode, Opcode_addx4_Slot_ae8_slot1_encode, 0, Opcode_addx4_Slot_ae9_slot0_encode, Opcode_addx4_Slot_ae9_slot1_encode, 0, 0, Opcode_addx4_Slot_ae10_slot0_encode, Opcode_addx4_Slot_ae10_slot1_encode, 0, 0, Opcode_addx4_Slot_ae4_slot0_encode, Opcode_addx4_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0, Opcode_addx8_Slot_ae_slot0_encode, Opcode_addx8_Slot_ae_slot1_encode, 0, 0, Opcode_addx8_Slot_ae2_slot0_encode, Opcode_addx8_Slot_ae2_slot1_encode, 0, Opcode_addx8_Slot_ae3_slot0_encode, Opcode_addx8_Slot_ae3_slot1_encode, Opcode_addx8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addx8_Slot_ae8_slot0_encode, Opcode_addx8_Slot_ae8_slot1_encode, 0, Opcode_addx8_Slot_ae9_slot0_encode, Opcode_addx8_Slot_ae9_slot1_encode, 0, 0, Opcode_addx8_Slot_ae10_slot0_encode, Opcode_addx8_Slot_ae10_slot1_encode, 0, 0, Opcode_addx8_Slot_ae4_slot0_encode, Opcode_addx8_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0, Opcode_sub_Slot_ae_slot0_encode, Opcode_sub_Slot_ae_slot1_encode, 0, 0, Opcode_sub_Slot_ae2_slot0_encode, Opcode_sub_Slot_ae2_slot1_encode, 0, Opcode_sub_Slot_ae3_slot0_encode, Opcode_sub_Slot_ae3_slot1_encode, Opcode_sub_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_Slot_ae8_slot0_encode, Opcode_sub_Slot_ae8_slot1_encode, 0, Opcode_sub_Slot_ae9_slot0_encode, Opcode_sub_Slot_ae9_slot1_encode, 0, 0, Opcode_sub_Slot_ae10_slot0_encode, Opcode_sub_Slot_ae10_slot1_encode, 0, 0, Opcode_sub_Slot_ae4_slot0_encode, Opcode_sub_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0, Opcode_subx2_Slot_ae_slot0_encode, Opcode_subx2_Slot_ae_slot1_encode, 0, 0, Opcode_subx2_Slot_ae2_slot0_encode, Opcode_subx2_Slot_ae2_slot1_encode, 0, Opcode_subx2_Slot_ae3_slot0_encode, Opcode_subx2_Slot_ae3_slot1_encode, Opcode_subx2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_subx2_Slot_ae8_slot0_encode, Opcode_subx2_Slot_ae8_slot1_encode, 0, Opcode_subx2_Slot_ae9_slot0_encode, Opcode_subx2_Slot_ae9_slot1_encode, 0, 0, Opcode_subx2_Slot_ae10_slot0_encode, Opcode_subx2_Slot_ae10_slot1_encode, 0, 0, Opcode_subx2_Slot_ae4_slot0_encode, Opcode_subx2_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0, Opcode_subx4_Slot_ae_slot0_encode, Opcode_subx4_Slot_ae_slot1_encode, 0, 0, Opcode_subx4_Slot_ae2_slot0_encode, Opcode_subx4_Slot_ae2_slot1_encode, 0, Opcode_subx4_Slot_ae3_slot0_encode, Opcode_subx4_Slot_ae3_slot1_encode, Opcode_subx4_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_subx4_Slot_ae8_slot0_encode, Opcode_subx4_Slot_ae8_slot1_encode, 0, Opcode_subx4_Slot_ae9_slot0_encode, Opcode_subx4_Slot_ae9_slot1_encode, 0, 0, Opcode_subx4_Slot_ae10_slot0_encode, Opcode_subx4_Slot_ae10_slot1_encode, 0, 0, Opcode_subx4_Slot_ae4_slot0_encode, Opcode_subx4_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0, Opcode_subx8_Slot_ae_slot0_encode, Opcode_subx8_Slot_ae_slot1_encode, 0, 0, Opcode_subx8_Slot_ae2_slot0_encode, Opcode_subx8_Slot_ae2_slot1_encode, 0, Opcode_subx8_Slot_ae3_slot0_encode, Opcode_subx8_Slot_ae3_slot1_encode, Opcode_subx8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_subx8_Slot_ae8_slot0_encode, Opcode_subx8_Slot_ae8_slot1_encode, 0, Opcode_subx8_Slot_ae9_slot0_encode, Opcode_subx8_Slot_ae9_slot1_encode, 0, 0, Opcode_subx8_Slot_ae10_slot0_encode, Opcode_subx8_Slot_ae10_slot1_encode, 0, 0, Opcode_subx8_Slot_ae4_slot0_encode, Opcode_subx8_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0, Opcode_and_Slot_ae_slot0_encode, Opcode_and_Slot_ae_slot1_encode, 0, 0, Opcode_and_Slot_ae2_slot0_encode, Opcode_and_Slot_ae2_slot1_encode, 0, Opcode_and_Slot_ae3_slot0_encode, Opcode_and_Slot_ae3_slot1_encode, Opcode_and_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_and_Slot_ae8_slot0_encode, Opcode_and_Slot_ae8_slot1_encode, 0, Opcode_and_Slot_ae9_slot0_encode, Opcode_and_Slot_ae9_slot1_encode, 0, 0, Opcode_and_Slot_ae10_slot0_encode, Opcode_and_Slot_ae10_slot1_encode, 0, 0, Opcode_and_Slot_ae4_slot0_encode, Opcode_and_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0, Opcode_or_Slot_ae_slot0_encode, Opcode_or_Slot_ae_slot1_encode, 0, 0, Opcode_or_Slot_ae2_slot0_encode, Opcode_or_Slot_ae2_slot1_encode, 0, Opcode_or_Slot_ae3_slot0_encode, Opcode_or_Slot_ae3_slot1_encode, Opcode_or_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_or_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_or_Slot_ae8_slot0_encode, Opcode_or_Slot_ae8_slot1_encode, 0, Opcode_or_Slot_ae9_slot0_encode, Opcode_or_Slot_ae9_slot1_encode, 0, 0, Opcode_or_Slot_ae10_slot0_encode, Opcode_or_Slot_ae10_slot1_encode, 0, 0, Opcode_or_Slot_ae4_slot0_encode, Opcode_or_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0, Opcode_xor_Slot_ae_slot0_encode, Opcode_xor_Slot_ae_slot1_encode, 0, 0, Opcode_xor_Slot_ae2_slot0_encode, Opcode_xor_Slot_ae2_slot1_encode, 0, Opcode_xor_Slot_ae3_slot0_encode, Opcode_xor_Slot_ae3_slot1_encode, Opcode_xor_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_xor_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_xor_Slot_ae8_slot0_encode, Opcode_xor_Slot_ae8_slot1_encode, 0, Opcode_xor_Slot_ae9_slot0_encode, Opcode_xor_Slot_ae9_slot1_encode, 0, 0, Opcode_xor_Slot_ae10_slot0_encode, Opcode_xor_Slot_ae10_slot1_encode, 0, 0, Opcode_xor_Slot_ae4_slot0_encode, Opcode_xor_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0, Opcode_call0_Slot_ae_slot0_encode, 0, 0, 0, Opcode_call0_Slot_ae2_slot0_encode, 0, 0, Opcode_call0_Slot_ae3_slot0_encode, 0, Opcode_call0_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_call0_Slot_ae8_slot0_encode, 0, 0, Opcode_call0_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_call0_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_call0_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0, Opcode_callx0_Slot_ae_slot0_encode, 0, 0, 0, Opcode_callx0_Slot_ae2_slot0_encode, 0, 0, Opcode_callx0_Slot_ae3_slot0_encode, 0, Opcode_callx0_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_callx0_Slot_ae8_slot0_encode, 0, 0, Opcode_callx0_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_callx0_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_callx0_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0, Opcode_extui_Slot_ae_slot0_encode, Opcode_extui_Slot_ae_slot1_encode, 0, 0, Opcode_extui_Slot_ae2_slot0_encode, Opcode_extui_Slot_ae2_slot1_encode, 0, Opcode_extui_Slot_ae3_slot0_encode, Opcode_extui_Slot_ae3_slot1_encode, Opcode_extui_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_extui_Slot_ae8_slot0_encode, Opcode_extui_Slot_ae8_slot1_encode, 0, Opcode_extui_Slot_ae9_slot0_encode, Opcode_extui_Slot_ae9_slot1_encode, 0, 0, Opcode_extui_Slot_ae10_slot0_encode, Opcode_extui_Slot_ae10_slot1_encode, 0, 0, Opcode_extui_Slot_ae4_slot0_encode, Opcode_extui_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0, Opcode_j_Slot_ae_slot0_encode, 0, 0, 0, Opcode_j_Slot_ae2_slot0_encode, 0, 0, Opcode_j_Slot_ae3_slot0_encode, 0, Opcode_j_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_j_Slot_ae8_slot0_encode, 0, 0, Opcode_j_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_j_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_j_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0, Opcode_jx_Slot_ae_slot0_encode, 0, 0, 0, Opcode_jx_Slot_ae2_slot0_encode, 0, 0, Opcode_jx_Slot_ae3_slot0_encode, 0, Opcode_jx_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_jx_Slot_ae8_slot0_encode, 0, 0, Opcode_jx_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_jx_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_jx_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode, Opcode_l16ui_Slot_ae_slot1_encode, 0, 0, Opcode_l16ui_Slot_ae2_slot0_encode, Opcode_l16ui_Slot_ae2_slot1_encode, 0, Opcode_l16ui_Slot_ae3_slot0_encode, Opcode_l16ui_Slot_ae3_slot1_encode, Opcode_l16ui_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l16ui_Slot_ae8_slot0_encode, Opcode_l16ui_Slot_ae8_slot1_encode, 0, Opcode_l16ui_Slot_ae9_slot0_encode, Opcode_l16ui_Slot_ae9_slot1_encode, 0, 0, Opcode_l16ui_Slot_ae10_slot0_encode, Opcode_l16ui_Slot_ae10_slot1_encode, 0, 0, Opcode_l16ui_Slot_ae4_slot0_encode, Opcode_l16ui_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0, Opcode_l16si_Slot_ae_slot0_encode, Opcode_l16si_Slot_ae_slot1_encode, 0, 0, Opcode_l16si_Slot_ae2_slot0_encode, Opcode_l16si_Slot_ae2_slot1_encode, 0, Opcode_l16si_Slot_ae3_slot0_encode, Opcode_l16si_Slot_ae3_slot1_encode, Opcode_l16si_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l16si_Slot_ae8_slot0_encode, Opcode_l16si_Slot_ae8_slot1_encode, 0, Opcode_l16si_Slot_ae9_slot0_encode, Opcode_l16si_Slot_ae9_slot1_encode, 0, 0, Opcode_l16si_Slot_ae10_slot0_encode, Opcode_l16si_Slot_ae10_slot1_encode, 0, 0, Opcode_l16si_Slot_ae4_slot0_encode, Opcode_l16si_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0, Opcode_l32i_Slot_ae_slot0_encode, Opcode_l32i_Slot_ae_slot1_encode, 0, 0, Opcode_l32i_Slot_ae2_slot0_encode, Opcode_l32i_Slot_ae2_slot1_encode, 0, Opcode_l32i_Slot_ae3_slot0_encode, Opcode_l32i_Slot_ae3_slot1_encode, Opcode_l32i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l32i_Slot_ae8_slot0_encode, Opcode_l32i_Slot_ae8_slot1_encode, 0, Opcode_l32i_Slot_ae9_slot0_encode, Opcode_l32i_Slot_ae9_slot1_encode, 0, 0, Opcode_l32i_Slot_ae10_slot0_encode, Opcode_l32i_Slot_ae10_slot1_encode, 0, 0, Opcode_l32i_Slot_ae4_slot0_encode, Opcode_l32i_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0, Opcode_l32r_Slot_ae_slot0_encode, 0, 0, 0, Opcode_l32r_Slot_ae2_slot0_encode, 0, 0, Opcode_l32r_Slot_ae3_slot0_encode, 0, Opcode_l32r_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l32r_Slot_ae8_slot0_encode, 0, 0, Opcode_l32r_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_l32r_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_l32r_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode, Opcode_l8ui_Slot_ae_slot1_encode, 0, 0, Opcode_l8ui_Slot_ae2_slot0_encode, Opcode_l8ui_Slot_ae2_slot1_encode, 0, Opcode_l8ui_Slot_ae3_slot0_encode, Opcode_l8ui_Slot_ae3_slot1_encode, Opcode_l8ui_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l8ui_Slot_ae8_slot0_encode, Opcode_l8ui_Slot_ae8_slot1_encode, 0, Opcode_l8ui_Slot_ae9_slot0_encode, Opcode_l8ui_Slot_ae9_slot1_encode, 0, 0, Opcode_l8ui_Slot_ae10_slot0_encode, Opcode_l8ui_Slot_ae10_slot1_encode, 0, 0, Opcode_l8ui_Slot_ae4_slot0_encode, Opcode_l8ui_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { + Opcode_loop_Slot_inst_encode, 0, 0, Opcode_loop_Slot_ae_slot0_encode, 0, 0, 0, Opcode_loop_Slot_ae2_slot0_encode, 0, 0, Opcode_loop_Slot_ae3_slot0_encode, 0, Opcode_loop_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_loop_Slot_ae8_slot0_encode, 0, 0, Opcode_loop_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_loop_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_loop_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { + Opcode_loopgtz_Slot_inst_encode, 0, 0, Opcode_loopgtz_Slot_ae_slot0_encode, 0, 0, 0, Opcode_loopgtz_Slot_ae2_slot0_encode, 0, 0, Opcode_loopgtz_Slot_ae3_slot0_encode, 0, Opcode_loopgtz_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_loopgtz_Slot_ae8_slot0_encode, 0, 0, Opcode_loopgtz_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_loopgtz_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_loopgtz_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { + Opcode_loopnez_Slot_inst_encode, 0, 0, Opcode_loopnez_Slot_ae_slot0_encode, 0, 0, 0, Opcode_loopnez_Slot_ae2_slot0_encode, 0, 0, Opcode_loopnez_Slot_ae3_slot0_encode, 0, Opcode_loopnez_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_loopnez_Slot_ae8_slot0_encode, 0, 0, Opcode_loopnez_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_loopnez_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_loopnez_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0, Opcode_movi_Slot_ae_slot0_encode, Opcode_movi_Slot_ae_slot1_encode, 0, 0, Opcode_movi_Slot_ae2_slot0_encode, Opcode_movi_Slot_ae2_slot1_encode, 0, Opcode_movi_Slot_ae3_slot0_encode, Opcode_movi_Slot_ae3_slot1_encode, Opcode_movi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movi_Slot_ae8_slot0_encode, Opcode_movi_Slot_ae8_slot1_encode, 0, Opcode_movi_Slot_ae9_slot0_encode, Opcode_movi_Slot_ae9_slot1_encode, 0, 0, Opcode_movi_Slot_ae10_slot0_encode, Opcode_movi_Slot_ae10_slot1_encode, 0, 0, Opcode_movi_Slot_ae4_slot0_encode, Opcode_movi_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode, Opcode_moveqz_Slot_ae_slot1_encode, 0, 0, Opcode_moveqz_Slot_ae2_slot0_encode, Opcode_moveqz_Slot_ae2_slot1_encode, 0, Opcode_moveqz_Slot_ae3_slot0_encode, Opcode_moveqz_Slot_ae3_slot1_encode, Opcode_moveqz_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_moveqz_Slot_ae8_slot0_encode, Opcode_moveqz_Slot_ae8_slot1_encode, 0, Opcode_moveqz_Slot_ae9_slot0_encode, Opcode_moveqz_Slot_ae9_slot1_encode, 0, 0, Opcode_moveqz_Slot_ae10_slot0_encode, Opcode_moveqz_Slot_ae10_slot1_encode, 0, 0, Opcode_moveqz_Slot_ae4_slot0_encode, Opcode_moveqz_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0, Opcode_movgez_Slot_ae_slot0_encode, Opcode_movgez_Slot_ae_slot1_encode, 0, 0, Opcode_movgez_Slot_ae2_slot0_encode, Opcode_movgez_Slot_ae2_slot1_encode, 0, Opcode_movgez_Slot_ae3_slot0_encode, Opcode_movgez_Slot_ae3_slot1_encode, Opcode_movgez_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movgez_Slot_ae8_slot0_encode, Opcode_movgez_Slot_ae8_slot1_encode, 0, Opcode_movgez_Slot_ae9_slot0_encode, Opcode_movgez_Slot_ae9_slot1_encode, 0, 0, Opcode_movgez_Slot_ae10_slot0_encode, Opcode_movgez_Slot_ae10_slot1_encode, 0, 0, Opcode_movgez_Slot_ae4_slot0_encode, Opcode_movgez_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0, Opcode_movltz_Slot_ae_slot0_encode, Opcode_movltz_Slot_ae_slot1_encode, 0, 0, Opcode_movltz_Slot_ae2_slot0_encode, Opcode_movltz_Slot_ae2_slot1_encode, 0, Opcode_movltz_Slot_ae3_slot0_encode, Opcode_movltz_Slot_ae3_slot1_encode, Opcode_movltz_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movltz_Slot_ae8_slot0_encode, Opcode_movltz_Slot_ae8_slot1_encode, 0, Opcode_movltz_Slot_ae9_slot0_encode, Opcode_movltz_Slot_ae9_slot1_encode, 0, 0, Opcode_movltz_Slot_ae10_slot0_encode, Opcode_movltz_Slot_ae10_slot1_encode, 0, 0, Opcode_movltz_Slot_ae4_slot0_encode, Opcode_movltz_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0, Opcode_movnez_Slot_ae_slot0_encode, Opcode_movnez_Slot_ae_slot1_encode, 0, 0, Opcode_movnez_Slot_ae2_slot0_encode, Opcode_movnez_Slot_ae2_slot1_encode, 0, Opcode_movnez_Slot_ae3_slot0_encode, Opcode_movnez_Slot_ae3_slot1_encode, Opcode_movnez_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movnez_Slot_ae8_slot0_encode, Opcode_movnez_Slot_ae8_slot1_encode, 0, Opcode_movnez_Slot_ae9_slot0_encode, Opcode_movnez_Slot_ae9_slot1_encode, 0, 0, Opcode_movnez_Slot_ae10_slot0_encode, Opcode_movnez_Slot_ae10_slot1_encode, 0, 0, Opcode_movnez_Slot_ae4_slot0_encode, Opcode_movnez_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0, Opcode_abs_Slot_ae_slot0_encode, Opcode_abs_Slot_ae_slot1_encode, 0, 0, Opcode_abs_Slot_ae2_slot0_encode, Opcode_abs_Slot_ae2_slot1_encode, 0, Opcode_abs_Slot_ae3_slot0_encode, Opcode_abs_Slot_ae3_slot1_encode, Opcode_abs_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_abs_Slot_ae8_slot0_encode, Opcode_abs_Slot_ae8_slot1_encode, 0, Opcode_abs_Slot_ae9_slot0_encode, Opcode_abs_Slot_ae9_slot1_encode, 0, 0, Opcode_abs_Slot_ae10_slot0_encode, Opcode_abs_Slot_ae10_slot1_encode, 0, 0, Opcode_abs_Slot_ae4_slot0_encode, Opcode_abs_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0, Opcode_neg_Slot_ae_slot0_encode, Opcode_neg_Slot_ae_slot1_encode, 0, 0, Opcode_neg_Slot_ae2_slot0_encode, Opcode_neg_Slot_ae2_slot1_encode, 0, Opcode_neg_Slot_ae3_slot0_encode, Opcode_neg_Slot_ae3_slot1_encode, Opcode_neg_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_neg_Slot_ae8_slot0_encode, Opcode_neg_Slot_ae8_slot1_encode, 0, Opcode_neg_Slot_ae9_slot0_encode, Opcode_neg_Slot_ae9_slot1_encode, 0, 0, Opcode_neg_Slot_ae10_slot0_encode, Opcode_neg_Slot_ae10_slot1_encode, 0, 0, Opcode_neg_Slot_ae4_slot0_encode, Opcode_neg_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot0_encode, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot2_encode, Opcode_nop_Slot_ae_slot3_encode, Opcode_nop_Slot_ae2_slot0_encode, Opcode_nop_Slot_ae2_slot1_encode, Opcode_nop_Slot_ae2_slot2_encode, Opcode_nop_Slot_ae3_slot0_encode, Opcode_nop_Slot_ae3_slot1_encode, Opcode_nop_Slot_ae5_slot0_encode, Opcode_nop_Slot_ae5_slot1_encode, Opcode_nop_Slot_ae5_slot2_encode, Opcode_nop_Slot_ae6_slot0_encode, Opcode_nop_Slot_ae6_slot1_encode, Opcode_nop_Slot_ae6_slot2_encode, Opcode_nop_Slot_ae6_slot3_encode, Opcode_nop_Slot_ae7_slot0_encode, Opcode_nop_Slot_ae7_slot1_encode, Opcode_nop_Slot_ae7_slot2_encode, Opcode_nop_Slot_ae7_slot3_encode, Opcode_nop_Slot_ae8_slot0_encode, Opcode_nop_Slot_ae8_slot1_encode, Opcode_nop_Slot_ae8_slot2_encode, Opcode_nop_Slot_ae9_slot0_encode, Opcode_nop_Slot_ae9_slot1_encode, Opcode_nop_Slot_ae9_slot2_encode, Opcode_nop_Slot_ae9_slot3_encode, Opcode_nop_Slot_ae10_slot0_encode, Opcode_nop_Slot_ae10_slot1_encode, Opcode_nop_Slot_ae10_slot2_encode, Opcode_nop_Slot_ae10_slot3_encode, Opcode_nop_Slot_ae4_slot0_encode, Opcode_nop_Slot_ae4_slot1_encode, Opcode_nop_Slot_ae4_slot2_encode, Opcode_nop_Slot_ae4_slot3_encode, Opcode_nop_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32ex_encode_fns[] = { + Opcode_l32ex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32ex_encode_fns[] = { + Opcode_s32ex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_getex_encode_fns[] = { + Opcode_getex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clrex_encode_fns[] = { + Opcode_clrex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0, Opcode_ret_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ret_Slot_ae2_slot0_encode, 0, 0, Opcode_ret_Slot_ae3_slot0_encode, 0, Opcode_ret_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ret_Slot_ae8_slot0_encode, 0, 0, Opcode_ret_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_ret_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_ret_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0, Opcode_s16i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_s16i_Slot_ae2_slot0_encode, 0, 0, Opcode_s16i_Slot_ae3_slot0_encode, 0, Opcode_s16i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s16i_Slot_ae8_slot0_encode, 0, 0, Opcode_s16i_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_s16i_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_s16i_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0, Opcode_s32i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_s32i_Slot_ae2_slot0_encode, 0, 0, Opcode_s32i_Slot_ae3_slot0_encode, 0, Opcode_s32i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s32i_Slot_ae8_slot0_encode, 0, 0, Opcode_s32i_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_s32i_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_s32i_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = { + Opcode_s32nb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0, Opcode_s8i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_s8i_Slot_ae2_slot0_encode, 0, 0, Opcode_s8i_Slot_ae3_slot0_encode, 0, Opcode_s8i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s8i_Slot_ae8_slot0_encode, 0, 0, Opcode_s8i_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_s8i_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_s8i_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode, Opcode_ssa8b_Slot_ae_slot1_encode, 0, 0, Opcode_ssa8b_Slot_ae2_slot0_encode, Opcode_ssa8b_Slot_ae2_slot1_encode, 0, Opcode_ssa8b_Slot_ae3_slot0_encode, Opcode_ssa8b_Slot_ae3_slot1_encode, Opcode_ssa8b_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssa8b_Slot_ae8_slot0_encode, Opcode_ssa8b_Slot_ae8_slot1_encode, 0, Opcode_ssa8b_Slot_ae9_slot0_encode, Opcode_ssa8b_Slot_ae9_slot1_encode, 0, 0, Opcode_ssa8b_Slot_ae10_slot0_encode, Opcode_ssa8b_Slot_ae10_slot1_encode, 0, 0, Opcode_ssa8b_Slot_ae4_slot0_encode, Opcode_ssa8b_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode, Opcode_ssa8l_Slot_ae_slot1_encode, 0, 0, Opcode_ssa8l_Slot_ae2_slot0_encode, Opcode_ssa8l_Slot_ae2_slot1_encode, 0, Opcode_ssa8l_Slot_ae3_slot0_encode, Opcode_ssa8l_Slot_ae3_slot1_encode, Opcode_ssa8l_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssa8l_Slot_ae8_slot0_encode, Opcode_ssa8l_Slot_ae8_slot1_encode, 0, Opcode_ssa8l_Slot_ae9_slot0_encode, Opcode_ssa8l_Slot_ae9_slot1_encode, 0, 0, Opcode_ssa8l_Slot_ae10_slot0_encode, Opcode_ssa8l_Slot_ae10_slot1_encode, 0, 0, Opcode_ssa8l_Slot_ae4_slot0_encode, Opcode_ssa8l_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0, Opcode_ssl_Slot_ae_slot0_encode, Opcode_ssl_Slot_ae_slot1_encode, 0, 0, Opcode_ssl_Slot_ae2_slot0_encode, Opcode_ssl_Slot_ae2_slot1_encode, 0, Opcode_ssl_Slot_ae3_slot0_encode, Opcode_ssl_Slot_ae3_slot1_encode, Opcode_ssl_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssl_Slot_ae8_slot0_encode, Opcode_ssl_Slot_ae8_slot1_encode, 0, Opcode_ssl_Slot_ae9_slot0_encode, Opcode_ssl_Slot_ae9_slot1_encode, 0, 0, Opcode_ssl_Slot_ae10_slot0_encode, Opcode_ssl_Slot_ae10_slot1_encode, 0, 0, Opcode_ssl_Slot_ae4_slot0_encode, Opcode_ssl_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0, Opcode_ssr_Slot_ae_slot0_encode, Opcode_ssr_Slot_ae_slot1_encode, 0, 0, Opcode_ssr_Slot_ae2_slot0_encode, Opcode_ssr_Slot_ae2_slot1_encode, 0, Opcode_ssr_Slot_ae3_slot0_encode, Opcode_ssr_Slot_ae3_slot1_encode, Opcode_ssr_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssr_Slot_ae8_slot0_encode, Opcode_ssr_Slot_ae8_slot1_encode, 0, Opcode_ssr_Slot_ae9_slot0_encode, Opcode_ssr_Slot_ae9_slot1_encode, 0, 0, Opcode_ssr_Slot_ae10_slot0_encode, Opcode_ssr_Slot_ae10_slot1_encode, 0, 0, Opcode_ssr_Slot_ae4_slot0_encode, Opcode_ssr_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0, Opcode_ssai_Slot_ae_slot0_encode, Opcode_ssai_Slot_ae_slot1_encode, 0, 0, Opcode_ssai_Slot_ae2_slot0_encode, Opcode_ssai_Slot_ae2_slot1_encode, 0, Opcode_ssai_Slot_ae3_slot0_encode, Opcode_ssai_Slot_ae3_slot1_encode, Opcode_ssai_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssai_Slot_ae8_slot0_encode, Opcode_ssai_Slot_ae8_slot1_encode, 0, Opcode_ssai_Slot_ae9_slot0_encode, Opcode_ssai_Slot_ae9_slot1_encode, 0, 0, Opcode_ssai_Slot_ae10_slot0_encode, Opcode_ssai_Slot_ae10_slot1_encode, 0, 0, Opcode_ssai_Slot_ae4_slot0_encode, Opcode_ssai_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0, Opcode_sll_Slot_ae_slot0_encode, Opcode_sll_Slot_ae_slot1_encode, 0, 0, Opcode_sll_Slot_ae2_slot0_encode, Opcode_sll_Slot_ae2_slot1_encode, 0, Opcode_sll_Slot_ae3_slot0_encode, Opcode_sll_Slot_ae3_slot1_encode, Opcode_sll_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sll_Slot_ae8_slot0_encode, Opcode_sll_Slot_ae8_slot1_encode, 0, Opcode_sll_Slot_ae9_slot0_encode, Opcode_sll_Slot_ae9_slot1_encode, 0, 0, Opcode_sll_Slot_ae10_slot0_encode, Opcode_sll_Slot_ae10_slot1_encode, 0, 0, Opcode_sll_Slot_ae4_slot0_encode, Opcode_sll_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0, Opcode_src_Slot_ae_slot0_encode, Opcode_src_Slot_ae_slot1_encode, 0, 0, Opcode_src_Slot_ae2_slot0_encode, Opcode_src_Slot_ae2_slot1_encode, 0, Opcode_src_Slot_ae3_slot0_encode, Opcode_src_Slot_ae3_slot1_encode, Opcode_src_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_src_Slot_ae8_slot0_encode, Opcode_src_Slot_ae8_slot1_encode, 0, Opcode_src_Slot_ae9_slot0_encode, Opcode_src_Slot_ae9_slot1_encode, 0, 0, Opcode_src_Slot_ae10_slot0_encode, Opcode_src_Slot_ae10_slot1_encode, 0, 0, Opcode_src_Slot_ae4_slot0_encode, Opcode_src_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0, Opcode_sra_Slot_ae_slot0_encode, Opcode_sra_Slot_ae_slot1_encode, 0, 0, Opcode_sra_Slot_ae2_slot0_encode, Opcode_sra_Slot_ae2_slot1_encode, 0, Opcode_sra_Slot_ae3_slot0_encode, Opcode_sra_Slot_ae3_slot1_encode, Opcode_sra_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sra_Slot_ae8_slot0_encode, Opcode_sra_Slot_ae8_slot1_encode, 0, Opcode_sra_Slot_ae9_slot0_encode, Opcode_sra_Slot_ae9_slot1_encode, 0, 0, Opcode_sra_Slot_ae10_slot0_encode, Opcode_sra_Slot_ae10_slot1_encode, 0, 0, Opcode_sra_Slot_ae4_slot0_encode, Opcode_sra_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0, Opcode_srl_Slot_ae_slot0_encode, Opcode_srl_Slot_ae_slot1_encode, 0, 0, Opcode_srl_Slot_ae2_slot0_encode, Opcode_srl_Slot_ae2_slot1_encode, 0, Opcode_srl_Slot_ae3_slot0_encode, Opcode_srl_Slot_ae3_slot1_encode, Opcode_srl_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_srl_Slot_ae8_slot0_encode, Opcode_srl_Slot_ae8_slot1_encode, 0, Opcode_srl_Slot_ae9_slot0_encode, Opcode_srl_Slot_ae9_slot1_encode, 0, 0, Opcode_srl_Slot_ae10_slot0_encode, Opcode_srl_Slot_ae10_slot1_encode, 0, 0, Opcode_srl_Slot_ae4_slot0_encode, Opcode_srl_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0, Opcode_slli_Slot_ae_slot0_encode, Opcode_slli_Slot_ae_slot1_encode, 0, 0, Opcode_slli_Slot_ae2_slot0_encode, Opcode_slli_Slot_ae2_slot1_encode, 0, Opcode_slli_Slot_ae3_slot0_encode, Opcode_slli_Slot_ae3_slot1_encode, Opcode_slli_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_slli_Slot_ae8_slot0_encode, Opcode_slli_Slot_ae8_slot1_encode, 0, Opcode_slli_Slot_ae9_slot0_encode, Opcode_slli_Slot_ae9_slot1_encode, 0, 0, Opcode_slli_Slot_ae10_slot0_encode, Opcode_slli_Slot_ae10_slot1_encode, 0, 0, Opcode_slli_Slot_ae4_slot0_encode, Opcode_slli_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0, Opcode_srai_Slot_ae_slot0_encode, Opcode_srai_Slot_ae_slot1_encode, 0, 0, Opcode_srai_Slot_ae2_slot0_encode, Opcode_srai_Slot_ae2_slot1_encode, 0, Opcode_srai_Slot_ae3_slot0_encode, Opcode_srai_Slot_ae3_slot1_encode, Opcode_srai_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_srai_Slot_ae8_slot0_encode, Opcode_srai_Slot_ae8_slot1_encode, 0, Opcode_srai_Slot_ae9_slot0_encode, Opcode_srai_Slot_ae9_slot1_encode, 0, 0, Opcode_srai_Slot_ae10_slot0_encode, Opcode_srai_Slot_ae10_slot1_encode, 0, 0, Opcode_srai_Slot_ae4_slot0_encode, Opcode_srai_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0, Opcode_srli_Slot_ae_slot0_encode, Opcode_srli_Slot_ae_slot1_encode, 0, 0, Opcode_srli_Slot_ae2_slot0_encode, Opcode_srli_Slot_ae2_slot1_encode, 0, Opcode_srli_Slot_ae3_slot0_encode, Opcode_srli_Slot_ae3_slot1_encode, Opcode_srli_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_srli_Slot_ae8_slot0_encode, Opcode_srli_Slot_ae8_slot1_encode, 0, Opcode_srli_Slot_ae9_slot0_encode, Opcode_srli_Slot_ae9_slot1_encode, 0, 0, Opcode_srli_Slot_ae10_slot0_encode, Opcode_srli_Slot_ae10_slot1_encode, 0, 0, Opcode_srli_Slot_ae4_slot0_encode, Opcode_srli_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { + Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { + Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { + Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { + Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { + Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { + Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = { + Opcode_rsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = { + Opcode_wsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = { + Opcode_xsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { + Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { + Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { + Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { + Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { + Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { + Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { + Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { + Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { + Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { + Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { + Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { + Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { + Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { + Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { + Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { + Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { + Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { + Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { + Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { + Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { + Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { + Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { + Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { + Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { + Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { + Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { + Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { + Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { + Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { + Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { + Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { + Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { + Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { + Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { + Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { + Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { + Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { + Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { + Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc2_encode_fns[] = { + Opcode_rsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc2_encode_fns[] = { + Opcode_wsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc2_encode_fns[] = { + Opcode_xsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc3_encode_fns[] = { + Opcode_rsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc3_encode_fns[] = { + Opcode_wsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc3_encode_fns[] = { + Opcode_xsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_mpucfg_encode_fns[] = { + Opcode_rsr_mpucfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mpucfg_encode_fns[] = { + Opcode_wsr_mpucfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_salt_encode_fns[] = { + Opcode_salt_Slot_inst_encode, 0, 0, Opcode_salt_Slot_ae_slot0_encode, Opcode_salt_Slot_ae_slot1_encode, 0, 0, Opcode_salt_Slot_ae2_slot0_encode, Opcode_salt_Slot_ae2_slot1_encode, 0, Opcode_salt_Slot_ae3_slot0_encode, Opcode_salt_Slot_ae3_slot1_encode, Opcode_salt_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_salt_Slot_ae8_slot0_encode, Opcode_salt_Slot_ae8_slot1_encode, 0, Opcode_salt_Slot_ae9_slot0_encode, Opcode_salt_Slot_ae9_slot1_encode, 0, 0, Opcode_salt_Slot_ae10_slot0_encode, Opcode_salt_Slot_ae10_slot1_encode, 0, 0, Opcode_salt_Slot_ae4_slot0_encode, Opcode_salt_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_saltu_encode_fns[] = { + Opcode_saltu_Slot_inst_encode, 0, 0, Opcode_saltu_Slot_ae_slot0_encode, Opcode_saltu_Slot_ae_slot1_encode, 0, 0, Opcode_saltu_Slot_ae2_slot0_encode, Opcode_saltu_Slot_ae2_slot1_encode, 0, Opcode_saltu_Slot_ae3_slot0_encode, Opcode_saltu_Slot_ae3_slot1_encode, Opcode_saltu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_saltu_Slot_ae8_slot0_encode, Opcode_saltu_Slot_ae8_slot1_encode, 0, Opcode_saltu_Slot_ae9_slot0_encode, Opcode_saltu_Slot_ae9_slot1_encode, 0, 0, Opcode_saltu_Slot_ae10_slot0_encode, Opcode_saltu_Slot_ae10_slot1_encode, 0, 0, Opcode_saltu_Slot_ae4_slot0_encode, Opcode_saltu_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_opmode_encode_fns[] = { + Opcode_rsr_opmode_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_opmode_encode_fns[] = { + Opcode_wsr_opmode_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_opmode_encode_fns[] = { + Opcode_xsr_opmode_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { + Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { + Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { + Opcode_mull_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = { + Opcode_lddr32_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = { + Opcode_sddr32_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { + Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { + Opcode_andb_Slot_inst_encode, 0, 0, Opcode_andb_Slot_ae_slot0_encode, 0, 0, 0, Opcode_andb_Slot_ae2_slot0_encode, 0, 0, Opcode_andb_Slot_ae3_slot0_encode, 0, Opcode_andb_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_andb_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_andb_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_andb_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { + Opcode_andbc_Slot_inst_encode, 0, 0, Opcode_andbc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_andbc_Slot_ae2_slot0_encode, 0, 0, Opcode_andbc_Slot_ae3_slot0_encode, 0, Opcode_andbc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_andbc_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_andbc_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_andbc_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { + Opcode_orb_Slot_inst_encode, 0, 0, Opcode_orb_Slot_ae_slot0_encode, 0, 0, 0, Opcode_orb_Slot_ae2_slot0_encode, 0, 0, Opcode_orb_Slot_ae3_slot0_encode, 0, Opcode_orb_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_orb_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_orb_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_orb_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { + Opcode_orbc_Slot_inst_encode, 0, 0, Opcode_orbc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_orbc_Slot_ae2_slot0_encode, 0, 0, Opcode_orbc_Slot_ae3_slot0_encode, 0, Opcode_orbc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_orbc_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_orbc_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_orbc_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { + Opcode_xorb_Slot_inst_encode, 0, 0, Opcode_xorb_Slot_ae_slot0_encode, 0, 0, 0, Opcode_xorb_Slot_ae2_slot0_encode, 0, 0, Opcode_xorb_Slot_ae3_slot0_encode, 0, Opcode_xorb_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_xorb_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_xorb_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_xorb_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { + Opcode_all4_Slot_inst_encode, 0, 0, Opcode_all4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_all4_Slot_ae2_slot0_encode, 0, 0, Opcode_all4_Slot_ae3_slot0_encode, 0, Opcode_all4_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_all4_Slot_ae8_slot0_encode, 0, 0, Opcode_all4_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_all4_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_all4_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { + Opcode_any4_Slot_inst_encode, 0, 0, Opcode_any4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_any4_Slot_ae2_slot0_encode, 0, 0, Opcode_any4_Slot_ae3_slot0_encode, 0, Opcode_any4_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_any4_Slot_ae8_slot0_encode, 0, 0, Opcode_any4_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_any4_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_any4_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { + Opcode_all8_Slot_inst_encode, 0, 0, Opcode_all8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_all8_Slot_ae2_slot0_encode, 0, 0, Opcode_all8_Slot_ae3_slot0_encode, 0, Opcode_all8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_all8_Slot_ae8_slot0_encode, 0, 0, Opcode_all8_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_all8_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_all8_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { + Opcode_any8_Slot_inst_encode, 0, 0, Opcode_any8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_any8_Slot_ae2_slot0_encode, 0, 0, Opcode_any8_Slot_ae3_slot0_encode, 0, Opcode_any8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_any8_Slot_ae8_slot0_encode, 0, 0, Opcode_any8_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_any8_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_any8_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { + Opcode_bf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { + Opcode_bt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { + Opcode_movf_Slot_inst_encode, 0, 0, Opcode_movf_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movf_Slot_ae2_slot0_encode, 0, 0, Opcode_movf_Slot_ae3_slot0_encode, 0, Opcode_movf_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movf_Slot_ae8_slot0_encode, 0, 0, Opcode_movf_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_movf_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_movf_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { + Opcode_movt_Slot_inst_encode, 0, 0, Opcode_movt_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movt_Slot_ae2_slot0_encode, 0, 0, Opcode_movt_Slot_ae3_slot0_encode, 0, Opcode_movt_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movt_Slot_ae8_slot0_encode, 0, 0, Opcode_movt_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_movt_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_movt_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { + Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { + Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { + Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { + Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { + Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { + Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { + Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { + Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { + Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { + Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { + Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { + Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { + Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { + Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { + Opcode_iii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { + Opcode_lict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { + Opcode_licw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { + Opcode_sict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { + Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { + Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { + Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = { + Opcode_diwbui_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { + Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { + Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { + Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { + Opcode_dii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { + Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { + Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { + Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { + Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { + Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { + Opcode_diu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { + Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { + Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { + Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdcw_encode_fns[] = { + Opcode_sdcw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldcw_encode_fns[] = { + Opcode_ldcw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prefctl_encode_fns[] = { + Opcode_rsr_prefctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_prefctl_encode_fns[] = { + Opcode_wsr_prefctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_prefctl_encode_fns[] = { + Opcode_xsr_prefctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_cacheadrdis_encode_fns[] = { + Opcode_wsr_cacheadrdis_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_cacheadrdis_encode_fns[] = { + Opcode_rsr_cacheadrdis_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_cacheadrdis_encode_fns[] = { + Opcode_xsr_cacheadrdis_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rptlb0_encode_fns[] = { + Opcode_rptlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pptlb_encode_fns[] = { + Opcode_pptlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rptlb1_encode_fns[] = { + Opcode_rptlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wptlb_encode_fns[] = { + Opcode_wptlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_mpuenb_encode_fns[] = { + Opcode_rsr_mpuenb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mpuenb_encode_fns[] = { + Opcode_wsr_mpuenb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_mpuenb_encode_fns[] = { + Opcode_xsr_mpuenb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { + Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { + Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { + Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { + Opcode_clamps_Slot_inst_encode, 0, 0, Opcode_clamps_Slot_ae_slot0_encode, Opcode_clamps_Slot_ae_slot1_encode, 0, 0, Opcode_clamps_Slot_ae2_slot0_encode, Opcode_clamps_Slot_ae2_slot1_encode, 0, Opcode_clamps_Slot_ae3_slot0_encode, Opcode_clamps_Slot_ae3_slot1_encode, Opcode_clamps_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_clamps_Slot_ae8_slot0_encode, Opcode_clamps_Slot_ae8_slot1_encode, 0, Opcode_clamps_Slot_ae9_slot0_encode, Opcode_clamps_Slot_ae9_slot1_encode, 0, 0, Opcode_clamps_Slot_ae10_slot0_encode, Opcode_clamps_Slot_ae10_slot1_encode, 0, 0, Opcode_clamps_Slot_ae4_slot0_encode, Opcode_clamps_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { + Opcode_max_Slot_inst_encode, 0, 0, Opcode_max_Slot_ae_slot0_encode, Opcode_max_Slot_ae_slot1_encode, 0, 0, Opcode_max_Slot_ae2_slot0_encode, Opcode_max_Slot_ae2_slot1_encode, 0, Opcode_max_Slot_ae3_slot0_encode, Opcode_max_Slot_ae3_slot1_encode, Opcode_max_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_max_Slot_ae8_slot0_encode, Opcode_max_Slot_ae8_slot1_encode, 0, Opcode_max_Slot_ae9_slot0_encode, Opcode_max_Slot_ae9_slot1_encode, 0, 0, Opcode_max_Slot_ae10_slot0_encode, Opcode_max_Slot_ae10_slot1_encode, 0, 0, Opcode_max_Slot_ae4_slot0_encode, Opcode_max_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { + Opcode_maxu_Slot_inst_encode, 0, 0, Opcode_maxu_Slot_ae_slot0_encode, Opcode_maxu_Slot_ae_slot1_encode, 0, 0, Opcode_maxu_Slot_ae2_slot0_encode, Opcode_maxu_Slot_ae2_slot1_encode, 0, Opcode_maxu_Slot_ae3_slot0_encode, Opcode_maxu_Slot_ae3_slot1_encode, Opcode_maxu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maxu_Slot_ae8_slot0_encode, Opcode_maxu_Slot_ae8_slot1_encode, 0, Opcode_maxu_Slot_ae9_slot0_encode, Opcode_maxu_Slot_ae9_slot1_encode, 0, 0, Opcode_maxu_Slot_ae10_slot0_encode, Opcode_maxu_Slot_ae10_slot1_encode, 0, 0, Opcode_maxu_Slot_ae4_slot0_encode, Opcode_maxu_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { + Opcode_min_Slot_inst_encode, 0, 0, Opcode_min_Slot_ae_slot0_encode, Opcode_min_Slot_ae_slot1_encode, 0, 0, Opcode_min_Slot_ae2_slot0_encode, Opcode_min_Slot_ae2_slot1_encode, 0, Opcode_min_Slot_ae3_slot0_encode, Opcode_min_Slot_ae3_slot1_encode, Opcode_min_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_min_Slot_ae8_slot0_encode, Opcode_min_Slot_ae8_slot1_encode, 0, Opcode_min_Slot_ae9_slot0_encode, Opcode_min_Slot_ae9_slot1_encode, 0, 0, Opcode_min_Slot_ae10_slot0_encode, Opcode_min_Slot_ae10_slot1_encode, 0, 0, Opcode_min_Slot_ae4_slot0_encode, Opcode_min_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { + Opcode_minu_Slot_inst_encode, 0, 0, Opcode_minu_Slot_ae_slot0_encode, Opcode_minu_Slot_ae_slot1_encode, 0, 0, Opcode_minu_Slot_ae2_slot0_encode, Opcode_minu_Slot_ae2_slot1_encode, 0, Opcode_minu_Slot_ae3_slot0_encode, Opcode_minu_Slot_ae3_slot1_encode, Opcode_minu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_minu_Slot_ae8_slot0_encode, Opcode_minu_Slot_ae8_slot1_encode, 0, Opcode_minu_Slot_ae9_slot0_encode, Opcode_minu_Slot_ae9_slot1_encode, 0, 0, Opcode_minu_Slot_ae10_slot0_encode, Opcode_minu_Slot_ae10_slot1_encode, 0, 0, Opcode_minu_Slot_ae4_slot0_encode, Opcode_minu_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { + Opcode_sext_Slot_inst_encode, 0, 0, Opcode_sext_Slot_ae_slot0_encode, Opcode_sext_Slot_ae_slot1_encode, 0, 0, Opcode_sext_Slot_ae2_slot0_encode, Opcode_sext_Slot_ae2_slot1_encode, 0, Opcode_sext_Slot_ae3_slot0_encode, Opcode_sext_Slot_ae3_slot1_encode, Opcode_sext_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sext_Slot_ae8_slot0_encode, Opcode_sext_Slot_ae8_slot1_encode, 0, Opcode_sext_Slot_ae9_slot0_encode, Opcode_sext_Slot_ae9_slot1_encode, 0, 0, Opcode_sext_Slot_ae10_slot0_encode, Opcode_sext_Slot_ae10_slot1_encode, 0, 0, Opcode_sext_Slot_ae4_slot0_encode, Opcode_sext_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { + Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { + Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { + Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { + Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { + Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { + Opcode_quos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { + Opcode_quou_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { + Opcode_rems_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { + Opcode_remu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eraccess_encode_fns[] = { + Opcode_rsr_eraccess_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eraccess_encode_fns[] = { + Opcode_wsr_eraccess_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eraccess_encode_fns[] = { + Opcode_xsr_eraccess_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { + Opcode_rer_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { + Opcode_wer_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_beqz_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_beqz_w15_Slot_ae3_slot0_encode, 0, Opcode_beqz_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bgez_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bgez_w15_Slot_ae3_slot0_encode, 0, Opcode_bgez_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bltz_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bltz_w15_Slot_ae3_slot0_encode, 0, Opcode_bltz_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bnez_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bnez_w15_Slot_ae3_slot0_encode, 0, Opcode_bnez_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_beqi_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_beqi_w15_Slot_ae3_slot0_encode, 0, Opcode_beqi_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bgei_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bgei_w15_Slot_ae3_slot0_encode, 0, Opcode_bgei_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_blti_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_blti_w15_Slot_ae3_slot0_encode, 0, Opcode_blti_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bnei_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bnei_w15_Slot_ae3_slot0_encode, 0, Opcode_bnei_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bgeui_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bgeui_w15_Slot_ae3_slot0_encode, 0, Opcode_bgeui_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bltui_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bltui_w15_Slot_ae3_slot0_encode, 0, Opcode_bltui_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bbci_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bbci_w15_Slot_ae3_slot0_encode, 0, Opcode_bbci_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bbsi_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bbsi_w15_Slot_ae3_slot0_encode, 0, Opcode_bbsi_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ball_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_ball_w15_Slot_ae3_slot0_encode, 0, Opcode_ball_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bany_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bany_w15_Slot_ae3_slot0_encode, 0, Opcode_bany_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bbc_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bbc_w15_Slot_ae3_slot0_encode, 0, Opcode_bbc_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bbs_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bbs_w15_Slot_ae3_slot0_encode, 0, Opcode_bbs_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_beq_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_beq_w15_Slot_ae3_slot0_encode, 0, Opcode_beq_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bgeu_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bgeu_w15_Slot_ae3_slot0_encode, 0, Opcode_bgeu_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bge_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bge_w15_Slot_ae3_slot0_encode, 0, Opcode_bge_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bltu_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bltu_w15_Slot_ae3_slot0_encode, 0, Opcode_bltu_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_blt_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_blt_w15_Slot_ae3_slot0_encode, 0, Opcode_blt_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bnall_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bnall_w15_Slot_ae3_slot0_encode, 0, Opcode_bnall_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bne_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bne_w15_Slot_ae3_slot0_encode, 0, Opcode_bne_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bnone_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bnone_w15_Slot_ae3_slot0_encode, 0, Opcode_bnone_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext16_encode_fns[] = { + 0, 0, Opcode_ae_sext16_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_zext16_encode_fns[] = { + 0, 0, Opcode_ae_zext16_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_zext8_encode_fns[] = { + 0, 0, Opcode_ae_zext8_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_clamps16_encode_fns[] = { + 0, 0, Opcode_ae_clamps16_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = { + Opcode_rur_fcr_Slot_inst_encode, 0, 0, Opcode_rur_fcr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = { + Opcode_wur_fcr_Slot_inst_encode, 0, 0, Opcode_wur_fcr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = { + Opcode_rur_fsr_Slot_inst_encode, 0, 0, Opcode_rur_fsr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = { + Opcode_wur_fsr_Slot_inst_encode, 0, 0, Opcode_wur_fsr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { + Opcode_read_impwire_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { + Opcode_setb_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { + Opcode_clrb_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { + Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = { + Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = { + Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = { + Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = { + Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = { + Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = { + Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cw_sd_no_encode_fns[] = { + Opcode_rur_ae_cw_sd_no_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cw_sd_no_encode_fns[] = { + Opcode_wur_ae_cw_sd_no_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cbegin0_encode_fns[] = { + Opcode_rur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cbegin0_encode_fns[] = { + Opcode_wur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cend0_encode_fns[] = { + Opcode_rur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cend0_encode_fns[] = { + Opcode_wur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cbegin1_encode_fns[] = { + Opcode_rur_ae_cbegin1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cbegin1_encode_fns[] = { + Opcode_wur_ae_cbegin1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cend1_encode_fns[] = { + Opcode_rur_ae_cend1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cend1_encode_fns[] = { + Opcode_wur_ae_cend1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cbegin2_encode_fns[] = { + Opcode_rur_ae_cbegin2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cbegin2_encode_fns[] = { + Opcode_wur_ae_cbegin2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cend2_encode_fns[] = { + Opcode_rur_ae_cend2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cend2_encode_fns[] = { + Opcode_wur_ae_cend2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { + Opcode_rur_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { + Opcode_wur_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = { + Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = { + Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = { + Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = { + Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = { + Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rur_ae_bitptr_Slot_ae3_slot0_encode, 0, Opcode_rur_ae_bitptr_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = { + Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = { + Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = { + Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = { + Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = { + Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = { + Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = { + Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = { + Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = { + Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = { + Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = { + Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cwrap_encode_fns[] = { + Opcode_rur_ae_cwrap_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cwrap_encode_fns[] = { + Opcode_wur_ae_cwrap_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4f_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4f_i_Slot_ae_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4f_i_Slot_ae2_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4f_i_Slot_ae3_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae3_slot1_encode, Opcode_ae_l8x4f_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4f_i_Slot_ae8_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4f_i_Slot_ae9_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4f_i_Slot_ae10_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4f_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4f_ip_Slot_ae_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4f_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4f_ip_Slot_ae3_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae3_slot1_encode, Opcode_ae_l8x4f_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4f_ip_Slot_ae8_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4f_ip_Slot_ae9_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4f_ip_Slot_ae10_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4f_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4f_x_Slot_ae_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4f_x_Slot_ae2_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4f_x_Slot_ae3_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae3_slot1_encode, Opcode_ae_l8x4f_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4f_x_Slot_ae8_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4f_x_Slot_ae9_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4f_x_Slot_ae10_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4f_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4f_xp_Slot_ae_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4f_xp_Slot_ae2_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4f_xp_Slot_ae3_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae3_slot1_encode, Opcode_ae_l8x4f_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4f_xp_Slot_ae8_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4f_xp_Slot_ae9_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4f_xp_Slot_ae10_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4s_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4s_i_Slot_ae_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4s_i_Slot_ae2_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4s_i_Slot_ae3_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae3_slot1_encode, Opcode_ae_l8x4s_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4s_i_Slot_ae8_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4s_i_Slot_ae9_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4s_i_Slot_ae10_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4s_ip_Slot_ae_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4s_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4s_ip_Slot_ae3_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae3_slot1_encode, Opcode_ae_l8x4s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4s_ip_Slot_ae8_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4s_ip_Slot_ae9_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4s_ip_Slot_ae10_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4s_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4s_x_Slot_ae_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4s_x_Slot_ae2_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4s_x_Slot_ae3_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae3_slot1_encode, Opcode_ae_l8x4s_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4s_x_Slot_ae8_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4s_x_Slot_ae9_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4s_x_Slot_ae10_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4s_xp_Slot_ae_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4s_xp_Slot_ae2_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4s_xp_Slot_ae3_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae3_slot1_encode, Opcode_ae_l8x4s_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4s_xp_Slot_ae8_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4s_xp_Slot_ae9_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4s_xp_Slot_ae10_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4u_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4u_i_Slot_ae_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4u_i_Slot_ae2_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4u_i_Slot_ae3_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae3_slot1_encode, Opcode_ae_l8x4u_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4u_i_Slot_ae8_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4u_i_Slot_ae9_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4u_i_Slot_ae10_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4u_ip_Slot_ae_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4u_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4u_ip_Slot_ae3_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae3_slot1_encode, Opcode_ae_l8x4u_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4u_ip_Slot_ae8_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4u_ip_Slot_ae9_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4u_ip_Slot_ae10_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4u_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4u_x_Slot_ae_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4u_x_Slot_ae2_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4u_x_Slot_ae3_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae3_slot1_encode, Opcode_ae_l8x4u_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4u_x_Slot_ae8_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4u_x_Slot_ae9_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4u_x_Slot_ae10_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4u_xp_Slot_ae_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4u_xp_Slot_ae2_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4u_xp_Slot_ae3_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae3_slot1_encode, Opcode_ae_l8x4u_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4u_xp_Slot_ae8_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4u_xp_Slot_ae9_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4u_xp_Slot_ae10_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x4u_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x4u_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x4u_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x4u_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x4u_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4u_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x4u_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x4u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x4u_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x4u_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x4u_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x4u_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4u_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x4u_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x4u_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x4u_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x4u_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x4u_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x4u_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4u_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x4u_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x4u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x4u_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x4u_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x4u_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x4u_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4u_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x4u_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16m_xc_Slot_ae_slot0_encode, Opcode_ae_l16m_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_xc_Slot_ae2_slot0_encode, Opcode_ae_l16m_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l16m_xc_Slot_ae3_slot0_encode, Opcode_ae_l16m_xc_Slot_ae3_slot1_encode, Opcode_ae_l16m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_xc_Slot_ae8_slot0_encode, Opcode_ae_l16m_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_xc_Slot_ae9_slot0_encode, Opcode_ae_l16m_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_xc_Slot_ae10_slot0_encode, Opcode_ae_l16m_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_xc1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_l16m_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_xc1_Slot_ae2_slot0_encode, Opcode_ae_l16m_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l16m_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_xc1_Slot_ae8_slot0_encode, Opcode_ae_l16m_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_xc1_Slot_ae9_slot0_encode, Opcode_ae_l16m_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_xc1_Slot_ae10_slot0_encode, Opcode_ae_l16m_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16m_i_Slot_ae_slot0_encode, Opcode_ae_l16m_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_i_Slot_ae2_slot0_encode, Opcode_ae_l16m_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l16m_i_Slot_ae3_slot0_encode, Opcode_ae_l16m_i_Slot_ae3_slot1_encode, Opcode_ae_l16m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_i_Slot_ae8_slot0_encode, Opcode_ae_l16m_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_i_Slot_ae9_slot0_encode, Opcode_ae_l16m_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_i_Slot_ae10_slot0_encode, Opcode_ae_l16m_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16m_iu_Slot_ae_slot0_encode, Opcode_ae_l16m_iu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_iu_Slot_ae2_slot0_encode, Opcode_ae_l16m_iu_Slot_ae2_slot1_encode, 0, Opcode_ae_l16m_iu_Slot_ae3_slot0_encode, Opcode_ae_l16m_iu_Slot_ae3_slot1_encode, Opcode_ae_l16m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_iu_Slot_ae8_slot0_encode, Opcode_ae_l16m_iu_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_iu_Slot_ae9_slot0_encode, Opcode_ae_l16m_iu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_iu_Slot_ae10_slot0_encode, Opcode_ae_l16m_iu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16m_x_Slot_ae_slot0_encode, Opcode_ae_l16m_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_x_Slot_ae2_slot0_encode, Opcode_ae_l16m_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l16m_x_Slot_ae3_slot0_encode, Opcode_ae_l16m_x_Slot_ae3_slot1_encode, Opcode_ae_l16m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_x_Slot_ae8_slot0_encode, Opcode_ae_l16m_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_x_Slot_ae9_slot0_encode, Opcode_ae_l16m_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_x_Slot_ae10_slot0_encode, Opcode_ae_l16m_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16m_xu_Slot_ae_slot0_encode, Opcode_ae_l16m_xu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_xu_Slot_ae2_slot0_encode, Opcode_ae_l16m_xu_Slot_ae2_slot1_encode, 0, Opcode_ae_l16m_xu_Slot_ae3_slot0_encode, Opcode_ae_l16m_xu_Slot_ae3_slot1_encode, Opcode_ae_l16m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_xu_Slot_ae8_slot0_encode, Opcode_ae_l16m_xu_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_xu_Slot_ae9_slot0_encode, Opcode_ae_l16m_xu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_xu_Slot_ae10_slot0_encode, Opcode_ae_l16m_xu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_xc_Slot_ae_slot0_encode, Opcode_ae_l16_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_xc_Slot_ae2_slot0_encode, Opcode_ae_l16_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l16_xc_Slot_ae3_slot0_encode, Opcode_ae_l16_xc_Slot_ae3_slot1_encode, Opcode_ae_l16_xc_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16_xc_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_xc_Slot_ae8_slot0_encode, Opcode_ae_l16_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_xc_Slot_ae9_slot0_encode, Opcode_ae_l16_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_xc_Slot_ae10_slot0_encode, Opcode_ae_l16_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_xc1_Slot_ae_slot0_encode, Opcode_ae_l16_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_xc1_Slot_ae2_slot0_encode, Opcode_ae_l16_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l16_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_xc1_Slot_ae8_slot0_encode, Opcode_ae_l16_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_xc1_Slot_ae9_slot0_encode, Opcode_ae_l16_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_xc1_Slot_ae10_slot0_encode, Opcode_ae_l16_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_i_Slot_ae_slot0_encode, Opcode_ae_l16_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_i_Slot_ae2_slot0_encode, Opcode_ae_l16_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l16_i_Slot_ae3_slot0_encode, Opcode_ae_l16_i_Slot_ae3_slot1_encode, Opcode_ae_l16_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16_i_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_i_Slot_ae8_slot0_encode, Opcode_ae_l16_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_i_Slot_ae9_slot0_encode, Opcode_ae_l16_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_i_Slot_ae10_slot0_encode, Opcode_ae_l16_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_ip_Slot_ae_slot0_encode, Opcode_ae_l16_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_ip_Slot_ae2_slot0_encode, Opcode_ae_l16_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l16_ip_Slot_ae3_slot0_encode, Opcode_ae_l16_ip_Slot_ae3_slot1_encode, Opcode_ae_l16_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16_ip_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_ip_Slot_ae8_slot0_encode, Opcode_ae_l16_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_ip_Slot_ae9_slot0_encode, Opcode_ae_l16_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_ip_Slot_ae10_slot0_encode, Opcode_ae_l16_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_x_Slot_ae_slot0_encode, Opcode_ae_l16_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_x_Slot_ae2_slot0_encode, Opcode_ae_l16_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l16_x_Slot_ae3_slot0_encode, Opcode_ae_l16_x_Slot_ae3_slot1_encode, Opcode_ae_l16_x_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16_x_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_x_Slot_ae8_slot0_encode, Opcode_ae_l16_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_x_Slot_ae9_slot0_encode, Opcode_ae_l16_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_x_Slot_ae10_slot0_encode, Opcode_ae_l16_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_xp_Slot_ae_slot0_encode, Opcode_ae_l16_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_xp_Slot_ae2_slot0_encode, Opcode_ae_l16_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l16_xp_Slot_ae3_slot0_encode, Opcode_ae_l16_xp_Slot_ae3_slot1_encode, Opcode_ae_l16_xp_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16_xp_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_xp_Slot_ae8_slot0_encode, Opcode_ae_l16_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_xp_Slot_ae9_slot0_encode, Opcode_ae_l16_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_xp_Slot_ae10_slot0_encode, Opcode_ae_l16_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_xc_Slot_ae_slot0_encode, Opcode_ae_l8_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_xc_Slot_ae2_slot0_encode, Opcode_ae_l8_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l8_xc_Slot_ae3_slot0_encode, Opcode_ae_l8_xc_Slot_ae3_slot1_encode, Opcode_ae_l8_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_xc_Slot_ae8_slot0_encode, Opcode_ae_l8_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_xc_Slot_ae9_slot0_encode, Opcode_ae_l8_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_xc_Slot_ae10_slot0_encode, Opcode_ae_l8_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_xc1_Slot_ae_slot0_encode, Opcode_ae_l8_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_xc1_Slot_ae2_slot0_encode, Opcode_ae_l8_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l8_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_xc1_Slot_ae8_slot0_encode, Opcode_ae_l8_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_xc1_Slot_ae9_slot0_encode, Opcode_ae_l8_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_xc1_Slot_ae10_slot0_encode, Opcode_ae_l8_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_i_Slot_ae_slot0_encode, Opcode_ae_l8_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_i_Slot_ae2_slot0_encode, Opcode_ae_l8_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l8_i_Slot_ae3_slot0_encode, Opcode_ae_l8_i_Slot_ae3_slot1_encode, Opcode_ae_l8_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_i_Slot_ae8_slot0_encode, Opcode_ae_l8_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_i_Slot_ae9_slot0_encode, Opcode_ae_l8_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_i_Slot_ae10_slot0_encode, Opcode_ae_l8_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_ip_Slot_ae_slot0_encode, Opcode_ae_l8_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_ip_Slot_ae2_slot0_encode, Opcode_ae_l8_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l8_ip_Slot_ae3_slot0_encode, Opcode_ae_l8_ip_Slot_ae3_slot1_encode, Opcode_ae_l8_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_ip_Slot_ae8_slot0_encode, Opcode_ae_l8_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_ip_Slot_ae9_slot0_encode, Opcode_ae_l8_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_ip_Slot_ae10_slot0_encode, Opcode_ae_l8_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_x_Slot_ae_slot0_encode, Opcode_ae_l8_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_x_Slot_ae2_slot0_encode, Opcode_ae_l8_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l8_x_Slot_ae3_slot0_encode, Opcode_ae_l8_x_Slot_ae3_slot1_encode, Opcode_ae_l8_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_x_Slot_ae8_slot0_encode, Opcode_ae_l8_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_x_Slot_ae9_slot0_encode, Opcode_ae_l8_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_x_Slot_ae10_slot0_encode, Opcode_ae_l8_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_xp_Slot_ae_slot0_encode, Opcode_ae_l8_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_xp_Slot_ae2_slot0_encode, Opcode_ae_l8_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l8_xp_Slot_ae3_slot0_encode, Opcode_ae_l8_xp_Slot_ae3_slot1_encode, Opcode_ae_l8_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_xp_Slot_ae8_slot0_encode, Opcode_ae_l8_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_xp_Slot_ae9_slot0_encode, Opcode_ae_l8_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_xp_Slot_ae10_slot0_encode, Opcode_ae_l8_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_xc_Slot_ae_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_xc_Slot_ae2_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l32f24_xc_Slot_ae3_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae3_slot1_encode, Opcode_ae_l32f24_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_xc_Slot_ae9_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_xc_Slot_ae10_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae_slot0_encode, Opcode_ae_l32f24_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae2_slot0_encode, Opcode_ae_l32f24_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae9_slot0_encode, Opcode_ae_l32f24_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae10_slot0_encode, Opcode_ae_l32f24_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_i_Slot_ae_slot0_encode, Opcode_ae_l32f24_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_i_Slot_ae2_slot0_encode, Opcode_ae_l32f24_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l32f24_i_Slot_ae3_slot0_encode, Opcode_ae_l32f24_i_Slot_ae3_slot1_encode, Opcode_ae_l32f24_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_i_Slot_ae9_slot0_encode, Opcode_ae_l32f24_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_i_Slot_ae10_slot0_encode, Opcode_ae_l32f24_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_ip_Slot_ae_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_ip_Slot_ae2_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l32f24_ip_Slot_ae3_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae3_slot1_encode, Opcode_ae_l32f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_ip_Slot_ae9_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_ip_Slot_ae10_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_x_Slot_ae_slot0_encode, Opcode_ae_l32f24_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_x_Slot_ae2_slot0_encode, Opcode_ae_l32f24_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l32f24_x_Slot_ae3_slot0_encode, Opcode_ae_l32f24_x_Slot_ae3_slot1_encode, Opcode_ae_l32f24_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_x_Slot_ae9_slot0_encode, Opcode_ae_l32f24_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_x_Slot_ae10_slot0_encode, Opcode_ae_l32f24_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_xp_Slot_ae_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_xp_Slot_ae2_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l32f24_xp_Slot_ae3_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae3_slot1_encode, Opcode_ae_l32f24_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_xp_Slot_ae9_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_xp_Slot_ae10_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_xc_Slot_ae_slot0_encode, Opcode_ae_l32_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_xc_Slot_ae2_slot0_encode, Opcode_ae_l32_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l32_xc_Slot_ae3_slot0_encode, Opcode_ae_l32_xc_Slot_ae3_slot1_encode, Opcode_ae_l32_xc_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32_xc_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_xc_Slot_ae8_slot0_encode, Opcode_ae_l32_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_xc_Slot_ae9_slot0_encode, Opcode_ae_l32_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_xc_Slot_ae10_slot0_encode, Opcode_ae_l32_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_xc1_Slot_ae_slot0_encode, Opcode_ae_l32_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_xc1_Slot_ae2_slot0_encode, Opcode_ae_l32_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_xc1_Slot_ae8_slot0_encode, Opcode_ae_l32_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_xc1_Slot_ae9_slot0_encode, Opcode_ae_l32_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_xc1_Slot_ae10_slot0_encode, Opcode_ae_l32_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_i_Slot_ae_slot0_encode, Opcode_ae_l32_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_i_Slot_ae2_slot0_encode, Opcode_ae_l32_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l32_i_Slot_ae3_slot0_encode, Opcode_ae_l32_i_Slot_ae3_slot1_encode, Opcode_ae_l32_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32_i_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_i_Slot_ae8_slot0_encode, Opcode_ae_l32_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_i_Slot_ae9_slot0_encode, Opcode_ae_l32_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_i_Slot_ae10_slot0_encode, Opcode_ae_l32_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_ip_Slot_ae_slot0_encode, Opcode_ae_l32_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_ip_Slot_ae2_slot0_encode, Opcode_ae_l32_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l32_ip_Slot_ae3_slot0_encode, Opcode_ae_l32_ip_Slot_ae3_slot1_encode, Opcode_ae_l32_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32_ip_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_ip_Slot_ae8_slot0_encode, Opcode_ae_l32_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_ip_Slot_ae9_slot0_encode, Opcode_ae_l32_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_ip_Slot_ae10_slot0_encode, Opcode_ae_l32_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_x_Slot_ae_slot0_encode, Opcode_ae_l32_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_x_Slot_ae2_slot0_encode, Opcode_ae_l32_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l32_x_Slot_ae3_slot0_encode, Opcode_ae_l32_x_Slot_ae3_slot1_encode, Opcode_ae_l32_x_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32_x_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_x_Slot_ae8_slot0_encode, Opcode_ae_l32_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_x_Slot_ae9_slot0_encode, Opcode_ae_l32_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_x_Slot_ae10_slot0_encode, Opcode_ae_l32_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_xp_Slot_ae_slot0_encode, Opcode_ae_l32_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_xp_Slot_ae2_slot0_encode, Opcode_ae_l32_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l32_xp_Slot_ae3_slot0_encode, Opcode_ae_l32_xp_Slot_ae3_slot1_encode, Opcode_ae_l32_xp_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32_xp_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_xp_Slot_ae8_slot0_encode, Opcode_ae_l32_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_xp_Slot_ae9_slot0_encode, Opcode_ae_l32_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_xp_Slot_ae10_slot0_encode, Opcode_ae_l32_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32m_xc_Slot_ae_slot0_encode, Opcode_ae_l32m_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32m_xc_Slot_ae2_slot0_encode, Opcode_ae_l32m_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l32m_xc_Slot_ae3_slot0_encode, Opcode_ae_l32m_xc_Slot_ae3_slot1_encode, Opcode_ae_l32m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32m_xc_Slot_ae8_slot0_encode, Opcode_ae_l32m_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l32m_xc_Slot_ae9_slot0_encode, Opcode_ae_l32m_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32m_xc_Slot_ae10_slot0_encode, Opcode_ae_l32m_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32m_i_Slot_ae_slot0_encode, Opcode_ae_l32m_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32m_i_Slot_ae2_slot0_encode, Opcode_ae_l32m_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l32m_i_Slot_ae3_slot0_encode, Opcode_ae_l32m_i_Slot_ae3_slot1_encode, Opcode_ae_l32m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32m_i_Slot_ae8_slot0_encode, Opcode_ae_l32m_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l32m_i_Slot_ae9_slot0_encode, Opcode_ae_l32m_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32m_i_Slot_ae10_slot0_encode, Opcode_ae_l32m_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32m_iu_Slot_ae_slot0_encode, Opcode_ae_l32m_iu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32m_iu_Slot_ae2_slot0_encode, Opcode_ae_l32m_iu_Slot_ae2_slot1_encode, 0, Opcode_ae_l32m_iu_Slot_ae3_slot0_encode, Opcode_ae_l32m_iu_Slot_ae3_slot1_encode, Opcode_ae_l32m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32m_iu_Slot_ae8_slot0_encode, Opcode_ae_l32m_iu_Slot_ae8_slot1_encode, 0, Opcode_ae_l32m_iu_Slot_ae9_slot0_encode, Opcode_ae_l32m_iu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32m_iu_Slot_ae10_slot0_encode, Opcode_ae_l32m_iu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32m_x_Slot_ae_slot0_encode, Opcode_ae_l32m_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32m_x_Slot_ae2_slot0_encode, Opcode_ae_l32m_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l32m_x_Slot_ae3_slot0_encode, Opcode_ae_l32m_x_Slot_ae3_slot1_encode, Opcode_ae_l32m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32m_x_Slot_ae8_slot0_encode, Opcode_ae_l32m_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l32m_x_Slot_ae9_slot0_encode, Opcode_ae_l32m_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32m_x_Slot_ae10_slot0_encode, Opcode_ae_l32m_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32m_xu_Slot_ae_slot0_encode, Opcode_ae_l32m_xu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32m_xu_Slot_ae2_slot0_encode, Opcode_ae_l32m_xu_Slot_ae2_slot1_encode, 0, Opcode_ae_l32m_xu_Slot_ae3_slot0_encode, Opcode_ae_l32m_xu_Slot_ae3_slot1_encode, Opcode_ae_l32m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32m_xu_Slot_ae8_slot0_encode, Opcode_ae_l32m_xu_Slot_ae8_slot1_encode, 0, Opcode_ae_l32m_xu_Slot_ae9_slot0_encode, Opcode_ae_l32m_xu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32m_xu_Slot_ae10_slot0_encode, Opcode_ae_l32m_xu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x2m_xc_Slot_ae_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_xc_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x2m_xc_Slot_ae3_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_xc_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_xc_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_xc_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_xc1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_xc1_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x2m_i_Slot_ae_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_i_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x2m_i_Slot_ae3_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_i_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_i_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_i_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x2m_iu_Slot_ae_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_iu_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x2m_iu_Slot_ae3_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_iu_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_iu_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_iu_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x2m_x_Slot_ae_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_x_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x2m_x_Slot_ae3_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_x_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_x_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_x_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x2m_xu_Slot_ae_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_xu_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x2m_xu_Slot_ae3_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_xu_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_xu_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_xu_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_xc_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_xc1_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_i_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_ip_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_rip_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ri_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_ri_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_ri_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_ric_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_ric1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ric1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_ric1_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_ric1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_ric1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_x_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_xp_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_xc_Slot_ae_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_xc_Slot_ae3_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae3_slot1_encode, Opcode_ae_l32x2_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_xc_Slot_ae7_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_xc_Slot_ae8_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_xc_Slot_ae9_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_xc_Slot_ae10_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae2_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae7_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae8_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_xc1_Slot_ae9_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae10_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_i_Slot_ae_slot0_encode, Opcode_ae_l32x2_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_i_Slot_ae2_slot0_encode, Opcode_ae_l32x2_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_i_Slot_ae3_slot0_encode, Opcode_ae_l32x2_i_Slot_ae3_slot1_encode, Opcode_ae_l32x2_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32x2_i_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l32x2_i_Slot_ae7_slot0_encode, Opcode_ae_l32x2_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_i_Slot_ae8_slot0_encode, Opcode_ae_l32x2_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_i_Slot_ae9_slot0_encode, Opcode_ae_l32x2_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_i_Slot_ae10_slot0_encode, Opcode_ae_l32x2_i_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2_i_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_ip_Slot_ae_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_ip_Slot_ae3_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae3_slot1_encode, Opcode_ae_l32x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32x2_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l32x2_ip_Slot_ae7_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_ip_Slot_ae8_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_ip_Slot_ae9_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_ip_Slot_ae10_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_ric_Slot_ae_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_ric_Slot_ae2_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_ric_Slot_ae3_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae3_slot1_encode, Opcode_ae_l32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_ric_Slot_ae7_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_ric_Slot_ae8_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_ric_Slot_ae9_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_ric_Slot_ae10_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae2_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae7_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae8_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_ric1_Slot_ae9_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae10_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_x_Slot_ae_slot0_encode, Opcode_ae_l32x2_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_x_Slot_ae2_slot0_encode, Opcode_ae_l32x2_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_x_Slot_ae3_slot0_encode, Opcode_ae_l32x2_x_Slot_ae3_slot1_encode, Opcode_ae_l32x2_x_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32x2_x_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l32x2_x_Slot_ae7_slot0_encode, Opcode_ae_l32x2_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_x_Slot_ae8_slot0_encode, Opcode_ae_l32x2_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_x_Slot_ae9_slot0_encode, Opcode_ae_l32x2_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_x_Slot_ae10_slot0_encode, Opcode_ae_l32x2_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_xp_Slot_ae_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_xp_Slot_ae3_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae3_slot1_encode, Opcode_ae_l32x2_xp_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32x2_xp_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l32x2_xp_Slot_ae7_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_xp_Slot_ae8_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_xp_Slot_ae9_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_xp_Slot_ae10_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2_xp_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_xc_Slot_ae_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_xc_Slot_ae2_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_xc_Slot_ae3_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae3_slot1_encode, Opcode_ae_l16x4_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc_Slot_ae7_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_xc_Slot_ae8_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_xc_Slot_ae9_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_xc_Slot_ae10_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae2_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae7_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae8_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_xc1_Slot_ae9_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae10_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_i_Slot_ae_slot0_encode, Opcode_ae_l16x4_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_i_Slot_ae2_slot0_encode, Opcode_ae_l16x4_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_i_Slot_ae3_slot0_encode, Opcode_ae_l16x4_i_Slot_ae3_slot1_encode, Opcode_ae_l16x4_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16x4_i_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l16x4_i_Slot_ae7_slot0_encode, Opcode_ae_l16x4_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_i_Slot_ae8_slot0_encode, Opcode_ae_l16x4_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_i_Slot_ae9_slot0_encode, Opcode_ae_l16x4_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_i_Slot_ae10_slot0_encode, Opcode_ae_l16x4_i_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4_i_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_ip_Slot_ae_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_ip_Slot_ae2_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_ip_Slot_ae3_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae3_slot1_encode, Opcode_ae_l16x4_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16x4_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l16x4_ip_Slot_ae7_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_ip_Slot_ae8_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_ip_Slot_ae9_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_ip_Slot_ae10_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_x_Slot_ae_slot0_encode, Opcode_ae_l16x4_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_x_Slot_ae2_slot0_encode, Opcode_ae_l16x4_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_x_Slot_ae3_slot0_encode, Opcode_ae_l16x4_x_Slot_ae3_slot1_encode, Opcode_ae_l16x4_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_x_Slot_ae7_slot0_encode, Opcode_ae_l16x4_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_x_Slot_ae8_slot0_encode, Opcode_ae_l16x4_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_x_Slot_ae9_slot0_encode, Opcode_ae_l16x4_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_x_Slot_ae10_slot0_encode, Opcode_ae_l16x4_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_xp_Slot_ae_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_xp_Slot_ae2_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_xp_Slot_ae3_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae3_slot1_encode, Opcode_ae_l16x4_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xp_Slot_ae7_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_xp_Slot_ae8_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_xp_Slot_ae9_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_xp_Slot_ae10_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4_xp_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_xc_Slot_ae_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_xc_Slot_ae2_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_xc_Slot_ae3_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae3_slot1_encode, Opcode_ae_l8x8_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_xc_Slot_ae7_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_xc_Slot_ae8_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_xc_Slot_ae9_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_xc_Slot_ae10_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae2_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae7_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae8_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_xc1_Slot_ae9_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae10_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_i_Slot_ae_slot0_encode, Opcode_ae_l8x8_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_i_Slot_ae2_slot0_encode, Opcode_ae_l8x8_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_i_Slot_ae3_slot0_encode, Opcode_ae_l8x8_i_Slot_ae3_slot1_encode, Opcode_ae_l8x8_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_i_Slot_ae7_slot0_encode, Opcode_ae_l8x8_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_i_Slot_ae8_slot0_encode, Opcode_ae_l8x8_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_i_Slot_ae9_slot0_encode, Opcode_ae_l8x8_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_i_Slot_ae10_slot0_encode, Opcode_ae_l8x8_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_ip_Slot_ae_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_ip_Slot_ae3_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae3_slot1_encode, Opcode_ae_l8x8_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_ip_Slot_ae7_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_ip_Slot_ae8_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_ip_Slot_ae9_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_ip_Slot_ae10_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_x_Slot_ae_slot0_encode, Opcode_ae_l8x8_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_x_Slot_ae2_slot0_encode, Opcode_ae_l8x8_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_x_Slot_ae3_slot0_encode, Opcode_ae_l8x8_x_Slot_ae3_slot1_encode, Opcode_ae_l8x8_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_x_Slot_ae7_slot0_encode, Opcode_ae_l8x8_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_x_Slot_ae8_slot0_encode, Opcode_ae_l8x8_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_x_Slot_ae9_slot0_encode, Opcode_ae_l8x8_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_x_Slot_ae10_slot0_encode, Opcode_ae_l8x8_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_xp_Slot_ae_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_xp_Slot_ae2_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_xp_Slot_ae3_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae3_slot1_encode, Opcode_ae_l8x8_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_xp_Slot_ae7_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_xp_Slot_ae8_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_xp_Slot_ae9_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_xp_Slot_ae10_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_xc_Slot_ae_slot0_encode, Opcode_ae_l64_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_xc_Slot_ae2_slot0_encode, Opcode_ae_l64_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_xc_Slot_ae3_slot0_encode, Opcode_ae_l64_xc_Slot_ae3_slot1_encode, Opcode_ae_l64_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_xc_Slot_ae7_slot0_encode, Opcode_ae_l64_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_xc_Slot_ae8_slot0_encode, Opcode_ae_l64_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_xc_Slot_ae9_slot0_encode, Opcode_ae_l64_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_xc_Slot_ae10_slot0_encode, Opcode_ae_l64_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_xc1_Slot_ae_slot0_encode, Opcode_ae_l64_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_xc1_Slot_ae2_slot0_encode, Opcode_ae_l64_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l64_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_xc1_Slot_ae7_slot0_encode, Opcode_ae_l64_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_xc1_Slot_ae8_slot0_encode, Opcode_ae_l64_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_xc1_Slot_ae9_slot0_encode, Opcode_ae_l64_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_xc1_Slot_ae10_slot0_encode, Opcode_ae_l64_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_i_Slot_ae_slot0_encode, Opcode_ae_l64_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_i_Slot_ae2_slot0_encode, Opcode_ae_l64_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_i_Slot_ae3_slot0_encode, Opcode_ae_l64_i_Slot_ae3_slot1_encode, Opcode_ae_l64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_i_Slot_ae7_slot0_encode, Opcode_ae_l64_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_i_Slot_ae8_slot0_encode, Opcode_ae_l64_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_i_Slot_ae9_slot0_encode, Opcode_ae_l64_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_i_Slot_ae10_slot0_encode, Opcode_ae_l64_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_ip_Slot_ae_slot0_encode, Opcode_ae_l64_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_ip_Slot_ae2_slot0_encode, Opcode_ae_l64_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_ip_Slot_ae3_slot0_encode, Opcode_ae_l64_ip_Slot_ae3_slot1_encode, Opcode_ae_l64_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_ip_Slot_ae7_slot0_encode, Opcode_ae_l64_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_ip_Slot_ae8_slot0_encode, Opcode_ae_l64_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_ip_Slot_ae9_slot0_encode, Opcode_ae_l64_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_ip_Slot_ae10_slot0_encode, Opcode_ae_l64_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_x_Slot_ae_slot0_encode, Opcode_ae_l64_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_x_Slot_ae2_slot0_encode, Opcode_ae_l64_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_x_Slot_ae3_slot0_encode, Opcode_ae_l64_x_Slot_ae3_slot1_encode, Opcode_ae_l64_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_x_Slot_ae7_slot0_encode, Opcode_ae_l64_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_x_Slot_ae8_slot0_encode, Opcode_ae_l64_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_x_Slot_ae9_slot0_encode, Opcode_ae_l64_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_x_Slot_ae10_slot0_encode, Opcode_ae_l64_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_xp_Slot_ae_slot0_encode, Opcode_ae_l64_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_xp_Slot_ae2_slot0_encode, Opcode_ae_l64_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_xp_Slot_ae3_slot0_encode, Opcode_ae_l64_xp_Slot_ae3_slot1_encode, Opcode_ae_l64_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_xp_Slot_ae7_slot0_encode, Opcode_ae_l64_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_xp_Slot_ae8_slot0_encode, Opcode_ae_l64_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_xp_Slot_ae9_slot0_encode, Opcode_ae_l64_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_xp_Slot_ae10_slot0_encode, Opcode_ae_l64_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x2m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x2m_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x2m_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x2m_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x2m_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x2m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x2m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x2m_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x2m_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x2m_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x2m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x2m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_ric_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_ric_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_x_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_xp_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2rng_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2rng_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2rng_x_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2rng_xp_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_x_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_xp_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s8x8_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s16m_l_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16m_l_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s16m_l_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae3_slot0_encode, 0, Opcode_ae_s16m_l_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16m_l_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s16m_l_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae3_slot0_encode, 0, Opcode_ae_s16m_l_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32f24_l_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32f24_l_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32f24_l_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32f24_l_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32f24_l_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_l_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_l_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_l_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_l_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_l_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_l_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_l_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_l_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_l_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_l_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_h_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_h_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32_h_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_h_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_h_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_h_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_h_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_h_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_h_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_h_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_h_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16_0_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s16_0_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16_0_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s16_0_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16_0_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s16_0_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16_0_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s16_0_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16_0_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s16_0_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8_0_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s8_0_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s8_0_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8_0_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s8_0_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8_0_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s8_0_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8_0_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s8_0_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8_0_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s8_0_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s64_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32m_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32m_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32m_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32m_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32m_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32m_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32m_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32m_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32m_iu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32m_iu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32m_iu_Slot_ae3_slot0_encode, 0, Opcode_ae_s32m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_iu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32m_iu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32m_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32m_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32m_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32m_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32m_xu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32m_xu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32m_xu_Slot_ae3_slot0_encode, 0, Opcode_ae_s32m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_xu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32m_xu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_xc2_Slot_ae_slot0_encode, Opcode_ae_l32x2_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_xc2_Slot_ae2_slot0_encode, Opcode_ae_l32x2_xc2_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_l32x2_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_xc2_Slot_ae8_slot0_encode, Opcode_ae_l32x2_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_xc2_Slot_ae9_slot0_encode, Opcode_ae_l32x2_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_xc2_Slot_ae_slot0_encode, Opcode_ae_l16x4_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_xc2_Slot_ae2_slot0_encode, Opcode_ae_l16x4_xc2_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_l16x4_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc2_Slot_ae8_slot0_encode, Opcode_ae_l16x4_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_xc2_Slot_ae9_slot0_encode, Opcode_ae_l16x4_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_xc2_Slot_ae_slot0_encode, Opcode_ae_l8x8_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_xc2_Slot_ae2_slot0_encode, Opcode_ae_l8x8_xc2_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_l8x8_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_xc2_Slot_ae8_slot0_encode, Opcode_ae_l8x8_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_xc2_Slot_ae9_slot0_encode, Opcode_ae_l8x8_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_xc2_Slot_ae_slot0_encode, Opcode_ae_l64_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_xc2_Slot_ae2_slot0_encode, Opcode_ae_l64_xc2_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_l64_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_xc2_Slot_ae8_slot0_encode, Opcode_ae_l64_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_xc2_Slot_ae9_slot0_encode, Opcode_ae_l64_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_xc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_xc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_xc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_xc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_xc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_xc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_xc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_xc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4rng_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4rng_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4rng_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4rng_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4rng_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4rng_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4rng_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4rng_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4rng_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4rng_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4rng_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4rng_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4rng_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4rng_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4rng_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4rng_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4rng_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4rng_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4rng_x_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4rng_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4rng_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4rng_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4rng_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4rng_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4rng_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4rng_xp_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4rng_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4rng_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_xc_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_xc1_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_i_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_i_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_i_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_i_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_i_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_i_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_ip_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_x_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_x_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_x_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_x_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_x_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_x_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_xp_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_xc_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_xc1_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_i_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_i_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_i_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_i_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_i_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_i_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_ip_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_x_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_x_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_x_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_x_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_x_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_x_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_xp_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_xc_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_xc_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_xc_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_xc1_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc1_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_xc1_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc1_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_xc1_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc1_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_i_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_i_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_i_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_i_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_i_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_i_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_ip_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_x_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_x_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_x_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_x_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_x_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_x_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_xp_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_xp_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xp_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_xp_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xp_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_xc_Slot_ae_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_xc_Slot_ae7_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_xc_Slot_ae8_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_xc_Slot_ae9_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_xc_Slot_ae10_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_xc1_Slot_ae_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_xc1_Slot_ae2_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_xc1_Slot_ae7_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_xc1_Slot_ae8_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_xc1_Slot_ae9_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_xc1_Slot_ae10_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_i_Slot_ae_slot0_encode, Opcode_ae_l64x2_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_i_Slot_ae2_slot0_encode, Opcode_ae_l64x2_i_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_i_Slot_ae7_slot0_encode, Opcode_ae_l64x2_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_i_Slot_ae8_slot0_encode, Opcode_ae_l64x2_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_i_Slot_ae9_slot0_encode, Opcode_ae_l64x2_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_i_Slot_ae10_slot0_encode, Opcode_ae_l64x2_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_ip_Slot_ae_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_ip_Slot_ae7_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_ip_Slot_ae8_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_ip_Slot_ae9_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_ip_Slot_ae10_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_x_Slot_ae_slot0_encode, Opcode_ae_l64x2_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_x_Slot_ae2_slot0_encode, Opcode_ae_l64x2_x_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_x_Slot_ae7_slot0_encode, Opcode_ae_l64x2_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_x_Slot_ae8_slot0_encode, Opcode_ae_l64x2_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_x_Slot_ae9_slot0_encode, Opcode_ae_l64x2_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_x_Slot_ae10_slot0_encode, Opcode_ae_l64x2_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_xp_Slot_ae_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_xp_Slot_ae7_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_xp_Slot_ae8_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_xp_Slot_ae9_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_xp_Slot_ae10_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_xc_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_xc1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_ip_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_x_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xp_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2rng_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2rng_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2rng_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2rng_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_ip_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2rng_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2rng_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2rng_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2rng_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_xp_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_xc_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_xc1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_xc_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_xc1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x4ux2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x4ux2_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4ux2_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4ux2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x4ux2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x4ux2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x4ux2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4ux2_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4ux2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x4ux2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x4ux2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x4ux2_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4ux2_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4ux2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x4ux2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x4ux2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x4ux2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4ux2_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4ux2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x4ux2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_xc_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_xc1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_xc2_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc2_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_xc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_xc2_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_xc2_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_xc2_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc2_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_xc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_xc2_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_xc2_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_xc2_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc2_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_xc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_xc2_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_xc2_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_xc2_Slot_ae_slot0_encode, Opcode_ae_l64x2_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_xc2_Slot_ae2_slot0_encode, Opcode_ae_l64x2_xc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_xc2_Slot_ae8_slot0_encode, Opcode_ae_l64x2_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_xc2_Slot_ae9_slot0_encode, Opcode_ae_l64x2_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_xc2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_xc2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_xc2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_xc2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2rng_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2rng_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2rng_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2rng_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2rng_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2rng_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2rng_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2rng_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2rng_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2rng_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2rng_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2rng_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_zalign64_encode_fns[] = { + 0, 0, 0, Opcode_ae_zalign64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_zalign64_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_zalign64_Slot_ae3_slot0_encode, 0, Opcode_ae_zalign64_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lalign64_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_lalign64_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lalign64_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_lalign64_i_Slot_ae3_slot0_encode, 0, Opcode_ae_lalign64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_salign64_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_salign64_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_salign64_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_salign64_i_Slot_ae3_slot0_encode, 0, Opcode_ae_salign64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movalign_encode_fns[] = { + 0, 0, 0, Opcode_ae_movalign_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movalign_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movalign_Slot_ae3_slot0_encode, 0, Opcode_ae_movalign_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la64_pp_encode_fns[] = { + 0, 0, 0, Opcode_ae_la64_pp_Slot_ae_slot0_encode, Opcode_ae_la64_pp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la64_pp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la64_pp_Slot_ae3_slot0_encode, Opcode_ae_la64_pp_Slot_ae3_slot1_encode, Opcode_ae_la64_pp_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la64_pp_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24pos_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24pos_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24pos_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la24pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24neg_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24neg_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24neg_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24neg_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la24neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24pos_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24neg_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24neg_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2pos_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2pos_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2pos_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2neg_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2neg_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2neg_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2neg_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2pos_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2neg_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2neg_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2pos_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2pos_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2pos_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2neg_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2neg_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2neg_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2neg_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2pos_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2neg_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2neg_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2pos_pc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2pos_pc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2pos_pc2_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2pos_pc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4pos_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4pos_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4pos_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4neg_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4neg_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4neg_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4neg_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4pos_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4neg_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4neg_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4pos_pc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4pos_pc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4pos_pc2_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4pos_pc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8pos_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8pos_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8pos_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8neg_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8neg_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8neg_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8neg_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8pos_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la8x8pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8neg_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8neg_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la8x8neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8pos_pc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8pos_pc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8pos_pc2_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8pos_pc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa64pos_fp_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa64pos_fp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa64pos_fp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa64pos_fp_Slot_ae3_slot0_encode, 0, Opcode_ae_sa64pos_fp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa64neg_fp_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa64neg_fp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa64neg_fp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa64neg_fp_Slot_ae3_slot0_encode, 0, Opcode_ae_sa64neg_fp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic_Slot_ae7_slot0_encode, Opcode_ae_la32x2_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_ic_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ic_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae7_slot0_encode, Opcode_ae_la32x2_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ic1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic2_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ic2_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ip_Slot_ae_slot0_encode, Opcode_ae_la32x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2_ip_Slot_ae3_slot0_encode, Opcode_ae_la32x2_ip_Slot_ae3_slot1_encode, Opcode_ae_la32x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la32x2_ip_Slot_ae7_slot0_encode, Opcode_ae_la32x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_ip_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_rip_Slot_ae_slot0_encode, Opcode_ae_la32x2_rip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_rip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la32x2_rip_Slot_ae7_slot0_encode, Opcode_ae_la32x2_rip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_rip_Slot_ae8_slot0_encode, Opcode_ae_la32x2_rip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ric_Slot_ae7_slot0_encode, Opcode_ae_la32x2_ric_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_ric_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ric_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae7_slot0_encode, Opcode_ae_la32x2_ric1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ric1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic_Slot_ae7_slot0_encode, Opcode_ae_la16x4_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_ic_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ic_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae7_slot0_encode, Opcode_ae_la16x4_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ic1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic2_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ic2_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ip_Slot_ae_slot0_encode, Opcode_ae_la16x4_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4_ip_Slot_ae3_slot0_encode, Opcode_ae_la16x4_ip_Slot_ae3_slot1_encode, Opcode_ae_la16x4_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la16x4_ip_Slot_ae7_slot0_encode, Opcode_ae_la16x4_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_ip_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_rip_Slot_ae_slot0_encode, Opcode_ae_la16x4_rip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4_rip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_rip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la16x4_rip_Slot_ae7_slot0_encode, Opcode_ae_la16x4_rip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_rip_Slot_ae8_slot0_encode, Opcode_ae_la16x4_rip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ric_Slot_ae7_slot0_encode, Opcode_ae_la16x4_ric_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_ric_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ric_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae7_slot0_encode, Opcode_ae_la16x4_ric1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ric1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8_ic_Slot_ae7_slot0_encode, Opcode_ae_la8x8_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_ic_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ic_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la8x8_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8_ic1_Slot_ae7_slot0_encode, Opcode_ae_la8x8_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_ic1_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ic1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8_ic2_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ic2_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ip_Slot_ae_slot0_encode, Opcode_ae_la8x8_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8_ip_Slot_ae3_slot0_encode, Opcode_ae_la8x8_ip_Slot_ae3_slot1_encode, Opcode_ae_la8x8_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la8x8_ip_Slot_ae7_slot0_encode, Opcode_ae_la8x8_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_ip_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_rip_Slot_ae_slot0_encode, Opcode_ae_la8x8_rip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8_rip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_rip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la8x8_rip_Slot_ae7_slot0_encode, Opcode_ae_la8x8_rip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_rip_Slot_ae8_slot0_encode, Opcode_ae_la8x8_rip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8_ric_Slot_ae7_slot0_encode, Opcode_ae_la8x8_ric_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_ric_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ric_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la8x8_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8_ric1_Slot_ae7_slot0_encode, Opcode_ae_la8x8_ric1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_ric1_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ric1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2f24_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_ic_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_ic1_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae_slot0_encode, Opcode_ae_la32x2f24_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_ip_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae_slot0_encode, Opcode_ae_la32x2f24_rip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_rip_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_ric_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_ric1_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la24_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_la24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ic2_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa16x4_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa16x4_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_sa16x4_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ic2_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa16x4_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa16x4_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa16x4_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa8x8_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa8x8_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ic_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa8x8_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ic1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa8x8_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_sa8x8_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ic2_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa8x8_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa8x8_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa8x8_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa8x8_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_rip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa8x8_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa8x8_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ric_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa8x8_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ric1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2f24_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24_l_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24_l_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24_l_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24_l_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24_l_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24_l_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24_l_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24_l_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24_l_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24_l_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24x2_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24x2_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24x2_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24x2_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addicirc_encode_fns[] = { + 0, 0, 0, Opcode_ae_addicirc_Slot_ae_slot0_encode, Opcode_ae_addicirc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_addicirc_Slot_ae2_slot0_encode, Opcode_ae_addicirc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcirc_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_addcirc_xc2_Slot_ae_slot0_encode, Opcode_ae_addcirc_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_addcirc_xc2_Slot_ae2_slot0_encode, Opcode_ae_addcirc_xc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addcirc_xc2_Slot_ae4_slot0_encode, Opcode_ae_addcirc_xc2_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcirc_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_addcirc_xc1_Slot_ae_slot0_encode, Opcode_ae_addcirc_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_addcirc_xc1_Slot_ae2_slot0_encode, Opcode_ae_addcirc_xc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addcirc_xc1_Slot_ae4_slot0_encode, Opcode_ae_addcirc_xc1_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcirc_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_addcirc_xc_Slot_ae_slot0_encode, Opcode_ae_addcirc_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_addcirc_xc_Slot_ae2_slot0_encode, Opcode_ae_addcirc_xc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addcirc_xc_Slot_ae4_slot0_encode, Opcode_ae_addcirc_xc_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32ra64s_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32ra64s_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32ra64s_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32ra64s_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32ra64s_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32ra64s_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32ra64s_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32ra64s_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32ra64s_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32ra64s_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24ra64s_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s24ra64s_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24ra64s_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s24ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24ra64s_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s24ra64s_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24ra64s_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s24ra64s_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24ra64s_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s24ra64s_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s24ra64s_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2ra64s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24x2ra64s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4ra32s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4ra32s_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4ra32s_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4ra32s_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4ra32s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addbrba32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addbrba32_Slot_ae_slot0_encode, Opcode_ae_addbrba32_Slot_ae_slot1_encode, 0, 0, Opcode_ae_addbrba32_Slot_ae2_slot0_encode, Opcode_ae_addbrba32_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_addbrba32_Slot_ae3_slot1_encode, 0, 0, 0, 0, Opcode_ae_addbrba32_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addbrba32_Slot_ae4_slot0_encode, Opcode_ae_addbrba32_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_l_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_l_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bitswap_encode_fns[] = { + 0, 0, 0, Opcode_ae_bitswap_Slot_ae_slot0_encode, Opcode_ae_bitswap_Slot_ae_slot1_encode, 0, 0, Opcode_ae_bitswap_Slot_ae2_slot0_encode, Opcode_ae_bitswap_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_bitswap_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32js_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32js_Slot_ae_slot0_encode, 0, Opcode_ae_mul32js_Slot_ae_slot2_encode, Opcode_ae_mul32js_Slot_ae_slot3_encode, Opcode_ae_mul32js_Slot_ae2_slot0_encode, 0, Opcode_ae_mul32js_Slot_ae2_slot2_encode, 0, 0, Opcode_ae_mul32js_Slot_ae5_slot0_encode, 0, Opcode_ae_mul32js_Slot_ae5_slot2_encode, Opcode_ae_mul32js_Slot_ae6_slot0_encode, 0, Opcode_ae_mul32js_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32js_Slot_ae4_slot2_encode, Opcode_ae_mul32js_Slot_ae4_slot3_encode, Opcode_ae_mul32js_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsub32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsub32s_Slot_ae_slot0_encode, 0, Opcode_ae_addandsub32s_Slot_ae_slot2_encode, Opcode_ae_addandsub32s_Slot_ae_slot3_encode, Opcode_ae_addandsub32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32s_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsub32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32s_Slot_ae4_slot2_encode, Opcode_ae_addandsub32s_Slot_ae4_slot3_encode, Opcode_ae_addandsub32s_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsub32js_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsub32js_Slot_ae_slot0_encode, 0, Opcode_ae_addandsub32js_Slot_ae_slot2_encode, Opcode_ae_addandsub32js_Slot_ae_slot3_encode, Opcode_ae_addandsub32js_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32js_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsub32js_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32js_Slot_ae4_slot2_encode, Opcode_ae_addandsub32js_Slot_ae4_slot3_encode, Opcode_ae_addandsub32js_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsubrng32_Slot_ae_slot0_encode, 0, Opcode_ae_addandsubrng32_Slot_ae_slot2_encode, Opcode_ae_addandsubrng32_Slot_ae_slot3_encode, Opcode_ae_addandsubrng32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsubrng32_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_Slot_ae4_slot2_encode, Opcode_ae_addandsubrng32_Slot_ae4_slot3_encode, Opcode_ae_addandsubrng32_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsubrng32_h_Slot_ae_slot0_encode, 0, Opcode_ae_addandsubrng32_h_Slot_ae_slot2_encode, Opcode_ae_addandsubrng32_h_Slot_ae_slot3_encode, Opcode_ae_addandsubrng32_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_h_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsubrng32_h_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_h_Slot_ae4_slot2_encode, Opcode_ae_addandsubrng32_h_Slot_ae4_slot3_encode, Opcode_ae_addandsubrng32_h_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsubrng32_l_Slot_ae_slot0_encode, 0, Opcode_ae_addandsubrng32_l_Slot_ae_slot2_encode, Opcode_ae_addandsubrng32_l_Slot_ae_slot3_encode, Opcode_ae_addandsubrng32_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_l_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsubrng32_l_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_l_Slot_ae4_slot2_encode, Opcode_ae_addandsubrng32_l_Slot_ae4_slot3_encode, Opcode_ae_addandsubrng32_l_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addrng32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_addrng32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subrng32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_subrng32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rng32x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_rng32x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel16i_encode_fns[] = { + 0, 0, 0, Opcode_ae_sel16i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sel16i_Slot_ae_slot3_encode, Opcode_ae_sel16i_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_ae_sel16i_Slot_ae3_slot1_encode, Opcode_ae_sel16i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sel16i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sel16i_Slot_ae9_slot0_encode, 0, 0, Opcode_ae_sel16i_Slot_ae9_slot3_encode, 0, 0, 0, Opcode_ae_sel16i_Slot_ae10_slot3_encode, 0, 0, 0, Opcode_ae_sel16i_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel16i_n_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sel16i_n_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sel16i_n_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sel16i_n_Slot_ae4_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_shortswap_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_shortswap_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movab4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movab4_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movab4_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movab2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movab2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movab2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movab_encode_fns[] = { + 0, 0, 0, Opcode_ae_movab_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movab_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba_encode_fns[] = { + 0, 0, 0, Opcode_ae_movba_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movba_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba1x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movba1x2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movba1x2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movba4_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movba4_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movba2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movba2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movb2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movb2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movb4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movb4_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt16x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt16x4_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movt16x4_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movt16x4_Slot_ae6_slot0_encode, 0, Opcode_ae_movt16x4_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movt16x4_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movf16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movf16x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movf16x4_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movf16x4_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movf16x4_Slot_ae6_slot0_encode, 0, Opcode_ae_movf16x4_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movf16x4_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt32x2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt32x2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movt32x2_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movt32x2_Slot_ae6_slot0_encode, 0, Opcode_ae_movt32x2_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movt32x2_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movf32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movf32x2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movf32x2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movf32x2_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movf32x2_Slot_ae6_slot0_encode, 0, Opcode_ae_movf32x2_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movf32x2_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movsara7x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movsara7x2_Slot_ae_slot0_encode, Opcode_ae_movsara7x2_Slot_ae_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movsard7_encode_fns[] = { + 0, 0, 0, Opcode_ae_movsard7_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movsard7_Slot_ae2_slot0_encode, Opcode_ae_movsard7_Slot_ae2_slot1_encode, 0, Opcode_ae_movsard7_Slot_ae3_slot0_encode, 0, Opcode_ae_movsard7_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movasar_encode_fns[] = { + 0, 0, 0, Opcode_ae_movasar_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movasar_Slot_ae2_slot0_encode, Opcode_ae_movasar_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movda32x2_Slot_ae_slot0_encode, Opcode_ae_movda32x2_Slot_ae_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movda32x2_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda32_encode_fns[] = { + 0, 0, 0, Opcode_ae_movda32_Slot_ae_slot0_encode, Opcode_ae_movda32_Slot_ae_slot1_encode, 0, 0, Opcode_ae_movda32_Slot_ae2_slot0_encode, Opcode_ae_movda32_Slot_ae2_slot1_encode, 0, Opcode_ae_movda32_Slot_ae3_slot0_encode, Opcode_ae_movda32_Slot_ae3_slot1_encode, Opcode_ae_movda32_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda16x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movda16x2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda16_encode_fns[] = { + 0, 0, 0, Opcode_ae_movda16_Slot_ae_slot0_encode, Opcode_ae_movda16_Slot_ae_slot1_encode, 0, 0, Opcode_ae_movda16_Slot_ae2_slot0_encode, Opcode_ae_movda16_Slot_ae2_slot1_encode, 0, Opcode_ae_movda16_Slot_ae3_slot0_encode, Opcode_ae_movda16_Slot_ae3_slot1_encode, Opcode_ae_movda16_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movi_encode_fns[] = { + 0, 0, 0, Opcode_ae_movi_Slot_ae_slot0_encode, Opcode_ae_movi_Slot_ae_slot1_encode, Opcode_ae_movi_Slot_ae_slot2_encode, Opcode_ae_movi_Slot_ae_slot3_encode, Opcode_ae_movi_Slot_ae2_slot0_encode, Opcode_ae_movi_Slot_ae2_slot1_encode, 0, Opcode_ae_movi_Slot_ae3_slot0_encode, Opcode_ae_movi_Slot_ae3_slot1_encode, Opcode_ae_movi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode, Opcode_ae_truncp24a32x2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae2_slot0_encode, Opcode_ae_truncp24a32x2_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat16x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sat16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sat16x4_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt32x2f16_32_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt32x2f16_32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvt32x2f16_32_Slot_ae_slot3_encode, Opcode_ae_cvt32x2f16_32_Slot_ae2_slot0_encode, Opcode_ae_cvt32x2f16_32_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt32x2f16_10_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt32x2f16_10_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvt32x2f16_10_Slot_ae_slot3_encode, Opcode_ae_cvt32x2f16_10_Slot_ae2_slot0_encode, Opcode_ae_cvt32x2f16_10_Slot_ae2_slot1_encode, 0, Opcode_ae_cvt32x2f16_10_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext32x2d16_32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sext32x2d16_32_Slot_ae_slot0_encode, 0, Opcode_ae_sext32x2d16_32_Slot_ae_slot2_encode, Opcode_ae_sext32x2d16_32_Slot_ae_slot3_encode, Opcode_ae_sext32x2d16_32_Slot_ae2_slot0_encode, Opcode_ae_sext32x2d16_32_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext32x2d16_10_encode_fns[] = { + 0, 0, 0, Opcode_ae_sext32x2d16_10_Slot_ae_slot0_encode, 0, Opcode_ae_sext32x2d16_10_Slot_ae_slot2_encode, Opcode_ae_sext32x2d16_10_Slot_ae_slot3_encode, Opcode_ae_sext32x2d16_10_Slot_ae2_slot0_encode, Opcode_ae_sext32x2d16_10_Slot_ae2_slot1_encode, 0, Opcode_ae_sext32x2d16_10_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32f24s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32f24s_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32f24s_l_Slot_ae2_slot0_encode, Opcode_ae_cvta32f24s_l_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32f24s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32f24s_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32f24s_h_Slot_ae2_slot0_encode, Opcode_ae_cvta32f24s_h_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae3_slot0_encode, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca32x2f64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunci32x2f64s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci32x2f64s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_trunci32x2f64s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, Opcode_ae_trunci32x2f64s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci32x2f64s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca32f64s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca32f64s_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunca32f64s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca32f64s_l_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunci32f64s_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci32f64s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci32f64s_l_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f64ssym_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_round32x2f64ssym_Slot_ae_slot2_encode, Opcode_ae_round32x2f64ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f64sasym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round32x2f64sasym_Slot_ae_slot0_encode, 0, Opcode_ae_round32x2f64sasym_Slot_ae_slot2_encode, Opcode_ae_round32x2f64sasym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f48ssym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round32x2f48ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f48sasym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round32x2f48sasym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round16x4f32ssym_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_round16x4f32ssym_Slot_ae_slot2_encode, Opcode_ae_round16x4f32ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_round16x4f32ssym_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round16x4f32sasym_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_round16x4f32sasym_Slot_ae_slot2_encode, Opcode_ae_round16x4f32sasym_Slot_ae_slot3_encode, 0, 0, 0, Opcode_ae_round16x4f32sasym_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_round16x4f32sasym_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round24x2f48ssym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round24x2f48ssym_Slot_ae_slot0_encode, 0, 0, Opcode_ae_round24x2f48ssym_Slot_ae_slot3_encode, 0, 0, 0, Opcode_ae_round24x2f48ssym_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round24x2f48sasym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round24x2f48sasym_Slot_ae_slot0_encode, 0, 0, Opcode_ae_round24x2f48sasym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48x2sym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsp16q48x2sym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48x2asym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsp16q48x2asym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minabs32s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_minabs32s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxabs32s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_maxabs32s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16f24sym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsp16f24sym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16f24asym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsp16f24asym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mov_encode_fns[] = { + 0, 0, 0, Opcode_ae_mov_Slot_ae_slot0_encode, 0, Opcode_ae_mov_Slot_ae_slot2_encode, Opcode_ae_mov_Slot_ae_slot3_encode, Opcode_ae_mov_Slot_ae2_slot0_encode, Opcode_ae_mov_Slot_ae2_slot1_encode, Opcode_ae_mov_Slot_ae2_slot2_encode, Opcode_ae_mov_Slot_ae3_slot0_encode, Opcode_ae_mov_Slot_ae3_slot1_encode, Opcode_ae_mov_Slot_ae5_slot0_encode, 0, Opcode_ae_mov_Slot_ae5_slot2_encode, Opcode_ae_mov_Slot_ae6_slot0_encode, Opcode_ae_mov_Slot_ae6_slot1_encode, Opcode_ae_mov_Slot_ae6_slot2_encode, Opcode_ae_mov_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mov_Slot_ae7_slot2_encode, Opcode_ae_mov_Slot_ae7_slot3_encode, Opcode_ae_mov_Slot_ae8_slot0_encode, 0, Opcode_ae_mov_Slot_ae8_slot2_encode, Opcode_ae_mov_Slot_ae9_slot0_encode, 0, Opcode_ae_mov_Slot_ae9_slot2_encode, Opcode_ae_mov_Slot_ae9_slot3_encode, 0, 0, Opcode_ae_mov_Slot_ae10_slot2_encode, Opcode_ae_mov_Slot_ae10_slot3_encode, 0, 0, Opcode_ae_mov_Slot_ae4_slot2_encode, Opcode_ae_mov_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt64_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt64_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movt64_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movt64_Slot_ae6_slot0_encode, 0, Opcode_ae_movt64_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movt64_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movf64_encode_fns[] = { + 0, 0, 0, Opcode_ae_movf64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movf64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movf64_Slot_ae6_slot0_encode, 0, Opcode_ae_movf64_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movf64_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq56a32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvtq56a32s_Slot_ae_slot0_encode, Opcode_ae_cvtq56a32s_Slot_ae_slot1_encode, 0, 0, Opcode_ae_cvtq56a32s_Slot_ae2_slot0_encode, Opcode_ae_cvtq56a32s_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_cvtq56a32s_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt48a32_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt48a32_Slot_ae_slot0_encode, Opcode_ae_cvt48a32_Slot_ae_slot1_encode, 0, 0, Opcode_ae_cvt48a32_Slot_ae2_slot0_encode, Opcode_ae_cvt48a32_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_cvt48a32_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt64a32_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt64a32_Slot_ae_slot0_encode, Opcode_ae_cvt64a32_Slot_ae_slot1_encode, 0, 0, Opcode_ae_cvt64a32_Slot_ae2_slot0_encode, Opcode_ae_cvt64a32_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_cvt64a32_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq56p32s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvtq56p32s_l_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvtq56p32s_l_Slot_ae_slot3_encode, Opcode_ae_cvtq56p32s_l_Slot_ae2_slot0_encode, Opcode_ae_cvtq56p32s_l_Slot_ae2_slot1_encode, 0, Opcode_ae_cvtq56p32s_l_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq56p32s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvtq56p32s_h_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvtq56p32s_h_Slot_ae_slot3_encode, Opcode_ae_cvtq56p32s_h_Slot_ae2_slot0_encode, Opcode_ae_cvtq56p32s_h_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt64f32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt64f32_h_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvt64f32_h_Slot_ae_slot3_encode, Opcode_ae_cvt64f32_h_Slot_ae2_slot0_encode, Opcode_ae_cvt64f32_h_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt48f32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt48f32_l_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvt48f32_l_Slot_ae_slot3_encode, Opcode_ae_cvt48f32_l_Slot_ae2_slot0_encode, Opcode_ae_cvt48f32_l_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt48f32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt48f32_h_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvt48f32_h_Slot_ae_slot3_encode, Opcode_ae_cvt48f32_h_Slot_ae2_slot0_encode, Opcode_ae_cvt48f32_h_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat48s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sat48s_Slot_ae_slot2_encode, Opcode_ae_sat48s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satq56s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_satq56s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat24s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sat24s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = { + 0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_truncq32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minabs64s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_minabs64s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxabs64s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_maxabs64s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsq32f48sym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsq32f48sym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsq32f48asym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsq32f48asym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae2_slot0_encode, Opcode_ae_trunca32q48_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad32_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad32_l_Slot_ae2_slot0_encode, Opcode_ae_movad32_l_Slot_ae2_slot1_encode, 0, Opcode_ae_movad32_l_Slot_ae3_slot0_encode, Opcode_ae_movad32_l_Slot_ae3_slot1_encode, Opcode_ae_movad32_l_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movad32_l_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad32_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad32_h_Slot_ae2_slot0_encode, Opcode_ae_movad32_h_Slot_ae2_slot1_encode, 0, Opcode_ae_movad32_h_Slot_ae3_slot0_encode, 0, Opcode_ae_movad32_h_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_3_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad16_3_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad16_3_Slot_ae2_slot0_encode, Opcode_ae_movad16_3_Slot_ae2_slot1_encode, 0, Opcode_ae_movad16_3_Slot_ae3_slot0_encode, 0, Opcode_ae_movad16_3_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad16_2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad16_2_Slot_ae2_slot0_encode, Opcode_ae_movad16_2_Slot_ae2_slot1_encode, 0, Opcode_ae_movad16_2_Slot_ae3_slot0_encode, 0, Opcode_ae_movad16_2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_1_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad16_1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad16_1_Slot_ae2_slot0_encode, Opcode_ae_movad16_1_Slot_ae2_slot1_encode, 0, Opcode_ae_movad16_1_Slot_ae3_slot0_encode, 0, Opcode_ae_movad16_1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_0_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad16_0_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad16_0_Slot_ae2_slot0_encode, Opcode_ae_movad16_0_Slot_ae2_slot1_encode, 0, Opcode_ae_movad16_0_Slot_ae3_slot0_encode, 0, Opcode_ae_movad16_0_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movad16_0_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sra64_32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sra64_32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sra64_32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksr32_encode_fns[] = { + 0, 0, 0, Opcode_ae_pksr32_Slot_ae_slot0_encode, 0, Opcode_ae_pksr32_Slot_ae_slot2_encode, 0, Opcode_ae_pksr32_Slot_ae2_slot0_encode, 0, Opcode_ae_pksr32_Slot_ae2_slot2_encode, 0, 0, Opcode_ae_pksr32_Slot_ae5_slot0_encode, 0, Opcode_ae_pksr32_Slot_ae5_slot2_encode, Opcode_ae_pksr32_Slot_ae6_slot0_encode, 0, Opcode_ae_pksr32_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_pksr32_Slot_ae4_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksr24_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_pksr24_Slot_ae_slot2_encode, 0, Opcode_ae_pksr24_Slot_ae2_slot0_encode, 0, Opcode_ae_pksr24_Slot_ae2_slot2_encode, 0, 0, Opcode_ae_pksr24_Slot_ae5_slot0_encode, 0, Opcode_ae_pksr24_Slot_ae5_slot2_encode, Opcode_ae_pksr24_Slot_ae6_slot0_encode, 0, Opcode_ae_pksr24_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_pksr24_Slot_ae4_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksrf32_encode_fns[] = { + 0, 0, 0, Opcode_ae_pksrf32_Slot_ae_slot0_encode, 0, Opcode_ae_pksrf32_Slot_ae_slot2_encode, 0, Opcode_ae_pksrf32_Slot_ae2_slot0_encode, 0, Opcode_ae_pksrf32_Slot_ae2_slot2_encode, 0, 0, Opcode_ae_pksrf32_Slot_ae5_slot0_encode, 0, Opcode_ae_pksrf32_Slot_ae5_slot2_encode, Opcode_ae_pksrf32_Slot_ae6_slot0_encode, 0, Opcode_ae_pksrf32_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_pksrf32_Slot_ae4_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksr16_encode_fns[] = { + 0, 0, 0, Opcode_ae_pksr16_Slot_ae_slot0_encode, 0, Opcode_ae_pksr16_Slot_ae_slot2_encode, 0, Opcode_ae_pksr16_Slot_ae2_slot0_encode, 0, Opcode_ae_pksr16_Slot_ae2_slot2_encode, 0, 0, Opcode_ae_pksr16_Slot_ae5_slot0_encode, 0, Opcode_ae_pksr16_Slot_ae5_slot2_encode, Opcode_ae_pksr16_Slot_ae6_slot0_encode, 0, Opcode_ae_pksr16_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_pksr16_Slot_ae4_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32_encode_fns[] = { + 0, 0, 0, Opcode_ae_add32_Slot_ae_slot0_encode, 0, Opcode_ae_add32_Slot_ae_slot2_encode, Opcode_ae_add32_Slot_ae_slot3_encode, Opcode_ae_add32_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_add32_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub32_Slot_ae_slot0_encode, 0, Opcode_ae_sub32_Slot_ae_slot2_encode, Opcode_ae_sub32_Slot_ae_slot3_encode, Opcode_ae_sub32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsub32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsub32_Slot_ae_slot0_encode, 0, Opcode_ae_addsub32_Slot_ae_slot2_encode, Opcode_ae_addsub32_Slot_ae_slot3_encode, Opcode_ae_addsub32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subadd32_encode_fns[] = { + 0, 0, 0, Opcode_ae_subadd32_Slot_ae_slot0_encode, 0, Opcode_ae_subadd32_Slot_ae_slot2_encode, Opcode_ae_subadd32_Slot_ae_slot3_encode, Opcode_ae_subadd32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add16_encode_fns[] = { + 0, 0, 0, Opcode_ae_add16_Slot_ae_slot0_encode, 0, Opcode_ae_add16_Slot_ae_slot2_encode, Opcode_ae_add16_Slot_ae_slot3_encode, Opcode_ae_add16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub16_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub16_Slot_ae_slot0_encode, 0, Opcode_ae_sub16_Slot_ae_slot2_encode, Opcode_ae_sub16_Slot_ae_slot3_encode, Opcode_ae_sub16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_add32_hl_lh_Slot_ae_slot0_encode, 0, Opcode_ae_add32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_add32_hl_lh_Slot_ae_slot3_encode, Opcode_ae_add32_hl_lh_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsub32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_addsub32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_addsub32_hl_lh_Slot_ae_slot3_encode, Opcode_ae_addsub32_hl_lh_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg32_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg32_Slot_ae_slot0_encode, 0, Opcode_ae_neg32_Slot_ae_slot2_encode, Opcode_ae_neg32_Slot_ae_slot3_encode, Opcode_ae_neg32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_neg32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs32_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs32_Slot_ae_slot0_encode, 0, Opcode_ae_abs32_Slot_ae_slot2_encode, Opcode_ae_abs32_Slot_ae_slot3_encode, Opcode_ae_abs32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_abs32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg32_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_neg32_l_Slot_ae_slot2_encode, Opcode_ae_neg32_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add24s_Slot_ae_slot0_encode, 0, Opcode_ae_add24s_Slot_ae_slot2_encode, Opcode_ae_add24s_Slot_ae_slot3_encode, Opcode_ae_add24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub24s_Slot_ae_slot0_encode, 0, Opcode_ae_sub24s_Slot_ae_slot2_encode, Opcode_ae_sub24s_Slot_ae_slot3_encode, Opcode_ae_sub24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add32s_Slot_ae_slot0_encode, 0, Opcode_ae_add32s_Slot_ae_slot2_encode, Opcode_ae_add32s_Slot_ae_slot3_encode, Opcode_ae_add32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_add32s_Slot_ae3_slot0_encode, 0, Opcode_ae_add32s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, Opcode_ae_add32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub32s_Slot_ae_slot0_encode, 0, Opcode_ae_sub32s_Slot_ae_slot2_encode, Opcode_ae_sub32s_Slot_ae_slot3_encode, Opcode_ae_sub32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sub32s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sub32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsub32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsub32s_Slot_ae_slot0_encode, 0, Opcode_ae_addsub32s_Slot_ae_slot2_encode, Opcode_ae_addsub32s_Slot_ae_slot3_encode, Opcode_ae_addsub32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subadd32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_subadd32s_Slot_ae_slot0_encode, 0, Opcode_ae_subadd32s_Slot_ae_slot2_encode, Opcode_ae_subadd32s_Slot_ae_slot3_encode, Opcode_ae_subadd32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add16s_Slot_ae_slot0_encode, 0, Opcode_ae_add16s_Slot_ae_slot2_encode, Opcode_ae_add16s_Slot_ae_slot3_encode, Opcode_ae_add16s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_add16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_add16s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub16s_Slot_ae_slot0_encode, 0, Opcode_ae_sub16s_Slot_ae_slot2_encode, Opcode_ae_sub16s_Slot_ae_slot3_encode, Opcode_ae_sub16s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sub16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sub16s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_add32s_hl_lh_Slot_ae_slot0_encode, 0, Opcode_ae_add32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_add32s_hl_lh_Slot_ae_slot3_encode, Opcode_ae_add32s_hl_lh_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsub32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_addsub32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_addsub32s_hl_lh_Slot_ae_slot3_encode, Opcode_ae_addsub32s_hl_lh_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg24s_Slot_ae_slot0_encode, 0, Opcode_ae_neg24s_Slot_ae_slot2_encode, Opcode_ae_neg24s_Slot_ae_slot3_encode, Opcode_ae_neg24s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_neg24s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs24s_Slot_ae_slot0_encode, 0, Opcode_ae_abs24s_Slot_ae_slot2_encode, Opcode_ae_abs24s_Slot_ae_slot3_encode, Opcode_ae_abs24s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_abs24s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg32s_Slot_ae_slot0_encode, 0, Opcode_ae_neg32s_Slot_ae_slot2_encode, Opcode_ae_neg32s_Slot_ae_slot3_encode, Opcode_ae_neg32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_neg32s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_neg32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs32s_Slot_ae_slot0_encode, 0, Opcode_ae_abs32s_Slot_ae_slot2_encode, Opcode_ae_abs32s_Slot_ae_slot3_encode, Opcode_ae_abs32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_abs32s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_abs32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg16s_Slot_ae_slot0_encode, 0, Opcode_ae_neg16s_Slot_ae_slot2_encode, Opcode_ae_neg16s_Slot_ae_slot3_encode, Opcode_ae_neg16s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_neg16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_neg16s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs16s_Slot_ae_slot0_encode, 0, Opcode_ae_abs16s_Slot_ae_slot2_encode, Opcode_ae_abs16s_Slot_ae_slot3_encode, Opcode_ae_abs16s_Slot_ae2_slot0_encode, 0, Opcode_ae_abs16s_Slot_ae2_slot2_encode, Opcode_ae_abs16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_abs16s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_abs16s_Slot_ae4_slot2_encode, Opcode_ae_abs16s_Slot_ae4_slot3_encode, Opcode_ae_abs16s_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs16_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs16_Slot_ae_slot0_encode, 0, Opcode_ae_abs16_Slot_ae_slot2_encode, Opcode_ae_abs16_Slot_ae_slot3_encode, Opcode_ae_abs16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16js_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc16js_h_Slot_ae_slot2_encode, Opcode_ae_mulc16js_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc16js_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16js_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc16js_l_Slot_ae_slot2_encode, Opcode_ae_mulc16js_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc16js_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16js_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac16js_h_Slot_ae_slot2_encode, Opcode_ae_mulac16js_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac16js_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16js_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac16js_l_Slot_ae_slot2_encode, Opcode_ae_mulac16js_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac16js_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt16_encode_fns[] = { + 0, 0, 0, Opcode_ae_lt16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lt16_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_lt16_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_lt16_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lt16_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le16_encode_fns[] = { + 0, 0, 0, Opcode_ae_le16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_le16_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_le16_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_le16_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_le16_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq16_encode_fns[] = { + 0, 0, 0, Opcode_ae_eq16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_eq16_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_eq16_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_eq16_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_eq16_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt32_encode_fns[] = { + 0, 0, 0, Opcode_ae_lt32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lt32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_lt32_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_lt32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lt32_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le32_encode_fns[] = { + 0, 0, 0, Opcode_ae_le32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_le32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_le32_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_le32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_le32_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq32_encode_fns[] = { + 0, 0, 0, Opcode_ae_eq32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_eq32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_eq32_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_eq32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_eq32_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_min32_encode_fns[] = { + 0, 0, 0, Opcode_ae_min32_Slot_ae_slot0_encode, 0, Opcode_ae_min32_Slot_ae_slot2_encode, Opcode_ae_min32_Slot_ae_slot3_encode, Opcode_ae_min32_Slot_ae2_slot0_encode, 0, Opcode_ae_min32_Slot_ae2_slot2_encode, Opcode_ae_min32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_min32_Slot_ae4_slot2_encode, Opcode_ae_min32_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_max32_encode_fns[] = { + 0, 0, 0, Opcode_ae_max32_Slot_ae_slot0_encode, 0, Opcode_ae_max32_Slot_ae_slot2_encode, Opcode_ae_max32_Slot_ae_slot3_encode, Opcode_ae_max32_Slot_ae2_slot0_encode, 0, Opcode_ae_max32_Slot_ae2_slot2_encode, Opcode_ae_max32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_max32_Slot_ae4_slot2_encode, Opcode_ae_max32_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minmax32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_minmax32_Slot_ae_slot2_encode, Opcode_ae_minmax32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minmax16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_minmax16_Slot_ae_slot2_encode, Opcode_ae_minmax16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_min16_encode_fns[] = { + 0, 0, 0, Opcode_ae_min16_Slot_ae_slot0_encode, 0, Opcode_ae_min16_Slot_ae_slot2_encode, Opcode_ae_min16_Slot_ae_slot3_encode, Opcode_ae_min16_Slot_ae2_slot0_encode, 0, Opcode_ae_min16_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_min16_Slot_ae4_slot2_encode, Opcode_ae_min16_Slot_ae4_slot3_encode, Opcode_ae_min16_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_max16_encode_fns[] = { + 0, 0, 0, Opcode_ae_max16_Slot_ae_slot0_encode, 0, Opcode_ae_max16_Slot_ae_slot2_encode, Opcode_ae_max16_Slot_ae_slot3_encode, Opcode_ae_max16_Slot_ae2_slot0_encode, 0, Opcode_ae_max16_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_max16_Slot_ae4_slot2_encode, Opcode_ae_max16_Slot_ae4_slot3_encode, Opcode_ae_max16_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_add64_encode_fns[] = { + 0, 0, 0, Opcode_ae_add64_Slot_ae_slot0_encode, 0, Opcode_ae_add64_Slot_ae_slot2_encode, Opcode_ae_add64_Slot_ae_slot3_encode, Opcode_ae_add64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub64_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub64_Slot_ae_slot0_encode, 0, Opcode_ae_sub64_Slot_ae_slot2_encode, Opcode_ae_sub64_Slot_ae_slot3_encode, Opcode_ae_sub64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg64_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg64_Slot_ae_slot0_encode, 0, Opcode_ae_neg64_Slot_ae_slot2_encode, Opcode_ae_neg64_Slot_ae_slot3_encode, Opcode_ae_neg64_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_neg64_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs64_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs64_Slot_ae_slot0_encode, 0, Opcode_ae_abs64_Slot_ae_slot2_encode, Opcode_ae_abs64_Slot_ae_slot3_encode, Opcode_ae_abs64_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_abs64_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot0_encode, 0, Opcode_ae_addsq56s_Slot_ae_slot2_encode, Opcode_ae_addsq56s_Slot_ae_slot3_encode, Opcode_ae_addsq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot0_encode, 0, Opcode_ae_subsq56s_Slot_ae_slot2_encode, Opcode_ae_subsq56s_Slot_ae_slot3_encode, Opcode_ae_subsq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add64s_Slot_ae_slot0_encode, 0, Opcode_ae_add64s_Slot_ae_slot2_encode, Opcode_ae_add64s_Slot_ae_slot3_encode, Opcode_ae_add64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub64s_Slot_ae_slot0_encode, 0, Opcode_ae_sub64s_Slot_ae_slot2_encode, Opcode_ae_sub64s_Slot_ae_slot3_encode, Opcode_ae_sub64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot0_encode, 0, Opcode_ae_negsq56s_Slot_ae_slot2_encode, Opcode_ae_negsq56s_Slot_ae_slot3_encode, Opcode_ae_negsq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot0_encode, 0, Opcode_ae_abssq56s_Slot_ae_slot2_encode, Opcode_ae_abssq56s_Slot_ae_slot3_encode, Opcode_ae_abssq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg64s_Slot_ae_slot0_encode, 0, Opcode_ae_neg64s_Slot_ae_slot2_encode, Opcode_ae_neg64s_Slot_ae_slot3_encode, Opcode_ae_neg64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs64s_Slot_ae_slot0_encode, 0, Opcode_ae_abs64s_Slot_ae_slot2_encode, Opcode_ae_abs64s_Slot_ae_slot3_encode, Opcode_ae_abs64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_and_encode_fns[] = { + 0, 0, 0, Opcode_ae_and_Slot_ae_slot0_encode, 0, 0, Opcode_ae_and_Slot_ae_slot3_encode, Opcode_ae_and_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_and_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nand_encode_fns[] = { + 0, 0, 0, Opcode_ae_nand_Slot_ae_slot0_encode, 0, 0, Opcode_ae_nand_Slot_ae_slot3_encode, Opcode_ae_nand_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_or_encode_fns[] = { + 0, 0, 0, Opcode_ae_or_Slot_ae_slot0_encode, 0, 0, Opcode_ae_or_Slot_ae_slot3_encode, Opcode_ae_or_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_or_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_xor_encode_fns[] = { + 0, 0, 0, Opcode_ae_xor_Slot_ae_slot0_encode, 0, 0, Opcode_ae_xor_Slot_ae_slot3_encode, Opcode_ae_xor_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_xor_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai24_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai24_Slot_ae_slot3_encode, Opcode_ae_slai24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srli24_Slot_ae_slot3_encode, Opcode_ae_srli24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai24_Slot_ae_slot3_encode, Opcode_ae_srai24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas24_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas24_Slot_ae_slot3_encode, Opcode_ae_slas24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srls24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srls24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srls24_Slot_ae_slot3_encode, Opcode_ae_srls24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sras24_encode_fns[] = { + 0, 0, 0, Opcode_ae_sras24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sras24_Slot_ae_slot3_encode, Opcode_ae_sras24_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sras24_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai16_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai16_Slot_ae_slot3_encode, Opcode_ae_srai16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai16r_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai16r_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai16r_Slot_ae_slot3_encode, Opcode_ae_srai16r_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai32_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai32_Slot_ae_slot3_encode, Opcode_ae_slai32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli32_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srli32_Slot_ae_slot3_encode, Opcode_ae_srli32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai32_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai32_Slot_ae_slot3_encode, Opcode_ae_srai32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai32r_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai32r_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai32r_Slot_ae_slot3_encode, Opcode_ae_srai32r_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas32_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas32_Slot_ae_slot3_encode, Opcode_ae_slas32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srls32_encode_fns[] = { + 0, 0, 0, Opcode_ae_srls32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srls32_Slot_ae_slot3_encode, Opcode_ae_srls32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sras32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sras32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sras32_Slot_ae_slot3_encode, Opcode_ae_sras32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa32_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srla32_encode_fns[] = { + 0, 0, 0, Opcode_ae_srla32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srla32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_srla32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai16s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai16s_Slot_ae_slot3_encode, Opcode_ae_slai16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa16s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa16s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slaa16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa16s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa16s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sraa16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa16rs_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa16rs_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa16rs_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sraa16rs_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai24s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai24s_Slot_ae_slot3_encode, Opcode_ae_slai24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas24s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas24s_Slot_ae_slot3_encode, Opcode_ae_slas24s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slas24s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai32s_Slot_ae_slot3_encode, Opcode_ae_slai32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas32s_Slot_ae_slot3_encode, Opcode_ae_slas32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa32s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slaa32s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa32s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sraa32s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32rs_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa32rs_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa32rs_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slasq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_slasq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slasq56_Slot_ae_slot3_encode, Opcode_ae_slasq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot3_encode, Opcode_ae_srlsq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srasq56_Slot_ae_slot3_encode, Opcode_ae_srasq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaaq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaaq56_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaaq56_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slaaq56_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sraaq56_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai64_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai64_Slot_ae_slot3_encode, Opcode_ae_slai64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli64_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srli64_Slot_ae_slot3_encode, Opcode_ae_srli64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai64_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai64_Slot_ae_slot3_encode, Opcode_ae_srai64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas64_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas64_Slot_ae_slot3_encode, Opcode_ae_slas64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srls64_encode_fns[] = { + 0, 0, 0, Opcode_ae_srls64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srls64_Slot_ae_slot3_encode, Opcode_ae_srls64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sras64_encode_fns[] = { + 0, 0, 0, Opcode_ae_sras64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sras64_Slot_ae_slot3_encode, Opcode_ae_sras64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa64_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa64_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slaa64_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srla64_encode_fns[] = { + 0, 0, 0, Opcode_ae_srla64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srla64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa64_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaisq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaisq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slaisq56s_Slot_ae_slot3_encode, Opcode_ae_slaisq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slassq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slassq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slassq56s_Slot_ae_slot3_encode, Opcode_ae_slassq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaasq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaasq56s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaasq56s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slaasq56s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai64s_Slot_ae_slot3_encode, Opcode_ae_slai64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas64s_Slot_ae_slot3_encode, Opcode_ae_slas64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa64s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt64_encode_fns[] = { + 0, 0, 0, Opcode_ae_lt64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lt64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lt64_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lt64_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le64_encode_fns[] = { + 0, 0, 0, Opcode_ae_le64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_le64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_le64_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_le64_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq64_encode_fns[] = { + 0, 0, 0, Opcode_ae_eq64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_eq64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_eq64_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_eq64_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_max64_encode_fns[] = { + 0, 0, 0, Opcode_ae_max64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_max64_Slot_ae_slot3_encode, Opcode_ae_max64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_min64_encode_fns[] = { + 0, 0, 0, Opcode_ae_min64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_min64_Slot_ae_slot3_encode, Opcode_ae_min64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsa64_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsa64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsa64_Slot_ae2_slot0_encode, Opcode_ae_nsa64_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsaz16_0_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsaz16_0_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsaz16_0_Slot_ae2_slot0_encode, Opcode_ae_nsaz16_0_Slot_ae2_slot1_encode, 0, Opcode_ae_nsaz16_0_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsaz32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsaz32_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsaz32_l_Slot_ae2_slot0_encode, Opcode_ae_nsaz32_l_Slot_ae2_slot1_encode, 0, Opcode_ae_nsaz32_l_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_ll_Slot_ae_slot2_encode, Opcode_ae_muls32f48p16s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32f48p16s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32s_ll_Slot_ae_slot2_encode, Opcode_ae_mulf32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32_ll_Slot_ae_slot2_encode, Opcode_ae_mul32_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32r_ll_Slot_ae_slot2_encode, Opcode_ae_mulf32r_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32r_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32r_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32ra_ll_Slot_ae_slot2_encode, Opcode_ae_mulf32ra_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32ra_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_lh_Slot_ae_slot2_encode, Opcode_ae_muls32f48p16s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32f48p16s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32s_lh_Slot_ae_slot2_encode, Opcode_ae_mulf32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32_lh_Slot_ae_slot2_encode, Opcode_ae_mul32_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32r_lh_Slot_ae_slot2_encode, Opcode_ae_mulf32r_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32r_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32r_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32ra_lh_Slot_ae_slot2_encode, Opcode_ae_mulf32ra_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32ra_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_hh_Slot_ae_slot2_encode, Opcode_ae_muls32f48p16s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32f48p16s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32s_hh_Slot_ae_slot2_encode, Opcode_ae_mulf32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32_hh_Slot_ae_slot2_encode, Opcode_ae_mul32_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32r_hh_Slot_ae_slot2_encode, Opcode_ae_mulf32r_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32r_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32r_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32ra_hh_Slot_ae_slot2_encode, Opcode_ae_mulf32ra_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32ra_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_ll_Slot_ae_slot2_encode, Opcode_ae_mulas32f48p16s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulas32f48p16s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32s_ll_Slot_ae_slot2_encode, Opcode_ae_mulaf32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32_ll_Slot_ae_slot2_encode, Opcode_ae_mula32_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32r_ll_Slot_ae_slot2_encode, Opcode_ae_mulaf32r_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32r_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32r_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32ra_ll_Slot_ae_slot2_encode, Opcode_ae_mulaf32ra_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32ra_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_lh_Slot_ae_slot2_encode, Opcode_ae_mulas32f48p16s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulas32f48p16s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32s_lh_Slot_ae_slot2_encode, Opcode_ae_mulaf32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32_lh_Slot_ae_slot2_encode, Opcode_ae_mula32_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32r_lh_Slot_ae_slot2_encode, Opcode_ae_mulaf32r_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32r_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32r_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32ra_lh_Slot_ae_slot2_encode, Opcode_ae_mulaf32ra_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32ra_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_hh_Slot_ae_slot2_encode, Opcode_ae_mulas32f48p16s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulas32f48p16s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32s_hh_Slot_ae_slot2_encode, Opcode_ae_mulaf32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32_hh_Slot_ae_slot2_encode, Opcode_ae_mula32_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32r_hh_Slot_ae_slot2_encode, Opcode_ae_mulaf32r_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32r_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32r_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32ra_hh_Slot_ae_slot2_encode, Opcode_ae_mulaf32ra_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32ra_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_ll_Slot_ae_slot2_encode, Opcode_ae_mulss32f48p16s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulss32f48p16s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32s_ll_Slot_ae_slot2_encode, Opcode_ae_mulsf32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32_ll_Slot_ae_slot2_encode, Opcode_ae_muls32_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32r_ll_Slot_ae_slot2_encode, Opcode_ae_mulsf32r_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32r_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32r_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32ra_ll_Slot_ae_slot2_encode, Opcode_ae_mulsf32ra_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32ra_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_lh_Slot_ae_slot2_encode, Opcode_ae_mulss32f48p16s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulss32f48p16s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32s_lh_Slot_ae_slot2_encode, Opcode_ae_mulsf32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32_lh_Slot_ae_slot2_encode, Opcode_ae_muls32_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32r_lh_Slot_ae_slot2_encode, Opcode_ae_mulsf32r_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32r_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32r_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32ra_lh_Slot_ae_slot2_encode, Opcode_ae_mulsf32ra_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32ra_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_hh_Slot_ae_slot2_encode, Opcode_ae_mulss32f48p16s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulss32f48p16s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32s_hh_Slot_ae_slot2_encode, Opcode_ae_mulsf32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32_hh_Slot_ae_slot2_encode, Opcode_ae_muls32_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32r_hh_Slot_ae_slot2_encode, Opcode_ae_mulsf32r_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32r_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32r_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32ra_hh_Slot_ae_slot2_encode, Opcode_ae_mulsf32ra_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32ra_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32u_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32u_ll_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mul32u_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32u_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32u_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32u_ll_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mula32u_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32u_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32u_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32u_ll_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_muls32u_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32u_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_33_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_33_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_33_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_22_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_22_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_32_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_21_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_21_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_21_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_31_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_31_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_31_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_30_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_30_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_30_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_10_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_10_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_10_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_20_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_20_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_20_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_11_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_11_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_11_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_00_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf16ss_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf16ss_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_33_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_33_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_33_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_22_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_22_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_32_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_21_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_21_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_21_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_31_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_31_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_31_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_30_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_30_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_30_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_10_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_10_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_10_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_20_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_20_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_20_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_11_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_11_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_11_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_00_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf16ss_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf16ss_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_33_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_33_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_33_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_22_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_22_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_32_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_21_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_21_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_21_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_31_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_31_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_31_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_30_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_30_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_30_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_10_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_10_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_10_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_20_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_20_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_20_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_11_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_11_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_11_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_00_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf16ss_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf16ss_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16s_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul16s_00_Slot_ae_slot2_encode, Opcode_ae_mul16s_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul16s_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul16s_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16s_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula16s_00_Slot_ae_slot2_encode, Opcode_ae_mula16s_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula16s_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula16s_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls16s_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls16s_00_Slot_ae_slot2_encode, Opcode_ae_muls16s_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls16s_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls16s_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_33_22_Slot_ae_slot2_encode, Opcode_ae_mulaafd16ss_33_22_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_13_02_Slot_ae_slot2_encode, Opcode_ae_mulaafd16ss_13_02_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_11_00_Slot_ae_slot2_encode, Opcode_ae_mulaafd16ss_11_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_33_22_Slot_ae_slot2_encode, Opcode_ae_mulssfd16ss_33_22_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_13_02_Slot_ae_slot2_encode, Opcode_ae_mulssfd16ss_13_02_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_11_00_Slot_ae_slot2_encode, Opcode_ae_mulssfd16ss_11_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_33_22_Slot_ae_slot2_encode, Opcode_ae_mulzaafd16ss_33_22_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_13_02_Slot_ae_slot2_encode, Opcode_ae_mulzaafd16ss_13_02_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_11_00_Slot_ae_slot2_encode, Opcode_ae_mulzaafd16ss_11_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_33_22_Slot_ae_slot2_encode, Opcode_ae_mulzssfd16ss_33_22_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_13_02_Slot_ae_slot2_encode, Opcode_ae_mulzssfd16ss_13_02_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_11_00_Slot_ae_slot2_encode, Opcode_ae_mulzssfd16ss_11_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf48q32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf48q32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulf48q32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf48q32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf48q32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf48q32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf48q32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulf48q32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf48q32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf48q32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulq32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulq32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf48q32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulaf48q32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf48q32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf48q32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulaf48q32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf48q32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf48q32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulsf48q32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf48q32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf48q32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulsf48q32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf48q32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24x2ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp24x2ra_Slot_ae_slot2_encode, Opcode_ae_mulfp24x2ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp24x2ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp24x2ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24x2r_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp24x2r_Slot_ae_slot2_encode, Opcode_ae_mulfp24x2r_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp24x2r_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp24x2r_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24x2ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp24x2ra_Slot_ae_slot2_encode, Opcode_ae_mulafp24x2ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp24x2ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp24x2ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24x2r_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp24x2r_Slot_ae_slot2_encode, Opcode_ae_mulafp24x2r_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp24x2r_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp24x2r_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24x2ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp24x2ra_Slot_ae_slot2_encode, Opcode_ae_mulsfp24x2ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp24x2ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp24x2ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24x2r_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp24x2r_Slot_ae_slot2_encode, Opcode_ae_mulsfp24x2r_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp24x2r_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp24x2r_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaad32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaad32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzasd32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzasd32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsad32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzsad32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssd32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzssd32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaafd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaad32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaafd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaad32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulasfd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulasd32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulasfd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulasd32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsafd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulsafd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsad32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulsad32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssfd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssd32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulssfd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulssd32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l0_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l0_Slot_ae_slot2_encode, Opcode_ae_mul32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l1_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l1_Slot_ae_slot2_encode, Opcode_ae_mul32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l2_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l2_Slot_ae_slot2_encode, Opcode_ae_mul32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l3_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l3_Slot_ae_slot2_encode, Opcode_ae_mul32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h0_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h0_Slot_ae_slot2_encode, Opcode_ae_mul32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h1_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h1_Slot_ae_slot2_encode, Opcode_ae_mul32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h2_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h2_Slot_ae_slot2_encode, Opcode_ae_mul32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h3_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h3_Slot_ae_slot2_encode, Opcode_ae_mul32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l0_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l0_Slot_ae_slot2_encode, Opcode_ae_mula32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l1_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l1_Slot_ae_slot2_encode, Opcode_ae_mula32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l2_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l2_Slot_ae_slot2_encode, Opcode_ae_mula32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l3_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l3_Slot_ae_slot2_encode, Opcode_ae_mula32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h0_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h0_Slot_ae_slot2_encode, Opcode_ae_mula32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h1_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h1_Slot_ae_slot2_encode, Opcode_ae_mula32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h2_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h2_Slot_ae_slot2_encode, Opcode_ae_mula32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h3_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h3_Slot_ae_slot2_encode, Opcode_ae_mula32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l0_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l0_Slot_ae_slot2_encode, Opcode_ae_muls32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l1_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l1_Slot_ae_slot2_encode, Opcode_ae_muls32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l2_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l2_Slot_ae_slot2_encode, Opcode_ae_muls32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l3_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l3_Slot_ae_slot2_encode, Opcode_ae_muls32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h0_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h0_Slot_ae_slot2_encode, Opcode_ae_muls32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h1_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h1_Slot_ae_slot2_encode, Opcode_ae_muls32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h2_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h2_Slot_ae_slot2_encode, Opcode_ae_muls32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h3_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h3_Slot_ae_slot2_encode, Opcode_ae_muls32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulaad32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulaad32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulasd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulasd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsad32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulsad32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsad32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulsad32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulssd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulssd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsad32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzsad32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsad32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzsad32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae_slot2_encode, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae_slot2_encode, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae_slot2_encode, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae_slot2_encode, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h2_l3_Slot_ae_slot2_encode, Opcode_ae_mulaad32x16_h2_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h0_l1_Slot_ae_slot2_encode, Opcode_ae_mulaad32x16_h0_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x16x2_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp32x16x2_h_Slot_ae_slot2_encode, Opcode_ae_mulp32x16x2_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp32x16x2_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp32x16x2_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2rs_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_h_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2rs_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2rs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2ras_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_h_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2ras_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_h_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x16x2_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp32x16x2_l_Slot_ae_slot2_encode, Opcode_ae_mulp32x16x2_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp32x16x2_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp32x16x2_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2rs_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_l_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2rs_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2rs_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2ras_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_l_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2ras_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_l_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x16x2_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap32x16x2_h_Slot_ae_slot2_encode, Opcode_ae_mulap32x16x2_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap32x16x2_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap32x16x2_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2rs_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_h_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2rs_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2rs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2ras_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_h_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2ras_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_h_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x16x2_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap32x16x2_l_Slot_ae_slot2_encode, Opcode_ae_mulap32x16x2_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap32x16x2_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap32x16x2_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2rs_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_l_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2rs_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2rs_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2ras_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_l_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2ras_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_l_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x16x2_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_h_Slot_ae_slot2_encode, Opcode_ae_mulsp32x16x2_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp32x16x2_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2rs_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2ras_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_h_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x16x2_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_l_Slot_ae_slot2_encode, Opcode_ae_mulsp32x16x2_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp32x16x2_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2rs_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2ras_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_l_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp32x2_Slot_ae_slot2_encode, Opcode_ae_mulp32x2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp32x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp32x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2rs_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2rs_Slot_ae_slot2_encode, Opcode_ae_mulfp32x2rs_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x2rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x2rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2ras_Slot_ae_slot2_encode, Opcode_ae_mulfp32x2ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x2ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x2ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2ts_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2ts_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulfp32x2ts_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x2ts_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x2t_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp32x2t_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulp32x2t_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp32x2t_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap32x2_Slot_ae_slot2_encode, Opcode_ae_mulap32x2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap32x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap32x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2rs_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2rs_Slot_ae_slot2_encode, Opcode_ae_mulafp32x2rs_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x2rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x2rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2ras_Slot_ae_slot2_encode, Opcode_ae_mulafp32x2ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x2ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x2ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2ts_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2ts_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulafp32x2ts_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x2ts_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x2t_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap32x2t_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulap32x2t_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap32x2t_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp32x2_Slot_ae_slot2_encode, Opcode_ae_mulsp32x2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp32x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp32x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2rs_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2rs_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x2rs_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x2rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x2rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2ras_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x2ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x2ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x2ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2ts_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2ts_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulsfp32x2ts_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x2ts_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x2t_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp32x2t_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulsp32x2t_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp32x2t_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp16x4s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp16x4s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp16x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp16x4ras_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc32_Slot_ae_slot2_encode, Opcode_ae_mulc32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc32_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulc32_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc24ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc24ra_Slot_ae_slot2_encode, Opcode_ae_mulfc24ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc24ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfc24ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32ras_Slot_ae_slot2_encode, Opcode_ae_mulfc32ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc32ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfc32ras_Slot_ae5_slot2_encode, 0, 0, Opcode_ae_mulfc32ras_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfc32ras_Slot_ae4_slot2_encode, Opcode_ae_mulfc32ras_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32x16_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc32x16_l_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulc32x16_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulc32x16_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32x16ras_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae_slot2_encode, Opcode_ae_mulfc32x16ras_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae5_slot2_encode, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32x16_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc32x16_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulc32x16_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulc32x16_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32x16ras_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae_slot2_encode, Opcode_ae_mulfc32x16ras_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae5_slot2_encode, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac32_Slot_ae_slot2_encode, Opcode_ae_mulac32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac32_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulac32_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc24ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc24ra_Slot_ae_slot2_encode, Opcode_ae_mulafc24ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc24ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafc24ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32ras_Slot_ae_slot2_encode, Opcode_ae_mulafc32ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc32ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafc32ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32x16_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac32x16_l_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulac32x16_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulac32x16_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32x16ras_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_l_Slot_ae_slot2_encode, Opcode_ae_mulafc32x16ras_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc32x16ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32x16_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac32x16_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulac32x16_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulac32x16_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32x16ras_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_h_Slot_ae_slot2_encode, Opcode_ae_mulafc32x16ras_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc32x16ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16x4ss_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf16x4ss_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16x4ss_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf16x4ss_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16x4ss_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf16x4ss_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul16x4s_Slot_ae_slot2_encode, Opcode_ae_mul16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul16x4s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula16x4s_Slot_ae_slot2_encode, Opcode_ae_mula16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls16x4s_Slot_ae_slot2_encode, Opcode_ae_muls16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul16x4_Slot_ae_slot2_encode, Opcode_ae_mul16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul16x4_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula16x4_Slot_ae_slot2_encode, Opcode_ae_mula16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls16x4_Slot_ae_slot2_encode, Opcode_ae_muls16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2s_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2s_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2s_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x2s_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2ra_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2ra_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2ra_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x2ra_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2s_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2s_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2s_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x2s_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2ra_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2ra_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2ra_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x2ra_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2s_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2s_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2s_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x2s_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2ra_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2ra_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2ra_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x2ra_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2s_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2s_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2s_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x2s_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2ra_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2ra_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2ra_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x2ra_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc16s_h_Slot_ae_slot2_encode, Opcode_ae_mulc16s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc16s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc16s_l_Slot_ae_slot2_encode, Opcode_ae_mulc16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac16s_h_Slot_ae_slot2_encode, Opcode_ae_mulac16s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac16s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac16s_l_Slot_ae_slot2_encode, Opcode_ae_mulac16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc16ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc16ras_Slot_ae_slot2_encode, Opcode_ae_mulfc16ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc16ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc16ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc16ras_Slot_ae_slot2_encode, Opcode_ae_mulafc16ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc16ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16js_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul16js_Slot_ae_slot3_encode, Opcode_ae_mul16js_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng16ras_s1_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot0_encode, 0, Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot2_encode, Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot3_encode, Opcode_ae_addandsubrng16ras_s1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng16ras_s1_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsubrng16ras_s1_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng16ras_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot0_encode, 0, Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot2_encode, Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot3_encode, Opcode_ae_addandsubrng16ras_s2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng16ras_s2_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsubrng16ras_s2_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_conj16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_conj16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq16x2_fir_3_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_3_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_3_Slot_ae7_slot2_encode, Opcode_ae_mulfq16x2_fir_3_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq16x2_fir_2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_2_Slot_ae7_slot2_encode, Opcode_ae_mulfq16x2_fir_2_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq16x2_fir_1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_1_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_1_Slot_ae7_slot2_encode, Opcode_ae_mulfq16x2_fir_1_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq16x2_fir_0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_0_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_0_Slot_ae7_slot2_encode, Opcode_ae_mulfq16x2_fir_0_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq16x2_fir_3_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_3_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_3_Slot_ae7_slot2_encode, Opcode_ae_mulafq16x2_fir_3_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq16x2_fir_2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_2_Slot_ae7_slot2_encode, Opcode_ae_mulafq16x2_fir_2_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq16x2_fir_1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_1_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_1_Slot_ae7_slot2_encode, Opcode_ae_mulafq16x2_fir_1_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq16x2_fir_0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_0_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_0_Slot_ae7_slot2_encode, Opcode_ae_mulafq16x2_fir_0_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaafq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaafq32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaafq32x16_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaafq32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaafq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaafq32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaafq32x16_Slot_ae7_slot2_encode, Opcode_ae_mulaaaafq32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaaq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaaq32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaaq32x16_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaaq32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaaq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaaq32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaaq32x16_Slot_ae7_slot2_encode, Opcode_ae_mulaaaaq32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul16_00_Slot_ae_slot2_encode, Opcode_ae_mul16_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul16_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul16_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula16_00_Slot_ae_slot2_encode, Opcode_ae_mula16_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula16_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula16_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaaq16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaaaaq16_Slot_ae_slot2_encode, Opcode_ae_mulzaaaaq16_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaaaaq16_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaaaaq16_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaaq16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaaaaq16_Slot_ae_slot2_encode, Opcode_ae_mulaaaaq16_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaaaaq16_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaaaaq16_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_div64d32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_div64d32_h_Slot_ae_slot0_encode, 0, Opcode_ae_div64d32_h_Slot_ae_slot2_encode, Opcode_ae_div64d32_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_div64d32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_div64d32_l_Slot_ae_slot0_encode, 0, Opcode_ae_div64d32_l_Slot_ae_slot2_encode, Opcode_ae_div64d32_l_Slot_ae_slot3_encode, 0, 0, 0, Opcode_ae_div64d32_l_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sha32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl32t_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16t_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16c_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16c_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16c_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16c_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldsht_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = { + 0, 0, 0, Opcode_ae_lb_Slot_ae_slot0_encode, Opcode_ae_lb_Slot_ae_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_lb_Slot_ae3_slot0_encode, Opcode_ae_lb_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = { + 0, 0, 0, Opcode_ae_lbi_Slot_ae_slot0_encode, Opcode_ae_lbi_Slot_ae_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_lbi_Slot_ae3_slot0_encode, Opcode_ae_lbi_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbk_Slot_ae3_slot0_encode, Opcode_ae_lbk_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbki_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbs_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbsi_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbsi_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = { + 0, 0, 0, Opcode_ae_db_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_db_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = { + 0, 0, 0, Opcode_ae_dbi_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_dbi_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_db_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_dbi_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_db_ic1_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_dbi_ic1_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_db_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_dbi_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_ardecnorm16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_ardecnorm16_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbki_dbi_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbki_dbi_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbki_dbi_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbki_dbi_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbki_dbi_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbki_dbi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbi_dbi_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbi_dbi_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbi_dbi_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbi_dbi_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbi_dbi_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbi_dbi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbk_db_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbk_db_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbk_db_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbk_db_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbk_db_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbk_db_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lb_db_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lb_db_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lb_db_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lb_db_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lb_db_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lb_db_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vlel32t_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vlel16t_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sb_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbi_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vles16c_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbf_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sb_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbi_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vles16c_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbf_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sb_ic1_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbi_ic1_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vles16c_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbf_ic1_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sb_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbi_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vles16c_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbf_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sext32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movae_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movae_Slot_ae3_slot0_encode, Opcode_ae_movae_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movea_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movea_Slot_ae3_slot0_encode, Opcode_ae_movea_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_moveep_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_moveep_Slot_ae_slot2_encode, Opcode_ae_moveep_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext72_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sext72_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add72_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_add72_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub72_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sub72_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add72x64_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_add72x64_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub72x64_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sub72x64_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32ep_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32ep_hh_Slot_ae_slot2_encode, Opcode_ae_mul32ep_hh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32ep_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32ep_hh_Slot_ae_slot2_encode, Opcode_ae_mula32ep_hh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32ep_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32ep_hh_Slot_ae_slot2_encode, Opcode_ae_muls32ep_hh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32ep_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaad32ep_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32ep_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssd32ep_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32ep_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaad32ep_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32ep_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssd32ep_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32usep_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32usep_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaad32usep_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32usep_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32usep_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaad32usep_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32usep_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32usep_lh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32usep_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32usep_lh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32usep_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32usep_ll_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32usep_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32usep_ll_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai72_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_srai72_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai72_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_slai72_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat64s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sat64s_Slot_ae_slot2_encode, Opcode_ae_sat64s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16si_n_encode_fns[] = { + 0, 0, Opcode_ae_l16si_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16ui_n_encode_fns[] = { + 0, 0, Opcode_ae_l16ui_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16i_n_encode_fns[] = { + 0, 0, Opcode_ae_s16i_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lalign128_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_lalign128_i_Slot_ae_slot0_encode, Opcode_ae_lalign128_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_lalign128_i_Slot_ae2_slot0_encode, Opcode_ae_lalign128_i_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lalign128_i_Slot_ae7_slot0_encode, Opcode_ae_lalign128_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_lalign128_i_Slot_ae8_slot0_encode, Opcode_ae_lalign128_i_Slot_ae8_slot1_encode, 0, Opcode_ae_lalign128_i_Slot_ae9_slot0_encode, Opcode_ae_lalign128_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_lalign128_i_Slot_ae10_slot0_encode, Opcode_ae_lalign128_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_salign128_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_salign128_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_salign128_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la128_pp_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_la128_pp_Slot_ae_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la128_pp_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa128pos_fp_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa128pos_fp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa128pos_fp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x4s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x4s_ip_Slot_ae_slot0_encode, Opcode_ae_la8x4s_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x4s_ip_Slot_ae2_slot0_encode, Opcode_ae_la8x4s_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x4s_ip_Slot_ae8_slot0_encode, Opcode_ae_la8x4s_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x4s_ip_Slot_ae9_slot0_encode, Opcode_ae_la8x4s_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x4s_ip_Slot_ae10_slot0_encode, Opcode_ae_la8x4s_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x4u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x4u_ip_Slot_ae_slot0_encode, Opcode_ae_la8x4u_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x4u_ip_Slot_ae2_slot0_encode, Opcode_ae_la8x4u_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x4u_ip_Slot_ae8_slot0_encode, Opcode_ae_la8x4u_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x4u_ip_Slot_ae9_slot0_encode, Opcode_ae_la8x4u_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x4u_ip_Slot_ae10_slot0_encode, Opcode_ae_la8x4u_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2_ip_Slot_ae_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ip_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2_ip_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ip_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2_ip_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ip_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2_ip_Slot_ae_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ip_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2_ip_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ip_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2_ip_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ip_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2_ip_Slot_ae_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ip_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2_ip_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ip_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2_ip_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ip_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2_ic_Slot_ae_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2_ic_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2_ic_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2_ic_Slot_ae_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2_ic_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2_ic_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2_ic_Slot_ae_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2_ic_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2_ic_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2_ic1_Slot_ae_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic1_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2_ic1_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic1_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2_ic1_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic1_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2_ic1_Slot_ae_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic1_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2_ic1_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic1_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2_ic1_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic1_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2_ic1_Slot_ae_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic1_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2_ic1_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic1_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2_ic1_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic1_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2_ic2_Slot_ae_slot0_encode, Opcode_ae_la8x8x2_ic2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic2_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2_ic2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2_ic2_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2_ic2_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2_ic2_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2_ic2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2_ic2_Slot_ae_slot0_encode, Opcode_ae_la16x4x2_ic2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic2_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2_ic2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2_ic2_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2_ic2_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2_ic2_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2_ic2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2_ic2_Slot_ae_slot0_encode, Opcode_ae_la32x2x2_ic2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic2_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2_ic2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2_ic2_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2_ic2_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2_ic2_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2_ic2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa8x8x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa16x4x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa32x2x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8x2_ic_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8x2_ic_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa8x8x2_ic_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4x2_ic_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4x2_ic_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa16x4x2_ic_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2x2_ic_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2x2_ic_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa32x2x2_ic_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8x2_ic1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa8x8x2_ic1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4x2_ic1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa16x4x2_ic1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2x2_ic1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa32x2x2_ic1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8x2_ic2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8x2_ic2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa8x8x2_ic2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4x2_ic2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4x2_ic2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa16x4x2_ic2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2x2_ic2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2x2_ic2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa32x2x2_ic2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs8_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_abs8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs8s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_abs8s_Slot_ae_slot3_encode, Opcode_ae_abs8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_abs8s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg8s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_neg8s_Slot_ae_slot3_encode, Opcode_ae_neg8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_neg8s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add8_encode_fns[] = { + 0, 0, 0, Opcode_ae_add8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_add8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub8_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sub8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_max8_encode_fns[] = { + 0, 0, 0, Opcode_ae_max8_Slot_ae_slot0_encode, 0, Opcode_ae_max8_Slot_ae_slot2_encode, 0, Opcode_ae_max8_Slot_ae2_slot0_encode, 0, Opcode_ae_max8_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_max8_Slot_ae4_slot2_encode, Opcode_ae_max8_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_min8_encode_fns[] = { + 0, 0, 0, Opcode_ae_min8_Slot_ae_slot0_encode, 0, Opcode_ae_min8_Slot_ae_slot2_encode, 0, Opcode_ae_min8_Slot_ae2_slot0_encode, 0, Opcode_ae_min8_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_min8_Slot_ae4_slot2_encode, Opcode_ae_min8_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add8s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add8s_Slot_ae_slot3_encode, Opcode_ae_add8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_add8s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub8s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sub8s_Slot_ae_slot3_encode, Opcode_ae_sub8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sub8s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le8_encode_fns[] = { + 0, 0, 0, Opcode_ae_le8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_le8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt8_encode_fns[] = { + 0, 0, 0, Opcode_ae_lt8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lt8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq8_encode_fns[] = { + 0, 0, 0, Opcode_ae_eq8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_eq8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satu16x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_satu16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_satu16x4_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat32x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sat32x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satu32x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_satu32x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat8x8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sat8x8x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satu8x8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_satu8x8x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat8x4x32_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sat8x4x32_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sat8x4x32_l_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satu8x4x32_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_satu8x4x32_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_satu8x4x32_l_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round8x8f16ssym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round8x8f16ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round8x8f16sasym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round8x8f16sasym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round8x4f32ssym_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round8x4f32ssym_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round8x4f32sasym_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round8x4f32sasym_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda8_encode_fns[] = { + 0, 0, 0, Opcode_ae_movda8_Slot_ae_slot0_encode, Opcode_ae_movda8_Slot_ae_slot1_encode, 0, 0, Opcode_ae_movda8_Slot_ae2_slot0_encode, Opcode_ae_movda8_Slot_ae2_slot1_encode, 0, Opcode_ae_movda8_Slot_ae3_slot0_encode, Opcode_ae_movda8_Slot_ae3_slot1_encode, Opcode_ae_movda8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad8_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad8_Slot_ae2_slot0_encode, Opcode_ae_movad8_Slot_ae2_slot1_encode, 0, Opcode_ae_movad8_Slot_ae3_slot0_encode, 0, Opcode_ae_movad8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movdx2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movdx2_Slot_ae_slot0_encode, 0, Opcode_ae_movdx2_Slot_ae_slot2_encode, Opcode_ae_movdx2_Slot_ae_slot3_encode, Opcode_ae_movdx2_Slot_ae2_slot0_encode, Opcode_ae_movdx2_Slot_ae2_slot1_encode, 0, Opcode_ae_movdx2_Slot_ae3_slot0_encode, 0, Opcode_ae_movdx2_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_movdx2_Slot_ae6_slot0_encode, Opcode_ae_movdx2_Slot_ae6_slot1_encode, Opcode_ae_movdx2_Slot_ae6_slot2_encode, Opcode_ae_movdx2_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movdx2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsub32j_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsub32j_Slot_ae_slot0_encode, 0, Opcode_ae_addandsub32j_Slot_ae_slot2_encode, Opcode_ae_addandsub32j_Slot_ae_slot3_encode, Opcode_ae_addandsub32j_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32j_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsub32j_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addw8_encode_fns[] = { + 0, 0, 0, Opcode_ae_addw8_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addw8_Slot_ae_slot3_encode, Opcode_ae_addw8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addw8_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addw16_encode_fns[] = { + 0, 0, 0, Opcode_ae_addw16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addw16_Slot_ae_slot3_encode, Opcode_ae_addw16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addw16_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addw32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addw32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addw32_Slot_ae_slot3_encode, Opcode_ae_addw32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addw32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subw8_encode_fns[] = { + 0, 0, 0, Opcode_ae_subw8_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subw8_Slot_ae_slot3_encode, Opcode_ae_subw8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subw8_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subw16_encode_fns[] = { + 0, 0, 0, Opcode_ae_subw16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subw16_Slot_ae_slot3_encode, Opcode_ae_subw16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subw16_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subw32_encode_fns[] = { + 0, 0, 0, Opcode_ae_subw32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subw32_Slot_ae_slot3_encode, Opcode_ae_subw32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subw32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_accw8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_accw8_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_accw8_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_accw16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_accw16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_accw16_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_accw32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_accw32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_accw32_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addw8u_encode_fns[] = { + 0, 0, 0, Opcode_ae_addw8u_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addw8u_Slot_ae_slot3_encode, Opcode_ae_addw8u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addw8u_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subw8u_encode_fns[] = { + 0, 0, 0, Opcode_ae_subw8u_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subw8u_Slot_ae_slot3_encode, Opcode_ae_subw8u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subw8u_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_accw8u_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_accw8u_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_accw8u_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulfp32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulafp32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulfp32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulafp32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulasf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsaf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulssf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulasf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsaf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulssf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32s_hh_Slot_ae_slot2_encode, Opcode_ae_mul32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32s_hh_Slot_ae_slot2_encode, Opcode_ae_mula32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32s_hh_Slot_ae_slot2_encode, Opcode_ae_muls32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32s_ll_Slot_ae_slot2_encode, Opcode_ae_mul32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32s_ll_Slot_ae_slot2_encode, Opcode_ae_mula32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32s_ll_Slot_ae_slot2_encode, Opcode_ae_muls32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32s_hl_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32s_hl_Slot_ae_slot2_encode, Opcode_ae_mul32s_hl_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32s_hl_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32s_hl_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32s_hl_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32s_hl_Slot_ae_slot2_encode, Opcode_ae_mula32s_hl_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32s_hl_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32s_hl_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32s_hl_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32s_hl_Slot_ae_slot2_encode, Opcode_ae_muls32s_hl_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32s_hl_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32s_hl_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32s_lh_Slot_ae_slot2_encode, Opcode_ae_mul32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32s_lh_Slot_ae_slot2_encode, Opcode_ae_mula32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32s_lh_Slot_ae_slot2_encode, Opcode_ae_muls32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaad32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzasd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsad32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzsad32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsad32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsad32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaad32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulasd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsad32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulsad32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsad32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsad32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaad32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzasd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsad32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzsad32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsad32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsad32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzssd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaad32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulasd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsad32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulsad32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsad32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsad32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulssd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x2ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x2ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x2ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x2ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x2ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x2ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x2ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x2ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x2ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x2ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x2ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x2ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsaf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsaf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x2r_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x2r_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x2r_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x2r_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x2r_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x2r_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x2r_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x2r_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x2r_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x2r_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x2r_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x2r_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfc32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafc32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfcj32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafcj32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj32ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfcj32ras_Slot_ae_slot2_encode, Opcode_ae_mulfcj32ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfcj32ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfcj32ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj32ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafcj32ras_Slot_ae_slot2_encode, Opcode_ae_mulafcj32ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafcj32ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafcj32ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2p32x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulf2p32x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf2p32x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulaf2p32x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf2p32x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulsf2p32x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2p32x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulf2p32x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf2p32x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulaf2p32x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf2p32x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulsf2p32x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x2s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulp32x2s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2p32x4s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4s_Slot_ae7_slot2_encode, Opcode_ae_mul2p32x4s_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2p32x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4_Slot_ae7_slot2_encode, Opcode_ae_mul2p32x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2p32x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula2p32x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2p32x4_Slot_ae7_slot2_encode, Opcode_ae_mula2p32x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls2p32x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muls2p32x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muls2p32x4_Slot_ae7_slot2_encode, Opcode_ae_muls2p32x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2p32x4t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4t_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4t_Slot_ae7_slot2_encode, Opcode_ae_mul2p32x4t_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2p32x4t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula2p32x4t_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2p32x4t_Slot_ae7_slot2_encode, Opcode_ae_mula2p32x4t_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls2p32x4t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muls2p32x4t_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muls2p32x4t_Slot_ae7_slot2_encode, Opcode_ae_muls2p32x4t_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaa32x2_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaa32x2_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzss32x2_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzss32x2_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaa32x2_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaa32x2_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32x2_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulss32x2_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulcj32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulcj32_Slot_ae_slot2_encode, Opcode_ae_mulcj32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulcj32_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulcj32_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulacj32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulacj32_Slot_ae_slot2_encode, Opcode_ae_mulacj32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulacj32_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulacj32_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muladdf32rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muladdf32rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muladdf32rs_Slot_ae7_slot2_encode, Opcode_ae_muladdf32rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muladdf32ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muladdf32ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muladdf32ras_Slot_ae7_slot2_encode, Opcode_ae_muladdf32ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsubf32rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsubf32rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsubf32rs_Slot_ae7_slot2_encode, Opcode_ae_mulsubf32rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsubf32ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsubf32ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsubf32ras_Slot_ae7_slot2_encode, Opcode_ae_mulsubf32ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32ra_Slot_ae_slot2_encode, Opcode_ae_mulfc32ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc32ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfc32ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32ra_Slot_ae_slot2_encode, Opcode_ae_mulafc32ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc32ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafc32ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulcj32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulcj32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulacj32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulacj32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulc32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulac32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2d32x2ws_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2d32x2ws_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2d32x2ws_Slot_ae7_slot2_encode, Opcode_ae_mulf2d32x2ws_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaa2q16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q16_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaa2q16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaa2q16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q16_Slot_ae7_slot2_encode, Opcode_ae_mulaaaa2q16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp16s_h_Slot_ae_slot2_encode, Opcode_ae_mulp16s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp16s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp16s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap16s_h_Slot_ae_slot2_encode, Opcode_ae_mulap16s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap16s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap16s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp16s_h_Slot_ae_slot2_encode, Opcode_ae_mulsp16s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp16s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp16s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap16s_l_Slot_ae_slot2_encode, Opcode_ae_mulap16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulsp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulc16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulac16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulc16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulac16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2c16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2c16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2c16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula2c16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfc16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafc16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfcj16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafcj16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj16ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfcj16ras_Slot_ae_slot2_encode, Opcode_ae_mulfcj16ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfcj16ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfcj16ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj16ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafcj16ras_Slot_ae_slot2_encode, Opcode_ae_mulafcj16ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafcj16ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafcj16ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc16s_Slot_ae_slot2_encode, Opcode_ae_mulc16s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc16s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulc16s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac16s_Slot_ae_slot2_encode, Opcode_ae_mulac16s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac16s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulac16s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp16x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp16x4rs_Slot_ae_slot2_encode, Opcode_ae_mulfp16x4rs_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp16x4rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp16x4rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd16x16x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd16x16x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd16x16x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulfd16x16x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp16x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp16x16x4s_Slot_ae_slot2_encode, Opcode_ae_mulp16x16x4s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp16x16x4s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp16x16x4s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap16x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap16x16x4s_Slot_ae_slot2_encode, Opcode_ae_mulap16x16x4s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap16x16x4s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap16x16x4s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp16x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp16x16x4s_Slot_ae_slot2_encode, Opcode_ae_mulsp16x16x4s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp16x16x4s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp16x16x4s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaa2d16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaa2d16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzss2d16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzss2d16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaa2d16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaa2d16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss2d16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulss2d16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulss2d16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulss2d16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulss2d16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss2d16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulss2d16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulss2d16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulss2d16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulss2d16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaafd16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaafd16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssfd16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulssfd16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd16x16x4ws_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd16x16x4ws_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd16x16x4ws_Slot_ae7_slot2_encode, Opcode_ae_mulfd16x16x4ws_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaa2q16x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q16x8_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q16x8_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaa2q16x8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaa2q16x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q16x8_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q16x8_Slot_ae7_slot2_encode, Opcode_ae_mulaaaa2q16x8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaa2q8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q8_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q8_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaa2q8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaa2q8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q8_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q8_Slot_ae7_slot2_encode, Opcode_ae_mulaaaa2q8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulc32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulac32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulc32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulac32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulpc32x16x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulpc32x16x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulpc32x16x2_Slot_ae7_slot2_encode, Opcode_ae_mulpc32x16x2_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulapc32x16x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulapc32x16x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulapc32x16x2_Slot_ae7_slot2_encode, Opcode_ae_mulapc32x16x2_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32x16w_h_Slot_ae_slot2_encode, Opcode_ae_mulfc32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32x16w_h_Slot_ae_slot2_encode, Opcode_ae_mulafc32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32x16w_l_Slot_ae_slot2_encode, Opcode_ae_mulfc32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32x16w_l_Slot_ae_slot2_encode, Opcode_ae_mulafc32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfcj32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafcj32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfcj32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafcj32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2p32x16x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulf2p32x16x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf2p32x16x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulaf2p32x16x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf2p32x16x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulsf2p32x16x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2p32x16x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulf2p32x16x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf2p32x16x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulaf2p32x16x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf2p32x16x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulsf2p32x16x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2p32x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4s_Slot_ae7_slot2_encode, Opcode_ae_mulf2p32x16x4s_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf2p32x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4s_Slot_ae7_slot2_encode, Opcode_ae_mulaf2p32x16x4s_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf2p32x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4s_Slot_ae7_slot2_encode, Opcode_ae_mulsf2p32x16x4s_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfpc32x16x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpc32x16x2ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpc32x16x2ras_Slot_ae7_slot2_encode, Opcode_ae_mulfpc32x16x2ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpc32x16x2ras_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafpc32x16x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafpc32x16x2ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafpc32x16x2ras_Slot_ae7_slot2_encode, Opcode_ae_mulafpc32x16x2ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfpcj32x16x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpcj32x16x2ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpcj32x16x2ras_Slot_ae7_slot2_encode, Opcode_ae_mulfpcj32x16x2ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpcj32x16x2ras_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafpcj32x16x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafpcj32x16x2ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafpcj32x16x2ras_Slot_ae7_slot2_encode, Opcode_ae_mulafpcj32x16x2ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaa2q32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q32x16_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaa2q32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaa2q32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q32x16_Slot_ae7_slot2_encode, Opcode_ae_mulaaaa2q32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2q32x16_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2q32x16_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2q32x16_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mul2q32x16_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2q32x16_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula2q32x16_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2q32x16_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mula2q32x16_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2q32x16_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2q32x16_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2q32x16_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mul2q32x16_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2q32x16_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula2q32x16_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2q32x16_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mula2q32x16_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai8_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srai8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai8r_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai8r_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srai8r_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli8_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srli8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai8_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slai8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai8s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slai8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa8_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srla8_encode_fns[] = { + 0, 0, 0, Opcode_ae_srla8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srla8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa8s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa8rs_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa8rs_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa8rs_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa8s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli16_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srli16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai16_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slai16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa16_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srla16_encode_fns[] = { + 0, 0, 0, Opcode_ae_srla16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srla16_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_srla16_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai16sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai16sym_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srai16sym_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa16syms_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa16syms_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa16syms_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai32sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai32sym_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srai32sym_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32syms_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa32syms_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa32syms_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srav16rs_encode_fns[] = { + 0, 0, 0, Opcode_ae_srav16rs_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srav16rs_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srav32rs_encode_fns[] = { + 0, 0, 0, Opcode_ae_srav32rs_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srav32rs_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8s_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8s_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8s_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8s_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8s_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8s_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8u_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8u_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8u_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8u_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8u_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8u_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8us_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8us_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8us_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8us_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8us_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8us_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8u_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8u_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8u_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8u_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8u_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8u_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8us_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8us_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8us_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8us_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8us_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8us_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f16_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f16s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f16_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f16s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f16u_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f16u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f16u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f16us_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f16us_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f16us_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f16u_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f16u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f16u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f16us_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f16us_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f16us_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti16x4x2f8_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti16x4x2f8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti16x4x2f8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvti16x4x2f8_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti16x4x2f8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti16x4x2f8s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti16x4x2f8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvti16x4x2f8s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta16x4x2f8_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta16x4x2f8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta16x4x2f8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvta16x4x2f8_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta16x4x2f8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta16x4x2f8s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta16x4x2f8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvta16x4x2f8s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti16x4x2f8u_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti16x4x2f8u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti16x4x2f8u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvti16x4x2f8u_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti16x4x2f8us_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti16x4x2f8us_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti16x4x2f8us_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta16x4x2f8u_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta16x4x2f8u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta16x4x2f8u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvta16x4x2f8u_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta16x4x2f8us_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta16x4x2f8us_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta16x4x2f8us_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel8x8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sel8x8_Slot_ae_slot2_encode, Opcode_ae_sel8x8_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sel8x8_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_sel8x8_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sel8x8_Slot_ae7_slot2_encode, Opcode_ae_sel8x8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_shfl8x8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_shfl8x8_Slot_ae_slot2_encode, Opcode_ae_shfl8x8_Slot_ae_slot3_encode, 0, 0, Opcode_ae_shfl8x8_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_shfl8x8_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_shfl8x8_Slot_ae7_slot2_encode, Opcode_ae_shfl8x8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sel16x4_Slot_ae_slot2_encode, Opcode_ae_sel16x4_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sel16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_sel16x4_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sel16x4_Slot_ae7_slot2_encode, Opcode_ae_sel16x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, Opcode_ae_sel16x4_Slot_ae9_slot2_encode, Opcode_ae_sel16x4_Slot_ae9_slot3_encode, 0, 0, Opcode_ae_sel16x4_Slot_ae10_slot2_encode, Opcode_ae_sel16x4_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_shfl16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_shfl16x4_Slot_ae_slot2_encode, Opcode_ae_shfl16x4_Slot_ae_slot3_encode, 0, 0, Opcode_ae_shfl16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_shfl16x4_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_shfl16x4_Slot_ae7_slot2_encode, Opcode_ae_shfl16x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dsel8x8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_dsel8x8_Slot_ae_slot2_encode, Opcode_ae_dsel8x8_Slot_ae_slot3_encode, 0, 0, Opcode_ae_dsel8x8_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_dsel8x8_Slot_ae7_slot2_encode, Opcode_ae_dsel8x8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dsel16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_dsel16x4_Slot_ae_slot2_encode, Opcode_ae_dsel16x4_Slot_ae_slot3_encode, 0, 0, Opcode_ae_dsel16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_dsel16x4_Slot_ae7_slot2_encode, Opcode_ae_dsel16x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, Opcode_ae_dsel16x4_Slot_ae9_slot2_encode, Opcode_ae_dsel16x4_Slot_ae9_slot3_encode, 0, 0, Opcode_ae_dsel16x4_Slot_ae10_slot2_encode, Opcode_ae_dsel16x4_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel8x8i_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sel8x8i_Slot_ae_slot2_encode, Opcode_ae_sel8x8i_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sel8x8i_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_sel8x8i_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sel8x8i_Slot_ae7_slot2_encode, Opcode_ae_sel8x8i_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rmax8x8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_rmax8x8_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_rmax8x8_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_rmax8x8_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rmin8x8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_rmin8x8_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_rmin8x8_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_rmin8x8_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rmax16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_rmax16x4_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_rmax16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_rmax16x4_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rmin16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_rmin16x4_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_rmin16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_rmin16x4_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sort16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sort16x4_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_sort16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sort16x4_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radd8x8_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radd8x8_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radd8x8_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radd8x8_h_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radda8x8_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radda8x8_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radda8x8_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radda8x8_h_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radd8x8_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radd8x8_l_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radd8x8_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radd8x8_l_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radda8x8_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radda8x8_l_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radda8x8_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radda8x8_l_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radd16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radd16x4_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radd16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radd16x4_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radda16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radda16x4_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radda16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radda16x4_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmax8x8_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_bmax8x8_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmax8x8_h_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmax8x8_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_bmax8x8_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmax8x8_l_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmax8x8_l_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmin8x8_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_bmin8x8_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmin8x8_h_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmin8x8_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_bmin8x8_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmin8x8_l_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmin8x8_l_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmax16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_bmax16x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_bmax16x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmax16x4_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmax16x4_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmin16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_bmin16x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_bmin16x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmin16x4_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmin16x4_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmax32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_bmax32x2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_bmax32x2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmax32x2_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmax32x2_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmin32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_bmin32x2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_bmin32x2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmin32x2_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmin32x2_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addinv16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addinv16s_Slot_ae_slot0_encode, 0, Opcode_ae_addinv16s_Slot_ae_slot2_encode, Opcode_ae_addinv16s_Slot_ae_slot3_encode, Opcode_ae_addinv16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addinv16s_Slot_ae6_slot0_encode, 0, Opcode_ae_addinv16s_Slot_ae6_slot2_encode, Opcode_ae_addinv16s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addinv32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addinv32s_Slot_ae_slot0_encode, 0, Opcode_ae_addinv32s_Slot_ae_slot2_encode, Opcode_ae_addinv32s_Slot_ae_slot3_encode, Opcode_ae_addinv32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addinv32s_Slot_ae6_slot0_encode, 0, Opcode_ae_addinv32s_Slot_ae6_slot2_encode, Opcode_ae_addinv32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt16x8_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt16x8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt16x8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt8x16_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt8x16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt8x16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt8x16_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt8x16_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt8x16_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movbd1x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movbd1x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movbd1x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movbd1x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movbd1x2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movbd1x2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movneg32s_t_encode_fns[] = { + 0, 0, 0, Opcode_ae_movneg32s_t_Slot_ae_slot0_encode, 0, Opcode_ae_movneg32s_t_Slot_ae_slot2_encode, Opcode_ae_movneg32s_t_Slot_ae_slot3_encode, Opcode_ae_movneg32s_t_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movdext_encode_fns[] = { + 0, 0, 0, Opcode_ae_movdext_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movdext_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movadext_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_movadext_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movadext_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movadext_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_movadext_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movadext_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsa16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsa16x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsa16x4_Slot_ae2_slot0_encode, Opcode_ae_nsa16x4_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsaz32x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsaz32x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsaz32x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsa32x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsa32x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsa32x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunci16x4f32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunci16x4f32s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunci16x4f32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci16x4f32s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci16x4f32s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunci16x4f64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunci16x4f64s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunci16x4f64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci16x4f64s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci16x4f64s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16x4f32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca16x4f32s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunca16x4f32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca16x4f32s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca16x4f32s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16x4f64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca16x4f64s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunca16x4f64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca16x4f64s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca16x4f64s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addc32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addc32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_addc32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addc32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subc32_encode_fns[] = { + 0, 0, 0, Opcode_ae_subc32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_subc32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subc32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addc32u_encode_fns[] = { + 0, 0, 0, Opcode_ae_addc32u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_addc32u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addc32u_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subc32u_encode_fns[] = { + 0, 0, 0, Opcode_ae_subc32u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_subc32u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subc32u_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_expadd16_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_expadd16_h_Slot_ae_slot2_encode, Opcode_ae_expadd16_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_expsub16_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_expsub16_h_Slot_ae_slot2_encode, Opcode_ae_expsub16_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_expadd16_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_expadd16_l_Slot_ae_slot2_encode, Opcode_ae_expadd16_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_expsub16_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_expsub16_l_Slot_ae_slot2_encode, Opcode_ae_expsub16_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcexp32_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_addcexp32_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcexp32_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_addcexp32_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_calcrng16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_calcrng16_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_calcrng32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_calcrng32_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rng32x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_rng32x4_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lav8x8x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_lav8x8x2_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lav8x8x2_xp_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lav8x8x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_lav8x8x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_ae_lav8x8x2_xp_Slot_ae10_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lav16x4x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_lav16x4x2_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lav16x4x2_xp_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lav16x4x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_lav16x4x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_ae_lav16x4x2_xp_Slot_ae10_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sav8x8x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_sav8x8x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sav8x8x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sav8x8x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sav16x4x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_sav16x4x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sav16x4x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sav16x4x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movzbvcdr_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_movzbvcdr_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movzbvcdr_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movdrzbvc_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_movdrzbvc_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movdrzbvc_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lavunsqz8x8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_lavunsqz8x8_xp_Slot_ae_slot0_encode, Opcode_ae_lavunsqz8x8_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_lavunsqz8x8_xp_Slot_ae2_slot0_encode, Opcode_ae_lavunsqz8x8_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lavunsqz8x8_xp_Slot_ae8_slot0_encode, Opcode_ae_lavunsqz8x8_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_lavunsqz8x8_xp_Slot_ae9_slot0_encode, Opcode_ae_lavunsqz8x8_xp_Slot_ae9_slot1_encode, 0, 0, 0, Opcode_ae_lavunsqz8x8_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lavunsqz16x4_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_lavunsqz16x4_xp_Slot_ae_slot0_encode, Opcode_ae_lavunsqz16x4_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_lavunsqz16x4_xp_Slot_ae2_slot0_encode, Opcode_ae_lavunsqz16x4_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lavunsqz16x4_xp_Slot_ae8_slot0_encode, Opcode_ae_lavunsqz16x4_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_lavunsqz16x4_xp_Slot_ae9_slot0_encode, Opcode_ae_lavunsqz16x4_xp_Slot_ae9_slot1_encode, 0, 0, 0, Opcode_ae_lavunsqz16x4_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2x4q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2x4q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2x4q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2x4q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulqq8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulqq8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaqq8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaqq8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2x4q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2x4q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2x4q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2x4q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2x4q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2x4q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2x4q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2x4q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulqq4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulqq4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaqq4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaqq4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulqq4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulqq4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaqq4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaqq4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o4x16cnv_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o4x16cnv_hh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o4x16cnv_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o4x16cnv_hl_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o4x16cnv_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o4x16cnv_lh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o4x16cnv_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o4x16cnv_ll_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o4x16cnv_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o4x16cnv_hh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o4x16cnv_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o4x16cnv_hl_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o4x16cnv_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o4x16cnv_lh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o4x16cnv_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o4x16cnv_ll_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus2x4q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus2x4q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus2x4q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus2x4q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulusqq8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulusqq8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulausqq8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulausqq8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus2x4q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus2x4q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus2x4q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus2x4q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus2x4q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus2x4q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus2x4q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus2x4q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulusqq4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulusqq4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulausqq4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulausqq4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulusqq4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulusqq4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulausqq4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulausqq4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o4x16cnv_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o4x16cnv_hh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o4x16cnv_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o4x16cnv_hl_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o4x16cnv_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o4x16cnv_lh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o4x16cnv_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o4x16cnv_ll_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o4x16cnv_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o4x16cnv_hh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o4x16cnv_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o4x16cnv_hl_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o4x16cnv_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o4x16cnv_lh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o4x16cnv_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o4x16cnv_ll_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb3x3o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb3x3o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb3x3o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb3x3o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzb8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzb8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulazb8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulazb8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzb4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzb4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulazb4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulazb4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzb8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzb8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulazb8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulazb8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzb8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzb8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulazb8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulazb8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzb2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzb2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulazb2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulazb2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzb2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzb2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulazb2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulazb2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzb4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzb4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulazb4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulazb4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzb4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzb4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulazb4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulazb4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzb3x3o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzb3x3o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulazb3x3o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulazb3x3o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtsf16_l_encode_fns[] = { + 0, 0, 0, Opcode_cvtsf16_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_cvtsf16_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtsf16_l_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtsf16_h_encode_fns[] = { + 0, 0, 0, Opcode_cvtsf16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_cvtsf16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtsf16_h_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtf16s_l_encode_fns[] = { + 0, 0, 0, Opcode_cvtf16s_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_cvtf16s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtf16s_l_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtf16s_h_encode_fns[] = { + 0, 0, 0, Opcode_cvtf16s_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_cvtf16s_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtf16s_h_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movfcrfsrv_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_movfcrfsrv_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movvfcrfsr_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_movvfcrfsr_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = { + 0, 0, 0, Opcode_movt_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movt_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_movt_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = { + 0, 0, 0, Opcode_movf_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movf_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_movf_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = { + 0, 0, 0, Opcode_moveqz_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_moveqz_s_Slot_ae2_slot0_encode, Opcode_moveqz_s_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_moveqz_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = { + 0, 0, 0, Opcode_movnez_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movnez_s_Slot_ae2_slot0_encode, Opcode_movnez_s_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_movnez_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = { + 0, 0, 0, Opcode_movgez_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movgez_s_Slot_ae2_slot0_encode, Opcode_movgez_s_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_movgez_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = { + 0, 0, 0, Opcode_movltz_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movltz_s_Slot_ae2_slot0_encode, Opcode_movltz_s_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_movltz_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = { + 0, 0, 0, Opcode_rfr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = { + 0, 0, 0, Opcode_wfr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mul_s_Slot_ae_slot2_encode, Opcode_mul_s_Slot_ae_slot3_encode, 0, 0, Opcode_mul_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_mul_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mul_s_Slot_ae9_slot2_encode, Opcode_mul_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mul_s_Slot_ae10_slot2_encode, Opcode_mul_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_madd_s_Slot_ae_slot2_encode, Opcode_madd_s_Slot_ae_slot3_encode, 0, 0, Opcode_madd_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_madd_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_madd_s_Slot_ae9_slot2_encode, Opcode_madd_s_Slot_ae9_slot3_encode, 0, 0, Opcode_madd_s_Slot_ae10_slot2_encode, Opcode_madd_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_msub_s_Slot_ae_slot2_encode, Opcode_msub_s_Slot_ae_slot3_encode, 0, 0, Opcode_msub_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_msub_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msub_s_Slot_ae9_slot2_encode, Opcode_msub_s_Slot_ae9_slot3_encode, 0, 0, Opcode_msub_s_Slot_ae10_slot2_encode, Opcode_msub_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msubn_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_msubn_s_Slot_ae_slot2_encode, Opcode_msubn_s_Slot_ae_slot3_encode, 0, 0, Opcode_msubn_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_msubn_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msubn_s_Slot_ae9_slot2_encode, Opcode_msubn_s_Slot_ae9_slot3_encode, 0, 0, Opcode_msubn_s_Slot_ae10_slot2_encode, Opcode_msubn_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddn_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maddn_s_Slot_ae_slot2_encode, Opcode_maddn_s_Slot_ae_slot3_encode, 0, 0, Opcode_maddn_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_maddn_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddn_s_Slot_ae9_slot2_encode, Opcode_maddn_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maddn_s_Slot_ae10_slot2_encode, Opcode_maddn_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_add_s_Slot_ae_slot2_encode, Opcode_add_s_Slot_ae_slot3_encode, 0, 0, Opcode_add_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_add_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_s_Slot_ae9_slot2_encode, Opcode_add_s_Slot_ae9_slot3_encode, 0, 0, Opcode_add_s_Slot_ae10_slot2_encode, Opcode_add_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_sub_s_Slot_ae_slot2_encode, Opcode_sub_s_Slot_ae_slot3_encode, 0, 0, Opcode_sub_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_sub_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_s_Slot_ae9_slot2_encode, Opcode_sub_s_Slot_ae9_slot3_encode, 0, 0, Opcode_sub_s_Slot_ae10_slot2_encode, Opcode_sub_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = { + 0, 0, 0, Opcode_ole_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ole_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ole_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ole_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = { + 0, 0, 0, Opcode_olt_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_olt_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_olt_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_olt_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = { + 0, 0, 0, Opcode_oeq_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_oeq_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_oeq_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_oeq_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = { + 0, 0, 0, Opcode_un_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_un_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_un_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_un_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = { + 0, 0, 0, Opcode_ule_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ule_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ule_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ule_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = { + 0, 0, 0, Opcode_ult_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ult_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ult_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ult_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = { + 0, 0, 0, Opcode_ueq_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ueq_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ueq_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ueq_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nexp01_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_nexp01_s_Slot_ae_slot2_encode, Opcode_nexp01_s_Slot_ae_slot3_encode, 0, 0, Opcode_nexp01_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_nexp01_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_nexp01_s_Slot_ae9_slot2_encode, Opcode_nexp01_s_Slot_ae9_slot3_encode, 0, 0, Opcode_nexp01_s_Slot_ae10_slot2_encode, Opcode_nexp01_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mksadj_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mksadj_s_Slot_ae_slot2_encode, Opcode_mksadj_s_Slot_ae_slot3_encode, 0, 0, Opcode_mksadj_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_mksadj_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mksadj_s_Slot_ae9_slot2_encode, Opcode_mksadj_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mksadj_s_Slot_ae10_slot2_encode, Opcode_mksadj_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mkdadj_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mkdadj_s_Slot_ae_slot2_encode, Opcode_mkdadj_s_Slot_ae_slot3_encode, 0, 0, Opcode_mkdadj_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_mkdadj_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mkdadj_s_Slot_ae9_slot2_encode, Opcode_mkdadj_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mkdadj_s_Slot_ae10_slot2_encode, Opcode_mkdadj_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_div0_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_div0_s_Slot_ae_slot2_encode, Opcode_div0_s_Slot_ae_slot3_encode, 0, 0, Opcode_div0_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_div0_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_div0_s_Slot_ae9_slot2_encode, Opcode_div0_s_Slot_ae9_slot3_encode, 0, 0, Opcode_div0_s_Slot_ae10_slot2_encode, Opcode_div0_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sqrt0_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_sqrt0_s_Slot_ae_slot2_encode, Opcode_sqrt0_s_Slot_ae_slot3_encode, 0, 0, Opcode_sqrt0_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_sqrt0_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sqrt0_s_Slot_ae9_slot2_encode, Opcode_sqrt0_s_Slot_ae9_slot3_encode, 0, 0, Opcode_sqrt0_s_Slot_ae10_slot2_encode, Opcode_sqrt0_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_recip0_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_recip0_s_Slot_ae_slot2_encode, Opcode_recip0_s_Slot_ae_slot3_encode, 0, 0, Opcode_recip0_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_recip0_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_recip0_s_Slot_ae9_slot2_encode, Opcode_recip0_s_Slot_ae9_slot3_encode, 0, 0, Opcode_recip0_s_Slot_ae10_slot2_encode, Opcode_recip0_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsqrt0_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_rsqrt0_s_Slot_ae_slot2_encode, Opcode_rsqrt0_s_Slot_ae_slot3_encode, 0, 0, Opcode_rsqrt0_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_rsqrt0_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rsqrt0_s_Slot_ae9_slot2_encode, Opcode_rsqrt0_s_Slot_ae9_slot3_encode, 0, 0, Opcode_rsqrt0_s_Slot_ae10_slot2_encode, Opcode_rsqrt0_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_divn_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_divn_s_Slot_ae_slot2_encode, Opcode_divn_s_Slot_ae_slot3_encode, 0, 0, Opcode_divn_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_divn_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_divn_s_Slot_ae9_slot2_encode, Opcode_divn_s_Slot_ae9_slot3_encode, 0, 0, Opcode_divn_s_Slot_ae10_slot2_encode, Opcode_divn_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexp_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addexp_s_Slot_ae_slot2_encode, Opcode_addexp_s_Slot_ae_slot3_encode, 0, 0, Opcode_addexp_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addexp_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addexp_s_Slot_ae9_slot2_encode, Opcode_addexp_s_Slot_ae9_slot3_encode, 0, 0, Opcode_addexp_s_Slot_ae10_slot2_encode, Opcode_addexp_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexpm_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addexpm_s_Slot_ae_slot2_encode, Opcode_addexpm_s_Slot_ae_slot3_encode, 0, 0, Opcode_addexpm_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addexpm_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addexpm_s_Slot_ae9_slot2_encode, Opcode_addexpm_s_Slot_ae9_slot3_encode, 0, 0, Opcode_addexpm_s_Slot_ae10_slot2_encode, Opcode_addexpm_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_min_s_Slot_ae_slot2_encode, Opcode_min_s_Slot_ae_slot3_encode, 0, 0, Opcode_min_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_min_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_min_s_Slot_ae9_slot2_encode, Opcode_min_s_Slot_ae9_slot3_encode, 0, 0, Opcode_min_s_Slot_ae10_slot2_encode, Opcode_min_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_max_s_Slot_ae_slot2_encode, Opcode_max_s_Slot_ae_slot3_encode, 0, 0, Opcode_max_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_max_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_max_s_Slot_ae9_slot2_encode, Opcode_max_s_Slot_ae9_slot3_encode, 0, 0, Opcode_max_s_Slot_ae10_slot2_encode, Opcode_max_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulmux_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mulmux_s_Slot_ae_slot2_encode, Opcode_mulmux_s_Slot_ae_slot3_encode, 0, 0, Opcode_mulmux_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulmux_s_Slot_ae9_slot2_encode, Opcode_mulmux_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mulmux_s_Slot_ae10_slot2_encode, Opcode_mulmux_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddmux_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maddmux_s_Slot_ae_slot2_encode, Opcode_maddmux_s_Slot_ae_slot3_encode, 0, 0, Opcode_maddmux_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddmux_s_Slot_ae9_slot2_encode, Opcode_maddmux_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maddmux_s_Slot_ae10_slot2_encode, Opcode_maddmux_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = { + 0, 0, 0, Opcode_trunc_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_trunc_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_trunc_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = { + 0, 0, 0, Opcode_utrunc_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_utrunc_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_utrunc_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc_sx2_encode_fns[] = { + 0, 0, 0, Opcode_trunc_sx2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_trunc_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_trunc_sx2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc_sx2_encode_fns[] = { + 0, 0, 0, Opcode_utrunc_sx2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_utrunc_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_utrunc_sx2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ficeil_s_encode_fns[] = { + 0, 0, 0, Opcode_ficeil_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ficeil_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ficeil_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_fifloor_s_encode_fns[] = { + 0, 0, 0, Opcode_fifloor_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_fifloor_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_fifloor_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_firint_s_encode_fns[] = { + 0, 0, 0, Opcode_firint_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_firint_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_firint_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_firound_s_encode_fns[] = { + 0, 0, 0, Opcode_firound_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_firound_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_firound_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_fitrunc_s_encode_fns[] = { + 0, 0, 0, Opcode_fitrunc_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_fitrunc_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_fitrunc_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = { + 0, 0, 0, Opcode_float_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_float_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_float_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = { + 0, 0, 0, Opcode_ufloat_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ufloat_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ufloat_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float_sx2_encode_fns[] = { + 0, 0, 0, Opcode_float_sx2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_float_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_float_sx2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat_sx2_encode_fns[] = { + 0, 0, 0, Opcode_ufloat_sx2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ufloat_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ufloat_sx2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_abs_s_Slot_ae_slot2_encode, Opcode_abs_s_Slot_ae_slot3_encode, 0, Opcode_abs_s_Slot_ae2_slot1_encode, Opcode_abs_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_abs_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_abs_s_Slot_ae9_slot2_encode, Opcode_abs_s_Slot_ae9_slot3_encode, 0, 0, Opcode_abs_s_Slot_ae10_slot2_encode, Opcode_abs_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_neg_s_Slot_ae_slot2_encode, Opcode_neg_s_Slot_ae_slot3_encode, 0, Opcode_neg_s_Slot_ae2_slot1_encode, Opcode_neg_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_neg_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_neg_s_Slot_ae9_slot2_encode, Opcode_neg_s_Slot_ae9_slot3_encode, 0, 0, Opcode_neg_s_Slot_ae10_slot2_encode, Opcode_neg_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_conjc_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_conjc_s_Slot_ae_slot2_encode, Opcode_conjc_s_Slot_ae_slot3_encode, 0, Opcode_conjc_s_Slot_ae2_slot1_encode, Opcode_conjc_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_conjc_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_conjc_s_Slot_ae9_slot2_encode, Opcode_conjc_s_Slot_ae9_slot3_encode, 0, 0, Opcode_conjc_s_Slot_ae10_slot2_encode, Opcode_conjc_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muljc_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_muljc_s_Slot_ae_slot2_encode, Opcode_muljc_s_Slot_ae_slot3_encode, 0, Opcode_muljc_s_Slot_ae2_slot1_encode, Opcode_muljc_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_muljc_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_muljc_s_Slot_ae9_slot2_encode, Opcode_muljc_s_Slot_ae9_slot3_encode, 0, 0, Opcode_muljc_s_Slot_ae10_slot2_encode, Opcode_muljc_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_const_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_const_s_Slot_ae_slot2_encode, Opcode_const_s_Slot_ae_slot3_encode, 0, Opcode_const_s_Slot_ae2_slot1_encode, Opcode_const_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_const_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_const_s_Slot_ae9_slot2_encode, Opcode_const_s_Slot_ae9_slot3_encode, 0, 0, Opcode_const_s_Slot_ae10_slot2_encode, Opcode_const_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clsfy_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_clsfy_s_Slot_ae_slot2_encode, Opcode_clsfy_s_Slot_ae_slot3_encode, 0, 0, Opcode_clsfy_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_clsfy_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_clsfy_s_Slot_ae9_slot2_encode, Opcode_clsfy_s_Slot_ae9_slot3_encode, 0, 0, Opcode_clsfy_s_Slot_ae10_slot2_encode, Opcode_clsfy_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minnum_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_minnum_s_Slot_ae_slot2_encode, Opcode_minnum_s_Slot_ae_slot3_encode, 0, 0, Opcode_minnum_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_minnum_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_minnum_s_Slot_ae9_slot2_encode, Opcode_minnum_s_Slot_ae9_slot3_encode, 0, 0, Opcode_minnum_s_Slot_ae10_slot2_encode, Opcode_minnum_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxnum_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maxnum_s_Slot_ae_slot2_encode, Opcode_maxnum_s_Slot_ae_slot3_encode, 0, 0, Opcode_maxnum_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_maxnum_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maxnum_s_Slot_ae9_slot2_encode, Opcode_maxnum_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maxnum_s_Slot_ae10_slot2_encode, Opcode_maxnum_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addandsub_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addandsub_s_Slot_ae_slot2_encode, Opcode_addandsub_s_Slot_ae_slot3_encode, 0, 0, Opcode_addandsub_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addandsub_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addandsub_s_Slot_ae9_slot2_encode, Opcode_addandsub_s_Slot_ae9_slot3_encode, 0, 0, Opcode_addandsub_s_Slot_ae10_slot2_encode, Opcode_addandsub_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addandsubjc_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addandsubjc_s_Slot_ae_slot2_encode, Opcode_addandsubjc_s_Slot_ae_slot3_encode, 0, 0, Opcode_addandsubjc_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addandsubjc_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addandsubjc_s_Slot_ae9_slot2_encode, Opcode_addandsubjc_s_Slot_ae9_slot3_encode, 0, 0, Opcode_addandsubjc_s_Slot_ae10_slot2_encode, Opcode_addandsubjc_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_hl_lh_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_add_hl_lh_s_Slot_ae_slot2_encode, Opcode_add_hl_lh_s_Slot_ae_slot3_encode, 0, 0, Opcode_add_hl_lh_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_add_hl_lh_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_hl_lh_s_Slot_ae9_slot2_encode, Opcode_add_hl_lh_s_Slot_ae9_slot3_encode, 0, 0, Opcode_add_hl_lh_s_Slot_ae10_slot2_encode, Opcode_add_hl_lh_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madda_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_madda_s_Slot_ae_slot2_encode, Opcode_madda_s_Slot_ae_slot3_encode, 0, 0, Opcode_madda_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_madda_s_Slot_ae9_slot2_encode, Opcode_madda_s_Slot_ae9_slot3_encode, 0, 0, Opcode_madda_s_Slot_ae10_slot2_encode, Opcode_madda_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_frexp_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_frexp_s_Slot_ae_slot2_encode, Opcode_frexp_s_Slot_ae_slot3_encode, 0, 0, Opcode_frexp_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_frexp_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_frexp_s_Slot_ae9_slot2_encode, Opcode_frexp_s_Slot_ae9_slot3_encode, 0, 0, Opcode_frexp_s_Slot_ae10_slot2_encode, Opcode_frexp_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_floatexp_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_floatexp_s_Slot_ae_slot2_encode, Opcode_floatexp_s_Slot_ae_slot3_encode, 0, 0, Opcode_floatexp_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_floatexp_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_floatexp_s_Slot_ae9_slot2_encode, Opcode_floatexp_s_Slot_ae9_slot3_encode, 0, 0, Opcode_floatexp_s_Slot_ae10_slot2_encode, Opcode_floatexp_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minnumabs_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_minnumabs_s_Slot_ae_slot2_encode, Opcode_minnumabs_s_Slot_ae_slot3_encode, 0, 0, Opcode_minnumabs_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_minnumabs_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_minnumabs_s_Slot_ae9_slot2_encode, Opcode_minnumabs_s_Slot_ae9_slot3_encode, 0, 0, Opcode_minnumabs_s_Slot_ae10_slot2_encode, Opcode_minnumabs_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxnumabs_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maxnumabs_s_Slot_ae_slot2_encode, Opcode_maxnumabs_s_Slot_ae_slot3_encode, 0, 0, Opcode_maxnumabs_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_maxnumabs_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maxnumabs_s_Slot_ae9_slot2_encode, Opcode_maxnumabs_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maxnumabs_s_Slot_ae10_slot2_encode, Opcode_maxnumabs_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulq_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulq_s_Slot_ae9_slot2_encode, Opcode_mulq_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mulq_s_Slot_ae10_slot2_encode, Opcode_mulq_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddq_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddq_s_Slot_ae9_slot2_encode, Opcode_maddq_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maddq_s_Slot_ae10_slot2_encode, Opcode_maddq_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msubq_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msubq_s_Slot_ae9_slot2_encode, Opcode_msubq_s_Slot_ae9_slot3_encode, 0, 0, Opcode_msubq_s_Slot_ae10_slot2_encode, Opcode_msubq_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulmuxq_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulmuxq_s_Slot_ae9_slot2_encode, Opcode_mulmuxq_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mulmuxq_s_Slot_ae10_slot2_encode, Opcode_mulmuxq_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddmuxq_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddmuxq_s_Slot_ae9_slot2_encode, Opcode_maddmuxq_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maddmuxq_s_Slot_ae10_slot2_encode, Opcode_maddmuxq_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bmaxnum_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_bmaxnum_s_Slot_ae_slot3_encode, 0, 0, Opcode_bmaxnum_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bmaxnum_s_Slot_ae9_slot3_encode, 0, 0, 0, Opcode_bmaxnum_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bminnum_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_bminnum_s_Slot_ae_slot3_encode, 0, 0, Opcode_bminnum_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bminnum_s_Slot_ae9_slot3_encode, 0, 0, 0, Opcode_bminnum_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bmaxnumabs_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_bmaxnumabs_s_Slot_ae_slot3_encode, 0, 0, Opcode_bmaxnumabs_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bmaxnumabs_s_Slot_ae9_slot3_encode, 0, 0, 0, Opcode_bmaxnumabs_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bminnumabs_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_bminnumabs_s_Slot_ae_slot3_encode, 0, 0, Opcode_bminnumabs_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bminnumabs_s_Slot_ae9_slot3_encode, 0, 0, 0, Opcode_bminnumabs_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_abs_sx2x2_Slot_ae_slot2_encode, Opcode_abs_sx2x2_Slot_ae_slot3_encode, 0, Opcode_abs_sx2x2_Slot_ae2_slot1_encode, Opcode_abs_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_abs_sx2x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_abs_sx2x2_Slot_ae9_slot2_encode, Opcode_abs_sx2x2_Slot_ae9_slot3_encode, 0, 0, Opcode_abs_sx2x2_Slot_ae10_slot2_encode, Opcode_abs_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_neg_sx2x2_Slot_ae_slot2_encode, Opcode_neg_sx2x2_Slot_ae_slot3_encode, 0, Opcode_neg_sx2x2_Slot_ae2_slot1_encode, Opcode_neg_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_neg_sx2x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_neg_sx2x2_Slot_ae9_slot2_encode, Opcode_neg_sx2x2_Slot_ae9_slot3_encode, 0, 0, Opcode_neg_sx2x2_Slot_ae10_slot2_encode, Opcode_neg_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_conjc_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_conjc_sx2x2_Slot_ae_slot2_encode, Opcode_conjc_sx2x2_Slot_ae_slot3_encode, 0, Opcode_conjc_sx2x2_Slot_ae2_slot1_encode, Opcode_conjc_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_conjc_sx2x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_conjc_sx2x2_Slot_ae9_slot2_encode, Opcode_conjc_sx2x2_Slot_ae9_slot3_encode, 0, 0, Opcode_conjc_sx2x2_Slot_ae10_slot2_encode, Opcode_conjc_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muljc_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_muljc_sx2x2_Slot_ae_slot2_encode, Opcode_muljc_sx2x2_Slot_ae_slot3_encode, 0, Opcode_muljc_sx2x2_Slot_ae2_slot1_encode, Opcode_muljc_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_muljc_sx2x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_muljc_sx2x2_Slot_ae9_slot2_encode, Opcode_muljc_sx2x2_Slot_ae9_slot3_encode, 0, 0, Opcode_muljc_sx2x2_Slot_ae10_slot2_encode, Opcode_muljc_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_const_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_const_sx2x2_Slot_ae_slot2_encode, Opcode_const_sx2x2_Slot_ae_slot3_encode, 0, Opcode_const_sx2x2_Slot_ae2_slot1_encode, Opcode_const_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_const_sx2x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_const_sx2x2_Slot_ae9_slot2_encode, Opcode_const_sx2x2_Slot_ae9_slot3_encode, 0, 0, Opcode_const_sx2x2_Slot_ae10_slot2_encode, Opcode_const_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_sx2x2_Slot_ae9_slot2_encode, 0, 0, 0, Opcode_add_sx2x2_Slot_ae10_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_sx2x2_Slot_ae9_slot2_encode, 0, 0, 0, Opcode_sub_sx2x2_Slot_ae10_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mul_sx2x2_Slot_ae10_slot2_encode, Opcode_mul_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madd_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_madd_sx2x2_Slot_ae10_slot2_encode, Opcode_madd_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msub_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msub_sx2x2_Slot_ae10_slot2_encode, Opcode_msub_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulmux_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulmux_sx2x2_Slot_ae10_slot2_encode, Opcode_mulmux_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddmux_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddmux_sx2x2_Slot_ae10_slot2_encode, Opcode_maddmux_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_abs_h_Slot_ae_slot2_encode, Opcode_abs_h_Slot_ae_slot3_encode, 0, Opcode_abs_h_Slot_ae2_slot1_encode, Opcode_abs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_abs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_abs_h_Slot_ae9_slot2_encode, Opcode_abs_h_Slot_ae9_slot3_encode, 0, 0, Opcode_abs_h_Slot_ae10_slot2_encode, Opcode_abs_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexp_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addexp_h_Slot_ae_slot2_encode, Opcode_addexp_h_Slot_ae_slot3_encode, 0, 0, Opcode_addexp_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addexp_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addexp_h_Slot_ae9_slot2_encode, Opcode_addexp_h_Slot_ae9_slot3_encode, 0, 0, Opcode_addexp_h_Slot_ae10_slot2_encode, Opcode_addexp_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexpm_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addexpm_h_Slot_ae_slot2_encode, Opcode_addexpm_h_Slot_ae_slot3_encode, 0, 0, Opcode_addexpm_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addexpm_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addexpm_h_Slot_ae9_slot2_encode, Opcode_addexpm_h_Slot_ae9_slot3_encode, 0, 0, Opcode_addexpm_h_Slot_ae10_slot2_encode, Opcode_addexpm_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clsfy_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_clsfy_h_Slot_ae_slot2_encode, Opcode_clsfy_h_Slot_ae_slot3_encode, 0, 0, Opcode_clsfy_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_clsfy_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_clsfy_h_Slot_ae9_slot2_encode, Opcode_clsfy_h_Slot_ae9_slot3_encode, 0, 0, Opcode_clsfy_h_Slot_ae10_slot2_encode, Opcode_clsfy_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_conjc_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_conjc_h_Slot_ae_slot2_encode, Opcode_conjc_h_Slot_ae_slot3_encode, 0, Opcode_conjc_h_Slot_ae2_slot1_encode, Opcode_conjc_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_conjc_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_conjc_h_Slot_ae9_slot2_encode, Opcode_conjc_h_Slot_ae9_slot3_encode, 0, 0, Opcode_conjc_h_Slot_ae10_slot2_encode, Opcode_conjc_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_const_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_const_h_Slot_ae_slot2_encode, Opcode_const_h_Slot_ae_slot3_encode, 0, Opcode_const_h_Slot_ae2_slot1_encode, Opcode_const_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_const_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_const_h_Slot_ae9_slot2_encode, Opcode_const_h_Slot_ae9_slot3_encode, 0, 0, Opcode_const_h_Slot_ae10_slot2_encode, Opcode_const_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_min_h_Slot_ae_slot2_encode, Opcode_min_h_Slot_ae_slot3_encode, 0, 0, Opcode_min_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_min_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_min_h_Slot_ae9_slot2_encode, Opcode_min_h_Slot_ae9_slot3_encode, 0, 0, Opcode_min_h_Slot_ae10_slot2_encode, Opcode_min_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_max_h_Slot_ae_slot2_encode, Opcode_max_h_Slot_ae_slot3_encode, 0, 0, Opcode_max_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_max_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_max_h_Slot_ae9_slot2_encode, Opcode_max_h_Slot_ae9_slot3_encode, 0, 0, Opcode_max_h_Slot_ae10_slot2_encode, Opcode_max_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minnum_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_minnum_h_Slot_ae_slot2_encode, Opcode_minnum_h_Slot_ae_slot3_encode, 0, 0, Opcode_minnum_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_minnum_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_minnum_h_Slot_ae9_slot2_encode, Opcode_minnum_h_Slot_ae9_slot3_encode, 0, 0, Opcode_minnum_h_Slot_ae10_slot2_encode, Opcode_minnum_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxnum_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maxnum_h_Slot_ae_slot2_encode, Opcode_maxnum_h_Slot_ae_slot3_encode, 0, 0, Opcode_maxnum_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_maxnum_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maxnum_h_Slot_ae9_slot2_encode, Opcode_maxnum_h_Slot_ae9_slot3_encode, 0, 0, Opcode_maxnum_h_Slot_ae10_slot2_encode, Opcode_maxnum_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muljc_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_muljc_h_Slot_ae_slot2_encode, Opcode_muljc_h_Slot_ae_slot3_encode, 0, Opcode_muljc_h_Slot_ae2_slot1_encode, Opcode_muljc_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_muljc_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_muljc_h_Slot_ae9_slot2_encode, Opcode_muljc_h_Slot_ae9_slot3_encode, 0, 0, Opcode_muljc_h_Slot_ae10_slot2_encode, Opcode_muljc_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_neg_h_Slot_ae_slot2_encode, Opcode_neg_h_Slot_ae_slot3_encode, 0, Opcode_neg_h_Slot_ae2_slot1_encode, Opcode_neg_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_neg_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_neg_h_Slot_ae9_slot2_encode, Opcode_neg_h_Slot_ae9_slot3_encode, 0, 0, Opcode_neg_h_Slot_ae10_slot2_encode, Opcode_neg_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_oeq_h_encode_fns[] = { + 0, 0, 0, Opcode_oeq_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ole_h_encode_fns[] = { + 0, 0, 0, Opcode_ole_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_olt_h_encode_fns[] = { + 0, 0, 0, Opcode_olt_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ueq_h_encode_fns[] = { + 0, 0, 0, Opcode_ueq_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ule_h_encode_fns[] = { + 0, 0, 0, Opcode_ule_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ult_h_encode_fns[] = { + 0, 0, 0, Opcode_ult_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_un_h_encode_fns[] = { + 0, 0, 0, Opcode_un_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_div0_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_div0_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ficeil_h_encode_fns[] = { + 0, 0, 0, Opcode_ficeil_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ficeil_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_fifloor_h_encode_fns[] = { + 0, 0, 0, Opcode_fifloor_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_fifloor_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_firint_h_encode_fns[] = { + 0, 0, 0, Opcode_firint_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_firint_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_firound_h_encode_fns[] = { + 0, 0, 0, Opcode_firound_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_firound_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_fitrunc_h_encode_fns[] = { + 0, 0, 0, Opcode_fitrunc_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_fitrunc_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mkdadj_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mkdadj_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mksadj_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mksadj_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nexp0_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_nexp0_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nexp01_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_nexp01_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_recip0_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_recip0_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsqrt0_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_rsqrt0_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sqrt0_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_sqrt0_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float16_h_encode_fns[] = { + 0, 0, 0, Opcode_float16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_float16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat16_h_encode_fns[] = { + 0, 0, 0, Opcode_ufloat16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ufloat16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc16_h_encode_fns[] = { + 0, 0, 0, Opcode_trunc16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_trunc16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc16_h_encode_fns[] = { + 0, 0, 0, Opcode_utrunc16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_utrunc16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float16_hx4_encode_fns[] = { + 0, 0, 0, Opcode_float16_hx4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_float16_hx4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat16_hx4_encode_fns[] = { + 0, 0, 0, Opcode_ufloat16_hx4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ufloat16_hx4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc16_hx4_encode_fns[] = { + 0, 0, 0, Opcode_trunc16_hx4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_trunc16_hx4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc16_hx4_encode_fns[] = { + 0, 0, 0, Opcode_utrunc16_hx4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_utrunc16_hx4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_add_h_Slot_ae_slot2_encode, Opcode_add_h_Slot_ae_slot3_encode, 0, 0, Opcode_add_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_add_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_h_Slot_ae9_slot2_encode, Opcode_add_h_Slot_ae9_slot3_encode, 0, 0, Opcode_add_h_Slot_ae10_slot2_encode, Opcode_add_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_sub_h_Slot_ae_slot2_encode, Opcode_sub_h_Slot_ae_slot3_encode, 0, 0, Opcode_sub_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_sub_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_h_Slot_ae9_slot2_encode, Opcode_sub_h_Slot_ae9_slot3_encode, 0, 0, Opcode_sub_h_Slot_ae10_slot2_encode, Opcode_sub_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mul_h_Slot_ae_slot2_encode, Opcode_mul_h_Slot_ae_slot3_encode, 0, 0, Opcode_mul_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_mul_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mul_h_Slot_ae9_slot2_encode, Opcode_mul_h_Slot_ae9_slot3_encode, 0, 0, Opcode_mul_h_Slot_ae10_slot2_encode, Opcode_mul_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madd_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_madd_h_Slot_ae_slot2_encode, Opcode_madd_h_Slot_ae_slot3_encode, 0, 0, Opcode_madd_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_madd_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_madd_h_Slot_ae9_slot2_encode, Opcode_madd_h_Slot_ae9_slot3_encode, 0, 0, Opcode_madd_h_Slot_ae10_slot2_encode, Opcode_madd_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msub_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_msub_h_Slot_ae_slot2_encode, Opcode_msub_h_Slot_ae_slot3_encode, 0, 0, Opcode_msub_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_msub_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msub_h_Slot_ae9_slot2_encode, Opcode_msub_h_Slot_ae9_slot3_encode, 0, 0, Opcode_msub_h_Slot_ae10_slot2_encode, Opcode_msub_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddn_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maddn_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_maddn_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msubn_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_msubn_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msubn_h_Slot_ae9_slot2_encode, Opcode_msubn_h_Slot_ae9_slot3_encode, 0, 0, Opcode_msubn_h_Slot_ae10_slot2_encode, Opcode_msubn_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_divn_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_divn_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_divn_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rminnum_h_encode_fns[] = { + 0, 0, 0, Opcode_rminnum_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_rminnum_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rminnum_h_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rmaxnum_h_encode_fns[] = { + 0, 0, 0, Opcode_rmaxnum_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_rmaxnum_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rmaxnum_h_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_abs_hx4x2_Slot_ae_slot2_encode, Opcode_abs_hx4x2_Slot_ae_slot3_encode, 0, Opcode_abs_hx4x2_Slot_ae2_slot1_encode, Opcode_abs_hx4x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_abs_hx4x2_Slot_ae9_slot2_encode, Opcode_abs_hx4x2_Slot_ae9_slot3_encode, 0, 0, Opcode_abs_hx4x2_Slot_ae10_slot2_encode, Opcode_abs_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_neg_hx4x2_Slot_ae_slot2_encode, Opcode_neg_hx4x2_Slot_ae_slot3_encode, 0, Opcode_neg_hx4x2_Slot_ae2_slot1_encode, Opcode_neg_hx4x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_neg_hx4x2_Slot_ae9_slot2_encode, Opcode_neg_hx4x2_Slot_ae9_slot3_encode, 0, 0, Opcode_neg_hx4x2_Slot_ae10_slot2_encode, Opcode_neg_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_conjc_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_conjc_hx4x2_Slot_ae_slot2_encode, Opcode_conjc_hx4x2_Slot_ae_slot3_encode, 0, Opcode_conjc_hx4x2_Slot_ae2_slot1_encode, Opcode_conjc_hx4x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_conjc_hx4x2_Slot_ae9_slot2_encode, Opcode_conjc_hx4x2_Slot_ae9_slot3_encode, 0, 0, Opcode_conjc_hx4x2_Slot_ae10_slot2_encode, Opcode_conjc_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_const_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_const_hx4x2_Slot_ae_slot2_encode, Opcode_const_hx4x2_Slot_ae_slot3_encode, 0, Opcode_const_hx4x2_Slot_ae2_slot1_encode, Opcode_const_hx4x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_const_hx4x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_const_hx4x2_Slot_ae9_slot2_encode, Opcode_const_hx4x2_Slot_ae9_slot3_encode, 0, 0, Opcode_const_hx4x2_Slot_ae10_slot2_encode, Opcode_const_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muljc_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_muljc_hx4x2_Slot_ae_slot2_encode, Opcode_muljc_hx4x2_Slot_ae_slot3_encode, 0, Opcode_muljc_hx4x2_Slot_ae2_slot1_encode, Opcode_muljc_hx4x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_muljc_hx4x2_Slot_ae9_slot2_encode, Opcode_muljc_hx4x2_Slot_ae9_slot3_encode, 0, 0, Opcode_muljc_hx4x2_Slot_ae10_slot2_encode, Opcode_muljc_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_hx4x2_Slot_ae10_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_hx4x2_Slot_ae10_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mul_hx4x2_Slot_ae10_slot2_encode, Opcode_mul_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madd_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_madd_hx4x2_Slot_ae10_slot2_encode, Opcode_madd_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msub_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msub_hx4x2_Slot_ae10_slot2_encode, Opcode_msub_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulq_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulq_h_Slot_ae9_slot2_encode, 0, 0, 0, Opcode_mulq_h_Slot_ae10_slot2_encode, Opcode_mulq_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddq_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddq_h_Slot_ae10_slot2_encode, Opcode_maddq_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulcnvh_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulcnvh_hx4x2_Slot_ae10_slot2_encode, Opcode_mulcnvh_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulacnvh_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulacnvh_hx4x2_Slot_ae10_slot2_encode, Opcode_mulacnvh_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulcnvl_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulcnvl_hx4x2_Slot_ae10_slot2_encode, Opcode_mulcnvl_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulacnvl_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulacnvl_hx4x2_Slot_ae10_slot2_encode, Opcode_mulacnvl_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +int num_bypass_groups() { + return 0; +} + +int num_bypass_group_chunks() { + return 0; +} + +uint32 *bypass_entry(int i) { + return 0; +} + + +/* Opcode table. */ + +static xtensa_funcUnit_use Opcode_l32e_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32e_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32i_n_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32i_n_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l16ui_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l16si_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32r_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l8ui_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32ex_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32ex_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s16i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32nb_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s8i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_lddr32_p_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sddr32_p_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_lict_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_licw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sict_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sicw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sdct_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ldct_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sdcw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ldcw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32ai_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32ri_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4f_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4f_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4f_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4f_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4s_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4s_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4s_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4u_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4u_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4u_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4u_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x4u_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x4u_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x4u_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x4u_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ri_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4rng_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4rng_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4rng_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4rng_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2rng_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2rng_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2rng_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2rng_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x4ux2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x4ux2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x4ux2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x4ux2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2rng_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2rng_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2rng_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2rng_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lalign64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_salign64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la64_pp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa64pos_fp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa64neg_fp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24x2ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4ra32s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 } +}; + +static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbs_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbsi_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbki_dbi_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbki_dbi_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbki_dbi_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbi_dbi_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbi_dbi_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbi_dbi_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbk_db_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbk_db_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbk_db_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lb_db_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lb_db_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lb_db_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16si_n_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16ui_n_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16i_n_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lalign128_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_salign128_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la128_pp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa128pos_fp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x4s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x4u_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lav8x8x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lav16x4x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sav8x8x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sav16x4x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lavunsqz8x8_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lavunsqz16x4_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_opcode_internal opcodes[] = { + { "excw", ICLASS_xt_iclass_excw, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", ICLASS_xt_iclass_rfe, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", ICLASS_xt_iclass_rfde, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", ICLASS_xt_iclass_syscall, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "call12", ICLASS_xt_iclass_call12, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", ICLASS_xt_iclass_call8, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", ICLASS_xt_iclass_call4, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", ICLASS_xt_iclass_callx12, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", ICLASS_xt_iclass_callx8, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", ICLASS_xt_iclass_callx4, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", ICLASS_xt_iclass_entry, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", ICLASS_xt_iclass_movsp, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", ICLASS_xt_iclass_rotw, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", ICLASS_xt_iclass_l32e, + 0, + Opcode_l32e_encode_fns, 1, Opcode_l32e_funcUnit_uses }, + { "s32e", ICLASS_xt_iclass_s32e, + 0, + Opcode_s32e_encode_fns, 1, Opcode_s32e_funcUnit_uses }, + { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", ICLASS_xt_iclass_add_n, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", ICLASS_xt_iclass_addi_n, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", ICLASS_xt_iclass_ill_n, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", ICLASS_xt_iclass_loadi4, + 0, + Opcode_l32i_n_encode_fns, 1, Opcode_l32i_n_funcUnit_uses }, + { "mov.n", ICLASS_xt_iclass_mov_n, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", ICLASS_xt_iclass_movi_n, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", ICLASS_xt_iclass_nopn, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", ICLASS_xt_iclass_retn, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", ICLASS_xt_iclass_storei4, + 0, + Opcode_s32i_n_encode_fns, 1, Opcode_s32i_n_funcUnit_uses }, + { "rur.threadptr", ICLASS_rur_threadptr, + 0, + Opcode_rur_threadptr_encode_fns, 0, 0 }, + { "wur.threadptr", ICLASS_wur_threadptr, + 0, + Opcode_wur_threadptr_encode_fns, 0, 0 }, + { "addi", ICLASS_xt_iclass_addi, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", ICLASS_xt_iclass_addmi, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", ICLASS_xt_iclass_addsub, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "addx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "sub", ICLASS_xt_iclass_addsub, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "subx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", ICLASS_xt_iclass_bit, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", ICLASS_xt_iclass_bit, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", ICLASS_xt_iclass_bit, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bgei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bnei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bbci", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "ball", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bany", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bbc", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beq", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bge", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "bgeu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "blt", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bltu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bnall", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bne", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bnone", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "beqz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bgez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "bnez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "call0", ICLASS_xt_iclass_call0, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", ICLASS_xt_iclass_callx0, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "extui", ICLASS_xt_iclass_exti, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", ICLASS_xt_iclass_ill, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", ICLASS_xt_iclass_jump, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", ICLASS_xt_iclass_jumpx, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", ICLASS_xt_iclass_l16ui, + 0, + Opcode_l16ui_encode_fns, 1, Opcode_l16ui_funcUnit_uses }, + { "l16si", ICLASS_xt_iclass_l16si, + 0, + Opcode_l16si_encode_fns, 1, Opcode_l16si_funcUnit_uses }, + { "l32i", ICLASS_xt_iclass_l32i, + 0, + Opcode_l32i_encode_fns, 1, Opcode_l32i_funcUnit_uses }, + { "l32r", ICLASS_xt_iclass_l32r, + 0, + Opcode_l32r_encode_fns, 1, Opcode_l32r_funcUnit_uses }, + { "l8ui", ICLASS_xt_iclass_l8i, + 0, + Opcode_l8ui_encode_fns, 1, Opcode_l8ui_funcUnit_uses }, + { "loop", ICLASS_xt_iclass_loop, + XTENSA_OPCODE_IS_LOOP, + Opcode_loop_encode_fns, 0, 0 }, + { "loopgtz", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopgtz_encode_fns, 0, 0 }, + { "loopnez", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopnez_encode_fns, 0, 0 }, + { "movi", ICLASS_xt_iclass_movi, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", ICLASS_xt_iclass_movz, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movgez", ICLASS_xt_iclass_movz, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "movltz", ICLASS_xt_iclass_movz, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movnez", ICLASS_xt_iclass_movz, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "abs", ICLASS_xt_iclass_neg, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "neg", ICLASS_xt_iclass_neg, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "nop", ICLASS_xt_iclass_nop, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "l32ex", ICLASS_xt_iclass_l32ex, + 0, + Opcode_l32ex_encode_fns, 1, Opcode_l32ex_funcUnit_uses }, + { "s32ex", ICLASS_xt_iclass_s32ex, + 0, + Opcode_s32ex_encode_fns, 1, Opcode_s32ex_funcUnit_uses }, + { "getex", ICLASS_xt_iclass_getex, + 0, + Opcode_getex_encode_fns, 0, 0 }, + { "clrex", ICLASS_xt_iclass_clrex, + 0, + Opcode_clrex_encode_fns, 0, 0 }, + { "ret", ICLASS_xt_iclass_return, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "simcall", ICLASS_xt_iclass_simcall, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "s16i", ICLASS_xt_iclass_s16i, + 0, + Opcode_s16i_encode_fns, 1, Opcode_s16i_funcUnit_uses }, + { "s32i", ICLASS_xt_iclass_s32i, + 0, + Opcode_s32i_encode_fns, 1, Opcode_s32i_funcUnit_uses }, + { "s32nb", ICLASS_xt_iclass_s32nb, + 0, + Opcode_s32nb_encode_fns, 1, Opcode_s32nb_funcUnit_uses }, + { "s8i", ICLASS_xt_iclass_s8i, + 0, + Opcode_s8i_encode_fns, 1, Opcode_s8i_funcUnit_uses }, + { "ssa8b", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssa8l", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssl", ICLASS_xt_iclass_sar, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssr", ICLASS_xt_iclass_sar, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssai", ICLASS_xt_iclass_sari, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", ICLASS_xt_iclass_shifts, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", ICLASS_xt_iclass_shiftst, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "sra", ICLASS_xt_iclass_shiftt, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "srl", ICLASS_xt_iclass_shiftt, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "slli", ICLASS_xt_iclass_slli, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", ICLASS_xt_iclass_srai, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", ICLASS_xt_iclass_srli, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", ICLASS_xt_iclass_memw, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", ICLASS_xt_iclass_extw, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", ICLASS_xt_iclass_isync, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "dsync", ICLASS_xt_iclass_sync, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "esync", ICLASS_xt_iclass_sync, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "rsync", ICLASS_xt_iclass_sync, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "rsil", ICLASS_xt_iclass_rsil, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.lend", ICLASS_xt_iclass_rsr_lend, + 0, + Opcode_rsr_lend_encode_fns, 0, 0 }, + { "wsr.lend", ICLASS_xt_iclass_wsr_lend, + 0, + Opcode_wsr_lend_encode_fns, 0, 0 }, + { "xsr.lend", ICLASS_xt_iclass_xsr_lend, + 0, + Opcode_xsr_lend_encode_fns, 0, 0 }, + { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, + 0, + Opcode_rsr_lcount_encode_fns, 0, 0 }, + { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, + 0, + Opcode_wsr_lcount_encode_fns, 0, 0 }, + { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, + 0, + Opcode_xsr_lcount_encode_fns, 0, 0 }, + { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, + 0, + Opcode_rsr_lbeg_encode_fns, 0, 0 }, + { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, + 0, + Opcode_wsr_lbeg_encode_fns, 0, 0 }, + { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, + 0, + Opcode_xsr_lbeg_encode_fns, 0, 0 }, + { "rsr.sar", ICLASS_xt_iclass_rsr_sar, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", ICLASS_xt_iclass_wsr_sar, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", ICLASS_xt_iclass_xsr_sar, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl, + 0, + Opcode_rsr_memctl_encode_fns, 0, 0 }, + { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl, + 0, + Opcode_wsr_memctl_encode_fns, 0, 0 }, + { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl, + 0, + Opcode_xsr_memctl_encode_fns, 0, 0 }, + { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, + 0, + Opcode_rsr_configid0_encode_fns, 0, 0 }, + { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, + 0, + Opcode_wsr_configid0_encode_fns, 0, 0 }, + { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, + 0, + Opcode_rsr_configid1_encode_fns, 0, 0 }, + { "rsr.ps", ICLASS_xt_iclass_rsr_ps, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", ICLASS_xt_iclass_wsr_ps, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", ICLASS_xt_iclass_xsr_ps, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, + 0, + Opcode_rsr_epc3_encode_fns, 0, 0 }, + { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, + 0, + Opcode_wsr_epc3_encode_fns, 0, 0 }, + { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, + 0, + Opcode_xsr_epc3_encode_fns, 0, 0 }, + { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, + 0, + Opcode_rsr_excsave3_encode_fns, 0, 0 }, + { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, + 0, + Opcode_wsr_excsave3_encode_fns, 0, 0 }, + { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, + 0, + Opcode_xsr_excsave3_encode_fns, 0, 0 }, + { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, + 0, + Opcode_rsr_epc4_encode_fns, 0, 0 }, + { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, + 0, + Opcode_wsr_epc4_encode_fns, 0, 0 }, + { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, + 0, + Opcode_xsr_epc4_encode_fns, 0, 0 }, + { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, + 0, + Opcode_rsr_excsave4_encode_fns, 0, 0 }, + { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, + 0, + Opcode_wsr_excsave4_encode_fns, 0, 0 }, + { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, + 0, + Opcode_xsr_excsave4_encode_fns, 0, 0 }, + { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, + 0, + Opcode_rsr_epc5_encode_fns, 0, 0 }, + { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, + 0, + Opcode_wsr_epc5_encode_fns, 0, 0 }, + { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, + 0, + Opcode_xsr_epc5_encode_fns, 0, 0 }, + { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, + 0, + Opcode_rsr_excsave5_encode_fns, 0, 0 }, + { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, + 0, + Opcode_wsr_excsave5_encode_fns, 0, 0 }, + { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, + 0, + Opcode_xsr_excsave5_encode_fns, 0, 0 }, + { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, + 0, + Opcode_rsr_epc6_encode_fns, 0, 0 }, + { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, + 0, + Opcode_wsr_epc6_encode_fns, 0, 0 }, + { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, + 0, + Opcode_xsr_epc6_encode_fns, 0, 0 }, + { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, + 0, + Opcode_rsr_excsave6_encode_fns, 0, 0 }, + { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, + 0, + Opcode_wsr_excsave6_encode_fns, 0, 0 }, + { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, + 0, + Opcode_xsr_excsave6_encode_fns, 0, 0 }, + { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, + 0, + Opcode_rsr_eps3_encode_fns, 0, 0 }, + { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, + 0, + Opcode_wsr_eps3_encode_fns, 0, 0 }, + { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, + 0, + Opcode_xsr_eps3_encode_fns, 0, 0 }, + { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, + 0, + Opcode_rsr_eps4_encode_fns, 0, 0 }, + { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, + 0, + Opcode_wsr_eps4_encode_fns, 0, 0 }, + { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, + 0, + Opcode_xsr_eps4_encode_fns, 0, 0 }, + { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, + 0, + Opcode_rsr_eps5_encode_fns, 0, 0 }, + { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, + 0, + Opcode_wsr_eps5_encode_fns, 0, 0 }, + { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, + 0, + Opcode_xsr_eps5_encode_fns, 0, 0 }, + { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, + 0, + Opcode_rsr_eps6_encode_fns, 0, 0 }, + { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, + 0, + Opcode_wsr_eps6_encode_fns, 0, 0 }, + { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, + 0, + Opcode_xsr_eps6_encode_fns, 0, 0 }, + { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", ICLASS_xt_iclass_rsr_depc, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", ICLASS_xt_iclass_wsr_depc, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", ICLASS_xt_iclass_xsr_depc, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, + 0, + Opcode_rsr_misc0_encode_fns, 0, 0 }, + { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, + 0, + Opcode_wsr_misc0_encode_fns, 0, 0 }, + { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, + 0, + Opcode_xsr_misc0_encode_fns, 0, 0 }, + { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, + 0, + Opcode_rsr_misc1_encode_fns, 0, 0 }, + { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, + 0, + Opcode_wsr_misc1_encode_fns, 0, 0 }, + { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, + 0, + Opcode_xsr_misc1_encode_fns, 0, 0 }, + { "rsr.misc2", ICLASS_xt_iclass_rsr_misc2, + 0, + Opcode_rsr_misc2_encode_fns, 0, 0 }, + { "wsr.misc2", ICLASS_xt_iclass_wsr_misc2, + 0, + Opcode_wsr_misc2_encode_fns, 0, 0 }, + { "xsr.misc2", ICLASS_xt_iclass_xsr_misc2, + 0, + Opcode_xsr_misc2_encode_fns, 0, 0 }, + { "rsr.misc3", ICLASS_xt_iclass_rsr_misc3, + 0, + Opcode_rsr_misc3_encode_fns, 0, 0 }, + { "wsr.misc3", ICLASS_xt_iclass_wsr_misc3, + 0, + Opcode_wsr_misc3_encode_fns, 0, 0 }, + { "xsr.misc3", ICLASS_xt_iclass_xsr_misc3, + 0, + Opcode_xsr_misc3_encode_fns, 0, 0 }, + { "rsr.prid", ICLASS_xt_iclass_rsr_prid, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, + 0, + Opcode_rsr_vecbase_encode_fns, 0, 0 }, + { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, + 0, + Opcode_wsr_vecbase_encode_fns, 0, 0 }, + { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, + 0, + Opcode_xsr_vecbase_encode_fns, 0, 0 }, + { "rsr.mpucfg", ICLASS_xt_iclass_rsr_mpucfg, + 0, + Opcode_rsr_mpucfg_encode_fns, 0, 0 }, + { "wsr.mpucfg", ICLASS_xt_iclass_wsr_mpucfg, + 0, + Opcode_wsr_mpucfg_encode_fns, 0, 0 }, + { "salt", ICLASS_xt_iclass_salt, + 0, + Opcode_salt_encode_fns, 0, 0 }, + { "saltu", ICLASS_xt_iclass_salt, + 0, + Opcode_saltu_encode_fns, 0, 0 }, + { "rsr.opmode", ICLASS_xt_iclass_rsr_opmode, + 0, + Opcode_rsr_opmode_encode_fns, 0, 0 }, + { "wsr.opmode", ICLASS_xt_iclass_wsr_opmode, + 0, + Opcode_wsr_opmode_encode_fns, 0, 0 }, + { "xsr.opmode", ICLASS_xt_iclass_xsr_opmode, + 0, + Opcode_xsr_opmode_encode_fns, 0, 0 }, + { "mul16s", ICLASS_xt_mul16, + 0, + Opcode_mul16s_encode_fns, 0, 0 }, + { "mul16u", ICLASS_xt_mul16, + 0, + Opcode_mul16u_encode_fns, 0, 0 }, + { "mull", ICLASS_xt_mul32, + 0, + Opcode_mull_encode_fns, 0, 0 }, + { "rfi", ICLASS_xt_iclass_rfi, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", ICLASS_xt_iclass_wait, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", ICLASS_xt_iclass_wsr_intset, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", ICLASS_xt_iclass_break, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", ICLASS_xt_iclass_break_n, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, + 0, + Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, + { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, + 0, + Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, + { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, + 0, + Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, + { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, + 0, + Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, + { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, + 0, + Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, + { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, + 0, + Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, + { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, + 0, + Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, + { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, + 0, + Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, + { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, + 0, + Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, + { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, + 0, + Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, + { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, + 0, + Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, + { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, + 0, + Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, + { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, + 0, + Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, + { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, + 0, + Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, + { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, + 0, + Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, + { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, + 0, + Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, + { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, + 0, + Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, + { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, + 0, + Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, + { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, + 0, + Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, + { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, + 0, + Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, + { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, + 0, + Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, + { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", ICLASS_xt_iclass_rsr_icount, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", ICLASS_xt_iclass_wsr_icount, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", ICLASS_xt_iclass_xsr_icount, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "lddr32.p", ICLASS_xt_iclass_lddr32_p, + 0, + Opcode_lddr32_p_encode_fns, 1, Opcode_lddr32_p_funcUnit_uses }, + { "sddr32.p", ICLASS_xt_iclass_sddr32_p, + 0, + Opcode_sddr32_p_encode_fns, 1, Opcode_sddr32_p_funcUnit_uses }, + { "rfdo", ICLASS_xt_iclass_rfdo, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", ICLASS_xt_iclass_rfdd, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, + 0, + Opcode_wsr_mmid_encode_fns, 0, 0 }, + { "andb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andb_encode_fns, 0, 0 }, + { "andbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andbc_encode_fns, 0, 0 }, + { "orb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orb_encode_fns, 0, 0 }, + { "orbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orbc_encode_fns, 0, 0 }, + { "xorb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_xorb_encode_fns, 0, 0 }, + { "all4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_all4_encode_fns, 0, 0 }, + { "any4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_any4_encode_fns, 0, 0 }, + { "all8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_all8_encode_fns, 0, 0 }, + { "any8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_any8_encode_fns, 0, 0 }, + { "bf", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bf_encode_fns, 0, 0 }, + { "bt", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bt_encode_fns, 0, 0 }, + { "movf", ICLASS_xt_iclass_bmove, + 0, + Opcode_movf_encode_fns, 0, 0 }, + { "movt", ICLASS_xt_iclass_bmove, + 0, + Opcode_movt_encode_fns, 0, 0 }, + { "rsr.br", ICLASS_xt_iclass_RSR_BR, + 0, + Opcode_rsr_br_encode_fns, 0, 0 }, + { "wsr.br", ICLASS_xt_iclass_WSR_BR, + 0, + Opcode_wsr_br_encode_fns, 0, 0 }, + { "xsr.br", ICLASS_xt_iclass_XSR_BR, + 0, + Opcode_xsr_br_encode_fns, 0, 0 }, + { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, + 0, + Opcode_rsr_ccompare1_encode_fns, 0, 0 }, + { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, + 0, + Opcode_wsr_ccompare1_encode_fns, 0, 0 }, + { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, + 0, + Opcode_xsr_ccompare1_encode_fns, 0, 0 }, + { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, + 0, + Opcode_rsr_ccompare2_encode_fns, 0, 0 }, + { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, + 0, + Opcode_wsr_ccompare2_encode_fns, 0, 0 }, + { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, + 0, + Opcode_xsr_ccompare2_encode_fns, 0, 0 }, + { "ihi", ICLASS_xt_iclass_icache, + 0, + Opcode_ihi_encode_fns, 0, 0 }, + { "ipf", ICLASS_xt_iclass_icache, + 0, + Opcode_ipf_encode_fns, 0, 0 }, + { "ihu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ihu_encode_fns, 0, 0 }, + { "iiu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_iiu_encode_fns, 0, 0 }, + { "ipfl", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ipfl_encode_fns, 0, 0 }, + { "iii", ICLASS_xt_iclass_icache_inv, + 0, + Opcode_iii_encode_fns, 0, 0 }, + { "lict", ICLASS_xt_iclass_licx, + 0, + Opcode_lict_encode_fns, 1, Opcode_lict_funcUnit_uses }, + { "licw", ICLASS_xt_iclass_licx, + 0, + Opcode_licw_encode_fns, 1, Opcode_licw_funcUnit_uses }, + { "sict", ICLASS_xt_iclass_sicx, + 0, + Opcode_sict_encode_fns, 1, Opcode_sict_funcUnit_uses }, + { "sicw", ICLASS_xt_iclass_sicx, + 0, + Opcode_sicw_encode_fns, 1, Opcode_sicw_funcUnit_uses }, + { "dhwb", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwb_encode_fns, 0, 0 }, + { "dhwbi", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwbi_encode_fns, 0, 0 }, + { "diwbui.p", ICLASS_xt_iclass_dcache_dyn, + 0, + Opcode_diwbui_p_encode_fns, 0, 0 }, + { "diwb", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwb_encode_fns, 0, 0 }, + { "diwbi", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwbi_encode_fns, 0, 0 }, + { "dhi", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dhi_encode_fns, 0, 0 }, + { "dii", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dii_encode_fns, 0, 0 }, + { "dpfr", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfr_encode_fns, 0, 0 }, + { "dpfro", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfro_encode_fns, 0, 0 }, + { "dpfw", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfw_encode_fns, 0, 0 }, + { "dpfwo", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfwo_encode_fns, 0, 0 }, + { "dhu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dhu_encode_fns, 0, 0 }, + { "diu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_diu_encode_fns, 0, 0 }, + { "dpfl", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dpfl_encode_fns, 0, 0 }, + { "sdct", ICLASS_xt_iclass_sdct, + 0, + Opcode_sdct_encode_fns, 1, Opcode_sdct_funcUnit_uses }, + { "ldct", ICLASS_xt_iclass_ldct, + 0, + Opcode_ldct_encode_fns, 1, Opcode_ldct_funcUnit_uses }, + { "sdcw", ICLASS_xt_iclass_sdcw, + 0, + Opcode_sdcw_encode_fns, 1, Opcode_sdcw_funcUnit_uses }, + { "ldcw", ICLASS_xt_iclass_ldcw, + 0, + Opcode_ldcw_encode_fns, 1, Opcode_ldcw_funcUnit_uses }, + { "rsr.prefctl", ICLASS_xt_iclass_rsr_prefctl, + 0, + Opcode_rsr_prefctl_encode_fns, 0, 0 }, + { "wsr.prefctl", ICLASS_xt_iclass_wsr_prefctl, + 0, + Opcode_wsr_prefctl_encode_fns, 0, 0 }, + { "xsr.prefctl", ICLASS_xt_iclass_xsr_prefctl, + 0, + Opcode_xsr_prefctl_encode_fns, 0, 0 }, + { "wsr.cacheadrdis", ICLASS_xt_iclass_wsr_cacheadrdis, + 0, + Opcode_wsr_cacheadrdis_encode_fns, 0, 0 }, + { "rsr.cacheadrdis", ICLASS_xt_iclass_rsr_cacheadrdis, + 0, + Opcode_rsr_cacheadrdis_encode_fns, 0, 0 }, + { "xsr.cacheadrdis", ICLASS_xt_iclass_xsr_cacheadrdis, + 0, + Opcode_xsr_cacheadrdis_encode_fns, 0, 0 }, + { "rptlb0", ICLASS_xt_iclass_rptlb0, + 0, + Opcode_rptlb0_encode_fns, 0, 0 }, + { "pptlb", ICLASS_xt_iclass_rptlb, + 0, + Opcode_pptlb_encode_fns, 0, 0 }, + { "rptlb1", ICLASS_xt_iclass_rptlb, + 0, + Opcode_rptlb1_encode_fns, 0, 0 }, + { "wptlb", ICLASS_xt_iclass_wptlb, + 0, + Opcode_wptlb_encode_fns, 0, 0 }, + { "rsr.mpuenb", ICLASS_xt_iclass_rsr_mpuenb, + 0, + Opcode_rsr_mpuenb_encode_fns, 0, 0 }, + { "wsr.mpuenb", ICLASS_xt_iclass_wsr_mpuenb, + 0, + Opcode_wsr_mpuenb_encode_fns, 0, 0 }, + { "xsr.mpuenb", ICLASS_xt_iclass_xsr_mpuenb, + 0, + Opcode_xsr_mpuenb_encode_fns, 0, 0 }, + { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, + 0, + Opcode_rsr_cpenable_encode_fns, 0, 0 }, + { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, + 0, + Opcode_wsr_cpenable_encode_fns, 0, 0 }, + { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, + 0, + Opcode_xsr_cpenable_encode_fns, 0, 0 }, + { "clamps", ICLASS_xt_iclass_clamp, + 0, + Opcode_clamps_encode_fns, 0, 0 }, + { "max", ICLASS_xt_iclass_minmax, + 0, + Opcode_max_encode_fns, 0, 0 }, + { "maxu", ICLASS_xt_iclass_minmax, + 0, + Opcode_maxu_encode_fns, 0, 0 }, + { "min", ICLASS_xt_iclass_minmax, + 0, + Opcode_min_encode_fns, 0, 0 }, + { "minu", ICLASS_xt_iclass_minmax, + 0, + Opcode_minu_encode_fns, 0, 0 }, + { "nsa", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsau_encode_fns, 0, 0 }, + { "sext", ICLASS_xt_iclass_sx, + 0, + Opcode_sext_encode_fns, 0, 0 }, + { "l32ai", ICLASS_xt_iclass_l32ai, + 0, + Opcode_l32ai_encode_fns, 1, Opcode_l32ai_funcUnit_uses }, + { "s32ri", ICLASS_xt_iclass_s32ri, + 0, + Opcode_s32ri_encode_fns, 1, Opcode_s32ri_funcUnit_uses }, + { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, + 0, + Opcode_rsr_atomctl_encode_fns, 0, 0 }, + { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, + 0, + Opcode_wsr_atomctl_encode_fns, 0, 0 }, + { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, + 0, + Opcode_xsr_atomctl_encode_fns, 0, 0 }, + { "quos", ICLASS_xt_iclass_div, + 0, + Opcode_quos_encode_fns, 0, 0 }, + { "quou", ICLASS_xt_iclass_div, + 0, + Opcode_quou_encode_fns, 0, 0 }, + { "rems", ICLASS_xt_iclass_div, + 0, + Opcode_rems_encode_fns, 0, 0 }, + { "remu", ICLASS_xt_iclass_div, + 0, + Opcode_remu_encode_fns, 0, 0 }, + { "rsr.eraccess", ICLASS_xt_iclass_rsr_eraccess, + 0, + Opcode_rsr_eraccess_encode_fns, 0, 0 }, + { "wsr.eraccess", ICLASS_xt_iclass_wsr_eraccess, + 0, + Opcode_wsr_eraccess_encode_fns, 0, 0 }, + { "xsr.eraccess", ICLASS_xt_iclass_xsr_eraccess, + 0, + Opcode_xsr_eraccess_encode_fns, 0, 0 }, + { "rer", ICLASS_xt_iclass_rer, + 0, + Opcode_rer_encode_fns, 0, 0 }, + { "wer", ICLASS_xt_iclass_wer, + 0, + Opcode_wer_encode_fns, 0, 0 }, + { "beqz.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_w15_encode_fns, 0, 0 }, + { "bgez.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_w15_encode_fns, 0, 0 }, + { "bltz.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_w15_encode_fns, 0, 0 }, + { "bnez.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_w15_encode_fns, 0, 0 }, + { "beqi.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_w15_encode_fns, 0, 0 }, + { "bgei.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_w15_encode_fns, 0, 0 }, + { "blti.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_w15_encode_fns, 0, 0 }, + { "bnei.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_w15_encode_fns, 0, 0 }, + { "bgeui.w15", ICLASS_xt_iclass_wb15_2, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_w15_encode_fns, 0, 0 }, + { "bltui.w15", ICLASS_xt_iclass_wb15_2, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_w15_encode_fns, 0, 0 }, + { "bbci.w15", ICLASS_xt_iclass_wb15_3, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_w15_encode_fns, 0, 0 }, + { "bbsi.w15", ICLASS_xt_iclass_wb15_3, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_w15_encode_fns, 0, 0 }, + { "ball.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_w15_encode_fns, 0, 0 }, + { "bany.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_w15_encode_fns, 0, 0 }, + { "bbc.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_w15_encode_fns, 0, 0 }, + { "bbs.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_w15_encode_fns, 0, 0 }, + { "beq.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_w15_encode_fns, 0, 0 }, + { "bgeu.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_w15_encode_fns, 0, 0 }, + { "bge.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_w15_encode_fns, 0, 0 }, + { "bltu.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_w15_encode_fns, 0, 0 }, + { "blt.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_w15_encode_fns, 0, 0 }, + { "bnall.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_w15_encode_fns, 0, 0 }, + { "bne.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_w15_encode_fns, 0, 0 }, + { "bnone.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_w15_encode_fns, 0, 0 }, + { "ae_sext16", ICLASS_ic_sext16, + 0, + Opcode_ae_sext16_encode_fns, 0, 0 }, + { "ae_zext16", ICLASS_ic_zext16, + 0, + Opcode_ae_zext16_encode_fns, 0, 0 }, + { "ae_zext8", ICLASS_ic_zext8, + 0, + Opcode_ae_zext8_encode_fns, 0, 0 }, + { "ae_clamps16", ICLASS_ic_clamps16, + 0, + Opcode_ae_clamps16_encode_fns, 0, 0 }, + { "rur.fcr", ICLASS_rur_fcr, + 0, + Opcode_rur_fcr_encode_fns, 0, 0 }, + { "wur.fcr", ICLASS_wur_fcr, + 0, + Opcode_wur_fcr_encode_fns, 0, 0 }, + { "rur.fsr", ICLASS_rur_fsr, + 0, + Opcode_rur_fsr_encode_fns, 0, 0 }, + { "wur.fsr", ICLASS_wur_fsr, + 0, + Opcode_wur_fsr_encode_fns, 0, 0 }, + { "read_impwire", ICLASS_iclass_READ_IMPWIRE, + 0, + Opcode_read_impwire_encode_fns, 0, 0 }, + { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, + 0, + Opcode_setb_expstate_encode_fns, 0, 0 }, + { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, + 0, + Opcode_clrb_expstate_encode_fns, 0, 0 }, + { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, + 0, + Opcode_wrmsk_expstate_encode_fns, 0, 0 }, + { "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar, + 0, + Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 }, + { "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar, + 0, + Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 }, + { "rur.ae_bithead", ICLASS_rur_ae_bithead, + 0, + Opcode_rur_ae_bithead_encode_fns, 0, 0 }, + { "wur.ae_bithead", ICLASS_wur_ae_bithead, + 0, + Opcode_wur_ae_bithead_encode_fns, 0, 0 }, + { "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp, + 0, + Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, + { "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp, + 0, + Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, + { "rur.ae_cw_sd_no", ICLASS_rur_ae_cw_sd_no, + 0, + Opcode_rur_ae_cw_sd_no_encode_fns, 0, 0 }, + { "wur.ae_cw_sd_no", ICLASS_wur_ae_cw_sd_no, + 0, + Opcode_wur_ae_cw_sd_no_encode_fns, 0, 0 }, + { "rur.ae_cbegin0", ICLASS_rur_ae_cbegin0, + 0, + Opcode_rur_ae_cbegin0_encode_fns, 0, 0 }, + { "wur.ae_cbegin0", ICLASS_wur_ae_cbegin0, + 0, + Opcode_wur_ae_cbegin0_encode_fns, 0, 0 }, + { "rur.ae_cend0", ICLASS_rur_ae_cend0, + 0, + Opcode_rur_ae_cend0_encode_fns, 0, 0 }, + { "wur.ae_cend0", ICLASS_wur_ae_cend0, + 0, + Opcode_wur_ae_cend0_encode_fns, 0, 0 }, + { "rur.ae_cbegin1", ICLASS_rur_ae_cbegin1, + 0, + Opcode_rur_ae_cbegin1_encode_fns, 0, 0 }, + { "wur.ae_cbegin1", ICLASS_wur_ae_cbegin1, + 0, + Opcode_wur_ae_cbegin1_encode_fns, 0, 0 }, + { "rur.ae_cend1", ICLASS_rur_ae_cend1, + 0, + Opcode_rur_ae_cend1_encode_fns, 0, 0 }, + { "wur.ae_cend1", ICLASS_wur_ae_cend1, + 0, + Opcode_wur_ae_cend1_encode_fns, 0, 0 }, + { "rur.ae_cbegin2", ICLASS_rur_ae_cbegin2, + 0, + Opcode_rur_ae_cbegin2_encode_fns, 0, 0 }, + { "wur.ae_cbegin2", ICLASS_wur_ae_cbegin2, + 0, + Opcode_wur_ae_cbegin2_encode_fns, 0, 0 }, + { "rur.ae_cend2", ICLASS_rur_ae_cend2, + 0, + Opcode_rur_ae_cend2_encode_fns, 0, 0 }, + { "wur.ae_cend2", ICLASS_wur_ae_cend2, + 0, + Opcode_wur_ae_cend2_encode_fns, 0, 0 }, + { "rur.expstate", ICLASS_rur_expstate, + 0, + Opcode_rur_expstate_encode_fns, 0, 0 }, + { "wur.expstate", ICLASS_wur_expstate, + 0, + Opcode_wur_expstate_encode_fns, 0, 0 }, + { "rur.ae_overflow", ICLASS_RUR_AE_OVERFLOW, + 0, + Opcode_rur_ae_overflow_encode_fns, 0, 0 }, + { "wur.ae_overflow", ICLASS_WUR_AE_OVERFLOW, + 0, + Opcode_wur_ae_overflow_encode_fns, 0, 0 }, + { "rur.ae_sar", ICLASS_RUR_AE_SAR, + 0, + Opcode_rur_ae_sar_encode_fns, 0, 0 }, + { "wur.ae_sar", ICLASS_WUR_AE_SAR, + 0, + Opcode_wur_ae_sar_encode_fns, 0, 0 }, + { "rur.ae_bitptr", ICLASS_RUR_AE_BITPTR, + 0, + Opcode_rur_ae_bitptr_encode_fns, 0, 0 }, + { "wur.ae_bitptr", ICLASS_WUR_AE_BITPTR, + 0, + Opcode_wur_ae_bitptr_encode_fns, 0, 0 }, + { "rur.ae_bitsused", ICLASS_RUR_AE_BITSUSED, + 0, + Opcode_rur_ae_bitsused_encode_fns, 0, 0 }, + { "wur.ae_bitsused", ICLASS_WUR_AE_BITSUSED, + 0, + Opcode_wur_ae_bitsused_encode_fns, 0, 0 }, + { "rur.ae_tablesize", ICLASS_RUR_AE_TABLESIZE, + 0, + Opcode_rur_ae_tablesize_encode_fns, 0, 0 }, + { "wur.ae_tablesize", ICLASS_WUR_AE_TABLESIZE, + 0, + Opcode_wur_ae_tablesize_encode_fns, 0, 0 }, + { "rur.ae_first_ts", ICLASS_RUR_AE_FIRST_TS, + 0, + Opcode_rur_ae_first_ts_encode_fns, 0, 0 }, + { "wur.ae_first_ts", ICLASS_WUR_AE_FIRST_TS, + 0, + Opcode_wur_ae_first_ts_encode_fns, 0, 0 }, + { "rur.ae_nextoffset", ICLASS_RUR_AE_NEXTOFFSET, + 0, + Opcode_rur_ae_nextoffset_encode_fns, 0, 0 }, + { "wur.ae_nextoffset", ICLASS_WUR_AE_NEXTOFFSET, + 0, + Opcode_wur_ae_nextoffset_encode_fns, 0, 0 }, + { "rur.ae_searchdone", ICLASS_RUR_AE_SEARCHDONE, + 0, + Opcode_rur_ae_searchdone_encode_fns, 0, 0 }, + { "wur.ae_searchdone", ICLASS_WUR_AE_SEARCHDONE, + 0, + Opcode_wur_ae_searchdone_encode_fns, 0, 0 }, + { "rur.ae_cwrap", ICLASS_RUR_AE_CWRAP, + 0, + Opcode_rur_ae_cwrap_encode_fns, 0, 0 }, + { "wur.ae_cwrap", ICLASS_WUR_AE_CWRAP, + 0, + Opcode_wur_ae_cwrap_encode_fns, 0, 0 }, + { "ae_l8x4f.i", ICLASS_AE_L8X4F_I, + 0, + Opcode_ae_l8x4f_i_encode_fns, 1, Opcode_ae_l8x4f_i_funcUnit_uses }, + { "ae_l8x4f.ip", ICLASS_AE_L8X4F_IP, + 0, + Opcode_ae_l8x4f_ip_encode_fns, 1, Opcode_ae_l8x4f_ip_funcUnit_uses }, + { "ae_l8x4f.x", ICLASS_AE_L8X4F_X, + 0, + Opcode_ae_l8x4f_x_encode_fns, 1, Opcode_ae_l8x4f_x_funcUnit_uses }, + { "ae_l8x4f.xp", ICLASS_AE_L8X4F_XP, + 0, + Opcode_ae_l8x4f_xp_encode_fns, 1, Opcode_ae_l8x4f_xp_funcUnit_uses }, + { "ae_l8x4s.i", ICLASS_AE_L8X4S_I, + 0, + Opcode_ae_l8x4s_i_encode_fns, 1, Opcode_ae_l8x4s_i_funcUnit_uses }, + { "ae_l8x4s.ip", ICLASS_AE_L8X4S_IP, + 0, + Opcode_ae_l8x4s_ip_encode_fns, 1, Opcode_ae_l8x4s_ip_funcUnit_uses }, + { "ae_l8x4s.x", ICLASS_AE_L8X4S_X, + 0, + Opcode_ae_l8x4s_x_encode_fns, 1, Opcode_ae_l8x4s_x_funcUnit_uses }, + { "ae_l8x4s.xp", ICLASS_AE_L8X4S_XP, + 0, + Opcode_ae_l8x4s_xp_encode_fns, 1, Opcode_ae_l8x4s_xp_funcUnit_uses }, + { "ae_l8x4u.i", ICLASS_AE_L8X4U_I, + 0, + Opcode_ae_l8x4u_i_encode_fns, 1, Opcode_ae_l8x4u_i_funcUnit_uses }, + { "ae_l8x4u.ip", ICLASS_AE_L8X4U_IP, + 0, + Opcode_ae_l8x4u_ip_encode_fns, 1, Opcode_ae_l8x4u_ip_funcUnit_uses }, + { "ae_l8x4u.x", ICLASS_AE_L8X4U_X, + 0, + Opcode_ae_l8x4u_x_encode_fns, 1, Opcode_ae_l8x4u_x_funcUnit_uses }, + { "ae_l8x4u.xp", ICLASS_AE_L8X4U_XP, + 0, + Opcode_ae_l8x4u_xp_encode_fns, 1, Opcode_ae_l8x4u_xp_funcUnit_uses }, + { "ae_s8x4u.i", ICLASS_AE_S8X4U_I, + 0, + Opcode_ae_s8x4u_i_encode_fns, 1, Opcode_ae_s8x4u_i_funcUnit_uses }, + { "ae_s8x4u.ip", ICLASS_AE_S8X4U_IP, + 0, + Opcode_ae_s8x4u_ip_encode_fns, 1, Opcode_ae_s8x4u_ip_funcUnit_uses }, + { "ae_s8x4u.x", ICLASS_AE_S8X4U_X, + 0, + Opcode_ae_s8x4u_x_encode_fns, 1, Opcode_ae_s8x4u_x_funcUnit_uses }, + { "ae_s8x4u.xp", ICLASS_AE_S8X4U_XP, + 0, + Opcode_ae_s8x4u_xp_encode_fns, 1, Opcode_ae_s8x4u_xp_funcUnit_uses }, + { "ae_l16m.xc", ICLASS_AE_L16M_XC, + 0, + Opcode_ae_l16m_xc_encode_fns, 1, Opcode_ae_l16m_xc_funcUnit_uses }, + { "ae_l16m.xc1", ICLASS_AE_L16M_XC1, + 0, + Opcode_ae_l16m_xc1_encode_fns, 1, Opcode_ae_l16m_xc1_funcUnit_uses }, + { "ae_l16m.i", ICLASS_AE_L16M_I, + 0, + Opcode_ae_l16m_i_encode_fns, 1, Opcode_ae_l16m_i_funcUnit_uses }, + { "ae_l16m.iu", ICLASS_AE_L16M_IU, + 0, + Opcode_ae_l16m_iu_encode_fns, 1, Opcode_ae_l16m_iu_funcUnit_uses }, + { "ae_l16m.x", ICLASS_AE_L16M_X, + 0, + Opcode_ae_l16m_x_encode_fns, 1, Opcode_ae_l16m_x_funcUnit_uses }, + { "ae_l16m.xu", ICLASS_AE_L16M_XU, + 0, + Opcode_ae_l16m_xu_encode_fns, 1, Opcode_ae_l16m_xu_funcUnit_uses }, + { "ae_l16.xc", ICLASS_AE_L16_XC, + 0, + Opcode_ae_l16_xc_encode_fns, 1, Opcode_ae_l16_xc_funcUnit_uses }, + { "ae_l16.xc1", ICLASS_AE_L16_XC1, + 0, + Opcode_ae_l16_xc1_encode_fns, 1, Opcode_ae_l16_xc1_funcUnit_uses }, + { "ae_l16.i", ICLASS_AE_L16_I, + 0, + Opcode_ae_l16_i_encode_fns, 1, Opcode_ae_l16_i_funcUnit_uses }, + { "ae_l16.ip", ICLASS_AE_L16_IP, + 0, + Opcode_ae_l16_ip_encode_fns, 1, Opcode_ae_l16_ip_funcUnit_uses }, + { "ae_l16.x", ICLASS_AE_L16_X, + 0, + Opcode_ae_l16_x_encode_fns, 1, Opcode_ae_l16_x_funcUnit_uses }, + { "ae_l16.xp", ICLASS_AE_L16_XP, + 0, + Opcode_ae_l16_xp_encode_fns, 1, Opcode_ae_l16_xp_funcUnit_uses }, + { "ae_l8.xc", ICLASS_AE_L8_XC, + 0, + Opcode_ae_l8_xc_encode_fns, 1, Opcode_ae_l8_xc_funcUnit_uses }, + { "ae_l8.xc1", ICLASS_AE_L8_XC1, + 0, + Opcode_ae_l8_xc1_encode_fns, 1, Opcode_ae_l8_xc1_funcUnit_uses }, + { "ae_l8.i", ICLASS_AE_L8_I, + 0, + Opcode_ae_l8_i_encode_fns, 1, Opcode_ae_l8_i_funcUnit_uses }, + { "ae_l8.ip", ICLASS_AE_L8_IP, + 0, + Opcode_ae_l8_ip_encode_fns, 1, Opcode_ae_l8_ip_funcUnit_uses }, + { "ae_l8.x", ICLASS_AE_L8_X, + 0, + Opcode_ae_l8_x_encode_fns, 1, Opcode_ae_l8_x_funcUnit_uses }, + { "ae_l8.xp", ICLASS_AE_L8_XP, + 0, + Opcode_ae_l8_xp_encode_fns, 1, Opcode_ae_l8_xp_funcUnit_uses }, + { "ae_l32f24.xc", ICLASS_AE_L32F24_XC, + 0, + Opcode_ae_l32f24_xc_encode_fns, 1, Opcode_ae_l32f24_xc_funcUnit_uses }, + { "ae_l32f24.xc1", ICLASS_AE_L32F24_XC1, + 0, + Opcode_ae_l32f24_xc1_encode_fns, 1, Opcode_ae_l32f24_xc1_funcUnit_uses }, + { "ae_l32f24.i", ICLASS_AE_L32F24_I, + 0, + Opcode_ae_l32f24_i_encode_fns, 1, Opcode_ae_l32f24_i_funcUnit_uses }, + { "ae_l32f24.ip", ICLASS_AE_L32F24_IP, + 0, + Opcode_ae_l32f24_ip_encode_fns, 1, Opcode_ae_l32f24_ip_funcUnit_uses }, + { "ae_l32f24.x", ICLASS_AE_L32F24_X, + 0, + Opcode_ae_l32f24_x_encode_fns, 1, Opcode_ae_l32f24_x_funcUnit_uses }, + { "ae_l32f24.xp", ICLASS_AE_L32F24_XP, + 0, + Opcode_ae_l32f24_xp_encode_fns, 1, Opcode_ae_l32f24_xp_funcUnit_uses }, + { "ae_l32.xc", ICLASS_AE_L32_XC, + 0, + Opcode_ae_l32_xc_encode_fns, 1, Opcode_ae_l32_xc_funcUnit_uses }, + { "ae_l32.xc1", ICLASS_AE_L32_XC1, + 0, + Opcode_ae_l32_xc1_encode_fns, 1, Opcode_ae_l32_xc1_funcUnit_uses }, + { "ae_l32.i", ICLASS_AE_L32_I, + 0, + Opcode_ae_l32_i_encode_fns, 1, Opcode_ae_l32_i_funcUnit_uses }, + { "ae_l32.ip", ICLASS_AE_L32_IP, + 0, + Opcode_ae_l32_ip_encode_fns, 1, Opcode_ae_l32_ip_funcUnit_uses }, + { "ae_l32.x", ICLASS_AE_L32_X, + 0, + Opcode_ae_l32_x_encode_fns, 1, Opcode_ae_l32_x_funcUnit_uses }, + { "ae_l32.xp", ICLASS_AE_L32_XP, + 0, + Opcode_ae_l32_xp_encode_fns, 1, Opcode_ae_l32_xp_funcUnit_uses }, + { "ae_l32m.xc", ICLASS_AE_L32M_XC, + 0, + Opcode_ae_l32m_xc_encode_fns, 1, Opcode_ae_l32m_xc_funcUnit_uses }, + { "ae_l32m.i", ICLASS_AE_L32M_I, + 0, + Opcode_ae_l32m_i_encode_fns, 1, Opcode_ae_l32m_i_funcUnit_uses }, + { "ae_l32m.iu", ICLASS_AE_L32M_IU, + 0, + Opcode_ae_l32m_iu_encode_fns, 1, Opcode_ae_l32m_iu_funcUnit_uses }, + { "ae_l32m.x", ICLASS_AE_L32M_X, + 0, + Opcode_ae_l32m_x_encode_fns, 1, Opcode_ae_l32m_x_funcUnit_uses }, + { "ae_l32m.xu", ICLASS_AE_L32M_XU, + 0, + Opcode_ae_l32m_xu_encode_fns, 1, Opcode_ae_l32m_xu_funcUnit_uses }, + { "ae_l16x2m.xc", ICLASS_AE_L16X2M_XC, + 0, + Opcode_ae_l16x2m_xc_encode_fns, 1, Opcode_ae_l16x2m_xc_funcUnit_uses }, + { "ae_l16x2m.xc1", ICLASS_AE_L16X2M_XC1, + 0, + Opcode_ae_l16x2m_xc1_encode_fns, 1, Opcode_ae_l16x2m_xc1_funcUnit_uses }, + { "ae_l16x2m.i", ICLASS_AE_L16X2M_I, + 0, + Opcode_ae_l16x2m_i_encode_fns, 1, Opcode_ae_l16x2m_i_funcUnit_uses }, + { "ae_l16x2m.iu", ICLASS_AE_L16X2M_IU, + 0, + Opcode_ae_l16x2m_iu_encode_fns, 1, Opcode_ae_l16x2m_iu_funcUnit_uses }, + { "ae_l16x2m.x", ICLASS_AE_L16X2M_X, + 0, + Opcode_ae_l16x2m_x_encode_fns, 1, Opcode_ae_l16x2m_x_funcUnit_uses }, + { "ae_l16x2m.xu", ICLASS_AE_L16X2M_XU, + 0, + Opcode_ae_l16x2m_xu_encode_fns, 1, Opcode_ae_l16x2m_xu_funcUnit_uses }, + { "ae_l32x2f24.xc", ICLASS_AE_L32X2F24_XC, + 0, + Opcode_ae_l32x2f24_xc_encode_fns, 1, Opcode_ae_l32x2f24_xc_funcUnit_uses }, + { "ae_l32x2f24.xc1", ICLASS_AE_L32X2F24_XC1, + 0, + Opcode_ae_l32x2f24_xc1_encode_fns, 1, Opcode_ae_l32x2f24_xc1_funcUnit_uses }, + { "ae_l32x2f24.i", ICLASS_AE_L32X2F24_I, + 0, + Opcode_ae_l32x2f24_i_encode_fns, 1, Opcode_ae_l32x2f24_i_funcUnit_uses }, + { "ae_l32x2f24.ip", ICLASS_AE_L32X2F24_IP, + 0, + Opcode_ae_l32x2f24_ip_encode_fns, 1, Opcode_ae_l32x2f24_ip_funcUnit_uses }, + { "ae_l32x2f24.rip", ICLASS_AE_L32X2F24_RIP, + 0, + Opcode_ae_l32x2f24_rip_encode_fns, 1, Opcode_ae_l32x2f24_rip_funcUnit_uses }, + { "ae_l32x2f24.ri", ICLASS_AE_L32X2F24_RI, + 0, + Opcode_ae_l32x2f24_ri_encode_fns, 1, Opcode_ae_l32x2f24_ri_funcUnit_uses }, + { "ae_l32x2f24.ric", ICLASS_AE_L32X2F24_RIC, + 0, + Opcode_ae_l32x2f24_ric_encode_fns, 1, Opcode_ae_l32x2f24_ric_funcUnit_uses }, + { "ae_l32x2f24.ric1", ICLASS_AE_L32X2F24_RIC1, + 0, + Opcode_ae_l32x2f24_ric1_encode_fns, 1, Opcode_ae_l32x2f24_ric1_funcUnit_uses }, + { "ae_l32x2f24.x", ICLASS_AE_L32X2F24_X, + 0, + Opcode_ae_l32x2f24_x_encode_fns, 1, Opcode_ae_l32x2f24_x_funcUnit_uses }, + { "ae_l32x2f24.xp", ICLASS_AE_L32X2F24_XP, + 0, + Opcode_ae_l32x2f24_xp_encode_fns, 1, Opcode_ae_l32x2f24_xp_funcUnit_uses }, + { "ae_l32x2.xc", ICLASS_AE_L32X2_XC, + 0, + Opcode_ae_l32x2_xc_encode_fns, 1, Opcode_ae_l32x2_xc_funcUnit_uses }, + { "ae_l32x2.xc1", ICLASS_AE_L32X2_XC1, + 0, + Opcode_ae_l32x2_xc1_encode_fns, 1, Opcode_ae_l32x2_xc1_funcUnit_uses }, + { "ae_l32x2.i", ICLASS_AE_L32X2_I, + 0, + Opcode_ae_l32x2_i_encode_fns, 1, Opcode_ae_l32x2_i_funcUnit_uses }, + { "ae_l32x2.ip", ICLASS_AE_L32X2_IP, + 0, + Opcode_ae_l32x2_ip_encode_fns, 1, Opcode_ae_l32x2_ip_funcUnit_uses }, + { "ae_l32x2.ric", ICLASS_AE_L32X2_RIC, + 0, + Opcode_ae_l32x2_ric_encode_fns, 1, Opcode_ae_l32x2_ric_funcUnit_uses }, + { "ae_l32x2.ric1", ICLASS_AE_L32X2_RIC1, + 0, + Opcode_ae_l32x2_ric1_encode_fns, 1, Opcode_ae_l32x2_ric1_funcUnit_uses }, + { "ae_l32x2.x", ICLASS_AE_L32X2_X, + 0, + Opcode_ae_l32x2_x_encode_fns, 1, Opcode_ae_l32x2_x_funcUnit_uses }, + { "ae_l32x2.xp", ICLASS_AE_L32X2_XP, + 0, + Opcode_ae_l32x2_xp_encode_fns, 1, Opcode_ae_l32x2_xp_funcUnit_uses }, + { "ae_l16x4.xc", ICLASS_AE_L16X4_XC, + 0, + Opcode_ae_l16x4_xc_encode_fns, 1, Opcode_ae_l16x4_xc_funcUnit_uses }, + { "ae_l16x4.xc1", ICLASS_AE_L16X4_XC1, + 0, + Opcode_ae_l16x4_xc1_encode_fns, 1, Opcode_ae_l16x4_xc1_funcUnit_uses }, + { "ae_l16x4.i", ICLASS_AE_L16X4_I, + 0, + Opcode_ae_l16x4_i_encode_fns, 1, Opcode_ae_l16x4_i_funcUnit_uses }, + { "ae_l16x4.ip", ICLASS_AE_L16X4_IP, + 0, + Opcode_ae_l16x4_ip_encode_fns, 1, Opcode_ae_l16x4_ip_funcUnit_uses }, + { "ae_l16x4.x", ICLASS_AE_L16X4_X, + 0, + Opcode_ae_l16x4_x_encode_fns, 1, Opcode_ae_l16x4_x_funcUnit_uses }, + { "ae_l16x4.xp", ICLASS_AE_L16X4_XP, + 0, + Opcode_ae_l16x4_xp_encode_fns, 1, Opcode_ae_l16x4_xp_funcUnit_uses }, + { "ae_l8x8.xc", ICLASS_AE_L8X8_XC, + 0, + Opcode_ae_l8x8_xc_encode_fns, 1, Opcode_ae_l8x8_xc_funcUnit_uses }, + { "ae_l8x8.xc1", ICLASS_AE_L8X8_XC1, + 0, + Opcode_ae_l8x8_xc1_encode_fns, 1, Opcode_ae_l8x8_xc1_funcUnit_uses }, + { "ae_l8x8.i", ICLASS_AE_L8X8_I, + 0, + Opcode_ae_l8x8_i_encode_fns, 1, Opcode_ae_l8x8_i_funcUnit_uses }, + { "ae_l8x8.ip", ICLASS_AE_L8X8_IP, + 0, + Opcode_ae_l8x8_ip_encode_fns, 1, Opcode_ae_l8x8_ip_funcUnit_uses }, + { "ae_l8x8.x", ICLASS_AE_L8X8_X, + 0, + Opcode_ae_l8x8_x_encode_fns, 1, Opcode_ae_l8x8_x_funcUnit_uses }, + { "ae_l8x8.xp", ICLASS_AE_L8X8_XP, + 0, + Opcode_ae_l8x8_xp_encode_fns, 1, Opcode_ae_l8x8_xp_funcUnit_uses }, + { "ae_l64.xc", ICLASS_AE_L64_XC, + 0, + Opcode_ae_l64_xc_encode_fns, 1, Opcode_ae_l64_xc_funcUnit_uses }, + { "ae_l64.xc1", ICLASS_AE_L64_XC1, + 0, + Opcode_ae_l64_xc1_encode_fns, 1, Opcode_ae_l64_xc1_funcUnit_uses }, + { "ae_l64.i", ICLASS_AE_L64_I, + 0, + Opcode_ae_l64_i_encode_fns, 1, Opcode_ae_l64_i_funcUnit_uses }, + { "ae_l64.ip", ICLASS_AE_L64_IP, + 0, + Opcode_ae_l64_ip_encode_fns, 1, Opcode_ae_l64_ip_funcUnit_uses }, + { "ae_l64.x", ICLASS_AE_L64_X, + 0, + Opcode_ae_l64_x_encode_fns, 1, Opcode_ae_l64_x_funcUnit_uses }, + { "ae_l64.xp", ICLASS_AE_L64_XP, + 0, + Opcode_ae_l64_xp_encode_fns, 1, Opcode_ae_l64_xp_funcUnit_uses }, + { "ae_s16x2m.xc", ICLASS_AE_S16X2M_XC, + 0, + Opcode_ae_s16x2m_xc_encode_fns, 1, Opcode_ae_s16x2m_xc_funcUnit_uses }, + { "ae_s16x2m.xc1", ICLASS_AE_S16X2M_XC1, + 0, + Opcode_ae_s16x2m_xc1_encode_fns, 1, Opcode_ae_s16x2m_xc1_funcUnit_uses }, + { "ae_s16x2m.i", ICLASS_AE_S16X2M_I, + 0, + Opcode_ae_s16x2m_i_encode_fns, 1, Opcode_ae_s16x2m_i_funcUnit_uses }, + { "ae_s16x2m.iu", ICLASS_AE_S16X2M_IU, + 0, + Opcode_ae_s16x2m_iu_encode_fns, 1, Opcode_ae_s16x2m_iu_funcUnit_uses }, + { "ae_s16x2m.x", ICLASS_AE_S16X2M_X, + 0, + Opcode_ae_s16x2m_x_encode_fns, 1, Opcode_ae_s16x2m_x_funcUnit_uses }, + { "ae_s16x2m.xu", ICLASS_AE_S16X2M_XU, + 0, + Opcode_ae_s16x2m_xu_encode_fns, 1, Opcode_ae_s16x2m_xu_funcUnit_uses }, + { "ae_s32x2f24.xc", ICLASS_AE_S32X2F24_XC, + 0, + Opcode_ae_s32x2f24_xc_encode_fns, 1, Opcode_ae_s32x2f24_xc_funcUnit_uses }, + { "ae_s32x2f24.xc1", ICLASS_AE_S32X2F24_XC1, + 0, + Opcode_ae_s32x2f24_xc1_encode_fns, 1, Opcode_ae_s32x2f24_xc1_funcUnit_uses }, + { "ae_s32x2f24.i", ICLASS_AE_S32X2F24_I, + 0, + Opcode_ae_s32x2f24_i_encode_fns, 1, Opcode_ae_s32x2f24_i_funcUnit_uses }, + { "ae_s32x2f24.ip", ICLASS_AE_S32X2F24_IP, + 0, + Opcode_ae_s32x2f24_ip_encode_fns, 1, Opcode_ae_s32x2f24_ip_funcUnit_uses }, + { "ae_s32x2f24.rip", ICLASS_AE_S32X2F24_RIP, + 0, + Opcode_ae_s32x2f24_rip_encode_fns, 1, Opcode_ae_s32x2f24_rip_funcUnit_uses }, + { "ae_s32x2f24.ric", ICLASS_AE_S32X2F24_RIC, + 0, + Opcode_ae_s32x2f24_ric_encode_fns, 1, Opcode_ae_s32x2f24_ric_funcUnit_uses }, + { "ae_s32x2f24.ric1", ICLASS_AE_S32X2F24_RIC1, + 0, + Opcode_ae_s32x2f24_ric1_encode_fns, 1, Opcode_ae_s32x2f24_ric1_funcUnit_uses }, + { "ae_s32x2f24.x", ICLASS_AE_S32X2F24_X, + 0, + Opcode_ae_s32x2f24_x_encode_fns, 1, Opcode_ae_s32x2f24_x_funcUnit_uses }, + { "ae_s32x2f24.xp", ICLASS_AE_S32X2F24_XP, + 0, + Opcode_ae_s32x2f24_xp_encode_fns, 1, Opcode_ae_s32x2f24_xp_funcUnit_uses }, + { "ae_s32x2.xc", ICLASS_AE_S32X2_XC, + 0, + Opcode_ae_s32x2_xc_encode_fns, 1, Opcode_ae_s32x2_xc_funcUnit_uses }, + { "ae_s32x2.xc1", ICLASS_AE_S32X2_XC1, + 0, + Opcode_ae_s32x2_xc1_encode_fns, 1, Opcode_ae_s32x2_xc1_funcUnit_uses }, + { "ae_s32x2.i", ICLASS_AE_S32X2_I, + 0, + Opcode_ae_s32x2_i_encode_fns, 1, Opcode_ae_s32x2_i_funcUnit_uses }, + { "ae_s32x2.ip", ICLASS_AE_S32X2_IP, + 0, + Opcode_ae_s32x2_ip_encode_fns, 1, Opcode_ae_s32x2_ip_funcUnit_uses }, + { "ae_s32x2.ric", ICLASS_AE_S32X2_RIC, + 0, + Opcode_ae_s32x2_ric_encode_fns, 1, Opcode_ae_s32x2_ric_funcUnit_uses }, + { "ae_s32x2.ric1", ICLASS_AE_S32X2_RIC1, + 0, + Opcode_ae_s32x2_ric1_encode_fns, 1, Opcode_ae_s32x2_ric1_funcUnit_uses }, + { "ae_s32x2.x", ICLASS_AE_S32X2_X, + 0, + Opcode_ae_s32x2_x_encode_fns, 1, Opcode_ae_s32x2_x_funcUnit_uses }, + { "ae_s32x2.xp", ICLASS_AE_S32X2_XP, + 0, + Opcode_ae_s32x2_xp_encode_fns, 1, Opcode_ae_s32x2_xp_funcUnit_uses }, + { "ae_s32x2rng.i", ICLASS_AE_S32X2RNG_I, + 0, + Opcode_ae_s32x2rng_i_encode_fns, 1, Opcode_ae_s32x2rng_i_funcUnit_uses }, + { "ae_s32x2rng.ip", ICLASS_AE_S32X2RNG_IP, + 0, + Opcode_ae_s32x2rng_ip_encode_fns, 1, Opcode_ae_s32x2rng_ip_funcUnit_uses }, + { "ae_s32x2rng.x", ICLASS_AE_S32X2RNG_X, + 0, + Opcode_ae_s32x2rng_x_encode_fns, 1, Opcode_ae_s32x2rng_x_funcUnit_uses }, + { "ae_s32x2rng.xp", ICLASS_AE_S32X2RNG_XP, + 0, + Opcode_ae_s32x2rng_xp_encode_fns, 1, Opcode_ae_s32x2rng_xp_funcUnit_uses }, + { "ae_s16x4.xc", ICLASS_AE_S16X4_XC, + 0, + Opcode_ae_s16x4_xc_encode_fns, 1, Opcode_ae_s16x4_xc_funcUnit_uses }, + { "ae_s16x4.xc1", ICLASS_AE_S16X4_XC1, + 0, + Opcode_ae_s16x4_xc1_encode_fns, 1, Opcode_ae_s16x4_xc1_funcUnit_uses }, + { "ae_s16x4.i", ICLASS_AE_S16X4_I, + 0, + Opcode_ae_s16x4_i_encode_fns, 1, Opcode_ae_s16x4_i_funcUnit_uses }, + { "ae_s16x4.ip", ICLASS_AE_S16X4_IP, + 0, + Opcode_ae_s16x4_ip_encode_fns, 1, Opcode_ae_s16x4_ip_funcUnit_uses }, + { "ae_s16x4.x", ICLASS_AE_S16X4_X, + 0, + Opcode_ae_s16x4_x_encode_fns, 1, Opcode_ae_s16x4_x_funcUnit_uses }, + { "ae_s16x4.xp", ICLASS_AE_S16X4_XP, + 0, + Opcode_ae_s16x4_xp_encode_fns, 1, Opcode_ae_s16x4_xp_funcUnit_uses }, + { "ae_s8x8.xc", ICLASS_AE_S8X8_XC, + 0, + Opcode_ae_s8x8_xc_encode_fns, 1, Opcode_ae_s8x8_xc_funcUnit_uses }, + { "ae_s8x8.xc1", ICLASS_AE_S8X8_XC1, + 0, + Opcode_ae_s8x8_xc1_encode_fns, 1, Opcode_ae_s8x8_xc1_funcUnit_uses }, + { "ae_s8x8.i", ICLASS_AE_S8X8_I, + 0, + Opcode_ae_s8x8_i_encode_fns, 1, Opcode_ae_s8x8_i_funcUnit_uses }, + { "ae_s8x8.ip", ICLASS_AE_S8X8_IP, + 0, + Opcode_ae_s8x8_ip_encode_fns, 1, Opcode_ae_s8x8_ip_funcUnit_uses }, + { "ae_s8x8.x", ICLASS_AE_S8X8_X, + 0, + Opcode_ae_s8x8_x_encode_fns, 1, Opcode_ae_s8x8_x_funcUnit_uses }, + { "ae_s8x8.xp", ICLASS_AE_S8X8_XP, + 0, + Opcode_ae_s8x8_xp_encode_fns, 1, Opcode_ae_s8x8_xp_funcUnit_uses }, + { "ae_s16m.l.xc", ICLASS_AE_S16M_L_XC, + 0, + Opcode_ae_s16m_l_xc_encode_fns, 1, Opcode_ae_s16m_l_xc_funcUnit_uses }, + { "ae_s16m.l.xc1", ICLASS_AE_S16M_L_XC1, + 0, + Opcode_ae_s16m_l_xc1_encode_fns, 1, Opcode_ae_s16m_l_xc1_funcUnit_uses }, + { "ae_s16m.l.i", ICLASS_AE_S16M_L_I, + 0, + Opcode_ae_s16m_l_i_encode_fns, 1, Opcode_ae_s16m_l_i_funcUnit_uses }, + { "ae_s16m.l.iu", ICLASS_AE_S16M_L_IU, + 0, + Opcode_ae_s16m_l_iu_encode_fns, 1, Opcode_ae_s16m_l_iu_funcUnit_uses }, + { "ae_s16m.l.x", ICLASS_AE_S16M_L_X, + 0, + Opcode_ae_s16m_l_x_encode_fns, 1, Opcode_ae_s16m_l_x_funcUnit_uses }, + { "ae_s16m.l.xu", ICLASS_AE_S16M_L_XU, + 0, + Opcode_ae_s16m_l_xu_encode_fns, 1, Opcode_ae_s16m_l_xu_funcUnit_uses }, + { "ae_s32f24.l.xc", ICLASS_AE_S32F24_L_XC, + 0, + Opcode_ae_s32f24_l_xc_encode_fns, 1, Opcode_ae_s32f24_l_xc_funcUnit_uses }, + { "ae_s32f24.l.xc1", ICLASS_AE_S32F24_L_XC1, + 0, + Opcode_ae_s32f24_l_xc1_encode_fns, 1, Opcode_ae_s32f24_l_xc1_funcUnit_uses }, + { "ae_s32f24.l.i", ICLASS_AE_S32F24_L_I, + 0, + Opcode_ae_s32f24_l_i_encode_fns, 1, Opcode_ae_s32f24_l_i_funcUnit_uses }, + { "ae_s32f24.l.ip", ICLASS_AE_S32F24_L_IP, + 0, + Opcode_ae_s32f24_l_ip_encode_fns, 1, Opcode_ae_s32f24_l_ip_funcUnit_uses }, + { "ae_s32f24.l.x", ICLASS_AE_S32F24_L_X, + 0, + Opcode_ae_s32f24_l_x_encode_fns, 1, Opcode_ae_s32f24_l_x_funcUnit_uses }, + { "ae_s32f24.l.xp", ICLASS_AE_S32F24_L_XP, + 0, + Opcode_ae_s32f24_l_xp_encode_fns, 1, Opcode_ae_s32f24_l_xp_funcUnit_uses }, + { "ae_s32.l.xc", ICLASS_AE_S32_L_XC, + 0, + Opcode_ae_s32_l_xc_encode_fns, 1, Opcode_ae_s32_l_xc_funcUnit_uses }, + { "ae_s32.l.xc1", ICLASS_AE_S32_L_XC1, + 0, + Opcode_ae_s32_l_xc1_encode_fns, 1, Opcode_ae_s32_l_xc1_funcUnit_uses }, + { "ae_s32.l.i", ICLASS_AE_S32_L_I, + 0, + Opcode_ae_s32_l_i_encode_fns, 1, Opcode_ae_s32_l_i_funcUnit_uses }, + { "ae_s32.l.ip", ICLASS_AE_S32_L_IP, + 0, + Opcode_ae_s32_l_ip_encode_fns, 1, Opcode_ae_s32_l_ip_funcUnit_uses }, + { "ae_s32.l.x", ICLASS_AE_S32_L_X, + 0, + Opcode_ae_s32_l_x_encode_fns, 1, Opcode_ae_s32_l_x_funcUnit_uses }, + { "ae_s32.l.xp", ICLASS_AE_S32_L_XP, + 0, + Opcode_ae_s32_l_xp_encode_fns, 1, Opcode_ae_s32_l_xp_funcUnit_uses }, + { "ae_s32.h.xc", ICLASS_AE_S32_H_XC, + 0, + Opcode_ae_s32_h_xc_encode_fns, 1, Opcode_ae_s32_h_xc_funcUnit_uses }, + { "ae_s32.h.xc1", ICLASS_AE_S32_H_XC1, + 0, + Opcode_ae_s32_h_xc1_encode_fns, 1, Opcode_ae_s32_h_xc1_funcUnit_uses }, + { "ae_s32.h.i", ICLASS_AE_S32_H_I, + 0, + Opcode_ae_s32_h_i_encode_fns, 1, Opcode_ae_s32_h_i_funcUnit_uses }, + { "ae_s32.h.ip", ICLASS_AE_S32_H_IP, + 0, + Opcode_ae_s32_h_ip_encode_fns, 1, Opcode_ae_s32_h_ip_funcUnit_uses }, + { "ae_s32.h.x", ICLASS_AE_S32_H_X, + 0, + Opcode_ae_s32_h_x_encode_fns, 1, Opcode_ae_s32_h_x_funcUnit_uses }, + { "ae_s32.h.xp", ICLASS_AE_S32_H_XP, + 0, + Opcode_ae_s32_h_xp_encode_fns, 1, Opcode_ae_s32_h_xp_funcUnit_uses }, + { "ae_s16.0.xc", ICLASS_AE_S16_0_XC, + 0, + Opcode_ae_s16_0_xc_encode_fns, 1, Opcode_ae_s16_0_xc_funcUnit_uses }, + { "ae_s16.0.xc1", ICLASS_AE_S16_0_XC1, + 0, + Opcode_ae_s16_0_xc1_encode_fns, 1, Opcode_ae_s16_0_xc1_funcUnit_uses }, + { "ae_s16.0.i", ICLASS_AE_S16_0_I, + 0, + Opcode_ae_s16_0_i_encode_fns, 1, Opcode_ae_s16_0_i_funcUnit_uses }, + { "ae_s16.0.ip", ICLASS_AE_S16_0_IP, + 0, + Opcode_ae_s16_0_ip_encode_fns, 1, Opcode_ae_s16_0_ip_funcUnit_uses }, + { "ae_s16.0.x", ICLASS_AE_S16_0_X, + 0, + Opcode_ae_s16_0_x_encode_fns, 1, Opcode_ae_s16_0_x_funcUnit_uses }, + { "ae_s16.0.xp", ICLASS_AE_S16_0_XP, + 0, + Opcode_ae_s16_0_xp_encode_fns, 1, Opcode_ae_s16_0_xp_funcUnit_uses }, + { "ae_s8.0.xc", ICLASS_AE_S8_0_XC, + 0, + Opcode_ae_s8_0_xc_encode_fns, 1, Opcode_ae_s8_0_xc_funcUnit_uses }, + { "ae_s8.0.xc1", ICLASS_AE_S8_0_XC1, + 0, + Opcode_ae_s8_0_xc1_encode_fns, 1, Opcode_ae_s8_0_xc1_funcUnit_uses }, + { "ae_s8.0.i", ICLASS_AE_S8_0_I, + 0, + Opcode_ae_s8_0_i_encode_fns, 1, Opcode_ae_s8_0_i_funcUnit_uses }, + { "ae_s8.0.ip", ICLASS_AE_S8_0_IP, + 0, + Opcode_ae_s8_0_ip_encode_fns, 1, Opcode_ae_s8_0_ip_funcUnit_uses }, + { "ae_s8.0.x", ICLASS_AE_S8_0_X, + 0, + Opcode_ae_s8_0_x_encode_fns, 1, Opcode_ae_s8_0_x_funcUnit_uses }, + { "ae_s8.0.xp", ICLASS_AE_S8_0_XP, + 0, + Opcode_ae_s8_0_xp_encode_fns, 1, Opcode_ae_s8_0_xp_funcUnit_uses }, + { "ae_s64.xc", ICLASS_AE_S64_XC, + 0, + Opcode_ae_s64_xc_encode_fns, 1, Opcode_ae_s64_xc_funcUnit_uses }, + { "ae_s64.xc1", ICLASS_AE_S64_XC1, + 0, + Opcode_ae_s64_xc1_encode_fns, 1, Opcode_ae_s64_xc1_funcUnit_uses }, + { "ae_s64.i", ICLASS_AE_S64_I, + 0, + Opcode_ae_s64_i_encode_fns, 1, Opcode_ae_s64_i_funcUnit_uses }, + { "ae_s64.ip", ICLASS_AE_S64_IP, + 0, + Opcode_ae_s64_ip_encode_fns, 1, Opcode_ae_s64_ip_funcUnit_uses }, + { "ae_s64.x", ICLASS_AE_S64_X, + 0, + Opcode_ae_s64_x_encode_fns, 1, Opcode_ae_s64_x_funcUnit_uses }, + { "ae_s64.xp", ICLASS_AE_S64_XP, + 0, + Opcode_ae_s64_xp_encode_fns, 1, Opcode_ae_s64_xp_funcUnit_uses }, + { "ae_s32m.xc", ICLASS_AE_S32M_XC, + 0, + Opcode_ae_s32m_xc_encode_fns, 1, Opcode_ae_s32m_xc_funcUnit_uses }, + { "ae_s32m.i", ICLASS_AE_S32M_I, + 0, + Opcode_ae_s32m_i_encode_fns, 1, Opcode_ae_s32m_i_funcUnit_uses }, + { "ae_s32m.iu", ICLASS_AE_S32M_IU, + 0, + Opcode_ae_s32m_iu_encode_fns, 1, Opcode_ae_s32m_iu_funcUnit_uses }, + { "ae_s32m.x", ICLASS_AE_S32M_X, + 0, + Opcode_ae_s32m_x_encode_fns, 1, Opcode_ae_s32m_x_funcUnit_uses }, + { "ae_s32m.xu", ICLASS_AE_S32M_XU, + 0, + Opcode_ae_s32m_xu_encode_fns, 1, Opcode_ae_s32m_xu_funcUnit_uses }, + { "ae_l32x2.xc2", ICLASS_AE_L32X2_XC2, + 0, + Opcode_ae_l32x2_xc2_encode_fns, 1, Opcode_ae_l32x2_xc2_funcUnit_uses }, + { "ae_l16x4.xc2", ICLASS_AE_L16X4_XC2, + 0, + Opcode_ae_l16x4_xc2_encode_fns, 1, Opcode_ae_l16x4_xc2_funcUnit_uses }, + { "ae_l8x8.xc2", ICLASS_AE_L8X8_XC2, + 0, + Opcode_ae_l8x8_xc2_encode_fns, 1, Opcode_ae_l8x8_xc2_funcUnit_uses }, + { "ae_l64.xc2", ICLASS_AE_L64_XC2, + 0, + Opcode_ae_l64_xc2_encode_fns, 1, Opcode_ae_l64_xc2_funcUnit_uses }, + { "ae_s32x2.xc2", ICLASS_AE_S32X2_XC2, + 0, + Opcode_ae_s32x2_xc2_encode_fns, 1, Opcode_ae_s32x2_xc2_funcUnit_uses }, + { "ae_s16x4.xc2", ICLASS_AE_S16X4_XC2, + 0, + Opcode_ae_s16x4_xc2_encode_fns, 1, Opcode_ae_s16x4_xc2_funcUnit_uses }, + { "ae_s8x8.xc2", ICLASS_AE_S8X8_XC2, + 0, + Opcode_ae_s8x8_xc2_encode_fns, 1, Opcode_ae_s8x8_xc2_funcUnit_uses }, + { "ae_s64.xc2", ICLASS_AE_S64_XC2, + 0, + Opcode_ae_s64_xc2_encode_fns, 1, Opcode_ae_s64_xc2_funcUnit_uses }, + { "ae_s16x4rng.i", ICLASS_AE_S16X4RNG_I, + 0, + Opcode_ae_s16x4rng_i_encode_fns, 1, Opcode_ae_s16x4rng_i_funcUnit_uses }, + { "ae_s16x4rng.ip", ICLASS_AE_S16X4RNG_IP, + 0, + Opcode_ae_s16x4rng_ip_encode_fns, 1, Opcode_ae_s16x4rng_ip_funcUnit_uses }, + { "ae_s16x4rng.x", ICLASS_AE_S16X4RNG_X, + 0, + Opcode_ae_s16x4rng_x_encode_fns, 1, Opcode_ae_s16x4rng_x_funcUnit_uses }, + { "ae_s16x4rng.xp", ICLASS_AE_S16X4RNG_XP, + 0, + Opcode_ae_s16x4rng_xp_encode_fns, 1, Opcode_ae_s16x4rng_xp_funcUnit_uses }, + { "ae_l32x2x2.xc", ICLASS_AE_L32X2X2_XC, + 0, + Opcode_ae_l32x2x2_xc_encode_fns, 1, Opcode_ae_l32x2x2_xc_funcUnit_uses }, + { "ae_l32x2x2.xc1", ICLASS_AE_L32X2X2_XC1, + 0, + Opcode_ae_l32x2x2_xc1_encode_fns, 1, Opcode_ae_l32x2x2_xc1_funcUnit_uses }, + { "ae_l32x2x2.i", ICLASS_AE_L32X2X2_I, + 0, + Opcode_ae_l32x2x2_i_encode_fns, 1, Opcode_ae_l32x2x2_i_funcUnit_uses }, + { "ae_l32x2x2.ip", ICLASS_AE_L32X2X2_IP, + 0, + Opcode_ae_l32x2x2_ip_encode_fns, 1, Opcode_ae_l32x2x2_ip_funcUnit_uses }, + { "ae_l32x2x2.x", ICLASS_AE_L32X2X2_X, + 0, + Opcode_ae_l32x2x2_x_encode_fns, 1, Opcode_ae_l32x2x2_x_funcUnit_uses }, + { "ae_l32x2x2.xp", ICLASS_AE_L32X2X2_XP, + 0, + Opcode_ae_l32x2x2_xp_encode_fns, 1, Opcode_ae_l32x2x2_xp_funcUnit_uses }, + { "ae_l16x4x2.xc", ICLASS_AE_L16X4X2_XC, + 0, + Opcode_ae_l16x4x2_xc_encode_fns, 1, Opcode_ae_l16x4x2_xc_funcUnit_uses }, + { "ae_l16x4x2.xc1", ICLASS_AE_L16X4X2_XC1, + 0, + Opcode_ae_l16x4x2_xc1_encode_fns, 1, Opcode_ae_l16x4x2_xc1_funcUnit_uses }, + { "ae_l16x4x2.i", ICLASS_AE_L16X4X2_I, + 0, + Opcode_ae_l16x4x2_i_encode_fns, 1, Opcode_ae_l16x4x2_i_funcUnit_uses }, + { "ae_l16x4x2.ip", ICLASS_AE_L16X4X2_IP, + 0, + Opcode_ae_l16x4x2_ip_encode_fns, 1, Opcode_ae_l16x4x2_ip_funcUnit_uses }, + { "ae_l16x4x2.x", ICLASS_AE_L16X4X2_X, + 0, + Opcode_ae_l16x4x2_x_encode_fns, 1, Opcode_ae_l16x4x2_x_funcUnit_uses }, + { "ae_l16x4x2.xp", ICLASS_AE_L16X4X2_XP, + 0, + Opcode_ae_l16x4x2_xp_encode_fns, 1, Opcode_ae_l16x4x2_xp_funcUnit_uses }, + { "ae_l8x8x2.xc", ICLASS_AE_L8X8X2_XC, + 0, + Opcode_ae_l8x8x2_xc_encode_fns, 1, Opcode_ae_l8x8x2_xc_funcUnit_uses }, + { "ae_l8x8x2.xc1", ICLASS_AE_L8X8X2_XC1, + 0, + Opcode_ae_l8x8x2_xc1_encode_fns, 1, Opcode_ae_l8x8x2_xc1_funcUnit_uses }, + { "ae_l8x8x2.i", ICLASS_AE_L8X8X2_I, + 0, + Opcode_ae_l8x8x2_i_encode_fns, 1, Opcode_ae_l8x8x2_i_funcUnit_uses }, + { "ae_l8x8x2.ip", ICLASS_AE_L8X8X2_IP, + 0, + Opcode_ae_l8x8x2_ip_encode_fns, 1, Opcode_ae_l8x8x2_ip_funcUnit_uses }, + { "ae_l8x8x2.x", ICLASS_AE_L8X8X2_X, + 0, + Opcode_ae_l8x8x2_x_encode_fns, 1, Opcode_ae_l8x8x2_x_funcUnit_uses }, + { "ae_l8x8x2.xp", ICLASS_AE_L8X8X2_XP, + 0, + Opcode_ae_l8x8x2_xp_encode_fns, 1, Opcode_ae_l8x8x2_xp_funcUnit_uses }, + { "ae_l64x2.xc", ICLASS_AE_L64X2_XC, + 0, + Opcode_ae_l64x2_xc_encode_fns, 1, Opcode_ae_l64x2_xc_funcUnit_uses }, + { "ae_l64x2.xc1", ICLASS_AE_L64X2_XC1, + 0, + Opcode_ae_l64x2_xc1_encode_fns, 1, Opcode_ae_l64x2_xc1_funcUnit_uses }, + { "ae_l64x2.i", ICLASS_AE_L64X2_I, + 0, + Opcode_ae_l64x2_i_encode_fns, 1, Opcode_ae_l64x2_i_funcUnit_uses }, + { "ae_l64x2.ip", ICLASS_AE_L64X2_IP, + 0, + Opcode_ae_l64x2_ip_encode_fns, 1, Opcode_ae_l64x2_ip_funcUnit_uses }, + { "ae_l64x2.x", ICLASS_AE_L64X2_X, + 0, + Opcode_ae_l64x2_x_encode_fns, 1, Opcode_ae_l64x2_x_funcUnit_uses }, + { "ae_l64x2.xp", ICLASS_AE_L64X2_XP, + 0, + Opcode_ae_l64x2_xp_encode_fns, 1, Opcode_ae_l64x2_xp_funcUnit_uses }, + { "ae_s32x2x2.xc", ICLASS_AE_S32X2X2_XC, + 0, + Opcode_ae_s32x2x2_xc_encode_fns, 1, Opcode_ae_s32x2x2_xc_funcUnit_uses }, + { "ae_s32x2x2.xc1", ICLASS_AE_S32X2X2_XC1, + 0, + Opcode_ae_s32x2x2_xc1_encode_fns, 1, Opcode_ae_s32x2x2_xc1_funcUnit_uses }, + { "ae_s32x2x2.i", ICLASS_AE_S32X2X2_I, + 0, + Opcode_ae_s32x2x2_i_encode_fns, 1, Opcode_ae_s32x2x2_i_funcUnit_uses }, + { "ae_s32x2x2.ip", ICLASS_AE_S32X2X2_IP, + 0, + Opcode_ae_s32x2x2_ip_encode_fns, 1, Opcode_ae_s32x2x2_ip_funcUnit_uses }, + { "ae_s32x2x2.x", ICLASS_AE_S32X2X2_X, + 0, + Opcode_ae_s32x2x2_x_encode_fns, 1, Opcode_ae_s32x2x2_x_funcUnit_uses }, + { "ae_s32x2x2.xp", ICLASS_AE_S32X2X2_XP, + 0, + Opcode_ae_s32x2x2_xp_encode_fns, 1, Opcode_ae_s32x2x2_xp_funcUnit_uses }, + { "ae_s32x2x2rng.i", ICLASS_AE_S32X2X2RNG_I, + 0, + Opcode_ae_s32x2x2rng_i_encode_fns, 1, Opcode_ae_s32x2x2rng_i_funcUnit_uses }, + { "ae_s32x2x2rng.ip", ICLASS_AE_S32X2X2RNG_IP, + 0, + Opcode_ae_s32x2x2rng_ip_encode_fns, 1, Opcode_ae_s32x2x2rng_ip_funcUnit_uses }, + { "ae_s32x2x2rng.x", ICLASS_AE_S32X2X2RNG_X, + 0, + Opcode_ae_s32x2x2rng_x_encode_fns, 1, Opcode_ae_s32x2x2rng_x_funcUnit_uses }, + { "ae_s32x2x2rng.xp", ICLASS_AE_S32X2X2RNG_XP, + 0, + Opcode_ae_s32x2x2rng_xp_encode_fns, 1, Opcode_ae_s32x2x2rng_xp_funcUnit_uses }, + { "ae_s16x4x2.xc", ICLASS_AE_S16X4X2_XC, + 0, + Opcode_ae_s16x4x2_xc_encode_fns, 1, Opcode_ae_s16x4x2_xc_funcUnit_uses }, + { "ae_s16x4x2.xc1", ICLASS_AE_S16X4X2_XC1, + 0, + Opcode_ae_s16x4x2_xc1_encode_fns, 1, Opcode_ae_s16x4x2_xc1_funcUnit_uses }, + { "ae_s16x4x2.i", ICLASS_AE_S16X4X2_I, + 0, + Opcode_ae_s16x4x2_i_encode_fns, 1, Opcode_ae_s16x4x2_i_funcUnit_uses }, + { "ae_s16x4x2.ip", ICLASS_AE_S16X4X2_IP, + 0, + Opcode_ae_s16x4x2_ip_encode_fns, 1, Opcode_ae_s16x4x2_ip_funcUnit_uses }, + { "ae_s16x4x2.x", ICLASS_AE_S16X4X2_X, + 0, + Opcode_ae_s16x4x2_x_encode_fns, 1, Opcode_ae_s16x4x2_x_funcUnit_uses }, + { "ae_s16x4x2.xp", ICLASS_AE_S16X4X2_XP, + 0, + Opcode_ae_s16x4x2_xp_encode_fns, 1, Opcode_ae_s16x4x2_xp_funcUnit_uses }, + { "ae_s8x8x2.xc", ICLASS_AE_S8X8X2_XC, + 0, + Opcode_ae_s8x8x2_xc_encode_fns, 1, Opcode_ae_s8x8x2_xc_funcUnit_uses }, + { "ae_s8x8x2.xc1", ICLASS_AE_S8X8X2_XC1, + 0, + Opcode_ae_s8x8x2_xc1_encode_fns, 1, Opcode_ae_s8x8x2_xc1_funcUnit_uses }, + { "ae_s8x8x2.i", ICLASS_AE_S8X8X2_I, + 0, + Opcode_ae_s8x8x2_i_encode_fns, 1, Opcode_ae_s8x8x2_i_funcUnit_uses }, + { "ae_s8x8x2.ip", ICLASS_AE_S8X8X2_IP, + 0, + Opcode_ae_s8x8x2_ip_encode_fns, 1, Opcode_ae_s8x8x2_ip_funcUnit_uses }, + { "ae_s8x8x2.x", ICLASS_AE_S8X8X2_X, + 0, + Opcode_ae_s8x8x2_x_encode_fns, 1, Opcode_ae_s8x8x2_x_funcUnit_uses }, + { "ae_s8x8x2.xp", ICLASS_AE_S8X8X2_XP, + 0, + Opcode_ae_s8x8x2_xp_encode_fns, 1, Opcode_ae_s8x8x2_xp_funcUnit_uses }, + { "ae_s8x4ux2.i", ICLASS_AE_S8X4UX2_I, + 0, + Opcode_ae_s8x4ux2_i_encode_fns, 1, Opcode_ae_s8x4ux2_i_funcUnit_uses }, + { "ae_s8x4ux2.ip", ICLASS_AE_S8X4UX2_IP, + 0, + Opcode_ae_s8x4ux2_ip_encode_fns, 1, Opcode_ae_s8x4ux2_ip_funcUnit_uses }, + { "ae_s8x4ux2.x", ICLASS_AE_S8X4UX2_X, + 0, + Opcode_ae_s8x4ux2_x_encode_fns, 1, Opcode_ae_s8x4ux2_x_funcUnit_uses }, + { "ae_s8x4ux2.xp", ICLASS_AE_S8X4UX2_XP, + 0, + Opcode_ae_s8x4ux2_xp_encode_fns, 1, Opcode_ae_s8x4ux2_xp_funcUnit_uses }, + { "ae_s64x2.xc", ICLASS_AE_S64X2_XC, + 0, + Opcode_ae_s64x2_xc_encode_fns, 1, Opcode_ae_s64x2_xc_funcUnit_uses }, + { "ae_s64x2.xc1", ICLASS_AE_S64X2_XC1, + 0, + Opcode_ae_s64x2_xc1_encode_fns, 1, Opcode_ae_s64x2_xc1_funcUnit_uses }, + { "ae_s64x2.i", ICLASS_AE_S64X2_I, + 0, + Opcode_ae_s64x2_i_encode_fns, 1, Opcode_ae_s64x2_i_funcUnit_uses }, + { "ae_s64x2.ip", ICLASS_AE_S64X2_IP, + 0, + Opcode_ae_s64x2_ip_encode_fns, 1, Opcode_ae_s64x2_ip_funcUnit_uses }, + { "ae_s64x2.x", ICLASS_AE_S64X2_X, + 0, + Opcode_ae_s64x2_x_encode_fns, 1, Opcode_ae_s64x2_x_funcUnit_uses }, + { "ae_s64x2.xp", ICLASS_AE_S64X2_XP, + 0, + Opcode_ae_s64x2_xp_encode_fns, 1, Opcode_ae_s64x2_xp_funcUnit_uses }, + { "ae_l32x2x2.xc2", ICLASS_AE_L32X2X2_XC2, + 0, + Opcode_ae_l32x2x2_xc2_encode_fns, 1, Opcode_ae_l32x2x2_xc2_funcUnit_uses }, + { "ae_l16x4x2.xc2", ICLASS_AE_L16X4X2_XC2, + 0, + Opcode_ae_l16x4x2_xc2_encode_fns, 1, Opcode_ae_l16x4x2_xc2_funcUnit_uses }, + { "ae_l8x8x2.xc2", ICLASS_AE_L8X8X2_XC2, + 0, + Opcode_ae_l8x8x2_xc2_encode_fns, 1, Opcode_ae_l8x8x2_xc2_funcUnit_uses }, + { "ae_l64x2.xc2", ICLASS_AE_L64X2_XC2, + 0, + Opcode_ae_l64x2_xc2_encode_fns, 1, Opcode_ae_l64x2_xc2_funcUnit_uses }, + { "ae_s32x2x2.xc2", ICLASS_AE_S32X2X2_XC2, + 0, + Opcode_ae_s32x2x2_xc2_encode_fns, 1, Opcode_ae_s32x2x2_xc2_funcUnit_uses }, + { "ae_s16x4x2.xc2", ICLASS_AE_S16X4X2_XC2, + 0, + Opcode_ae_s16x4x2_xc2_encode_fns, 1, Opcode_ae_s16x4x2_xc2_funcUnit_uses }, + { "ae_s8x8x2.xc2", ICLASS_AE_S8X8X2_XC2, + 0, + Opcode_ae_s8x8x2_xc2_encode_fns, 1, Opcode_ae_s8x8x2_xc2_funcUnit_uses }, + { "ae_s64x2.xc2", ICLASS_AE_S64X2_XC2, + 0, + Opcode_ae_s64x2_xc2_encode_fns, 1, Opcode_ae_s64x2_xc2_funcUnit_uses }, + { "ae_s16x4x2rng.i", ICLASS_AE_S16X4X2RNG_I, + 0, + Opcode_ae_s16x4x2rng_i_encode_fns, 1, Opcode_ae_s16x4x2rng_i_funcUnit_uses }, + { "ae_s16x4x2rng.ip", ICLASS_AE_S16X4X2RNG_IP, + 0, + Opcode_ae_s16x4x2rng_ip_encode_fns, 1, Opcode_ae_s16x4x2rng_ip_funcUnit_uses }, + { "ae_s16x4x2rng.x", ICLASS_AE_S16X4X2RNG_X, + 0, + Opcode_ae_s16x4x2rng_x_encode_fns, 1, Opcode_ae_s16x4x2rng_x_funcUnit_uses }, + { "ae_s16x4x2rng.xp", ICLASS_AE_S16X4X2RNG_XP, + 0, + Opcode_ae_s16x4x2rng_xp_encode_fns, 1, Opcode_ae_s16x4x2rng_xp_funcUnit_uses }, + { "ae_zalign64", ICLASS_AE_ZALIGN64, + 0, + Opcode_ae_zalign64_encode_fns, 0, 0 }, + { "ae_lalign64.i", ICLASS_AE_LALIGN64_I, + 0, + Opcode_ae_lalign64_i_encode_fns, 1, Opcode_ae_lalign64_i_funcUnit_uses }, + { "ae_salign64.i", ICLASS_AE_SALIGN64_I, + 0, + Opcode_ae_salign64_i_encode_fns, 1, Opcode_ae_salign64_i_funcUnit_uses }, + { "ae_movalign", ICLASS_AE_MOVALIGN, + 0, + Opcode_ae_movalign_encode_fns, 0, 0 }, + { "ae_la64.pp", ICLASS_AE_LA64_PP, + 0, + Opcode_ae_la64_pp_encode_fns, 1, Opcode_ae_la64_pp_funcUnit_uses }, + { "ae_la24pos.pc", ICLASS_AE_LA24POS_PC, + 0, + Opcode_ae_la24pos_pc_encode_fns, 1, Opcode_ae_la24pos_pc_funcUnit_uses }, + { "ae_la24neg.pc", ICLASS_AE_LA24NEG_PC, + 0, + Opcode_ae_la24neg_pc_encode_fns, 1, Opcode_ae_la24neg_pc_funcUnit_uses }, + { "ae_la24pos.pc1", ICLASS_AE_LA24POS_PC1, + 0, + Opcode_ae_la24pos_pc1_encode_fns, 1, Opcode_ae_la24pos_pc1_funcUnit_uses }, + { "ae_la24neg.pc1", ICLASS_AE_LA24NEG_PC1, + 0, + Opcode_ae_la24neg_pc1_encode_fns, 1, Opcode_ae_la24neg_pc1_funcUnit_uses }, + { "ae_la24x2pos.pc", ICLASS_AE_LA24X2POS_PC, + 0, + Opcode_ae_la24x2pos_pc_encode_fns, 1, Opcode_ae_la24x2pos_pc_funcUnit_uses }, + { "ae_la24x2neg.pc", ICLASS_AE_LA24X2NEG_PC, + 0, + Opcode_ae_la24x2neg_pc_encode_fns, 1, Opcode_ae_la24x2neg_pc_funcUnit_uses }, + { "ae_la24x2pos.pc1", ICLASS_AE_LA24X2POS_PC1, + 0, + Opcode_ae_la24x2pos_pc1_encode_fns, 1, Opcode_ae_la24x2pos_pc1_funcUnit_uses }, + { "ae_la24x2neg.pc1", ICLASS_AE_LA24X2NEG_PC1, + 0, + Opcode_ae_la24x2neg_pc1_encode_fns, 1, Opcode_ae_la24x2neg_pc1_funcUnit_uses }, + { "ae_la32x2pos.pc", ICLASS_AE_LA32X2POS_PC, + 0, + Opcode_ae_la32x2pos_pc_encode_fns, 1, Opcode_ae_la32x2pos_pc_funcUnit_uses }, + { "ae_la32x2neg.pc", ICLASS_AE_LA32X2NEG_PC, + 0, + Opcode_ae_la32x2neg_pc_encode_fns, 1, Opcode_ae_la32x2neg_pc_funcUnit_uses }, + { "ae_la32x2pos.pc1", ICLASS_AE_LA32X2POS_PC1, + 0, + Opcode_ae_la32x2pos_pc1_encode_fns, 1, Opcode_ae_la32x2pos_pc1_funcUnit_uses }, + { "ae_la32x2neg.pc1", ICLASS_AE_LA32X2NEG_PC1, + 0, + Opcode_ae_la32x2neg_pc1_encode_fns, 1, Opcode_ae_la32x2neg_pc1_funcUnit_uses }, + { "ae_la32x2pos.pc2", ICLASS_AE_LA32X2POS_PC2, + 0, + Opcode_ae_la32x2pos_pc2_encode_fns, 1, Opcode_ae_la32x2pos_pc2_funcUnit_uses }, + { "ae_la16x4pos.pc", ICLASS_AE_LA16X4POS_PC, + 0, + Opcode_ae_la16x4pos_pc_encode_fns, 1, Opcode_ae_la16x4pos_pc_funcUnit_uses }, + { "ae_la16x4neg.pc", ICLASS_AE_LA16X4NEG_PC, + 0, + Opcode_ae_la16x4neg_pc_encode_fns, 1, Opcode_ae_la16x4neg_pc_funcUnit_uses }, + { "ae_la16x4pos.pc1", ICLASS_AE_LA16X4POS_PC1, + 0, + Opcode_ae_la16x4pos_pc1_encode_fns, 1, Opcode_ae_la16x4pos_pc1_funcUnit_uses }, + { "ae_la16x4neg.pc1", ICLASS_AE_LA16X4NEG_PC1, + 0, + Opcode_ae_la16x4neg_pc1_encode_fns, 1, Opcode_ae_la16x4neg_pc1_funcUnit_uses }, + { "ae_la16x4pos.pc2", ICLASS_AE_LA16X4POS_PC2, + 0, + Opcode_ae_la16x4pos_pc2_encode_fns, 1, Opcode_ae_la16x4pos_pc2_funcUnit_uses }, + { "ae_la8x8pos.pc", ICLASS_AE_LA8X8POS_PC, + 0, + Opcode_ae_la8x8pos_pc_encode_fns, 1, Opcode_ae_la8x8pos_pc_funcUnit_uses }, + { "ae_la8x8neg.pc", ICLASS_AE_LA8X8NEG_PC, + 0, + Opcode_ae_la8x8neg_pc_encode_fns, 1, Opcode_ae_la8x8neg_pc_funcUnit_uses }, + { "ae_la8x8pos.pc1", ICLASS_AE_LA8X8POS_PC1, + 0, + Opcode_ae_la8x8pos_pc1_encode_fns, 1, Opcode_ae_la8x8pos_pc1_funcUnit_uses }, + { "ae_la8x8neg.pc1", ICLASS_AE_LA8X8NEG_PC1, + 0, + Opcode_ae_la8x8neg_pc1_encode_fns, 1, Opcode_ae_la8x8neg_pc1_funcUnit_uses }, + { "ae_la8x8pos.pc2", ICLASS_AE_LA8X8POS_PC2, + 0, + Opcode_ae_la8x8pos_pc2_encode_fns, 1, Opcode_ae_la8x8pos_pc2_funcUnit_uses }, + { "ae_la32x2x2pos.pc", ICLASS_AE_LA32X2X2POS_PC, + 0, + Opcode_ae_la32x2x2pos_pc_encode_fns, 1, Opcode_ae_la32x2x2pos_pc_funcUnit_uses }, + { "ae_la32x2x2pos.pc1", ICLASS_AE_LA32X2X2POS_PC1, + 0, + Opcode_ae_la32x2x2pos_pc1_encode_fns, 1, Opcode_ae_la32x2x2pos_pc1_funcUnit_uses }, + { "ae_la32x2x2pos.pc2", ICLASS_AE_LA32X2X2POS_PC2, + 0, + Opcode_ae_la32x2x2pos_pc2_encode_fns, 1, Opcode_ae_la32x2x2pos_pc2_funcUnit_uses }, + { "ae_la16x4x2pos.pc", ICLASS_AE_LA16X4X2POS_PC, + 0, + Opcode_ae_la16x4x2pos_pc_encode_fns, 1, Opcode_ae_la16x4x2pos_pc_funcUnit_uses }, + { "ae_la16x4x2pos.pc1", ICLASS_AE_LA16X4X2POS_PC1, + 0, + Opcode_ae_la16x4x2pos_pc1_encode_fns, 1, Opcode_ae_la16x4x2pos_pc1_funcUnit_uses }, + { "ae_la16x4x2pos.pc2", ICLASS_AE_LA16X4X2POS_PC2, + 0, + Opcode_ae_la16x4x2pos_pc2_encode_fns, 1, Opcode_ae_la16x4x2pos_pc2_funcUnit_uses }, + { "ae_la8x8x2pos.pc", ICLASS_AE_LA8X8X2POS_PC, + 0, + Opcode_ae_la8x8x2pos_pc_encode_fns, 1, Opcode_ae_la8x8x2pos_pc_funcUnit_uses }, + { "ae_la8x8x2pos.pc1", ICLASS_AE_LA8X8X2POS_PC1, + 0, + Opcode_ae_la8x8x2pos_pc1_encode_fns, 1, Opcode_ae_la8x8x2pos_pc1_funcUnit_uses }, + { "ae_la8x8x2pos.pc2", ICLASS_AE_LA8X8X2POS_PC2, + 0, + Opcode_ae_la8x8x2pos_pc2_encode_fns, 1, Opcode_ae_la8x8x2pos_pc2_funcUnit_uses }, + { "ae_sa64pos.fp", ICLASS_AE_SA64POS_FP, + 0, + Opcode_ae_sa64pos_fp_encode_fns, 1, Opcode_ae_sa64pos_fp_funcUnit_uses }, + { "ae_sa64neg.fp", ICLASS_AE_SA64NEG_FP, + 0, + Opcode_ae_sa64neg_fp_encode_fns, 1, Opcode_ae_sa64neg_fp_funcUnit_uses }, + { "ae_la32x2.ic", ICLASS_AE_LA32X2_IC, + 0, + Opcode_ae_la32x2_ic_encode_fns, 1, Opcode_ae_la32x2_ic_funcUnit_uses }, + { "ae_la32x2.ic1", ICLASS_AE_LA32X2_IC1, + 0, + Opcode_ae_la32x2_ic1_encode_fns, 1, Opcode_ae_la32x2_ic1_funcUnit_uses }, + { "ae_la32x2.ic2", ICLASS_AE_LA32X2_IC2, + 0, + Opcode_ae_la32x2_ic2_encode_fns, 1, Opcode_ae_la32x2_ic2_funcUnit_uses }, + { "ae_la32x2.ip", ICLASS_AE_LA32X2_IP, + 0, + Opcode_ae_la32x2_ip_encode_fns, 1, Opcode_ae_la32x2_ip_funcUnit_uses }, + { "ae_la32x2.rip", ICLASS_AE_LA32X2_RIP, + 0, + Opcode_ae_la32x2_rip_encode_fns, 1, Opcode_ae_la32x2_rip_funcUnit_uses }, + { "ae_la32x2.ric", ICLASS_AE_LA32X2_RIC, + 0, + Opcode_ae_la32x2_ric_encode_fns, 1, Opcode_ae_la32x2_ric_funcUnit_uses }, + { "ae_la32x2.ric1", ICLASS_AE_LA32X2_RIC1, + 0, + Opcode_ae_la32x2_ric1_encode_fns, 1, Opcode_ae_la32x2_ric1_funcUnit_uses }, + { "ae_la16x4.ic", ICLASS_AE_LA16X4_IC, + 0, + Opcode_ae_la16x4_ic_encode_fns, 1, Opcode_ae_la16x4_ic_funcUnit_uses }, + { "ae_la16x4.ic1", ICLASS_AE_LA16X4_IC1, + 0, + Opcode_ae_la16x4_ic1_encode_fns, 1, Opcode_ae_la16x4_ic1_funcUnit_uses }, + { "ae_la16x4.ic2", ICLASS_AE_LA16X4_IC2, + 0, + Opcode_ae_la16x4_ic2_encode_fns, 1, Opcode_ae_la16x4_ic2_funcUnit_uses }, + { "ae_la16x4.ip", ICLASS_AE_LA16X4_IP, + 0, + Opcode_ae_la16x4_ip_encode_fns, 1, Opcode_ae_la16x4_ip_funcUnit_uses }, + { "ae_la16x4.rip", ICLASS_AE_LA16X4_RIP, + 0, + Opcode_ae_la16x4_rip_encode_fns, 1, Opcode_ae_la16x4_rip_funcUnit_uses }, + { "ae_la16x4.ric", ICLASS_AE_LA16X4_RIC, + 0, + Opcode_ae_la16x4_ric_encode_fns, 1, Opcode_ae_la16x4_ric_funcUnit_uses }, + { "ae_la16x4.ric1", ICLASS_AE_LA16X4_RIC1, + 0, + Opcode_ae_la16x4_ric1_encode_fns, 1, Opcode_ae_la16x4_ric1_funcUnit_uses }, + { "ae_la8x8.ic", ICLASS_AE_LA8X8_IC, + 0, + Opcode_ae_la8x8_ic_encode_fns, 1, Opcode_ae_la8x8_ic_funcUnit_uses }, + { "ae_la8x8.ic1", ICLASS_AE_LA8X8_IC1, + 0, + Opcode_ae_la8x8_ic1_encode_fns, 1, Opcode_ae_la8x8_ic1_funcUnit_uses }, + { "ae_la8x8.ic2", ICLASS_AE_LA8X8_IC2, + 0, + Opcode_ae_la8x8_ic2_encode_fns, 1, Opcode_ae_la8x8_ic2_funcUnit_uses }, + { "ae_la8x8.ip", ICLASS_AE_LA8X8_IP, + 0, + Opcode_ae_la8x8_ip_encode_fns, 1, Opcode_ae_la8x8_ip_funcUnit_uses }, + { "ae_la8x8.rip", ICLASS_AE_LA8X8_RIP, + 0, + Opcode_ae_la8x8_rip_encode_fns, 1, Opcode_ae_la8x8_rip_funcUnit_uses }, + { "ae_la8x8.ric", ICLASS_AE_LA8X8_RIC, + 0, + Opcode_ae_la8x8_ric_encode_fns, 1, Opcode_ae_la8x8_ric_funcUnit_uses }, + { "ae_la8x8.ric1", ICLASS_AE_LA8X8_RIC1, + 0, + Opcode_ae_la8x8_ric1_encode_fns, 1, Opcode_ae_la8x8_ric1_funcUnit_uses }, + { "ae_la32x2f24.ic", ICLASS_AE_LA32X2F24_IC, + 0, + Opcode_ae_la32x2f24_ic_encode_fns, 1, Opcode_ae_la32x2f24_ic_funcUnit_uses }, + { "ae_la32x2f24.ic1", ICLASS_AE_LA32X2F24_IC1, + 0, + Opcode_ae_la32x2f24_ic1_encode_fns, 1, Opcode_ae_la32x2f24_ic1_funcUnit_uses }, + { "ae_la32x2f24.ip", ICLASS_AE_LA32X2F24_IP, + 0, + Opcode_ae_la32x2f24_ip_encode_fns, 1, Opcode_ae_la32x2f24_ip_funcUnit_uses }, + { "ae_la32x2f24.rip", ICLASS_AE_LA32X2F24_RIP, + 0, + Opcode_ae_la32x2f24_rip_encode_fns, 1, Opcode_ae_la32x2f24_rip_funcUnit_uses }, + { "ae_la32x2f24.ric", ICLASS_AE_LA32X2F24_RIC, + 0, + Opcode_ae_la32x2f24_ric_encode_fns, 1, Opcode_ae_la32x2f24_ric_funcUnit_uses }, + { "ae_la32x2f24.ric1", ICLASS_AE_LA32X2F24_RIC1, + 0, + Opcode_ae_la32x2f24_ric1_encode_fns, 1, Opcode_ae_la32x2f24_ric1_funcUnit_uses }, + { "ae_la24.ic", ICLASS_AE_LA24_IC, + 0, + Opcode_ae_la24_ic_encode_fns, 1, Opcode_ae_la24_ic_funcUnit_uses }, + { "ae_la24.ic1", ICLASS_AE_LA24_IC1, + 0, + Opcode_ae_la24_ic1_encode_fns, 1, Opcode_ae_la24_ic1_funcUnit_uses }, + { "ae_la24.ip", ICLASS_AE_LA24_IP, + 0, + Opcode_ae_la24_ip_encode_fns, 1, Opcode_ae_la24_ip_funcUnit_uses }, + { "ae_la24.rip", ICLASS_AE_LA24_RIP, + 0, + Opcode_ae_la24_rip_encode_fns, 1, Opcode_ae_la24_rip_funcUnit_uses }, + { "ae_la24.ric", ICLASS_AE_LA24_RIC, + 0, + Opcode_ae_la24_ric_encode_fns, 1, Opcode_ae_la24_ric_funcUnit_uses }, + { "ae_la24.ric1", ICLASS_AE_LA24_RIC1, + 0, + Opcode_ae_la24_ric1_encode_fns, 1, Opcode_ae_la24_ric1_funcUnit_uses }, + { "ae_la24x2.ic", ICLASS_AE_LA24X2_IC, + 0, + Opcode_ae_la24x2_ic_encode_fns, 1, Opcode_ae_la24x2_ic_funcUnit_uses }, + { "ae_la24x2.ic1", ICLASS_AE_LA24X2_IC1, + 0, + Opcode_ae_la24x2_ic1_encode_fns, 1, Opcode_ae_la24x2_ic1_funcUnit_uses }, + { "ae_la24x2.ip", ICLASS_AE_LA24X2_IP, + 0, + Opcode_ae_la24x2_ip_encode_fns, 1, Opcode_ae_la24x2_ip_funcUnit_uses }, + { "ae_la24x2.rip", ICLASS_AE_LA24X2_RIP, + 0, + Opcode_ae_la24x2_rip_encode_fns, 1, Opcode_ae_la24x2_rip_funcUnit_uses }, + { "ae_la24x2.ric", ICLASS_AE_LA24X2_RIC, + 0, + Opcode_ae_la24x2_ric_encode_fns, 1, Opcode_ae_la24x2_ric_funcUnit_uses }, + { "ae_la24x2.ric1", ICLASS_AE_LA24X2_RIC1, + 0, + Opcode_ae_la24x2_ric1_encode_fns, 1, Opcode_ae_la24x2_ric1_funcUnit_uses }, + { "ae_sa32x2.ic", ICLASS_AE_SA32X2_IC, + 0, + Opcode_ae_sa32x2_ic_encode_fns, 1, Opcode_ae_sa32x2_ic_funcUnit_uses }, + { "ae_sa32x2.ic1", ICLASS_AE_SA32X2_IC1, + 0, + Opcode_ae_sa32x2_ic1_encode_fns, 1, Opcode_ae_sa32x2_ic1_funcUnit_uses }, + { "ae_sa32x2.ic2", ICLASS_AE_SA32X2_IC2, + 0, + Opcode_ae_sa32x2_ic2_encode_fns, 1, Opcode_ae_sa32x2_ic2_funcUnit_uses }, + { "ae_sa32x2.ip", ICLASS_AE_SA32X2_IP, + 0, + Opcode_ae_sa32x2_ip_encode_fns, 1, Opcode_ae_sa32x2_ip_funcUnit_uses }, + { "ae_sa32x2.rip", ICLASS_AE_SA32X2_RIP, + 0, + Opcode_ae_sa32x2_rip_encode_fns, 1, Opcode_ae_sa32x2_rip_funcUnit_uses }, + { "ae_sa32x2.ric", ICLASS_AE_SA32X2_RIC, + 0, + Opcode_ae_sa32x2_ric_encode_fns, 1, Opcode_ae_sa32x2_ric_funcUnit_uses }, + { "ae_sa32x2.ric1", ICLASS_AE_SA32X2_RIC1, + 0, + Opcode_ae_sa32x2_ric1_encode_fns, 1, Opcode_ae_sa32x2_ric1_funcUnit_uses }, + { "ae_sa16x4.ic", ICLASS_AE_SA16X4_IC, + 0, + Opcode_ae_sa16x4_ic_encode_fns, 1, Opcode_ae_sa16x4_ic_funcUnit_uses }, + { "ae_sa16x4.ic1", ICLASS_AE_SA16X4_IC1, + 0, + Opcode_ae_sa16x4_ic1_encode_fns, 1, Opcode_ae_sa16x4_ic1_funcUnit_uses }, + { "ae_sa16x4.ic2", ICLASS_AE_SA16X4_IC2, + 0, + Opcode_ae_sa16x4_ic2_encode_fns, 1, Opcode_ae_sa16x4_ic2_funcUnit_uses }, + { "ae_sa16x4.ip", ICLASS_AE_SA16X4_IP, + 0, + Opcode_ae_sa16x4_ip_encode_fns, 1, Opcode_ae_sa16x4_ip_funcUnit_uses }, + { "ae_sa16x4.rip", ICLASS_AE_SA16X4_RIP, + 0, + Opcode_ae_sa16x4_rip_encode_fns, 1, Opcode_ae_sa16x4_rip_funcUnit_uses }, + { "ae_sa16x4.ric", ICLASS_AE_SA16X4_RIC, + 0, + Opcode_ae_sa16x4_ric_encode_fns, 1, Opcode_ae_sa16x4_ric_funcUnit_uses }, + { "ae_sa16x4.ric1", ICLASS_AE_SA16X4_RIC1, + 0, + Opcode_ae_sa16x4_ric1_encode_fns, 1, Opcode_ae_sa16x4_ric1_funcUnit_uses }, + { "ae_sa8x8.ic", ICLASS_AE_SA8X8_IC, + 0, + Opcode_ae_sa8x8_ic_encode_fns, 1, Opcode_ae_sa8x8_ic_funcUnit_uses }, + { "ae_sa8x8.ic1", ICLASS_AE_SA8X8_IC1, + 0, + Opcode_ae_sa8x8_ic1_encode_fns, 1, Opcode_ae_sa8x8_ic1_funcUnit_uses }, + { "ae_sa8x8.ic2", ICLASS_AE_SA8X8_IC2, + 0, + Opcode_ae_sa8x8_ic2_encode_fns, 1, Opcode_ae_sa8x8_ic2_funcUnit_uses }, + { "ae_sa8x8.ip", ICLASS_AE_SA8X8_IP, + 0, + Opcode_ae_sa8x8_ip_encode_fns, 1, Opcode_ae_sa8x8_ip_funcUnit_uses }, + { "ae_sa8x8.rip", ICLASS_AE_SA8X8_RIP, + 0, + Opcode_ae_sa8x8_rip_encode_fns, 1, Opcode_ae_sa8x8_rip_funcUnit_uses }, + { "ae_sa8x8.ric", ICLASS_AE_SA8X8_RIC, + 0, + Opcode_ae_sa8x8_ric_encode_fns, 1, Opcode_ae_sa8x8_ric_funcUnit_uses }, + { "ae_sa8x8.ric1", ICLASS_AE_SA8X8_RIC1, + 0, + Opcode_ae_sa8x8_ric1_encode_fns, 1, Opcode_ae_sa8x8_ric1_funcUnit_uses }, + { "ae_sa32x2f24.ic", ICLASS_AE_SA32X2F24_IC, + 0, + Opcode_ae_sa32x2f24_ic_encode_fns, 1, Opcode_ae_sa32x2f24_ic_funcUnit_uses }, + { "ae_sa32x2f24.ic1", ICLASS_AE_SA32X2F24_IC1, + 0, + Opcode_ae_sa32x2f24_ic1_encode_fns, 1, Opcode_ae_sa32x2f24_ic1_funcUnit_uses }, + { "ae_sa32x2f24.ip", ICLASS_AE_SA32X2F24_IP, + 0, + Opcode_ae_sa32x2f24_ip_encode_fns, 1, Opcode_ae_sa32x2f24_ip_funcUnit_uses }, + { "ae_sa32x2f24.rip", ICLASS_AE_SA32X2F24_RIP, + 0, + Opcode_ae_sa32x2f24_rip_encode_fns, 1, Opcode_ae_sa32x2f24_rip_funcUnit_uses }, + { "ae_sa32x2f24.ric", ICLASS_AE_SA32X2F24_RIC, + 0, + Opcode_ae_sa32x2f24_ric_encode_fns, 1, Opcode_ae_sa32x2f24_ric_funcUnit_uses }, + { "ae_sa32x2f24.ric1", ICLASS_AE_SA32X2F24_RIC1, + 0, + Opcode_ae_sa32x2f24_ric1_encode_fns, 1, Opcode_ae_sa32x2f24_ric1_funcUnit_uses }, + { "ae_sa24.l.ic", ICLASS_AE_SA24_L_IC, + 0, + Opcode_ae_sa24_l_ic_encode_fns, 1, Opcode_ae_sa24_l_ic_funcUnit_uses }, + { "ae_sa24.l.ic1", ICLASS_AE_SA24_L_IC1, + 0, + Opcode_ae_sa24_l_ic1_encode_fns, 1, Opcode_ae_sa24_l_ic1_funcUnit_uses }, + { "ae_sa24.l.ip", ICLASS_AE_SA24_L_IP, + 0, + Opcode_ae_sa24_l_ip_encode_fns, 1, Opcode_ae_sa24_l_ip_funcUnit_uses }, + { "ae_sa24.l.rip", ICLASS_AE_SA24_L_RIP, + 0, + Opcode_ae_sa24_l_rip_encode_fns, 1, Opcode_ae_sa24_l_rip_funcUnit_uses }, + { "ae_sa24.l.ric", ICLASS_AE_SA24_L_RIC, + 0, + Opcode_ae_sa24_l_ric_encode_fns, 1, Opcode_ae_sa24_l_ric_funcUnit_uses }, + { "ae_sa24.l.ric1", ICLASS_AE_SA24_L_RIC1, + 0, + Opcode_ae_sa24_l_ric1_encode_fns, 1, Opcode_ae_sa24_l_ric1_funcUnit_uses }, + { "ae_sa24x2.ic", ICLASS_AE_SA24X2_IC, + 0, + Opcode_ae_sa24x2_ic_encode_fns, 1, Opcode_ae_sa24x2_ic_funcUnit_uses }, + { "ae_sa24x2.ic1", ICLASS_AE_SA24X2_IC1, + 0, + Opcode_ae_sa24x2_ic1_encode_fns, 1, Opcode_ae_sa24x2_ic1_funcUnit_uses }, + { "ae_sa24x2.ip", ICLASS_AE_SA24X2_IP, + 0, + Opcode_ae_sa24x2_ip_encode_fns, 1, Opcode_ae_sa24x2_ip_funcUnit_uses }, + { "ae_sa24x2.rip", ICLASS_AE_SA24X2_RIP, + 0, + Opcode_ae_sa24x2_rip_encode_fns, 1, Opcode_ae_sa24x2_rip_funcUnit_uses }, + { "ae_sa24x2.ric", ICLASS_AE_SA24X2_RIC, + 0, + Opcode_ae_sa24x2_ric_encode_fns, 1, Opcode_ae_sa24x2_ric_funcUnit_uses }, + { "ae_sa24x2.ric1", ICLASS_AE_SA24X2_RIC1, + 0, + Opcode_ae_sa24x2_ric1_encode_fns, 1, Opcode_ae_sa24x2_ric1_funcUnit_uses }, + { "ae_addicirc", ICLASS_AE_ADDICIRC, + 0, + Opcode_ae_addicirc_encode_fns, 0, 0 }, + { "ae_addcirc.xc2", ICLASS_AE_ADDCIRC_XC2, + 0, + Opcode_ae_addcirc_xc2_encode_fns, 0, 0 }, + { "ae_addcirc.xc1", ICLASS_AE_ADDCIRC_XC1, + 0, + Opcode_ae_addcirc_xc1_encode_fns, 0, 0 }, + { "ae_addcirc.xc", ICLASS_AE_ADDCIRC_XC, + 0, + Opcode_ae_addcirc_xc_encode_fns, 0, 0 }, + { "ae_s32ra64s.i", ICLASS_AE_S32RA64S_I, + 0, + Opcode_ae_s32ra64s_i_encode_fns, 1, Opcode_ae_s32ra64s_i_funcUnit_uses }, + { "ae_s32ra64s.ip", ICLASS_AE_S32RA64S_IP, + 0, + Opcode_ae_s32ra64s_ip_encode_fns, 1, Opcode_ae_s32ra64s_ip_funcUnit_uses }, + { "ae_s32ra64s.x", ICLASS_AE_S32RA64S_X, + 0, + Opcode_ae_s32ra64s_x_encode_fns, 1, Opcode_ae_s32ra64s_x_funcUnit_uses }, + { "ae_s32ra64s.xp", ICLASS_AE_S32RA64S_XP, + 0, + Opcode_ae_s32ra64s_xp_encode_fns, 1, Opcode_ae_s32ra64s_xp_funcUnit_uses }, + { "ae_s32ra64s.xc", ICLASS_AE_S32RA64S_XC, + 0, + Opcode_ae_s32ra64s_xc_encode_fns, 1, Opcode_ae_s32ra64s_xc_funcUnit_uses }, + { "ae_s32ra64s.xc1", ICLASS_AE_S32RA64S_XC1, + 0, + Opcode_ae_s32ra64s_xc1_encode_fns, 1, Opcode_ae_s32ra64s_xc1_funcUnit_uses }, + { "ae_s24ra64s.i", ICLASS_AE_S24RA64S_I, + 0, + Opcode_ae_s24ra64s_i_encode_fns, 1, Opcode_ae_s24ra64s_i_funcUnit_uses }, + { "ae_s24ra64s.ip", ICLASS_AE_S24RA64S_IP, + 0, + Opcode_ae_s24ra64s_ip_encode_fns, 1, Opcode_ae_s24ra64s_ip_funcUnit_uses }, + { "ae_s24ra64s.x", ICLASS_AE_S24RA64S_X, + 0, + Opcode_ae_s24ra64s_x_encode_fns, 1, Opcode_ae_s24ra64s_x_funcUnit_uses }, + { "ae_s24ra64s.xp", ICLASS_AE_S24RA64S_XP, + 0, + Opcode_ae_s24ra64s_xp_encode_fns, 1, Opcode_ae_s24ra64s_xp_funcUnit_uses }, + { "ae_s24ra64s.xc", ICLASS_AE_S24RA64S_XC, + 0, + Opcode_ae_s24ra64s_xc_encode_fns, 1, Opcode_ae_s24ra64s_xc_funcUnit_uses }, + { "ae_s24ra64s.xc1", ICLASS_AE_S24RA64S_XC1, + 0, + Opcode_ae_s24ra64s_xc1_encode_fns, 1, Opcode_ae_s24ra64s_xc1_funcUnit_uses }, + { "ae_s32x2ra64s.ip", ICLASS_AE_S32X2RA64S_IP, + 0, + Opcode_ae_s32x2ra64s_ip_encode_fns, 1, Opcode_ae_s32x2ra64s_ip_funcUnit_uses }, + { "ae_s24x2ra64s.ip", ICLASS_AE_S24X2RA64S_IP, + 0, + Opcode_ae_s24x2ra64s_ip_encode_fns, 1, Opcode_ae_s24x2ra64s_ip_funcUnit_uses }, + { "ae_s16x4ra32s.ip", ICLASS_AE_S16X4RA32S_IP, + 0, + Opcode_ae_s16x4ra32s_ip_encode_fns, 1, Opcode_ae_s16x4ra32s_ip_funcUnit_uses }, + { "ae_addbrba32", ICLASS_AE_ADDBRBA32, + 0, + Opcode_ae_addbrba32_encode_fns, 0, 0 }, + { "ae_s32x2.l.ip", ICLASS_AE_S32X2_L_IP, + 0, + Opcode_ae_s32x2_l_ip_encode_fns, 1, Opcode_ae_s32x2_l_ip_funcUnit_uses }, + { "ae_bitswap", ICLASS_AE_BITSWAP, + 0, + Opcode_ae_bitswap_encode_fns, 0, 0 }, + { "ae_mul32js", ICLASS_AE_MUL32JS, + 0, + Opcode_ae_mul32js_encode_fns, 0, 0 }, + { "ae_addandsub32s", ICLASS_AE_ADDANDSUB32S, + 0, + Opcode_ae_addandsub32s_encode_fns, 0, 0 }, + { "ae_addandsub32js", ICLASS_AE_ADDANDSUB32JS, + 0, + Opcode_ae_addandsub32js_encode_fns, 0, 0 }, + { "ae_addandsubrng32", ICLASS_AE_ADDANDSUBRNG32, + 0, + Opcode_ae_addandsubrng32_encode_fns, 0, 0 }, + { "ae_addandsubrng32.h", ICLASS_AE_ADDANDSUBRNG32_H, + 0, + Opcode_ae_addandsubrng32_h_encode_fns, 0, 0 }, + { "ae_addandsubrng32.l", ICLASS_AE_ADDANDSUBRNG32_L, + 0, + Opcode_ae_addandsubrng32_l_encode_fns, 0, 0 }, + { "ae_addrng32", ICLASS_AE_ADDRNG32, + 0, + Opcode_ae_addrng32_encode_fns, 0, 0 }, + { "ae_subrng32", ICLASS_AE_SUBRNG32, + 0, + Opcode_ae_subrng32_encode_fns, 0, 0 }, + { "ae_rng32x2", ICLASS_AE_RNG32X2, + 0, + Opcode_ae_rng32x2_encode_fns, 0, 0 }, + { "ae_sel16i", ICLASS_AE_SEL16I, + 0, + Opcode_ae_sel16i_encode_fns, 0, 0 }, + { "ae_sel16i.n", ICLASS_AE_SEL16I_N, + 0, + Opcode_ae_sel16i_n_encode_fns, 0, 0 }, + { "ae_shortswap", ICLASS_AE_SHORTSWAP, + 0, + Opcode_ae_shortswap_encode_fns, 0, 0 }, + { "ae_movab4", ICLASS_AE_MOVAB4, + 0, + Opcode_ae_movab4_encode_fns, 0, 0 }, + { "ae_movab2", ICLASS_AE_MOVAB2, + 0, + Opcode_ae_movab2_encode_fns, 0, 0 }, + { "ae_movab", ICLASS_AE_MOVAB, + 0, + Opcode_ae_movab_encode_fns, 0, 0 }, + { "ae_movba", ICLASS_AE_MOVBA, + 0, + Opcode_ae_movba_encode_fns, 0, 0 }, + { "ae_movba1x2", ICLASS_AE_MOVBA1X2, + 0, + Opcode_ae_movba1x2_encode_fns, 0, 0 }, + { "ae_movba4", ICLASS_AE_MOVBA4, + 0, + Opcode_ae_movba4_encode_fns, 0, 0 }, + { "ae_movba2", ICLASS_AE_MOVBA2, + 0, + Opcode_ae_movba2_encode_fns, 0, 0 }, + { "ae_movb2", ICLASS_AE_MOVB2, + 0, + Opcode_ae_movb2_encode_fns, 0, 0 }, + { "ae_movb4", ICLASS_AE_MOVB4, + 0, + Opcode_ae_movb4_encode_fns, 0, 0 }, + { "ae_movt16x4", ICLASS_AE_MOVT16X4, + 0, + Opcode_ae_movt16x4_encode_fns, 0, 0 }, + { "ae_movf16x4", ICLASS_AE_MOVF16X4, + 0, + Opcode_ae_movf16x4_encode_fns, 0, 0 }, + { "ae_movt32x2", ICLASS_AE_MOVT32X2, + 0, + Opcode_ae_movt32x2_encode_fns, 0, 0 }, + { "ae_movf32x2", ICLASS_AE_MOVF32X2, + 0, + Opcode_ae_movf32x2_encode_fns, 0, 0 }, + { "ae_movsara7x2", ICLASS_AE_MOVSARA7X2, + 0, + Opcode_ae_movsara7x2_encode_fns, 0, 0 }, + { "ae_movsard7", ICLASS_AE_MOVSARD7, + 0, + Opcode_ae_movsard7_encode_fns, 0, 0 }, + { "ae_movasar", ICLASS_AE_MOVASAR, + 0, + Opcode_ae_movasar_encode_fns, 0, 0 }, + { "ae_movda32x2", ICLASS_AE_MOVDA32X2, + 0, + Opcode_ae_movda32x2_encode_fns, 0, 0 }, + { "ae_movda32", ICLASS_AE_MOVDA32, + 0, + Opcode_ae_movda32_encode_fns, 0, 0 }, + { "ae_movda16x2", ICLASS_AE_MOVDA16X2, + 0, + Opcode_ae_movda16x2_encode_fns, 0, 0 }, + { "ae_movda16", ICLASS_AE_MOVDA16, + 0, + Opcode_ae_movda16_encode_fns, 0, 0 }, + { "ae_movi", ICLASS_AE_MOVI, + 0, + Opcode_ae_movi_encode_fns, 0, 0 }, + { "ae_truncp24a32x2", ICLASS_AE_TRUNCP24A32X2, + 0, + Opcode_ae_truncp24a32x2_encode_fns, 0, 0 }, + { "ae_sat16x4", ICLASS_AE_SAT16X4, + 0, + Opcode_ae_sat16x4_encode_fns, 0, 0 }, + { "ae_cvt32x2f16.32", ICLASS_AE_CVT32X2F16_32, + 0, + Opcode_ae_cvt32x2f16_32_encode_fns, 0, 0 }, + { "ae_cvt32x2f16.10", ICLASS_AE_CVT32X2F16_10, + 0, + Opcode_ae_cvt32x2f16_10_encode_fns, 0, 0 }, + { "ae_sext32x2d16.32", ICLASS_AE_SEXT32X2D16_32, + 0, + Opcode_ae_sext32x2d16_32_encode_fns, 0, 0 }, + { "ae_sext32x2d16.10", ICLASS_AE_SEXT32X2D16_10, + 0, + Opcode_ae_sext32x2d16_10_encode_fns, 0, 0 }, + { "ae_cvta32f24s.l", ICLASS_AE_CVTA32F24S_L, + 0, + Opcode_ae_cvta32f24s_l_encode_fns, 0, 0 }, + { "ae_cvta32f24s.h", ICLASS_AE_CVTA32F24S_H, + 0, + Opcode_ae_cvta32f24s_h_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.ll", ICLASS_AE_CVTP24A16X2_LL, + 0, + Opcode_ae_cvtp24a16x2_ll_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.lh", ICLASS_AE_CVTP24A16X2_LH, + 0, + Opcode_ae_cvtp24a16x2_lh_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.hl", ICLASS_AE_CVTP24A16X2_HL, + 0, + Opcode_ae_cvtp24a16x2_hl_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.hh", ICLASS_AE_CVTP24A16X2_HH, + 0, + Opcode_ae_cvtp24a16x2_hh_encode_fns, 0, 0 }, + { "ae_truncp24q48x2", ICLASS_AE_TRUNCP24Q48X2, + 0, + Opcode_ae_truncp24q48x2_encode_fns, 0, 0 }, + { "ae_trunca32x2f64s", ICLASS_AE_TRUNCA32X2F64S, + 0, + Opcode_ae_trunca32x2f64s_encode_fns, 0, 0 }, + { "ae_trunci32x2f64s", ICLASS_AE_TRUNCI32X2F64S, + 0, + Opcode_ae_trunci32x2f64s_encode_fns, 0, 0 }, + { "ae_trunca32f64s.l", ICLASS_AE_TRUNCA32F64S_L, + 0, + Opcode_ae_trunca32f64s_l_encode_fns, 0, 0 }, + { "ae_trunci32f64s.l", ICLASS_AE_TRUNCI32F64S_L, + 0, + Opcode_ae_trunci32f64s_l_encode_fns, 0, 0 }, + { "ae_truncp16", ICLASS_AE_TRUNCP16, + 0, + Opcode_ae_truncp16_encode_fns, 0, 0 }, + { "ae_round32x2f64ssym", ICLASS_AE_ROUND32X2F64SSYM, + 0, + Opcode_ae_round32x2f64ssym_encode_fns, 0, 0 }, + { "ae_round32x2f64sasym", ICLASS_AE_ROUND32X2F64SASYM, + 0, + Opcode_ae_round32x2f64sasym_encode_fns, 0, 0 }, + { "ae_round32x2f48ssym", ICLASS_AE_ROUND32X2F48SSYM, + 0, + Opcode_ae_round32x2f48ssym_encode_fns, 0, 0 }, + { "ae_round32x2f48sasym", ICLASS_AE_ROUND32X2F48SASYM, + 0, + Opcode_ae_round32x2f48sasym_encode_fns, 0, 0 }, + { "ae_round16x4f32ssym", ICLASS_AE_ROUND16X4F32SSYM, + 0, + Opcode_ae_round16x4f32ssym_encode_fns, 0, 0 }, + { "ae_round16x4f32sasym", ICLASS_AE_ROUND16X4F32SASYM, + 0, + Opcode_ae_round16x4f32sasym_encode_fns, 0, 0 }, + { "ae_round24x2f48ssym", ICLASS_AE_ROUND24X2F48SSYM, + 0, + Opcode_ae_round24x2f48ssym_encode_fns, 0, 0 }, + { "ae_round24x2f48sasym", ICLASS_AE_ROUND24X2F48SASYM, + 0, + Opcode_ae_round24x2f48sasym_encode_fns, 0, 0 }, + { "ae_roundsp16q48x2sym", ICLASS_AE_ROUNDSP16Q48X2SYM, + 0, + Opcode_ae_roundsp16q48x2sym_encode_fns, 0, 0 }, + { "ae_roundsp16q48x2asym", ICLASS_AE_ROUNDSP16Q48X2ASYM, + 0, + Opcode_ae_roundsp16q48x2asym_encode_fns, 0, 0 }, + { "ae_minabs32s", ICLASS_AE_MINABS32S, + 0, + Opcode_ae_minabs32s_encode_fns, 0, 0 }, + { "ae_maxabs32s", ICLASS_AE_MAXABS32S, + 0, + Opcode_ae_maxabs32s_encode_fns, 0, 0 }, + { "ae_roundsp16f24sym", ICLASS_AE_ROUNDSP16F24SYM, + 0, + Opcode_ae_roundsp16f24sym_encode_fns, 0, 0 }, + { "ae_roundsp16f24asym", ICLASS_AE_ROUNDSP16F24ASYM, + 0, + Opcode_ae_roundsp16f24asym_encode_fns, 0, 0 }, + { "ae_mov", ICLASS_AE_MOV, + 0, + Opcode_ae_mov_encode_fns, 0, 0 }, + { "ae_movt64", ICLASS_AE_MOVT64, + 0, + Opcode_ae_movt64_encode_fns, 0, 0 }, + { "ae_movf64", ICLASS_AE_MOVF64, + 0, + Opcode_ae_movf64_encode_fns, 0, 0 }, + { "ae_cvtq56a32s", ICLASS_AE_CVTQ56A32S, + 0, + Opcode_ae_cvtq56a32s_encode_fns, 0, 0 }, + { "ae_cvt48a32", ICLASS_AE_CVT48A32, + 0, + Opcode_ae_cvt48a32_encode_fns, 0, 0 }, + { "ae_cvt64a32", ICLASS_AE_CVT64A32, + 0, + Opcode_ae_cvt64a32_encode_fns, 0, 0 }, + { "ae_cvtq56p32s.l", ICLASS_AE_CVTQ56P32S_L, + 0, + Opcode_ae_cvtq56p32s_l_encode_fns, 0, 0 }, + { "ae_cvtq56p32s.h", ICLASS_AE_CVTQ56P32S_H, + 0, + Opcode_ae_cvtq56p32s_h_encode_fns, 0, 0 }, + { "ae_cvt64f32.h", ICLASS_AE_CVT64F32_H, + 0, + Opcode_ae_cvt64f32_h_encode_fns, 0, 0 }, + { "ae_cvt48f32.l", ICLASS_AE_CVT48F32_L, + 0, + Opcode_ae_cvt48f32_l_encode_fns, 0, 0 }, + { "ae_cvt48f32.h", ICLASS_AE_CVT48F32_H, + 0, + Opcode_ae_cvt48f32_h_encode_fns, 0, 0 }, + { "ae_sat48s", ICLASS_AE_SAT48S, + 0, + Opcode_ae_sat48s_encode_fns, 0, 0 }, + { "ae_satq56s", ICLASS_AE_SATQ56S, + 0, + Opcode_ae_satq56s_encode_fns, 0, 0 }, + { "ae_sat24s", ICLASS_AE_SAT24S, + 0, + Opcode_ae_sat24s_encode_fns, 0, 0 }, + { "ae_truncq32", ICLASS_AE_TRUNCQ32, + 0, + Opcode_ae_truncq32_encode_fns, 0, 0 }, + { "ae_minabs64s", ICLASS_AE_MINABS64S, + 0, + Opcode_ae_minabs64s_encode_fns, 0, 0 }, + { "ae_maxabs64s", ICLASS_AE_MAXABS64S, + 0, + Opcode_ae_maxabs64s_encode_fns, 0, 0 }, + { "ae_roundsq32f48sym", ICLASS_AE_ROUNDSQ32F48SYM, + 0, + Opcode_ae_roundsq32f48sym_encode_fns, 0, 0 }, + { "ae_roundsq32f48asym", ICLASS_AE_ROUNDSQ32F48ASYM, + 0, + Opcode_ae_roundsq32f48asym_encode_fns, 0, 0 }, + { "ae_trunca32q48", ICLASS_AE_TRUNCA32Q48, + 0, + Opcode_ae_trunca32q48_encode_fns, 0, 0 }, + { "ae_movad32.l", ICLASS_AE_MOVAD32_L, + 0, + Opcode_ae_movad32_l_encode_fns, 0, 0 }, + { "ae_movad32.h", ICLASS_AE_MOVAD32_H, + 0, + Opcode_ae_movad32_h_encode_fns, 0, 0 }, + { "ae_movad16.3", ICLASS_AE_MOVAD16_3, + 0, + Opcode_ae_movad16_3_encode_fns, 0, 0 }, + { "ae_movad16.2", ICLASS_AE_MOVAD16_2, + 0, + Opcode_ae_movad16_2_encode_fns, 0, 0 }, + { "ae_movad16.1", ICLASS_AE_MOVAD16_1, + 0, + Opcode_ae_movad16_1_encode_fns, 0, 0 }, + { "ae_movad16.0", ICLASS_AE_MOVAD16_0, + 0, + Opcode_ae_movad16_0_encode_fns, 0, 0 }, + { "ae_sra64_32", ICLASS_AE_SRA64_32, + 0, + Opcode_ae_sra64_32_encode_fns, 0, 0 }, + { "ae_pksr32", ICLASS_AE_PKSR32, + 0, + Opcode_ae_pksr32_encode_fns, 0, 0 }, + { "ae_pksr24", ICLASS_AE_PKSR24, + 0, + Opcode_ae_pksr24_encode_fns, 0, 0 }, + { "ae_pksrf32", ICLASS_AE_PKSRF32, + 0, + Opcode_ae_pksrf32_encode_fns, 0, 0 }, + { "ae_pksr16", ICLASS_AE_PKSR16, + 0, + Opcode_ae_pksr16_encode_fns, 0, 0 }, + { "ae_trunca16p24s.l", ICLASS_AE_TRUNCA16P24S_L, + 0, + Opcode_ae_trunca16p24s_l_encode_fns, 0, 0 }, + { "ae_trunca16p24s.h", ICLASS_AE_TRUNCA16P24S_H, + 0, + Opcode_ae_trunca16p24s_h_encode_fns, 0, 0 }, + { "ae_add32", ICLASS_AE_ADD32, + 0, + Opcode_ae_add32_encode_fns, 0, 0 }, + { "ae_sub32", ICLASS_AE_SUB32, + 0, + Opcode_ae_sub32_encode_fns, 0, 0 }, + { "ae_addsub32", ICLASS_AE_ADDSUB32, + 0, + Opcode_ae_addsub32_encode_fns, 0, 0 }, + { "ae_subadd32", ICLASS_AE_SUBADD32, + 0, + Opcode_ae_subadd32_encode_fns, 0, 0 }, + { "ae_add16", ICLASS_AE_ADD16, + 0, + Opcode_ae_add16_encode_fns, 0, 0 }, + { "ae_sub16", ICLASS_AE_SUB16, + 0, + Opcode_ae_sub16_encode_fns, 0, 0 }, + { "ae_add32_hl_lh", ICLASS_AE_ADD32_HL_LH, + 0, + Opcode_ae_add32_hl_lh_encode_fns, 0, 0 }, + { "ae_addsub32_hl_lh", ICLASS_AE_ADDSUB32_HL_LH, + 0, + Opcode_ae_addsub32_hl_lh_encode_fns, 0, 0 }, + { "ae_neg32", ICLASS_AE_NEG32, + 0, + Opcode_ae_neg32_encode_fns, 0, 0 }, + { "ae_abs32", ICLASS_AE_ABS32, + 0, + Opcode_ae_abs32_encode_fns, 0, 0 }, + { "ae_neg32_l", ICLASS_AE_NEG32_L, + 0, + Opcode_ae_neg32_l_encode_fns, 0, 0 }, + { "ae_add24s", ICLASS_AE_ADD24S, + 0, + Opcode_ae_add24s_encode_fns, 0, 0 }, + { "ae_sub24s", ICLASS_AE_SUB24S, + 0, + Opcode_ae_sub24s_encode_fns, 0, 0 }, + { "ae_add32s", ICLASS_AE_ADD32S, + 0, + Opcode_ae_add32s_encode_fns, 0, 0 }, + { "ae_sub32s", ICLASS_AE_SUB32S, + 0, + Opcode_ae_sub32s_encode_fns, 0, 0 }, + { "ae_addsub32s", ICLASS_AE_ADDSUB32S, + 0, + Opcode_ae_addsub32s_encode_fns, 0, 0 }, + { "ae_subadd32s", ICLASS_AE_SUBADD32S, + 0, + Opcode_ae_subadd32s_encode_fns, 0, 0 }, + { "ae_add16s", ICLASS_AE_ADD16S, + 0, + Opcode_ae_add16s_encode_fns, 0, 0 }, + { "ae_sub16s", ICLASS_AE_SUB16S, + 0, + Opcode_ae_sub16s_encode_fns, 0, 0 }, + { "ae_add32s_hl_lh", ICLASS_AE_ADD32S_HL_LH, + 0, + Opcode_ae_add32s_hl_lh_encode_fns, 0, 0 }, + { "ae_addsub32s_hl_lh", ICLASS_AE_ADDSUB32S_HL_LH, + 0, + Opcode_ae_addsub32s_hl_lh_encode_fns, 0, 0 }, + { "ae_neg24s", ICLASS_AE_NEG24S, + 0, + Opcode_ae_neg24s_encode_fns, 0, 0 }, + { "ae_abs24s", ICLASS_AE_ABS24S, + 0, + Opcode_ae_abs24s_encode_fns, 0, 0 }, + { "ae_neg32s", ICLASS_AE_NEG32S, + 0, + Opcode_ae_neg32s_encode_fns, 0, 0 }, + { "ae_abs32s", ICLASS_AE_ABS32S, + 0, + Opcode_ae_abs32s_encode_fns, 0, 0 }, + { "ae_neg16s", ICLASS_AE_NEG16S, + 0, + Opcode_ae_neg16s_encode_fns, 0, 0 }, + { "ae_abs16s", ICLASS_AE_ABS16S, + 0, + Opcode_ae_abs16s_encode_fns, 0, 0 }, + { "ae_abs16", ICLASS_AE_ABS16, + 0, + Opcode_ae_abs16_encode_fns, 0, 0 }, + { "ae_mulc16js.h", ICLASS_AE_MULC16JS_H, + 0, + Opcode_ae_mulc16js_h_encode_fns, 0, 0 }, + { "ae_mulc16js.l", ICLASS_AE_MULC16JS_L, + 0, + Opcode_ae_mulc16js_l_encode_fns, 0, 0 }, + { "ae_mulac16js.h", ICLASS_AE_MULAC16JS_H, + 0, + Opcode_ae_mulac16js_h_encode_fns, 0, 0 }, + { "ae_mulac16js.l", ICLASS_AE_MULAC16JS_L, + 0, + Opcode_ae_mulac16js_l_encode_fns, 0, 0 }, + { "ae_lt16", ICLASS_AE_LT16, + 0, + Opcode_ae_lt16_encode_fns, 0, 0 }, + { "ae_le16", ICLASS_AE_LE16, + 0, + Opcode_ae_le16_encode_fns, 0, 0 }, + { "ae_eq16", ICLASS_AE_EQ16, + 0, + Opcode_ae_eq16_encode_fns, 0, 0 }, + { "ae_lt32", ICLASS_AE_LT32, + 0, + Opcode_ae_lt32_encode_fns, 0, 0 }, + { "ae_le32", ICLASS_AE_LE32, + 0, + Opcode_ae_le32_encode_fns, 0, 0 }, + { "ae_eq32", ICLASS_AE_EQ32, + 0, + Opcode_ae_eq32_encode_fns, 0, 0 }, + { "ae_min32", ICLASS_AE_MIN32, + 0, + Opcode_ae_min32_encode_fns, 0, 0 }, + { "ae_max32", ICLASS_AE_MAX32, + 0, + Opcode_ae_max32_encode_fns, 0, 0 }, + { "ae_minmax32", ICLASS_AE_MINMAX32, + 0, + Opcode_ae_minmax32_encode_fns, 0, 0 }, + { "ae_minmax16", ICLASS_AE_MINMAX16, + 0, + Opcode_ae_minmax16_encode_fns, 0, 0 }, + { "ae_min16", ICLASS_AE_MIN16, + 0, + Opcode_ae_min16_encode_fns, 0, 0 }, + { "ae_max16", ICLASS_AE_MAX16, + 0, + Opcode_ae_max16_encode_fns, 0, 0 }, + { "ae_add64", ICLASS_AE_ADD64, + 0, + Opcode_ae_add64_encode_fns, 0, 0 }, + { "ae_sub64", ICLASS_AE_SUB64, + 0, + Opcode_ae_sub64_encode_fns, 0, 0 }, + { "ae_neg64", ICLASS_AE_NEG64, + 0, + Opcode_ae_neg64_encode_fns, 0, 0 }, + { "ae_abs64", ICLASS_AE_ABS64, + 0, + Opcode_ae_abs64_encode_fns, 0, 0 }, + { "ae_addsq56s", ICLASS_AE_ADDSQ56S, + 0, + Opcode_ae_addsq56s_encode_fns, 0, 0 }, + { "ae_subsq56s", ICLASS_AE_SUBSQ56S, + 0, + Opcode_ae_subsq56s_encode_fns, 0, 0 }, + { "ae_add64s", ICLASS_AE_ADD64S, + 0, + Opcode_ae_add64s_encode_fns, 0, 0 }, + { "ae_sub64s", ICLASS_AE_SUB64S, + 0, + Opcode_ae_sub64s_encode_fns, 0, 0 }, + { "ae_negsq56s", ICLASS_AE_NEGSQ56S, + 0, + Opcode_ae_negsq56s_encode_fns, 0, 0 }, + { "ae_abssq56s", ICLASS_AE_ABSSQ56S, + 0, + Opcode_ae_abssq56s_encode_fns, 0, 0 }, + { "ae_neg64s", ICLASS_AE_NEG64S, + 0, + Opcode_ae_neg64s_encode_fns, 0, 0 }, + { "ae_abs64s", ICLASS_AE_ABS64S, + 0, + Opcode_ae_abs64s_encode_fns, 0, 0 }, + { "ae_and", ICLASS_AE_AND, + 0, + Opcode_ae_and_encode_fns, 0, 0 }, + { "ae_nand", ICLASS_AE_NAND, + 0, + Opcode_ae_nand_encode_fns, 0, 0 }, + { "ae_or", ICLASS_AE_OR, + 0, + Opcode_ae_or_encode_fns, 0, 0 }, + { "ae_xor", ICLASS_AE_XOR, + 0, + Opcode_ae_xor_encode_fns, 0, 0 }, + { "ae_slai24", ICLASS_AE_SLAI24, + 0, + Opcode_ae_slai24_encode_fns, 0, 0 }, + { "ae_srli24", ICLASS_AE_SRLI24, + 0, + Opcode_ae_srli24_encode_fns, 0, 0 }, + { "ae_srai24", ICLASS_AE_SRAI24, + 0, + Opcode_ae_srai24_encode_fns, 0, 0 }, + { "ae_slas24", ICLASS_AE_SLAS24, + 0, + Opcode_ae_slas24_encode_fns, 0, 0 }, + { "ae_srls24", ICLASS_AE_SRLS24, + 0, + Opcode_ae_srls24_encode_fns, 0, 0 }, + { "ae_sras24", ICLASS_AE_SRAS24, + 0, + Opcode_ae_sras24_encode_fns, 0, 0 }, + { "ae_srai16", ICLASS_AE_SRAI16, + 0, + Opcode_ae_srai16_encode_fns, 0, 0 }, + { "ae_srai16r", ICLASS_AE_SRAI16R, + 0, + Opcode_ae_srai16r_encode_fns, 0, 0 }, + { "ae_slai32", ICLASS_AE_SLAI32, + 0, + Opcode_ae_slai32_encode_fns, 0, 0 }, + { "ae_srli32", ICLASS_AE_SRLI32, + 0, + Opcode_ae_srli32_encode_fns, 0, 0 }, + { "ae_srai32", ICLASS_AE_SRAI32, + 0, + Opcode_ae_srai32_encode_fns, 0, 0 }, + { "ae_srai32r", ICLASS_AE_SRAI32R, + 0, + Opcode_ae_srai32r_encode_fns, 0, 0 }, + { "ae_slas32", ICLASS_AE_SLAS32, + 0, + Opcode_ae_slas32_encode_fns, 0, 0 }, + { "ae_srls32", ICLASS_AE_SRLS32, + 0, + Opcode_ae_srls32_encode_fns, 0, 0 }, + { "ae_sras32", ICLASS_AE_SRAS32, + 0, + Opcode_ae_sras32_encode_fns, 0, 0 }, + { "ae_slaa32", ICLASS_AE_SLAA32, + 0, + Opcode_ae_slaa32_encode_fns, 0, 0 }, + { "ae_srla32", ICLASS_AE_SRLA32, + 0, + Opcode_ae_srla32_encode_fns, 0, 0 }, + { "ae_sraa32", ICLASS_AE_SRAA32, + 0, + Opcode_ae_sraa32_encode_fns, 0, 0 }, + { "ae_slai16s", ICLASS_AE_SLAI16S, + 0, + Opcode_ae_slai16s_encode_fns, 0, 0 }, + { "ae_slaa16s", ICLASS_AE_SLAA16S, + 0, + Opcode_ae_slaa16s_encode_fns, 0, 0 }, + { "ae_sraa16s", ICLASS_AE_SRAA16S, + 0, + Opcode_ae_sraa16s_encode_fns, 0, 0 }, + { "ae_sraa16rs", ICLASS_AE_SRAA16RS, + 0, + Opcode_ae_sraa16rs_encode_fns, 0, 0 }, + { "ae_slai24s", ICLASS_AE_SLAI24S, + 0, + Opcode_ae_slai24s_encode_fns, 0, 0 }, + { "ae_slas24s", ICLASS_AE_SLAS24S, + 0, + Opcode_ae_slas24s_encode_fns, 0, 0 }, + { "ae_slai32s", ICLASS_AE_SLAI32S, + 0, + Opcode_ae_slai32s_encode_fns, 0, 0 }, + { "ae_slas32s", ICLASS_AE_SLAS32S, + 0, + Opcode_ae_slas32s_encode_fns, 0, 0 }, + { "ae_slaa32s", ICLASS_AE_SLAA32S, + 0, + Opcode_ae_slaa32s_encode_fns, 0, 0 }, + { "ae_sraa32s", ICLASS_AE_SRAA32S, + 0, + Opcode_ae_sraa32s_encode_fns, 0, 0 }, + { "ae_sraa32rs", ICLASS_AE_SRAA32RS, + 0, + Opcode_ae_sraa32rs_encode_fns, 0, 0 }, + { "ae_slasq56", ICLASS_AE_SLASQ56, + 0, + Opcode_ae_slasq56_encode_fns, 0, 0 }, + { "ae_srlsq56", ICLASS_AE_SRLSQ56, + 0, + Opcode_ae_srlsq56_encode_fns, 0, 0 }, + { "ae_srasq56", ICLASS_AE_SRASQ56, + 0, + Opcode_ae_srasq56_encode_fns, 0, 0 }, + { "ae_slaaq56", ICLASS_AE_SLAAQ56, + 0, + Opcode_ae_slaaq56_encode_fns, 0, 0 }, + { "ae_srlaq56", ICLASS_AE_SRLAQ56, + 0, + Opcode_ae_srlaq56_encode_fns, 0, 0 }, + { "ae_sraaq56", ICLASS_AE_SRAAQ56, + 0, + Opcode_ae_sraaq56_encode_fns, 0, 0 }, + { "ae_slai64", ICLASS_AE_SLAI64, + 0, + Opcode_ae_slai64_encode_fns, 0, 0 }, + { "ae_srli64", ICLASS_AE_SRLI64, + 0, + Opcode_ae_srli64_encode_fns, 0, 0 }, + { "ae_srai64", ICLASS_AE_SRAI64, + 0, + Opcode_ae_srai64_encode_fns, 0, 0 }, + { "ae_slas64", ICLASS_AE_SLAS64, + 0, + Opcode_ae_slas64_encode_fns, 0, 0 }, + { "ae_srls64", ICLASS_AE_SRLS64, + 0, + Opcode_ae_srls64_encode_fns, 0, 0 }, + { "ae_sras64", ICLASS_AE_SRAS64, + 0, + Opcode_ae_sras64_encode_fns, 0, 0 }, + { "ae_slaa64", ICLASS_AE_SLAA64, + 0, + Opcode_ae_slaa64_encode_fns, 0, 0 }, + { "ae_srla64", ICLASS_AE_SRLA64, + 0, + Opcode_ae_srla64_encode_fns, 0, 0 }, + { "ae_sraa64", ICLASS_AE_SRAA64, + 0, + Opcode_ae_sraa64_encode_fns, 0, 0 }, + { "ae_slaisq56s", ICLASS_AE_SLAISQ56S, + 0, + Opcode_ae_slaisq56s_encode_fns, 0, 0 }, + { "ae_slassq56s", ICLASS_AE_SLASSQ56S, + 0, + Opcode_ae_slassq56s_encode_fns, 0, 0 }, + { "ae_slaasq56s", ICLASS_AE_SLAASQ56S, + 0, + Opcode_ae_slaasq56s_encode_fns, 0, 0 }, + { "ae_slai64s", ICLASS_AE_SLAI64S, + 0, + Opcode_ae_slai64s_encode_fns, 0, 0 }, + { "ae_slas64s", ICLASS_AE_SLAS64S, + 0, + Opcode_ae_slas64s_encode_fns, 0, 0 }, + { "ae_slaa64s", ICLASS_AE_SLAA64S, + 0, + Opcode_ae_slaa64s_encode_fns, 0, 0 }, + { "ae_lt64", ICLASS_AE_LT64, + 0, + Opcode_ae_lt64_encode_fns, 0, 0 }, + { "ae_le64", ICLASS_AE_LE64, + 0, + Opcode_ae_le64_encode_fns, 0, 0 }, + { "ae_eq64", ICLASS_AE_EQ64, + 0, + Opcode_ae_eq64_encode_fns, 0, 0 }, + { "ae_max64", ICLASS_AE_MAX64, + 0, + Opcode_ae_max64_encode_fns, 0, 0 }, + { "ae_min64", ICLASS_AE_MIN64, + 0, + Opcode_ae_min64_encode_fns, 0, 0 }, + { "ae_nsa64", ICLASS_AE_NSA64, + 0, + Opcode_ae_nsa64_encode_fns, 0, 0 }, + { "ae_nsaz16.0", ICLASS_AE_NSAZ16_0, + 0, + Opcode_ae_nsaz16_0_encode_fns, 0, 0 }, + { "ae_nsaz32.l", ICLASS_AE_NSAZ32_L, + 0, + Opcode_ae_nsaz32_l_encode_fns, 0, 0 }, + { "ae_muls32f48p16s.ll", ICLASS_AE_MULS32F48P16S_LL, + 0, + Opcode_ae_muls32f48p16s_ll_encode_fns, 0, 0 }, + { "ae_mulf32s.ll", ICLASS_AE_MULF32S_LL, + 0, + Opcode_ae_mulf32s_ll_encode_fns, 0, 0 }, + { "ae_mul32.ll", ICLASS_AE_MUL32_LL, + 0, + Opcode_ae_mul32_ll_encode_fns, 0, 0 }, + { "ae_mulf32r.ll", ICLASS_AE_MULF32R_LL, + 0, + Opcode_ae_mulf32r_ll_encode_fns, 0, 0 }, + { "ae_mulf32ra.ll", ICLASS_AE_MULF32RA_LL, + 0, + Opcode_ae_mulf32ra_ll_encode_fns, 0, 0 }, + { "ae_muls32f48p16s.lh", ICLASS_AE_MULS32F48P16S_LH, + 0, + Opcode_ae_muls32f48p16s_lh_encode_fns, 0, 0 }, + { "ae_mulf32s.lh", ICLASS_AE_MULF32S_LH, + 0, + Opcode_ae_mulf32s_lh_encode_fns, 0, 0 }, + { "ae_mul32.lh", ICLASS_AE_MUL32_LH, + 0, + Opcode_ae_mul32_lh_encode_fns, 0, 0 }, + { "ae_mulf32r.lh", ICLASS_AE_MULF32R_LH, + 0, + Opcode_ae_mulf32r_lh_encode_fns, 0, 0 }, + { "ae_mulf32ra.lh", ICLASS_AE_MULF32RA_LH, + 0, + Opcode_ae_mulf32ra_lh_encode_fns, 0, 0 }, + { "ae_muls32f48p16s.hh", ICLASS_AE_MULS32F48P16S_HH, + 0, + Opcode_ae_muls32f48p16s_hh_encode_fns, 0, 0 }, + { "ae_mulf32s.hh", ICLASS_AE_MULF32S_HH, + 0, + Opcode_ae_mulf32s_hh_encode_fns, 0, 0 }, + { "ae_mul32.hh", ICLASS_AE_MUL32_HH, + 0, + Opcode_ae_mul32_hh_encode_fns, 0, 0 }, + { "ae_mulf32r.hh", ICLASS_AE_MULF32R_HH, + 0, + Opcode_ae_mulf32r_hh_encode_fns, 0, 0 }, + { "ae_mulf32ra.hh", ICLASS_AE_MULF32RA_HH, + 0, + Opcode_ae_mulf32ra_hh_encode_fns, 0, 0 }, + { "ae_mulas32f48p16s.ll", ICLASS_AE_MULAS32F48P16S_LL, + 0, + Opcode_ae_mulas32f48p16s_ll_encode_fns, 0, 0 }, + { "ae_mulaf32s.ll", ICLASS_AE_MULAF32S_LL, + 0, + Opcode_ae_mulaf32s_ll_encode_fns, 0, 0 }, + { "ae_mula32.ll", ICLASS_AE_MULA32_LL, + 0, + Opcode_ae_mula32_ll_encode_fns, 0, 0 }, + { "ae_mulaf32r.ll", ICLASS_AE_MULAF32R_LL, + 0, + Opcode_ae_mulaf32r_ll_encode_fns, 0, 0 }, + { "ae_mulaf32ra.ll", ICLASS_AE_MULAF32RA_LL, + 0, + Opcode_ae_mulaf32ra_ll_encode_fns, 0, 0 }, + { "ae_mulas32f48p16s.lh", ICLASS_AE_MULAS32F48P16S_LH, + 0, + Opcode_ae_mulas32f48p16s_lh_encode_fns, 0, 0 }, + { "ae_mulaf32s.lh", ICLASS_AE_MULAF32S_LH, + 0, + Opcode_ae_mulaf32s_lh_encode_fns, 0, 0 }, + { "ae_mula32.lh", ICLASS_AE_MULA32_LH, + 0, + Opcode_ae_mula32_lh_encode_fns, 0, 0 }, + { "ae_mulaf32r.lh", ICLASS_AE_MULAF32R_LH, + 0, + Opcode_ae_mulaf32r_lh_encode_fns, 0, 0 }, + { "ae_mulaf32ra.lh", ICLASS_AE_MULAF32RA_LH, + 0, + Opcode_ae_mulaf32ra_lh_encode_fns, 0, 0 }, + { "ae_mulas32f48p16s.hh", ICLASS_AE_MULAS32F48P16S_HH, + 0, + Opcode_ae_mulas32f48p16s_hh_encode_fns, 0, 0 }, + { "ae_mulaf32s.hh", ICLASS_AE_MULAF32S_HH, + 0, + Opcode_ae_mulaf32s_hh_encode_fns, 0, 0 }, + { "ae_mula32.hh", ICLASS_AE_MULA32_HH, + 0, + Opcode_ae_mula32_hh_encode_fns, 0, 0 }, + { "ae_mulaf32r.hh", ICLASS_AE_MULAF32R_HH, + 0, + Opcode_ae_mulaf32r_hh_encode_fns, 0, 0 }, + { "ae_mulaf32ra.hh", ICLASS_AE_MULAF32RA_HH, + 0, + Opcode_ae_mulaf32ra_hh_encode_fns, 0, 0 }, + { "ae_mulss32f48p16s.ll", ICLASS_AE_MULSS32F48P16S_LL, + 0, + Opcode_ae_mulss32f48p16s_ll_encode_fns, 0, 0 }, + { "ae_mulsf32s.ll", ICLASS_AE_MULSF32S_LL, + 0, + Opcode_ae_mulsf32s_ll_encode_fns, 0, 0 }, + { "ae_muls32.ll", ICLASS_AE_MULS32_LL, + 0, + Opcode_ae_muls32_ll_encode_fns, 0, 0 }, + { "ae_mulsf32r.ll", ICLASS_AE_MULSF32R_LL, + 0, + Opcode_ae_mulsf32r_ll_encode_fns, 0, 0 }, + { "ae_mulsf32ra.ll", ICLASS_AE_MULSF32RA_LL, + 0, + Opcode_ae_mulsf32ra_ll_encode_fns, 0, 0 }, + { "ae_mulss32f48p16s.lh", ICLASS_AE_MULSS32F48P16S_LH, + 0, + Opcode_ae_mulss32f48p16s_lh_encode_fns, 0, 0 }, + { "ae_mulsf32s.lh", ICLASS_AE_MULSF32S_LH, + 0, + Opcode_ae_mulsf32s_lh_encode_fns, 0, 0 }, + { "ae_muls32.lh", ICLASS_AE_MULS32_LH, + 0, + Opcode_ae_muls32_lh_encode_fns, 0, 0 }, + { "ae_mulsf32r.lh", ICLASS_AE_MULSF32R_LH, + 0, + Opcode_ae_mulsf32r_lh_encode_fns, 0, 0 }, + { "ae_mulsf32ra.lh", ICLASS_AE_MULSF32RA_LH, + 0, + Opcode_ae_mulsf32ra_lh_encode_fns, 0, 0 }, + { "ae_mulss32f48p16s.hh", ICLASS_AE_MULSS32F48P16S_HH, + 0, + Opcode_ae_mulss32f48p16s_hh_encode_fns, 0, 0 }, + { "ae_mulsf32s.hh", ICLASS_AE_MULSF32S_HH, + 0, + Opcode_ae_mulsf32s_hh_encode_fns, 0, 0 }, + { "ae_muls32.hh", ICLASS_AE_MULS32_HH, + 0, + Opcode_ae_muls32_hh_encode_fns, 0, 0 }, + { "ae_mulsf32r.hh", ICLASS_AE_MULSF32R_HH, + 0, + Opcode_ae_mulsf32r_hh_encode_fns, 0, 0 }, + { "ae_mulsf32ra.hh", ICLASS_AE_MULSF32RA_HH, + 0, + Opcode_ae_mulsf32ra_hh_encode_fns, 0, 0 }, + { "ae_mul32u.ll", ICLASS_AE_MUL32U_LL, + 0, + Opcode_ae_mul32u_ll_encode_fns, 0, 0 }, + { "ae_mula32u.ll", ICLASS_AE_MULA32U_LL, + 0, + Opcode_ae_mula32u_ll_encode_fns, 0, 0 }, + { "ae_muls32u.ll", ICLASS_AE_MULS32U_LL, + 0, + Opcode_ae_muls32u_ll_encode_fns, 0, 0 }, + { "ae_mulf16ss.33", ICLASS_AE_MULF16SS_33, + 0, + Opcode_ae_mulf16ss_33_encode_fns, 0, 0 }, + { "ae_mulf16ss.22", ICLASS_AE_MULF16SS_22, + 0, + Opcode_ae_mulf16ss_22_encode_fns, 0, 0 }, + { "ae_mulf16ss.32", ICLASS_AE_MULF16SS_32, + 0, + Opcode_ae_mulf16ss_32_encode_fns, 0, 0 }, + { "ae_mulf16ss.21", ICLASS_AE_MULF16SS_21, + 0, + Opcode_ae_mulf16ss_21_encode_fns, 0, 0 }, + { "ae_mulf16ss.31", ICLASS_AE_MULF16SS_31, + 0, + Opcode_ae_mulf16ss_31_encode_fns, 0, 0 }, + { "ae_mulf16ss.30", ICLASS_AE_MULF16SS_30, + 0, + Opcode_ae_mulf16ss_30_encode_fns, 0, 0 }, + { "ae_mulf16ss.10", ICLASS_AE_MULF16SS_10, + 0, + Opcode_ae_mulf16ss_10_encode_fns, 0, 0 }, + { "ae_mulf16ss.20", ICLASS_AE_MULF16SS_20, + 0, + Opcode_ae_mulf16ss_20_encode_fns, 0, 0 }, + { "ae_mulf16ss.11", ICLASS_AE_MULF16SS_11, + 0, + Opcode_ae_mulf16ss_11_encode_fns, 0, 0 }, + { "ae_mulf16ss.00", ICLASS_AE_MULF16SS_00, + 0, + Opcode_ae_mulf16ss_00_encode_fns, 0, 0 }, + { "ae_mulsf16ss.33", ICLASS_AE_MULSF16SS_33, + 0, + Opcode_ae_mulsf16ss_33_encode_fns, 0, 0 }, + { "ae_mulsf16ss.22", ICLASS_AE_MULSF16SS_22, + 0, + Opcode_ae_mulsf16ss_22_encode_fns, 0, 0 }, + { "ae_mulsf16ss.32", ICLASS_AE_MULSF16SS_32, + 0, + Opcode_ae_mulsf16ss_32_encode_fns, 0, 0 }, + { "ae_mulsf16ss.21", ICLASS_AE_MULSF16SS_21, + 0, + Opcode_ae_mulsf16ss_21_encode_fns, 0, 0 }, + { "ae_mulsf16ss.31", ICLASS_AE_MULSF16SS_31, + 0, + Opcode_ae_mulsf16ss_31_encode_fns, 0, 0 }, + { "ae_mulsf16ss.30", ICLASS_AE_MULSF16SS_30, + 0, + Opcode_ae_mulsf16ss_30_encode_fns, 0, 0 }, + { "ae_mulsf16ss.10", ICLASS_AE_MULSF16SS_10, + 0, + Opcode_ae_mulsf16ss_10_encode_fns, 0, 0 }, + { "ae_mulsf16ss.20", ICLASS_AE_MULSF16SS_20, + 0, + Opcode_ae_mulsf16ss_20_encode_fns, 0, 0 }, + { "ae_mulsf16ss.11", ICLASS_AE_MULSF16SS_11, + 0, + Opcode_ae_mulsf16ss_11_encode_fns, 0, 0 }, + { "ae_mulsf16ss.00", ICLASS_AE_MULSF16SS_00, + 0, + Opcode_ae_mulsf16ss_00_encode_fns, 0, 0 }, + { "ae_mulaf16ss.33", ICLASS_AE_MULAF16SS_33, + 0, + Opcode_ae_mulaf16ss_33_encode_fns, 0, 0 }, + { "ae_mulaf16ss.22", ICLASS_AE_MULAF16SS_22, + 0, + Opcode_ae_mulaf16ss_22_encode_fns, 0, 0 }, + { "ae_mulaf16ss.32", ICLASS_AE_MULAF16SS_32, + 0, + Opcode_ae_mulaf16ss_32_encode_fns, 0, 0 }, + { "ae_mulaf16ss.21", ICLASS_AE_MULAF16SS_21, + 0, + Opcode_ae_mulaf16ss_21_encode_fns, 0, 0 }, + { "ae_mulaf16ss.31", ICLASS_AE_MULAF16SS_31, + 0, + Opcode_ae_mulaf16ss_31_encode_fns, 0, 0 }, + { "ae_mulaf16ss.30", ICLASS_AE_MULAF16SS_30, + 0, + Opcode_ae_mulaf16ss_30_encode_fns, 0, 0 }, + { "ae_mulaf16ss.10", ICLASS_AE_MULAF16SS_10, + 0, + Opcode_ae_mulaf16ss_10_encode_fns, 0, 0 }, + { "ae_mulaf16ss.20", ICLASS_AE_MULAF16SS_20, + 0, + Opcode_ae_mulaf16ss_20_encode_fns, 0, 0 }, + { "ae_mulaf16ss.11", ICLASS_AE_MULAF16SS_11, + 0, + Opcode_ae_mulaf16ss_11_encode_fns, 0, 0 }, + { "ae_mulaf16ss.00", ICLASS_AE_MULAF16SS_00, + 0, + Opcode_ae_mulaf16ss_00_encode_fns, 0, 0 }, + { "ae_mul16s.00", ICLASS_AE_MUL16S_00, + 0, + Opcode_ae_mul16s_00_encode_fns, 0, 0 }, + { "ae_mula16s.00", ICLASS_AE_MULA16S_00, + 0, + Opcode_ae_mula16s_00_encode_fns, 0, 0 }, + { "ae_muls16s.00", ICLASS_AE_MULS16S_00, + 0, + Opcode_ae_muls16s_00_encode_fns, 0, 0 }, + { "ae_mulaafd16ss.33_22", ICLASS_AE_MULAAFD16SS_33_22, + 0, + Opcode_ae_mulaafd16ss_33_22_encode_fns, 0, 0 }, + { "ae_mulaafd16ss.13_02", ICLASS_AE_MULAAFD16SS_13_02, + 0, + Opcode_ae_mulaafd16ss_13_02_encode_fns, 0, 0 }, + { "ae_mulaafd16ss.11_00", ICLASS_AE_MULAAFD16SS_11_00, + 0, + Opcode_ae_mulaafd16ss_11_00_encode_fns, 0, 0 }, + { "ae_mulssfd16ss.33_22", ICLASS_AE_MULSSFD16SS_33_22, + 0, + Opcode_ae_mulssfd16ss_33_22_encode_fns, 0, 0 }, + { "ae_mulssfd16ss.13_02", ICLASS_AE_MULSSFD16SS_13_02, + 0, + Opcode_ae_mulssfd16ss_13_02_encode_fns, 0, 0 }, + { "ae_mulssfd16ss.11_00", ICLASS_AE_MULSSFD16SS_11_00, + 0, + Opcode_ae_mulssfd16ss_11_00_encode_fns, 0, 0 }, + { "ae_mulzaafd16ss.33_22", ICLASS_AE_MULZAAFD16SS_33_22, + 0, + Opcode_ae_mulzaafd16ss_33_22_encode_fns, 0, 0 }, + { "ae_mulzaafd16ss.13_02", ICLASS_AE_MULZAAFD16SS_13_02, + 0, + Opcode_ae_mulzaafd16ss_13_02_encode_fns, 0, 0 }, + { "ae_mulzaafd16ss.11_00", ICLASS_AE_MULZAAFD16SS_11_00, + 0, + Opcode_ae_mulzaafd16ss_11_00_encode_fns, 0, 0 }, + { "ae_mulzssfd16ss.33_22", ICLASS_AE_MULZSSFD16SS_33_22, + 0, + Opcode_ae_mulzssfd16ss_33_22_encode_fns, 0, 0 }, + { "ae_mulzssfd16ss.13_02", ICLASS_AE_MULZSSFD16SS_13_02, + 0, + Opcode_ae_mulzssfd16ss_13_02_encode_fns, 0, 0 }, + { "ae_mulzssfd16ss.11_00", ICLASS_AE_MULZSSFD16SS_11_00, + 0, + Opcode_ae_mulzssfd16ss_11_00_encode_fns, 0, 0 }, + { "ae_mulf48q32sp16s.l", ICLASS_AE_MULF48Q32SP16S_L, + 0, + Opcode_ae_mulf48q32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulf48q32sp16u.l", ICLASS_AE_MULF48Q32SP16U_L, + 0, + Opcode_ae_mulf48q32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulq32sp16s.l", ICLASS_AE_MULQ32SP16S_L, + 0, + Opcode_ae_mulq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulq32sp16u.l", ICLASS_AE_MULQ32SP16U_L, + 0, + Opcode_ae_mulq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulaf48q32sp16s.l", ICLASS_AE_MULAF48Q32SP16S_L, + 0, + Opcode_ae_mulaf48q32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulaf48q32sp16u.l", ICLASS_AE_MULAF48Q32SP16U_L, + 0, + Opcode_ae_mulaf48q32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulaq32sp16s.l", ICLASS_AE_MULAQ32SP16S_L, + 0, + Opcode_ae_mulaq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulaq32sp16u.l", ICLASS_AE_MULAQ32SP16U_L, + 0, + Opcode_ae_mulaq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulsf48q32sp16s.l", ICLASS_AE_MULSF48Q32SP16S_L, + 0, + Opcode_ae_mulsf48q32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulsf48q32sp16u.l", ICLASS_AE_MULSF48Q32SP16U_L, + 0, + Opcode_ae_mulsf48q32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulsq32sp16s.l", ICLASS_AE_MULSQ32SP16S_L, + 0, + Opcode_ae_mulsq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulsq32sp16u.l", ICLASS_AE_MULSQ32SP16U_L, + 0, + Opcode_ae_mulsq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulfp24x2ra", ICLASS_AE_MULFP24X2RA, + 0, + Opcode_ae_mulfp24x2ra_encode_fns, 0, 0 }, + { "ae_mulfp24x2r", ICLASS_AE_MULFP24X2R, + 0, + Opcode_ae_mulfp24x2r_encode_fns, 0, 0 }, + { "ae_mulafp24x2ra", ICLASS_AE_MULAFP24X2RA, + 0, + Opcode_ae_mulafp24x2ra_encode_fns, 0, 0 }, + { "ae_mulafp24x2r", ICLASS_AE_MULAFP24X2R, + 0, + Opcode_ae_mulafp24x2r_encode_fns, 0, 0 }, + { "ae_mulsfp24x2ra", ICLASS_AE_MULSFP24X2RA, + 0, + Opcode_ae_mulsfp24x2ra_encode_fns, 0, 0 }, + { "ae_mulsfp24x2r", ICLASS_AE_MULSFP24X2R, + 0, + Opcode_ae_mulsfp24x2r_encode_fns, 0, 0 }, + { "ae_mulzaafd32s.hh.ll", ICLASS_AE_MULZAAFD32S_HH_LL, + 0, + Opcode_ae_mulzaafd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaafd32ra.hh.ll", ICLASS_AE_MULZAAFD32RA_HH_LL, + 0, + Opcode_ae_mulzaafd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaad32.hh.ll", ICLASS_AE_MULZAAD32_HH_LL, + 0, + Opcode_ae_mulzaad32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaafd32s.hl.lh", ICLASS_AE_MULZAAFD32S_HL_LH, + 0, + Opcode_ae_mulzaafd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaafd32ra.hl.lh", ICLASS_AE_MULZAAFD32RA_HL_LH, + 0, + Opcode_ae_mulzaafd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaad32.hl.lh", ICLASS_AE_MULZAAD32_HL_LH, + 0, + Opcode_ae_mulzaad32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasfd32s.hh.ll", ICLASS_AE_MULZASFD32S_HH_LL, + 0, + Opcode_ae_mulzasfd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasfd32ra.hh.ll", ICLASS_AE_MULZASFD32RA_HH_LL, + 0, + Opcode_ae_mulzasfd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasd32.hh.ll", ICLASS_AE_MULZASD32_HH_LL, + 0, + Opcode_ae_mulzasd32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasfd32s.hl.lh", ICLASS_AE_MULZASFD32S_HL_LH, + 0, + Opcode_ae_mulzasfd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasfd32ra.hl.lh", ICLASS_AE_MULZASFD32RA_HL_LH, + 0, + Opcode_ae_mulzasfd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasd32.hl.lh", ICLASS_AE_MULZASD32_HL_LH, + 0, + Opcode_ae_mulzasd32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzsafd32s.hh.ll", ICLASS_AE_MULZSAFD32S_HH_LL, + 0, + Opcode_ae_mulzsafd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsafd32ra.hh.ll", ICLASS_AE_MULZSAFD32RA_HH_LL, + 0, + Opcode_ae_mulzsafd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsad32.hh.ll", ICLASS_AE_MULZSAD32_HH_LL, + 0, + Opcode_ae_mulzsad32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssfd32s.hh.ll", ICLASS_AE_MULZSSFD32S_HH_LL, + 0, + Opcode_ae_mulzssfd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssfd32ra.hh.ll", ICLASS_AE_MULZSSFD32RA_HH_LL, + 0, + Opcode_ae_mulzssfd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssd32.hh.ll", ICLASS_AE_MULZSSD32_HH_LL, + 0, + Opcode_ae_mulzssd32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssfd32s.hl.lh", ICLASS_AE_MULZSSFD32S_HL_LH, + 0, + Opcode_ae_mulzssfd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssfd32ra.hl.lh", ICLASS_AE_MULZSSFD32RA_HL_LH, + 0, + Opcode_ae_mulzssfd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssd32.hl.lh", ICLASS_AE_MULZSSD32_HL_LH, + 0, + Opcode_ae_mulzssd32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaafd32s.hh.ll", ICLASS_AE_MULAAFD32S_HH_LL, + 0, + Opcode_ae_mulaafd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaafd32ra.hh.ll", ICLASS_AE_MULAAFD32RA_HH_LL, + 0, + Opcode_ae_mulaafd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaad32.hh.ll", ICLASS_AE_MULAAD32_HH_LL, + 0, + Opcode_ae_mulaad32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaafd32s.hl.lh", ICLASS_AE_MULAAFD32S_HL_LH, + 0, + Opcode_ae_mulaafd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaafd32ra.hl.lh", ICLASS_AE_MULAAFD32RA_HL_LH, + 0, + Opcode_ae_mulaafd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaad32.hl.lh", ICLASS_AE_MULAAD32_HL_LH, + 0, + Opcode_ae_mulaad32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasfd32s.hh.ll", ICLASS_AE_MULASFD32S_HH_LL, + 0, + Opcode_ae_mulasfd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasfd32ra.hh.ll", ICLASS_AE_MULASFD32RA_HH_LL, + 0, + Opcode_ae_mulasfd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasd32.hh.ll", ICLASS_AE_MULASD32_HH_LL, + 0, + Opcode_ae_mulasd32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasfd32s.hl.lh", ICLASS_AE_MULASFD32S_HL_LH, + 0, + Opcode_ae_mulasfd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasfd32ra.hl.lh", ICLASS_AE_MULASFD32RA_HL_LH, + 0, + Opcode_ae_mulasfd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasd32.hl.lh", ICLASS_AE_MULASD32_HL_LH, + 0, + Opcode_ae_mulasd32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsafd32s.hh.ll", ICLASS_AE_MULSAFD32S_HH_LL, + 0, + Opcode_ae_mulsafd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsafd32ra.hh.ll", ICLASS_AE_MULSAFD32RA_HH_LL, + 0, + Opcode_ae_mulsafd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsad32.hh.ll", ICLASS_AE_MULSAD32_HH_LL, + 0, + Opcode_ae_mulsad32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssfd32s.hh.ll", ICLASS_AE_MULSSFD32S_HH_LL, + 0, + Opcode_ae_mulssfd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssfd32ra.hh.ll", ICLASS_AE_MULSSFD32RA_HH_LL, + 0, + Opcode_ae_mulssfd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssd32.hh.ll", ICLASS_AE_MULSSD32_HH_LL, + 0, + Opcode_ae_mulssd32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssfd32s.hl.lh", ICLASS_AE_MULSSFD32S_HL_LH, + 0, + Opcode_ae_mulssfd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssfd32ra.hl.lh", ICLASS_AE_MULSSFD32RA_HL_LH, + 0, + Opcode_ae_mulssfd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssd32.hl.lh", ICLASS_AE_MULSSD32_HL_LH, + 0, + Opcode_ae_mulssd32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulf32x16.l0", ICLASS_AE_MULF32X16_L0, + 0, + Opcode_ae_mulf32x16_l0_encode_fns, 0, 0 }, + { "ae_mul32x16.l0", ICLASS_AE_MUL32X16_L0, + 0, + Opcode_ae_mul32x16_l0_encode_fns, 0, 0 }, + { "ae_mulf32x16.l1", ICLASS_AE_MULF32X16_L1, + 0, + Opcode_ae_mulf32x16_l1_encode_fns, 0, 0 }, + { "ae_mul32x16.l1", ICLASS_AE_MUL32X16_L1, + 0, + Opcode_ae_mul32x16_l1_encode_fns, 0, 0 }, + { "ae_mulf32x16.l2", ICLASS_AE_MULF32X16_L2, + 0, + Opcode_ae_mulf32x16_l2_encode_fns, 0, 0 }, + { "ae_mul32x16.l2", ICLASS_AE_MUL32X16_L2, + 0, + Opcode_ae_mul32x16_l2_encode_fns, 0, 0 }, + { "ae_mulf32x16.l3", ICLASS_AE_MULF32X16_L3, + 0, + Opcode_ae_mulf32x16_l3_encode_fns, 0, 0 }, + { "ae_mul32x16.l3", ICLASS_AE_MUL32X16_L3, + 0, + Opcode_ae_mul32x16_l3_encode_fns, 0, 0 }, + { "ae_mulf32x16.h0", ICLASS_AE_MULF32X16_H0, + 0, + Opcode_ae_mulf32x16_h0_encode_fns, 0, 0 }, + { "ae_mul32x16.h0", ICLASS_AE_MUL32X16_H0, + 0, + Opcode_ae_mul32x16_h0_encode_fns, 0, 0 }, + { "ae_mulf32x16.h1", ICLASS_AE_MULF32X16_H1, + 0, + Opcode_ae_mulf32x16_h1_encode_fns, 0, 0 }, + { "ae_mul32x16.h1", ICLASS_AE_MUL32X16_H1, + 0, + Opcode_ae_mul32x16_h1_encode_fns, 0, 0 }, + { "ae_mulf32x16.h2", ICLASS_AE_MULF32X16_H2, + 0, + Opcode_ae_mulf32x16_h2_encode_fns, 0, 0 }, + { "ae_mul32x16.h2", ICLASS_AE_MUL32X16_H2, + 0, + Opcode_ae_mul32x16_h2_encode_fns, 0, 0 }, + { "ae_mulf32x16.h3", ICLASS_AE_MULF32X16_H3, + 0, + Opcode_ae_mulf32x16_h3_encode_fns, 0, 0 }, + { "ae_mul32x16.h3", ICLASS_AE_MUL32X16_H3, + 0, + Opcode_ae_mul32x16_h3_encode_fns, 0, 0 }, + { "ae_mulaf32x16.l0", ICLASS_AE_MULAF32X16_L0, + 0, + Opcode_ae_mulaf32x16_l0_encode_fns, 0, 0 }, + { "ae_mula32x16.l0", ICLASS_AE_MULA32X16_L0, + 0, + Opcode_ae_mula32x16_l0_encode_fns, 0, 0 }, + { "ae_mulaf32x16.l1", ICLASS_AE_MULAF32X16_L1, + 0, + Opcode_ae_mulaf32x16_l1_encode_fns, 0, 0 }, + { "ae_mula32x16.l1", ICLASS_AE_MULA32X16_L1, + 0, + Opcode_ae_mula32x16_l1_encode_fns, 0, 0 }, + { "ae_mulaf32x16.l2", ICLASS_AE_MULAF32X16_L2, + 0, + Opcode_ae_mulaf32x16_l2_encode_fns, 0, 0 }, + { "ae_mula32x16.l2", ICLASS_AE_MULA32X16_L2, + 0, + Opcode_ae_mula32x16_l2_encode_fns, 0, 0 }, + { "ae_mulaf32x16.l3", ICLASS_AE_MULAF32X16_L3, + 0, + Opcode_ae_mulaf32x16_l3_encode_fns, 0, 0 }, + { "ae_mula32x16.l3", ICLASS_AE_MULA32X16_L3, + 0, + Opcode_ae_mula32x16_l3_encode_fns, 0, 0 }, + { "ae_mulaf32x16.h0", ICLASS_AE_MULAF32X16_H0, + 0, + Opcode_ae_mulaf32x16_h0_encode_fns, 0, 0 }, + { "ae_mula32x16.h0", ICLASS_AE_MULA32X16_H0, + 0, + Opcode_ae_mula32x16_h0_encode_fns, 0, 0 }, + { "ae_mulaf32x16.h1", ICLASS_AE_MULAF32X16_H1, + 0, + Opcode_ae_mulaf32x16_h1_encode_fns, 0, 0 }, + { "ae_mula32x16.h1", ICLASS_AE_MULA32X16_H1, + 0, + Opcode_ae_mula32x16_h1_encode_fns, 0, 0 }, + { "ae_mulaf32x16.h2", ICLASS_AE_MULAF32X16_H2, + 0, + Opcode_ae_mulaf32x16_h2_encode_fns, 0, 0 }, + { "ae_mula32x16.h2", ICLASS_AE_MULA32X16_H2, + 0, + Opcode_ae_mula32x16_h2_encode_fns, 0, 0 }, + { "ae_mulaf32x16.h3", ICLASS_AE_MULAF32X16_H3, + 0, + Opcode_ae_mulaf32x16_h3_encode_fns, 0, 0 }, + { "ae_mula32x16.h3", ICLASS_AE_MULA32X16_H3, + 0, + Opcode_ae_mula32x16_h3_encode_fns, 0, 0 }, + { "ae_mulsf32x16.l0", ICLASS_AE_MULSF32X16_L0, + 0, + Opcode_ae_mulsf32x16_l0_encode_fns, 0, 0 }, + { "ae_muls32x16.l0", ICLASS_AE_MULS32X16_L0, + 0, + Opcode_ae_muls32x16_l0_encode_fns, 0, 0 }, + { "ae_mulsf32x16.l1", ICLASS_AE_MULSF32X16_L1, + 0, + Opcode_ae_mulsf32x16_l1_encode_fns, 0, 0 }, + { "ae_muls32x16.l1", ICLASS_AE_MULS32X16_L1, + 0, + Opcode_ae_muls32x16_l1_encode_fns, 0, 0 }, + { "ae_mulsf32x16.l2", ICLASS_AE_MULSF32X16_L2, + 0, + Opcode_ae_mulsf32x16_l2_encode_fns, 0, 0 }, + { "ae_muls32x16.l2", ICLASS_AE_MULS32X16_L2, + 0, + Opcode_ae_muls32x16_l2_encode_fns, 0, 0 }, + { "ae_mulsf32x16.l3", ICLASS_AE_MULSF32X16_L3, + 0, + Opcode_ae_mulsf32x16_l3_encode_fns, 0, 0 }, + { "ae_muls32x16.l3", ICLASS_AE_MULS32X16_L3, + 0, + Opcode_ae_muls32x16_l3_encode_fns, 0, 0 }, + { "ae_mulsf32x16.h0", ICLASS_AE_MULSF32X16_H0, + 0, + Opcode_ae_mulsf32x16_h0_encode_fns, 0, 0 }, + { "ae_muls32x16.h0", ICLASS_AE_MULS32X16_H0, + 0, + Opcode_ae_muls32x16_h0_encode_fns, 0, 0 }, + { "ae_mulsf32x16.h1", ICLASS_AE_MULSF32X16_H1, + 0, + Opcode_ae_mulsf32x16_h1_encode_fns, 0, 0 }, + { "ae_muls32x16.h1", ICLASS_AE_MULS32X16_H1, + 0, + Opcode_ae_muls32x16_h1_encode_fns, 0, 0 }, + { "ae_mulsf32x16.h2", ICLASS_AE_MULSF32X16_H2, + 0, + Opcode_ae_mulsf32x16_h2_encode_fns, 0, 0 }, + { "ae_muls32x16.h2", ICLASS_AE_MULS32X16_H2, + 0, + Opcode_ae_muls32x16_h2_encode_fns, 0, 0 }, + { "ae_mulsf32x16.h3", ICLASS_AE_MULSF32X16_H3, + 0, + Opcode_ae_mulsf32x16_h3_encode_fns, 0, 0 }, + { "ae_muls32x16.h3", ICLASS_AE_MULS32X16_H3, + 0, + Opcode_ae_muls32x16_h3_encode_fns, 0, 0 }, + { "ae_mulaafd32x16.h3.l2", ICLASS_AE_MULAAFD32X16_H3_L2, + 0, + Opcode_ae_mulaafd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulaad32x16.h3.l2", ICLASS_AE_MULAAD32X16_H3_L2, + 0, + Opcode_ae_mulaad32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulaafd32x16.h1.l0", ICLASS_AE_MULAAFD32X16_H1_L0, + 0, + Opcode_ae_mulaafd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulaad32x16.h1.l0", ICLASS_AE_MULAAD32X16_H1_L0, + 0, + Opcode_ae_mulaad32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulasfd32x16.h3.l2", ICLASS_AE_MULASFD32X16_H3_L2, + 0, + Opcode_ae_mulasfd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulasd32x16.h3.l2", ICLASS_AE_MULASD32X16_H3_L2, + 0, + Opcode_ae_mulasd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulasfd32x16.h1.l0", ICLASS_AE_MULASFD32X16_H1_L0, + 0, + Opcode_ae_mulasfd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulasd32x16.h1.l0", ICLASS_AE_MULASD32X16_H1_L0, + 0, + Opcode_ae_mulasd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulsafd32x16.h3.l2", ICLASS_AE_MULSAFD32X16_H3_L2, + 0, + Opcode_ae_mulsafd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulsad32x16.h3.l2", ICLASS_AE_MULSAD32X16_H3_L2, + 0, + Opcode_ae_mulsad32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulsafd32x16.h1.l0", ICLASS_AE_MULSAFD32X16_H1_L0, + 0, + Opcode_ae_mulsafd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulsad32x16.h1.l0", ICLASS_AE_MULSAD32X16_H1_L0, + 0, + Opcode_ae_mulsad32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulssfd32x16.h3.l2", ICLASS_AE_MULSSFD32X16_H3_L2, + 0, + Opcode_ae_mulssfd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulssd32x16.h3.l2", ICLASS_AE_MULSSD32X16_H3_L2, + 0, + Opcode_ae_mulssd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulssfd32x16.h1.l0", ICLASS_AE_MULSSFD32X16_H1_L0, + 0, + Opcode_ae_mulssfd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulssd32x16.h1.l0", ICLASS_AE_MULSSD32X16_H1_L0, + 0, + Opcode_ae_mulssd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzaafd32x16.h3.l2", ICLASS_AE_MULZAAFD32X16_H3_L2, + 0, + Opcode_ae_mulzaafd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzaad32x16.h3.l2", ICLASS_AE_MULZAAD32X16_H3_L2, + 0, + Opcode_ae_mulzaad32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzaafd32x16.h1.l0", ICLASS_AE_MULZAAFD32X16_H1_L0, + 0, + Opcode_ae_mulzaafd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzaad32x16.h1.l0", ICLASS_AE_MULZAAD32X16_H1_L0, + 0, + Opcode_ae_mulzaad32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzasfd32x16.h3.l2", ICLASS_AE_MULZASFD32X16_H3_L2, + 0, + Opcode_ae_mulzasfd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzasd32x16.h3.l2", ICLASS_AE_MULZASD32X16_H3_L2, + 0, + Opcode_ae_mulzasd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzasfd32x16.h1.l0", ICLASS_AE_MULZASFD32X16_H1_L0, + 0, + Opcode_ae_mulzasfd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzasd32x16.h1.l0", ICLASS_AE_MULZASD32X16_H1_L0, + 0, + Opcode_ae_mulzasd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzsafd32x16.h3.l2", ICLASS_AE_MULZSAFD32X16_H3_L2, + 0, + Opcode_ae_mulzsafd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzsad32x16.h3.l2", ICLASS_AE_MULZSAD32X16_H3_L2, + 0, + Opcode_ae_mulzsad32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzsafd32x16.h1.l0", ICLASS_AE_MULZSAFD32X16_H1_L0, + 0, + Opcode_ae_mulzsafd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzsad32x16.h1.l0", ICLASS_AE_MULZSAD32X16_H1_L0, + 0, + Opcode_ae_mulzsad32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzssfd32x16.h3.l2", ICLASS_AE_MULZSSFD32X16_H3_L2, + 0, + Opcode_ae_mulzssfd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzssd32x16.h3.l2", ICLASS_AE_MULZSSD32X16_H3_L2, + 0, + Opcode_ae_mulzssd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzssfd32x16.h1.l0", ICLASS_AE_MULZSSFD32X16_H1_L0, + 0, + Opcode_ae_mulzssfd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzssd32x16.h1.l0", ICLASS_AE_MULZSSD32X16_H1_L0, + 0, + Opcode_ae_mulzssd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzaafd32x16.h2.l3", ICLASS_AE_MULZAAFD32X16_H2_L3, + 0, + Opcode_ae_mulzaafd32x16_h2_l3_encode_fns, 0, 0 }, + { "ae_mulzaafd32x16.h0.l1", ICLASS_AE_MULZAAFD32X16_H0_L1, + 0, + Opcode_ae_mulzaafd32x16_h0_l1_encode_fns, 0, 0 }, + { "ae_mulaafd32x16.h2.l3", ICLASS_AE_MULAAFD32X16_H2_L3, + 0, + Opcode_ae_mulaafd32x16_h2_l3_encode_fns, 0, 0 }, + { "ae_mulaafd32x16.h0.l1", ICLASS_AE_MULAAFD32X16_H0_L1, + 0, + Opcode_ae_mulaafd32x16_h0_l1_encode_fns, 0, 0 }, + { "ae_mulzaad32x16.h2.l3", ICLASS_AE_MULZAAD32X16_H2_L3, + 0, + Opcode_ae_mulzaad32x16_h2_l3_encode_fns, 0, 0 }, + { "ae_mulzaad32x16.h0.l1", ICLASS_AE_MULZAAD32X16_H0_L1, + 0, + Opcode_ae_mulzaad32x16_h0_l1_encode_fns, 0, 0 }, + { "ae_mulaad32x16.h2.l3", ICLASS_AE_MULAAD32X16_H2_L3, + 0, + Opcode_ae_mulaad32x16_h2_l3_encode_fns, 0, 0 }, + { "ae_mulaad32x16.h0.l1", ICLASS_AE_MULAAD32X16_H0_L1, + 0, + Opcode_ae_mulaad32x16_h0_l1_encode_fns, 0, 0 }, + { "ae_mulp32x16x2.h", ICLASS_AE_MULP32X16X2_H, + 0, + Opcode_ae_mulp32x16x2_h_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2rs.h", ICLASS_AE_MULFP32X16X2RS_H, + 0, + Opcode_ae_mulfp32x16x2rs_h_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2ras.h", ICLASS_AE_MULFP32X16X2RAS_H, + 0, + Opcode_ae_mulfp32x16x2ras_h_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2s.h", ICLASS_AE_MULFP32X16X2S_H, + 0, + Opcode_ae_mulfp32x16x2s_h_encode_fns, 0, 0 }, + { "ae_mulp32x16x2.l", ICLASS_AE_MULP32X16X2_L, + 0, + Opcode_ae_mulp32x16x2_l_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2rs.l", ICLASS_AE_MULFP32X16X2RS_L, + 0, + Opcode_ae_mulfp32x16x2rs_l_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2ras.l", ICLASS_AE_MULFP32X16X2RAS_L, + 0, + Opcode_ae_mulfp32x16x2ras_l_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2s.l", ICLASS_AE_MULFP32X16X2S_L, + 0, + Opcode_ae_mulfp32x16x2s_l_encode_fns, 0, 0 }, + { "ae_mulap32x16x2.h", ICLASS_AE_MULAP32X16X2_H, + 0, + Opcode_ae_mulap32x16x2_h_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2rs.h", ICLASS_AE_MULAFP32X16X2RS_H, + 0, + Opcode_ae_mulafp32x16x2rs_h_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2ras.h", ICLASS_AE_MULAFP32X16X2RAS_H, + 0, + Opcode_ae_mulafp32x16x2ras_h_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2s.h", ICLASS_AE_MULAFP32X16X2S_H, + 0, + Opcode_ae_mulafp32x16x2s_h_encode_fns, 0, 0 }, + { "ae_mulap32x16x2.l", ICLASS_AE_MULAP32X16X2_L, + 0, + Opcode_ae_mulap32x16x2_l_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2rs.l", ICLASS_AE_MULAFP32X16X2RS_L, + 0, + Opcode_ae_mulafp32x16x2rs_l_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2ras.l", ICLASS_AE_MULAFP32X16X2RAS_L, + 0, + Opcode_ae_mulafp32x16x2ras_l_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2s.l", ICLASS_AE_MULAFP32X16X2S_L, + 0, + Opcode_ae_mulafp32x16x2s_l_encode_fns, 0, 0 }, + { "ae_mulsp32x16x2.h", ICLASS_AE_MULSP32X16X2_H, + 0, + Opcode_ae_mulsp32x16x2_h_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2rs.h", ICLASS_AE_MULSFP32X16X2RS_H, + 0, + Opcode_ae_mulsfp32x16x2rs_h_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2ras.h", ICLASS_AE_MULSFP32X16X2RAS_H, + 0, + Opcode_ae_mulsfp32x16x2ras_h_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2s.h", ICLASS_AE_MULSFP32X16X2S_H, + 0, + Opcode_ae_mulsfp32x16x2s_h_encode_fns, 0, 0 }, + { "ae_mulsp32x16x2.l", ICLASS_AE_MULSP32X16X2_L, + 0, + Opcode_ae_mulsp32x16x2_l_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2rs.l", ICLASS_AE_MULSFP32X16X2RS_L, + 0, + Opcode_ae_mulsfp32x16x2rs_l_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2ras.l", ICLASS_AE_MULSFP32X16X2RAS_L, + 0, + Opcode_ae_mulsfp32x16x2ras_l_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2s.l", ICLASS_AE_MULSFP32X16X2S_L, + 0, + Opcode_ae_mulsfp32x16x2s_l_encode_fns, 0, 0 }, + { "ae_mulp32x2", ICLASS_AE_MULP32X2, + 0, + Opcode_ae_mulp32x2_encode_fns, 0, 0 }, + { "ae_mulfp32x2rs", ICLASS_AE_MULFP32X2RS, + 0, + Opcode_ae_mulfp32x2rs_encode_fns, 0, 0 }, + { "ae_mulfp32x2ras", ICLASS_AE_MULFP32X2RAS, + 0, + Opcode_ae_mulfp32x2ras_encode_fns, 0, 0 }, + { "ae_mulfp32x2ts", ICLASS_AE_MULFP32X2TS, + 0, + Opcode_ae_mulfp32x2ts_encode_fns, 0, 0 }, + { "ae_mulp32x2t", ICLASS_AE_MULP32X2T, + 0, + Opcode_ae_mulp32x2t_encode_fns, 0, 0 }, + { "ae_mulap32x2", ICLASS_AE_MULAP32X2, + 0, + Opcode_ae_mulap32x2_encode_fns, 0, 0 }, + { "ae_mulafp32x2rs", ICLASS_AE_MULAFP32X2RS, + 0, + Opcode_ae_mulafp32x2rs_encode_fns, 0, 0 }, + { "ae_mulafp32x2ras", ICLASS_AE_MULAFP32X2RAS, + 0, + Opcode_ae_mulafp32x2ras_encode_fns, 0, 0 }, + { "ae_mulafp32x2ts", ICLASS_AE_MULAFP32X2TS, + 0, + Opcode_ae_mulafp32x2ts_encode_fns, 0, 0 }, + { "ae_mulap32x2t", ICLASS_AE_MULAP32X2T, + 0, + Opcode_ae_mulap32x2t_encode_fns, 0, 0 }, + { "ae_mulsp32x2", ICLASS_AE_MULSP32X2, + 0, + Opcode_ae_mulsp32x2_encode_fns, 0, 0 }, + { "ae_mulsfp32x2rs", ICLASS_AE_MULSFP32X2RS, + 0, + Opcode_ae_mulsfp32x2rs_encode_fns, 0, 0 }, + { "ae_mulsfp32x2ras", ICLASS_AE_MULSFP32X2RAS, + 0, + Opcode_ae_mulsfp32x2ras_encode_fns, 0, 0 }, + { "ae_mulsfp32x2ts", ICLASS_AE_MULSFP32X2TS, + 0, + Opcode_ae_mulsfp32x2ts_encode_fns, 0, 0 }, + { "ae_mulsp32x2t", ICLASS_AE_MULSP32X2T, + 0, + Opcode_ae_mulsp32x2t_encode_fns, 0, 0 }, + { "ae_mulfp16x4s", ICLASS_AE_MULFP16X4S, + 0, + Opcode_ae_mulfp16x4s_encode_fns, 0, 0 }, + { "ae_mulfp16x4ras", ICLASS_AE_MULFP16X4RAS, + 0, + Opcode_ae_mulfp16x4ras_encode_fns, 0, 0 }, + { "ae_mulc32", ICLASS_AE_MULC32, + 0, + Opcode_ae_mulc32_encode_fns, 0, 0 }, + { "ae_mulfc24ra", ICLASS_AE_MULFC24RA, + 0, + Opcode_ae_mulfc24ra_encode_fns, 0, 0 }, + { "ae_mulfc32ras", ICLASS_AE_MULFC32RAS, + 0, + Opcode_ae_mulfc32ras_encode_fns, 0, 0 }, + { "ae_mulc32x16.l", ICLASS_AE_MULC32X16_L, + 0, + Opcode_ae_mulc32x16_l_encode_fns, 0, 0 }, + { "ae_mulfc32x16ras.l", ICLASS_AE_MULFC32X16RAS_L, + 0, + Opcode_ae_mulfc32x16ras_l_encode_fns, 0, 0 }, + { "ae_mulc32x16.h", ICLASS_AE_MULC32X16_H, + 0, + Opcode_ae_mulc32x16_h_encode_fns, 0, 0 }, + { "ae_mulfc32x16ras.h", ICLASS_AE_MULFC32X16RAS_H, + 0, + Opcode_ae_mulfc32x16ras_h_encode_fns, 0, 0 }, + { "ae_mulac32", ICLASS_AE_MULAC32, + 0, + Opcode_ae_mulac32_encode_fns, 0, 0 }, + { "ae_mulafc24ra", ICLASS_AE_MULAFC24RA, + 0, + Opcode_ae_mulafc24ra_encode_fns, 0, 0 }, + { "ae_mulafc32ras", ICLASS_AE_MULAFC32RAS, + 0, + Opcode_ae_mulafc32ras_encode_fns, 0, 0 }, + { "ae_mulac32x16.l", ICLASS_AE_MULAC32X16_L, + 0, + Opcode_ae_mulac32x16_l_encode_fns, 0, 0 }, + { "ae_mulafc32x16ras.l", ICLASS_AE_MULAFC32X16RAS_L, + 0, + Opcode_ae_mulafc32x16ras_l_encode_fns, 0, 0 }, + { "ae_mulac32x16.h", ICLASS_AE_MULAC32X16_H, + 0, + Opcode_ae_mulac32x16_h_encode_fns, 0, 0 }, + { "ae_mulafc32x16ras.h", ICLASS_AE_MULAFC32X16RAS_H, + 0, + Opcode_ae_mulafc32x16ras_h_encode_fns, 0, 0 }, + { "ae_mulf16x4ss", ICLASS_AE_MULF16X4SS, + 0, + Opcode_ae_mulf16x4ss_encode_fns, 0, 0 }, + { "ae_mulaf16x4ss", ICLASS_AE_MULAF16X4SS, + 0, + Opcode_ae_mulaf16x4ss_encode_fns, 0, 0 }, + { "ae_mulsf16x4ss", ICLASS_AE_MULSF16X4SS, + 0, + Opcode_ae_mulsf16x4ss_encode_fns, 0, 0 }, + { "ae_mul16x4s", ICLASS_AE_MUL16X4S, + 0, + Opcode_ae_mul16x4s_encode_fns, 0, 0 }, + { "ae_mula16x4s", ICLASS_AE_MULA16X4S, + 0, + Opcode_ae_mula16x4s_encode_fns, 0, 0 }, + { "ae_muls16x4s", ICLASS_AE_MULS16X4S, + 0, + Opcode_ae_muls16x4s_encode_fns, 0, 0 }, + { "ae_mul16x4", ICLASS_AE_MUL16X4, + 0, + Opcode_ae_mul16x4_encode_fns, 0, 0 }, + { "ae_mula16x4", ICLASS_AE_MULA16X4, + 0, + Opcode_ae_mula16x4_encode_fns, 0, 0 }, + { "ae_muls16x4", ICLASS_AE_MULS16X4, + 0, + Opcode_ae_muls16x4_encode_fns, 0, 0 }, + { "ae_mulfd32x2s.fir.h", ICLASS_AE_MULFD32X2S_FIR_H, + 0, + Opcode_ae_mulfd32x2s_fir_h_encode_fns, 0, 0 }, + { "ae_mulfd32x2ra.fir.h", ICLASS_AE_MULFD32X2RA_FIR_H, + 0, + Opcode_ae_mulfd32x2ra_fir_h_encode_fns, 0, 0 }, + { "ae_mulfd32x2s.fir.l", ICLASS_AE_MULFD32X2S_FIR_L, + 0, + Opcode_ae_mulfd32x2s_fir_l_encode_fns, 0, 0 }, + { "ae_mulfd32x2ra.fir.l", ICLASS_AE_MULFD32X2RA_FIR_L, + 0, + Opcode_ae_mulfd32x2ra_fir_l_encode_fns, 0, 0 }, + { "ae_mulfd32x16x2.fir.hh", ICLASS_AE_MULFD32X16X2_FIR_HH, + 0, + Opcode_ae_mulfd32x16x2_fir_hh_encode_fns, 0, 0 }, + { "ae_mulfd32x16x2.fir.hl", ICLASS_AE_MULFD32X16X2_FIR_HL, + 0, + Opcode_ae_mulfd32x16x2_fir_hl_encode_fns, 0, 0 }, + { "ae_mulfd32x16x2.fir.lh", ICLASS_AE_MULFD32X16X2_FIR_LH, + 0, + Opcode_ae_mulfd32x16x2_fir_lh_encode_fns, 0, 0 }, + { "ae_mulfd32x16x2.fir.ll", ICLASS_AE_MULFD32X16X2_FIR_LL, + 0, + Opcode_ae_mulfd32x16x2_fir_ll_encode_fns, 0, 0 }, + { "ae_mulafd32x2s.fir.h", ICLASS_AE_MULAFD32X2S_FIR_H, + 0, + Opcode_ae_mulafd32x2s_fir_h_encode_fns, 0, 0 }, + { "ae_mulafd32x2ra.fir.h", ICLASS_AE_MULAFD32X2RA_FIR_H, + 0, + Opcode_ae_mulafd32x2ra_fir_h_encode_fns, 0, 0 }, + { "ae_mulafd32x2s.fir.l", ICLASS_AE_MULAFD32X2S_FIR_L, + 0, + Opcode_ae_mulafd32x2s_fir_l_encode_fns, 0, 0 }, + { "ae_mulafd32x2ra.fir.l", ICLASS_AE_MULAFD32X2RA_FIR_L, + 0, + Opcode_ae_mulafd32x2ra_fir_l_encode_fns, 0, 0 }, + { "ae_mulafd32x16x2.fir.hh", ICLASS_AE_MULAFD32X16X2_FIR_HH, + 0, + Opcode_ae_mulafd32x16x2_fir_hh_encode_fns, 0, 0 }, + { "ae_mulafd32x16x2.fir.hl", ICLASS_AE_MULAFD32X16X2_FIR_HL, + 0, + Opcode_ae_mulafd32x16x2_fir_hl_encode_fns, 0, 0 }, + { "ae_mulafd32x16x2.fir.lh", ICLASS_AE_MULAFD32X16X2_FIR_LH, + 0, + Opcode_ae_mulafd32x16x2_fir_lh_encode_fns, 0, 0 }, + { "ae_mulafd32x16x2.fir.ll", ICLASS_AE_MULAFD32X16X2_FIR_LL, + 0, + Opcode_ae_mulafd32x16x2_fir_ll_encode_fns, 0, 0 }, + { "ae_mulc16s.h", ICLASS_AE_MULC16S_H, + 0, + Opcode_ae_mulc16s_h_encode_fns, 0, 0 }, + { "ae_mulc16s.l", ICLASS_AE_MULC16S_L, + 0, + Opcode_ae_mulc16s_l_encode_fns, 0, 0 }, + { "ae_mulac16s.h", ICLASS_AE_MULAC16S_H, + 0, + Opcode_ae_mulac16s_h_encode_fns, 0, 0 }, + { "ae_mulac16s.l", ICLASS_AE_MULAC16S_L, + 0, + Opcode_ae_mulac16s_l_encode_fns, 0, 0 }, + { "ae_mulfc16ras", ICLASS_AE_MULFC16RAS, + 0, + Opcode_ae_mulfc16ras_encode_fns, 0, 0 }, + { "ae_mulafc16ras", ICLASS_AE_MULAFC16RAS, + 0, + Opcode_ae_mulafc16ras_encode_fns, 0, 0 }, + { "ae_mul16js", ICLASS_AE_MUL16JS, + 0, + Opcode_ae_mul16js_encode_fns, 0, 0 }, + { "ae_addandsubrng16ras_s1", ICLASS_AE_ADDANDSUBRNG16RAS_S1, + 0, + Opcode_ae_addandsubrng16ras_s1_encode_fns, 0, 0 }, + { "ae_addandsubrng16ras_s2", ICLASS_AE_ADDANDSUBRNG16RAS_S2, + 0, + Opcode_ae_addandsubrng16ras_s2_encode_fns, 0, 0 }, + { "ae_conj16s", ICLASS_AE_CONJ16S, + 0, + Opcode_ae_conj16s_encode_fns, 0, 0 }, + { "ae_mulfq16x2.fir.3", ICLASS_AE_MULFQ16X2_FIR_3, + 0, + Opcode_ae_mulfq16x2_fir_3_encode_fns, 0, 0 }, + { "ae_mulfq16x2.fir.2", ICLASS_AE_MULFQ16X2_FIR_2, + 0, + Opcode_ae_mulfq16x2_fir_2_encode_fns, 0, 0 }, + { "ae_mulfq16x2.fir.1", ICLASS_AE_MULFQ16X2_FIR_1, + 0, + Opcode_ae_mulfq16x2_fir_1_encode_fns, 0, 0 }, + { "ae_mulfq16x2.fir.0", ICLASS_AE_MULFQ16X2_FIR_0, + 0, + Opcode_ae_mulfq16x2_fir_0_encode_fns, 0, 0 }, + { "ae_mulafq16x2.fir.3", ICLASS_AE_MULAFQ16X2_FIR_3, + 0, + Opcode_ae_mulafq16x2_fir_3_encode_fns, 0, 0 }, + { "ae_mulafq16x2.fir.2", ICLASS_AE_MULAFQ16X2_FIR_2, + 0, + Opcode_ae_mulafq16x2_fir_2_encode_fns, 0, 0 }, + { "ae_mulafq16x2.fir.1", ICLASS_AE_MULAFQ16X2_FIR_1, + 0, + Opcode_ae_mulafq16x2_fir_1_encode_fns, 0, 0 }, + { "ae_mulafq16x2.fir.0", ICLASS_AE_MULAFQ16X2_FIR_0, + 0, + Opcode_ae_mulafq16x2_fir_0_encode_fns, 0, 0 }, + { "ae_mulzaaaafq32x16", ICLASS_AE_MULZAAAAFQ32X16, + 0, + Opcode_ae_mulzaaaafq32x16_encode_fns, 0, 0 }, + { "ae_mulaaaafq32x16", ICLASS_AE_MULAAAAFQ32X16, + 0, + Opcode_ae_mulaaaafq32x16_encode_fns, 0, 0 }, + { "ae_mulzaaaaq32x16", ICLASS_AE_MULZAAAAQ32X16, + 0, + Opcode_ae_mulzaaaaq32x16_encode_fns, 0, 0 }, + { "ae_mulaaaaq32x16", ICLASS_AE_MULAAAAQ32X16, + 0, + Opcode_ae_mulaaaaq32x16_encode_fns, 0, 0 }, + { "ae_mul16.00", ICLASS_AE_MUL16_00, + 0, + Opcode_ae_mul16_00_encode_fns, 0, 0 }, + { "ae_mula16.00", ICLASS_AE_MULA16_00, + 0, + Opcode_ae_mula16_00_encode_fns, 0, 0 }, + { "ae_mulzaaaaq16", ICLASS_AE_MULZAAAAQ16, + 0, + Opcode_ae_mulzaaaaq16_encode_fns, 0, 0 }, + { "ae_mulaaaaq16", ICLASS_AE_MULAAAAQ16, + 0, + Opcode_ae_mulaaaaq16_encode_fns, 0, 0 }, + { "ae_div64d32.h", ICLASS_AE_DIV64D32_H, + 0, + Opcode_ae_div64d32_h_encode_fns, 0, 0 }, + { "ae_div64d32.l", ICLASS_AE_DIV64D32_L, + 0, + Opcode_ae_div64d32_l_encode_fns, 0, 0 }, + { "ae_sha32", ICLASS_AE_SHA32, + 0, + Opcode_ae_sha32_encode_fns, 0, 0 }, + { "ae_vldl32t", ICLASS_AE_VLDL32T, + 0, + Opcode_ae_vldl32t_encode_fns, 2, Opcode_ae_vldl32t_funcUnit_uses }, + { "ae_vldl16t", ICLASS_AE_VLDL16T, + 0, + Opcode_ae_vldl16t_encode_fns, 2, Opcode_ae_vldl16t_funcUnit_uses }, + { "ae_vldl16c", ICLASS_AE_VLDL16C, + 0, + Opcode_ae_vldl16c_encode_fns, 4, Opcode_ae_vldl16c_funcUnit_uses }, + { "ae_vldl16c.ip", ICLASS_AE_VLDL16C_IP, + 0, + Opcode_ae_vldl16c_ip_encode_fns, 4, Opcode_ae_vldl16c_ip_funcUnit_uses }, + { "ae_vldl16c.ic", ICLASS_AE_VLDL16C_IC, + 0, + Opcode_ae_vldl16c_ic_encode_fns, 4, Opcode_ae_vldl16c_ic_funcUnit_uses }, + { "ae_vldl16c.ic1", ICLASS_AE_VLDL16C_IC1, + 0, + Opcode_ae_vldl16c_ic1_encode_fns, 4, Opcode_ae_vldl16c_ic1_funcUnit_uses }, + { "ae_vldsht", ICLASS_AE_VLDSHT, + 0, + Opcode_ae_vldsht_encode_fns, 3, Opcode_ae_vldsht_funcUnit_uses }, + { "ae_lb", ICLASS_AE_LB, + 0, + Opcode_ae_lb_encode_fns, 1, Opcode_ae_lb_funcUnit_uses }, + { "ae_lbi", ICLASS_AE_LBI, + 0, + Opcode_ae_lbi_encode_fns, 1, Opcode_ae_lbi_funcUnit_uses }, + { "ae_lbk", ICLASS_AE_LBK, + 0, + Opcode_ae_lbk_encode_fns, 1, Opcode_ae_lbk_funcUnit_uses }, + { "ae_lbki", ICLASS_AE_LBKI, + 0, + Opcode_ae_lbki_encode_fns, 1, Opcode_ae_lbki_funcUnit_uses }, + { "ae_lbs", ICLASS_AE_LBS, + 0, + Opcode_ae_lbs_encode_fns, 1, Opcode_ae_lbs_funcUnit_uses }, + { "ae_lbsi", ICLASS_AE_LBSI, + 0, + Opcode_ae_lbsi_encode_fns, 1, Opcode_ae_lbsi_funcUnit_uses }, + { "ae_db", ICLASS_AE_DB, + 0, + Opcode_ae_db_encode_fns, 3, Opcode_ae_db_funcUnit_uses }, + { "ae_dbi", ICLASS_AE_DBI, + 0, + Opcode_ae_dbi_encode_fns, 3, Opcode_ae_dbi_funcUnit_uses }, + { "ae_db.ic", ICLASS_AE_DB_IC, + 0, + Opcode_ae_db_ic_encode_fns, 3, Opcode_ae_db_ic_funcUnit_uses }, + { "ae_dbi.ic", ICLASS_AE_DBI_IC, + 0, + Opcode_ae_dbi_ic_encode_fns, 3, Opcode_ae_dbi_ic_funcUnit_uses }, + { "ae_db.ic1", ICLASS_AE_DB_IC1, + 0, + Opcode_ae_db_ic1_encode_fns, 3, Opcode_ae_db_ic1_funcUnit_uses }, + { "ae_dbi.ic1", ICLASS_AE_DBI_IC1, + 0, + Opcode_ae_dbi_ic1_encode_fns, 3, Opcode_ae_dbi_ic1_funcUnit_uses }, + { "ae_db.ip", ICLASS_AE_DB_IP, + 0, + Opcode_ae_db_ip_encode_fns, 3, Opcode_ae_db_ip_funcUnit_uses }, + { "ae_dbi.ip", ICLASS_AE_DBI_IP, + 0, + Opcode_ae_dbi_ip_encode_fns, 3, Opcode_ae_dbi_ip_funcUnit_uses }, + { "ae_ardecnorm16", ICLASS_AE_ARDECNORM16, + 0, + Opcode_ae_ardecnorm16_encode_fns, 0, 0 }, + { "ae_lbki_dbi.ic", ICLASS_AE_LBKI_DBI_IC, + 0, + Opcode_ae_lbki_dbi_ic_encode_fns, 1, Opcode_ae_lbki_dbi_ic_funcUnit_uses }, + { "ae_lbki_dbi.ip", ICLASS_AE_LBKI_DBI_IP, + 0, + Opcode_ae_lbki_dbi_ip_encode_fns, 1, Opcode_ae_lbki_dbi_ip_funcUnit_uses }, + { "ae_lbki_dbi", ICLASS_AE_LBKI_DBI, + 0, + Opcode_ae_lbki_dbi_encode_fns, 1, Opcode_ae_lbki_dbi_funcUnit_uses }, + { "ae_lbi_dbi.ic", ICLASS_AE_LBI_DBI_IC, + 0, + Opcode_ae_lbi_dbi_ic_encode_fns, 1, Opcode_ae_lbi_dbi_ic_funcUnit_uses }, + { "ae_lbi_dbi.ip", ICLASS_AE_LBI_DBI_IP, + 0, + Opcode_ae_lbi_dbi_ip_encode_fns, 1, Opcode_ae_lbi_dbi_ip_funcUnit_uses }, + { "ae_lbi_dbi", ICLASS_AE_LBI_DBI, + 0, + Opcode_ae_lbi_dbi_encode_fns, 1, Opcode_ae_lbi_dbi_funcUnit_uses }, + { "ae_lbk_db.ic", ICLASS_AE_LBK_DB_IC, + 0, + Opcode_ae_lbk_db_ic_encode_fns, 1, Opcode_ae_lbk_db_ic_funcUnit_uses }, + { "ae_lbk_db.ip", ICLASS_AE_LBK_DB_IP, + 0, + Opcode_ae_lbk_db_ip_encode_fns, 1, Opcode_ae_lbk_db_ip_funcUnit_uses }, + { "ae_lbk_db", ICLASS_AE_LBK_DB, + 0, + Opcode_ae_lbk_db_encode_fns, 1, Opcode_ae_lbk_db_funcUnit_uses }, + { "ae_lb_db.ic", ICLASS_AE_LB_DB_IC, + 0, + Opcode_ae_lb_db_ic_encode_fns, 1, Opcode_ae_lb_db_ic_funcUnit_uses }, + { "ae_lb_db.ip", ICLASS_AE_LB_DB_IP, + 0, + Opcode_ae_lb_db_ip_encode_fns, 1, Opcode_ae_lb_db_ip_funcUnit_uses }, + { "ae_lb_db", ICLASS_AE_LB_DB, + 0, + Opcode_ae_lb_db_encode_fns, 1, Opcode_ae_lb_db_funcUnit_uses }, + { "ae_vlel32t", ICLASS_AE_VLEL32T, + 0, + Opcode_ae_vlel32t_encode_fns, 2, Opcode_ae_vlel32t_funcUnit_uses }, + { "ae_vlel16t", ICLASS_AE_VLEL16T, + 0, + Opcode_ae_vlel16t_encode_fns, 2, Opcode_ae_vlel16t_funcUnit_uses }, + { "ae_sb", ICLASS_AE_SB, + 0, + Opcode_ae_sb_encode_fns, 3, Opcode_ae_sb_funcUnit_uses }, + { "ae_sbi", ICLASS_AE_SBI, + 0, + Opcode_ae_sbi_encode_fns, 3, Opcode_ae_sbi_funcUnit_uses }, + { "ae_vles16c", ICLASS_AE_VLES16C, + 0, + Opcode_ae_vles16c_encode_fns, 3, Opcode_ae_vles16c_funcUnit_uses }, + { "ae_sbf", ICLASS_AE_SBF, + 0, + Opcode_ae_sbf_encode_fns, 3, Opcode_ae_sbf_funcUnit_uses }, + { "ae_sb.ic", ICLASS_AE_SB_IC, + 0, + Opcode_ae_sb_ic_encode_fns, 3, Opcode_ae_sb_ic_funcUnit_uses }, + { "ae_sbi.ic", ICLASS_AE_SBI_IC, + 0, + Opcode_ae_sbi_ic_encode_fns, 3, Opcode_ae_sbi_ic_funcUnit_uses }, + { "ae_vles16c.ic", ICLASS_AE_VLES16C_IC, + 0, + Opcode_ae_vles16c_ic_encode_fns, 3, Opcode_ae_vles16c_ic_funcUnit_uses }, + { "ae_sbf.ic", ICLASS_AE_SBF_IC, + 0, + Opcode_ae_sbf_ic_encode_fns, 3, Opcode_ae_sbf_ic_funcUnit_uses }, + { "ae_sb.ic1", ICLASS_AE_SB_IC1, + 0, + Opcode_ae_sb_ic1_encode_fns, 3, Opcode_ae_sb_ic1_funcUnit_uses }, + { "ae_sbi.ic1", ICLASS_AE_SBI_IC1, + 0, + Opcode_ae_sbi_ic1_encode_fns, 3, Opcode_ae_sbi_ic1_funcUnit_uses }, + { "ae_vles16c.ic1", ICLASS_AE_VLES16C_IC1, + 0, + Opcode_ae_vles16c_ic1_encode_fns, 3, Opcode_ae_vles16c_ic1_funcUnit_uses }, + { "ae_sbf.ic1", ICLASS_AE_SBF_IC1, + 0, + Opcode_ae_sbf_ic1_encode_fns, 3, Opcode_ae_sbf_ic1_funcUnit_uses }, + { "ae_sb.ip", ICLASS_AE_SB_IP, + 0, + Opcode_ae_sb_ip_encode_fns, 3, Opcode_ae_sb_ip_funcUnit_uses }, + { "ae_sbi.ip", ICLASS_AE_SBI_IP, + 0, + Opcode_ae_sbi_ip_encode_fns, 3, Opcode_ae_sbi_ip_funcUnit_uses }, + { "ae_vles16c.ip", ICLASS_AE_VLES16C_IP, + 0, + Opcode_ae_vles16c_ip_encode_fns, 3, Opcode_ae_vles16c_ip_funcUnit_uses }, + { "ae_sbf.ip", ICLASS_AE_SBF_IP, + 0, + Opcode_ae_sbf_ip_encode_fns, 3, Opcode_ae_sbf_ip_funcUnit_uses }, + { "ae_sext32", ICLASS_AE_SEXT32, + 0, + Opcode_ae_sext32_encode_fns, 0, 0 }, + { "ae_movae", ICLASS_AE_MOVAE, + 0, + Opcode_ae_movae_encode_fns, 0, 0 }, + { "ae_movea", ICLASS_AE_MOVEA, + 0, + Opcode_ae_movea_encode_fns, 0, 0 }, + { "ae_moveep", ICLASS_AE_MOVEEP, + 0, + Opcode_ae_moveep_encode_fns, 0, 0 }, + { "ae_sext72", ICLASS_AE_SEXT72, + 0, + Opcode_ae_sext72_encode_fns, 0, 0 }, + { "ae_add72", ICLASS_AE_ADD72, + 0, + Opcode_ae_add72_encode_fns, 0, 0 }, + { "ae_sub72", ICLASS_AE_SUB72, + 0, + Opcode_ae_sub72_encode_fns, 0, 0 }, + { "ae_add72x64", ICLASS_AE_ADD72X64, + 0, + Opcode_ae_add72x64_encode_fns, 0, 0 }, + { "ae_sub72x64", ICLASS_AE_SUB72X64, + 0, + Opcode_ae_sub72x64_encode_fns, 0, 0 }, + { "ae_mul32ep.hh", ICLASS_AE_MUL32EP_HH, + 0, + Opcode_ae_mul32ep_hh_encode_fns, 0, 0 }, + { "ae_mula32ep.hh", ICLASS_AE_MULA32EP_HH, + 0, + Opcode_ae_mula32ep_hh_encode_fns, 0, 0 }, + { "ae_muls32ep.hh", ICLASS_AE_MULS32EP_HH, + 0, + Opcode_ae_muls32ep_hh_encode_fns, 0, 0 }, + { "ae_mulzaad32ep.hh.ll", ICLASS_AE_MULZAAD32EP_HH_LL, + 0, + Opcode_ae_mulzaad32ep_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssd32ep.hh.ll", ICLASS_AE_MULZSSD32EP_HH_LL, + 0, + Opcode_ae_mulzssd32ep_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaad32ep.hh.ll", ICLASS_AE_MULAAD32EP_HH_LL, + 0, + Opcode_ae_mulaad32ep_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssd32ep.hh.ll", ICLASS_AE_MULSSD32EP_HH_LL, + 0, + Opcode_ae_mulssd32ep_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaad32usep.hl.lh", ICLASS_AE_MULAAD32USEP_HL_LH, + 0, + Opcode_ae_mulaad32usep_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaad32usep.hl.lh", ICLASS_AE_MULZAAD32USEP_HL_LH, + 0, + Opcode_ae_mulzaad32usep_hl_lh_encode_fns, 0, 0 }, + { "ae_mul32usep.lh", ICLASS_AE_MUL32USEP_LH, + 0, + Opcode_ae_mul32usep_lh_encode_fns, 0, 0 }, + { "ae_mula32usep.lh", ICLASS_AE_MULA32USEP_LH, + 0, + Opcode_ae_mula32usep_lh_encode_fns, 0, 0 }, + { "ae_mul32usep.ll", ICLASS_AE_MUL32USEP_LL, + 0, + Opcode_ae_mul32usep_ll_encode_fns, 0, 0 }, + { "ae_mula32usep.ll", ICLASS_AE_MULA32USEP_LL, + 0, + Opcode_ae_mula32usep_ll_encode_fns, 0, 0 }, + { "ae_srai72", ICLASS_AE_SRAI72, + 0, + Opcode_ae_srai72_encode_fns, 0, 0 }, + { "ae_slai72", ICLASS_AE_SLAI72, + 0, + Opcode_ae_slai72_encode_fns, 0, 0 }, + { "ae_sat64s", ICLASS_AE_SAT64S, + 0, + Opcode_ae_sat64s_encode_fns, 0, 0 }, + { "ae_l16si.n", ICLASS_AE_L16SI_N, + 0, + Opcode_ae_l16si_n_encode_fns, 2, Opcode_ae_l16si_n_funcUnit_uses }, + { "ae_l16ui.n", ICLASS_AE_L16UI_N, + 0, + Opcode_ae_l16ui_n_encode_fns, 2, Opcode_ae_l16ui_n_funcUnit_uses }, + { "ae_s16i.n", ICLASS_AE_S16I_N, + 0, + Opcode_ae_s16i_n_encode_fns, 2, Opcode_ae_s16i_n_funcUnit_uses }, + { "ae_lalign128.i", ICLASS_AE_LALIGN128_I, + 0, + Opcode_ae_lalign128_i_encode_fns, 1, Opcode_ae_lalign128_i_funcUnit_uses }, + { "ae_salign128.i", ICLASS_AE_SALIGN128_I, + 0, + Opcode_ae_salign128_i_encode_fns, 1, Opcode_ae_salign128_i_funcUnit_uses }, + { "ae_la128.pp", ICLASS_AE_LA128_PP, + 0, + Opcode_ae_la128_pp_encode_fns, 1, Opcode_ae_la128_pp_funcUnit_uses }, + { "ae_sa128pos.fp", ICLASS_AE_SA128POS_FP, + 0, + Opcode_ae_sa128pos_fp_encode_fns, 1, Opcode_ae_sa128pos_fp_funcUnit_uses }, + { "ae_la8x4s_ip", ICLASS_AE_LA8X4S_IP, + 0, + Opcode_ae_la8x4s_ip_encode_fns, 1, Opcode_ae_la8x4s_ip_funcUnit_uses }, + { "ae_la8x4u_ip", ICLASS_AE_LA8X4U_IP, + 0, + Opcode_ae_la8x4u_ip_encode_fns, 1, Opcode_ae_la8x4u_ip_funcUnit_uses }, + { "ae_la8x8x2_ip", ICLASS_AE_LA8X8X2_IP, + 0, + Opcode_ae_la8x8x2_ip_encode_fns, 1, Opcode_ae_la8x8x2_ip_funcUnit_uses }, + { "ae_la16x4x2_ip", ICLASS_AE_LA16X4X2_IP, + 0, + Opcode_ae_la16x4x2_ip_encode_fns, 1, Opcode_ae_la16x4x2_ip_funcUnit_uses }, + { "ae_la32x2x2_ip", ICLASS_AE_LA32X2X2_IP, + 0, + Opcode_ae_la32x2x2_ip_encode_fns, 1, Opcode_ae_la32x2x2_ip_funcUnit_uses }, + { "ae_la8x8x2_ic", ICLASS_AE_LA8X8X2_IC, + 0, + Opcode_ae_la8x8x2_ic_encode_fns, 1, Opcode_ae_la8x8x2_ic_funcUnit_uses }, + { "ae_la16x4x2_ic", ICLASS_AE_LA16X4X2_IC, + 0, + Opcode_ae_la16x4x2_ic_encode_fns, 1, Opcode_ae_la16x4x2_ic_funcUnit_uses }, + { "ae_la32x2x2_ic", ICLASS_AE_LA32X2X2_IC, + 0, + Opcode_ae_la32x2x2_ic_encode_fns, 1, Opcode_ae_la32x2x2_ic_funcUnit_uses }, + { "ae_la8x8x2_ic1", ICLASS_AE_LA8X8X2_IC1, + 0, + Opcode_ae_la8x8x2_ic1_encode_fns, 1, Opcode_ae_la8x8x2_ic1_funcUnit_uses }, + { "ae_la16x4x2_ic1", ICLASS_AE_LA16X4X2_IC1, + 0, + Opcode_ae_la16x4x2_ic1_encode_fns, 1, Opcode_ae_la16x4x2_ic1_funcUnit_uses }, + { "ae_la32x2x2_ic1", ICLASS_AE_LA32X2X2_IC1, + 0, + Opcode_ae_la32x2x2_ic1_encode_fns, 1, Opcode_ae_la32x2x2_ic1_funcUnit_uses }, + { "ae_la8x8x2_ic2", ICLASS_AE_LA8X8X2_IC2, + 0, + Opcode_ae_la8x8x2_ic2_encode_fns, 1, Opcode_ae_la8x8x2_ic2_funcUnit_uses }, + { "ae_la16x4x2_ic2", ICLASS_AE_LA16X4X2_IC2, + 0, + Opcode_ae_la16x4x2_ic2_encode_fns, 1, Opcode_ae_la16x4x2_ic2_funcUnit_uses }, + { "ae_la32x2x2_ic2", ICLASS_AE_LA32X2X2_IC2, + 0, + Opcode_ae_la32x2x2_ic2_encode_fns, 1, Opcode_ae_la32x2x2_ic2_funcUnit_uses }, + { "ae_sa8x8x2_ip", ICLASS_AE_SA8X8X2_IP, + 0, + Opcode_ae_sa8x8x2_ip_encode_fns, 1, Opcode_ae_sa8x8x2_ip_funcUnit_uses }, + { "ae_sa16x4x2_ip", ICLASS_AE_SA16X4X2_IP, + 0, + Opcode_ae_sa16x4x2_ip_encode_fns, 1, Opcode_ae_sa16x4x2_ip_funcUnit_uses }, + { "ae_sa32x2x2_ip", ICLASS_AE_SA32X2X2_IP, + 0, + Opcode_ae_sa32x2x2_ip_encode_fns, 1, Opcode_ae_sa32x2x2_ip_funcUnit_uses }, + { "ae_sa8x8x2_ic", ICLASS_AE_SA8X8X2_IC, + 0, + Opcode_ae_sa8x8x2_ic_encode_fns, 1, Opcode_ae_sa8x8x2_ic_funcUnit_uses }, + { "ae_sa16x4x2_ic", ICLASS_AE_SA16X4X2_IC, + 0, + Opcode_ae_sa16x4x2_ic_encode_fns, 1, Opcode_ae_sa16x4x2_ic_funcUnit_uses }, + { "ae_sa32x2x2_ic", ICLASS_AE_SA32X2X2_IC, + 0, + Opcode_ae_sa32x2x2_ic_encode_fns, 1, Opcode_ae_sa32x2x2_ic_funcUnit_uses }, + { "ae_sa8x8x2_ic1", ICLASS_AE_SA8X8X2_IC1, + 0, + Opcode_ae_sa8x8x2_ic1_encode_fns, 1, Opcode_ae_sa8x8x2_ic1_funcUnit_uses }, + { "ae_sa16x4x2_ic1", ICLASS_AE_SA16X4X2_IC1, + 0, + Opcode_ae_sa16x4x2_ic1_encode_fns, 1, Opcode_ae_sa16x4x2_ic1_funcUnit_uses }, + { "ae_sa32x2x2_ic1", ICLASS_AE_SA32X2X2_IC1, + 0, + Opcode_ae_sa32x2x2_ic1_encode_fns, 1, Opcode_ae_sa32x2x2_ic1_funcUnit_uses }, + { "ae_sa8x8x2_ic2", ICLASS_AE_SA8X8X2_IC2, + 0, + Opcode_ae_sa8x8x2_ic2_encode_fns, 1, Opcode_ae_sa8x8x2_ic2_funcUnit_uses }, + { "ae_sa16x4x2_ic2", ICLASS_AE_SA16X4X2_IC2, + 0, + Opcode_ae_sa16x4x2_ic2_encode_fns, 1, Opcode_ae_sa16x4x2_ic2_funcUnit_uses }, + { "ae_sa32x2x2_ic2", ICLASS_AE_SA32X2X2_IC2, + 0, + Opcode_ae_sa32x2x2_ic2_encode_fns, 1, Opcode_ae_sa32x2x2_ic2_funcUnit_uses }, + { "ae_abs8", ICLASS_AE_ABS8, + 0, + Opcode_ae_abs8_encode_fns, 0, 0 }, + { "ae_abs8s", ICLASS_AE_ABS8S, + 0, + Opcode_ae_abs8s_encode_fns, 0, 0 }, + { "ae_neg8s", ICLASS_AE_NEG8S, + 0, + Opcode_ae_neg8s_encode_fns, 0, 0 }, + { "ae_add8", ICLASS_AE_ADD8, + 0, + Opcode_ae_add8_encode_fns, 0, 0 }, + { "ae_sub8", ICLASS_AE_SUB8, + 0, + Opcode_ae_sub8_encode_fns, 0, 0 }, + { "ae_max8", ICLASS_AE_MAX8, + 0, + Opcode_ae_max8_encode_fns, 0, 0 }, + { "ae_min8", ICLASS_AE_MIN8, + 0, + Opcode_ae_min8_encode_fns, 0, 0 }, + { "ae_add8s", ICLASS_AE_ADD8S, + 0, + Opcode_ae_add8s_encode_fns, 0, 0 }, + { "ae_sub8s", ICLASS_AE_SUB8S, + 0, + Opcode_ae_sub8s_encode_fns, 0, 0 }, + { "ae_le8", ICLASS_AE_LE8, + 0, + Opcode_ae_le8_encode_fns, 0, 0 }, + { "ae_lt8", ICLASS_AE_LT8, + 0, + Opcode_ae_lt8_encode_fns, 0, 0 }, + { "ae_eq8", ICLASS_AE_EQ8, + 0, + Opcode_ae_eq8_encode_fns, 0, 0 }, + { "ae_satu16x4", ICLASS_AE_SATU16X4, + 0, + Opcode_ae_satu16x4_encode_fns, 0, 0 }, + { "ae_sat32x2", ICLASS_AE_SAT32X2, + 0, + Opcode_ae_sat32x2_encode_fns, 0, 0 }, + { "ae_satu32x2", ICLASS_AE_SATU32X2, + 0, + Opcode_ae_satu32x2_encode_fns, 0, 0 }, + { "ae_sat8x8x16", ICLASS_AE_SAT8X8X16, + 0, + Opcode_ae_sat8x8x16_encode_fns, 0, 0 }, + { "ae_satu8x8x16", ICLASS_AE_SATU8X8X16, + 0, + Opcode_ae_satu8x8x16_encode_fns, 0, 0 }, + { "ae_sat8x4x32_l", ICLASS_AE_SAT8X4X32_L, + 0, + Opcode_ae_sat8x4x32_l_encode_fns, 0, 0 }, + { "ae_satu8x4x32_l", ICLASS_AE_SATU8X4X32_L, + 0, + Opcode_ae_satu8x4x32_l_encode_fns, 0, 0 }, + { "ae_round8x8f16ssym", ICLASS_AE_ROUND8X8F16SSYM, + 0, + Opcode_ae_round8x8f16ssym_encode_fns, 0, 0 }, + { "ae_round8x8f16sasym", ICLASS_AE_ROUND8X8F16SASYM, + 0, + Opcode_ae_round8x8f16sasym_encode_fns, 0, 0 }, + { "ae_round8x4f32ssym_l", ICLASS_AE_ROUND8X4F32SSYM_L, + 0, + Opcode_ae_round8x4f32ssym_l_encode_fns, 0, 0 }, + { "ae_round8x4f32sasym_l", ICLASS_AE_ROUND8X4F32SASYM_L, + 0, + Opcode_ae_round8x4f32sasym_l_encode_fns, 0, 0 }, + { "ae_movda8", ICLASS_AE_MOVDA8, + 0, + Opcode_ae_movda8_encode_fns, 0, 0 }, + { "ae_movad8", ICLASS_AE_MOVAD8, + 0, + Opcode_ae_movad8_encode_fns, 0, 0 }, + { "ae_movdx2", ICLASS_AE_MOVDX2, + 0, + Opcode_ae_movdx2_encode_fns, 0, 0 }, + { "ae_addandsub32j", ICLASS_AE_ADDANDSUB32J, + 0, + Opcode_ae_addandsub32j_encode_fns, 0, 0 }, + { "ae_addw8", ICLASS_AE_ADDW8, + 0, + Opcode_ae_addw8_encode_fns, 0, 0 }, + { "ae_addw16", ICLASS_AE_ADDW16, + 0, + Opcode_ae_addw16_encode_fns, 0, 0 }, + { "ae_addw32", ICLASS_AE_ADDW32, + 0, + Opcode_ae_addw32_encode_fns, 0, 0 }, + { "ae_subw8", ICLASS_AE_SUBW8, + 0, + Opcode_ae_subw8_encode_fns, 0, 0 }, + { "ae_subw16", ICLASS_AE_SUBW16, + 0, + Opcode_ae_subw16_encode_fns, 0, 0 }, + { "ae_subw32", ICLASS_AE_SUBW32, + 0, + Opcode_ae_subw32_encode_fns, 0, 0 }, + { "ae_accw8", ICLASS_AE_ACCW8, + 0, + Opcode_ae_accw8_encode_fns, 0, 0 }, + { "ae_accw16", ICLASS_AE_ACCW16, + 0, + Opcode_ae_accw16_encode_fns, 0, 0 }, + { "ae_accw32", ICLASS_AE_ACCW32, + 0, + Opcode_ae_accw32_encode_fns, 0, 0 }, + { "ae_addw8u", ICLASS_AE_ADDW8U, + 0, + Opcode_ae_addw8u_encode_fns, 0, 0 }, + { "ae_subw8u", ICLASS_AE_SUBW8U, + 0, + Opcode_ae_subw8u_encode_fns, 0, 0 }, + { "ae_accw8u", ICLASS_AE_ACCW8U, + 0, + Opcode_ae_accw8u_encode_fns, 0, 0 }, + { "ae_mulfp32x2s.hh.ll", ICLASS_AE_MULFP32X2S_HH_LL, + 0, + Opcode_ae_mulfp32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulafp32x2s.hh.ll", ICLASS_AE_MULAFP32X2S_HH_LL, + 0, + Opcode_ae_mulafp32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsfp32x2s.hh.ll", ICLASS_AE_MULSFP32X2S_HH_LL, + 0, + Opcode_ae_mulsfp32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulfp32x2s.hl.lh", ICLASS_AE_MULFP32X2S_HL_LH, + 0, + Opcode_ae_mulfp32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulafp32x2s.hl.lh", ICLASS_AE_MULAFP32X2S_HL_LH, + 0, + Opcode_ae_mulafp32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsfp32x2s.hl.lh", ICLASS_AE_MULSFP32X2S_HL_LH, + 0, + Opcode_ae_mulsfp32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaaf2d32s.hh.ll", ICLASS_AE_MULZAAF2D32S_HH_LL, + 0, + Opcode_ae_mulzaaf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasf2d32s.hh.ll", ICLASS_AE_MULZASF2D32S_HH_LL, + 0, + Opcode_ae_mulzasf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsaf2d32s.hh.ll", ICLASS_AE_MULZSAF2D32S_HH_LL, + 0, + Opcode_ae_mulzsaf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssf2d32s.hh.ll", ICLASS_AE_MULZSSF2D32S_HH_LL, + 0, + Opcode_ae_mulzssf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaaf2d32s.hh.ll", ICLASS_AE_MULAAF2D32S_HH_LL, + 0, + Opcode_ae_mulaaf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasf2d32s.hh.ll", ICLASS_AE_MULASF2D32S_HH_LL, + 0, + Opcode_ae_mulasf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsaf2d32s.hh.ll", ICLASS_AE_MULSAF2D32S_HH_LL, + 0, + Opcode_ae_mulsaf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssf2d32s.hh.ll", ICLASS_AE_MULSSF2D32S_HH_LL, + 0, + Opcode_ae_mulssf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaaf2d32s.hl.lh", ICLASS_AE_MULZAAF2D32S_HL_LH, + 0, + Opcode_ae_mulzaaf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasf2d32s.hl.lh", ICLASS_AE_MULZASF2D32S_HL_LH, + 0, + Opcode_ae_mulzasf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzsaf2d32s.hl.lh", ICLASS_AE_MULZSAF2D32S_HL_LH, + 0, + Opcode_ae_mulzsaf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssf2d32s.hl.lh", ICLASS_AE_MULZSSF2D32S_HL_LH, + 0, + Opcode_ae_mulzssf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaaf2d32s.hl.lh", ICLASS_AE_MULAAF2D32S_HL_LH, + 0, + Opcode_ae_mulaaf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasf2d32s.hl.lh", ICLASS_AE_MULASF2D32S_HL_LH, + 0, + Opcode_ae_mulasf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsaf2d32s.hl.lh", ICLASS_AE_MULSAF2D32S_HL_LH, + 0, + Opcode_ae_mulsaf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssf2d32s.hl.lh", ICLASS_AE_MULSSF2D32S_HL_LH, + 0, + Opcode_ae_mulssf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mul32s.hh", ICLASS_AE_MUL32S_HH, + 0, + Opcode_ae_mul32s_hh_encode_fns, 0, 0 }, + { "ae_mula32s.hh", ICLASS_AE_MULA32S_HH, + 0, + Opcode_ae_mula32s_hh_encode_fns, 0, 0 }, + { "ae_muls32s.hh", ICLASS_AE_MULS32S_HH, + 0, + Opcode_ae_muls32s_hh_encode_fns, 0, 0 }, + { "ae_mul32s.ll", ICLASS_AE_MUL32S_LL, + 0, + Opcode_ae_mul32s_ll_encode_fns, 0, 0 }, + { "ae_mula32s.ll", ICLASS_AE_MULA32S_LL, + 0, + Opcode_ae_mula32s_ll_encode_fns, 0, 0 }, + { "ae_muls32s.ll", ICLASS_AE_MULS32S_LL, + 0, + Opcode_ae_muls32s_ll_encode_fns, 0, 0 }, + { "ae_mul32s.hl", ICLASS_AE_MUL32S_HL, + 0, + Opcode_ae_mul32s_hl_encode_fns, 0, 0 }, + { "ae_mula32s.hl", ICLASS_AE_MULA32S_HL, + 0, + Opcode_ae_mula32s_hl_encode_fns, 0, 0 }, + { "ae_muls32s.hl", ICLASS_AE_MULS32S_HL, + 0, + Opcode_ae_muls32s_hl_encode_fns, 0, 0 }, + { "ae_mul32s.lh", ICLASS_AE_MUL32S_LH, + 0, + Opcode_ae_mul32s_lh_encode_fns, 0, 0 }, + { "ae_mula32s.lh", ICLASS_AE_MULA32S_LH, + 0, + Opcode_ae_mula32s_lh_encode_fns, 0, 0 }, + { "ae_muls32s.lh", ICLASS_AE_MULS32S_LH, + 0, + Opcode_ae_muls32s_lh_encode_fns, 0, 0 }, + { "ae_mul32x2s.hh.ll", ICLASS_AE_MUL32X2S_HH_LL, + 0, + Opcode_ae_mul32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_mula32x2s.hh.ll", ICLASS_AE_MULA32X2S_HH_LL, + 0, + Opcode_ae_mula32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_muls32x2s.hh.ll", ICLASS_AE_MULS32X2S_HH_LL, + 0, + Opcode_ae_muls32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_mul32x2s.hl.lh", ICLASS_AE_MUL32X2S_HL_LH, + 0, + Opcode_ae_mul32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_mula32x2s.hl.lh", ICLASS_AE_MULA32X2S_HL_LH, + 0, + Opcode_ae_mula32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_muls32x2s.hl.lh", ICLASS_AE_MULS32X2S_HL_LH, + 0, + Opcode_ae_muls32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaad32s.hh.ll", ICLASS_AE_MULZAAD32S_HH_LL, + 0, + Opcode_ae_mulzaad32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasd32s.hh.ll", ICLASS_AE_MULZASD32S_HH_LL, + 0, + Opcode_ae_mulzasd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsad32s.hh.ll", ICLASS_AE_MULZSAD32S_HH_LL, + 0, + Opcode_ae_mulzsad32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssd32s.hh.ll", ICLASS_AE_MULZSSD32S_HH_LL, + 0, + Opcode_ae_mulzssd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaad32s.hh.ll", ICLASS_AE_MULAAD32S_HH_LL, + 0, + Opcode_ae_mulaad32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasd32s.hh.ll", ICLASS_AE_MULASD32S_HH_LL, + 0, + Opcode_ae_mulasd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsad32s.hh.ll", ICLASS_AE_MULSAD32S_HH_LL, + 0, + Opcode_ae_mulsad32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssd32s.hh.ll", ICLASS_AE_MULSSD32S_HH_LL, + 0, + Opcode_ae_mulssd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaad32s.hl.lh", ICLASS_AE_MULZAAD32S_HL_LH, + 0, + Opcode_ae_mulzaad32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasd32s.hl.lh", ICLASS_AE_MULZASD32S_HL_LH, + 0, + Opcode_ae_mulzasd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzsad32s.hl.lh", ICLASS_AE_MULZSAD32S_HL_LH, + 0, + Opcode_ae_mulzsad32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssd32s.hl.lh", ICLASS_AE_MULZSSD32S_HL_LH, + 0, + Opcode_ae_mulzssd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaad32s.hl.lh", ICLASS_AE_MULAAD32S_HL_LH, + 0, + Opcode_ae_mulaad32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasd32s.hl.lh", ICLASS_AE_MULASD32S_HL_LH, + 0, + Opcode_ae_mulasd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsad32s.hl.lh", ICLASS_AE_MULSAD32S_HL_LH, + 0, + Opcode_ae_mulsad32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssd32s.hl.lh", ICLASS_AE_MULSSD32S_HL_LH, + 0, + Opcode_ae_mulssd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulf32x2ra.hh.ll", ICLASS_AE_MULF32X2RA_HH_LL, + 0, + Opcode_ae_mulf32x2ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaf32x2ra.hh.ll", ICLASS_AE_MULAF32X2RA_HH_LL, + 0, + Opcode_ae_mulaf32x2ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsf32x2ra.hh.ll", ICLASS_AE_MULSF32X2RA_HH_LL, + 0, + Opcode_ae_mulsf32x2ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulf32x2ra.hl.lh", ICLASS_AE_MULF32X2RA_HL_LH, + 0, + Opcode_ae_mulf32x2ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaf32x2ra.hl.lh", ICLASS_AE_MULAF32X2RA_HL_LH, + 0, + Opcode_ae_mulaf32x2ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsf32x2ra.hl.lh", ICLASS_AE_MULSF32X2RA_HL_LH, + 0, + Opcode_ae_mulsf32x2ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaaf2d32ra.hh.ll", ICLASS_AE_MULZAAF2D32RA_HH_LL, + 0, + Opcode_ae_mulzaaf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasf2d32ra.hh.ll", ICLASS_AE_MULZASF2D32RA_HH_LL, + 0, + Opcode_ae_mulzasf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsaf2d32ra.hh.ll", ICLASS_AE_MULZSAF2D32RA_HH_LL, + 0, + Opcode_ae_mulzsaf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssf2d32ra.hh.ll", ICLASS_AE_MULZSSF2D32RA_HH_LL, + 0, + Opcode_ae_mulzssf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaaf2d32ra.hh.ll", ICLASS_AE_MULAAF2D32RA_HH_LL, + 0, + Opcode_ae_mulaaf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasf2d32ra.hh.ll", ICLASS_AE_MULASF2D32RA_HH_LL, + 0, + Opcode_ae_mulasf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsaf2d32ra.hh.ll", ICLASS_AE_MULSAF2D32RA_HH_LL, + 0, + Opcode_ae_mulsaf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssf2d32ra.hh.ll", ICLASS_AE_MULSSF2D32RA_HH_LL, + 0, + Opcode_ae_mulssf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaaf2d32ra.hl.lh", ICLASS_AE_MULZAAF2D32RA_HL_LH, + 0, + Opcode_ae_mulzaaf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasf2d32ra.hl.lh", ICLASS_AE_MULZASF2D32RA_HL_LH, + 0, + Opcode_ae_mulzasf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzsaf2d32ra.hl.lh", ICLASS_AE_MULZSAF2D32RA_HL_LH, + 0, + Opcode_ae_mulzsaf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssf2d32ra.hl.lh", ICLASS_AE_MULZSSF2D32RA_HL_LH, + 0, + Opcode_ae_mulzssf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaaf2d32ra.hl.lh", ICLASS_AE_MULAAF2D32RA_HL_LH, + 0, + Opcode_ae_mulaaf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasf2d32ra.hl.lh", ICLASS_AE_MULASF2D32RA_HL_LH, + 0, + Opcode_ae_mulasf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsaf2d32ra.hl.lh", ICLASS_AE_MULSAF2D32RA_HL_LH, + 0, + Opcode_ae_mulsaf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssf2d32ra.hl.lh", ICLASS_AE_MULSSF2D32RA_HL_LH, + 0, + Opcode_ae_mulssf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulf32x2r.hh.ll", ICLASS_AE_MULF32X2R_HH_LL, + 0, + Opcode_ae_mulf32x2r_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaf32x2r.hh.ll", ICLASS_AE_MULAF32X2R_HH_LL, + 0, + Opcode_ae_mulaf32x2r_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsf32x2r.hh.ll", ICLASS_AE_MULSF32X2R_HH_LL, + 0, + Opcode_ae_mulsf32x2r_hh_ll_encode_fns, 0, 0 }, + { "ae_mulf32x2r.hl.lh", ICLASS_AE_MULF32X2R_HL_LH, + 0, + Opcode_ae_mulf32x2r_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaf32x2r.hl.lh", ICLASS_AE_MULAF32X2R_HL_LH, + 0, + Opcode_ae_mulaf32x2r_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsf32x2r.hl.lh", ICLASS_AE_MULSF32X2R_HL_LH, + 0, + Opcode_ae_mulsf32x2r_hl_lh_encode_fns, 0, 0 }, + { "ae_mulfc32w", ICLASS_AE_MULFC32W, + 0, + Opcode_ae_mulfc32w_encode_fns, 0, 0 }, + { "ae_mulafc32w", ICLASS_AE_MULAFC32W, + 0, + Opcode_ae_mulafc32w_encode_fns, 0, 0 }, + { "ae_mulfcj32w", ICLASS_AE_MULFCJ32W, + 0, + Opcode_ae_mulfcj32w_encode_fns, 0, 0 }, + { "ae_mulafcj32w", ICLASS_AE_MULAFCJ32W, + 0, + Opcode_ae_mulafcj32w_encode_fns, 0, 0 }, + { "ae_mulfcj32ras", ICLASS_AE_MULFCJ32RAS, + 0, + Opcode_ae_mulfcj32ras_encode_fns, 0, 0 }, + { "ae_mulafcj32ras", ICLASS_AE_MULAFCJ32RAS, + 0, + Opcode_ae_mulafcj32ras_encode_fns, 0, 0 }, + { "ae_mulf2p32x4rs", ICLASS_AE_MULF2P32X4RS, + 0, + Opcode_ae_mulf2p32x4rs_encode_fns, 0, 0 }, + { "ae_mulaf2p32x4rs", ICLASS_AE_MULAF2P32X4RS, + 0, + Opcode_ae_mulaf2p32x4rs_encode_fns, 0, 0 }, + { "ae_mulsf2p32x4rs", ICLASS_AE_MULSF2P32X4RS, + 0, + Opcode_ae_mulsf2p32x4rs_encode_fns, 0, 0 }, + { "ae_mulf2p32x4ras", ICLASS_AE_MULF2P32X4RAS, + 0, + Opcode_ae_mulf2p32x4ras_encode_fns, 0, 0 }, + { "ae_mulaf2p32x4ras", ICLASS_AE_MULAF2P32X4RAS, + 0, + Opcode_ae_mulaf2p32x4ras_encode_fns, 0, 0 }, + { "ae_mulsf2p32x4ras", ICLASS_AE_MULSF2P32X4RAS, + 0, + Opcode_ae_mulsf2p32x4ras_encode_fns, 0, 0 }, + { "ae_mulp32x2s", ICLASS_AE_MULP32X2S, + 0, + Opcode_ae_mulp32x2s_encode_fns, 0, 0 }, + { "ae_mul2p32x4s", ICLASS_AE_MUL2P32X4S, + 0, + Opcode_ae_mul2p32x4s_encode_fns, 0, 0 }, + { "ae_mul2p32x4", ICLASS_AE_MUL2P32X4, + 0, + Opcode_ae_mul2p32x4_encode_fns, 0, 0 }, + { "ae_mula2p32x4", ICLASS_AE_MULA2P32X4, + 0, + Opcode_ae_mula2p32x4_encode_fns, 0, 0 }, + { "ae_muls2p32x4", ICLASS_AE_MULS2P32X4, + 0, + Opcode_ae_muls2p32x4_encode_fns, 0, 0 }, + { "ae_mul2p32x4t", ICLASS_AE_MUL2P32X4T, + 0, + Opcode_ae_mul2p32x4t_encode_fns, 0, 0 }, + { "ae_mula2p32x4t", ICLASS_AE_MULA2P32X4T, + 0, + Opcode_ae_mula2p32x4t_encode_fns, 0, 0 }, + { "ae_muls2p32x4t", ICLASS_AE_MULS2P32X4T, + 0, + Opcode_ae_muls2p32x4t_encode_fns, 0, 0 }, + { "ae_mulzaa32x2.hh.ll", ICLASS_AE_MULZAA32X2_HH_LL, + 0, + Opcode_ae_mulzaa32x2_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzss32x2.hh.ll", ICLASS_AE_MULZSS32X2_HH_LL, + 0, + Opcode_ae_mulzss32x2_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaa32x2.hh.ll", ICLASS_AE_MULAA32X2_HH_LL, + 0, + Opcode_ae_mulaa32x2_hh_ll_encode_fns, 0, 0 }, + { "ae_mulss32x2.hh.ll", ICLASS_AE_MULSS32X2_HH_LL, + 0, + Opcode_ae_mulss32x2_hh_ll_encode_fns, 0, 0 }, + { "ae_mulcj32", ICLASS_AE_MULCJ32, + 0, + Opcode_ae_mulcj32_encode_fns, 0, 0 }, + { "ae_mulacj32", ICLASS_AE_MULACJ32, + 0, + Opcode_ae_mulacj32_encode_fns, 0, 0 }, + { "ae_muladdf32rs", ICLASS_AE_MULADDF32RS, + 0, + Opcode_ae_muladdf32rs_encode_fns, 0, 0 }, + { "ae_muladdf32ras", ICLASS_AE_MULADDF32RAS, + 0, + Opcode_ae_muladdf32ras_encode_fns, 0, 0 }, + { "ae_mulsubf32rs", ICLASS_AE_MULSUBF32RS, + 0, + Opcode_ae_mulsubf32rs_encode_fns, 0, 0 }, + { "ae_mulsubf32ras", ICLASS_AE_MULSUBF32RAS, + 0, + Opcode_ae_mulsubf32ras_encode_fns, 0, 0 }, + { "ae_mulfc32ra", ICLASS_AE_MULFC32RA, + 0, + Opcode_ae_mulfc32ra_encode_fns, 0, 0 }, + { "ae_mulafc32ra", ICLASS_AE_MULAFC32RA, + 0, + Opcode_ae_mulafc32ra_encode_fns, 0, 0 }, + { "ae_mulcj32w", ICLASS_AE_MULCJ32W, + 0, + Opcode_ae_mulcj32w_encode_fns, 0, 0 }, + { "ae_mulacj32w", ICLASS_AE_MULACJ32W, + 0, + Opcode_ae_mulacj32w_encode_fns, 0, 0 }, + { "ae_mulc32w", ICLASS_AE_MULC32W, + 0, + Opcode_ae_mulc32w_encode_fns, 0, 0 }, + { "ae_mulac32w", ICLASS_AE_MULAC32W, + 0, + Opcode_ae_mulac32w_encode_fns, 0, 0 }, + { "ae_mulf2d32x2ws", ICLASS_AE_MULF2D32X2WS, + 0, + Opcode_ae_mulf2d32x2ws_encode_fns, 0, 0 }, + { "ae_mulzaaaa2q16", ICLASS_AE_MULZAAAA2Q16, + 0, + Opcode_ae_mulzaaaa2q16_encode_fns, 0, 0 }, + { "ae_mulaaaa2q16", ICLASS_AE_MULAAAA2Q16, + 0, + Opcode_ae_mulaaaa2q16_encode_fns, 0, 0 }, + { "ae_mulp16s.h", ICLASS_AE_MULP16S_H, + 0, + Opcode_ae_mulp16s_h_encode_fns, 0, 0 }, + { "ae_mulap16s.h", ICLASS_AE_MULAP16S_H, + 0, + Opcode_ae_mulap16s_h_encode_fns, 0, 0 }, + { "ae_mulsp16s.h", ICLASS_AE_MULSP16S_H, + 0, + Opcode_ae_mulsp16s_h_encode_fns, 0, 0 }, + { "ae_mulp16s.l", ICLASS_AE_MULP16S_L, + 0, + Opcode_ae_mulp16s_l_encode_fns, 0, 0 }, + { "ae_mulap16s.l", ICLASS_AE_MULAP16S_L, + 0, + Opcode_ae_mulap16s_l_encode_fns, 0, 0 }, + { "ae_mulsp16s.l", ICLASS_AE_MULSP16S_L, + 0, + Opcode_ae_mulsp16s_l_encode_fns, 0, 0 }, + { "ae_mulc16w.h", ICLASS_AE_MULC16W_H, + 0, + Opcode_ae_mulc16w_h_encode_fns, 0, 0 }, + { "ae_mulac16w.h", ICLASS_AE_MULAC16W_H, + 0, + Opcode_ae_mulac16w_h_encode_fns, 0, 0 }, + { "ae_mulc16w.l", ICLASS_AE_MULC16W_L, + 0, + Opcode_ae_mulc16w_l_encode_fns, 0, 0 }, + { "ae_mulac16w.l", ICLASS_AE_MULAC16W_L, + 0, + Opcode_ae_mulac16w_l_encode_fns, 0, 0 }, + { "ae_mul2c16s", ICLASS_AE_MUL2C16S, + 0, + Opcode_ae_mul2c16s_encode_fns, 0, 0 }, + { "ae_mula2c16s", ICLASS_AE_MULA2C16S, + 0, + Opcode_ae_mula2c16s_encode_fns, 0, 0 }, + { "ae_mulfc16s", ICLASS_AE_MULFC16S, + 0, + Opcode_ae_mulfc16s_encode_fns, 0, 0 }, + { "ae_mulafc16s", ICLASS_AE_MULAFC16S, + 0, + Opcode_ae_mulafc16s_encode_fns, 0, 0 }, + { "ae_mulfcj16s", ICLASS_AE_MULFCJ16S, + 0, + Opcode_ae_mulfcj16s_encode_fns, 0, 0 }, + { "ae_mulafcj16s", ICLASS_AE_MULAFCJ16S, + 0, + Opcode_ae_mulafcj16s_encode_fns, 0, 0 }, + { "ae_mulfcj16ras", ICLASS_AE_MULFCJ16RAS, + 0, + Opcode_ae_mulfcj16ras_encode_fns, 0, 0 }, + { "ae_mulafcj16ras", ICLASS_AE_MULAFCJ16RAS, + 0, + Opcode_ae_mulafcj16ras_encode_fns, 0, 0 }, + { "ae_mulc16s", ICLASS_AE_MULC16S, + 0, + Opcode_ae_mulc16s_encode_fns, 0, 0 }, + { "ae_mulac16s", ICLASS_AE_MULAC16S, + 0, + Opcode_ae_mulac16s_encode_fns, 0, 0 }, + { "ae_mulfp16x4rs", ICLASS_AE_MULFP16X4RS, + 0, + Opcode_ae_mulfp16x4rs_encode_fns, 0, 0 }, + { "ae_mulfd16x16x4ras", ICLASS_AE_MULFD16X16X4RAS, + 0, + Opcode_ae_mulfd16x16x4ras_encode_fns, 0, 0 }, + { "ae_mulp16x16x4s", ICLASS_AE_MULP16X16X4S, + 0, + Opcode_ae_mulp16x16x4s_encode_fns, 0, 0 }, + { "ae_mulap16x16x4s", ICLASS_AE_MULAP16X16X4S, + 0, + Opcode_ae_mulap16x16x4s_encode_fns, 0, 0 }, + { "ae_mulsp16x16x4s", ICLASS_AE_MULSP16X16X4S, + 0, + Opcode_ae_mulsp16x16x4s_encode_fns, 0, 0 }, + { "ae_mulzaa2d16ss.hh_ll", ICLASS_AE_MULZAA2D16SS_HH_LL, + 0, + Opcode_ae_mulzaa2d16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaa2d16ss.hl_lh", ICLASS_AE_MULZAA2D16SS_HL_LH, + 0, + Opcode_ae_mulzaa2d16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzss2d16ss.hh_ll", ICLASS_AE_MULZSS2D16SS_HH_LL, + 0, + Opcode_ae_mulzss2d16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzss2d16ss.hl_lh", ICLASS_AE_MULZSS2D16SS_HL_LH, + 0, + Opcode_ae_mulzss2d16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaa2d16ss.hh_ll", ICLASS_AE_MULAA2D16SS_HH_LL, + 0, + Opcode_ae_mulaa2d16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaa2d16ss.hl_lh", ICLASS_AE_MULAA2D16SS_HL_LH, + 0, + Opcode_ae_mulaa2d16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulss2d16ss.hh_ll", ICLASS_AE_MULSS2D16SS_HH_LL, + 0, + Opcode_ae_mulss2d16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulss2d16ss.hl_lh", ICLASS_AE_MULSS2D16SS_HL_LH, + 0, + Opcode_ae_mulss2d16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaafd16ss.hh_ll", ICLASS_AE_MULZAAFD16SS_HH_LL, + 0, + Opcode_ae_mulzaafd16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaafd16ss.hl_lh", ICLASS_AE_MULZAAFD16SS_HL_LH, + 0, + Opcode_ae_mulzaafd16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssfd16ss.hh_ll", ICLASS_AE_MULZSSFD16SS_HH_LL, + 0, + Opcode_ae_mulzssfd16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssfd16ss.hl_lh", ICLASS_AE_MULZSSFD16SS_HL_LH, + 0, + Opcode_ae_mulzssfd16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaafd16ss.hh_ll", ICLASS_AE_MULAAFD16SS_HH_LL, + 0, + Opcode_ae_mulaafd16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaafd16ss.hl_lh", ICLASS_AE_MULAAFD16SS_HL_LH, + 0, + Opcode_ae_mulaafd16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssfd16ss.hh_ll", ICLASS_AE_MULSSFD16SS_HH_LL, + 0, + Opcode_ae_mulssfd16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssfd16ss.hl_lh", ICLASS_AE_MULSSFD16SS_HL_LH, + 0, + Opcode_ae_mulssfd16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulfd16x16x4ws", ICLASS_AE_MULFD16X16X4WS, + 0, + Opcode_ae_mulfd16x16x4ws_encode_fns, 0, 0 }, + { "ae_mulzaaaa2q16x8", ICLASS_AE_MULZAAAA2Q16X8, + 0, + Opcode_ae_mulzaaaa2q16x8_encode_fns, 0, 0 }, + { "ae_mulaaaa2q16x8", ICLASS_AE_MULAAAA2Q16X8, + 0, + Opcode_ae_mulaaaa2q16x8_encode_fns, 0, 0 }, + { "ae_mulzaaaa2q8", ICLASS_AE_MULZAAAA2Q8, + 0, + Opcode_ae_mulzaaaa2q8_encode_fns, 0, 0 }, + { "ae_mulaaaa2q8", ICLASS_AE_MULAAAA2Q8, + 0, + Opcode_ae_mulaaaa2q8_encode_fns, 0, 0 }, + { "ae_mulc32x16w.h", ICLASS_AE_MULC32X16W_H, + 0, + Opcode_ae_mulc32x16w_h_encode_fns, 0, 0 }, + { "ae_mulac32x16w.h", ICLASS_AE_MULAC32X16W_H, + 0, + Opcode_ae_mulac32x16w_h_encode_fns, 0, 0 }, + { "ae_mulc32x16w.l", ICLASS_AE_MULC32X16W_L, + 0, + Opcode_ae_mulc32x16w_l_encode_fns, 0, 0 }, + { "ae_mulac32x16w.l", ICLASS_AE_MULAC32X16W_L, + 0, + Opcode_ae_mulac32x16w_l_encode_fns, 0, 0 }, + { "ae_mulpc32x16x2", ICLASS_AE_MULPC32X16X2, + 0, + Opcode_ae_mulpc32x16x2_encode_fns, 0, 0 }, + { "ae_mulapc32x16x2", ICLASS_AE_MULAPC32X16X2, + 0, + Opcode_ae_mulapc32x16x2_encode_fns, 0, 0 }, + { "ae_mulfp32x16.h", ICLASS_AE_MULFP32X16_H, + 0, + Opcode_ae_mulfp32x16_h_encode_fns, 0, 0 }, + { "ae_mulafp32x16.h", ICLASS_AE_MULAFP32X16_H, + 0, + Opcode_ae_mulafp32x16_h_encode_fns, 0, 0 }, + { "ae_mulsfp32x16.h", ICLASS_AE_MULSFP32X16_H, + 0, + Opcode_ae_mulsfp32x16_h_encode_fns, 0, 0 }, + { "ae_mulfp32x16.l", ICLASS_AE_MULFP32X16_L, + 0, + Opcode_ae_mulfp32x16_l_encode_fns, 0, 0 }, + { "ae_mulafp32x16.l", ICLASS_AE_MULAFP32X16_L, + 0, + Opcode_ae_mulafp32x16_l_encode_fns, 0, 0 }, + { "ae_mulsfp32x16.l", ICLASS_AE_MULSFP32X16_L, + 0, + Opcode_ae_mulsfp32x16_l_encode_fns, 0, 0 }, + { "ae_mulfc32x16w.h", ICLASS_AE_MULFC32X16W_H, + 0, + Opcode_ae_mulfc32x16w_h_encode_fns, 0, 0 }, + { "ae_mulafc32x16w.h", ICLASS_AE_MULAFC32X16W_H, + 0, + Opcode_ae_mulafc32x16w_h_encode_fns, 0, 0 }, + { "ae_mulfc32x16w.l", ICLASS_AE_MULFC32X16W_L, + 0, + Opcode_ae_mulfc32x16w_l_encode_fns, 0, 0 }, + { "ae_mulafc32x16w.l", ICLASS_AE_MULAFC32X16W_L, + 0, + Opcode_ae_mulafc32x16w_l_encode_fns, 0, 0 }, + { "ae_mulfcj32x16w.h", ICLASS_AE_MULFCJ32X16W_H, + 0, + Opcode_ae_mulfcj32x16w_h_encode_fns, 0, 0 }, + { "ae_mulafcj32x16w.h", ICLASS_AE_MULAFCJ32X16W_H, + 0, + Opcode_ae_mulafcj32x16w_h_encode_fns, 0, 0 }, + { "ae_mulfcj32x16w.l", ICLASS_AE_MULFCJ32X16W_L, + 0, + Opcode_ae_mulfcj32x16w_l_encode_fns, 0, 0 }, + { "ae_mulafcj32x16w.l", ICLASS_AE_MULAFCJ32X16W_L, + 0, + Opcode_ae_mulafcj32x16w_l_encode_fns, 0, 0 }, + { "ae_mulf2p32x16x4ras", ICLASS_AE_MULF2P32X16X4RAS, + 0, + Opcode_ae_mulf2p32x16x4ras_encode_fns, 0, 0 }, + { "ae_mulaf2p32x16x4ras", ICLASS_AE_MULAF2P32X16X4RAS, + 0, + Opcode_ae_mulaf2p32x16x4ras_encode_fns, 0, 0 }, + { "ae_mulsf2p32x16x4ras", ICLASS_AE_MULSF2P32X16X4RAS, + 0, + Opcode_ae_mulsf2p32x16x4ras_encode_fns, 0, 0 }, + { "ae_mulf2p32x16x4rs", ICLASS_AE_MULF2P32X16X4RS, + 0, + Opcode_ae_mulf2p32x16x4rs_encode_fns, 0, 0 }, + { "ae_mulaf2p32x16x4rs", ICLASS_AE_MULAF2P32X16X4RS, + 0, + Opcode_ae_mulaf2p32x16x4rs_encode_fns, 0, 0 }, + { "ae_mulsf2p32x16x4rs", ICLASS_AE_MULSF2P32X16X4RS, + 0, + Opcode_ae_mulsf2p32x16x4rs_encode_fns, 0, 0 }, + { "ae_mulf2p32x16x4s", ICLASS_AE_MULF2P32X16X4S, + 0, + Opcode_ae_mulf2p32x16x4s_encode_fns, 0, 0 }, + { "ae_mulaf2p32x16x4s", ICLASS_AE_MULAF2P32X16X4S, + 0, + Opcode_ae_mulaf2p32x16x4s_encode_fns, 0, 0 }, + { "ae_mulsf2p32x16x4s", ICLASS_AE_MULSF2P32X16X4S, + 0, + Opcode_ae_mulsf2p32x16x4s_encode_fns, 0, 0 }, + { "ae_mulfpc32x16x2ras", ICLASS_AE_MULFPC32X16X2RAS, + 0, + Opcode_ae_mulfpc32x16x2ras_encode_fns, 0, 0 }, + { "ae_mulafpc32x16x2ras", ICLASS_AE_MULAFPC32X16X2RAS, + 0, + Opcode_ae_mulafpc32x16x2ras_encode_fns, 0, 0 }, + { "ae_mulfpcj32x16x2ras", ICLASS_AE_MULFPCJ32X16X2RAS, + 0, + Opcode_ae_mulfpcj32x16x2ras_encode_fns, 0, 0 }, + { "ae_mulafpcj32x16x2ras", ICLASS_AE_MULAFPCJ32X16X2RAS, + 0, + Opcode_ae_mulafpcj32x16x2ras_encode_fns, 0, 0 }, + { "ae_mulzaaaa2q32x16", ICLASS_AE_MULZAAAA2Q32X16, + 0, + Opcode_ae_mulzaaaa2q32x16_encode_fns, 0, 0 }, + { "ae_mulaaaa2q32x16", ICLASS_AE_MULAAAA2Q32X16, + 0, + Opcode_ae_mulaaaa2q32x16_encode_fns, 0, 0 }, + { "ae_mul2q32x16.fir.h", ICLASS_AE_MUL2Q32X16_FIR_H, + 0, + Opcode_ae_mul2q32x16_fir_h_encode_fns, 0, 0 }, + { "ae_mula2q32x16.fir.h", ICLASS_AE_MULA2Q32X16_FIR_H, + 0, + Opcode_ae_mula2q32x16_fir_h_encode_fns, 0, 0 }, + { "ae_mul2q32x16.fir.l", ICLASS_AE_MUL2Q32X16_FIR_L, + 0, + Opcode_ae_mul2q32x16_fir_l_encode_fns, 0, 0 }, + { "ae_mula2q32x16.fir.l", ICLASS_AE_MULA2Q32X16_FIR_L, + 0, + Opcode_ae_mula2q32x16_fir_l_encode_fns, 0, 0 }, + { "ae_srai8", ICLASS_AE_SRAI8, + 0, + Opcode_ae_srai8_encode_fns, 0, 0 }, + { "ae_srai8r", ICLASS_AE_SRAI8R, + 0, + Opcode_ae_srai8r_encode_fns, 0, 0 }, + { "ae_srli8", ICLASS_AE_SRLI8, + 0, + Opcode_ae_srli8_encode_fns, 0, 0 }, + { "ae_slai8", ICLASS_AE_SLAI8, + 0, + Opcode_ae_slai8_encode_fns, 0, 0 }, + { "ae_slai8s", ICLASS_AE_SLAI8S, + 0, + Opcode_ae_slai8s_encode_fns, 0, 0 }, + { "ae_slaa8", ICLASS_AE_SLAA8, + 0, + Opcode_ae_slaa8_encode_fns, 0, 0 }, + { "ae_srla8", ICLASS_AE_SRLA8, + 0, + Opcode_ae_srla8_encode_fns, 0, 0 }, + { "ae_slaa8s", ICLASS_AE_SLAA8S, + 0, + Opcode_ae_slaa8s_encode_fns, 0, 0 }, + { "ae_sraa8rs", ICLASS_AE_SRAA8RS, + 0, + Opcode_ae_sraa8rs_encode_fns, 0, 0 }, + { "ae_sraa8s", ICLASS_AE_SRAA8S, + 0, + Opcode_ae_sraa8s_encode_fns, 0, 0 }, + { "ae_srli16", ICLASS_AE_SRLI16, + 0, + Opcode_ae_srli16_encode_fns, 0, 0 }, + { "ae_slai16", ICLASS_AE_SLAI16, + 0, + Opcode_ae_slai16_encode_fns, 0, 0 }, + { "ae_slaa16", ICLASS_AE_SLAA16, + 0, + Opcode_ae_slaa16_encode_fns, 0, 0 }, + { "ae_srla16", ICLASS_AE_SRLA16, + 0, + Opcode_ae_srla16_encode_fns, 0, 0 }, + { "ae_srai16sym", ICLASS_AE_SRAI16SYM, + 0, + Opcode_ae_srai16sym_encode_fns, 0, 0 }, + { "ae_sraa16syms", ICLASS_AE_SRAA16SYMS, + 0, + Opcode_ae_sraa16syms_encode_fns, 0, 0 }, + { "ae_srai32sym", ICLASS_AE_SRAI32SYM, + 0, + Opcode_ae_srai32sym_encode_fns, 0, 0 }, + { "ae_sraa32syms", ICLASS_AE_SRAA32SYMS, + 0, + Opcode_ae_sraa32syms_encode_fns, 0, 0 }, + { "ae_srav16rs", ICLASS_AE_SRAV16RS, + 0, + Opcode_ae_srav16rs_encode_fns, 0, 0 }, + { "ae_srav32rs", ICLASS_AE_SRAV32RS, + 0, + Opcode_ae_srav32rs_encode_fns, 0, 0 }, + { "ae_cvti32x4f8.h", ICLASS_AE_CVTI32X4F8_H, + 0, + Opcode_ae_cvti32x4f8_h_encode_fns, 0, 0 }, + { "ae_cvti32x4f8.l", ICLASS_AE_CVTI32X4F8_L, + 0, + Opcode_ae_cvti32x4f8_l_encode_fns, 0, 0 }, + { "ae_cvti32x4f8s.h", ICLASS_AE_CVTI32X4F8S_H, + 0, + Opcode_ae_cvti32x4f8s_h_encode_fns, 0, 0 }, + { "ae_cvti32x4f8s.l", ICLASS_AE_CVTI32X4F8S_L, + 0, + Opcode_ae_cvti32x4f8s_l_encode_fns, 0, 0 }, + { "ae_cvta32x4f8.h", ICLASS_AE_CVTA32X4F8_H, + 0, + Opcode_ae_cvta32x4f8_h_encode_fns, 0, 0 }, + { "ae_cvta32x4f8.l", ICLASS_AE_CVTA32X4F8_L, + 0, + Opcode_ae_cvta32x4f8_l_encode_fns, 0, 0 }, + { "ae_cvta32x4f8s.h", ICLASS_AE_CVTA32X4F8S_H, + 0, + Opcode_ae_cvta32x4f8s_h_encode_fns, 0, 0 }, + { "ae_cvta32x4f8s.l", ICLASS_AE_CVTA32X4F8S_L, + 0, + Opcode_ae_cvta32x4f8s_l_encode_fns, 0, 0 }, + { "ae_cvti32x4f8u.h", ICLASS_AE_CVTI32X4F8U_H, + 0, + Opcode_ae_cvti32x4f8u_h_encode_fns, 0, 0 }, + { "ae_cvti32x4f8u.l", ICLASS_AE_CVTI32X4F8U_L, + 0, + Opcode_ae_cvti32x4f8u_l_encode_fns, 0, 0 }, + { "ae_cvti32x4f8us.h", ICLASS_AE_CVTI32X4F8US_H, + 0, + Opcode_ae_cvti32x4f8us_h_encode_fns, 0, 0 }, + { "ae_cvti32x4f8us.l", ICLASS_AE_CVTI32X4F8US_L, + 0, + Opcode_ae_cvti32x4f8us_l_encode_fns, 0, 0 }, + { "ae_cvta32x4f8u.h", ICLASS_AE_CVTA32X4F8U_H, + 0, + Opcode_ae_cvta32x4f8u_h_encode_fns, 0, 0 }, + { "ae_cvta32x4f8u.l", ICLASS_AE_CVTA32X4F8U_L, + 0, + Opcode_ae_cvta32x4f8u_l_encode_fns, 0, 0 }, + { "ae_cvta32x4f8us.h", ICLASS_AE_CVTA32X4F8US_H, + 0, + Opcode_ae_cvta32x4f8us_h_encode_fns, 0, 0 }, + { "ae_cvta32x4f8us.l", ICLASS_AE_CVTA32X4F8US_L, + 0, + Opcode_ae_cvta32x4f8us_l_encode_fns, 0, 0 }, + { "ae_cvti32x4f16", ICLASS_AE_CVTI32X4F16, + 0, + Opcode_ae_cvti32x4f16_encode_fns, 0, 0 }, + { "ae_cvti32x4f16s", ICLASS_AE_CVTI32X4F16S, + 0, + Opcode_ae_cvti32x4f16s_encode_fns, 0, 0 }, + { "ae_cvta32x4f16", ICLASS_AE_CVTA32X4F16, + 0, + Opcode_ae_cvta32x4f16_encode_fns, 0, 0 }, + { "ae_cvta32x4f16s", ICLASS_AE_CVTA32X4F16S, + 0, + Opcode_ae_cvta32x4f16s_encode_fns, 0, 0 }, + { "ae_cvti32x4f16u", ICLASS_AE_CVTI32X4F16U, + 0, + Opcode_ae_cvti32x4f16u_encode_fns, 0, 0 }, + { "ae_cvti32x4f16us", ICLASS_AE_CVTI32X4F16US, + 0, + Opcode_ae_cvti32x4f16us_encode_fns, 0, 0 }, + { "ae_cvta32x4f16u", ICLASS_AE_CVTA32X4F16U, + 0, + Opcode_ae_cvta32x4f16u_encode_fns, 0, 0 }, + { "ae_cvta32x4f16us", ICLASS_AE_CVTA32X4F16US, + 0, + Opcode_ae_cvta32x4f16us_encode_fns, 0, 0 }, + { "ae_cvti16x4x2f8", ICLASS_AE_CVTI16X4X2F8, + 0, + Opcode_ae_cvti16x4x2f8_encode_fns, 0, 0 }, + { "ae_cvti16x4x2f8s", ICLASS_AE_CVTI16X4X2F8S, + 0, + Opcode_ae_cvti16x4x2f8s_encode_fns, 0, 0 }, + { "ae_cvta16x4x2f8", ICLASS_AE_CVTA16X4X2F8, + 0, + Opcode_ae_cvta16x4x2f8_encode_fns, 0, 0 }, + { "ae_cvta16x4x2f8s", ICLASS_AE_CVTA16X4X2F8S, + 0, + Opcode_ae_cvta16x4x2f8s_encode_fns, 0, 0 }, + { "ae_cvti16x4x2f8u", ICLASS_AE_CVTI16X4X2F8U, + 0, + Opcode_ae_cvti16x4x2f8u_encode_fns, 0, 0 }, + { "ae_cvti16x4x2f8us", ICLASS_AE_CVTI16X4X2F8US, + 0, + Opcode_ae_cvti16x4x2f8us_encode_fns, 0, 0 }, + { "ae_cvta16x4x2f8u", ICLASS_AE_CVTA16X4X2F8U, + 0, + Opcode_ae_cvta16x4x2f8u_encode_fns, 0, 0 }, + { "ae_cvta16x4x2f8us", ICLASS_AE_CVTA16X4X2F8US, + 0, + Opcode_ae_cvta16x4x2f8us_encode_fns, 0, 0 }, + { "ae_sel8x8", ICLASS_AE_SEL8X8, + 0, + Opcode_ae_sel8x8_encode_fns, 0, 0 }, + { "ae_shfl8x8", ICLASS_AE_SHFL8X8, + 0, + Opcode_ae_shfl8x8_encode_fns, 0, 0 }, + { "ae_sel16x4", ICLASS_AE_SEL16X4, + 0, + Opcode_ae_sel16x4_encode_fns, 0, 0 }, + { "ae_shfl16x4", ICLASS_AE_SHFL16X4, + 0, + Opcode_ae_shfl16x4_encode_fns, 0, 0 }, + { "ae_dsel8x8", ICLASS_AE_DSEL8X8, + 0, + Opcode_ae_dsel8x8_encode_fns, 0, 0 }, + { "ae_dsel16x4", ICLASS_AE_DSEL16X4, + 0, + Opcode_ae_dsel16x4_encode_fns, 0, 0 }, + { "ae_sel8x8i", ICLASS_AE_SEL8X8I, + 0, + Opcode_ae_sel8x8i_encode_fns, 0, 0 }, + { "ae_rmax8x8", ICLASS_AE_RMAX8X8, + 0, + Opcode_ae_rmax8x8_encode_fns, 0, 0 }, + { "ae_rmin8x8", ICLASS_AE_RMIN8X8, + 0, + Opcode_ae_rmin8x8_encode_fns, 0, 0 }, + { "ae_rmax16x4", ICLASS_AE_RMAX16X4, + 0, + Opcode_ae_rmax16x4_encode_fns, 0, 0 }, + { "ae_rmin16x4", ICLASS_AE_RMIN16X4, + 0, + Opcode_ae_rmin16x4_encode_fns, 0, 0 }, + { "ae_sort16x4", ICLASS_AE_SORT16X4, + 0, + Opcode_ae_sort16x4_encode_fns, 0, 0 }, + { "ae_radd8x8.h", ICLASS_AE_RADD8X8_H, + 0, + Opcode_ae_radd8x8_h_encode_fns, 0, 0 }, + { "ae_radda8x8.h", ICLASS_AE_RADDA8X8_H, + 0, + Opcode_ae_radda8x8_h_encode_fns, 0, 0 }, + { "ae_radd8x8.l", ICLASS_AE_RADD8X8_L, + 0, + Opcode_ae_radd8x8_l_encode_fns, 0, 0 }, + { "ae_radda8x8.l", ICLASS_AE_RADDA8X8_L, + 0, + Opcode_ae_radda8x8_l_encode_fns, 0, 0 }, + { "ae_radd16x4", ICLASS_AE_RADD16X4, + 0, + Opcode_ae_radd16x4_encode_fns, 0, 0 }, + { "ae_radda16x4", ICLASS_AE_RADDA16X4, + 0, + Opcode_ae_radda16x4_encode_fns, 0, 0 }, + { "ae_bmax8x8.h", ICLASS_AE_BMAX8X8_H, + 0, + Opcode_ae_bmax8x8_h_encode_fns, 0, 0 }, + { "ae_bmax8x8.l", ICLASS_AE_BMAX8X8_L, + 0, + Opcode_ae_bmax8x8_l_encode_fns, 0, 0 }, + { "ae_bmin8x8.h", ICLASS_AE_BMIN8X8_H, + 0, + Opcode_ae_bmin8x8_h_encode_fns, 0, 0 }, + { "ae_bmin8x8.l", ICLASS_AE_BMIN8X8_L, + 0, + Opcode_ae_bmin8x8_l_encode_fns, 0, 0 }, + { "ae_bmax16x4", ICLASS_AE_BMAX16X4, + 0, + Opcode_ae_bmax16x4_encode_fns, 0, 0 }, + { "ae_bmin16x4", ICLASS_AE_BMIN16X4, + 0, + Opcode_ae_bmin16x4_encode_fns, 0, 0 }, + { "ae_bmax32x2", ICLASS_AE_BMAX32X2, + 0, + Opcode_ae_bmax32x2_encode_fns, 0, 0 }, + { "ae_bmin32x2", ICLASS_AE_BMIN32X2, + 0, + Opcode_ae_bmin32x2_encode_fns, 0, 0 }, + { "ae_addinv16s", ICLASS_AE_ADDINV16S, + 0, + Opcode_ae_addinv16s_encode_fns, 0, 0 }, + { "ae_addinv32s", ICLASS_AE_ADDINV32S, + 0, + Opcode_ae_addinv32s_encode_fns, 0, 0 }, + { "ae_movt16x8", ICLASS_AE_MOVT16X8, + 0, + Opcode_ae_movt16x8_encode_fns, 0, 0 }, + { "ae_movt8x16.h", ICLASS_AE_MOVT8X16_H, + 0, + Opcode_ae_movt8x16_h_encode_fns, 0, 0 }, + { "ae_movt8x16.l", ICLASS_AE_MOVT8X16_L, + 0, + Opcode_ae_movt8x16_l_encode_fns, 0, 0 }, + { "ae_movbd1x4", ICLASS_AE_MOVBD1X4, + 0, + Opcode_ae_movbd1x4_encode_fns, 0, 0 }, + { "ae_movbd1x2", ICLASS_AE_MOVBD1X2, + 0, + Opcode_ae_movbd1x2_encode_fns, 0, 0 }, + { "ae_movneg32s_t", ICLASS_AE_MOVNEG32S_T, + 0, + Opcode_ae_movneg32s_t_encode_fns, 0, 0 }, + { "ae_movdext", ICLASS_AE_MOVDEXT, + 0, + Opcode_ae_movdext_encode_fns, 0, 0 }, + { "ae_movadext.h", ICLASS_AE_MOVADEXT_H, + 0, + Opcode_ae_movadext_h_encode_fns, 0, 0 }, + { "ae_movadext.l", ICLASS_AE_MOVADEXT_L, + 0, + Opcode_ae_movadext_l_encode_fns, 0, 0 }, + { "ae_nsa16x4", ICLASS_AE_NSA16X4, + 0, + Opcode_ae_nsa16x4_encode_fns, 0, 0 }, + { "ae_nsaz32x4", ICLASS_AE_NSAZ32X4, + 0, + Opcode_ae_nsaz32x4_encode_fns, 0, 0 }, + { "ae_nsa32x4", ICLASS_AE_NSA32X4, + 0, + Opcode_ae_nsa32x4_encode_fns, 0, 0 }, + { "ae_trunci16x4f32s", ICLASS_AE_TRUNCI16X4F32S, + 0, + Opcode_ae_trunci16x4f32s_encode_fns, 0, 0 }, + { "ae_trunci16x4f64s", ICLASS_AE_TRUNCI16X4F64S, + 0, + Opcode_ae_trunci16x4f64s_encode_fns, 0, 0 }, + { "ae_trunca16x4f32s", ICLASS_AE_TRUNCA16X4F32S, + 0, + Opcode_ae_trunca16x4f32s_encode_fns, 0, 0 }, + { "ae_trunca16x4f64s", ICLASS_AE_TRUNCA16X4F64S, + 0, + Opcode_ae_trunca16x4f64s_encode_fns, 0, 0 }, + { "ae_addc32", ICLASS_AE_ADDC32, + 0, + Opcode_ae_addc32_encode_fns, 0, 0 }, + { "ae_subc32", ICLASS_AE_SUBC32, + 0, + Opcode_ae_subc32_encode_fns, 0, 0 }, + { "ae_addc32u", ICLASS_AE_ADDC32U, + 0, + Opcode_ae_addc32u_encode_fns, 0, 0 }, + { "ae_subc32u", ICLASS_AE_SUBC32U, + 0, + Opcode_ae_subc32u_encode_fns, 0, 0 }, + { "ae_expadd16.h", ICLASS_AE_EXPADD16_H, + 0, + Opcode_ae_expadd16_h_encode_fns, 0, 0 }, + { "ae_expsub16.h", ICLASS_AE_EXPSUB16_H, + 0, + Opcode_ae_expsub16_h_encode_fns, 0, 0 }, + { "ae_expadd16.l", ICLASS_AE_EXPADD16_L, + 0, + Opcode_ae_expadd16_l_encode_fns, 0, 0 }, + { "ae_expsub16.l", ICLASS_AE_EXPSUB16_L, + 0, + Opcode_ae_expsub16_l_encode_fns, 0, 0 }, + { "ae_addcexp32.h", ICLASS_AE_ADDCEXP32_H, + 0, + Opcode_ae_addcexp32_h_encode_fns, 0, 0 }, + { "ae_addcexp32.l", ICLASS_AE_ADDCEXP32_L, + 0, + Opcode_ae_addcexp32_l_encode_fns, 0, 0 }, + { "ae_calcrng16", ICLASS_AE_CALCRNG16, + 0, + Opcode_ae_calcrng16_encode_fns, 0, 0 }, + { "ae_calcrng32", ICLASS_AE_CALCRNG32, + 0, + Opcode_ae_calcrng32_encode_fns, 0, 0 }, + { "ae_rng32x4", ICLASS_AE_RNG32X4, + 0, + Opcode_ae_rng32x4_encode_fns, 0, 0 }, + { "ae_lav8x8x2_xp", ICLASS_AE_LAV8X8X2_XP, + 0, + Opcode_ae_lav8x8x2_xp_encode_fns, 1, Opcode_ae_lav8x8x2_xp_funcUnit_uses }, + { "ae_lav16x4x2_xp", ICLASS_AE_LAV16X4X2_XP, + 0, + Opcode_ae_lav16x4x2_xp_encode_fns, 1, Opcode_ae_lav16x4x2_xp_funcUnit_uses }, + { "ae_sav8x8x2_xp", ICLASS_AE_SAV8X8X2_XP, + 0, + Opcode_ae_sav8x8x2_xp_encode_fns, 1, Opcode_ae_sav8x8x2_xp_funcUnit_uses }, + { "ae_sav16x4x2_xp", ICLASS_AE_SAV16X4X2_XP, + 0, + Opcode_ae_sav16x4x2_xp_encode_fns, 1, Opcode_ae_sav16x4x2_xp_funcUnit_uses }, + { "ae_movzbvcdr", ICLASS_AE_MOVZBVCDR, + 0, + Opcode_ae_movzbvcdr_encode_fns, 0, 0 }, + { "ae_movdrzbvc", ICLASS_AE_MOVDRZBVC, + 0, + Opcode_ae_movdrzbvc_encode_fns, 0, 0 }, + { "ae_lavunsqz8x8_xp", ICLASS_AE_LAVUNSQZ8X8_XP, + 0, + Opcode_ae_lavunsqz8x8_xp_encode_fns, 1, Opcode_ae_lavunsqz8x8_xp_funcUnit_uses }, + { "ae_lavunsqz16x4_xp", ICLASS_AE_LAVUNSQZ16X4_XP, + 0, + Opcode_ae_lavunsqz16x4_xp_encode_fns, 1, Opcode_ae_lavunsqz16x4_xp_funcUnit_uses }, + { "ae_mul8q8x8", ICLASS_AE_MUL8Q8X8, + 0, + Opcode_ae_mul8q8x8_encode_fns, 0, 0 }, + { "ae_mula8q8x8", ICLASS_AE_MULA8Q8X8, + 0, + Opcode_ae_mula8q8x8_encode_fns, 0, 0 }, + { "ae_mul8q4x16", ICLASS_AE_MUL8Q4X16, + 0, + Opcode_ae_mul8q4x16_encode_fns, 0, 0 }, + { "ae_mula8q4x16", ICLASS_AE_MULA8Q4X16, + 0, + Opcode_ae_mula8q4x16_encode_fns, 0, 0 }, + { "ae_mul8q8x16", ICLASS_AE_MUL8Q8X16, + 0, + Opcode_ae_mul8q8x16_encode_fns, 0, 0 }, + { "ae_mula8q8x16", ICLASS_AE_MULA8Q8X16, + 0, + Opcode_ae_mula8q8x16_encode_fns, 0, 0 }, + { "ae_mul8qw8x16", ICLASS_AE_MUL8QW8X16, + 0, + Opcode_ae_mul8qw8x16_encode_fns, 0, 0 }, + { "ae_mula8qw8x16", ICLASS_AE_MULA8QW8X16, + 0, + Opcode_ae_mula8qw8x16_encode_fns, 0, 0 }, + { "ae_mul4o8x8", ICLASS_AE_MUL4O8X8, + 0, + Opcode_ae_mul4o8x8_encode_fns, 0, 0 }, + { "ae_mula4o8x8", ICLASS_AE_MULA4O8X8, + 0, + Opcode_ae_mula4o8x8_encode_fns, 0, 0 }, + { "ae_mul4o4x16", ICLASS_AE_MUL4O4X16, + 0, + Opcode_ae_mul4o4x16_encode_fns, 0, 0 }, + { "ae_mula4o4x16", ICLASS_AE_MULA4O4X16, + 0, + Opcode_ae_mula4o4x16_encode_fns, 0, 0 }, + { "ae_mul4o8x16", ICLASS_AE_MUL4O8X16, + 0, + Opcode_ae_mul4o8x16_encode_fns, 0, 0 }, + { "ae_mula4o8x16", ICLASS_AE_MULA4O8X16, + 0, + Opcode_ae_mula4o8x16_encode_fns, 0, 0 }, + { "ae_mul4qw8x16", ICLASS_AE_MUL4QW8X16, + 0, + Opcode_ae_mul4qw8x16_encode_fns, 0, 0 }, + { "ae_mula4qw8x16", ICLASS_AE_MULA4QW8X16, + 0, + Opcode_ae_mula4qw8x16_encode_fns, 0, 0 }, + { "ae_mul8q8x8cnv_l", ICLASS_AE_MUL8Q8X8CNV_L, + 0, + Opcode_ae_mul8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mul8q8x8cnv_h", ICLASS_AE_MUL8Q8X8CNV_H, + 0, + Opcode_ae_mul8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mula8q8x8cnv_l", ICLASS_AE_MULA8Q8X8CNV_L, + 0, + Opcode_ae_mula8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mula8q8x8cnv_h", ICLASS_AE_MULA8Q8X8CNV_H, + 0, + Opcode_ae_mula8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mul8q8x16cnv", ICLASS_AE_MUL8Q8X16CNV, + 0, + Opcode_ae_mul8q8x16cnv_encode_fns, 0, 0 }, + { "ae_mula8q8x16cnv", ICLASS_AE_MULA8Q8X16CNV, + 0, + Opcode_ae_mula8q8x16cnv_encode_fns, 0, 0 }, + { "ae_mul2x4q8x8cnv_h", ICLASS_AE_MUL2X4Q8X8CNV_H, + 0, + Opcode_ae_mul2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mula2x4q8x8cnv_h", ICLASS_AE_MULA2X4Q8X8CNV_H, + 0, + Opcode_ae_mula2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mul2x4q8x8cnv_l", ICLASS_AE_MUL2X4Q8X8CNV_L, + 0, + Opcode_ae_mul2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mula2x4q8x8cnv_l", ICLASS_AE_MULA2X4Q8X8CNV_L, + 0, + Opcode_ae_mula2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mul2x4q8x16cnv", ICLASS_AE_MUL2X4Q8X16CNV, + 0, + Opcode_ae_mul2x4q8x16cnv_encode_fns, 0, 0 }, + { "ae_mula2x4q8x16cnv", ICLASS_AE_MULA2X4Q8X16CNV, + 0, + Opcode_ae_mula2x4q8x16cnv_encode_fns, 0, 0 }, + { "ae_mulqq8x16cnv", ICLASS_AE_MULQQ8X16CNV, + 0, + Opcode_ae_mulqq8x16cnv_encode_fns, 0, 0 }, + { "ae_mulaqq8x16cnv", ICLASS_AE_MULAQQ8X16CNV, + 0, + Opcode_ae_mulaqq8x16cnv_encode_fns, 0, 0 }, + { "ae_mul4o8x8cnv_h", ICLASS_AE_MUL4O8X8CNV_H, + 0, + Opcode_ae_mul4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mula4o8x8cnv_h", ICLASS_AE_MULA4O8X8CNV_H, + 0, + Opcode_ae_mula4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mul4o8x8cnv_l", ICLASS_AE_MUL4O8X8CNV_L, + 0, + Opcode_ae_mul4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mula4o8x8cnv_l", ICLASS_AE_MULA4O8X8CNV_L, + 0, + Opcode_ae_mula4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mul4o8x16cnv_h", ICLASS_AE_MUL4O8X16CNV_H, + 0, + Opcode_ae_mul4o8x16cnv_h_encode_fns, 0, 0 }, + { "ae_mula4o8x16cnv_h", ICLASS_AE_MULA4O8X16CNV_H, + 0, + Opcode_ae_mula4o8x16cnv_h_encode_fns, 0, 0 }, + { "ae_mul4o8x16cnv_l", ICLASS_AE_MUL4O8X16CNV_L, + 0, + Opcode_ae_mul4o8x16cnv_l_encode_fns, 0, 0 }, + { "ae_mula4o8x16cnv_l", ICLASS_AE_MULA4O8X16CNV_L, + 0, + Opcode_ae_mula4o8x16cnv_l_encode_fns, 0, 0 }, + { "ae_mul8q4x16cnv_h", ICLASS_AE_MUL8Q4X16CNV_H, + 0, + Opcode_ae_mul8q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mula8q4x16cnv_h", ICLASS_AE_MULA8Q4X16CNV_H, + 0, + Opcode_ae_mula8q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mul8q4x16cnv_l", ICLASS_AE_MUL8Q4X16CNV_L, + 0, + Opcode_ae_mul8q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mula8q4x16cnv_l", ICLASS_AE_MULA8Q4X16CNV_L, + 0, + Opcode_ae_mula8q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mul2x4q4x16cnv_h", ICLASS_AE_MUL2X4Q4X16CNV_H, + 0, + Opcode_ae_mul2x4q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mula2x4q4x16cnv_h", ICLASS_AE_MULA2X4Q4X16CNV_H, + 0, + Opcode_ae_mula2x4q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mul2x4q4x16cnv_l", ICLASS_AE_MUL2X4Q4X16CNV_L, + 0, + Opcode_ae_mul2x4q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mula2x4q4x16cnv_l", ICLASS_AE_MULA2X4Q4X16CNV_L, + 0, + Opcode_ae_mula2x4q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulqq4x16cnv_h", ICLASS_AE_MULQQ4X16CNV_H, + 0, + Opcode_ae_mulqq4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulaqq4x16cnv_h", ICLASS_AE_MULAQQ4X16CNV_H, + 0, + Opcode_ae_mulaqq4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulqq4x16cnv_l", ICLASS_AE_MULQQ4X16CNV_L, + 0, + Opcode_ae_mulqq4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulaqq4x16cnv_l", ICLASS_AE_MULAQQ4X16CNV_L, + 0, + Opcode_ae_mulaqq4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mul4o4x16cnv_hh", ICLASS_AE_MUL4O4X16CNV_HH, + 0, + Opcode_ae_mul4o4x16cnv_hh_encode_fns, 0, 0 }, + { "ae_mul4o4x16cnv_hl", ICLASS_AE_MUL4O4X16CNV_HL, + 0, + Opcode_ae_mul4o4x16cnv_hl_encode_fns, 0, 0 }, + { "ae_mul4o4x16cnv_lh", ICLASS_AE_MUL4O4X16CNV_LH, + 0, + Opcode_ae_mul4o4x16cnv_lh_encode_fns, 0, 0 }, + { "ae_mul4o4x16cnv_ll", ICLASS_AE_MUL4O4X16CNV_LL, + 0, + Opcode_ae_mul4o4x16cnv_ll_encode_fns, 0, 0 }, + { "ae_mula4o4x16cnv_hh", ICLASS_AE_MULA4O4X16CNV_HH, + 0, + Opcode_ae_mula4o4x16cnv_hh_encode_fns, 0, 0 }, + { "ae_mula4o4x16cnv_hl", ICLASS_AE_MULA4O4X16CNV_HL, + 0, + Opcode_ae_mula4o4x16cnv_hl_encode_fns, 0, 0 }, + { "ae_mula4o4x16cnv_lh", ICLASS_AE_MULA4O4X16CNV_LH, + 0, + Opcode_ae_mula4o4x16cnv_lh_encode_fns, 0, 0 }, + { "ae_mula4o4x16cnv_ll", ICLASS_AE_MULA4O4X16CNV_LL, + 0, + Opcode_ae_mula4o4x16cnv_ll_encode_fns, 0, 0 }, + { "ae_muluu8q8x8", ICLASS_AE_MULUU8Q8X8, + 0, + Opcode_ae_muluu8q8x8_encode_fns, 0, 0 }, + { "ae_mulauu8q8x8", ICLASS_AE_MULAUU8Q8X8, + 0, + Opcode_ae_mulauu8q8x8_encode_fns, 0, 0 }, + { "ae_muluu4o8x8", ICLASS_AE_MULUU4O8X8, + 0, + Opcode_ae_muluu4o8x8_encode_fns, 0, 0 }, + { "ae_mulauu4o8x8", ICLASS_AE_MULAUU4O8X8, + 0, + Opcode_ae_mulauu4o8x8_encode_fns, 0, 0 }, + { "ae_muluu8q8x8cnv_l", ICLASS_AE_MULUU8Q8X8CNV_L, + 0, + Opcode_ae_muluu8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauu8q8x8cnv_l", ICLASS_AE_MULAUU8Q8X8CNV_L, + 0, + Opcode_ae_mulauu8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluu8q8x8cnv_h", ICLASS_AE_MULUU8Q8X8CNV_H, + 0, + Opcode_ae_muluu8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauu8q8x8cnv_h", ICLASS_AE_MULAUU8Q8X8CNV_H, + 0, + Opcode_ae_mulauu8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluu2x4q8x8cnv_h", ICLASS_AE_MULUU2X4Q8X8CNV_H, + 0, + Opcode_ae_muluu2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauu2x4q8x8cnv_h", ICLASS_AE_MULAUU2X4Q8X8CNV_H, + 0, + Opcode_ae_mulauu2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluu2x4q8x8cnv_l", ICLASS_AE_MULUU2X4Q8X8CNV_L, + 0, + Opcode_ae_muluu2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauu2x4q8x8cnv_l", ICLASS_AE_MULAUU2X4Q8X8CNV_L, + 0, + Opcode_ae_mulauu2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluu4o8x8cnv_h", ICLASS_AE_MULUU4O8X8CNV_H, + 0, + Opcode_ae_muluu4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauu4o8x8cnv_h", ICLASS_AE_MULAUU4O8X8CNV_H, + 0, + Opcode_ae_mulauu4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluu4o8x8cnv_l", ICLASS_AE_MULUU4O8X8CNV_L, + 0, + Opcode_ae_muluu4o8x8cnv_l_encode_fns, 0, 0 }, + { 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ICLASS_AE_MULAUS4O8X8, + 0, + Opcode_ae_mulaus4o8x8_encode_fns, 0, 0 }, + { "ae_mulus4o4x16", ICLASS_AE_MULUS4O4X16, + 0, + Opcode_ae_mulus4o4x16_encode_fns, 0, 0 }, + { "ae_mulaus4o4x16", ICLASS_AE_MULAUS4O4X16, + 0, + Opcode_ae_mulaus4o4x16_encode_fns, 0, 0 }, + { "ae_mulus4o8x16", ICLASS_AE_MULUS4O8X16, + 0, + Opcode_ae_mulus4o8x16_encode_fns, 0, 0 }, + { "ae_mulaus4o8x16", ICLASS_AE_MULAUS4O8X16, + 0, + Opcode_ae_mulaus4o8x16_encode_fns, 0, 0 }, + { "ae_mulus4qw8x16", ICLASS_AE_MULUS4QW8X16, + 0, + Opcode_ae_mulus4qw8x16_encode_fns, 0, 0 }, + { "ae_mulaus4qw8x16", ICLASS_AE_MULAUS4QW8X16, + 0, + Opcode_ae_mulaus4qw8x16_encode_fns, 0, 0 }, + { "ae_mulus8q8x8cnv_l", ICLASS_AE_MULUS8Q8X8CNV_L, + 0, + Opcode_ae_mulus8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulaus8q8x8cnv_l", ICLASS_AE_MULAUS8Q8X8CNV_L, + 0, + Opcode_ae_mulaus8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulus8q8x8cnv_h", ICLASS_AE_MULUS8Q8X8CNV_H, + 0, + Opcode_ae_mulus8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulaus8q8x8cnv_h", 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ICLASS_AE_MULUSQQ8X16CNV, + 0, + Opcode_ae_mulusqq8x16cnv_encode_fns, 0, 0 }, + { "ae_mulausqq8x16cnv", ICLASS_AE_MULAUSQQ8X16CNV, + 0, + Opcode_ae_mulausqq8x16cnv_encode_fns, 0, 0 }, + { "ae_mulus4o8x8cnv_h", ICLASS_AE_MULUS4O8X8CNV_H, + 0, + Opcode_ae_mulus4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulaus4o8x8cnv_h", ICLASS_AE_MULAUS4O8X8CNV_H, + 0, + Opcode_ae_mulaus4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulus4o8x8cnv_l", ICLASS_AE_MULUS4O8X8CNV_L, + 0, + Opcode_ae_mulus4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulaus4o8x8cnv_l", ICLASS_AE_MULAUS4O8X8CNV_L, + 0, + Opcode_ae_mulaus4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulus4o8x16cnv_h", ICLASS_AE_MULUS4O8X16CNV_H, + 0, + Opcode_ae_mulus4o8x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulaus4o8x16cnv_h", ICLASS_AE_MULAUS4O8X16CNV_H, + 0, + Opcode_ae_mulaus4o8x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulus4o8x16cnv_l", ICLASS_AE_MULUS4O8X16CNV_L, + 0, + Opcode_ae_mulus4o8x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulaus4o8x16cnv_l", ICLASS_AE_MULAUS4O8X16CNV_L, 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Opcode_ae_mulasu4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluuzb8q8x8", ICLASS_AE_MULUUZB8Q8X8, + 0, + Opcode_ae_muluuzb8q8x8_encode_fns, 0, 0 }, + { "ae_mulauuzb8q8x8", ICLASS_AE_MULAUUZB8Q8X8, + 0, + Opcode_ae_mulauuzb8q8x8_encode_fns, 0, 0 }, + { "ae_muluuzb4o8x8", ICLASS_AE_MULUUZB4O8X8, + 0, + Opcode_ae_muluuzb4o8x8_encode_fns, 0, 0 }, + { "ae_mulauuzb4o8x8", ICLASS_AE_MULAUUZB4O8X8, + 0, + Opcode_ae_mulauuzb4o8x8_encode_fns, 0, 0 }, + { "ae_muluuzb8q8x8cnv_l", ICLASS_AE_MULUUZB8Q8X8CNV_L, + 0, + Opcode_ae_muluuzb8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauuzb8q8x8cnv_l", ICLASS_AE_MULAUUZB8Q8X8CNV_L, + 0, + Opcode_ae_mulauuzb8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluuzb8q8x8cnv_h", ICLASS_AE_MULUUZB8Q8X8CNV_H, + 0, + Opcode_ae_muluuzb8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauuzb8q8x8cnv_h", ICLASS_AE_MULAUUZB8Q8X8CNV_H, + 0, + Opcode_ae_mulauuzb8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluuzb2x4q8x8cnv_h", ICLASS_AE_MULUUZB2X4Q8X8CNV_H, + 0, + Opcode_ae_muluuzb2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauuzb2x4q8x8cnv_h", ICLASS_AE_MULAUUZB2X4Q8X8CNV_H, + 0, + Opcode_ae_mulauuzb2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluuzb2x4q8x8cnv_l", ICLASS_AE_MULUUZB2X4Q8X8CNV_L, + 0, + Opcode_ae_muluuzb2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauuzb2x4q8x8cnv_l", ICLASS_AE_MULAUUZB2X4Q8X8CNV_L, + 0, + Opcode_ae_mulauuzb2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluuzb4o8x8cnv_h", ICLASS_AE_MULUUZB4O8X8CNV_H, + 0, + Opcode_ae_muluuzb4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauuzb4o8x8cnv_h", ICLASS_AE_MULAUUZB4O8X8CNV_H, + 0, + Opcode_ae_mulauuzb4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluuzb4o8x8cnv_l", ICLASS_AE_MULUUZB4O8X8CNV_L, + 0, + Opcode_ae_muluuzb4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauuzb4o8x8cnv_l", ICLASS_AE_MULAUUZB4O8X8CNV_L, + 0, + Opcode_ae_mulauuzb4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluuzb3x3o8x8", ICLASS_AE_MULUUZB3X3O8X8, + 0, + Opcode_ae_muluuzb3x3o8x8_encode_fns, 0, 0 }, + { "ae_mulauuzb3x3o8x8", ICLASS_AE_MULAUUZB3X3O8X8, + 0, + Opcode_ae_mulauuzb3x3o8x8_encode_fns, 0, 0 }, + { "ae_mulzb8q8x8", ICLASS_AE_MULZB8Q8X8, + 0, + Opcode_ae_mulzb8q8x8_encode_fns, 0, 0 }, + { "ae_mulazb8q8x8", ICLASS_AE_MULAZB8Q8X8, + 0, + Opcode_ae_mulazb8q8x8_encode_fns, 0, 0 }, + { "ae_mulzb4o8x8", ICLASS_AE_MULZB4O8X8, + 0, + Opcode_ae_mulzb4o8x8_encode_fns, 0, 0 }, + { "ae_mulazb4o8x8", ICLASS_AE_MULAZB4O8X8, + 0, + Opcode_ae_mulazb4o8x8_encode_fns, 0, 0 }, + { "ae_mulzb8q8x8cnv_l", ICLASS_AE_MULZB8Q8X8CNV_L, + 0, + Opcode_ae_mulzb8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulazb8q8x8cnv_l", ICLASS_AE_MULAZB8Q8X8CNV_L, + 0, + Opcode_ae_mulazb8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulzb8q8x8cnv_h", ICLASS_AE_MULZB8Q8X8CNV_H, + 0, + Opcode_ae_mulzb8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulazb8q8x8cnv_h", ICLASS_AE_MULAZB8Q8X8CNV_H, + 0, + Opcode_ae_mulazb8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulzb2x4q8x8cnv_h", ICLASS_AE_MULZB2X4Q8X8CNV_H, + 0, + Opcode_ae_mulzb2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulazb2x4q8x8cnv_h", ICLASS_AE_MULAZB2X4Q8X8CNV_H, + 0, + Opcode_ae_mulazb2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulzb2x4q8x8cnv_l", ICLASS_AE_MULZB2X4Q8X8CNV_L, + 0, + Opcode_ae_mulzb2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulazb2x4q8x8cnv_l", ICLASS_AE_MULAZB2X4Q8X8CNV_L, + 0, + Opcode_ae_mulazb2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulzb4o8x8cnv_h", ICLASS_AE_MULZB4O8X8CNV_H, + 0, + Opcode_ae_mulzb4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulazb4o8x8cnv_h", ICLASS_AE_MULAZB4O8X8CNV_H, + 0, + Opcode_ae_mulazb4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulzb4o8x8cnv_l", ICLASS_AE_MULZB4O8X8CNV_L, + 0, + Opcode_ae_mulzb4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulazb4o8x8cnv_l", ICLASS_AE_MULAZB4O8X8CNV_L, + 0, + Opcode_ae_mulazb4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulzb3x3o8x8", ICLASS_AE_MULZB3X3O8X8, + 0, + Opcode_ae_mulzb3x3o8x8_encode_fns, 0, 0 }, + { "ae_mulazb3x3o8x8", ICLASS_AE_MULAZB3X3O8X8, + 0, + Opcode_ae_mulazb3x3o8x8_encode_fns, 0, 0 }, + { "cvtsf16.l", ICLASS_CVTSF16_L, + 0, + Opcode_cvtsf16_l_encode_fns, 0, 0 }, + { "cvtsf16.h", ICLASS_CVTSF16_H, + 0, + Opcode_cvtsf16_h_encode_fns, 0, 0 }, + { "cvtf16s.l", ICLASS_CVTF16S_L, + 0, + Opcode_cvtf16s_l_encode_fns, 0, 0 }, + { "cvtf16s.h", ICLASS_CVTF16S_H, + 0, + Opcode_cvtf16s_h_encode_fns, 0, 0 }, + { "ae_movfcrfsrv", ICLASS_AE_MOVFCRFSRV, + 0, + Opcode_ae_movfcrfsrv_encode_fns, 0, 0 }, + { "ae_movvfcrfsr", ICLASS_AE_MOVVFCRFSR, + 0, + Opcode_ae_movvfcrfsr_encode_fns, 0, 0 }, + { "movt.s", ICLASS_MOVT_S, + 0, + Opcode_movt_s_encode_fns, 0, 0 }, + { "movf.s", ICLASS_MOVF_S, + 0, + Opcode_movf_s_encode_fns, 0, 0 }, + { "moveqz.s", ICLASS_MOVEQZ_S, + 0, + Opcode_moveqz_s_encode_fns, 0, 0 }, + { "movnez.s", ICLASS_MOVNEZ_S, + 0, + Opcode_movnez_s_encode_fns, 0, 0 }, + { "movgez.s", ICLASS_MOVGEZ_S, + 0, + Opcode_movgez_s_encode_fns, 0, 0 }, + { "movltz.s", ICLASS_MOVLTZ_S, + 0, + Opcode_movltz_s_encode_fns, 0, 0 }, + { "rfr", ICLASS_RFR, + 0, + Opcode_rfr_encode_fns, 0, 0 }, + { "wfr", ICLASS_WFR, + 0, + Opcode_wfr_encode_fns, 0, 0 }, + { "mul.s", ICLASS_MUL_S, + 0, + Opcode_mul_s_encode_fns, 0, 0 }, + { "madd.s", ICLASS_MADD_S, + 0, + Opcode_madd_s_encode_fns, 0, 0 }, + { "msub.s", ICLASS_MSUB_S, + 0, + Opcode_msub_s_encode_fns, 0, 0 }, + { "msubn.s", ICLASS_MSUBN_S, + 0, + Opcode_msubn_s_encode_fns, 0, 0 }, + { "maddn.s", ICLASS_MADDN_S, + 0, + Opcode_maddn_s_encode_fns, 0, 0 }, + { "add.s", ICLASS_ADD_S, + 0, + Opcode_add_s_encode_fns, 0, 0 }, + { "sub.s", ICLASS_SUB_S, + 0, + Opcode_sub_s_encode_fns, 0, 0 }, + { "ole.s", ICLASS_OLE_S, + 0, + Opcode_ole_s_encode_fns, 0, 0 }, + { "olt.s", ICLASS_OLT_S, + 0, + Opcode_olt_s_encode_fns, 0, 0 }, + { "oeq.s", ICLASS_OEQ_S, + 0, + Opcode_oeq_s_encode_fns, 0, 0 }, + { "un.s", ICLASS_UN_S, + 0, + Opcode_un_s_encode_fns, 0, 0 }, + { "ule.s", ICLASS_ULE_S, + 0, + Opcode_ule_s_encode_fns, 0, 0 }, + { "ult.s", ICLASS_ULT_S, + 0, + Opcode_ult_s_encode_fns, 0, 0 }, + { "ueq.s", ICLASS_UEQ_S, + 0, + Opcode_ueq_s_encode_fns, 0, 0 }, + { "nexp01.s", ICLASS_NEXP01_S, + 0, + Opcode_nexp01_s_encode_fns, 0, 0 }, + { "mksadj.s", ICLASS_MKSADJ_S, + 0, + Opcode_mksadj_s_encode_fns, 0, 0 }, + { "mkdadj.s", ICLASS_MKDADJ_S, + 0, + Opcode_mkdadj_s_encode_fns, 0, 0 }, + { "div0.s", ICLASS_DIV0_S, + 0, + Opcode_div0_s_encode_fns, 0, 0 }, + { "sqrt0.s", ICLASS_SQRT0_S, + 0, + Opcode_sqrt0_s_encode_fns, 0, 0 }, + { "recip0.s", ICLASS_RECIP0_S, + 0, + Opcode_recip0_s_encode_fns, 0, 0 }, + { "rsqrt0.s", ICLASS_RSQRT0_S, + 0, + Opcode_rsqrt0_s_encode_fns, 0, 0 }, + { "divn.s", ICLASS_DIVN_S, + 0, + Opcode_divn_s_encode_fns, 0, 0 }, + { "addexp.s", ICLASS_ADDEXP_S, + 0, + Opcode_addexp_s_encode_fns, 0, 0 }, + { "addexpm.s", ICLASS_ADDEXPM_S, + 0, + Opcode_addexpm_s_encode_fns, 0, 0 }, + { "min.s", ICLASS_MIN_S, + 0, + Opcode_min_s_encode_fns, 0, 0 }, + { "max.s", ICLASS_MAX_S, + 0, + Opcode_max_s_encode_fns, 0, 0 }, + { "mulmux.s", ICLASS_MULMUX_S, + 0, + Opcode_mulmux_s_encode_fns, 0, 0 }, + { "maddmux.s", ICLASS_MADDMUX_S, + 0, + Opcode_maddmux_s_encode_fns, 0, 0 }, + { "trunc.s", ICLASS_TRUNC_S, + 0, + Opcode_trunc_s_encode_fns, 0, 0 }, + { "utrunc.s", ICLASS_UTRUNC_S, + 0, + Opcode_utrunc_s_encode_fns, 0, 0 }, + { "trunc.sx2", ICLASS_TRUNC_SX2, + 0, + Opcode_trunc_sx2_encode_fns, 0, 0 }, + { "utrunc.sx2", ICLASS_UTRUNC_SX2, + 0, + Opcode_utrunc_sx2_encode_fns, 0, 0 }, + { "ficeil.s", ICLASS_FICEIL_S, + 0, + Opcode_ficeil_s_encode_fns, 0, 0 }, + { "fifloor.s", ICLASS_FIFLOOR_S, + 0, + Opcode_fifloor_s_encode_fns, 0, 0 }, + { "firint.s", ICLASS_FIRINT_S, + 0, + Opcode_firint_s_encode_fns, 0, 0 }, + { "firound.s", ICLASS_FIROUND_S, + 0, + Opcode_firound_s_encode_fns, 0, 0 }, + { "fitrunc.s", ICLASS_FITRUNC_S, + 0, + Opcode_fitrunc_s_encode_fns, 0, 0 }, + { "float.s", ICLASS_FLOAT_S, + 0, + Opcode_float_s_encode_fns, 0, 0 }, + { "ufloat.s", ICLASS_UFLOAT_S, + 0, + Opcode_ufloat_s_encode_fns, 0, 0 }, + { "float.sx2", ICLASS_FLOAT_SX2, + 0, + Opcode_float_sx2_encode_fns, 0, 0 }, + { "ufloat.sx2", ICLASS_UFLOAT_SX2, + 0, + Opcode_ufloat_sx2_encode_fns, 0, 0 }, + { "abs.s", ICLASS_ABS_S, + 0, + Opcode_abs_s_encode_fns, 0, 0 }, + { "neg.s", ICLASS_NEG_S, + 0, + Opcode_neg_s_encode_fns, 0, 0 }, + { "conjc.s", ICLASS_CONJC_S, + 0, + Opcode_conjc_s_encode_fns, 0, 0 }, + { "muljc.s", ICLASS_MULJC_S, + 0, + Opcode_muljc_s_encode_fns, 0, 0 }, + { "const.s", ICLASS_CONST_S, + 0, + Opcode_const_s_encode_fns, 0, 0 }, + { "clsfy.s", ICLASS_CLSFY_S, + 0, + Opcode_clsfy_s_encode_fns, 0, 0 }, + { "minnum.s", ICLASS_MINNUM_S, + 0, + Opcode_minnum_s_encode_fns, 0, 0 }, + { "maxnum.s", ICLASS_MAXNUM_S, + 0, + Opcode_maxnum_s_encode_fns, 0, 0 }, + { "addandsub.s", ICLASS_ADDANDSUB_S, + 0, + Opcode_addandsub_s_encode_fns, 0, 0 }, + { "addandsubjc.s", ICLASS_ADDANDSUBJC_S, + 0, + Opcode_addandsubjc_s_encode_fns, 0, 0 }, + { "add_hl_lh.s", ICLASS_ADD_HL_LH_S, + 0, + Opcode_add_hl_lh_s_encode_fns, 0, 0 }, + { "madda.s", ICLASS_MADDA_S, + 0, + Opcode_madda_s_encode_fns, 0, 0 }, + { "frexp.s", ICLASS_FREXP_S, + 0, + Opcode_frexp_s_encode_fns, 0, 0 }, + { "floatexp.s", ICLASS_FLOATEXP_S, + 0, + Opcode_floatexp_s_encode_fns, 0, 0 }, + { "minnumabs.s", ICLASS_MINNUMABS_S, + 0, + Opcode_minnumabs_s_encode_fns, 0, 0 }, + { "maxnumabs.s", ICLASS_MAXNUMABS_S, + 0, + Opcode_maxnumabs_s_encode_fns, 0, 0 }, + { "mulq.s", ICLASS_MULQ_S, + 0, + Opcode_mulq_s_encode_fns, 0, 0 }, + { "maddq.s", ICLASS_MADDQ_S, + 0, + Opcode_maddq_s_encode_fns, 0, 0 }, + { "msubq.s", ICLASS_MSUBQ_S, + 0, + Opcode_msubq_s_encode_fns, 0, 0 }, + { "mulmuxq.s", ICLASS_MULMUXQ_S, + 0, + Opcode_mulmuxq_s_encode_fns, 0, 0 }, + { "maddmuxq.s", ICLASS_MADDMUXQ_S, + 0, + Opcode_maddmuxq_s_encode_fns, 0, 0 }, + { "bmaxnum.s", ICLASS_BMAXNUM_S, + 0, + Opcode_bmaxnum_s_encode_fns, 0, 0 }, + { "bminnum.s", ICLASS_BMINNUM_S, + 0, + Opcode_bminnum_s_encode_fns, 0, 0 }, + { "bmaxnumabs.s", ICLASS_BMAXNUMABS_S, + 0, + Opcode_bmaxnumabs_s_encode_fns, 0, 0 }, + { "bminnumabs.s", ICLASS_BMINNUMABS_S, + 0, + Opcode_bminnumabs_s_encode_fns, 0, 0 }, + { "abs.sx2x2", ICLASS_ABS_SX2X2, + 0, + Opcode_abs_sx2x2_encode_fns, 0, 0 }, + { "neg.sx2x2", ICLASS_NEG_SX2X2, + 0, + Opcode_neg_sx2x2_encode_fns, 0, 0 }, + { "conjc.sx2x2", ICLASS_CONJC_SX2X2, + 0, + Opcode_conjc_sx2x2_encode_fns, 0, 0 }, + { "muljc.sx2x2", ICLASS_MULJC_SX2X2, + 0, + Opcode_muljc_sx2x2_encode_fns, 0, 0 }, + { "const.sx2x2", ICLASS_CONST_SX2X2, + 0, + Opcode_const_sx2x2_encode_fns, 0, 0 }, + { "add.sx2x2", ICLASS_ADD_SX2X2, + 0, + Opcode_add_sx2x2_encode_fns, 0, 0 }, + { "sub.sx2x2", ICLASS_SUB_SX2X2, + 0, + Opcode_sub_sx2x2_encode_fns, 0, 0 }, + { "mul.sx2x2", ICLASS_MUL_SX2X2, + 0, + Opcode_mul_sx2x2_encode_fns, 0, 0 }, + { "madd.sx2x2", ICLASS_MADD_SX2X2, + 0, + Opcode_madd_sx2x2_encode_fns, 0, 0 }, + { "msub.sx2x2", ICLASS_MSUB_SX2X2, + 0, + Opcode_msub_sx2x2_encode_fns, 0, 0 }, + { "mulmux.sx2x2", ICLASS_MULMUX_SX2X2, + 0, + Opcode_mulmux_sx2x2_encode_fns, 0, 0 }, + { "maddmux.sx2x2", ICLASS_MADDMUX_SX2X2, + 0, + Opcode_maddmux_sx2x2_encode_fns, 0, 0 }, + { "abs.h", ICLASS_ABS_H, + 0, + Opcode_abs_h_encode_fns, 0, 0 }, + { "addexp.h", ICLASS_ADDEXP_H, + 0, + Opcode_addexp_h_encode_fns, 0, 0 }, + { "addexpm.h", ICLASS_ADDEXPM_H, + 0, + Opcode_addexpm_h_encode_fns, 0, 0 }, + { "clsfy.h", ICLASS_CLSFY_H, + 0, + Opcode_clsfy_h_encode_fns, 0, 0 }, + { "conjc.h", ICLASS_CONJC_H, + 0, + Opcode_conjc_h_encode_fns, 0, 0 }, + { "const.h", ICLASS_CONST_H, + 0, + Opcode_const_h_encode_fns, 0, 0 }, + { "min.h", ICLASS_MIN_H, + 0, + Opcode_min_h_encode_fns, 0, 0 }, + { "max.h", ICLASS_MAX_H, + 0, + Opcode_max_h_encode_fns, 0, 0 }, + { "minnum.h", ICLASS_MINNUM_H, + 0, + Opcode_minnum_h_encode_fns, 0, 0 }, + { "maxnum.h", ICLASS_MAXNUM_H, + 0, + Opcode_maxnum_h_encode_fns, 0, 0 }, + { "muljc.h", ICLASS_MULJC_H, + 0, + Opcode_muljc_h_encode_fns, 0, 0 }, + { "neg.h", ICLASS_NEG_H, + 0, + Opcode_neg_h_encode_fns, 0, 0 }, + { "oeq.h", ICLASS_OEQ_H, + 0, + Opcode_oeq_h_encode_fns, 0, 0 }, + { "ole.h", ICLASS_OLE_H, + 0, + Opcode_ole_h_encode_fns, 0, 0 }, + { "olt.h", ICLASS_OLT_H, + 0, + Opcode_olt_h_encode_fns, 0, 0 }, + { "ueq.h", ICLASS_UEQ_H, + 0, + Opcode_ueq_h_encode_fns, 0, 0 }, + { "ule.h", ICLASS_ULE_H, + 0, + Opcode_ule_h_encode_fns, 0, 0 }, + { "ult.h", ICLASS_ULT_H, + 0, + Opcode_ult_h_encode_fns, 0, 0 }, + { "un.h", ICLASS_UN_H, + 0, + Opcode_un_h_encode_fns, 0, 0 }, + { "div0.h", ICLASS_DIV0_H, + 0, + Opcode_div0_h_encode_fns, 0, 0 }, + { "ficeil.h", ICLASS_FICEIL_H, + 0, + Opcode_ficeil_h_encode_fns, 0, 0 }, + { "fifloor.h", ICLASS_FIFLOOR_H, + 0, + Opcode_fifloor_h_encode_fns, 0, 0 }, + { "firint.h", ICLASS_FIRINT_H, + 0, + Opcode_firint_h_encode_fns, 0, 0 }, + { "firound.h", ICLASS_FIROUND_H, + 0, + Opcode_firound_h_encode_fns, 0, 0 }, + { "fitrunc.h", ICLASS_FITRUNC_H, + 0, + Opcode_fitrunc_h_encode_fns, 0, 0 }, + { "mkdadj.h", ICLASS_MKDADJ_H, + 0, + Opcode_mkdadj_h_encode_fns, 0, 0 }, + { "mksadj.h", ICLASS_MKSADJ_H, + 0, + Opcode_mksadj_h_encode_fns, 0, 0 }, + { "nexp0.h", ICLASS_NEXP0_H, + 0, + Opcode_nexp0_h_encode_fns, 0, 0 }, + { "nexp01.h", ICLASS_NEXP01_H, + 0, + Opcode_nexp01_h_encode_fns, 0, 0 }, + { "recip0.h", ICLASS_RECIP0_H, + 0, + Opcode_recip0_h_encode_fns, 0, 0 }, + { "rsqrt0.h", ICLASS_RSQRT0_H, + 0, + Opcode_rsqrt0_h_encode_fns, 0, 0 }, + { "sqrt0.h", ICLASS_SQRT0_H, + 0, + Opcode_sqrt0_h_encode_fns, 0, 0 }, + { "float16.h", ICLASS_FLOAT16_H, + 0, + Opcode_float16_h_encode_fns, 0, 0 }, + { "ufloat16.h", ICLASS_UFLOAT16_H, + 0, + Opcode_ufloat16_h_encode_fns, 0, 0 }, + { "trunc16.h", ICLASS_TRUNC16_H, + 0, + Opcode_trunc16_h_encode_fns, 0, 0 }, + { "utrunc16.h", ICLASS_UTRUNC16_H, + 0, + Opcode_utrunc16_h_encode_fns, 0, 0 }, + { "float16.hx4", ICLASS_FLOAT16_HX4, + 0, + Opcode_float16_hx4_encode_fns, 0, 0 }, + { "ufloat16.hx4", ICLASS_UFLOAT16_HX4, + 0, + Opcode_ufloat16_hx4_encode_fns, 0, 0 }, + { "trunc16.hx4", ICLASS_TRUNC16_HX4, + 0, + Opcode_trunc16_hx4_encode_fns, 0, 0 }, + { "utrunc16.hx4", ICLASS_UTRUNC16_HX4, + 0, + Opcode_utrunc16_hx4_encode_fns, 0, 0 }, + { "add.h", ICLASS_ADD_H, + 0, + Opcode_add_h_encode_fns, 0, 0 }, + { "sub.h", ICLASS_SUB_H, + 0, + Opcode_sub_h_encode_fns, 0, 0 }, + { "mul.h", ICLASS_MUL_H, + 0, + Opcode_mul_h_encode_fns, 0, 0 }, + { "madd.h", ICLASS_MADD_H, + 0, + Opcode_madd_h_encode_fns, 0, 0 }, + { "msub.h", ICLASS_MSUB_H, + 0, + Opcode_msub_h_encode_fns, 0, 0 }, + { "maddn.h", ICLASS_MADDN_H, + 0, + Opcode_maddn_h_encode_fns, 0, 0 }, + { "msubn.h", ICLASS_MSUBN_H, + 0, + Opcode_msubn_h_encode_fns, 0, 0 }, + { "divn.h", ICLASS_DIVN_H, + 0, + Opcode_divn_h_encode_fns, 0, 0 }, + { "rminnum.h", ICLASS_RMINNUM_H, + 0, + Opcode_rminnum_h_encode_fns, 0, 0 }, + { "rmaxnum.h", ICLASS_RMAXNUM_H, + 0, + Opcode_rmaxnum_h_encode_fns, 0, 0 }, + { "abs.hx4x2", ICLASS_ABS_HX4X2, + 0, + Opcode_abs_hx4x2_encode_fns, 0, 0 }, + { "neg.hx4x2", ICLASS_NEG_HX4X2, + 0, + Opcode_neg_hx4x2_encode_fns, 0, 0 }, + { "conjc.hx4x2", ICLASS_CONJC_HX4X2, + 0, + Opcode_conjc_hx4x2_encode_fns, 0, 0 }, + { "const.hx4x2", ICLASS_CONST_HX4X2, + 0, + Opcode_const_hx4x2_encode_fns, 0, 0 }, + { "muljc.hx4x2", ICLASS_MULJC_HX4X2, + 0, + Opcode_muljc_hx4x2_encode_fns, 0, 0 }, + { "add.hx4x2", ICLASS_ADD_HX4X2, + 0, + Opcode_add_hx4x2_encode_fns, 0, 0 }, + { "sub.hx4x2", ICLASS_SUB_HX4X2, + 0, + Opcode_sub_hx4x2_encode_fns, 0, 0 }, + { "mul.hx4x2", ICLASS_MUL_HX4X2, + 0, + Opcode_mul_hx4x2_encode_fns, 0, 0 }, + { "madd.hx4x2", ICLASS_MADD_HX4X2, + 0, + Opcode_madd_hx4x2_encode_fns, 0, 0 }, + { "msub.hx4x2", ICLASS_MSUB_HX4X2, + 0, + Opcode_msub_hx4x2_encode_fns, 0, 0 }, + { "mulq.h", ICLASS_MULQ_H, + 0, + Opcode_mulq_h_encode_fns, 0, 0 }, + { "maddq.h", ICLASS_MADDQ_H, + 0, + Opcode_maddq_h_encode_fns, 0, 0 }, + { "mulcnvh.hx4x2", ICLASS_MULCNVH_HX4X2, + 0, + Opcode_mulcnvh_hx4x2_encode_fns, 0, 0 }, + { "mulacnvh.hx4x2", ICLASS_MULACNVH_HX4X2, + 0, + Opcode_mulacnvh_hx4x2_encode_fns, 0, 0 }, + { "mulcnvl.hx4x2", ICLASS_MULCNVL_HX4X2, + 0, + Opcode_mulcnvl_hx4x2_encode_fns, 0, 0 }, + { "mulacnvl.hx4x2", ICLASS_MULACNVL_HX4X2, + 0, + Opcode_mulacnvl_hx4x2_encode_fns, 0, 0 } +}; + +enum xtensa_opcode_id { + OPCODE_EXCW, + OPCODE_RFE, + OPCODE_RFDE, + OPCODE_SYSCALL, + OPCODE_CALL12, + OPCODE_CALL8, + OPCODE_CALL4, + OPCODE_CALLX12, + OPCODE_CALLX8, + OPCODE_CALLX4, + OPCODE_ENTRY, + OPCODE_MOVSP, + OPCODE_ROTW, + OPCODE_RETW, + OPCODE_RETW_N, + OPCODE_RFWO, + OPCODE_RFWU, + OPCODE_L32E, + OPCODE_S32E, + OPCODE_RSR_WINDOWBASE, + OPCODE_WSR_WINDOWBASE, + OPCODE_XSR_WINDOWBASE, + OPCODE_RSR_WINDOWSTART, + OPCODE_WSR_WINDOWSTART, + OPCODE_XSR_WINDOWSTART, + OPCODE_ADD_N, + OPCODE_ADDI_N, + OPCODE_BEQZ_N, + OPCODE_BNEZ_N, + OPCODE_ILL_N, + OPCODE_L32I_N, + OPCODE_MOV_N, + OPCODE_MOVI_N, + OPCODE_NOP_N, + OPCODE_RET_N, + OPCODE_S32I_N, + OPCODE_RUR_THREADPTR, + OPCODE_WUR_THREADPTR, + OPCODE_ADDI, + OPCODE_ADDMI, + OPCODE_ADD, + OPCODE_ADDX2, + OPCODE_ADDX4, + OPCODE_ADDX8, + OPCODE_SUB, + OPCODE_SUBX2, + OPCODE_SUBX4, + OPCODE_SUBX8, + OPCODE_AND, + OPCODE_OR, + OPCODE_XOR, + OPCODE_BEQI, + OPCODE_BGEI, + OPCODE_BLTI, + OPCODE_BNEI, + OPCODE_BBCI, + OPCODE_BBSI, + OPCODE_BGEUI, + OPCODE_BLTUI, + OPCODE_BALL, + OPCODE_BANY, + OPCODE_BBC, + OPCODE_BBS, + OPCODE_BEQ, + OPCODE_BGE, + OPCODE_BGEU, + OPCODE_BLT, + OPCODE_BLTU, + OPCODE_BNALL, + OPCODE_BNE, + OPCODE_BNONE, + OPCODE_BEQZ, + OPCODE_BGEZ, + OPCODE_BLTZ, + OPCODE_BNEZ, + OPCODE_CALL0, + OPCODE_CALLX0, + OPCODE_EXTUI, + OPCODE_ILL, + OPCODE_J, + OPCODE_JX, + OPCODE_L16UI, + OPCODE_L16SI, + OPCODE_L32I, + OPCODE_L32R, + OPCODE_L8UI, + OPCODE_LOOP, + OPCODE_LOOPGTZ, + OPCODE_LOOPNEZ, + OPCODE_MOVI, + OPCODE_MOVEQZ, + OPCODE_MOVGEZ, + OPCODE_MOVLTZ, + OPCODE_MOVNEZ, + OPCODE_ABS, + OPCODE_NEG, + OPCODE_NOP, + OPCODE_L32EX, + OPCODE_S32EX, + OPCODE_GETEX, + OPCODE_CLREX, + OPCODE_RET, + OPCODE_SIMCALL, + OPCODE_S16I, + OPCODE_S32I, + OPCODE_S32NB, + OPCODE_S8I, + OPCODE_SSA8B, + OPCODE_SSA8L, + OPCODE_SSL, + OPCODE_SSR, + OPCODE_SSAI, + OPCODE_SLL, + OPCODE_SRC, + OPCODE_SRA, + OPCODE_SRL, + OPCODE_SLLI, + OPCODE_SRAI, + OPCODE_SRLI, + OPCODE_MEMW, + OPCODE_EXTW, + OPCODE_ISYNC, + OPCODE_DSYNC, + OPCODE_ESYNC, + OPCODE_RSYNC, + OPCODE_RSIL, + OPCODE_RSR_LEND, + OPCODE_WSR_LEND, + OPCODE_XSR_LEND, + OPCODE_RSR_LCOUNT, + OPCODE_WSR_LCOUNT, + OPCODE_XSR_LCOUNT, + OPCODE_RSR_LBEG, + OPCODE_WSR_LBEG, + OPCODE_XSR_LBEG, + OPCODE_RSR_SAR, + OPCODE_WSR_SAR, + OPCODE_XSR_SAR, + OPCODE_RSR_MEMCTL, + OPCODE_WSR_MEMCTL, + OPCODE_XSR_MEMCTL, + OPCODE_RSR_CONFIGID0, + OPCODE_WSR_CONFIGID0, + OPCODE_RSR_CONFIGID1, + OPCODE_RSR_PS, + OPCODE_WSR_PS, + OPCODE_XSR_PS, + OPCODE_RSR_EPC1, + OPCODE_WSR_EPC1, + OPCODE_XSR_EPC1, + OPCODE_RSR_EXCSAVE1, + OPCODE_WSR_EXCSAVE1, + OPCODE_XSR_EXCSAVE1, + OPCODE_RSR_EPC2, + OPCODE_WSR_EPC2, + OPCODE_XSR_EPC2, + OPCODE_RSR_EXCSAVE2, + OPCODE_WSR_EXCSAVE2, + OPCODE_XSR_EXCSAVE2, + OPCODE_RSR_EPC3, + OPCODE_WSR_EPC3, + OPCODE_XSR_EPC3, + OPCODE_RSR_EXCSAVE3, + OPCODE_WSR_EXCSAVE3, + OPCODE_XSR_EXCSAVE3, + OPCODE_RSR_EPC4, + OPCODE_WSR_EPC4, + OPCODE_XSR_EPC4, + OPCODE_RSR_EXCSAVE4, + OPCODE_WSR_EXCSAVE4, + OPCODE_XSR_EXCSAVE4, + OPCODE_RSR_EPC5, + OPCODE_WSR_EPC5, + OPCODE_XSR_EPC5, + OPCODE_RSR_EXCSAVE5, + OPCODE_WSR_EXCSAVE5, + OPCODE_XSR_EXCSAVE5, + OPCODE_RSR_EPC6, + OPCODE_WSR_EPC6, + OPCODE_XSR_EPC6, + OPCODE_RSR_EXCSAVE6, + OPCODE_WSR_EXCSAVE6, + OPCODE_XSR_EXCSAVE6, + OPCODE_RSR_EPS2, + OPCODE_WSR_EPS2, + OPCODE_XSR_EPS2, + OPCODE_RSR_EPS3, + OPCODE_WSR_EPS3, + OPCODE_XSR_EPS3, + OPCODE_RSR_EPS4, + OPCODE_WSR_EPS4, + OPCODE_XSR_EPS4, + OPCODE_RSR_EPS5, + OPCODE_WSR_EPS5, + OPCODE_XSR_EPS5, + OPCODE_RSR_EPS6, + OPCODE_WSR_EPS6, + OPCODE_XSR_EPS6, + OPCODE_RSR_EXCVADDR, + OPCODE_WSR_EXCVADDR, + OPCODE_XSR_EXCVADDR, + OPCODE_RSR_DEPC, + OPCODE_WSR_DEPC, + OPCODE_XSR_DEPC, + OPCODE_RSR_EXCCAUSE, + OPCODE_WSR_EXCCAUSE, + OPCODE_XSR_EXCCAUSE, + OPCODE_RSR_MISC0, + OPCODE_WSR_MISC0, + OPCODE_XSR_MISC0, + OPCODE_RSR_MISC1, + OPCODE_WSR_MISC1, + OPCODE_XSR_MISC1, + OPCODE_RSR_MISC2, + OPCODE_WSR_MISC2, + OPCODE_XSR_MISC2, + OPCODE_RSR_MISC3, + OPCODE_WSR_MISC3, + OPCODE_XSR_MISC3, + OPCODE_RSR_PRID, + OPCODE_RSR_VECBASE, + OPCODE_WSR_VECBASE, + OPCODE_XSR_VECBASE, + OPCODE_RSR_MPUCFG, + OPCODE_WSR_MPUCFG, + OPCODE_SALT, + OPCODE_SALTU, + OPCODE_RSR_OPMODE, + OPCODE_WSR_OPMODE, + OPCODE_XSR_OPMODE, + OPCODE_MUL16S, + OPCODE_MUL16U, + OPCODE_MULL, + OPCODE_RFI, + OPCODE_WAITI, + OPCODE_RSR_INTERRUPT, + OPCODE_WSR_INTSET, + OPCODE_WSR_INTCLEAR, + OPCODE_RSR_INTENABLE, + OPCODE_WSR_INTENABLE, + OPCODE_XSR_INTENABLE, + OPCODE_BREAK, + OPCODE_BREAK_N, + OPCODE_RSR_DBREAKA0, + OPCODE_WSR_DBREAKA0, + OPCODE_XSR_DBREAKA0, + OPCODE_RSR_DBREAKC0, + OPCODE_WSR_DBREAKC0, + OPCODE_XSR_DBREAKC0, + OPCODE_RSR_DBREAKA1, + OPCODE_WSR_DBREAKA1, + OPCODE_XSR_DBREAKA1, + OPCODE_RSR_DBREAKC1, + OPCODE_WSR_DBREAKC1, + OPCODE_XSR_DBREAKC1, + OPCODE_RSR_IBREAKA0, + OPCODE_WSR_IBREAKA0, + OPCODE_XSR_IBREAKA0, + OPCODE_RSR_IBREAKA1, + OPCODE_WSR_IBREAKA1, + OPCODE_XSR_IBREAKA1, + OPCODE_RSR_IBREAKENABLE, + OPCODE_WSR_IBREAKENABLE, + OPCODE_XSR_IBREAKENABLE, + OPCODE_RSR_DEBUGCAUSE, + OPCODE_WSR_DEBUGCAUSE, + OPCODE_XSR_DEBUGCAUSE, + OPCODE_RSR_ICOUNT, + OPCODE_WSR_ICOUNT, + OPCODE_XSR_ICOUNT, + OPCODE_RSR_ICOUNTLEVEL, + OPCODE_WSR_ICOUNTLEVEL, + OPCODE_XSR_ICOUNTLEVEL, + OPCODE_RSR_DDR, + OPCODE_WSR_DDR, + OPCODE_XSR_DDR, + OPCODE_LDDR32_P, + OPCODE_SDDR32_P, + OPCODE_RFDO, + OPCODE_RFDD, + OPCODE_WSR_MMID, + OPCODE_ANDB, + OPCODE_ANDBC, + OPCODE_ORB, + OPCODE_ORBC, + OPCODE_XORB, + OPCODE_ALL4, + OPCODE_ANY4, + OPCODE_ALL8, + OPCODE_ANY8, + OPCODE_BF, + OPCODE_BT, + OPCODE_MOVF, + OPCODE_MOVT, + OPCODE_RSR_BR, + OPCODE_WSR_BR, + OPCODE_XSR_BR, + OPCODE_RSR_CCOUNT, + OPCODE_WSR_CCOUNT, + OPCODE_XSR_CCOUNT, + OPCODE_RSR_CCOMPARE0, + OPCODE_WSR_CCOMPARE0, + OPCODE_XSR_CCOMPARE0, + OPCODE_RSR_CCOMPARE1, + OPCODE_WSR_CCOMPARE1, + OPCODE_XSR_CCOMPARE1, + OPCODE_RSR_CCOMPARE2, + OPCODE_WSR_CCOMPARE2, + OPCODE_XSR_CCOMPARE2, + OPCODE_IHI, + OPCODE_IPF, + OPCODE_IHU, + OPCODE_IIU, + OPCODE_IPFL, + OPCODE_III, + OPCODE_LICT, + OPCODE_LICW, + OPCODE_SICT, + OPCODE_SICW, + OPCODE_DHWB, + OPCODE_DHWBI, + OPCODE_DIWBUI_P, + OPCODE_DIWB, + OPCODE_DIWBI, + OPCODE_DHI, + OPCODE_DII, + OPCODE_DPFR, + OPCODE_DPFRO, + OPCODE_DPFW, + OPCODE_DPFWO, + OPCODE_DHU, + OPCODE_DIU, + OPCODE_DPFL, + OPCODE_SDCT, + OPCODE_LDCT, + OPCODE_SDCW, + OPCODE_LDCW, + OPCODE_RSR_PREFCTL, + OPCODE_WSR_PREFCTL, + OPCODE_XSR_PREFCTL, + OPCODE_WSR_CACHEADRDIS, + OPCODE_RSR_CACHEADRDIS, + OPCODE_XSR_CACHEADRDIS, + OPCODE_RPTLB0, + OPCODE_PPTLB, + OPCODE_RPTLB1, + OPCODE_WPTLB, + OPCODE_RSR_MPUENB, + OPCODE_WSR_MPUENB, + OPCODE_XSR_MPUENB, + OPCODE_RSR_CPENABLE, + OPCODE_WSR_CPENABLE, + OPCODE_XSR_CPENABLE, + OPCODE_CLAMPS, + OPCODE_MAX, + OPCODE_MAXU, + OPCODE_MIN, + OPCODE_MINU, + OPCODE_NSA, + OPCODE_NSAU, + OPCODE_SEXT, + OPCODE_L32AI, + OPCODE_S32RI, + OPCODE_RSR_ATOMCTL, + OPCODE_WSR_ATOMCTL, + OPCODE_XSR_ATOMCTL, + OPCODE_QUOS, + OPCODE_QUOU, + OPCODE_REMS, + OPCODE_REMU, + OPCODE_RSR_ERACCESS, + OPCODE_WSR_ERACCESS, + OPCODE_XSR_ERACCESS, + OPCODE_RER, + OPCODE_WER, + OPCODE_BEQZ_W15, + OPCODE_BGEZ_W15, + OPCODE_BLTZ_W15, + OPCODE_BNEZ_W15, + OPCODE_BEQI_W15, + OPCODE_BGEI_W15, + OPCODE_BLTI_W15, + OPCODE_BNEI_W15, + OPCODE_BGEUI_W15, + OPCODE_BLTUI_W15, + OPCODE_BBCI_W15, + OPCODE_BBSI_W15, + OPCODE_BALL_W15, + OPCODE_BANY_W15, + OPCODE_BBC_W15, + OPCODE_BBS_W15, + OPCODE_BEQ_W15, + OPCODE_BGEU_W15, + OPCODE_BGE_W15, + OPCODE_BLTU_W15, + OPCODE_BLT_W15, + OPCODE_BNALL_W15, + OPCODE_BNE_W15, + OPCODE_BNONE_W15, + OPCODE_AE_SEXT16, + OPCODE_AE_ZEXT16, + OPCODE_AE_ZEXT8, + OPCODE_AE_CLAMPS16, + OPCODE_RUR_FCR, + OPCODE_WUR_FCR, + OPCODE_RUR_FSR, + OPCODE_WUR_FSR, + OPCODE_READ_IMPWIRE, + OPCODE_SETB_EXPSTATE, + OPCODE_CLRB_EXPSTATE, + OPCODE_WRMSK_EXPSTATE, + OPCODE_RUR_AE_OVF_SAR, + OPCODE_WUR_AE_OVF_SAR, + OPCODE_RUR_AE_BITHEAD, + OPCODE_WUR_AE_BITHEAD, + OPCODE_RUR_AE_TS_FTS_BU_BP, + OPCODE_WUR_AE_TS_FTS_BU_BP, + OPCODE_RUR_AE_CW_SD_NO, + OPCODE_WUR_AE_CW_SD_NO, + OPCODE_RUR_AE_CBEGIN0, + OPCODE_WUR_AE_CBEGIN0, + OPCODE_RUR_AE_CEND0, + OPCODE_WUR_AE_CEND0, + OPCODE_RUR_AE_CBEGIN1, + OPCODE_WUR_AE_CBEGIN1, + OPCODE_RUR_AE_CEND1, + OPCODE_WUR_AE_CEND1, + OPCODE_RUR_AE_CBEGIN2, + OPCODE_WUR_AE_CBEGIN2, + OPCODE_RUR_AE_CEND2, + OPCODE_WUR_AE_CEND2, + OPCODE_RUR_EXPSTATE, + OPCODE_WUR_EXPSTATE, + OPCODE_RUR_AE_OVERFLOW, + OPCODE_WUR_AE_OVERFLOW, + OPCODE_RUR_AE_SAR, + OPCODE_WUR_AE_SAR, + OPCODE_RUR_AE_BITPTR, + OPCODE_WUR_AE_BITPTR, + OPCODE_RUR_AE_BITSUSED, + OPCODE_WUR_AE_BITSUSED, + OPCODE_RUR_AE_TABLESIZE, + OPCODE_WUR_AE_TABLESIZE, + OPCODE_RUR_AE_FIRST_TS, + OPCODE_WUR_AE_FIRST_TS, + OPCODE_RUR_AE_NEXTOFFSET, + OPCODE_WUR_AE_NEXTOFFSET, + OPCODE_RUR_AE_SEARCHDONE, + OPCODE_WUR_AE_SEARCHDONE, + OPCODE_RUR_AE_CWRAP, + OPCODE_WUR_AE_CWRAP, + OPCODE_AE_L8X4F_I, + OPCODE_AE_L8X4F_IP, + OPCODE_AE_L8X4F_X, + OPCODE_AE_L8X4F_XP, + OPCODE_AE_L8X4S_I, + OPCODE_AE_L8X4S_IP, + OPCODE_AE_L8X4S_X, + OPCODE_AE_L8X4S_XP, + OPCODE_AE_L8X4U_I, + OPCODE_AE_L8X4U_IP, + OPCODE_AE_L8X4U_X, + OPCODE_AE_L8X4U_XP, + OPCODE_AE_S8X4U_I, + OPCODE_AE_S8X4U_IP, + OPCODE_AE_S8X4U_X, + OPCODE_AE_S8X4U_XP, + OPCODE_AE_L16M_XC, + OPCODE_AE_L16M_XC1, + OPCODE_AE_L16M_I, + OPCODE_AE_L16M_IU, + OPCODE_AE_L16M_X, + OPCODE_AE_L16M_XU, + OPCODE_AE_L16_XC, + OPCODE_AE_L16_XC1, + OPCODE_AE_L16_I, + OPCODE_AE_L16_IP, + OPCODE_AE_L16_X, + OPCODE_AE_L16_XP, + OPCODE_AE_L8_XC, + OPCODE_AE_L8_XC1, + OPCODE_AE_L8_I, + OPCODE_AE_L8_IP, + OPCODE_AE_L8_X, + OPCODE_AE_L8_XP, + OPCODE_AE_L32F24_XC, + OPCODE_AE_L32F24_XC1, + OPCODE_AE_L32F24_I, + OPCODE_AE_L32F24_IP, + OPCODE_AE_L32F24_X, + OPCODE_AE_L32F24_XP, + OPCODE_AE_L32_XC, + OPCODE_AE_L32_XC1, + OPCODE_AE_L32_I, + OPCODE_AE_L32_IP, + OPCODE_AE_L32_X, + OPCODE_AE_L32_XP, + OPCODE_AE_L32M_XC, + OPCODE_AE_L32M_I, + OPCODE_AE_L32M_IU, + OPCODE_AE_L32M_X, + OPCODE_AE_L32M_XU, + OPCODE_AE_L16X2M_XC, + OPCODE_AE_L16X2M_XC1, + OPCODE_AE_L16X2M_I, + OPCODE_AE_L16X2M_IU, + OPCODE_AE_L16X2M_X, + OPCODE_AE_L16X2M_XU, + OPCODE_AE_L32X2F24_XC, + OPCODE_AE_L32X2F24_XC1, + OPCODE_AE_L32X2F24_I, + OPCODE_AE_L32X2F24_IP, + OPCODE_AE_L32X2F24_RIP, + OPCODE_AE_L32X2F24_RI, + OPCODE_AE_L32X2F24_RIC, + OPCODE_AE_L32X2F24_RIC1, + OPCODE_AE_L32X2F24_X, + OPCODE_AE_L32X2F24_XP, + OPCODE_AE_L32X2_XC, + OPCODE_AE_L32X2_XC1, + OPCODE_AE_L32X2_I, + OPCODE_AE_L32X2_IP, + OPCODE_AE_L32X2_RIC, + OPCODE_AE_L32X2_RIC1, + OPCODE_AE_L32X2_X, + OPCODE_AE_L32X2_XP, + OPCODE_AE_L16X4_XC, + OPCODE_AE_L16X4_XC1, + OPCODE_AE_L16X4_I, + OPCODE_AE_L16X4_IP, + OPCODE_AE_L16X4_X, + OPCODE_AE_L16X4_XP, + OPCODE_AE_L8X8_XC, + OPCODE_AE_L8X8_XC1, + OPCODE_AE_L8X8_I, + OPCODE_AE_L8X8_IP, + OPCODE_AE_L8X8_X, + OPCODE_AE_L8X8_XP, + OPCODE_AE_L64_XC, + OPCODE_AE_L64_XC1, + OPCODE_AE_L64_I, + OPCODE_AE_L64_IP, + OPCODE_AE_L64_X, + OPCODE_AE_L64_XP, + OPCODE_AE_S16X2M_XC, + OPCODE_AE_S16X2M_XC1, + OPCODE_AE_S16X2M_I, + OPCODE_AE_S16X2M_IU, + OPCODE_AE_S16X2M_X, + OPCODE_AE_S16X2M_XU, + OPCODE_AE_S32X2F24_XC, + OPCODE_AE_S32X2F24_XC1, + OPCODE_AE_S32X2F24_I, + OPCODE_AE_S32X2F24_IP, + OPCODE_AE_S32X2F24_RIP, + OPCODE_AE_S32X2F24_RIC, + OPCODE_AE_S32X2F24_RIC1, + OPCODE_AE_S32X2F24_X, + OPCODE_AE_S32X2F24_XP, + OPCODE_AE_S32X2_XC, + OPCODE_AE_S32X2_XC1, + OPCODE_AE_S32X2_I, + OPCODE_AE_S32X2_IP, + OPCODE_AE_S32X2_RIC, + OPCODE_AE_S32X2_RIC1, + OPCODE_AE_S32X2_X, + OPCODE_AE_S32X2_XP, + OPCODE_AE_S32X2RNG_I, + OPCODE_AE_S32X2RNG_IP, + OPCODE_AE_S32X2RNG_X, + OPCODE_AE_S32X2RNG_XP, + OPCODE_AE_S16X4_XC, + OPCODE_AE_S16X4_XC1, + OPCODE_AE_S16X4_I, + OPCODE_AE_S16X4_IP, + OPCODE_AE_S16X4_X, + OPCODE_AE_S16X4_XP, + OPCODE_AE_S8X8_XC, + OPCODE_AE_S8X8_XC1, + OPCODE_AE_S8X8_I, + OPCODE_AE_S8X8_IP, + OPCODE_AE_S8X8_X, + OPCODE_AE_S8X8_XP, + OPCODE_AE_S16M_L_XC, + OPCODE_AE_S16M_L_XC1, + OPCODE_AE_S16M_L_I, + OPCODE_AE_S16M_L_IU, + OPCODE_AE_S16M_L_X, + OPCODE_AE_S16M_L_XU, + OPCODE_AE_S32F24_L_XC, + OPCODE_AE_S32F24_L_XC1, + OPCODE_AE_S32F24_L_I, + OPCODE_AE_S32F24_L_IP, + OPCODE_AE_S32F24_L_X, + OPCODE_AE_S32F24_L_XP, + OPCODE_AE_S32_L_XC, + OPCODE_AE_S32_L_XC1, + OPCODE_AE_S32_L_I, + OPCODE_AE_S32_L_IP, + OPCODE_AE_S32_L_X, + OPCODE_AE_S32_L_XP, + OPCODE_AE_S32_H_XC, + OPCODE_AE_S32_H_XC1, + OPCODE_AE_S32_H_I, + OPCODE_AE_S32_H_IP, + OPCODE_AE_S32_H_X, + OPCODE_AE_S32_H_XP, + OPCODE_AE_S16_0_XC, + OPCODE_AE_S16_0_XC1, + OPCODE_AE_S16_0_I, + OPCODE_AE_S16_0_IP, + OPCODE_AE_S16_0_X, + OPCODE_AE_S16_0_XP, + OPCODE_AE_S8_0_XC, + OPCODE_AE_S8_0_XC1, + OPCODE_AE_S8_0_I, + OPCODE_AE_S8_0_IP, + OPCODE_AE_S8_0_X, + OPCODE_AE_S8_0_XP, + OPCODE_AE_S64_XC, + OPCODE_AE_S64_XC1, + OPCODE_AE_S64_I, + OPCODE_AE_S64_IP, + OPCODE_AE_S64_X, + OPCODE_AE_S64_XP, + OPCODE_AE_S32M_XC, + OPCODE_AE_S32M_I, + OPCODE_AE_S32M_IU, + OPCODE_AE_S32M_X, + OPCODE_AE_S32M_XU, + OPCODE_AE_L32X2_XC2, + OPCODE_AE_L16X4_XC2, + OPCODE_AE_L8X8_XC2, + OPCODE_AE_L64_XC2, + OPCODE_AE_S32X2_XC2, + OPCODE_AE_S16X4_XC2, + OPCODE_AE_S8X8_XC2, + OPCODE_AE_S64_XC2, + OPCODE_AE_S16X4RNG_I, + OPCODE_AE_S16X4RNG_IP, + OPCODE_AE_S16X4RNG_X, + OPCODE_AE_S16X4RNG_XP, + OPCODE_AE_L32X2X2_XC, + OPCODE_AE_L32X2X2_XC1, + OPCODE_AE_L32X2X2_I, + OPCODE_AE_L32X2X2_IP, + OPCODE_AE_L32X2X2_X, + OPCODE_AE_L32X2X2_XP, + OPCODE_AE_L16X4X2_XC, + OPCODE_AE_L16X4X2_XC1, + OPCODE_AE_L16X4X2_I, + OPCODE_AE_L16X4X2_IP, + OPCODE_AE_L16X4X2_X, + OPCODE_AE_L16X4X2_XP, + OPCODE_AE_L8X8X2_XC, + OPCODE_AE_L8X8X2_XC1, + OPCODE_AE_L8X8X2_I, + OPCODE_AE_L8X8X2_IP, + OPCODE_AE_L8X8X2_X, + OPCODE_AE_L8X8X2_XP, + OPCODE_AE_L64X2_XC, + OPCODE_AE_L64X2_XC1, + OPCODE_AE_L64X2_I, + OPCODE_AE_L64X2_IP, + OPCODE_AE_L64X2_X, + OPCODE_AE_L64X2_XP, + OPCODE_AE_S32X2X2_XC, + OPCODE_AE_S32X2X2_XC1, + OPCODE_AE_S32X2X2_I, + OPCODE_AE_S32X2X2_IP, + OPCODE_AE_S32X2X2_X, + OPCODE_AE_S32X2X2_XP, + OPCODE_AE_S32X2X2RNG_I, + OPCODE_AE_S32X2X2RNG_IP, + OPCODE_AE_S32X2X2RNG_X, + OPCODE_AE_S32X2X2RNG_XP, + OPCODE_AE_S16X4X2_XC, + OPCODE_AE_S16X4X2_XC1, + OPCODE_AE_S16X4X2_I, + OPCODE_AE_S16X4X2_IP, + OPCODE_AE_S16X4X2_X, + OPCODE_AE_S16X4X2_XP, + OPCODE_AE_S8X8X2_XC, + OPCODE_AE_S8X8X2_XC1, + OPCODE_AE_S8X8X2_I, + OPCODE_AE_S8X8X2_IP, + OPCODE_AE_S8X8X2_X, + OPCODE_AE_S8X8X2_XP, + OPCODE_AE_S8X4UX2_I, + OPCODE_AE_S8X4UX2_IP, + OPCODE_AE_S8X4UX2_X, + OPCODE_AE_S8X4UX2_XP, + OPCODE_AE_S64X2_XC, + OPCODE_AE_S64X2_XC1, + OPCODE_AE_S64X2_I, + OPCODE_AE_S64X2_IP, + OPCODE_AE_S64X2_X, + OPCODE_AE_S64X2_XP, + OPCODE_AE_L32X2X2_XC2, + OPCODE_AE_L16X4X2_XC2, + OPCODE_AE_L8X8X2_XC2, + OPCODE_AE_L64X2_XC2, + OPCODE_AE_S32X2X2_XC2, + OPCODE_AE_S16X4X2_XC2, + OPCODE_AE_S8X8X2_XC2, + OPCODE_AE_S64X2_XC2, + OPCODE_AE_S16X4X2RNG_I, + OPCODE_AE_S16X4X2RNG_IP, + OPCODE_AE_S16X4X2RNG_X, + OPCODE_AE_S16X4X2RNG_XP, + OPCODE_AE_ZALIGN64, + OPCODE_AE_LALIGN64_I, + OPCODE_AE_SALIGN64_I, + OPCODE_AE_MOVALIGN, + OPCODE_AE_LA64_PP, + OPCODE_AE_LA24POS_PC, + OPCODE_AE_LA24NEG_PC, + OPCODE_AE_LA24POS_PC1, + OPCODE_AE_LA24NEG_PC1, + OPCODE_AE_LA24X2POS_PC, + OPCODE_AE_LA24X2NEG_PC, + OPCODE_AE_LA24X2POS_PC1, + OPCODE_AE_LA24X2NEG_PC1, + OPCODE_AE_LA32X2POS_PC, + OPCODE_AE_LA32X2NEG_PC, + OPCODE_AE_LA32X2POS_PC1, + OPCODE_AE_LA32X2NEG_PC1, + OPCODE_AE_LA32X2POS_PC2, + OPCODE_AE_LA16X4POS_PC, + OPCODE_AE_LA16X4NEG_PC, + OPCODE_AE_LA16X4POS_PC1, + OPCODE_AE_LA16X4NEG_PC1, + OPCODE_AE_LA16X4POS_PC2, + OPCODE_AE_LA8X8POS_PC, + OPCODE_AE_LA8X8NEG_PC, + OPCODE_AE_LA8X8POS_PC1, + OPCODE_AE_LA8X8NEG_PC1, + OPCODE_AE_LA8X8POS_PC2, + OPCODE_AE_LA32X2X2POS_PC, + OPCODE_AE_LA32X2X2POS_PC1, + OPCODE_AE_LA32X2X2POS_PC2, + OPCODE_AE_LA16X4X2POS_PC, + OPCODE_AE_LA16X4X2POS_PC1, + OPCODE_AE_LA16X4X2POS_PC2, + OPCODE_AE_LA8X8X2POS_PC, + OPCODE_AE_LA8X8X2POS_PC1, + OPCODE_AE_LA8X8X2POS_PC2, + OPCODE_AE_SA64POS_FP, + OPCODE_AE_SA64NEG_FP, + OPCODE_AE_LA32X2_IC, + OPCODE_AE_LA32X2_IC1, + OPCODE_AE_LA32X2_IC2, + OPCODE_AE_LA32X2_IP, + OPCODE_AE_LA32X2_RIP, + OPCODE_AE_LA32X2_RIC, + OPCODE_AE_LA32X2_RIC1, + OPCODE_AE_LA16X4_IC, + OPCODE_AE_LA16X4_IC1, + OPCODE_AE_LA16X4_IC2, + OPCODE_AE_LA16X4_IP, + OPCODE_AE_LA16X4_RIP, + OPCODE_AE_LA16X4_RIC, + OPCODE_AE_LA16X4_RIC1, + OPCODE_AE_LA8X8_IC, + OPCODE_AE_LA8X8_IC1, + OPCODE_AE_LA8X8_IC2, + OPCODE_AE_LA8X8_IP, + OPCODE_AE_LA8X8_RIP, + OPCODE_AE_LA8X8_RIC, + OPCODE_AE_LA8X8_RIC1, + OPCODE_AE_LA32X2F24_IC, + OPCODE_AE_LA32X2F24_IC1, + OPCODE_AE_LA32X2F24_IP, + OPCODE_AE_LA32X2F24_RIP, + OPCODE_AE_LA32X2F24_RIC, + OPCODE_AE_LA32X2F24_RIC1, + OPCODE_AE_LA24_IC, + OPCODE_AE_LA24_IC1, + OPCODE_AE_LA24_IP, + OPCODE_AE_LA24_RIP, + OPCODE_AE_LA24_RIC, + OPCODE_AE_LA24_RIC1, + OPCODE_AE_LA24X2_IC, + OPCODE_AE_LA24X2_IC1, + OPCODE_AE_LA24X2_IP, + OPCODE_AE_LA24X2_RIP, + OPCODE_AE_LA24X2_RIC, + OPCODE_AE_LA24X2_RIC1, + OPCODE_AE_SA32X2_IC, + OPCODE_AE_SA32X2_IC1, + OPCODE_AE_SA32X2_IC2, + OPCODE_AE_SA32X2_IP, + OPCODE_AE_SA32X2_RIP, + OPCODE_AE_SA32X2_RIC, + OPCODE_AE_SA32X2_RIC1, + OPCODE_AE_SA16X4_IC, + OPCODE_AE_SA16X4_IC1, + OPCODE_AE_SA16X4_IC2, + OPCODE_AE_SA16X4_IP, + OPCODE_AE_SA16X4_RIP, + OPCODE_AE_SA16X4_RIC, + OPCODE_AE_SA16X4_RIC1, + OPCODE_AE_SA8X8_IC, + OPCODE_AE_SA8X8_IC1, + OPCODE_AE_SA8X8_IC2, + OPCODE_AE_SA8X8_IP, + OPCODE_AE_SA8X8_RIP, + OPCODE_AE_SA8X8_RIC, + OPCODE_AE_SA8X8_RIC1, + OPCODE_AE_SA32X2F24_IC, + OPCODE_AE_SA32X2F24_IC1, + OPCODE_AE_SA32X2F24_IP, + OPCODE_AE_SA32X2F24_RIP, + OPCODE_AE_SA32X2F24_RIC, + OPCODE_AE_SA32X2F24_RIC1, + OPCODE_AE_SA24_L_IC, + OPCODE_AE_SA24_L_IC1, + OPCODE_AE_SA24_L_IP, + OPCODE_AE_SA24_L_RIP, + OPCODE_AE_SA24_L_RIC, + OPCODE_AE_SA24_L_RIC1, + OPCODE_AE_SA24X2_IC, + OPCODE_AE_SA24X2_IC1, + OPCODE_AE_SA24X2_IP, + OPCODE_AE_SA24X2_RIP, + OPCODE_AE_SA24X2_RIC, + OPCODE_AE_SA24X2_RIC1, + OPCODE_AE_ADDICIRC, + OPCODE_AE_ADDCIRC_XC2, + OPCODE_AE_ADDCIRC_XC1, + OPCODE_AE_ADDCIRC_XC, + OPCODE_AE_S32RA64S_I, + OPCODE_AE_S32RA64S_IP, + OPCODE_AE_S32RA64S_X, + OPCODE_AE_S32RA64S_XP, + OPCODE_AE_S32RA64S_XC, + OPCODE_AE_S32RA64S_XC1, + OPCODE_AE_S24RA64S_I, + OPCODE_AE_S24RA64S_IP, + OPCODE_AE_S24RA64S_X, + OPCODE_AE_S24RA64S_XP, + OPCODE_AE_S24RA64S_XC, + OPCODE_AE_S24RA64S_XC1, + OPCODE_AE_S32X2RA64S_IP, + OPCODE_AE_S24X2RA64S_IP, + OPCODE_AE_S16X4RA32S_IP, + OPCODE_AE_ADDBRBA32, + OPCODE_AE_S32X2_L_IP, + OPCODE_AE_BITSWAP, + OPCODE_AE_MUL32JS, + OPCODE_AE_ADDANDSUB32S, + OPCODE_AE_ADDANDSUB32JS, + OPCODE_AE_ADDANDSUBRNG32, + OPCODE_AE_ADDANDSUBRNG32_H, + OPCODE_AE_ADDANDSUBRNG32_L, + OPCODE_AE_ADDRNG32, + OPCODE_AE_SUBRNG32, + OPCODE_AE_RNG32X2, + OPCODE_AE_SEL16I, + OPCODE_AE_SEL16I_N, + OPCODE_AE_SHORTSWAP, + OPCODE_AE_MOVAB4, + OPCODE_AE_MOVAB2, + OPCODE_AE_MOVAB, + OPCODE_AE_MOVBA, + OPCODE_AE_MOVBA1X2, + OPCODE_AE_MOVBA4, + OPCODE_AE_MOVBA2, + OPCODE_AE_MOVB2, + OPCODE_AE_MOVB4, + OPCODE_AE_MOVT16X4, + OPCODE_AE_MOVF16X4, + OPCODE_AE_MOVT32X2, + OPCODE_AE_MOVF32X2, + OPCODE_AE_MOVSARA7X2, + OPCODE_AE_MOVSARD7, + OPCODE_AE_MOVASAR, + OPCODE_AE_MOVDA32X2, + OPCODE_AE_MOVDA32, + OPCODE_AE_MOVDA16X2, + OPCODE_AE_MOVDA16, + OPCODE_AE_MOVI, + OPCODE_AE_TRUNCP24A32X2, + OPCODE_AE_SAT16X4, + OPCODE_AE_CVT32X2F16_32, + OPCODE_AE_CVT32X2F16_10, + OPCODE_AE_SEXT32X2D16_32, + OPCODE_AE_SEXT32X2D16_10, + OPCODE_AE_CVTA32F24S_L, + OPCODE_AE_CVTA32F24S_H, + OPCODE_AE_CVTP24A16X2_LL, + OPCODE_AE_CVTP24A16X2_LH, + OPCODE_AE_CVTP24A16X2_HL, + OPCODE_AE_CVTP24A16X2_HH, + OPCODE_AE_TRUNCP24Q48X2, + OPCODE_AE_TRUNCA32X2F64S, + OPCODE_AE_TRUNCI32X2F64S, + OPCODE_AE_TRUNCA32F64S_L, + OPCODE_AE_TRUNCI32F64S_L, + OPCODE_AE_TRUNCP16, + OPCODE_AE_ROUND32X2F64SSYM, + OPCODE_AE_ROUND32X2F64SASYM, + OPCODE_AE_ROUND32X2F48SSYM, + OPCODE_AE_ROUND32X2F48SASYM, + OPCODE_AE_ROUND16X4F32SSYM, + OPCODE_AE_ROUND16X4F32SASYM, + OPCODE_AE_ROUND24X2F48SSYM, + OPCODE_AE_ROUND24X2F48SASYM, + OPCODE_AE_ROUNDSP16Q48X2SYM, + OPCODE_AE_ROUNDSP16Q48X2ASYM, + OPCODE_AE_MINABS32S, + OPCODE_AE_MAXABS32S, + OPCODE_AE_ROUNDSP16F24SYM, + OPCODE_AE_ROUNDSP16F24ASYM, + OPCODE_AE_MOV, + OPCODE_AE_MOVT64, + OPCODE_AE_MOVF64, + OPCODE_AE_CVTQ56A32S, + OPCODE_AE_CVT48A32, + OPCODE_AE_CVT64A32, + OPCODE_AE_CVTQ56P32S_L, + OPCODE_AE_CVTQ56P32S_H, + OPCODE_AE_CVT64F32_H, + OPCODE_AE_CVT48F32_L, + OPCODE_AE_CVT48F32_H, + OPCODE_AE_SAT48S, + OPCODE_AE_SATQ56S, + OPCODE_AE_SAT24S, + OPCODE_AE_TRUNCQ32, + OPCODE_AE_MINABS64S, + OPCODE_AE_MAXABS64S, + OPCODE_AE_ROUNDSQ32F48SYM, + OPCODE_AE_ROUNDSQ32F48ASYM, + OPCODE_AE_TRUNCA32Q48, + OPCODE_AE_MOVAD32_L, + OPCODE_AE_MOVAD32_H, + OPCODE_AE_MOVAD16_3, + OPCODE_AE_MOVAD16_2, + OPCODE_AE_MOVAD16_1, + OPCODE_AE_MOVAD16_0, + OPCODE_AE_SRA64_32, + OPCODE_AE_PKSR32, + OPCODE_AE_PKSR24, + OPCODE_AE_PKSRF32, + OPCODE_AE_PKSR16, + OPCODE_AE_TRUNCA16P24S_L, + OPCODE_AE_TRUNCA16P24S_H, + OPCODE_AE_ADD32, + OPCODE_AE_SUB32, + OPCODE_AE_ADDSUB32, + OPCODE_AE_SUBADD32, + OPCODE_AE_ADD16, + OPCODE_AE_SUB16, + OPCODE_AE_ADD32_HL_LH, + OPCODE_AE_ADDSUB32_HL_LH, + OPCODE_AE_NEG32, + OPCODE_AE_ABS32, + OPCODE_AE_NEG32_L, + OPCODE_AE_ADD24S, + OPCODE_AE_SUB24S, + OPCODE_AE_ADD32S, + OPCODE_AE_SUB32S, + OPCODE_AE_ADDSUB32S, + OPCODE_AE_SUBADD32S, + OPCODE_AE_ADD16S, + OPCODE_AE_SUB16S, + OPCODE_AE_ADD32S_HL_LH, + OPCODE_AE_ADDSUB32S_HL_LH, + OPCODE_AE_NEG24S, + OPCODE_AE_ABS24S, + OPCODE_AE_NEG32S, + OPCODE_AE_ABS32S, + OPCODE_AE_NEG16S, + OPCODE_AE_ABS16S, + OPCODE_AE_ABS16, + OPCODE_AE_MULC16JS_H, + OPCODE_AE_MULC16JS_L, + OPCODE_AE_MULAC16JS_H, + OPCODE_AE_MULAC16JS_L, + OPCODE_AE_LT16, + OPCODE_AE_LE16, + OPCODE_AE_EQ16, + OPCODE_AE_LT32, + OPCODE_AE_LE32, + OPCODE_AE_EQ32, + OPCODE_AE_MIN32, + OPCODE_AE_MAX32, + OPCODE_AE_MINMAX32, + OPCODE_AE_MINMAX16, + OPCODE_AE_MIN16, + OPCODE_AE_MAX16, + OPCODE_AE_ADD64, + OPCODE_AE_SUB64, + OPCODE_AE_NEG64, + OPCODE_AE_ABS64, + OPCODE_AE_ADDSQ56S, + OPCODE_AE_SUBSQ56S, + OPCODE_AE_ADD64S, + OPCODE_AE_SUB64S, + OPCODE_AE_NEGSQ56S, + OPCODE_AE_ABSSQ56S, + OPCODE_AE_NEG64S, + OPCODE_AE_ABS64S, + OPCODE_AE_AND, + OPCODE_AE_NAND, + OPCODE_AE_OR, + OPCODE_AE_XOR, + OPCODE_AE_SLAI24, + OPCODE_AE_SRLI24, + OPCODE_AE_SRAI24, + OPCODE_AE_SLAS24, + OPCODE_AE_SRLS24, + OPCODE_AE_SRAS24, + OPCODE_AE_SRAI16, + OPCODE_AE_SRAI16R, + OPCODE_AE_SLAI32, + OPCODE_AE_SRLI32, + OPCODE_AE_SRAI32, + OPCODE_AE_SRAI32R, + OPCODE_AE_SLAS32, + OPCODE_AE_SRLS32, + OPCODE_AE_SRAS32, + OPCODE_AE_SLAA32, + OPCODE_AE_SRLA32, + OPCODE_AE_SRAA32, + OPCODE_AE_SLAI16S, + OPCODE_AE_SLAA16S, + OPCODE_AE_SRAA16S, + OPCODE_AE_SRAA16RS, + OPCODE_AE_SLAI24S, + OPCODE_AE_SLAS24S, + OPCODE_AE_SLAI32S, + OPCODE_AE_SLAS32S, + OPCODE_AE_SLAA32S, + OPCODE_AE_SRAA32S, + OPCODE_AE_SRAA32RS, + OPCODE_AE_SLASQ56, + OPCODE_AE_SRLSQ56, + OPCODE_AE_SRASQ56, + OPCODE_AE_SLAAQ56, + OPCODE_AE_SRLAQ56, + OPCODE_AE_SRAAQ56, + OPCODE_AE_SLAI64, + OPCODE_AE_SRLI64, + OPCODE_AE_SRAI64, + OPCODE_AE_SLAS64, + OPCODE_AE_SRLS64, + OPCODE_AE_SRAS64, + OPCODE_AE_SLAA64, + OPCODE_AE_SRLA64, + OPCODE_AE_SRAA64, + OPCODE_AE_SLAISQ56S, + OPCODE_AE_SLASSQ56S, + OPCODE_AE_SLAASQ56S, + OPCODE_AE_SLAI64S, + OPCODE_AE_SLAS64S, + OPCODE_AE_SLAA64S, + OPCODE_AE_LT64, + OPCODE_AE_LE64, + OPCODE_AE_EQ64, + OPCODE_AE_MAX64, + OPCODE_AE_MIN64, + OPCODE_AE_NSA64, + OPCODE_AE_NSAZ16_0, + OPCODE_AE_NSAZ32_L, + OPCODE_AE_MULS32F48P16S_LL, + OPCODE_AE_MULF32S_LL, + OPCODE_AE_MUL32_LL, + OPCODE_AE_MULF32R_LL, + OPCODE_AE_MULF32RA_LL, + OPCODE_AE_MULS32F48P16S_LH, + OPCODE_AE_MULF32S_LH, + OPCODE_AE_MUL32_LH, + OPCODE_AE_MULF32R_LH, + OPCODE_AE_MULF32RA_LH, + OPCODE_AE_MULS32F48P16S_HH, + OPCODE_AE_MULF32S_HH, + OPCODE_AE_MUL32_HH, + OPCODE_AE_MULF32R_HH, + OPCODE_AE_MULF32RA_HH, + OPCODE_AE_MULAS32F48P16S_LL, + OPCODE_AE_MULAF32S_LL, + OPCODE_AE_MULA32_LL, + OPCODE_AE_MULAF32R_LL, + OPCODE_AE_MULAF32RA_LL, + OPCODE_AE_MULAS32F48P16S_LH, + OPCODE_AE_MULAF32S_LH, + OPCODE_AE_MULA32_LH, + OPCODE_AE_MULAF32R_LH, + OPCODE_AE_MULAF32RA_LH, + OPCODE_AE_MULAS32F48P16S_HH, + OPCODE_AE_MULAF32S_HH, + OPCODE_AE_MULA32_HH, + OPCODE_AE_MULAF32R_HH, + OPCODE_AE_MULAF32RA_HH, + OPCODE_AE_MULSS32F48P16S_LL, + OPCODE_AE_MULSF32S_LL, + OPCODE_AE_MULS32_LL, + OPCODE_AE_MULSF32R_LL, + OPCODE_AE_MULSF32RA_LL, + OPCODE_AE_MULSS32F48P16S_LH, + OPCODE_AE_MULSF32S_LH, + OPCODE_AE_MULS32_LH, + OPCODE_AE_MULSF32R_LH, + OPCODE_AE_MULSF32RA_LH, + OPCODE_AE_MULSS32F48P16S_HH, + OPCODE_AE_MULSF32S_HH, + OPCODE_AE_MULS32_HH, + OPCODE_AE_MULSF32R_HH, + OPCODE_AE_MULSF32RA_HH, + OPCODE_AE_MUL32U_LL, + OPCODE_AE_MULA32U_LL, + OPCODE_AE_MULS32U_LL, + OPCODE_AE_MULF16SS_33, + OPCODE_AE_MULF16SS_22, + OPCODE_AE_MULF16SS_32, + OPCODE_AE_MULF16SS_21, + OPCODE_AE_MULF16SS_31, + OPCODE_AE_MULF16SS_30, + OPCODE_AE_MULF16SS_10, + OPCODE_AE_MULF16SS_20, + OPCODE_AE_MULF16SS_11, + OPCODE_AE_MULF16SS_00, + OPCODE_AE_MULSF16SS_33, + OPCODE_AE_MULSF16SS_22, + OPCODE_AE_MULSF16SS_32, + OPCODE_AE_MULSF16SS_21, + OPCODE_AE_MULSF16SS_31, + OPCODE_AE_MULSF16SS_30, + OPCODE_AE_MULSF16SS_10, + OPCODE_AE_MULSF16SS_20, + OPCODE_AE_MULSF16SS_11, + OPCODE_AE_MULSF16SS_00, + OPCODE_AE_MULAF16SS_33, + OPCODE_AE_MULAF16SS_22, + OPCODE_AE_MULAF16SS_32, + OPCODE_AE_MULAF16SS_21, + OPCODE_AE_MULAF16SS_31, + OPCODE_AE_MULAF16SS_30, + OPCODE_AE_MULAF16SS_10, + OPCODE_AE_MULAF16SS_20, + OPCODE_AE_MULAF16SS_11, + OPCODE_AE_MULAF16SS_00, + OPCODE_AE_MUL16S_00, + OPCODE_AE_MULA16S_00, + OPCODE_AE_MULS16S_00, + OPCODE_AE_MULAAFD16SS_33_22, + OPCODE_AE_MULAAFD16SS_13_02, + OPCODE_AE_MULAAFD16SS_11_00, + OPCODE_AE_MULSSFD16SS_33_22, + OPCODE_AE_MULSSFD16SS_13_02, + OPCODE_AE_MULSSFD16SS_11_00, + OPCODE_AE_MULZAAFD16SS_33_22, + OPCODE_AE_MULZAAFD16SS_13_02, + OPCODE_AE_MULZAAFD16SS_11_00, + OPCODE_AE_MULZSSFD16SS_33_22, + OPCODE_AE_MULZSSFD16SS_13_02, + OPCODE_AE_MULZSSFD16SS_11_00, + OPCODE_AE_MULF48Q32SP16S_L, + OPCODE_AE_MULF48Q32SP16U_L, + OPCODE_AE_MULQ32SP16S_L, + OPCODE_AE_MULQ32SP16U_L, + OPCODE_AE_MULAF48Q32SP16S_L, + OPCODE_AE_MULAF48Q32SP16U_L, + OPCODE_AE_MULAQ32SP16S_L, + OPCODE_AE_MULAQ32SP16U_L, + OPCODE_AE_MULSF48Q32SP16S_L, + OPCODE_AE_MULSF48Q32SP16U_L, + OPCODE_AE_MULSQ32SP16S_L, + OPCODE_AE_MULSQ32SP16U_L, + OPCODE_AE_MULFP24X2RA, + OPCODE_AE_MULFP24X2R, + OPCODE_AE_MULAFP24X2RA, + OPCODE_AE_MULAFP24X2R, + OPCODE_AE_MULSFP24X2RA, + OPCODE_AE_MULSFP24X2R, + OPCODE_AE_MULZAAFD32S_HH_LL, + OPCODE_AE_MULZAAFD32RA_HH_LL, + OPCODE_AE_MULZAAD32_HH_LL, + OPCODE_AE_MULZAAFD32S_HL_LH, + OPCODE_AE_MULZAAFD32RA_HL_LH, + OPCODE_AE_MULZAAD32_HL_LH, + OPCODE_AE_MULZASFD32S_HH_LL, + OPCODE_AE_MULZASFD32RA_HH_LL, + OPCODE_AE_MULZASD32_HH_LL, + OPCODE_AE_MULZASFD32S_HL_LH, + OPCODE_AE_MULZASFD32RA_HL_LH, + OPCODE_AE_MULZASD32_HL_LH, + OPCODE_AE_MULZSAFD32S_HH_LL, + OPCODE_AE_MULZSAFD32RA_HH_LL, + OPCODE_AE_MULZSAD32_HH_LL, + OPCODE_AE_MULZSSFD32S_HH_LL, + OPCODE_AE_MULZSSFD32RA_HH_LL, + OPCODE_AE_MULZSSD32_HH_LL, + OPCODE_AE_MULZSSFD32S_HL_LH, + OPCODE_AE_MULZSSFD32RA_HL_LH, + OPCODE_AE_MULZSSD32_HL_LH, + OPCODE_AE_MULAAFD32S_HH_LL, + OPCODE_AE_MULAAFD32RA_HH_LL, + OPCODE_AE_MULAAD32_HH_LL, + OPCODE_AE_MULAAFD32S_HL_LH, + OPCODE_AE_MULAAFD32RA_HL_LH, + OPCODE_AE_MULAAD32_HL_LH, + OPCODE_AE_MULASFD32S_HH_LL, + OPCODE_AE_MULASFD32RA_HH_LL, + OPCODE_AE_MULASD32_HH_LL, + OPCODE_AE_MULASFD32S_HL_LH, + OPCODE_AE_MULASFD32RA_HL_LH, + OPCODE_AE_MULASD32_HL_LH, + OPCODE_AE_MULSAFD32S_HH_LL, + OPCODE_AE_MULSAFD32RA_HH_LL, + OPCODE_AE_MULSAD32_HH_LL, + OPCODE_AE_MULSSFD32S_HH_LL, + OPCODE_AE_MULSSFD32RA_HH_LL, + OPCODE_AE_MULSSD32_HH_LL, + OPCODE_AE_MULSSFD32S_HL_LH, + OPCODE_AE_MULSSFD32RA_HL_LH, + OPCODE_AE_MULSSD32_HL_LH, + OPCODE_AE_MULF32X16_L0, + OPCODE_AE_MUL32X16_L0, + OPCODE_AE_MULF32X16_L1, + OPCODE_AE_MUL32X16_L1, + OPCODE_AE_MULF32X16_L2, + OPCODE_AE_MUL32X16_L2, + OPCODE_AE_MULF32X16_L3, + OPCODE_AE_MUL32X16_L3, + OPCODE_AE_MULF32X16_H0, + OPCODE_AE_MUL32X16_H0, + OPCODE_AE_MULF32X16_H1, + OPCODE_AE_MUL32X16_H1, + OPCODE_AE_MULF32X16_H2, + OPCODE_AE_MUL32X16_H2, + OPCODE_AE_MULF32X16_H3, + OPCODE_AE_MUL32X16_H3, + OPCODE_AE_MULAF32X16_L0, + OPCODE_AE_MULA32X16_L0, + OPCODE_AE_MULAF32X16_L1, + OPCODE_AE_MULA32X16_L1, + OPCODE_AE_MULAF32X16_L2, + OPCODE_AE_MULA32X16_L2, + OPCODE_AE_MULAF32X16_L3, + OPCODE_AE_MULA32X16_L3, + OPCODE_AE_MULAF32X16_H0, + OPCODE_AE_MULA32X16_H0, + OPCODE_AE_MULAF32X16_H1, + OPCODE_AE_MULA32X16_H1, + OPCODE_AE_MULAF32X16_H2, + OPCODE_AE_MULA32X16_H2, + OPCODE_AE_MULAF32X16_H3, + OPCODE_AE_MULA32X16_H3, + OPCODE_AE_MULSF32X16_L0, + OPCODE_AE_MULS32X16_L0, + OPCODE_AE_MULSF32X16_L1, + OPCODE_AE_MULS32X16_L1, + OPCODE_AE_MULSF32X16_L2, + OPCODE_AE_MULS32X16_L2, + OPCODE_AE_MULSF32X16_L3, + OPCODE_AE_MULS32X16_L3, + OPCODE_AE_MULSF32X16_H0, + OPCODE_AE_MULS32X16_H0, + OPCODE_AE_MULSF32X16_H1, + OPCODE_AE_MULS32X16_H1, + OPCODE_AE_MULSF32X16_H2, + OPCODE_AE_MULS32X16_H2, + OPCODE_AE_MULSF32X16_H3, + OPCODE_AE_MULS32X16_H3, + OPCODE_AE_MULAAFD32X16_H3_L2, + OPCODE_AE_MULAAD32X16_H3_L2, + OPCODE_AE_MULAAFD32X16_H1_L0, + OPCODE_AE_MULAAD32X16_H1_L0, + OPCODE_AE_MULASFD32X16_H3_L2, + OPCODE_AE_MULASD32X16_H3_L2, + OPCODE_AE_MULASFD32X16_H1_L0, + OPCODE_AE_MULASD32X16_H1_L0, + OPCODE_AE_MULSAFD32X16_H3_L2, + OPCODE_AE_MULSAD32X16_H3_L2, + OPCODE_AE_MULSAFD32X16_H1_L0, + OPCODE_AE_MULSAD32X16_H1_L0, + OPCODE_AE_MULSSFD32X16_H3_L2, + OPCODE_AE_MULSSD32X16_H3_L2, + OPCODE_AE_MULSSFD32X16_H1_L0, + OPCODE_AE_MULSSD32X16_H1_L0, + OPCODE_AE_MULZAAFD32X16_H3_L2, + OPCODE_AE_MULZAAD32X16_H3_L2, + OPCODE_AE_MULZAAFD32X16_H1_L0, + OPCODE_AE_MULZAAD32X16_H1_L0, + OPCODE_AE_MULZASFD32X16_H3_L2, + OPCODE_AE_MULZASD32X16_H3_L2, + OPCODE_AE_MULZASFD32X16_H1_L0, + OPCODE_AE_MULZASD32X16_H1_L0, + OPCODE_AE_MULZSAFD32X16_H3_L2, + OPCODE_AE_MULZSAD32X16_H3_L2, + OPCODE_AE_MULZSAFD32X16_H1_L0, + OPCODE_AE_MULZSAD32X16_H1_L0, + OPCODE_AE_MULZSSFD32X16_H3_L2, + OPCODE_AE_MULZSSD32X16_H3_L2, + OPCODE_AE_MULZSSFD32X16_H1_L0, + OPCODE_AE_MULZSSD32X16_H1_L0, + OPCODE_AE_MULZAAFD32X16_H2_L3, + OPCODE_AE_MULZAAFD32X16_H0_L1, + OPCODE_AE_MULAAFD32X16_H2_L3, + OPCODE_AE_MULAAFD32X16_H0_L1, + OPCODE_AE_MULZAAD32X16_H2_L3, + OPCODE_AE_MULZAAD32X16_H0_L1, + OPCODE_AE_MULAAD32X16_H2_L3, + OPCODE_AE_MULAAD32X16_H0_L1, + OPCODE_AE_MULP32X16X2_H, + OPCODE_AE_MULFP32X16X2RS_H, + OPCODE_AE_MULFP32X16X2RAS_H, + OPCODE_AE_MULFP32X16X2S_H, + OPCODE_AE_MULP32X16X2_L, + OPCODE_AE_MULFP32X16X2RS_L, + OPCODE_AE_MULFP32X16X2RAS_L, + OPCODE_AE_MULFP32X16X2S_L, + OPCODE_AE_MULAP32X16X2_H, + OPCODE_AE_MULAFP32X16X2RS_H, + OPCODE_AE_MULAFP32X16X2RAS_H, + OPCODE_AE_MULAFP32X16X2S_H, + OPCODE_AE_MULAP32X16X2_L, + OPCODE_AE_MULAFP32X16X2RS_L, + OPCODE_AE_MULAFP32X16X2RAS_L, + OPCODE_AE_MULAFP32X16X2S_L, + OPCODE_AE_MULSP32X16X2_H, + OPCODE_AE_MULSFP32X16X2RS_H, + OPCODE_AE_MULSFP32X16X2RAS_H, + OPCODE_AE_MULSFP32X16X2S_H, + OPCODE_AE_MULSP32X16X2_L, + OPCODE_AE_MULSFP32X16X2RS_L, + OPCODE_AE_MULSFP32X16X2RAS_L, + OPCODE_AE_MULSFP32X16X2S_L, + OPCODE_AE_MULP32X2, + OPCODE_AE_MULFP32X2RS, + OPCODE_AE_MULFP32X2RAS, + OPCODE_AE_MULFP32X2TS, + OPCODE_AE_MULP32X2T, + OPCODE_AE_MULAP32X2, + OPCODE_AE_MULAFP32X2RS, + OPCODE_AE_MULAFP32X2RAS, + OPCODE_AE_MULAFP32X2TS, + OPCODE_AE_MULAP32X2T, + OPCODE_AE_MULSP32X2, + OPCODE_AE_MULSFP32X2RS, + OPCODE_AE_MULSFP32X2RAS, + OPCODE_AE_MULSFP32X2TS, + OPCODE_AE_MULSP32X2T, + OPCODE_AE_MULFP16X4S, + OPCODE_AE_MULFP16X4RAS, + OPCODE_AE_MULC32, + OPCODE_AE_MULFC24RA, + OPCODE_AE_MULFC32RAS, + OPCODE_AE_MULC32X16_L, + OPCODE_AE_MULFC32X16RAS_L, + OPCODE_AE_MULC32X16_H, + OPCODE_AE_MULFC32X16RAS_H, + OPCODE_AE_MULAC32, + OPCODE_AE_MULAFC24RA, + OPCODE_AE_MULAFC32RAS, + OPCODE_AE_MULAC32X16_L, + OPCODE_AE_MULAFC32X16RAS_L, + OPCODE_AE_MULAC32X16_H, + OPCODE_AE_MULAFC32X16RAS_H, + OPCODE_AE_MULF16X4SS, + OPCODE_AE_MULAF16X4SS, + OPCODE_AE_MULSF16X4SS, + OPCODE_AE_MUL16X4S, + OPCODE_AE_MULA16X4S, + OPCODE_AE_MULS16X4S, + OPCODE_AE_MUL16X4, + OPCODE_AE_MULA16X4, + OPCODE_AE_MULS16X4, + OPCODE_AE_MULFD32X2S_FIR_H, + OPCODE_AE_MULFD32X2RA_FIR_H, + OPCODE_AE_MULFD32X2S_FIR_L, + OPCODE_AE_MULFD32X2RA_FIR_L, + OPCODE_AE_MULFD32X16X2_FIR_HH, + OPCODE_AE_MULFD32X16X2_FIR_HL, + OPCODE_AE_MULFD32X16X2_FIR_LH, + OPCODE_AE_MULFD32X16X2_FIR_LL, + OPCODE_AE_MULAFD32X2S_FIR_H, + OPCODE_AE_MULAFD32X2RA_FIR_H, + OPCODE_AE_MULAFD32X2S_FIR_L, + OPCODE_AE_MULAFD32X2RA_FIR_L, + OPCODE_AE_MULAFD32X16X2_FIR_HH, + OPCODE_AE_MULAFD32X16X2_FIR_HL, + OPCODE_AE_MULAFD32X16X2_FIR_LH, + OPCODE_AE_MULAFD32X16X2_FIR_LL, + OPCODE_AE_MULC16S_H, + OPCODE_AE_MULC16S_L, + OPCODE_AE_MULAC16S_H, + OPCODE_AE_MULAC16S_L, + OPCODE_AE_MULFC16RAS, + OPCODE_AE_MULAFC16RAS, + OPCODE_AE_MUL16JS, + OPCODE_AE_ADDANDSUBRNG16RAS_S1, + OPCODE_AE_ADDANDSUBRNG16RAS_S2, + OPCODE_AE_CONJ16S, + OPCODE_AE_MULFQ16X2_FIR_3, + OPCODE_AE_MULFQ16X2_FIR_2, + OPCODE_AE_MULFQ16X2_FIR_1, + OPCODE_AE_MULFQ16X2_FIR_0, + OPCODE_AE_MULAFQ16X2_FIR_3, + OPCODE_AE_MULAFQ16X2_FIR_2, + OPCODE_AE_MULAFQ16X2_FIR_1, + OPCODE_AE_MULAFQ16X2_FIR_0, + OPCODE_AE_MULZAAAAFQ32X16, + OPCODE_AE_MULAAAAFQ32X16, + OPCODE_AE_MULZAAAAQ32X16, + OPCODE_AE_MULAAAAQ32X16, + OPCODE_AE_MUL16_00, + OPCODE_AE_MULA16_00, + OPCODE_AE_MULZAAAAQ16, + OPCODE_AE_MULAAAAQ16, + OPCODE_AE_DIV64D32_H, + OPCODE_AE_DIV64D32_L, + OPCODE_AE_SHA32, + OPCODE_AE_VLDL32T, + OPCODE_AE_VLDL16T, + OPCODE_AE_VLDL16C, + OPCODE_AE_VLDL16C_IP, + OPCODE_AE_VLDL16C_IC, + OPCODE_AE_VLDL16C_IC1, + OPCODE_AE_VLDSHT, + OPCODE_AE_LB, + OPCODE_AE_LBI, + OPCODE_AE_LBK, + OPCODE_AE_LBKI, + OPCODE_AE_LBS, + OPCODE_AE_LBSI, + OPCODE_AE_DB, + OPCODE_AE_DBI, + OPCODE_AE_DB_IC, + OPCODE_AE_DBI_IC, + OPCODE_AE_DB_IC1, + OPCODE_AE_DBI_IC1, + OPCODE_AE_DB_IP, + OPCODE_AE_DBI_IP, + OPCODE_AE_ARDECNORM16, + OPCODE_AE_LBKI_DBI_IC, + OPCODE_AE_LBKI_DBI_IP, + OPCODE_AE_LBKI_DBI, + OPCODE_AE_LBI_DBI_IC, + OPCODE_AE_LBI_DBI_IP, + OPCODE_AE_LBI_DBI, + OPCODE_AE_LBK_DB_IC, + OPCODE_AE_LBK_DB_IP, + OPCODE_AE_LBK_DB, + OPCODE_AE_LB_DB_IC, + OPCODE_AE_LB_DB_IP, + OPCODE_AE_LB_DB, + OPCODE_AE_VLEL32T, + OPCODE_AE_VLEL16T, + OPCODE_AE_SB, + OPCODE_AE_SBI, + OPCODE_AE_VLES16C, + OPCODE_AE_SBF, + OPCODE_AE_SB_IC, + OPCODE_AE_SBI_IC, + OPCODE_AE_VLES16C_IC, + OPCODE_AE_SBF_IC, + OPCODE_AE_SB_IC1, + OPCODE_AE_SBI_IC1, + OPCODE_AE_VLES16C_IC1, + OPCODE_AE_SBF_IC1, + OPCODE_AE_SB_IP, + OPCODE_AE_SBI_IP, + OPCODE_AE_VLES16C_IP, + OPCODE_AE_SBF_IP, + OPCODE_AE_SEXT32, + OPCODE_AE_MOVAE, + OPCODE_AE_MOVEA, + OPCODE_AE_MOVEEP, + OPCODE_AE_SEXT72, + OPCODE_AE_ADD72, + OPCODE_AE_SUB72, + OPCODE_AE_ADD72X64, + OPCODE_AE_SUB72X64, + OPCODE_AE_MUL32EP_HH, + OPCODE_AE_MULA32EP_HH, + OPCODE_AE_MULS32EP_HH, + OPCODE_AE_MULZAAD32EP_HH_LL, + OPCODE_AE_MULZSSD32EP_HH_LL, + OPCODE_AE_MULAAD32EP_HH_LL, + OPCODE_AE_MULSSD32EP_HH_LL, + OPCODE_AE_MULAAD32USEP_HL_LH, + OPCODE_AE_MULZAAD32USEP_HL_LH, + OPCODE_AE_MUL32USEP_LH, + OPCODE_AE_MULA32USEP_LH, + OPCODE_AE_MUL32USEP_LL, + OPCODE_AE_MULA32USEP_LL, + OPCODE_AE_SRAI72, + OPCODE_AE_SLAI72, + OPCODE_AE_SAT64S, + OPCODE_AE_L16SI_N, + OPCODE_AE_L16UI_N, + OPCODE_AE_S16I_N, + OPCODE_AE_LALIGN128_I, + OPCODE_AE_SALIGN128_I, + OPCODE_AE_LA128_PP, + OPCODE_AE_SA128POS_FP, + OPCODE_AE_LA8X4S_IP, + OPCODE_AE_LA8X4U_IP, + OPCODE_AE_LA8X8X2_IP, + OPCODE_AE_LA16X4X2_IP, + OPCODE_AE_LA32X2X2_IP, + OPCODE_AE_LA8X8X2_IC, + OPCODE_AE_LA16X4X2_IC, + OPCODE_AE_LA32X2X2_IC, + OPCODE_AE_LA8X8X2_IC1, + OPCODE_AE_LA16X4X2_IC1, + OPCODE_AE_LA32X2X2_IC1, + OPCODE_AE_LA8X8X2_IC2, + OPCODE_AE_LA16X4X2_IC2, + OPCODE_AE_LA32X2X2_IC2, + OPCODE_AE_SA8X8X2_IP, + OPCODE_AE_SA16X4X2_IP, + OPCODE_AE_SA32X2X2_IP, + OPCODE_AE_SA8X8X2_IC, + OPCODE_AE_SA16X4X2_IC, + OPCODE_AE_SA32X2X2_IC, + OPCODE_AE_SA8X8X2_IC1, + OPCODE_AE_SA16X4X2_IC1, + OPCODE_AE_SA32X2X2_IC1, + OPCODE_AE_SA8X8X2_IC2, + OPCODE_AE_SA16X4X2_IC2, + OPCODE_AE_SA32X2X2_IC2, + OPCODE_AE_ABS8, + OPCODE_AE_ABS8S, + OPCODE_AE_NEG8S, + OPCODE_AE_ADD8, + OPCODE_AE_SUB8, + OPCODE_AE_MAX8, + OPCODE_AE_MIN8, + OPCODE_AE_ADD8S, + OPCODE_AE_SUB8S, + OPCODE_AE_LE8, + OPCODE_AE_LT8, + OPCODE_AE_EQ8, + OPCODE_AE_SATU16X4, + OPCODE_AE_SAT32X2, + OPCODE_AE_SATU32X2, + OPCODE_AE_SAT8X8X16, + OPCODE_AE_SATU8X8X16, + OPCODE_AE_SAT8X4X32_L, + OPCODE_AE_SATU8X4X32_L, + OPCODE_AE_ROUND8X8F16SSYM, + OPCODE_AE_ROUND8X8F16SASYM, + OPCODE_AE_ROUND8X4F32SSYM_L, + OPCODE_AE_ROUND8X4F32SASYM_L, + OPCODE_AE_MOVDA8, + OPCODE_AE_MOVAD8, + OPCODE_AE_MOVDX2, + OPCODE_AE_ADDANDSUB32J, + OPCODE_AE_ADDW8, + OPCODE_AE_ADDW16, + OPCODE_AE_ADDW32, + OPCODE_AE_SUBW8, + OPCODE_AE_SUBW16, + OPCODE_AE_SUBW32, + OPCODE_AE_ACCW8, + OPCODE_AE_ACCW16, + OPCODE_AE_ACCW32, + OPCODE_AE_ADDW8U, + OPCODE_AE_SUBW8U, + OPCODE_AE_ACCW8U, + OPCODE_AE_MULFP32X2S_HH_LL, + OPCODE_AE_MULAFP32X2S_HH_LL, + OPCODE_AE_MULSFP32X2S_HH_LL, + OPCODE_AE_MULFP32X2S_HL_LH, + OPCODE_AE_MULAFP32X2S_HL_LH, + OPCODE_AE_MULSFP32X2S_HL_LH, + OPCODE_AE_MULZAAF2D32S_HH_LL, + OPCODE_AE_MULZASF2D32S_HH_LL, + OPCODE_AE_MULZSAF2D32S_HH_LL, + OPCODE_AE_MULZSSF2D32S_HH_LL, + OPCODE_AE_MULAAF2D32S_HH_LL, + OPCODE_AE_MULASF2D32S_HH_LL, + OPCODE_AE_MULSAF2D32S_HH_LL, + OPCODE_AE_MULSSF2D32S_HH_LL, + OPCODE_AE_MULZAAF2D32S_HL_LH, + OPCODE_AE_MULZASF2D32S_HL_LH, + OPCODE_AE_MULZSAF2D32S_HL_LH, + OPCODE_AE_MULZSSF2D32S_HL_LH, + OPCODE_AE_MULAAF2D32S_HL_LH, + OPCODE_AE_MULASF2D32S_HL_LH, + OPCODE_AE_MULSAF2D32S_HL_LH, + OPCODE_AE_MULSSF2D32S_HL_LH, + OPCODE_AE_MUL32S_HH, + OPCODE_AE_MULA32S_HH, + OPCODE_AE_MULS32S_HH, + OPCODE_AE_MUL32S_LL, + OPCODE_AE_MULA32S_LL, + OPCODE_AE_MULS32S_LL, + OPCODE_AE_MUL32S_HL, + OPCODE_AE_MULA32S_HL, + OPCODE_AE_MULS32S_HL, + OPCODE_AE_MUL32S_LH, + OPCODE_AE_MULA32S_LH, + OPCODE_AE_MULS32S_LH, + OPCODE_AE_MUL32X2S_HH_LL, + OPCODE_AE_MULA32X2S_HH_LL, + OPCODE_AE_MULS32X2S_HH_LL, + OPCODE_AE_MUL32X2S_HL_LH, + OPCODE_AE_MULA32X2S_HL_LH, + OPCODE_AE_MULS32X2S_HL_LH, + OPCODE_AE_MULZAAD32S_HH_LL, + OPCODE_AE_MULZASD32S_HH_LL, + OPCODE_AE_MULZSAD32S_HH_LL, + OPCODE_AE_MULZSSD32S_HH_LL, + OPCODE_AE_MULAAD32S_HH_LL, + OPCODE_AE_MULASD32S_HH_LL, + OPCODE_AE_MULSAD32S_HH_LL, + OPCODE_AE_MULSSD32S_HH_LL, + OPCODE_AE_MULZAAD32S_HL_LH, + OPCODE_AE_MULZASD32S_HL_LH, + OPCODE_AE_MULZSAD32S_HL_LH, + OPCODE_AE_MULZSSD32S_HL_LH, + OPCODE_AE_MULAAD32S_HL_LH, + OPCODE_AE_MULASD32S_HL_LH, + OPCODE_AE_MULSAD32S_HL_LH, + OPCODE_AE_MULSSD32S_HL_LH, + OPCODE_AE_MULF32X2RA_HH_LL, + OPCODE_AE_MULAF32X2RA_HH_LL, + OPCODE_AE_MULSF32X2RA_HH_LL, + OPCODE_AE_MULF32X2RA_HL_LH, + OPCODE_AE_MULAF32X2RA_HL_LH, + OPCODE_AE_MULSF32X2RA_HL_LH, + OPCODE_AE_MULZAAF2D32RA_HH_LL, + OPCODE_AE_MULZASF2D32RA_HH_LL, + OPCODE_AE_MULZSAF2D32RA_HH_LL, + OPCODE_AE_MULZSSF2D32RA_HH_LL, + OPCODE_AE_MULAAF2D32RA_HH_LL, + OPCODE_AE_MULASF2D32RA_HH_LL, + OPCODE_AE_MULSAF2D32RA_HH_LL, + OPCODE_AE_MULSSF2D32RA_HH_LL, + OPCODE_AE_MULZAAF2D32RA_HL_LH, + OPCODE_AE_MULZASF2D32RA_HL_LH, + OPCODE_AE_MULZSAF2D32RA_HL_LH, + OPCODE_AE_MULZSSF2D32RA_HL_LH, + OPCODE_AE_MULAAF2D32RA_HL_LH, + OPCODE_AE_MULASF2D32RA_HL_LH, + OPCODE_AE_MULSAF2D32RA_HL_LH, + OPCODE_AE_MULSSF2D32RA_HL_LH, + OPCODE_AE_MULF32X2R_HH_LL, + OPCODE_AE_MULAF32X2R_HH_LL, + OPCODE_AE_MULSF32X2R_HH_LL, + OPCODE_AE_MULF32X2R_HL_LH, + OPCODE_AE_MULAF32X2R_HL_LH, + OPCODE_AE_MULSF32X2R_HL_LH, + OPCODE_AE_MULFC32W, + OPCODE_AE_MULAFC32W, + OPCODE_AE_MULFCJ32W, + OPCODE_AE_MULAFCJ32W, + OPCODE_AE_MULFCJ32RAS, + OPCODE_AE_MULAFCJ32RAS, + OPCODE_AE_MULF2P32X4RS, + OPCODE_AE_MULAF2P32X4RS, + OPCODE_AE_MULSF2P32X4RS, + OPCODE_AE_MULF2P32X4RAS, + OPCODE_AE_MULAF2P32X4RAS, + OPCODE_AE_MULSF2P32X4RAS, + OPCODE_AE_MULP32X2S, + OPCODE_AE_MUL2P32X4S, + OPCODE_AE_MUL2P32X4, + OPCODE_AE_MULA2P32X4, + OPCODE_AE_MULS2P32X4, + OPCODE_AE_MUL2P32X4T, + OPCODE_AE_MULA2P32X4T, + OPCODE_AE_MULS2P32X4T, + OPCODE_AE_MULZAA32X2_HH_LL, + OPCODE_AE_MULZSS32X2_HH_LL, + OPCODE_AE_MULAA32X2_HH_LL, + OPCODE_AE_MULSS32X2_HH_LL, + OPCODE_AE_MULCJ32, + OPCODE_AE_MULACJ32, + OPCODE_AE_MULADDF32RS, + OPCODE_AE_MULADDF32RAS, + OPCODE_AE_MULSUBF32RS, + OPCODE_AE_MULSUBF32RAS, + OPCODE_AE_MULFC32RA, + OPCODE_AE_MULAFC32RA, + OPCODE_AE_MULCJ32W, + OPCODE_AE_MULACJ32W, + OPCODE_AE_MULC32W, + OPCODE_AE_MULAC32W, + OPCODE_AE_MULF2D32X2WS, + OPCODE_AE_MULZAAAA2Q16, + OPCODE_AE_MULAAAA2Q16, + OPCODE_AE_MULP16S_H, + OPCODE_AE_MULAP16S_H, + OPCODE_AE_MULSP16S_H, + OPCODE_AE_MULP16S_L, + OPCODE_AE_MULAP16S_L, + OPCODE_AE_MULSP16S_L, + OPCODE_AE_MULC16W_H, + OPCODE_AE_MULAC16W_H, + OPCODE_AE_MULC16W_L, + OPCODE_AE_MULAC16W_L, + OPCODE_AE_MUL2C16S, + OPCODE_AE_MULA2C16S, + OPCODE_AE_MULFC16S, + OPCODE_AE_MULAFC16S, + OPCODE_AE_MULFCJ16S, + OPCODE_AE_MULAFCJ16S, + OPCODE_AE_MULFCJ16RAS, + OPCODE_AE_MULAFCJ16RAS, + OPCODE_AE_MULC16S, + OPCODE_AE_MULAC16S, + OPCODE_AE_MULFP16X4RS, + OPCODE_AE_MULFD16X16X4RAS, + OPCODE_AE_MULP16X16X4S, + OPCODE_AE_MULAP16X16X4S, + OPCODE_AE_MULSP16X16X4S, + OPCODE_AE_MULZAA2D16SS_HH_LL, + OPCODE_AE_MULZAA2D16SS_HL_LH, + OPCODE_AE_MULZSS2D16SS_HH_LL, + OPCODE_AE_MULZSS2D16SS_HL_LH, + OPCODE_AE_MULAA2D16SS_HH_LL, + OPCODE_AE_MULAA2D16SS_HL_LH, + OPCODE_AE_MULSS2D16SS_HH_LL, + OPCODE_AE_MULSS2D16SS_HL_LH, + OPCODE_AE_MULZAAFD16SS_HH_LL, + OPCODE_AE_MULZAAFD16SS_HL_LH, + OPCODE_AE_MULZSSFD16SS_HH_LL, + OPCODE_AE_MULZSSFD16SS_HL_LH, + OPCODE_AE_MULAAFD16SS_HH_LL, + OPCODE_AE_MULAAFD16SS_HL_LH, + OPCODE_AE_MULSSFD16SS_HH_LL, + OPCODE_AE_MULSSFD16SS_HL_LH, + OPCODE_AE_MULFD16X16X4WS, + OPCODE_AE_MULZAAAA2Q16X8, + OPCODE_AE_MULAAAA2Q16X8, + OPCODE_AE_MULZAAAA2Q8, + OPCODE_AE_MULAAAA2Q8, + OPCODE_AE_MULC32X16W_H, + OPCODE_AE_MULAC32X16W_H, + OPCODE_AE_MULC32X16W_L, + OPCODE_AE_MULAC32X16W_L, + OPCODE_AE_MULPC32X16X2, + OPCODE_AE_MULAPC32X16X2, + OPCODE_AE_MULFP32X16_H, + OPCODE_AE_MULAFP32X16_H, + OPCODE_AE_MULSFP32X16_H, + OPCODE_AE_MULFP32X16_L, + OPCODE_AE_MULAFP32X16_L, + OPCODE_AE_MULSFP32X16_L, + OPCODE_AE_MULFC32X16W_H, + OPCODE_AE_MULAFC32X16W_H, + OPCODE_AE_MULFC32X16W_L, + OPCODE_AE_MULAFC32X16W_L, + OPCODE_AE_MULFCJ32X16W_H, + OPCODE_AE_MULAFCJ32X16W_H, + OPCODE_AE_MULFCJ32X16W_L, + OPCODE_AE_MULAFCJ32X16W_L, + OPCODE_AE_MULF2P32X16X4RAS, + OPCODE_AE_MULAF2P32X16X4RAS, + OPCODE_AE_MULSF2P32X16X4RAS, + OPCODE_AE_MULF2P32X16X4RS, + OPCODE_AE_MULAF2P32X16X4RS, + OPCODE_AE_MULSF2P32X16X4RS, + OPCODE_AE_MULF2P32X16X4S, + OPCODE_AE_MULAF2P32X16X4S, + OPCODE_AE_MULSF2P32X16X4S, + OPCODE_AE_MULFPC32X16X2RAS, + OPCODE_AE_MULAFPC32X16X2RAS, + OPCODE_AE_MULFPCJ32X16X2RAS, + OPCODE_AE_MULAFPCJ32X16X2RAS, + OPCODE_AE_MULZAAAA2Q32X16, + OPCODE_AE_MULAAAA2Q32X16, + OPCODE_AE_MUL2Q32X16_FIR_H, + OPCODE_AE_MULA2Q32X16_FIR_H, + OPCODE_AE_MUL2Q32X16_FIR_L, + OPCODE_AE_MULA2Q32X16_FIR_L, + OPCODE_AE_SRAI8, + OPCODE_AE_SRAI8R, + OPCODE_AE_SRLI8, + OPCODE_AE_SLAI8, + OPCODE_AE_SLAI8S, + OPCODE_AE_SLAA8, + OPCODE_AE_SRLA8, + OPCODE_AE_SLAA8S, + OPCODE_AE_SRAA8RS, + OPCODE_AE_SRAA8S, + OPCODE_AE_SRLI16, + OPCODE_AE_SLAI16, + OPCODE_AE_SLAA16, + OPCODE_AE_SRLA16, + OPCODE_AE_SRAI16SYM, + OPCODE_AE_SRAA16SYMS, + OPCODE_AE_SRAI32SYM, + OPCODE_AE_SRAA32SYMS, + OPCODE_AE_SRAV16RS, + OPCODE_AE_SRAV32RS, + OPCODE_AE_CVTI32X4F8_H, + OPCODE_AE_CVTI32X4F8_L, + OPCODE_AE_CVTI32X4F8S_H, + OPCODE_AE_CVTI32X4F8S_L, + OPCODE_AE_CVTA32X4F8_H, + OPCODE_AE_CVTA32X4F8_L, + OPCODE_AE_CVTA32X4F8S_H, + OPCODE_AE_CVTA32X4F8S_L, + OPCODE_AE_CVTI32X4F8U_H, + OPCODE_AE_CVTI32X4F8U_L, + OPCODE_AE_CVTI32X4F8US_H, + OPCODE_AE_CVTI32X4F8US_L, + OPCODE_AE_CVTA32X4F8U_H, + OPCODE_AE_CVTA32X4F8U_L, + OPCODE_AE_CVTA32X4F8US_H, + OPCODE_AE_CVTA32X4F8US_L, + OPCODE_AE_CVTI32X4F16, + OPCODE_AE_CVTI32X4F16S, + OPCODE_AE_CVTA32X4F16, + OPCODE_AE_CVTA32X4F16S, + OPCODE_AE_CVTI32X4F16U, + OPCODE_AE_CVTI32X4F16US, + OPCODE_AE_CVTA32X4F16U, + OPCODE_AE_CVTA32X4F16US, + OPCODE_AE_CVTI16X4X2F8, + OPCODE_AE_CVTI16X4X2F8S, + OPCODE_AE_CVTA16X4X2F8, + OPCODE_AE_CVTA16X4X2F8S, + OPCODE_AE_CVTI16X4X2F8U, + OPCODE_AE_CVTI16X4X2F8US, + OPCODE_AE_CVTA16X4X2F8U, + OPCODE_AE_CVTA16X4X2F8US, + OPCODE_AE_SEL8X8, + OPCODE_AE_SHFL8X8, + OPCODE_AE_SEL16X4, + OPCODE_AE_SHFL16X4, + OPCODE_AE_DSEL8X8, + OPCODE_AE_DSEL16X4, + OPCODE_AE_SEL8X8I, + OPCODE_AE_RMAX8X8, + OPCODE_AE_RMIN8X8, + OPCODE_AE_RMAX16X4, + OPCODE_AE_RMIN16X4, + OPCODE_AE_SORT16X4, + OPCODE_AE_RADD8X8_H, + OPCODE_AE_RADDA8X8_H, + OPCODE_AE_RADD8X8_L, + OPCODE_AE_RADDA8X8_L, + OPCODE_AE_RADD16X4, + OPCODE_AE_RADDA16X4, + OPCODE_AE_BMAX8X8_H, + OPCODE_AE_BMAX8X8_L, + OPCODE_AE_BMIN8X8_H, + OPCODE_AE_BMIN8X8_L, + OPCODE_AE_BMAX16X4, + OPCODE_AE_BMIN16X4, + OPCODE_AE_BMAX32X2, + OPCODE_AE_BMIN32X2, + OPCODE_AE_ADDINV16S, + OPCODE_AE_ADDINV32S, + OPCODE_AE_MOVT16X8, + OPCODE_AE_MOVT8X16_H, + OPCODE_AE_MOVT8X16_L, + OPCODE_AE_MOVBD1X4, + OPCODE_AE_MOVBD1X2, + OPCODE_AE_MOVNEG32S_T, + OPCODE_AE_MOVDEXT, + OPCODE_AE_MOVADEXT_H, + OPCODE_AE_MOVADEXT_L, + OPCODE_AE_NSA16X4, + OPCODE_AE_NSAZ32X4, + OPCODE_AE_NSA32X4, + OPCODE_AE_TRUNCI16X4F32S, + OPCODE_AE_TRUNCI16X4F64S, + OPCODE_AE_TRUNCA16X4F32S, + OPCODE_AE_TRUNCA16X4F64S, + OPCODE_AE_ADDC32, + OPCODE_AE_SUBC32, + OPCODE_AE_ADDC32U, + OPCODE_AE_SUBC32U, + OPCODE_AE_EXPADD16_H, + OPCODE_AE_EXPSUB16_H, + OPCODE_AE_EXPADD16_L, + OPCODE_AE_EXPSUB16_L, + OPCODE_AE_ADDCEXP32_H, + OPCODE_AE_ADDCEXP32_L, + OPCODE_AE_CALCRNG16, + OPCODE_AE_CALCRNG32, + OPCODE_AE_RNG32X4, + OPCODE_AE_LAV8X8X2_XP, + OPCODE_AE_LAV16X4X2_XP, + OPCODE_AE_SAV8X8X2_XP, + OPCODE_AE_SAV16X4X2_XP, + OPCODE_AE_MOVZBVCDR, + OPCODE_AE_MOVDRZBVC, + OPCODE_AE_LAVUNSQZ8X8_XP, + OPCODE_AE_LAVUNSQZ16X4_XP, + OPCODE_AE_MUL8Q8X8, + OPCODE_AE_MULA8Q8X8, + OPCODE_AE_MUL8Q4X16, + OPCODE_AE_MULA8Q4X16, + OPCODE_AE_MUL8Q8X16, + OPCODE_AE_MULA8Q8X16, + OPCODE_AE_MUL8QW8X16, + OPCODE_AE_MULA8QW8X16, + OPCODE_AE_MUL4O8X8, + OPCODE_AE_MULA4O8X8, + OPCODE_AE_MUL4O4X16, + OPCODE_AE_MULA4O4X16, + OPCODE_AE_MUL4O8X16, + OPCODE_AE_MULA4O8X16, + OPCODE_AE_MUL4QW8X16, + OPCODE_AE_MULA4QW8X16, + OPCODE_AE_MUL8Q8X8CNV_L, + OPCODE_AE_MUL8Q8X8CNV_H, + OPCODE_AE_MULA8Q8X8CNV_L, + OPCODE_AE_MULA8Q8X8CNV_H, + OPCODE_AE_MUL8Q8X16CNV, + OPCODE_AE_MULA8Q8X16CNV, + OPCODE_AE_MUL2X4Q8X8CNV_H, + OPCODE_AE_MULA2X4Q8X8CNV_H, + OPCODE_AE_MUL2X4Q8X8CNV_L, + OPCODE_AE_MULA2X4Q8X8CNV_L, + OPCODE_AE_MUL2X4Q8X16CNV, + OPCODE_AE_MULA2X4Q8X16CNV, + OPCODE_AE_MULQQ8X16CNV, + OPCODE_AE_MULAQQ8X16CNV, + OPCODE_AE_MUL4O8X8CNV_H, + OPCODE_AE_MULA4O8X8CNV_H, + OPCODE_AE_MUL4O8X8CNV_L, + OPCODE_AE_MULA4O8X8CNV_L, + OPCODE_AE_MUL4O8X16CNV_H, + OPCODE_AE_MULA4O8X16CNV_H, + OPCODE_AE_MUL4O8X16CNV_L, + OPCODE_AE_MULA4O8X16CNV_L, + OPCODE_AE_MUL8Q4X16CNV_H, + OPCODE_AE_MULA8Q4X16CNV_H, + OPCODE_AE_MUL8Q4X16CNV_L, + OPCODE_AE_MULA8Q4X16CNV_L, + OPCODE_AE_MUL2X4Q4X16CNV_H, + OPCODE_AE_MULA2X4Q4X16CNV_H, + OPCODE_AE_MUL2X4Q4X16CNV_L, + OPCODE_AE_MULA2X4Q4X16CNV_L, + OPCODE_AE_MULQQ4X16CNV_H, + OPCODE_AE_MULAQQ4X16CNV_H, + OPCODE_AE_MULQQ4X16CNV_L, + OPCODE_AE_MULAQQ4X16CNV_L, + OPCODE_AE_MUL4O4X16CNV_HH, + OPCODE_AE_MUL4O4X16CNV_HL, + OPCODE_AE_MUL4O4X16CNV_LH, + OPCODE_AE_MUL4O4X16CNV_LL, + OPCODE_AE_MULA4O4X16CNV_HH, + OPCODE_AE_MULA4O4X16CNV_HL, + OPCODE_AE_MULA4O4X16CNV_LH, + OPCODE_AE_MULA4O4X16CNV_LL, + OPCODE_AE_MULUU8Q8X8, + OPCODE_AE_MULAUU8Q8X8, + OPCODE_AE_MULUU4O8X8, + OPCODE_AE_MULAUU4O8X8, + OPCODE_AE_MULUU8Q8X8CNV_L, + OPCODE_AE_MULAUU8Q8X8CNV_L, + OPCODE_AE_MULUU8Q8X8CNV_H, + OPCODE_AE_MULAUU8Q8X8CNV_H, + OPCODE_AE_MULUU2X4Q8X8CNV_H, + OPCODE_AE_MULAUU2X4Q8X8CNV_H, + OPCODE_AE_MULUU2X4Q8X8CNV_L, + OPCODE_AE_MULAUU2X4Q8X8CNV_L, + OPCODE_AE_MULUU4O8X8CNV_H, + OPCODE_AE_MULAUU4O8X8CNV_H, + OPCODE_AE_MULUU4O8X8CNV_L, + OPCODE_AE_MULAUU4O8X8CNV_L, + OPCODE_AE_MULUS8Q8X8, + OPCODE_AE_MULAUS8Q8X8, + OPCODE_AE_MULUS8Q4X16, + OPCODE_AE_MULAUS8Q4X16, + OPCODE_AE_MULUS8Q8X16, + OPCODE_AE_MULAUS8Q8X16, + OPCODE_AE_MULUS8QW8X16, + OPCODE_AE_MULAUS8QW8X16, + OPCODE_AE_MULUS4O8X8, + OPCODE_AE_MULAUS4O8X8, + OPCODE_AE_MULUS4O4X16, + OPCODE_AE_MULAUS4O4X16, + OPCODE_AE_MULUS4O8X16, + OPCODE_AE_MULAUS4O8X16, + OPCODE_AE_MULUS4QW8X16, + OPCODE_AE_MULAUS4QW8X16, + OPCODE_AE_MULUS8Q8X8CNV_L, + OPCODE_AE_MULAUS8Q8X8CNV_L, + OPCODE_AE_MULUS8Q8X8CNV_H, + OPCODE_AE_MULAUS8Q8X8CNV_H, + OPCODE_AE_MULUS8Q8X16CNV, + OPCODE_AE_MULAUS8Q8X16CNV, + OPCODE_AE_MULUS2X4Q8X8CNV_H, + OPCODE_AE_MULAUS2X4Q8X8CNV_H, + OPCODE_AE_MULUS2X4Q8X8CNV_L, + OPCODE_AE_MULAUS2X4Q8X8CNV_L, + OPCODE_AE_MULUS2X4Q8X16CNV, + OPCODE_AE_MULAUS2X4Q8X16CNV, + OPCODE_AE_MULUSQQ8X16CNV, + OPCODE_AE_MULAUSQQ8X16CNV, + OPCODE_AE_MULUS4O8X8CNV_H, + OPCODE_AE_MULAUS4O8X8CNV_H, + OPCODE_AE_MULUS4O8X8CNV_L, + OPCODE_AE_MULAUS4O8X8CNV_L, + OPCODE_AE_MULUS4O8X16CNV_H, + OPCODE_AE_MULAUS4O8X16CNV_H, + OPCODE_AE_MULUS4O8X16CNV_L, + OPCODE_AE_MULAUS4O8X16CNV_L, + OPCODE_AE_MULUS8Q4X16CNV_H, + OPCODE_AE_MULAUS8Q4X16CNV_H, + OPCODE_AE_MULUS8Q4X16CNV_L, + OPCODE_AE_MULAUS8Q4X16CNV_L, + OPCODE_AE_MULUS2X4Q4X16CNV_H, + OPCODE_AE_MULAUS2X4Q4X16CNV_H, + OPCODE_AE_MULUS2X4Q4X16CNV_L, + OPCODE_AE_MULAUS2X4Q4X16CNV_L, + OPCODE_AE_MULUSQQ4X16CNV_H, + OPCODE_AE_MULAUSQQ4X16CNV_H, + OPCODE_AE_MULUSQQ4X16CNV_L, + OPCODE_AE_MULAUSQQ4X16CNV_L, + OPCODE_AE_MULUS4O4X16CNV_HH, + OPCODE_AE_MULUS4O4X16CNV_HL, + OPCODE_AE_MULUS4O4X16CNV_LH, + OPCODE_AE_MULUS4O4X16CNV_LL, + OPCODE_AE_MULAUS4O4X16CNV_HH, + OPCODE_AE_MULAUS4O4X16CNV_HL, + OPCODE_AE_MULAUS4O4X16CNV_LH, + OPCODE_AE_MULAUS4O4X16CNV_LL, + OPCODE_AE_MULSU8Q8X8, + OPCODE_AE_MULASU8Q8X8, + OPCODE_AE_MULSU4O8X8, + OPCODE_AE_MULASU4O8X8, + OPCODE_AE_MULSU8Q8X8CNV_L, + OPCODE_AE_MULASU8Q8X8CNV_L, + OPCODE_AE_MULSU8Q8X8CNV_H, + OPCODE_AE_MULASU8Q8X8CNV_H, + OPCODE_AE_MULSU2X4Q8X8CNV_H, + OPCODE_AE_MULASU2X4Q8X8CNV_H, + OPCODE_AE_MULSU2X4Q8X8CNV_L, + OPCODE_AE_MULASU2X4Q8X8CNV_L, + OPCODE_AE_MULSU4O8X8CNV_H, + OPCODE_AE_MULASU4O8X8CNV_H, + OPCODE_AE_MULSU4O8X8CNV_L, + OPCODE_AE_MULASU4O8X8CNV_L, + OPCODE_AE_MULUUZB8Q8X8, + OPCODE_AE_MULAUUZB8Q8X8, + OPCODE_AE_MULUUZB4O8X8, + OPCODE_AE_MULAUUZB4O8X8, + OPCODE_AE_MULUUZB8Q8X8CNV_L, + OPCODE_AE_MULAUUZB8Q8X8CNV_L, + OPCODE_AE_MULUUZB8Q8X8CNV_H, + OPCODE_AE_MULAUUZB8Q8X8CNV_H, + OPCODE_AE_MULUUZB2X4Q8X8CNV_H, + OPCODE_AE_MULAUUZB2X4Q8X8CNV_H, + OPCODE_AE_MULUUZB2X4Q8X8CNV_L, + OPCODE_AE_MULAUUZB2X4Q8X8CNV_L, + OPCODE_AE_MULUUZB4O8X8CNV_H, + OPCODE_AE_MULAUUZB4O8X8CNV_H, + OPCODE_AE_MULUUZB4O8X8CNV_L, + OPCODE_AE_MULAUUZB4O8X8CNV_L, + OPCODE_AE_MULUUZB3X3O8X8, + OPCODE_AE_MULAUUZB3X3O8X8, + OPCODE_AE_MULZB8Q8X8, + OPCODE_AE_MULAZB8Q8X8, + OPCODE_AE_MULZB4O8X8, + OPCODE_AE_MULAZB4O8X8, + OPCODE_AE_MULZB8Q8X8CNV_L, + OPCODE_AE_MULAZB8Q8X8CNV_L, + OPCODE_AE_MULZB8Q8X8CNV_H, + OPCODE_AE_MULAZB8Q8X8CNV_H, + OPCODE_AE_MULZB2X4Q8X8CNV_H, + OPCODE_AE_MULAZB2X4Q8X8CNV_H, + OPCODE_AE_MULZB2X4Q8X8CNV_L, + OPCODE_AE_MULAZB2X4Q8X8CNV_L, + OPCODE_AE_MULZB4O8X8CNV_H, + OPCODE_AE_MULAZB4O8X8CNV_H, + OPCODE_AE_MULZB4O8X8CNV_L, + OPCODE_AE_MULAZB4O8X8CNV_L, + OPCODE_AE_MULZB3X3O8X8, + OPCODE_AE_MULAZB3X3O8X8, + OPCODE_CVTSF16_L, + OPCODE_CVTSF16_H, + OPCODE_CVTF16S_L, + OPCODE_CVTF16S_H, + OPCODE_AE_MOVFCRFSRV, + OPCODE_AE_MOVVFCRFSR, + OPCODE_MOVT_S, + OPCODE_MOVF_S, + OPCODE_MOVEQZ_S, + OPCODE_MOVNEZ_S, + OPCODE_MOVGEZ_S, + OPCODE_MOVLTZ_S, + OPCODE_RFR, + OPCODE_WFR, + OPCODE_MUL_S, + OPCODE_MADD_S, + OPCODE_MSUB_S, + OPCODE_MSUBN_S, + OPCODE_MADDN_S, + OPCODE_ADD_S, + OPCODE_SUB_S, + OPCODE_OLE_S, + OPCODE_OLT_S, + OPCODE_OEQ_S, + OPCODE_UN_S, + OPCODE_ULE_S, + OPCODE_ULT_S, + OPCODE_UEQ_S, + OPCODE_NEXP01_S, + OPCODE_MKSADJ_S, + OPCODE_MKDADJ_S, + OPCODE_DIV0_S, + OPCODE_SQRT0_S, + OPCODE_RECIP0_S, + OPCODE_RSQRT0_S, + OPCODE_DIVN_S, + OPCODE_ADDEXP_S, + OPCODE_ADDEXPM_S, + OPCODE_MIN_S, + OPCODE_MAX_S, + OPCODE_MULMUX_S, + OPCODE_MADDMUX_S, + OPCODE_TRUNC_S, + OPCODE_UTRUNC_S, + OPCODE_TRUNC_SX2, + OPCODE_UTRUNC_SX2, + OPCODE_FICEIL_S, + OPCODE_FIFLOOR_S, + OPCODE_FIRINT_S, + OPCODE_FIROUND_S, + OPCODE_FITRUNC_S, + OPCODE_FLOAT_S, + OPCODE_UFLOAT_S, + OPCODE_FLOAT_SX2, + OPCODE_UFLOAT_SX2, + OPCODE_ABS_S, + OPCODE_NEG_S, + OPCODE_CONJC_S, + OPCODE_MULJC_S, + OPCODE_CONST_S, + OPCODE_CLSFY_S, + OPCODE_MINNUM_S, + OPCODE_MAXNUM_S, + OPCODE_ADDANDSUB_S, + OPCODE_ADDANDSUBJC_S, + OPCODE_ADD_HL_LH_S, + OPCODE_MADDA_S, + OPCODE_FREXP_S, + OPCODE_FLOATEXP_S, + OPCODE_MINNUMABS_S, + OPCODE_MAXNUMABS_S, + OPCODE_MULQ_S, + OPCODE_MADDQ_S, + OPCODE_MSUBQ_S, + OPCODE_MULMUXQ_S, + OPCODE_MADDMUXQ_S, + OPCODE_BMAXNUM_S, + OPCODE_BMINNUM_S, + OPCODE_BMAXNUMABS_S, + OPCODE_BMINNUMABS_S, + OPCODE_ABS_SX2X2, + OPCODE_NEG_SX2X2, + OPCODE_CONJC_SX2X2, + OPCODE_MULJC_SX2X2, + OPCODE_CONST_SX2X2, + OPCODE_ADD_SX2X2, + OPCODE_SUB_SX2X2, + OPCODE_MUL_SX2X2, + OPCODE_MADD_SX2X2, + OPCODE_MSUB_SX2X2, + OPCODE_MULMUX_SX2X2, + OPCODE_MADDMUX_SX2X2, + OPCODE_ABS_H, + OPCODE_ADDEXP_H, + OPCODE_ADDEXPM_H, + OPCODE_CLSFY_H, + OPCODE_CONJC_H, + OPCODE_CONST_H, + OPCODE_MIN_H, + OPCODE_MAX_H, + OPCODE_MINNUM_H, + OPCODE_MAXNUM_H, + OPCODE_MULJC_H, + OPCODE_NEG_H, + OPCODE_OEQ_H, + OPCODE_OLE_H, + OPCODE_OLT_H, + OPCODE_UEQ_H, + OPCODE_ULE_H, + OPCODE_ULT_H, + OPCODE_UN_H, + OPCODE_DIV0_H, + OPCODE_FICEIL_H, + OPCODE_FIFLOOR_H, + OPCODE_FIRINT_H, + OPCODE_FIROUND_H, + OPCODE_FITRUNC_H, + OPCODE_MKDADJ_H, + OPCODE_MKSADJ_H, + OPCODE_NEXP0_H, + OPCODE_NEXP01_H, + OPCODE_RECIP0_H, + OPCODE_RSQRT0_H, + OPCODE_SQRT0_H, + OPCODE_FLOAT16_H, + OPCODE_UFLOAT16_H, + OPCODE_TRUNC16_H, + OPCODE_UTRUNC16_H, + OPCODE_FLOAT16_HX4, + OPCODE_UFLOAT16_HX4, + OPCODE_TRUNC16_HX4, + OPCODE_UTRUNC16_HX4, + OPCODE_ADD_H, + OPCODE_SUB_H, + OPCODE_MUL_H, + OPCODE_MADD_H, + OPCODE_MSUB_H, + OPCODE_MADDN_H, + OPCODE_MSUBN_H, + OPCODE_DIVN_H, + OPCODE_RMINNUM_H, + OPCODE_RMAXNUM_H, + OPCODE_ABS_HX4X2, + OPCODE_NEG_HX4X2, + OPCODE_CONJC_HX4X2, + OPCODE_CONST_HX4X2, + OPCODE_MULJC_HX4X2, + OPCODE_ADD_HX4X2, + OPCODE_SUB_HX4X2, + OPCODE_MUL_HX4X2, + OPCODE_MADD_HX4X2, + OPCODE_MSUB_HX4X2, + OPCODE_MULQ_H, + OPCODE_MADDQ_H, + OPCODE_MULCNVH_HX4X2, + OPCODE_MULACNVH_HX4X2, + OPCODE_MULCNVL_HX4X2, + OPCODE_MULACNVL_HX4X2 +}; + + +/* Slot-specific opcode decode functions. */ + +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst_get (insn) == 0) + { + if (Field_op1_Slot_inst_get (insn) == 0) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_r_Slot_inst_get (insn) == 0) + { + if (Field_m_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return OPCODE_ILL; + if (Field_m_Slot_inst_get (insn) == 2) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_RET; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_RETW; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_JX; + } + if (Field_m_Slot_inst_get (insn) == 3) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALLX0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALLX4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALLX8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALLX12; + } + } + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_MOVSP; + if (Field_r_Slot_inst_get (insn) == 2) + { + if (Field_s_Slot_inst_get (insn) == 0) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_ISYNC; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RSYNC; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_ESYNC; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DSYNC; + if (Field_t_Slot_inst_get (insn) == 8) + return OPCODE_EXCW; + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_MEMW; + if (Field_t_Slot_inst_get (insn) == 13) + return OPCODE_EXTW; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_NOP; + } + } + if (Field_r_Slot_inst_get (insn) == 3) + { + if (Field_t_Slot_inst_get (insn) == 0) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_RFE; + if (Field_s_Slot_inst_get (insn) == 2) + return OPCODE_RFDE; + if (Field_s_Slot_inst_get (insn) == 4) + return OPCODE_RFWO; + if (Field_s_Slot_inst_get (insn) == 5) + return OPCODE_RFWU; + } + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFI; + if (Field_t_Slot_inst_get (insn) == 2 && + Field_s_Slot_inst_get (insn) == 1) + return OPCODE_CLREX; + } + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BREAK; + if (Field_r_Slot_inst_get (insn) == 5) + { + if (Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SYSCALL; + if (Field_s_Slot_inst_get (insn) == 1) + return OPCODE_SIMCALL; + } + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RSIL; + if (Field_r_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_WAITI; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_LDDR32_P; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_SDDR32_P; + } + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_ANY4; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_ALL4; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_ANY8; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_ALL8; + } + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_AND; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_OR; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_XOR; + if (Field_op2_Slot_inst_get (insn) == 4) + { + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSR; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSL; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8L; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8B; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_thi3_Slot_inst_get (insn) == 0) + return OPCODE_SSAI; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RER; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_WER; + if (Field_r_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_ROTW; + if (Field_r_Slot_inst_get (insn) == 10 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_GETEX; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_NSA; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_NSAU; + } + if (Field_op2_Slot_inst_get (insn) == 5) + { + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_RPTLB0; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_PPTLB; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_WPTLB; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_RPTLB1; + } + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_NEG; + if (Field_s_Slot_inst_get (insn) == 1) + return OPCODE_ABS; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_ADD; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_ADDX2; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_ADDX4; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_ADDX8; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_SUB; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_SUBX2; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_SUBX4; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_SUBX8; + } + if (Field_op1_Slot_inst_get (insn) == 1) + { + if ((Field_op2_Slot_inst_get (insn) == 0 || + Field_op2_Slot_inst_get (insn) == 1)) + return OPCODE_SLLI; + if ((Field_op2_Slot_inst_get (insn) == 2 || + Field_op2_Slot_inst_get (insn) == 3)) + return OPCODE_SRAI; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_SRLI; + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_XSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_XSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_XSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_XSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_XSR_BR; + if (Field_sr_Slot_inst_get (insn) == 40) + return OPCODE_XSR_PREFCTL; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_XSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_XSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_XSR_MPUENB; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_XSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_XSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_XSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 98) + return OPCODE_XSR_CACHEADRDIS; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_XSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_XSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 119) + return OPCODE_XSR_OPMODE; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_XSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_XSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_XSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_XSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_XSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_XSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_XSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_XSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_XSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_XSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_XSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_XSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_XSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_XSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_XSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_XSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_XSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_XSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_XSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_XSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_XSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_XSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_XSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_XSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_XSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_XSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_XSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_XSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_XSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_XSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_XSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_XSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_XSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_XSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_XSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_XSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_XSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_XSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_XSR_MISC1; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_XSR_MISC2; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_XSR_MISC3; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_SRC; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRL; + if (Field_op2_Slot_inst_get (insn) == 10 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SLL; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRA; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MUL16U; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MUL16S; + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_LICT; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_SICT; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_LICW; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_SICW; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_L32EX; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_S32EX; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LDCT; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_SDCT; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_LDCW; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_SDCW; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_RFDO; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFDD; + } + } + if (Field_op1_Slot_inst_get (insn) == 2) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_ANDB; + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_ANDBC; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_ORB; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_ORBC; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_XORB; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_SALTU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_SALT; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MULL; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_QUOU; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_QUOS; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_REMU; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_REMS; + } + if (Field_op1_Slot_inst_get (insn) == 3) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_RSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_RSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_RSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_RSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_RSR_BR; + if (Field_sr_Slot_inst_get (insn) == 40) + return OPCODE_RSR_PREFCTL; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_RSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_RSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_RSR_MPUENB; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_RSR_MPUCFG; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_RSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_RSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_RSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 98) + return OPCODE_RSR_CACHEADRDIS; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_RSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_RSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 119) + return OPCODE_RSR_OPMODE; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_RSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_RSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_RSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_RSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_RSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_RSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_RSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_RSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_RSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_RSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_RSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_RSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_RSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_RSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_RSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_RSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_RSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_RSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_RSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 208) + return OPCODE_RSR_CONFIGID1; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_RSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_RSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_RSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_RSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_RSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_RSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_RSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_RSR_INTERRUPT; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_RSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_RSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_RSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_RSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_RSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_RSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 235) + return OPCODE_RSR_PRID; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_RSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_RSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_RSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_RSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_RSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_RSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_RSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_RSR_MISC1; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_RSR_MISC2; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_RSR_MISC3; + } + if (Field_op2_Slot_inst_get (insn) == 1) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_WSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_WSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_WSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_WSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_WSR_BR; + if (Field_sr_Slot_inst_get (insn) == 40) + return OPCODE_WSR_PREFCTL; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_WSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_WSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 89) + return OPCODE_WSR_MMID; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_WSR_MPUENB; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_WSR_MPUCFG; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_WSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_WSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_WSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 98) + return OPCODE_WSR_CACHEADRDIS; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_WSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_WSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 119) + return OPCODE_WSR_OPMODE; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_WSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_WSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_WSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_WSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_WSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_WSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_WSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_WSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_WSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_WSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_WSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_WSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_WSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_WSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_WSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_WSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_WSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_WSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_WSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_WSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_WSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_WSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_WSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_WSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_WSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_WSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_WSR_INTSET; + if (Field_sr_Slot_inst_get (insn) == 227) + return OPCODE_WSR_INTCLEAR; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_WSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_WSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_WSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_WSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_WSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_WSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_WSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_WSR_MISC1; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_WSR_MISC2; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_WSR_MISC3; + } + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_SEXT; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_CLAMPS; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_MIN; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_MAX; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_MINU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_MAXU; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MOVEQZ; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_MOVNEZ; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MOVLTZ; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MOVGEZ; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MOVF; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MOVT; + if (Field_op2_Slot_inst_get (insn) == 14) + { + if (Field_st_Slot_inst_get (insn) == 230) + return OPCODE_RUR_EXPSTATE; + if (Field_st_Slot_inst_get (insn) == 231) + return OPCODE_RUR_THREADPTR; + if (Field_st_Slot_inst_get (insn) == 232) + return OPCODE_RUR_FCR; + if (Field_st_Slot_inst_get (insn) == 233) + return OPCODE_RUR_FSR; + if (Field_st_Slot_inst_get (insn) == 240) + return OPCODE_RUR_AE_OVF_SAR; + if (Field_st_Slot_inst_get (insn) == 241) + return OPCODE_RUR_AE_BITHEAD; + if (Field_st_Slot_inst_get (insn) == 242) + return OPCODE_RUR_AE_TS_FTS_BU_BP; + if (Field_st_Slot_inst_get (insn) == 243) + return OPCODE_RUR_AE_CW_SD_NO; + if (Field_st_Slot_inst_get (insn) == 246) + return OPCODE_RUR_AE_CBEGIN0; + if (Field_st_Slot_inst_get (insn) == 247) + return OPCODE_RUR_AE_CEND0; + if (Field_st_Slot_inst_get (insn) == 248) + return OPCODE_RUR_AE_CBEGIN1; + if (Field_st_Slot_inst_get (insn) == 249) + return OPCODE_RUR_AE_CEND1; + if (Field_st_Slot_inst_get (insn) == 250) + return OPCODE_RUR_AE_CBEGIN2; + if (Field_st_Slot_inst_get (insn) == 251) + return OPCODE_RUR_AE_CEND2; + } + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WUR_EXPSTATE; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WUR_THREADPTR; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WUR_FCR; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WUR_FSR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WUR_AE_OVF_SAR; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WUR_AE_BITHEAD; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_WUR_AE_TS_FTS_BU_BP; + if (Field_sr_Slot_inst_get (insn) == 243) + return OPCODE_WUR_AE_CW_SD_NO; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_WUR_AE_CBEGIN0; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_WUR_AE_CEND0; + if (Field_sr_Slot_inst_get (insn) == 248) + return OPCODE_WUR_AE_CBEGIN1; + if (Field_sr_Slot_inst_get (insn) == 249) + return OPCODE_WUR_AE_CEND1; + if (Field_sr_Slot_inst_get (insn) == 250) + return OPCODE_WUR_AE_CBEGIN2; + if (Field_sr_Slot_inst_get (insn) == 251) + return OPCODE_WUR_AE_CEND2; + } + } + if ((Field_op1_Slot_inst_get (insn) == 4 || + Field_op1_Slot_inst_get (insn) == 5)) + return OPCODE_EXTUI; + if (Field_op1_Slot_inst_get (insn) == 9) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_L32E; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_S32E; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_S32NB; + } + if (Field_r_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_READ_IMPWIRE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_SETB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_CLRB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_WRMSK_EXPSTATE; + } + if (Field_op0_Slot_inst_get (insn) == 1) + return OPCODE_L32R; + if (Field_op0_Slot_inst_get (insn) == 2) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_L8UI; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_L16UI; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_L32I; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_S8I; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_S16I; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_S32I; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_DPFR; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_DPFW; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_DPFRO; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DPFWO; + if (Field_t_Slot_inst_get (insn) == 4) + return OPCODE_DHWB; + if (Field_t_Slot_inst_get (insn) == 5) + return OPCODE_DHWBI; + if (Field_t_Slot_inst_get (insn) == 6) + return OPCODE_DHI; + if (Field_t_Slot_inst_get (insn) == 7) + return OPCODE_DII; + if (Field_t_Slot_inst_get (insn) == 8) + { + if (Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_DPFL; + if (Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_DHU; + if (Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_DIU; + if (Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_DIWB; + if (Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_DIWBI; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_DIWBUI_P; + } + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_IPF; + if (Field_t_Slot_inst_get (insn) == 13) + { + if (Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_IPFL; + if (Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_IHU; + if (Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_IIU; + } + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_IHI; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_III; + } + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_L16SI; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_MOVI; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_L32AI; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_ADDI; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_ADDMI; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_S32RI; + } + if (Field_op0_Slot_inst_get (insn) == 4) + { + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 10) + return OPCODE_RUR_AE_OVERFLOW; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 11) + return OPCODE_WUR_AE_OVERFLOW; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_SAR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 13) + return OPCODE_WUR_AE_SAR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 14) + return OPCODE_RUR_AE_BITPTR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 15) + return OPCODE_WUR_AE_BITPTR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 0) + return OPCODE_RUR_AE_BITSUSED; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 1) + return OPCODE_WUR_AE_BITSUSED; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 2) + return OPCODE_RUR_AE_TABLESIZE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 3) + return OPCODE_WUR_AE_TABLESIZE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 4) + return OPCODE_RUR_AE_FIRST_TS; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 5) + return OPCODE_WUR_AE_FIRST_TS; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 6) + return OPCODE_RUR_AE_NEXTOFFSET; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 7) + return OPCODE_WUR_AE_NEXTOFFSET; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 8) + return OPCODE_RUR_AE_SEARCHDONE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 9) + return OPCODE_WUR_AE_SEARCHDONE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 10) + return OPCODE_RUR_AE_CWRAP; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 11) + return OPCODE_WUR_AE_CWRAP; + } + if (Field_op0_Slot_inst_get (insn) == 5) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALL0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALL4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALL8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALL12; + } + if (Field_op0_Slot_inst_get (insn) == 6) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_J; + if (Field_n_Slot_inst_get (insn) == 1) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQZ; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEZ; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTZ; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEZ; + } + if (Field_n_Slot_inst_get (insn) == 2) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQI; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEI; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEI; + } + if (Field_n_Slot_inst_get (insn) == 3) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_ENTRY; + if (Field_m_Slot_inst_get (insn) == 1) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BF; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BT; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LOOP; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_LOOPNEZ; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_LOOPGTZ; + } + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTUI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEUI; + } + } + if (Field_op0_Slot_inst_get (insn) == 7) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BNONE; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BEQ; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_BLT; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_BLTU; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BALL; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_BBC; + if ((Field_r_Slot_inst_get (insn) == 6 || + Field_r_Slot_inst_get (insn) == 7)) + return OPCODE_BBCI; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_BANY; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_BNE; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_BGE; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_BGEU; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_BNALL; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_BBS; + if ((Field_r_Slot_inst_get (insn) == 14 || + Field_r_Slot_inst_get (insn) == 15)) + return OPCODE_BBSI; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16b_get (insn) == 12) + { + if (Field_i_Slot_inst16b_get (insn) == 0) + return OPCODE_MOVI_N; + if (Field_i_Slot_inst16b_get (insn) == 1) + { + if (Field_z_Slot_inst16b_get (insn) == 0) + return OPCODE_BEQZ_N; + if (Field_z_Slot_inst16b_get (insn) == 1) + return OPCODE_BNEZ_N; + } + } + if (Field_op0_Slot_inst16b_get (insn) == 13) + { + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 1) + return OPCODE_AE_L16SI_N; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 2) + return OPCODE_AE_L16UI_N; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 3) + return OPCODE_AE_S16I_N; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 4 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 0) + return OPCODE_AE_SEXT16; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 4 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 1) + return OPCODE_AE_ZEXT16; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 5 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 1) + return OPCODE_AE_ZEXT8; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 5 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 0) + return OPCODE_AE_CLAMPS16; + if (Field_r_Slot_inst16b_get (insn) == 0) + return OPCODE_MOV_N; + if (Field_r_Slot_inst16b_get (insn) == 15) + { + if (Field_t_Slot_inst16b_get (insn) == 0) + return OPCODE_RET_N; + if (Field_t_Slot_inst16b_get (insn) == 1) + return OPCODE_RETW_N; + if (Field_t_Slot_inst16b_get (insn) == 2) + return OPCODE_BREAK_N; + if (Field_t_Slot_inst16b_get (insn) == 3 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_NOP_N; + if (Field_t_Slot_inst16b_get (insn) == 6 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_ILL_N; + } + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16a_get (insn) == 8) + return OPCODE_L32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 9) + return OPCODE_S32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 10) + return OPCODE_ADD_N; + if (Field_op0_Slot_inst16a_get (insn) == 11) + return OPCODE_ADDI_N; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae10_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae10_slot0_24_0_Slot_ae10_slot0_get (insn) == 12720387) + return OPCODE_NOP; + if (Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (insn) == 12872 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_ALL4; + if (Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (insn) == 12872 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_ANY4; + if (Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (insn) == 12873 && + Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_get (insn) == 18) + return OPCODE_SSAI; + if (Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (insn) == 12873 && + Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_ALL8; + if (Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (insn) == 12873 && + Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_ANY8; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3082) + return OPCODE_MAXU; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3083) + return OPCODE_MIN; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3084) + return OPCODE_SALT; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3085) + return OPCODE_SALTU; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3086) + return OPCODE_MOVF; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3087) + return OPCODE_MOVT; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3088) + return OPCODE_ORBC; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3089) + return OPCODE_XORB; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3090 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_ABS; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3090 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_NEG; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3104 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3144) + return OPCODE_ADD; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3145) + return OPCODE_ADDX2; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3146) + return OPCODE_MINU; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3147) + return OPCODE_MOVEQZ; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3148) + return OPCODE_SRC; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3149) + return OPCODE_SUB; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3150) + return OPCODE_CLAMPS; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3151) + return OPCODE_SEXT; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3154 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3154 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3208) + return OPCODE_ADDX4; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3209) + return OPCODE_ADDX8; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3210) + return OPCODE_MOVGEZ; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3211) + return OPCODE_MOVLTZ; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3212) + return OPCODE_SUBX2; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3213) + return OPCODE_SUBX4; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3214) + return OPCODE_SRLI; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3215) + return OPCODE_ANDB; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3272) + return OPCODE_AND; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3273) + return OPCODE_MAX; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3274) + return OPCODE_MOVNEZ; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3275) + return OPCODE_OR; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3276) + return OPCODE_SUBX8; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3277) + return OPCODE_XOR; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3278) + return OPCODE_ANDBC; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3279) + return OPCODE_ORB; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1296) + return OPCODE_AE_L16M_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1297) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1298) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1299) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1300) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1301) + return OPCODE_AE_L16_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1302) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1303) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1304) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1305) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1306) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1307) + return OPCODE_AE_L32_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1308) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1309) + return OPCODE_AE_L64_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1310) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1311) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1328) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1329) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1330) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1331) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1332) + return OPCODE_AE_L16_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1333) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1334) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1335) + return OPCODE_AE_L32M_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1336) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1337) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1338) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1339) + return OPCODE_AE_L32_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1340) + return OPCODE_AE_L32_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1341) + return OPCODE_AE_L64_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1342) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1343) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1360) + return OPCODE_AE_L16M_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1361) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1362) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1363) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1364) + return OPCODE_AE_L16_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1365) + return OPCODE_AE_L16_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1366) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1367) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1368) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1369) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1370) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1371) + return OPCODE_AE_L32_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1372) + return OPCODE_AE_L64_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1373) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1374) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1375) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1392) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1393) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1394) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1395) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1396) + return OPCODE_AE_L16_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1397) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1398) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1399) + return OPCODE_AE_L32M_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1400) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1401) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1402) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1403) + return OPCODE_AE_L32_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1404) + return OPCODE_AE_L64_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1405) + return OPCODE_AE_L64_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1406) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1407) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1536) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1537) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1538) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1539) + return OPCODE_AE_L8_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1540) + return OPCODE_SRAI; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1568) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1569) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1570) + return OPCODE_AE_L8_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1571) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1576 && + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1576 && + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1600) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1601) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1602) + return OPCODE_AE_L8_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1603) + return OPCODE_AE_L8_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1608 && + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1608 && + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1632) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1633) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1634) + return OPCODE_AE_L8_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1635) + return OPCODE_SLLI; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_6_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 12) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 13) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 14) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 15) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 158) + return OPCODE_ADDI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 159) + return OPCODE_ADDMI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 160) + return OPCODE_L16SI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 161) + return OPCODE_S16I; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 164) + return OPCODE_L16UI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 165) + return OPCODE_S32I; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 168) + return OPCODE_L32I; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 169) + return OPCODE_S8I; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 172) + return OPCODE_L8UI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 173) + return OPCODE_MOVI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 194 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 194 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 194 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae10_slot0_24_17_Slot_ae10_slot0_get (insn) == 78) + return OPCODE_EXTUI; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 12) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 13) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 14) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 15) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 16) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 17) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 18) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 19) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 20) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 21) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 22) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 23) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 24) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 25) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 26) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 27) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 28) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 29) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 30) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 31) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 32) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 33) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 34) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 35) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 36) + return OPCODE_J; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 37) + return OPCODE_CALL0; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_LAV16X4X2_XP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_AE_LAV8X8X2_XP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_L32R; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 6) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 7) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5155) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5156) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5157) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5152) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5153) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5154) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5158) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5159) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5160) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_8_Slot_ae10_slot0_get (insn) == 320) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_get (insn) == 9 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_get (insn) == 9 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49680 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_CALLX0; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49682 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_JX; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49683 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_RET; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49685 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SSA8B; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49686 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SSA8L; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49687 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SSL; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49688 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SSR; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae10_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae10_slot1_25_1_Slot_ae10_slot1_get (insn) == 10793092 && + Field_fld_ae10_slot1_0_0_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5134) + return OPCODE_MAXU; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5135) + return OPCODE_MIN; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5136) + return OPCODE_SALT; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5137) + return OPCODE_SALTU; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5138) + return OPCODE_CLAMPS; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5139) + return OPCODE_SEXT; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5140 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 10) + return OPCODE_SLL; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5196) + return OPCODE_ADD; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5197) + return OPCODE_ADDX2; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5198) + return OPCODE_MINU; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5199) + return OPCODE_MOVEQZ; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5200) + return OPCODE_SRC; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5201) + return OPCODE_SUB; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5202) + return OPCODE_SRLI; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5203 && + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5203 && + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5203 && + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5203 && + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5260) + return OPCODE_ADDX4; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5261) + return OPCODE_ADDX8; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5262) + return OPCODE_MOVGEZ; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5263) + return OPCODE_MOVLTZ; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5264) + return OPCODE_SUBX2; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5265) + return OPCODE_SUBX4; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5324) + return OPCODE_AND; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5325) + return OPCODE_MAX; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5326) + return OPCODE_MOVNEZ; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5327) + return OPCODE_OR; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5328) + return OPCODE_SUBX8; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5329) + return OPCODE_XOR; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2328) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2329) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2330) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2331) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2332) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2333) + return OPCODE_AE_L32_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2334) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2335) + return OPCODE_AE_L64_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2352) + return OPCODE_AE_L16M_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2353) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2354) + return OPCODE_AE_L16M_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2355) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2356) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2357) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2358) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2359) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2360) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2361) + return OPCODE_AE_L32M_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2362) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2363) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2364) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2365) + return OPCODE_AE_L32_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2366) + return OPCODE_AE_L32_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2367) + return OPCODE_AE_L64_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2384) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2385) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2386) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2387) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2388) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2389) + return OPCODE_AE_L16_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2390) + return OPCODE_AE_L16_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2391) + return OPCODE_AE_L16_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2392) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2393) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2394) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2395) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2396) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2397) + return OPCODE_AE_L32_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2398) + return OPCODE_AE_L64_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2399) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2416) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2417) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2418) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2419) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2420) + return OPCODE_AE_L16_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2421) + return OPCODE_AE_L16_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2422) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2423) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2424) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2425) + return OPCODE_AE_L32M_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2426) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2427) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2428) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2429) + return OPCODE_AE_L32_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2430) + return OPCODE_AE_L64_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2431) + return OPCODE_AE_L64_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2560) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2561) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2562) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2563) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2564) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2565) + return OPCODE_AE_L8_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2566) + return OPCODE_SRAI; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2570 && + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2592) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2593) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2594) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2595) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2596) + return OPCODE_AE_L8_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2597) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2602 && + Field_fld_ae10_slot1_3_2_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2602 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 4) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2602 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 5) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2602 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 6) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2602 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 7) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2624) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2625) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2626) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2627) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2628) + return OPCODE_AE_L8_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2629) + return OPCODE_AE_L8_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2633 && + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2633 && + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2656) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2657) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2658) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2659) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2660) + return OPCODE_AE_L8_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2661) + return OPCODE_SLLI; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2665 && + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2665 && + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 290) + return OPCODE_MOVI; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 292) + return OPCODE_ADDI; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 293) + return OPCODE_ADDMI; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 296) + return OPCODE_L16SI; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 297) + return OPCODE_L32I; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 300) + return OPCODE_L16UI; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 301) + return OPCODE_L8UI; + if (Field_fld_ae10_slot1_25_17_Slot_ae10_slot1_get (insn) == 144) + return OPCODE_EXTUI; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 48) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 49) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 50) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 51) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 52) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 53) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 54) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 55) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 56) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 57) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 58) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 59) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 60) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 61) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 62) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 63) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 64) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 65) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 66) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 67) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 68) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 69) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 70) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 71) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 6) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 7) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 6) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 7) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 352) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_get (insn) == 10 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 8) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_get (insn) == 10 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 9) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae10_slot1_25_22_Slot_ae10_slot1_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae10_slot1_25_23_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get (insn) == 82273 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 9) + return OPCODE_SSL; + if (Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get (insn) == 83266 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 10) + return OPCODE_SSA8B; + if (Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get (insn) == 83267 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 10) + return OPCODE_SSA8L; + if (Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get (insn) == 83297 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 9) + return OPCODE_SSR; + if (Field_fld_ae10_slot1_25_9_Slot_ae10_slot1_get (insn) == 41632 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 10) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae2_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L64_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L64_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L64_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32M_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S32_H_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S64_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S64_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S64_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_ADD; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_ADDX2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_ADDX4; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_ADDX8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AND; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SLLI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_SRAI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_MAX; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S8_0_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L8_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L8_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L8_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L8_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L8_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_SUB; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_SUBX2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_SUBX4; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_SUBX8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_OR; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_XOR; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_MOVEQZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_MOVGEZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_MOVLTZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_MOVNEZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_SRC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_SALT; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_SALTU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_MAXU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_MIN; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_MINU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_SRLI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_ANDB; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_ANDBC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_ORB; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_ORBC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_XORB; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_MOVF; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_MOVT; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_CLAMPS; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SEXT; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_CALLX0; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 10 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_JX; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_RET; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 22 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_SSA8B; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_SSA8L; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 30 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_SSL; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 12 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_MOVBD1X4; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_MOVBD1X2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_SA32X2_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_SA32X2F24_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_SA32X2F24_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SA24_L_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SA24_L_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_SA24X2_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SA24X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16X2M_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1878 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S8X4U_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1878 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S8X4U_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1878 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S8X4U_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1878 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S8X4U_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S32M_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6304 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 175) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6304 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 47) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6305 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 47) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6308 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 175 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_SSR; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA32X2POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA32X2NEG_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4NEG_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA32X2POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA8X8POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA8X8NEG_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA8X8NEG_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA8X8POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA8X8POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_0_Slot_ae2_slot0_get (insn) == 36789) + return OPCODE_NOP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_0_Slot_ae2_slot0_get (insn) == 4020) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_2_Slot_ae2_slot0_get (insn) == 1004) + return OPCODE_AE_MOVALIGN; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24NEG_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6325 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6325 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6326 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6326 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24X2NEG_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6327 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6327 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24X2POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 49) + return OPCODE_SSAI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_ALL4; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_ANY4; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 33) + return OPCODE_ALL8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 33) + return OPCODE_ANY8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_4_Slot_ae2_slot0_get (insn) == 1585) + return OPCODE_AE_MOVASAR; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6407 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6411 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6415 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6419 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6420 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6423 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6426 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6426 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVTA32F24S_L; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6426 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVTA32F24S_H; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6426 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6427 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6427 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6427 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6427 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6427 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6430 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6430 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_NSA64; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6430 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_NSAZ16_0; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6430 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_ABS; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_NEG; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 12 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_TRUNCA32Q48; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6456 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6456 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6457 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6457 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6458 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6458 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6459 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6459 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6460 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6460 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6461 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6461 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6462 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6462 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6463 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6463 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16M_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L16M_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7534) + return OPCODE_ADDI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7535) + return OPCODE_ADDMI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7544) + return OPCODE_L16SI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7545) + return OPCODE_L32I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7546) + return OPCODE_S16I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7547) + return OPCODE_S8I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7548) + return OPCODE_L16UI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7549) + return OPCODE_L8UI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7550) + return OPCODE_S32I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7551) + return OPCODE_MOVI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7554 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7554 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7554 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_MOVI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_MOVAD8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7558 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7558 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7558 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_LA24_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_LA24_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_LA24X2_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_LA24X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L16_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L16_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L16_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L16_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L16_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L32M_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32M_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L32_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L32_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L32_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_get (insn) == 3224 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_TRUNC16_H; + if (Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_get (insn) == 3225 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_UTRUNC16_H; + if (Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_get (insn) == 3765) + return OPCODE_EXTUI; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 457) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 459) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 461) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 463) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1564 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_EQ8; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1565 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_LE8; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1566 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1566 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 31) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1566 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_LT8; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1567 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1567 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 31) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1567 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1567 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 27) + return OPCODE_AE_S24RA64S_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1568 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1569 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1570 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1571 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1572 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1573 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1600 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1600 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1600 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1600 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1601 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_AE_MOV; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1601 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1601 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1601 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1602 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1602 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1602 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_CVTF16S_L; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1602 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_CVTF16S_H; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1603 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_CVTSF16_L; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1603 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_CVTSF16_H; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1603 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_FICEIL_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1603 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_FIFLOOR_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1604 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1604 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_FIRINT_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1604 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_FIROUND_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1604 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_FITRUNC_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1605 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1608 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_OLE_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1608 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_OEQ_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1609 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_OLT_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1609 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_UEQ_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1610 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_ULE_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1610 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_ULT_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1611 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1611 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1611 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_UN_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1613 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_PKSR32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1613 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_PKSR24; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1613 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1613 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_PKSR16; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1806) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1807) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1810) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1811) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1812) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1813) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1814) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1815) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1816) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1817) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_S16X4RA32S_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_MOVT64; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MOVF64; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_MOVT_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_MOVF_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1864) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1865) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1866) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1867) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1868) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1869) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1870) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1871) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1874) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1875) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1876) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1877) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1878) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1879) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_LT16; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_LE16; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_EQ16; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LT32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_LE32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_EQ32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_LT64; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_LE64; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_EQ64; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_MOVEQZ_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_MOVNEZ_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_MOVGEZ_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_MOVLTZ_S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 232 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRAA32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 232 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRAA32RS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 232 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SLAA64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 233 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRAA32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 233 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SLAA64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 233 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRAA32SYMS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 234 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRAA64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 234 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SLAA8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 234 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRAA8RS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 235 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRAAQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 235 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SLAA8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 235 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRAA8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 768 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADD64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 768 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADD8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 769 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 769 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADD8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 770 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 770 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 771 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADDSUB32_HL_LH; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 771 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADDSUB32S_HL_LH; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 772 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_MAX32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 772 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MAX16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 773 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MAX64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 773 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_MAX8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 774 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_MIN32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 774 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MIN16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 775 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MIN64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 775 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_MIN8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 776 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUB16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 776 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MOVNEG32S_T; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 777 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUB24S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 777 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUB16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 778 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUB32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 778 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUB32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 779 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUB64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 779 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUB64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 780 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUB8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 780 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUB8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 781 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 781 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 782 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 787 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_FLOAT16_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 787 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_UFLOAT16_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 788 && + Field_fld_ae2_slot0_14_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 241) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 242) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 246) + return OPCODE_AE_ABS32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 245) + return OPCODE_AE_ABS24S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 247) + return OPCODE_AE_ABS32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 244) + return OPCODE_AE_ABS16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 243) + return OPCODE_AE_ABS16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 248) + return OPCODE_AE_ABS64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 252) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_ABS64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 255) + return OPCODE_AE_MUL16JS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 240) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_ABS8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_ABS8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 253) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 254) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 240) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 243) + return OPCODE_AE_NEG32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 242) + return OPCODE_AE_NEG24S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 244) + return OPCODE_AE_NEG32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 241) + return OPCODE_AE_NEG16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 245) + return OPCODE_AE_NEG64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 248) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 246) + return OPCODE_AE_NEG64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 247) + return OPCODE_AE_NEG8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 800 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 800 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 800 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 800 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 801 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 801 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L64_IP; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 801 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 801 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 802 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 802 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 802 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 802 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S64_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S64_IP; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_NSA16X4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FICEIL_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FIFLOOR_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FIRINT_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FIROUND_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 10 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FITRUNC_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 15 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_RMINNUM_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_RMAXNUM_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 804 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 28 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS24; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 804 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 30 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 804 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 29 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 804 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 31 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 805 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 30 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLASQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 805 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 28 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 805 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 31 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLASSQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 805 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 29 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 806 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 28 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAS24; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 806 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 29 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAS32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 806 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 31 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRASQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 806 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 30 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAS64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 807 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 28 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRLS24; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 807 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 29 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRLS32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 807 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 31 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRLSQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 807 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 30 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRLS64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 898) + return OPCODE_AE_TRUNCA16X4F32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 899) + return OPCODE_AE_TRUNCA16X4F64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 900) + return OPCODE_AE_TRUNCI32F64S_L; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 901) + return OPCODE_AE_TRUNCI32X2F64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 902) + return OPCODE_AE_SEL16I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 909 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_ADDC32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 909 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_ADDC32U; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 910 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_BMAX32X2; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 910 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_BMIN32X2; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 911 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SUBC32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 911 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SUBC32U; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 16) + return OPCODE_AE_SRAI16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 17) + return OPCODE_AE_SRAI16R; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 20) + return OPCODE_AE_SRLA32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SLAI16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SLAA16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_SLAAQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 23) + return OPCODE_AE_SRLAQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 21) + return OPCODE_AE_SRLA64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SLAASQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 22) + return OPCODE_AE_SRLA8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 24) + return OPCODE_AE_SRLI16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_SLAI16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_SLAA16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 19) + return OPCODE_AE_SRLA16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 18) + return OPCODE_AE_SRAI16SYM; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_AND; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_NAND; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_OR; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_XOR; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SRAV16RS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAV32RS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_NSAZ32X4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_NSA32X4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 930) + return OPCODE_AE_TRUNCA32F64S_L; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 931) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 940 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_CALL0; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 940 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_J; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_ADD32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_ADD16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_ADD24S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_ADD32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_ADD16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADD64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_BMAX16X4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_BMIN16X4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_SRA64_32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_SLAA32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_SRAA16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SRAA16RS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SLAA32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 18 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAI8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 19 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAI8R; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 20 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRLI8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAI8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 17 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAI8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SRAA16SYMS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_FLOAT16_HX4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_UFLOAT16_HX4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_TRUNC16_HX4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_UTRUNC16_HX4; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 56) + return OPCODE_AE_TRUNCI16X4F64S; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 57 && + Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_L32R; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 58 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SLAI64; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 58 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_SRLI64; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 58 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SRAI64; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 58 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SLAISQ56S; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 58 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAI64S; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 49 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_FLOAT_S; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 49 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_UFLOAT_S; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_TRUNC_S; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_UTRUNC_S; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 36) + return OPCODE_TRUNC_SX2; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 44) + return OPCODE_UTRUNC_SX2; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 32) + return OPCODE_FLOAT_SX2; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 40) + return OPCODE_UFLOAT_SX2; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_MOVT8X16_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_MOVT8X16_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_18_17_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_ADDW8; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_ADDW16; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_ADDW32; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SUBW8; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SUBW16; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SUBW32; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_ADDW8U; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SUBW8U; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 9 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 4 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 12 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 8 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 10 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 26) + return OPCODE_AE_CVTA32X4F8_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 27) + return OPCODE_AE_CVTA32X4F8_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 20) + return OPCODE_AE_CVTA32X4F8S_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 21) + return OPCODE_AE_CVTA32X4F8S_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 24) + return OPCODE_AE_CVTA32X4F8U_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 25) + return OPCODE_AE_CVTA32X4F8U_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 22) + return OPCODE_AE_CVTA32X4F8US_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 23) + return OPCODE_AE_CVTA32X4F8US_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 16) + return OPCODE_AE_CVTA32X4F16; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 17) + return OPCODE_AE_CVTA32X4F16S; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 18) + return OPCODE_AE_CVTA32X4F16U; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 19) + return OPCODE_AE_CVTA32X4F16US; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 28) + return OPCODE_AE_CVTI16X4X2F8; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 29) + return OPCODE_AE_CVTI16X4X2F8S; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 30) + return OPCODE_AE_CVTI16X4X2F8U; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 31) + return OPCODE_AE_CVTI16X4X2F8US; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_LAV8X8X2_XP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LAV16X4X2_XP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 27 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_CVTA16X4X2F8; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 27 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_CVTA16X4X2F8S; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 27 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_CVTA16X4X2F8U; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 27 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_CVTA16X4X2F8US; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_CVTI32X4F8_H; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_CVTI32X4F8_L; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_CVTI32X4F8S_H; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_CVTI32X4F8S_L; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_CVTI32X4F8U_H; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_CVTI32X4F8U_L; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_CVTI32X4F8US_H; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_CVTI32X4F8US_L; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_CVTI32X4F16; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_CVTI32X4F16S; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_CVTI32X4F16U; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVTI32X4F16US; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SLAI24; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_SRLI24; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_SRAI24; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SLAI32; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SRLI32; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SRAI32; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRAI32R; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAI24S; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SLAI32S; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRAI32SYM; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVDEXT; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_get (insn) == 16) + return OPCODE_AE_MOVADEXT_H; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_get (insn) == 17) + return OPCODE_AE_MOVADEXT_L; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCI16X4F32S; + if (Field_fld_ae2_slot0_40_26_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVT16X8; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_BBSI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_BALL_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_BANY_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_BBC_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_BBS_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_BEQ_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_BGEU_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_BGE_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_BLTU_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_BLT_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_BNALL_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_BNE_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_BNONE_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_BEQZ_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_BGEZ_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_BLTZ_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_BNEZ_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_BEQI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_BGEI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_BLTI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_BNEI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_BGEUI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_BLTUI_W15; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae2_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7692 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_SLL; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7692 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_TRUNCA32Q48; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7692 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_NSA64; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7692 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_NSAZ16_0; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7692 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7693 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7694 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7694 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7694 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7694 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7695 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7695 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7695 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7695 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7698) + return OPCODE_ADD; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7700 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7700 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7700 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7700 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7706) + return OPCODE_ADDX2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_0_Slot_ae2_slot1_get (insn) == 1794) + return OPCODE_NOP; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_SSL; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 5 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_SSR; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 6 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_MOVASAR; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7746) + return OPCODE_ADDX4; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7747 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_CVTA32F24S_H; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7754) + return OPCODE_ADDX8; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7755 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_CVTA32F24S_L; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7762) + return OPCODE_AND; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7763 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7770) + return OPCODE_MAX; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7771 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7778) + return OPCODE_MAXU; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7779 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7786) + return OPCODE_MIN; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7787 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7794) + return OPCODE_MINU; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7795 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7802) + return OPCODE_MOVEQZ; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7803 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7810) + return OPCODE_MOVGEZ; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7818) + return OPCODE_MOVLTZ; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7826) + return OPCODE_MOVNEZ; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7834) + return OPCODE_OR; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7842) + return OPCODE_SALT; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7850) + return OPCODE_SALTU; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7858) + return OPCODE_SRC; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7866) + return OPCODE_SUB; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7874) + return OPCODE_SUBX2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7882) + return OPCODE_SUBX4; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7890) + return OPCODE_SUBX8; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7898) + return OPCODE_XOR; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7906) + return OPCODE_CLAMPS; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7914) + return OPCODE_SEXT; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7922) + return OPCODE_SRLI; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7930) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7936 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_SSA8B; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7944 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_SSA8L; + if (Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_get (insn) == 1921 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_get (insn) == 1923 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 928 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_ABS_S; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 929 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_CONJC_H; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 930 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_CONJC_S; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 931 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_MULJC_H; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 932 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_MULJC_S; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 933 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_NEG_S; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 934 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 11) + return OPCODE_CONST_S; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 934 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 10) + return OPCODE_CONST_H; + if (Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_get (insn) == 480 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_SRAI; + if (Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_get (insn) == 496 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_SSAI; + if (Field_fld_ae2_slot1_36_17_Slot_ae2_slot1_get (insn) == 241 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_SLLI; + if (Field_fld_ae2_slot1_36_18_Slot_ae2_slot1_get (insn) == 120 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 13 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD8; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 12) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 13) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 14) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 15) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 16) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 17) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 18) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 19) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 20) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 21 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 21 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 21 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 21 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 22 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 22 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 22 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 22 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 23 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 23 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 23 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 23 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 24 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 24 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 24 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 24 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 25 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 25 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 25 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 25 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 26 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 26 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 26 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 26 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 27 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 27 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 27 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 27 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_ADDI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_ADDMI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_L16UI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_L16SI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_L32I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_L8UI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_MOVI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 83) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 84) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 80) + return OPCODE_AE_L16M_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 81) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 82) + return OPCODE_AE_L16M_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 85) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 100) + return OPCODE_AE_L16_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 101) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 97) + return OPCODE_AE_L16_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 98) + return OPCODE_AE_L16_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 99) + return OPCODE_AE_L16_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 102) + return OPCODE_AE_L16_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 106) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 107) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 103) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 104) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 105) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 108) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 126) + return OPCODE_AE_L32_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 127) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 123) + return OPCODE_AE_L32_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 124) + return OPCODE_AE_L32_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 125) + return OPCODE_AE_L32_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 112) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 109) + return OPCODE_AE_L32M_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 110) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 111) + return OPCODE_AE_L32M_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 113) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 89) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 90) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 86) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 87) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 88) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 91) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 115) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 116) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 114) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 117) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 119) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 120) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 118) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 122) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 93) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 94) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 92) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 96) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 121) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 95) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 8 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_MOVEQZ_S; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 9 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_MOVNEZ_S; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 8 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_MOVGEZ_S; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 9 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_MOVLTZ_S; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 11) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L64_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 11) + return OPCODE_AE_L64_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 13) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 7) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 15) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 8) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 14) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 12) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 7) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 8) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 9) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 10) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 11) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 12) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 13) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 14) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 15) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 16) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 17) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 26) + return OPCODE_AE_L8_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 27) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 23) + return OPCODE_AE_L8_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 24) + return OPCODE_AE_L8_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 25) + return OPCODE_AE_L8_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 28) + return OPCODE_AE_L8_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 49 && + Field_fld_ae2_slot1_3_3_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 19) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 20) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 48 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 18) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 22) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L64_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L64_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_AE_L64_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 21) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 49 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 14) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 29) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_MOV; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 49 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 12) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 49 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 8) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 49 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 10) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 14 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 14 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_NSA16X4; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_ABS_H; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_NEG_H; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 8 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_2_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 8 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae2_slot1_36_22_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae2_slot1_36_23_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae3_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (insn) == 133982 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_ALL4; + if (Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (insn) == 133982 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_ANY4; + if (Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (insn) == 133983 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 2 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_SSAI; + if (Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (insn) == 133983 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_ALL8; + if (Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (insn) == 133983 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_ANY8; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66890) + return OPCODE_AE_LBK; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66891) + return OPCODE_AND; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66894) + return OPCODE_MAX; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66895) + return OPCODE_MAXU; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66898) + return OPCODE_AE_SBI_IC; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66899) + return OPCODE_AE_SBI_IC1; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66902) + return OPCODE_AE_SBI_IP; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66903) + return OPCODE_AE_VLDL16T; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66906) + return OPCODE_AE_VLDL32T; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66907) + return OPCODE_AE_VLEL16T; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66910) + return OPCODE_AE_VLEL32T; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66911) + return OPCODE_MOVF; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66914) + return OPCODE_MOVT; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66915) + return OPCODE_AE_LBKI; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66918) + return OPCODE_CLAMPS; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66919) + return OPCODE_SEXT; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66922) + return OPCODE_SRLI; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66923) + return OPCODE_ANDB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66926) + return OPCODE_ANDBC; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66927) + return OPCODE_ORB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66930) + return OPCODE_ORBC; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66931) + return OPCODE_XORB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66950 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_SLL; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66951 && + Field_fld_ae3_slot0_9_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_MOVEA; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66990 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVBA1X2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_SRA; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_SRL; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_MOVAB4; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_MOVAB2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_MOVAB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_MOVBA; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_MOVBA4; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_AE_MOVBA2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get (insn) == 22) + return OPCODE_AE_MOVB2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get (insn) == 39) + return OPCODE_AE_MOVB4; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_AE_LBI; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_LBSI; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 2 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_MOVAE; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67354 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_ABS; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67354 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_AE_LB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67355 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_NEG; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67355 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_LBS; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67364) + return OPCODE_ADD; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67365) + return OPCODE_ADDX2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67366) + return OPCODE_ADDX4; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67367) + return OPCODE_ADDX8; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67368) + return OPCODE_SALTU; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67369) + return OPCODE_SRC; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67370) + return OPCODE_SUB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67371) + return OPCODE_SUBX2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67372) + return OPCODE_SUBX4; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67373) + return OPCODE_SUBX8; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67374) + return OPCODE_XOR; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67375) + return OPCODE_AE_SBI; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67409) + return OPCODE_MIN; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67411) + return OPCODE_MINU; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67413) + return OPCODE_MOVEQZ; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67415) + return OPCODE_MOVGEZ; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67417) + return OPCODE_MOVLTZ; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67419) + return OPCODE_MOVNEZ; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67421) + return OPCODE_OR; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67423) + return OPCODE_SALT; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33329) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33331) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33333) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33335) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33337) + return OPCODE_AE_L16_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33339) + return OPCODE_AE_L16_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33341) + return OPCODE_AE_L16_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33343) + return OPCODE_AE_L16_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33398) + return OPCODE_AE_L16M_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33399) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33400) + return OPCODE_AE_L16M_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33401) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33402) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33403) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33404) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33405) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33406) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33407) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33409) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33411) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33413) + return OPCODE_AE_S64_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33415) + return OPCODE_AE_S64_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33417) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33419) + return OPCODE_AE_S64_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33421) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33423) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33425) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33427) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33429) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33431) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33433) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33435) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33437) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33439) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33441) + return OPCODE_SLLI; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33443) + return OPCODE_SRAI; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33467 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33467 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33469 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33469 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33471 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33471 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33473 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33477 && + Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_get (insn) == 192) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33489 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33489 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33489 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33489 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33491 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33491 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33491 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33491 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA8X8_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33493 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33493 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33493 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33493 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_MOVI; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33497) + return OPCODE_AE_S8X4U_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33499 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S8X4U_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33536 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33537 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33538 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33539 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33540 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33541 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33542 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33543 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33544 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33545 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33546 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33547 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33548 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33549 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33550 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33551 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33552 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33553 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33554 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33555 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33556 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33557 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33558 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33559 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33560 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33561 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33562 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33563 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33564 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33565 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33566 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33567 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33568) + return OPCODE_AE_L16_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33569) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33570) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33571) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33572) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33573) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33574) + return OPCODE_AE_L32M_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33575) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33576) + return OPCODE_AE_L32M_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33577) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33578) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33579) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33580) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33581) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33582) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33583) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33584) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33585) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33586) + return OPCODE_AE_L32_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33587) + return OPCODE_AE_L32_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33588) + return OPCODE_AE_L32_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33589) + return OPCODE_AE_L32_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33590) + return OPCODE_AE_L32_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33591) + return OPCODE_AE_L64_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33592) + return OPCODE_AE_L64_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33593) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33594) + return OPCODE_AE_L64_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33595) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33596) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33597) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33598) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33599) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33600) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33601) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33602) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33603) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33604) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33605) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33606) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33607) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33608) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33609) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33610) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33611) + return OPCODE_AE_L8_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33612) + return OPCODE_AE_L8_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33613) + return OPCODE_AE_L8_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33614) + return OPCODE_AE_L8_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33615) + return OPCODE_AE_L8_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33616) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33617) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33618) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33619) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33620) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33621) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33622) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33623) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33624) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33625) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33626) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33627) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33628) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33629) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33630) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33631) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33632) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33633) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33634) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33635) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33636) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33637) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33638) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33639) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33640) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33641) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33642) + return OPCODE_AE_S32M_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33643) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33644) + return OPCODE_AE_S32M_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33645) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33646) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33647) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33648) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33649) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33650) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33651) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33652) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33653) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33654) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33655) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33656) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33657) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33658) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33659) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33660) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33661) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33662) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33663) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_AE_TRUNCA16P24S_L; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_NSAZ16_0; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33688 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33688 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33689 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33689 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33690 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33690 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_MOVAD8; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33691 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33691 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33691 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33691 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33694 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33694 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33694 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33694 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33695 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33695 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33695 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33695 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33728 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33729 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33730) + return OPCODE_AE_S8X4U_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33731) + return OPCODE_AE_S8X4U_X; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16698) + return OPCODE_AE_MOVT64; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16840 && + Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16840 && + Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_ABS32; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_AE_NEG24S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_ABS24S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 13) + return OPCODE_AE_ABS32S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_AE_NEG16S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_ABS16S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_ABS64; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_MOV; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_NEG32; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_AE_NEG32S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_AE_NEG64; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8338) + return OPCODE_AE_ADD16S; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8339) + return OPCODE_AE_ADD32S; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8340) + return OPCODE_AE_MAX32; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8341) + return OPCODE_AE_MIN32; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8342) + return OPCODE_AE_ROUND16X4F32SASYM; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8343) + return OPCODE_AE_ROUND24X2F48SSYM; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8344) + return OPCODE_AE_SUB16S; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8345) + return OPCODE_AE_SUB32S; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8346) + return OPCODE_AE_AND; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8347) + return OPCODE_AE_OR; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8348) + return OPCODE_AE_XOR; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8416 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8416 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8416 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8416 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8417 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8417 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L64_IP; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8417 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8417 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8418 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8418 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8418 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8418 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_S64_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8419 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8419 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S64_IP; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8424 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LT16; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8424 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LE32; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8424 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_EQ32; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8425 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8425 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8425 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LE16; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8425 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_EQ16; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8425 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LT32; + if (Field_fld_ae3_slot0_32_16_Slot_ae3_slot0_get (insn) == 4168) + return OPCODE_MOVI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2078) + return OPCODE_EXTUI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2079 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_ADDI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2079 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_ADDMI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2080 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_L16UI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2080 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_L16SI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2081 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_L32I; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2081 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_L8UI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2082 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_S16I; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2082 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_S32I; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2083 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_S8I; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2092 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2092 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_LOOPGTZ; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2092 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_LOOPNEZ; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1036) + return OPCODE_J; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1037) + return OPCODE_CALL0; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1048 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1048 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1048 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S16X4RA32S_IP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 256) + return OPCODE_L32R; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 257) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 258 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 258 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCI32X2F64S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 13 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SRAS24; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_SRLA32; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_SLAA16S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_SRAA16S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_SRAA16RS; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 13 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_AE_SLAA32S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_SRAA32S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_SLAAQ56; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SRAAQ56; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_AE_SLAA64; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SLAASQ56S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_SRLA16; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_BBSI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_BALL_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_BANY_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_BBC_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_BBS_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_BEQ_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_BGEU_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_BGE_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 13) + return OPCODE_BLTU_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_BLT_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_BNALL_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_BNE_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_BNONE_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_BEQZ_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_BGEZ_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get (insn) == 74) + return OPCODE_BLTZ_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get (insn) == 78) + return OPCODE_BNEZ_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_BEQI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_BGEI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_BLTI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_BNEI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_BGEUI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_BLTUI_W15; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071217 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_SBF; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071218 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLDL16C; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071219 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLES16C_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071221 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_SBF_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071222 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLDL16C_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071223 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLES16C_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071225 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_SBF_IC1; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071226 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLDL16C_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071227 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_CALLX0; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071229 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_SBF_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071230 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLES16C; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071841) + return OPCODE_AE_DB; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071843) + return OPCODE_AE_SB; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071845) + return OPCODE_AE_DB_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071847) + return OPCODE_AE_SB_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071849) + return OPCODE_AE_DB_IC1; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071851) + return OPCODE_AE_SB_IC1; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071853) + return OPCODE_AE_DB_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071855) + return OPCODE_AE_SB_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071856 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071858 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071860 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071862 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2POS_PC2; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071864 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071866 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071866 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_AE_VLDSHT; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071868 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071870 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_RUR_AE_BITPTR; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071870 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8NEG_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078411) + return OPCODE_AE_DBI; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078415) + return OPCODE_AE_DBI_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078443) + return OPCODE_AE_DBI_IC1; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078447) + return OPCODE_AE_DBI_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078475) + return OPCODE_AE_SHA32; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078479 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078479 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078479 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078479 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4POS_PC2; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078507 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8POS_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078507 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8POS_PC2; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078507 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078507 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_JX; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_get (insn) == 116) + return OPCODE_NOP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_RET; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_SSA8B; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_SSA8L; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_SSL; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_SSR; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_2_Slot_ae3_slot0_get (insn) == 28) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 2 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVALIGN; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae3_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae3_slot1_23_0_Slot_ae3_slot1_get (insn) == 1873411) + return OPCODE_NOP; + if (Field_fld_ae3_slot1_23_11_Slot_ae3_slot1_get (insn) == 914 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSAI; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 420) + return OPCODE_ADD; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 421) + return OPCODE_ADDX2; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 422) + return OPCODE_ADDX4; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 423) + return OPCODE_ADDX8; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 424) + return OPCODE_AE_LBK; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 425) + return OPCODE_AND; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 426) + return OPCODE_MAX; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 427) + return OPCODE_MAXU; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 428) + return OPCODE_MIN; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 429) + return OPCODE_MINU; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 430) + return OPCODE_MOVEQZ; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 431) + return OPCODE_MOVGEZ; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 432) + return OPCODE_MOVLTZ; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 433) + return OPCODE_MOVNEZ; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 434) + return OPCODE_OR; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 435) + return OPCODE_SALT; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 436) + return OPCODE_SALTU; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 437) + return OPCODE_SRC; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 438) + return OPCODE_SUB; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 439) + return OPCODE_SUBX2; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 440) + return OPCODE_SUBX4; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 441) + return OPCODE_SUBX8; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 442) + return OPCODE_XOR; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 443) + return OPCODE_CLAMPS; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 444) + return OPCODE_SEXT; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 445) + return OPCODE_SRLI; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 446) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 456 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 456 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 456 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 456 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 4) + return OPCODE_SRL; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 456 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_LB; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 457 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 457 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 457 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_LBI; + if (Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_get (insn) == 208) + return OPCODE_SLLI; + if (Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_get (insn) == 209) + return OPCODE_SRAI; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 34 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 34 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16M_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 34 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 34 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L16M_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 35 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 35 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 35 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 35 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 36 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 36 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 36 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 36 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 37 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L16_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 37 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L16_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 37 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 37 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 38 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L16_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 38 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 38 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L16_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 38 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 39 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 39 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 39 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 39 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 40 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 40 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32M_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 40 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 40 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L32M_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 41 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 41 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 41 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 41 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 42 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 42 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 42 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 42 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 43 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 43 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L32_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 43 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 43 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 44 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 44 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 44 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L64_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 44 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L64_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 45 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 45 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L64_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 45 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L64_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 45 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L64_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 46 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 46 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 46 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 46 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 47 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 47 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 47 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 47 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 48 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 48 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 48 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 48 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 49 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 49 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 49 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 49 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 50 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L8_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 50 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 50 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L8_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 50 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3 && + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3 && + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_MOVDA32X2; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 14) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 15) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0 && + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_MOVI; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_1_Slot_ae3_slot1_get (insn) == 6) + return OPCODE_AE_MOV; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 10) + return OPCODE_ADDI; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 11) + return OPCODE_ADDMI; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 12) + return OPCODE_L16SI; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 13) + return OPCODE_L16UI; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 14) + return OPCODE_L32I; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 15) + return OPCODE_L8UI; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 16) + return OPCODE_MOVI; + if (Field_fld_ae3_slot1_23_17_Slot_ae3_slot1_get (insn) == 4) + return OPCODE_EXTUI; + if (Field_fld_ae3_slot1_23_19_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_SEL16I; + if (Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_get (insn) == 28624) + return OPCODE_AE_MOVAE; + if (Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_get (insn) == 28625) + return OPCODE_AE_MOVEA; + if (Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (insn) == 7157 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (insn) == 7313 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSA8B; + if (Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (insn) == 7314 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSL; + if (Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (insn) == 7315 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSR; + if (Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (insn) == 7317 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSA8L; + if (Field_fld_ae3_slot1_23_9_Slot_ae3_slot1_get (insn) == 3576) + return OPCODE_AE_MOVAD32_L; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot0_22_0_Slot_ae4_slot0_get (insn) == 4088843) + return OPCODE_NOP; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 964) + return OPCODE_ADD; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 965) + return OPCODE_ADDX2; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 966) + return OPCODE_ADDX4; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 967) + return OPCODE_ADDX8; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 968) + return OPCODE_AND; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 969) + return OPCODE_MAX; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 970) + return OPCODE_MAXU; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 971) + return OPCODE_MIN; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 972) + return OPCODE_MINU; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 973) + return OPCODE_MOVEQZ; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 974) + return OPCODE_MOVGEZ; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 975) + return OPCODE_MOVLTZ; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 976) + return OPCODE_MOVNEZ; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 977) + return OPCODE_OR; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 978) + return OPCODE_SALT; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 979) + return OPCODE_SALTU; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 980) + return OPCODE_SRC; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 981) + return OPCODE_SUB; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 982) + return OPCODE_SUBX2; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 983) + return OPCODE_SUBX4; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 984) + return OPCODE_SUBX8; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 985) + return OPCODE_XOR; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 986) + return OPCODE_MOVF; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 987) + return OPCODE_MOVT; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 988) + return OPCODE_CLAMPS; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 989) + return OPCODE_SEXT; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 990) + return OPCODE_SRLI; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 991) + return OPCODE_ANDB; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 992) + return OPCODE_ANDBC; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 993) + return OPCODE_ORB; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 994) + return OPCODE_ORBC; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 995) + return OPCODE_XORB; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 996) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 997 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 997 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 997 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 1) + return OPCODE_SRA; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 997 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 1008 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_get (insn) == 480) + return OPCODE_SLLI; + if (Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_get (insn) == 481) + return OPCODE_SRAI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 50) + return OPCODE_ADDI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 51) + return OPCODE_ADDMI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 52) + return OPCODE_L16SI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 53) + return OPCODE_L16UI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 54) + return OPCODE_L32I; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 55) + return OPCODE_L8UI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 56) + return OPCODE_S16I; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 57) + return OPCODE_S32I; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 58) + return OPCODE_S8I; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 59) + return OPCODE_MOVI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 63 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 63 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 63 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae4_slot0_22_17_Slot_ae4_slot0_get (insn) == 24) + return OPCODE_EXTUI; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 4) + return OPCODE_AE_S32X2X2RNG_IP; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 5) + return OPCODE_AE_S32X2X2RNG_XP; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 6) + return OPCODE_AE_S32X2X2_IP; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 7) + return OPCODE_AE_S32X2X2_X; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 8) + return OPCODE_AE_S32X2X2_XP; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 9) + return OPCODE_J; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 10) + return OPCODE_CALL0; + if (Field_fld_ae4_slot0_22_20_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_L32R; + if (Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get (insn) == 63884) + return OPCODE_ALL4; + if (Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get (insn) == 63885) + return OPCODE_ANY4; + if (Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get (insn) == 63886 && + Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_ALL8; + if (Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get (insn) == 63886 && + Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_get (insn) == 1) + return OPCODE_ANY8; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15968) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15969) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15970) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 2) + return OPCODE_CALLX0; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 4) + return OPCODE_JX; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 5) + return OPCODE_RET; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 7) + return OPCODE_SSA8B; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 8) + return OPCODE_SSA8L; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 9) + return OPCODE_SSL; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 10) + return OPCODE_SSR; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_1_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot1_22_0_Slot_ae4_slot1_get (insn) == 2847494) + return OPCODE_NOP; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 668) + return OPCODE_ADD; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 669) + return OPCODE_ADDX2; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 670) + return OPCODE_ADDX4; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 671) + return OPCODE_ADDX8; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 672) + return OPCODE_AND; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 673) + return OPCODE_MAX; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 674) + return OPCODE_MAXU; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 675) + return OPCODE_MIN; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 676) + return OPCODE_MINU; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 677) + return OPCODE_MOVEQZ; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 678) + return OPCODE_MOVGEZ; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 679) + return OPCODE_MOVLTZ; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 680) + return OPCODE_MOVNEZ; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 681) + return OPCODE_OR; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 682) + return OPCODE_SALT; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 683) + return OPCODE_SALTU; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 684) + return OPCODE_SRC; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 685) + return OPCODE_SUB; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 686) + return OPCODE_SUBX2; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 687) + return OPCODE_SUBX4; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 688) + return OPCODE_SUBX8; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 689) + return OPCODE_XOR; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 690) + return OPCODE_CLAMPS; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 691) + return OPCODE_SEXT; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 692) + return OPCODE_SRLI; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 693) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 694 && + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 694 && + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 694 && + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 694 && + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 696 && + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 328) + return OPCODE_SLLI; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 329) + return OPCODE_SRAI; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 330) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 331) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 332) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 333) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 34) + return OPCODE_ADDI; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 35) + return OPCODE_ADDMI; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 36) + return OPCODE_L16SI; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 37) + return OPCODE_L16UI; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 38) + return OPCODE_L32I; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 39) + return OPCODE_L8UI; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 40) + return OPCODE_MOVI; + if (Field_fld_ae4_slot1_22_17_Slot_ae4_slot1_get (insn) == 16) + return OPCODE_EXTUI; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 0) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 1) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 2) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 3) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 4) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 5) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 6) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 7) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11120) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11121) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11122) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11123 && + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (insn) == 2) + return OPCODE_SSA8B; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11123 && + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (insn) == 3) + return OPCODE_SSA8L; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11123 && + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (insn) == 4) + return OPCODE_SSL; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11123 && + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (insn) == 5) + return OPCODE_SSR; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11123 && + Field_fld_ae4_slot1_3_1_Slot_ae4_slot1_get (insn) == 0) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae5_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67092) + return OPCODE_ADD; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67093) + return OPCODE_ADDX2; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67094) + return OPCODE_ADDX4; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67095) + return OPCODE_ADDX8; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67128) + return OPCODE_AND; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67129) + return OPCODE_MAX; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67130) + return OPCODE_MAXU; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67131) + return OPCODE_MIN; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67132) + return OPCODE_MINU; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67133) + return OPCODE_MOVEQZ; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67134) + return OPCODE_MOVGEZ; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67135) + return OPCODE_MOVLTZ; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67137) + return OPCODE_MOVNEZ; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67139) + return OPCODE_OR; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67141) + return OPCODE_SALT; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67143) + return OPCODE_SALTU; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67145) + return OPCODE_SRC; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67147) + return OPCODE_SUB; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67149) + return OPCODE_SUBX2; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67151) + return OPCODE_SUBX4; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67153) + return OPCODE_SUBX8; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67155) + return OPCODE_XOR; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67157) + return OPCODE_MOVF; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67159) + return OPCODE_MOVT; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67161) + return OPCODE_CLAMPS; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67163) + return OPCODE_SEXT; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67165) + return OPCODE_SRLI; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67167) + return OPCODE_AE_ARDECNORM16; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67169) + return OPCODE_ANDB; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67171) + return OPCODE_ANDBC; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67173) + return OPCODE_ORB; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67175) + return OPCODE_ORBC; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67177) + return OPCODE_XORB; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67228 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67234 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 11) + return OPCODE_ABS; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67234 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 7) + return OPCODE_SRA; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67234 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 15) + return OPCODE_SRL; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67235 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 11) + return OPCODE_NEG; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33328) + return OPCODE_AE_L16M_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33329) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33330) + return OPCODE_AE_L16M_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33331) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33332) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33333) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33334) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33335) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33336) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33337) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33338) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33339) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33340) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33341) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33342) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33343) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33376 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33376 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33377 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33377 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33378 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33378 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33379 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33379 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33380 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33380 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33381 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33381 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33382 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33382 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33383 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33383 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33384 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33384 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33385 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33385 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33386 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33386 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33387 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33387 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33387 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33388 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33388 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33388 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33389 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33389 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33389 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33390 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33390 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33390 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33391 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33391 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33391 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33392 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33392 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33392 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33393 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33393 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33393 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33394 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33394 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33394 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33395 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33395 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33395 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33396 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33396 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33396 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33397 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33397 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33397 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33398 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33398 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33398 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33399 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33399 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33399 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33400 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33400 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33400 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33401 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33401 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33401 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33402 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33402 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33402 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33403 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33403 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33403 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33404 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33404 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33404 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33405 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33405 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33405 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33406 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33406 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33406 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33407 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33407 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33407 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33408) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33409) + return OPCODE_AE_L16_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33410) + return OPCODE_AE_L16_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33411) + return OPCODE_AE_L16_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33412) + return OPCODE_AE_L16_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33413) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33414) + return OPCODE_AE_L16_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33415) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33416) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33417) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33418) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33419) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33420) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33421) + return OPCODE_AE_L32M_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33422) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33423) + return OPCODE_AE_L32M_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33424) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33425) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33426) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33427) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33428) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33429) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33430) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33431) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33432) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33433) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33434) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33435) + return OPCODE_AE_L32_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33436) + return OPCODE_AE_L32_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33437) + return OPCODE_AE_L32_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33438) + return OPCODE_AE_L32_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33439) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33440) + return OPCODE_AE_L32_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33441) + return OPCODE_AE_L64_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33442) + return OPCODE_AE_L64_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33443) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33444) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33445) + return OPCODE_AE_L64_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33446) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33447) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33448) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33449) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33450) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33451) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33452) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33453) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33454) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33455) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33456) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33457) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33458) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33459) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33460) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33461) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33462) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33463) + return OPCODE_AE_L8_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33464) + return OPCODE_AE_L8_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33465) + return OPCODE_AE_L8_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33466) + return OPCODE_AE_L8_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33467) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33468) + return OPCODE_AE_L8_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33469) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33470) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33471) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33472) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33473) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33474) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33475) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33476) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33477) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33478) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33479) + return OPCODE_AE_S16X2M_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33480) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33481) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33482) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33483) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33484) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33485) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33486) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33487) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33488) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33489) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33490) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33491) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33492) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33493) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33494) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33495) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33496) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33497) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33498) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33499) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33500) + return OPCODE_AE_S32M_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33501) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33502) + return OPCODE_AE_S32M_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33503) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33504) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33505) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33506) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33507) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33508) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33509) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33510) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33511) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33512) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33513) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33514) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33515) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33516) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33517) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33518) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33519) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33520) + return OPCODE_AE_S32_H_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33521) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33522) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33523) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33524) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33525) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33526) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33527) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33528) + return OPCODE_AE_S64_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33529) + return OPCODE_AE_S64_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33530) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33531) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33532) + return OPCODE_AE_S64_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33533) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33534) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33535) + return OPCODE_AE_S8X8_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33536) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33537) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33538) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33539) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33540) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33541) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33542) + return OPCODE_AE_S8_0_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33543) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33544) + return OPCODE_SLLI; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33545) + return OPCODE_SRAI; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33608 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33608 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_MOVAD8; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33609 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33610 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33611 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33612 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33613 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33615 && + Field_fld_ae5_slot0_7_0_Slot_ae5_slot0_get (insn) == 48) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33616 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33616 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33616 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33616 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA8X8_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 9) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 13) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 10) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 14) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33618) + return OPCODE_AE_S8X4U_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33619) + return OPCODE_AE_S8X4U_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33620) + return OPCODE_AE_S8X4U_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33621 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_S8X4U_IP; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8387 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8387 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8387 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8387 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8388 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8388 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_L64_IP; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8388 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8388 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8389 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8389 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8389 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8389 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_S64_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8390 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8390 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_S64_IP; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8400 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8400 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 7) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4150) + return OPCODE_ADDI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4151) + return OPCODE_ADDMI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4152) + return OPCODE_AE_LBK_DB; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4153) + return OPCODE_AE_LBK_DB_IC; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4154) + return OPCODE_AE_LBK_DB_IP; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4155) + return OPCODE_L16SI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4156) + return OPCODE_L16UI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4157) + return OPCODE_L32I; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4158) + return OPCODE_L8UI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4159) + return OPCODE_S16I; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4160) + return OPCODE_S32I; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4161) + return OPCODE_S8I; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4162) + return OPCODE_AE_LBKI_DBI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4163) + return OPCODE_AE_LBKI_DBI_IC; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4164) + return OPCODE_AE_LBKI_DBI_IP; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4165) + return OPCODE_MOVI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_AE_LBI_DBI_IC; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_AE_LBI_DBI_IP; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LBI_DBI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LB_DB_IC; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LB_DB_IP; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LB_DB; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_get (insn) == 2 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_CALCRNG16; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_get (insn) == 3 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_CALCRNG32; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4201 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4201 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4201 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae5_slot0_29_17_Slot_ae5_slot0_get (insn) == 2074) + return OPCODE_EXTUI; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1034) + return OPCODE_J; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1035) + return OPCODE_CALL0; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 25) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 27) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 28) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 31) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 30) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 29) + return OPCODE_AE_S32RA64S_XC1; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 20) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 22) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 21) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 26) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 23) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 24) + return OPCODE_AE_S24RA64S_XC1; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_ADD32; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_ADD32S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 9) + return OPCODE_MOVT_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_MOVF_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_MOVEQZ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_MOVNEZ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_MOVGEZ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 7) + return OPCODE_MOVLTZ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_S16X4RA32S_IP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (insn) == 12) + return OPCODE_AE_PKSR32; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (insn) == 28) + return OPCODE_AE_PKSR24; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (insn) == 28) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (insn) == 12) + return OPCODE_AE_PKSR16; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_get (insn) == 101) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_AE_MOVDA16X2; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_get (insn) == 100) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_6_Slot_ae5_slot0_get (insn) == 24) + return OPCODE_AE_MOVI; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_CVTP24A16X2_LH; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_CVTP24A16X2_HL; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_CVTP24A16X2_HH; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_get (insn) == 102) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_OLE_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 2 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_OLT_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_OEQ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 3 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_UN_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 2 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_ULE_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 2 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_ULT_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 2 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_UEQ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1051 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1051 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_MOV; + if (Field_fld_ae5_slot0_29_19_Slot_ae5_slot0_get (insn) == 516) + return OPCODE_AE_SEL16I; + if (Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_get (insn) == 256) + return OPCODE_L32R; + if (Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_get (insn) == 257) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_BBSI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_BALL_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_BANY_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_BBC_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 7) + return OPCODE_BBS_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_BEQ_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 9) + return OPCODE_BGEU_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 10) + return OPCODE_BGE_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 11) + return OPCODE_BLTU_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 12) + return OPCODE_BLT_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 13) + return OPCODE_BNALL_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 14) + return OPCODE_BNE_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 15) + return OPCODE_BNONE_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get (insn) == 12) + return OPCODE_BEQZ_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get (insn) == 14) + return OPCODE_BGEZ_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get (insn) == 28) + return OPCODE_BLTZ_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get (insn) == 30) + return OPCODE_BNEZ_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_BEQI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_BGEI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_BLTI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 10) + return OPCODE_BNEI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_BGEUI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_BLTUI_W15; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605313 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_VLDL16C_IC1; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605321 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_VLES16C_IC1; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605329 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_CALLX0; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605345 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_JX; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605353 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_RET; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605369 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_SSA8B; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605377 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_SSA8L; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605385 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_SSL; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605393 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_SSR; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605401 && + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (insn) == 17) + return OPCODE_NOP; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605401 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae5_slot0_29_6_Slot_ae5_slot0_get (insn) == 4301276 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_MOVALIGN; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075222 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075222 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075222 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4POS_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075222 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4NEG_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075223 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075223 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075223 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24NEG_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075223 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4POS_PC2; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075254 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA24POS_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075254 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075254 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075254 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2NEG_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075255 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA24X2POS_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075255 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075255 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075255 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2NEG_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075286 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075286 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2POS_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075286 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2POS_PC2; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075286 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8NEG_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075287 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8POS_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075287 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8POS_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075287 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8NEG_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075287 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8POS_PC2; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075318 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_ALL4; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075318 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_ANY4; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075318 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075318 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075319 && + Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_SSAI; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075319 && + Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_ALL8; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075319 && + Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_ANY8; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075319 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_RUR_AE_BITPTR; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae8_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10761) + return OPCODE_ADD; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10765) + return OPCODE_ADDX2; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10769) + return OPCODE_ADDX4; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10773) + return OPCODE_ADDX8; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10777) + return OPCODE_AND; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10781) + return OPCODE_MAX; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10785) + return OPCODE_MAXU; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10789) + return OPCODE_MIN; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10793) + return OPCODE_MINU; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10797) + return OPCODE_MOVEQZ; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10801) + return OPCODE_MOVGEZ; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10805) + return OPCODE_MOVLTZ; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10809) + return OPCODE_MOVNEZ; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10813) + return OPCODE_OR; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10817) + return OPCODE_SALT; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10821) + return OPCODE_SALTU; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10825) + return OPCODE_SRC; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10829) + return OPCODE_SUB; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10833) + return OPCODE_SUBX2; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10837) + return OPCODE_SUBX4; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10841) + return OPCODE_SUBX8; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10845) + return OPCODE_XOR; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10849) + return OPCODE_MOVF; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10853) + return OPCODE_MOVT; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10857) + return OPCODE_CLAMPS; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10861) + return OPCODE_SEXT; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10865) + return OPCODE_SRLI; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10869) + return OPCODE_ANDB; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10873) + return OPCODE_ANDBC; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10877) + return OPCODE_ORB; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10881) + return OPCODE_ORBC; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10885) + return OPCODE_XORB; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10889 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10889 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10889 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10889 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10893 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (insn) == 1344 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_SLLI; + if (Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (insn) == 1360 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_ALL4; + if (Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (insn) == 1360 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_ANY4; + if (Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (insn) == 1360 && + Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_get (insn) == 102) + return OPCODE_ALL8; + if (Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (insn) == 1360 && + Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_get (insn) == 103) + return OPCODE_ANY8; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 94) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 95) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 96) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 97) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 98) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 99) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 100) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 101) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 102) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 103) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 104) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 105) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 106) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 107) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 108) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 109) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 110) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 111) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 112) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 113) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 114) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 115) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 116) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 117) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 118) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 119) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 120) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 121) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 122) + return OPCODE_AE_S16X4X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 123) + return OPCODE_AE_S16X4X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 124) + return OPCODE_AE_S16X4X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 125) + return OPCODE_AE_S16X4X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 126) + return OPCODE_AE_S16X4X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 127) + return OPCODE_AE_S16X4X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 128) + return OPCODE_AE_S16X4X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 129) + return OPCODE_AE_S32X2X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 130) + return OPCODE_AE_S32X2X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 131) + return OPCODE_AE_S32X2X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 132) + return OPCODE_AE_S32X2X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 133) + return OPCODE_AE_S32X2X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 134) + return OPCODE_AE_S32X2X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 135) + return OPCODE_AE_S32X2X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 136) + return OPCODE_AE_S64X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 137) + return OPCODE_AE_S64X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 138) + return OPCODE_AE_S64X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 139) + return OPCODE_AE_S64X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 140) + return OPCODE_AE_S64X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 141) + return OPCODE_AE_S64X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 142) + return OPCODE_AE_S64X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 143) + return OPCODE_AE_S8X8X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 144) + return OPCODE_AE_S8X8X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 145) + return OPCODE_AE_S8X8X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 146) + return OPCODE_AE_S8X8X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 147) + return OPCODE_AE_S8X8X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 148) + return OPCODE_AE_S8X8X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 149) + return OPCODE_AE_S8X8X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 150) + return OPCODE_J; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 151) + return OPCODE_CALL0; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 153 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 153 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 153 && + Field_fld_ae8_slot0_13_13_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 154 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_L16SI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 154 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_L32I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 154 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_S16I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 154 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_S8I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 155 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_L16UI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 155 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_L8UI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 155 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_MOVI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 155 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_S32I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 160 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 0 && + Field_fld_ae8_slot0_7_5_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_SRAI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L16M_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_L16_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 17) + return OPCODE_AE_L8_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_L32_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_L32_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_L32M_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_L64_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 20) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 26) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 21) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 19) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 18) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 29) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 27) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 28) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 23) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 30) + return OPCODE_AE_S64_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 24) + return OPCODE_AE_S32M_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 25) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 16) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 22) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 31) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_L16_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 17) + return OPCODE_AE_L8_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_L32_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 16) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_L64_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 20) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 25) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 21) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 22) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 18) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 19) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 29) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 28) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 27) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 23) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 30) + return OPCODE_AE_S64_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 31) + return OPCODE_AE_S64_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 24) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 26) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L16M_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_L16_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 17) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 16) + return OPCODE_AE_L8_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_L32_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_L32M_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_L64_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 20) + return OPCODE_AE_S16X2M_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 19) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 25) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 26) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 21) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 31) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 18) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 28) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 29) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 27) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 23) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 22) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 30) + return OPCODE_AE_S64_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 24) + return OPCODE_AE_S32M_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_L16_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_L16_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 16) + return OPCODE_AE_L8_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 17) + return OPCODE_AE_L8_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_L32_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_L64_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_L64_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 19) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 20) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 25) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 21) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 31) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 18) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 28) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 27) + return OPCODE_AE_S32_H_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 26) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 22) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 23) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 30) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 29) + return OPCODE_AE_S64_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 24) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 168 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 168 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 168 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_S8_0_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 168 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 169 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 169 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 169 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 169 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X4U_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 172) + return OPCODE_AE_S8X4UX2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 173) + return OPCODE_AE_S8X4UX2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 174 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X4UX2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 174 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S8X4UX2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 175 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X4U_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 175 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S8X4U_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 175 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_S8X4U_XP; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 40) + return OPCODE_AE_TRUNCA16X4F32S; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 41) + return OPCODE_AE_TRUNCA16X4F64S; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 42) + return OPCODE_AE_TRUNCA32F64S_L; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 43) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 44) + return OPCODE_AE_TRUNCI32F64S_L; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 45) + return OPCODE_AE_TRUNCI32X2F64S; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 46) + return OPCODE_AE_SEL16I; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_SAT16X4; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_ROUND16X4F32SSYM; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_ROUND16X4F32SASYM; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_SATU16X4; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_SAT8X4X32_L; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_SATU8X4X32_L; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 81 && + Field_fld_ae8_slot0_8_0_Slot_ae8_slot0_get (insn) == 128) + return OPCODE_AE_MOV; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_LAV16X4X2_XP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_LAV8X8X2_XP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 16) + return OPCODE_AE_SAV16X4X2_XP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 17) + return OPCODE_AE_SAV8X8X2_XP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 18) + return OPCODE_L32R; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 19) + return OPCODE_AE_TRUNCI16X4F32S; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_SA16X4X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_SA16X4X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_SA16X4X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_SA16X4X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_SA8X8X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_SA8X8X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_SA8X8X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_SA8X8X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 243) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 244) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 245) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 240) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 241) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 242) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 246) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 247) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 248) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_SA32X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_SA8X8_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_SA8X8_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_SA8X8_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_SA8X8_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_8_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae8_slot0_31_21_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_TRUNCI16X4F64S; + if (Field_fld_ae8_slot0_31_22_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae8_slot0_31_23_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae8_slot0_31_7_Slot_ae8_slot0_get (insn) == 348594 && + Field_fld_ae8_slot0_6_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174288 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_CALLX0; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174290 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_JX; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174291 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_RET; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174293 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_SSA8B; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174294 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_SSA8L; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174295 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_SSL; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174296 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_SSR; + if (Field_fld_ae8_slot0_31_9_Slot_ae8_slot0_get (insn) == 87107 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae8_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5386) + return OPCODE_AND; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5387) + return OPCODE_MINU; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5388) + return OPCODE_MOVNEZ; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5389) + return OPCODE_SRC; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5390) + return OPCODE_SUBX8; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5391) + return OPCODE_SRLI; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5450) + return OPCODE_MAX; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5451) + return OPCODE_MOVEQZ; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5452) + return OPCODE_OR; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5453) + return OPCODE_SUB; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5454) + return OPCODE_XOR; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5455 && + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5455 && + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5455 && + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5455 && + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5512) + return OPCODE_ADD; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5513) + return OPCODE_ADDX4; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5514) + return OPCODE_MAXU; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5515) + return OPCODE_MOVGEZ; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5516) + return OPCODE_SALT; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5517) + return OPCODE_SUBX2; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5518) + return OPCODE_CLAMPS; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5522 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SLL; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5576) + return OPCODE_ADDX2; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5577) + return OPCODE_ADDX8; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5578) + return OPCODE_MIN; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5579) + return OPCODE_MOVLTZ; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5580) + return OPCODE_SALTU; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5581) + return OPCODE_SUBX4; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5582) + return OPCODE_SEXT; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2450) + return OPCODE_AE_L16M_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2451) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2452) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2453) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2454) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2455) + return OPCODE_AE_L16_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2456) + return OPCODE_AE_L32M_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2457) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2458) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2459) + return OPCODE_AE_L32_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2460) + return OPCODE_AE_L32_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2461) + return OPCODE_AE_L64_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2462) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2463) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2482) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2483) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2484) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2485) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2486) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2487) + return OPCODE_AE_L16_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2488) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2489) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2490) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2491) + return OPCODE_AE_L32_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2492) + return OPCODE_AE_L64_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2493) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2494) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2495) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2514) + return OPCODE_AE_L16M_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2515) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2516) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2517) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2518) + return OPCODE_AE_L16_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2519) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2520) + return OPCODE_AE_L32M_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2521) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2522) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2523) + return OPCODE_AE_L32_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2524) + return OPCODE_AE_L64_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2525) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2526) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2527) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2546) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2547) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2548) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2549) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2550) + return OPCODE_AE_L16_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2551) + return OPCODE_AE_L16_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2552) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2553) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2554) + return OPCODE_AE_L32_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2555) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2556) + return OPCODE_AE_L64_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2557) + return OPCODE_AE_L64_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2558) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2559) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2688) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2689) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2690) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2691) + return OPCODE_AE_L8_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2692) + return OPCODE_SLLI; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2696 && + Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2697 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2720) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2721) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2722) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2723) + return OPCODE_AE_L8_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2724) + return OPCODE_SRAI; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2728 && + Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2729 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2752) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2753) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2754) + return OPCODE_AE_L8_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2755) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2760 && + Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2784) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2785) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2786) + return OPCODE_AE_L8_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2787) + return OPCODE_AE_L8_XP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 48) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 49) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 50) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 51) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 52) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 53) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 54) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 55) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 56) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 57) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 58) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 59) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 60) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 61) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 62) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 63) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 64) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 65) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 66) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 67) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 68) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 69) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 70) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 71) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 72) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 73) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 74) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 75) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_15_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 5) + return OPCODE_L16UI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 4) + return OPCODE_L16SI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 6) + return OPCODE_L32I; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 7) + return OPCODE_L8UI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 8) + return OPCODE_MOVI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 7) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 10) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 6) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 6) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 7) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 8) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 9) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 10) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 11) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 14) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 12) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 13) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 9) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 10) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 14) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 12) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 13) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 320) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 6) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 7) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae8_slot1_29_22_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae8_slot1_29_23_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae8_slot1_29_5_Slot_ae8_slot1_get (insn) == 715056 && + Field_fld_ae8_slot1_4_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_NOP; + if (Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get (insn) == 89378 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SSA8B; + if (Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get (insn) == 89379 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SSA8L; + if (Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get (insn) == 89380 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SSL; + if (Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get (insn) == 89381 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SSR; + if (Field_fld_ae8_slot1_29_9_Slot_ae8_slot1_get (insn) == 44688 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae9_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (insn) == 40364 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_ALL4; + if (Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (insn) == 40364 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_ANY4; + if (Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (insn) == 40365 && + Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_get (insn) == 18) + return OPCODE_SSAI; + if (Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (insn) == 40365 && + Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_ALL8; + if (Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (insn) == 40365 && + Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_ANY8; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10064) + return OPCODE_ADD; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10065) + return OPCODE_ADDX2; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10066) + return OPCODE_ADDX4; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10067) + return OPCODE_ADDX8; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10068) + return OPCODE_AND; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10069) + return OPCODE_MAX; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10070) + return OPCODE_MAXU; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10071) + return OPCODE_MIN; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10072) + return OPCODE_MINU; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10073) + return OPCODE_MOVEQZ; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10074) + return OPCODE_MOVGEZ; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10075) + return OPCODE_MOVLTZ; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10076) + return OPCODE_MOVNEZ; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10077) + return OPCODE_OR; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10078) + return OPCODE_SALT; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10079) + return OPCODE_SALTU; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10080) + return OPCODE_SRC; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10081) + return OPCODE_SUB; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10082) + return OPCODE_SUBX2; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10083) + return OPCODE_SUBX4; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10084) + return OPCODE_SUBX8; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10085) + return OPCODE_XOR; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10086) + return OPCODE_MOVF; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10087) + return OPCODE_MOVT; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10088) + return OPCODE_CLAMPS; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10089) + return OPCODE_SEXT; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10090) + return OPCODE_SRLI; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10091 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_SRA; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10091 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_SRL; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10112 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10694 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_ABS; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10695 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4864) + return OPCODE_AE_L16M_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4865) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4866) + return OPCODE_AE_L16M_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4867) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4868) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4869) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4870) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4871) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4872) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4873) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4874) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4875) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4876) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4877) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4878) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4879) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4880) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4881) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4882) + return OPCODE_AE_L16_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4883) + return OPCODE_AE_L16_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4884) + return OPCODE_AE_L16_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4885) + return OPCODE_AE_L16_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4886) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4887) + return OPCODE_AE_L16_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4888) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4889) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4890) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4891) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4892) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4893) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4894) + return OPCODE_AE_L32M_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4895) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4896) + return OPCODE_AE_L32M_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4897) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4898) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4899) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4900) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4901) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4902) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4903) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4904) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4905) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4906) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4907) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4908) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4909) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4910) + return OPCODE_AE_L32_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4911) + return OPCODE_AE_L32_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4912) + return OPCODE_AE_L32_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4913) + return OPCODE_AE_L32_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4914) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4915) + return OPCODE_AE_L32_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4916) + return OPCODE_AE_L64_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4917) + return OPCODE_AE_L64_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4918) + return OPCODE_AE_L64_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4919) + return OPCODE_AE_L64_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4920) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4921) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4922) + return OPCODE_AE_L64_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4923) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4924) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4925) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4926) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4927) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4928) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4929) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4930) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4931) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4932) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4933) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4934) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4935) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4936) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4937) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4938) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4939) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4940) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4941) + return OPCODE_AE_L8_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4942) + return OPCODE_AE_L8_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4943) + return OPCODE_AE_L8_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4944) + return OPCODE_AE_L8_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4945) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4946) + return OPCODE_AE_L8_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4947) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4948) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4949) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4950) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4951) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4952) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4953) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4954) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4955) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4956) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4957) + return OPCODE_AE_S16X2M_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4958) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4959) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4960) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4961) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4962) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4963) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4964) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4965) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4966) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4967) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4968) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4969) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4970) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4971) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4972) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4973) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4974) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4975) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4976) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4977) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4978) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4979) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4980) + return OPCODE_AE_S32M_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4981) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4982) + return OPCODE_AE_S32M_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4983) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4984) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4985) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4986) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4987) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4988) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4989) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4990) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4991) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4992) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4993) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4994) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4995) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4996) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4997) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4998) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4999) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5000) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5001) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5002) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5003) + return OPCODE_AE_S32_H_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5004) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5005) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5006) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5007) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5008) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5009) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5010) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5011) + return OPCODE_AE_S64_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5012) + return OPCODE_AE_S64_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5013) + return OPCODE_AE_S64_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5014) + return OPCODE_AE_S64_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5015) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5016) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5017) + return OPCODE_AE_S64_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5018) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5019) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5020) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5021) + return OPCODE_AE_S8X8_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5022) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5023) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5024) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5025) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5026) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5027) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5028) + return OPCODE_AE_S8_0_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5029) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5030) + return OPCODE_SLLI; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5031) + return OPCODE_SRAI; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5046 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5046 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5047 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5047 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5048 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5049 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5050 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5051 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5052 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5053 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5054 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5055 && + Field_fld_ae9_slot0_7_6_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5055 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5055 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5055 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5055 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5064) + return OPCODE_AE_S8X4U_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5065) + return OPCODE_AE_S8X4U_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5066) + return OPCODE_AE_S8X4U_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5067 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S8X4U_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5250 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5251 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5282 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5283 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5314 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5315 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5346 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 566) + return OPCODE_ADDI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 567) + return OPCODE_ADDMI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 568) + return OPCODE_L16SI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 569) + return OPCODE_L16UI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 570) + return OPCODE_L32I; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 571) + return OPCODE_L8UI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 572) + return OPCODE_S16I; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 573) + return OPCODE_S32I; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 574) + return OPCODE_S8I; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 575) + return OPCODE_MOVI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 632 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 632 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 632 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae9_slot0_27_17_Slot_ae9_slot0_get (insn) == 282) + return OPCODE_EXTUI; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 74) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 75) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 76) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 77) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 78) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 79) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 80) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 81) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 82) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 83) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 84) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 85) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 86) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 87) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 88) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 89) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 90) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 91) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 92) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 93) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 94) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 95) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 96) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 97) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 98) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 99) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 100) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 101) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 102) + return OPCODE_AE_S16X4X2RNG_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 103) + return OPCODE_AE_S16X4X2RNG_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 104) + return OPCODE_AE_S16X4X2RNG_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 105) + return OPCODE_AE_S16X4X2RNG_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 106) + return OPCODE_AE_S16X4X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 107) + return OPCODE_AE_S16X4X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 108) + return OPCODE_AE_S16X4X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 109) + return OPCODE_AE_S16X4X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 110) + return OPCODE_AE_S16X4X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 111) + return OPCODE_AE_S16X4X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 112) + return OPCODE_AE_S16X4X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 113) + return OPCODE_AE_S32X2X2RNG_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 114) + return OPCODE_AE_S32X2X2RNG_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 115) + return OPCODE_AE_S32X2X2RNG_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 116) + return OPCODE_AE_S32X2X2RNG_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 117) + return OPCODE_AE_S32X2X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 118) + return OPCODE_AE_S32X2X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 119) + return OPCODE_AE_S32X2X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 120) + return OPCODE_AE_S32X2X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 121) + return OPCODE_AE_S32X2X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 122) + return OPCODE_AE_S32X2X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 123) + return OPCODE_AE_S32X2X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 124) + return OPCODE_AE_S64X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 125) + return OPCODE_AE_S64X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 126) + return OPCODE_AE_S64X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 127) + return OPCODE_AE_S64X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 128) + return OPCODE_AE_S64X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 129) + return OPCODE_AE_S64X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 130) + return OPCODE_AE_S64X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 131) + return OPCODE_AE_S8X8X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 132) + return OPCODE_AE_S8X8X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 133) + return OPCODE_AE_S8X8X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 134) + return OPCODE_AE_S8X8X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 135) + return OPCODE_AE_S8X8X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 136) + return OPCODE_AE_S8X8X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 137) + return OPCODE_AE_S8X8X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 138) + return OPCODE_J; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 139) + return OPCODE_CALL0; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 148 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_get (insn) == 15) + return OPCODE_AE_LE32; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 148 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_get (insn) == 7) + return OPCODE_AE_EQ32; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 148 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_LT64; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 148 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_get (insn) == 5) + return OPCODE_AE_LE64; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 148 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_AE_EQ64; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_get (insn) == 23) + return OPCODE_AE_MOV; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_get (insn) == 7) + return OPCODE_AE_LT16; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_get (insn) == 30) + return OPCODE_AE_LE16; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_get (insn) == 14) + return OPCODE_AE_EQ16; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_LT32; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 183) + return OPCODE_CVTSF16_L; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 181) + return OPCODE_CVTSF16_H; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 179) + return OPCODE_CVTF16S_L; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 177) + return OPCODE_CVTF16S_H; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 8 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_OLE_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 9 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_OLT_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 8 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_OEQ_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 11 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_UN_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 10 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_ULE_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 10 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_ULT_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 9 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_UEQ_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 185) + return OPCODE_FICEIL_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 187) + return OPCODE_FIFLOOR_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 189) + return OPCODE_FIRINT_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 191) + return OPCODE_FIROUND_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_get (insn) == 87) + return OPCODE_RMINNUM_H; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_get (insn) == 55) + return OPCODE_RMAXNUM_H; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 150 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S8X4UX2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 151 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S8X4UX2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 159) + return OPCODE_AE_S8X4UX2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 160 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 8) + return OPCODE_FITRUNC_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 704) + return OPCODE_AE_S8X4UX2_XP; + if (Field_fld_ae9_slot0_27_19_Slot_ae9_slot0_get (insn) == 36) + return OPCODE_AE_SEL16I; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 12) + return OPCODE_AE_LAV16X4X2_XP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 13) + return OPCODE_AE_LAV8X8X2_XP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 14) + return OPCODE_AE_SAV16X4X2_XP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 15) + return OPCODE_AE_SAV8X8X2_XP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 16) + return OPCODE_L32R; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 17) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 11) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 7) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 10) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 15) + return OPCODE_AE_SA16X4X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 12) + return OPCODE_AE_SA16X4X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 13) + return OPCODE_AE_SA16X4X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 14) + return OPCODE_AE_SA16X4X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 7) + return OPCODE_AE_SA8X8X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_AE_SA8X8X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 5) + return OPCODE_AE_SA8X8X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_SA8X8X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 40 && + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get (insn) == 2 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 40 && + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get (insn) == 3 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 579) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 580) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 581) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 576) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 577) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 578) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 582) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 583) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 584) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_SALIGN128_I; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 585) + return OPCODE_AE_SA128POS_FP; + if (Field_fld_ae9_slot0_27_22_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_TRUNC_S; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get (insn) == 1 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_UTRUNC_S; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_TRUNC_SX2; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_UTRUNC_SX2; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_FLOAT_SX2; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_UFLOAT_SX2; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 6 && + Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_FLOAT_S; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 6 && + Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_UFLOAT_S; + if (Field_fld_ae9_slot0_27_3_Slot_ae9_slot0_get (insn) == 5178144 && + Field_fld_ae9_slot0_2_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_NOP; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161808 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_CALLX0; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161810 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_JX; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161811 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_RET; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161813 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_SSA8B; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161814 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_SSA8L; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161815 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_SSL; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161816 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_SSR; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae9_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5392) + return OPCODE_MAXU; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5393) + return OPCODE_MIN; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5394) + return OPCODE_SALT; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5395) + return OPCODE_SALTU; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5396) + return OPCODE_CLAMPS; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5397) + return OPCODE_SEXT; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5398 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 10) + return OPCODE_SLL; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5454) + return OPCODE_ADD; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5455) + return OPCODE_ADDX2; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5456) + return OPCODE_MINU; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5457) + return OPCODE_MOVEQZ; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5458) + return OPCODE_SRC; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5459) + return OPCODE_SUB; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5460) + return OPCODE_SRLI; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5461 && + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5461 && + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5461 && + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5461 && + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5518) + return OPCODE_ADDX4; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5519) + return OPCODE_ADDX8; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5520) + return OPCODE_MOVGEZ; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5521) + return OPCODE_MOVLTZ; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5522) + return OPCODE_SUBX2; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5523) + return OPCODE_SUBX4; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5582) + return OPCODE_AND; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5583) + return OPCODE_MAX; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5584) + return OPCODE_MOVNEZ; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5585) + return OPCODE_OR; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5586) + return OPCODE_SUBX8; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5587) + return OPCODE_XOR; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2456) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2457) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2458) + return OPCODE_AE_L32M_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2459) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2460) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2461) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2462) + return OPCODE_AE_L32_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2463) + return OPCODE_AE_L64_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2480) + return OPCODE_AE_L16M_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2481) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2482) + return OPCODE_AE_L16M_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2483) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2484) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2485) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2486) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2487) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2488) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2489) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2490) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2491) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2492) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2493) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2494) + return OPCODE_AE_L32_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2495) + return OPCODE_AE_L64_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2512) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2513) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2514) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2515) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2516) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2517) + return OPCODE_AE_L16_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2518) + return OPCODE_AE_L16_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2519) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2520) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2521) + return OPCODE_AE_L32M_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2522) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2523) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2524) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2525) + return OPCODE_AE_L32_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2526) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2527) + return OPCODE_AE_L64_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2544) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2545) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2546) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2547) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2548) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2549) + return OPCODE_AE_L16_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2550) + return OPCODE_AE_L16_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2551) + return OPCODE_AE_L16_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2552) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2553) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2554) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2555) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2556) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2557) + return OPCODE_AE_L32_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2558) + return OPCODE_AE_L32_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2559) + return OPCODE_AE_L64_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2688) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2689) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2690) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2691) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2692) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2693) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2694) + return OPCODE_AE_L8_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2695) + return OPCODE_SRAI; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2699 && + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2720) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2721) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2722) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2723) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2724) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2725) + return OPCODE_AE_L8_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2726) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2731 && + Field_fld_ae9_slot1_3_2_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2731 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 4) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2731 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 5) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2731 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 6) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2731 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 7) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2752) + return OPCODE_AE_L64_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2753) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2754) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2755) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2756) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2757) + return OPCODE_AE_L8_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2758) + return OPCODE_AE_L8_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2762 && + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2762 && + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2784) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2785) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2786) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2787) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2788) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2789) + return OPCODE_AE_L8_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2790) + return OPCODE_SLLI; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2794 && + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2794 && + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 306) + return OPCODE_MOVI; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 308) + return OPCODE_ADDI; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 309) + return OPCODE_ADDMI; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 312) + return OPCODE_L16SI; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 313) + return OPCODE_L32I; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 316) + return OPCODE_L16UI; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 317) + return OPCODE_L8UI; + if (Field_fld_ae9_slot1_26_17_Slot_ae9_slot1_get (insn) == 152) + return OPCODE_EXTUI; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 48) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 49) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 50) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 51) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 52) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 53) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 54) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 55) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 56) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 57) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 58) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 59) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 60) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 61) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 62) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 63) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 64) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 65) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 66) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 67) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 68) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 69) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 70) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 71) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 72) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 73) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 74) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 75) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae9_slot1_26_2_Slot_ae9_slot1_get (insn) == 5659202 && + Field_fld_ae9_slot1_1_0_Slot_ae9_slot1_get (insn) == 3) + return OPCODE_NOP; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 7) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 10) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 6) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 355 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 356 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 357 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 352 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 353 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 354 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 358 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 359 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 360 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 384) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_get (insn) == 11 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 8) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_get (insn) == 11 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 9) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae9_slot1_26_22_Slot_ae9_slot1_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae9_slot1_26_23_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get (insn) == 86377 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_SSL; + if (Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get (insn) == 87401 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_SSR; + if (Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get (insn) == 87402 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_SSA8B; + if (Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get (insn) == 87403 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_SSA8L; + if (Field_fld_ae9_slot1_26_9_Slot_ae9_slot1_get (insn) == 43189 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116372 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116373 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116380 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116381 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ALL4; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116381 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ANY4; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116381 && + Field_fld_ae_slot0_8_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_ALL8; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116381 && + Field_fld_ae_slot0_8_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_ANY8; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28835 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28835 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28835 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28835 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LB; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28837 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28839 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 48) + return OPCODE_RUR_FCR; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28839 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 112) + return OPCODE_RUR_FSR; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28839 && + Field_fld_ae_slot0_5_0_Slot_ae_slot0_get (insn) == 16) + return OPCODE_AE_MOVAB4; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28839 && + Field_fld_ae_slot0_4_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVAB2; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 29091 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_SRL; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 29091 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAB; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 29091 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVBA; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 29091 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LBI; + if (Field_fld_ae_slot0_28_14_Slot_ae_slot0_get (insn) == 10904 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_SSAI; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3612 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 56) + return OPCODE_SLL; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1080) + return OPCODE_CALLX0; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1208) + return OPCODE_JX; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1272) + return OPCODE_RET; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1400) + return OPCODE_SSA8B; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1464) + return OPCODE_SSA8L; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1528) + return OPCODE_SSL; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1592) + return OPCODE_SSR; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1656) + return OPCODE_AE_MOVASAR; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4871 && + Field_fld_ae_slot0_12_10_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4871 && + Field_fld_ae_slot0_12_10_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4871 && + Field_fld_ae_slot0_12_10_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4900 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_SUBX8; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4900 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AND; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4900 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ANDBC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4900 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_CLAMPS; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4900 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ADDX4; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SRLI; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ORBC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_MOVF; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MAXU; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_DB; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4908 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_XOR; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4908 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ORB; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4908 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MAX; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4908 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SEXT; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ADDX8; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_ANDB; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_XORB; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_MOVT; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MIN; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVSARA7X2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4910 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_MOVGEZ; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4910 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_MINU; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4911 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_MOVEQZ; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4911 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_MOVLTZ; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4942 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_MOVNEZ; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4942 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SRC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4943 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADD; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4943 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SUB; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4943 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_OR; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4974 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SUBX2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4974 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_SALT; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4975 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADDX2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4975 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SUBX4; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4975 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_SALTU; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA24X2POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA24X2NEG_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2NEG_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA24POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA24NEG_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA16X4POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4NEG_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA8X8POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA8X8NEG_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA8X8NEG_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_DBI; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5380 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5388 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5412 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5420 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5444 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5476 && + Field_fld_ae_slot0_12_0_Slot_ae_slot0_get (insn) == 69) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5476 && + Field_fld_ae_slot0_12_6_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_MOVALIGN; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 1802 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 1806 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 1818 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 1822 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2106 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2110 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2362 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2366 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16M_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S8_0_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32M_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2450 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2450 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2450 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2450 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SRAI; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L64_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16M_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2471 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2471 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2471 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2471 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S64_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32M_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32M_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32M_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2482 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8X4U_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2482 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S8X4U_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2482 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8X4U_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2482 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S8X4U_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2496 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2618 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2622 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2712 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2712 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2712 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2712 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2716 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2716 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2716 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2716 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L8_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32_H_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2874 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2878 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L64_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L64_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S8X8_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S64_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S64_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3130 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3134 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3386 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3390 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3642 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3646 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3898 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3902 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L64_X; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_NEG32; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ABS32; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_NEG24S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ABS24S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_NEG32S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_ABS32S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_NEG16S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_ABS16S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ABS16; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_NEG64; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_ABS64; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_NEG64S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_ABS64S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_DIV64D32_H; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_ABS8; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ABS8S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_NEG8S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 192 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_EQ64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 193 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_CVTF16S_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 193 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_CVTF16S_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 194 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LE64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 195 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_CVTSF16_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 195 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_CVTSF16_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 196 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LT64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 197 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FICEIL_S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 197 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FIFLOOR_S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 199 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FIRINT_S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 199 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FIROUND_S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_MAX32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_MAX16; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADD64S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_ADD8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADD8S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_ROUND24X2F48SASYM; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_MIN32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MIN16; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MAX64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MIN64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MAX8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_MIN8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_MOVNEG32S_T; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 228 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0) + return OPCODE_J; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_ROUND32X2F64SASYM; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ROUND24X2F48SSYM; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SUB32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SUB16; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SUB24S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SUB32S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_SUB16S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SUB64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 230 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0) + return OPCODE_CALL0; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 230 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0) + return OPCODE_L32I; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 230 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1) + return OPCODE_L8UI; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 230 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0) + return OPCODE_S16I; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 230 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1) + return OPCODE_S32I; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SUB64S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SUB8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SUB8S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LE8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LT8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_EQ8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_RNG32X4; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FITRUNC_S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 273 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADD16; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 273 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADD16S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 275 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADD32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 275 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADD24S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 277 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADD32S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 277 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 279 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 279 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADD64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 280 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_9_Slot_ae_slot0_get (insn) == 9 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 1) + return OPCODE_TRUNC16_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 280 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_9_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 1) + return OPCODE_UTRUNC16_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_SLLI; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCA32Q48; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCA16P24S_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCA16P24S_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSA64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSAZ16_0; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_RFR; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 310 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 310 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_LOOPGTZ; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 310 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 8) + return OPCODE_LOOPNEZ; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32F24S_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32F24S_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 337 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 608 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 339 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0) + return OPCODE_S8I; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 370 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ADDI; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 370 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADDMI; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 374 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1) + return OPCODE_L16UI; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 374 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0) + return OPCODE_L16SI; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0) + return OPCODE_L32R; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_10_Slot_ae_slot0_get (insn) == 172 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_SA32X2_IC2; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IC2; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_IC2; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SA8X8_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_SA32X2F24_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_SA32X2F24_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_SA24_L_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_SA24_L_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SA24X2_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SA24X2_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 32) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 24) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_12_Slot_ae_slot0_get (insn) == 161 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 16) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_10_Slot_ae_slot0_get (insn) == 164 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SALIGN128_I; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 40) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 48) + return OPCODE_WFR; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 77 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVDA32X2; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 77 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 77 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 84 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 576 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 84 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 608 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SA128POS_FP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 85 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 608 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LT16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LE16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_EQ16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LT32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LE32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_EQ32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OLE_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OLT_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OEQ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UN_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ULE_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ULT_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UEQ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OEQ_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OLE_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OLT_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UEQ_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ULE_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ULT_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UN_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SEL16I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 52 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 52 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVT64; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVF64; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_13_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_AND; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_13_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_NAND; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_13_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_OR; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_13_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_XOR; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 53 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_BMAX32X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_BMIN32X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVADEXT_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVADEXT_L; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADDC32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADDC32U; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVT_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVF_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S32X2X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S32X2X2RNG_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2X2RNG_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S32X2X2RNG_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2X2RNG_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S16X4X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X4X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X4X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S16X4X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X4X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X4X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S16X4X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X4X2RNG_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S16X4X2RNG_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X4X2RNG_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S16X4X2RNG_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 32 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 33 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 33 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S32X2X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8X8X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S8X8X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8X4UX2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S8X4UX2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X4RA32S_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8X2_IC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4X2_IC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2X2_IC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8X2_IC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4X2_IC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2X2_IC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8X2_IC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4X2_IC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2X2_IC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_BMAX16X4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_BMIN16X4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SUBC32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SUBC32U; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 36 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 37 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 37 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 0) + return OPCODE_MOVI; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S32X2X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S8X8X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_1_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8X4UX2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_1_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8X4UX2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8X8X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S24RA64S_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOV; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCQ32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_PKSR32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_PKSR16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_MOVEQZ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 12) + return OPCODE_MOVNEZ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_MOVGEZ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 8) + return OPCODE_MOVLTZ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 40 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 41 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 41 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16) + return OPCODE_EXTUI; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S32X2X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVBA1X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_19_8_Slot_ae_slot0_get (insn) == 1568 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVBA4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_18_8_Slot_ae_slot0_get (insn) == 544 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVBA2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 576 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVBD1X4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 512 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVBD1X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 44 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 45 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDW16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 45 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDW32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 46 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 46 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S64X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 48 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 49 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDW8; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 49 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDW8U; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 50 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S64X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 50 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 52 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 53 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SUBW16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 53 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SUBW32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 54 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 54 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S64X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 57 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SUBW8; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 57 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SUBW8U; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 58 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S8X8X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 58 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 60 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 61 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SAV8X8X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 61 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SAV16X4X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 62 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8X8X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 62 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S8X8X2_X; + if (Field_fld_ae_slot0_28_24_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVT8X16_H; + if (Field_fld_ae_slot0_28_24_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_MOVT8X16_L; + if (Field_fld_ae_slot0_28_24_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae_slot0_28_26_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVT16X8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 392 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 384 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 392 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 387 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 395 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 386 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 394 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 386 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 387 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 395 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 384 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 392 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 384 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LA24_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 384 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 392 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA24_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_LA24X2_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_LA24X2_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_TRUNCA32F64S_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRA64_32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 36 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 36 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_SRLI24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 36 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SRAI24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_SRLS24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SRAS24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAI16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAI16R; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 44 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_SRLI32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SRAI32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 44 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SRAI32R; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_SRLS32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SRAS32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAA32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLA32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI16S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAA16S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA16S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA16RS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI24S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 46 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAA32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA32RS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLASQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_SRLSQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SRASQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAAQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLAQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAAQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SLAI64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLI64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAI64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_SRLS64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SRAS64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAA64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLA64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAA64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLAISQ56S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLASSQ56S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAASQ56S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SLAI64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAA64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 386 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 394 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRAI8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRAI8R; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLI8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAI8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAI8S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAA8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLA8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAA8S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAA8RS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAA8S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLI16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAA16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRLA16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAI16SYM; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA16SYMS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 46 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SRAI32SYM; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA32SYMS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAV16RS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAV32RS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTI32X4F8_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTI32X4F8_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTI32X4F8S_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTI32X4F8S_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32X4F8_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_CVTA32X4F8_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTA32X4F8S_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTA32X4F8S_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTI32X4F8U_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTI32X4F8U_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTI32X4F8US_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTI32X4F8US_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTA32X4F8U_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTA32X4F8U_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32X4F8US_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_CVTA32X4F8US_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTI32X4F16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTI32X4F16S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTA32X4F16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTA32X4F16S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTI32X4F16U; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTI32X4F16US; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32X4F16U; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_CVTA32X4F16US; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTI16X4X2F8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTI16X4X2F8S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTA16X4X2F8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTA16X4X2F8S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTI16X4X2F8U; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_CVTI16X4X2F8US; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA16X4X2F8U; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_CVTA16X4X2F8US; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_MOVDEXT; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_NSA16X4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSAZ32X4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSA32X4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_TRUNCI16X4F32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCI16X4F64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_TRUNCA16X4F32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCA16X4F64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LAV8X8X2_XP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LAV16X4X2_XP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_TRUNC_S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_UTRUNC_S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_TRUNC_SX2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_UTRUNC_SX2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_17_Slot_ae_slot0_get (insn) == 96 && + Field_fld_ae_slot0_9_4_Slot_ae_slot0_get (insn) == 16) + return OPCODE_FLOAT_S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_17_Slot_ae_slot0_get (insn) == 96 && + Field_fld_ae_slot0_9_4_Slot_ae_slot0_get (insn) == 20) + return OPCODE_UFLOAT_S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FLOAT_SX2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_UFLOAT_SX2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_FICEIL_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_FIFLOOR_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_FIRINT_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_FIROUND_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_FITRUNC_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_17_Slot_ae_slot0_get (insn) == 96 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_3_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FLOAT16_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_17_Slot_ae_slot0_get (insn) == 96 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_3_Slot_ae_slot0_get (insn) == 8) + return OPCODE_UFLOAT16_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FLOAT16_HX4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UFLOAT16_HX4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_12_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_TRUNC16_HX4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UTRUNC16_HX4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_RMINNUM_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_RMAXNUM_H; + if (Field_fld_ae_slot0_28_4_Slot_ae_slot0_get (insn) == 11214853 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_NOP; + if (Field_fld_ae_slot0_28_8_Slot_ae_slot0_get (insn) == 697920 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_WUR_FCR; + if (Field_fld_ae_slot0_28_8_Slot_ae_slot0_get (insn) == 697952 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_WUR_FSR; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot1_25_1_Slot_ae_slot1_get (insn) == 10858630 && + Field_fld_ae_slot1_0_0_Slot_ae_slot1_get (insn) == 0) + return OPCODE_NOP; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5390) + return OPCODE_MAXU; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5391) + return OPCODE_MIN; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5392) + return OPCODE_SALT; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5393) + return OPCODE_SALTU; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5394) + return OPCODE_CLAMPS; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5395) + return OPCODE_SEXT; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5409 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5409 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5409 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5409 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SRL; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5409 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_LB; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5452) + return OPCODE_ADD; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5453) + return OPCODE_ADDX2; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5454) + return OPCODE_MINU; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5455) + return OPCODE_MOVEQZ; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5456) + return OPCODE_SRC; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5457) + return OPCODE_SUB; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5458) + return OPCODE_SRLI; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5459) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5516) + return OPCODE_ADDX4; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5517) + return OPCODE_ADDX8; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5518) + return OPCODE_MOVGEZ; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5519) + return OPCODE_MOVLTZ; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5520) + return OPCODE_SUBX2; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5521) + return OPCODE_SUBX4; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5526 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SLL; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5527 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5580) + return OPCODE_AND; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5581) + return OPCODE_MAX; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5582) + return OPCODE_MOVNEZ; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5583) + return OPCODE_OR; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5584) + return OPCODE_SUBX8; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5585) + return OPCODE_XOR; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5590 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_LBI; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2456) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2457) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2458) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2459) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2460) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2461) + return OPCODE_AE_L32_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2462) + return OPCODE_AE_L32_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2463) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2480) + return OPCODE_AE_L16M_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2481) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2482) + return OPCODE_AE_L16M_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2483) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2484) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2485) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2486) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2487) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2488) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2489) + return OPCODE_AE_L32M_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2490) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2491) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2492) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2493) + return OPCODE_AE_L32_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2494) + return OPCODE_AE_L64_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2495) + return OPCODE_AE_L64_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2512) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2513) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2514) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2515) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2516) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2517) + return OPCODE_AE_L16_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2518) + return OPCODE_AE_L16_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2519) + return OPCODE_AE_L16_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2520) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2521) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2522) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2523) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2524) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2525) + return OPCODE_AE_L32_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2526) + return OPCODE_AE_L64_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2527) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2544) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2545) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2546) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2547) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2548) + return OPCODE_AE_L16_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2549) + return OPCODE_AE_L16_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2550) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2551) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2552) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2553) + return OPCODE_AE_L32M_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2554) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2555) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2556) + return OPCODE_AE_L32_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2557) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2558) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2559) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2688) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2689) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2690) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2691) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2692) + return OPCODE_AE_L8_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2693) + return OPCODE_AE_L8_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2694) + return OPCODE_SRAI; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2698 && + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2699 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2699 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2699 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2720) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2721) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2722) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2723) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2724) + return OPCODE_AE_L8_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2725) + return OPCODE_AE_MOVDA32X2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2730 && + Field_fld_ae_slot1_3_2_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2730 && + Field_fld_ae_slot1_3_2_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2731 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2731 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2731 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2752) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2753) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2754) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2755) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2756) + return OPCODE_AE_L8_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2757) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2761 && + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2761 && + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2763 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2763 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2784) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2785) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2786) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2787) + return OPCODE_AE_L8_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2788) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2789) + return OPCODE_SLLI; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2793 && + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2793 && + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2795 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2795 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 306) + return OPCODE_MOVI; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 308) + return OPCODE_ADDI; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 309) + return OPCODE_ADDMI; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 312) + return OPCODE_L16SI; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 313) + return OPCODE_L32I; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 316) + return OPCODE_L16UI; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 317) + return OPCODE_L8UI; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 152) + return OPCODE_EXTUI; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 160 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 13) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 160 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 14) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 160 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 160 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 15) + return OPCODE_AE_L64_I; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 162 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 13) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 162 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_L64_IP; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 169 && + Field_fld_ae_slot1_12_8_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 48) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 49) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 50) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 51) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 52) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 53) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 54) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 55) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 56) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 57) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 58) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 59) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 60) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 61) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 62) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 63) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 64) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 65) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 66) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 67) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 68) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 69) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 70) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 71) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 72) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 73) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 74) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 75) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 737 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 641 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 673 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 705 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 545 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 577 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 609 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 769 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 801 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 833 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_17_Slot_ae_slot1_get (insn) == 1 && + Field_fld_ae_slot1_12_8_Slot_ae_slot1_get (insn) == 0 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 513 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA128_PP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 7) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 10) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 13) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 8) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 9) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 11 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 11 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 10) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 11) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 14) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 15) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae_slot1_25_22_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae_slot1_25_23_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 82785 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_SSL; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 83809 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_SSR; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 86576) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 86577) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 86578) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 86579) + return OPCODE_AE_MOVSARA7X2; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 89458 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SSA8B; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 89459 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SSA8L; + if (Field_fld_ae_slot1_25_9_Slot_ae_slot1_get (insn) == 44728 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_get (insn) == 2560) + return OPCODE_OR; + if (Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_get (insn) == 2561) + return OPCODE_XOR; + if (Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_get (insn) == 2562) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 288 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 289 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16_I; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 290 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 291 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16_X; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 292 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16_XC; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 293 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16_XP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 294 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 295 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 296 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 297 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32_I; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 298 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 299 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32_X; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 300 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32_XC; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 301 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32_XP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 302 && + Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_get (insn) == 7) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 302 && + Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_get (insn) == 6) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 303 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 12) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 303 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 13) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 303 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 14) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 303 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 15) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 321 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 321 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 321 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 321 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 321 && + Field_fld_ae6_slot1_9_5_Slot_ae6_slot1_get (insn) == 8) + return OPCODE_AE_MOV; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 2) + return OPCODE_AE_TRUNCI16X4F32S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 4 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_CVTA16X4X2F8; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 4 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_CVTA16X4X2F8S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 5 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_CVTI16X4X2F8; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 5 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_CVTA16X4X2F8U; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 6 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_CVTI16X4X2F8S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 6 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_CVTI16X4X2F8U; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 7 && + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_TRUNCA16X4F32S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 7 && + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_TRUNCA16X4F64S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 8 && + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 8 && + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_TRUNCI32X2F64S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 9 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 9 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 9 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 2) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae6_slot1_27_21_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_TRUNCI16X4F64S; + if (Field_fld_ae6_slot1_27_3_Slot_ae6_slot1_get (insn) == 1315112 && + Field_fld_ae6_slot1_2_0_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_NOP; + if (Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_get (insn) == 164357) + return OPCODE_AE_LA128_PP; + if (Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_get (insn) == 164373) + return OPCODE_AE_LA64_PP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae10_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae10_slot2_34_10_Slot_ae10_slot2_get (insn) == 28442624 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 101) + return OPCODE_NOP; + if (Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get (insn) == 1968640) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get (insn) == 1968641) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get (insn) == 1968642 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 17) + return OPCODE_CONST_S; + if (Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get (insn) == 1968642 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 16) + return OPCODE_CONST_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 15) + return OPCODE_AE_MOV; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 8) + return OPCODE_NEXP01_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 4) + return OPCODE_MKSADJ_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_DIV0_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 11) + return OPCODE_SQRT0_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 9) + return OPCODE_RECIP0_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 10) + return OPCODE_RSQRT0_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_ABS_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 7) + return OPCODE_NEG_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_CONJC_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 6) + return OPCODE_MULJC_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 12) + return OPCODE_ABS_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 13) + return OPCODE_CLSFY_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_CONJC_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 5) + return OPCODE_MULJC_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 14) + return OPCODE_NEG_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984322 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_CLSFY_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984322 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24640 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MAX_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24640 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MAXNUM_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24641 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MIN_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24641 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MINNUM_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24704 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_FREXP_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24704 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 25728 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MAX_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 25728 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MAXNUM_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 26752 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_DIVN_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 26752 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MINNUM_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 26752 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MADDN_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 98) + return OPCODE_MKDADJ_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 97) + return OPCODE_ADDEXP_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 96) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MIN_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 100) + return OPCODE_ADDEXP_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 99) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 28800 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MADD_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 29824 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MSUBN_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30752) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30753) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30754) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30755) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30756) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30757) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30758) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30759) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30848 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MSUB_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 31872 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MUL_S; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_ADD_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 161) + return OPCODE_SUB_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 129) + return OPCODE_MUL_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 33) + return OPCODE_MADD_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 97) + return OPCODE_MSUB_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 65) + return OPCODE_MSUBN_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 833) + return OPCODE_MADDQ_S; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 865) + return OPCODE_MSUBQ_S; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 897) + return OPCODE_MULQ_S; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 929) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 993 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_MADDA_S; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 10) + return OPCODE_MADD_SX2X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 11) + return OPCODE_MSUB_SX2X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 12) + return OPCODE_MUL_SX2X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 13) + return OPCODE_ADD_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 14) + return OPCODE_MADD_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 15) + return OPCODE_MSUB_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 16) + return OPCODE_MUL_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 17) + return OPCODE_SUB_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 18) + return OPCODE_ADD_SX2X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 19) + return OPCODE_SUB_SX2X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 5) + return OPCODE_MULQ_H; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_MADDQ_H; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MULCNVH_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MULACNVH_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 4) + return OPCODE_MULCNVL_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MULACNVL_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 21 && + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (insn) == 0 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 34) + return OPCODE_ADD_S; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 21 && + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (insn) == 0 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 66) + return OPCODE_SUB_S; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 21 && + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (insn) == 0 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 21 && + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (insn) == 0 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 21 && + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (insn) == 0 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_get (insn) == 4) + return OPCODE_MULMUX_SX2X2; + if (Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_get (insn) == 12 && + Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_get (insn) == 128 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MULMUX_S; + if (Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_get (insn) == 12 && + Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MULMUXQ_S; + if (Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_MADDMUX_SX2X2; + if (Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_get (insn) == 3 && + Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_get (insn) == 128 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_get (insn) == 3 && + Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_MADDMUXQ_S; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae10_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae10_slot3_34_10_Slot_ae10_slot3_get (insn) == 23102864 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 18) + return OPCODE_NOP; + if (Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get (insn) == 1443864) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get (insn) == 1443865) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get (insn) == 1443928 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 19) + return OPCODE_CONST_S; + if (Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get (insn) == 1443928 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 18) + return OPCODE_CONST_H; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 17) + return OPCODE_AE_MOV; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 4) + return OPCODE_NEXP01_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 3) + return OPCODE_MKSADJ_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_DIV0_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 7) + return OPCODE_SQRT0_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 5) + return OPCODE_RECIP0_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 6) + return OPCODE_RSQRT0_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 8) + return OPCODE_ABS_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 13) + return OPCODE_NEG_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 10) + return OPCODE_CONJC_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 12) + return OPCODE_MULJC_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_CLSFY_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 2) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 14) + return OPCODE_ABS_H; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 15) + return OPCODE_CLSFY_H; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 9) + return OPCODE_CONJC_H; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 11) + return OPCODE_MULJC_H; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 16) + return OPCODE_NEG_H; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 18496 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_DIVN_S; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 19520 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MADDN_S; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 20544 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MADD_S; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 21568 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MSUBN_S; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 22592 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MSUB_S; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 23616 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MUL_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 577) + return OPCODE_MADDQ_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 609) + return OPCODE_MSUBQ_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 641) + return OPCODE_MULQ_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 673) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_4_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_AE_SEL16I; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 27) + return OPCODE_MIN_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 25) + return OPCODE_MAX_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 26) + return OPCODE_MINNUM_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 25) + return OPCODE_MAXNUM_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 9) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 8) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 24) + return OPCODE_FREXP_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 26) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 24) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_BMAXNUM_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get (insn) == 2) + return OPCODE_BMINNUM_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_BMAXNUMABS_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get (insn) == 2) + return OPCODE_BMINNUMABS_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 7) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 3) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 5) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 29) + return OPCODE_MIN_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 28) + return OPCODE_MAX_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 28) + return OPCODE_MINNUM_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 27) + return OPCODE_MAXNUM_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 6) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 2) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 4) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 5) + return OPCODE_ADD_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 6) + return OPCODE_SUB_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 226) + return OPCODE_MKDADJ_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 225) + return OPCODE_ADDEXP_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 224) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 4) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_MADDA_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 228) + return OPCODE_ADDEXP_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 227) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 64) + return OPCODE_ADD_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 98) + return OPCODE_SUB_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 66) + return OPCODE_MUL_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 96) + return OPCODE_MADD_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 97) + return OPCODE_MSUB_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 65) + return OPCODE_MSUBN_H; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 10) + return OPCODE_MADD_SX2X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 11) + return OPCODE_MSUB_SX2X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 12) + return OPCODE_MUL_SX2X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 13) + return OPCODE_MADD_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 14) + return OPCODE_MSUB_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 15) + return OPCODE_MUL_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 5) + return OPCODE_MULQ_H; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_MADDQ_H; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 3) + return OPCODE_MULCNVH_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MULACNVH_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 4) + return OPCODE_MULCNVL_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 2) + return OPCODE_MULACNVL_HX4X2; + if (Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_get (insn) == 4) + return OPCODE_MULMUX_SX2X2; + if (Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_get (insn) == 8 && + Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_get (insn) == 64 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MULMUX_S; + if (Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_get (insn) == 8 && + Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MULMUXQ_S; + if (Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_MADDMUX_SX2X2; + if (Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_get (insn) == 2 && + Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_get (insn) == 64 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_get (insn) == 2 && + Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_MADDMUXQ_S; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae2_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12292 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_ADD_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12420 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_DIVN_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12548 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MADDN_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12676 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MADD_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12684 && + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_PKSR24; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12684 && + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get (insn) == 0 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_PKSR16; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12685 && + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get (insn) == 0 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_PKSR32; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12685 && + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 131) + return OPCODE_AE_RADD8X8_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 227) + return OPCODE_AE_RADDA8X8_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 163) + return OPCODE_AE_RADD8X8_L; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 99) + return OPCODE_AE_RADD16X4; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 195) + return OPCODE_AE_RADDA16X4; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 67) + return OPCODE_MKDADJ_S; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 35) + return OPCODE_ADDEXP_S; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_0_Slot_ae2_slot2_get (insn) == 232448) + return OPCODE_NOP; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 67) + return OPCODE_AE_RMAX8X8; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 131) + return OPCODE_AE_RMIN8X8; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 35) + return OPCODE_AE_RMAX16X4; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 99) + return OPCODE_AE_RMIN16X4; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_RADDA8X8_L; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 195) + return OPCODE_ADDEXP_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 163) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12804 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MSUB_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12932 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MUL_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 13060 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_SUB_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3072) + return OPCODE_AE_MULAFC32RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3074 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3074 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP16S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3074 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAA2D16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3075 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3075 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3075 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MSUBN_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3104) + return OPCODE_AE_MULFC32RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3106 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3106 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3106 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3107 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3107 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3107 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MSUB_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3136) + return OPCODE_MADDA_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3138 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3138 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3138 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP16X16X4S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3139 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3139 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3139 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MUL_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULA32U_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 27) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 26) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 25) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 30) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 23) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 31) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 24) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 22) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 20) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 21) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 19) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 16) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULA32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 17) + return OPCODE_AE_MULAAD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 18) + return OPCODE_AE_MULAAD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULAA2D16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULAA2D16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 28) + return OPCODE_AE_MULAAFD16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 29) + return OPCODE_AE_MULAAFD16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3170 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3170 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3170 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3171 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFC16RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3171 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 18) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULF32RA_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32RA_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 22) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 17) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 29) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 23) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 28) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 21) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 27) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 20) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 24) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 16) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULFP32X2TS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULC32X16_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULC16S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 19) + return OPCODE_AE_MULS32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULFCJ32RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3202 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3202 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3202 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3203 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3203 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULC16JS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 18) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULF32RA_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 22) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 24) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 17) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 29) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 23) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 28) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 21) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 27) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 20) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 16) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULC16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 19) + return OPCODE_AE_MULS32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULASD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULCJ32; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULP16S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULFP16X4RS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3234 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3234 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3234 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3235 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3235 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULC16JS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 24) + return OPCODE_AE_MULSF32RA_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 19) + return OPCODE_AE_MULS32U_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 17) + return OPCODE_AE_MULS16S_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 29) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 23) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 28) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 21) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 27) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 20) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 16) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULC32; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULFC16RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 18) + return OPCODE_AE_MULS32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 22) + return OPCODE_AE_MULSAD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULASD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3266 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC16JS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3266 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3266 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP32X2T; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3267 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3267 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 17) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULF32RA_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 24) + return OPCODE_AE_MULSF32RA_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 21) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 28) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 27) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 20) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 19) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 23) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 29) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 16) + return OPCODE_AE_MULP32X2T; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X2TS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULC32X16_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 18) + return OPCODE_AE_MULS32S_HL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 22) + return OPCODE_AE_MULSAD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULFCJ16RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULC16S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULP16X16X4S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3298 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC16JS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3298 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3298 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3299 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3299 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3330 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3330 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3330 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC16S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3331 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3331 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFCJ16RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3362 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3362 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC16S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3362 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSS2D16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3363 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3363 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFCJ32RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3394 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3394 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3394 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSS2D16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3395 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL16S_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3395 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3395 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSS2D16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3426 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3426 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3426 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC32; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3427 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3427 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3427 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSS2D16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3458 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3458 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3458 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC32X16_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3459 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3459 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3459 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3490 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3490 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC32X16_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3490 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3491 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3491 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32S_HL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3491 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3522 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3522 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULACJ32; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3522 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3523 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3523 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3523 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3554 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3554 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3554 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3555 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3555 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3555 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3586 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32RA_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3586 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3586 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3587 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32U_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3587 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3587 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3618 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32RA_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3618 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3618 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3619 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3619 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3619 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3650 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32RA_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3650 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3650 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3651 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3651 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3651 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3682 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3682 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3682 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3683 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3683 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3683 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3714 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3714 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3714 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3715 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3715 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3715 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X2TS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3746 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3746 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3746 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3747 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3747 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP16S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3747 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3778 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3778 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3778 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3779 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3779 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3779 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3810 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3810 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3810 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3811 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3811 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3811 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP16X16X4S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3842 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3842 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3842 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3843 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3843 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3843 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3874 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3874 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3874 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3875 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3875 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3875 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3906 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3906 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3906 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3907 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3907 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3907 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3938 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3938 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3938 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3939 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3939 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3939 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP32X2T; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3970 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3970 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3970 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3971 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA16S_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3971 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3971 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4002 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4002 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4002 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4003 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4003 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4003 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_DIVN_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4034 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4034 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4034 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4035 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4035 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4035 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_MADDN_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4066 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4066 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4066 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZAA2D16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4067 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4067 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA32S_HL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4067 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_MADD_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 64 && + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_BMAXNUMABS_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 65 && + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_BMAXNUM_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 66 && + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_BMINNUMABS_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 67 && + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_BMINNUM_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 68 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 320) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 68 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 256) + return OPCODE_FREXP_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 68 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 288) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 69 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 320) + return OPCODE_ADD_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 69 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 288) + return OPCODE_MINNUM_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 69 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 256) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 70 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 320) + return OPCODE_SUB_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 70 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 288) + return OPCODE_MIN_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 70 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 256) + return OPCODE_MAXNUM_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 71 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 288) + return OPCODE_AE_SORT16X4; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 71 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 256) + return OPCODE_MAX_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 71 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 320 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_CLSFY_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 71 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 320 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae2_slot2_42_26_Slot_ae2_slot2_get (insn) == 52 && + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_MULMUX_S; + if (Field_fld_ae2_slot2_42_28_Slot_ae2_slot2_get (insn) == 12 && + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_ADD_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_SUB_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_get (insn) == 67745) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 15430 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MOV; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_get (insn) == 67744) + return OPCODE_AE_ABS16S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_DSEL8X8; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 2118 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_NEXP01_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 1094 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_MKSADJ_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 70 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_DIV0_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 5190 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_SQRT0_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 3142 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_RECIP0_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 4166 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_RSQRT0_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 6214 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_ABS_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 11334 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_NEG_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 8262 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_CONJC_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 10310 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_MULJC_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_get (insn) == 32909 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_CONST_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 100) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 68) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 96) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 99) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 97) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 98) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_get (insn) == 141 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 12358 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_ABS_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 13382 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_CLSFY_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 7238 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_CONJC_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_get (insn) == 32908 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_CONST_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 1125) + return OPCODE_MIN_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 101) + return OPCODE_MAX_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 1093) + return OPCODE_MINNUM_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 69) + return OPCODE_MAXNUM_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 9286 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_MULJC_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 14406 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_NEG_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 64) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 67) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 65) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_get (insn) == 140 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 66) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MIN32; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MAX32; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MIN16; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MAX16; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MAX8; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MIN8; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 33) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 32) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_SEL8X8I; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot2_23_0_Slot_ae4_slot2_get (insn) == 5668865) + return OPCODE_NOP; + if (Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get (insn) == 1368) + return OPCODE_AE_PKSR16; + if (Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get (insn) == 1369) + return OPCODE_AE_PKSR24; + if (Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get (insn) == 1370) + return OPCODE_AE_PKSR32; + if (Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get (insn) == 1371) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 164) + return OPCODE_AE_MAX16; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 165) + return OPCODE_AE_MAX32; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 166) + return OPCODE_AE_MAX8; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 167) + return OPCODE_AE_MIN16; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 168) + return OPCODE_AE_MIN32; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 169) + return OPCODE_AE_MIN8; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 170) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 172 && + Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_get (insn) == 1) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 172 && + Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_get (insn) == 0) + return OPCODE_AE_ABS16S; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 173 && + Field_fld_ae4_slot2_4_0_Slot_ae4_slot2_get (insn) == 0) + return OPCODE_AE_MOV; + if (Field_fld_ae4_slot2_23_17_Slot_ae4_slot2_get (insn) == 40) + return OPCODE_AE_SEL16I_N; + if (Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (insn) == 1) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (insn) == 2) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (insn) == 3) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (insn) == 4) + return OPCODE_AE_ADDANDSUBRNG32_L; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot3_27_20_Slot_ae4_slot3_get (insn) == 96 && + Field_fld_ae4_slot3_14_10_Slot_ae4_slot3_get (insn) == 0) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 0) + return OPCODE_AE_MULFPC32X16X2RAS; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 1) + return OPCODE_AE_MULFPCJ32X16X2RAS; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 22 && + Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_get (insn) == 161) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 1) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 2) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 3) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 4) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_19_Slot_ae4_slot3_get (insn) == 0 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_SEL16I; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_5_Slot_ae4_slot3_get (insn) == 23557) + return OPCODE_AE_MOV; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 22 && + Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_get (insn) == 160) + return OPCODE_AE_ABS16S; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 20 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MIN32; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 17 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MAX32; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 19 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MIN16; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 16 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MAX16; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 18 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MAX8; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 21 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MIN8; + if (Field_fld_ae4_slot3_27_3_Slot_ae4_slot3_get (insn) == 8482964 && + Field_fld_ae4_slot3_2_0_Slot_ae4_slot3_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot4_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot4_22_0_Slot_ae4_slot4_get (insn) == 5308480) + return OPCODE_NOP; + if (Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get (insn) == 160) + return OPCODE_AE_MAX16; + if (Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get (insn) == 161) + return OPCODE_AE_MIN16; + if (Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get (insn) == 162 && + Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_get (insn) == 1) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get (insn) == 162 && + Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_get (insn) == 0) + return OPCODE_AE_ABS16S; + if (Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (insn) == 1) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (insn) == 2) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (insn) == 3) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (insn) == 4) + return OPCODE_AE_ADDANDSUBRNG32_L; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae5_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae5_slot1_1_0_Slot_ae5_slot1_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae5_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae5_slot2_24_0_Slot_ae5_slot2_get (insn) == 24117778) + return OPCODE_NOP; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 752 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 753 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_ADDEXP_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 754 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_MKDADJ_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 755 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 756 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_ADDEXP_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 768) + return OPCODE_FREXP_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 769) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 770) + return OPCODE_MAXNUM_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 771) + return OPCODE_MAX_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 772) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 773) + return OPCODE_MINNUM_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 774) + return OPCODE_MIN_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 775) + return OPCODE_ADD_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 776) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 777) + return OPCODE_ADD_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 778) + return OPCODE_MADD_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 779) + return OPCODE_MSUB_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 780) + return OPCODE_MUL_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 781) + return OPCODE_SUB_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 782) + return OPCODE_SUB_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 783 && + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_CLSFY_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 783 && + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get (insn) == 184 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_PKSR16; + if (Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get (insn) == 185 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_PKSR24; + if (Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get (insn) == 186 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_PKSR32; + if (Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get (insn) == 187 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MUL16X4; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MUL16X4S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULAFC32RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULFC32RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_SEL8X8I; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_7_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_SEL16I_N; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MUL32U_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULA32U_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MUL16S_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULA16S_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MUL32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULA32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MUL32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULA32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MUL32S_HL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULA32S_HL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MUL32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULA32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULAAD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULAAD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULAA2D16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULAA2D16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULAAFD16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULAAFD16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULAC32; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULAC32X16_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULAC32X16_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULAFCJ32RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULACJ32; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULAFCJ16RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULAC16S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULAFP32X2TS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULAP32X2T; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULASD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULASD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULAP16S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULAP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULC16S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULAP16X16X4S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULFP16X4S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULC32; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULC32X16_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULC32X16_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULFCJ32RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULCJ32; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULFCJ16RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULFP16X4RS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULS32U_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULS16S_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULFP32X2TS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULP32X2T; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULS32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULS32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULS32S_HL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULS32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULP16S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULP16X16X4S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULSAD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULSAD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULSFP32X2TS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULSP32X2T; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULSSD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULSSD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULSP16S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULSP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULSP16X16X4S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULSS2D16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULSS2D16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULSSFD16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULZAAD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULZASD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULZAAD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULZAA2D16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULZAA2D16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULZAAFD16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULZAAFD16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULSSFD16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULZSAD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULZSSD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULZASD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULZSAD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULZSSD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULZSS2D16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULZSS2D16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULZSSFD16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULZSSFD16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_14_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 527) + return OPCODE_AE_MOV; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_MUL_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_MADD_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_MSUB_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_MSUBN_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_MADDN_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 514) + return OPCODE_NEXP01_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 513) + return OPCODE_MKSADJ_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 512) + return OPCODE_DIV0_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 517) + return OPCODE_SQRT0_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 515) + return OPCODE_RECIP0_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 516) + return OPCODE_RSQRT0_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_DIVN_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 518) + return OPCODE_ABS_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 523) + return OPCODE_NEG_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 520) + return OPCODE_CONJC_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 522) + return OPCODE_MULJC_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get (insn) == 0 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 529) + return OPCODE_CONST_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 524) + return OPCODE_ABS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 525) + return OPCODE_CLSFY_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 519) + return OPCODE_CONJC_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get (insn) == 0 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 528) + return OPCODE_CONST_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_MIN_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_MAX_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_MINNUM_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_MAXNUM_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 521) + return OPCODE_MULJC_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 526) + return OPCODE_NEG_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 25 && + Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 25 && + Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 25 && + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get (insn) == 1 && + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 25 && + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get (insn) == 1 && + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_CONST_HX4X2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19688) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19689) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19690) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19691) + return OPCODE_AE_MOV; + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19692) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19693) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2452) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2453) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2454 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2454 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2455 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_PKSR24; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2455 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_PKSR16; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2460 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_PKSR32; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2460 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_get (insn) == 1224) + return OPCODE_AE_MOVF64; + if (Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_get (insn) == 1225) + return OPCODE_AE_MOVT64; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 608 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_LE64; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 608 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_EQ64; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 609 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 609 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 609 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 609 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 610 && + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (insn) == 1 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 610 && + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 610 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_LT64; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 611 && + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 611 && + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 611 && + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (insn) == 1 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 611 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 3 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 611 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 2 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 614 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 2) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 614 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 3) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 614 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 614 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 624 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 624 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 2 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 624 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 1 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 60) + return OPCODE_AE_ADDC32; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 61) + return OPCODE_AE_ADDC32U; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 62) + return OPCODE_AE_BMAX32X2; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 63) + return OPCODE_AE_BMIN32X2; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 64) + return OPCODE_AE_SUBC32; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 65) + return OPCODE_AE_SUBC32U; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 66) + return OPCODE_AE_S16X4X2_I; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 67) + return OPCODE_AE_S16X4X2_IP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 68) + return OPCODE_AE_S16X4X2_X; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 69) + return OPCODE_AE_S16X4X2_XP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 70) + return OPCODE_AE_S32X2X2_I; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 71) + return OPCODE_AE_S32X2X2_IP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 72) + return OPCODE_AE_S32X2X2_X; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 73) + return OPCODE_AE_S32X2X2_XP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 74 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_BMAX8X8_L; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 74 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_BMAX16X4; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 75 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_BMIN8X8_L; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 75 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_BMIN16X4; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_7_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_L_IP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 20) + return OPCODE_AE_LT16; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 1 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 19) + return OPCODE_AE_LE16; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 19) + return OPCODE_AE_EQ16; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 18) + return OPCODE_AE_LT32; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 17) + return OPCODE_AE_LE32; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 16) + return OPCODE_AE_EQ32; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 79) + return OPCODE_AE_S8X4UX2_X; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 2104) + return OPCODE_AE_S8X4UX2_XP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 2105 && + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S8X4UX2_I; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 2106 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S8X4UX2_IP; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 2) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 3) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 4) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 5) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 6) + return OPCODE_AE_ADDW16; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 7) + return OPCODE_AE_ADDW32; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 8) + return OPCODE_AE_ADDW8; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 9) + return OPCODE_AE_ADDW8U; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 10) + return OPCODE_AE_SUBW16; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 11) + return OPCODE_AE_SUBW32; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 12) + return OPCODE_AE_SUBW8; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 13) + return OPCODE_AE_SUBW8U; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 14) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae6_slot0_29_5_Slot_ae6_slot0_get (insn) == 630208 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot2_24_0_Slot_ae6_slot2_get (insn) == 1245280) + return OPCODE_NOP; + if (Field_fld_ae6_slot2_24_10_Slot_ae6_slot2_get (insn) == 1170) + return OPCODE_AE_MOV; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 70) + return OPCODE_AE_MOVF64; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 71) + return OPCODE_AE_MOVT64; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 72 && + Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_get (insn) == 1) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 72 && + Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 73 && + Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_get (insn) == 1) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 73 && + Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 32) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 33) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 34) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 37 && + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get (insn) == 2) + return OPCODE_AE_PKSR32; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 37 && + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get (insn) == 1) + return OPCODE_AE_PKSR24; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 37 && + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get (insn) == 3) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 37 && + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_PKSR16; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 38 && + Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_get (insn) == 2) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 38 && + Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 38 && + Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_get (insn) == 1) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae6_slot2_24_20_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_MOVDX2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot3_37_13_Slot_ae6_slot3_get (insn) == 1179648 && + Field_fld_ae6_slot3_12_0_Slot_ae6_slot3_get (insn) == 33) + return OPCODE_NOP; + if (Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_get (insn) == 274432 && + Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_get (insn) == 274433 && + Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8192) + return OPCODE_AE_ACCW16; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8224) + return OPCODE_AE_ACCW32; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8256) + return OPCODE_AE_ACCW8; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8288) + return OPCODE_AE_ACCW8U; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8320) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8352) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8384) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8416) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8448) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8480) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 2 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_BMAX8X8_H; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 3 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_BMAX8X8_L; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 2 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_BMAX16X4; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 3 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_BMIN16X4; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_BMAX32X2; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_BMIN32X2; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 9) + return OPCODE_AE_ADD32S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 12) + return OPCODE_AE_SUB32S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 8) + return OPCODE_AE_ADD16S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 11) + return OPCODE_AE_SUB16S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 451) + return OPCODE_AE_NEG32S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 480) + return OPCODE_AE_ABS32S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 482) + return OPCODE_AE_NEG16S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 448) + return OPCODE_AE_ABS16S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 449) + return OPCODE_AE_ABS8S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 483) + return OPCODE_AE_NEG8S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 10) + return OPCODE_AE_ADD8S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 13) + return OPCODE_AE_SUB8S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 0 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_BMIN8X8_H; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 0 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_BMIN8X8_L; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 481) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 450) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_MULZAAF2D32RA_HH_LL; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_MULZAAF2D32RA_HL_LH; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 2) + return OPCODE_AE_MULZASF2D32RA_HH_LL; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 3) + return OPCODE_AE_MULZASF2D32RA_HL_LH; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 4) + return OPCODE_AE_MULZSAF2D32RA_HH_LL; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 5) + return OPCODE_AE_MULZSAF2D32RA_HL_LH; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 6) + return OPCODE_AE_MULZSSF2D32RA_HH_LL; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 7) + return OPCODE_AE_MULZSSF2D32RA_HL_LH; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 9 && + Field_fld_ae6_slot3_24_20_Slot_ae6_slot3_get (insn) == 0 && + Field_fld_ae6_slot3_14_0_Slot_ae6_slot3_get (insn) == 32) + return OPCODE_AE_MOV; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 9 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_MOVDX2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot0_23_0_Slot_ae7_slot0_get (insn) == 6889856) + return OPCODE_NOP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 864) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 865) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 866) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 867) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 868) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 869) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 870) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 871) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 872) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 873) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 874) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 875) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 876) + return OPCODE_AE_L64_X; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 877) + return OPCODE_AE_L64_XC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 878) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 879) + return OPCODE_AE_L64_XP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 880) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 881) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 882) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 883) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 884 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 884 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 885 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 885 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 885 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 886 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 886 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 886 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 887 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 887 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 887 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 888 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 888 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 888 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 889 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 889 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 889 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 890 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 890 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 890 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 8) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 9) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 10) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 11) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 892 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 892 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 893 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 893 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 894 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 894 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 895 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 895 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 52 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 52 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 6) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 52 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 4) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 52 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 7) + return OPCODE_AE_L64_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 52 && + Field_fld_ae7_slot0_12_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 53 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 5) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 53 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 4) + return OPCODE_AE_L64_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 4) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 5) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 6) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 7) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 8) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 9) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 10) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 11) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 12) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 13) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 14) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 15) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 16) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 17) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 18) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 19) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 20) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 21) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 22) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 23) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 24 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 24 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 24 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 24 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 25 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 25 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 25 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 25 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 26 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 106502) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 106630) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 106758) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 106886) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 107014) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 107142) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 107270) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 107398) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 107526) + return OPCODE_AE_LA8X8X2POS_PC2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot1_23_0_Slot_ae7_slot1_get (insn) == 6889856) + return OPCODE_NOP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 864) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 865) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 866) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 867) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 868) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 869) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 870) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 871) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 872) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 873) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 874) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 875) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 876) + return OPCODE_AE_L64_X; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 877) + return OPCODE_AE_L64_XC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 878) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 879) + return OPCODE_AE_L64_XP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 880) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 881) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 882) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 883) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 884 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 884 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 885 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 885 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 885 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 886 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 886 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 886 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 887 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 887 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 887 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 888 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 888 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 888 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 889 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 889 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 889 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 890 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 890 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 890 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 8) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 9) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 10) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 11) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 892 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 892 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 893 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 893 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 894 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 894 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 895 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 895 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 52 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 5) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 52 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 6) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 52 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 4) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 52 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 7) + return OPCODE_AE_L64_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 52 && + Field_fld_ae7_slot1_12_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 53 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 5) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 53 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 4) + return OPCODE_AE_L64_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 4) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 5) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 6) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 7) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 8) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 9) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 10) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 11) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 12) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 13) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 14) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 15) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 16) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 17) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 18) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 19) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 20) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 21) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 22) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 23) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 24 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 24 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 24 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 24 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 25 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 25 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 25 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 25 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 26 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 106502) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 106630) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 106758) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 106886) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 107014) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 107142) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 107270) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 107398) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 107526) + return OPCODE_AE_LA8X8X2POS_PC2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot2_36_12_Slot_ae7_slot2_get (insn) == 14772992 && + Field_fld_ae7_slot2_11_0_Slot_ae7_slot2_get (insn) == 1376) + return OPCODE_NOP; + if (Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_get (insn) == 1846592) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_get (insn) == 1846593) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57696) + return OPCODE_AE_MULAAAA2Q8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57697) + return OPCODE_AE_MULADDF32RAS; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57698) + return OPCODE_AE_MULADDF32RS; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57699) + return OPCODE_AE_MULSUBF32RAS; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57700) + return OPCODE_AE_MULSUBF32RS; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57701) + return OPCODE_AE_MULZAAAA2Q8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57702) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57703) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57704) + return OPCODE_AE_SEL8X8I; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 0) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 2) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 3) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 4) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 5) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 6) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 42) + return OPCODE_AE_MOV; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 39) + return OPCODE_AE_RMAX8X8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 41) + return OPCODE_AE_RMIN8X8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 38) + return OPCODE_AE_RMAX16X4; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 40) + return OPCODE_AE_RMIN16X4; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_10_Slot_ae7_slot2_get (insn) == 0) + return OPCODE_AE_SORT16X4; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 33) + return OPCODE_AE_RADD8X8_H; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 36) + return OPCODE_AE_RADDA8X8_H; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 34) + return OPCODE_AE_RADD8X8_L; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 37) + return OPCODE_AE_RADDA8X8_L; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 32) + return OPCODE_AE_RADD16X4; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 35) + return OPCODE_AE_RADDA16X4; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1760) + return OPCODE_AE_MULAAAA2Q16X8; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1761) + return OPCODE_AE_MULAF2P32X16X4RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1762) + return OPCODE_AE_MULAF2P32X16X4RS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1763) + return OPCODE_AE_MULAF2P32X16X4S; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1764) + return OPCODE_AE_MULAFD32X16X2_FIR_HH; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1765) + return OPCODE_AE_MULAFD32X16X2_FIR_HL; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1766) + return OPCODE_AE_MULAFD32X16X2_FIR_LH; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1767) + return OPCODE_AE_MULAFD32X16X2_FIR_LL; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1768) + return OPCODE_AE_MULAFD32X2RA_FIR_H; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1769) + return OPCODE_AE_MULAFD32X2RA_FIR_L; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1770) + return OPCODE_AE_MULAFD32X2S_FIR_H; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1771) + return OPCODE_AE_MULAFD32X2S_FIR_L; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1772) + return OPCODE_AE_MULAFPC32X16X2RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1773) + return OPCODE_AE_MULAFPCJ32X16X2RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1774) + return OPCODE_AE_MULAFQ16X2_FIR_0; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1775) + return OPCODE_AE_MULAFQ16X2_FIR_1; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1776) + return OPCODE_AE_MULAFQ16X2_FIR_2; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1777) + return OPCODE_AE_MULAFQ16X2_FIR_3; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1778) + return OPCODE_AE_MULAPC32X16X2; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1779) + return OPCODE_AE_MULF2P32X16X4RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1780) + return OPCODE_AE_MULF2P32X16X4RS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1781) + return OPCODE_AE_MULF2P32X16X4S; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1782) + return OPCODE_AE_MULFD32X16X2_FIR_HH; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1783) + return OPCODE_AE_MULFD32X16X2_FIR_HL; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1784) + return OPCODE_AE_MULFD32X16X2_FIR_LH; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1785) + return OPCODE_AE_MULFD32X16X2_FIR_LL; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1786) + return OPCODE_AE_MULFD32X2RA_FIR_H; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1787) + return OPCODE_AE_MULFD32X2RA_FIR_L; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1788) + return OPCODE_AE_MULFD32X2S_FIR_H; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1789) + return OPCODE_AE_MULFD32X2S_FIR_L; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1790) + return OPCODE_AE_MULFPC32X16X2RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1791) + return OPCODE_AE_MULFPCJ32X16X2RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1792) + return OPCODE_AE_MULFQ16X2_FIR_0; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1793) + return OPCODE_AE_MULFQ16X2_FIR_1; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1794) + return OPCODE_AE_MULFQ16X2_FIR_2; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1795) + return OPCODE_AE_MULFQ16X2_FIR_3; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1796) + return OPCODE_AE_MULPC32X16X2; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1797) + return OPCODE_AE_MULSF2P32X16X4RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1798) + return OPCODE_AE_MULSF2P32X16X4RS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1799) + return OPCODE_AE_MULSF2P32X16X4S; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1800) + return OPCODE_AE_MULZAAAA2Q16X8; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1801) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1802) + return OPCODE_AE_DSEL8X8; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1824 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULAAAAFQ32X16; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1825 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULAAAAQ32X16; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1826 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULZAAAAFQ32X16; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1827 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULZAAAAQ32X16; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 0) + return OPCODE_AE_MUL2P32X4; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MUL2P32X4S; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 2) + return OPCODE_AE_MUL2P32X4T; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 3) + return OPCODE_AE_MUL2Q32X16_FIR_H; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 4) + return OPCODE_AE_MUL2Q32X16_FIR_L; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 5) + return OPCODE_AE_MULA2P32X4; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 6) + return OPCODE_AE_MULA2P32X4T; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 7) + return OPCODE_AE_MULA2Q32X16_FIR_H; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 8) + return OPCODE_AE_MULA2Q32X16_FIR_L; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 9) + return OPCODE_AE_MULAAAA2Q16; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 10) + return OPCODE_AE_MULAAAA2Q32X16; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 11) + return OPCODE_AE_MULAAF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 12) + return OPCODE_AE_MULAAF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 13) + return OPCODE_AE_MULAAF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 14) + return OPCODE_AE_MULAAF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 15) + return OPCODE_AE_MULAF2P32X4RAS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 16) + return OPCODE_AE_MULAF2P32X4RS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 17) + return OPCODE_AE_MULASF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 18) + return OPCODE_AE_MULASF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 19) + return OPCODE_AE_MULASF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 20) + return OPCODE_AE_MULASF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 21) + return OPCODE_AE_MULF2D32X2WS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 22) + return OPCODE_AE_MULF2P32X4RAS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 23) + return OPCODE_AE_MULF2P32X4RS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 24) + return OPCODE_AE_MULFD16X16X4WS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 25) + return OPCODE_AE_MULS2P32X4; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 26) + return OPCODE_AE_MULS2P32X4T; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 27) + return OPCODE_AE_MULSAF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 28) + return OPCODE_AE_MULSAF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 29) + return OPCODE_AE_MULSAF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 30) + return OPCODE_AE_MULSAF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 31) + return OPCODE_AE_MULSF2P32X4RAS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 32) + return OPCODE_AE_MULSF2P32X4RS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 33) + return OPCODE_AE_MULSSF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 34) + return OPCODE_AE_MULSSF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 35) + return OPCODE_AE_MULSSF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 36) + return OPCODE_AE_MULSSF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 37) + return OPCODE_AE_MULZAAAA2Q16; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 38) + return OPCODE_AE_MULZAAAA2Q32X16; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 39) + return OPCODE_AE_MULZAAF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 40) + return OPCODE_AE_MULZAAF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 41) + return OPCODE_AE_MULZAAF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 42) + return OPCODE_AE_MULZAAF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 43) + return OPCODE_AE_MULZASF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 44) + return OPCODE_AE_MULZASF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 45) + return OPCODE_AE_MULZASF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 46) + return OPCODE_AE_MULZASF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 47) + return OPCODE_AE_MULZSAF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 48) + return OPCODE_AE_MULZSAF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 49) + return OPCODE_AE_MULZSAF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 50) + return OPCODE_AE_MULZSAF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 51) + return OPCODE_AE_MULZSSF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 52) + return OPCODE_AE_MULZSSF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 53) + return OPCODE_AE_MULZSSF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 54) + return OPCODE_AE_MULZSSF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 57 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 0) + return OPCODE_AE_MULFD16X16X4RAS; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot3_35_11_Slot_ae7_slot3_get (insn) == 29884417 && + Field_fld_ae7_slot3_10_0_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57632) + return OPCODE_AE_MULAAAA2Q8; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57633) + return OPCODE_AE_MULADDF32RAS; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57634) + return OPCODE_AE_MULADDF32RS; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57635) + return OPCODE_AE_MULSUBF32RAS; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57636) + return OPCODE_AE_MULSUBF32RS; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57637) + return OPCODE_AE_MULZAAAA2Q8; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57638 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57638 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57638 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 2) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57638 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 3) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57639 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57639 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57639 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 2) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1760) + return OPCODE_AE_MULAAAA2Q16X8; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1761) + return OPCODE_AE_MULAF2P32X16X4RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1762) + return OPCODE_AE_MULAF2P32X16X4RS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1763) + return OPCODE_AE_MULAF2P32X16X4S; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1764) + return OPCODE_AE_MULAFD32X16X2_FIR_HH; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1765) + return OPCODE_AE_MULAFD32X16X2_FIR_HL; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1766) + return OPCODE_AE_MULAFD32X16X2_FIR_LH; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1767) + return OPCODE_AE_MULAFD32X16X2_FIR_LL; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1768) + return OPCODE_AE_MULAFD32X2RA_FIR_H; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1769) + return OPCODE_AE_MULAFD32X2RA_FIR_L; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1770) + return OPCODE_AE_MULAFD32X2S_FIR_H; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1771) + return OPCODE_AE_MULAFD32X2S_FIR_L; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1772) + return OPCODE_AE_MULAFPC32X16X2RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1773) + return OPCODE_AE_MULAFPCJ32X16X2RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1774) + return OPCODE_AE_MULAFQ16X2_FIR_0; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1775) + return OPCODE_AE_MULAFQ16X2_FIR_1; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1776) + return OPCODE_AE_MULAFQ16X2_FIR_2; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1777) + return OPCODE_AE_MULAFQ16X2_FIR_3; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1778) + return OPCODE_AE_MULAPC32X16X2; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1779) + return OPCODE_AE_MULF2P32X16X4RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1780) + return OPCODE_AE_MULF2P32X16X4RS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1781) + return OPCODE_AE_MULF2P32X16X4S; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1782) + return OPCODE_AE_MULFD32X16X2_FIR_HH; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1783) + return OPCODE_AE_MULFD32X16X2_FIR_HL; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1784) + return OPCODE_AE_MULFD32X16X2_FIR_LH; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1785) + return OPCODE_AE_MULFD32X16X2_FIR_LL; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1786) + return OPCODE_AE_MULFD32X2RA_FIR_H; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1787) + return OPCODE_AE_MULFD32X2RA_FIR_L; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1788) + return OPCODE_AE_MULFD32X2S_FIR_H; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1789) + return OPCODE_AE_MULFD32X2S_FIR_L; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1790) + return OPCODE_AE_MULFPC32X16X2RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1791) + return OPCODE_AE_MULFPCJ32X16X2RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1792) + return OPCODE_AE_MULFQ16X2_FIR_0; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1793) + return OPCODE_AE_MULFQ16X2_FIR_1; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1794) + return OPCODE_AE_MULFQ16X2_FIR_2; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1795) + return OPCODE_AE_MULFQ16X2_FIR_3; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1796) + return OPCODE_AE_MULPC32X16X2; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1797) + return OPCODE_AE_MULSF2P32X16X4RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1798) + return OPCODE_AE_MULSF2P32X16X4RS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1799) + return OPCODE_AE_MULSF2P32X16X4S; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1800) + return OPCODE_AE_MULZAAAA2Q16X8; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1856 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULAAAAFQ32X16; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1856 && + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (insn) == 98) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1857 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULAAAAQ32X16; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1857 && + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (insn) == 98) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1858 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULZAAAAFQ32X16; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1859 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULZAAAAQ32X16; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MUL2P32X4; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MUL2P32X4S; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 2) + return OPCODE_AE_MUL2P32X4T; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 3) + return OPCODE_AE_MUL2Q32X16_FIR_H; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 4) + return OPCODE_AE_MUL2Q32X16_FIR_L; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 5) + return OPCODE_AE_MULA2P32X4; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 6) + return OPCODE_AE_MULA2P32X4T; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 7) + return OPCODE_AE_MULA2Q32X16_FIR_H; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 8) + return OPCODE_AE_MULA2Q32X16_FIR_L; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 9) + return OPCODE_AE_MULAAAA2Q16; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 10) + return OPCODE_AE_MULAAAA2Q32X16; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 11) + return OPCODE_AE_MULAAF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 12) + return OPCODE_AE_MULAAF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 13) + return OPCODE_AE_MULAAF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 14) + return OPCODE_AE_MULAAF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 15) + return OPCODE_AE_MULAF2P32X4RAS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 16) + return OPCODE_AE_MULAF2P32X4RS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 17) + return OPCODE_AE_MULASF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 18) + return OPCODE_AE_MULASF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 19) + return OPCODE_AE_MULASF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 20) + return OPCODE_AE_MULASF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 21) + return OPCODE_AE_MULF2D32X2WS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 22) + return OPCODE_AE_MULF2P32X4RAS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 23) + return OPCODE_AE_MULF2P32X4RS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 24) + return OPCODE_AE_MULFD16X16X4WS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 25) + return OPCODE_AE_MULS2P32X4; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 26) + return OPCODE_AE_MULS2P32X4T; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 27) + return OPCODE_AE_MULSAF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 28) + return OPCODE_AE_MULSAF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 29) + return OPCODE_AE_MULSAF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 30) + return OPCODE_AE_MULSAF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 31) + return OPCODE_AE_MULSF2P32X4RAS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 32) + return OPCODE_AE_MULSF2P32X4RS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 33) + return OPCODE_AE_MULSSF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 34) + return OPCODE_AE_MULSSF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 35) + return OPCODE_AE_MULSSF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 36) + return OPCODE_AE_MULSSF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 37) + return OPCODE_AE_MULZAAAA2Q16; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 38) + return OPCODE_AE_MULZAAAA2Q32X16; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 39) + return OPCODE_AE_MULZAAF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 40) + return OPCODE_AE_MULZAAF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 41) + return OPCODE_AE_MULZAAF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 42) + return OPCODE_AE_MULZAAF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 43) + return OPCODE_AE_MULZASF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 44) + return OPCODE_AE_MULZASF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 45) + return OPCODE_AE_MULZASF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 46) + return OPCODE_AE_MULZASF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 47) + return OPCODE_AE_MULZSAF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 48) + return OPCODE_AE_MULZSAF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 49) + return OPCODE_AE_MULZSAF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 50) + return OPCODE_AE_MULZSAF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 51) + return OPCODE_AE_MULZSSF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 52) + return OPCODE_AE_MULZSSF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 53) + return OPCODE_AE_MULZSSF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 54) + return OPCODE_AE_MULZSSF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 57 && + Field_fld_ae7_slot3_24_10_Slot_ae7_slot3_get (insn) == 2 && + Field_fld_ae7_slot3_4_0_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MOV; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 57 && + Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_DSEL8X8; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 57 && + Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 58 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MULFD16X16X4RAS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 58 && + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (insn) == 34) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 58 && + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (insn) == 2) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 58 && + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (insn) == 66) + return OPCODE_AE_SEL8X8I; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae8_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get (insn) == 566808 && + Field_fld_ae8_slot2_33_9_Slot_ae8_slot2_get (insn) == 4096 && + Field_fld_ae8_slot2_8_0_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get (insn) == 566808 && + Field_fld_ae8_slot2_33_25_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_15_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_get (insn) == 0) + return OPCODE_AE_MOV; + if (Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get (insn) == 566808 && + Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_get (insn) == 32 && + Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MOVZBVCDR; + if (Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get (insn) == 566808 && + Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MOVDRZBVC; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 262924) + return OPCODE_AE_MUL4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 263948) + return OPCODE_AE_MUL4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 264972) + return OPCODE_AE_MULA4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 265996) + return OPCODE_AE_MULA4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 267020) + return OPCODE_AE_MULASU4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 268044) + return OPCODE_AE_MULASU4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 269068) + return OPCODE_AE_MULAUS4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 270092) + return OPCODE_AE_MULAUS4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 271116) + return OPCODE_AE_MULAUU4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 272140) + return OPCODE_AE_MULAUU4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 273164) + return OPCODE_AE_MULAUUZB4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 274188) + return OPCODE_AE_MULAUUZB4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 275212) + return OPCODE_AE_MULSU4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 276236) + return OPCODE_AE_MULSU4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 277260) + return OPCODE_AE_MULUS4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 278284) + return OPCODE_AE_MULUS4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 279308) + return OPCODE_AE_MULUU4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 280332) + return OPCODE_AE_MULUU4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 281356) + return OPCODE_AE_MULUUZB4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 282380) + return OPCODE_AE_MULUUZB4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 287500) + return OPCODE_AE_MULAZB4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 288524) + return OPCODE_AE_MULZB4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 289548) + return OPCODE_AE_MULAZB4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 290572) + return OPCODE_AE_MULZB4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 360645 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MUL8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 360645 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MUL2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 360677 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MUL8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 360677 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULA2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 361669 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULA8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 361669 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULA8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 361701 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULASU8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 361701 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULASU2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 362693 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUS2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 362693 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULASU8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 362725 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUS8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 362725 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUS8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 363717 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUU8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 363717 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUU2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 363749 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUU8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 363749 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUUZB2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 364741 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUUZB8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 364741 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUUZB8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 364773 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULSU8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 364773 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULSU2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 365765 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 365765 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULSU8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 365797 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 365797 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUS8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 366789 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUU8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 366789 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUU2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 366821 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUU8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 366821 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUUZB2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 367813 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUUZB8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 367813 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUUZB8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 368837 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULZB2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 369893 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAZB8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 371941 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAZB8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 372933 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULZB8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 373989 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAZB2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 375013 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULZB8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10240) + return OPCODE_AE_MUL4O4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10272) + return OPCODE_AE_MUL4QW8X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10304) + return OPCODE_AE_MULA4O4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10336) + return OPCODE_AE_MULA4QW8X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10368) + return OPCODE_AE_MULAUS4O4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10400) + return OPCODE_AE_MULAUS4QW8X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10432) + return OPCODE_AE_MULUS4O4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10464) + return OPCODE_AE_MULUS4QW8X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 11264 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MUL8Q4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 11265 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MULA8Q4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 11266 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MULAUS8Q4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 11267 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MULUS8Q4X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 0) + return OPCODE_AE_MUL4O8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MUL8QW8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 2) + return OPCODE_AE_MULA4O8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 3) + return OPCODE_AE_MULA8QW8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULAUS4O8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULAUS8QW8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUS4O8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS8QW8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULQQ8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 2) + return OPCODE_AE_MULAQQ8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 140) + return OPCODE_AE_MUL4O8X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 332) + return OPCODE_AE_MULA4O8X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 172) + return OPCODE_AE_MUL4O8X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 364) + return OPCODE_AE_MULA4O8X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULQQ4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 0) + return OPCODE_AE_MULAQQ4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULQQ4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MULAQQ4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 12) + return OPCODE_AE_MUL4O4X16CNV_HH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 44) + return OPCODE_AE_MUL4O4X16CNV_HL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 76) + return OPCODE_AE_MUL4O4X16CNV_LH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 108) + return OPCODE_AE_MUL4O4X16CNV_LL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 204) + return OPCODE_AE_MULA4O4X16CNV_HH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 236) + return OPCODE_AE_MULA4O4X16CNV_HL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 268) + return OPCODE_AE_MULA4O4X16CNV_LH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 300) + return OPCODE_AE_MULA4O4X16CNV_LL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 11) + return OPCODE_AE_MULUSQQ8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULAUSQQ8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 716) + return OPCODE_AE_MULUS4O8X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 524) + return OPCODE_AE_MULAUS4O8X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 748) + return OPCODE_AE_MULUS4O8X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 556) + return OPCODE_AE_MULAUS4O8X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MULUSQQ4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3) + return OPCODE_AE_MULAUSQQ4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 10) + return OPCODE_AE_MULUSQQ4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULAUSQQ4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 588) + return OPCODE_AE_MULUS4O4X16CNV_HH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 620) + return OPCODE_AE_MULUS4O4X16CNV_HL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 652) + return OPCODE_AE_MULUS4O4X16CNV_LH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 684) + return OPCODE_AE_MULUS4O4X16CNV_LL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 396) + return OPCODE_AE_MULAUS4O4X16CNV_HH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 428) + return OPCODE_AE_MULAUS4O4X16CNV_HL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 460) + return OPCODE_AE_MULAUS4O4X16CNV_LH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 492) + return OPCODE_AE_MULAUS4O4X16CNV_LL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 0) + return OPCODE_AE_MUL4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MULA4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULUU4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULAUU4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 3) + return OPCODE_AE_MULAUS4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULSU4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 2) + return OPCODE_AE_MULASU4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MULUUZB4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULAUUZB4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 13) + return OPCODE_AE_MULZB4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 12) + return OPCODE_AE_MULAZB4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MUL8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 1 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULA8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 0) + return OPCODE_AE_MUL8Q8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MULA8Q8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 37 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MUL8Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 69 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULA8Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MUL2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 1 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULA2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MUL2X4Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 1 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULA2X4Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 5 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MUL8Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 37 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULA8Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 5 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MUL8Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 69 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULA8Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MUL2X4Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 1 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULA2X4Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MUL2X4Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 1 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULA2X4Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULUU8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 4 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULAUU8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 5 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULUU2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULAUU2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 7 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULUS8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULAUS8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 3) + return OPCODE_AE_MULUS8Q8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 2) + return OPCODE_AE_MULAUS8Q8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 165 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS8Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 133 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUS8Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 4 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULAUS2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 4 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUS2X4Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 2 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUS2X4Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 133 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS8Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 101 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUS8Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 165 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUS8Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 101 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUS8Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 4 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULUS2X4Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 2 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULAUS2X4Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 4 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULUS2X4Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 2 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUS2X4Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 6 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULSU8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 2 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULASU8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULSU2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 2 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULASU2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULUUZB8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 5 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULAUUZB8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 5 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULUUZB2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUUZB2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 14 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULZB8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 10 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULAZB8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 14) + return OPCODE_AE_MULZB2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 12) + return OPCODE_AE_MULAZB2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 256) + return OPCODE_AE_MULZB3X3O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 257) + return OPCODE_AE_MULAZB3X3O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 262) + return OPCODE_AE_MULAUUZB3X3O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 266) + return OPCODE_AE_MULUUZB3X3O8X8; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae9_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_get (insn) == 228098 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONST_H; + if (Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_get (insn) == 228099 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONST_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 98689 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ABS_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 99713 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONJC_H; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 100737 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONJC_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 101761 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_DIV0_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 102785 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MKSADJ_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 103809 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MULJC_H; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 104833 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MULJC_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 105857 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_NEG_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 106881 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_NEXP01_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 107905 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_RECIP0_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 108929 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_RSQRT0_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 109953 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_SQRT0_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 110977 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ABS_H; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 112001 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CLSFY_H; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 113025 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_NEG_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2624 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_DIVN_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2656 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MADDN_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2688 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MADD_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2720 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MSUBN_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2752 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MSUB_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2784 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MUL_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3083 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MAXNUM_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3115 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MAX_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3147 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MINNUM_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3179 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MIN_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3211 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 1 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_AE_MOVT64; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3211 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_AE_MOVF64; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 1 && + Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_get (insn) == 33) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 1 && + Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_get (insn) == 33) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 865) + return OPCODE_AE_MOV; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 705) + return OPCODE_MKDADJ_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 609) + return OPCODE_ADDEXP_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 577) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 833) + return OPCODE_ADDEXP_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 737) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 74) + return OPCODE_MADDQ_S; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 75) + return OPCODE_MSUBQ_S; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 76) + return OPCODE_MULQ_S; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 77) + return OPCODE_MULQ_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 0) + return OPCODE_MADDA_S; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 128) + return OPCODE_ADD_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 133) + return OPCODE_SUB_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 132) + return OPCODE_MUL_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 129) + return OPCODE_MADD_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 131) + return OPCODE_MSUB_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 130) + return OPCODE_MSUBN_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 96 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 2) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_get (insn) == 36) + return OPCODE_MULMUXQ_S; + if (Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_get (insn) == 40 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MULMUX_S; + if (Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_get (insn) == 8) + return OPCODE_MADDMUXQ_S; + if (Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 0) + return OPCODE_ADD_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_SUB_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 0) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 33) + return OPCODE_ADD_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 161) + return OPCODE_SUB_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 321) + return OPCODE_MIN_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 385) + return OPCODE_MAX_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_get (insn) == 386 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CLSFY_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 193) + return OPCODE_MINNUM_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 257) + return OPCODE_MAXNUM_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 9 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 8 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 449) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_FREXP_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_get (insn) == 386 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 33) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 65) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 129) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 1 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 7 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 5 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_get (insn) == 769 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 6 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 2 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_get (insn) == 768 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 4 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae9_slot2_33_9_Slot_ae9_slot2_get (insn) == 6316160 && + Field_fld_ae9_slot2_8_0_Slot_ae9_slot2_get (insn) == 65) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae9_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get (insn) == 28696) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get (insn) == 28697) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get (insn) == 29846 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CONST_H; + if (Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get (insn) == 29847 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CONST_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14347 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CLSFY_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14379 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_DIV0_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14411 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14443 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_MKSADJ_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14475 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_NEXP01_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14507 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_RECIP0_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14539 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_RSQRT0_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14571 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_SQRT0_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14603 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_ABS_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14635 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CONJC_H; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14667 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CONJC_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14699 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_MULJC_H; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14731 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_MULJC_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14763 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_NEG_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14795 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_ABS_H; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14827 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CLSFY_H; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14859 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_NEG_H; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14891 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_AE_MOV; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 576 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_DIVN_S; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 608 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MADDN_S; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 640 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MADD_S; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 672 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MSUBN_S; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 704 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MSUB_S; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 736 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MUL_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 10) + return OPCODE_MADDQ_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 11) + return OPCODE_MSUBQ_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 12) + return OPCODE_MULQ_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 13) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_4_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_AE_SEL16I; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 27) + return OPCODE_MIN_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 25) + return OPCODE_MAX_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 26) + return OPCODE_MINNUM_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 25) + return OPCODE_MAXNUM_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 9) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 8) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 24) + return OPCODE_FREXP_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 26) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 24) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_BMAXNUM_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get (insn) == 2) + return OPCODE_BMINNUM_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_BMAXNUMABS_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get (insn) == 2) + return OPCODE_BMINNUMABS_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 7) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 3) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 5) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_MIN_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 28) + return OPCODE_MAX_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 28) + return OPCODE_MINNUM_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 27) + return OPCODE_MAXNUM_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 6) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 2) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 4) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 5) + return OPCODE_ADD_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 6) + return OPCODE_SUB_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 226) + return OPCODE_MKDADJ_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 225) + return OPCODE_ADDEXP_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 224) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 4) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_MADDA_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 228) + return OPCODE_ADDEXP_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 227) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 64) + return OPCODE_ADD_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 98) + return OPCODE_SUB_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 66) + return OPCODE_MUL_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 96) + return OPCODE_MADD_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 97) + return OPCODE_MSUB_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 65) + return OPCODE_MSUBN_H; + if (Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_get (insn) == 4) + return OPCODE_MULMUXQ_S; + if (Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_get (insn) == 8 && + Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MULMUX_S; + if (Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_MADDMUXQ_S; + if (Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_get (insn) == 2 && + Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae9_slot3_31_7_Slot_ae9_slot3_get (insn) == 3828480 && + Field_fld_ae9_slot3_6_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4096) + return OPCODE_AE_EXPADD16_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4097) + return OPCODE_AE_EXPADD16_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4098) + return OPCODE_AE_EXPSUB16_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4099) + return OPCODE_AE_EXPSUB16_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4100) + return OPCODE_AE_ADD16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4101) + return OPCODE_AE_ADD16S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4102) + return OPCODE_AE_ADD24S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4103) + return OPCODE_AE_ADD32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4104) + return OPCODE_AE_ADD32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4105) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4106) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4107) + return OPCODE_AE_ADD64; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4108) + return OPCODE_AE_ADD64S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4109) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4110) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4111) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4112) + return OPCODE_AE_ADDSUB32S_HL_LH; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4113) + return OPCODE_AE_ADDSUB32_HL_LH; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4114) + return OPCODE_AE_MAX16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4115) + return OPCODE_AE_MAX32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4116) + return OPCODE_AE_MAX8; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4117) + return OPCODE_AE_MIN16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4118) + return OPCODE_AE_MIN32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4119) + return OPCODE_AE_MIN8; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4120) + return OPCODE_AE_MINMAX16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4121) + return OPCODE_AE_MINMAX32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4122) + return OPCODE_AE_MOVNEG32S_T; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4123) + return OPCODE_AE_ROUND16X4F32SASYM; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4124) + return OPCODE_AE_ROUND16X4F32SSYM; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4125) + return OPCODE_AE_ROUND32X2F64SASYM; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4126) + return OPCODE_AE_ROUND32X2F64SSYM; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4127) + return OPCODE_AE_SUB16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4128) + return OPCODE_AE_SUB16S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4129) + return OPCODE_AE_SUB24S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4130) + return OPCODE_AE_SUB32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4131) + return OPCODE_AE_SUB32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4132) + return OPCODE_AE_SUB64; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4133) + return OPCODE_AE_SUB64S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4134) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4135) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4136) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4137) + return OPCODE_ADD_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4138) + return OPCODE_DIVN_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4139) + return OPCODE_MADDN_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4140) + return OPCODE_MADD_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4141) + return OPCODE_MSUB_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4142) + return OPCODE_MUL_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4143) + return OPCODE_SUB_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5131 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5163 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SAT48S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5195 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5208 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5209 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG16S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5210 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG24S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5211 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5212 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5213 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG32_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5214 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG64; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5215 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG64S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5227 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ADDEXP_S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5233 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5234 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5235 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS64; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5237 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS16S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5238 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS64S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5239 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5241 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS24S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5242 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5243 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5245 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5246 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_DIV64D32_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5247 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5259 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MKDADJ_S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5291 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADD16X4; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5323 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADD8X8_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5355 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADD8X8_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5387 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADDA16X4; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5419 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADDA8X8_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5451 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADDA8X8_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5483 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RMAX16X4; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5515 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RMAX8X8; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5547 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RMIN16X4; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5579 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RMIN8X8; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5611 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ABS_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5643 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_CLSFY_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5675 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_NEG_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5707 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MKDADJ_H; + if (Field_fld_ae_slot2_28_17_Slot_ae_slot2_get (insn) == 1300 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ADD72X64; + if (Field_fld_ae_slot2_28_17_Slot_ae_slot2_get (insn) == 1301 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SUB72X64; + if (Field_fld_ae_slot2_28_17_Slot_ae_slot2_get (insn) == 1316 && + Field_fld_ae_slot2_14_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SEXT72; + if (Field_fld_ae_slot2_28_19_Slot_ae_slot2_get (insn) == 321 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ADD72; + if (Field_fld_ae_slot2_28_19_Slot_ae_slot2_get (insn) == 323 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SUB72; + if (Field_fld_ae_slot2_28_19_Slot_ae_slot2_get (insn) == 327 && + Field_fld_ae_slot2_16_15_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SAT64S; + if (Field_fld_ae_slot2_28_19_Slot_ae_slot2_get (insn) == 342 && + Field_fld_ae_slot2_14_0_Slot_ae_slot2_get (insn) == 1062) + return OPCODE_AE_MOVEEP; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 64) + return OPCODE_AE_MUL16X4; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 65) + return OPCODE_AE_MUL16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 66) + return OPCODE_AE_MULA16X4; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 67) + return OPCODE_AE_MULA16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 68) + return OPCODE_AE_MULAFC32RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 69) + return OPCODE_AE_MULAFC32X16W_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 70) + return OPCODE_AE_MULAFC32X16W_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 71) + return OPCODE_AE_MULAFP32X2S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 72) + return OPCODE_AE_MULAFP32X2S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 73) + return OPCODE_AE_MULFC32RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 74) + return OPCODE_AE_MULFC32X16W_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 75) + return OPCODE_AE_MULFC32X16W_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 76) + return OPCODE_AE_MULFP32X2S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 77) + return OPCODE_AE_MULFP32X2S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 78) + return OPCODE_AE_MULS16X4; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 79) + return OPCODE_AE_MULS16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 80) + return OPCODE_AE_MULSFP32X2S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 81) + return OPCODE_AE_MULSFP32X2S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 82) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 83) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 84) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 85) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 86) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 87) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 88) + return OPCODE_MADDA_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 89) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 90) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 91) + return OPCODE_AE_SEL8X8I; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 2) + return OPCODE_AE_MUL32EP_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 5) + return OPCODE_AE_MULA32EP_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 3) + return OPCODE_AE_MUL32USEP_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 6) + return OPCODE_AE_MULA32USEP_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 4) + return OPCODE_AE_MUL32USEP_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 7) + return OPCODE_AE_MULA32USEP_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_8_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 7) + return OPCODE_AE_SEL16I_N; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 2) + return OPCODE_AE_MULS32EP_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 4) + return OPCODE_AE_MULZAAD32EP_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 6) + return OPCODE_AE_MULZSSD32EP_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_MULAAD32EP_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 3) + return OPCODE_AE_MULSSD32EP_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 1) + return OPCODE_AE_MULAAD32USEP_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 5) + return OPCODE_AE_MULZAAD32USEP_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 8) + return OPCODE_AE_MUL32U_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULA32U_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 2) + return OPCODE_AE_MUL16S_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULA16S_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 10) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 3) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 4) + return OPCODE_AE_MUL32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULA32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 7) + return OPCODE_AE_MUL32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULA32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 5) + return OPCODE_AE_MUL32S_HL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULA32S_HL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 6) + return OPCODE_AE_MUL32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULA32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_6_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MULMUX_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULAC16JS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULAC16JS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 5) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 4) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 3) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 1) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 2) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 8) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_MULAAD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 10) + return OPCODE_AE_MULAAD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 6) + return OPCODE_AE_MULAA2D16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 7) + return OPCODE_AE_MULAA2D16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULAAFD16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULAAFD16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULSAD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULSAD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULSAD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULSAD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC16S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULSF32RA_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32RA_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32RA_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULSF16SS_33; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULSF16SS_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULSF16SS_32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULSF16SS_21; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULSF16SS_31; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULSF16SS_30; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULSF16SS_10; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULSF16SS_20; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULSF16SS_11; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC16S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAFC16RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAFCJ32RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAFCJ16RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULSFP32X2TS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULSP32X2T; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULSP16S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULSP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULSP16X16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC32X16_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULSSD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULSSD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULSS2D16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULSS2D16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULSSFD16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULSSFD16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAFP32X2TS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC32X16_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULZAAD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULZAAD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAP16S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULZAA2D16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULZAA2D16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULZASD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULZASD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULACJ32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAP16X16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULZAAFD16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULZAAFD16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULZSAD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULZSAD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAP32X2T; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULZSAD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULZSAD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_10; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULZSSD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULASD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULZSSD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULASD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULZSS2D16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULZSS2D16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULZSSFD16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULZSSFD16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_11; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_MUL_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_MADD_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_MSUB_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_MSUBN_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_MADDN_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_DIVN_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_MIN_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_MAX_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_MINNUM_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_MAXNUM_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 106 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_20; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 106 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 106 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 106 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 106 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 107 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULC16JS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 107 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULC16JS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 107 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_21; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 107 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 107 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 108 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 108 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULC32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 108 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULC16S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 108 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULC16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 108 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULC16S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 109 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 109 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_30; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 109 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULC32X16_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 109 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULC32X16_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 109 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULCJ32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 110 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF16SS_21; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 110 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF16SS_10; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 110 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF16SS_20; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 110 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF16SS_11; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 110 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_31; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 111 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF16SS_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 111 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF16SS_32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 111 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF16SS_31; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 111 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF16SS_30; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 111 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 112 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF32RA_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 112 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF32RA_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 112 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF32RA_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 112 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF16SS_33; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 112 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_33; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 113 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 113 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 113 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 113 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 113 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32RA_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 114 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 114 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 114 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32RA_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 114 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 114 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 115 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32RA_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 115 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 115 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 115 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 115 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 116 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 116 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 116 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 116 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 116 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 117 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 117 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 117 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 117 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 117 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFC16RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 118 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 118 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULFP16X4RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 118 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 118 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULFCJ32RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 118 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULFCJ16RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 119 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 119 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 119 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 119 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULFP16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 119 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFP16X4RS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 120 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 120 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 120 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 120 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 120 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 121 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 121 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 121 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 121 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 121 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 122 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 122 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFP32X2TS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 122 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULP16S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 122 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 122 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULP16X16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 123 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 123 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 123 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 123 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 123 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULP32X2T; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 124 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 124 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULS16S_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 124 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 124 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 124 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 125 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 125 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 125 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 125 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULS32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 125 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULS32S_HL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 126 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULS32U_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 126 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 126 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 126 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULS32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 126 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULS32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 127 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 127 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 127 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 127 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 127 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 130 && + Field_fld_ae_slot2_14_10_Slot_ae_slot2_get (insn) == 1) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 130 && + Field_fld_ae_slot2_14_10_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 160 && + Field_fld_ae_slot2_9_2_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_PKSR16; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 161 && + Field_fld_ae_slot2_9_2_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_PKSR24; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 162 && + Field_fld_ae_slot2_9_2_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_PKSR32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 163 && + Field_fld_ae_slot2_9_2_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 164 && + Field_fld_ae_slot2_9_1_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 164 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_ABS_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 164 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_CONJC_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 165 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_MKSADJ_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 165 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_DIV0_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 165 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_CONJC_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 165 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_MULJC_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 166 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_NEXP01_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 166 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_RECIP0_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 166 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_NEG_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 166 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_MULJC_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 167 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_SQRT0_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 167 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_RSQRT0_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 167 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_ADDEXP_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 167 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 168 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 168 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 168 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_AE_MOV; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 168 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_DIV0_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 169 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_MKSADJ_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 169 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_NEXP0_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 169 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_NEXP01_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 169 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_RECIP0_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 170 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 170 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 170 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_RSQRT0_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 170 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_SQRT0_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 171 && + Field_fld_ae_slot2_14_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_AE_MOVZBVCDR; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 171 && + Field_fld_ae_slot2_14_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_AE_MOVDRZBVC; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 171 && + Field_fld_ae_slot2_14_14_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_CONST_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 171 && + Field_fld_ae_slot2_14_14_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_CONST_H; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 1) + return OPCODE_AE_DSEL8X8; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 8) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 10) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 9) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 1) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 7) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 3) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 5) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 6) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 2) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 4) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 7 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SORT16X4; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 9 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ADD_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 10 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_SUB_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 6 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MIN_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MAX_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 33) + return OPCODE_CLSFY_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MINNUM_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 2 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MAXNUM_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 8 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_FREXP_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 1 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 33) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 4 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 1 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_14_14_Slot_ae_slot2_get (insn) == 1 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 32) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_14_14_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 32) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae_slot2_28_4_Slot_ae_slot2_get (insn) == 11206722 && + Field_fld_ae_slot2_3_0_Slot_ae_slot2_get (insn) == 7) + return OPCODE_NOP; + if (Field_fld_ae_slot2_28_5_Slot_ae_slot2_get (insn) == 5394432) + return OPCODE_AE_MOVFCRFSRV; + if (Field_fld_ae_slot2_28_5_Slot_ae_slot2_get (insn) == 5395456) + return OPCODE_AE_MOVVFCRFSR; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot3_36_12_Slot_ae_slot3_get (insn) == 15205414 && + Field_fld_ae_slot3_11_0_Slot_ae_slot3_get (insn) == 2146) + return OPCODE_NOP; + if (Field_fld_ae_slot3_36_16_Slot_ae_slot3_get (insn) == 934928 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot3_36_19_Slot_ae_slot3_get (insn) == 116864 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae_slot3_36_19_Slot_ae_slot3_get (insn) == 116868 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_CONST_H; + if (Field_fld_ae_slot3_36_19_Slot_ae_slot3_get (insn) == 116870 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_CONST_S; + if (Field_fld_ae_slot3_36_19_Slot_ae_slot3_get (insn) == 116928 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57632) + return OPCODE_AE_MUL16X4; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57633) + return OPCODE_AE_MUL16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57634) + return OPCODE_AE_MUL2C16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57635) + return OPCODE_AE_MUL32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57636) + return OPCODE_AE_MUL32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57637) + return OPCODE_AE_MULA16X4; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57638) + return OPCODE_AE_MULA16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57639) + return OPCODE_AE_MULA2C16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57640) + return OPCODE_AE_MULA32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57641) + return OPCODE_AE_MULA32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57642) + return OPCODE_AE_MULAA32X2_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57643) + return OPCODE_AE_MULAAAA2Q8; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57644) + return OPCODE_AE_MULAC16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57645) + return OPCODE_AE_MULAC16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57646) + return OPCODE_AE_MULAC32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57647) + return OPCODE_AE_MULAC32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57648) + return OPCODE_AE_MULAC32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57649) + return OPCODE_AE_MULACJ32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57650) + return OPCODE_AE_MULADDF32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57651) + return OPCODE_AE_MULADDF32RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57652) + return OPCODE_AE_MULAF16X4SS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57653) + return OPCODE_AE_MULAF32X2RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57654) + return OPCODE_AE_MULAF32X2RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57655) + return OPCODE_AE_MULAF32X2R_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57656) + return OPCODE_AE_MULAF32X2R_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57657) + return OPCODE_AE_MULAFC16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57658) + return OPCODE_AE_MULAFC32RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57659) + return OPCODE_AE_MULAFC32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57660) + return OPCODE_AE_MULAFC32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57661) + return OPCODE_AE_MULAFC32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57662) + return OPCODE_AE_MULAFCJ16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57663) + return OPCODE_AE_MULAFCJ32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57664) + return OPCODE_AE_MULAFCJ32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57665) + return OPCODE_AE_MULAFCJ32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57666) + return OPCODE_AE_MULAFP32X16_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57667) + return OPCODE_AE_MULAFP32X16_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57668) + return OPCODE_AE_MULC32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57669) + return OPCODE_AE_MULC32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57670) + return OPCODE_AE_MULC32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57671) + return OPCODE_AE_MULCJ32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57672) + return OPCODE_AE_MULF32X2R_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57673) + return OPCODE_AE_MULFC16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57674) + return OPCODE_AE_MULFC32RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57675) + return OPCODE_AE_MULFC32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57676) + return OPCODE_AE_MULFCJ32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57677) + return OPCODE_AE_MULFCJ32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57678) + return OPCODE_AE_MULFP32X16_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57679) + return OPCODE_AE_MULFP32X16_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57680) + return OPCODE_AE_MULS32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57681) + return OPCODE_AE_MULS32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57682) + return OPCODE_AE_MULSF16X4SS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57683) + return OPCODE_AE_MULSF32X2RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57684) + return OPCODE_AE_MULSFP32X16_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57685) + return OPCODE_AE_MULSFP32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57686) + return OPCODE_AE_MULSFP32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57687) + return OPCODE_AE_MULSS32X2_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57688) + return OPCODE_AE_MULZSS32X2_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULAC16JS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULAC16JS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULAAD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULAAD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULAA2D16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULAA2D16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULAAFD16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULAAFD16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULC16JS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULF32RA_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULF16SS_33; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULF16SS_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULF16SS_31; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULF16SS_10; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULF16SS_20; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULC16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULFC16RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULFCJ32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULCJ32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULC16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULC16JS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULF32RA_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULF32RA_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULF16SS_32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULF16SS_21; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULF16SS_30; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULF16SS_11; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULC32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULC16S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULFCJ16RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULFP16X4RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSS2D16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57693 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57693 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57693 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57693 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57693 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57694 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57694 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57694 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57694 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57694 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57695 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57695 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57695 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57695 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57695 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZSAD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57696) + return OPCODE_AE_MULAFP32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57697) + return OPCODE_AE_MULAFP32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57698) + return OPCODE_AE_MULC16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57699) + return OPCODE_AE_MULC16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57700) + return OPCODE_AE_MULF16X4SS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57701) + return OPCODE_AE_MULF32X2RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57702) + return OPCODE_AE_MULF32X2RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57703) + return OPCODE_AE_MULF32X2R_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57704) + return OPCODE_AE_MULFC32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57705) + return OPCODE_AE_MULFC32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57706) + return OPCODE_AE_MULFCJ16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57707) + return OPCODE_AE_MULFCJ32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57708) + return OPCODE_AE_MULFP32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57709) + return OPCODE_AE_MULFP32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57710) + return OPCODE_AE_MULS16X4; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57711) + return OPCODE_AE_MULS16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57712) + return OPCODE_AE_MULSF32X2RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57713) + return OPCODE_AE_MULSF32X2R_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57714) + return OPCODE_AE_MULSF32X2R_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57715) + return OPCODE_AE_MULSFP32X16_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57716) + return OPCODE_AE_MULSUBF32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57717) + return OPCODE_AE_MULSUBF32RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57718) + return OPCODE_AE_MULZAA32X2_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57719) + return OPCODE_AE_MULZAAAA2Q8; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULSF32RA_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULSF16SS_31; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULSF16SS_20; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULS32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULSAD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULP16S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULSP16S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULSS2D16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULZAAFD16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULSF32RA_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULSF16SS_32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULSF16SS_21; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULS16S_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULS32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULZAAD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULSSD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULSAD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULSP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULSS2D16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULZAAFD16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULSF16SS_33; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULSF16SS_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULSF16SS_10; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULSAD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULS32S_HL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULZAAD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULSSD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULP32X2S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULP16X16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULSP16X16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULZAA2D16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULSSFD16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULSF32RA_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULSF16SS_30; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULSF16SS_11; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULSAD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULS32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULZAA2D16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULSSFD16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57725 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57725 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57725 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57725 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57725 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57726 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57726 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57726 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57726 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57726 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57727 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57727 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57727 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57727 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZSAD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57727 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSS2D16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59532 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59533 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59534 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32S_HL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59535 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59536 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAC16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59537 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULACJ32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59538 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_20; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59539 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_31; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59540 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32RA_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59541 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59542 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59543 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59544 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59545 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59546 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFCJ32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59547 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59548 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59549 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59550 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59551 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59560 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL16S_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59561 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59562 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59563 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32S_HL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59564 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59565 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA16S_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59566 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59567 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59568 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAC16S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59569 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59570 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_21; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59571 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59572 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32RA_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59573 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59574 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59575 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59576 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59577 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59578 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59579 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59580 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59581 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP16X16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59582 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59583 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59592 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59593 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59594 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59595 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59596 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59597 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59598 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59599 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59600 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAC16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59601 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_10; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59602 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59603 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_33; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59604 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59605 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59606 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59607 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59608 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFC16RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59609 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59610 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59611 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59612 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59613 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59614 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59615 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULASD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59624 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59625 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59626 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59627 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59628 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59629 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59630 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59631 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59632 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAC32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59633 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_11; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59634 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_30; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59635 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32RA_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59636 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59637 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59638 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59639 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59640 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59641 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFCJ16RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59642 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59643 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59644 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP16S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59645 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59646 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59647 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULASD32S_HL_LH; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14849 && + Field_fld_ae_slot3_19_17_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26722) + return OPCODE_AE_MOVEEP; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14880 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32EP_HH; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14881 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULS32EP_HH; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14882 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSSD32EP_HH_LL; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14888 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32EP_HH; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14889 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULSSD32EP_HH_LL; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14896 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAAD32EP_HH_LL; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14897 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZAAD32EP_HH_LL; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14904 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAAD32USEP_HL_LH; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14905 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZAAD32USEP_HL_LH; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1760) + return OPCODE_AE_MULAAAA2Q16X8; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1761) + return OPCODE_AE_MULAF2P32X16X4RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1762) + return OPCODE_AE_MULAF2P32X16X4RS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1763) + return OPCODE_AE_MULAF2P32X16X4S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1764) + return OPCODE_AE_MULAFD32X16X2_FIR_HH; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1765) + return OPCODE_AE_MULAFD32X16X2_FIR_HL; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1766) + return OPCODE_AE_MULAFD32X16X2_FIR_LH; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1767) + return OPCODE_AE_MULAFD32X16X2_FIR_LL; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1768) + return OPCODE_AE_MULAFD32X2RA_FIR_H; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1769) + return OPCODE_AE_MULAFD32X2RA_FIR_L; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1770) + return OPCODE_AE_MULAFD32X2S_FIR_H; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1771) + return OPCODE_AE_MULAFD32X2S_FIR_L; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1772) + return OPCODE_AE_MULAFPC32X16X2RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1773) + return OPCODE_AE_MULAFPCJ32X16X2RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1774) + return OPCODE_AE_MULAFQ16X2_FIR_0; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1775) + return OPCODE_AE_MULAFQ16X2_FIR_1; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1776) + return OPCODE_AE_MULAFQ16X2_FIR_2; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1777) + return OPCODE_AE_MULAFQ16X2_FIR_3; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1778) + return OPCODE_AE_MULAPC32X16X2; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1779) + return OPCODE_AE_MULF2P32X16X4RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1780) + return OPCODE_AE_MULF2P32X16X4RS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1781) + return OPCODE_AE_MULF2P32X16X4S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1782) + return OPCODE_AE_MULFD32X16X2_FIR_HH; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1783) + return OPCODE_AE_MULFD32X16X2_FIR_HL; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1784) + return OPCODE_AE_MULFD32X16X2_FIR_LH; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1785) + return OPCODE_AE_MULFD32X16X2_FIR_LL; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1786) + return OPCODE_AE_MULFD32X2RA_FIR_H; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1787) + return OPCODE_AE_MULFD32X2RA_FIR_L; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1788) + return OPCODE_AE_MULFD32X2S_FIR_H; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1789) + return OPCODE_AE_MULFD32X2S_FIR_L; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1790) + return OPCODE_AE_MULFPC32X16X2RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1791) + return OPCODE_AE_MULFPCJ32X16X2RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1792) + return OPCODE_AE_MULFQ16X2_FIR_0; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1793) + return OPCODE_AE_MULFQ16X2_FIR_1; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1794) + return OPCODE_AE_MULFQ16X2_FIR_2; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1795) + return OPCODE_AE_MULFQ16X2_FIR_3; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1796) + return OPCODE_AE_MULPC32X16X2; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1797) + return OPCODE_AE_MULSF2P32X16X4RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1798) + return OPCODE_AE_MULSF2P32X16X4RS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1799) + return OPCODE_AE_MULSF2P32X16X4S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1800) + return OPCODE_AE_MULZAAAA2Q16X8; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 433250) + return OPCODE_AE_RNG32X2; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 24 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 29 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 26 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 30 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 31 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI32R; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 25 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI24S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 27 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI32S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLI64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (insn) == 13 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (insn) == 9 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAISQ56S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (insn) == 5 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI64S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_13_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI72; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 28 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI72; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLI24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 515 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 899 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLS24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 771 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAS24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_19_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI16; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_19_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI16R; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLI32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 579 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 931 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLS32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 803 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAS32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_19_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI16S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 547 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 611 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS32S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 707 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLASQ56; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 995 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLSQ56; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 867 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRASQ56; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 643 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 963 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLS64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 835 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAS64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 739 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLASSQ56S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 675 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS64S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1856 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAAAAFQ32X16; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1856 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 99) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1857 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAAAAQ32X16; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1857 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 99) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1858 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZAAAAFQ32X16; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1859 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZAAAAQ32X16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MUL2P32X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MUL2P32X4S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL2P32X4T; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MUL2Q32X16_FIR_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MUL2Q32X16_FIR_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULA2P32X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULA2P32X4T; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULA2Q32X16_FIR_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULA2Q32X16_FIR_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULAAAA2Q16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULAAAA2Q32X16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULAAF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULAAF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULAAF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULAAF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULAF2P32X4RAS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULAF2P32X4RS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULASF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULASF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULASF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULASF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULF2D32X2WS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULF2P32X4RAS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULF2P32X4RS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULFD16X16X4WS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULS2P32X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULS2P32X4T; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULSAF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULSAF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULSAF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULSAF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULSF2P32X4RAS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 32) + return OPCODE_AE_MULSF2P32X4RS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 33) + return OPCODE_AE_MULSSF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 34) + return OPCODE_AE_MULSSF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 35) + return OPCODE_AE_MULSSF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 36) + return OPCODE_AE_MULSSF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 37) + return OPCODE_AE_MULZAAAA2Q16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 38) + return OPCODE_AE_MULZAAAA2Q32X16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 39) + return OPCODE_AE_MULZAAF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 40) + return OPCODE_AE_MULZAAF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 41) + return OPCODE_AE_MULZAAF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 42) + return OPCODE_AE_MULZAAF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 43) + return OPCODE_AE_MULZASF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 44) + return OPCODE_AE_MULZASF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 45) + return OPCODE_AE_MULZASF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 46) + return OPCODE_AE_MULZASF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 47) + return OPCODE_AE_MULZSAF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 48) + return OPCODE_AE_MULZSAF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 49) + return OPCODE_AE_MULZSAF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 50) + return OPCODE_AE_MULZSAF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 51) + return OPCODE_AE_MULZSSF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 52) + return OPCODE_AE_MULZSSF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 53) + return OPCODE_AE_MULZSSF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 54) + return OPCODE_AE_MULZSSF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_19_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SEL16I; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1860 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SHORTSWAP; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1572 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1540 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1828 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1796 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 611 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_TRUNCP24Q48X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1892 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_TRUNCP16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1764 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MOV; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1732 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1700 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1668 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1636 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1604 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1924 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_TRUNCQ32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 515 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_AND; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 547 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_NAND; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 579 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_OR; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 643 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_XOR; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 431202) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 432226) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_19_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 4 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SEXT32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_DSEL8X8; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 13 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 34) + return OPCODE_ADD_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 13 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 66) + return OPCODE_SUB_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3588 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_NEXP01_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2564 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MKSADJ_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 428130) + return OPCODE_MKDADJ_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1988 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_DIV0_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2628 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_SQRT0_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2596 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_RECIP0_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3620 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_RSQRT0_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 427106) + return OPCODE_ADDEXP_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 426082) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 867 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MIN_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 771 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MAX_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3652 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ABS_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2724 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_NEG_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3684 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CONJC_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3716 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MULJC_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1956 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CLSFY_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 835 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MINNUM_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 739 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MAXNUM_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 9 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 12 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 13 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 675 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_FREXP_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2020 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 803 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 707 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_18_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_BMAXNUM_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_18_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_BMINNUM_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_18_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_BMAXNUMABS_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_18_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_BMINNUMABS_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 8 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3748 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ABS_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 430178) + return OPCODE_ADDEXP_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 429154) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2756 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CLSFY_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2660 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CONJC_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 995 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MIN_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 931 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MAX_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 963 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MINNUM_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 899 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MAXNUM_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2692 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MULJC_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3780 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_NEG_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 4 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 7 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 5 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 6 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 648290) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 38) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 37) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 39) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 40) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 41) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 30816) + return OPCODE_AE_ADDRNG32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 17506) + return OPCODE_AE_SUBRNG32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 31841) + return OPCODE_AE_SAT16X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 24673) + return OPCODE_AE_ROUND32X2F64SSYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 23649) + return OPCODE_AE_ROUND32X2F64SASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 22625) + return OPCODE_AE_ROUND32X2F48SSYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 21601) + return OPCODE_AE_ROUND32X2F48SASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 18529) + return OPCODE_AE_ROUND16X4F32SSYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 17505) + return OPCODE_AE_ROUND16X4F32SASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 20577) + return OPCODE_AE_ROUND24X2F48SSYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 19553) + return OPCODE_AE_ROUND24X2F48SASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 30817) + return OPCODE_AE_ROUNDSP16Q48X2SYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 29793) + return OPCODE_AE_ROUNDSP16Q48X2ASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 12385) + return OPCODE_AE_MINABS32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 7265) + return OPCODE_AE_MAXABS32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26722) + return OPCODE_AE_ROUNDSP16F24SYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26722) + return OPCODE_AE_ROUNDSP16F24ASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 1008738) + return OPCODE_AE_SAT48S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 1041506) + return OPCODE_AE_SATQ56S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 975970) + return OPCODE_AE_SAT24S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 13409) + return OPCODE_AE_MINABS64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 8289) + return OPCODE_AE_MAXABS64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26722) + return OPCODE_AE_ROUNDSQ32F48SYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26722) + return OPCODE_AE_ROUNDSQ32F48ASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 23648) + return OPCODE_AE_ADD32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 10338) + return OPCODE_AE_SUB32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 97) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 15458) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 20576) + return OPCODE_AE_ADD16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 7266) + return OPCODE_AE_SUB16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26720) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 3169) + return OPCODE_AE_ADDSUB32_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 746594) + return OPCODE_AE_NEG32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 255074) + return OPCODE_AE_ABS32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 812130) + return OPCODE_AE_NEG32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 22624) + return OPCODE_AE_ADD24S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 9314) + return OPCODE_AE_SUB24S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 24672) + return OPCODE_AE_ADD32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 11362) + return OPCODE_AE_SUB32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 1121) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 16482) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 21600) + return OPCODE_AE_ADD16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 8290) + return OPCODE_AE_SUB16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 25696) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 2145) + return OPCODE_AE_ADDSUB32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 713826) + return OPCODE_AE_NEG24S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 222306) + return OPCODE_AE_ABS24S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 779362) + return OPCODE_AE_NEG32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 287842) + return OPCODE_AE_ABS32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 681058) + return OPCODE_AE_NEG16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 189538) + return OPCODE_AE_ABS16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 156770) + return OPCODE_AE_ABS16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 10337) + return OPCODE_AE_MIN32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 5217) + return OPCODE_AE_MAX32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 15457) + return OPCODE_AE_MINMAX32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 14433) + return OPCODE_AE_MINMAX16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 9313) + return OPCODE_AE_MIN16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 4193) + return OPCODE_AE_MAX16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 27744) + return OPCODE_AE_ADD64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 12386) + return OPCODE_AE_SUB64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 844898) + return OPCODE_AE_NEG64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 320610) + return OPCODE_AE_ABS64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 31840) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 18530) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 28768) + return OPCODE_AE_ADD64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 13410) + return OPCODE_AE_SUB64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 943202) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 418914) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 877666) + return OPCODE_AE_NEG64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 353378) + return OPCODE_AE_ABS64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 6241) + return OPCODE_AE_MAX64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 11361) + return OPCODE_AE_MIN64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 615522) + return OPCODE_AE_MUL16JS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 517218) + return OPCODE_AE_CONJ16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 549986) + return OPCODE_AE_DIV64D32_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 582754) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_17_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 25698) + return OPCODE_AE_SAT64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 386146) + return OPCODE_AE_ABS8S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 910434) + return OPCODE_AE_NEG8S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 29792) + return OPCODE_AE_ADD8S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 14434) + return OPCODE_AE_SUB8S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 3170) + return OPCODE_AE_SATU16X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 98) + return OPCODE_AE_SAT32X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 4194) + return OPCODE_AE_SATU32X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 2146) + return OPCODE_AE_SAT8X8X16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 6242) + return OPCODE_AE_SATU8X8X16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 1122) + return OPCODE_AE_SAT8X4X32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 5218) + return OPCODE_AE_SATU8X4X32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 28769) + return OPCODE_AE_ROUND8X8F16SSYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 27745) + return OPCODE_AE_ROUND8X8F16SASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26721) + return OPCODE_AE_ROUND8X4F32SSYM_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 25697) + return OPCODE_AE_ROUND8X4F32SASYM_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 36) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 46) + return OPCODE_AE_ADDW8; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 44) + return OPCODE_AE_ADDW16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 45) + return OPCODE_AE_ADDW32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 50) + return OPCODE_AE_SUBW8; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 48) + return OPCODE_AE_SUBW16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 49) + return OPCODE_AE_SUBW32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 34) + return OPCODE_AE_ACCW8; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 32) + return OPCODE_AE_ACCW16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 33) + return OPCODE_AE_ACCW32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 47) + return OPCODE_AE_ADDW8U; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 51) + return OPCODE_AE_SUBW8U; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 35) + return OPCODE_AE_ACCW8U; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULFD16X16X4RAS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 54) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 53) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 55) + return OPCODE_AE_SEL8X8I; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_12_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 96) + return OPCODE_AE_BMAX8X8_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_12_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 96) + return OPCODE_AE_BMAX8X8_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_12_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 96) + return OPCODE_AE_BMIN8X8_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_12_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 96) + return OPCODE_AE_BMIN8X8_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 451682) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 484450) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 16481) + return OPCODE_AE_MOVNEG32S_T; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 16480) + return OPCODE_AE_EXPADD16_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 18528) + return OPCODE_AE_EXPSUB16_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 17504) + return OPCODE_AE_EXPADD16_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 19552) + return OPCODE_AE_EXPSUB16_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 42) + return OPCODE_AE_ADDCEXP32_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 43) + return OPCODE_AE_ADDCEXP32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 63) + return OPCODE_MUL_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 60) + return OPCODE_MADD_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 62) + return OPCODE_MSUB_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 61) + return OPCODE_MSUBN_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 59) + return OPCODE_MADDN_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 58) + return OPCODE_DIVN_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_1_Slot_ae_slot3_get (insn) == 28) + return OPCODE_MULMUX_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_9_3_Slot_ae_slot3_get (insn) == 7) + return OPCODE_MADDMUX_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 52) + return OPCODE_MADDA_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 19554) + return OPCODE_ADD_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 24674) + return OPCODE_SUB_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 23650) + return OPCODE_MUL_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 20578) + return OPCODE_MADD_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 22626) + return OPCODE_MSUB_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 21602) + return OPCODE_MSUBN_H; + return XTENSA_UNDEFINED; +} + + +/* Instruction slots. */ + +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = (insn[0] & 0xffffff); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_ae_format_Format_ae_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x300) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xc) | (((insn[0] & 0x18000000) >> 27) << 2); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf0) >> 4) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf000) >> 12) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | ((insn[1] & 0x1) << 12); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[0] & 0xc00) >> 10) << 13); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[1] & 0x6) >> 1) << 15); + slotbuf[0] = (slotbuf[0] & ~0x20000) | (((insn[2] & 0x1000000) >> 24) << 17); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x10000) >> 16) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[1] & 0x800000) >> 23) << 19); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[0] & 0x4000000) >> 26) << 20); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[1] & 0x1000000) >> 24) << 21); + slotbuf[0] = (slotbuf[0] & ~0xc00000) | (((insn[2] & 0x6000000) >> 25) << 22); + slotbuf[0] = (slotbuf[0] & ~0x7000000) | (((insn[2] & 0xe00000) >> 21) << 24); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x2000) >> 13) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x10000000) >> 28) << 28); +} + +static void +Slot_ae_format_Format_ae_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x300) | ((slotbuf[0] & 0x3) << 8); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0xc) >> 2) << 27); + insn[0] = (insn[0] & ~0xf0) | (((slotbuf[0] & 0xf0) >> 4) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0xf00) >> 8) << 12); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x1000) >> 12); + insn[0] = (insn[0] & ~0xc00) | (((slotbuf[0] & 0x6000) >> 13) << 10); + insn[1] = (insn[1] & ~0x6) | (((slotbuf[0] & 0x18000) >> 15) << 1); + insn[2] = (insn[2] & ~0x1000000) | (((slotbuf[0] & 0x20000) >> 17) << 24); + insn[2] = (insn[2] & ~0x10000) | (((slotbuf[0] & 0x40000) >> 18) << 16); + insn[1] = (insn[1] & ~0x800000) | (((slotbuf[0] & 0x80000) >> 19) << 23); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x100000) >> 20) << 26); + insn[1] = (insn[1] & ~0x1000000) | (((slotbuf[0] & 0x200000) >> 21) << 24); + insn[2] = (insn[2] & ~0x6000000) | (((slotbuf[0] & 0xc00000) >> 22) << 25); + insn[2] = (insn[2] & ~0xe00000) | (((slotbuf[0] & 0x7000000) >> 24) << 21); + insn[3] = (insn[3] & ~0x2000) | (((slotbuf[0] & 0x8000000) >> 27) << 13); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[0] & 0x10000000) >> 28) << 28); +} + +static void +Slot_ae_format_Format_ae_slot1_72_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[2] & 0xf8000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[2] & 0x60000) >> 17) << 18); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[3] & 0x7c000) >> 14) << 20); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x20000000) >> 29) << 25); +} + +static void +Slot_ae_format_Format_ae_slot1_72_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x1f00) >> 8) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[2] = (insn[2] & ~0x60000) | (((slotbuf[0] & 0xc0000) >> 18) << 17); + insn[3] = (insn[3] & ~0x7c000) | (((slotbuf[0] & 0x1f00000) >> 20) << 14); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x2000000) >> 25) << 29); +} + +static void +Slot_ae_format_Format_ae_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x1ff8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0xffc00) | (((insn[0] & 0x3ff0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[3] & 0x3e0) >> 5) << 20); + slotbuf[0] = (slotbuf[0] & ~0xe000000) | (((insn[3] & 0x380000) >> 19) << 25); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x40000000) >> 30) << 28); +} + +static void +Slot_ae_format_Format_ae_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x1ff8) | ((slotbuf[0] & 0x3ff) << 3); + insn[0] = (insn[0] & ~0x3ff0000) | (((slotbuf[0] & 0xffc00) >> 10) << 16); + insn[3] = (insn[3] & ~0x3e0) | (((slotbuf[0] & 0x1f00000) >> 20) << 5); + insn[3] = (insn[3] & ~0x380000) | (((slotbuf[0] & 0xe000000) >> 25) << 19); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x10000000) >> 28) << 30); +} + +static void +Slot_ae_format_Format_ae_slot3_45_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xfe000000) >> 25); + slotbuf[0] = (slotbuf[0] & ~0x7f80) | ((insn[2] & 0xff) << 7); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x180000) >> 19) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[3] & 0x1c00) >> 10) << 17); + slotbuf[0] = (slotbuf[0] & ~0x3ff00000) | (((insn[1] & 0x7fe000) >> 13) << 20); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0xc00000) >> 22) << 30); + slotbuf[1] = ((insn[3] & 0xf000000) >> 24); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x80000000) >> 31) << 4); +} + +static void +Slot_ae_format_Format_ae_slot3_45_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xfe000000) | ((slotbuf[0] & 0x7f) << 25); + insn[2] = (insn[2] & ~0xff) | ((slotbuf[0] & 0x7f80) >> 7); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x18000) >> 15) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0xe0000) >> 17) << 10); + insn[1] = (insn[1] & ~0x7fe000) | (((slotbuf[0] & 0x3ff00000) >> 20) << 13); + insn[3] = (insn[3] & ~0xc00000) | (((slotbuf[0] & 0xc0000000) >> 30) << 22); + insn[3] = (insn[3] & ~0xf000000) | ((slotbuf[1] & 0xf) << 24); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x10) >> 4) << 31); +} + +static void +Slot_ae_format_2_Format_ae2_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xff0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[0] & 0x18000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1c00) | ((insn[1] & 0x7) << 10); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x1000000) >> 24) << 13); + slotbuf[0] = (slotbuf[0] & ~0x1c000) | (((insn[0] & 0xe000) >> 13) << 14); + slotbuf[0] = (slotbuf[0] & ~0x20000) | (((insn[0] & 0x4000000) >> 26) << 17); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x800000) >> 23) << 18); + slotbuf[0] = (slotbuf[0] & ~0x180000) | (((insn[2] & 0x30000) >> 16) << 19); + slotbuf[0] = (slotbuf[0] & ~0xe00000) | (((insn[2] & 0x7000000) >> 24) << 21); + slotbuf[0] = (slotbuf[0] & ~0x7000000) | (((insn[1] & 0xe00000) >> 21) << 24); + slotbuf[0] = (slotbuf[0] & ~0x18000000) | (((insn[1] & 0x6000000) >> 25) << 27); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[2] & 0x100) >> 8) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[2] & 0x200) >> 9) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[2] & 0x400) >> 10) << 31); + slotbuf[1] = ((insn[2] & 0x800) >> 11); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[2] & 0x1000) >> 12) << 1); + slotbuf[1] = (slotbuf[1] & ~0x4) | (((insn[2] & 0x2000) >> 13) << 2); + slotbuf[1] = (slotbuf[1] & ~0x8) | (((insn[2] & 0x4000) >> 14) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[2] & 0x8000) >> 15) << 4); + slotbuf[1] = (slotbuf[1] & ~0x20) | (((insn[2] & 0x40000) >> 18) << 5); + slotbuf[1] = (slotbuf[1] & ~0x40) | (((insn[2] & 0x80000) >> 19) << 6); + slotbuf[1] = (slotbuf[1] & ~0x80) | (((insn[2] & 0x100000) >> 20) << 7); + slotbuf[1] = (slotbuf[1] & ~0x100) | (((insn[2] & 0x200000) >> 21) << 8); +} + +static void +Slot_ae_format_2_Format_ae2_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff0) | ((slotbuf[0] & 0xff) << 4); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x300) >> 8) << 27); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x1c00) >> 10); + insn[1] = (insn[1] & ~0x1000000) | (((slotbuf[0] & 0x2000) >> 13) << 24); + insn[0] = (insn[0] & ~0xe000) | (((slotbuf[0] & 0x1c000) >> 14) << 13); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x20000) >> 17) << 26); + insn[2] = (insn[2] & ~0x800000) | (((slotbuf[0] & 0x40000) >> 18) << 23); + insn[2] = (insn[2] & ~0x30000) | (((slotbuf[0] & 0x180000) >> 19) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0xe00000) >> 21) << 24); + insn[1] = (insn[1] & ~0xe00000) | (((slotbuf[0] & 0x7000000) >> 24) << 21); + insn[1] = (insn[1] & ~0x6000000) | (((slotbuf[0] & 0x18000000) >> 27) << 25); + insn[2] = (insn[2] & ~0x100) | (((slotbuf[0] & 0x20000000) >> 29) << 8); + insn[2] = (insn[2] & ~0x200) | (((slotbuf[0] & 0x40000000) >> 30) << 9); + insn[2] = (insn[2] & ~0x400) | (((slotbuf[0] & 0x80000000) >> 31) << 10); + insn[2] = (insn[2] & ~0x800) | ((slotbuf[1] & 0x1) << 11); + insn[2] = (insn[2] & ~0x1000) | (((slotbuf[1] & 0x2) >> 1) << 12); + insn[2] = (insn[2] & ~0x2000) | (((slotbuf[1] & 0x4) >> 2) << 13); + insn[2] = (insn[2] & ~0x4000) | (((slotbuf[1] & 0x8) >> 3) << 14); + insn[2] = (insn[2] & ~0x8000) | (((slotbuf[1] & 0x10) >> 4) << 15); + insn[2] = (insn[2] & ~0x40000) | (((slotbuf[1] & 0x20) >> 5) << 18); + insn[2] = (insn[2] & ~0x80000) | (((slotbuf[1] & 0x40) >> 6) << 19); + insn[2] = (insn[2] & ~0x100000) | (((slotbuf[1] & 0x80) >> 7) << 20); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[1] & 0x100) >> 8) << 21); +} + +static void +Slot_ae_format_2_Format_ae2_slot1_12_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x40000000) >> 30); + slotbuf[0] = (slotbuf[0] & ~0x2) | (((insn[1] & 0x20000000) >> 29) << 1); + slotbuf[0] = (slotbuf[0] & ~0xc) | (((insn[2] & 0x18000000) >> 27) << 2); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[1] & 0x80000000) >> 31) << 4); + slotbuf[0] = (slotbuf[0] & ~0xe0) | ((insn[2] & 0x7) << 5); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[2] & 0x60000000) >> 29) << 8); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | ((insn[3] & 0x1f) << 10); + slotbuf[0] = (slotbuf[0] & ~0x8000) | (((insn[0] & 0x1000) >> 12) << 15); + slotbuf[0] = (slotbuf[0] & ~0x70000) | (((insn[1] & 0xe000) >> 13) << 16); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[2] & 0x80000000) >> 31) << 19); + slotbuf[0] = (slotbuf[0] & ~0x300000) | (((insn[1] & 0x18000000) >> 27) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1c00000) | (((insn[2] & 0x38) >> 3) << 22); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[2] & 0x400000) >> 22) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x400) >> 10) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x800) >> 11) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x1000) >> 12) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x2000) >> 13) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x4000) >> 14) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x8000) >> 15) << 31); + slotbuf[1] = ((insn[3] & 0x10000) >> 16); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[3] & 0x20000) >> 17) << 1); + slotbuf[1] = (slotbuf[1] & ~0x4) | (((insn[3] & 0x40000) >> 18) << 2); + slotbuf[1] = (slotbuf[1] & ~0x8) | (((insn[3] & 0x80000) >> 19) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x100000) >> 20) << 4); +} + +static void +Slot_ae_format_2_Format_ae2_slot1_12_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x40000000) | ((slotbuf[0] & 0x1) << 30); + insn[1] = (insn[1] & ~0x20000000) | (((slotbuf[0] & 0x2) >> 1) << 29); + insn[2] = (insn[2] & ~0x18000000) | (((slotbuf[0] & 0xc) >> 2) << 27); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x10) >> 4) << 31); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0xe0) >> 5); + insn[2] = (insn[2] & ~0x60000000) | (((slotbuf[0] & 0x300) >> 8) << 29); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x7c00) >> 10); + insn[0] = (insn[0] & ~0x1000) | (((slotbuf[0] & 0x8000) >> 15) << 12); + insn[1] = (insn[1] & ~0xe000) | (((slotbuf[0] & 0x70000) >> 16) << 13); + insn[2] = (insn[2] & ~0x80000000) | (((slotbuf[0] & 0x80000) >> 19) << 31); + insn[1] = (insn[1] & ~0x18000000) | (((slotbuf[0] & 0x300000) >> 20) << 27); + insn[2] = (insn[2] & ~0x38) | (((slotbuf[0] & 0x1c00000) >> 22) << 3); + insn[2] = (insn[2] & ~0x400000) | (((slotbuf[0] & 0x2000000) >> 25) << 22); + insn[3] = (insn[3] & ~0x400) | (((slotbuf[0] & 0x4000000) >> 26) << 10); + insn[3] = (insn[3] & ~0x800) | (((slotbuf[0] & 0x8000000) >> 27) << 11); + insn[3] = (insn[3] & ~0x1000) | (((slotbuf[0] & 0x10000000) >> 28) << 12); + insn[3] = (insn[3] & ~0x2000) | (((slotbuf[0] & 0x20000000) >> 29) << 13); + insn[3] = (insn[3] & ~0x4000) | (((slotbuf[0] & 0x40000000) >> 30) << 14); + insn[3] = (insn[3] & ~0x8000) | (((slotbuf[0] & 0x80000000) >> 31) << 15); + insn[3] = (insn[3] & ~0x10000) | ((slotbuf[1] & 0x1) << 16); + insn[3] = (insn[3] & ~0x20000) | (((slotbuf[1] & 0x2) >> 1) << 17); + insn[3] = (insn[3] & ~0x40000) | (((slotbuf[1] & 0x4) >> 2) << 18); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[1] & 0x8) >> 3) << 19); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[1] & 0x10) >> 4) << 20); +} + +static void +Slot_ae_format_2_Format_ae2_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xf8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0x3e0) | (((insn[0] & 0x1f0000) >> 16) << 5); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[1] & 0x1f00) >> 8) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[3] & 0x3e0) >> 5) << 15); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[0] & 0x3e00000) >> 21) << 20); + slotbuf[0] = (slotbuf[0] & ~0x3e000000) | (((insn[1] & 0x1f0000) >> 16) << 25); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[2] & 0xc0) >> 6) << 30); + slotbuf[1] = ((insn[3] & 0x200000) >> 21); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[3] & 0x400000) >> 22) << 1); + slotbuf[1] = (slotbuf[1] & ~0x4) | (((insn[3] & 0x800000) >> 23) << 2); + slotbuf[1] = (slotbuf[1] & ~0x8) | (((insn[3] & 0x1000000) >> 24) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x2000000) >> 25) << 4); + slotbuf[1] = (slotbuf[1] & ~0x20) | (((insn[3] & 0x4000000) >> 26) << 5); + slotbuf[1] = (slotbuf[1] & ~0x40) | (((insn[3] & 0x8000000) >> 27) << 6); + slotbuf[1] = (slotbuf[1] & ~0x80) | (((insn[3] & 0x10000000) >> 28) << 7); + slotbuf[1] = (slotbuf[1] & ~0x100) | (((insn[3] & 0x20000000) >> 29) << 8); + slotbuf[1] = (slotbuf[1] & ~0x200) | (((insn[3] & 0x40000000) >> 30) << 9); + slotbuf[1] = (slotbuf[1] & ~0x400) | (((insn[3] & 0x80000000) >> 31) << 10); +} + +static void +Slot_ae_format_2_Format_ae2_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xf8) | ((slotbuf[0] & 0x1f) << 3); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0x3e0) >> 5) << 16); + insn[1] = (insn[1] & ~0x1f00) | (((slotbuf[0] & 0x7c00) >> 10) << 8); + insn[3] = (insn[3] & ~0x3e0) | (((slotbuf[0] & 0xf8000) >> 15) << 5); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x1f00000) >> 20) << 21); + insn[1] = (insn[1] & ~0x1f0000) | (((slotbuf[0] & 0x3e000000) >> 25) << 16); + insn[2] = (insn[2] & ~0xc0) | (((slotbuf[0] & 0xc0000000) >> 30) << 6); + insn[3] = (insn[3] & ~0x200000) | ((slotbuf[1] & 0x1) << 21); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[1] & 0x2) >> 1) << 22); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[1] & 0x4) >> 2) << 23); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[1] & 0x8) >> 3) << 24); + insn[3] = (insn[3] & ~0x2000000) | (((slotbuf[1] & 0x10) >> 4) << 25); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[1] & 0x20) >> 5) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[1] & 0x40) >> 6) << 27); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[1] & 0x80) >> 7) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[1] & 0x100) >> 8) << 29); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[1] & 0x200) >> 9) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x400) >> 10) << 31); +} + +static void +Slot_ae_format_3_Format_ae3_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xf00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf0) >> 4) << 4); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[0] & 0x18000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1c00) | ((insn[1] & 0x7) << 10); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x1000000) >> 24) << 13); + slotbuf[0] = (slotbuf[0] & ~0x1c000) | (((insn[0] & 0xe000) >> 13) << 14); + slotbuf[0] = (slotbuf[0] & ~0x20000) | (((insn[0] & 0x4000000) >> 26) << 17); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[1] & 0x6000) >> 13) << 18); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[0] & 0x3e00000) >> 21) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1e000000) | (((insn[1] & 0x78) >> 3) << 25); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[1] & 0x80000) >> 19) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[1] & 0x100000) >> 20) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[1] & 0x200000) >> 21) << 31); + slotbuf[1] = ((insn[1] & 0x400000) >> 22); +} + +static void +Slot_ae_format_3_Format_ae3_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf00) | ((slotbuf[0] & 0xf) << 8); + insn[0] = (insn[0] & ~0xf0) | (((slotbuf[0] & 0xf0) >> 4) << 4); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x300) >> 8) << 27); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x1c00) >> 10); + insn[1] = (insn[1] & ~0x1000000) | (((slotbuf[0] & 0x2000) >> 13) << 24); + insn[0] = (insn[0] & ~0xe000) | (((slotbuf[0] & 0x1c000) >> 14) << 13); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x20000) >> 17) << 26); + insn[1] = (insn[1] & ~0x6000) | (((slotbuf[0] & 0xc0000) >> 18) << 13); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x1f00000) >> 20) << 21); + insn[1] = (insn[1] & ~0x78) | (((slotbuf[0] & 0x1e000000) >> 25) << 3); + insn[1] = (insn[1] & ~0x80000) | (((slotbuf[0] & 0x20000000) >> 29) << 19); + insn[1] = (insn[1] & ~0x100000) | (((slotbuf[0] & 0x40000000) >> 30) << 20); + insn[1] = (insn[1] & ~0x200000) | (((slotbuf[0] & 0x80000000) >> 31) << 21); + insn[1] = (insn[1] & ~0x400000) | ((slotbuf[1] & 0x1) << 22); +} + +static void +Slot_ae_format_3_Format_ae3_slot1_12_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x1000) >> 12); + slotbuf[0] = (slotbuf[0] & ~0xe) | (((insn[1] & 0xe000000) >> 25) << 1); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[1] & 0xf00) >> 8) << 4); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[1] & 0x30000000) >> 28) << 8); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x1f0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x8000) | (((insn[1] & 0x80) >> 7) << 15); + slotbuf[0] = (slotbuf[0] & ~0x10000) | (((insn[1] & 0x1000) >> 12) << 16); + slotbuf[0] = (slotbuf[0] & ~0x1e0000) | (((insn[1] & 0x78000) >> 15) << 17); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[1] & 0x800000) >> 23) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[1] & 0x40000000) >> 30) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[1] & 0x80000000) >> 31) << 23); +} + +static void +Slot_ae_format_3_Format_ae3_slot1_12_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x1000) | ((slotbuf[0] & 0x1) << 12); + insn[1] = (insn[1] & ~0xe000000) | (((slotbuf[0] & 0xe) >> 1) << 25); + insn[1] = (insn[1] & ~0xf00) | (((slotbuf[0] & 0xf0) >> 4) << 8); + insn[1] = (insn[1] & ~0x30000000) | (((slotbuf[0] & 0x300) >> 8) << 28); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0x7c00) >> 10) << 16); + insn[1] = (insn[1] & ~0x80) | (((slotbuf[0] & 0x8000) >> 15) << 7); + insn[1] = (insn[1] & ~0x1000) | (((slotbuf[0] & 0x10000) >> 16) << 12); + insn[1] = (insn[1] & ~0x78000) | (((slotbuf[0] & 0x1e0000) >> 17) << 15); + insn[1] = (insn[1] & ~0x800000) | (((slotbuf[0] & 0x200000) >> 21) << 23); + insn[1] = (insn[1] & ~0x40000000) | (((slotbuf[0] & 0x400000) >> 22) << 30); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x800000) >> 23) << 31); +} + +static void +Slot_ae_format_5_Format_ae5_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xf00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf0) >> 4) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf000) >> 12) << 8); + slotbuf[0] = (slotbuf[0] & ~0x7000) | (((insn[0] & 0x1c000000) >> 26) << 12); + slotbuf[0] = (slotbuf[0] & ~0x38000) | ((insn[1] & 0x7) << 15); + slotbuf[0] = (slotbuf[0] & ~0x1ffc0000) | (((insn[1] & 0xffe000) >> 13) << 18); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[1] & 0x40000000) >> 30) << 29); +} + +static void +Slot_ae_format_5_Format_ae5_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf00) | ((slotbuf[0] & 0xf) << 8); + insn[0] = (insn[0] & ~0xf0) | (((slotbuf[0] & 0xf0) >> 4) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0xf00) >> 8) << 12); + insn[0] = (insn[0] & ~0x1c000000) | (((slotbuf[0] & 0x7000) >> 12) << 26); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x38000) >> 15); + insn[1] = (insn[1] & ~0xffe000) | (((slotbuf[0] & 0x1ffc0000) >> 18) << 13); + insn[1] = (insn[1] & ~0x40000000) | (((slotbuf[0] & 0x20000000) >> 29) << 30); +} + +static void +Slot_ae_format_5_Format_ae5_slot1_56_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x1000000) >> 24); + slotbuf[0] = (slotbuf[0] & ~0x2) | (((insn[1] & 0x80000000) >> 31) << 1); +} + +static void +Slot_ae_format_5_Format_ae5_slot1_56_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x1000000) | ((slotbuf[0] & 0x1) << 24); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x2) >> 1) << 31); +} + +static void +Slot_ae_format_5_Format_ae5_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x1ff8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0xffc00) | (((insn[0] & 0x3ff0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[1] & 0x3e000000) >> 25) << 20); +} + +static void +Slot_ae_format_5_Format_ae5_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x1ff8) | ((slotbuf[0] & 0x3ff) << 3); + insn[0] = (insn[0] & ~0x3ff0000) | (((slotbuf[0] & 0xffc00) >> 10) << 16); + insn[1] = (insn[1] & ~0x3e000000) | (((slotbuf[0] & 0x1f00000) >> 20) << 25); +} + +static void +Slot_ae_format_6_Format_ae6_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xf0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[2] & 0x800000) >> 23) << 4); + slotbuf[0] = (slotbuf[0] & ~0x60) | (((insn[0] & 0x18000000) >> 27) << 5); + slotbuf[0] = (slotbuf[0] & ~0x380) | ((insn[1] & 0x7) << 7); + slotbuf[0] = (slotbuf[0] & ~0x3c00) | (((insn[0] & 0xf000) >> 12) << 10); + slotbuf[0] = (slotbuf[0] & ~0x4000) | (((insn[0] & 0x4000000) >> 26) << 14); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x30000) >> 16) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[2] & 0x7000000) >> 24) << 17); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[1] & 0x1000) >> 12) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1e00000) | (((insn[2] & 0xf00) >> 8) << 21); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x8000) >> 15) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x10000) >> 16) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x20000) >> 17) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x40000) >> 18) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x80000) >> 19) << 29); +} + +static void +Slot_ae_format_6_Format_ae6_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0) | ((slotbuf[0] & 0xf) << 4); + insn[2] = (insn[2] & ~0x800000) | (((slotbuf[0] & 0x10) >> 4) << 23); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x60) >> 5) << 27); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x380) >> 7); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0x3c00) >> 10) << 12); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x4000) >> 14) << 26); + insn[2] = (insn[2] & ~0x30000) | (((slotbuf[0] & 0x18000) >> 15) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0xe0000) >> 17) << 24); + insn[1] = (insn[1] & ~0x1000) | (((slotbuf[0] & 0x100000) >> 20) << 12); + insn[2] = (insn[2] & ~0xf00) | (((slotbuf[0] & 0x1e00000) >> 21) << 8); + insn[3] = (insn[3] & ~0x8000) | (((slotbuf[0] & 0x2000000) >> 25) << 15); + insn[3] = (insn[3] & ~0x10000) | (((slotbuf[0] & 0x4000000) >> 26) << 16); + insn[3] = (insn[3] & ~0x20000) | (((slotbuf[0] & 0x8000000) >> 27) << 17); + insn[3] = (insn[3] & ~0x40000) | (((slotbuf[0] & 0x10000000) >> 28) << 18); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[0] & 0x20000000) >> 29) << 19); +} + +static void +Slot_ae_format_6_Format_ae6_slot1_57_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xc0000000) >> 30); + slotbuf[0] = (slotbuf[0] & ~0x1c) | ((insn[2] & 0x7) << 2); + slotbuf[0] = (slotbuf[0] & ~0x3e0) | (((insn[1] & 0x3e000000) >> 25) << 5); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[2] & 0xf8000000) >> 27) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | ((insn[3] & 0x1f) << 15); + slotbuf[0] = (slotbuf[0] & ~0xf00000) | (((insn[2] & 0xf000) >> 12) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x100000) >> 20) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x200000) >> 21) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x400000) >> 22) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x800000) >> 23) << 27); +} + +static void +Slot_ae_format_6_Format_ae6_slot1_57_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xc0000000) | ((slotbuf[0] & 0x3) << 30); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0x1c) >> 2); + insn[1] = (insn[1] & ~0x3e000000) | (((slotbuf[0] & 0x3e0) >> 5) << 25); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x7c00) >> 10) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0xf8000) >> 15); + insn[2] = (insn[2] & ~0xf000) | (((slotbuf[0] & 0xf00000) >> 20) << 12); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[0] & 0x1000000) >> 24) << 20); + insn[3] = (insn[3] & ~0x200000) | (((slotbuf[0] & 0x2000000) >> 25) << 21); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[0] & 0x4000000) >> 26) << 22); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[0] & 0x8000000) >> 27) << 23); +} + +static void +Slot_ae_format_6_Format_ae6_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xf8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0x7fe0) | (((insn[0] & 0x3ff0000) >> 16) << 5); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[3] & 0x3e0) >> 5) << 15); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[2] & 0x40000) >> 18) << 20); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x1000000) >> 24) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x2000000) >> 25) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x4000000) >> 26) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x8000000) >> 27) << 24); +} + +static void +Slot_ae_format_6_Format_ae6_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xf8) | ((slotbuf[0] & 0x1f) << 3); + insn[0] = (insn[0] & ~0x3ff0000) | (((slotbuf[0] & 0x7fe0) >> 5) << 16); + insn[3] = (insn[3] & ~0x3e0) | (((slotbuf[0] & 0xf8000) >> 15) << 5); + insn[2] = (insn[2] & ~0x40000) | (((slotbuf[0] & 0x100000) >> 20) << 18); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x200000) >> 21) << 24); + insn[3] = (insn[3] & ~0x2000000) | (((slotbuf[0] & 0x400000) >> 22) << 25); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x800000) >> 23) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x1000000) >> 24) << 27); +} + +static void +Slot_ae_format_6_Format_ae6_slot3_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x3e000) >> 13); + slotbuf[0] = (slotbuf[0] & ~0x60) | (((insn[2] & 0x180000) >> 19) << 5); + slotbuf[0] = (slotbuf[0] & ~0x380) | (((insn[3] & 0x1c00) >> 10) << 7); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[2] & 0xf8) >> 3) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[1] & 0x7c0000) >> 18) << 15); + slotbuf[0] = (slotbuf[0] & ~0x700000) | (((insn[0] & 0x700) >> 8) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1800000) | (((insn[1] & 0x1800000) >> 23) << 23); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[0] & 0x800) >> 11) << 25); + slotbuf[0] = (slotbuf[0] & ~0x3c000000) | (((insn[1] & 0xf00) >> 8) << 26); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[2] & 0x600000) >> 21) << 30); + slotbuf[1] = ((insn[3] & 0x6000) >> 13); + slotbuf[1] = (slotbuf[1] & ~0x4) | (((insn[3] & 0x10000000) >> 28) << 2); + slotbuf[1] = (slotbuf[1] & ~0x8) | (((insn[3] & 0x20000000) >> 29) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x40000000) >> 30) << 4); + slotbuf[1] = (slotbuf[1] & ~0x20) | (((insn[3] & 0x80000000) >> 31) << 5); +} + +static void +Slot_ae_format_6_Format_ae6_slot3_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x3e000) | ((slotbuf[0] & 0x1f) << 13); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x60) >> 5) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0x380) >> 7) << 10); + insn[2] = (insn[2] & ~0xf8) | (((slotbuf[0] & 0x7c00) >> 10) << 3); + insn[1] = (insn[1] & ~0x7c0000) | (((slotbuf[0] & 0xf8000) >> 15) << 18); + insn[0] = (insn[0] & ~0x700) | (((slotbuf[0] & 0x700000) >> 20) << 8); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x1800000) >> 23) << 23); + insn[0] = (insn[0] & ~0x800) | (((slotbuf[0] & 0x2000000) >> 25) << 11); + insn[1] = (insn[1] & ~0xf00) | (((slotbuf[0] & 0x3c000000) >> 26) << 8); + insn[2] = (insn[2] & ~0x600000) | (((slotbuf[0] & 0xc0000000) >> 30) << 21); + insn[3] = (insn[3] & ~0x6000) | ((slotbuf[1] & 0x3) << 13); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[1] & 0x4) >> 2) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[1] & 0x8) >> 3) << 29); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[1] & 0x10) >> 4) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x20) >> 5) << 31); +} + +static void +Slot_ae_format_7_Format_ae7_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x3f0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x3c0) | (((insn[0] & 0xf000) >> 12) << 6); + slotbuf[0] = (slotbuf[0] & ~0x1c00) | (((insn[2] & 0xe00000) >> 21) << 10); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[2] & 0x30000) >> 16) << 13); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[2] & 0x7000000) >> 24) << 15); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[0] & 0xc00) >> 10) << 18); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[0] & 0x4000000) >> 26) << 20); + slotbuf[0] = (slotbuf[0] & ~0x600000) | (((insn[1] & 0x1800000) >> 23) << 21); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x20000000) >> 29) << 23); +} + +static void +Slot_ae_format_7_Format_ae7_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3f0) | ((slotbuf[0] & 0x3f) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0x3c0) >> 6) << 12); + insn[2] = (insn[2] & ~0xe00000) | (((slotbuf[0] & 0x1c00) >> 10) << 21); + insn[2] = (insn[2] & ~0x30000) | (((slotbuf[0] & 0x6000) >> 13) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0x38000) >> 15) << 24); + insn[0] = (insn[0] & ~0xc00) | (((slotbuf[0] & 0xc0000) >> 18) << 10); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x100000) >> 20) << 26); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x600000) >> 21) << 23); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x800000) >> 23) << 29); +} + +static void +Slot_ae_format_7_Format_ae7_slot1_72_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xf000) >> 12); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[2] & 0xf00) >> 8) << 4); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[2] & 0xf8000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x40000) >> 18) << 18); + slotbuf[0] = (slotbuf[0] & ~0x780000) | (((insn[3] & 0x1e000) >> 13) << 19); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x40000000) >> 30) << 23); +} + +static void +Slot_ae_format_7_Format_ae7_slot1_72_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xf000) | ((slotbuf[0] & 0xf) << 12); + insn[2] = (insn[2] & ~0xf00) | (((slotbuf[0] & 0xf0) >> 4) << 8); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x1f00) >> 8) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[2] = (insn[2] & ~0x40000) | (((slotbuf[0] & 0x40000) >> 18) << 18); + insn[3] = (insn[3] & ~0x1e000) | (((slotbuf[0] & 0x780000) >> 19) << 13); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x800000) >> 23) << 30); +} + +static void +Slot_ae_format_7_Format_ae7_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x1ff8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x3e00000) >> 21) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[0] & 0x1f0000) >> 16) << 15); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[3] & 0x3e0) >> 5) << 20); + slotbuf[0] = (slotbuf[0] & ~0x6000000) | (((insn[0] & 0x18000000) >> 27) << 25); + slotbuf[0] = (slotbuf[0] & ~0x38000000) | ((insn[1] & 0x7) << 27); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0x60000) >> 17) << 30); + slotbuf[1] = ((insn[3] & 0x780000) >> 19); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x80000000) >> 31) << 4); +} + +static void +Slot_ae_format_7_Format_ae7_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x1ff8) | ((slotbuf[0] & 0x3ff) << 3); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x7c00) >> 10) << 21); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0xf8000) >> 15) << 16); + insn[3] = (insn[3] & ~0x3e0) | (((slotbuf[0] & 0x1f00000) >> 20) << 5); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x6000000) >> 25) << 27); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x38000000) >> 27); + insn[3] = (insn[3] & ~0x60000) | (((slotbuf[0] & 0xc0000000) >> 30) << 17); + insn[3] = (insn[3] & ~0x780000) | ((slotbuf[1] & 0xf) << 19); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x10) >> 4) << 31); +} + +static void +Slot_ae_format_7_Format_ae7_slot3_45_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xfe000000) >> 25); + slotbuf[0] = (slotbuf[0] & ~0x7f80) | ((insn[2] & 0xff) << 7); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x180000) >> 19) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[3] & 0x1c00) >> 10) << 17); + slotbuf[0] = (slotbuf[0] & ~0x3ff00000) | (((insn[1] & 0x7fe000) >> 13) << 20); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0x1800000) >> 23) << 30); + slotbuf[1] = ((insn[3] & 0x1e000000) >> 25); +} + +static void +Slot_ae_format_7_Format_ae7_slot3_45_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xfe000000) | ((slotbuf[0] & 0x7f) << 25); + insn[2] = (insn[2] & ~0xff) | ((slotbuf[0] & 0x7f80) >> 7); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x18000) >> 15) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0xe0000) >> 17) << 10); + insn[1] = (insn[1] & ~0x7fe000) | (((slotbuf[0] & 0x3ff00000) >> 20) << 13); + insn[3] = (insn[3] & ~0x1800000) | (((slotbuf[0] & 0xc0000000) >> 30) << 23); + insn[3] = (insn[3] & ~0x1e000000) | ((slotbuf[1] & 0xf) << 25); +} + +static void +Slot_ae_format_8_Format_ae8_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xf0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x70) | (((insn[2] & 0x3800000) >> 23) << 4); + slotbuf[0] = (slotbuf[0] & ~0x80) | (((insn[0] & 0x2000) >> 13) << 7); + slotbuf[0] = (slotbuf[0] & ~0x100) | (((insn[0] & 0x100) >> 8) << 8); + slotbuf[0] = (slotbuf[0] & ~0x600) | (((insn[0] & 0x18000000) >> 27) << 9); + slotbuf[0] = (slotbuf[0] & ~0x800) | ((insn[1] & 0x1) << 11); + slotbuf[0] = (slotbuf[0] & ~0x3000) | (((insn[1] & 0x1800000) >> 23) << 12); + slotbuf[0] = (slotbuf[0] & ~0x4000) | (((insn[0] & 0x200) >> 9) << 14); + slotbuf[0] = (slotbuf[0] & ~0x8000) | (((insn[0] & 0x1000) >> 12) << 15); + slotbuf[0] = (slotbuf[0] & ~0x30000) | (((insn[0] & 0xc00) >> 10) << 16); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x10000) >> 16) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[2] & 0x200000) >> 21) << 19); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[1] & 0x1000) >> 12) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1e00000) | (((insn[1] & 0x1e000000) >> 25) << 21); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[2] & 0x400000) >> 22) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x10000) >> 16) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x20000) >> 17) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x40000) >> 18) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x80000) >> 19) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x100000) >> 20) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x200000) >> 21) << 31); +} + +static void +Slot_ae_format_8_Format_ae8_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0) | ((slotbuf[0] & 0xf) << 4); + insn[2] = (insn[2] & ~0x3800000) | (((slotbuf[0] & 0x70) >> 4) << 23); + insn[0] = (insn[0] & ~0x2000) | (((slotbuf[0] & 0x80) >> 7) << 13); + insn[0] = (insn[0] & ~0x100) | (((slotbuf[0] & 0x100) >> 8) << 8); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x600) >> 9) << 27); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x800) >> 11); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x3000) >> 12) << 23); + insn[0] = (insn[0] & ~0x200) | (((slotbuf[0] & 0x4000) >> 14) << 9); + insn[0] = (insn[0] & ~0x1000) | (((slotbuf[0] & 0x8000) >> 15) << 12); + insn[0] = (insn[0] & ~0xc00) | (((slotbuf[0] & 0x30000) >> 16) << 10); + insn[2] = (insn[2] & ~0x10000) | (((slotbuf[0] & 0x40000) >> 18) << 16); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[0] & 0x80000) >> 19) << 21); + insn[1] = (insn[1] & ~0x1000) | (((slotbuf[0] & 0x100000) >> 20) << 12); + insn[1] = (insn[1] & ~0x1e000000) | (((slotbuf[0] & 0x1e00000) >> 21) << 25); + insn[2] = (insn[2] & ~0x400000) | (((slotbuf[0] & 0x2000000) >> 25) << 22); + insn[3] = (insn[3] & ~0x10000) | (((slotbuf[0] & 0x4000000) >> 26) << 16); + insn[3] = (insn[3] & ~0x20000) | (((slotbuf[0] & 0x8000000) >> 27) << 17); + insn[3] = (insn[3] & ~0x40000) | (((slotbuf[0] & 0x10000000) >> 28) << 18); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[0] & 0x20000000) >> 29) << 19); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[0] & 0x40000000) >> 30) << 20); + insn[3] = (insn[3] & ~0x200000) | (((slotbuf[0] & 0x80000000) >> 31) << 21); +} + +static void +Slot_ae_format_8_Format_ae8_slot1_14_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[0] & 0xc000) >> 14) << 8); + slotbuf[0] = (slotbuf[0] & ~0x400) | (((insn[1] & 0x2) >> 1) << 10); + slotbuf[0] = (slotbuf[0] & ~0x800) | (((insn[1] & 0x8) >> 3) << 11); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[2] & 0x80000000) >> 31) << 12); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[2] & 0x60000) >> 17) << 18); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[2] & 0x4000000) >> 26) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1e00000) | (((insn[3] & 0x1e0) >> 5) << 21); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x400000) >> 22) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x800000) >> 23) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x1000000) >> 24) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x2000000) >> 25) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x4000000) >> 26) << 29); +} + +static void +Slot_ae_format_8_Format_ae8_slot1_14_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[0] = (insn[0] & ~0xc000) | (((slotbuf[0] & 0x300) >> 8) << 14); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x400) >> 10) << 1); + insn[1] = (insn[1] & ~0x8) | (((slotbuf[0] & 0x800) >> 11) << 3); + insn[2] = (insn[2] & ~0x80000000) | (((slotbuf[0] & 0x1000) >> 12) << 31); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[2] = (insn[2] & ~0x60000) | (((slotbuf[0] & 0xc0000) >> 18) << 17); + insn[2] = (insn[2] & ~0x4000000) | (((slotbuf[0] & 0x100000) >> 20) << 26); + insn[3] = (insn[3] & ~0x1e0) | (((slotbuf[0] & 0x1e00000) >> 21) << 5); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[0] & 0x2000000) >> 25) << 22); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[0] & 0x4000000) >> 26) << 23); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x8000000) >> 27) << 24); + insn[3] = (insn[3] & ~0x2000000) | (((slotbuf[0] & 0x10000000) >> 28) << 25); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x20000000) >> 29) << 26); +} + +static void +Slot_ae_format_8_Format_ae8_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xc0000000) >> 30); + slotbuf[0] = (slotbuf[0] & ~0x3fc) | ((insn[2] & 0xff) << 2); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x3e00000) >> 21) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[0] & 0x1f0000) >> 16) << 15); + slotbuf[0] = (slotbuf[0] & ~0xf00000) | (((insn[1] & 0xf0) >> 4) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[1] & 0x800) >> 11) << 24); + slotbuf[0] = (slotbuf[0] & ~0x6000000) | (((insn[2] & 0x180000) >> 19) << 25); + slotbuf[0] = (slotbuf[0] & ~0x38000000) | (((insn[3] & 0x1c00) >> 10) << 27); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[1] & 0xc0000) >> 18) << 30); + slotbuf[1] = ((insn[1] & 0x700000) >> 20); + slotbuf[1] = (slotbuf[1] & ~0x8) | (((insn[0] & 0x4000000) >> 26) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[1] & 0x4) >> 2) << 4); + slotbuf[1] = (slotbuf[1] & ~0xe0) | (((insn[1] & 0x700) >> 8) << 5); + slotbuf[1] = (slotbuf[1] & ~0x1f00) | (((insn[1] & 0x3e000) >> 13) << 8); + slotbuf[1] = (slotbuf[1] & ~0x2000) | (((insn[1] & 0x20000000) >> 29) << 13); + slotbuf[1] = (slotbuf[1] & ~0x3c000) | (((insn[2] & 0x78000000) >> 27) << 14); + slotbuf[1] = (slotbuf[1] & ~0x40000) | (((insn[3] & 0x200) >> 9) << 18); + slotbuf[1] = (slotbuf[1] & ~0x380000) | (((insn[3] & 0xe000) >> 13) << 19); + slotbuf[1] = (slotbuf[1] & ~0x400000) | (((insn[3] & 0x8000000) >> 27) << 22); + slotbuf[1] = (slotbuf[1] & ~0x800000) | (((insn[3] & 0x10000000) >> 28) << 23); + slotbuf[1] = (slotbuf[1] & ~0x1000000) | (((insn[3] & 0x20000000) >> 29) << 24); + slotbuf[1] = (slotbuf[1] & ~0x2000000) | (((insn[3] & 0x40000000) >> 30) << 25); + slotbuf[1] = (slotbuf[1] & ~0x4000000) | (((insn[3] & 0x80000000) >> 31) << 26); +} + +static void +Slot_ae_format_8_Format_ae8_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xc0000000) | ((slotbuf[0] & 0x3) << 30); + insn[2] = (insn[2] & ~0xff) | ((slotbuf[0] & 0x3fc) >> 2); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x7c00) >> 10) << 21); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0xf8000) >> 15) << 16); + insn[1] = (insn[1] & ~0xf0) | (((slotbuf[0] & 0xf00000) >> 20) << 4); + insn[1] = (insn[1] & ~0x800) | (((slotbuf[0] & 0x1000000) >> 24) << 11); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x6000000) >> 25) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0x38000000) >> 27) << 10); + insn[1] = (insn[1] & ~0xc0000) | (((slotbuf[0] & 0xc0000000) >> 30) << 18); + insn[1] = (insn[1] & ~0x700000) | ((slotbuf[1] & 0x7) << 20); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[1] & 0x8) >> 3) << 26); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[1] & 0x10) >> 4) << 2); + insn[1] = (insn[1] & ~0x700) | (((slotbuf[1] & 0xe0) >> 5) << 8); + insn[1] = (insn[1] & ~0x3e000) | (((slotbuf[1] & 0x1f00) >> 8) << 13); + insn[1] = (insn[1] & ~0x20000000) | (((slotbuf[1] & 0x2000) >> 13) << 29); + insn[2] = (insn[2] & ~0x78000000) | (((slotbuf[1] & 0x3c000) >> 14) << 27); + insn[3] = (insn[3] & ~0x200) | (((slotbuf[1] & 0x40000) >> 18) << 9); + insn[3] = (insn[3] & ~0xe000) | (((slotbuf[1] & 0x380000) >> 19) << 13); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[1] & 0x400000) >> 22) << 27); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[1] & 0x800000) >> 23) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[1] & 0x1000000) >> 24) << 29); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[1] & 0x2000000) >> 25) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x4000000) >> 26) << 31); +} + +static void +Slot_ae_format_9_Format_ae9_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xfff0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x7000) | (((insn[0] & 0x1c000000) >> 26) << 12); + slotbuf[0] = (slotbuf[0] & ~0x38000) | ((insn[1] & 0x7) << 15); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x10000) >> 16) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[2] & 0x200000) >> 21) << 19); + slotbuf[0] = (slotbuf[0] & ~0x300000) | (((insn[1] & 0x1800000) >> 23) << 20); + slotbuf[0] = (slotbuf[0] & ~0x3c00000) | (((insn[2] & 0x3c00000) >> 22) << 22); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x1000000) >> 24) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x2000000) >> 25) << 27); +} + +static void +Slot_ae_format_9_Format_ae9_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xfff0) | ((slotbuf[0] & 0xfff) << 4); + insn[0] = (insn[0] & ~0x1c000000) | (((slotbuf[0] & 0x7000) >> 12) << 26); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x38000) >> 15); + insn[2] = (insn[2] & ~0x10000) | (((slotbuf[0] & 0x40000) >> 18) << 16); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[0] & 0x80000) >> 19) << 21); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x300000) >> 20) << 23); + insn[2] = (insn[2] & ~0x3c00000) | (((slotbuf[0] & 0x3c00000) >> 22) << 22); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x4000000) >> 26) << 24); + insn[3] = (insn[3] & ~0x2000000) | (((slotbuf[0] & 0x8000000) >> 27) << 25); +} + +static void +Slot_ae_format_9_Format_ae9_slot1_72_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[2] & 0xf8000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[2] & 0x60000) >> 17) << 18); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[2] & 0x4000000) >> 26) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1e00000) | (((insn[3] & 0x1e000) >> 13) << 21); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x4000000) >> 26) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x8000000) >> 27) << 26); +} + +static void +Slot_ae_format_9_Format_ae9_slot1_72_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x1f00) >> 8) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[2] = (insn[2] & ~0x60000) | (((slotbuf[0] & 0xc0000) >> 18) << 17); + insn[2] = (insn[2] & ~0x4000000) | (((slotbuf[0] & 0x100000) >> 20) << 26); + insn[3] = (insn[3] & ~0x1e000) | (((slotbuf[0] & 0x1e00000) >> 21) << 13); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x2000000) >> 25) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x4000000) >> 26) << 27); +} + +static void +Slot_ae_format_9_Format_ae9_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[3] & 0x3e0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x60) | (((insn[1] & 0xc0000000) >> 30) << 5); + slotbuf[0] = (slotbuf[0] & ~0x380) | ((insn[2] & 0x7) << 7); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x1f0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1ff8000) | (((insn[1] & 0x1ff8) >> 3) << 15); + slotbuf[0] = (slotbuf[0] & ~0x3e000000) | (((insn[0] & 0x3e00000) >> 21) << 25); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0x60000) >> 17) << 30); + slotbuf[1] = ((insn[3] & 0x10000000) >> 28); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[3] & 0x20000000) >> 29) << 1); +} + +static void +Slot_ae_format_9_Format_ae9_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[3] = (insn[3] & ~0x3e0) | ((slotbuf[0] & 0x1f) << 5); + insn[1] = (insn[1] & ~0xc0000000) | (((slotbuf[0] & 0x60) >> 5) << 30); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0x380) >> 7); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0x7c00) >> 10) << 16); + insn[1] = (insn[1] & ~0x1ff8) | (((slotbuf[0] & 0x1ff8000) >> 15) << 3); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x3e000000) >> 25) << 21); + insn[3] = (insn[3] & ~0x60000) | (((slotbuf[0] & 0xc0000000) >> 30) << 17); + insn[3] = (insn[3] & ~0x10000000) | ((slotbuf[1] & 0x1) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[1] & 0x2) >> 1) << 29); +} + +static void +Slot_ae_format_9_Format_ae9_slot3_45_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xf8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0x3e0) | (((insn[1] & 0x3e000000) >> 25) << 5); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[1] & 0x7c0000) >> 18) << 10); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x180000) >> 19) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[3] & 0x1c00) >> 10) << 17); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[1] & 0x3e000) >> 13) << 20); + slotbuf[0] = (slotbuf[0] & ~0x3e000000) | (((insn[3] & 0xf80000) >> 19) << 25); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x40000000) >> 30) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x80000000) >> 31) << 31); +} + +static void +Slot_ae_format_9_Format_ae9_slot3_45_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xf8) | ((slotbuf[0] & 0x1f) << 3); + insn[1] = (insn[1] & ~0x3e000000) | (((slotbuf[0] & 0x3e0) >> 5) << 25); + insn[1] = (insn[1] & ~0x7c0000) | (((slotbuf[0] & 0x7c00) >> 10) << 18); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x18000) >> 15) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0xe0000) >> 17) << 10); + insn[1] = (insn[1] & ~0x3e000) | (((slotbuf[0] & 0x1f00000) >> 20) << 13); + insn[3] = (insn[3] & ~0xf80000) | (((slotbuf[0] & 0x3e000000) >> 25) << 19); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x40000000) >> 30) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x80000000) >> 31) << 31); +} + +static void +Slot_ae_format_10_Format_ae10_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x3f0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x3c0) | (((insn[0] & 0xf000) >> 12) << 6); + slotbuf[0] = (slotbuf[0] & ~0xc00) | (((insn[0] & 0xc00) >> 10) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[2] & 0x800000) >> 23) << 12); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[2] & 0x30000) >> 16) << 13); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[2] & 0x7000000) >> 24) << 15); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[1] & 0x2) >> 1) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[0] & 0x4000000) >> 26) << 19); + slotbuf[0] = (slotbuf[0] & ~0x300000) | (((insn[2] & 0x600000) >> 21) << 20); + slotbuf[0] = (slotbuf[0] & ~0xc00000) | (((insn[3] & 0x6000) >> 13) << 22); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x40000000) >> 30) << 24); +} + +static void +Slot_ae_format_10_Format_ae10_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3f0) | ((slotbuf[0] & 0x3f) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0x3c0) >> 6) << 12); + insn[0] = (insn[0] & ~0xc00) | (((slotbuf[0] & 0xc00) >> 10) << 10); + insn[2] = (insn[2] & ~0x800000) | (((slotbuf[0] & 0x1000) >> 12) << 23); + insn[2] = (insn[2] & ~0x30000) | (((slotbuf[0] & 0x6000) >> 13) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0x38000) >> 15) << 24); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x40000) >> 18) << 1); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x80000) >> 19) << 26); + insn[2] = (insn[2] & ~0x600000) | (((slotbuf[0] & 0x300000) >> 20) << 21); + insn[3] = (insn[3] & ~0x6000) | (((slotbuf[0] & 0xc00000) >> 22) << 13); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x1000000) >> 24) << 30); +} + +static void +Slot_ae_format_10_Format_ae10_slot1_34_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[2] & 0xf8000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[1] & 0x4) >> 2) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[2] & 0x40000) >> 18) << 19); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[3] & 0xf8000) >> 15) << 20); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x80000000) >> 31) << 25); +} + +static void +Slot_ae_format_10_Format_ae10_slot1_34_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x1f00) >> 8) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[0] & 0x40000) >> 18) << 2); + insn[2] = (insn[2] & ~0x40000) | (((slotbuf[0] & 0x80000) >> 19) << 18); + insn[3] = (insn[3] & ~0xf8000) | (((slotbuf[0] & 0x1f00000) >> 20) << 15); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x2000000) >> 25) << 31); +} + +static void +Slot_ae_format_10_Format_ae10_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[3] & 0x3e0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x60) | (((insn[1] & 0xc0000000) >> 30) << 5); + slotbuf[0] = (slotbuf[0] & ~0x380) | ((insn[2] & 0x7) << 7); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x1f0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1ff8000) | (((insn[1] & 0x1ff8) >> 3) << 15); + slotbuf[0] = (slotbuf[0] & ~0x3e000000) | (((insn[0] & 0x3e00000) >> 21) << 25); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0x300000) >> 20) << 30); + slotbuf[1] = ((insn[3] & 0x1c00000) >> 22); +} + +static void +Slot_ae_format_10_Format_ae10_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[3] = (insn[3] & ~0x3e0) | ((slotbuf[0] & 0x1f) << 5); + insn[1] = (insn[1] & ~0xc0000000) | (((slotbuf[0] & 0x60) >> 5) << 30); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0x380) >> 7); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0x7c00) >> 10) << 16); + insn[1] = (insn[1] & ~0x1ff8) | (((slotbuf[0] & 0x1ff8000) >> 15) << 3); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x3e000000) >> 25) << 21); + insn[3] = (insn[3] & ~0x300000) | (((slotbuf[0] & 0xc0000000) >> 30) << 20); + insn[3] = (insn[3] & ~0x1c00000) | ((slotbuf[1] & 0x7) << 22); +} + +static void +Slot_ae_format_10_Format_ae10_slot3_27_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xf8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0x3e0) | (((insn[1] & 0x3e000000) >> 25) << 5); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[1] & 0x7c0000) >> 18) << 10); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x180000) >> 19) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[3] & 0x1c00) >> 10) << 17); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[1] & 0x3e000) >> 13) << 20); + slotbuf[0] = (slotbuf[0] & ~0x6000000) | (((insn[0] & 0x18000000) >> 27) << 25); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | ((insn[1] & 0x1) << 27); + slotbuf[0] = (slotbuf[0] & ~0x30000000) | (((insn[1] & 0x1800000) >> 23) << 28); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0x6000000) >> 25) << 30); + slotbuf[1] = ((insn[3] & 0x38000000) >> 27); +} + +static void +Slot_ae_format_10_Format_ae10_slot3_27_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xf8) | ((slotbuf[0] & 0x1f) << 3); + insn[1] = (insn[1] & ~0x3e000000) | (((slotbuf[0] & 0x3e0) >> 5) << 25); + insn[1] = (insn[1] & ~0x7c0000) | (((slotbuf[0] & 0x7c00) >> 10) << 18); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x18000) >> 15) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0xe0000) >> 17) << 10); + insn[1] = (insn[1] & ~0x3e000) | (((slotbuf[0] & 0x1f00000) >> 20) << 13); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x6000000) >> 25) << 27); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x8000000) >> 27); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x30000000) >> 28) << 23); + insn[3] = (insn[3] & ~0x6000000) | (((slotbuf[0] & 0xc0000000) >> 30) << 25); + insn[3] = (insn[3] & ~0x38000000) | ((slotbuf[1] & 0x7) << 27); +} + +static void +Slot_ae_format_4_Format_ae4_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x3f0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x3c0) | (((insn[0] & 0xf000) >> 12) << 6); + slotbuf[0] = (slotbuf[0] & ~0xc00) | (((insn[0] & 0xc00) >> 10) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x2) >> 1) << 12); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[0] & 0x18000000) >> 27) << 13); + slotbuf[0] = (slotbuf[0] & ~0x8000) | ((insn[1] & 0x1) << 15); + slotbuf[0] = (slotbuf[0] & ~0x30000) | (((insn[1] & 0x1800000) >> 23) << 16); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x40000) >> 18) << 18); + slotbuf[0] = (slotbuf[0] & ~0x380000) | (((insn[3] & 0xe000) >> 13) << 19); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x10000000) >> 28) << 22); +} + +static void +Slot_ae_format_4_Format_ae4_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3f0) | ((slotbuf[0] & 0x3f) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0x3c0) >> 6) << 12); + insn[0] = (insn[0] & ~0xc00) | (((slotbuf[0] & 0xc00) >> 10) << 10); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x1000) >> 12) << 1); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x6000) >> 13) << 27); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x8000) >> 15); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x30000) >> 16) << 23); + insn[2] = (insn[2] & ~0x40000) | (((slotbuf[0] & 0x40000) >> 18) << 18); + insn[3] = (insn[3] & ~0xe000) | (((slotbuf[0] & 0x380000) >> 19) << 13); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[0] & 0x400000) >> 22) << 28); +} + +static void +Slot_ae_format_4_Format_ae4_slot1_72_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[2] & 0xf8000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0x3c0000) | (((insn[3] & 0xf0000) >> 16) << 18); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x20000000) >> 29) << 22); +} + +static void +Slot_ae_format_4_Format_ae4_slot1_72_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x1f00) >> 8) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[3] = (insn[3] & ~0xf0000) | (((slotbuf[0] & 0x3c0000) >> 18) << 16); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x400000) >> 22) << 29); +} + +static void +Slot_ae_format_4_Format_ae4_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x3e00000) >> 21); + slotbuf[0] = (slotbuf[0] & ~0x3e0) | (((insn[0] & 0x1f0000) >> 16) << 5); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[1] & 0xf8) >> 3) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[3] & 0x3e0) >> 5) << 15); + slotbuf[0] = (slotbuf[0] & ~0x700000) | (((insn[3] & 0x700000) >> 20) << 20); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x40000000) >> 30) << 23); +} + +static void +Slot_ae_format_4_Format_ae4_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3e00000) | ((slotbuf[0] & 0x1f) << 21); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0x3e0) >> 5) << 16); + insn[1] = (insn[1] & ~0xf8) | (((slotbuf[0] & 0x7c00) >> 10) << 3); + insn[3] = (insn[3] & ~0x3e0) | (((slotbuf[0] & 0xf8000) >> 15) << 5); + insn[3] = (insn[3] & ~0x700000) | (((slotbuf[0] & 0x700000) >> 20) << 20); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x800000) >> 23) << 30); +} + +static void +Slot_ae_format_4_Format_ae4_slot3_26_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0x180000) >> 19); + slotbuf[0] = (slotbuf[0] & ~0x1c) | (((insn[3] & 0x1c00) >> 10) << 2); + slotbuf[0] = (slotbuf[0] & ~0x20) | (((insn[0] & 0x4000000) >> 26) << 5); + slotbuf[0] = (slotbuf[0] & ~0x40) | (((insn[1] & 0x4) >> 2) << 6); + slotbuf[0] = (slotbuf[0] & ~0x380) | (((insn[1] & 0x700) >> 8) << 7); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[1] & 0x3e000) >> 13) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[2] & 0xf8) >> 3) << 15); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[1] & 0x7c0000) >> 18) << 20); + slotbuf[0] = (slotbuf[0] & ~0x6000000) | (((insn[3] & 0x1800000) >> 23) << 25); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x80000000) >> 31) << 27); +} + +static void +Slot_ae_format_4_Format_ae4_slot3_26_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0x180000) | ((slotbuf[0] & 0x3) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0x1c) >> 2) << 10); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x20) >> 5) << 26); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[0] & 0x40) >> 6) << 2); + insn[1] = (insn[1] & ~0x700) | (((slotbuf[0] & 0x380) >> 7) << 8); + insn[1] = (insn[1] & ~0x3e000) | (((slotbuf[0] & 0x7c00) >> 10) << 13); + insn[2] = (insn[2] & ~0xf8) | (((slotbuf[0] & 0xf8000) >> 15) << 3); + insn[1] = (insn[1] & ~0x7c0000) | (((slotbuf[0] & 0x1f00000) >> 20) << 18); + insn[3] = (insn[3] & ~0x1800000) | (((slotbuf[0] & 0x6000000) >> 25) << 23); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x8000000) >> 27) << 31); +} + +static void +Slot_ae_format_4_Format_ae4_slot4_43_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xfe000000) >> 25); + slotbuf[0] = (slotbuf[0] & ~0x380) | ((insn[2] & 0x7) << 7); + slotbuf[0] = (slotbuf[0] & ~0xc00) | (((insn[1] & 0x1800) >> 11) << 10); + slotbuf[0] = (slotbuf[0] & ~0x7000) | (((insn[2] & 0xe00000) >> 21) << 12); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x30000) >> 16) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[2] & 0x7000000) >> 24) << 17); + slotbuf[0] = (slotbuf[0] & ~0x700000) | (((insn[3] & 0xe000000) >> 25) << 20); +} + +static void +Slot_ae_format_4_Format_ae4_slot4_43_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xfe000000) | ((slotbuf[0] & 0x7f) << 25); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0x380) >> 7); + insn[1] = (insn[1] & ~0x1800) | (((slotbuf[0] & 0xc00) >> 10) << 11); + insn[2] = (insn[2] & ~0xe00000) | (((slotbuf[0] & 0x7000) >> 12) << 21); + insn[2] = (insn[2] & ~0x30000) | (((slotbuf[0] & 0x18000) >> 15) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0xe0000) >> 17) << 24); + insn[3] = (insn[3] & ~0xe000000) | (((slotbuf[0] & 0x700000) >> 20) << 25); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_s8_Slot_inst_get, + Field_imms8_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_r_disp_Slot_inst_get, + Field_r_3_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst_get, + Field_s2_Slot_inst_get, + Field_r2_Slot_inst_get, + Field_t4_Slot_inst_get, + Field_s4_Slot_inst_get, + Field_r4_Slot_inst_get, + Field_t8_Slot_inst_get, + Field_r8_Slot_inst_get, + Field_xt_wbr15_imm_Slot_inst_get, + Field_xt_wloop_imm_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_inst_11_8_Slot_inst_get, + Field_fld_inst_12_12_Slot_inst_get, + Field_fld_inst_12_8_Slot_inst_get, + Field_fld_inst_13_8_Slot_inst_get, + Field_fld_inst_15_12_Slot_inst_get, + Field_fld_inst_19_17_Slot_inst_get, + Field_fld_inst_19_18_Slot_inst_get, + Field_fld_inst_23_12_Slot_inst_get, + Field_fld_inst_23_16_Slot_inst_get, + Field_fld_inst_4_4_Slot_inst_get, + Field_fld_inst_5_4_Slot_inst_get, + Field_fld_inst_7_4_Slot_inst_get, + Field_fld_inst_7_6_Slot_inst_get, + Field_fld_inst_7_7_Slot_inst_get, + Field_fld_inst_9_8_Slot_inst_get, + Field_bitindex_Slot_inst_get, + Field_s3to1_Slot_inst_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_s8_Slot_inst_set, + Field_imms8_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_r_disp_Slot_inst_set, + Field_r_3_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst_set, + Field_s2_Slot_inst_set, + Field_r2_Slot_inst_set, + Field_t4_Slot_inst_set, + Field_s4_Slot_inst_set, + Field_r4_Slot_inst_set, + Field_t8_Slot_inst_set, + Field_r8_Slot_inst_set, + Field_xt_wbr15_imm_Slot_inst_set, + Field_xt_wloop_imm_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_inst_11_8_Slot_inst_set, + Field_fld_inst_12_12_Slot_inst_set, + Field_fld_inst_12_8_Slot_inst_set, + Field_fld_inst_13_8_Slot_inst_set, + Field_fld_inst_15_12_Slot_inst_set, + Field_fld_inst_19_17_Slot_inst_set, + Field_fld_inst_19_18_Slot_inst_set, + Field_fld_inst_23_12_Slot_inst_set, + Field_fld_inst_23_16_Slot_inst_set, + Field_fld_inst_4_4_Slot_inst_set, + Field_fld_inst_5_4_Slot_inst_set, + Field_fld_inst_7_4_Slot_inst_set, + Field_fld_inst_7_6_Slot_inst_set, + Field_fld_inst_7_7_Slot_inst_set, + Field_fld_inst_9_8_Slot_inst_set, + Field_bitindex_Slot_inst_set, + Field_s3to1_Slot_inst_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_get, + 0, + 0, + Field_r_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_set, + 0, + 0, + Field_r_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, 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+ 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_get, + 0, + 0, + Field_r_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_inst16b_12_Slot_inst16b_get, + Field_ae_fld_inst16b_15_13_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_set, + 0, + 0, + Field_r_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_inst16b_12_Slot_inst16b_set, + Field_ae_fld_inst16b_15_13_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot0_get_field_fns[] = { + Field_t_Slot_ae_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot0_get, + Field_s_Slot_ae_slot0_get, + Field_s8_Slot_ae_slot0_get, + 0, + Field_imm12b_Slot_ae_slot0_get, + Field_imm16_Slot_ae_slot0_get, + 0, + 0, + Field_offset_Slot_ae_slot0_get, + 0, + 0, + Field_op2_Slot_ae_slot0_get, + Field_r_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae_slot0_get, + Field_sal_Slot_ae_slot0_get, + Field_sargt_Slot_ae_slot0_get, + 0, + Field_sas_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae_slot0_get, + 0, + Field_r2_Slot_ae_slot0_get, + Field_t4_Slot_ae_slot0_get, + Field_s4_Slot_ae_slot0_get, + Field_r4_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_art_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_d1_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcmp_br4t_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcnv_arr_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcnv_art_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot0_get, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae_slot0_get, + Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_a_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_su_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_vu_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_x_Slot_ae_slot0_get, + Field_fld_ae_sem_pks_d_Slot_ae_slot0_get, + Field_fld_ae_sem_pks_pos_Slot_ae_slot0_get, + Field_fld_ae_sem_pks_s_Slot_ae_slot0_get, + Field_fld_ae_sem_rng_v0_Slot_ae_slot0_get, + Field_fld_ae_sem_rng_v1_Slot_ae_slot0_get, + Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_a_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_a0_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_d_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_d0_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_d1_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_da_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_i16_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_i32_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_i64_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_imm32_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_imm8_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_sd_Slot_ae_slot0_get, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae_slot0_get, + Field_fld_ae_sem_sp32cvt_art_Slot_ae_slot0_get, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae_slot0_get, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae_slot0_get, + Field_fld_ae_sem_spmisc_brt_Slot_ae_slot0_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot0_get, + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get, + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get, + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_10_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_6_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_9_Slot_ae_slot0_get, + Field_fld_ae_slot0_14_12_Slot_ae_slot0_get, + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_10_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_13_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get, + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get, + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get, + Field_fld_ae_slot0_18_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_19_12_Slot_ae_slot0_get, + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get, + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get, + Field_fld_ae_slot0_19_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_1_1_Slot_ae_slot0_get, + Field_fld_ae_slot0_20_16_Slot_ae_slot0_get, + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get, + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get, + Field_fld_ae_slot0_23_17_Slot_ae_slot0_get, + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get, + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_10_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_12_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_14_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_15_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_16_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_17_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_19_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_21_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_22_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_24_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_26_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_27_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_4_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get, + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get, + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get, + Field_fld_ae_slot0_4_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get, + Field_fld_ae_slot0_5_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get, + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get, + Field_fld_ae_slot0_7_3_Slot_ae_slot0_get, + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get, + Field_fld_ae_slot0_8_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_9_4_Slot_ae_slot0_get, + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot0_set_field_fns[] = { + Field_t_Slot_ae_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot0_set, + Field_s_Slot_ae_slot0_set, + Field_s8_Slot_ae_slot0_set, + 0, + Field_imm12b_Slot_ae_slot0_set, + Field_imm16_Slot_ae_slot0_set, + 0, + 0, + Field_offset_Slot_ae_slot0_set, + 0, + 0, + Field_op2_Slot_ae_slot0_set, + Field_r_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae_slot0_set, + Field_sal_Slot_ae_slot0_set, + Field_sargt_Slot_ae_slot0_set, + 0, + Field_sas_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae_slot0_set, + 0, + Field_r2_Slot_ae_slot0_set, + Field_t4_Slot_ae_slot0_set, + Field_s4_Slot_ae_slot0_set, + Field_r4_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_art_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_d1_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcmp_br4t_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcnv_arr_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcnv_art_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot0_set, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae_slot0_set, + Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_a_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_su_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_vu_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_x_Slot_ae_slot0_set, + Field_fld_ae_sem_pks_d_Slot_ae_slot0_set, + Field_fld_ae_sem_pks_pos_Slot_ae_slot0_set, + Field_fld_ae_sem_pks_s_Slot_ae_slot0_set, + Field_fld_ae_sem_rng_v0_Slot_ae_slot0_set, + Field_fld_ae_sem_rng_v1_Slot_ae_slot0_set, + Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_a_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_a0_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_d_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_d0_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_d1_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_da_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_i16_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_i32_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_i64_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_imm32_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_imm8_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_sd_Slot_ae_slot0_set, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae_slot0_set, + Field_fld_ae_sem_sp32cvt_art_Slot_ae_slot0_set, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae_slot0_set, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae_slot0_set, + Field_fld_ae_sem_spmisc_brt_Slot_ae_slot0_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot0_set, + Field_fld_ae_slot0_11_10_Slot_ae_slot0_set, + Field_fld_ae_slot0_11_11_Slot_ae_slot0_set, + Field_fld_ae_slot0_11_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_11_9_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_10_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_12_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_2_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_6_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_9_Slot_ae_slot0_set, + Field_fld_ae_slot0_14_12_Slot_ae_slot0_set, + Field_fld_ae_slot0_14_13_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_10_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_12_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_13_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_14_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_15_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_16_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_17_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_18_13_Slot_ae_slot0_set, + Field_fld_ae_slot0_18_15_Slot_ae_slot0_set, + Field_fld_ae_slot0_18_16_Slot_ae_slot0_set, + Field_fld_ae_slot0_18_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_19_12_Slot_ae_slot0_set, + Field_fld_ae_slot0_19_15_Slot_ae_slot0_set, + Field_fld_ae_slot0_19_19_Slot_ae_slot0_set, + Field_fld_ae_slot0_19_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_1_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_1_1_Slot_ae_slot0_set, + Field_fld_ae_slot0_20_16_Slot_ae_slot0_set, + Field_fld_ae_slot0_20_20_Slot_ae_slot0_set, + Field_fld_ae_slot0_23_15_Slot_ae_slot0_set, + Field_fld_ae_slot0_23_17_Slot_ae_slot0_set, + Field_fld_ae_slot0_23_19_Slot_ae_slot0_set, + Field_fld_ae_slot0_23_22_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_10_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_12_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_14_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_15_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_16_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_17_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_19_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_21_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_22_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_24_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_26_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_27_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_4_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_3_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_3_1_Slot_ae_slot0_set, + Field_fld_ae_slot0_3_2_Slot_ae_slot0_set, + Field_fld_ae_slot0_3_3_Slot_ae_slot0_set, + Field_fld_ae_slot0_4_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_4_4_Slot_ae_slot0_set, + Field_fld_ae_slot0_5_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_5_4_Slot_ae_slot0_set, + Field_fld_ae_slot0_7_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_7_2_Slot_ae_slot0_set, + Field_fld_ae_slot0_7_3_Slot_ae_slot0_set, + Field_fld_ae_slot0_7_4_Slot_ae_slot0_set, + Field_fld_ae_slot0_8_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_9_4_Slot_ae_slot0_set, + Field_fld_ae_slot0_9_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_9_9_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot1_get_field_fns[] = { + Field_t_Slot_ae_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot1_get, + Field_s_Slot_ae_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae_slot1_get, + Field_r_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae_slot1_get, + Field_sal_Slot_ae_slot1_get, + Field_sargt_Slot_ae_slot1_get, + 0, + Field_sas_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot1_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot1_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot1_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_a_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_0_0_Slot_ae_slot1_get, + Field_fld_ae_slot1_12_8_Slot_ae_slot1_get, + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get, + Field_fld_ae_slot1_17_17_Slot_ae_slot1_get, + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_1_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_12_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_13_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_16_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_17_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_18_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_20_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_22_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_23_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_8_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_9_Slot_ae_slot1_get, + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get, + Field_fld_ae_slot1_3_2_Slot_ae_slot1_get, + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get, + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot1_set_field_fns[] = { + Field_t_Slot_ae_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot1_set, + Field_s_Slot_ae_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae_slot1_set, + Field_r_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae_slot1_set, + Field_sal_Slot_ae_slot1_set, + Field_sargt_Slot_ae_slot1_set, + 0, + Field_sas_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot1_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot1_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot1_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_a_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_0_0_Slot_ae_slot1_set, + Field_fld_ae_slot1_12_8_Slot_ae_slot1_set, + Field_fld_ae_slot1_17_13_Slot_ae_slot1_set, + Field_fld_ae_slot1_17_17_Slot_ae_slot1_set, + Field_fld_ae_slot1_17_8_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_1_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_12_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_13_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_16_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_17_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_18_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_20_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_22_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_23_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_8_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_9_Slot_ae_slot1_set, + Field_fld_ae_slot1_3_0_Slot_ae_slot1_set, + Field_fld_ae_slot1_3_2_Slot_ae_slot1_set, + Field_fld_ae_slot1_3_3_Slot_ae_slot1_set, + Field_fld_ae_slot1_7_4_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot2_get, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot2_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae_slot2_get, + Field_fld_ae_sem_pks_pos_Slot_ae_slot2_get, + Field_fld_ae_sem_pks_s_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae_slot2_get, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot2_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae_slot2_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_hpcnv_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_hpfma_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_get, + Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot2_get, + Field_fld_ae_sem_multiply_d0_Slot_ae_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae_slot2_get, + Field_fld_ae_sem_multiply_q1_Slot_ae_slot2_get, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae_slot2_get, + Field_fld_ae_sem_reduction_sort_v_Slot_ae_slot2_get, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae_slot2_get, + Field_fld_ae_sem_select_isel_Slot_ae_slot2_get, + Field_fld_ae_sem_select_ss_Slot_ae_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_select_vu_Slot_ae_slot2_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_vp_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot2_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot2_get, + Field_fld_ae_slot2_14_0_Slot_ae_slot2_get, + Field_fld_ae_slot2_14_10_Slot_ae_slot2_get, + Field_fld_ae_slot2_14_14_Slot_ae_slot2_get, + Field_fld_ae_slot2_14_5_Slot_ae_slot2_get, + Field_fld_ae_slot2_16_15_Slot_ae_slot2_get, + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_15_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_17_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_19_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_20_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_25_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_4_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_5_Slot_ae_slot2_get, + Field_fld_ae_slot2_3_0_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_1_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_2_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_6_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_8_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot2_set, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot2_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae_slot2_set, + Field_fld_ae_sem_pks_pos_Slot_ae_slot2_set, + Field_fld_ae_sem_pks_s_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae_slot2_set, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot2_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae_slot2_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_hpcnv_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_hpfma_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_set, + Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot2_set, + Field_fld_ae_sem_multiply_d0_Slot_ae_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae_slot2_set, + Field_fld_ae_sem_multiply_q1_Slot_ae_slot2_set, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae_slot2_set, + Field_fld_ae_sem_reduction_sort_v_Slot_ae_slot2_set, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae_slot2_set, + Field_fld_ae_sem_select_isel_Slot_ae_slot2_set, + Field_fld_ae_sem_select_ss_Slot_ae_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_select_vu_Slot_ae_slot2_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_vp_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot2_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot2_set, + Field_fld_ae_slot2_14_0_Slot_ae_slot2_set, + Field_fld_ae_slot2_14_10_Slot_ae_slot2_set, + Field_fld_ae_slot2_14_14_Slot_ae_slot2_set, + Field_fld_ae_slot2_14_5_Slot_ae_slot2_set, + Field_fld_ae_slot2_16_15_Slot_ae_slot2_set, + Field_fld_ae_slot2_19_15_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_15_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_17_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_19_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_20_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_25_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_4_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_5_Slot_ae_slot2_set, + Field_fld_ae_slot2_3_0_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_0_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_1_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_2_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_5_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_6_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_7_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_8_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r4_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot3_get, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot3_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot3_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_d_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_d0_Slot_ae_slot3_get, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_i32_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_i64_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae_slot3_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_get, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot3_get, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot3_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae_slot3_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae_slot3_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae_slot3_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae_slot3_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_d0_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_d2_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_q0_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_q1_Slot_ae_slot3_get, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae_slot3_get, + Field_fld_ae_sem_select_ss_Slot_ae_slot3_get, + Field_fld_ae_sem_select_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_select_vs_Slot_ae_slot3_get, + Field_fld_ae_sem_select_vt_Slot_ae_slot3_get, + Field_fld_ae_sem_select_vu_Slot_ae_slot3_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot3_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot3_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_vp_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_vs_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_vt_Slot_ae_slot3_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot3_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae_slot3_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_imm_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_d1_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_d3_Slot_ae_slot3_get, + Field_fld_ae_sem_rng_d_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_e_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_i8_Slot_ae_slot3_get, + Field_fld_ae_slot3_11_0_Slot_ae_slot3_get, + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get, + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get, + Field_fld_ae_slot3_14_12_Slot_ae_slot3_get, + Field_fld_ae_slot3_14_13_Slot_ae_slot3_get, + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_17_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_18_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_19_Slot_ae_slot3_get, + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get, + Field_fld_ae_slot3_24_19_Slot_ae_slot3_get, + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_12_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_16_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_19_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_20_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_22_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_25_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_30_Slot_ae_slot3_get, + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get, + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get, + Field_fld_ae_slot3_9_1_Slot_ae_slot3_get, + Field_fld_ae_slot3_9_3_Slot_ae_slot3_get, + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r4_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot3_set, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot3_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot3_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_d_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_d0_Slot_ae_slot3_set, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_i32_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_i64_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae_slot3_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_set, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot3_set, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot3_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae_slot3_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae_slot3_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae_slot3_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae_slot3_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_d0_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_d2_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_q0_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_q1_Slot_ae_slot3_set, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae_slot3_set, + Field_fld_ae_sem_select_ss_Slot_ae_slot3_set, + Field_fld_ae_sem_select_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_select_vs_Slot_ae_slot3_set, + Field_fld_ae_sem_select_vt_Slot_ae_slot3_set, + Field_fld_ae_sem_select_vu_Slot_ae_slot3_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot3_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot3_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_vp_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_vs_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_vt_Slot_ae_slot3_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot3_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae_slot3_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_imm_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_d1_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_d3_Slot_ae_slot3_set, + Field_fld_ae_sem_rng_d_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_e_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_i8_Slot_ae_slot3_set, + Field_fld_ae_slot3_11_0_Slot_ae_slot3_set, + Field_fld_ae_slot3_14_0_Slot_ae_slot3_set, + Field_fld_ae_slot3_14_10_Slot_ae_slot3_set, + Field_fld_ae_slot3_14_12_Slot_ae_slot3_set, + Field_fld_ae_slot3_14_13_Slot_ae_slot3_set, + Field_fld_ae_slot3_16_13_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_0_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_10_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_15_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_17_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_18_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_19_Slot_ae_slot3_set, + Field_fld_ae_slot3_24_10_Slot_ae_slot3_set, + Field_fld_ae_slot3_24_19_Slot_ae_slot3_set, + Field_fld_ae_slot3_24_20_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_12_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_16_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_19_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_20_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_22_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_25_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_30_Slot_ae_slot3_set, + Field_fld_ae_slot3_4_0_Slot_ae_slot3_set, + Field_fld_ae_slot3_9_0_Slot_ae_slot3_set, + Field_fld_ae_slot3_9_1_Slot_ae_slot3_set, + Field_fld_ae_slot3_9_3_Slot_ae_slot3_set, + Field_fld_ae_slot3_9_5_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae2_slot0_get_field_fns[] = { + Field_t_Slot_ae2_slot0_get, + 0, + Field_bbi_Slot_ae2_slot0_get, + 0, + Field_imm8_Slot_ae2_slot0_get, + Field_s_Slot_ae2_slot0_get, + Field_s8_Slot_ae2_slot0_get, + 0, + Field_imm12b_Slot_ae2_slot0_get, + Field_imm16_Slot_ae2_slot0_get, + 0, + 0, + Field_offset_Slot_ae2_slot0_get, + 0, + 0, + Field_op2_Slot_ae2_slot0_get, + Field_r_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot0_get, + Field_sal_Slot_ae2_slot0_get, + Field_sargt_Slot_ae2_slot0_get, + 0, + Field_sas_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae2_slot0_get, + 0, + Field_r2_Slot_ae2_slot0_get, + Field_t4_Slot_ae2_slot0_get, + Field_s4_Slot_ae2_slot0_get, + Field_r4_Slot_ae2_slot0_get, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae2_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_art_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_ds_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_d1_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_hpcnv_arr_Slot_ae2_slot0_get, + Field_fld_ae_sem_hpcnv_art_Slot_ae2_slot0_get, + Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae2_slot0_get, + Field_fld_ae_sem_hpcnv_vr_Slot_ae2_slot0_get, + Field_fld_ae_sem_hpcnv_vt_Slot_ae2_slot0_get, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae2_slot0_get, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae2_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_su_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_vu_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot0_get, + Field_fld_ae_sem_pks_d_Slot_ae2_slot0_get, + Field_fld_ae_sem_pks_pos_Slot_ae2_slot0_get, + Field_fld_ae_sem_pks_s_Slot_ae2_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_a0_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_d_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_d0_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_d1_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_da_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_i16_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_i32_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_i64_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_imm32_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_imm8_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_sd_Slot_ae2_slot0_get, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae2_slot0_get, + Field_fld_ae_sem_sp32cvt_art_Slot_ae2_slot0_get, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae2_slot0_get, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae2_slot0_get, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae2_slot0_get, + Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot0_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot0_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_12_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_12_2_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_14_8_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_4_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_18_17_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_26_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae2_slot0_set_field_fns[] = { + Field_t_Slot_ae2_slot0_set, + 0, + Field_bbi_Slot_ae2_slot0_set, + 0, + Field_imm8_Slot_ae2_slot0_set, + Field_s_Slot_ae2_slot0_set, + Field_s8_Slot_ae2_slot0_set, + 0, + Field_imm12b_Slot_ae2_slot0_set, + Field_imm16_Slot_ae2_slot0_set, + 0, + 0, + Field_offset_Slot_ae2_slot0_set, + 0, + 0, + Field_op2_Slot_ae2_slot0_set, + Field_r_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot0_set, + Field_sal_Slot_ae2_slot0_set, + Field_sargt_Slot_ae2_slot0_set, + 0, + Field_sas_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae2_slot0_set, + 0, + Field_r2_Slot_ae2_slot0_set, + Field_t4_Slot_ae2_slot0_set, + Field_s4_Slot_ae2_slot0_set, + Field_r4_Slot_ae2_slot0_set, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae2_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_art_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_ds_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_d1_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_hpcnv_arr_Slot_ae2_slot0_set, + Field_fld_ae_sem_hpcnv_art_Slot_ae2_slot0_set, + Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae2_slot0_set, + Field_fld_ae_sem_hpcnv_vr_Slot_ae2_slot0_set, + Field_fld_ae_sem_hpcnv_vt_Slot_ae2_slot0_set, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae2_slot0_set, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae2_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_su_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_vu_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot0_set, + Field_fld_ae_sem_pks_d_Slot_ae2_slot0_set, + Field_fld_ae_sem_pks_pos_Slot_ae2_slot0_set, + Field_fld_ae_sem_pks_s_Slot_ae2_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_a0_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_d_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_d0_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_d1_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_da_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_i16_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_i32_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_i64_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_imm32_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_imm8_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_sd_Slot_ae2_slot0_set, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae2_slot0_set, + Field_fld_ae_sem_sp32cvt_art_Slot_ae2_slot0_set, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae2_slot0_set, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae2_slot0_set, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae2_slot0_set, + Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot0_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot0_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_12_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_12_2_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_14_8_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_4_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_18_17_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_26_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae2_slot1_get_field_fns[] = { + Field_t_Slot_ae2_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae2_slot1_get, + Field_s_Slot_ae2_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae2_slot1_get, + Field_r_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot1_get, + Field_sal_Slot_ae2_slot1_get, + Field_sargt_Slot_ae2_slot1_get, + 0, + Field_sas_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot1_get, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot1_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot1_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot1_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot1_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot1_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_11_0_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_17_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_18_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_22_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_23_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_3_2_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_3_3_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae2_slot1_set_field_fns[] = { + Field_t_Slot_ae2_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae2_slot1_set, + Field_s_Slot_ae2_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae2_slot1_set, + Field_r_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot1_set, + Field_sal_Slot_ae2_slot1_set, + Field_sargt_Slot_ae2_slot1_set, + 0, + Field_sas_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot1_set, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot1_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot1_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot1_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot1_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot1_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_11_0_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_17_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_18_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_22_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_23_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_3_2_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_3_3_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae2_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot2_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot2_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot2_get, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae2_slot2_get, + Field_fld_ae_sem_pks_pos_Slot_ae2_slot2_get, + Field_fld_ae_sem_pks_s_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot2_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot2_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot2_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot2_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot2_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot2_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae2_slot2_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae2_slot2_get, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae2_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae2_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae2_slot2_get, + Field_fld_ae_sem_multiply_q1_Slot_ae2_slot2_get, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae2_slot2_get, + Field_fld_ae_sem_reduction_sort_v_Slot_ae2_slot2_get, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_isel_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_ss_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_vu_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_vp_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_vs_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_vt_Slot_ae2_slot2_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae2_slot2_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae2_slot2_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_17_0_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_26_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_28_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vp_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vq_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae2_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot2_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot2_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot2_set, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae2_slot2_set, + Field_fld_ae_sem_pks_pos_Slot_ae2_slot2_set, + Field_fld_ae_sem_pks_s_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot2_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot2_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot2_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot2_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot2_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot2_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae2_slot2_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae2_slot2_set, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae2_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae2_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae2_slot2_set, + Field_fld_ae_sem_multiply_q1_Slot_ae2_slot2_set, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae2_slot2_set, + Field_fld_ae_sem_reduction_sort_v_Slot_ae2_slot2_set, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_isel_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_ss_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_vu_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_vp_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_vs_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_vt_Slot_ae2_slot2_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae2_slot2_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae2_slot2_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_17_0_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_26_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_28_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vp_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vq_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae3_slot0_get_field_fns[] = { + Field_t_Slot_ae3_slot0_get, + 0, + Field_bbi_Slot_ae3_slot0_get, + 0, + Field_imm8_Slot_ae3_slot0_get, + Field_s_Slot_ae3_slot0_get, + Field_s8_Slot_ae3_slot0_get, + 0, + Field_imm12b_Slot_ae3_slot0_get, + Field_imm16_Slot_ae3_slot0_get, + 0, + 0, + Field_offset_Slot_ae3_slot0_get, + 0, + 0, + Field_op2_Slot_ae3_slot0_get, + Field_r_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot0_get, + Field_sal_Slot_ae3_slot0_get, + Field_sargt_Slot_ae3_slot0_get, + 0, + Field_sas_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae3_slot0_get, + 0, + Field_r2_Slot_ae3_slot0_get, + Field_t4_Slot_ae3_slot0_get, + Field_s4_Slot_ae3_slot0_get, + Field_r4_Slot_ae3_slot0_get, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae3_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae3_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae3_slot0_get, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae3_slot0_get, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_su_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_vu_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae3_slot0_get, + Field_fld_ae_sem_shift_d_Slot_ae3_slot0_get, + Field_fld_ae_sem_shift_d0_Slot_ae3_slot0_get, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_16_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_7_2_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_9_4_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot0_get, + Field_fld_ae_sem_sb_loads_stores_iba2_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae3_slot0_set_field_fns[] = { + Field_t_Slot_ae3_slot0_set, + 0, + Field_bbi_Slot_ae3_slot0_set, + 0, + Field_imm8_Slot_ae3_slot0_set, + Field_s_Slot_ae3_slot0_set, + Field_s8_Slot_ae3_slot0_set, + 0, + Field_imm12b_Slot_ae3_slot0_set, + Field_imm16_Slot_ae3_slot0_set, + 0, + 0, + Field_offset_Slot_ae3_slot0_set, + 0, + 0, + Field_op2_Slot_ae3_slot0_set, + Field_r_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot0_set, + Field_sal_Slot_ae3_slot0_set, + Field_sargt_Slot_ae3_slot0_set, + 0, + Field_sas_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae3_slot0_set, + 0, + Field_r2_Slot_ae3_slot0_set, + Field_t4_Slot_ae3_slot0_set, + Field_s4_Slot_ae3_slot0_set, + Field_r4_Slot_ae3_slot0_set, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae3_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae3_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae3_slot0_set, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae3_slot0_set, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_su_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_vu_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae3_slot0_set, + Field_fld_ae_sem_shift_d_Slot_ae3_slot0_set, + Field_fld_ae_sem_shift_d0_Slot_ae3_slot0_set, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_16_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_7_2_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_9_4_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot0_set, + Field_fld_ae_sem_sb_loads_stores_iba2_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae3_slot1_get_field_fns[] = { + Field_t_Slot_ae3_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae3_slot1_get, + Field_s_Slot_ae3_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae3_slot1_get, + Field_r_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot1_get, + Field_sal_Slot_ae3_slot1_get, + Field_sargt_Slot_ae3_slot1_get, + 0, + Field_sas_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot1_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot1_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot1_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot1_get, + 0, + Field_fld_ae3_slot1_23_0_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_11_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_17_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_19_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_9_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_3_1_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae3_slot1_set_field_fns[] = { + Field_t_Slot_ae3_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae3_slot1_set, + Field_s_Slot_ae3_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae3_slot1_set, + Field_r_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot1_set, + Field_sal_Slot_ae3_slot1_set, + Field_sargt_Slot_ae3_slot1_set, + 0, + Field_sas_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot1_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot1_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot1_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot1_set, + 0, + Field_fld_ae3_slot1_23_0_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_11_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_17_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_19_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_9_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_3_1_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae5_slot0_get_field_fns[] = { + Field_t_Slot_ae5_slot0_get, + 0, + Field_bbi_Slot_ae5_slot0_get, + 0, + Field_imm8_Slot_ae5_slot0_get, + Field_s_Slot_ae5_slot0_get, + Field_s8_Slot_ae5_slot0_get, + 0, + Field_imm12b_Slot_ae5_slot0_get, + Field_imm16_Slot_ae5_slot0_get, + 0, + 0, + Field_offset_Slot_ae5_slot0_get, + 0, + 0, + Field_op2_Slot_ae5_slot0_get, + Field_r_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae5_slot0_get, + Field_sal_Slot_ae5_slot0_get, + Field_sargt_Slot_ae5_slot0_get, + 0, + Field_sas_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae5_slot0_get, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae5_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot0_get, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae5_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae5_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae5_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae5_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae5_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae5_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_su_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_vu_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_x_Slot_ae5_slot0_get, + Field_fld_ae_sem_pks_d_Slot_ae5_slot0_get, + Field_fld_ae_sem_pks_pos_Slot_ae5_slot0_get, + Field_fld_ae_sem_pks_s_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae5_slot0_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot0_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_ardecnorm16_ar_u_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_12_6_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_17_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_19_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_6_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_7_0_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get, + Field_fld_ae_sem_lb_db_ops_ar_u_Slot_ae5_slot0_get, + Field_fld_ae_sem_lb_db_ops_iba_Slot_ae5_slot0_get, + Field_fld_ae_sem_rng_a_Slot_ae5_slot0_get, + Field_fld_ae_sem_rng_art_Slot_ae5_slot0_get, + Field_fld_ae_sem_rng_i2_Slot_ae5_slot0_get, + Field_fld_ae_sem_rng_imm2_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae5_slot0_set_field_fns[] = { + Field_t_Slot_ae5_slot0_set, + 0, + Field_bbi_Slot_ae5_slot0_set, + 0, + Field_imm8_Slot_ae5_slot0_set, + Field_s_Slot_ae5_slot0_set, + Field_s8_Slot_ae5_slot0_set, + 0, + Field_imm12b_Slot_ae5_slot0_set, + Field_imm16_Slot_ae5_slot0_set, + 0, + 0, + Field_offset_Slot_ae5_slot0_set, + 0, + 0, + Field_op2_Slot_ae5_slot0_set, + Field_r_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae5_slot0_set, + Field_sal_Slot_ae5_slot0_set, + Field_sargt_Slot_ae5_slot0_set, + 0, + Field_sas_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae5_slot0_set, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae5_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot0_set, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae5_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae5_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae5_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae5_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae5_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae5_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_su_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_vu_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_x_Slot_ae5_slot0_set, + Field_fld_ae_sem_pks_d_Slot_ae5_slot0_set, + Field_fld_ae_sem_pks_pos_Slot_ae5_slot0_set, + Field_fld_ae_sem_pks_s_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae5_slot0_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot0_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_ardecnorm16_ar_u_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_12_6_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_17_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_19_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_6_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_7_0_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_set, + Field_fld_ae_sem_lb_db_ops_ar_u_Slot_ae5_slot0_set, + Field_fld_ae_sem_lb_db_ops_iba_Slot_ae5_slot0_set, + Field_fld_ae_sem_rng_a_Slot_ae5_slot0_set, + Field_fld_ae_sem_rng_art_Slot_ae5_slot0_set, + Field_fld_ae_sem_rng_i2_Slot_ae5_slot0_set, + Field_fld_ae_sem_rng_imm2_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae5_slot1_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot1_1_0_Slot_ae5_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae5_slot1_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot1_1_0_Slot_ae5_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae5_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot2_get, + 0, + Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot2_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot2_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae5_slot2_get, + Field_fld_ae_sem_pks_pos_Slot_ae5_slot2_get, + Field_fld_ae_sem_pks_s_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae5_slot2_get, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae5_slot2_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae5_slot2_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae5_slot2_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae5_slot2_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae5_slot2_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae5_slot2_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae5_slot2_get, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae5_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae5_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae5_slot2_get, + Field_fld_ae_sem_multiply_q1_Slot_ae5_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae5_slot2_get, + Field_fld_ae_sem_select_ss_Slot_ae5_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae5_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae5_slot2_get, + 0, + Field_fld_ae_sem_spaddsub_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae5_slot2_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae5_slot2_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae5_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_spfma_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_spfma_vs_Slot_ae5_slot2_get, + Field_fld_ae_sem_spfma_vt_Slot_ae5_slot2_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae5_slot2_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae5_slot2_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_14_5_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_24_0_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_9_7_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae5_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot2_set, + 0, + Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot2_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot2_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae5_slot2_set, + Field_fld_ae_sem_pks_pos_Slot_ae5_slot2_set, + Field_fld_ae_sem_pks_s_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae5_slot2_set, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae5_slot2_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae5_slot2_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae5_slot2_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae5_slot2_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae5_slot2_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae5_slot2_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae5_slot2_set, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae5_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae5_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae5_slot2_set, + Field_fld_ae_sem_multiply_q1_Slot_ae5_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae5_slot2_set, + Field_fld_ae_sem_select_ss_Slot_ae5_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae5_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae5_slot2_set, + 0, + Field_fld_ae_sem_spaddsub_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae5_slot2_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae5_slot2_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae5_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_spfma_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_spfma_vs_Slot_ae5_slot2_set, + Field_fld_ae_sem_spfma_vt_Slot_ae5_slot2_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae5_slot2_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae5_slot2_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_14_5_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_24_0_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_9_7_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot0_get_field_fns[] = { + Field_t_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae6_slot0_get, + 0, + Field_r2_Slot_ae6_slot0_get, + Field_t4_Slot_ae6_slot0_get, + 0, + Field_r4_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot0_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot0_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot0_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot0_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot0_get, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot0_get, + Field_fld_ae_sem_pks_d_Slot_ae6_slot0_get, + Field_fld_ae_sem_pks_pos_Slot_ae6_slot0_get, + Field_fld_ae_sem_pks_s_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_5_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_7_4_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot0_set_field_fns[] = { + Field_t_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae6_slot0_set, + 0, + Field_r2_Slot_ae6_slot0_set, + Field_t4_Slot_ae6_slot0_set, + 0, + Field_r4_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot0_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot0_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot0_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot0_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot0_set, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot0_set, + Field_fld_ae_sem_pks_d_Slot_ae6_slot0_set, + Field_fld_ae_sem_pks_pos_Slot_ae6_slot0_set, + Field_fld_ae_sem_pks_s_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_5_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_7_4_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot1_get_field_fns[] = { + Field_t_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + Field_s_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae6_slot1_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae6_slot1_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot1_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot1_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot1_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae6_slot1_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae6_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae6_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot1_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae6_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae6_slot1_get, + Field_fld_ae_sem_shift_d_Slot_ae6_slot1_get, + Field_fld_ae_sem_shift_d0_Slot_ae6_slot1_get, + 0, + Field_fld_ae_sem_shift_da_Slot_ae6_slot1_get, + Field_fld_ae_sem_shift_i16_Slot_ae6_slot1_get, + Field_fld_ae_sem_shift_i32_Slot_ae6_slot1_get, + Field_fld_ae_sem_shift_i64_Slot_ae6_slot1_get, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_21_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_3_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_2_0_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_9_5_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot1_set_field_fns[] = { + Field_t_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + Field_s_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae6_slot1_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae6_slot1_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot1_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot1_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot1_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae6_slot1_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae6_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae6_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot1_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae6_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae6_slot1_set, + Field_fld_ae_sem_shift_d_Slot_ae6_slot1_set, + Field_fld_ae_sem_shift_d0_Slot_ae6_slot1_set, + 0, + Field_fld_ae_sem_shift_da_Slot_ae6_slot1_set, + Field_fld_ae_sem_shift_i16_Slot_ae6_slot1_set, + Field_fld_ae_sem_shift_i32_Slot_ae6_slot1_set, + Field_fld_ae_sem_shift_i64_Slot_ae6_slot1_set, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_21_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_3_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_2_0_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_9_5_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot2_get_field_fns[] = { + Field_t_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae6_slot2_get, + 0, + 0, + Field_t4_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot2_get, + 0, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot2_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae6_slot2_get, + Field_fld_ae_sem_pks_pos_Slot_ae6_slot2_get, + Field_fld_ae_sem_pks_s_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae6_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae6_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_24_0_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_24_10_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_24_20_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot2_set_field_fns[] = { + Field_t_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae6_slot2_set, + 0, + 0, + Field_t4_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot2_set, + 0, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot2_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae6_slot2_set, + Field_fld_ae_sem_pks_pos_Slot_ae6_slot2_set, + Field_fld_ae_sem_pks_s_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae6_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae6_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_24_0_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_24_10_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_24_20_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r2_Slot_ae6_slot3_get, + 0, + 0, + Field_r4_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot3_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot3_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot3_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot3_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot3_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot3_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae6_slot3_get, + Field_fld_ae_sem_multiply_d2_Slot_ae6_slot3_get, + Field_fld_ae_sem_multiply_q0_Slot_ae6_slot3_get, + Field_fld_ae_sem_multiply_q1_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae6_slot3_get, + Field_fld_ae_sem_multiply_d3_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_12_0_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_14_0_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_24_20_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_37_13_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r2_Slot_ae6_slot3_set, + 0, + 0, + Field_r4_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot3_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot3_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot3_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot3_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot3_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot3_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae6_slot3_set, + Field_fld_ae_sem_multiply_d2_Slot_ae6_slot3_set, + Field_fld_ae_sem_multiply_q0_Slot_ae6_slot3_set, + Field_fld_ae_sem_multiply_q1_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae6_slot3_set, + Field_fld_ae_sem_multiply_d3_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_12_0_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_14_0_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_24_20_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_37_13_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot0_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_12_6_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_23_0_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot0_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_12_6_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_23_0_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot1_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_12_6_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_23_0_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot1_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_12_6_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_23_0_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae7_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae7_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae7_slot2_get, + Field_fld_ae_sem_multiply_q1_Slot_ae7_slot2_get, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae7_slot2_get, + Field_fld_ae_sem_reduction_sort_v_Slot_ae7_slot2_get, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_isel_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_ss_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_vu_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae7_slot2_get, + Field_fld_ae_sem_multiply_d3_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot2_11_0_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_14_10_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_36_12_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae7_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae7_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae7_slot2_set, + Field_fld_ae_sem_multiply_q1_Slot_ae7_slot2_set, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae7_slot2_set, + Field_fld_ae_sem_reduction_sort_v_Slot_ae7_slot2_set, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_isel_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_ss_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_vu_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae7_slot2_set, + Field_fld_ae_sem_multiply_d3_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot2_11_0_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_14_10_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_36_12_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae7_slot3_get, + Field_fld_ae_sem_multiply_d2_Slot_ae7_slot3_get, + Field_fld_ae_sem_multiply_q0_Slot_ae7_slot3_get, + Field_fld_ae_sem_multiply_q1_Slot_ae7_slot3_get, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae7_slot3_get, + Field_fld_ae_sem_select_ss_Slot_ae7_slot3_get, + Field_fld_ae_sem_select_vr_Slot_ae7_slot3_get, + Field_fld_ae_sem_select_vs_Slot_ae7_slot3_get, + Field_fld_ae_sem_select_vt_Slot_ae7_slot3_get, + Field_fld_ae_sem_select_vu_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae7_slot3_get, + Field_fld_ae_sem_multiply_d3_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot3_10_0_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_24_10_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_35_11_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_4_0_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae7_slot3_set, + Field_fld_ae_sem_multiply_d2_Slot_ae7_slot3_set, + Field_fld_ae_sem_multiply_q0_Slot_ae7_slot3_set, + Field_fld_ae_sem_multiply_q1_Slot_ae7_slot3_set, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae7_slot3_set, + Field_fld_ae_sem_select_ss_Slot_ae7_slot3_set, + Field_fld_ae_sem_select_vr_Slot_ae7_slot3_set, + Field_fld_ae_sem_select_vs_Slot_ae7_slot3_set, + Field_fld_ae_sem_select_vt_Slot_ae7_slot3_set, + Field_fld_ae_sem_select_vu_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae7_slot3_set, + Field_fld_ae_sem_multiply_d3_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot3_10_0_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_24_10_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_35_11_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_4_0_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae8_slot0_get_field_fns[] = { + Field_t_Slot_ae8_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae8_slot0_get, + Field_s_Slot_ae8_slot0_get, + Field_s8_Slot_ae8_slot0_get, + 0, + Field_imm12b_Slot_ae8_slot0_get, + Field_imm16_Slot_ae8_slot0_get, + 0, + 0, + Field_offset_Slot_ae8_slot0_get, + 0, + 0, + Field_op2_Slot_ae8_slot0_get, + Field_r_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae8_slot0_get, + Field_sal_Slot_ae8_slot0_get, + Field_sargt_Slot_ae8_slot0_get, + 0, + Field_sas_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae8_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae8_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae8_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot0_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_su_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae8_slot0_get, + Field_fld_ae_sem_shift_d_Slot_ae8_slot0_get, + Field_fld_ae_sem_shift_d0_Slot_ae8_slot0_get, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae8_slot0_get, + Field_fld_ae_sem_shift_i32_Slot_ae8_slot0_get, + Field_fld_ae_sem_shift_i64_Slot_ae8_slot0_get, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_13_13_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_17_8_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_21_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_22_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_23_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_7_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_9_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_6_0_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_7_5_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_8_0_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae8_slot0_set_field_fns[] = { + Field_t_Slot_ae8_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae8_slot0_set, + Field_s_Slot_ae8_slot0_set, + Field_s8_Slot_ae8_slot0_set, + 0, + Field_imm12b_Slot_ae8_slot0_set, + Field_imm16_Slot_ae8_slot0_set, + 0, + 0, + Field_offset_Slot_ae8_slot0_set, + 0, + 0, + Field_op2_Slot_ae8_slot0_set, + Field_r_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae8_slot0_set, + Field_sal_Slot_ae8_slot0_set, + Field_sargt_Slot_ae8_slot0_set, + 0, + Field_sas_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae8_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae8_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae8_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot0_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_su_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae8_slot0_set, + Field_fld_ae_sem_shift_d_Slot_ae8_slot0_set, + Field_fld_ae_sem_shift_d0_Slot_ae8_slot0_set, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae8_slot0_set, + Field_fld_ae_sem_shift_i32_Slot_ae8_slot0_set, + Field_fld_ae_sem_shift_i64_Slot_ae8_slot0_set, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_13_13_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_17_8_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_21_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_22_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_23_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_7_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_9_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_6_0_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_7_5_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_8_0_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae8_slot1_get_field_fns[] = { + Field_t_Slot_ae8_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae8_slot1_get, + Field_s_Slot_ae8_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae8_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae8_slot1_get, + Field_r_Slot_ae8_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae8_slot1_get, + Field_sal_Slot_ae8_slot1_get, + Field_sargt_Slot_ae8_slot1_get, + 0, + Field_sas_Slot_ae8_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot1_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_17_15_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_22_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_23_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_5_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_9_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_4_0_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae8_slot1_set_field_fns[] = { + Field_t_Slot_ae8_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae8_slot1_set, + Field_s_Slot_ae8_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae8_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae8_slot1_set, + Field_r_Slot_ae8_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae8_slot1_set, + Field_sal_Slot_ae8_slot1_set, + Field_sargt_Slot_ae8_slot1_set, + 0, + Field_sas_Slot_ae8_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot1_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_17_15_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_22_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_23_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_5_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_9_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_4_0_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae8_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_19_15_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_33_25_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_33_9_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_8_0_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_c0_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_c1_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_c2_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_c3_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_q0_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_q1_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_q2_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_q3_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_v0_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_v1_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_v2_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_v3_Slot_ae8_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae8_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_19_15_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_33_25_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_33_9_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_8_0_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_c0_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_c1_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_c2_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_c3_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_q0_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_q1_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_q2_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_q3_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_v0_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_v1_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_v2_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_v3_Slot_ae8_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae9_slot0_get_field_fns[] = { + Field_t_Slot_ae9_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae9_slot0_get, + Field_s_Slot_ae9_slot0_get, + Field_s8_Slot_ae9_slot0_get, + 0, + Field_imm12b_Slot_ae9_slot0_get, + Field_imm16_Slot_ae9_slot0_get, + 0, + 0, + Field_offset_Slot_ae9_slot0_get, + 0, + 0, + Field_op2_Slot_ae9_slot0_get, + Field_r_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae9_slot0_get, + Field_sal_Slot_ae9_slot0_get, + Field_sargt_Slot_ae9_slot0_get, + 0, + Field_sas_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r2_Slot_ae9_slot0_get, + 0, + Field_s4_Slot_ae9_slot0_get, + Field_r4_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v0_Slot_ae9_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae9_slot0_get, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae9_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae9_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae9_slot0_get, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae9_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_su_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae9_slot0_get, + Field_fld_ae_sem_sp32cvt_art_Slot_ae9_slot0_get, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae9_slot0_get, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae9_slot0_get, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae9_slot0_get, + Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot0_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot0_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_17_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_19_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_22_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_3_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_2_0_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_7_6_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae9_slot0_set_field_fns[] = { + Field_t_Slot_ae9_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae9_slot0_set, + Field_s_Slot_ae9_slot0_set, + Field_s8_Slot_ae9_slot0_set, + 0, + Field_imm12b_Slot_ae9_slot0_set, + Field_imm16_Slot_ae9_slot0_set, + 0, + 0, + Field_offset_Slot_ae9_slot0_set, + 0, + 0, + Field_op2_Slot_ae9_slot0_set, + Field_r_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae9_slot0_set, + Field_sal_Slot_ae9_slot0_set, + Field_sargt_Slot_ae9_slot0_set, + 0, + Field_sas_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r2_Slot_ae9_slot0_set, + 0, + Field_s4_Slot_ae9_slot0_set, + Field_r4_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v0_Slot_ae9_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae9_slot0_set, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae9_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae9_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae9_slot0_set, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae9_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_su_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae9_slot0_set, + Field_fld_ae_sem_sp32cvt_art_Slot_ae9_slot0_set, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae9_slot0_set, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae9_slot0_set, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae9_slot0_set, + Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot0_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot0_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_17_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_19_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_22_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_3_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_2_0_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_7_6_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae9_slot1_get_field_fns[] = { + Field_t_Slot_ae9_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae9_slot1_get, + Field_s_Slot_ae9_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae9_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae9_slot1_get, + Field_r_Slot_ae9_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae9_slot1_get, + Field_sal_Slot_ae9_slot1_get, + Field_sargt_Slot_ae9_slot1_get, + 0, + Field_sas_Slot_ae9_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_1_0_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_17_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_2_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_22_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_23_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_9_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_3_2_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae9_slot1_set_field_fns[] = { + Field_t_Slot_ae9_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae9_slot1_set, + Field_s_Slot_ae9_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae9_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae9_slot1_set, + Field_r_Slot_ae9_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae9_slot1_set, + Field_sal_Slot_ae9_slot1_set, + Field_sargt_Slot_ae9_slot1_set, + 0, + Field_sas_Slot_ae9_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_1_0_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_17_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_2_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_22_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_23_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_9_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_3_2_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae9_slot2_get_field_fns[] = { + Field_t_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae9_slot2_get, + 0, + 0, + Field_t4_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot2_get, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot2_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot2_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot2_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot2_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae9_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae9_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae9_slot2_get, + Field_fld_ae_sem_select_vu_Slot_ae9_slot2_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot2_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot2_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_vp_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_vs_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_vt_Slot_ae9_slot2_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot2_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot2_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spaddsub_vp_Slot_ae9_slot2_get, + Field_fld_ae_sem_spaddsub_vq_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_9_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_8_0_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpfma_vp_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpfma_vu_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_vu_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae9_slot2_set_field_fns[] = { + Field_t_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae9_slot2_set, + 0, + 0, + Field_t4_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot2_set, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot2_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot2_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot2_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot2_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae9_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae9_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae9_slot2_set, + Field_fld_ae_sem_select_vu_Slot_ae9_slot2_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot2_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot2_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_vp_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_vs_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_vt_Slot_ae9_slot2_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot2_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot2_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spaddsub_vp_Slot_ae9_slot2_set, + Field_fld_ae_sem_spaddsub_vq_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_9_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_8_0_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpfma_vp_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpfma_vu_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_vu_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae9_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot3_get, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot3_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot3_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot3_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot3_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot3_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot3_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot3_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot3_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot3_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae9_slot3_get, + Field_fld_ae_sem_select_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_select_vs_Slot_ae9_slot3_get, + Field_fld_ae_sem_select_vt_Slot_ae9_slot3_get, + Field_fld_ae_sem_select_vu_Slot_ae9_slot3_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot3_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot3_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_vp_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_vs_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_vt_Slot_ae9_slot3_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot3_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot3_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spfma_vu_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_7_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_4_4_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_6_0_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae9_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot3_set, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot3_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot3_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot3_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot3_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot3_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot3_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot3_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot3_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot3_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae9_slot3_set, + Field_fld_ae_sem_select_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_select_vs_Slot_ae9_slot3_set, + Field_fld_ae_sem_select_vt_Slot_ae9_slot3_set, + Field_fld_ae_sem_select_vu_Slot_ae9_slot3_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot3_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot3_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_vp_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_vs_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_vt_Slot_ae9_slot3_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot3_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot3_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spfma_vu_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_7_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_4_4_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_6_0_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae10_slot0_get_field_fns[] = { + Field_t_Slot_ae10_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae10_slot0_get, + Field_s_Slot_ae10_slot0_get, + Field_s8_Slot_ae10_slot0_get, + 0, + Field_imm12b_Slot_ae10_slot0_get, + Field_imm16_Slot_ae10_slot0_get, + 0, + 0, + Field_offset_Slot_ae10_slot0_get, + 0, + 0, + Field_op2_Slot_ae10_slot0_get, + Field_r_Slot_ae10_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae10_slot0_get, + Field_sal_Slot_ae10_slot0_get, + Field_sargt_Slot_ae10_slot0_get, + 0, + Field_sas_Slot_ae10_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae10_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot0_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_17_8_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_0_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_17_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_7_6_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae10_slot0_set_field_fns[] = { + Field_t_Slot_ae10_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae10_slot0_set, + Field_s_Slot_ae10_slot0_set, + Field_s8_Slot_ae10_slot0_set, + 0, + Field_imm12b_Slot_ae10_slot0_set, + Field_imm16_Slot_ae10_slot0_set, + 0, + 0, + Field_offset_Slot_ae10_slot0_set, + 0, + 0, + Field_op2_Slot_ae10_slot0_set, + Field_r_Slot_ae10_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae10_slot0_set, + Field_sal_Slot_ae10_slot0_set, + Field_sargt_Slot_ae10_slot0_set, + 0, + Field_sas_Slot_ae10_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae10_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot0_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_17_8_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_0_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_17_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_7_6_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae10_slot1_get_field_fns[] = { + Field_t_Slot_ae10_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae10_slot1_get, + Field_s_Slot_ae10_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae10_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae10_slot1_get, + Field_r_Slot_ae10_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae10_slot1_get, + Field_sal_Slot_ae10_slot1_get, + Field_sargt_Slot_ae10_slot1_get, + 0, + Field_sas_Slot_ae10_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae10_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot1_0_0_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_1_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_17_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_22_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_23_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_9_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_3_2_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae10_slot1_set_field_fns[] = { + Field_t_Slot_ae10_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae10_slot1_set, + Field_s_Slot_ae10_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae10_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae10_slot1_set, + Field_r_Slot_ae10_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae10_slot1_set, + Field_sal_Slot_ae10_slot1_set, + Field_sargt_Slot_ae10_slot1_set, + 0, + Field_sas_Slot_ae10_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae10_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot1_0_0_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_1_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_17_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_22_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_23_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_9_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_3_2_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae10_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot2_get, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot2_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot2_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot2_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot2_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae10_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae10_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae10_slot2_get, + Field_fld_ae_sem_select_vu_Slot_ae10_slot2_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot2_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot2_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vp_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vs_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vt_Slot_ae10_slot2_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot2_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot2_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spaddsub_vp_Slot_ae10_slot2_get, + Field_fld_ae_sem_spaddsub_vq_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vu_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_10_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vq_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae10_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot2_set, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot2_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot2_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot2_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot2_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae10_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae10_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae10_slot2_set, + Field_fld_ae_sem_select_vu_Slot_ae10_slot2_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot2_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot2_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vp_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vs_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vt_Slot_ae10_slot2_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot2_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot2_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spaddsub_vp_Slot_ae10_slot2_set, + Field_fld_ae_sem_spaddsub_vq_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vu_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_10_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vq_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae10_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae10_slot3_get, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot3_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae10_slot3_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae10_slot3_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot3_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot3_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot3_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot3_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot3_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot3_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae10_slot3_get, + Field_fld_ae_sem_select_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_select_vs_Slot_ae10_slot3_get, + Field_fld_ae_sem_select_vt_Slot_ae10_slot3_get, + Field_fld_ae_sem_select_vu_Slot_ae10_slot3_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot3_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot3_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vp_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vs_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vt_Slot_ae10_slot3_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot3_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot3_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot3_get, + Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vu_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vq_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_10_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_4_4_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae10_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae10_slot3_set, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot3_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae10_slot3_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae10_slot3_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot3_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot3_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot3_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot3_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot3_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot3_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae10_slot3_set, + Field_fld_ae_sem_select_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_select_vs_Slot_ae10_slot3_set, + Field_fld_ae_sem_select_vt_Slot_ae10_slot3_set, + Field_fld_ae_sem_select_vu_Slot_ae10_slot3_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot3_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot3_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vp_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vs_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vt_Slot_ae10_slot3_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot3_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot3_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot3_set, + Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vu_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vq_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_10_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_4_4_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot0_get_field_fns[] = { + Field_t_Slot_ae4_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae4_slot0_get, + Field_s_Slot_ae4_slot0_get, + Field_s8_Slot_ae4_slot0_get, + 0, + Field_imm12b_Slot_ae4_slot0_get, + Field_imm16_Slot_ae4_slot0_get, + 0, + 0, + Field_offset_Slot_ae4_slot0_get, + 0, + 0, + Field_op2_Slot_ae4_slot0_get, + Field_r_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae4_slot0_get, + Field_sal_Slot_ae4_slot0_get, + Field_sargt_Slot_ae4_slot0_get, + 0, + Field_sas_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot0_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot0_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot0_22_0_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_17_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_20_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_3_1_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot0_set_field_fns[] = { + Field_t_Slot_ae4_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae4_slot0_set, + Field_s_Slot_ae4_slot0_set, + Field_s8_Slot_ae4_slot0_set, + 0, + Field_imm12b_Slot_ae4_slot0_set, + Field_imm16_Slot_ae4_slot0_set, + 0, + 0, + Field_offset_Slot_ae4_slot0_set, + 0, + 0, + Field_op2_Slot_ae4_slot0_set, + Field_r_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae4_slot0_set, + Field_sal_Slot_ae4_slot0_set, + Field_sargt_Slot_ae4_slot0_set, + 0, + Field_sas_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot0_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot0_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot0_22_0_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_17_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_20_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_3_1_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot1_get_field_fns[] = { + Field_t_Slot_ae4_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae4_slot1_get, + Field_s_Slot_ae4_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae4_slot1_get, + Field_r_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae4_slot1_get, + Field_sal_Slot_ae4_slot1_get, + Field_sargt_Slot_ae4_slot1_get, + 0, + Field_sas_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot1_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot1_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot1_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot1_22_0_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_17_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_3_1_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot1_set_field_fns[] = { + Field_t_Slot_ae4_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae4_slot1_set, + Field_s_Slot_ae4_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae4_slot1_set, + Field_r_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae4_slot1_set, + Field_sal_Slot_ae4_slot1_set, + Field_sargt_Slot_ae4_slot1_set, + 0, + Field_sas_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot1_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot1_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot1_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot1_22_0_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_17_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_3_1_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot2_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot2_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot2_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot2_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae4_slot2_get, + Field_fld_ae_sem_pks_pos_Slot_ae4_slot2_get, + Field_fld_ae_sem_pks_s_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae4_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae4_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot2_23_0_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_23_17_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_4_0_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot2_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot2_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot2_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot2_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae4_slot2_set, + Field_fld_ae_sem_pks_pos_Slot_ae4_slot2_set, + Field_fld_ae_sem_pks_s_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae4_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae4_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot2_23_0_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_23_17_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_4_0_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot3_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot3_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot3_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae4_slot3_get, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot3_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae4_slot3_get, + Field_fld_ae_sem_multiply_d2_Slot_ae4_slot3_get, + Field_fld_ae_sem_multiply_q0_Slot_ae4_slot3_get, + Field_fld_ae_sem_multiply_q1_Slot_ae4_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae4_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot3_14_10_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_19_19_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_19_5_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_27_20_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_27_3_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_2_0_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot3_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot3_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot3_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae4_slot3_set, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot3_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae4_slot3_set, + Field_fld_ae_sem_multiply_d2_Slot_ae4_slot3_set, + Field_fld_ae_sem_multiply_q0_Slot_ae4_slot3_set, + Field_fld_ae_sem_multiply_q1_Slot_ae4_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae4_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot3_14_10_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_19_19_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_19_5_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_27_20_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_27_3_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_2_0_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot4_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot4_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot4_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot4_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot4_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot4_22_0_Slot_ae4_slot4_get, + Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get, + Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get, + Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot4_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot4_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot4_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot4_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot4_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot4_22_0_Slot_ae4_slot4_set, + Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_set, + Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_set, + Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_slot_internal slots[] = { + { "Inst", "x24", 0, + Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, + Slot_inst_get_field_fns, Slot_inst_set_field_fns, + Slot_inst_decode, "nop" }, + { "Inst16a", "x16a", 0, + Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, + Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, + Slot_inst16a_decode, "" }, + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, + Slot_inst16b_decode, "nop.n" }, + { "ae_slot0", "ae_format", 0, + Slot_ae_format_Format_ae_slot0_4_get, Slot_ae_format_Format_ae_slot0_4_set, + Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns, + Slot_ae_slot0_decode, "nop" }, + { "ae_slot1", "ae_format", 1, + Slot_ae_format_Format_ae_slot1_72_get, Slot_ae_format_Format_ae_slot1_72_set, + Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns, + Slot_ae_slot1_decode, "nop" }, + { "ae_slot2", "ae_format", 2, + Slot_ae_format_Format_ae_slot2_16_get, Slot_ae_format_Format_ae_slot2_16_set, + Slot_ae_slot2_get_field_fns, Slot_ae_slot2_set_field_fns, + Slot_ae_slot2_decode, "nop" }, + { "ae_slot3", "ae_format", 3, + Slot_ae_format_Format_ae_slot3_45_get, Slot_ae_format_Format_ae_slot3_45_set, + Slot_ae_slot3_get_field_fns, Slot_ae_slot3_set_field_fns, + Slot_ae_slot3_decode, "nop" }, + { "ae2_slot0", "ae_format_2", 0, + Slot_ae_format_2_Format_ae2_slot0_4_get, Slot_ae_format_2_Format_ae2_slot0_4_set, + Slot_ae2_slot0_get_field_fns, Slot_ae2_slot0_set_field_fns, + Slot_ae2_slot0_decode, "nop" }, + { "ae2_slot1", "ae_format_2", 1, + Slot_ae_format_2_Format_ae2_slot1_12_get, Slot_ae_format_2_Format_ae2_slot1_12_set, + Slot_ae2_slot1_get_field_fns, Slot_ae2_slot1_set_field_fns, + Slot_ae2_slot1_decode, "nop" }, + { "ae2_slot2", "ae_format_2", 2, + Slot_ae_format_2_Format_ae2_slot2_16_get, Slot_ae_format_2_Format_ae2_slot2_16_set, + Slot_ae2_slot2_get_field_fns, Slot_ae2_slot2_set_field_fns, + Slot_ae2_slot2_decode, "nop" }, + { "ae3_slot0", "ae_format_3", 0, + Slot_ae_format_3_Format_ae3_slot0_4_get, Slot_ae_format_3_Format_ae3_slot0_4_set, + Slot_ae3_slot0_get_field_fns, Slot_ae3_slot0_set_field_fns, + Slot_ae3_slot0_decode, "nop" }, + { "ae3_slot1", "ae_format_3", 1, + Slot_ae_format_3_Format_ae3_slot1_12_get, Slot_ae_format_3_Format_ae3_slot1_12_set, + Slot_ae3_slot1_get_field_fns, Slot_ae3_slot1_set_field_fns, + Slot_ae3_slot1_decode, "nop" }, + { "ae5_slot0", "ae_format_5", 0, + Slot_ae_format_5_Format_ae5_slot0_4_get, Slot_ae_format_5_Format_ae5_slot0_4_set, + Slot_ae5_slot0_get_field_fns, Slot_ae5_slot0_set_field_fns, + Slot_ae5_slot0_decode, "nop" }, + { "ae5_slot1", "ae_format_5", 1, + Slot_ae_format_5_Format_ae5_slot1_56_get, Slot_ae_format_5_Format_ae5_slot1_56_set, + Slot_ae5_slot1_get_field_fns, Slot_ae5_slot1_set_field_fns, + Slot_ae5_slot1_decode, "nop" }, + { "ae5_slot2", "ae_format_5", 2, + Slot_ae_format_5_Format_ae5_slot2_16_get, Slot_ae_format_5_Format_ae5_slot2_16_set, + Slot_ae5_slot2_get_field_fns, Slot_ae5_slot2_set_field_fns, + Slot_ae5_slot2_decode, "nop" }, + { "ae6_slot0", "ae_format_6", 0, + Slot_ae_format_6_Format_ae6_slot0_4_get, Slot_ae_format_6_Format_ae6_slot0_4_set, + Slot_ae6_slot0_get_field_fns, Slot_ae6_slot0_set_field_fns, + Slot_ae6_slot0_decode, "nop" }, + { "ae6_slot1", "ae_format_6", 1, + Slot_ae_format_6_Format_ae6_slot1_57_get, Slot_ae_format_6_Format_ae6_slot1_57_set, + Slot_ae6_slot1_get_field_fns, Slot_ae6_slot1_set_field_fns, + Slot_ae6_slot1_decode, "nop" }, + { "ae6_slot2", "ae_format_6", 2, + Slot_ae_format_6_Format_ae6_slot2_16_get, Slot_ae_format_6_Format_ae6_slot2_16_set, + Slot_ae6_slot2_get_field_fns, Slot_ae6_slot2_set_field_fns, + Slot_ae6_slot2_decode, "nop" }, + { "ae6_slot3", "ae_format_6", 3, + Slot_ae_format_6_Format_ae6_slot3_8_get, Slot_ae_format_6_Format_ae6_slot3_8_set, + Slot_ae6_slot3_get_field_fns, Slot_ae6_slot3_set_field_fns, + Slot_ae6_slot3_decode, "nop" }, + { "ae7_slot0", "ae_format_7", 0, + Slot_ae_format_7_Format_ae7_slot0_4_get, Slot_ae_format_7_Format_ae7_slot0_4_set, + Slot_ae7_slot0_get_field_fns, Slot_ae7_slot0_set_field_fns, + Slot_ae7_slot0_decode, "nop" }, + { "ae7_slot1", "ae_format_7", 1, + Slot_ae_format_7_Format_ae7_slot1_72_get, Slot_ae_format_7_Format_ae7_slot1_72_set, + Slot_ae7_slot1_get_field_fns, Slot_ae7_slot1_set_field_fns, + Slot_ae7_slot1_decode, "nop" }, + { "ae7_slot2", "ae_format_7", 2, + Slot_ae_format_7_Format_ae7_slot2_16_get, Slot_ae_format_7_Format_ae7_slot2_16_set, + Slot_ae7_slot2_get_field_fns, Slot_ae7_slot2_set_field_fns, + Slot_ae7_slot2_decode, "nop" }, + { "ae7_slot3", "ae_format_7", 3, + Slot_ae_format_7_Format_ae7_slot3_45_get, Slot_ae_format_7_Format_ae7_slot3_45_set, + Slot_ae7_slot3_get_field_fns, Slot_ae7_slot3_set_field_fns, + Slot_ae7_slot3_decode, "nop" }, + { "ae8_slot0", "ae_format_8", 0, + Slot_ae_format_8_Format_ae8_slot0_4_get, Slot_ae_format_8_Format_ae8_slot0_4_set, + Slot_ae8_slot0_get_field_fns, Slot_ae8_slot0_set_field_fns, + Slot_ae8_slot0_decode, "nop" }, + { "ae8_slot1", "ae_format_8", 1, + Slot_ae_format_8_Format_ae8_slot1_14_get, Slot_ae_format_8_Format_ae8_slot1_14_set, + Slot_ae8_slot1_get_field_fns, Slot_ae8_slot1_set_field_fns, + Slot_ae8_slot1_decode, "nop" }, + { "ae8_slot2", "ae_format_8", 2, + Slot_ae_format_8_Format_ae8_slot2_16_get, Slot_ae_format_8_Format_ae8_slot2_16_set, + Slot_ae8_slot2_get_field_fns, Slot_ae8_slot2_set_field_fns, + Slot_ae8_slot2_decode, "nop" }, + { "ae9_slot0", "ae_format_9", 0, + Slot_ae_format_9_Format_ae9_slot0_4_get, Slot_ae_format_9_Format_ae9_slot0_4_set, + Slot_ae9_slot0_get_field_fns, Slot_ae9_slot0_set_field_fns, + Slot_ae9_slot0_decode, "nop" }, + { "ae9_slot1", "ae_format_9", 1, + Slot_ae_format_9_Format_ae9_slot1_72_get, Slot_ae_format_9_Format_ae9_slot1_72_set, + Slot_ae9_slot1_get_field_fns, Slot_ae9_slot1_set_field_fns, + Slot_ae9_slot1_decode, "nop" }, + { "ae9_slot2", "ae_format_9", 2, + Slot_ae_format_9_Format_ae9_slot2_16_get, Slot_ae_format_9_Format_ae9_slot2_16_set, + Slot_ae9_slot2_get_field_fns, Slot_ae9_slot2_set_field_fns, + Slot_ae9_slot2_decode, "nop" }, + { "ae9_slot3", "ae_format_9", 3, + Slot_ae_format_9_Format_ae9_slot3_45_get, Slot_ae_format_9_Format_ae9_slot3_45_set, + Slot_ae9_slot3_get_field_fns, Slot_ae9_slot3_set_field_fns, + Slot_ae9_slot3_decode, "nop" }, + { "ae10_slot0", "ae_format_10", 0, + Slot_ae_format_10_Format_ae10_slot0_4_get, Slot_ae_format_10_Format_ae10_slot0_4_set, + Slot_ae10_slot0_get_field_fns, Slot_ae10_slot0_set_field_fns, + Slot_ae10_slot0_decode, "nop" }, + { "ae10_slot1", "ae_format_10", 1, + Slot_ae_format_10_Format_ae10_slot1_34_get, Slot_ae_format_10_Format_ae10_slot1_34_set, + Slot_ae10_slot1_get_field_fns, Slot_ae10_slot1_set_field_fns, + Slot_ae10_slot1_decode, "nop" }, + { "ae10_slot2", "ae_format_10", 2, + Slot_ae_format_10_Format_ae10_slot2_16_get, Slot_ae_format_10_Format_ae10_slot2_16_set, + Slot_ae10_slot2_get_field_fns, Slot_ae10_slot2_set_field_fns, + Slot_ae10_slot2_decode, "nop" }, + { "ae10_slot3", "ae_format_10", 3, + Slot_ae_format_10_Format_ae10_slot3_27_get, Slot_ae_format_10_Format_ae10_slot3_27_set, + Slot_ae10_slot3_get_field_fns, Slot_ae10_slot3_set_field_fns, + Slot_ae10_slot3_decode, "nop" }, + { "ae4_slot0", "ae_format_4", 0, + Slot_ae_format_4_Format_ae4_slot0_4_get, Slot_ae_format_4_Format_ae4_slot0_4_set, + Slot_ae4_slot0_get_field_fns, Slot_ae4_slot0_set_field_fns, + Slot_ae4_slot0_decode, "nop" }, + { "ae4_slot1", "ae_format_4", 1, + Slot_ae_format_4_Format_ae4_slot1_72_get, Slot_ae_format_4_Format_ae4_slot1_72_set, + Slot_ae4_slot1_get_field_fns, Slot_ae4_slot1_set_field_fns, + Slot_ae4_slot1_decode, "nop" }, + { "ae4_slot2", "ae_format_4", 2, + Slot_ae_format_4_Format_ae4_slot2_16_get, Slot_ae_format_4_Format_ae4_slot2_16_set, + Slot_ae4_slot2_get_field_fns, Slot_ae4_slot2_set_field_fns, + Slot_ae4_slot2_decode, "nop" }, + { "ae4_slot3", "ae_format_4", 3, + Slot_ae_format_4_Format_ae4_slot3_26_get, Slot_ae_format_4_Format_ae4_slot3_26_set, + Slot_ae4_slot3_get_field_fns, Slot_ae4_slot3_set_field_fns, + Slot_ae4_slot3_decode, "nop" }, + { "ae4_slot4", "ae_format_4", 4, + Slot_ae_format_4_Format_ae4_slot4_43_get, Slot_ae_format_4_Format_ae4_slot4_43_set, + Slot_ae4_slot4_get_field_fns, Slot_ae4_slot4_set_field_fns, + Slot_ae4_slot4_decode, "nop" } +}; + + +/* Instruction formats. */ + +static void +Format_x24_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_x16a_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_x16b_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xf; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_2_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x2000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_3_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_5_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x2000000e; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_6_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x6000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_7_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_8_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xa000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_9_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_10_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_4_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x4000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static int Format_x24_slots[] = { 0 }; + +static int Format_x16a_slots[] = { 1 }; + +static int Format_x16b_slots[] = { 2 }; + +static int Format_ae_format_slots[] = { 3, 5, 6, 4 }; + +static int Format_ae_format_2_slots[] = { 7, 8, 9 }; + +static int Format_ae_format_3_slots[] = { 10, 11 }; + +static int Format_ae_format_5_slots[] = { 12, 14, 13 }; + +static int Format_ae_format_6_slots[] = { 15, 18, 17, 16 }; + +static int Format_ae_format_7_slots[] = { 19, 21, 22, 20 }; + +static int Format_ae_format_8_slots[] = { 23, 24, 25 }; + +static int Format_ae_format_9_slots[] = { 26, 28, 29, 27 }; + +static int Format_ae_format_10_slots[] = { 30, 32, 33, 31 }; + +static int Format_ae_format_4_slots[] = { 34, 36, 37, 38, 35 }; + +static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }, + { "ae_format", 16, Format_ae_format_encode, 4, Format_ae_format_slots }, + { "ae_format_2", 16, Format_ae_format_2_encode, 3, Format_ae_format_2_slots }, + { "ae_format_3", 8, Format_ae_format_3_encode, 2, Format_ae_format_3_slots }, + { "ae_format_5", 8, Format_ae_format_5_encode, 3, Format_ae_format_5_slots }, + { "ae_format_6", 16, Format_ae_format_6_encode, 4, Format_ae_format_6_slots }, + { "ae_format_7", 16, Format_ae_format_7_encode, 4, Format_ae_format_7_slots }, + { "ae_format_8", 16, Format_ae_format_8_encode, 3, Format_ae_format_8_slots }, + { "ae_format_9", 16, Format_ae_format_9_encode, 4, Format_ae_format_9_slots }, + { "ae_format_10", 16, Format_ae_format_10_encode, 4, Format_ae_format_10_slots }, + { "ae_format_4", 16, Format_ae_format_4_encode, 5, Format_ae_format_4_slots } +}; + + +static int +format_decoder (const xtensa_insnbuf insn) +{ + if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 0; /* x24 */ + if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 1; /* x16a */ + if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 2; /* x16b */ + if ((insn[0] & 0xe000000f) == 0xf && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 3; /* ae_format */ + if ((insn[0] & 0xe000000f) == 0x2000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 4; /* ae_format_2 */ + if ((insn[0] & 0xe000000f) == 0xe && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 5; /* ae_format_3 */ + if ((insn[0] & 0xe000000f) == 0x2000000e && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 6; /* ae_format_5 */ + if ((insn[0] & 0xe000000f) == 0x6000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 7; /* ae_format_6 */ + if ((insn[0] & 0xe000000f) == 0x8000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 8; /* ae_format_7 */ + if ((insn[0] & 0xe000000f) == 0xa000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 9; /* ae_format_8 */ + if ((insn[0] & 0xe000000f) == 0xc000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 10; /* ae_format_9 */ + if ((insn[0] & 0xe000000f) == 0xe000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 11; /* ae_format_10 */ + if ((insn[0] & 0xe000000f) == 0x4000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 12; /* ae_format_4 */ + return -1; +} + +static int length_table[256] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16 +}; + +static int +length_decoder (const unsigned char *insn) +{ + int l = insn[0]; + return length_table[l]; +} + + +/* Top-level ISA structure. */ + +xtensa_isa_internal xtensa_modules = { + 0 /* little-endian */, + 16 /* insn_size */, 0, + 13, formats, format_decoder, length_decoder, + 39, slots, + 886 /* num_fields */, + 1100, operands, + 2139, iclasses, + 2231, opcodes, 0, + 9, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, + 6, interfaces, 0, + 7, funcUnits, 0 +}; diff --git a/overlays/xtensa_mtk_mt8196_adsp/gcc/xtensa-config.h b/overlays/xtensa_mtk_mt8196_adsp/gcc/xtensa-config.h new file mode 100644 index 00000000..036261de --- /dev/null +++ b/overlays/xtensa_mtk_mt8196_adsp/gcc/xtensa-config.h @@ -0,0 +1,185 @@ +/* Xtensa configuration settings. + Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 + Free Software Foundation, Inc. + Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef XTENSA_CONFIG_H +#define XTENSA_CONFIG_H + +/* The macros defined here match those with the same names in the Xtensa + compile-time HAL (Hardware Abstraction Layer). Please refer to the + Xtensa System Software Reference Manual for documentation of these + macros. */ + +#undef XCHAL_HAVE_BE +#define XCHAL_HAVE_BE 0 + +#undef XCHAL_HAVE_DENSITY +#define XCHAL_HAVE_DENSITY 1 + +#undef XCHAL_HAVE_CONST16 +#define XCHAL_HAVE_CONST16 0 + +#undef XCHAL_HAVE_ABS +#define XCHAL_HAVE_ABS 1 + +#undef XCHAL_HAVE_ADDX +#define XCHAL_HAVE_ADDX 1 + +#undef XCHAL_HAVE_L32R +#define XCHAL_HAVE_L32R 1 + +#undef XSHAL_USE_ABSOLUTE_LITERALS +#define XSHAL_USE_ABSOLUTE_LITERALS 0 + +#undef XSHAL_HAVE_TEXT_SECTION_LITERALS +#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ + +#undef XCHAL_HAVE_MAC16 +#define XCHAL_HAVE_MAC16 0 + +#undef XCHAL_HAVE_MUL16 +#define XCHAL_HAVE_MUL16 1 + +#undef XCHAL_HAVE_MUL32 +#define XCHAL_HAVE_MUL32 1 + +#undef XCHAL_HAVE_MUL32_HIGH +#define XCHAL_HAVE_MUL32_HIGH 0 + +#undef XCHAL_HAVE_DIV32 +#define XCHAL_HAVE_DIV32 1 + +#undef XCHAL_HAVE_NSA +#define XCHAL_HAVE_NSA 1 + +#undef XCHAL_HAVE_MINMAX +#define XCHAL_HAVE_MINMAX 1 + +#undef XCHAL_HAVE_SEXT +#define XCHAL_HAVE_SEXT 1 + +#undef XCHAL_HAVE_LOOPS +#define XCHAL_HAVE_LOOPS 1 + +#undef XCHAL_HAVE_THREADPTR +#define XCHAL_HAVE_THREADPTR 1 + +#undef XCHAL_HAVE_RELEASE_SYNC +#define XCHAL_HAVE_RELEASE_SYNC 1 + +#undef XCHAL_HAVE_S32C1I +#define XCHAL_HAVE_S32C1I 0 + +#undef XCHAL_HAVE_BOOLEANS +#define XCHAL_HAVE_BOOLEANS 1 + +#undef XCHAL_HAVE_FP +#define XCHAL_HAVE_FP 0 + +#undef XCHAL_HAVE_FP_DIV +#define XCHAL_HAVE_FP_DIV 0 + +#undef XCHAL_HAVE_FP_RECIP +#define XCHAL_HAVE_FP_RECIP 0 + +#undef XCHAL_HAVE_FP_SQRT +#define XCHAL_HAVE_FP_SQRT 0 + +#undef XCHAL_HAVE_FP_RSQRT +#define XCHAL_HAVE_FP_RSQRT 0 + +#undef XCHAL_HAVE_DFP_ACCEL +#define XCHAL_HAVE_DFP_ACCEL 0 +/* For backward compatibility */ +#undef XCHAL_HAVE_DFP_accel +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL + +#undef XCHAL_HAVE_WINDOWED +#define XCHAL_HAVE_WINDOWED 1 + +#undef XCHAL_NUM_AREGS +#define XCHAL_NUM_AREGS 64 + +#undef XCHAL_HAVE_WIDE_BRANCHES +#define XCHAL_HAVE_WIDE_BRANCHES 0 + +#undef XCHAL_ICACHE_SIZE +#define XCHAL_ICACHE_SIZE 65536 + +#undef XCHAL_DCACHE_SIZE +#define XCHAL_DCACHE_SIZE 131072 + +#undef XCHAL_ICACHE_LINESIZE +#define XCHAL_ICACHE_LINESIZE 128 + +#undef XCHAL_DCACHE_LINESIZE +#define XCHAL_DCACHE_LINESIZE 128 + +#undef XCHAL_ICACHE_LINEWIDTH +#define XCHAL_ICACHE_LINEWIDTH 7 + +#undef XCHAL_DCACHE_LINEWIDTH +#define XCHAL_DCACHE_LINEWIDTH 7 + +#undef XCHAL_DCACHE_IS_WRITEBACK +#define XCHAL_DCACHE_IS_WRITEBACK 1 + + +#undef XCHAL_HAVE_MMU +#define XCHAL_HAVE_MMU 0 + + +#undef XCHAL_HAVE_DEBUG +#define XCHAL_HAVE_DEBUG 1 + +#undef XCHAL_NUM_IBREAK +#define XCHAL_NUM_IBREAK 2 + +#undef XCHAL_NUM_DBREAK +#define XCHAL_NUM_DBREAK 2 + +#undef XCHAL_DEBUGLEVEL +#define XCHAL_DEBUGLEVEL 5 + + +#undef XCHAL_MAX_INSTRUCTION_SIZE +#define XCHAL_MAX_INSTRUCTION_SIZE 16 + +#undef XCHAL_INST_FETCH_WIDTH +#define XCHAL_INST_FETCH_WIDTH 16 + + +#undef XSHAL_ABI +#undef XTHAL_ABI_WINDOWED +#undef XTHAL_ABI_CALL0 +#define XSHAL_ABI XTHAL_ABI_WINDOWED +#define XTHAL_ABI_WINDOWED 0 +#define XTHAL_ABI_CALL0 1 + + +#undef XCHAL_M_STAGE +#define XCHAL_M_STAGE 3 + +#undef XTENSA_MARCH_LATEST +#define XTENSA_MARCH_LATEST 281080 + +#undef XTENSA_MARCH_EARLIEST +#define XTENSA_MARCH_EARLIEST 281080 + + +#endif /* !XTENSA_CONFIG_H */ diff --git a/overlays/xtensa_mtk_mt8196_adsp/gdb/reg-xtensa.dat b/overlays/xtensa_mtk_mt8196_adsp/gdb/reg-xtensa.dat new file mode 100644 index 00000000..9df36235 --- /dev/null +++ b/overlays/xtensa_mtk_mt8196_adsp/gdb/reg-xtensa.dat @@ -0,0 +1,132 @@ +name:xtensa +expedite:pc,windowbase,windowstart +32:pc +32:ar0 +32:ar1 +32:ar2 +32:ar3 +32:ar4 +32:ar5 +32:ar6 +32:ar7 +32:ar8 +32:ar9 +32:ar10 +32:ar11 +32:ar12 +32:ar13 +32:ar14 +32:ar15 +32:ar16 +32:ar17 +32:ar18 +32:ar19 +32:ar20 +32:ar21 +32:ar22 +32:ar23 +32:ar24 +32:ar25 +32:ar26 +32:ar27 +32:ar28 +32:ar29 +32:ar30 +32:ar31 +32:ar32 +32:ar33 +32:ar34 +32:ar35 +32:ar36 +32:ar37 +32:ar38 +32:ar39 +32:ar40 +32:ar41 +32:ar42 +32:ar43 +32:ar44 +32:ar45 +32:ar46 +32:ar47 +32:ar48 +32:ar49 +32:ar50 +32:ar51 +32:ar52 +32:ar53 +32:ar54 +32:ar55 +32:ar56 +32:ar57 +32:ar58 +32:ar59 +32:ar60 +32:ar61 +32:ar62 +32:ar63 +32:lbeg +32:lend +32:lcount +32:sar +32:prefctl +32:windowbase +32:windowstart +32:configid0 +32:configid1 +32:ps +32:threadptr +32:br +32:expstate +32:ae_ovf_sar +32:ae_bithead +32:ae_ts_fts_bu_bp +32:ae_cw_sd_no +32:ae_cbegin0 +32:ae_cend0 +32:ae_cbegin1 +32:ae_cend1 +32:ae_cbegin2 +32:ae_cend2 +64:aed0 +64:aed1 +64:aed2 +64:aed3 +64:aed4 +64:aed5 +64:aed6 +64:aed7 +64:aed8 +64:aed9 +64:aed10 +64:aed11 +64:aed12 +64:aed13 +64:aed14 +64:aed15 +64:aed16 +64:aed17 +64:aed18 +64:aed19 +64:aed20 +64:aed21 +64:aed22 +64:aed23 +64:aed24 +64:aed25 +64:aed26 +64:aed27 +64:aed28 +64:aed29 +64:aed30 +64:aed31 +128:u0 +128:u1 +128:u2 +128:u3 +8:aep0 +8:aep1 +8:aep2 +8:aep3 +32:ae_zbiasv8c +32:fcr_fsr diff --git a/overlays/xtensa_mtk_mt8196_adsp/gdb/xtensa-config.c b/overlays/xtensa_mtk_mt8196_adsp/gdb/xtensa-config.c new file mode 100644 index 00000000..e00fd002 --- /dev/null +++ b/overlays/xtensa_mtk_mt8196_adsp/gdb/xtensa-config.c @@ -0,0 +1,562 @@ +/* Configuration for the Xtensa architecture for GDB, the GNU debugger. + + Copyright (c) 2003-2024 Cadence Design Systems, Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#define XTENSA_CONFIG_VERSION 0x70 + +#include "xtensa-config.h" +#include "xtensa-tdep.h" + + + +/* Masked registers. */ +xtensa_reg_mask_t xtensa_submask0[] = { { 76, 0, 1 } }; +const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 }; +xtensa_reg_mask_t xtensa_submask1[] = { { 76, 1, 1 } }; +const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 }; +xtensa_reg_mask_t xtensa_submask2[] = { { 76, 2, 1 } }; +const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 }; +xtensa_reg_mask_t xtensa_submask3[] = { { 76, 3, 1 } }; +const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 }; +xtensa_reg_mask_t xtensa_submask4[] = { { 76, 4, 1 } }; +const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 }; +xtensa_reg_mask_t xtensa_submask5[] = { { 76, 5, 1 } }; +const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 }; +xtensa_reg_mask_t xtensa_submask6[] = { { 76, 6, 1 } }; +const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 }; +xtensa_reg_mask_t xtensa_submask7[] = { { 76, 7, 1 } }; +const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 }; +xtensa_reg_mask_t xtensa_submask8[] = { { 76, 8, 1 } }; +const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 }; +xtensa_reg_mask_t xtensa_submask9[] = { { 76, 9, 1 } }; +const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 }; +xtensa_reg_mask_t xtensa_submask10[] = { { 76, 10, 1 } }; +const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 }; +xtensa_reg_mask_t xtensa_submask11[] = { { 76, 11, 1 } }; +const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 }; +xtensa_reg_mask_t xtensa_submask12[] = { { 76, 12, 1 } }; +const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 }; +xtensa_reg_mask_t xtensa_submask13[] = { { 76, 13, 1 } }; +const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 }; +xtensa_reg_mask_t xtensa_submask14[] = { { 76, 14, 1 } }; +const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 }; +xtensa_reg_mask_t xtensa_submask15[] = { { 76, 15, 1 } }; +const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 }; +xtensa_reg_mask_t xtensa_submask16[] = { { 169, 0, 1 } }; +const xtensa_mask_t xtensa_mask16 = { 1, xtensa_submask16 }; +xtensa_reg_mask_t xtensa_submask17[] = { { 74, 0, 4 } }; +const xtensa_mask_t xtensa_mask17 = { 1, xtensa_submask17 }; +xtensa_reg_mask_t xtensa_submask18[] = { { 74, 5, 1 } }; +const xtensa_mask_t xtensa_mask18 = { 1, xtensa_submask18 }; +xtensa_reg_mask_t xtensa_submask19[] = { { 74, 18, 1 } }; +const xtensa_mask_t xtensa_mask19 = { 1, xtensa_submask19 }; +xtensa_reg_mask_t xtensa_submask20[] = { { 74, 6, 2 } }; +const xtensa_mask_t xtensa_mask20 = { 1, xtensa_submask20 }; +xtensa_reg_mask_t xtensa_submask21[] = { { 74, 4, 1 } }; +const xtensa_mask_t xtensa_mask21 = { 1, xtensa_submask21 }; +xtensa_reg_mask_t xtensa_submask22[] = { { 74, 16, 2 } }; +const xtensa_mask_t xtensa_mask22 = { 1, xtensa_submask22 }; +xtensa_reg_mask_t xtensa_submask23[] = { { 74, 8, 4 } }; +const xtensa_mask_t xtensa_mask23 = { 1, xtensa_submask23 }; +xtensa_reg_mask_t xtensa_submask24[] = { { 132, 0, 6 } }; +const xtensa_mask_t xtensa_mask24 = { 1, xtensa_submask24 }; +xtensa_reg_mask_t xtensa_submask25[] = { { 139, 0, 2 } }; +const xtensa_mask_t xtensa_mask25 = { 1, xtensa_submask25 }; +xtensa_reg_mask_t xtensa_submask26[] = { { 171, 8, 4 } }; +const xtensa_mask_t xtensa_mask26 = { 1, xtensa_submask26 }; +xtensa_reg_mask_t xtensa_submask27[] = { { 78, 7, 1 } }; +const xtensa_mask_t xtensa_mask27 = { 1, xtensa_submask27 }; +xtensa_reg_mask_t xtensa_submask28[] = { { 78, 0, 7 }, { 78, 8, 7 } }; +const xtensa_mask_t xtensa_mask28 = { 2, xtensa_submask28 }; +xtensa_reg_mask_t xtensa_submask29[] = { { 81, 28, 1 } }; +const xtensa_mask_t xtensa_mask29 = { 1, xtensa_submask29 }; +xtensa_reg_mask_t xtensa_submask30[] = { { 80, 0, 4 } }; +const xtensa_mask_t xtensa_mask30 = { 1, xtensa_submask30 }; +xtensa_reg_mask_t xtensa_submask31[] = { { 80, 4, 4 } }; +const xtensa_mask_t xtensa_mask31 = { 1, xtensa_submask31 }; +xtensa_reg_mask_t xtensa_submask32[] = { { 80, 12, 4 } }; +const xtensa_mask_t xtensa_mask32 = { 1, xtensa_submask32 }; +xtensa_reg_mask_t xtensa_submask33[] = { { 80, 8, 4 } }; +const xtensa_mask_t xtensa_mask33 = { 1, xtensa_submask33 }; +xtensa_reg_mask_t xtensa_submask34[] = { { 81, 0, 27 } }; +const xtensa_mask_t xtensa_mask34 = { 1, xtensa_submask34 }; +xtensa_reg_mask_t xtensa_submask35[] = { { 81, 27, 1 } }; +const xtensa_mask_t xtensa_mask35 = { 1, xtensa_submask35 }; +xtensa_reg_mask_t xtensa_submask36[] = { { 128, 8, 8 } }; +const xtensa_mask_t xtensa_mask36 = { 1, xtensa_submask36 }; +xtensa_reg_mask_t xtensa_submask37[] = { { 128, 0, 8 } }; +const xtensa_mask_t xtensa_mask37 = { 1, xtensa_submask37 }; +xtensa_reg_mask_t xtensa_submask38[] = { { 129, 5, 2 } }; +const xtensa_mask_t xtensa_mask38 = { 1, xtensa_submask38 }; +xtensa_reg_mask_t xtensa_submask39[] = { { 129, 4, 1 } }; +const xtensa_mask_t xtensa_mask39 = { 1, xtensa_submask39 }; +xtensa_reg_mask_t xtensa_submask40[] = { { 129, 3, 1 } }; +const xtensa_mask_t xtensa_mask40 = { 1, xtensa_submask40 }; +xtensa_reg_mask_t xtensa_submask41[] = { { 129, 2, 1 } }; +const xtensa_mask_t xtensa_mask41 = { 1, xtensa_submask41 }; +xtensa_reg_mask_t xtensa_submask42[] = { { 129, 1, 1 } }; +const xtensa_mask_t xtensa_mask42 = { 1, xtensa_submask42 }; +xtensa_reg_mask_t xtensa_submask43[] = { { 129, 0, 1 } }; +const xtensa_mask_t xtensa_mask43 = { 1, xtensa_submask43 }; + + +/* Register map. */ +xtensa_register_t rmap[] = +{ + /* idx ofs bi sz al targno flags cp typ group name */ + XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x2100,pc, 0,0,0,0,0,0) + XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) + XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) + XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0) + XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0) + XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0) + XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0) + XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0) + XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0) + XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0) + XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0) + XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0) + XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0) + XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0) + XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0) + XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0) + XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0) + XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0) + XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0) + XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0) + XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0) + XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0) + XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0) + XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0) + XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0) + XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0) + XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0) + XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0) + XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0) + XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0) + XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0) + XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0) + XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0) + XTREG( 33,132,32, 4, 4,0x0120,0x0006,-2, 1,0x0002,ar32, 0,0,0,0,0,0) + XTREG( 34,136,32, 4, 4,0x0121,0x0006,-2, 1,0x0002,ar33, 0,0,0,0,0,0) + XTREG( 35,140,32, 4, 4,0x0122,0x0006,-2, 1,0x0002,ar34, 0,0,0,0,0,0) + XTREG( 36,144,32, 4, 4,0x0123,0x0006,-2, 1,0x0002,ar35, 0,0,0,0,0,0) + XTREG( 37,148,32, 4, 4,0x0124,0x0006,-2, 1,0x0002,ar36, 0,0,0,0,0,0) + XTREG( 38,152,32, 4, 4,0x0125,0x0006,-2, 1,0x0002,ar37, 0,0,0,0,0,0) + XTREG( 39,156,32, 4, 4,0x0126,0x0006,-2, 1,0x0002,ar38, 0,0,0,0,0,0) + XTREG( 40,160,32, 4, 4,0x0127,0x0006,-2, 1,0x0002,ar39, 0,0,0,0,0,0) + XTREG( 41,164,32, 4, 4,0x0128,0x0006,-2, 1,0x0002,ar40, 0,0,0,0,0,0) + XTREG( 42,168,32, 4, 4,0x0129,0x0006,-2, 1,0x0002,ar41, 0,0,0,0,0,0) + XTREG( 43,172,32, 4, 4,0x012a,0x0006,-2, 1,0x0002,ar42, 0,0,0,0,0,0) + XTREG( 44,176,32, 4, 4,0x012b,0x0006,-2, 1,0x0002,ar43, 0,0,0,0,0,0) + XTREG( 45,180,32, 4, 4,0x012c,0x0006,-2, 1,0x0002,ar44, 0,0,0,0,0,0) + XTREG( 46,184,32, 4, 4,0x012d,0x0006,-2, 1,0x0002,ar45, 0,0,0,0,0,0) + XTREG( 47,188,32, 4, 4,0x012e,0x0006,-2, 1,0x0002,ar46, 0,0,0,0,0,0) + XTREG( 48,192,32, 4, 4,0x012f,0x0006,-2, 1,0x0002,ar47, 0,0,0,0,0,0) + XTREG( 49,196,32, 4, 4,0x0130,0x0006,-2, 1,0x0002,ar48, 0,0,0,0,0,0) + XTREG( 50,200,32, 4, 4,0x0131,0x0006,-2, 1,0x0002,ar49, 0,0,0,0,0,0) + XTREG( 51,204,32, 4, 4,0x0132,0x0006,-2, 1,0x0002,ar50, 0,0,0,0,0,0) + XTREG( 52,208,32, 4, 4,0x0133,0x0006,-2, 1,0x0002,ar51, 0,0,0,0,0,0) + XTREG( 53,212,32, 4, 4,0x0134,0x0006,-2, 1,0x0002,ar52, 0,0,0,0,0,0) + XTREG( 54,216,32, 4, 4,0x0135,0x0006,-2, 1,0x0002,ar53, 0,0,0,0,0,0) + XTREG( 55,220,32, 4, 4,0x0136,0x0006,-2, 1,0x0002,ar54, 0,0,0,0,0,0) + XTREG( 56,224,32, 4, 4,0x0137,0x0006,-2, 1,0x0002,ar55, 0,0,0,0,0,0) + XTREG( 57,228,32, 4, 4,0x0138,0x0006,-2, 1,0x0002,ar56, 0,0,0,0,0,0) + XTREG( 58,232,32, 4, 4,0x0139,0x0006,-2, 1,0x0002,ar57, 0,0,0,0,0,0) + XTREG( 59,236,32, 4, 4,0x013a,0x0006,-2, 1,0x0002,ar58, 0,0,0,0,0,0) + XTREG( 60,240,32, 4, 4,0x013b,0x0006,-2, 1,0x0002,ar59, 0,0,0,0,0,0) + XTREG( 61,244,32, 4, 4,0x013c,0x0006,-2, 1,0x0002,ar60, 0,0,0,0,0,0) + XTREG( 62,248,32, 4, 4,0x013d,0x0006,-2, 1,0x0002,ar61, 0,0,0,0,0,0) + XTREG( 63,252,32, 4, 4,0x013e,0x0006,-2, 1,0x0002,ar62, 0,0,0,0,0,0) + XTREG( 64,256,32, 4, 4,0x013f,0x0006,-2, 1,0x0002,ar63, 0,0,0,0,0,0) + XTREG( 65,260,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0) + XTREG( 66,264,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0) + XTREG( 67,268,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0) + XTREG( 68,272, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0) + XTREG( 69,276,13, 4, 4,0x0228,0x0006,-2, 2,0x1100,prefctl, 0,0,0,0,0,0) + XTREG( 70,280, 4, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) + XTREG( 71,284,16, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) + XTREG( 72,288,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0) + XTREG( 73,292,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0) + XTREG( 74,296,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) + XTREG( 75,300,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0) + XTREG( 76,304,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0) + XTREG( 77,308,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0) + XTREG( 78,312,15, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0) + XTREG( 79,316,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0) + XTREG( 80,320,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0) + XTREG( 81,324,29, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_cw_sd_no, 0,0,0,0,0,0) + XTREG( 82,328,32, 4, 4,0x03f6,0x0006, 1, 3,0x0110,ae_cbegin0, 0,0,0,0,0,0) + XTREG( 83,332,32, 4, 4,0x03f7,0x0006, 1, 3,0x0110,ae_cend0, 0,0,0,0,0,0) + XTREG( 84,336,32, 4, 4,0x03f8,0x0006, 1, 3,0x0110,ae_cbegin1, 0,0,0,0,0,0) + XTREG( 85,340,32, 4, 4,0x03f9,0x0006, 1, 3,0x0110,ae_cend1, 0,0,0,0,0,0) + XTREG( 86,344,32, 4, 4,0x03fa,0x0006, 1, 3,0x0110,ae_cbegin2, 0,0,0,0,0,0) + XTREG( 87,348,32, 4, 4,0x03fb,0x0006, 1, 3,0x0110,ae_cend2, 0,0,0,0,0,0) + XTREG( 88,352,64, 8, 8,0x1000,0x0006, 1, 4,0x0101,aed0, + "10:4f:03:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:03:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 89,360,64, 8, 8,0x1001,0x0006, 1, 4,0x0101,aed1, + "10:4f:43:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:43:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 90,368,64, 8, 8,0x1002,0x0006, 1, 4,0x0101,aed2, + "10:4f:83:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:83:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 91,376,64, 8, 8,0x1003,0x0006, 1, 4,0x0101,aed3, + "10:4f:c3:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:c3:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 92,384,64, 8, 8,0x1004,0x0006, 1, 4,0x0101,aed4, + "10:4f:07:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:07:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 93,392,64, 8, 8,0x1005,0x0006, 1, 4,0x0101,aed5, + "10:4f:47:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:47:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 94,400,64, 8, 8,0x1006,0x0006, 1, 4,0x0101,aed6, + "10:4f:87:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:87:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 95,408,64, 8, 8,0x1007,0x0006, 1, 4,0x0101,aed7, + "10:4f:c7:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:c7:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 96,416,64, 8, 8,0x1008,0x0006, 1, 4,0x0101,aed8, + "10:4f:0b:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:0b:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 97,424,64, 8, 8,0x1009,0x0006, 1, 4,0x0101,aed9, + "10:4f:4b:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:4b:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 98,432,64, 8, 8,0x100a,0x0006, 1, 4,0x0101,aed10, + "10:4f:8b:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:8b:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG( 99,440,64, 8, 8,0x100b,0x0006, 1, 4,0x0101,aed11, + "10:4f:cb:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:cb:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(100,448,64, 8, 8,0x100c,0x0006, 1, 4,0x0101,aed12, + "10:4f:0f:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:0f:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(101,456,64, 8, 8,0x100d,0x0006, 1, 4,0x0101,aed13, + "10:4f:4f:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:4f:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(102,464,64, 8, 8,0x100e,0x0006, 1, 4,0x0101,aed14, + "10:4f:8f:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:8f:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(103,472,64, 8, 8,0x100f,0x0006, 1, 4,0x0101,aed15, + "10:4f:cf:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:cf:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(104,480,64, 8, 8,0x1010,0x0006, 1, 4,0x0101,aed16, + "10:4f:03:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:03:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(105,488,64, 8, 8,0x1011,0x0006, 1, 4,0x0101,aed17, + "10:4f:43:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:43:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(106,496,64, 8, 8,0x1012,0x0006, 1, 4,0x0101,aed18, + "10:4f:83:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:83:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(107,504,64, 8, 8,0x1013,0x0006, 1, 4,0x0101,aed19, + "10:4f:c3:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:c3:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(108,512,64, 8, 8,0x1014,0x0006, 1, 4,0x0101,aed20, + "10:4f:07:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:07:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(109,520,64, 8, 8,0x1015,0x0006, 1, 4,0x0101,aed21, + "10:4f:47:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:47:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(110,528,64, 8, 8,0x1016,0x0006, 1, 4,0x0101,aed22, + "10:4f:87:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:87:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(111,536,64, 8, 8,0x1017,0x0006, 1, 4,0x0101,aed23, + "10:4f:c7:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:c7:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(112,544,64, 8, 8,0x1018,0x0006, 1, 4,0x0101,aed24, + "10:4f:0b:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:0b:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(113,552,64, 8, 8,0x1019,0x0006, 1, 4,0x0101,aed25, + "10:4f:4b:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:4b:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(114,560,64, 8, 8,0x101a,0x0006, 1, 4,0x0101,aed26, + "10:4f:8b:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:8b:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(115,568,64, 8, 8,0x101b,0x0006, 1, 4,0x0101,aed27, + "10:4f:cb:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:cb:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(116,576,64, 8, 8,0x101c,0x0006, 1, 4,0x0101,aed28, + "10:4f:0f:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:0f:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(117,584,64, 8, 8,0x101d,0x0006, 1, 4,0x0101,aed29, + "10:4f:4f:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:4f:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(118,592,64, 8, 8,0x101e,0x0006, 1, 4,0x0101,aed30, + "10:4f:8f:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:8f:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(119,600,64, 8, 8,0x101f,0x0006, 1, 4,0x0101,aed31, + "10:4f:cf:01:00:3e:81:00:c5:d0:0c:25:0d:7b:25:ad:0e","10:4f:cf:01:00:3f:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(120,608,128,16,16,0x1020,0x0006, 1, 4,0x0101,u0, + "10:4f:00:01:00:3b:81:80:c4:d0:0c:e4:09:7b:05:ad:0e","10:4f:c0:01:00:3f:81:00:c4:d0:0c:24:0d:7b:25:ad:0e",0,0,0,0) + XTREG(121,624,128,16,16,0x1021,0x0006, 1, 4,0x0101,u1, + "10:4f:00:01:00:3b:81:80:c4:d0:0c:e5:09:7b:05:ad:0e","10:4f:c4:01:00:3f:81:00:c4:d0:0c:24:0d:7b:25:ad:0e",0,0,0,0) + XTREG(122,640,128,16,16,0x1022,0x0006, 1, 4,0x0101,u2, + "10:4f:00:01:04:3b:81:80:c4:d0:0c:e4:09:7b:05:ad:0e","10:4f:c8:01:00:3f:81:00:c4:d0:0c:24:0d:7b:25:ad:0e",0,0,0,0) + XTREG(123,656,128,16,16,0x1023,0x0006, 1, 4,0x0101,u3, + "10:4f:00:01:04:3b:81:80:c4:d0:0c:e5:09:7b:05:ad:0e","10:4f:cc:01:00:3f:81:00:c4:d0:0c:24:0d:7b:25:ad:0e",0,0,0,0) + XTREG(124,672, 8, 1, 1,0x1024,0x0006, 1, 4,0x0101,aep0, + "03:52:64:01:08:5e:79:a5:14:c4:40:07:23:03:52:44:00:03:52:24:01","03:52:64:01:03:52:04:00:08:ce:35:a5:00:c4:40:07:23:03:52:24:01",0,0,0,0) + XTREG(125,673, 8, 1, 1,0x1025,0x0006, 1, 4,0x0101,aep1, + "03:52:64:01:08:5e:79:a5:14:c5:40:07:23:03:52:44:00:03:52:24:01","03:52:64:01:03:52:04:00:08:ce:35:a5:00:c5:40:07:23:03:52:24:01",0,0,0,0) + XTREG(126,674, 8, 1, 1,0x1026,0x0006, 1, 4,0x0101,aep2, + "03:52:64:01:08:5e:79:a5:14:c6:40:07:23:03:52:44:00:03:52:24:01","03:52:64:01:03:52:04:00:08:ce:35:a5:00:c6:40:07:23:03:52:24:01",0,0,0,0) + XTREG(127,675, 8, 1, 1,0x1027,0x0006, 1, 4,0x0101,aep3, + "03:52:64:01:08:5e:79:a5:14:c7:40:07:23:03:52:44:00:03:52:24:01","03:52:64:01:03:52:04:00:08:ce:35:a5:00:c7:40:07:23:03:52:24:01",0,0,0,0) + XTREG(128,676,16, 4, 4,0x1029,0x0006, 1, 3,0x0200,ae_zbiasv8c, + "10:4f:03:01:08:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e:10:5f:01:00:0c:30:81:00:c5:d0:0c:44:0d:7b:25:ad:0e:10:4f:03:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e:10:4f:03:01:08:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e","10:4f:03:01:08:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e:10:4f:03:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e:10:5f:01:00:0c:38:81:00:c5:d0:0c:44:0d:7b:25:ad:0e:10:4f:03:01:08:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(129,680, 7, 4, 4,0x102a,0x0006, 1, 3,0x0200,fcr_fsr, + "10:4f:03:01:08:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e:10:5f:01:a0:0e:00:80:00:c5:d0:0c:44:0d:9b:24:ad:0e:10:4f:03:01:00:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e:10:4f:03:01:08:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e","10:4f:03:01:08:3c:81:00:c5:d0:0c:25:0d:7b:25:ad:0e:10:4f:03:01:00:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e:10:5f:01:80:0e:00:80:00:c5:d0:0c:44:0d:9b:24:ad:0e:10:4f:03:01:08:3d:81:00:c4:d0:0c:25:0d:7b:25:ad:0e",0,0,0,0) + XTREG(130,684,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0) + XTREG(131,688,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,mpuenb, 0,0,0,0,0,0) + XTREG(132,692, 6, 4, 4,0x025c,0x0007,-2, 2,0x1000,mpucfg, 0,0,0,0,0,0) + XTREG(133,696,16, 4, 4,0x025f,0x0007,-2, 2,0x1000,eraccess, 0,0,0,0,0,0) + XTREG(134,700, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0) + XTREG(135,704,24, 4, 4,0x0261,0x0007,-2, 2,0x1000,memctl, 0,0,0,0,0,0) + XTREG(136,708, 8, 4, 4,0x0262,0x0007,-2, 2,0x1000,cacheadrdis, 0,0,0,0,0,0) + XTREG(137,712, 9, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0) + XTREG(138,716,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0) + XTREG(139,720, 2, 4, 4,0x0277,0x0007,-2, 2,0x1000,opmode, 0,0,0,0,0,0) + XTREG(140,724,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0) + XTREG(141,728,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0) + XTREG(142,732,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0) + XTREG(143,736,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0) + XTREG(144,740,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0) + XTREG(145,744,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0) + XTREG(146,748,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0) + XTREG(147,752,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0) + XTREG(148,756,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0) + XTREG(149,760,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0) + XTREG(150,764,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0) + XTREG(151,768,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0) + XTREG(152,772,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0) + XTREG(153,776,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0) + XTREG(154,780,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0) + XTREG(155,784,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0) + XTREG(156,788,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0) + XTREG(157,792,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0) + XTREG(158,796,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) + XTREG(159,800,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) + XTREG(160,804,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0) + XTREG(161,808,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0) + XTREG(162,812,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0) + XTREG(163,816,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0) + XTREG(164,820, 2, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0) + XTREG(165,824,32, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) + XTREG(166,828,32, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0) + XTREG(167,832,32, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0) + XTREG(168,836,32, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0) + XTREG(169,840,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) + XTREG(170,844, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0) + XTREG(171,848,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) + XTREG(172,852,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0) + XTREG(173,856,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0) + XTREG(174,860,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0) + XTREG(175,864, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) + XTREG(176,868,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) + XTREG(177,872,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) + XTREG(178,876,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0) + XTREG(179,880,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0) + XTREG(180,884,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0) + XTREG(181,888,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0) + XTREG(182,892,32, 4, 4,0x02f6,0x0007,-2, 2,0x1000,misc2, 0,0,0,0,0,0) + XTREG(183,896,32, 4, 4,0x02f7,0x0007,-2, 2,0x1000,misc3, 0,0,0,0,0,0) + XTREG(184,900,32, 4, 4,0x202a,0x000f,-2, 4,0x0101,pwrctl, + "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(185,904,32, 4, 4,0x202b,0x000f,-2, 4,0x0101,pwrstat, + "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(186,908, 1, 4, 4,0x202c,0x000f,-2, 4,0x0101,eristat, + "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(187,912,32, 4, 4,0x202d,0x000f,-2, 4,0x0101,cs_itctrl, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(188,916,16, 4, 4,0x202e,0x000f,-2, 4,0x0101,cs_claimset, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(189,920,16, 4, 4,0x202f,0x000f,-2, 4,0x0101,cs_claimclr, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(190,924,32, 4, 4,0x2030,0x000d,-2, 4,0x0101,cs_lockaccess, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(191,928,32, 4, 4,0x2031,0x000b,-2, 4,0x0101,cs_lockstatus, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(192,932, 1, 4, 4,0x2032,0x000b,-2, 4,0x0101,cs_authstatus, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(193,936,32, 4, 4,0x2041,0x000f,-2, 4,0x0101,fault_info, + "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:30:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:30:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(194,940,32, 4, 4,0x2042,0x0003,-2, 4,0x0101,trax_id, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(195,944,32, 4, 4,0x2043,0x000f,-2, 4,0x0101,trax_control, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(196,948,32, 4, 4,0x2044,0x000b,-2, 4,0x0101,trax_status, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(197,952,32, 4, 4,0x2045,0x000f,-2, 4,0x0101,trax_data, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(198,956,32, 4, 4,0x2046,0x000f,-2, 4,0x0101,trax_address, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(199,960,32, 4, 4,0x2047,0x000f,-2, 4,0x0101,trax_pctrigger, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(200,964,32, 4, 4,0x2048,0x000f,-2, 4,0x0101,trax_pcmatch, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(201,968,32, 4, 4,0x2049,0x000f,-2, 4,0x0101,trax_delay, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(202,972,32, 4, 4,0x204a,0x000f,-2, 4,0x0101,trax_memstart, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(203,976,32, 4, 4,0x204b,0x000f,-2, 4,0x0101,trax_memend, + "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(204,980,32, 4, 4,0x2059,0x000f,-2, 4,0x0101,pmg, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(205,984,32, 4, 4,0x205a,0x000f,-2, 4,0x0101,pmpc, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(206,988,32, 4, 4,0x205b,0x000f,-2, 4,0x0101,pm0, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(207,992,32, 4, 4,0x205c,0x000f,-2, 4,0x0101,pm1, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(208,996,32, 4, 4,0x205d,0x000f,-2, 4,0x0101,pm2, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(209,1000,32, 4, 4,0x205e,0x000f,-2, 4,0x0101,pm3, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(210,1004,32, 4, 4,0x205f,0x000f,-2, 4,0x0101,pm4, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(211,1008,32, 4, 4,0x2060,0x000f,-2, 4,0x0101,pm5, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(212,1012,32, 4, 4,0x2061,0x000f,-2, 4,0x0101,pm6, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(213,1016,32, 4, 4,0x2062,0x000f,-2, 4,0x0101,pm7, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(214,1020,32, 4, 4,0x2063,0x000f,-2, 4,0x0101,pmctrl0, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(215,1024,32, 4, 4,0x2064,0x000f,-2, 4,0x0101,pmctrl1, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(216,1028,32, 4, 4,0x2065,0x000f,-2, 4,0x0101,pmctrl2, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(217,1032,32, 4, 4,0x2066,0x000f,-2, 4,0x0101,pmctrl3, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(218,1036,32, 4, 4,0x2067,0x000f,-2, 4,0x0101,pmctrl4, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(219,1040,32, 4, 4,0x2068,0x000f,-2, 4,0x0101,pmctrl5, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(220,1044,32, 4, 4,0x2069,0x000f,-2, 4,0x0101,pmctrl6, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(221,1048,32, 4, 4,0x206a,0x000f,-2, 4,0x0101,pmctrl7, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(222,1052,32, 4, 4,0x206b,0x000f,-2, 4,0x0101,pmstat0, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(223,1056,32, 4, 4,0x206c,0x000f,-2, 4,0x0101,pmstat1, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(224,1060,32, 4, 4,0x206d,0x000f,-2, 4,0x0101,pmstat2, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(225,1064,32, 4, 4,0x206e,0x000f,-2, 4,0x0101,pmstat3, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(226,1068,32, 4, 4,0x206f,0x000f,-2, 4,0x0101,pmstat4, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(227,1072,32, 4, 4,0x2070,0x000f,-2, 4,0x0101,pmstat5, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(228,1076,32, 4, 4,0x2071,0x000f,-2, 4,0x0101,pmstat6, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(229,1080,32, 4, 4,0x2072,0x000f,-2, 4,0x0101,pmstat7, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(230,1084,32, 4, 4,0x2073,0x0003,-2, 4,0x0101,ocdid, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(231,1088,32, 4, 4,0x2074,0x000f,-2, 4,0x0101,ocd_dcrclr, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(232,1092,32, 4, 4,0x2075,0x000f,-2, 4,0x0101,ocd_dcrset, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(233,1096,32, 4, 4,0x2076,0x000f,-2, 4,0x0101,ocd_dsr, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(234,1100,32, 4, 4,0x0000,0x0006,-2, 8,0x2100,a0, 0,0,0,0,0,0) + XTREG(235,1104,32, 4, 4,0x0001,0x0006,-2, 8,0x2100,a1, 0,0,0,0,0,0) + XTREG(236,1108,32, 4, 4,0x0002,0x0006,-2, 8,0x2100,a2, 0,0,0,0,0,0) + XTREG(237,1112,32, 4, 4,0x0003,0x0006,-2, 8,0x2100,a3, 0,0,0,0,0,0) + XTREG(238,1116,32, 4, 4,0x0004,0x0006,-2, 8,0x2100,a4, 0,0,0,0,0,0) + XTREG(239,1120,32, 4, 4,0x0005,0x0006,-2, 8,0x2100,a5, 0,0,0,0,0,0) + XTREG(240,1124,32, 4, 4,0x0006,0x0006,-2, 8,0x2100,a6, 0,0,0,0,0,0) + XTREG(241,1128,32, 4, 4,0x0007,0x0006,-2, 8,0x2100,a7, 0,0,0,0,0,0) + XTREG(242,1132,32, 4, 4,0x0008,0x0006,-2, 8,0x2100,a8, 0,0,0,0,0,0) + XTREG(243,1136,32, 4, 4,0x0009,0x0006,-2, 8,0x2100,a9, 0,0,0,0,0,0) + XTREG(244,1140,32, 4, 4,0x000a,0x0006,-2, 8,0x2100,a10, 0,0,0,0,0,0) + XTREG(245,1144,32, 4, 4,0x000b,0x0006,-2, 8,0x2100,a11, 0,0,0,0,0,0) + XTREG(246,1148,32, 4, 4,0x000c,0x0006,-2, 8,0x2100,a12, 0,0,0,0,0,0) + XTREG(247,1152,32, 4, 4,0x000d,0x0006,-2, 8,0x2100,a13, 0,0,0,0,0,0) + XTREG(248,1156,32, 4, 4,0x000e,0x0006,-2, 8,0x2100,a14, 0,0,0,0,0,0) + XTREG(249,1160,32, 4, 4,0x000f,0x0006,-2, 8,0x2100,a15, 0,0,0,0,0,0) + XTREG(250,1164, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0, + 0,0,&xtensa_mask0,0,0,0) + XTREG(251,1165, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1, + 0,0,&xtensa_mask1,0,0,0) + XTREG(252,1166, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2, + 0,0,&xtensa_mask2,0,0,0) + XTREG(253,1167, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3, + 0,0,&xtensa_mask3,0,0,0) + XTREG(254,1168, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4, + 0,0,&xtensa_mask4,0,0,0) + XTREG(255,1169, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5, + 0,0,&xtensa_mask5,0,0,0) + XTREG(256,1170, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6, + 0,0,&xtensa_mask6,0,0,0) + XTREG(257,1171, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7, + 0,0,&xtensa_mask7,0,0,0) + XTREG(258,1172, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8, + 0,0,&xtensa_mask8,0,0,0) + XTREG(259,1173, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9, + 0,0,&xtensa_mask9,0,0,0) + XTREG(260,1174, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10, + 0,0,&xtensa_mask10,0,0,0) + XTREG(261,1175, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11, + 0,0,&xtensa_mask11,0,0,0) + XTREG(262,1176, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12, + 0,0,&xtensa_mask12,0,0,0) + XTREG(263,1177, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13, + 0,0,&xtensa_mask13,0,0,0) + XTREG(264,1178, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14, + 0,0,&xtensa_mask14,0,0,0) + XTREG(265,1179, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15, + 0,0,&xtensa_mask15,0,0,0) + XTREG(266,1180, 1, 4, 4,0x2002,0x0006,-2, 6,0x1010,vecbaselock, + 0,0,&xtensa_mask16,0,0,0) + XTREG(267,1184, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel, + 0,0,&xtensa_mask17,0,0,0) + XTREG(268,1188, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum, + 0,0,&xtensa_mask18,0,0,0) + XTREG(269,1192, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe, + 0,0,&xtensa_mask19,0,0,0) + XTREG(270,1196, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,psring, + 0,0,&xtensa_mask20,0,0,0) + XTREG(271,1200, 1, 4, 4,0x200c,0x0006,-2, 6,0x1010,psexcm, + 0,0,&xtensa_mask21,0,0,0) + XTREG(272,1204, 2, 4, 4,0x200d,0x0006,-2, 6,0x1010,pscallinc, + 0,0,&xtensa_mask22,0,0,0) + XTREG(273,1208, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,psowb, + 0,0,&xtensa_mask23,0,0,0) + XTREG(274,1212, 6, 4, 4,0x200f,0x0006,-2, 6,0x1010,mpunumentries, + 0,0,&xtensa_mask24,0,0,0) + XTREG(275,1216, 2, 4, 4,0x2010,0x0006,-2, 6,0x1010,opmodeeccfence, + 0,0,&xtensa_mask25,0,0,0) + XTREG(276,1220, 4, 4, 4,0x2015,0x0006,-2, 6,0x1010,dbnum, + 0,0,&xtensa_mask26,0,0,0) + XTREG(277,1224, 1, 4, 4,0x2019,0x0006, 1, 6,0x1010,ae_overflow, + 0,0,&xtensa_mask27,0,0,0) + XTREG(278,1228,14, 4, 4,0x201a,0x0006, 1, 6,0x1010,ae_sar, + 0,0,&xtensa_mask28,0,0,0) + XTREG(279,1232, 1, 4, 4,0x201b,0x0006, 1, 6,0x1010,ae_cwrap, + 0,0,&xtensa_mask29,0,0,0) + XTREG(280,1236, 4, 4, 4,0x201c,0x0006, 1, 6,0x1010,ae_bitptr, + 0,0,&xtensa_mask30,0,0,0) + XTREG(281,1240, 4, 4, 4,0x201d,0x0006, 1, 6,0x1010,ae_bitsused, + 0,0,&xtensa_mask31,0,0,0) + XTREG(282,1244, 4, 4, 4,0x201e,0x0006, 1, 6,0x1010,ae_tablesize, + 0,0,&xtensa_mask32,0,0,0) + XTREG(283,1248, 4, 4, 4,0x201f,0x0006, 1, 6,0x1010,ae_first_ts, + 0,0,&xtensa_mask33,0,0,0) + XTREG(284,1252,27, 4, 4,0x2020,0x0006, 1, 6,0x1010,ae_nextoffset, + 0,0,&xtensa_mask34,0,0,0) + XTREG(285,1256, 1, 4, 4,0x2021,0x0006, 1, 6,0x1010,ae_searchdone, + 0,0,&xtensa_mask35,0,0,0) + XTREG(286,1260, 8, 4, 4,0x2022,0x0006, 1, 6,0x1010,ae_zbiasv8, + 0,0,&xtensa_mask36,0,0,0) + XTREG(287,1264, 8, 4, 4,0x2023,0x0006, 1, 6,0x1010,ae_zbiasc8, + 0,0,&xtensa_mask37,0,0,0) + XTREG(288,1268, 2, 4, 4,0x2024,0x0006, 1, 6,0x1010,roundmode, + 0,0,&xtensa_mask38,0,0,0) + XTREG(289,1272, 1, 4, 4,0x2025,0x0006, 1, 6,0x1010,invalidflag, + 0,0,&xtensa_mask39,0,0,0) + XTREG(290,1276, 1, 4, 4,0x2026,0x0006, 1, 6,0x1010,divzeroflag, + 0,0,&xtensa_mask40,0,0,0) + XTREG(291,1280, 1, 4, 4,0x2027,0x0006, 1, 6,0x1010,overflowflag, + 0,0,&xtensa_mask41,0,0,0) + XTREG(292,1284, 1, 4, 4,0x2028,0x0006, 1, 6,0x1010,underflowflag, + 0,0,&xtensa_mask42,0,0,0) + XTREG_END +}; + + + +#ifdef XTENSA_CONFIG_INSTANTIATE +XTENSA_CONFIG_INSTANTIATE(rmap,16) +#endif + diff --git a/overlays/xtensa_mtk_mt8196_adsp/gdb/xtensa-config.h b/overlays/xtensa_mtk_mt8196_adsp/gdb/xtensa-config.h new file mode 100644 index 00000000..036261de --- /dev/null +++ b/overlays/xtensa_mtk_mt8196_adsp/gdb/xtensa-config.h @@ -0,0 +1,185 @@ +/* Xtensa configuration settings. + Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 + Free Software Foundation, Inc. + Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef XTENSA_CONFIG_H +#define XTENSA_CONFIG_H + +/* The macros defined here match those with the same names in the Xtensa + compile-time HAL (Hardware Abstraction Layer). Please refer to the + Xtensa System Software Reference Manual for documentation of these + macros. */ + +#undef XCHAL_HAVE_BE +#define XCHAL_HAVE_BE 0 + +#undef XCHAL_HAVE_DENSITY +#define XCHAL_HAVE_DENSITY 1 + +#undef XCHAL_HAVE_CONST16 +#define XCHAL_HAVE_CONST16 0 + +#undef XCHAL_HAVE_ABS +#define XCHAL_HAVE_ABS 1 + +#undef XCHAL_HAVE_ADDX +#define XCHAL_HAVE_ADDX 1 + +#undef XCHAL_HAVE_L32R +#define XCHAL_HAVE_L32R 1 + +#undef XSHAL_USE_ABSOLUTE_LITERALS +#define XSHAL_USE_ABSOLUTE_LITERALS 0 + +#undef XSHAL_HAVE_TEXT_SECTION_LITERALS +#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ + +#undef XCHAL_HAVE_MAC16 +#define XCHAL_HAVE_MAC16 0 + +#undef XCHAL_HAVE_MUL16 +#define XCHAL_HAVE_MUL16 1 + +#undef XCHAL_HAVE_MUL32 +#define XCHAL_HAVE_MUL32 1 + +#undef XCHAL_HAVE_MUL32_HIGH +#define XCHAL_HAVE_MUL32_HIGH 0 + +#undef XCHAL_HAVE_DIV32 +#define XCHAL_HAVE_DIV32 1 + +#undef XCHAL_HAVE_NSA +#define XCHAL_HAVE_NSA 1 + +#undef XCHAL_HAVE_MINMAX +#define XCHAL_HAVE_MINMAX 1 + +#undef XCHAL_HAVE_SEXT +#define XCHAL_HAVE_SEXT 1 + +#undef XCHAL_HAVE_LOOPS +#define XCHAL_HAVE_LOOPS 1 + +#undef XCHAL_HAVE_THREADPTR +#define XCHAL_HAVE_THREADPTR 1 + +#undef XCHAL_HAVE_RELEASE_SYNC +#define XCHAL_HAVE_RELEASE_SYNC 1 + +#undef XCHAL_HAVE_S32C1I +#define XCHAL_HAVE_S32C1I 0 + +#undef XCHAL_HAVE_BOOLEANS +#define XCHAL_HAVE_BOOLEANS 1 + +#undef XCHAL_HAVE_FP +#define XCHAL_HAVE_FP 0 + +#undef XCHAL_HAVE_FP_DIV +#define XCHAL_HAVE_FP_DIV 0 + +#undef XCHAL_HAVE_FP_RECIP +#define XCHAL_HAVE_FP_RECIP 0 + +#undef XCHAL_HAVE_FP_SQRT +#define XCHAL_HAVE_FP_SQRT 0 + +#undef XCHAL_HAVE_FP_RSQRT +#define XCHAL_HAVE_FP_RSQRT 0 + +#undef XCHAL_HAVE_DFP_ACCEL +#define XCHAL_HAVE_DFP_ACCEL 0 +/* For backward compatibility */ +#undef XCHAL_HAVE_DFP_accel +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL + +#undef XCHAL_HAVE_WINDOWED +#define XCHAL_HAVE_WINDOWED 1 + +#undef XCHAL_NUM_AREGS +#define XCHAL_NUM_AREGS 64 + +#undef XCHAL_HAVE_WIDE_BRANCHES +#define XCHAL_HAVE_WIDE_BRANCHES 0 + +#undef XCHAL_ICACHE_SIZE +#define XCHAL_ICACHE_SIZE 65536 + +#undef XCHAL_DCACHE_SIZE +#define XCHAL_DCACHE_SIZE 131072 + +#undef XCHAL_ICACHE_LINESIZE +#define XCHAL_ICACHE_LINESIZE 128 + +#undef XCHAL_DCACHE_LINESIZE +#define XCHAL_DCACHE_LINESIZE 128 + +#undef XCHAL_ICACHE_LINEWIDTH +#define XCHAL_ICACHE_LINEWIDTH 7 + +#undef XCHAL_DCACHE_LINEWIDTH +#define XCHAL_DCACHE_LINEWIDTH 7 + +#undef XCHAL_DCACHE_IS_WRITEBACK +#define XCHAL_DCACHE_IS_WRITEBACK 1 + + +#undef XCHAL_HAVE_MMU +#define XCHAL_HAVE_MMU 0 + + +#undef XCHAL_HAVE_DEBUG +#define XCHAL_HAVE_DEBUG 1 + +#undef XCHAL_NUM_IBREAK +#define XCHAL_NUM_IBREAK 2 + +#undef XCHAL_NUM_DBREAK +#define XCHAL_NUM_DBREAK 2 + +#undef XCHAL_DEBUGLEVEL +#define XCHAL_DEBUGLEVEL 5 + + +#undef XCHAL_MAX_INSTRUCTION_SIZE +#define XCHAL_MAX_INSTRUCTION_SIZE 16 + +#undef XCHAL_INST_FETCH_WIDTH +#define XCHAL_INST_FETCH_WIDTH 16 + + +#undef XSHAL_ABI +#undef XTHAL_ABI_WINDOWED +#undef XTHAL_ABI_CALL0 +#define XSHAL_ABI XTHAL_ABI_WINDOWED +#define XTHAL_ABI_WINDOWED 0 +#define XTHAL_ABI_CALL0 1 + + +#undef XCHAL_M_STAGE +#define XCHAL_M_STAGE 3 + +#undef XTENSA_MARCH_LATEST +#define XTENSA_MARCH_LATEST 281080 + +#undef XTENSA_MARCH_EARLIEST +#define XTENSA_MARCH_EARLIEST 281080 + + +#endif /* !XTENSA_CONFIG_H */ diff --git a/overlays/xtensa_mtk_mt8196_adsp/gdb/xtensa-modules.c b/overlays/xtensa_mtk_mt8196_adsp/gdb/xtensa-modules.c new file mode 100644 index 00000000..24233d0a --- /dev/null +++ b/overlays/xtensa_mtk_mt8196_adsp/gdb/xtensa-modules.c @@ -0,0 +1,244783 @@ +/* Xtensa configuration-specific ISA information. + + Copyright (c) 2003-2024 Cadence Design Systems, Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "ansidecl.h" +#include +#include "xtensa-isa-internal.h" + + +/* Sysregs. */ + +static xtensa_sysreg_internal sysregs[] = { + { "LBEG", 0, 0 }, + { "LEND", 1, 0 }, + { "LCOUNT", 2, 0 }, + { "BR", 4, 0 }, + { "MMID", 89, 0 }, + { "DDR", 104, 0 }, + { "CONFIGID0", 176, 0 }, + { "CONFIGID1", 208, 0 }, + { "INTERRUPT", 226, 0 }, + { "INTCLEAR", 227, 0 }, + { "CCOUNT", 234, 0 }, + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, + { "CCOMPARE1", 241, 0 }, + { "CCOMPARE2", 242, 0 }, + { "VECBASE", 231, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EPC3", 179, 0 }, + { "EPC4", 180, 0 }, + { "EPC5", 181, 0 }, + { "EPC6", 182, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EXCSAVE3", 211, 0 }, + { "EXCSAVE4", 212, 0 }, + { "EXCSAVE5", 213, 0 }, + { "EXCSAVE6", 214, 0 }, + { "EPS2", 194, 0 }, + { "EPS3", 195, 0 }, + { "EPS4", 196, 0 }, + { "EPS5", 197, 0 }, + { "EPS6", 198, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, + { "WINDOWBASE", 72, 0 }, + { "WINDOWSTART", 73, 0 }, + { "MEMCTL", 97, 0 }, + { "SAR", 3, 0 }, + { "PS", 230, 0 }, + { "MISC0", 244, 0 }, + { "MISC1", 245, 0 }, + { "MISC2", 246, 0 }, + { "MISC3", 247, 0 }, + { "MPUCFG", 92, 0 }, + { "OPMODE", 119, 0 }, + { "INTENABLE", 228, 0 }, + { "DBREAKA0", 144, 0 }, + { "DBREAKC0", 160, 0 }, + { "DBREAKA1", 145, 0 }, + { "DBREAKC1", 161, 0 }, + { "IBREAKA0", 128, 0 }, + { "IBREAKA1", 129, 0 }, + { "IBREAKENABLE", 96, 0 }, + { "ICOUNTLEVEL", 237, 0 }, + { "DEBUGCAUSE", 233, 0 }, + { "PREFCTL", 40, 0 }, + { "CACHEADRDIS", 98, 0 }, + { "MPUENB", 90, 0 }, + { "CPENABLE", 224, 0 }, + { "ATOMCTL", 99, 0 }, + { "ERACCESS", 95, 0 }, + { "THREADPTR", 231, 1 }, + { "AE_OVF_SAR", 240, 1 }, + { "AE_BITHEAD", 241, 1 }, + { "AE_TS_FTS_BU_BP", 242, 1 }, + { "AE_CW_SD_NO", 243, 1 }, + { "AE_CBEGIN0", 246, 1 }, + { "AE_CEND0", 247, 1 }, + { "AE_CBEGIN1", 248, 1 }, + { "AE_CEND1", 249, 1 }, + { "AE_CBEGIN2", 250, 1 }, + { "AE_CEND2", 251, 1 }, + { "AE_ZBIASV8C", -1, 1 }, + { "FCR_FSR", -1, 1 }, + { "EXPSTATE", 230, 1 } +}; + +#define NUM_SYSREGS 78 +#define MAX_SPECIAL_REG 247 +#define MAX_USER_REG 251 + + +/* Processor states. */ + +static xtensa_state_internal states[] = { + { "LCOUNT", 32, 0 }, + { "PC", 32, 0 }, + { "DDR", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "INTERRUPT", 32, 0 }, + { "CCOUNT", 32, 0 }, + { "XTSYNC", 1, 0 }, + { "VECBASE", 22, 0 }, + { "VECBASELOCK", 1, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EPC3", 32, 0 }, + { "EPC4", 32, 0 }, + { "EPC5", 32, 0 }, + { "EPC6", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EXCSAVE3", 32, 0 }, + { "EXCSAVE4", 32, 0 }, + { "EXCSAVE5", 32, 0 }, + { "EXCSAVE6", 32, 0 }, + { "EPS2", 15, 0 }, + { "EPS3", 15, 0 }, + { "EPS4", 15, 0 }, + { "EPS5", 15, 0 }, + { "EPS6", 15, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, + { "PSWOE", 1, 0 }, + { "PSRING", 2, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, + { "WindowBase", 4, 0 }, + { "WindowStart", 16, 0 }, + { "PSCALLINC", 2, 0 }, + { "PSOWB", 4, 0 }, + { "LBEG", 32, 0 }, + { "LEND", 32, 0 }, + { "MEMCTL", 24, 0 }, + { "SAR", 6, 0 }, + { "THREADPTR", 32, 0 }, + { "MISC0", 32, 0 }, + { "MISC1", 32, 0 }, + { "MISC2", 32, 0 }, + { "MISC3", 32, 0 }, + { "MPUNUMENTRIES", 6, 0 }, + { "OPMODEECCFENCE", 2, 0 }, + { "InOCDMode", 1, 0 }, + { "INTENABLE", 32, 0 }, + { "DBREAKA0", 32, 0 }, + { "DBREAKC0", 8, 0 }, + { "DBREAKA1", 32, 0 }, + { "DBREAKC1", 8, 0 }, + { "IBREAKA0", 32, 0 }, + { "IBREAKA1", 32, 0 }, + { "IBREAKENABLE", 2, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, + { "CCOMPARE0", 32, 0 }, + { "CCOMPARE1", 32, 0 }, + { "CCOMPARE2", 32, 0 }, + { "PREFCTL", 9, 0 }, + { "CACHEADRDIS", 8, 0 }, + { "MPUENB", 32, 0 }, + { "MPULOCK", 32, 0 }, + { "CPENABLE", 2, 0 }, + { "ATOMCTL", 9, 0 }, + { "ERI_RAW_INTERLOCK", 1, 0 }, + { "ERACCESS", 16, 0 }, + { "AE_OVERFLOW", 1, XTENSA_STATE_IS_SHARED_OR }, + { "AE_CBEGIN0", 32, 0 }, + { "AE_CEND0", 32, 0 }, + { "AE_CBEGIN1", 32, 0 }, + { "AE_CEND1", 32, 0 }, + { "AE_CBEGIN2", 32, 0 }, + { "AE_CEND2", 32, 0 }, + { "AE_SAR", 14, 0 }, + { "AE_CWRAP", 1, 0 }, + { "AE_BITHEAD", 32, 0 }, + { "AE_BITPTR", 4, 0 }, + { "AE_BITSUSED", 4, 0 }, + { "AE_TABLESIZE", 4, 0 }, + { "AE_FIRST_TS", 4, 0 }, + { "AE_NEXTOFFSET", 27, 0 }, + { "AE_SEARCHDONE", 1, 0 }, + { "AE_ZBIASV8", 8, 0 }, + { "AE_ZBIASC8", 8, 0 }, + { "RoundMode", 2, 0 }, + { "InvalidFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "DivZeroFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "OverflowFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "UnderflowFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "InexactFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } +}; + +#define NUM_STATES 97 + +enum xtensa_state_id { + STATE_LCOUNT, + STATE_PC, + STATE_DDR, + STATE_ICOUNT, + STATE_INTERRUPT, + STATE_CCOUNT, + STATE_XTSYNC, + STATE_VECBASE, + STATE_VECBASELOCK, + STATE_EPC1, + STATE_EPC2, + STATE_EPC3, + STATE_EPC4, + STATE_EPC5, + STATE_EPC6, + STATE_EXCSAVE1, + STATE_EXCSAVE2, + STATE_EXCSAVE3, + STATE_EXCSAVE4, + STATE_EXCSAVE5, + STATE_EXCSAVE6, + STATE_EPS2, + STATE_EPS3, + STATE_EPS4, + STATE_EPS5, + STATE_EPS6, + STATE_EXCCAUSE, + STATE_PSINTLEVEL, + STATE_PSUM, + STATE_PSWOE, + STATE_PSRING, + STATE_PSEXCM, + STATE_DEPC, + STATE_EXCVADDR, + STATE_WindowBase, + STATE_WindowStart, + STATE_PSCALLINC, + STATE_PSOWB, + STATE_LBEG, + STATE_LEND, + STATE_MEMCTL, + STATE_SAR, + STATE_THREADPTR, + STATE_MISC0, + STATE_MISC1, + STATE_MISC2, + STATE_MISC3, + STATE_MPUNUMENTRIES, + STATE_OPMODEECCFENCE, + STATE_InOCDMode, + STATE_INTENABLE, + STATE_DBREAKA0, + STATE_DBREAKC0, + STATE_DBREAKA1, + STATE_DBREAKC1, + STATE_IBREAKA0, + STATE_IBREAKA1, + STATE_IBREAKENABLE, + STATE_ICOUNTLEVEL, + STATE_DEBUGCAUSE, + STATE_DBNUM, + STATE_CCOMPARE0, + STATE_CCOMPARE1, + STATE_CCOMPARE2, + STATE_PREFCTL, + STATE_CACHEADRDIS, + STATE_MPUENB, + STATE_MPULOCK, + STATE_CPENABLE, + STATE_ATOMCTL, + STATE_ERI_RAW_INTERLOCK, + STATE_ERACCESS, + STATE_AE_OVERFLOW, + STATE_AE_CBEGIN0, + STATE_AE_CEND0, + STATE_AE_CBEGIN1, + STATE_AE_CEND1, + STATE_AE_CBEGIN2, + STATE_AE_CEND2, + STATE_AE_SAR, + STATE_AE_CWRAP, + STATE_AE_BITHEAD, + STATE_AE_BITPTR, + STATE_AE_BITSUSED, + STATE_AE_TABLESIZE, + STATE_AE_FIRST_TS, + STATE_AE_NEXTOFFSET, + STATE_AE_SEARCHDONE, + STATE_AE_ZBIASV8, + STATE_AE_ZBIASC8, + STATE_RoundMode, + STATE_InvalidFlag, + STATE_DivZeroFlag, + STATE_OverflowFlag, + STATE_UnderflowFlag, + STATE_InexactFlag, + STATE_EXPSTATE +}; + + +/* Field definitions. */ + +static unsigned +Field_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_n_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_m_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_inst_15_12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_inst_15_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_inst_11_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_inst_11_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_inst16b_15_13_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_ae_fld_inst16b_15_13_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_ae_fld_inst16b_12_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_ae_fld_inst16b_12_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 3) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_19_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 3) >> 18); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x1fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_3_2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_17_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 3) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_22_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 11) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 3) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_21_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe00000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_19_19_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_18_16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_3_3_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 3) >> 15); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_3_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_28_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 3) >> 7); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_28_14_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 3) >> 17); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_14_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 3) >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 3) >> 13); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x1ffffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot0_8_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_8_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_28_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 3) >> 11); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x1fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_3_1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_1_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_9_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_1_1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_1_1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_slot0_12_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_12_10_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot0_17_10_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 14) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot0_12_6_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_6_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 3) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_27_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000000) | (tie_t << 27); +} + +static unsigned +Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 8) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot0_23_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_18_13_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 3) >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_17_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_9_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_11_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae_slot0_5_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_5_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_4_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_4_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_18_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_19_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot0_19_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_18_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 13) >> 21); + return tie_t; +} + +static void +Field_fld_ae_slot0_18_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_5_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_4_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_19_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_19_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_19_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_23_19_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_14_13_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_17_13_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_13_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_23_22_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_28_24_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 3) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_24_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_17_14_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_slot0_28_26_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 3) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_28_26_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c000000) | (tie_t << 26); +} + +static unsigned +Field_fld_ae_slot0_23_17_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot0_23_17_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot0_9_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_9_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_9_9_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_slot0_7_3_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_3_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae_slot0_12_9_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 19) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_12_9_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_slot0_14_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot0_14_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 6) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_16_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 6) >> 18); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 6) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_17_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot1_7_4_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot1_25_1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 6) >> 7); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_slot1_0_0_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot1_0_0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot1_3_0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot1_25_9_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 6) >> 15); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_9_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 6) >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x3ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot1_3_3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae_slot1_3_2_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot1_3_2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 6) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_18_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 6) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot1_17_8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot1_17_13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot1_12_8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot1_12_8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot1_17_17_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot1_17_17_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot1_25_22_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 6) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_22_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae_slot1_25_23_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 6) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot1_25_23_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae_slot2_28_4_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 3) >> 7); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_4_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot2_3_0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot2_3_0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 3) >> 18); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_15_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x1fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_5_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 3) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_20_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_7_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_fld_ae_slot2_9_1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 22) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot2_9_2_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_2_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot2_28_19_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 3) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_19_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot2_14_0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 17) >> 17); + return tie_t; +} + +static void +Field_fld_ae_slot2_14_0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot2_28_17_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 3) >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_17_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot2_14_5_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot2_14_5_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_slot2_16_15_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot2_16_15_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 3) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_25_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_slot2_14_10_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot2_14_10_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot2_19_15_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot2_28_5_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 3) >> 8); + return tie_t; +} + +static void +Field_fld_ae_slot2_28_5_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0x1fffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_slot2_9_6_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_6_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae_slot2_9_8_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_8_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot2_14_14_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot2_14_14_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_slot3_36_12_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 20) | (insn[0] >> 12); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_12_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 20); +} + +static unsigned +Field_fld_ae_slot3_11_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot3_11_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_30_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 12) >> 12); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot3_9_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 17) >> 17); + return tie_t; +} + +static void +Field_fld_ae_slot3_14_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_25_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae_slot3_19_19_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_19_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_14_10_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_4_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_ae_slot3_24_10_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot3_36_16_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 16) | (insn[0] >> 16); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_16_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 16); +} + +static unsigned +Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_10_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_24_20_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_20_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_9_5_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot3_16_13_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot3_24_19_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 7) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot3_24_19_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x1f80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 10) | (insn[0] >> 22); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_22_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xffc00000) | (tie_t << 22); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 10); +} + +static unsigned +Field_fld_ae_slot3_19_17_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_17_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot3_14_13_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot3_14_13_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_15_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot3_14_12_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot3_14_12_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot3_9_1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 22) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot3_9_1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_slot3_9_3_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 22) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot3_9_3_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae_slot3_36_19_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 13) | (insn[0] >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot3_36_19_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xfff80000) | (tie_t << 19); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 13); +} + +static unsigned +Field_fld_ae_slot3_19_18_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot3_19_18_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 16) | (insn[0] >> 16); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 16); +} + +static unsigned +Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 13) | (insn[0] >> 19); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xfff80000) | (tie_t << 19); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 13); +} + +static unsigned +Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 15) | (insn[0] >> 17); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xfffe0000) | (tie_t << 17); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 15); +} + +static unsigned +Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 11) | (insn[0] >> 21); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffe00000) | (tie_t << 21); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 11); +} + +static unsigned +Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_15_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 5) | (insn[0] >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 5); +} + +static unsigned +Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 14); +} + +static unsigned +Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae2_slot0_12_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_ae2_slot0_12_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_12_2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_fld_ae2_slot0_12_2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae2_slot0_14_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_fld_ae2_slot0_14_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 8) | (insn[0] >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xff000000) | (tie_t << 24); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 8); +} + +static unsigned +Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_15_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot0_15_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae2_slot0_40_26_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 6) | (insn[0] >> 26); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_26_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 6); +} + +static unsigned +Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + return tie_t; +} + +static void +Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae2_slot0_18_17_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_18_17_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | (insn[1] & 0x1ff); + tie_t = (tie_t << 9) | (insn[0] >> 23); + return tie_t; +} + +static void +Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xff800000) | (tie_t << 23); + insn[1] = (insn[1] & ~0x1ff) | (tie_t >> 9); +} + +static unsigned +Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 20) | (insn[0] >> 12); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 20); +} + +static unsigned +Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot1_11_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot1_11_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 16) | (insn[0] >> 16); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 16); +} + +static unsigned +Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); + return tie_t; +} + +static void +Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot1_36_17_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 15) | (insn[0] >> 17); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_17_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffe0000) | (tie_t << 17); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 15); +} + +static unsigned +Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot1_3_3_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot1_3_3_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 18); +} + +static unsigned +Field_fld_ae2_slot1_3_2_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot1_3_2_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot1_36_18_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_18_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 14); +} + +static unsigned +Field_fld_ae2_slot1_36_22_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 10) | (insn[0] >> 22); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_22_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xffc00000) | (tie_t << 22); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 10); +} + +static unsigned +Field_fld_ae2_slot1_36_23_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 9) | (insn[0] >> 23); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_23_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xff800000) | (tie_t << 23); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 9); +} + +static unsigned +Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 14); +} + +static unsigned +Field_fld_ae2_slot2_17_0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_fld_ae2_slot2_17_0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 7) >> 12); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0x1ffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 7) >> 22); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 14) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + return tie_t; +} + +static void +Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae2_slot2_42_26_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 6) | (insn[0] >> 26); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_26_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 6); +} + +static unsigned +Field_fld_ae2_slot2_42_28_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | (insn[1] & 0x7ff); + tie_t = (tie_t << 4) | (insn[0] >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot2_42_28_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xf0000000) | (tie_t << 28); + insn[1] = (insn[1] & ~0x7ff) | (tie_t >> 4); +} + +static unsigned +Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 7) >> 16); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x1fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 12) >> 21); + return tie_t; +} + +static void +Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 15) | (insn[0] >> 17); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xfffe0000) | (tie_t << 17); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 15); +} + +static unsigned +Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 20) | (insn[0] >> 12); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 20); +} + +static unsigned +Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 14) | (insn[0] >> 18); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 14); +} + +static unsigned +Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 24) | (insn[0] >> 8); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff00) | (tie_t << 8); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 24); +} + +static unsigned +Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae3_slot0_32_16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 16) | (insn[0] >> 16); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xffff0000) | (tie_t << 16); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 16); +} + +static unsigned +Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 21) | (insn[0] >> 11); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xfffff800) | (tie_t << 11); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 21); +} + +static unsigned +Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 19) | (insn[0] >> 13); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffffe000) | (tie_t << 13); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 19); +} + +static unsigned +Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 5) | (insn[0] >> 27); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 5); +} + +static unsigned +Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae3_slot0_7_2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_fld_ae3_slot0_7_2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 18); +} + +static unsigned +Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_9_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ae3_slot0_9_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae3_slot1_23_17_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_17_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot1_23_0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot1_23_11_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 8) >> 19); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_11_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 8) >> 21); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 8) >> 23); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae3_slot1_23_19_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_19_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae3_slot1_3_1_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae3_slot1_3_1_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae3_slot1_23_9_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_9_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 2) >> 18); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 2) >> 14); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 2) >> 20); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 2) >> 7); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae5_slot0_29_17_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 2) >> 19); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_17_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x3ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 2) >> 10); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x3fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 2) >> 15); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 2) >> 29); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000000) | (tie_t << 27); +} + +static unsigned +Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2) | (tie_t << 1); +} + +static unsigned +Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 2) >> 17); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x3fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae5_slot0_29_6_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 2) >> 8); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_6_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0x3fffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 19) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae5_slot0_29_19_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 2) >> 21); + return tie_t; +} + +static void +Field_fld_ae5_slot0_29_19_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x3ff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae5_slot0_7_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae5_slot0_7_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 19) >> 23); + return tie_t; +} + +static void +Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae5_slot0_12_6_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_fld_ae5_slot0_12_6_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae5_slot1_1_0_Slot_ae5_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot1_1_0_Slot_ae5_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot2_24_0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 7) >> 7); + return tie_t; +} + +static void +Field_fld_ae5_slot2_24_0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae5_slot2_14_5_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_ae5_slot2_14_5_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae5_slot2_9_7_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_fld_ae5_slot2_9_7_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 7) >> 24); + return tie_t; +} + +static void +Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 7) >> 22); + return tie_t; +} + +static void +Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot0_29_5_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 2) >> 7); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_5_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 2) >> 17); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x3fff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 2) >> 20); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae6_slot0_7_4_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae6_slot0_7_4_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 2) >> 12); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0x3ffffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 2) >> 15); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 2) >> 16); + return tie_t; +} + +static void +Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x3fffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 4) >> 16); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae6_slot1_27_3_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 4) >> 7); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_3_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae6_slot1_2_0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae6_slot1_2_0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 4) >> 19); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 4) >> 24); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 4) >> 10); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xfffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae6_slot1_9_5_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot1_9_5_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae6_slot1_27_21_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 4) >> 25); + return tie_t; +} + +static void +Field_fld_ae6_slot1_27_21_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe00000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae6_slot2_24_0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 7) >> 7); + return tie_t; +} + +static void +Field_fld_ae6_slot2_24_0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 7) >> 22); + return tie_t; +} + +static void +Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 7) >> 21); + return tie_t; +} + +static void +Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot2_24_10_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_ae6_slot2_24_10_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_fld_ae6_slot2_24_20_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot2_24_20_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae6_slot3_37_13_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | (insn[1] & 0x3f); + tie_t = (tie_t << 19) | (insn[0] >> 13); + return tie_t; +} + +static void +Field_fld_ae6_slot3_37_13_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffe000) | (tie_t << 13); + insn[1] = (insn[1] & ~0x3f) | (tie_t >> 19); +} + +static unsigned +Field_fld_ae6_slot3_12_0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 19) >> 19); + return tie_t; +} + +static void +Field_fld_ae6_slot3_12_0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | (insn[1] & 0x3f); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x3f) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | (insn[1] & 0x3f); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x3f) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae6_slot3_24_20_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot3_24_20_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae6_slot3_14_0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 17) >> 17); + return tie_t; +} + +static void +Field_fld_ae6_slot3_14_0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | (insn[1] & 0x3f); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x3f) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_ae7_slot0_23_0_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_ae7_slot0_23_0_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 8) >> 21); + return tie_t; +} + +static void +Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + return tie_t; +} + +static void +Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot0_12_6_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot0_12_6_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot1_23_0_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_ae7_slot1_23_0_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 8) >> 21); + return tie_t; +} + +static void +Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + return tie_t; +} + +static void +Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot1_12_6_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot1_12_6_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae7_slot2_36_12_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 20) | (insn[0] >> 12); + return tie_t; +} + +static void +Field_fld_ae7_slot2_36_12_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 20); +} + +static unsigned +Field_fld_ae7_slot2_11_0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); + return tie_t; +} + +static void +Field_fld_ae7_slot2_11_0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | (insn[1] & 0x1f); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x1f) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae7_slot2_14_10_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae7_slot2_14_10_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae7_slot3_35_11_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | (insn[1] & 0xf); + tie_t = (tie_t << 21) | (insn[0] >> 11); + return tie_t; +} + +static void +Field_fld_ae7_slot3_35_11_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffff800) | (tie_t << 11); + insn[1] = (insn[1] & ~0xf) | (tie_t >> 21); +} + +static unsigned +Field_fld_ae7_slot3_10_0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 21) >> 21); + return tie_t; +} + +static void +Field_fld_ae7_slot3_10_0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | (insn[1] & 0xf); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0xf) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae7_slot3_24_10_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_ae7_slot3_24_10_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae7_slot3_4_0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae7_slot3_4_0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | (insn[1] & 0xf); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0xf) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | (insn[1] & 0xf); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0xf) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 17) >> 22); + return tie_t; +} + +static void +Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 0) >> 18); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 0) >> 12); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 0) >> 8); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot0_13_13_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_fld_ae8_slot0_13_13_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 0) >> 20); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae8_slot0_31_7_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 0) >> 7); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_7_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae8_slot0_6_0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ae8_slot0_6_0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot0_31_9_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 0) >> 9); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_9_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0xfffffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 0) >> 15); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae8_slot0_7_5_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ae8_slot0_7_5_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 18) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 14) >> 18); + return tie_t; +} + +static void +Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 0) >> 19); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0xfff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae8_slot0_8_0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_ae8_slot0_8_0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot0_17_8_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot0_17_8_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae8_slot0_31_21_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 0) >> 21); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_21_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe00000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae8_slot0_31_22_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 0) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_22_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae8_slot0_31_23_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 0) >> 23); + return tie_t; +} + +static void +Field_fld_ae8_slot0_31_23_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + return tie_t; +} + +static void +Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 2) >> 14); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae8_slot1_17_15_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae8_slot1_17_15_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae8_slot1_29_5_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 2) >> 7); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_5_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae8_slot1_4_0_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae8_slot1_4_0_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 2) >> 10); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x3fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot1_29_9_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 2) >> 11); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_9_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x3ffffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 2) >> 15); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 2) >> 20); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae8_slot1_29_22_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 2) >> 24); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_22_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae8_slot1_29_23_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 2) >> 25); + return tie_t; +} + +static void +Field_fld_ae8_slot1_29_23_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[1] << 5) >> 7); + return tie_t; +} + +static void +Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[1] = (insn[1] & ~0x7fffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae8_slot2_33_9_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 23) | (insn[0] >> 9); + return tie_t; +} + +static void +Field_fld_ae8_slot2_33_9_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffffe00) | (tie_t << 9); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 23); +} + +static unsigned +Field_fld_ae8_slot2_8_0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_ae8_slot2_8_0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot2_33_25_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae8_slot2_33_25_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae8_slot2_19_15_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae8_slot2_19_15_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[1] << 5) >> 23); + return tie_t; +} + +static void +Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[1] = (insn[1] & ~0x7fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[1] << 5) >> 13); + return tie_t; +} + +static void +Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[1] = (insn[1] & ~0x7ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[1] << 5) >> 8); + return tie_t; +} + +static void +Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[1] = (insn[1] & ~0x7fffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[1] << 19) >> 22); + return tie_t; +} + +static void +Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[1] = (insn[1] & ~0x1ff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 4) >> 20); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 4) >> 16); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 4) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 4) >> 12); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot0_27_17_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 4) >> 21); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_17_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 4) >> 24); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae9_slot0_27_3_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 4) >> 7); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_3_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae9_slot0_2_0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae9_slot0_2_0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 4) >> 14); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 4) >> 17); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae9_slot0_7_6_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae9_slot0_7_6_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 14) >> 18); + return tie_t; +} + +static void +Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae9_slot0_27_19_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 4) >> 23); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_19_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 19) >> 24); + return tie_t; +} + +static void +Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 23) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae9_slot0_27_22_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 4) >> 26); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_22_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 4) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 5) >> 21); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae9_slot1_26_17_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 5) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_17_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae9_slot1_26_2_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 5) >> 7); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_2_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x7fffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae9_slot1_1_0_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae9_slot1_1_0_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 5) >> 13); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x7ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot1_26_9_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 5) >> 14); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_9_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x7fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 5) >> 18); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x7ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae9_slot1_3_2_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae9_slot1_3_2_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 5) >> 23); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 5) >> 25); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae9_slot1_26_22_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 5) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_22_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae9_slot1_26_23_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot1_26_23_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae9_slot2_33_9_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 23) | (insn[0] >> 9); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_9_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffffe00) | (tie_t << 9); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 23); +} + +static unsigned +Field_fld_ae9_slot2_8_0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 23) >> 23); + return tie_t; +} + +static void +Field_fld_ae9_slot2_8_0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 6) | (insn[0] >> 26); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 6); +} + +static unsigned +Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 4) | (insn[0] >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xf0000000) | (tie_t << 28); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 4); +} + +static unsigned +Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | (insn[1] & 0x3); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x3) | (tie_t >> 18); +} + +static unsigned +Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 7) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 7) >> 21); + return tie_t; +} + +static void +Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae9_slot3_31_7_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 0) >> 7); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_7_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae9_slot3_6_0_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); + return tie_t; +} + +static void +Field_fld_ae9_slot3_6_0_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 0) >> 25); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae9_slot3_4_4_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae9_slot3_4_4_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 0) >> 15); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 0) >> 20); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 0) >> 26); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc000000) | (tie_t << 26); +} + +static unsigned +Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 0) >> 28); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000000) | (tie_t << 28); +} + +static unsigned +Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 0) >> 14); + return tie_t; +} + +static void +Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); +} + +static unsigned +Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 7) >> 23); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 7) >> 19); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 7) >> 25); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 7) >> 15); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot0_24_17_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 7) >> 24); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_17_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae10_slot0_24_0_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 7) >> 7); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_0_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 7) >> 17); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 7) >> 20); + return tie_t; +} + +static void +Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae10_slot0_7_6_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot0_7_6_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 14) >> 18); + return tie_t; +} + +static void +Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae10_slot0_17_8_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot0_17_8_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 6) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 6) >> 18); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae10_slot1_25_17_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 6) >> 23); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_17_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae10_slot1_25_1_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 6) >> 7); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_1_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x3fffffe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae10_slot1_0_0_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot1_0_0_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot1_25_9_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 6) >> 15); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_9_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x3fffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 6) >> 19); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x3ffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae10_slot1_3_2_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot1_3_2_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 6) >> 24); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 6) >> 26); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 14) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae10_slot1_25_22_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 6) >> 28); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_22_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae10_slot1_25_23_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 6) >> 29); + return tie_t; +} + +static void +Field_fld_ae10_slot1_25_23_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae10_slot2_34_10_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 22) | (insn[0] >> 10); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_10_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffffc00) | (tie_t << 10); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 22); +} + +static unsigned +Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 1) | (insn[0] >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x80000000) | (tie_t << 31); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 1); +} + +static unsigned +Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[1] << 29) >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[1] = (insn[1] & ~0x6) | (tie_t << 1); +} + +static unsigned +Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 18); +} + +static unsigned +Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae10_slot3_34_10_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 22) | (insn[0] >> 10); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_10_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xfffffc00) | (tie_t << 10); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 22); +} + +static unsigned +Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 7) | (insn[0] >> 25); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xfe000000) | (tie_t << 25); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 7); +} + +static unsigned +Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae10_slot3_4_4_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot3_4_4_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 17) | (insn[0] >> 15); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xffff8000) | (tie_t << 15); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 17); +} + +static unsigned +Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 12) | (insn[0] >> 20); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfff00000) | (tie_t << 20); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 12); +} + +static unsigned +Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 1) | (insn[0] >> 31); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x80000000) | (tie_t << 31); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 1); +} + +static unsigned +Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 2) >> 22); + return tie_t; +} + +static void +Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[1] << 29) >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[1] = (insn[1] & ~0x6) | (tie_t << 1); +} + +static unsigned +Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 18) | (insn[0] >> 14); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0xffffc000) | (tie_t << 14); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 18); +} + +static unsigned +Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); +} + +static unsigned +Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 9) >> 21); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 9) >> 17); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot0_22_17_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 9) >> 26); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_17_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae4_slot0_22_20_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_20_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae4_slot0_22_0_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 9) >> 9); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_0_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot0_3_1_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot0_3_1_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 9) >> 22); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 9) >> 15); + return tie_t; +} + +static void +Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x7fffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 9) >> 21); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x7ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae4_slot1_22_17_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 9) >> 26); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_17_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae4_slot1_22_0_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 9) >> 9); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_0_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 9) >> 17); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot1_3_1_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot1_3_1_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 9) >> 22); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae4_slot2_23_0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8); + return tie_t; +} + +static void +Field_fld_ae4_slot2_23_0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 8) >> 8; + insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 8) >> 23); + return tie_t; +} + +static void +Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae4_slot2_23_17_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + return tie_t; +} + +static void +Field_fld_ae4_slot2_23_17_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae4_slot2_4_0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot2_4_0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae4_slot3_27_3_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 4) >> 7); + return tie_t; +} + +static void +Field_fld_ae4_slot3_27_3_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae4_slot3_2_0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot3_2_0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 22) >> 22); + return tie_t; +} + +static void +Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae4_slot3_19_19_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_fld_ae4_slot3_19_19_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae4_slot3_19_5_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 12) >> 17); + return tie_t; +} + +static void +Field_fld_ae4_slot3_19_5_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae4_slot3_27_20_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 4) >> 24); + return tie_t; +} + +static void +Field_fld_ae4_slot3_27_20_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae4_slot3_14_10_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot3_14_10_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae4_slot4_22_0_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 23) | ((insn[0] << 9) >> 9); + return tie_t; +} + +static void +Field_fld_ae4_slot4_22_0_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 9) >> 9; + insn[0] = (insn[0] & ~0x7fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 9) >> 24); + return tie_t; +} + +static void +Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_t_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_t_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 23) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e0) | (tie_t << 5); +} + +static unsigned +Field_t_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_bbi_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_bbi_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_bbi_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 24) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_imm8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_imm8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_imm8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29); + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_imm8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); + tie_t = (val << 24) >> 29; + insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14); +} + +static unsigned +Field_imm8_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_imm8_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_imm8_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_imm8_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_imm8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_s_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_s8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_s8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_s8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_s8_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_s8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_s8_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_s8_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_imms8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_imms8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 22) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); + tie_t = (val << 21) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 20) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_imm12b_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_imm12b_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 20) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_imm12b_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_imm12b_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 10) | ((insn[0] << 18) >> 22); + return tie_t; +} + +static void +Field_imm12b_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0) | (tie_t << 4); + tie_t = (val << 20) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_imm12b_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm12b_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_imm12b_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); +} + +static unsigned +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 11) | ((insn[0] << 13) >> 21); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 17) >> 21; + insn[0] = (insn[0] & ~0x7ff00) | (tie_t << 8); + tie_t = (val << 16) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_imm16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 14) | ((insn[0] << 14) >> 18); + return tie_t; +} + +static void +Field_imm16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff0) | (tie_t << 4); + tie_t = (val << 16) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_imm16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_imm16_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_imm16_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_imm16_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_offset_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 17) | ((insn[0] << 15) >> 15); + return tie_t; +} + +static void +Field_offset_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff) | (tie_t << 0); + tie_t = (val << 14) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_offset_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 17) | ((insn[0] << 15) >> 15); + return tie_t; +} + +static void +Field_offset_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff) | (tie_t << 0); + tie_t = (val << 14) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_offset_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_offset_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_op2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_op2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_op2_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_op2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_op2_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_op2_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_op2_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_op2_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_r_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_disp_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_r_disp_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_r_3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r_3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_sae_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_sae_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_sae_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sae_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_sae_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_sal_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_sal_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_sal_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sal_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_sargt_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_sargt_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sargt_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_sargt_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_sas_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sas_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_sas_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_sas_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_sas_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 24) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_sas_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_sas_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_sas_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_sas_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_sas_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_sas_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_t2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_t2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_t2_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_t2_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); +} + +static unsigned +Field_s2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_r2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_r2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_r2_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_r2_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_t4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_t4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_t4_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_t4_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); +} + +static unsigned +Field_s4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_s4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_s4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_s4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_s4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_s4_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_s4_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_s4_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_s4_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_s4_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_r4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_r4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_r4_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_r4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_r4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_r4_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_r4_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_r4_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_t8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_r8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_xt_wbr15_imm_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_xt_wbr15_imm_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_xt_wbr15_imm_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_xt_wloop_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_xt_wloop_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_arithmetic_art_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_art_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_art_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_art_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot4_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot4_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_a_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_a_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_d1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_d1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_v0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_arr_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_bt_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_ds_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 6) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 6) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 16) >> 26); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_br4t_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_br4t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpcnv_arr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_arr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_hpcnv_arr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_arr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_hpcnv_art_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_art_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_hpcnv_art_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_art_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i3_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i3_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i32pos_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 23) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 29) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i64x2_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_imm2_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_imm2_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_su_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_su_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_loads_stores_vu_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_vu_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_vu_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_vu_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_vu_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_vu_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_vu_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_vu_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_pks_d_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_d_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_pos_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_pos_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_pks_s_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_pks_s_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_rng_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_rng_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_a_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_a_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_shift_a0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_a0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_a0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_shift_a0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_a0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_a0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_d_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_shift_d0_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d0_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_shift_d1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_d1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_d1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_da_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_da_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_da_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_da_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_shift_da_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_da_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_i16_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i16_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_i32_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_shift_i32_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i32_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_i32_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 7) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i32_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_shift_i32_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i32_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_sem_shift_i32_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i32_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_shift_i64_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i64_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_i64_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i64_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_sem_shift_i64_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i64_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_shift_i64_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i64_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_shift_i64_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i64_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_shift_imm32_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_imm32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_imm32_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_imm32_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_imm8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_imm8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_shift_sd_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_sd_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_sd_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_sd_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_shift_sd_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_sd_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_shift_sd_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_sd_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_shift_sd_Slot_ae8_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_sd_Slot_ae8_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_arr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_arr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_arr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_arr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_arr_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_arr_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_art_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_art_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_art_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_art_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_art_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_art_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vr_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vr_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_sp32cvt_vt_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_sp32cvt_vt_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_brt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_brt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 23) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpcnv_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpcnv_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_d0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_d2_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d2_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae4_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae4_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_q0_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q0_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_multiply_q1_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_q1_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_ds_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_ds_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_ds_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_ds_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_ds_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_ds_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_reduction_sort_v0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_reduction_sort_v0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_isel_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_isel_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_ss_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_ss_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_select_vu_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_select_vu_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 1) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000000) | (tie_t << 30); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 1) >> 31); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000000) | (tie_t << 30); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 4) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | (insn[1] & 0x1); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x1) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spfma_vp_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vp_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vr_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vr_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vs_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vs_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spfma_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_dr_to_dr_imm_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_dr_imm_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_multiply_d1_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d1_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_multiply_d1_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d1_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_multiply_d1_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d1_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_multiply_d1_Slot_ae4_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d1_Slot_ae4_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_multiply_d3_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d3_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_multiply_d3_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d3_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_multiply_d3_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d3_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_multiply_d3_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_multiply_d3_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_rng_d_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_d_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_shift_e_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_e_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_shift_i8_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i8_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vp_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vp_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vp_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vp_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vp_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vp_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vq_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vq_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vq_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vq_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_spaddsub_vq_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spaddsub_vq_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_sb_loads_stores_iba2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_sb_loads_stores_iba2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_ardecnorm16_ar_u_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_ardecnorm16_ar_u_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_lb_db_ops_ar_u_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_db_ops_ar_u_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_lb_db_ops_iba_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_lb_db_ops_iba_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_rng_a_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_a_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_rng_art_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_art_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_rng_i2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_i2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_rng_imm2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_imm2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_nn_c0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_c0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae_sem_mul_nn_c1_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 24) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_c1_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0xf8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae_sem_mul_nn_c2_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_c2_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_mul_nn_c3_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_c3_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_nn_q0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_q0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_mul_nn_q1_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_q1_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_nn_q2_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_q2_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_mul_nn_q3_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 12) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_q3_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_sem_mul_nn_v0_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_v0_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_mul_nn_v1_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | (insn[1] & 0x7); + tie_t = (tie_t << 2) | (insn[0] >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_v1_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xc0000000) | (tie_t << 30); + insn[1] = (insn[1] & ~0x7) | (tie_t >> 2); +} + +static unsigned +Field_fld_ae_sem_mul_nn_v2_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 14) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_v2_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_sem_mul_nn_v3_Slot_ae8_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[1] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_nn_v3_Slot_ae8_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[1] = (insn[1] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_hpfma_vp_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vp_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_hpfma_vu_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vu_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_vu_Slot_ae9_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vu_Slot_ae9_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vu_Slot_ae9_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vu_Slot_ae9_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vu_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vu_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vu_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vu_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_sem_spfma_vq_Slot_ae10_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vq_Slot_ae10_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_ae_sem_spfma_vq_Slot_ae10_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 2) >> 27); + return tie_t; +} + +static void +Field_fld_ae_sem_spfma_vq_Slot_ae10_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000000) | (tie_t << 25); +} + +static unsigned +Field_fld_inst_12_12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_inst_12_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_inst_12_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_inst_12_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_fld_inst_13_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_fld_inst_13_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); +} + +static unsigned +Field_fld_inst_19_17_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_fld_inst_19_17_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_inst_19_18_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_fld_inst_19_18_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_inst_23_12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_fld_inst_23_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_fld_inst_23_16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_fld_inst_23_16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_inst_4_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_inst_4_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_inst_5_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_inst_5_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_inst_7_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_inst_7_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_inst_7_6_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_inst_7_6_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_inst_7_7_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_inst_7_7_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_inst_9_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_inst_9_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) +{ + /* Do nothing. */ +} + +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 4; +} + +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 8; +} + +static unsigned +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 12; +} + +static unsigned +Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +enum xtensa_field_id { + FIELD_t, + FIELD_bbi4, + FIELD_bbi, + FIELD_imm12, + FIELD_imm8, + FIELD_s, + FIELD_s8, + FIELD_imms8, + FIELD_imm12b, + FIELD_imm16, + FIELD_m, + FIELD_n, + FIELD_offset, + FIELD_op0, + FIELD_op1, + FIELD_op2, + FIELD_r, + FIELD_r_disp, + FIELD_r_3, + FIELD_sa4, + FIELD_sae4, + FIELD_sae, + FIELD_sal, + FIELD_sargt, + FIELD_sas4, + FIELD_sas, + FIELD_sr, + FIELD_st, + FIELD_thi3, + FIELD_imm4, + FIELD_mn, + FIELD_i, + FIELD_imm6lo, + FIELD_imm6hi, + FIELD_imm7lo, + FIELD_imm7hi, + FIELD_z, + FIELD_imm6, + FIELD_imm7, + FIELD_t2, + FIELD_s2, + FIELD_r2, + FIELD_t4, + FIELD_s4, + FIELD_r4, + FIELD_t8, + FIELD_r8, + FIELD_xt_wbr15_imm, + FIELD_xt_wloop_imm, + FIELD_ae_fld_Inst16b_12, + FIELD_ae_fld_Inst16b_15_13, + FIELD_fld_ae_sem_arithmetic_art, + FIELD_fld_ae_sem_arithmetic_ds, + FIELD_fld_ae_sem_arithmetic_v, + FIELD_fld_ae_sem_arithmetic_v0, + FIELD_fld_ae_sem_arithmetic_v1, + FIELD_fld_ae_sem_arithmetic_va, + FIELD_fld_ae_sem_arithmetic_vs, + FIELD_fld_ae_sem_dr_to_ar_a, + FIELD_fld_ae_sem_dr_to_ar_ab, + FIELD_fld_ae_sem_dr_to_ar_ai, + FIELD_fld_ae_sem_dr_to_ar_aoe, + FIELD_fld_ae_sem_dr_to_ar_d, + FIELD_fld_ae_sem_dr_to_ar_d0, + FIELD_fld_ae_sem_dr_to_ar_d1, + FIELD_fld_ae_sem_dr_to_ar_imm8, + FIELD_fld_ae_sem_dr_to_ar_v0, + FIELD_fld_ae_sem_dr_to_ar_vr, + FIELD_fld_ae_sem_dr_to_dr_arr, + FIELD_fld_ae_sem_dr_to_dr_bt, + FIELD_fld_ae_sem_dr_to_dr_ds, + FIELD_fld_ae_sem_dr_to_dr_imm2, + FIELD_fld_ae_sem_dr_to_dr_immed, + FIELD_fld_ae_sem_dr_to_dr_movi_imm, + FIELD_fld_ae_sem_dr_to_dr_v, + FIELD_fld_ae_sem_dr_to_dr_v0, + FIELD_fld_ae_sem_dr_to_dr_v1, + FIELD_fld_ae_sem_hpcmp_br4t, + FIELD_fld_ae_sem_hpcmp_vr, + FIELD_fld_ae_sem_hpcmp_vs, + FIELD_fld_ae_sem_hpcnv_arr, + FIELD_fld_ae_sem_hpcnv_art, + FIELD_fld_ae_sem_hpcnv_i_imm4, + FIELD_fld_ae_sem_hpcnv_vr, + FIELD_fld_ae_sem_hpcnv_vt, + FIELD_fld_ae_sem_hprminmaxnum_vr, + FIELD_fld_ae_sem_hprminmaxnum_vt, + FIELD_fld_ae_sem_lb_ops_iba, + FIELD_fld_ae_sem_loads_stores_a, + FIELD_fld_ae_sem_loads_stores_a_0, + FIELD_fld_ae_sem_loads_stores_av, + FIELD_fld_ae_sem_loads_stores_av1, + FIELD_fld_ae_sem_loads_stores_end, + FIELD_fld_ae_sem_loads_stores_i128, + FIELD_fld_ae_sem_loads_stores_i16, + FIELD_fld_ae_sem_loads_stores_i3, + FIELD_fld_ae_sem_loads_stores_i32, + FIELD_fld_ae_sem_loads_stores_i32pos, + FIELD_fld_ae_sem_loads_stores_i64, + FIELD_fld_ae_sem_loads_stores_i64half, + FIELD_fld_ae_sem_loads_stores_i64neg, + FIELD_fld_ae_sem_loads_stores_i64pos, + FIELD_fld_ae_sem_loads_stores_i64x2, + FIELD_fld_ae_sem_loads_stores_i8, + FIELD_fld_ae_sem_loads_stores_imm2, + FIELD_fld_ae_sem_loads_stores_su, + FIELD_fld_ae_sem_loads_stores_uu, + FIELD_fld_ae_sem_loads_stores_v, + FIELD_fld_ae_sem_loads_stores_v1, + FIELD_fld_ae_sem_loads_stores_vu, + FIELD_fld_ae_sem_loads_stores_x, + FIELD_fld_ae_sem_pks_d, + FIELD_fld_ae_sem_pks_pos, + FIELD_fld_ae_sem_pks_s, + FIELD_fld_ae_sem_rng_v0, + FIELD_fld_ae_sem_rng_v1, + FIELD_fld_ae_sem_sb_loads_stores_iba, + FIELD_fld_ae_sem_shift_a, + FIELD_fld_ae_sem_shift_a0, + FIELD_fld_ae_sem_shift_d, + FIELD_fld_ae_sem_shift_d0, + FIELD_fld_ae_sem_shift_d1, + FIELD_fld_ae_sem_shift_da, + FIELD_fld_ae_sem_shift_i16, + FIELD_fld_ae_sem_shift_i32, + FIELD_fld_ae_sem_shift_i64, + FIELD_fld_ae_sem_shift_imm32, + FIELD_fld_ae_sem_shift_imm8, + FIELD_fld_ae_sem_shift_sd, + FIELD_fld_ae_sem_sp32cvt_arr, + FIELD_fld_ae_sem_sp32cvt_art, + FIELD_fld_ae_sem_sp32cvt_i_imm5, + FIELD_fld_ae_sem_sp32cvt_vr, + FIELD_fld_ae_sem_sp32cvt_vt, + FIELD_fld_ae_sem_spmisc_brt, + FIELD_fld_ae_sem_spmisc_vr, + FIELD_fld_ae_sem_spmisc_vs, + FIELD_fld_ae_slot0_11_10, + FIELD_fld_ae_slot0_11_11, + FIELD_fld_ae_slot0_11_8, + FIELD_fld_ae_slot0_11_9, + FIELD_fld_ae_slot0_12_0, + FIELD_fld_ae_slot0_12_10, + FIELD_fld_ae_slot0_12_12, + FIELD_fld_ae_slot0_12_2, + FIELD_fld_ae_slot0_12_6, + FIELD_fld_ae_slot0_12_8, + FIELD_fld_ae_slot0_12_9, + FIELD_fld_ae_slot0_14_12, + FIELD_fld_ae_slot0_14_13, + FIELD_fld_ae_slot0_17_10, + FIELD_fld_ae_slot0_17_12, + FIELD_fld_ae_slot0_17_13, + FIELD_fld_ae_slot0_17_14, + FIELD_fld_ae_slot0_17_15, + FIELD_fld_ae_slot0_17_16, + FIELD_fld_ae_slot0_17_17, + FIELD_fld_ae_slot0_17_8, + FIELD_fld_ae_slot0_18_13, + FIELD_fld_ae_slot0_18_15, + FIELD_fld_ae_slot0_18_16, + FIELD_fld_ae_slot0_18_8, + FIELD_fld_ae_slot0_19_12, + FIELD_fld_ae_slot0_19_15, + FIELD_fld_ae_slot0_19_19, + FIELD_fld_ae_slot0_19_8, + FIELD_fld_ae_slot0_1_0, + FIELD_fld_ae_slot0_1_1, + FIELD_fld_ae_slot0_20_16, + FIELD_fld_ae_slot0_20_20, + FIELD_fld_ae_slot0_23_15, + FIELD_fld_ae_slot0_23_17, + FIELD_fld_ae_slot0_23_19, + FIELD_fld_ae_slot0_23_22, + FIELD_fld_ae_slot0_28_10, + FIELD_fld_ae_slot0_28_12, + FIELD_fld_ae_slot0_28_14, + FIELD_fld_ae_slot0_28_15, + FIELD_fld_ae_slot0_28_16, + FIELD_fld_ae_slot0_28_17, + FIELD_fld_ae_slot0_28_19, + FIELD_fld_ae_slot0_28_21, + FIELD_fld_ae_slot0_28_22, + FIELD_fld_ae_slot0_28_24, + FIELD_fld_ae_slot0_28_26, + FIELD_fld_ae_slot0_28_27, + FIELD_fld_ae_slot0_28_4, + FIELD_fld_ae_slot0_28_8, + FIELD_fld_ae_slot0_3_0, + FIELD_fld_ae_slot0_3_1, + FIELD_fld_ae_slot0_3_2, + FIELD_fld_ae_slot0_3_3, + FIELD_fld_ae_slot0_4_0, + FIELD_fld_ae_slot0_4_4, + FIELD_fld_ae_slot0_5_0, + FIELD_fld_ae_slot0_5_4, + FIELD_fld_ae_slot0_7_0, + FIELD_fld_ae_slot0_7_2, + FIELD_fld_ae_slot0_7_3, + FIELD_fld_ae_slot0_7_4, + FIELD_fld_ae_slot0_8_8, + FIELD_fld_ae_slot0_9_4, + FIELD_fld_ae_slot0_9_8, + FIELD_fld_ae_slot0_9_9, + FIELD_fld_ae_slot1_0_0, + FIELD_fld_ae_slot1_12_8, + FIELD_fld_ae_slot1_17_13, + FIELD_fld_ae_slot1_17_17, + FIELD_fld_ae_slot1_17_8, + FIELD_fld_ae_slot1_25_1, + FIELD_fld_ae_slot1_25_12, + FIELD_fld_ae_slot1_25_13, + FIELD_fld_ae_slot1_25_16, + FIELD_fld_ae_slot1_25_17, + FIELD_fld_ae_slot1_25_18, + FIELD_fld_ae_slot1_25_20, + FIELD_fld_ae_slot1_25_22, + FIELD_fld_ae_slot1_25_23, + FIELD_fld_ae_slot1_25_8, + FIELD_fld_ae_slot1_25_9, + FIELD_fld_ae_slot1_3_0, + FIELD_fld_ae_slot1_3_2, + FIELD_fld_ae_slot1_3_3, + FIELD_fld_ae_slot1_7_4, + FIELD_fld_ae_sem_arithmetic_e, + FIELD_fld_ae_sem_arithmetic_ep, + FIELD_fld_ae_sem_arithmetic_ep1, + FIELD_fld_ae_sem_dr_to_ar_ei, + FIELD_fld_ae_sem_dr_to_ar_eo, + FIELD_fld_ae_sem_dr_to_dr_immed_N, + FIELD_fld_ae_sem_fpmov_i_imm4, + FIELD_fld_ae_sem_fpmov_vr, + FIELD_fld_ae_sem_fpmov_vs, + FIELD_fld_ae_sem_fpmov_vt, + FIELD_fld_ae_sem_fpmov_vu, + FIELD_fld_ae_sem_hpcmp_vt, + FIELD_fld_ae_sem_hpcnv_vs, + FIELD_fld_ae_sem_hpfma_vr, + FIELD_fld_ae_sem_hpfma_vs, + FIELD_fld_ae_sem_hpfma_vt, + FIELD_fld_ae_sem_movfpstate_v, + FIELD_fld_ae_sem_multiply_acc_ep, + FIELD_fld_ae_sem_multiply_d0, + FIELD_fld_ae_sem_multiply_d2, + FIELD_fld_ae_sem_multiply_q0, + FIELD_fld_ae_sem_multiply_q1, + FIELD_fld_ae_sem_reduction_sort_ds, + FIELD_fld_ae_sem_reduction_sort_v, + FIELD_fld_ae_sem_reduction_sort_v0, + FIELD_fld_ae_sem_select_isel, + FIELD_fld_ae_sem_select_ss, + FIELD_fld_ae_sem_select_vr, + FIELD_fld_ae_sem_select_vs, + FIELD_fld_ae_sem_select_vt, + FIELD_fld_ae_sem_select_vu, + FIELD_fld_ae_sem_spaddsub_vr, + FIELD_fld_ae_sem_spaddsub_vs, + FIELD_fld_ae_sem_spaddsub_vt, + FIELD_fld_ae_sem_spaddsub_vu, + FIELD_fld_ae_sem_spfma_i_imm1, + FIELD_fld_ae_sem_spfma_i_imm3, + FIELD_fld_ae_sem_spfma_vp, + FIELD_fld_ae_sem_spfma_vr, + FIELD_fld_ae_sem_spfma_vs, + FIELD_fld_ae_sem_spfma_vt, + FIELD_fld_ae_sem_spmisc_vsM, + FIELD_fld_ae_sem_spmisc_vt, + FIELD_fld_ae_sem_spmisc_vtM, + FIELD_fld_ae_slot2_14_0, + FIELD_fld_ae_slot2_14_10, + FIELD_fld_ae_slot2_14_14, + FIELD_fld_ae_slot2_14_5, + FIELD_fld_ae_slot2_16_15, + FIELD_fld_ae_slot2_19_15, + FIELD_fld_ae_slot2_28_15, + FIELD_fld_ae_slot2_28_17, + FIELD_fld_ae_slot2_28_19, + FIELD_fld_ae_slot2_28_20, + FIELD_fld_ae_slot2_28_25, + FIELD_fld_ae_slot2_28_4, + FIELD_fld_ae_slot2_28_5, + FIELD_fld_ae_slot2_3_0, + FIELD_fld_ae_slot2_9_0, + FIELD_fld_ae_slot2_9_1, + FIELD_fld_ae_slot2_9_2, + FIELD_fld_ae_slot2_9_5, + FIELD_fld_ae_slot2_9_6, + FIELD_fld_ae_slot2_9_7, + FIELD_fld_ae_slot2_9_8, + FIELD_fld_ae_sem_dr_to_dr_imm, + FIELD_fld_ae_sem_multiply_d1, + FIELD_fld_ae_sem_multiply_d3, + FIELD_fld_ae_sem_rng_d, + FIELD_fld_ae_sem_shift_e, + FIELD_fld_ae_sem_shift_i8, + FIELD_fld_ae_slot3_11_0, + FIELD_fld_ae_slot3_14_0, + FIELD_fld_ae_slot3_14_10, + FIELD_fld_ae_slot3_14_12, + FIELD_fld_ae_slot3_14_13, + FIELD_fld_ae_slot3_16_13, + FIELD_fld_ae_slot3_19_0, + FIELD_fld_ae_slot3_19_10, + FIELD_fld_ae_slot3_19_15, + FIELD_fld_ae_slot3_19_17, + FIELD_fld_ae_slot3_19_18, + FIELD_fld_ae_slot3_19_19, + FIELD_fld_ae_slot3_24_10, + FIELD_fld_ae_slot3_24_19, + FIELD_fld_ae_slot3_24_20, + FIELD_fld_ae_slot3_36_12, + FIELD_fld_ae_slot3_36_16, + FIELD_fld_ae_slot3_36_19, + FIELD_fld_ae_slot3_36_20, + FIELD_fld_ae_slot3_36_22, + FIELD_fld_ae_slot3_36_25, + FIELD_fld_ae_slot3_36_30, + FIELD_fld_ae_slot3_4_0, + FIELD_fld_ae_slot3_9_0, + FIELD_fld_ae_slot3_9_1, + FIELD_fld_ae_slot3_9_3, + FIELD_fld_ae_slot3_9_5, + FIELD_fld_ae2_slot0_0_0, + FIELD_fld_ae2_slot0_11_4, + FIELD_fld_ae2_slot0_11_8, + FIELD_fld_ae2_slot0_11_9, + FIELD_fld_ae2_slot0_12_0, + FIELD_fld_ae2_slot0_12_2, + FIELD_fld_ae2_slot0_12_4, + FIELD_fld_ae2_slot0_12_8, + FIELD_fld_ae2_slot0_14_13, + FIELD_fld_ae2_slot0_14_8, + FIELD_fld_ae2_slot0_15_0, + FIELD_fld_ae2_slot0_15_12, + FIELD_fld_ae2_slot0_15_13, + FIELD_fld_ae2_slot0_15_15, + FIELD_fld_ae2_slot0_15_4, + FIELD_fld_ae2_slot0_15_8, + FIELD_fld_ae2_slot0_17_13, + FIELD_fld_ae2_slot0_17_17, + FIELD_fld_ae2_slot0_18_15, + FIELD_fld_ae2_slot0_18_17, + FIELD_fld_ae2_slot0_18_18, + FIELD_fld_ae2_slot0_1_0, + FIELD_fld_ae2_slot0_23_18, + FIELD_fld_ae2_slot0_23_19, + FIELD_fld_ae2_slot0_3_0, + FIELD_fld_ae2_slot0_40_16, + FIELD_fld_ae2_slot0_40_17, + FIELD_fld_ae2_slot0_40_18, + FIELD_fld_ae2_slot0_40_19, + FIELD_fld_ae2_slot0_40_21, + FIELD_fld_ae2_slot0_40_23, + FIELD_fld_ae2_slot0_40_24, + FIELD_fld_ae2_slot0_40_25, + FIELD_fld_ae2_slot0_40_26, + FIELD_fld_ae2_slot0_40_27, + FIELD_fld_ae2_slot0_7_0, + FIELD_fld_ae2_slot0_7_4, + FIELD_fld_ae2_slot0_7_6, + FIELD_fld_ae2_slot0_7_7, + FIELD_fld_ae2_slot0_8_8, + FIELD_fld_ae2_slot0_9_8, + FIELD_fld_ae2_slot1_0_0, + FIELD_fld_ae2_slot1_11_0, + FIELD_fld_ae2_slot1_11_10, + FIELD_fld_ae2_slot1_11_8, + FIELD_fld_ae2_slot1_14_10, + FIELD_fld_ae2_slot1_14_11, + FIELD_fld_ae2_slot1_14_12, + FIELD_fld_ae2_slot1_14_14, + FIELD_fld_ae2_slot1_14_8, + FIELD_fld_ae2_slot1_36_12, + FIELD_fld_ae2_slot1_36_14, + FIELD_fld_ae2_slot1_36_15, + FIELD_fld_ae2_slot1_36_16, + FIELD_fld_ae2_slot1_36_17, + FIELD_fld_ae2_slot1_36_18, + FIELD_fld_ae2_slot1_36_20, + FIELD_fld_ae2_slot1_36_22, + FIELD_fld_ae2_slot1_36_23, + FIELD_fld_ae2_slot1_3_0, + FIELD_fld_ae2_slot1_3_1, + FIELD_fld_ae2_slot1_3_2, + FIELD_fld_ae2_slot1_3_3, + FIELD_fld_ae2_slot1_7_4, + FIELD_fld_ae2_slot1_9_8, + FIELD_fld_ae2_slot1_9_9, + FIELD_fld_ae2_slot2_14_10, + FIELD_fld_ae2_slot2_17_0, + FIELD_fld_ae2_slot2_17_10, + FIELD_fld_ae2_slot2_17_15, + FIELD_fld_ae2_slot2_17_17, + FIELD_fld_ae2_slot2_19_10, + FIELD_fld_ae2_slot2_19_15, + FIELD_fld_ae2_slot2_19_18, + FIELD_fld_ae2_slot2_19_9, + FIELD_fld_ae2_slot2_24_10, + FIELD_fld_ae2_slot2_24_15, + FIELD_fld_ae2_slot2_24_20, + FIELD_fld_ae2_slot2_24_5, + FIELD_fld_ae2_slot2_24_9, + FIELD_fld_ae2_slot2_42_18, + FIELD_fld_ae2_slot2_42_20, + FIELD_fld_ae2_slot2_42_25, + FIELD_fld_ae2_slot2_42_26, + FIELD_fld_ae2_slot2_42_28, + FIELD_fld_ae2_slot2_42_30, + FIELD_fld_ae2_slot2_4_0, + FIELD_fld_ae2_slot2_9_5, + FIELD_fld_ae_sem_spaddsub_vp, + FIELD_fld_ae_sem_spaddsub_vq, + FIELD_fld_ae3_slot0_11_11, + FIELD_fld_ae3_slot0_11_4, + FIELD_fld_ae3_slot0_11_8, + FIELD_fld_ae3_slot0_12_12, + FIELD_fld_ae3_slot0_12_8, + FIELD_fld_ae3_slot0_13_13, + FIELD_fld_ae3_slot0_13_8, + FIELD_fld_ae3_slot0_1_0, + FIELD_fld_ae3_slot0_32_11, + FIELD_fld_ae3_slot0_32_12, + FIELD_fld_ae3_slot0_32_13, + FIELD_fld_ae3_slot0_32_14, + FIELD_fld_ae3_slot0_32_15, + FIELD_fld_ae3_slot0_32_16, + FIELD_fld_ae3_slot0_32_17, + FIELD_fld_ae3_slot0_32_18, + FIELD_fld_ae3_slot0_32_20, + FIELD_fld_ae3_slot0_32_27, + FIELD_fld_ae3_slot0_32_8, + FIELD_fld_ae3_slot0_3_0, + FIELD_fld_ae3_slot0_3_2, + FIELD_fld_ae3_slot0_3_3, + FIELD_fld_ae3_slot0_4_0, + FIELD_fld_ae3_slot0_4_4, + FIELD_fld_ae3_slot0_5_0, + FIELD_fld_ae3_slot0_5_4, + FIELD_fld_ae3_slot0_7_0, + FIELD_fld_ae3_slot0_7_2, + FIELD_fld_ae3_slot0_7_4, + FIELD_fld_ae3_slot0_7_6, + FIELD_fld_ae3_slot0_8_8, + FIELD_fld_ae3_slot0_9_4, + FIELD_fld_ae3_slot0_9_8, + FIELD_fld_ae_sem_dr_to_ar_ar_s, + FIELD_fld_ae_sem_sb_loads_stores_iba2, + FIELD_fld_ae3_slot1_23_0, + FIELD_fld_ae3_slot1_23_11, + FIELD_fld_ae3_slot1_23_12, + FIELD_fld_ae3_slot1_23_13, + FIELD_fld_ae3_slot1_23_15, + FIELD_fld_ae3_slot1_23_16, + FIELD_fld_ae3_slot1_23_17, + FIELD_fld_ae3_slot1_23_19, + FIELD_fld_ae3_slot1_23_6, + FIELD_fld_ae3_slot1_23_8, + FIELD_fld_ae3_slot1_23_9, + FIELD_fld_ae3_slot1_3_0, + FIELD_fld_ae3_slot1_3_1, + FIELD_fld_ae3_slot1_3_2, + FIELD_fld_ae3_slot1_3_3, + FIELD_fld_ae3_slot1_7_4, + FIELD_fld_ae3_slot1_9_8, + FIELD_fld_AE_ARDECNORM16_ar_u, + FIELD_fld_ae5_slot0_11_10, + FIELD_fld_ae5_slot0_11_4, + FIELD_fld_ae5_slot0_11_8, + FIELD_fld_ae5_slot0_11_9, + FIELD_fld_ae5_slot0_12_10, + FIELD_fld_ae5_slot0_12_4, + FIELD_fld_ae5_slot0_12_6, + FIELD_fld_ae5_slot0_12_8, + FIELD_fld_ae5_slot0_12_9, + FIELD_fld_ae5_slot0_1_0, + FIELD_fld_ae5_slot0_1_1, + FIELD_fld_ae5_slot0_29_12, + FIELD_fld_ae5_slot0_29_13, + FIELD_fld_ae5_slot0_29_15, + FIELD_fld_ae5_slot0_29_16, + FIELD_fld_ae5_slot0_29_17, + FIELD_fld_ae5_slot0_29_18, + FIELD_fld_ae5_slot0_29_19, + FIELD_fld_ae5_slot0_29_20, + FIELD_fld_ae5_slot0_29_27, + FIELD_fld_ae5_slot0_29_5, + FIELD_fld_ae5_slot0_29_6, + FIELD_fld_ae5_slot0_29_8, + FIELD_fld_ae5_slot0_2_0, + FIELD_fld_ae5_slot0_3_0, + FIELD_fld_ae5_slot0_3_2, + FIELD_fld_ae5_slot0_4_0, + FIELD_fld_ae5_slot0_4_4, + FIELD_fld_ae5_slot0_7_0, + FIELD_fld_ae5_slot0_7_4, + FIELD_fld_ae5_slot0_7_7, + FIELD_fld_ae5_slot0_8_8, + FIELD_fld_ae_sem_lb_db_ops_ar_u, + FIELD_fld_ae_sem_lb_db_ops_iba, + FIELD_fld_ae_sem_rng_a, + FIELD_fld_ae_sem_rng_art, + FIELD_fld_ae_sem_rng_i2, + FIELD_fld_ae_sem_rng_imm2, + FIELD_fld_ae5_slot1_1_0, + FIELD_fld_ae5_slot2_14_10, + FIELD_fld_ae5_slot2_14_14, + FIELD_fld_ae5_slot2_14_5, + FIELD_fld_ae5_slot2_24_0, + FIELD_fld_ae5_slot2_24_15, + FIELD_fld_ae5_slot2_24_17, + FIELD_fld_ae5_slot2_24_20, + FIELD_fld_ae5_slot2_4_0, + FIELD_fld_ae5_slot2_9_0, + FIELD_fld_ae5_slot2_9_5, + FIELD_fld_ae5_slot2_9_7, + FIELD_fld_ae6_slot0_10_10, + FIELD_fld_ae6_slot0_15_15, + FIELD_fld_ae6_slot0_29_10, + FIELD_fld_ae6_slot0_29_13, + FIELD_fld_ae6_slot0_29_14, + FIELD_fld_ae6_slot0_29_15, + FIELD_fld_ae6_slot0_29_18, + FIELD_fld_ae6_slot0_29_20, + FIELD_fld_ae6_slot0_29_5, + FIELD_fld_ae6_slot0_4_0, + FIELD_fld_ae6_slot0_4_4, + FIELD_fld_ae6_slot0_7_4, + FIELD_fld_ae6_slot0_7_7, + FIELD_fld_ae6_slot0_9_8, + FIELD_fld_ae6_slot0_9_9, + FIELD_fld_ae6_slot1_14_14, + FIELD_fld_ae6_slot1_27_12, + FIELD_fld_ae6_slot1_27_15, + FIELD_fld_ae6_slot1_27_20, + FIELD_fld_ae6_slot1_27_21, + FIELD_fld_ae6_slot1_27_3, + FIELD_fld_ae6_slot1_27_6, + FIELD_fld_ae6_slot1_2_0, + FIELD_fld_ae6_slot1_9_5, + FIELD_fld_ae6_slot1_9_6, + FIELD_fld_ae6_slot1_9_7, + FIELD_fld_ae6_slot1_9_8, + FIELD_fld_ae6_slot1_9_9, + FIELD_fld_ae6_slot2_10_10, + FIELD_fld_ae6_slot2_11_10, + FIELD_fld_ae6_slot2_24_0, + FIELD_fld_ae6_slot2_24_10, + FIELD_fld_ae6_slot2_24_14, + FIELD_fld_ae6_slot2_24_15, + FIELD_fld_ae6_slot2_24_20, + FIELD_fld_ae6_slot2_4_2, + FIELD_fld_ae6_slot2_9_5, + FIELD_fld_ae6_slot3_10_10, + FIELD_fld_ae6_slot3_12_0, + FIELD_fld_ae6_slot3_14_0, + FIELD_fld_ae6_slot3_14_10, + FIELD_fld_ae6_slot3_14_13, + FIELD_fld_ae6_slot3_14_5, + FIELD_fld_ae6_slot3_24_20, + FIELD_fld_ae6_slot3_37_13, + FIELD_fld_ae6_slot3_37_15, + FIELD_fld_ae6_slot3_37_20, + FIELD_fld_ae6_slot3_37_30, + FIELD_fld_ae6_slot3_9_5, + FIELD_fld_ae7_slot0_12_6, + FIELD_fld_ae7_slot0_23_0, + FIELD_fld_ae7_slot0_23_13, + FIELD_fld_ae7_slot0_23_17, + FIELD_fld_ae7_slot0_23_18, + FIELD_fld_ae7_slot0_23_6, + FIELD_fld_ae7_slot0_7_4, + FIELD_fld_ae7_slot0_7_6, + FIELD_fld_ae7_slot0_7_7, + FIELD_fld_ae7_slot1_12_6, + FIELD_fld_ae7_slot1_23_0, + FIELD_fld_ae7_slot1_23_13, + FIELD_fld_ae7_slot1_23_17, + FIELD_fld_ae7_slot1_23_18, + FIELD_fld_ae7_slot1_23_6, + FIELD_fld_ae7_slot1_7_4, + FIELD_fld_ae7_slot1_7_6, + FIELD_fld_ae7_slot1_7_7, + FIELD_fld_ae7_slot2_11_0, + FIELD_fld_ae7_slot2_14_10, + FIELD_fld_ae7_slot2_14_5, + FIELD_fld_ae7_slot2_36_12, + FIELD_fld_ae7_slot2_36_15, + FIELD_fld_ae7_slot2_36_20, + FIELD_fld_ae7_slot2_36_25, + FIELD_fld_ae7_slot2_36_30, + FIELD_fld_ae7_slot2_9_5, + FIELD_fld_ae7_slot3_10_0, + FIELD_fld_ae7_slot3_14_10, + FIELD_fld_ae7_slot3_14_5, + FIELD_fld_ae7_slot3_24_10, + FIELD_fld_ae7_slot3_35_11, + FIELD_fld_ae7_slot3_35_20, + FIELD_fld_ae7_slot3_35_25, + FIELD_fld_ae7_slot3_35_30, + FIELD_fld_ae7_slot3_4_0, + FIELD_fld_ae7_slot3_9_5, + FIELD_fld_ae8_slot0_13_12, + FIELD_fld_ae8_slot0_13_13, + FIELD_fld_ae8_slot0_13_4, + FIELD_fld_ae8_slot0_13_9, + FIELD_fld_ae8_slot0_17_4, + FIELD_fld_ae8_slot0_17_8, + FIELD_fld_ae8_slot0_31_12, + FIELD_fld_ae8_slot0_31_15, + FIELD_fld_ae8_slot0_31_18, + FIELD_fld_ae8_slot0_31_19, + FIELD_fld_ae8_slot0_31_20, + FIELD_fld_ae8_slot0_31_21, + FIELD_fld_ae8_slot0_31_22, + FIELD_fld_ae8_slot0_31_23, + FIELD_fld_ae8_slot0_31_7, + FIELD_fld_ae8_slot0_31_8, + FIELD_fld_ae8_slot0_31_9, + FIELD_fld_ae8_slot0_3_0, + FIELD_fld_ae8_slot0_6_0, + FIELD_fld_ae8_slot0_7_4, + FIELD_fld_ae8_slot0_7_5, + FIELD_fld_ae8_slot0_7_7, + FIELD_fld_ae8_slot0_8_0, + FIELD_fld_ae8_slot1_17_13, + FIELD_fld_ae8_slot1_17_14, + FIELD_fld_ae8_slot1_17_15, + FIELD_fld_ae8_slot1_17_8, + FIELD_fld_ae8_slot1_29_12, + FIELD_fld_ae8_slot1_29_13, + FIELD_fld_ae8_slot1_29_18, + FIELD_fld_ae8_slot1_29_20, + FIELD_fld_ae8_slot1_29_22, + FIELD_fld_ae8_slot1_29_23, + FIELD_fld_ae8_slot1_29_5, + FIELD_fld_ae8_slot1_29_8, + FIELD_fld_ae8_slot1_29_9, + FIELD_fld_ae8_slot1_3_0, + FIELD_fld_ae8_slot1_3_3, + FIELD_fld_ae8_slot1_4_0, + FIELD_fld_ae8_slot1_7_4, + FIELD_fld_ae8_slot2_19_10, + FIELD_fld_ae8_slot2_19_15, + FIELD_fld_ae8_slot2_33_15, + FIELD_fld_ae8_slot2_33_25, + FIELD_fld_ae8_slot2_33_9, + FIELD_fld_ae8_slot2_34_30, + FIELD_fld_ae8_slot2_39_35, + FIELD_fld_ae8_slot2_44_35, + FIELD_fld_ae8_slot2_58_34, + FIELD_fld_ae8_slot2_58_35, + FIELD_fld_ae8_slot2_58_40, + FIELD_fld_ae8_slot2_58_50, + FIELD_fld_ae8_slot2_8_0, + FIELD_fld_ae8_slot2_9_0, + FIELD_fld_ae_sem_mul_nn_c0, + FIELD_fld_ae_sem_mul_nn_c1, + FIELD_fld_ae_sem_mul_nn_c2, + FIELD_fld_ae_sem_mul_nn_c3, + FIELD_fld_ae_sem_mul_nn_q0, + FIELD_fld_ae_sem_mul_nn_q1, + FIELD_fld_ae_sem_mul_nn_q2, + FIELD_fld_ae_sem_mul_nn_q3, + FIELD_fld_ae_sem_mul_nn_v0, + FIELD_fld_ae_sem_mul_nn_v1, + FIELD_fld_ae_sem_mul_nn_v2, + FIELD_fld_ae_sem_mul_nn_v3, + FIELD_fld_ae9_slot0_0_0, + FIELD_fld_ae9_slot0_12_12, + FIELD_fld_ae9_slot0_12_5, + FIELD_fld_ae9_slot0_12_8, + FIELD_fld_ae9_slot0_17_13, + FIELD_fld_ae9_slot0_17_4, + FIELD_fld_ae9_slot0_17_8, + FIELD_fld_ae9_slot0_27_10, + FIELD_fld_ae9_slot0_27_12, + FIELD_fld_ae9_slot0_27_13, + FIELD_fld_ae9_slot0_27_16, + FIELD_fld_ae9_slot0_27_17, + FIELD_fld_ae9_slot0_27_18, + FIELD_fld_ae9_slot0_27_19, + FIELD_fld_ae9_slot0_27_20, + FIELD_fld_ae9_slot0_27_22, + FIELD_fld_ae9_slot0_27_23, + FIELD_fld_ae9_slot0_27_3, + FIELD_fld_ae9_slot0_27_8, + FIELD_fld_ae9_slot0_2_0, + FIELD_fld_ae9_slot0_3_0, + FIELD_fld_ae9_slot0_7_0, + FIELD_fld_ae9_slot0_7_4, + FIELD_fld_ae9_slot0_7_5, + FIELD_fld_ae9_slot0_7_6, + FIELD_fld_ae9_slot0_7_7, + FIELD_fld_ae9_slot0_8_4, + FIELD_fld_ae9_slot0_8_5, + FIELD_fld_ae9_slot0_9_5, + FIELD_fld_ae9_slot1_17_13, + FIELD_fld_ae9_slot1_17_8, + FIELD_fld_ae9_slot1_1_0, + FIELD_fld_ae9_slot1_26_12, + FIELD_fld_ae9_slot1_26_13, + FIELD_fld_ae9_slot1_26_16, + FIELD_fld_ae9_slot1_26_17, + FIELD_fld_ae9_slot1_26_18, + FIELD_fld_ae9_slot1_26_2, + FIELD_fld_ae9_slot1_26_20, + FIELD_fld_ae9_slot1_26_22, + FIELD_fld_ae9_slot1_26_23, + FIELD_fld_ae9_slot1_26_8, + FIELD_fld_ae9_slot1_26_9, + FIELD_fld_ae9_slot1_3_0, + FIELD_fld_ae9_slot1_3_2, + FIELD_fld_ae9_slot1_3_3, + FIELD_fld_ae9_slot1_7_4, + FIELD_fld_ae9_slot2_24_14, + FIELD_fld_ae9_slot2_24_15, + FIELD_fld_ae9_slot2_24_20, + FIELD_fld_ae9_slot2_33_14, + FIELD_fld_ae9_slot2_33_15, + FIELD_fld_ae9_slot2_33_20, + FIELD_fld_ae9_slot2_33_25, + FIELD_fld_ae9_slot2_33_26, + FIELD_fld_ae9_slot2_33_28, + FIELD_fld_ae9_slot2_33_30, + FIELD_fld_ae9_slot2_33_9, + FIELD_fld_ae9_slot2_4_0, + FIELD_fld_ae9_slot2_5_0, + FIELD_fld_ae9_slot2_6_0, + FIELD_fld_ae9_slot2_8_0, + FIELD_fld_ae9_slot2_9_0, + FIELD_fld_ae9_slot2_9_5, + FIELD_fld_ae9_slot2_9_9, + FIELD_fld_ae_sem_hpfma_vp, + FIELD_fld_ae_sem_hpfma_vu, + FIELD_fld_ae_sem_spfma_vu, + FIELD_fld_ae9_slot3_19_15, + FIELD_fld_ae9_slot3_24_20, + FIELD_fld_ae9_slot3_31_14, + FIELD_fld_ae9_slot3_31_15, + FIELD_fld_ae9_slot3_31_20, + FIELD_fld_ae9_slot3_31_25, + FIELD_fld_ae9_slot3_31_26, + FIELD_fld_ae9_slot3_31_28, + FIELD_fld_ae9_slot3_31_7, + FIELD_fld_ae9_slot3_4_0, + FIELD_fld_ae9_slot3_4_3, + FIELD_fld_ae9_slot3_4_4, + FIELD_fld_ae9_slot3_6_0, + FIELD_fld_ae9_slot3_9_0, + FIELD_fld_ae9_slot3_9_5, + FIELD_fld_ae10_slot0_17_13, + FIELD_fld_ae10_slot0_17_4, + FIELD_fld_ae10_slot0_17_8, + FIELD_fld_ae10_slot0_24_0, + FIELD_fld_ae10_slot0_24_10, + FIELD_fld_ae10_slot0_24_12, + FIELD_fld_ae10_slot0_24_13, + FIELD_fld_ae10_slot0_24_16, + FIELD_fld_ae10_slot0_24_17, + FIELD_fld_ae10_slot0_24_18, + FIELD_fld_ae10_slot0_24_20, + FIELD_fld_ae10_slot0_24_8, + FIELD_fld_ae10_slot0_3_0, + FIELD_fld_ae10_slot0_7_4, + FIELD_fld_ae10_slot0_7_6, + FIELD_fld_ae10_slot0_7_7, + FIELD_fld_ae10_slot0_8_4, + FIELD_fld_ae10_slot1_0_0, + FIELD_fld_ae10_slot1_17_13, + FIELD_fld_ae10_slot1_17_8, + FIELD_fld_ae10_slot1_25_1, + FIELD_fld_ae10_slot1_25_12, + FIELD_fld_ae10_slot1_25_13, + FIELD_fld_ae10_slot1_25_16, + FIELD_fld_ae10_slot1_25_17, + FIELD_fld_ae10_slot1_25_18, + FIELD_fld_ae10_slot1_25_20, + FIELD_fld_ae10_slot1_25_22, + FIELD_fld_ae10_slot1_25_23, + FIELD_fld_ae10_slot1_25_8, + FIELD_fld_ae10_slot1_25_9, + FIELD_fld_ae10_slot1_3_0, + FIELD_fld_ae10_slot1_3_2, + FIELD_fld_ae10_slot1_3_3, + FIELD_fld_ae10_slot1_7_4, + FIELD_fld_ae10_slot2_24_20, + FIELD_fld_ae10_slot2_29_20, + FIELD_fld_ae10_slot2_29_25, + FIELD_fld_ae10_slot2_34_10, + FIELD_fld_ae10_slot2_34_14, + FIELD_fld_ae10_slot2_34_15, + FIELD_fld_ae10_slot2_34_20, + FIELD_fld_ae10_slot2_34_25, + FIELD_fld_ae10_slot2_34_30, + FIELD_fld_ae10_slot2_34_31, + FIELD_fld_ae10_slot2_34_33, + FIELD_fld_ae10_slot2_4_0, + FIELD_fld_ae10_slot2_9_0, + FIELD_fld_ae10_slot2_9_5, + FIELD_fld_ae_sem_hpfma_vq, + FIELD_fld_ae_sem_spfma_vq, + FIELD_fld_ae10_slot3_19_15, + FIELD_fld_ae10_slot3_29_20, + FIELD_fld_ae10_slot3_29_25, + FIELD_fld_ae10_slot3_34_10, + FIELD_fld_ae10_slot3_34_14, + FIELD_fld_ae10_slot3_34_15, + FIELD_fld_ae10_slot3_34_20, + FIELD_fld_ae10_slot3_34_25, + FIELD_fld_ae10_slot3_34_30, + FIELD_fld_ae10_slot3_34_31, + FIELD_fld_ae10_slot3_34_33, + FIELD_fld_ae10_slot3_4_0, + FIELD_fld_ae10_slot3_4_3, + FIELD_fld_ae10_slot3_4_4, + FIELD_fld_ae10_slot3_9_0, + FIELD_fld_ae10_slot3_9_5, + FIELD_fld_ae4_slot0_22_0, + FIELD_fld_ae4_slot0_22_12, + FIELD_fld_ae4_slot0_22_13, + FIELD_fld_ae4_slot0_22_16, + FIELD_fld_ae4_slot0_22_17, + FIELD_fld_ae4_slot0_22_18, + FIELD_fld_ae4_slot0_22_20, + FIELD_fld_ae4_slot0_22_6, + FIELD_fld_ae4_slot0_22_8, + FIELD_fld_ae4_slot0_3_0, + FIELD_fld_ae4_slot0_3_1, + FIELD_fld_ae4_slot0_4_4, + FIELD_fld_ae4_slot0_7_4, + FIELD_fld_ae4_slot1_22_0, + FIELD_fld_ae4_slot1_22_12, + FIELD_fld_ae4_slot1_22_13, + FIELD_fld_ae4_slot1_22_16, + FIELD_fld_ae4_slot1_22_17, + FIELD_fld_ae4_slot1_22_18, + FIELD_fld_ae4_slot1_22_8, + FIELD_fld_ae4_slot1_3_0, + FIELD_fld_ae4_slot1_3_1, + FIELD_fld_ae4_slot1_7_4, + FIELD_fld_ae4_slot2_23_0, + FIELD_fld_ae4_slot2_23_12, + FIELD_fld_ae4_slot2_23_15, + FIELD_fld_ae4_slot2_23_17, + FIELD_fld_ae4_slot2_23_20, + FIELD_fld_ae4_slot2_4_0, + FIELD_fld_ae4_slot2_9_5, + FIELD_fld_ae4_slot3_14_10, + FIELD_fld_ae4_slot3_19_15, + FIELD_fld_ae4_slot3_19_19, + FIELD_fld_ae4_slot3_19_5, + FIELD_fld_ae4_slot3_27_20, + FIELD_fld_ae4_slot3_27_25, + FIELD_fld_ae4_slot3_27_3, + FIELD_fld_ae4_slot3_2_0, + FIELD_fld_ae4_slot3_9_0, + FIELD_fld_ae4_slot3_9_5, + FIELD_fld_ae4_slot4_22_0, + FIELD_fld_ae4_slot4_22_15, + FIELD_fld_ae4_slot4_22_20, + FIELD_fld_ae4_slot4_9_5, + FIELD_fld_Inst_11_8, + FIELD_fld_Inst_12_12, + FIELD_fld_Inst_12_8, + FIELD_fld_Inst_13_8, + FIELD_fld_Inst_15_12, + FIELD_fld_Inst_19_17, + FIELD_fld_Inst_19_18, + FIELD_fld_Inst_23_12, + FIELD_fld_Inst_23_16, + FIELD_fld_Inst_4_4, + FIELD_fld_Inst_5_4, + FIELD_fld_Inst_7_4, + FIELD_fld_Inst_7_6, + FIELD_fld_Inst_7_7, + FIELD_fld_Inst_9_8, + FIELD_bitindex, + FIELD_s3to1, + FIELD__ar0, + FIELD__ar4, + FIELD__ar8, + FIELD__ar12, + FIELD__bt16, + FIELD__bs16, + FIELD__br16, + FIELD__brall +}; + + +/* Functional units. */ + +static xtensa_funcUnit_internal funcUnits[] = { + {"XT_LOADSTORE_UNIT", 2}, + { "mul_function", 1 }, + { "mul_S2_function", 1 }, + { "ae_add32x27", 1 }, + { "ae_shift32x4", 1 }, + { "ae_shift32x5", 1 }, + { "ae_leftshift32x5", 2 } +}; + +enum xtensa_funcUnit_id { + FUNCUNIT_XT_LOADSTORE_UNIT, + FUNCUNIT_mul_function, + FUNCUNIT_mul_S2_function, + FUNCUNIT_ae_add32x27, + FUNCUNIT_ae_shift32x4, + FUNCUNIT_ae_shift32x5, + FUNCUNIT_ae_leftshift32x5 +}; + + +/* Register files. */ + +enum xtensa_regfile_id { + REGFILE_AR, + REGFILE_BR, + REGFILE_AE_DR, + REGFILE_AE_VALIGN, + REGFILE_AE_EP, + REGFILE_BR2, + REGFILE_BR4, + REGFILE_BR8, + REGFILE_BR16 +}; + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", REGFILE_AR, 32, 64 }, + { "BR", "b", REGFILE_BR, 1, 16 }, + { "AE_DR", "aed", REGFILE_AE_DR, 64, 32 }, + { "AE_VALIGN", "u", REGFILE_AE_VALIGN, 128, 4 }, + { "AE_EP", "aep", REGFILE_AE_EP, 8, 4 }, + { "BR2", "b", REGFILE_BR, 2, 8 }, + { "BR4", "b", REGFILE_BR, 4, 4 }, + { "BR8", "b", REGFILE_BR, 8, 2 }, + { "BR16", "b", REGFILE_BR, 16, 1 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + { "IMPWIRE", 32, 0, 0, 'i' }, + { "ERI_RD_Rdy", 1, 0, 1, 'i' }, + { "ERI_RD_Out", 14, 0, 1, 'o' }, + { "ERI_RD_In", 32, 0, 2, 'i' }, + { "ERI_WR_Out", 46, 0, 3, 'o' }, + { "ERI_WR_In", 1, 0, 4, 'i' } +}; + +enum xtensa_interface_id { + INTERFACE_IMPWIRE, + INTERFACE_ERI_RD_Rdy, + INTERFACE_ERI_RD_Out, + INTERFACE_ERI_RD_In, + INTERFACE_ERI_WR_Out, + INTERFACE_ERI_WR_In +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table bitmask8 */ +static const unsigned CONST_TBL_bitmask8_0[] = { + 0 & 0xff, + 0x1 & 0xff, + 0x3 & 0xff, + 0x7 & 0xff, + 0xf & 0xff, + 0x1f & 0xff, + 0x3f & 0xff, + 0x7f & 0xff, + 0 +}; + +/* constant table bitmask16 */ +static const unsigned CONST_TBL_bitmask16_0[] = { + 0 & 0xffff, + 0x1 & 0xffff, + 0x3 & 0xffff, + 0x7 & 0xffff, + 0xf & 0xffff, + 0x1f & 0xffff, + 0x3f & 0xffff, + 0x7f & 0xffff, + 0xff & 0xffff, + 0x1ff & 0xffff, + 0x3ff & 0xffff, + 0x7ff & 0xffff, + 0xfff & 0xffff, + 0x1fff & 0xffff, + 0x3fff & 0xffff, + 0x7fff & 0xffff, + 0 +}; + +/* constant table ae_ltr4_table */ +static const unsigned CONST_TBL_ae_ltr4_table_0[] = { + 0 & 0xf, + 0x8 & 0xf, + 0xc & 0xf, + 0xe & 0xf, + 0 +}; + +/* constant table ae_ltr8_table */ +static const unsigned CONST_TBL_ae_ltr8_table_0[] = { + 0 & 0xff, + 0x80 & 0xff, + 0xc0 & 0xff, + 0xe0 & 0xff, + 0xf0 & 0xff, + 0xf8 & 0xff, + 0xfc & 0xff, + 0xfe & 0xff, + 0 +}; + +/* constant table ae_immls64neg */ +static const unsigned CONST_TBL_ae_immls64neg_0[] = { + 0xffffffe0, + 0xffffffe8, + 0xfffffff0, + 0xfffffff8, + 0 +}; + +/* constant table ae_slai72table */ +static const unsigned CONST_TBL_ae_slai72table_0[] = { + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0 +}; + +/* constant table ae_seliencode */ +static const unsigned CONST_TBL_ae_seliencode_0[] = { + 0x4e5 & 0xfff, + 0x65 & 0xfff, + 0x77 & 0xfff, + 0x4f7 & 0xfff, + 0x72e & 0xfff, + 0x29c & 0xfff, + 0xaf & 0xfff, + 0xa6 & 0xfff, + 0x2ef & 0xfff, + 0x10d & 0xfff, + 0x599 & 0xfff, + 0x59f & 0xfff, + 0xb3e & 0xfff, + 0x18f & 0xfff, + 0x51d & 0xfff, + 0xa6 & 0xfff, + 0 +}; + +/* constant table ae_ohba */ +static const unsigned CONST_TBL_ae_ohba_0[] = { + 0x1 & 0x1f, + 0x2 & 0x1f, + 0x3 & 0x1f, + 0x4 & 0x1f, + 0x5 & 0x1f, + 0x6 & 0x1f, + 0x7 & 0x1f, + 0x8 & 0x1f, + 0x9 & 0x1f, + 0xa & 0x1f, + 0xb & 0x1f, + 0xc & 0x1f, + 0xd & 0x1f, + 0xe & 0x1f, + 0xf & 0x1f, + 0x10 & 0x1f, + 0 +}; + +/* constant table ae_ohba2 */ +static const unsigned CONST_TBL_ae_ohba2_0[] = { + 0x1 & 0x1f, + 0x2 & 0x1f, + 0x3 & 0x1f, + 0x4 & 0x1f, + 0x5 & 0x1f, + 0x6 & 0x1f, + 0x7 & 0x1f, + 0x8 & 0x1f, + 0x9 & 0x1f, + 0xa & 0x1f, + 0xb & 0x1f, + 0xc & 0x1f, + 0xd & 0x1f, + 0xe & 0x1f, + 0xf & 0x1f, + 0x10 & 0x1f, + 0 +}; + +/* constant table ae_opnd_tp7 */ +static const unsigned CONST_TBL_ae_opnd_tp7_0[] = { + 0x7 & 0x1f, + 0x8 & 0x1f, + 0x9 & 0x1f, + 0xa & 0x1f, + 0xb & 0x1f, + 0xc & 0x1f, + 0xd & 0x1f, + 0xe & 0x1f, + 0xf & 0x1f, + 0x10 & 0x1f, + 0x11 & 0x1f, + 0x12 & 0x1f, + 0x13 & 0x1f, + 0x14 & 0x1f, + 0x15 & 0x1f, + 0x16 & 0x1f, + 0 +}; + +/* constant table xd_seli_8x8_table0 */ +static const unsigned CONST_TBL_xd_seli_8x8_table0_0[] = { + 0xba987654, + 0xfedc7654, + 0xfedc3210, + 0xba983210, + 0x98765432, + 0xdcba9876, + 0xfeba5410, + 0xfeba7632, + 0xdc985410, + 0xfe76dc54, + 0xba3298dc, + 0xba329810, + 0x54761032, + 0xfe32dc10, + 0xba769854, + 0xfeba7632, + 0xedcba987, + 0xcba98765, + 0xa9876543, + 0x87654321, + 0xf7e6d5c4, + 0xb3a29180, + 0xf3e2d1c0, + 0xb7a69584, + 0xfe76ba32, + 0xeca86420, + 0xfdb97531, + 0xeca87531, + 0xfdb96420, + 0xdc987632, + 0xefcdab89, + 0x32107654, + 0 +}; + +/* constant table xd_seli_8x8_table0_be */ +static const unsigned CONST_TBL_xd_seli_8x8_table0_be_0[] = { + 0x456789ab, + 0x12389ab, + 0x123cdef, + 0x4567cdef, + 0x6789abcd, + 0x23456789, + 0x145abef, + 0x14589cd, + 0x2367abef, + 0x18923ab, + 0x45cd6723, + 0x45cd67ef, + 0xab89efcd, + 0x1cd23ef, + 0x458967ab, + 0x14589cd, + 0x12345678, + 0x3456789a, + 0x56789abc, + 0x789abcde, + 0x8192a3b, + 0x4c5d6e7f, + 0xc1d2e3f, + 0x48596a7b, + 0x18945cd, + 0x13579bdf, + 0x2468ace, + 0x13578ace, + 0x2469bdf, + 0x236789cd, + 0x10325476, + 0xcdef89ab, + 0 +}; + +/* constant table tab_lavunqz_8x8 */ +static const unsigned CONST_TBL_tab_lavunqz_8x8_0[] = { + 0, + 0x7, + 0x70, + 0x76, + 0x700, + 0x706, + 0x760, + 0x765, + 0x7000, + 0x7006, + 0x7060, + 0x7065, + 0x7600, + 0x7605, + 0x7650, + 0x7654, + 0x70000, + 0x70006, + 0x70060, + 0x70065, + 0x70600, + 0x70605, + 0x70650, + 0x70654, + 0x76000, + 0x76005, + 0x76050, + 0x76054, + 0x76500, + 0x76504, + 0x76540, + 0x76543, + 0x700000, + 0x700006, + 0x700060, + 0x700065, + 0x700600, + 0x700605, + 0x700650, + 0x700654, + 0x706000, + 0x706005, + 0x706050, + 0x706054, + 0x706500, + 0x706504, + 0x706540, + 0x706543, + 0x760000, + 0x760005, + 0x760050, + 0x760054, + 0x760500, + 0x760504, + 0x760540, + 0x760543, + 0x765000, + 0x765004, + 0x765040, + 0x765043, + 0x765400, + 0x765403, + 0x765430, + 0x765432, + 0x7000000, + 0x7000006, + 0x7000060, + 0x7000065, + 0x7000600, + 0x7000605, + 0x7000650, + 0x7000654, + 0x7006000, + 0x7006005, + 0x7006050, + 0x7006054, + 0x7006500, + 0x7006504, + 0x7006540, + 0x7006543, + 0x7060000, + 0x7060005, + 0x7060050, + 0x7060054, + 0x7060500, + 0x7060504, + 0x7060540, + 0x7060543, + 0x7065000, + 0x7065004, + 0x7065040, + 0x7065043, + 0x7065400, + 0x7065403, + 0x7065430, + 0x7065432, + 0x7600000, + 0x7600005, + 0x7600050, + 0x7600054, + 0x7600500, + 0x7600504, + 0x7600540, + 0x7600543, + 0x7605000, + 0x7605004, + 0x7605040, + 0x7605043, + 0x7605400, + 0x7605403, + 0x7605430, + 0x7605432, + 0x7650000, + 0x7650004, + 0x7650040, + 0x7650043, + 0x7650400, + 0x7650403, + 0x7650430, + 0x7650432, + 0x7654000, + 0x7654003, + 0x7654030, + 0x7654032, + 0x7654300, + 0x7654302, + 0x7654320, + 0x7654321, + 0x70000000, + 0x70000006, + 0x70000060, + 0x70000065, + 0x70000600, + 0x70000605, + 0x70000650, + 0x70000654, + 0x70006000, + 0x70006005, + 0x70006050, + 0x70006054, + 0x70006500, + 0x70006504, + 0x70006540, + 0x70006543, + 0x70060000, + 0x70060005, + 0x70060050, + 0x70060054, + 0x70060500, + 0x70060504, + 0x70060540, + 0x70060543, + 0x70065000, + 0x70065004, + 0x70065040, + 0x70065043, + 0x70065400, + 0x70065403, + 0x70065430, + 0x70065432, + 0x70600000, + 0x70600005, + 0x70600050, + 0x70600054, + 0x70600500, + 0x70600504, + 0x70600540, + 0x70600543, + 0x70605000, + 0x70605004, + 0x70605040, + 0x70605043, + 0x70605400, + 0x70605403, + 0x70605430, + 0x70605432, + 0x70650000, + 0x70650004, + 0x70650040, + 0x70650043, + 0x70650400, + 0x70650403, + 0x70650430, + 0x70650432, + 0x70654000, + 0x70654003, + 0x70654030, + 0x70654032, + 0x70654300, + 0x70654302, + 0x70654320, + 0x70654321, + 0x76000000, + 0x76000005, + 0x76000050, + 0x76000054, + 0x76000500, + 0x76000504, + 0x76000540, + 0x76000543, + 0x76005000, + 0x76005004, + 0x76005040, + 0x76005043, + 0x76005400, + 0x76005403, + 0x76005430, + 0x76005432, + 0x76050000, + 0x76050004, + 0x76050040, + 0x76050043, + 0x76050400, + 0x76050403, + 0x76050430, + 0x76050432, + 0x76054000, + 0x76054003, + 0x76054030, + 0x76054032, + 0x76054300, + 0x76054302, + 0x76054320, + 0x76054321, + 0x76500000, + 0x76500004, + 0x76500040, + 0x76500043, + 0x76500400, + 0x76500403, + 0x76500430, + 0x76500432, + 0x76504000, + 0x76504003, + 0x76504030, + 0x76504032, + 0x76504300, + 0x76504302, + 0x76504320, + 0x76504321, + 0x76540000, + 0x76540003, + 0x76540030, + 0x76540032, + 0x76540300, + 0x76540302, + 0x76540320, + 0x76540321, + 0x76543000, + 0x76543002, + 0x76543020, + 0x76543021, + 0x76543200, + 0x76543201, + 0x76543210, + 0x76543210, + 0 +}; + +/* constant table tab_lavunqz_16x4 */ +static const unsigned CONST_TBL_tab_lavunqz_16x4_0[] = { + 0 & 0xff, + 0x3 & 0xff, + 0xc & 0xff, + 0xe & 0xff, + 0x30 & 0xff, + 0x32 & 0xff, + 0x38 & 0xff, + 0x39 & 0xff, + 0xc0 & 0xff, + 0xc2 & 0xff, + 0xc8 & 0xff, + 0xc9 & 0xff, + 0xe0 & 0xff, + 0xe1 & 0xff, + 0xe4 & 0xff, + 0xe4 & 0xff, + 0 +}; + +/* constant table xd_recip0_table128_8 */ +static const unsigned CONST_TBL_xd_recip0_table128_8_0[] = { + 0xff & 0xff, + 0xfd & 0xff, + 0xfb & 0xff, + 0xf9 & 0xff, + 0xf7 & 0xff, + 0xf5 & 0xff, + 0xf4 & 0xff, + 0xf2 & 0xff, + 0xf0 & 0xff, + 0xee & 0xff, + 0xed & 0xff, + 0xeb & 0xff, + 0xe9 & 0xff, + 0xe8 & 0xff, + 0xe6 & 0xff, + 0xe4 & 0xff, + 0xe3 & 0xff, + 0xe1 & 0xff, + 0xe0 & 0xff, + 0xde & 0xff, + 0xdd & 0xff, + 0xdb & 0xff, + 0xda & 0xff, + 0xd8 & 0xff, + 0xd7 & 0xff, + 0xd5 & 0xff, + 0xd4 & 0xff, + 0xd3 & 0xff, + 0xd1 & 0xff, + 0xd0 & 0xff, + 0xcf & 0xff, + 0xcd & 0xff, + 0xcc & 0xff, + 0xcb & 0xff, + 0xca & 0xff, + 0xc8 & 0xff, + 0xc7 & 0xff, + 0xc6 & 0xff, + 0xc5 & 0xff, + 0xc4 & 0xff, + 0xc2 & 0xff, + 0xc1 & 0xff, + 0xc0 & 0xff, + 0xbf & 0xff, + 0xbe & 0xff, + 0xbd & 0xff, + 0xbc & 0xff, + 0xbb & 0xff, + 0xba & 0xff, + 0xb9 & 0xff, + 0xb8 & 0xff, + 0xb7 & 0xff, + 0xb6 & 0xff, + 0xb5 & 0xff, + 0xb4 & 0xff, + 0xb3 & 0xff, + 0xb2 & 0xff, + 0xb1 & 0xff, + 0xb0 & 0xff, + 0xaf & 0xff, + 0xae & 0xff, + 0xad & 0xff, + 0xac & 0xff, + 0xab & 0xff, + 0xaa & 0xff, + 0xa9 & 0xff, + 0xa8 & 0xff, + 0xa8 & 0xff, + 0xa7 & 0xff, + 0xa6 & 0xff, + 0xa5 & 0xff, + 0xa4 & 0xff, + 0xa3 & 0xff, + 0xa3 & 0xff, + 0xa2 & 0xff, + 0xa1 & 0xff, + 0xa0 & 0xff, + 0x9f & 0xff, + 0x9f & 0xff, + 0x9e & 0xff, + 0x9d & 0xff, + 0x9c & 0xff, + 0x9c & 0xff, + 0x9b & 0xff, + 0x9a & 0xff, + 0x99 & 0xff, + 0x99 & 0xff, + 0x98 & 0xff, + 0x97 & 0xff, + 0x97 & 0xff, + 0x96 & 0xff, + 0x95 & 0xff, + 0x95 & 0xff, + 0x94 & 0xff, + 0x93 & 0xff, + 0x93 & 0xff, + 0x92 & 0xff, + 0x91 & 0xff, + 0x91 & 0xff, + 0x90 & 0xff, + 0x8f & 0xff, + 0x8f & 0xff, + 0x8e & 0xff, + 0x8e & 0xff, + 0x8d & 0xff, + 0x8c & 0xff, + 0x8c & 0xff, + 0x8b & 0xff, + 0x8b & 0xff, + 0x8a & 0xff, + 0x89 & 0xff, + 0x89 & 0xff, + 0x88 & 0xff, + 0x88 & 0xff, + 0x87 & 0xff, + 0x87 & 0xff, + 0x86 & 0xff, + 0x85 & 0xff, + 0x85 & 0xff, + 0x84 & 0xff, + 0x84 & 0xff, + 0x83 & 0xff, + 0x83 & 0xff, + 0x82 & 0xff, + 0x82 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0 +}; + +/* constant table xd_rsqrt0_table128_8 */ +static const unsigned CONST_TBL_xd_rsqrt0_table128_8_0[] = { + 0xb4 & 0xff, + 0xb3 & 0xff, + 0xb2 & 0xff, + 0xb0 & 0xff, + 0xaf & 0xff, + 0xae & 0xff, + 0xac & 0xff, + 0xab & 0xff, + 0xaa & 0xff, + 0xa9 & 0xff, + 0xa8 & 0xff, + 0xa7 & 0xff, + 0xa6 & 0xff, + 0xa5 & 0xff, + 0xa3 & 0xff, + 0xa2 & 0xff, + 0xa1 & 0xff, + 0xa0 & 0xff, + 0x9f & 0xff, + 0x9e & 0xff, + 0x9e & 0xff, + 0x9d & 0xff, + 0x9c & 0xff, + 0x9b & 0xff, + 0x9a & 0xff, + 0x99 & 0xff, + 0x98 & 0xff, + 0x97 & 0xff, + 0x97 & 0xff, + 0x96 & 0xff, + 0x95 & 0xff, + 0x94 & 0xff, + 0x93 & 0xff, + 0x93 & 0xff, + 0x92 & 0xff, + 0x91 & 0xff, + 0x90 & 0xff, + 0x90 & 0xff, + 0x8f & 0xff, + 0x8e & 0xff, + 0x8e & 0xff, + 0x8d & 0xff, + 0x8c & 0xff, + 0x8c & 0xff, + 0x8b & 0xff, + 0x8a & 0xff, + 0x8a & 0xff, + 0x89 & 0xff, + 0x89 & 0xff, + 0x88 & 0xff, + 0x87 & 0xff, + 0x87 & 0xff, + 0x86 & 0xff, + 0x86 & 0xff, + 0x85 & 0xff, + 0x84 & 0xff, + 0x84 & 0xff, + 0x83 & 0xff, + 0x83 & 0xff, + 0x82 & 0xff, + 0x82 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0x80 & 0xff, + 0xff & 0xff, + 0xfd & 0xff, + 0xfb & 0xff, + 0xf9 & 0xff, + 0xf7 & 0xff, + 0xf6 & 0xff, + 0xf4 & 0xff, + 0xf2 & 0xff, + 0xf1 & 0xff, + 0xef & 0xff, + 0xed & 0xff, + 0xec & 0xff, + 0xea & 0xff, + 0xe9 & 0xff, + 0xe7 & 0xff, + 0xe6 & 0xff, + 0xe4 & 0xff, + 0xe3 & 0xff, + 0xe1 & 0xff, + 0xe0 & 0xff, + 0xdf & 0xff, + 0xdd & 0xff, + 0xdc & 0xff, + 0xdb & 0xff, + 0xda & 0xff, + 0xd8 & 0xff, + 0xd7 & 0xff, + 0xd6 & 0xff, + 0xd5 & 0xff, + 0xd4 & 0xff, + 0xd3 & 0xff, + 0xd2 & 0xff, + 0xd0 & 0xff, + 0xcf & 0xff, + 0xce & 0xff, + 0xcd & 0xff, + 0xcc & 0xff, + 0xcb & 0xff, + 0xca & 0xff, + 0xc9 & 0xff, + 0xc8 & 0xff, + 0xc7 & 0xff, + 0xc6 & 0xff, + 0xc6 & 0xff, + 0xc5 & 0xff, + 0xc4 & 0xff, + 0xc3 & 0xff, + 0xc2 & 0xff, + 0xc1 & 0xff, + 0xc0 & 0xff, + 0xbf & 0xff, + 0xbf & 0xff, + 0xbe & 0xff, + 0xbd & 0xff, + 0xbc & 0xff, + 0xbb & 0xff, + 0xbb & 0xff, + 0xba & 0xff, + 0xb9 & 0xff, + 0xb8 & 0xff, + 0xb8 & 0xff, + 0xb7 & 0xff, + 0xb6 & 0xff, + 0xb5 & 0xff, + 0 +}; + +/* constant table vfpu2_table_mulmux */ +static const unsigned CONST_TBL_vfpu2_table_mulmux_0[] = { + 0xe & 0x3f, + 0x1e & 0x3f, + 0 +}; + +/* constant table vfpu2_table_maddmux */ +static const unsigned CONST_TBL_vfpu2_table_maddmux_0[] = { + 0xe & 0x3f, + 0x21 & 0x3f, + 0x3e & 0x3f, + 0x11 & 0x3f, + 0x1e & 0x3f, + 0x1 & 0x3f, + 0x2e & 0x3f, + 0x31 & 0x3f, + 0 +}; + +/* constant table xdsem_tab_la_default */ +static const unsigned CONST_TBL_xdsem_tab_la_default_0[] = { + 0xffff & 0xffff, + 0xfffe & 0xffff, + 0xfffc & 0xffff, + 0xfff8 & 0xffff, + 0xfff0 & 0xffff, + 0xffe0 & 0xffff, + 0xffc0 & 0xffff, + 0xff80 & 0xffff, + 0xff00 & 0xffff, + 0xfe00 & 0xffff, + 0xfc00 & 0xffff, + 0xf800 & 0xffff, + 0xf000 & 0xffff, + 0xe000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_lahr */ +static const unsigned CONST_TBL_xdsem_tab_lahr_0[] = { + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0 +}; + +/* constant table xdsem_tab_lahs */ +static const unsigned CONST_TBL_xdsem_tab_lahs_0[] = { + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev8_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev8_m64_0[] = { + 0x100 & 0xffff, + 0x200 & 0xffff, + 0x400 & 0xffff, + 0x800 & 0xffff, + 0x1000 & 0xffff, + 0x2000 & 0xffff, + 0x4000 & 0xffff, + 0x8000 & 0xffff, + 0x1 & 0xffff, + 0x2 & 0xffff, + 0x4 & 0xffff, + 0x8 & 0xffff, + 0x10 & 0xffff, + 0x20 & 0xffff, + 0x40 & 0xffff, + 0x80 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev8_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev8_m32_0[] = { + 0x1010 & 0xffff, + 0x2020 & 0xffff, + 0x4040 & 0xffff, + 0x8080 & 0xffff, + 0x101 & 0xffff, + 0x202 & 0xffff, + 0x404 & 0xffff, + 0x808 & 0xffff, + 0x1010 & 0xffff, + 0x2020 & 0xffff, + 0x4040 & 0xffff, + 0x8080 & 0xffff, + 0x101 & 0xffff, + 0x202 & 0xffff, + 0x404 & 0xffff, + 0x808 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev8_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev8_m16_0[] = { + 0x4444 & 0xffff, + 0x8888 & 0xffff, + 0x1111 & 0xffff, + 0x2222 & 0xffff, + 0x4444 & 0xffff, + 0x8888 & 0xffff, + 0x1111 & 0xffff, + 0x2222 & 0xffff, + 0x4444 & 0xffff, + 0x8888 & 0xffff, + 0x1111 & 0xffff, + 0x2222 & 0xffff, + 0x4444 & 0xffff, + 0x8888 & 0xffff, + 0x1111 & 0xffff, + 0x2222 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev8_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev8_m8_0[] = { + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0xaaaa & 0xffff, + 0x5555 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev16_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev16_m64_0[] = { + 0 & 0xffff, + 0 & 0xffff, + 0x3 & 0xffff, + 0x3 & 0xffff, + 0xf & 0xffff, + 0xf & 0xffff, + 0x3f & 0xffff, + 0x3f & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xfc & 0xffff, + 0xfc & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0xc0 & 0xffff, + 0xc0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev16_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev16_m32_0[] = { + 0xff & 0xffff, + 0xff & 0xffff, + 0xcc & 0xffff, + 0xcc & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0x33 & 0xffff, + 0x33 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xcc & 0xffff, + 0xcc & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev16_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev16_m16_0[] = { + 0xff & 0xffff, + 0xff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev16_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev16_m8_0[] = { + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_128rev16_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_128rev16_m32_0[] = { + 0xffff & 0xffff, + 0xffff & 0xffff, + 0xcccc & 0xffff, + 0xcccc & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0x33 & 0xffff, + 0x33 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xcc & 0xffff, + 0xcc & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_128rev16_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_128rev16_m16_0[] = { + 0xffff & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xf0ff & 0xffff, + 0xf0ff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev32_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev32_m64_0[] = { + 0xf00 & 0xffff, + 0xf00 & 0xffff, + 0xf00 & 0xffff, + 0xf00 & 0xffff, + 0xf000 & 0xffff, + 0xf000 & 0xffff, + 0xf000 & 0xffff, + 0xf000 & 0xffff, + 0xf & 0xffff, + 0xf & 0xffff, + 0xf & 0xffff, + 0xf & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0xf0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev32_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev32_m32_0[] = { + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f0 & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0xf0f & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_rev64_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_rev64_m64_0[] = { + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff00 & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0xff & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_r16_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_r16_m64_0[] = { + 0x300 & 0xffff, + 0x300 & 0xffff, + 0xc00 & 0xffff, + 0xc00 & 0xffff, + 0x3000 & 0xffff, + 0x3000 & 0xffff, + 0xc000 & 0xffff, + 0xc000 & 0xffff, + 0x3 & 0xffff, + 0x3 & 0xffff, + 0xc & 0xffff, + 0xc & 0xffff, + 0x30 & 0xffff, + 0x30 & 0xffff, + 0xc0 & 0xffff, + 0xc0 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_r16_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_r16_m32_0[] = { + 0x3030 & 0xffff, + 0x3030 & 0xffff, + 0xc0c0 & 0xffff, + 0xc0c0 & 0xffff, + 0x303 & 0xffff, + 0x303 & 0xffff, + 0xc0c & 0xffff, + 0xc0c & 0xffff, + 0x3030 & 0xffff, + 0x3030 & 0xffff, + 0xc0c0 & 0xffff, + 0xc0c0 & 0xffff, + 0x303 & 0xffff, + 0x303 & 0xffff, + 0xc0c & 0xffff, + 0xc0c & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_r16_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_r16_m16_0[] = { + 0xcccc & 0xffff, + 0xcccc & 0xffff, + 0x3333 & 0xffff, + 0x3333 & 0xffff, + 0xcccc & 0xffff, + 0xcccc & 0xffff, + 0x3333 & 0xffff, + 0x3333 & 0xffff, + 0xcccc & 0xffff, + 0xcccc & 0xffff, + 0x3333 & 0xffff, + 0x3333 & 0xffff, + 0xcccc & 0xffff, + 0xcccc & 0xffff, + 0x3333 & 0xffff, + 0x3333 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_shiftrot_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_shiftrot_m64_0[] = { + 0 & 0xffff, + 0x101 & 0xffff, + 0x303 & 0xffff, + 0x707 & 0xffff, + 0xf0f & 0xffff, + 0x1f1f & 0xffff, + 0x3f3f & 0xffff, + 0x7f7f & 0xffff, + 0xffff & 0xffff, + 0xfefe & 0xffff, + 0xfcfc & 0xffff, + 0xf8f8 & 0xffff, + 0xf0f0 & 0xffff, + 0xe0e0 & 0xffff, + 0xc0c0 & 0xffff, + 0x8080 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_shiftrot_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_shiftrot_m32_0[] = { + 0 & 0xffff, + 0x1111 & 0xffff, + 0x3333 & 0xffff, + 0x7777 & 0xffff, + 0xffff & 0xffff, + 0xeeee & 0xffff, + 0xcccc & 0xffff, + 0x8888 & 0xffff, + 0 & 0xffff, + 0x1111 & 0xffff, + 0x3333 & 0xffff, + 0x7777 & 0xffff, + 0xffff & 0xffff, + 0xeeee & 0xffff, + 0xcccc & 0xffff, + 0x8888 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_shiftrot_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_shiftrot_m16_0[] = { + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 & 0xffff, + 0x5555 & 0xffff, + 0xffff & 0xffff, + 0xaaaa & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_shiftrot_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_shiftrot_m8_0[] = { + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 & 0xffff, + 0xffff & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to16_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to16_m64_0[] = { + 0xf000 & 0xffff, + 0xe000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 & 0xffff, + 0x1 & 0xffff, + 0x3 & 0xffff, + 0x7 & 0xffff, + 0xf & 0xffff, + 0x11e & 0xffff, + 0x33c & 0xffff, + 0x778 & 0xffff, + 0xff0 & 0xffff, + 0x1ee0 & 0xffff, + 0x3cc0 & 0xffff, + 0x7880 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to16_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to16_m32_0[] = { + 0x3c0 & 0xffff, + 0x1680 & 0xffff, + 0x3c00 & 0xffff, + 0x6801 & 0xffff, + 0xc003 & 0xffff, + 0x8016 & 0xffff, + 0x3c & 0xffff, + 0x168 & 0xffff, + 0x3c0 & 0xffff, + 0x1680 & 0xffff, + 0x3c00 & 0xffff, + 0x6801 & 0xffff, + 0xc003 & 0xffff, + 0x8016 & 0xffff, + 0x3c & 0xffff, + 0x168 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to16_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to16_m16_0[] = { + 0x1818 & 0xffff, + 0x6060 & 0xffff, + 0x8181 & 0xffff, + 0x606 & 0xffff, + 0x1818 & 0xffff, + 0x6060 & 0xffff, + 0x8181 & 0xffff, + 0x606 & 0xffff, + 0x1818 & 0xffff, + 0x6060 & 0xffff, + 0x8181 & 0xffff, + 0x606 & 0xffff, + 0x1818 & 0xffff, + 0x6060 & 0xffff, + 0x8181 & 0xffff, + 0x606 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to16_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to16_m8_0[] = { + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0x6666 & 0xffff, + 0x9999 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp16to32_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp16to32_m16_0[] = { + 0x3838 & 0xffff, + 0x6161 & 0xffff, + 0x8383 & 0xffff, + 0x1616 & 0xffff, + 0x3838 & 0xffff, + 0x6161 & 0xffff, + 0x8383 & 0xffff, + 0x1616 & 0xffff, + 0x3838 & 0xffff, + 0x6161 & 0xffff, + 0x8383 & 0xffff, + 0x1616 & 0xffff, + 0x3838 & 0xffff, + 0x6161 & 0xffff, + 0x8383 & 0xffff, + 0x1616 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp16to32_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp16to32_m8_0[] = { + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0x4444 & 0xffff, + 0xbbbb & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to32_m64 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to32_m64_0[] = { + 0xc00 & 0xffff, + 0x1800 & 0xffff, + 0x3000 & 0xffff, + 0x6000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 & 0xffff, + 0x1 & 0xffff, + 0x3 & 0xffff, + 0x6 & 0xffff, + 0xc & 0xffff, + 0x18 & 0xffff, + 0x30 & 0xffff, + 0x160 & 0xffff, + 0x3c0 & 0xffff, + 0x680 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to32_m32 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to32_m32_0[] = { + 0x8020 & 0xffff, + 0x40 & 0xffff, + 0x180 & 0xffff, + 0x200 & 0xffff, + 0x401 & 0xffff, + 0x1802 & 0xffff, + 0x2004 & 0xffff, + 0x4018 & 0xffff, + 0x8020 & 0xffff, + 0x40 & 0xffff, + 0x180 & 0xffff, + 0x200 & 0xffff, + 0x401 & 0xffff, + 0x1802 & 0xffff, + 0x2004 & 0xffff, + 0x4018 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to32_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to32_m16_0[] = { + 0x2184 & 0xffff, + 0x4218 & 0xffff, + 0x8421 & 0xffff, + 0x1842 & 0xffff, + 0x2184 & 0xffff, + 0x4218 & 0xffff, + 0x8421 & 0xffff, + 0x1842 & 0xffff, + 0x2184 & 0xffff, + 0x4218 & 0xffff, + 0x8421 & 0xffff, + 0x1842 & 0xffff, + 0x2184 & 0xffff, + 0x4218 & 0xffff, + 0x8421 & 0xffff, + 0x1842 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp8to32_m8 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp8to32_m8_0[] = { + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0x5a5a & 0xffff, + 0xa5a5 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_ld_exp16to32h_m16 */ +static const unsigned CONST_TBL_xdsem_tab_ld_exp16to32h_m16_0[] = { + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0x3c3c & 0xffff, + 0x6969 & 0xffff, + 0xc3c3 & 0xffff, + 0x9696 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr16to8_m8 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr16to8_m8_0[] = { + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0x8888 & 0xffff, + 0x2222 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr16to8_m16 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr16to8_m16_0[] = { + 0x4242 & 0xffff, + 0x9090 & 0xffff, + 0x2424 & 0xffff, + 0x909 & 0xffff, + 0x4242 & 0xffff, + 0x9090 & 0xffff, + 0x2424 & 0xffff, + 0x909 & 0xffff, + 0x4242 & 0xffff, + 0x9090 & 0xffff, + 0x2424 & 0xffff, + 0x909 & 0xffff, + 0x4242 & 0xffff, + 0x9090 & 0xffff, + 0x2424 & 0xffff, + 0x909 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr16to8_m32 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr16to8_m32_0[] = { + 0x300c & 0xffff, + 0x6108 & 0xffff, + 0xc300 & 0xffff, + 0x8610 & 0xffff, + 0xc30 & 0xffff, + 0x861 & 0xffff, + 0xc3 & 0xffff, + 0x1086 & 0xffff, + 0x300c & 0xffff, + 0x6108 & 0xffff, + 0xc300 & 0xffff, + 0x8610 & 0xffff, + 0xc30 & 0xffff, + 0x861 & 0xffff, + 0xc3 & 0xffff, + 0x1086 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr16to8_m64 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr16to8_m64_0[] = { + 0xf0 & 0xffff, + 0xe0 & 0xffff, + 0xc0 & 0xffff, + 0x80 & 0xffff, + 0 & 0xffff, + 0x100 & 0xffff, + 0x300 & 0xffff, + 0x700 & 0xffff, + 0xf00 & 0xffff, + 0x1e01 & 0xffff, + 0x3c03 & 0xffff, + 0x7807 & 0xffff, + 0xf00f & 0xffff, + 0xe01e & 0xffff, + 0xc03c & 0xffff, + 0x8078 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to8_m8 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to8_m8_0[] = { + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0x2020 & 0xffff, + 0x202 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to8_m16 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to8_m16_0[] = { + 0x8400 & 0xffff, + 0x840 & 0xffff, + 0x84 & 0xffff, + 0x4008 & 0xffff, + 0x8400 & 0xffff, + 0x840 & 0xffff, + 0x84 & 0xffff, + 0x4008 & 0xffff, + 0x8400 & 0xffff, + 0x840 & 0xffff, + 0x84 & 0xffff, + 0x4008 & 0xffff, + 0x8400 & 0xffff, + 0x840 & 0xffff, + 0x84 & 0xffff, + 0x4008 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to8_m32 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to8_m32_0[] = { + 0x802 & 0xffff, + 0x4 & 0xffff, + 0x1008 & 0xffff, + 0x2000 & 0xffff, + 0x4010 & 0xffff, + 0x8120 & 0xffff, + 0x240 & 0xffff, + 0x481 & 0xffff, + 0x802 & 0xffff, + 0x4 & 0xffff, + 0x1008 & 0xffff, + 0x2000 & 0xffff, + 0x4010 & 0xffff, + 0x8120 & 0xffff, + 0x240 & 0xffff, + 0x481 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to8_m64 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to8_m64_0[] = { + 0xc & 0xffff, + 0x18 & 0xffff, + 0x30 & 0xffff, + 0x60 & 0xffff, + 0xc0 & 0xffff, + 0x80 & 0xffff, + 0 & 0xffff, + 0x100 & 0xffff, + 0x300 & 0xffff, + 0x600 & 0xffff, + 0xc00 & 0xffff, + 0x1800 & 0xffff, + 0x3000 & 0xffff, + 0x6001 & 0xffff, + 0xc003 & 0xffff, + 0x8006 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to16_m8 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to16_m8_0[] = { + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 & 0xffff, + 0x3333 & 0xffff, + 0 +}; + +/* constant table xdsem_tab_st_compr32to16_m16 */ +static const unsigned CONST_TBL_xdsem_tab_st_compr32to16_m16_0[] = { + 0xc0c0 & 0xffff, + 0x8484 & 0xffff, + 0xc0c & 0xffff, + 0x4848 & 0xffff, + 0xc0c0 & 0xffff, + 0x8484 & 0xffff, + 0xc0c & 0xffff, + 0x4848 & 0xffff, + 0xc0c0 & 0xffff, + 0x8484 & 0xffff, + 0xc0c & 0xffff, + 0x4848 & 0xffff, + 0xc0c0 & 0xffff, + 0x8484 & 0xffff, + 0xc0c & 0xffff, + 0x4848 & 0xffff, + 0 +}; + +/* constant table bitmask16rev */ +static const unsigned CONST_TBL_bitmask16rev_0[] = { + 0xffff & 0xffff, + 0xfffe & 0xffff, + 0xfffc & 0xffff, + 0xfff8 & 0xffff, + 0xfff0 & 0xffff, + 0xffe0 & 0xffff, + 0xffc0 & 0xffff, + 0xff80 & 0xffff, + 0xff00 & 0xffff, + 0xfe00 & 0xffff, + 0xfc00 & 0xffff, + 0xf800 & 0xffff, + 0xf000 & 0xffff, + 0xe000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 +}; + +/* constant table bitmask16sbe */ +static const unsigned CONST_TBL_bitmask16sbe_0[] = { + 0xfffe & 0xffff, + 0xfffc & 0xffff, + 0xfff8 & 0xffff, + 0xfff0 & 0xffff, + 0xffe0 & 0xffff, + 0xffc0 & 0xffff, + 0xff80 & 0xffff, + 0xff00 & 0xffff, + 0xfe00 & 0xffff, + 0xfc00 & 0xffff, + 0xf800 & 0xffff, + 0xf000 & 0xffff, + 0xe000 & 0xffff, + 0xc000 & 0xffff, + 0x8000 & 0xffff, + 0 & 0xffff, + 0 +}; + +/* constant table bitmask16rxp */ +static const unsigned CONST_TBL_bitmask16rxp_0[] = { + 0 & 0xffff, + 0x8000 & 0xffff, + 0xc000 & 0xffff, + 0xe000 & 0xffff, + 0xf000 & 0xffff, + 0xf800 & 0xffff, + 0xfc00 & 0xffff, + 0xfe00 & 0xffff, + 0xff00 & 0xffff, + 0xff80 & 0xffff, + 0xffc0 & 0xffff, + 0xffe0 & 0xffff, + 0xfff0 & 0xffff, + 0xfff8 & 0xffff, + 0xfffc & 0xffff, + 0xfffe & 0xffff, + 0 +}; + + +/* Instruction operands. */ + +static int +OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) +{ + unsigned soffsetx4_out_0; + unsigned soffsetx4_in_0; + soffsetx4_in_0 = *valp & 0x3ffff; + soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); + *valp = soffsetx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) +{ + unsigned soffsetx4_in_0; + unsigned soffsetx4_out_0; + soffsetx4_out_0 = *valp; + soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; + *valp = soffsetx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_immr_decode (uint32 *valp) +{ + unsigned immr_out_0; + unsigned immr_in_0; + immr_in_0 = *valp & 0xf; + immr_out_0 = immr_in_0; + *valp = immr_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immr_encode (uint32 *valp) +{ + unsigned immr_in_0; + unsigned immr_out_0; + immr_out_0 = *valp; + immr_in_0 = (immr_out_0 & 0xf); + *valp = immr_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) +{ + unsigned uimm12x8_out_0; + unsigned uimm12x8_in_0; + uimm12x8_in_0 = *valp & 0xfff; + uimm12x8_out_0 = uimm12x8_in_0 << 3; + *valp = uimm12x8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) +{ + unsigned uimm12x8_in_0; + unsigned uimm12x8_out_0; + uimm12x8_out_0 = *valp; + uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); + *valp = uimm12x8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_decode (uint32 *valp) +{ + unsigned simm4_out_0; + unsigned simm4_in_0; + simm4_in_0 = *valp & 0xf; + simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; + *valp = simm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_encode (uint32 *valp) +{ + unsigned simm4_in_0; + unsigned simm4_out_0; + simm4_out_0 = *valp; + simm4_in_0 = (simm4_out_0 & 0xf); + *valp = simm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_0_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_4_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_8_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_8_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_12_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_12_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_AR_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_entry_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 64); + return error; +} + +static int +OperandSem_opnd_sem_immrx4_decode (uint32 *valp) +{ + unsigned immrx4_out_0; + unsigned immrx4_in_0; + immrx4_in_0 = *valp & 0xf; + immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; + *valp = immrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immrx4_encode (uint32 *valp) +{ + unsigned immrx4_in_0; + unsigned immrx4_out_0; + immrx4_out_0 = *valp; + immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); + *valp = immrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) +{ + unsigned lsi4x4_out_0; + unsigned lsi4x4_in_0; + lsi4x4_in_0 = *valp & 0xf; + lsi4x4_out_0 = lsi4x4_in_0 << 2; + *valp = lsi4x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) +{ + unsigned lsi4x4_in_0; + unsigned lsi4x4_out_0; + lsi4x4_out_0 = *valp; + lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); + *valp = lsi4x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_decode (uint32 *valp) +{ + unsigned simm7_out_0; + unsigned simm7_in_0; + simm7_in_0 = *valp & 0x7f; + simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; + *valp = simm7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_encode (uint32 *valp) +{ + unsigned simm7_in_0; + unsigned simm7_out_0; + simm7_out_0 = *valp; + simm7_in_0 = (simm7_out_0 & 0x7f); + *valp = simm7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_decode (uint32 *valp) +{ + unsigned uimm6_out_0; + unsigned uimm6_in_0; + uimm6_in_0 = *valp & 0x3f; + uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); + *valp = uimm6_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_encode (uint32 *valp) +{ + unsigned uimm6_in_0; + unsigned uimm6_out_0; + uimm6_out_0 = *valp; + uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; + *valp = uimm6_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_decode (uint32 *valp) +{ + unsigned ai4const_out_0; + unsigned ai4const_in_0; + ai4const_in_0 = *valp & 0xf; + ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; + *valp = ai4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_encode (uint32 *valp) +{ + unsigned ai4const_in_0; + unsigned ai4const_out_0; + ai4const_out_0 = *valp; + switch (ai4const_out_0) + { + case 0xffffffff: ai4const_in_0 = 0; break; + case 0x1: ai4const_in_0 = 0x1; break; + case 0x2: ai4const_in_0 = 0x2; break; + case 0x3: ai4const_in_0 = 0x3; break; + case 0x4: ai4const_in_0 = 0x4; break; + case 0x5: ai4const_in_0 = 0x5; break; + case 0x6: ai4const_in_0 = 0x6; break; + case 0x7: ai4const_in_0 = 0x7; break; + case 0x8: ai4const_in_0 = 0x8; break; + case 0x9: ai4const_in_0 = 0x9; break; + case 0xa: ai4const_in_0 = 0xa; break; + case 0xb: ai4const_in_0 = 0xb; break; + case 0xc: ai4const_in_0 = 0xc; break; + case 0xd: ai4const_in_0 = 0xd; break; + case 0xe: ai4const_in_0 = 0xe; break; + default: ai4const_in_0 = 0xf; break; + } + *valp = ai4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_decode (uint32 *valp) +{ + unsigned b4const_out_0; + unsigned b4const_in_0; + b4const_in_0 = *valp & 0xf; + b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; + *valp = b4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_encode (uint32 *valp) +{ + unsigned b4const_in_0; + unsigned b4const_out_0; + b4const_out_0 = *valp; + switch (b4const_out_0) + { + case 0xffffffff: b4const_in_0 = 0; break; + case 0x1: b4const_in_0 = 0x1; break; + case 0x2: b4const_in_0 = 0x2; break; + case 0x3: b4const_in_0 = 0x3; break; + case 0x4: b4const_in_0 = 0x4; break; + case 0x5: b4const_in_0 = 0x5; break; + case 0x6: b4const_in_0 = 0x6; break; + case 0x7: b4const_in_0 = 0x7; break; + case 0x8: b4const_in_0 = 0x8; break; + case 0xa: b4const_in_0 = 0x9; break; + case 0xc: b4const_in_0 = 0xa; break; + case 0x10: b4const_in_0 = 0xb; break; + case 0x20: b4const_in_0 = 0xc; break; + case 0x40: b4const_in_0 = 0xd; break; + case 0x80: b4const_in_0 = 0xe; break; + default: b4const_in_0 = 0xf; break; + } + *valp = b4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_decode (uint32 *valp) +{ + unsigned b4constu_out_0; + unsigned b4constu_in_0; + b4constu_in_0 = *valp & 0xf; + b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; + *valp = b4constu_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_encode (uint32 *valp) +{ + unsigned b4constu_in_0; + unsigned b4constu_out_0; + b4constu_out_0 = *valp; + switch (b4constu_out_0) + { + case 0x8000: b4constu_in_0 = 0; break; + case 0x10000: b4constu_in_0 = 0x1; break; + case 0x2: b4constu_in_0 = 0x2; break; + case 0x3: b4constu_in_0 = 0x3; break; + case 0x4: b4constu_in_0 = 0x4; break; + case 0x5: b4constu_in_0 = 0x5; break; + case 0x6: b4constu_in_0 = 0x6; break; + case 0x7: b4constu_in_0 = 0x7; break; + case 0x8: b4constu_in_0 = 0x8; break; + case 0xa: b4constu_in_0 = 0x9; break; + case 0xc: b4constu_in_0 = 0xa; break; + case 0x10: b4constu_in_0 = 0xb; break; + case 0x20: b4constu_in_0 = 0xc; break; + case 0x40: b4constu_in_0 = 0xd; break; + case 0x80: b4constu_in_0 = 0xe; break; + default: b4constu_in_0 = 0xf; break; + } + *valp = b4constu_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_decode (uint32 *valp) +{ + unsigned immt_out_0; + unsigned immt_in_0; + immt_in_0 = *valp & 0xf; + immt_out_0 = immt_in_0; + *valp = immt_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_encode (uint32 *valp) +{ + unsigned immt_in_0; + unsigned immt_out_0; + immt_out_0 = *valp; + immt_in_0 = immt_out_0 & 0xf; + *valp = immt_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimms8_decode (uint32 *valp) +{ + unsigned uimms8_out_0; + unsigned uimms8_in_0; + uimms8_in_0 = *valp & 0x7; + uimms8_out_0 = uimms8_in_0; + *valp = uimms8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimms8_encode (uint32 *valp) +{ + unsigned uimms8_in_0; + unsigned uimms8_out_0; + uimms8_out_0 = *valp; + uimms8_in_0 = uimms8_out_0 & 0x7; + *valp = uimms8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_decode (uint32 *valp) +{ + unsigned uimm8_out_0; + unsigned uimm8_in_0; + uimm8_in_0 = *valp & 0xff; + uimm8_out_0 = uimm8_in_0; + *valp = uimm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_encode (uint32 *valp) +{ + unsigned uimm8_in_0; + unsigned uimm8_out_0; + uimm8_out_0 = *valp; + uimm8_in_0 = (uimm8_out_0 & 0xff); + *valp = uimm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) +{ + unsigned uimm8x2_out_0; + unsigned uimm8x2_in_0; + uimm8x2_in_0 = *valp & 0xff; + uimm8x2_out_0 = uimm8x2_in_0 << 1; + *valp = uimm8x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) +{ + unsigned uimm8x2_in_0; + unsigned uimm8x2_out_0; + uimm8x2_out_0 = *valp; + uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); + *valp = uimm8x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) +{ + unsigned uimm8x4_out_0; + unsigned uimm8x4_in_0; + uimm8x4_in_0 = *valp & 0xff; + uimm8x4_out_0 = uimm8x4_in_0 << 2; + *valp = uimm8x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) +{ + unsigned uimm8x4_in_0; + unsigned uimm8x4_out_0; + uimm8x4_out_0 = *valp; + uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); + *valp = uimm8x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) +{ + unsigned uimm4x16_out_0; + unsigned uimm4x16_in_0; + uimm4x16_in_0 = *valp & 0xf; + uimm4x16_out_0 = ((0 << 4) | uimm4x16_in_0) << 4; + *valp = uimm4x16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) +{ + unsigned uimm4x16_in_0; + unsigned uimm4x16_out_0; + uimm4x16_out_0 = *valp; + uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); + *valp = uimm4x16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp) +{ + unsigned uimmrx4_out_0; + unsigned uimmrx4_in_0; + uimmrx4_in_0 = *valp & 0xf; + uimmrx4_out_0 = ((0 << 4) | uimmrx4_in_0) << 2; + *valp = uimmrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp) +{ + unsigned uimmrx4_in_0; + unsigned uimmrx4_out_0; + uimmrx4_out_0 = *valp; + uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf); + *valp = uimmrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_decode (uint32 *valp) +{ + unsigned simm8_out_0; + unsigned simm8_in_0; + simm8_in_0 = *valp & 0xff; + simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; + *valp = simm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_encode (uint32 *valp) +{ + unsigned simm8_in_0; + unsigned simm8_out_0; + simm8_out_0 = *valp; + simm8_in_0 = (simm8_out_0 & 0xff); + *valp = simm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) +{ + unsigned simm8x256_out_0; + unsigned simm8x256_in_0; + simm8x256_in_0 = *valp & 0xff; + simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; + *valp = simm8x256_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) +{ + unsigned simm8x256_in_0; + unsigned simm8x256_out_0; + simm8x256_out_0 = *valp; + simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); + *valp = simm8x256_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_decode (uint32 *valp) +{ + unsigned simm12b_out_0; + unsigned simm12b_in_0; + simm12b_in_0 = *valp & 0xfff; + simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; + *valp = simm12b_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_encode (uint32 *valp) +{ + unsigned simm12b_in_0; + unsigned simm12b_out_0; + simm12b_out_0 = *valp; + simm12b_in_0 = (simm12b_out_0 & 0xfff); + *valp = simm12b_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_decode (uint32 *valp) +{ + unsigned msalp32_out_0; + unsigned msalp32_in_0; + msalp32_in_0 = *valp & 0x1f; + msalp32_out_0 = 0x20 - msalp32_in_0; + *valp = msalp32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_encode (uint32 *valp) +{ + unsigned msalp32_in_0; + unsigned msalp32_out_0; + msalp32_out_0 = *valp; + msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; + *valp = msalp32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_out_0; + unsigned op2p1_in_0; + op2p1_in_0 = *valp & 0xf; + op2p1_out_0 = op2p1_in_0 + 0x1; + *valp = op2p1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_encode (uint32 *valp) +{ + unsigned op2p1_in_0; + unsigned op2p1_out_0; + op2p1_out_0 = *valp; + op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; + *valp = op2p1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_decode (uint32 *valp) +{ + unsigned label8_out_0; + unsigned label8_in_0; + label8_in_0 = *valp & 0xff; + label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); + *valp = label8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_encode (uint32 *valp) +{ + unsigned label8_in_0; + unsigned label8_out_0; + label8_out_0 = *valp; + label8_in_0 = (label8_out_0 - 0x4) & 0xff; + *valp = label8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_decode (uint32 *valp) +{ + unsigned ulabel8_out_0; + unsigned ulabel8_in_0; + ulabel8_in_0 = *valp & 0xff; + ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0); + *valp = ulabel8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_encode (uint32 *valp) +{ + unsigned ulabel8_in_0; + unsigned ulabel8_out_0; + ulabel8_out_0 = *valp; + ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff; + *valp = ulabel8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_decode (uint32 *valp) +{ + unsigned label12_out_0; + unsigned label12_in_0; + label12_in_0 = *valp & 0xfff; + label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); + *valp = label12_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_encode (uint32 *valp) +{ + unsigned label12_in_0; + unsigned label12_out_0; + label12_out_0 = *valp; + label12_in_0 = (label12_out_0 - 0x4) & 0xfff; + *valp = label12_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_decode (uint32 *valp) +{ + unsigned soffset_out_0; + unsigned soffset_in_0; + soffset_in_0 = *valp & 0x3ffff; + soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); + *valp = soffset_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_encode (uint32 *valp) +{ + unsigned soffset_in_0; + unsigned soffset_out_0; + soffset_out_0 = *valp; + soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; + *valp = soffset_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) +{ + unsigned uimm16x4_out_0; + unsigned uimm16x4_in_0; + uimm16x4_in_0 = *valp & 0xffff; + uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; + *valp = uimm16x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) +{ + unsigned uimm16x4_in_0; + unsigned uimm16x4_out_0; + uimm16x4_out_0 = *valp; + uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; + *valp = uimm16x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_imms_decode (uint32 *valp) +{ + unsigned imms_out_0; + unsigned imms_in_0; + imms_in_0 = *valp & 0xf; + imms_out_0 = imms_in_0; + *valp = imms_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_imms_encode (uint32 *valp) +{ + unsigned imms_in_0; + unsigned imms_out_0; + imms_out_0 = *valp; + imms_in_0 = imms_out_0 & 0xf; + *valp = imms_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_BR_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16); + return error; +} + +static int +OperandSem_opnd_sem_BR2_decode (uint32 *valp) +{ + *valp = *valp << 1; + return 0; +} + +static int +OperandSem_opnd_sem_BR2_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 1) != 0); + *valp = *valp >> 1; + return error; +} + +static int +OperandSem_opnd_sem_BR4_decode (uint32 *valp) +{ + *valp = *valp << 2; + return 0; +} + +static int +OperandSem_opnd_sem_BR4_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 3) != 0); + *valp = *valp >> 2; + return error; +} + +static int +OperandSem_opnd_sem_BR8_decode (uint32 *valp) +{ + *valp = *valp << 3; + return 0; +} + +static int +OperandSem_opnd_sem_BR8_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 7) != 0); + *valp = *valp >> 3; + return error; +} + +static int +OperandSem_opnd_sem_BR16_decode (uint32 *valp) +{ + *valp = *valp << 4; + return 0; +} + +static int +OperandSem_opnd_sem_BR16_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 15) != 0); + *valp = *valp >> 4; + return error; +} + +static int +OperandSem_opnd_sem_tp7_decode (uint32 *valp) +{ + unsigned tp7_out_0; + unsigned tp7_in_0; + tp7_in_0 = *valp & 0xf; + tp7_out_0 = tp7_in_0 + 0x7; + *valp = tp7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_tp7_encode (uint32 *valp) +{ + unsigned tp7_in_0; + unsigned tp7_out_0; + tp7_out_0 = *valp; + tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; + *valp = tp7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) +{ + unsigned xt_wbr15_label_out_0; + unsigned xt_wbr15_label_in_0; + xt_wbr15_label_in_0 = *valp & 0x7fff; + xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); + *valp = xt_wbr15_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) +{ + unsigned xt_wbr15_label_in_0; + unsigned xt_wbr15_label_out_0; + xt_wbr15_label_out_0 = *valp; + xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; + *valp = xt_wbr15_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wloop_label_decode (uint32 *valp) +{ + unsigned xt_wloop_label_out_0; + unsigned xt_wloop_label_in_0; + xt_wloop_label_in_0 = *valp & 0x7fff; + xt_wloop_label_out_0 = 0x4 + (((0) << 15) | xt_wloop_label_in_0); + *valp = xt_wloop_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wloop_label_encode (uint32 *valp) +{ + unsigned xt_wloop_label_in_0; + unsigned xt_wloop_label_out_0; + xt_wloop_label_out_0 = *valp; + xt_wloop_label_in_0 = (xt_wloop_label_out_0 - 0x4) & 0x7fff; + *valp = xt_wloop_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_uimm2x2_decode (uint32 *valp) +{ + unsigned ae_uimm2x2_out_0; + unsigned ae_uimm2x2_in_0; + ae_uimm2x2_in_0 = *valp & 0x1; + ae_uimm2x2_out_0 = (0 << 2) | (ae_uimm2x2_in_0 << 1) | 0; + *valp = ae_uimm2x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_uimm2x2_encode (uint32 *valp) +{ + unsigned ae_uimm2x2_in_0; + unsigned ae_uimm2x2_out_0; + ae_uimm2x2_out_0 = *valp; + ae_uimm2x2_in_0 = (((ae_uimm2x2_out_0 >> 1) & 1)) & 0x1; + *valp = ae_uimm2x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AE_DR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_DR_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64_out_0; + unsigned opnd_ae_sem_loads_stores_i64_in_0; + opnd_ae_sem_loads_stores_i64_in_0 = *valp & 0xf; + opnd_ae_sem_loads_stores_i64_out_0 = (((int) opnd_ae_sem_loads_stores_i64_in_0 << 28) >> 28) << 3; + *valp = opnd_ae_sem_loads_stores_i64_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64_in_0; + unsigned opnd_ae_sem_loads_stores_i64_out_0; + opnd_ae_sem_loads_stores_i64_out_0 = *valp; + opnd_ae_sem_loads_stores_i64_in_0 = ((opnd_ae_sem_loads_stores_i64_out_0 >> 3) & 0xf); + *valp = opnd_ae_sem_loads_stores_i64_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_sb_loads_stores_iba_out_0; + unsigned opnd_ae_sem_sb_loads_stores_iba_in_0; + opnd_ae_sem_sb_loads_stores_iba_in_0 = *valp & 0xf; + opnd_ae_sem_sb_loads_stores_iba_out_0 = CONST_TBL_ae_ohba_0[opnd_ae_sem_sb_loads_stores_iba_in_0 & 0xf]; + *valp = opnd_ae_sem_sb_loads_stores_iba_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_sb_loads_stores_iba_in_0; + unsigned opnd_ae_sem_sb_loads_stores_iba_out_0; + opnd_ae_sem_sb_loads_stores_iba_out_0 = *valp; + switch (opnd_ae_sem_sb_loads_stores_iba_out_0) + { + case 0x1: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0; break; + case 0x2: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x1; break; + case 0x3: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x2; break; + case 0x4: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x3; break; + case 0x5: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x4; break; + case 0x6: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x5; break; + case 0x7: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x6; break; + case 0x8: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x7; break; + case 0x9: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x8; break; + case 0xa: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0x9; break; + case 0xb: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xa; break; + case 0xc: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xb; break; + case 0xd: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xc; break; + case 0xe: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xd; break; + case 0xf: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xe; break; + default: opnd_ae_sem_sb_loads_stores_iba_in_0 = 0xf; break; + } + *valp = opnd_ae_sem_sb_loads_stores_iba_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_imm2_out_0; + unsigned opnd_ae_sem_loads_stores_imm2_in_0; + opnd_ae_sem_loads_stores_imm2_in_0 = *valp & 0x3; + opnd_ae_sem_loads_stores_imm2_out_0 = (0 << 2) | opnd_ae_sem_loads_stores_imm2_in_0; + *valp = opnd_ae_sem_loads_stores_imm2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_imm2_in_0; + unsigned opnd_ae_sem_loads_stores_imm2_out_0; + opnd_ae_sem_loads_stores_imm2_out_0 = *valp; + opnd_ae_sem_loads_stores_imm2_in_0 = (opnd_ae_sem_loads_stores_imm2_out_0 & 0x3); + *valp = opnd_ae_sem_loads_stores_imm2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_movi_imm_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_dr_to_dr_movi_imm_out_0; + unsigned opnd_ae_sem_dr_to_dr_movi_imm_in_0; + opnd_ae_sem_dr_to_dr_movi_imm_in_0 = *valp & 0x3f; + opnd_ae_sem_dr_to_dr_movi_imm_out_0 = (((-(( ( ((((opnd_ae_sem_dr_to_dr_movi_imm_in_0 >> 4) & 0x3)) | 0xfffffffc)) == 0xffffffff))) & 0x3ffffff) << 6) | opnd_ae_sem_dr_to_dr_movi_imm_in_0; + *valp = opnd_ae_sem_dr_to_dr_movi_imm_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_movi_imm_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_dr_to_dr_movi_imm_in_0; + unsigned opnd_ae_sem_dr_to_dr_movi_imm_out_0; + opnd_ae_sem_dr_to_dr_movi_imm_out_0 = *valp; + opnd_ae_sem_dr_to_dr_movi_imm_in_0 = (opnd_ae_sem_dr_to_dr_movi_imm_out_0 & 0x3f); + *valp = opnd_ae_sem_dr_to_dr_movi_imm_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_spfma_i_imm3_out_0; + unsigned opnd_ae_sem_spfma_i_imm3_in_0; + opnd_ae_sem_spfma_i_imm3_in_0 = *valp & 0x7; + opnd_ae_sem_spfma_i_imm3_out_0 = (0 << 3) | opnd_ae_sem_spfma_i_imm3_in_0; + *valp = opnd_ae_sem_spfma_i_imm3_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_spfma_i_imm3_in_0; + unsigned opnd_ae_sem_spfma_i_imm3_out_0; + opnd_ae_sem_spfma_i_imm3_out_0 = *valp; + opnd_ae_sem_spfma_i_imm3_in_0 = (opnd_ae_sem_spfma_i_imm3_out_0 & 0x7); + *valp = opnd_ae_sem_spfma_i_imm3_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AE_VALIGN_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_VALIGN_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i32_out_0; + unsigned opnd_ae_sem_loads_stores_i32_in_0; + opnd_ae_sem_loads_stores_i32_in_0 = *valp & 0xf; + opnd_ae_sem_loads_stores_i32_out_0 = (((int) opnd_ae_sem_loads_stores_i32_in_0 << 28) >> 28) << 2; + *valp = opnd_ae_sem_loads_stores_i32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i32_in_0; + unsigned opnd_ae_sem_loads_stores_i32_out_0; + opnd_ae_sem_loads_stores_i32_out_0 = *valp; + opnd_ae_sem_loads_stores_i32_in_0 = ((opnd_ae_sem_loads_stores_i32_out_0 >> 2) & 0xf); + *valp = opnd_ae_sem_loads_stores_i32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32pos_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i32pos_out_0; + unsigned opnd_ae_sem_loads_stores_i32pos_in_0; + opnd_ae_sem_loads_stores_i32pos_in_0 = *valp & 0x7; + opnd_ae_sem_loads_stores_i32pos_out_0 = ((0 << 3) | opnd_ae_sem_loads_stores_i32pos_in_0) << 2; + *valp = opnd_ae_sem_loads_stores_i32pos_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32pos_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i32pos_in_0; + unsigned opnd_ae_sem_loads_stores_i32pos_out_0; + opnd_ae_sem_loads_stores_i32pos_out_0 = *valp; + opnd_ae_sem_loads_stores_i32pos_in_0 = ((opnd_ae_sem_loads_stores_i32pos_out_0 >> 2) & 0x7); + *valp = opnd_ae_sem_loads_stores_i32pos_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i16_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i16_out_0; + unsigned opnd_ae_sem_loads_stores_i16_in_0; + opnd_ae_sem_loads_stores_i16_in_0 = *valp & 0xf; + opnd_ae_sem_loads_stores_i16_out_0 = (((int) opnd_ae_sem_loads_stores_i16_in_0 << 28) >> 28) << 1; + *valp = opnd_ae_sem_loads_stores_i16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i16_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i16_in_0; + unsigned opnd_ae_sem_loads_stores_i16_out_0; + opnd_ae_sem_loads_stores_i16_out_0 = *valp; + opnd_ae_sem_loads_stores_i16_in_0 = ((opnd_ae_sem_loads_stores_i16_out_0 >> 1) & 0xf); + *valp = opnd_ae_sem_loads_stores_i16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i8_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i8_out_0; + unsigned opnd_ae_sem_loads_stores_i8_in_0; + opnd_ae_sem_loads_stores_i8_in_0 = *valp & 0xf; + opnd_ae_sem_loads_stores_i8_out_0 = ((int) opnd_ae_sem_loads_stores_i8_in_0 << 28) >> 28; + *valp = opnd_ae_sem_loads_stores_i8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i8_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i8_in_0; + unsigned opnd_ae_sem_loads_stores_i8_out_0; + opnd_ae_sem_loads_stores_i8_out_0 = *valp; + opnd_ae_sem_loads_stores_i8_in_0 = (opnd_ae_sem_loads_stores_i8_out_0 & 0xf); + *valp = opnd_ae_sem_loads_stores_i8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64pos_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64pos_out_0; + unsigned opnd_ae_sem_loads_stores_i64pos_in_0; + opnd_ae_sem_loads_stores_i64pos_in_0 = *valp & 0x7; + opnd_ae_sem_loads_stores_i64pos_out_0 = ((0 << 3) | opnd_ae_sem_loads_stores_i64pos_in_0) << 3; + *valp = opnd_ae_sem_loads_stores_i64pos_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64pos_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64pos_in_0; + unsigned opnd_ae_sem_loads_stores_i64pos_out_0; + opnd_ae_sem_loads_stores_i64pos_out_0 = *valp; + opnd_ae_sem_loads_stores_i64pos_in_0 = ((opnd_ae_sem_loads_stores_i64pos_out_0 >> 3) & 0x7); + *valp = opnd_ae_sem_loads_stores_i64pos_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64neg_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64neg_out_0; + unsigned opnd_ae_sem_loads_stores_i64neg_in_0; + opnd_ae_sem_loads_stores_i64neg_in_0 = *valp & 0x3; + opnd_ae_sem_loads_stores_i64neg_out_0 = CONST_TBL_ae_immls64neg_0[opnd_ae_sem_loads_stores_i64neg_in_0 & 0x3]; + *valp = opnd_ae_sem_loads_stores_i64neg_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64neg_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64neg_in_0; + unsigned opnd_ae_sem_loads_stores_i64neg_out_0; + opnd_ae_sem_loads_stores_i64neg_out_0 = *valp; + opnd_ae_sem_loads_stores_i64neg_in_0 = (((opnd_ae_sem_loads_stores_i64neg_out_0 == (CONST_TBL_ae_immls64neg_0[0]))) ? 0 : (((opnd_ae_sem_loads_stores_i64neg_out_0 == (CONST_TBL_ae_immls64neg_0[1]))) ? 0x1 : (((opnd_ae_sem_loads_stores_i64neg_out_0 == (CONST_TBL_ae_immls64neg_0[2]))) ? 0x2 : 0x3))) & 0x3; + *valp = opnd_ae_sem_loads_stores_i64neg_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64half_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64half_out_0; + unsigned opnd_ae_sem_loads_stores_i64half_in_0; + opnd_ae_sem_loads_stores_i64half_in_0 = *valp & 0x7; + opnd_ae_sem_loads_stores_i64half_out_0 = (((int) opnd_ae_sem_loads_stores_i64half_in_0 << 29) >> 29) << 3; + *valp = opnd_ae_sem_loads_stores_i64half_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64half_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64half_in_0; + unsigned opnd_ae_sem_loads_stores_i64half_out_0; + opnd_ae_sem_loads_stores_i64half_out_0 = *valp; + opnd_ae_sem_loads_stores_i64half_in_0 = ((opnd_ae_sem_loads_stores_i64half_out_0 >> 3) & 0x7); + *valp = opnd_ae_sem_loads_stores_i64half_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_hpcnv_i_imm4_out_0; + unsigned opnd_ae_sem_hpcnv_i_imm4_in_0; + opnd_ae_sem_hpcnv_i_imm4_in_0 = *valp & 0xf; + opnd_ae_sem_hpcnv_i_imm4_out_0 = (0 << 4) | opnd_ae_sem_hpcnv_i_imm4_in_0; + *valp = opnd_ae_sem_hpcnv_i_imm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_hpcnv_i_imm4_in_0; + unsigned opnd_ae_sem_hpcnv_i_imm4_out_0; + opnd_ae_sem_hpcnv_i_imm4_out_0 = *valp; + opnd_ae_sem_hpcnv_i_imm4_in_0 = (opnd_ae_sem_hpcnv_i_imm4_out_0 & 0xf); + *valp = opnd_ae_sem_hpcnv_i_imm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_sp32cvt_i_imm5_out_0; + unsigned opnd_ae_sem_sp32cvt_i_imm5_in_0; + opnd_ae_sem_sp32cvt_i_imm5_in_0 = *valp & 0x1f; + opnd_ae_sem_sp32cvt_i_imm5_out_0 = (0 << 5) | opnd_ae_sem_sp32cvt_i_imm5_in_0; + *valp = opnd_ae_sem_sp32cvt_i_imm5_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_sp32cvt_i_imm5_in_0; + unsigned opnd_ae_sem_sp32cvt_i_imm5_out_0; + opnd_ae_sem_sp32cvt_i_imm5_out_0 = *valp; + opnd_ae_sem_sp32cvt_i_imm5_in_0 = (opnd_ae_sem_sp32cvt_i_imm5_out_0 & 0x1f); + *valp = opnd_ae_sem_sp32cvt_i_imm5_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_shift_i64_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_shift_i64_out_0; + unsigned opnd_ae_sem_shift_i64_in_0; + opnd_ae_sem_shift_i64_in_0 = *valp & 0x3f; + opnd_ae_sem_shift_i64_out_0 = (0 << 6) | opnd_ae_sem_shift_i64_in_0; + *valp = opnd_ae_sem_shift_i64_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_shift_i64_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_shift_i64_in_0; + unsigned opnd_ae_sem_shift_i64_out_0; + opnd_ae_sem_shift_i64_out_0 = *valp; + opnd_ae_sem_shift_i64_in_0 = (opnd_ae_sem_shift_i64_out_0 & 0x3f); + *valp = opnd_ae_sem_shift_i64_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i128_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i128_out_0; + unsigned opnd_ae_sem_loads_stores_i128_in_0; + opnd_ae_sem_loads_stores_i128_in_0 = *valp & 0xf; + opnd_ae_sem_loads_stores_i128_out_0 = (((int) opnd_ae_sem_loads_stores_i128_in_0 << 28) >> 28) << 4; + *valp = opnd_ae_sem_loads_stores_i128_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i128_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i128_in_0; + unsigned opnd_ae_sem_loads_stores_i128_out_0; + opnd_ae_sem_loads_stores_i128_out_0 = *valp; + opnd_ae_sem_loads_stores_i128_in_0 = ((opnd_ae_sem_loads_stores_i128_out_0 >> 4) & 0xf); + *valp = opnd_ae_sem_loads_stores_i128_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64x2_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64x2_out_0; + unsigned opnd_ae_sem_loads_stores_i64x2_in_0; + opnd_ae_sem_loads_stores_i64x2_in_0 = *valp & 0x7; + opnd_ae_sem_loads_stores_i64x2_out_0 = ((0 << 3) | opnd_ae_sem_loads_stores_i64x2_in_0) << 3; + *valp = opnd_ae_sem_loads_stores_i64x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64x2_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_loads_stores_i64x2_in_0; + unsigned opnd_ae_sem_loads_stores_i64x2_out_0; + opnd_ae_sem_loads_stores_i64x2_out_0 = *valp; + opnd_ae_sem_loads_stores_i64x2_in_0 = (((opnd_ae_sem_loads_stores_i64x2_out_0 >> 3) & 0xf)) & 0x7; + *valp = opnd_ae_sem_loads_stores_i64x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AE_EP_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_EP_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_shift_i8_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_shift_i8_out_0; + unsigned opnd_ae_sem_shift_i8_in_0; + opnd_ae_sem_shift_i8_in_0 = *valp & 0x7; + opnd_ae_sem_shift_i8_out_0 = CONST_TBL_ae_slai72table_0[opnd_ae_sem_shift_i8_in_0 & 0x7]; + *valp = opnd_ae_sem_shift_i8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_shift_i8_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_shift_i8_in_0; + unsigned opnd_ae_sem_shift_i8_out_0; + opnd_ae_sem_shift_i8_out_0 = *valp; + switch (opnd_ae_sem_shift_i8_out_0) + { + case 0x1: opnd_ae_sem_shift_i8_in_0 = 0; break; + case 0x2: opnd_ae_sem_shift_i8_in_0 = 0x1; break; + case 0x3: opnd_ae_sem_shift_i8_in_0 = 0x2; break; + case 0x4: opnd_ae_sem_shift_i8_in_0 = 0x3; break; + case 0x5: opnd_ae_sem_shift_i8_in_0 = 0x4; break; + case 0x6: opnd_ae_sem_shift_i8_in_0 = 0x5; break; + case 0x7: opnd_ae_sem_shift_i8_in_0 = 0x6; break; + default: opnd_ae_sem_shift_i8_in_0 = 0x7; break; + } + *valp = opnd_ae_sem_shift_i8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_imm_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_dr_to_dr_imm_out_0; + unsigned opnd_ae_sem_dr_to_dr_imm_in_0; + opnd_ae_sem_dr_to_dr_imm_in_0 = *valp & 0xf; + opnd_ae_sem_dr_to_dr_imm_out_0 = CONST_TBL_ae_opnd_tp7_0[opnd_ae_sem_dr_to_dr_imm_in_0 & 0xf]; + *valp = opnd_ae_sem_dr_to_dr_imm_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_imm_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_dr_to_dr_imm_in_0; + unsigned opnd_ae_sem_dr_to_dr_imm_out_0; + opnd_ae_sem_dr_to_dr_imm_out_0 = *valp; + switch (opnd_ae_sem_dr_to_dr_imm_out_0) + { + case 0x7: opnd_ae_sem_dr_to_dr_imm_in_0 = 0; break; + case 0x8: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x1; break; + case 0x9: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x2; break; + case 0xa: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x3; break; + case 0xb: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x4; break; + case 0xc: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x5; break; + case 0xd: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x6; break; + case 0xe: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x7; break; + case 0xf: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x8; break; + case 0x10: opnd_ae_sem_dr_to_dr_imm_in_0 = 0x9; break; + case 0x11: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xa; break; + case 0x12: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xb; break; + case 0x13: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xc; break; + case 0x14: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xd; break; + case 0x15: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xe; break; + default: opnd_ae_sem_dr_to_dr_imm_in_0 = 0xf; break; + } + *valp = opnd_ae_sem_dr_to_dr_imm_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba2_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_sb_loads_stores_iba2_out_0; + unsigned opnd_ae_sem_sb_loads_stores_iba2_in_0; + opnd_ae_sem_sb_loads_stores_iba2_in_0 = *valp & 0xf; + opnd_ae_sem_sb_loads_stores_iba2_out_0 = CONST_TBL_ae_ohba2_0[opnd_ae_sem_sb_loads_stores_iba2_in_0 & 0xf]; + *valp = opnd_ae_sem_sb_loads_stores_iba2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba2_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_sb_loads_stores_iba2_in_0; + unsigned opnd_ae_sem_sb_loads_stores_iba2_out_0; + opnd_ae_sem_sb_loads_stores_iba2_out_0 = *valp; + switch (opnd_ae_sem_sb_loads_stores_iba2_out_0) + { + case 0x1: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0; break; + case 0x2: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x1; break; + case 0x3: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x2; break; + case 0x4: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x3; break; + case 0x5: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x4; break; + case 0x6: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x5; break; + case 0x7: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x6; break; + case 0x8: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x7; break; + case 0x9: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x8; break; + case 0xa: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0x9; break; + case 0xb: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xa; break; + case 0xc: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xb; break; + case 0xd: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xc; break; + case 0xe: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xd; break; + case 0xf: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xe; break; + default: opnd_ae_sem_sb_loads_stores_iba2_in_0 = 0xf; break; + } + *valp = opnd_ae_sem_sb_loads_stores_iba2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm1_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_spfma_i_imm1_out_0; + unsigned opnd_ae_sem_spfma_i_imm1_in_0; + opnd_ae_sem_spfma_i_imm1_in_0 = *valp & 0x1; + opnd_ae_sem_spfma_i_imm1_out_0 = (0 << 1) | opnd_ae_sem_spfma_i_imm1_in_0; + *valp = opnd_ae_sem_spfma_i_imm1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm1_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_spfma_i_imm1_in_0; + unsigned opnd_ae_sem_spfma_i_imm1_out_0; + opnd_ae_sem_spfma_i_imm1_out_0 = *valp; + opnd_ae_sem_spfma_i_imm1_in_0 = (((opnd_ae_sem_spfma_i_imm1_out_0 >> 0) & 1)) & 0x1; + *valp = opnd_ae_sem_spfma_i_imm1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_decode (uint32 *valp) +{ + unsigned bbi_out_0; + unsigned bbi_in_0; + bbi_in_0 = *valp & 0x1f; + bbi_out_0 = (0 << 5) | bbi_in_0; + *valp = bbi_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_encode (uint32 *valp) +{ + unsigned bbi_in_0; + unsigned bbi_out_0; + bbi_out_0 = *valp; + bbi_in_0 = (bbi_out_0 & 0x1f); + *valp = bbi_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_decode (uint32 *valp) +{ + unsigned s_out_0; + unsigned s_in_0; + s_in_0 = *valp & 0xf; + s_out_0 = (0 << 4) | s_in_0; + *valp = s_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_encode (uint32 *valp) +{ + unsigned s_in_0; + unsigned s_out_0; + s_out_0 = *valp; + s_in_0 = (s_out_0 & 0xf); + *valp = s_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bitindex_decode (uint32 *valp) +{ + unsigned bitindex_out_0; + unsigned bitindex_in_0; + bitindex_in_0 = *valp & 0x1f; + bitindex_out_0 = (0 << 5) | bitindex_in_0; + *valp = bitindex_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bitindex_encode (uint32 *valp) +{ + unsigned bitindex_in_0; + unsigned bitindex_out_0; + bitindex_out_0 = *valp; + bitindex_in_0 = (bitindex_out_0 & 0x1f); + *valp = bitindex_in_0; + return 0; +} + +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +{ + *valp -= (pc & ~0x3); + return 0; +} + +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += (pc & ~0x3); + return 0; +} + +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ulabel8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label12_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +{ + *valp -= ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_xt_wloop_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wloop_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static xtensa_operand_internal operands[] = { + { "soffsetx4", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa, + -1, 0 }, + { "immr", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_immr_encode, OperandSem_opnd_sem_immr_decode, + 0, 0, + -1, 0 }, + { "uimm12x8", FIELD_imm12, -1, 0, + 0, + OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, + 0, 0, + -1, 0 }, + { "simm4", FIELD_mn, -1, 0, + 0, + OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, + 0, 0, + -1, 0 }, + { "arr", FIELD_r, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "ars", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "*ars_invisible", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "art", FIELD_t, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "ar0", FIELD__ar0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, + 0, 0, + 0, 63 }, + { "ar4", FIELD__ar4, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, + 0, 0, + 0, 63 }, + { "ar8", FIELD__ar8, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_8_encode, OperandSem_opnd_sem_AR_8_decode, + 0, 0, + 0, 63 }, + { "ar12", FIELD__ar12, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_12_encode, OperandSem_opnd_sem_AR_12_decode, + 0, 0, + 0, 63 }, + { "ars_entry", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_entry_encode, OperandSem_opnd_sem_AR_entry_decode, + 0, 0, + 0, 63 }, + { "immrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, + 0, 0, + -1, 0 }, + { "lsi4x4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, + 0, 0, + -1, 0 }, + { "simm7", FIELD_imm7, -1, 0, + 0, + OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, + 0, 0, + -1, 0 }, + { "uimm6", FIELD_imm6, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa, + -1, 0 }, + { "ai4const", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, + 0, 0, + -1, 0 }, + { "b4const", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, + 0, 0, + -1, 0 }, + { "b4constu", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, + 0, 0, + -1, 0 }, + { "immt", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, + 0, 0, + -1, 0 }, + { "uimms8", FIELD_imms8, -1, 0, + 0, + OperandSem_opnd_sem_uimms8_encode, OperandSem_opnd_sem_uimms8_decode, + 0, 0, + -1, 0 }, + { "uimm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, + 0, 0, + -1, 0 }, + { "uimm8x2", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, + 0, 0, + -1, 0 }, + { "uimm8x4", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, + 0, 0, + -1, 0 }, + { "uimm4x16", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, + 0, 0, + -1, 0 }, + { "uimmrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode, + 0, 0, + -1, 0 }, + { "simm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, + 0, 0, + -1, 0 }, + { "simm8x256", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, + 0, 0, + -1, 0 }, + { "simm12b", FIELD_imm12b, -1, 0, + 0, + OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, + 0, 0, + -1, 0 }, + { "msalp32", FIELD_sal, -1, 0, + 0, + OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, + 0, 0, + -1, 0 }, + { "op2p1", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, + 0, 0, + -1, 0 }, + { "label8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, + Operand_label8_ator, Operand_label8_rtoa, + -1, 0 }, + { "ulabel8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode, + Operand_ulabel8_ator, Operand_ulabel8_rtoa, + -1, 0 }, + { "label12", FIELD_imm12, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, + Operand_label12_ator, Operand_label12_rtoa, + -1, 0 }, + { "soffset", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa, + -1, 0 }, + { "uimm16x4", FIELD_imm16, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa, + -1, 0 }, + { "imms", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_imms_encode, OperandSem_opnd_sem_imms_decode, + 0, 0, + -1, 0 }, + { "imms1", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_imms_encode, OperandSem_opnd_sem_imms_decode, + 0, 0, + -1, 0 }, + { "bt", FIELD_t, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "bs", FIELD_s, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "br", FIELD_r, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "bt2", FIELD_t2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "bs2", FIELD_s2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "br2", FIELD_r2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "bt4", FIELD_t4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "bs4", FIELD_s4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "br4", FIELD_r4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "bt8", FIELD_t8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0, + 0, 15 }, + { "bs8", FIELD_s8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0, + 0, 15 }, + { "br8", FIELD_r8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0, + 0, 15 }, + { "bt16", FIELD__bt16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "bs16", FIELD__bs16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "br16", FIELD__br16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "brall", FIELD__brall, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "tp7", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, + 0, 0, + -1, 0 }, + { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa, + -1, 0 }, + { "xt_wloop_label", FIELD_xt_wloop_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wloop_label_encode, OperandSem_opnd_sem_xt_wloop_label_decode, + Operand_xt_wloop_label_ator, Operand_xt_wloop_label_rtoa, + -1, 0 }, + { "ae_uimm2x2", FIELD_ae_fld_Inst16b_12, -1, 0, + 0, + OperandSem_opnd_sem_ae_uimm2x2_encode, OperandSem_opnd_sem_ae_uimm2x2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_dr_v", FIELD_fld_ae_sem_dr_to_dr_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_arithmetic_v", FIELD_fld_ae_sem_arithmetic_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_arithmetic_v0", FIELD_fld_ae_sem_arithmetic_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_arithmetic_v1", FIELD_fld_ae_sem_arithmetic_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_a.0", FIELD_fld_ae_sem_loads_stores_a_0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_loads_stores_x", FIELD_fld_ae_sem_loads_stores_x, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_loads_stores_end", FIELD_fld_ae_sem_loads_stores_end, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_loads_stores_i64", FIELD_fld_ae_sem_loads_stores_i64, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_lb_ops_iba", FIELD_fld_ae_sem_lb_ops_iba, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_encode, OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_sb_loads_stores_iba", FIELD_fld_ae_sem_sb_loads_stores_iba, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_encode, OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_pks_d", FIELD_fld_ae_sem_pks_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_pks_pos", FIELD_fld_ae_sem_pks_pos, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_pks_s", FIELD_fld_ae_sem_pks_s, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_a", FIELD_fld_ae_sem_dr_to_ar_a, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_dr_to_ar_v0", FIELD_fld_ae_sem_dr_to_ar_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_v0", FIELD_fld_ae_sem_dr_to_dr_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_ab", FIELD_fld_ae_sem_dr_to_ar_ab, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_dr_to_ar_ai", FIELD_fld_ae_sem_dr_to_ar_ai, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_dr_to_ar_aoe", FIELD_fld_ae_sem_dr_to_ar_aoe, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_dr_to_dr_movi_imm", FIELD_fld_ae_sem_dr_to_dr_movi_imm, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_movi_imm_encode, OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_movi_imm_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_dr_ds", FIELD_fld_ae_sem_dr_to_dr_ds, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_v1", FIELD_fld_ae_sem_dr_to_dr_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_imm8", FIELD_fld_ae_sem_dr_to_ar_imm8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_encode, OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_a0", FIELD_fld_ae_sem_shift_a0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_shift_d", FIELD_fld_ae_sem_shift_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_shift_d0", FIELD_fld_ae_sem_shift_d0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_d", FIELD_fld_ae_sem_dr_to_ar_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_d0", FIELD_fld_ae_sem_dr_to_ar_d0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_ar_d1", FIELD_fld_ae_sem_dr_to_ar_d1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_imm2", FIELD_fld_ae_sem_dr_to_dr_imm2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_arithmetic_ds", FIELD_fld_ae_sem_arithmetic_ds, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_uu", FIELD_fld_ae_sem_loads_stores_uu, REGFILE_AE_VALIGN, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_VALIGN_encode, OperandSem_opnd_sem_AE_VALIGN_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_loads_stores_vu", FIELD_fld_ae_sem_loads_stores_vu, REGFILE_AE_VALIGN, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_VALIGN_encode, OperandSem_opnd_sem_AE_VALIGN_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_loads_stores_i32", FIELD_fld_ae_sem_loads_stores_i32, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_v", FIELD_fld_ae_sem_loads_stores_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_i32pos", FIELD_fld_ae_sem_loads_stores_i32pos, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32pos_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i32pos_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i16", FIELD_fld_ae_sem_loads_stores_i16, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i16_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i16_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i8", FIELD_fld_ae_sem_loads_stores_i8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i8_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i8_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i64pos", FIELD_fld_ae_sem_loads_stores_i64pos, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64pos_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64pos_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i64neg", FIELD_fld_ae_sem_loads_stores_i64neg, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64neg_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64neg_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i64half", FIELD_fld_ae_sem_loads_stores_i64half, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64half_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64half_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_su", FIELD_fld_ae_sem_loads_stores_su, REGFILE_AE_VALIGN, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_VALIGN_encode, OperandSem_opnd_sem_AE_VALIGN_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_loads_stores_v1", FIELD_fld_ae_sem_loads_stores_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_av", FIELD_fld_ae_sem_loads_stores_av, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_shift_i16", FIELD_fld_ae_sem_shift_i16, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_encode, OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_i32", FIELD_fld_ae_sem_shift_i32, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_encode, OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_d1", FIELD_fld_ae_sem_shift_d1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_shift_da", FIELD_fld_ae_sem_shift_da, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_shift_imm32", FIELD_fld_ae_sem_shift_imm32, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_encode, OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_a", FIELD_fld_ae_sem_shift_a, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_shift_sd", FIELD_fld_ae_sem_shift_sd, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_shift_i64", FIELD_fld_ae_sem_shift_i64, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_shift_i64_encode, OperandSem_opnd_sem_opnd_ae_sem_shift_i64_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_imm8", FIELD_fld_ae_sem_shift_imm8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_encode, OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_dr_immed", FIELD_fld_ae_sem_dr_to_dr_immed, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_encode, OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_arithmetic_art", FIELD_fld_ae_sem_arithmetic_art, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_arithmetic_va", FIELD_fld_ae_sem_arithmetic_va, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_arithmetic_vs", FIELD_fld_ae_sem_arithmetic_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_i128", FIELD_fld_ae_sem_loads_stores_i128, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i128_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i128_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i64x2", FIELD_fld_ae_sem_loads_stores_i64x2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64x2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_i64x2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_av1", FIELD_fld_ae_sem_loads_stores_av1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_loads_stores_imm2", FIELD_fld_ae_sem_loads_stores_imm2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_i3", FIELD_fld_ae_sem_loads_stores_i3, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_encode, OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_rng_v0", FIELD_fld_ae_sem_rng_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_rng_v1", FIELD_fld_ae_sem_rng_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_reduction_sort_v", FIELD_fld_ae_sem_reduction_sort_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_reduction_sort_v0", FIELD_fld_ae_sem_reduction_sort_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_reduction_sort_ds", FIELD_fld_ae_sem_reduction_sort_ds, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_multiply_d0", FIELD_fld_ae_sem_multiply_d0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_multiply_d2", FIELD_fld_ae_sem_multiply_d2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_multiply_q0", FIELD_fld_ae_sem_multiply_q0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_multiply_q1", FIELD_fld_ae_sem_multiply_q1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_immed.N", FIELD_fld_ae_sem_dr_to_dr_immed_N, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_ar_ei", FIELD_fld_ae_sem_dr_to_ar_ei, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_dr_to_ar_eo", FIELD_fld_ae_sem_dr_to_ar_eo, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_multiply_acc_ep", FIELD_fld_ae_sem_multiply_acc_ep, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_arithmetic_e", FIELD_fld_ae_sem_arithmetic_e, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_arithmetic_ep", FIELD_fld_ae_sem_arithmetic_ep, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_arithmetic_ep1", FIELD_fld_ae_sem_arithmetic_ep1, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_select_ss", FIELD_fld_ae_sem_select_ss, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_select_vr", FIELD_fld_ae_sem_select_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_select_vs", FIELD_fld_ae_sem_select_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_select_vt", FIELD_fld_ae_sem_select_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_select_vu", FIELD_fld_ae_sem_select_vu, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_select_isel", FIELD_fld_ae_sem_select_isel, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_encode, OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_shift_e", FIELD_fld_ae_sem_shift_e, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_shift_i8", FIELD_fld_ae_sem_shift_i8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_shift_i8_encode, OperandSem_opnd_sem_opnd_ae_sem_shift_i8_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_multiply_d1", FIELD_fld_ae_sem_multiply_d1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_multiply_d3", FIELD_fld_ae_sem_multiply_d3, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_imm", FIELD_fld_ae_sem_dr_to_dr_imm, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_imm_encode, OperandSem_opnd_sem_opnd_ae_sem_dr_to_dr_imm_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_rng_d", FIELD_fld_ae_sem_rng_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_sb_loads_stores_iba2", FIELD_fld_ae_sem_sb_loads_stores_iba2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba2_encode, OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_ar_ar_s", FIELD_fld_ae_sem_dr_to_ar_ar_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_AE_ARDECNORM16_ar_u", FIELD_fld_AE_ARDECNORM16_ar_u, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_rng_a", FIELD_fld_ae_sem_rng_a, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_rng_art", FIELD_fld_ae_sem_rng_art, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_rng_i2", FIELD_fld_ae_sem_rng_i2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_rng_imm2", FIELD_fld_ae_sem_rng_imm2, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_encode, OperandSem_opnd_sem_opnd_ae_sem_loads_stores_imm2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_lb_db_ops_ar_u", FIELD_fld_ae_sem_lb_db_ops_ar_u, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_lb_db_ops_iba", FIELD_fld_ae_sem_lb_db_ops_iba, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_encode, OperandSem_opnd_sem_opnd_ae_sem_sb_loads_stores_iba_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_dr_to_ar_vr", FIELD_fld_ae_sem_dr_to_ar_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spmisc_brt", FIELD_fld_ae_sem_spmisc_brt, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_spmisc_vr", FIELD_fld_ae_sem_spmisc_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spmisc_vs", FIELD_fld_ae_sem_spmisc_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_dr_to_dr_arr", FIELD_fld_ae_sem_dr_to_dr_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_dr_to_dr_bt", FIELD_fld_ae_sem_dr_to_dr_bt, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_sp32cvt_art", FIELD_fld_ae_sem_sp32cvt_art, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_sp32cvt_i_imm5", FIELD_fld_ae_sem_sp32cvt_i_imm5, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_encode, OperandSem_opnd_sem_opnd_ae_sem_sp32cvt_i_imm5_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_sp32cvt_vr", FIELD_fld_ae_sem_sp32cvt_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_sp32cvt_vt", FIELD_fld_ae_sem_sp32cvt_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_sp32cvt_arr", FIELD_fld_ae_sem_sp32cvt_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_movfpstate_v", FIELD_fld_ae_sem_movfpstate_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_fpmov_vr", FIELD_fld_ae_sem_fpmov_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_fpmov_vt", FIELD_fld_ae_sem_fpmov_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_fpmov_i_imm4", FIELD_fld_ae_sem_fpmov_i_imm4, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_encode, OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_fpmov_vs", FIELD_fld_ae_sem_fpmov_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_fpmov_vu", FIELD_fld_ae_sem_fpmov_vu, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spmisc_vsM", FIELD_fld_ae_sem_spmisc_vsM, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spmisc_vtM", FIELD_fld_ae_sem_spmisc_vtM, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spmisc_vt", FIELD_fld_ae_sem_spmisc_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spaddsub_vr", FIELD_fld_ae_sem_spaddsub_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spaddsub_vs", FIELD_fld_ae_sem_spaddsub_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spaddsub_vt", FIELD_fld_ae_sem_spaddsub_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spaddsub_vu", FIELD_fld_ae_sem_spaddsub_vu, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vr", FIELD_fld_ae_sem_spfma_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vs", FIELD_fld_ae_sem_spfma_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vt", FIELD_fld_ae_sem_spfma_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vp", FIELD_fld_ae_sem_spfma_vp, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_i_imm1", FIELD_fld_ae_sem_spfma_i_imm1, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm1_encode, OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm1_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_spfma_i_imm3", FIELD_fld_ae_sem_spfma_i_imm3, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_encode, OperandSem_opnd_sem_opnd_ae_sem_spfma_i_imm3_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_spaddsub_vp", FIELD_fld_ae_sem_spaddsub_vp, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spaddsub_vq", FIELD_fld_ae_sem_spaddsub_vq, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vu", FIELD_fld_ae_sem_spfma_vu, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_spfma_vq", FIELD_fld_ae_sem_spfma_vq, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hprminmaxnum_vr", FIELD_fld_ae_sem_hprminmaxnum_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hprminmaxnum_vt", FIELD_fld_ae_sem_hprminmaxnum_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcmp_br4t", FIELD_fld_ae_sem_hpcmp_br4t, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_hpcmp_vr", FIELD_fld_ae_sem_hpcmp_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcmp_vs", FIELD_fld_ae_sem_hpcmp_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcnv_art", FIELD_fld_ae_sem_hpcnv_art, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_hpcnv_i_imm4", FIELD_fld_ae_sem_hpcnv_i_imm4, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_encode, OperandSem_opnd_sem_opnd_ae_sem_hpcnv_i_imm4_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_hpcnv_vr", FIELD_fld_ae_sem_hpcnv_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcnv_arr", FIELD_fld_ae_sem_hpcnv_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 63 }, + { "opnd_ae_sem_hpcnv_vt", FIELD_fld_ae_sem_hpcnv_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcmp_vt", FIELD_fld_ae_sem_hpcmp_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpcnv_vs", FIELD_fld_ae_sem_hpcnv_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vr", FIELD_fld_ae_sem_hpfma_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vs", FIELD_fld_ae_sem_hpfma_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vt", FIELD_fld_ae_sem_hpfma_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vp", FIELD_fld_ae_sem_hpfma_vp, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vu", FIELD_fld_ae_sem_hpfma_vu, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_hpfma_vq", FIELD_fld_ae_sem_hpfma_vq, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_c0", FIELD_fld_ae_sem_mul_nn_c0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_c1", FIELD_fld_ae_sem_mul_nn_c1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_c2", FIELD_fld_ae_sem_mul_nn_c2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_c3", FIELD_fld_ae_sem_mul_nn_c3, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_q0", FIELD_fld_ae_sem_mul_nn_q0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_q1", FIELD_fld_ae_sem_mul_nn_q1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_v0", FIELD_fld_ae_sem_mul_nn_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_v1", FIELD_fld_ae_sem_mul_nn_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_q2", FIELD_fld_ae_sem_mul_nn_q2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_q3", FIELD_fld_ae_sem_mul_nn_q3, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_v2", FIELD_fld_ae_sem_mul_nn_v2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_mul_nn_v3", FIELD_fld_ae_sem_mul_nn_v3, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 31 }, + { "bbi", FIELD_bbi, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "sae", FIELD_sae, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "sas", FIELD_sas, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "sargt", FIELD_sargt, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "s", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, + 0, 0, + -1, 0 }, + { "bitindex", FIELD_bitindex, -1, 0, + 0, + OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode, + 0, 0, + -1, 0 }, + { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 }, + { "imms8", FIELD_imms8, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, + { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, + { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, + { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, + { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, + { "r_disp", FIELD_r_disp, -1, 0, 0, 0, 0, 0, 0 }, + { "r_3", FIELD_r_3, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, + { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, + { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, + { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, + { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 }, + { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 }, + { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 }, + { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 }, + { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 }, + { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 }, + { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 }, + { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wloop_imm", FIELD_xt_wloop_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_Inst16b_12", FIELD_ae_fld_Inst16b_12, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_Inst16b_15_13", FIELD_ae_fld_Inst16b_15_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_art", FIELD_fld_ae_sem_arithmetic_art, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_ds", FIELD_fld_ae_sem_arithmetic_ds, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_v", FIELD_fld_ae_sem_arithmetic_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_v0", FIELD_fld_ae_sem_arithmetic_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_v1", FIELD_fld_ae_sem_arithmetic_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_va", FIELD_fld_ae_sem_arithmetic_va, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_vs", FIELD_fld_ae_sem_arithmetic_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_a", FIELD_fld_ae_sem_dr_to_ar_a, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_ab", FIELD_fld_ae_sem_dr_to_ar_ab, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_ai", FIELD_fld_ae_sem_dr_to_ar_ai, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_aoe", FIELD_fld_ae_sem_dr_to_ar_aoe, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_d", FIELD_fld_ae_sem_dr_to_ar_d, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_d0", FIELD_fld_ae_sem_dr_to_ar_d0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_d1", FIELD_fld_ae_sem_dr_to_ar_d1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_imm8", FIELD_fld_ae_sem_dr_to_ar_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_v0", FIELD_fld_ae_sem_dr_to_ar_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_vr", FIELD_fld_ae_sem_dr_to_ar_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_arr", FIELD_fld_ae_sem_dr_to_dr_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_bt", FIELD_fld_ae_sem_dr_to_dr_bt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_ds", FIELD_fld_ae_sem_dr_to_dr_ds, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_imm2", FIELD_fld_ae_sem_dr_to_dr_imm2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_immed", FIELD_fld_ae_sem_dr_to_dr_immed, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_movi_imm", FIELD_fld_ae_sem_dr_to_dr_movi_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_v", FIELD_fld_ae_sem_dr_to_dr_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_v0", FIELD_fld_ae_sem_dr_to_dr_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_v1", FIELD_fld_ae_sem_dr_to_dr_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcmp_br4t", FIELD_fld_ae_sem_hpcmp_br4t, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcmp_vr", FIELD_fld_ae_sem_hpcmp_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcmp_vs", FIELD_fld_ae_sem_hpcmp_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_arr", FIELD_fld_ae_sem_hpcnv_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_art", FIELD_fld_ae_sem_hpcnv_art, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_i_imm4", FIELD_fld_ae_sem_hpcnv_i_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_vr", FIELD_fld_ae_sem_hpcnv_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_vt", FIELD_fld_ae_sem_hpcnv_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hprminmaxnum_vr", FIELD_fld_ae_sem_hprminmaxnum_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hprminmaxnum_vt", FIELD_fld_ae_sem_hprminmaxnum_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_lb_ops_iba", FIELD_fld_ae_sem_lb_ops_iba, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_a", FIELD_fld_ae_sem_loads_stores_a, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_a.0", FIELD_fld_ae_sem_loads_stores_a_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_av", FIELD_fld_ae_sem_loads_stores_av, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_av1", FIELD_fld_ae_sem_loads_stores_av1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_end", FIELD_fld_ae_sem_loads_stores_end, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i128", FIELD_fld_ae_sem_loads_stores_i128, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i16", FIELD_fld_ae_sem_loads_stores_i16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i3", FIELD_fld_ae_sem_loads_stores_i3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i32", FIELD_fld_ae_sem_loads_stores_i32, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i32pos", FIELD_fld_ae_sem_loads_stores_i32pos, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i64", FIELD_fld_ae_sem_loads_stores_i64, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i64half", FIELD_fld_ae_sem_loads_stores_i64half, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i64neg", FIELD_fld_ae_sem_loads_stores_i64neg, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i64pos", FIELD_fld_ae_sem_loads_stores_i64pos, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i64x2", FIELD_fld_ae_sem_loads_stores_i64x2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_i8", FIELD_fld_ae_sem_loads_stores_i8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_imm2", FIELD_fld_ae_sem_loads_stores_imm2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_su", FIELD_fld_ae_sem_loads_stores_su, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_uu", FIELD_fld_ae_sem_loads_stores_uu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_v", FIELD_fld_ae_sem_loads_stores_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_v1", FIELD_fld_ae_sem_loads_stores_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_vu", FIELD_fld_ae_sem_loads_stores_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_x", FIELD_fld_ae_sem_loads_stores_x, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_pks_d", FIELD_fld_ae_sem_pks_d, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_pks_pos", FIELD_fld_ae_sem_pks_pos, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_pks_s", FIELD_fld_ae_sem_pks_s, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_v0", FIELD_fld_ae_sem_rng_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_v1", FIELD_fld_ae_sem_rng_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sb_loads_stores_iba", FIELD_fld_ae_sem_sb_loads_stores_iba, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_a", FIELD_fld_ae_sem_shift_a, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_a0", FIELD_fld_ae_sem_shift_a0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_d", FIELD_fld_ae_sem_shift_d, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_d0", FIELD_fld_ae_sem_shift_d0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_d1", FIELD_fld_ae_sem_shift_d1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_da", FIELD_fld_ae_sem_shift_da, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_i16", FIELD_fld_ae_sem_shift_i16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_i32", FIELD_fld_ae_sem_shift_i32, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_i64", FIELD_fld_ae_sem_shift_i64, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_imm32", FIELD_fld_ae_sem_shift_imm32, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_imm8", FIELD_fld_ae_sem_shift_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_sd", FIELD_fld_ae_sem_shift_sd, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sp32cvt_arr", FIELD_fld_ae_sem_sp32cvt_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sp32cvt_art", FIELD_fld_ae_sem_sp32cvt_art, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sp32cvt_i_imm5", FIELD_fld_ae_sem_sp32cvt_i_imm5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sp32cvt_vr", FIELD_fld_ae_sem_sp32cvt_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sp32cvt_vt", FIELD_fld_ae_sem_sp32cvt_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_brt", FIELD_fld_ae_sem_spmisc_brt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_vr", FIELD_fld_ae_sem_spmisc_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_vs", FIELD_fld_ae_sem_spmisc_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_10", FIELD_fld_ae_slot0_11_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_11", FIELD_fld_ae_slot0_11_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_8", FIELD_fld_ae_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_9", FIELD_fld_ae_slot0_11_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_0", FIELD_fld_ae_slot0_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_10", FIELD_fld_ae_slot0_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_12", FIELD_fld_ae_slot0_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_2", FIELD_fld_ae_slot0_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_6", FIELD_fld_ae_slot0_12_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_8", FIELD_fld_ae_slot0_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_12_9", FIELD_fld_ae_slot0_12_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_14_12", FIELD_fld_ae_slot0_14_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_14_13", FIELD_fld_ae_slot0_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_10", FIELD_fld_ae_slot0_17_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_12", FIELD_fld_ae_slot0_17_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_13", FIELD_fld_ae_slot0_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_14", FIELD_fld_ae_slot0_17_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_15", FIELD_fld_ae_slot0_17_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_16", FIELD_fld_ae_slot0_17_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_17", FIELD_fld_ae_slot0_17_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_17_8", FIELD_fld_ae_slot0_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_18_13", FIELD_fld_ae_slot0_18_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_18_15", FIELD_fld_ae_slot0_18_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_18_16", FIELD_fld_ae_slot0_18_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_18_8", FIELD_fld_ae_slot0_18_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_19_12", FIELD_fld_ae_slot0_19_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_19_15", FIELD_fld_ae_slot0_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_19_19", FIELD_fld_ae_slot0_19_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_19_8", FIELD_fld_ae_slot0_19_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_1_0", FIELD_fld_ae_slot0_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_1_1", FIELD_fld_ae_slot0_1_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_16", FIELD_fld_ae_slot0_20_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_20", FIELD_fld_ae_slot0_20_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_23_15", FIELD_fld_ae_slot0_23_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_23_17", FIELD_fld_ae_slot0_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_23_19", FIELD_fld_ae_slot0_23_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_23_22", FIELD_fld_ae_slot0_23_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_10", FIELD_fld_ae_slot0_28_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_12", FIELD_fld_ae_slot0_28_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_14", FIELD_fld_ae_slot0_28_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_15", FIELD_fld_ae_slot0_28_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_16", FIELD_fld_ae_slot0_28_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_17", FIELD_fld_ae_slot0_28_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_19", FIELD_fld_ae_slot0_28_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_21", FIELD_fld_ae_slot0_28_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_22", FIELD_fld_ae_slot0_28_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_24", FIELD_fld_ae_slot0_28_24, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_26", FIELD_fld_ae_slot0_28_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_27", FIELD_fld_ae_slot0_28_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_4", FIELD_fld_ae_slot0_28_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_28_8", FIELD_fld_ae_slot0_28_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_3_0", FIELD_fld_ae_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_3_1", FIELD_fld_ae_slot0_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_3_2", FIELD_fld_ae_slot0_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_3_3", FIELD_fld_ae_slot0_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_4_0", FIELD_fld_ae_slot0_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_4_4", FIELD_fld_ae_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_5_0", FIELD_fld_ae_slot0_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_5_4", FIELD_fld_ae_slot0_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_0", FIELD_fld_ae_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_2", FIELD_fld_ae_slot0_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_3", FIELD_fld_ae_slot0_7_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_4", FIELD_fld_ae_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_8_8", FIELD_fld_ae_slot0_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_9_4", FIELD_fld_ae_slot0_9_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_9_8", FIELD_fld_ae_slot0_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_9_9", FIELD_fld_ae_slot0_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_0_0", FIELD_fld_ae_slot1_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_12_8", FIELD_fld_ae_slot1_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_17_13", FIELD_fld_ae_slot1_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_17_17", FIELD_fld_ae_slot1_17_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_17_8", FIELD_fld_ae_slot1_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_1", FIELD_fld_ae_slot1_25_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_12", FIELD_fld_ae_slot1_25_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_13", FIELD_fld_ae_slot1_25_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_16", FIELD_fld_ae_slot1_25_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_17", FIELD_fld_ae_slot1_25_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_18", FIELD_fld_ae_slot1_25_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_20", FIELD_fld_ae_slot1_25_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_22", FIELD_fld_ae_slot1_25_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_23", FIELD_fld_ae_slot1_25_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_8", FIELD_fld_ae_slot1_25_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_25_9", FIELD_fld_ae_slot1_25_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_3_0", FIELD_fld_ae_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_3_2", FIELD_fld_ae_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_3_3", FIELD_fld_ae_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_7_4", FIELD_fld_ae_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_e", FIELD_fld_ae_sem_arithmetic_e, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_ep", FIELD_fld_ae_sem_arithmetic_ep, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_ep1", FIELD_fld_ae_sem_arithmetic_ep1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_ei", FIELD_fld_ae_sem_dr_to_ar_ei, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_eo", FIELD_fld_ae_sem_dr_to_ar_eo, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_immed.N", FIELD_fld_ae_sem_dr_to_dr_immed_N, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_fpmov_i_imm4", FIELD_fld_ae_sem_fpmov_i_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_fpmov_vr", FIELD_fld_ae_sem_fpmov_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_fpmov_vs", FIELD_fld_ae_sem_fpmov_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_fpmov_vt", FIELD_fld_ae_sem_fpmov_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_fpmov_vu", FIELD_fld_ae_sem_fpmov_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcmp_vt", FIELD_fld_ae_sem_hpcmp_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpcnv_vs", FIELD_fld_ae_sem_hpcnv_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vr", FIELD_fld_ae_sem_hpfma_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vs", FIELD_fld_ae_sem_hpfma_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vt", FIELD_fld_ae_sem_hpfma_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_movfpstate_v", FIELD_fld_ae_sem_movfpstate_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_acc_ep", FIELD_fld_ae_sem_multiply_acc_ep, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_d0", FIELD_fld_ae_sem_multiply_d0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_d2", FIELD_fld_ae_sem_multiply_d2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_q0", FIELD_fld_ae_sem_multiply_q0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_q1", FIELD_fld_ae_sem_multiply_q1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_reduction_sort_ds", FIELD_fld_ae_sem_reduction_sort_ds, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_reduction_sort_v", FIELD_fld_ae_sem_reduction_sort_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_reduction_sort_v0", FIELD_fld_ae_sem_reduction_sort_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_isel", FIELD_fld_ae_sem_select_isel, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_ss", FIELD_fld_ae_sem_select_ss, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_vr", FIELD_fld_ae_sem_select_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_vs", FIELD_fld_ae_sem_select_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_vt", FIELD_fld_ae_sem_select_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_select_vu", FIELD_fld_ae_sem_select_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vr", FIELD_fld_ae_sem_spaddsub_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vs", FIELD_fld_ae_sem_spaddsub_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vt", FIELD_fld_ae_sem_spaddsub_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vu", FIELD_fld_ae_sem_spaddsub_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_i_imm1", FIELD_fld_ae_sem_spfma_i_imm1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_i_imm3", FIELD_fld_ae_sem_spfma_i_imm3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vp", FIELD_fld_ae_sem_spfma_vp, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vr", FIELD_fld_ae_sem_spfma_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vs", FIELD_fld_ae_sem_spfma_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vt", FIELD_fld_ae_sem_spfma_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_vsM", FIELD_fld_ae_sem_spmisc_vsM, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_vt", FIELD_fld_ae_sem_spmisc_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spmisc_vtM", FIELD_fld_ae_sem_spmisc_vtM, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_14_0", FIELD_fld_ae_slot2_14_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_14_10", FIELD_fld_ae_slot2_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_14_14", FIELD_fld_ae_slot2_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_14_5", FIELD_fld_ae_slot2_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_16_15", FIELD_fld_ae_slot2_16_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_19_15", FIELD_fld_ae_slot2_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_15", FIELD_fld_ae_slot2_28_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_17", FIELD_fld_ae_slot2_28_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_19", FIELD_fld_ae_slot2_28_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_20", FIELD_fld_ae_slot2_28_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_25", FIELD_fld_ae_slot2_28_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_4", FIELD_fld_ae_slot2_28_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_28_5", FIELD_fld_ae_slot2_28_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_3_0", FIELD_fld_ae_slot2_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_0", FIELD_fld_ae_slot2_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_1", FIELD_fld_ae_slot2_9_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_2", FIELD_fld_ae_slot2_9_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_5", FIELD_fld_ae_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_6", FIELD_fld_ae_slot2_9_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_7", FIELD_fld_ae_slot2_9_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_8", FIELD_fld_ae_slot2_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_dr_imm", FIELD_fld_ae_sem_dr_to_dr_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_d1", FIELD_fld_ae_sem_multiply_d1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_multiply_d3", FIELD_fld_ae_sem_multiply_d3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_d", FIELD_fld_ae_sem_rng_d, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_e", FIELD_fld_ae_sem_shift_e, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_i8", FIELD_fld_ae_sem_shift_i8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_11_0", FIELD_fld_ae_slot3_11_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_14_0", FIELD_fld_ae_slot3_14_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_14_10", FIELD_fld_ae_slot3_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_14_12", FIELD_fld_ae_slot3_14_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_14_13", FIELD_fld_ae_slot3_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_16_13", FIELD_fld_ae_slot3_16_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_0", FIELD_fld_ae_slot3_19_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_10", FIELD_fld_ae_slot3_19_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_15", FIELD_fld_ae_slot3_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_17", FIELD_fld_ae_slot3_19_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_18", FIELD_fld_ae_slot3_19_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_19_19", FIELD_fld_ae_slot3_19_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_24_10", FIELD_fld_ae_slot3_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_24_19", FIELD_fld_ae_slot3_24_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_24_20", FIELD_fld_ae_slot3_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_12", FIELD_fld_ae_slot3_36_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_16", FIELD_fld_ae_slot3_36_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_19", FIELD_fld_ae_slot3_36_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_20", FIELD_fld_ae_slot3_36_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_22", FIELD_fld_ae_slot3_36_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_25", FIELD_fld_ae_slot3_36_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_36_30", FIELD_fld_ae_slot3_36_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_4_0", FIELD_fld_ae_slot3_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_9_0", FIELD_fld_ae_slot3_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_9_1", FIELD_fld_ae_slot3_9_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_9_3", FIELD_fld_ae_slot3_9_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_9_5", FIELD_fld_ae_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_0_0", FIELD_fld_ae2_slot0_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_11_4", FIELD_fld_ae2_slot0_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_11_8", FIELD_fld_ae2_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_11_9", FIELD_fld_ae2_slot0_11_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_12_0", FIELD_fld_ae2_slot0_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_12_2", FIELD_fld_ae2_slot0_12_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_12_4", FIELD_fld_ae2_slot0_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_12_8", FIELD_fld_ae2_slot0_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_14_13", FIELD_fld_ae2_slot0_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_14_8", FIELD_fld_ae2_slot0_14_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_0", FIELD_fld_ae2_slot0_15_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_12", FIELD_fld_ae2_slot0_15_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_13", FIELD_fld_ae2_slot0_15_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_15", FIELD_fld_ae2_slot0_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_4", FIELD_fld_ae2_slot0_15_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_15_8", FIELD_fld_ae2_slot0_15_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_17_13", FIELD_fld_ae2_slot0_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_17_17", FIELD_fld_ae2_slot0_17_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_18_15", FIELD_fld_ae2_slot0_18_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_18_17", FIELD_fld_ae2_slot0_18_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_18_18", FIELD_fld_ae2_slot0_18_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_1_0", FIELD_fld_ae2_slot0_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_23_18", FIELD_fld_ae2_slot0_23_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_23_19", FIELD_fld_ae2_slot0_23_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_3_0", FIELD_fld_ae2_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_16", FIELD_fld_ae2_slot0_40_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_17", FIELD_fld_ae2_slot0_40_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_18", FIELD_fld_ae2_slot0_40_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_19", FIELD_fld_ae2_slot0_40_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_21", FIELD_fld_ae2_slot0_40_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_23", FIELD_fld_ae2_slot0_40_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_24", FIELD_fld_ae2_slot0_40_24, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_25", FIELD_fld_ae2_slot0_40_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_26", FIELD_fld_ae2_slot0_40_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_40_27", FIELD_fld_ae2_slot0_40_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_0", FIELD_fld_ae2_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_4", FIELD_fld_ae2_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_6", FIELD_fld_ae2_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_7", FIELD_fld_ae2_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_8_8", FIELD_fld_ae2_slot0_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_9_8", FIELD_fld_ae2_slot0_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_0_0", FIELD_fld_ae2_slot1_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_11_0", FIELD_fld_ae2_slot1_11_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_11_10", FIELD_fld_ae2_slot1_11_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_11_8", FIELD_fld_ae2_slot1_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_14_10", FIELD_fld_ae2_slot1_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_14_11", FIELD_fld_ae2_slot1_14_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_14_12", FIELD_fld_ae2_slot1_14_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_14_14", FIELD_fld_ae2_slot1_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_14_8", FIELD_fld_ae2_slot1_14_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_12", FIELD_fld_ae2_slot1_36_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_14", FIELD_fld_ae2_slot1_36_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_15", FIELD_fld_ae2_slot1_36_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_16", FIELD_fld_ae2_slot1_36_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_17", FIELD_fld_ae2_slot1_36_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_18", FIELD_fld_ae2_slot1_36_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_20", FIELD_fld_ae2_slot1_36_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_22", FIELD_fld_ae2_slot1_36_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_36_23", FIELD_fld_ae2_slot1_36_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_3_0", FIELD_fld_ae2_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_3_1", FIELD_fld_ae2_slot1_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_3_2", FIELD_fld_ae2_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_3_3", FIELD_fld_ae2_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_7_4", FIELD_fld_ae2_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_9_8", FIELD_fld_ae2_slot1_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_9_9", FIELD_fld_ae2_slot1_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_14_10", FIELD_fld_ae2_slot2_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_17_0", FIELD_fld_ae2_slot2_17_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_17_10", FIELD_fld_ae2_slot2_17_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_17_15", FIELD_fld_ae2_slot2_17_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_17_17", FIELD_fld_ae2_slot2_17_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_19_10", FIELD_fld_ae2_slot2_19_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_19_15", FIELD_fld_ae2_slot2_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_19_18", FIELD_fld_ae2_slot2_19_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_19_9", FIELD_fld_ae2_slot2_19_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_10", FIELD_fld_ae2_slot2_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_15", FIELD_fld_ae2_slot2_24_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_20", FIELD_fld_ae2_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_5", FIELD_fld_ae2_slot2_24_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_9", FIELD_fld_ae2_slot2_24_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_18", FIELD_fld_ae2_slot2_42_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_20", FIELD_fld_ae2_slot2_42_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_25", FIELD_fld_ae2_slot2_42_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_26", FIELD_fld_ae2_slot2_42_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_28", FIELD_fld_ae2_slot2_42_28, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_42_30", FIELD_fld_ae2_slot2_42_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_4_0", FIELD_fld_ae2_slot2_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_9_5", FIELD_fld_ae2_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vp", FIELD_fld_ae_sem_spaddsub_vp, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spaddsub_vq", FIELD_fld_ae_sem_spaddsub_vq, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_11_11", FIELD_fld_ae3_slot0_11_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_11_4", FIELD_fld_ae3_slot0_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_11_8", FIELD_fld_ae3_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_12_12", FIELD_fld_ae3_slot0_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_12_8", FIELD_fld_ae3_slot0_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_13_13", FIELD_fld_ae3_slot0_13_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_13_8", FIELD_fld_ae3_slot0_13_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_1_0", FIELD_fld_ae3_slot0_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_11", FIELD_fld_ae3_slot0_32_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_12", FIELD_fld_ae3_slot0_32_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_13", FIELD_fld_ae3_slot0_32_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_14", FIELD_fld_ae3_slot0_32_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_15", FIELD_fld_ae3_slot0_32_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_16", FIELD_fld_ae3_slot0_32_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_17", FIELD_fld_ae3_slot0_32_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_18", FIELD_fld_ae3_slot0_32_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_20", FIELD_fld_ae3_slot0_32_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_27", FIELD_fld_ae3_slot0_32_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_32_8", FIELD_fld_ae3_slot0_32_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_3_0", FIELD_fld_ae3_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_3_2", FIELD_fld_ae3_slot0_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_3_3", FIELD_fld_ae3_slot0_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_4_0", FIELD_fld_ae3_slot0_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_4_4", FIELD_fld_ae3_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_5_0", FIELD_fld_ae3_slot0_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_5_4", FIELD_fld_ae3_slot0_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_7_0", FIELD_fld_ae3_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_7_2", FIELD_fld_ae3_slot0_7_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_7_4", FIELD_fld_ae3_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_7_6", FIELD_fld_ae3_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_8_8", FIELD_fld_ae3_slot0_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_9_4", FIELD_fld_ae3_slot0_9_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_9_8", FIELD_fld_ae3_slot0_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_ar_s", FIELD_fld_ae_sem_dr_to_ar_ar_s, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_sb_loads_stores_iba2", FIELD_fld_ae_sem_sb_loads_stores_iba2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_0", FIELD_fld_ae3_slot1_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_11", FIELD_fld_ae3_slot1_23_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_12", FIELD_fld_ae3_slot1_23_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_13", FIELD_fld_ae3_slot1_23_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_15", FIELD_fld_ae3_slot1_23_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_16", FIELD_fld_ae3_slot1_23_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_17", FIELD_fld_ae3_slot1_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_19", FIELD_fld_ae3_slot1_23_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_6", FIELD_fld_ae3_slot1_23_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_8", FIELD_fld_ae3_slot1_23_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_23_9", FIELD_fld_ae3_slot1_23_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_3_0", FIELD_fld_ae3_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_3_1", FIELD_fld_ae3_slot1_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_3_2", FIELD_fld_ae3_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_3_3", FIELD_fld_ae3_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_7_4", FIELD_fld_ae3_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_9_8", FIELD_fld_ae3_slot1_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_AE_ARDECNORM16_ar_u", FIELD_fld_AE_ARDECNORM16_ar_u, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_11_10", FIELD_fld_ae5_slot0_11_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_11_4", FIELD_fld_ae5_slot0_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_11_8", FIELD_fld_ae5_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_11_9", FIELD_fld_ae5_slot0_11_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_12_10", FIELD_fld_ae5_slot0_12_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_12_4", FIELD_fld_ae5_slot0_12_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_12_6", FIELD_fld_ae5_slot0_12_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_12_8", FIELD_fld_ae5_slot0_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_12_9", FIELD_fld_ae5_slot0_12_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_1_0", FIELD_fld_ae5_slot0_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_1_1", FIELD_fld_ae5_slot0_1_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_12", FIELD_fld_ae5_slot0_29_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_13", FIELD_fld_ae5_slot0_29_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_15", FIELD_fld_ae5_slot0_29_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_16", FIELD_fld_ae5_slot0_29_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_17", FIELD_fld_ae5_slot0_29_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_18", FIELD_fld_ae5_slot0_29_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_19", FIELD_fld_ae5_slot0_29_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_20", FIELD_fld_ae5_slot0_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_27", FIELD_fld_ae5_slot0_29_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_5", FIELD_fld_ae5_slot0_29_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_6", FIELD_fld_ae5_slot0_29_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_29_8", FIELD_fld_ae5_slot0_29_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_2_0", FIELD_fld_ae5_slot0_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_3_0", FIELD_fld_ae5_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_3_2", FIELD_fld_ae5_slot0_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_4_0", FIELD_fld_ae5_slot0_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_4_4", FIELD_fld_ae5_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_7_0", FIELD_fld_ae5_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_7_4", FIELD_fld_ae5_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_7_7", FIELD_fld_ae5_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_8_8", FIELD_fld_ae5_slot0_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_lb_db_ops_ar_u", FIELD_fld_ae_sem_lb_db_ops_ar_u, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_lb_db_ops_iba", FIELD_fld_ae_sem_lb_db_ops_iba, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_a", FIELD_fld_ae_sem_rng_a, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_art", FIELD_fld_ae_sem_rng_art, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_i2", FIELD_fld_ae_sem_rng_i2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_imm2", FIELD_fld_ae_sem_rng_imm2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot1_1_0", FIELD_fld_ae5_slot1_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_14_10", FIELD_fld_ae5_slot2_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_14_14", FIELD_fld_ae5_slot2_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_14_5", FIELD_fld_ae5_slot2_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_24_0", FIELD_fld_ae5_slot2_24_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_24_15", FIELD_fld_ae5_slot2_24_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_24_17", FIELD_fld_ae5_slot2_24_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_24_20", FIELD_fld_ae5_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_4_0", FIELD_fld_ae5_slot2_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_9_0", FIELD_fld_ae5_slot2_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_9_5", FIELD_fld_ae5_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_9_7", FIELD_fld_ae5_slot2_9_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_10_10", FIELD_fld_ae6_slot0_10_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_15_15", FIELD_fld_ae6_slot0_15_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_10", FIELD_fld_ae6_slot0_29_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_13", FIELD_fld_ae6_slot0_29_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_14", FIELD_fld_ae6_slot0_29_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_15", FIELD_fld_ae6_slot0_29_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_18", FIELD_fld_ae6_slot0_29_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_20", FIELD_fld_ae6_slot0_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_29_5", FIELD_fld_ae6_slot0_29_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_4_0", FIELD_fld_ae6_slot0_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_4_4", FIELD_fld_ae6_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_7_4", FIELD_fld_ae6_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_7_7", FIELD_fld_ae6_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_9_8", FIELD_fld_ae6_slot0_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_9_9", FIELD_fld_ae6_slot0_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_14_14", FIELD_fld_ae6_slot1_14_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_12", FIELD_fld_ae6_slot1_27_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_15", FIELD_fld_ae6_slot1_27_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_20", FIELD_fld_ae6_slot1_27_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_21", FIELD_fld_ae6_slot1_27_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_3", FIELD_fld_ae6_slot1_27_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_27_6", FIELD_fld_ae6_slot1_27_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_2_0", FIELD_fld_ae6_slot1_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_9_5", FIELD_fld_ae6_slot1_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_9_6", FIELD_fld_ae6_slot1_9_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_9_7", FIELD_fld_ae6_slot1_9_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_9_8", FIELD_fld_ae6_slot1_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_9_9", FIELD_fld_ae6_slot1_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_10_10", FIELD_fld_ae6_slot2_10_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_11_10", FIELD_fld_ae6_slot2_11_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_24_0", FIELD_fld_ae6_slot2_24_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_24_10", FIELD_fld_ae6_slot2_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_24_14", FIELD_fld_ae6_slot2_24_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_24_15", FIELD_fld_ae6_slot2_24_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_24_20", FIELD_fld_ae6_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_4_2", FIELD_fld_ae6_slot2_4_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_9_5", FIELD_fld_ae6_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_10_10", FIELD_fld_ae6_slot3_10_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_12_0", FIELD_fld_ae6_slot3_12_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_14_0", FIELD_fld_ae6_slot3_14_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_14_10", FIELD_fld_ae6_slot3_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_14_13", FIELD_fld_ae6_slot3_14_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_14_5", FIELD_fld_ae6_slot3_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_24_20", FIELD_fld_ae6_slot3_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_37_13", FIELD_fld_ae6_slot3_37_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_37_15", FIELD_fld_ae6_slot3_37_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_37_20", FIELD_fld_ae6_slot3_37_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_37_30", FIELD_fld_ae6_slot3_37_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_9_5", FIELD_fld_ae6_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_12_6", FIELD_fld_ae7_slot0_12_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_23_0", FIELD_fld_ae7_slot0_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_23_13", FIELD_fld_ae7_slot0_23_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_23_17", FIELD_fld_ae7_slot0_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_23_18", FIELD_fld_ae7_slot0_23_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_23_6", FIELD_fld_ae7_slot0_23_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_7_4", FIELD_fld_ae7_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_7_6", FIELD_fld_ae7_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_7_7", FIELD_fld_ae7_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_12_6", FIELD_fld_ae7_slot1_12_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_23_0", FIELD_fld_ae7_slot1_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_23_13", FIELD_fld_ae7_slot1_23_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_23_17", FIELD_fld_ae7_slot1_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_23_18", FIELD_fld_ae7_slot1_23_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_23_6", FIELD_fld_ae7_slot1_23_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_7_4", FIELD_fld_ae7_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_7_6", FIELD_fld_ae7_slot1_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_7_7", FIELD_fld_ae7_slot1_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_11_0", FIELD_fld_ae7_slot2_11_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_14_10", FIELD_fld_ae7_slot2_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_14_5", FIELD_fld_ae7_slot2_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_36_12", FIELD_fld_ae7_slot2_36_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_36_15", FIELD_fld_ae7_slot2_36_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_36_20", FIELD_fld_ae7_slot2_36_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_36_25", FIELD_fld_ae7_slot2_36_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_36_30", FIELD_fld_ae7_slot2_36_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_9_5", FIELD_fld_ae7_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_10_0", FIELD_fld_ae7_slot3_10_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_14_10", FIELD_fld_ae7_slot3_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_14_5", FIELD_fld_ae7_slot3_14_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_24_10", FIELD_fld_ae7_slot3_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_35_11", FIELD_fld_ae7_slot3_35_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_35_20", FIELD_fld_ae7_slot3_35_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_35_25", FIELD_fld_ae7_slot3_35_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_35_30", FIELD_fld_ae7_slot3_35_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_4_0", FIELD_fld_ae7_slot3_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_9_5", FIELD_fld_ae7_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_13_12", FIELD_fld_ae8_slot0_13_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_13_13", FIELD_fld_ae8_slot0_13_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_13_4", FIELD_fld_ae8_slot0_13_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_13_9", FIELD_fld_ae8_slot0_13_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_17_4", FIELD_fld_ae8_slot0_17_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_17_8", FIELD_fld_ae8_slot0_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_12", FIELD_fld_ae8_slot0_31_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_15", FIELD_fld_ae8_slot0_31_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_18", FIELD_fld_ae8_slot0_31_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_19", FIELD_fld_ae8_slot0_31_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_20", FIELD_fld_ae8_slot0_31_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_21", FIELD_fld_ae8_slot0_31_21, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_22", FIELD_fld_ae8_slot0_31_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_23", FIELD_fld_ae8_slot0_31_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_7", FIELD_fld_ae8_slot0_31_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_8", FIELD_fld_ae8_slot0_31_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_31_9", FIELD_fld_ae8_slot0_31_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_3_0", FIELD_fld_ae8_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_6_0", FIELD_fld_ae8_slot0_6_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_7_4", FIELD_fld_ae8_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_7_5", FIELD_fld_ae8_slot0_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_7_7", FIELD_fld_ae8_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot0_8_0", FIELD_fld_ae8_slot0_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_17_13", FIELD_fld_ae8_slot1_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_17_14", FIELD_fld_ae8_slot1_17_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_17_15", FIELD_fld_ae8_slot1_17_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_17_8", FIELD_fld_ae8_slot1_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_12", FIELD_fld_ae8_slot1_29_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_13", FIELD_fld_ae8_slot1_29_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_18", FIELD_fld_ae8_slot1_29_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_20", FIELD_fld_ae8_slot1_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_22", FIELD_fld_ae8_slot1_29_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_23", FIELD_fld_ae8_slot1_29_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_5", FIELD_fld_ae8_slot1_29_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_8", FIELD_fld_ae8_slot1_29_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_29_9", FIELD_fld_ae8_slot1_29_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_3_0", FIELD_fld_ae8_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_3_3", FIELD_fld_ae8_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_4_0", FIELD_fld_ae8_slot1_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot1_7_4", FIELD_fld_ae8_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_19_10", FIELD_fld_ae8_slot2_19_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_19_15", FIELD_fld_ae8_slot2_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_33_15", FIELD_fld_ae8_slot2_33_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_33_25", FIELD_fld_ae8_slot2_33_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_33_9", FIELD_fld_ae8_slot2_33_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_34_30", FIELD_fld_ae8_slot2_34_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_39_35", FIELD_fld_ae8_slot2_39_35, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_44_35", FIELD_fld_ae8_slot2_44_35, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_58_34", FIELD_fld_ae8_slot2_58_34, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_58_35", FIELD_fld_ae8_slot2_58_35, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_58_40", FIELD_fld_ae8_slot2_58_40, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_58_50", FIELD_fld_ae8_slot2_58_50, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_8_0", FIELD_fld_ae8_slot2_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae8_slot2_9_0", FIELD_fld_ae8_slot2_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_c0", FIELD_fld_ae_sem_mul_nn_c0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_c1", FIELD_fld_ae_sem_mul_nn_c1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_c2", FIELD_fld_ae_sem_mul_nn_c2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_c3", FIELD_fld_ae_sem_mul_nn_c3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_q0", FIELD_fld_ae_sem_mul_nn_q0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_q1", FIELD_fld_ae_sem_mul_nn_q1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_q2", FIELD_fld_ae_sem_mul_nn_q2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_q3", FIELD_fld_ae_sem_mul_nn_q3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_v0", FIELD_fld_ae_sem_mul_nn_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_v1", FIELD_fld_ae_sem_mul_nn_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_v2", FIELD_fld_ae_sem_mul_nn_v2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_nn_v3", FIELD_fld_ae_sem_mul_nn_v3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_0_0", FIELD_fld_ae9_slot0_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_12_12", FIELD_fld_ae9_slot0_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_12_5", FIELD_fld_ae9_slot0_12_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_12_8", FIELD_fld_ae9_slot0_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_17_13", FIELD_fld_ae9_slot0_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_17_4", FIELD_fld_ae9_slot0_17_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_17_8", FIELD_fld_ae9_slot0_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_10", FIELD_fld_ae9_slot0_27_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_12", FIELD_fld_ae9_slot0_27_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_13", FIELD_fld_ae9_slot0_27_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_16", FIELD_fld_ae9_slot0_27_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_17", FIELD_fld_ae9_slot0_27_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_18", FIELD_fld_ae9_slot0_27_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_19", FIELD_fld_ae9_slot0_27_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_20", FIELD_fld_ae9_slot0_27_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_22", FIELD_fld_ae9_slot0_27_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_23", FIELD_fld_ae9_slot0_27_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_3", FIELD_fld_ae9_slot0_27_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_27_8", FIELD_fld_ae9_slot0_27_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_2_0", FIELD_fld_ae9_slot0_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_3_0", FIELD_fld_ae9_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_7_0", FIELD_fld_ae9_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_7_4", FIELD_fld_ae9_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_7_5", FIELD_fld_ae9_slot0_7_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_7_6", FIELD_fld_ae9_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_7_7", FIELD_fld_ae9_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_8_4", FIELD_fld_ae9_slot0_8_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_8_5", FIELD_fld_ae9_slot0_8_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot0_9_5", FIELD_fld_ae9_slot0_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_17_13", FIELD_fld_ae9_slot1_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_17_8", FIELD_fld_ae9_slot1_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_1_0", FIELD_fld_ae9_slot1_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_12", FIELD_fld_ae9_slot1_26_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_13", FIELD_fld_ae9_slot1_26_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_16", FIELD_fld_ae9_slot1_26_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_17", FIELD_fld_ae9_slot1_26_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_18", FIELD_fld_ae9_slot1_26_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_2", FIELD_fld_ae9_slot1_26_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_20", FIELD_fld_ae9_slot1_26_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_22", FIELD_fld_ae9_slot1_26_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_23", FIELD_fld_ae9_slot1_26_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_8", FIELD_fld_ae9_slot1_26_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_26_9", FIELD_fld_ae9_slot1_26_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_3_0", FIELD_fld_ae9_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_3_2", FIELD_fld_ae9_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_3_3", FIELD_fld_ae9_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot1_7_4", FIELD_fld_ae9_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_24_14", FIELD_fld_ae9_slot2_24_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_24_15", FIELD_fld_ae9_slot2_24_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_24_20", FIELD_fld_ae9_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_14", FIELD_fld_ae9_slot2_33_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_15", FIELD_fld_ae9_slot2_33_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_20", FIELD_fld_ae9_slot2_33_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_25", FIELD_fld_ae9_slot2_33_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_26", FIELD_fld_ae9_slot2_33_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_28", FIELD_fld_ae9_slot2_33_28, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_30", FIELD_fld_ae9_slot2_33_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_33_9", FIELD_fld_ae9_slot2_33_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_4_0", FIELD_fld_ae9_slot2_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_5_0", FIELD_fld_ae9_slot2_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_6_0", FIELD_fld_ae9_slot2_6_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_8_0", FIELD_fld_ae9_slot2_8_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_9_0", FIELD_fld_ae9_slot2_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_9_5", FIELD_fld_ae9_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot2_9_9", FIELD_fld_ae9_slot2_9_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vp", FIELD_fld_ae_sem_hpfma_vp, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vu", FIELD_fld_ae_sem_hpfma_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vu", FIELD_fld_ae_sem_spfma_vu, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_19_15", FIELD_fld_ae9_slot3_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_24_20", FIELD_fld_ae9_slot3_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_14", FIELD_fld_ae9_slot3_31_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_15", FIELD_fld_ae9_slot3_31_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_20", FIELD_fld_ae9_slot3_31_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_25", FIELD_fld_ae9_slot3_31_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_26", FIELD_fld_ae9_slot3_31_26, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_28", FIELD_fld_ae9_slot3_31_28, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_31_7", FIELD_fld_ae9_slot3_31_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_4_0", FIELD_fld_ae9_slot3_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_4_3", FIELD_fld_ae9_slot3_4_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_4_4", FIELD_fld_ae9_slot3_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_6_0", FIELD_fld_ae9_slot3_6_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_9_0", FIELD_fld_ae9_slot3_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae9_slot3_9_5", FIELD_fld_ae9_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_17_13", FIELD_fld_ae10_slot0_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_17_4", FIELD_fld_ae10_slot0_17_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_17_8", FIELD_fld_ae10_slot0_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_0", FIELD_fld_ae10_slot0_24_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_10", FIELD_fld_ae10_slot0_24_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_12", FIELD_fld_ae10_slot0_24_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_13", FIELD_fld_ae10_slot0_24_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_16", FIELD_fld_ae10_slot0_24_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_17", FIELD_fld_ae10_slot0_24_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_18", FIELD_fld_ae10_slot0_24_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_20", FIELD_fld_ae10_slot0_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_24_8", FIELD_fld_ae10_slot0_24_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_3_0", FIELD_fld_ae10_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_7_4", FIELD_fld_ae10_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_7_6", FIELD_fld_ae10_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_7_7", FIELD_fld_ae10_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot0_8_4", FIELD_fld_ae10_slot0_8_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_0_0", FIELD_fld_ae10_slot1_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_17_13", FIELD_fld_ae10_slot1_17_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_17_8", FIELD_fld_ae10_slot1_17_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_1", FIELD_fld_ae10_slot1_25_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_12", FIELD_fld_ae10_slot1_25_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_13", FIELD_fld_ae10_slot1_25_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_16", FIELD_fld_ae10_slot1_25_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_17", FIELD_fld_ae10_slot1_25_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_18", FIELD_fld_ae10_slot1_25_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_20", FIELD_fld_ae10_slot1_25_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_22", FIELD_fld_ae10_slot1_25_22, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_23", FIELD_fld_ae10_slot1_25_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_8", FIELD_fld_ae10_slot1_25_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_25_9", FIELD_fld_ae10_slot1_25_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_3_0", FIELD_fld_ae10_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_3_2", FIELD_fld_ae10_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_3_3", FIELD_fld_ae10_slot1_3_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot1_7_4", FIELD_fld_ae10_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_24_20", FIELD_fld_ae10_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_29_20", FIELD_fld_ae10_slot2_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_29_25", FIELD_fld_ae10_slot2_29_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_10", FIELD_fld_ae10_slot2_34_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_14", FIELD_fld_ae10_slot2_34_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_15", FIELD_fld_ae10_slot2_34_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_20", FIELD_fld_ae10_slot2_34_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_25", FIELD_fld_ae10_slot2_34_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_30", FIELD_fld_ae10_slot2_34_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_31", FIELD_fld_ae10_slot2_34_31, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_34_33", FIELD_fld_ae10_slot2_34_33, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_4_0", FIELD_fld_ae10_slot2_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_9_0", FIELD_fld_ae10_slot2_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot2_9_5", FIELD_fld_ae10_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_hpfma_vq", FIELD_fld_ae_sem_hpfma_vq, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_spfma_vq", FIELD_fld_ae_sem_spfma_vq, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_19_15", FIELD_fld_ae10_slot3_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_29_20", FIELD_fld_ae10_slot3_29_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_29_25", FIELD_fld_ae10_slot3_29_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_10", FIELD_fld_ae10_slot3_34_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_14", FIELD_fld_ae10_slot3_34_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_15", FIELD_fld_ae10_slot3_34_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_20", FIELD_fld_ae10_slot3_34_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_25", FIELD_fld_ae10_slot3_34_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_30", FIELD_fld_ae10_slot3_34_30, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_31", FIELD_fld_ae10_slot3_34_31, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_34_33", FIELD_fld_ae10_slot3_34_33, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_4_0", FIELD_fld_ae10_slot3_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_4_3", FIELD_fld_ae10_slot3_4_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_4_4", FIELD_fld_ae10_slot3_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_9_0", FIELD_fld_ae10_slot3_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae10_slot3_9_5", FIELD_fld_ae10_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_0", FIELD_fld_ae4_slot0_22_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_12", FIELD_fld_ae4_slot0_22_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_13", FIELD_fld_ae4_slot0_22_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_16", FIELD_fld_ae4_slot0_22_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_17", FIELD_fld_ae4_slot0_22_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_18", FIELD_fld_ae4_slot0_22_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_20", FIELD_fld_ae4_slot0_22_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_6", FIELD_fld_ae4_slot0_22_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_22_8", FIELD_fld_ae4_slot0_22_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_3_0", FIELD_fld_ae4_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_3_1", FIELD_fld_ae4_slot0_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_4_4", FIELD_fld_ae4_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_7_4", FIELD_fld_ae4_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_0", FIELD_fld_ae4_slot1_22_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_12", FIELD_fld_ae4_slot1_22_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_13", FIELD_fld_ae4_slot1_22_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_16", FIELD_fld_ae4_slot1_22_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_17", FIELD_fld_ae4_slot1_22_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_18", FIELD_fld_ae4_slot1_22_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_22_8", FIELD_fld_ae4_slot1_22_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_3_0", FIELD_fld_ae4_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_3_1", FIELD_fld_ae4_slot1_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_7_4", FIELD_fld_ae4_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_23_0", FIELD_fld_ae4_slot2_23_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_23_12", FIELD_fld_ae4_slot2_23_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_23_15", FIELD_fld_ae4_slot2_23_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_23_17", FIELD_fld_ae4_slot2_23_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_23_20", FIELD_fld_ae4_slot2_23_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_4_0", FIELD_fld_ae4_slot2_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot2_9_5", FIELD_fld_ae4_slot2_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_14_10", FIELD_fld_ae4_slot3_14_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_19_15", FIELD_fld_ae4_slot3_19_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_19_19", FIELD_fld_ae4_slot3_19_19, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_19_5", FIELD_fld_ae4_slot3_19_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_27_20", FIELD_fld_ae4_slot3_27_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_27_25", FIELD_fld_ae4_slot3_27_25, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_27_3", FIELD_fld_ae4_slot3_27_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_2_0", FIELD_fld_ae4_slot3_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_9_0", FIELD_fld_ae4_slot3_9_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot3_9_5", FIELD_fld_ae4_slot3_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot4_22_0", FIELD_fld_ae4_slot4_22_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot4_22_15", FIELD_fld_ae4_slot4_22_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot4_22_20", FIELD_fld_ae4_slot4_22_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot4_9_5", FIELD_fld_ae4_slot4_9_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_11_8", FIELD_fld_Inst_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_12_12", FIELD_fld_Inst_12_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_12_8", FIELD_fld_Inst_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_13_8", FIELD_fld_Inst_13_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_15_12", FIELD_fld_Inst_15_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_19_17", FIELD_fld_Inst_19_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_19_18", FIELD_fld_Inst_19_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_23_12", FIELD_fld_Inst_23_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_23_16", FIELD_fld_Inst_23_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_4_4", FIELD_fld_Inst_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_5_4", FIELD_fld_Inst_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_7_4", FIELD_fld_Inst_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_7_6", FIELD_fld_Inst_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_7_7", FIELD_fld_Inst_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_9_8", FIELD_fld_Inst_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 } +}; + +enum xtensa_operand_id { + OPERAND_soffsetx4, + OPERAND_immr, + OPERAND_uimm12x8, + OPERAND_simm4, + OPERAND_arr, + OPERAND_ars, + OPERAND__ars_invisible, + OPERAND_art, + OPERAND_ar0, + OPERAND_ar4, + OPERAND_ar8, + OPERAND_ar12, + OPERAND_ars_entry, + OPERAND_immrx4, + OPERAND_lsi4x4, + OPERAND_simm7, + OPERAND_uimm6, + OPERAND_ai4const, + OPERAND_b4const, + OPERAND_b4constu, + OPERAND_immt, + OPERAND_uimms8, + OPERAND_uimm8, + OPERAND_uimm8x2, + OPERAND_uimm8x4, + OPERAND_uimm4x16, + OPERAND_uimmrx4, + OPERAND_simm8, + OPERAND_simm8x256, + OPERAND_simm12b, + OPERAND_msalp32, + OPERAND_op2p1, + OPERAND_label8, + OPERAND_ulabel8, + OPERAND_label12, + OPERAND_soffset, + OPERAND_uimm16x4, + OPERAND_imms, + OPERAND_imms1, + OPERAND_bt, + OPERAND_bs, + OPERAND_br, + OPERAND_bt2, + OPERAND_bs2, + OPERAND_br2, + OPERAND_bt4, + OPERAND_bs4, + OPERAND_br4, + OPERAND_bt8, + OPERAND_bs8, + OPERAND_br8, + OPERAND_bt16, + OPERAND_bs16, + OPERAND_br16, + OPERAND_brall, + OPERAND_tp7, + OPERAND_xt_wbr15_label, + OPERAND_xt_wloop_label, + OPERAND_ae_uimm2x2, + OPERAND_opnd_ae_sem_dr_to_dr_v, + OPERAND_opnd_ae_sem_arithmetic_v, + OPERAND_opnd_ae_sem_arithmetic_v0, + OPERAND_opnd_ae_sem_arithmetic_v1, + OPERAND_opnd_ae_sem_loads_stores_a_0, + OPERAND_opnd_ae_sem_loads_stores_x, + OPERAND_opnd_ae_sem_loads_stores_end, + OPERAND_opnd_ae_sem_loads_stores_i64, + OPERAND_opnd_ae_sem_lb_ops_iba, + OPERAND_opnd_ae_sem_sb_loads_stores_iba, + OPERAND_opnd_ae_sem_pks_d, + OPERAND_opnd_ae_sem_pks_pos, + OPERAND_opnd_ae_sem_pks_s, + OPERAND_opnd_ae_sem_dr_to_ar_a, + OPERAND_opnd_ae_sem_dr_to_ar_v0, + OPERAND_opnd_ae_sem_dr_to_dr_v0, + OPERAND_opnd_ae_sem_dr_to_ar_ab, + OPERAND_opnd_ae_sem_dr_to_ar_ai, + OPERAND_opnd_ae_sem_dr_to_ar_aoe, + OPERAND_opnd_ae_sem_dr_to_dr_movi_imm, + OPERAND_opnd_ae_sem_dr_to_dr_ds, + OPERAND_opnd_ae_sem_dr_to_dr_v1, + OPERAND_opnd_ae_sem_dr_to_ar_imm8, + OPERAND_opnd_ae_sem_shift_a0, + OPERAND_opnd_ae_sem_shift_d, + OPERAND_opnd_ae_sem_shift_d0, + OPERAND_opnd_ae_sem_dr_to_ar_d, + OPERAND_opnd_ae_sem_dr_to_ar_d0, + OPERAND_opnd_ae_sem_dr_to_ar_d1, + OPERAND_opnd_ae_sem_dr_to_dr_imm2, + OPERAND_opnd_ae_sem_arithmetic_ds, + OPERAND_opnd_ae_sem_loads_stores_uu, + OPERAND_opnd_ae_sem_loads_stores_vu, + OPERAND_opnd_ae_sem_loads_stores_i32, + OPERAND_opnd_ae_sem_loads_stores_v, + OPERAND_opnd_ae_sem_loads_stores_i32pos, + OPERAND_opnd_ae_sem_loads_stores_i16, + OPERAND_opnd_ae_sem_loads_stores_i8, + OPERAND_opnd_ae_sem_loads_stores_i64pos, + OPERAND_opnd_ae_sem_loads_stores_i64neg, + OPERAND_opnd_ae_sem_loads_stores_i64half, + OPERAND_opnd_ae_sem_loads_stores_su, + OPERAND_opnd_ae_sem_loads_stores_v1, + OPERAND_opnd_ae_sem_loads_stores_av, + OPERAND_opnd_ae_sem_shift_i16, + OPERAND_opnd_ae_sem_shift_i32, + OPERAND_opnd_ae_sem_shift_d1, + OPERAND_opnd_ae_sem_shift_da, + OPERAND_opnd_ae_sem_shift_imm32, + OPERAND_opnd_ae_sem_shift_a, + OPERAND_opnd_ae_sem_shift_sd, + OPERAND_opnd_ae_sem_shift_i64, + OPERAND_opnd_ae_sem_shift_imm8, + OPERAND_opnd_ae_sem_dr_to_dr_immed, + OPERAND_opnd_ae_sem_arithmetic_art, + OPERAND_opnd_ae_sem_arithmetic_va, + OPERAND_opnd_ae_sem_arithmetic_vs, + OPERAND_opnd_ae_sem_loads_stores_i128, + OPERAND_opnd_ae_sem_loads_stores_i64x2, + OPERAND_opnd_ae_sem_loads_stores_av1, + OPERAND_opnd_ae_sem_loads_stores_imm2, + OPERAND_opnd_ae_sem_loads_stores_i3, + OPERAND_opnd_ae_sem_rng_v0, + OPERAND_opnd_ae_sem_rng_v1, + OPERAND_opnd_ae_sem_reduction_sort_v, + OPERAND_opnd_ae_sem_reduction_sort_v0, + OPERAND_opnd_ae_sem_reduction_sort_ds, + OPERAND_opnd_ae_sem_multiply_d0, + OPERAND_opnd_ae_sem_multiply_d2, + OPERAND_opnd_ae_sem_multiply_q0, + OPERAND_opnd_ae_sem_multiply_q1, + OPERAND_opnd_ae_sem_dr_to_dr_immed_N, + OPERAND_opnd_ae_sem_dr_to_ar_ei, + OPERAND_opnd_ae_sem_dr_to_ar_eo, + OPERAND_opnd_ae_sem_multiply_acc_ep, + OPERAND_opnd_ae_sem_arithmetic_e, + OPERAND_opnd_ae_sem_arithmetic_ep, + OPERAND_opnd_ae_sem_arithmetic_ep1, + OPERAND_opnd_ae_sem_select_ss, + OPERAND_opnd_ae_sem_select_vr, + OPERAND_opnd_ae_sem_select_vs, + OPERAND_opnd_ae_sem_select_vt, + OPERAND_opnd_ae_sem_select_vu, + OPERAND_opnd_ae_sem_select_isel, + OPERAND_opnd_ae_sem_shift_e, + OPERAND_opnd_ae_sem_shift_i8, + OPERAND_opnd_ae_sem_multiply_d1, + OPERAND_opnd_ae_sem_multiply_d3, + OPERAND_opnd_ae_sem_dr_to_dr_imm, + OPERAND_opnd_ae_sem_rng_d, + OPERAND_opnd_ae_sem_sb_loads_stores_iba2, + OPERAND_opnd_ae_sem_dr_to_ar_ar_s, + OPERAND_opnd_AE_ARDECNORM16_ar_u, + OPERAND_opnd_ae_sem_rng_a, + OPERAND_opnd_ae_sem_rng_art, + OPERAND_opnd_ae_sem_rng_i2, + OPERAND_opnd_ae_sem_rng_imm2, + OPERAND_opnd_ae_sem_lb_db_ops_ar_u, + OPERAND_opnd_ae_sem_lb_db_ops_iba, + OPERAND_opnd_ae_sem_dr_to_ar_vr, + OPERAND_opnd_ae_sem_spmisc_brt, + OPERAND_opnd_ae_sem_spmisc_vr, + OPERAND_opnd_ae_sem_spmisc_vs, + OPERAND_opnd_ae_sem_dr_to_dr_arr, + OPERAND_opnd_ae_sem_dr_to_dr_bt, + OPERAND_opnd_ae_sem_sp32cvt_art, + OPERAND_opnd_ae_sem_sp32cvt_i_imm5, + OPERAND_opnd_ae_sem_sp32cvt_vr, + OPERAND_opnd_ae_sem_sp32cvt_vt, + OPERAND_opnd_ae_sem_sp32cvt_arr, + OPERAND_opnd_ae_sem_movfpstate_v, + OPERAND_opnd_ae_sem_fpmov_vr, + OPERAND_opnd_ae_sem_fpmov_vt, + OPERAND_opnd_ae_sem_fpmov_i_imm4, + OPERAND_opnd_ae_sem_fpmov_vs, + OPERAND_opnd_ae_sem_fpmov_vu, + OPERAND_opnd_ae_sem_spmisc_vsM, + OPERAND_opnd_ae_sem_spmisc_vtM, + OPERAND_opnd_ae_sem_spmisc_vt, + OPERAND_opnd_ae_sem_spaddsub_vr, + OPERAND_opnd_ae_sem_spaddsub_vs, + OPERAND_opnd_ae_sem_spaddsub_vt, + OPERAND_opnd_ae_sem_spaddsub_vu, + OPERAND_opnd_ae_sem_spfma_vr, + OPERAND_opnd_ae_sem_spfma_vs, + OPERAND_opnd_ae_sem_spfma_vt, + OPERAND_opnd_ae_sem_spfma_vp, + OPERAND_opnd_ae_sem_spfma_i_imm1, + OPERAND_opnd_ae_sem_spfma_i_imm3, + OPERAND_opnd_ae_sem_spaddsub_vp, + OPERAND_opnd_ae_sem_spaddsub_vq, + OPERAND_opnd_ae_sem_spfma_vu, + OPERAND_opnd_ae_sem_spfma_vq, + OPERAND_opnd_ae_sem_hprminmaxnum_vr, + OPERAND_opnd_ae_sem_hprminmaxnum_vt, + OPERAND_opnd_ae_sem_hpcmp_br4t, + OPERAND_opnd_ae_sem_hpcmp_vr, + OPERAND_opnd_ae_sem_hpcmp_vs, + OPERAND_opnd_ae_sem_hpcnv_art, + OPERAND_opnd_ae_sem_hpcnv_i_imm4, + OPERAND_opnd_ae_sem_hpcnv_vr, + OPERAND_opnd_ae_sem_hpcnv_arr, + OPERAND_opnd_ae_sem_hpcnv_vt, + OPERAND_opnd_ae_sem_hpcmp_vt, + OPERAND_opnd_ae_sem_hpcnv_vs, + OPERAND_opnd_ae_sem_hpfma_vr, + OPERAND_opnd_ae_sem_hpfma_vs, + OPERAND_opnd_ae_sem_hpfma_vt, + OPERAND_opnd_ae_sem_hpfma_vp, + OPERAND_opnd_ae_sem_hpfma_vu, + OPERAND_opnd_ae_sem_hpfma_vq, + OPERAND_opnd_ae_sem_mul_nn_c0, + OPERAND_opnd_ae_sem_mul_nn_c1, + OPERAND_opnd_ae_sem_mul_nn_c2, + OPERAND_opnd_ae_sem_mul_nn_c3, + OPERAND_opnd_ae_sem_mul_nn_q0, + OPERAND_opnd_ae_sem_mul_nn_q1, + OPERAND_opnd_ae_sem_mul_nn_v0, + OPERAND_opnd_ae_sem_mul_nn_v1, + OPERAND_opnd_ae_sem_mul_nn_q2, + OPERAND_opnd_ae_sem_mul_nn_q3, + OPERAND_opnd_ae_sem_mul_nn_v2, + OPERAND_opnd_ae_sem_mul_nn_v3, + OPERAND_bbi, + OPERAND_sae, + OPERAND_sas, + OPERAND_sargt, + OPERAND_s, + OPERAND_bitindex, + OPERAND_t, + OPERAND_bbi4, + OPERAND_imm12, + OPERAND_imm8, + OPERAND_s8, + OPERAND_imms8, + OPERAND_imm12b, + OPERAND_imm16, + OPERAND_m, + OPERAND_n, + OPERAND_offset, + OPERAND_op0, + OPERAND_op1, + OPERAND_op2, + OPERAND_r, + OPERAND_r_disp, + OPERAND_r_3, + OPERAND_sa4, + OPERAND_sae4, + OPERAND_sal, + OPERAND_sas4, + OPERAND_sr, + OPERAND_st, + OPERAND_thi3, + OPERAND_imm4, + OPERAND_mn, + OPERAND_i, + OPERAND_imm6lo, + OPERAND_imm6hi, + OPERAND_imm7lo, + OPERAND_imm7hi, + OPERAND_z, + OPERAND_imm6, + OPERAND_imm7, + OPERAND_t2, + OPERAND_s2, + OPERAND_r2, + OPERAND_t4, + OPERAND_s4, + OPERAND_r4, + OPERAND_t8, + OPERAND_r8, + OPERAND_xt_wbr15_imm, + OPERAND_xt_wloop_imm, + OPERAND_ae_fld_Inst16b_12, + OPERAND_ae_fld_Inst16b_15_13, + OPERAND_fld_ae_sem_arithmetic_art, + OPERAND_fld_ae_sem_arithmetic_ds, + OPERAND_fld_ae_sem_arithmetic_v, + OPERAND_fld_ae_sem_arithmetic_v0, + OPERAND_fld_ae_sem_arithmetic_v1, + OPERAND_fld_ae_sem_arithmetic_va, + OPERAND_fld_ae_sem_arithmetic_vs, + OPERAND_fld_ae_sem_dr_to_ar_a, + OPERAND_fld_ae_sem_dr_to_ar_ab, + OPERAND_fld_ae_sem_dr_to_ar_ai, + OPERAND_fld_ae_sem_dr_to_ar_aoe, + OPERAND_fld_ae_sem_dr_to_ar_d, + OPERAND_fld_ae_sem_dr_to_ar_d0, + OPERAND_fld_ae_sem_dr_to_ar_d1, + OPERAND_fld_ae_sem_dr_to_ar_imm8, + OPERAND_fld_ae_sem_dr_to_ar_v0, + OPERAND_fld_ae_sem_dr_to_ar_vr, + OPERAND_fld_ae_sem_dr_to_dr_arr, + OPERAND_fld_ae_sem_dr_to_dr_bt, + OPERAND_fld_ae_sem_dr_to_dr_ds, + OPERAND_fld_ae_sem_dr_to_dr_imm2, + OPERAND_fld_ae_sem_dr_to_dr_immed, + OPERAND_fld_ae_sem_dr_to_dr_movi_imm, + OPERAND_fld_ae_sem_dr_to_dr_v, + OPERAND_fld_ae_sem_dr_to_dr_v0, + OPERAND_fld_ae_sem_dr_to_dr_v1, + OPERAND_fld_ae_sem_hpcmp_br4t, + OPERAND_fld_ae_sem_hpcmp_vr, + OPERAND_fld_ae_sem_hpcmp_vs, + OPERAND_fld_ae_sem_hpcnv_arr, + OPERAND_fld_ae_sem_hpcnv_art, + OPERAND_fld_ae_sem_hpcnv_i_imm4, + OPERAND_fld_ae_sem_hpcnv_vr, + OPERAND_fld_ae_sem_hpcnv_vt, + OPERAND_fld_ae_sem_hprminmaxnum_vr, + OPERAND_fld_ae_sem_hprminmaxnum_vt, + OPERAND_fld_ae_sem_lb_ops_iba, + OPERAND_fld_ae_sem_loads_stores_a, + OPERAND_fld_ae_sem_loads_stores_a_0, + OPERAND_fld_ae_sem_loads_stores_av, + OPERAND_fld_ae_sem_loads_stores_av1, + OPERAND_fld_ae_sem_loads_stores_end, + OPERAND_fld_ae_sem_loads_stores_i128, + OPERAND_fld_ae_sem_loads_stores_i16, + OPERAND_fld_ae_sem_loads_stores_i3, + OPERAND_fld_ae_sem_loads_stores_i32, + OPERAND_fld_ae_sem_loads_stores_i32pos, + OPERAND_fld_ae_sem_loads_stores_i64, + OPERAND_fld_ae_sem_loads_stores_i64half, + OPERAND_fld_ae_sem_loads_stores_i64neg, + OPERAND_fld_ae_sem_loads_stores_i64pos, + OPERAND_fld_ae_sem_loads_stores_i64x2, + OPERAND_fld_ae_sem_loads_stores_i8, + OPERAND_fld_ae_sem_loads_stores_imm2, + OPERAND_fld_ae_sem_loads_stores_su, + OPERAND_fld_ae_sem_loads_stores_uu, + OPERAND_fld_ae_sem_loads_stores_v, + OPERAND_fld_ae_sem_loads_stores_v1, + OPERAND_fld_ae_sem_loads_stores_vu, + OPERAND_fld_ae_sem_loads_stores_x, + OPERAND_fld_ae_sem_pks_d, + OPERAND_fld_ae_sem_pks_pos, + OPERAND_fld_ae_sem_pks_s, + OPERAND_fld_ae_sem_rng_v0, + OPERAND_fld_ae_sem_rng_v1, + OPERAND_fld_ae_sem_sb_loads_stores_iba, + OPERAND_fld_ae_sem_shift_a, + OPERAND_fld_ae_sem_shift_a0, + OPERAND_fld_ae_sem_shift_d, + OPERAND_fld_ae_sem_shift_d0, + OPERAND_fld_ae_sem_shift_d1, + OPERAND_fld_ae_sem_shift_da, + OPERAND_fld_ae_sem_shift_i16, + OPERAND_fld_ae_sem_shift_i32, + OPERAND_fld_ae_sem_shift_i64, + OPERAND_fld_ae_sem_shift_imm32, + OPERAND_fld_ae_sem_shift_imm8, + OPERAND_fld_ae_sem_shift_sd, + OPERAND_fld_ae_sem_sp32cvt_arr, + OPERAND_fld_ae_sem_sp32cvt_art, + OPERAND_fld_ae_sem_sp32cvt_i_imm5, + OPERAND_fld_ae_sem_sp32cvt_vr, + OPERAND_fld_ae_sem_sp32cvt_vt, + OPERAND_fld_ae_sem_spmisc_brt, + OPERAND_fld_ae_sem_spmisc_vr, + OPERAND_fld_ae_sem_spmisc_vs, + OPERAND_fld_ae_slot0_11_10, + OPERAND_fld_ae_slot0_11_11, + OPERAND_fld_ae_slot0_11_8, + OPERAND_fld_ae_slot0_11_9, + OPERAND_fld_ae_slot0_12_0, + OPERAND_fld_ae_slot0_12_10, + OPERAND_fld_ae_slot0_12_12, + OPERAND_fld_ae_slot0_12_2, + OPERAND_fld_ae_slot0_12_6, + OPERAND_fld_ae_slot0_12_8, + OPERAND_fld_ae_slot0_12_9, + OPERAND_fld_ae_slot0_14_12, + OPERAND_fld_ae_slot0_14_13, + OPERAND_fld_ae_slot0_17_10, + OPERAND_fld_ae_slot0_17_12, + OPERAND_fld_ae_slot0_17_13, + OPERAND_fld_ae_slot0_17_14, + OPERAND_fld_ae_slot0_17_15, + OPERAND_fld_ae_slot0_17_16, + OPERAND_fld_ae_slot0_17_17, + OPERAND_fld_ae_slot0_17_8, + OPERAND_fld_ae_slot0_18_13, + OPERAND_fld_ae_slot0_18_15, + OPERAND_fld_ae_slot0_18_16, + OPERAND_fld_ae_slot0_18_8, + OPERAND_fld_ae_slot0_19_12, + OPERAND_fld_ae_slot0_19_15, + OPERAND_fld_ae_slot0_19_19, + OPERAND_fld_ae_slot0_19_8, + OPERAND_fld_ae_slot0_1_0, + OPERAND_fld_ae_slot0_1_1, + OPERAND_fld_ae_slot0_20_16, + OPERAND_fld_ae_slot0_20_20, + OPERAND_fld_ae_slot0_23_15, + OPERAND_fld_ae_slot0_23_17, + OPERAND_fld_ae_slot0_23_19, + OPERAND_fld_ae_slot0_23_22, + OPERAND_fld_ae_slot0_28_10, + OPERAND_fld_ae_slot0_28_12, + OPERAND_fld_ae_slot0_28_14, + OPERAND_fld_ae_slot0_28_15, + OPERAND_fld_ae_slot0_28_16, + OPERAND_fld_ae_slot0_28_17, + OPERAND_fld_ae_slot0_28_19, + OPERAND_fld_ae_slot0_28_21, + OPERAND_fld_ae_slot0_28_22, + OPERAND_fld_ae_slot0_28_24, + OPERAND_fld_ae_slot0_28_26, + OPERAND_fld_ae_slot0_28_27, + OPERAND_fld_ae_slot0_28_4, + OPERAND_fld_ae_slot0_28_8, + OPERAND_fld_ae_slot0_3_0, + OPERAND_fld_ae_slot0_3_1, + OPERAND_fld_ae_slot0_3_2, + OPERAND_fld_ae_slot0_3_3, + OPERAND_fld_ae_slot0_4_0, + OPERAND_fld_ae_slot0_4_4, + OPERAND_fld_ae_slot0_5_0, + OPERAND_fld_ae_slot0_5_4, + OPERAND_fld_ae_slot0_7_0, + OPERAND_fld_ae_slot0_7_2, + OPERAND_fld_ae_slot0_7_3, + OPERAND_fld_ae_slot0_7_4, + OPERAND_fld_ae_slot0_8_8, + OPERAND_fld_ae_slot0_9_4, + OPERAND_fld_ae_slot0_9_8, + OPERAND_fld_ae_slot0_9_9, + OPERAND_fld_ae_slot1_0_0, + OPERAND_fld_ae_slot1_12_8, + OPERAND_fld_ae_slot1_17_13, + OPERAND_fld_ae_slot1_17_17, + OPERAND_fld_ae_slot1_17_8, + OPERAND_fld_ae_slot1_25_1, + OPERAND_fld_ae_slot1_25_12, + OPERAND_fld_ae_slot1_25_13, + OPERAND_fld_ae_slot1_25_16, + OPERAND_fld_ae_slot1_25_17, + OPERAND_fld_ae_slot1_25_18, + OPERAND_fld_ae_slot1_25_20, + OPERAND_fld_ae_slot1_25_22, + OPERAND_fld_ae_slot1_25_23, + OPERAND_fld_ae_slot1_25_8, + OPERAND_fld_ae_slot1_25_9, + OPERAND_fld_ae_slot1_3_0, + OPERAND_fld_ae_slot1_3_2, + OPERAND_fld_ae_slot1_3_3, + OPERAND_fld_ae_slot1_7_4, + OPERAND_fld_ae_sem_arithmetic_e, + OPERAND_fld_ae_sem_arithmetic_ep, + OPERAND_fld_ae_sem_arithmetic_ep1, + OPERAND_fld_ae_sem_dr_to_ar_ei, + OPERAND_fld_ae_sem_dr_to_ar_eo, + OPERAND_fld_ae_sem_dr_to_dr_immed_N, + OPERAND_fld_ae_sem_fpmov_i_imm4, + OPERAND_fld_ae_sem_fpmov_vr, + OPERAND_fld_ae_sem_fpmov_vs, + OPERAND_fld_ae_sem_fpmov_vt, + OPERAND_fld_ae_sem_fpmov_vu, + OPERAND_fld_ae_sem_hpcmp_vt, + OPERAND_fld_ae_sem_hpcnv_vs, + OPERAND_fld_ae_sem_hpfma_vr, + OPERAND_fld_ae_sem_hpfma_vs, + OPERAND_fld_ae_sem_hpfma_vt, + OPERAND_fld_ae_sem_movfpstate_v, + OPERAND_fld_ae_sem_multiply_acc_ep, + OPERAND_fld_ae_sem_multiply_d0, + OPERAND_fld_ae_sem_multiply_d2, + OPERAND_fld_ae_sem_multiply_q0, + OPERAND_fld_ae_sem_multiply_q1, + OPERAND_fld_ae_sem_reduction_sort_ds, + OPERAND_fld_ae_sem_reduction_sort_v, + OPERAND_fld_ae_sem_reduction_sort_v0, + OPERAND_fld_ae_sem_select_isel, + OPERAND_fld_ae_sem_select_ss, + OPERAND_fld_ae_sem_select_vr, + OPERAND_fld_ae_sem_select_vs, + OPERAND_fld_ae_sem_select_vt, + OPERAND_fld_ae_sem_select_vu, + OPERAND_fld_ae_sem_spaddsub_vr, + OPERAND_fld_ae_sem_spaddsub_vs, + OPERAND_fld_ae_sem_spaddsub_vt, + OPERAND_fld_ae_sem_spaddsub_vu, + OPERAND_fld_ae_sem_spfma_i_imm1, + OPERAND_fld_ae_sem_spfma_i_imm3, + OPERAND_fld_ae_sem_spfma_vp, + OPERAND_fld_ae_sem_spfma_vr, + OPERAND_fld_ae_sem_spfma_vs, + OPERAND_fld_ae_sem_spfma_vt, + OPERAND_fld_ae_sem_spmisc_vsM, + OPERAND_fld_ae_sem_spmisc_vt, + OPERAND_fld_ae_sem_spmisc_vtM, + OPERAND_fld_ae_slot2_14_0, + OPERAND_fld_ae_slot2_14_10, + OPERAND_fld_ae_slot2_14_14, + OPERAND_fld_ae_slot2_14_5, + OPERAND_fld_ae_slot2_16_15, + OPERAND_fld_ae_slot2_19_15, + OPERAND_fld_ae_slot2_28_15, + OPERAND_fld_ae_slot2_28_17, + OPERAND_fld_ae_slot2_28_19, + OPERAND_fld_ae_slot2_28_20, + OPERAND_fld_ae_slot2_28_25, + OPERAND_fld_ae_slot2_28_4, + OPERAND_fld_ae_slot2_28_5, + OPERAND_fld_ae_slot2_3_0, + OPERAND_fld_ae_slot2_9_0, + OPERAND_fld_ae_slot2_9_1, + OPERAND_fld_ae_slot2_9_2, + OPERAND_fld_ae_slot2_9_5, + OPERAND_fld_ae_slot2_9_6, + OPERAND_fld_ae_slot2_9_7, + OPERAND_fld_ae_slot2_9_8, + OPERAND_fld_ae_sem_dr_to_dr_imm, + OPERAND_fld_ae_sem_multiply_d1, + OPERAND_fld_ae_sem_multiply_d3, + OPERAND_fld_ae_sem_rng_d, + OPERAND_fld_ae_sem_shift_e, + OPERAND_fld_ae_sem_shift_i8, + OPERAND_fld_ae_slot3_11_0, + OPERAND_fld_ae_slot3_14_0, + OPERAND_fld_ae_slot3_14_10, + OPERAND_fld_ae_slot3_14_12, + OPERAND_fld_ae_slot3_14_13, + OPERAND_fld_ae_slot3_16_13, + OPERAND_fld_ae_slot3_19_0, + OPERAND_fld_ae_slot3_19_10, + OPERAND_fld_ae_slot3_19_15, + OPERAND_fld_ae_slot3_19_17, + OPERAND_fld_ae_slot3_19_18, + OPERAND_fld_ae_slot3_19_19, + OPERAND_fld_ae_slot3_24_10, + OPERAND_fld_ae_slot3_24_19, + OPERAND_fld_ae_slot3_24_20, + OPERAND_fld_ae_slot3_36_12, + OPERAND_fld_ae_slot3_36_16, + OPERAND_fld_ae_slot3_36_19, + OPERAND_fld_ae_slot3_36_20, + OPERAND_fld_ae_slot3_36_22, + OPERAND_fld_ae_slot3_36_25, + OPERAND_fld_ae_slot3_36_30, + OPERAND_fld_ae_slot3_4_0, + OPERAND_fld_ae_slot3_9_0, + OPERAND_fld_ae_slot3_9_1, + OPERAND_fld_ae_slot3_9_3, + OPERAND_fld_ae_slot3_9_5, + OPERAND_fld_ae2_slot0_0_0, + OPERAND_fld_ae2_slot0_11_4, + OPERAND_fld_ae2_slot0_11_8, + OPERAND_fld_ae2_slot0_11_9, + OPERAND_fld_ae2_slot0_12_0, + OPERAND_fld_ae2_slot0_12_2, + OPERAND_fld_ae2_slot0_12_4, + OPERAND_fld_ae2_slot0_12_8, + OPERAND_fld_ae2_slot0_14_13, + OPERAND_fld_ae2_slot0_14_8, + OPERAND_fld_ae2_slot0_15_0, + OPERAND_fld_ae2_slot0_15_12, + OPERAND_fld_ae2_slot0_15_13, + OPERAND_fld_ae2_slot0_15_15, + OPERAND_fld_ae2_slot0_15_4, + OPERAND_fld_ae2_slot0_15_8, + OPERAND_fld_ae2_slot0_17_13, + OPERAND_fld_ae2_slot0_17_17, + OPERAND_fld_ae2_slot0_18_15, + OPERAND_fld_ae2_slot0_18_17, + OPERAND_fld_ae2_slot0_18_18, + OPERAND_fld_ae2_slot0_1_0, + OPERAND_fld_ae2_slot0_23_18, + OPERAND_fld_ae2_slot0_23_19, + OPERAND_fld_ae2_slot0_3_0, + OPERAND_fld_ae2_slot0_40_16, + OPERAND_fld_ae2_slot0_40_17, + OPERAND_fld_ae2_slot0_40_18, + OPERAND_fld_ae2_slot0_40_19, + OPERAND_fld_ae2_slot0_40_21, + OPERAND_fld_ae2_slot0_40_23, + OPERAND_fld_ae2_slot0_40_24, + OPERAND_fld_ae2_slot0_40_25, + OPERAND_fld_ae2_slot0_40_26, + OPERAND_fld_ae2_slot0_40_27, + OPERAND_fld_ae2_slot0_7_0, + OPERAND_fld_ae2_slot0_7_4, + OPERAND_fld_ae2_slot0_7_6, + OPERAND_fld_ae2_slot0_7_7, + OPERAND_fld_ae2_slot0_8_8, + OPERAND_fld_ae2_slot0_9_8, + OPERAND_fld_ae2_slot1_0_0, + OPERAND_fld_ae2_slot1_11_0, + OPERAND_fld_ae2_slot1_11_10, + OPERAND_fld_ae2_slot1_11_8, + OPERAND_fld_ae2_slot1_14_10, + OPERAND_fld_ae2_slot1_14_11, + OPERAND_fld_ae2_slot1_14_12, + OPERAND_fld_ae2_slot1_14_14, + OPERAND_fld_ae2_slot1_14_8, + OPERAND_fld_ae2_slot1_36_12, + OPERAND_fld_ae2_slot1_36_14, + OPERAND_fld_ae2_slot1_36_15, + OPERAND_fld_ae2_slot1_36_16, + OPERAND_fld_ae2_slot1_36_17, + OPERAND_fld_ae2_slot1_36_18, + OPERAND_fld_ae2_slot1_36_20, + OPERAND_fld_ae2_slot1_36_22, + OPERAND_fld_ae2_slot1_36_23, + OPERAND_fld_ae2_slot1_3_0, + OPERAND_fld_ae2_slot1_3_1, + OPERAND_fld_ae2_slot1_3_2, + OPERAND_fld_ae2_slot1_3_3, + OPERAND_fld_ae2_slot1_7_4, + OPERAND_fld_ae2_slot1_9_8, + OPERAND_fld_ae2_slot1_9_9, + OPERAND_fld_ae2_slot2_14_10, + OPERAND_fld_ae2_slot2_17_0, + OPERAND_fld_ae2_slot2_17_10, + OPERAND_fld_ae2_slot2_17_15, + OPERAND_fld_ae2_slot2_17_17, + OPERAND_fld_ae2_slot2_19_10, + OPERAND_fld_ae2_slot2_19_15, + OPERAND_fld_ae2_slot2_19_18, + OPERAND_fld_ae2_slot2_19_9, + OPERAND_fld_ae2_slot2_24_10, + OPERAND_fld_ae2_slot2_24_15, + OPERAND_fld_ae2_slot2_24_20, + OPERAND_fld_ae2_slot2_24_5, + OPERAND_fld_ae2_slot2_24_9, + OPERAND_fld_ae2_slot2_42_18, + OPERAND_fld_ae2_slot2_42_20, + OPERAND_fld_ae2_slot2_42_25, + OPERAND_fld_ae2_slot2_42_26, + OPERAND_fld_ae2_slot2_42_28, + OPERAND_fld_ae2_slot2_42_30, + OPERAND_fld_ae2_slot2_4_0, + OPERAND_fld_ae2_slot2_9_5, + OPERAND_fld_ae_sem_spaddsub_vp, + OPERAND_fld_ae_sem_spaddsub_vq, + OPERAND_fld_ae3_slot0_11_11, + OPERAND_fld_ae3_slot0_11_4, + OPERAND_fld_ae3_slot0_11_8, + OPERAND_fld_ae3_slot0_12_12, + OPERAND_fld_ae3_slot0_12_8, + OPERAND_fld_ae3_slot0_13_13, + OPERAND_fld_ae3_slot0_13_8, + OPERAND_fld_ae3_slot0_1_0, + OPERAND_fld_ae3_slot0_32_11, + OPERAND_fld_ae3_slot0_32_12, + OPERAND_fld_ae3_slot0_32_13, + OPERAND_fld_ae3_slot0_32_14, + OPERAND_fld_ae3_slot0_32_15, + OPERAND_fld_ae3_slot0_32_16, + OPERAND_fld_ae3_slot0_32_17, + OPERAND_fld_ae3_slot0_32_18, + OPERAND_fld_ae3_slot0_32_20, + OPERAND_fld_ae3_slot0_32_27, + OPERAND_fld_ae3_slot0_32_8, + OPERAND_fld_ae3_slot0_3_0, + OPERAND_fld_ae3_slot0_3_2, + OPERAND_fld_ae3_slot0_3_3, + OPERAND_fld_ae3_slot0_4_0, + OPERAND_fld_ae3_slot0_4_4, + OPERAND_fld_ae3_slot0_5_0, + OPERAND_fld_ae3_slot0_5_4, + OPERAND_fld_ae3_slot0_7_0, + OPERAND_fld_ae3_slot0_7_2, + OPERAND_fld_ae3_slot0_7_4, + OPERAND_fld_ae3_slot0_7_6, + OPERAND_fld_ae3_slot0_8_8, + OPERAND_fld_ae3_slot0_9_4, + OPERAND_fld_ae3_slot0_9_8, + OPERAND_fld_ae_sem_dr_to_ar_ar_s, + OPERAND_fld_ae_sem_sb_loads_stores_iba2, + OPERAND_fld_ae3_slot1_23_0, + OPERAND_fld_ae3_slot1_23_11, + OPERAND_fld_ae3_slot1_23_12, + OPERAND_fld_ae3_slot1_23_13, + OPERAND_fld_ae3_slot1_23_15, + OPERAND_fld_ae3_slot1_23_16, + OPERAND_fld_ae3_slot1_23_17, + OPERAND_fld_ae3_slot1_23_19, + OPERAND_fld_ae3_slot1_23_6, + OPERAND_fld_ae3_slot1_23_8, + OPERAND_fld_ae3_slot1_23_9, + OPERAND_fld_ae3_slot1_3_0, + OPERAND_fld_ae3_slot1_3_1, + OPERAND_fld_ae3_slot1_3_2, + OPERAND_fld_ae3_slot1_3_3, + OPERAND_fld_ae3_slot1_7_4, + OPERAND_fld_ae3_slot1_9_8, + OPERAND_fld_AE_ARDECNORM16_ar_u, + OPERAND_fld_ae5_slot0_11_10, + OPERAND_fld_ae5_slot0_11_4, + OPERAND_fld_ae5_slot0_11_8, + OPERAND_fld_ae5_slot0_11_9, + OPERAND_fld_ae5_slot0_12_10, + OPERAND_fld_ae5_slot0_12_4, + OPERAND_fld_ae5_slot0_12_6, + OPERAND_fld_ae5_slot0_12_8, + OPERAND_fld_ae5_slot0_12_9, + OPERAND_fld_ae5_slot0_1_0, + OPERAND_fld_ae5_slot0_1_1, + OPERAND_fld_ae5_slot0_29_12, + OPERAND_fld_ae5_slot0_29_13, + OPERAND_fld_ae5_slot0_29_15, + OPERAND_fld_ae5_slot0_29_16, + OPERAND_fld_ae5_slot0_29_17, + OPERAND_fld_ae5_slot0_29_18, + OPERAND_fld_ae5_slot0_29_19, + OPERAND_fld_ae5_slot0_29_20, + OPERAND_fld_ae5_slot0_29_27, + OPERAND_fld_ae5_slot0_29_5, + OPERAND_fld_ae5_slot0_29_6, + OPERAND_fld_ae5_slot0_29_8, + OPERAND_fld_ae5_slot0_2_0, + OPERAND_fld_ae5_slot0_3_0, + OPERAND_fld_ae5_slot0_3_2, + OPERAND_fld_ae5_slot0_4_0, + OPERAND_fld_ae5_slot0_4_4, + OPERAND_fld_ae5_slot0_7_0, + OPERAND_fld_ae5_slot0_7_4, + OPERAND_fld_ae5_slot0_7_7, + OPERAND_fld_ae5_slot0_8_8, + OPERAND_fld_ae_sem_lb_db_ops_ar_u, + OPERAND_fld_ae_sem_lb_db_ops_iba, + OPERAND_fld_ae_sem_rng_a, + OPERAND_fld_ae_sem_rng_art, + OPERAND_fld_ae_sem_rng_i2, + OPERAND_fld_ae_sem_rng_imm2, + OPERAND_fld_ae5_slot1_1_0, + OPERAND_fld_ae5_slot2_14_10, + OPERAND_fld_ae5_slot2_14_14, + OPERAND_fld_ae5_slot2_14_5, + OPERAND_fld_ae5_slot2_24_0, + OPERAND_fld_ae5_slot2_24_15, + OPERAND_fld_ae5_slot2_24_17, + OPERAND_fld_ae5_slot2_24_20, + OPERAND_fld_ae5_slot2_4_0, + OPERAND_fld_ae5_slot2_9_0, + OPERAND_fld_ae5_slot2_9_5, + OPERAND_fld_ae5_slot2_9_7, + OPERAND_fld_ae6_slot0_10_10, + OPERAND_fld_ae6_slot0_15_15, + OPERAND_fld_ae6_slot0_29_10, + OPERAND_fld_ae6_slot0_29_13, + OPERAND_fld_ae6_slot0_29_14, + OPERAND_fld_ae6_slot0_29_15, + OPERAND_fld_ae6_slot0_29_18, + OPERAND_fld_ae6_slot0_29_20, + OPERAND_fld_ae6_slot0_29_5, + OPERAND_fld_ae6_slot0_4_0, + OPERAND_fld_ae6_slot0_4_4, + OPERAND_fld_ae6_slot0_7_4, + OPERAND_fld_ae6_slot0_7_7, + OPERAND_fld_ae6_slot0_9_8, + OPERAND_fld_ae6_slot0_9_9, + OPERAND_fld_ae6_slot1_14_14, + OPERAND_fld_ae6_slot1_27_12, + OPERAND_fld_ae6_slot1_27_15, + OPERAND_fld_ae6_slot1_27_20, + OPERAND_fld_ae6_slot1_27_21, + OPERAND_fld_ae6_slot1_27_3, + OPERAND_fld_ae6_slot1_27_6, + OPERAND_fld_ae6_slot1_2_0, + OPERAND_fld_ae6_slot1_9_5, + OPERAND_fld_ae6_slot1_9_6, + OPERAND_fld_ae6_slot1_9_7, + OPERAND_fld_ae6_slot1_9_8, + OPERAND_fld_ae6_slot1_9_9, + OPERAND_fld_ae6_slot2_10_10, + OPERAND_fld_ae6_slot2_11_10, + OPERAND_fld_ae6_slot2_24_0, + OPERAND_fld_ae6_slot2_24_10, + OPERAND_fld_ae6_slot2_24_14, + OPERAND_fld_ae6_slot2_24_15, + OPERAND_fld_ae6_slot2_24_20, + OPERAND_fld_ae6_slot2_4_2, + OPERAND_fld_ae6_slot2_9_5, + OPERAND_fld_ae6_slot3_10_10, + OPERAND_fld_ae6_slot3_12_0, + OPERAND_fld_ae6_slot3_14_0, + OPERAND_fld_ae6_slot3_14_10, + OPERAND_fld_ae6_slot3_14_13, + OPERAND_fld_ae6_slot3_14_5, + OPERAND_fld_ae6_slot3_24_20, + OPERAND_fld_ae6_slot3_37_13, + OPERAND_fld_ae6_slot3_37_15, + OPERAND_fld_ae6_slot3_37_20, + OPERAND_fld_ae6_slot3_37_30, + OPERAND_fld_ae6_slot3_9_5, + OPERAND_fld_ae7_slot0_12_6, + OPERAND_fld_ae7_slot0_23_0, + OPERAND_fld_ae7_slot0_23_13, + OPERAND_fld_ae7_slot0_23_17, + OPERAND_fld_ae7_slot0_23_18, + OPERAND_fld_ae7_slot0_23_6, + OPERAND_fld_ae7_slot0_7_4, + OPERAND_fld_ae7_slot0_7_6, + OPERAND_fld_ae7_slot0_7_7, + OPERAND_fld_ae7_slot1_12_6, + OPERAND_fld_ae7_slot1_23_0, + OPERAND_fld_ae7_slot1_23_13, + OPERAND_fld_ae7_slot1_23_17, + OPERAND_fld_ae7_slot1_23_18, + OPERAND_fld_ae7_slot1_23_6, + OPERAND_fld_ae7_slot1_7_4, + OPERAND_fld_ae7_slot1_7_6, + OPERAND_fld_ae7_slot1_7_7, + OPERAND_fld_ae7_slot2_11_0, + OPERAND_fld_ae7_slot2_14_10, + OPERAND_fld_ae7_slot2_14_5, + OPERAND_fld_ae7_slot2_36_12, + OPERAND_fld_ae7_slot2_36_15, + OPERAND_fld_ae7_slot2_36_20, + OPERAND_fld_ae7_slot2_36_25, + OPERAND_fld_ae7_slot2_36_30, + OPERAND_fld_ae7_slot2_9_5, + OPERAND_fld_ae7_slot3_10_0, + OPERAND_fld_ae7_slot3_14_10, + OPERAND_fld_ae7_slot3_14_5, + OPERAND_fld_ae7_slot3_24_10, + OPERAND_fld_ae7_slot3_35_11, + OPERAND_fld_ae7_slot3_35_20, + OPERAND_fld_ae7_slot3_35_25, + OPERAND_fld_ae7_slot3_35_30, + OPERAND_fld_ae7_slot3_4_0, + OPERAND_fld_ae7_slot3_9_5, + OPERAND_fld_ae8_slot0_13_12, + OPERAND_fld_ae8_slot0_13_13, + OPERAND_fld_ae8_slot0_13_4, + OPERAND_fld_ae8_slot0_13_9, + OPERAND_fld_ae8_slot0_17_4, + OPERAND_fld_ae8_slot0_17_8, + OPERAND_fld_ae8_slot0_31_12, + OPERAND_fld_ae8_slot0_31_15, + OPERAND_fld_ae8_slot0_31_18, + OPERAND_fld_ae8_slot0_31_19, + OPERAND_fld_ae8_slot0_31_20, + OPERAND_fld_ae8_slot0_31_21, + OPERAND_fld_ae8_slot0_31_22, + OPERAND_fld_ae8_slot0_31_23, + OPERAND_fld_ae8_slot0_31_7, + OPERAND_fld_ae8_slot0_31_8, + OPERAND_fld_ae8_slot0_31_9, + OPERAND_fld_ae8_slot0_3_0, + OPERAND_fld_ae8_slot0_6_0, + OPERAND_fld_ae8_slot0_7_4, + OPERAND_fld_ae8_slot0_7_5, + OPERAND_fld_ae8_slot0_7_7, + OPERAND_fld_ae8_slot0_8_0, + OPERAND_fld_ae8_slot1_17_13, + OPERAND_fld_ae8_slot1_17_14, + OPERAND_fld_ae8_slot1_17_15, + OPERAND_fld_ae8_slot1_17_8, + OPERAND_fld_ae8_slot1_29_12, + OPERAND_fld_ae8_slot1_29_13, + OPERAND_fld_ae8_slot1_29_18, + OPERAND_fld_ae8_slot1_29_20, + OPERAND_fld_ae8_slot1_29_22, + OPERAND_fld_ae8_slot1_29_23, + OPERAND_fld_ae8_slot1_29_5, + OPERAND_fld_ae8_slot1_29_8, + OPERAND_fld_ae8_slot1_29_9, + OPERAND_fld_ae8_slot1_3_0, + OPERAND_fld_ae8_slot1_3_3, + OPERAND_fld_ae8_slot1_4_0, + OPERAND_fld_ae8_slot1_7_4, + OPERAND_fld_ae8_slot2_19_10, + OPERAND_fld_ae8_slot2_19_15, + OPERAND_fld_ae8_slot2_33_15, + OPERAND_fld_ae8_slot2_33_25, + OPERAND_fld_ae8_slot2_33_9, + OPERAND_fld_ae8_slot2_34_30, + OPERAND_fld_ae8_slot2_39_35, + OPERAND_fld_ae8_slot2_44_35, + OPERAND_fld_ae8_slot2_58_34, + OPERAND_fld_ae8_slot2_58_35, + OPERAND_fld_ae8_slot2_58_40, + OPERAND_fld_ae8_slot2_58_50, + OPERAND_fld_ae8_slot2_8_0, + OPERAND_fld_ae8_slot2_9_0, + OPERAND_fld_ae_sem_mul_nn_c0, + OPERAND_fld_ae_sem_mul_nn_c1, + OPERAND_fld_ae_sem_mul_nn_c2, + OPERAND_fld_ae_sem_mul_nn_c3, + OPERAND_fld_ae_sem_mul_nn_q0, + OPERAND_fld_ae_sem_mul_nn_q1, + OPERAND_fld_ae_sem_mul_nn_q2, + OPERAND_fld_ae_sem_mul_nn_q3, + OPERAND_fld_ae_sem_mul_nn_v0, + OPERAND_fld_ae_sem_mul_nn_v1, + OPERAND_fld_ae_sem_mul_nn_v2, + OPERAND_fld_ae_sem_mul_nn_v3, + OPERAND_fld_ae9_slot0_0_0, + OPERAND_fld_ae9_slot0_12_12, + OPERAND_fld_ae9_slot0_12_5, + OPERAND_fld_ae9_slot0_12_8, + OPERAND_fld_ae9_slot0_17_13, + OPERAND_fld_ae9_slot0_17_4, + OPERAND_fld_ae9_slot0_17_8, + OPERAND_fld_ae9_slot0_27_10, + OPERAND_fld_ae9_slot0_27_12, + OPERAND_fld_ae9_slot0_27_13, + OPERAND_fld_ae9_slot0_27_16, + OPERAND_fld_ae9_slot0_27_17, + OPERAND_fld_ae9_slot0_27_18, + OPERAND_fld_ae9_slot0_27_19, + OPERAND_fld_ae9_slot0_27_20, + OPERAND_fld_ae9_slot0_27_22, + OPERAND_fld_ae9_slot0_27_23, + OPERAND_fld_ae9_slot0_27_3, + OPERAND_fld_ae9_slot0_27_8, + OPERAND_fld_ae9_slot0_2_0, + OPERAND_fld_ae9_slot0_3_0, + OPERAND_fld_ae9_slot0_7_0, + OPERAND_fld_ae9_slot0_7_4, + OPERAND_fld_ae9_slot0_7_5, + OPERAND_fld_ae9_slot0_7_6, + OPERAND_fld_ae9_slot0_7_7, + OPERAND_fld_ae9_slot0_8_4, + OPERAND_fld_ae9_slot0_8_5, + OPERAND_fld_ae9_slot0_9_5, + OPERAND_fld_ae9_slot1_17_13, + OPERAND_fld_ae9_slot1_17_8, + OPERAND_fld_ae9_slot1_1_0, + OPERAND_fld_ae9_slot1_26_12, + OPERAND_fld_ae9_slot1_26_13, + OPERAND_fld_ae9_slot1_26_16, + OPERAND_fld_ae9_slot1_26_17, + OPERAND_fld_ae9_slot1_26_18, + OPERAND_fld_ae9_slot1_26_2, + OPERAND_fld_ae9_slot1_26_20, + OPERAND_fld_ae9_slot1_26_22, + OPERAND_fld_ae9_slot1_26_23, + OPERAND_fld_ae9_slot1_26_8, + OPERAND_fld_ae9_slot1_26_9, + OPERAND_fld_ae9_slot1_3_0, + OPERAND_fld_ae9_slot1_3_2, + OPERAND_fld_ae9_slot1_3_3, + OPERAND_fld_ae9_slot1_7_4, + OPERAND_fld_ae9_slot2_24_14, + OPERAND_fld_ae9_slot2_24_15, + OPERAND_fld_ae9_slot2_24_20, + OPERAND_fld_ae9_slot2_33_14, + OPERAND_fld_ae9_slot2_33_15, + OPERAND_fld_ae9_slot2_33_20, + OPERAND_fld_ae9_slot2_33_25, + OPERAND_fld_ae9_slot2_33_26, + OPERAND_fld_ae9_slot2_33_28, + OPERAND_fld_ae9_slot2_33_30, + OPERAND_fld_ae9_slot2_33_9, + OPERAND_fld_ae9_slot2_4_0, + OPERAND_fld_ae9_slot2_5_0, + OPERAND_fld_ae9_slot2_6_0, + OPERAND_fld_ae9_slot2_8_0, + OPERAND_fld_ae9_slot2_9_0, + OPERAND_fld_ae9_slot2_9_5, + OPERAND_fld_ae9_slot2_9_9, + OPERAND_fld_ae_sem_hpfma_vp, + OPERAND_fld_ae_sem_hpfma_vu, + OPERAND_fld_ae_sem_spfma_vu, + OPERAND_fld_ae9_slot3_19_15, + OPERAND_fld_ae9_slot3_24_20, + OPERAND_fld_ae9_slot3_31_14, + OPERAND_fld_ae9_slot3_31_15, + OPERAND_fld_ae9_slot3_31_20, + OPERAND_fld_ae9_slot3_31_25, + OPERAND_fld_ae9_slot3_31_26, + OPERAND_fld_ae9_slot3_31_28, + OPERAND_fld_ae9_slot3_31_7, + OPERAND_fld_ae9_slot3_4_0, + OPERAND_fld_ae9_slot3_4_3, + OPERAND_fld_ae9_slot3_4_4, + OPERAND_fld_ae9_slot3_6_0, + OPERAND_fld_ae9_slot3_9_0, + OPERAND_fld_ae9_slot3_9_5, + OPERAND_fld_ae10_slot0_17_13, + OPERAND_fld_ae10_slot0_17_4, + OPERAND_fld_ae10_slot0_17_8, + OPERAND_fld_ae10_slot0_24_0, + OPERAND_fld_ae10_slot0_24_10, + OPERAND_fld_ae10_slot0_24_12, + OPERAND_fld_ae10_slot0_24_13, + OPERAND_fld_ae10_slot0_24_16, + OPERAND_fld_ae10_slot0_24_17, + OPERAND_fld_ae10_slot0_24_18, + OPERAND_fld_ae10_slot0_24_20, + OPERAND_fld_ae10_slot0_24_8, + OPERAND_fld_ae10_slot0_3_0, + OPERAND_fld_ae10_slot0_7_4, + OPERAND_fld_ae10_slot0_7_6, + OPERAND_fld_ae10_slot0_7_7, + OPERAND_fld_ae10_slot0_8_4, + OPERAND_fld_ae10_slot1_0_0, + OPERAND_fld_ae10_slot1_17_13, + OPERAND_fld_ae10_slot1_17_8, + OPERAND_fld_ae10_slot1_25_1, + OPERAND_fld_ae10_slot1_25_12, + OPERAND_fld_ae10_slot1_25_13, + OPERAND_fld_ae10_slot1_25_16, + OPERAND_fld_ae10_slot1_25_17, + OPERAND_fld_ae10_slot1_25_18, + OPERAND_fld_ae10_slot1_25_20, + OPERAND_fld_ae10_slot1_25_22, + OPERAND_fld_ae10_slot1_25_23, + OPERAND_fld_ae10_slot1_25_8, + OPERAND_fld_ae10_slot1_25_9, + OPERAND_fld_ae10_slot1_3_0, + OPERAND_fld_ae10_slot1_3_2, + OPERAND_fld_ae10_slot1_3_3, + OPERAND_fld_ae10_slot1_7_4, + OPERAND_fld_ae10_slot2_24_20, + OPERAND_fld_ae10_slot2_29_20, + OPERAND_fld_ae10_slot2_29_25, + OPERAND_fld_ae10_slot2_34_10, + OPERAND_fld_ae10_slot2_34_14, + OPERAND_fld_ae10_slot2_34_15, + OPERAND_fld_ae10_slot2_34_20, + OPERAND_fld_ae10_slot2_34_25, + OPERAND_fld_ae10_slot2_34_30, + OPERAND_fld_ae10_slot2_34_31, + OPERAND_fld_ae10_slot2_34_33, + OPERAND_fld_ae10_slot2_4_0, + OPERAND_fld_ae10_slot2_9_0, + OPERAND_fld_ae10_slot2_9_5, + OPERAND_fld_ae_sem_hpfma_vq, + OPERAND_fld_ae_sem_spfma_vq, + OPERAND_fld_ae10_slot3_19_15, + OPERAND_fld_ae10_slot3_29_20, + OPERAND_fld_ae10_slot3_29_25, + OPERAND_fld_ae10_slot3_34_10, + OPERAND_fld_ae10_slot3_34_14, + OPERAND_fld_ae10_slot3_34_15, + OPERAND_fld_ae10_slot3_34_20, + OPERAND_fld_ae10_slot3_34_25, + OPERAND_fld_ae10_slot3_34_30, + OPERAND_fld_ae10_slot3_34_31, + OPERAND_fld_ae10_slot3_34_33, + OPERAND_fld_ae10_slot3_4_0, + OPERAND_fld_ae10_slot3_4_3, + OPERAND_fld_ae10_slot3_4_4, + OPERAND_fld_ae10_slot3_9_0, + OPERAND_fld_ae10_slot3_9_5, + OPERAND_fld_ae4_slot0_22_0, + OPERAND_fld_ae4_slot0_22_12, + OPERAND_fld_ae4_slot0_22_13, + OPERAND_fld_ae4_slot0_22_16, + OPERAND_fld_ae4_slot0_22_17, + OPERAND_fld_ae4_slot0_22_18, + OPERAND_fld_ae4_slot0_22_20, + OPERAND_fld_ae4_slot0_22_6, + OPERAND_fld_ae4_slot0_22_8, + OPERAND_fld_ae4_slot0_3_0, + OPERAND_fld_ae4_slot0_3_1, + OPERAND_fld_ae4_slot0_4_4, + OPERAND_fld_ae4_slot0_7_4, + OPERAND_fld_ae4_slot1_22_0, + OPERAND_fld_ae4_slot1_22_12, + OPERAND_fld_ae4_slot1_22_13, + OPERAND_fld_ae4_slot1_22_16, + OPERAND_fld_ae4_slot1_22_17, + OPERAND_fld_ae4_slot1_22_18, + OPERAND_fld_ae4_slot1_22_8, + OPERAND_fld_ae4_slot1_3_0, + OPERAND_fld_ae4_slot1_3_1, + OPERAND_fld_ae4_slot1_7_4, + OPERAND_fld_ae4_slot2_23_0, + OPERAND_fld_ae4_slot2_23_12, + OPERAND_fld_ae4_slot2_23_15, + OPERAND_fld_ae4_slot2_23_17, + OPERAND_fld_ae4_slot2_23_20, + OPERAND_fld_ae4_slot2_4_0, + OPERAND_fld_ae4_slot2_9_5, + OPERAND_fld_ae4_slot3_14_10, + OPERAND_fld_ae4_slot3_19_15, + OPERAND_fld_ae4_slot3_19_19, + OPERAND_fld_ae4_slot3_19_5, + OPERAND_fld_ae4_slot3_27_20, + OPERAND_fld_ae4_slot3_27_25, + OPERAND_fld_ae4_slot3_27_3, + OPERAND_fld_ae4_slot3_2_0, + OPERAND_fld_ae4_slot3_9_0, + OPERAND_fld_ae4_slot3_9_5, + OPERAND_fld_ae4_slot4_22_0, + OPERAND_fld_ae4_slot4_22_15, + OPERAND_fld_ae4_slot4_22_20, + OPERAND_fld_ae4_slot4_9_5, + OPERAND_fld_Inst_11_8, + OPERAND_fld_Inst_12_12, + OPERAND_fld_Inst_12_8, + OPERAND_fld_Inst_13_8, + OPERAND_fld_Inst_15_12, + OPERAND_fld_Inst_19_17, + OPERAND_fld_Inst_19_18, + OPERAND_fld_Inst_23_12, + OPERAND_fld_Inst_23_16, + OPERAND_fld_Inst_4_4, + OPERAND_fld_Inst_5_4, + OPERAND_fld_Inst_7_4, + OPERAND_fld_Inst_7_6, + OPERAND_fld_Inst_7_7, + OPERAND_fld_Inst_9_8, + OPERAND_s3to1 +}; + + +/* Iclass table. */ + +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSRING }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { OPERAND_ars_entry }, 's' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm12x8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { OPERAND_simm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ai4const }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_simm7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8x256 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_label12 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sae }, 'i' }, + { { OPERAND_op2p1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { OPERAND_soffset }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_uimm16x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_simm12b }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ex_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ex_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_getex_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_getex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clrex_stateArgs[] = { + { { STATE_XTSYNC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_simcall_args[] = { + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimmrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { OPERAND_sas }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_msalp32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sargt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { + { { STATE_LEND }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { + { { STATE_LEND }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { + { { STATE_LEND }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { + { { STATE_LCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MEMCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MEMCTL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MEMCTL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'i' }, + { { STATE_VECBASELOCK }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'm' }, + { { STATE_VECBASELOCK }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'm' }, + { { STATE_VECBASELOCK }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpucfg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpucfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUNUMENTRIES }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpucfg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpucfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUNUMENTRIES }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_salt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_opmode_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_opmode_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_OPMODEECCFENCE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_opmode_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_opmode_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_OPMODEECCFENCE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_opmode_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_opmode_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_OPMODEECCFENCE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_mul16_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_EPC5 }, 'i' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_EPS3 }, 'i' }, + { { STATE_EPS4 }, 'i' }, + { { STATE_EPS5 }, 'i' }, + { { STATE_EPS6 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTERRUPT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { OPERAND_imms }, 'i' }, + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC5 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_VECBASE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_bs }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { + { { OPERAND_bs }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_brall }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_brall }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_brall }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdcw_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdcw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldcw_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldcw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_stateArgs[] = { + { { STATE_PREFCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_stateArgs[] = { + { { STATE_PREFCTL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_stateArgs[] = { + { { STATE_PREFCTL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cacheadrdis_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cacheadrdis_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CACHEADRDIS }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cacheadrdis_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cacheadrdis_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CACHEADRDIS }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cacheadrdis_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cacheadrdis_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CACHEADRDIS }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb0_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rptlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wptlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wptlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'm' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_MPULOCK }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpuenb_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_mpuenb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpuenb_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mpuenb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'm' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_MPULOCK }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_mpuenb_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_mpuenb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MPUENB }, 'm' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_MPULOCK }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ERACCESS }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ERACCESS }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ERACCESS }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { + { { STATE_ERACCESS }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_ERI_RAW_INTERLOCK }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = { + INTERFACE_ERI_RD_In, + INTERFACE_ERI_RD_Out +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { + { { STATE_ERACCESS }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_ERI_RAW_INTERLOCK }, 'o' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = { + INTERFACE_ERI_WR_In, + INTERFACE_ERI_WR_Out +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_1_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_2_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_3_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_sext16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_zext16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_zext8_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_clamps16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_fcr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fcr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = { + { { STATE_RoundMode }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_fsr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = { + { { STATE_InvalidFlag }, 'i' }, + { { STATE_DivZeroFlag }, 'i' }, + { { STATE_OverflowFlag }, 'i' }, + { { STATE_UnderflowFlag }, 'i' }, + { { STATE_InexactFlag }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fsr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = { + { { STATE_InvalidFlag }, 'o' }, + { { STATE_DivZeroFlag }, 'o' }, + { { STATE_OverflowFlag }, 'o' }, + { { STATE_UnderflowFlag }, 'o' }, + { { STATE_InexactFlag }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { + INTERFACE_IMPWIRE +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'i' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'o' }, + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = { + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = { + { { STATE_AE_BITHEAD }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_TABLESIZE }, 'i' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = { + { { STATE_AE_BITPTR }, 'o' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cw_sd_no_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cw_sd_no_stateArgs[] = { + { { STATE_AE_CWRAP }, 'i' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cw_sd_no_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cw_sd_no_stateArgs[] = { + { { STATE_AE_CWRAP }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin0_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin0_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend0_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend0_stateArgs[] = { + { { STATE_AE_CEND0 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin1_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend1_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin2_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend2_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_OVERFLOW_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_OVERFLOW_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_OVERFLOW_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_OVERFLOW_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SAR_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SAR_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SAR_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SAR_stateArgs[] = { + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITPTR_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITPTR_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITPTR_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITPTR_stateArgs[] = { + { { STATE_AE_BITPTR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITSUSED_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITSUSED_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITSUSED_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITSUSED_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_TABLESIZE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_TABLESIZE_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_TABLESIZE_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_TABLESIZE_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_FIRST_TS_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_FIRST_TS_stateArgs[] = { + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_FIRST_TS_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_FIRST_TS_stateArgs[] = { + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_NEXTOFFSET_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_NEXTOFFSET_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_NEXTOFFSET_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_NEXTOFFSET_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SEARCHDONE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SEARCHDONE_stateArgs[] = { + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SEARCHDONE_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SEARCHDONE_stateArgs[] = { + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_CWRAP_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_CWRAP_stateArgs[] = { + { { STATE_AE_CWRAP }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_CWRAP_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_CWRAP_stateArgs[] = { + { { STATE_AE_CWRAP }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4S_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4U_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4U_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4U_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4U_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4U_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4U_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4U_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64neg }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RI_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64half }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_I_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_IP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_X_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_XP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_H_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8_0_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_IU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XU_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_I_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_IP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_X_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RNG_XP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_I_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_IP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_X_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2RNG_XP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4UX2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4UX2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4UX2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4UX2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4UX2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4UX2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4UX2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X4UX2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X8X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S8X8X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64X2_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_I_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i128 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_IP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_X_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4X2RNG_XP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ZALIGN64_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_ZALIGN64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LALIGN64_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LALIGN64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SALIGN64_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SALIGN64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVALIGN_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_vu }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVALIGN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA64_PP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA64_PP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8NEG_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8NEG_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2POS_PC2_stateArgs[] = { + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64POS_FP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64POS_FP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64NEG_FP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64NEG_FP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDICIRC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_end }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_I_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_X_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_I_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_X_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_X_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RA64S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24X2RA64S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S24X2RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RA32S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4RA32S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDBRBA32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_aoe }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ab }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ai }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_L_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BITSWAP_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_aoe }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ab }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32JS_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32JS_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32JS_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32JS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_H_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_H_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_L_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDRNG32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBRNG32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RNG32X2_args[] = { + { { OPERAND_opnd_ae_sem_rng_d }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RNG32X2_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_immed }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_N_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_immed_N }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_N_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHORTSWAP_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHORTSWAP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAB4_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAB2_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAB_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA1X2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVB2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVB4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT16X4_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF16X4_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT32X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF32X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARA7X2_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARA7X2_stateArgs[] = { + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARD7_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARD7_stateArgs[] = { + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVASAR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_MOVASAR_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVI_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_movi_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24A32X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24A32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT16X4_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT16X4_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_10_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_10_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_10_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_10_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LL_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LH_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HL_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HH_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24Q48X2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24Q48X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32X2F64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32X2F64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32X2F64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32X2F64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32F64S_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32F64S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32F64S_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32F64S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP16_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SSYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SSYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SSYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SSYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2SYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2SYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2ASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2ASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24SYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24SYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24ASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24ASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOV_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT64_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF64_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56A32S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56A32S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48A32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48A32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64A32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64A32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64F32_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64F32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT48S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT48S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATQ56S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT24S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCQ32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCQ32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48SYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48SYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48ASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48ASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32Q48_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32Q48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_3_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_1_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_0_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRA64_32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRA64_32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR32_args[] = { + { { OPERAND_opnd_ae_sem_pks_d }, 'm' }, + { { OPERAND_opnd_ae_sem_pks_s }, 'i' }, + { { OPERAND_opnd_ae_sem_pks_pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR24_args[] = { + { { OPERAND_opnd_ae_sem_pks_d }, 'm' }, + { { OPERAND_opnd_ae_sem_pks_s }, 'i' }, + { { OPERAND_opnd_ae_sem_pks_pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR24_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSRF32_args[] = { + { { OPERAND_opnd_ae_sem_pks_d }, 'm' }, + { { OPERAND_opnd_ae_sem_pks_s }, 'i' }, + { { OPERAND_opnd_ae_sem_pks_pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSRF32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR16_args[] = { + { { OPERAND_opnd_ae_sem_pks_d }, 'm' }, + { { OPERAND_opnd_ae_sem_pks_s }, 'i' }, + { { OPERAND_opnd_ae_sem_pks_pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR16_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD24S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB24S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG24S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS24S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG16S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS16S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16JS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16JS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16JS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16JS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16JS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16JS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16JS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16JS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT16_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE16_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ16_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINMAX32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINMAX32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINMAX16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINMAX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSQ56S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBSQ56S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEGSQ56S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEGSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABSSQ56S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABSSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_AND_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_AND_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NAND_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NAND_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_OR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_OR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_XOR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_XOR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS24_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16R_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32R_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI16S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA16S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16RS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32RS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASQ56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLSQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLSQ56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRASQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRASQ56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAAQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAAQ56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLAQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLAQ56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAAQ56_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAAQ56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS64_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS64_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA64_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAISQ56S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAISQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASSQ56S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAASQ56S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAASQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT64_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE64_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ64_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA64_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ16_0_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ16_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ32_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32U_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32U_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32U_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32U_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32U_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32U_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_33_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_33_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_21_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_21_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_31_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_31_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_30_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_30_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_10_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_10_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_20_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_20_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_11_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_11_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_33_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_33_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_21_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_21_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_31_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_31_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_30_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_30_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_10_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_10_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_20_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_20_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_11_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_11_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_33_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_33_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_21_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_21_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_31_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_31_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_30_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_30_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_10_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_10_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_20_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_20_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_11_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_11_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16S_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16S_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16S_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16S_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16S_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16S_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2R_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2R_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2R_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2TS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2TS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2TS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2TS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2TS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2TS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC24RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC24RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC24RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC24RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16X4SS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16X4SS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16X4SS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16X4SS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16X4SS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16X4SS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC16RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC16RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC16RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC16RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16JS_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16JS_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG16RAS_S1_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_vs }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG16RAS_S1_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG16RAS_S2_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_vs }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG16RAS_S2_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CONJ16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CONJ16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFQ16X2_FIR_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_3_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_1_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_0_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFQ16X2_FIR_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAFQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAFQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAFQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAFQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16_00_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16_00_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16_00_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_H_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHA32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_aoe }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ai }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL32T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL32T_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16T_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IP_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IP_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC1_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDSHT_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDSHT_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_opnd_ae_sem_lb_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ae_sem_lb_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBS_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBS_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBSI_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_opnd_ae_sem_lb_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBSI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ARDECNORM16_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_opnd_AE_ARDECNORM16_ar_u }, 'm' }, + { { OPERAND_arr }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_DBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_iba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_DBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_arr }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_DB_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_lb_db_ops_ar_u }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_DB_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL32T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL32T_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL16T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL16T_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC1_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC1_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IP_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_opnd_ae_sem_sb_loads_stores_iba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IP_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IP_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAE_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ei }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAE_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEA_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_eo }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ar_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEEP_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_eo }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_ei }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEEP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT72_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ep1 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ep1 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72X64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72X64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72X64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72X64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32EP_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32EP_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32EP_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32EP_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32EP_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32EP_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32USEP_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32USEP_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32USEP_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32USEP_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI72_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_e }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI72_args[] = { + { { OPERAND_opnd_ae_sem_shift_e }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT64S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_e }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16SI_N_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_uimm2x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16UI_N_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_uimm2x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16I_N_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_uimm2x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LALIGN128_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LALIGN128_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SALIGN128_I_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SALIGN128_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA128_PP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA128_PP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA128POS_FP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA128POS_FP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X4S_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X4S_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X4U_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X4U_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA8X8X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC1_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA8X8X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC2_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2X2_IC2_stateArgs[] = { + { { STATE_AE_CEND2 }, 'i' }, + { { STATE_AE_CBEGIN2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS8S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG8S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD8S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB8S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_art }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_art }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_art }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU16X4_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU16X4_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT32X2_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT32X2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU32X2_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU32X2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT8X8X16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT8X8X16_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU8X8X16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU8X8X16_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT8X4X32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT8X4X32_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU8X4X32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATU8X4X32_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X8F16SSYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X8F16SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X8F16SASYM_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X8F16SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X4F32SSYM_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X4F32SSYM_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X4F32SASYM_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND8X4F32SASYM_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA8_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD8_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDX2_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDX2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32J_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32J_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW8_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW16_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW32_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW8U_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDW8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW8U_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBW8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW8U_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ACCW8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_HL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_HL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_HL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_HL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_HL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_HL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X2S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X2S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X2S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X2S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSF2D32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2R_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2R_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2R_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2R_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2R_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2R_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2R_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X2R_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2R_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X2R_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2R_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X2R_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2P32X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2P32X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS2P32X4_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS2P32X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2P32X4T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2P32X4T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2P32X4T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS2P32X4T_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS2P32X4T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA32X2_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA32X2_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS32X2_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS32X2_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA32X2_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA32X2_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32X2_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32X2_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULCJ32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULCJ32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULACJ32_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULACJ32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULADDF32RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULADDF32RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULADDF32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULADDF32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSUBF32RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSUBF32RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSUBF32RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSUBF32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32RA_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULCJ32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULCJ32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULACJ32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULACJ32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32W_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32W_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2D32X2WS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2D32X2WS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16S_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2C16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2C16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2C16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2C16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ16RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ16RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ16RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ16RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD16X16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD16X16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP16X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP16X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP16X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA2D16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA2D16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA2D16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAA2D16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS2D16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS2D16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS2D16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSS2D16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA2D16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA2D16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA2D16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAA2D16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS2D16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS2D16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS2D16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS2D16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD16X16X4WS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD16X16X4WS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q16X8_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q16X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q16X8_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q16X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q8_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q8_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULPC32X16X2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULPC32X16X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAPC32X16X2_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAPC32X16X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32X16W_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32X16W_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFCJ32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32X16W_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFCJ32X16W_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4RS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF2P32X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF2P32X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4S_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF2P32X16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFPC32X16X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFPC32X16X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFPC32X16X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFPC32X16X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFPCJ32X16X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFPCJ32X16X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFPCJ32X16X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFPCJ32X16X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAA2Q32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q32X16_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAA2Q32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2Q32X16_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2Q32X16_FIR_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2Q32X16_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2Q32X16_FIR_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2Q32X16_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2Q32X16_FIR_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2Q32X16_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_multiply_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_multiply_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d2 }, 'i' }, + { { OPERAND_opnd_ae_sem_multiply_d3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2Q32X16_FIR_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI8_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI8R_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI8R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI8_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI8_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI8S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA8_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA8_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA8S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA8RS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA8RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA8S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI16_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI16_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA16_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA16_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16SYM_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16SYM_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16SYMS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16SYMS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32SYM_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32SYM_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32SYMS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32SYMS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAV16RS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAV16RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAV32RS_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAV32RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8S_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8S_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8S_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8S_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8U_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8U_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8U_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8US_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8US_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8US_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F8US_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8U_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8U_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8U_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8US_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8US_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8US_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F8US_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16S_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16S_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16U_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16US_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI32X4F16US_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16U_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16US_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32X4F16US_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8S_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8S_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8U_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8US_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTI16X4X2F8US_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8U_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8US_args[] = { + { { OPERAND_opnd_ae_sem_shift_da }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA16X4X2F8US_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL8X8_args[] = { + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHFL8X8_args[] = { + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHFL8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16X4_args[] = { + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHFL16X4_args[] = { + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHFL16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DSEL8X8_args[] = { + { { OPERAND_opnd_ae_sem_select_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DSEL8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DSEL16X4_args[] = { + { { OPERAND_opnd_ae_sem_select_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_ss }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DSEL16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL8X8I_args[] = { + { { OPERAND_opnd_ae_sem_select_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_select_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_select_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_select_isel }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL8X8I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMAX8X8_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMAX8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMIN8X8_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMIN8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMAX16X4_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMAX16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMIN16X4_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RMIN16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SORT16X4_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SORT16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD8X8_H_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD8X8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA8X8_H_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'm' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA8X8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD8X8_L_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD8X8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA8X8_L_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'm' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA8X8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD16X4_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'o' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADD16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA16X4_args[] = { + { { OPERAND_opnd_ae_sem_reduction_sort_v }, 'm' }, + { { OPERAND_opnd_ae_sem_reduction_sort_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RADDA16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX8X8_H_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX8X8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX8X8_L_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX8X8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN8X8_H_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN8X8_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN8X8_L_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN8X8_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX16X4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN16X4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX32X2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMAX32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN32X2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BMIN32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDINV16S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDINV16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDINV32S_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDINV32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT16X8_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT16X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT8X16_H_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT8X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT8X16_L_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_ds }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v1 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT8X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBD1X4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBD1X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBD1X2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBD1X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVNEG32S_T_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVNEG32S_T_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDEXT_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDEXT_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVADEXT_H_args[] = { + { { OPERAND_opnd_ae_sem_shift_a }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVADEXT_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVADEXT_L_args[] = { + { { OPERAND_opnd_ae_sem_shift_a }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_imm32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVADEXT_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA16X4_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_d }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ32X4_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_d }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ32X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA32X4_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_d }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA32X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI16X4F32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI16X4F32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI16X4F64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI16X4F64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16X4F32S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16X4F32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16X4F64S_args[] = { + { { OPERAND_opnd_ae_sem_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_sd }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_a0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16X4F64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDC32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDC32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBC32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBC32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDC32U_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDC32U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBC32U_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBC32U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPADD16_H_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPADD16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPSUB16_H_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPSUB16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPADD16_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPADD16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPSUB16_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_va }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EXPSUB16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCEXP32_H_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCEXP32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCEXP32_L_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_arithmetic_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCEXP32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG16_args[] = { + { { OPERAND_opnd_ae_sem_rng_a }, 'o' }, + { { OPERAND_opnd_ae_sem_rng_art }, 'o' }, + { { OPERAND_opnd_ae_sem_rng_i2 }, 'i' }, + { { OPERAND_opnd_ae_sem_rng_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG16_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG32_args[] = { + { { OPERAND_opnd_ae_sem_rng_a }, 'o' }, + { { OPERAND_opnd_ae_sem_rng_art }, 'o' }, + { { OPERAND_opnd_ae_sem_rng_i2 }, 'i' }, + { { OPERAND_opnd_ae_sem_rng_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RNG32X4_args[] = { + { { OPERAND_opnd_ae_sem_rng_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_rng_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RNG32X4_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAV8X8X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAV8X8X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAV16X4X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAV16X4X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAV8X8X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAV8X8X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAV16X4X2_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_v }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_su }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAV16X4X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVZBVCDR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVZBVCDR_stateArgs[] = { + { { STATE_AE_ZBIASV8 }, 'o' }, + { { STATE_AE_ZBIASC8 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDRZBVC_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDRZBVC_stateArgs[] = { + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAVUNSQZ8X8_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAVUNSQZ8X8_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAVUNSQZ16X4_XP_args[] = { + { { OPERAND_opnd_ae_sem_loads_stores_av }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_av1 }, 'o' }, + { { OPERAND_opnd_ae_sem_loads_stores_uu }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_a_0 }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_x }, 'i' }, + { { OPERAND_opnd_ae_sem_loads_stores_i3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LAVUNSQZ16X4_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O8X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O8X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL8Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA8Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL2X4Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA2X4Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQQ4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQQ4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_HL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL4O4X16CNV_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_HL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA4O4X16CNV_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUU4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUU4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4QW8X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4QW8X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ8X16CNV_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ8X16CNV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O8X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O8X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS8Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS8Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS2X4Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS2X4Q4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ4X16CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ4X16CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUSQQ4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ4X16CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUSQQ4X16CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_HL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUS4O4X16CNV_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_HL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUS4O4X16CNV_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU8Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8CNV_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSU4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASU4O8X8CNV_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB8Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB8Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB4O8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB4O8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB3X3O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULUUZB3X3O8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB3X3O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAUUZB3X3O8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB8Q8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB8Q8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB8Q8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB4O8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB4O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c3 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB4O8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB8Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB8Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB8Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB8Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB8Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB8Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB2X4Q8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB2X4Q8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB2X4Q8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB2X4Q8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB4O8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB4O8X8CNV_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB4O8X8CNV_H_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB4O8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB4O8X8CNV_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB4O8X8CNV_L_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB3X3O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZB3X3O8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB3X3O8X8_args[] = { + { { OPERAND_opnd_ae_sem_mul_nn_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q2 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_q3 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_nn_c0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_c2 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_nn_v3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAZB3X3O8X8_stateArgs[] = { + { { STATE_AE_ZBIASC8 }, 'i' }, + { { STATE_AE_ZBIASV8 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_L_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_L_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_H_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_L_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_L_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_H_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVFCRFSRV_args[] = { + { { OPERAND_opnd_ae_sem_movfpstate_v }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVFCRFSRV_stateArgs[] = { + { { STATE_RoundMode }, 'o' }, + { { STATE_InvalidFlag }, 'o' }, + { { STATE_DivZeroFlag }, 'o' }, + { { STATE_OverflowFlag }, 'o' }, + { { STATE_UnderflowFlag }, 'o' }, + { { STATE_InexactFlag }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVVFCRFSR_args[] = { + { { OPERAND_opnd_ae_sem_movfpstate_v }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_MOVVFCRFSR_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_InvalidFlag }, 'i' }, + { { STATE_DivZeroFlag }, 'i' }, + { { STATE_OverflowFlag }, 'i' }, + { { STATE_UnderflowFlag }, 'i' }, + { { STATE_InexactFlag }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVT_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVT_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVF_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVF_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVEQZ_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVEQZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVNEZ_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVNEZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVGEZ_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVGEZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVLTZ_S_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'm' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_dr_to_dr_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVLTZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RFR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_ar_a }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RFR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WFR_args[] = { + { { OPERAND_opnd_ae_sem_dr_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_WFR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBN_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBN_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_S_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_S_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'm' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_S_stateArgs[] = { + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vsM }, 'm' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vsM }, 'm' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MIN_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MIN_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAX_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAX_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUX_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUX_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUX_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUX_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_art }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_art }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_SX2_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_SX2_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_SX2_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_SX2_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FICEIL_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FICEIL_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIFLOOR_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIFLOOR_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIRINT_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIRINT_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIROUND_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIROUND_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FITRUNC_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FITRUNC_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_S_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_SX2_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_SX2_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_SX2_args[] = { + { { OPERAND_opnd_ae_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_SX2_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_S_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_S_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_S_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_S_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_S_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CLSFY_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CLSFY_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUM_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUM_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUM_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUM_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDANDSUB_S_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDANDSUB_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDANDSUBJC_S_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDANDSUBJC_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_HL_LH_S_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_HL_LH_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDA_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDA_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FREXP_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vsM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FREXP_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOATEXP_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOATEXP_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUMABS_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUMABS_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUMABS_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUMABS_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUXQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUXQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUXQ_S_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUXQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMAXNUM_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMAXNUM_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMINNUM_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMINNUM_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMAXNUMABS_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMAXNUMABS_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMINNUMABS_S_args[] = { + { { OPERAND_opnd_ae_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_ae_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_BMINNUMABS_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_SX2X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_SX2X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_SX2X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_SX2X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_SX2X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spaddsub_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spaddsub_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spaddsub_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUX_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUX_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUX_SX2X2_args[] = { + { { OPERAND_opnd_ae_sem_spfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_vp }, 'i' }, + { { OPERAND_opnd_ae_sem_spfma_i_imm3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUX_SX2X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'm' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'm' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CLSFY_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CLSFY_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_H_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_H_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MIN_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MIN_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAX_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAX_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUM_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MINNUM_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUM_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAXNUM_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_H_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcmp_br4t }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcmp_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcmp_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FICEIL_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FICEIL_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIFLOOR_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIFLOOR_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIRINT_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIRINT_H_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIROUND_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIROUND_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FITRUNC_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FITRUNC_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vs }, 'm' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP0_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP0_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT16_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT16_H_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT16_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_arr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT16_H_stateArgs[] = { + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC16_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_art }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC16_H_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC16_H_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_art }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC16_H_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT16_HX4_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT16_HX4_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT16_HX4_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT16_HX4_stateArgs[] = { + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC16_HX4_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC16_HX4_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC16_HX4_args[] = { + { { OPERAND_opnd_ae_sem_hpcnv_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpcnv_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpcnv_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC16_HX4_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBN_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBN_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_H_stateArgs[] = { + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RMINNUM_H_args[] = { + { { OPERAND_opnd_ae_sem_hprminmaxnum_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hprminmaxnum_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RMINNUM_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RMAXNUM_H_args[] = { + { { OPERAND_opnd_ae_sem_hprminmaxnum_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hprminmaxnum_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RMAXNUM_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_HX4X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_HX4X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_HX4X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_HX4X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_fpmov_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_fpmov_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_fpmov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULJC_HX4X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vq }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULQ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULQ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDQ_H_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDQ_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULCNVH_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULCNVH_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULACNVH_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULACNVH_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULCNVL_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'o' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULCNVL_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULACNVL_HX4X2_args[] = { + { { OPERAND_opnd_ae_sem_hpfma_vu }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vt }, 'm' }, + { { OPERAND_opnd_ae_sem_hpfma_vs }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vr }, 'i' }, + { { OPERAND_opnd_ae_sem_hpfma_vp }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULACNVL_HX4X2_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_iclass_internal iclasses[] = { + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_threadptr_args, + 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, + { 1, Iclass_wur_threadptr_args, + 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_loop_args, + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_loopz_args, + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32ex_args, + 1, Iclass_xt_iclass_l32ex_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_s32ex_args, + 1, Iclass_xt_iclass_s32ex_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_getex_args, + 1, Iclass_xt_iclass_getex_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_clrex */, + 1, Iclass_xt_iclass_clrex_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_simcall_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32nb_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lend_args, + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lend_args, + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lend_args, + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lcount_args, + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lcount_args, + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lcount_args, + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lbeg_args, + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lbeg_args, + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lbeg_args, + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_memctl_args, + 3, Iclass_xt_iclass_rsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_memctl_args, + 3, Iclass_xt_iclass_wsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_memctl_args, + 3, Iclass_xt_iclass_xsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid0_args, + 2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_configid0_args, + 2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid1_args, + 2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc3_args, + 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc3_args, + 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc3_args, + 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave3_args, + 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave3_args, + 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave3_args, + 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc4_args, + 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc4_args, + 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc4_args, + 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave4_args, + 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave4_args, + 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave4_args, + 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc5_args, + 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc5_args, + 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc5_args, + 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave5_args, + 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave5_args, + 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave5_args, + 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc6_args, + 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc6_args, + 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc6_args, + 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave6_args, + 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave6_args, + 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave6_args, + 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps3_args, + 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps3_args, + 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps3_args, + 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps4_args, + 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps4_args, + 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps4_args, + 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps5_args, + 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps5_args, + 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps5_args, + 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps6_args, + 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps6_args, + 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps6_args, + 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc0_args, + 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc0_args, + 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc0_args, + 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc1_args, + 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc1_args, + 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc1_args, + 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc2_args, + 3, Iclass_xt_iclass_rsr_misc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc2_args, + 3, Iclass_xt_iclass_wsr_misc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc2_args, + 3, Iclass_xt_iclass_xsr_misc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc3_args, + 3, Iclass_xt_iclass_rsr_misc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc3_args, + 3, Iclass_xt_iclass_wsr_misc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc3_args, + 3, Iclass_xt_iclass_xsr_misc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_vecbase_args, + 4, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_vecbase_args, + 4, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_vecbase_args, + 4, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_mpucfg_args, + 3, Iclass_xt_iclass_rsr_mpucfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mpucfg_args, + 3, Iclass_xt_iclass_wsr_mpucfg_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_salt_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_opmode_args, + 3, Iclass_xt_iclass_rsr_opmode_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_opmode_args, + 3, Iclass_xt_iclass_wsr_opmode_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_opmode_args, + 3, Iclass_xt_iclass_xsr_opmode_stateArgs, 0, 0 }, + { 3, Iclass_xt_mul16_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 19, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka0_args, + 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka0_args, + 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka0_args, + 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc0_args, + 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc0_args, + 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc0_args, + 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka1_args, + 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka1_args, + 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka1_args, + 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc1_args, + 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc1_args, + 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc1_args, + 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka0_args, + 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka0_args, + 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka0_args, + 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka1_args, + 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka1_args, + 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka1_args, + 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreakenable_args, + 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreakenable_args, + 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreakenable_args, + 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_lddr32_p_args, + 5, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sddr32_p_args, + 4, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfdo_args, + 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 2, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mmid_args, + 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_bbool1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbranch_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bmove_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_RSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_WSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_XSR_BR_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare1_args, + 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare1_args, + 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare1_args, + 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare2_args, + 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare2_args, + 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare2_args, + 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_lock_args, + 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_inv_args, + 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_licx_args, + 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sicx_args, + 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_dcache_dyn_args, + 2, Iclass_xt_iclass_dcache_dyn_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_ind_args, + 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_inv_args, + 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dpf_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_lock_args, + 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sdct_args, + 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ldct_args, + 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sdcw_args, + 2, Iclass_xt_iclass_sdcw_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ldcw_args, + 2, Iclass_xt_iclass_ldcw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prefctl_args, + 1, Iclass_xt_iclass_rsr_prefctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_prefctl_args, + 1, Iclass_xt_iclass_wsr_prefctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_prefctl_args, + 1, Iclass_xt_iclass_xsr_prefctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cacheadrdis_args, + 4, Iclass_xt_iclass_wsr_cacheadrdis_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cacheadrdis_args, + 3, Iclass_xt_iclass_rsr_cacheadrdis_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cacheadrdis_args, + 4, Iclass_xt_iclass_xsr_cacheadrdis_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rptlb0_args, + 3, Iclass_xt_iclass_rptlb0_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rptlb_args, + 2, Iclass_xt_iclass_rptlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_wptlb_args, + 5, Iclass_xt_iclass_wptlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_mpuenb_args, + 3, Iclass_xt_iclass_rsr_mpuenb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mpuenb_args, + 5, Iclass_xt_iclass_wsr_mpuenb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_mpuenb_args, + 5, Iclass_xt_iclass_xsr_mpuenb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cpenable_args, + 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cpenable_args, + 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cpenable_args, + 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_clamp_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_minmax_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_sx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32ai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32ri_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_atomctl_args, + 4, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_atomctl_args, + 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_atomctl_args, + 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_div_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eraccess_args, + 3, Iclass_xt_iclass_rsr_eraccess_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eraccess_args, + 3, Iclass_xt_iclass_wsr_eraccess_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eraccess_args, + 3, Iclass_xt_iclass_xsr_eraccess_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rer_args, + 4, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs }, + { 2, Iclass_xt_iclass_wer_args, + 4, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs }, + { 2, Iclass_xt_iclass_wb15_0_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_1_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_2_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_3_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_4_args, + 0, 0, 0, 0 }, + { 2, Iclass_ic_sext16_args, + 0, 0, 0, 0 }, + { 2, Iclass_ic_zext16_args, + 0, 0, 0, 0 }, + { 2, Iclass_ic_zext8_args, + 0, 0, 0, 0 }, + { 2, Iclass_ic_clamps16_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_fcr_args, + 2, Iclass_rur_fcr_stateArgs, 0, 0 }, + { 1, Iclass_wur_fcr_args, + 2, Iclass_wur_fcr_stateArgs, 0, 0 }, + { 1, Iclass_rur_fsr_args, + 6, Iclass_rur_fsr_stateArgs, 0, 0 }, + { 1, Iclass_wur_fsr_args, + 6, Iclass_wur_fsr_stateArgs, 0, 0 }, + { 1, Iclass_iclass_READ_IMPWIRE_args, + 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, + { 1, Iclass_iclass_SETB_EXPSTATE_args, + 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, + { 1, Iclass_iclass_CLRB_EXPSTATE_args, + 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, + { 2, Iclass_iclass_WRMSK_EXPSTATE_args, + 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_ovf_sar_args, + 3, Iclass_rur_ae_ovf_sar_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_ovf_sar_args, + 3, Iclass_wur_ae_ovf_sar_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_bithead_args, + 2, Iclass_rur_ae_bithead_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_bithead_args, + 2, Iclass_wur_ae_bithead_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_ts_fts_bu_bp_args, + 5, Iclass_rur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_ts_fts_bu_bp_args, + 5, Iclass_wur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cw_sd_no_args, + 4, Iclass_rur_ae_cw_sd_no_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cw_sd_no_args, + 4, Iclass_wur_ae_cw_sd_no_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cbegin0_args, + 2, Iclass_rur_ae_cbegin0_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cbegin0_args, + 2, Iclass_wur_ae_cbegin0_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cend0_args, + 2, Iclass_rur_ae_cend0_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cend0_args, + 2, Iclass_wur_ae_cend0_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cbegin1_args, + 2, Iclass_rur_ae_cbegin1_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cbegin1_args, + 2, Iclass_wur_ae_cbegin1_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cend1_args, + 2, Iclass_rur_ae_cend1_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cend1_args, + 2, Iclass_wur_ae_cend1_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cbegin2_args, + 2, Iclass_rur_ae_cbegin2_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cbegin2_args, + 2, Iclass_wur_ae_cbegin2_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cend2_args, + 2, Iclass_rur_ae_cend2_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cend2_args, + 2, Iclass_wur_ae_cend2_stateArgs, 0, 0 }, + { 1, Iclass_rur_expstate_args, + 1, Iclass_rur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_wur_expstate_args, + 1, Iclass_wur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_OVERFLOW_args, + 2, Iclass_RUR_AE_OVERFLOW_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_OVERFLOW_args, + 2, Iclass_WUR_AE_OVERFLOW_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_SAR_args, + 2, Iclass_RUR_AE_SAR_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_SAR_args, + 2, Iclass_WUR_AE_SAR_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_BITPTR_args, + 2, Iclass_RUR_AE_BITPTR_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_BITPTR_args, + 2, Iclass_WUR_AE_BITPTR_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_BITSUSED_args, + 2, Iclass_RUR_AE_BITSUSED_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_BITSUSED_args, + 2, Iclass_WUR_AE_BITSUSED_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_TABLESIZE_args, + 2, Iclass_RUR_AE_TABLESIZE_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_TABLESIZE_args, + 2, Iclass_WUR_AE_TABLESIZE_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_FIRST_TS_args, + 2, Iclass_RUR_AE_FIRST_TS_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_FIRST_TS_args, + 2, Iclass_WUR_AE_FIRST_TS_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_NEXTOFFSET_args, + 2, Iclass_RUR_AE_NEXTOFFSET_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_NEXTOFFSET_args, + 2, Iclass_WUR_AE_NEXTOFFSET_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_SEARCHDONE_args, + 2, Iclass_RUR_AE_SEARCHDONE_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_SEARCHDONE_args, + 2, Iclass_WUR_AE_SEARCHDONE_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_CWRAP_args, + 2, Iclass_RUR_AE_CWRAP_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_CWRAP_args, + 2, Iclass_WUR_AE_CWRAP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8X4F_I_args, + 1, Iclass_AE_L8X4F_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8X4F_IP_args, + 1, Iclass_AE_L8X4F_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8X4F_X_args, + 1, Iclass_AE_L8X4F_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8X4F_XP_args, + 1, Iclass_AE_L8X4F_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8X4S_I_args, + 1, Iclass_AE_L8X4S_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8X4S_IP_args, + 1, Iclass_AE_L8X4S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8X4S_X_args, + 1, Iclass_AE_L8X4S_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8X4S_XP_args, + 1, Iclass_AE_L8X4S_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8X4U_I_args, + 1, Iclass_AE_L8X4U_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8X4U_IP_args, + 1, Iclass_AE_L8X4U_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8X4U_X_args, + 1, Iclass_AE_L8X4U_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8X4U_XP_args, + 1, Iclass_AE_L8X4U_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S8X4U_I_args, + 1, Iclass_AE_S8X4U_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S8X4U_IP_args, + 1, Iclass_AE_S8X4U_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S8X4U_X_args, + 1, Iclass_AE_S8X4U_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S8X4U_XP_args, + 1, Iclass_AE_S8X4U_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16M_XC_args, + 3, Iclass_AE_L16M_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16M_XC1_args, + 3, Iclass_AE_L16M_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16M_I_args, + 1, Iclass_AE_L16M_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16M_IU_args, + 1, Iclass_AE_L16M_IU_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16M_X_args, + 1, Iclass_AE_L16M_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16M_XU_args, + 1, Iclass_AE_L16M_XU_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16_XC_args, + 3, Iclass_AE_L16_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16_XC1_args, + 3, Iclass_AE_L16_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16_I_args, + 1, Iclass_AE_L16_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16_IP_args, + 1, Iclass_AE_L16_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16_X_args, + 1, Iclass_AE_L16_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16_XP_args, + 1, Iclass_AE_L16_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8_XC_args, + 3, Iclass_AE_L8_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8_XC1_args, + 3, Iclass_AE_L8_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8_I_args, + 1, Iclass_AE_L8_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8_IP_args, + 1, Iclass_AE_L8_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8_X_args, + 1, Iclass_AE_L8_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8_XP_args, + 1, Iclass_AE_L8_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32F24_XC_args, + 3, Iclass_AE_L32F24_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32F24_XC1_args, + 3, Iclass_AE_L32F24_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32F24_I_args, + 1, Iclass_AE_L32F24_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32F24_IP_args, + 1, Iclass_AE_L32F24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32F24_X_args, + 1, Iclass_AE_L32F24_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32F24_XP_args, + 1, Iclass_AE_L32F24_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32_XC_args, + 3, Iclass_AE_L32_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32_XC1_args, + 3, Iclass_AE_L32_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32_I_args, + 1, Iclass_AE_L32_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32_IP_args, + 1, Iclass_AE_L32_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32_X_args, + 1, Iclass_AE_L32_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32_XP_args, + 1, Iclass_AE_L32_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32M_XC_args, + 3, Iclass_AE_L32M_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32M_I_args, + 1, Iclass_AE_L32M_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32M_IU_args, + 1, Iclass_AE_L32M_IU_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32M_X_args, + 1, Iclass_AE_L32M_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32M_XU_args, + 1, Iclass_AE_L32M_XU_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X2M_XC_args, + 3, Iclass_AE_L16X2M_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X2M_XC1_args, + 3, Iclass_AE_L16X2M_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X2M_I_args, + 1, Iclass_AE_L16X2M_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X2M_IU_args, + 1, Iclass_AE_L16X2M_IU_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X2M_X_args, + 1, Iclass_AE_L16X2M_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X2M_XU_args, + 1, Iclass_AE_L16X2M_XU_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2F24_XC_args, + 3, Iclass_AE_L32X2F24_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2F24_XC1_args, + 3, Iclass_AE_L32X2F24_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2F24_I_args, + 1, Iclass_AE_L32X2F24_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2F24_IP_args, + 1, Iclass_AE_L32X2F24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2F24_RIP_args, + 1, Iclass_AE_L32X2F24_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2F24_RI_args, + 1, Iclass_AE_L32X2F24_RI_stateArgs, 0, 0 }, + { 2, Iclass_AE_L32X2F24_RIC_args, + 3, Iclass_AE_L32X2F24_RIC_stateArgs, 0, 0 }, + { 2, Iclass_AE_L32X2F24_RIC1_args, + 3, Iclass_AE_L32X2F24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2F24_X_args, + 1, Iclass_AE_L32X2F24_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2F24_XP_args, + 1, Iclass_AE_L32X2F24_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2_XC_args, + 3, Iclass_AE_L32X2_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2_XC1_args, + 3, Iclass_AE_L32X2_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2_I_args, + 1, Iclass_AE_L32X2_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2_IP_args, + 1, Iclass_AE_L32X2_IP_stateArgs, 0, 0 }, + { 2, Iclass_AE_L32X2_RIC_args, + 3, Iclass_AE_L32X2_RIC_stateArgs, 0, 0 }, + { 2, Iclass_AE_L32X2_RIC1_args, + 3, Iclass_AE_L32X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2_X_args, + 1, Iclass_AE_L32X2_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2_XP_args, + 1, Iclass_AE_L32X2_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X4_XC_args, + 3, Iclass_AE_L16X4_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X4_XC1_args, + 3, Iclass_AE_L16X4_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X4_I_args, + 1, Iclass_AE_L16X4_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X4_IP_args, + 1, Iclass_AE_L16X4_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X4_X_args, + 1, Iclass_AE_L16X4_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X4_XP_args, + 1, Iclass_AE_L16X4_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8X8_XC_args, + 3, Iclass_AE_L8X8_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8X8_XC1_args, + 3, Iclass_AE_L8X8_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8X8_I_args, + 1, Iclass_AE_L8X8_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8X8_IP_args, + 1, Iclass_AE_L8X8_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8X8_X_args, + 1, Iclass_AE_L8X8_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8X8_XP_args, + 1, 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}, + { 3, Iclass_AE_S32X2F24_XC1_args, + 3, Iclass_AE_S32X2F24_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2F24_I_args, + 1, Iclass_AE_S32X2F24_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2F24_IP_args, + 1, Iclass_AE_S32X2F24_IP_stateArgs, 0, 0 }, + { 2, Iclass_AE_S32X2F24_RIP_args, + 1, Iclass_AE_S32X2F24_RIP_stateArgs, 0, 0 }, + { 2, Iclass_AE_S32X2F24_RIC_args, + 3, Iclass_AE_S32X2F24_RIC_stateArgs, 0, 0 }, + { 2, Iclass_AE_S32X2F24_RIC1_args, + 3, Iclass_AE_S32X2F24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2F24_X_args, + 1, Iclass_AE_S32X2F24_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2F24_XP_args, + 1, Iclass_AE_S32X2F24_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2_XC_args, + 3, Iclass_AE_S32X2_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2_XC1_args, + 3, Iclass_AE_S32X2_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2_I_args, + 1, Iclass_AE_S32X2_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2_IP_args, + 1, Iclass_AE_S32X2_IP_stateArgs, 0, 0 }, + { 2, Iclass_AE_S32X2_RIC_args, + 3, Iclass_AE_S32X2_RIC_stateArgs, 0, 0 }, + { 2, Iclass_AE_S32X2_RIC1_args, + 3, Iclass_AE_S32X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2_X_args, + 1, Iclass_AE_S32X2_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2_XP_args, + 1, Iclass_AE_S32X2_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2RNG_I_args, + 2, Iclass_AE_S32X2RNG_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2RNG_IP_args, + 2, Iclass_AE_S32X2RNG_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2RNG_X_args, + 2, Iclass_AE_S32X2RNG_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2RNG_XP_args, + 2, Iclass_AE_S32X2RNG_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_XC_args, + 3, Iclass_AE_S16X4_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_XC1_args, + 3, Iclass_AE_S16X4_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_I_args, + 1, Iclass_AE_S16X4_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_IP_args, + 1, Iclass_AE_S16X4_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_X_args, + 1, Iclass_AE_S16X4_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_XP_args, + 1, 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Iclass_AE_S32F24_L_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32F24_L_XC1_args, + 3, Iclass_AE_S32F24_L_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32F24_L_I_args, + 1, Iclass_AE_S32F24_L_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32F24_L_IP_args, + 1, Iclass_AE_S32F24_L_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32F24_L_X_args, + 1, Iclass_AE_S32F24_L_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32F24_L_XP_args, + 1, Iclass_AE_S32F24_L_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32_L_XC_args, + 3, Iclass_AE_S32_L_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32_L_XC1_args, + 3, Iclass_AE_S32_L_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32_L_I_args, + 1, Iclass_AE_S32_L_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32_L_IP_args, + 1, Iclass_AE_S32_L_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32_L_X_args, + 1, Iclass_AE_S32_L_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32_L_XP_args, + 1, Iclass_AE_S32_L_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32_H_XC_args, + 3, Iclass_AE_S32_H_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32_H_XC1_args, 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Iclass_AE_LA24NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24X2POS_PC_args, + 3, Iclass_AE_LA24X2POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24X2NEG_PC_args, + 3, Iclass_AE_LA24X2NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24X2POS_PC1_args, + 3, Iclass_AE_LA24X2POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24X2NEG_PC1_args, + 3, Iclass_AE_LA24X2NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2POS_PC_args, + 3, Iclass_AE_LA32X2POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2NEG_PC_args, + 3, Iclass_AE_LA32X2NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2POS_PC1_args, + 3, Iclass_AE_LA32X2POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2NEG_PC1_args, + 3, Iclass_AE_LA32X2NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2POS_PC2_args, + 3, Iclass_AE_LA32X2POS_PC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4POS_PC_args, + 3, Iclass_AE_LA16X4POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4NEG_PC_args, + 3, Iclass_AE_LA16X4NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4POS_PC1_args, + 3, Iclass_AE_LA16X4POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4NEG_PC1_args, + 3, Iclass_AE_LA16X4NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4POS_PC2_args, + 3, Iclass_AE_LA16X4POS_PC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8POS_PC_args, + 3, Iclass_AE_LA8X8POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8NEG_PC_args, + 3, Iclass_AE_LA8X8NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8POS_PC1_args, + 3, Iclass_AE_LA8X8POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8NEG_PC1_args, + 3, Iclass_AE_LA8X8NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8POS_PC2_args, + 3, Iclass_AE_LA8X8POS_PC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2X2POS_PC_args, + 3, Iclass_AE_LA32X2X2POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2X2POS_PC1_args, + 3, Iclass_AE_LA32X2X2POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2X2POS_PC2_args, + 3, Iclass_AE_LA32X2X2POS_PC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4X2POS_PC_args, + 3, Iclass_AE_LA16X4X2POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4X2POS_PC1_args, + 3, Iclass_AE_LA16X4X2POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4X2POS_PC2_args, + 3, Iclass_AE_LA16X4X2POS_PC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8X2POS_PC_args, + 3, Iclass_AE_LA8X8X2POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8X2POS_PC1_args, + 3, Iclass_AE_LA8X8X2POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA8X8X2POS_PC2_args, + 3, Iclass_AE_LA8X8X2POS_PC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_SA64POS_FP_args, + 1, Iclass_AE_SA64POS_FP_stateArgs, 0, 0 }, + { 2, Iclass_AE_SA64NEG_FP_args, + 1, Iclass_AE_SA64NEG_FP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IC_args, + 3, Iclass_AE_LA32X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IC1_args, + 3, Iclass_AE_LA32X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IC2_args, + 3, Iclass_AE_LA32X2_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IP_args, + 1, Iclass_AE_LA32X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_RIP_args, + 1, Iclass_AE_LA32X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_RIC_args, + 3, Iclass_AE_LA32X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_RIC1_args, + 3, Iclass_AE_LA32X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IC_args, + 3, Iclass_AE_LA16X4_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IC1_args, + 3, Iclass_AE_LA16X4_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IC2_args, + 3, Iclass_AE_LA16X4_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IP_args, + 1, Iclass_AE_LA16X4_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_RIP_args, + 1, Iclass_AE_LA16X4_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_RIC_args, + 3, Iclass_AE_LA16X4_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_RIC1_args, + 3, Iclass_AE_LA16X4_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_IC_args, + 3, Iclass_AE_LA8X8_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_IC1_args, + 3, Iclass_AE_LA8X8_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_IC2_args, + 3, Iclass_AE_LA8X8_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_IP_args, + 1, Iclass_AE_LA8X8_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_RIP_args, + 1, Iclass_AE_LA8X8_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_RIC_args, + 3, Iclass_AE_LA8X8_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA8X8_RIC1_args, + 3, Iclass_AE_LA8X8_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_IC_args, + 3, Iclass_AE_LA32X2F24_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_IC1_args, + 3, Iclass_AE_LA32X2F24_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_IP_args, + 1, Iclass_AE_LA32X2F24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_RIP_args, + 1, Iclass_AE_LA32X2F24_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_RIC_args, + 3, Iclass_AE_LA32X2F24_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_RIC1_args, + 3, Iclass_AE_LA32X2F24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_IC_args, + 3, Iclass_AE_LA24_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_IC1_args, + 3, Iclass_AE_LA24_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_IP_args, + 1, Iclass_AE_LA24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_RIP_args, + 1, Iclass_AE_LA24_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_RIC_args, + 3, Iclass_AE_LA24_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_RIC1_args, + 3, Iclass_AE_LA24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_IC_args, + 3, Iclass_AE_LA24X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_IC1_args, + 3, Iclass_AE_LA24X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_IP_args, + 1, Iclass_AE_LA24X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_RIP_args, + 1, Iclass_AE_LA24X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_RIC_args, + 3, Iclass_AE_LA24X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_RIC1_args, + 3, Iclass_AE_LA24X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IC_args, + 3, Iclass_AE_SA32X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IC1_args, + 3, Iclass_AE_SA32X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IC2_args, + 3, Iclass_AE_SA32X2_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IP_args, + 1, Iclass_AE_SA32X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_RIP_args, + 1, Iclass_AE_SA32X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_RIC_args, + 3, Iclass_AE_SA32X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_RIC1_args, + 3, Iclass_AE_SA32X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IC_args, + 3, Iclass_AE_SA16X4_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IC1_args, + 3, Iclass_AE_SA16X4_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IC2_args, + 3, Iclass_AE_SA16X4_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IP_args, + 1, Iclass_AE_SA16X4_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_RIP_args, + 1, Iclass_AE_SA16X4_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_RIC_args, + 3, Iclass_AE_SA16X4_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_RIC1_args, + 3, Iclass_AE_SA16X4_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_IC_args, + 3, Iclass_AE_SA8X8_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_IC1_args, + 3, Iclass_AE_SA8X8_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_IC2_args, + 3, Iclass_AE_SA8X8_IC2_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_IP_args, + 1, Iclass_AE_SA8X8_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_RIP_args, + 1, Iclass_AE_SA8X8_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_RIC_args, + 3, Iclass_AE_SA8X8_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA8X8_RIC1_args, + 3, Iclass_AE_SA8X8_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_IC_args, + 3, Iclass_AE_SA32X2F24_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_IC1_args, + 3, Iclass_AE_SA32X2F24_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_IP_args, + 1, Iclass_AE_SA32X2F24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_RIP_args, + 1, Iclass_AE_SA32X2F24_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_RIC_args, + 3, Iclass_AE_SA32X2F24_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_RIC1_args, + 3, Iclass_AE_SA32X2F24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_IC_args, + 3, Iclass_AE_SA24_L_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_IC1_args, + 3, Iclass_AE_SA24_L_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_IP_args, + 1, Iclass_AE_SA24_L_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_RIP_args, + 1, Iclass_AE_SA24_L_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_RIC_args, + 3, Iclass_AE_SA24_L_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_RIC1_args, + 3, Iclass_AE_SA24_L_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_IC_args, + 3, Iclass_AE_SA24X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_IC1_args, + 3, Iclass_AE_SA24X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_IP_args, + 1, Iclass_AE_SA24X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_RIP_args, + 1, Iclass_AE_SA24X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_RIC_args, + 3, Iclass_AE_SA24X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_RIC1_args, + 3, Iclass_AE_SA24X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDICIRC_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_ADDCIRC_XC2_args, + 3, Iclass_AE_ADDCIRC_XC2_stateArgs, 0, 0 }, + { 2, Iclass_AE_ADDCIRC_XC1_args, + 3, Iclass_AE_ADDCIRC_XC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_ADDCIRC_XC_args, + 3, Iclass_AE_ADDCIRC_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_I_args, + 2, Iclass_AE_S32RA64S_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_IP_args, + 2, Iclass_AE_S32RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_X_args, + 2, Iclass_AE_S32RA64S_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_XP_args, + 2, Iclass_AE_S32RA64S_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_XC_args, + 4, Iclass_AE_S32RA64S_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_XC1_args, + 4, Iclass_AE_S32RA64S_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_I_args, + 2, Iclass_AE_S24RA64S_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_IP_args, + 2, Iclass_AE_S24RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_X_args, + 2, Iclass_AE_S24RA64S_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_XP_args, + 2, Iclass_AE_S24RA64S_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_XC_args, + 4, Iclass_AE_S24RA64S_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_XC1_args, + 4, Iclass_AE_S24RA64S_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2RA64S_IP_args, + 2, Iclass_AE_S32X2RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24X2RA64S_IP_args, + 2, Iclass_AE_S24X2RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4RA32S_IP_args, + 2, Iclass_AE_S16X4RA32S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDBRBA32_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_S32X2_L_IP_args, + 1, Iclass_AE_S32X2_L_IP_stateArgs, 0, 0 }, + { 2, Iclass_AE_BITSWAP_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MUL32JS_args, + 1, Iclass_AE_MUL32JS_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUB32S_args, + 2, Iclass_AE_ADDANDSUB32S_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUB32JS_args, + 2, Iclass_AE_ADDANDSUB32JS_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUBRNG32_args, + 2, Iclass_AE_ADDANDSUBRNG32_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUBRNG32_H_args, + 2, Iclass_AE_ADDANDSUBRNG32_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUBRNG32_L_args, + 2, Iclass_AE_ADDANDSUBRNG32_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDRNG32_args, + 2, Iclass_AE_ADDRNG32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUBRNG32_args, + 2, Iclass_AE_SUBRNG32_stateArgs, 0, 0 }, + { 1, Iclass_AE_RNG32X2_args, + 2, Iclass_AE_RNG32X2_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL16I_args, + 1, Iclass_AE_SEL16I_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL16I_N_args, + 1, Iclass_AE_SEL16I_N_stateArgs, 0, 0 }, + { 2, Iclass_AE_SHORTSWAP_args, + 1, Iclass_AE_SHORTSWAP_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAB4_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVAB2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVAB_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVBA_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_MOVBA1X2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVBA4_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVBA2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVB2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVB4_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_MOVT16X4_args, + 1, Iclass_AE_MOVT16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVF16X4_args, + 1, Iclass_AE_MOVF16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVT32X2_args, + 1, Iclass_AE_MOVT32X2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVF32X2_args, + 1, Iclass_AE_MOVF32X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVSARA7X2_args, + 2, Iclass_AE_MOVSARA7X2_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVSARD7_args, + 2, Iclass_AE_MOVSARD7_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVASAR_args, + 2, Iclass_AE_MOVASAR_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVDA32X2_args, + 1, Iclass_AE_MOVDA32X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVDA32_args, + 1, Iclass_AE_MOVDA32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVDA16X2_args, + 1, Iclass_AE_MOVDA16X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVDA16_args, + 1, Iclass_AE_MOVDA16_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVI_args, + 1, Iclass_AE_MOVI_stateArgs, 0, 0 }, + { 3, Iclass_AE_TRUNCP24A32X2_args, + 1, Iclass_AE_TRUNCP24A32X2_stateArgs, 0, 0 }, + { 3, Iclass_AE_SAT16X4_args, + 2, Iclass_AE_SAT16X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT32X2F16_32_args, + 1, Iclass_AE_CVT32X2F16_32_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT32X2F16_10_args, + 1, Iclass_AE_CVT32X2F16_10_stateArgs, 0, 0 }, + { 2, Iclass_AE_SEXT32X2D16_32_args, + 1, Iclass_AE_SEXT32X2D16_32_stateArgs, 0, 0 }, + { 2, Iclass_AE_SEXT32X2D16_10_args, + 1, Iclass_AE_SEXT32X2D16_10_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTA32F24S_L_args, + 1, Iclass_AE_CVTA32F24S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTA32F24S_H_args, + 1, Iclass_AE_CVTA32F24S_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_LL_args, + 1, Iclass_AE_CVTP24A16X2_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_LH_args, + 1, Iclass_AE_CVTP24A16X2_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_HL_args, + 1, Iclass_AE_CVTP24A16X2_HL_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_HH_args, + 1, Iclass_AE_CVTP24A16X2_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_TRUNCP24Q48X2_args, + 1, Iclass_AE_TRUNCP24Q48X2_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCA32X2F64S_args, + 2, Iclass_AE_TRUNCA32X2F64S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCI32X2F64S_args, + 2, Iclass_AE_TRUNCI32X2F64S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCA32F64S_L_args, + 2, Iclass_AE_TRUNCA32F64S_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCI32F64S_L_args, + 2, Iclass_AE_TRUNCI32F64S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCP16_args, + 1, Iclass_AE_TRUNCP16_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F64SSYM_args, + 2, Iclass_AE_ROUND32X2F64SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F64SASYM_args, + 2, Iclass_AE_ROUND32X2F64SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F48SSYM_args, + 2, Iclass_AE_ROUND32X2F48SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F48SASYM_args, + 2, Iclass_AE_ROUND32X2F48SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND16X4F32SSYM_args, + 2, Iclass_AE_ROUND16X4F32SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND16X4F32SASYM_args, + 2, Iclass_AE_ROUND16X4F32SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND24X2F48SSYM_args, + 2, Iclass_AE_ROUND24X2F48SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND24X2F48SASYM_args, + 2, Iclass_AE_ROUND24X2F48SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUNDSP16Q48X2SYM_args, + 2, Iclass_AE_ROUNDSP16Q48X2SYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUNDSP16Q48X2ASYM_args, + 2, Iclass_AE_ROUNDSP16Q48X2ASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_MINABS32S_args, + 2, Iclass_AE_MINABS32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAXABS32S_args, + 2, Iclass_AE_MAXABS32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSP16F24SYM_args, + 2, Iclass_AE_ROUNDSP16F24SYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSP16F24ASYM_args, + 2, Iclass_AE_ROUNDSP16F24ASYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOV_args, + 1, Iclass_AE_MOV_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVT64_args, + 1, Iclass_AE_MOVT64_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVF64_args, + 1, Iclass_AE_MOVF64_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTQ56A32S_args, + 1, Iclass_AE_CVTQ56A32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT48A32_args, + 1, Iclass_AE_CVT48A32_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT64A32_args, + 1, Iclass_AE_CVT64A32_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTQ56P32S_L_args, + 1, Iclass_AE_CVTQ56P32S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTQ56P32S_H_args, + 1, Iclass_AE_CVTQ56P32S_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT64F32_H_args, + 1, Iclass_AE_CVT64F32_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT48F32_L_args, + 1, Iclass_AE_CVT48F32_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT48F32_H_args, + 1, Iclass_AE_CVT48F32_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_SAT48S_args, + 2, Iclass_AE_SAT48S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SATQ56S_args, + 2, Iclass_AE_SATQ56S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SAT24S_args, + 2, Iclass_AE_SAT24S_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCQ32_args, + 1, Iclass_AE_TRUNCQ32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MINABS64S_args, + 2, Iclass_AE_MINABS64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAXABS64S_args, + 2, Iclass_AE_MAXABS64S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSQ32F48SYM_args, + 2, Iclass_AE_ROUNDSQ32F48SYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSQ32F48ASYM_args, + 2, Iclass_AE_ROUNDSQ32F48ASYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCA32Q48_args, + 1, Iclass_AE_TRUNCA32Q48_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD32_L_args, + 1, Iclass_AE_MOVAD32_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD32_H_args, + 1, Iclass_AE_MOVAD32_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_3_args, + 1, Iclass_AE_MOVAD16_3_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_2_args, + 1, Iclass_AE_MOVAD16_2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_1_args, + 1, Iclass_AE_MOVAD16_1_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_0_args, + 1, Iclass_AE_MOVAD16_0_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRA64_32_args, + 1, Iclass_AE_SRA64_32_stateArgs, 0, 0 }, + { 3, Iclass_AE_PKSR32_args, + 2, Iclass_AE_PKSR32_stateArgs, 0, 0 }, + { 3, Iclass_AE_PKSR24_args, + 2, Iclass_AE_PKSR24_stateArgs, 0, 0 }, + { 3, Iclass_AE_PKSRF32_args, + 2, Iclass_AE_PKSRF32_stateArgs, 0, 0 }, + { 3, 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2, Iclass_AE_SATU8X4X32_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND8X8F16SSYM_args, + 2, Iclass_AE_ROUND8X8F16SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND8X8F16SASYM_args, + 2, Iclass_AE_ROUND8X8F16SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND8X4F32SSYM_L_args, + 2, Iclass_AE_ROUND8X4F32SSYM_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND8X4F32SASYM_L_args, + 2, Iclass_AE_ROUND8X4F32SASYM_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVDA8_args, + 1, Iclass_AE_MOVDA8_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVAD8_args, + 1, Iclass_AE_MOVAD8_stateArgs, 0, 0 }, + { 4, Iclass_AE_MOVDX2_args, + 1, Iclass_AE_MOVDX2_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUB32J_args, + 1, Iclass_AE_ADDANDSUB32J_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDW8_args, + 1, Iclass_AE_ADDW8_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDW16_args, + 1, Iclass_AE_ADDW16_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDW32_args, + 1, Iclass_AE_ADDW32_stateArgs, 0, 0 }, + { 4, Iclass_AE_SUBW8_args, + 1, Iclass_AE_SUBW8_stateArgs, 0, 0 }, + { 4, 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Iclass_AE_MULAFP32X2S_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSFP32X2S_HL_LH_args, + 2, Iclass_AE_MULSFP32X2S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZAAF2D32S_HH_LL_args, + 2, Iclass_AE_MULZAAF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZASF2D32S_HH_LL_args, + 2, Iclass_AE_MULZASF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSAF2D32S_HH_LL_args, + 2, Iclass_AE_MULZSAF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSSF2D32S_HH_LL_args, + 2, Iclass_AE_MULZSSF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAAF2D32S_HH_LL_args, + 2, Iclass_AE_MULAAF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULASF2D32S_HH_LL_args, + 2, Iclass_AE_MULASF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSAF2D32S_HH_LL_args, + 2, Iclass_AE_MULSAF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSSF2D32S_HH_LL_args, + 2, Iclass_AE_MULSSF2D32S_HH_LL_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZAAF2D32S_HL_LH_args, + 2, Iclass_AE_MULZAAF2D32S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZASF2D32S_HL_LH_args, + 2, Iclass_AE_MULZASF2D32S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSAF2D32S_HL_LH_args, + 2, Iclass_AE_MULZSAF2D32S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSSF2D32S_HL_LH_args, + 2, Iclass_AE_MULZSSF2D32S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAAF2D32S_HL_LH_args, + 2, Iclass_AE_MULAAF2D32S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULASF2D32S_HL_LH_args, + 2, Iclass_AE_MULASF2D32S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSAF2D32S_HL_LH_args, + 2, Iclass_AE_MULSAF2D32S_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSSF2D32S_HL_LH_args, + 2, Iclass_AE_MULSSF2D32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32S_HH_args, + 2, Iclass_AE_MUL32S_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA32S_HH_args, + 2, Iclass_AE_MULA32S_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32S_HH_args, + 2, Iclass_AE_MULS32S_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32S_LL_args, + 2, Iclass_AE_MUL32S_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA32S_LL_args, + 2, Iclass_AE_MULA32S_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32S_LL_args, + 2, Iclass_AE_MULS32S_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32S_HL_args, + 2, Iclass_AE_MUL32S_HL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA32S_HL_args, + 2, Iclass_AE_MULA32S_HL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32S_HL_args, + 2, Iclass_AE_MULS32S_HL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32S_LH_args, + 2, Iclass_AE_MUL32S_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA32S_LH_args, + 2, Iclass_AE_MULA32S_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32S_LH_args, + 2, Iclass_AE_MULS32S_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MUL32X2S_HH_LL_args, + 2, Iclass_AE_MUL32X2S_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULA32X2S_HH_LL_args, + 2, Iclass_AE_MULA32X2S_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULS32X2S_HH_LL_args, + 2, Iclass_AE_MULS32X2S_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MUL32X2S_HL_LH_args, + 2, Iclass_AE_MUL32X2S_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULA32X2S_HL_LH_args, + 2, Iclass_AE_MULA32X2S_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULS32X2S_HL_LH_args, + 2, Iclass_AE_MULS32X2S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZAAD32S_HH_LL_args, + 2, Iclass_AE_MULZAAD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZASD32S_HH_LL_args, + 2, Iclass_AE_MULZASD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZSAD32S_HH_LL_args, + 2, Iclass_AE_MULZSAD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZSSD32S_HH_LL_args, + 2, Iclass_AE_MULZSSD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAAD32S_HH_LL_args, + 2, Iclass_AE_MULAAD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULASD32S_HH_LL_args, + 2, Iclass_AE_MULASD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSAD32S_HH_LL_args, + 2, Iclass_AE_MULSAD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSSD32S_HH_LL_args, + 2, Iclass_AE_MULSSD32S_HH_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZAAD32S_HL_LH_args, + 2, Iclass_AE_MULZAAD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZASD32S_HL_LH_args, + 2, Iclass_AE_MULZASD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZSAD32S_HL_LH_args, + 2, Iclass_AE_MULZSAD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZSSD32S_HL_LH_args, + 2, Iclass_AE_MULZSSD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAAD32S_HL_LH_args, + 2, Iclass_AE_MULAAD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULASD32S_HL_LH_args, + 2, Iclass_AE_MULASD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSAD32S_HL_LH_args, + 2, Iclass_AE_MULSAD32S_HL_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULSSD32S_HL_LH_args, + 2, Iclass_AE_MULSSD32S_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULF32X2RA_HH_LL_args, + 1, Iclass_AE_MULF32X2RA_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAF32X2RA_HH_LL_args, + 1, Iclass_AE_MULAF32X2RA_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSF32X2RA_HH_LL_args, + 1, Iclass_AE_MULSF32X2RA_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULF32X2RA_HL_LH_args, + 1, Iclass_AE_MULF32X2RA_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAF32X2RA_HL_LH_args, + 1, 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0 }, + { 6, Iclass_AE_MULZASF2D32RA_HL_LH_args, + 1, Iclass_AE_MULZASF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSAF2D32RA_HL_LH_args, + 1, Iclass_AE_MULZSAF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULZSSF2D32RA_HL_LH_args, + 1, Iclass_AE_MULZSSF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAAF2D32RA_HL_LH_args, + 1, Iclass_AE_MULAAF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULASF2D32RA_HL_LH_args, + 1, Iclass_AE_MULASF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSAF2D32RA_HL_LH_args, + 1, Iclass_AE_MULSAF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULSSF2D32RA_HL_LH_args, + 1, Iclass_AE_MULSSF2D32RA_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULF32X2R_HH_LL_args, + 1, Iclass_AE_MULF32X2R_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAF32X2R_HH_LL_args, + 1, Iclass_AE_MULAF32X2R_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSF32X2R_HH_LL_args, + 1, Iclass_AE_MULSF32X2R_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULF32X2R_HL_LH_args, + 1, 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0, 0 }, + { 4, Iclass_AE_SEL8X8_args, + 1, Iclass_AE_SEL8X8_stateArgs, 0, 0 }, + { 3, Iclass_AE_SHFL8X8_args, + 1, Iclass_AE_SHFL8X8_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL16X4_args, + 1, Iclass_AE_SEL16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_SHFL16X4_args, + 1, Iclass_AE_SHFL16X4_stateArgs, 0, 0 }, + { 5, Iclass_AE_DSEL8X8_args, + 1, Iclass_AE_DSEL8X8_stateArgs, 0, 0 }, + { 5, Iclass_AE_DSEL16X4_args, + 1, Iclass_AE_DSEL16X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL8X8I_args, + 1, Iclass_AE_SEL8X8I_stateArgs, 0, 0 }, + { 2, Iclass_AE_RMAX8X8_args, + 1, Iclass_AE_RMAX8X8_stateArgs, 0, 0 }, + { 2, Iclass_AE_RMIN8X8_args, + 1, Iclass_AE_RMIN8X8_stateArgs, 0, 0 }, + { 2, Iclass_AE_RMAX16X4_args, + 1, Iclass_AE_RMAX16X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_RMIN16X4_args, + 1, Iclass_AE_RMIN16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_SORT16X4_args, + 1, Iclass_AE_SORT16X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADD8X8_H_args, + 1, Iclass_AE_RADD8X8_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADDA8X8_H_args, + 1, Iclass_AE_RADDA8X8_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADD8X8_L_args, + 1, Iclass_AE_RADD8X8_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADDA8X8_L_args, + 1, Iclass_AE_RADDA8X8_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADD16X4_args, + 1, Iclass_AE_RADD16X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_RADDA16X4_args, + 1, Iclass_AE_RADDA16X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMAX8X8_H_args, + 1, Iclass_AE_BMAX8X8_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMAX8X8_L_args, + 1, Iclass_AE_BMAX8X8_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMIN8X8_H_args, + 1, Iclass_AE_BMIN8X8_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMIN8X8_L_args, + 1, Iclass_AE_BMIN8X8_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMAX16X4_args, + 1, Iclass_AE_BMAX16X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMIN16X4_args, + 1, Iclass_AE_BMIN16X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMAX32X2_args, + 1, Iclass_AE_BMAX32X2_stateArgs, 0, 0 }, + { 4, Iclass_AE_BMIN32X2_args, + 1, Iclass_AE_BMIN32X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_ADDINV16S_args, + 2, Iclass_AE_ADDINV16S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ADDINV32S_args, + 2, Iclass_AE_ADDINV32S_stateArgs, 0, 0 }, + { 6, Iclass_AE_MOVT16X8_args, + 1, Iclass_AE_MOVT16X8_stateArgs, 0, 0 }, + { 5, Iclass_AE_MOVT8X16_H_args, + 1, Iclass_AE_MOVT8X16_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MOVT8X16_L_args, + 1, Iclass_AE_MOVT8X16_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVBD1X4_args, + 1, Iclass_AE_MOVBD1X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVBD1X2_args, + 1, Iclass_AE_MOVBD1X2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVNEG32S_T_args, + 1, Iclass_AE_MOVNEG32S_T_stateArgs, 0, 0 }, + { 4, Iclass_AE_MOVDEXT_args, + 1, Iclass_AE_MOVDEXT_stateArgs, 0, 0 }, + { 4, Iclass_AE_MOVADEXT_H_args, + 1, Iclass_AE_MOVADEXT_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_MOVADEXT_L_args, + 1, Iclass_AE_MOVADEXT_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_NSA16X4_args, + 1, Iclass_AE_NSA16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_NSAZ32X4_args, + 1, Iclass_AE_NSAZ32X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_NSA32X4_args, + 1, Iclass_AE_NSA32X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCI16X4F32S_args, + 2, Iclass_AE_TRUNCI16X4F32S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCI16X4F64S_args, + 2, Iclass_AE_TRUNCI16X4F64S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCA16X4F32S_args, + 2, Iclass_AE_TRUNCA16X4F32S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCA16X4F64S_args, + 2, Iclass_AE_TRUNCA16X4F64S_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDC32_args, + 1, Iclass_AE_ADDC32_stateArgs, 0, 0 }, + { 4, Iclass_AE_SUBC32_args, + 1, Iclass_AE_SUBC32_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDC32U_args, + 1, Iclass_AE_ADDC32U_stateArgs, 0, 0 }, + { 4, Iclass_AE_SUBC32U_args, + 1, Iclass_AE_SUBC32U_stateArgs, 0, 0 }, + { 3, Iclass_AE_EXPADD16_H_args, + 1, Iclass_AE_EXPADD16_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_EXPSUB16_H_args, + 1, Iclass_AE_EXPSUB16_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_EXPADD16_L_args, + 1, Iclass_AE_EXPADD16_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_EXPSUB16_L_args, + 1, Iclass_AE_EXPSUB16_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDCEXP32_H_args, + 1, Iclass_AE_ADDCEXP32_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDCEXP32_L_args, + 1, Iclass_AE_ADDCEXP32_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_CALCRNG16_args, + 2, Iclass_AE_CALCRNG16_stateArgs, 0, 0 }, + { 4, Iclass_AE_CALCRNG32_args, + 2, Iclass_AE_CALCRNG32_stateArgs, 0, 0 }, + { 2, Iclass_AE_RNG32X4_args, + 2, Iclass_AE_RNG32X4_stateArgs, 0, 0 }, + { 5, Iclass_AE_LAV8X8X2_XP_args, + 1, Iclass_AE_LAV8X8X2_XP_stateArgs, 0, 0 }, + { 5, Iclass_AE_LAV16X4X2_XP_args, + 1, Iclass_AE_LAV16X4X2_XP_stateArgs, 0, 0 }, + { 5, Iclass_AE_SAV8X8X2_XP_args, + 1, Iclass_AE_SAV8X8X2_XP_stateArgs, 0, 0 }, + { 5, Iclass_AE_SAV16X4X2_XP_args, + 1, Iclass_AE_SAV16X4X2_XP_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVZBVCDR_args, + 3, Iclass_AE_MOVZBVCDR_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVDRZBVC_args, + 3, Iclass_AE_MOVDRZBVC_stateArgs, 0, 0 }, + { 6, Iclass_AE_LAVUNSQZ8X8_XP_args, + 1, Iclass_AE_LAVUNSQZ8X8_XP_stateArgs, 0, 0 }, + { 6, Iclass_AE_LAVUNSQZ16X4_XP_args, + 1, Iclass_AE_LAVUNSQZ16X4_XP_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL8Q8X8_args, + 1, Iclass_AE_MUL8Q8X8_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA8Q8X8_args, + 1, Iclass_AE_MULA8Q8X8_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL8Q4X16_args, + 1, Iclass_AE_MUL8Q4X16_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA8Q4X16_args, + 1, Iclass_AE_MULA8Q4X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL8Q8X16_args, + 1, Iclass_AE_MUL8Q8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA8Q8X16_args, + 1, Iclass_AE_MULA8Q8X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MUL8QW8X16_args, + 1, Iclass_AE_MUL8QW8X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MULA8QW8X16_args, + 1, Iclass_AE_MULA8QW8X16_stateArgs, 0, 0 }, + { 9, Iclass_AE_MUL4O8X8_args, + 1, Iclass_AE_MUL4O8X8_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULA4O8X8_args, + 1, Iclass_AE_MULA4O8X8_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O4X16_args, + 1, Iclass_AE_MUL4O4X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O4X16_args, + 1, Iclass_AE_MULA4O4X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MUL4O8X16_args, + 1, Iclass_AE_MUL4O8X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MULA4O8X16_args, + 1, Iclass_AE_MULA4O8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4QW8X16_args, + 1, Iclass_AE_MUL4QW8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4QW8X16_args, + 1, Iclass_AE_MULA4QW8X16_stateArgs, 0, 0 }, + { 5, Iclass_AE_MUL8Q8X8CNV_L_args, + 1, Iclass_AE_MUL8Q8X8CNV_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MUL8Q8X8CNV_H_args, + 1, Iclass_AE_MUL8Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULA8Q8X8CNV_L_args, + 1, Iclass_AE_MULA8Q8X8CNV_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULA8Q8X8CNV_H_args, + 1, Iclass_AE_MULA8Q8X8CNV_H_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL8Q8X16CNV_args, + 1, Iclass_AE_MUL8Q8X16CNV_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA8Q8X16CNV_args, + 1, Iclass_AE_MULA8Q8X16CNV_stateArgs, 0, 0 }, + { 5, Iclass_AE_MUL2X4Q8X8CNV_H_args, + 1, Iclass_AE_MUL2X4Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULA2X4Q8X8CNV_H_args, + 1, Iclass_AE_MULA2X4Q8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL2X4Q8X8CNV_L_args, + 1, Iclass_AE_MUL2X4Q8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA2X4Q8X8CNV_L_args, + 1, Iclass_AE_MULA2X4Q8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL2X4Q8X16CNV_args, + 1, Iclass_AE_MUL2X4Q8X16CNV_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA2X4Q8X16CNV_args, + 1, Iclass_AE_MULA2X4Q8X16CNV_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULQQ8X16CNV_args, + 1, Iclass_AE_MULQQ8X16CNV_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAQQ8X16CNV_args, + 1, Iclass_AE_MULAQQ8X16CNV_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL4O8X8CNV_H_args, + 1, Iclass_AE_MUL4O8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA4O8X8CNV_H_args, + 1, Iclass_AE_MULA4O8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL4O8X8CNV_L_args, + 1, Iclass_AE_MUL4O8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA4O8X8CNV_L_args, + 1, Iclass_AE_MULA4O8X8CNV_L_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O8X16CNV_H_args, + 1, Iclass_AE_MUL4O8X16CNV_H_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O8X16CNV_H_args, + 1, Iclass_AE_MULA4O8X16CNV_H_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O8X16CNV_L_args, + 1, Iclass_AE_MUL4O8X16CNV_L_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O8X16CNV_L_args, + 1, Iclass_AE_MULA4O8X16CNV_L_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL8Q4X16CNV_H_args, + 1, Iclass_AE_MUL8Q4X16CNV_H_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA8Q4X16CNV_H_args, + 1, Iclass_AE_MULA8Q4X16CNV_H_stateArgs, 0, 0 }, + { 6, Iclass_AE_MUL8Q4X16CNV_L_args, + 1, Iclass_AE_MUL8Q4X16CNV_L_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULA8Q4X16CNV_L_args, + 1, Iclass_AE_MULA8Q4X16CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL2X4Q4X16CNV_H_args, + 1, Iclass_AE_MUL2X4Q4X16CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA2X4Q4X16CNV_H_args, + 1, Iclass_AE_MULA2X4Q4X16CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MUL2X4Q4X16CNV_L_args, + 1, Iclass_AE_MUL2X4Q4X16CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULA2X4Q4X16CNV_L_args, + 1, Iclass_AE_MULA2X4Q4X16CNV_L_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULQQ4X16CNV_H_args, + 1, Iclass_AE_MULQQ4X16CNV_H_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAQQ4X16CNV_H_args, + 1, Iclass_AE_MULAQQ4X16CNV_H_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULQQ4X16CNV_L_args, + 1, Iclass_AE_MULQQ4X16CNV_L_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAQQ4X16CNV_L_args, + 1, Iclass_AE_MULAQQ4X16CNV_L_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O4X16CNV_HH_args, + 1, Iclass_AE_MUL4O4X16CNV_HH_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O4X16CNV_HL_args, + 1, Iclass_AE_MUL4O4X16CNV_HL_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O4X16CNV_LH_args, + 1, Iclass_AE_MUL4O4X16CNV_LH_stateArgs, 0, 0 }, + { 8, Iclass_AE_MUL4O4X16CNV_LL_args, + 1, Iclass_AE_MUL4O4X16CNV_LL_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O4X16CNV_HH_args, + 1, Iclass_AE_MULA4O4X16CNV_HH_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O4X16CNV_HL_args, + 1, Iclass_AE_MULA4O4X16CNV_HL_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O4X16CNV_LH_args, + 1, Iclass_AE_MULA4O4X16CNV_LH_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULA4O4X16CNV_LL_args, + 1, Iclass_AE_MULA4O4X16CNV_LL_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUU8Q8X8_args, + 1, Iclass_AE_MULUU8Q8X8_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUU8Q8X8_args, + 1, Iclass_AE_MULAUU8Q8X8_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULUU4O8X8_args, + 1, Iclass_AE_MULUU4O8X8_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAUU4O8X8_args, + 1, Iclass_AE_MULAUU4O8X8_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULUU8Q8X8CNV_L_args, + 1, Iclass_AE_MULUU8Q8X8CNV_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAUU8Q8X8CNV_L_args, + 1, Iclass_AE_MULAUU8Q8X8CNV_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULUU8Q8X8CNV_H_args, + 1, Iclass_AE_MULUU8Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAUU8Q8X8CNV_H_args, + 1, Iclass_AE_MULAUU8Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULUU2X4Q8X8CNV_H_args, + 1, Iclass_AE_MULUU2X4Q8X8CNV_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAUU2X4Q8X8CNV_H_args, + 1, Iclass_AE_MULAUU2X4Q8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUU2X4Q8X8CNV_L_args, + 1, Iclass_AE_MULUU2X4Q8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUU2X4Q8X8CNV_L_args, + 1, Iclass_AE_MULAUU2X4Q8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUU4O8X8CNV_H_args, + 1, Iclass_AE_MULUU4O8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUU4O8X8CNV_H_args, + 1, Iclass_AE_MULAUU4O8X8CNV_H_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUU4O8X8CNV_L_args, + 1, Iclass_AE_MULUU4O8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUU4O8X8CNV_L_args, + 1, Iclass_AE_MULAUU4O8X8CNV_L_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULUS8Q8X8_args, + 1, Iclass_AE_MULUS8Q8X8_stateArgs, 0, 0 }, + { 7, Iclass_AE_MULAUS8Q8X8_args, + 1, Iclass_AE_MULAUS8Q8X8_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULUS8Q4X16_args, + 1, Iclass_AE_MULUS8Q4X16_stateArgs, 0, 0 }, + { 6, Iclass_AE_MULAUS8Q4X16_args, + 1, Iclass_AE_MULAUS8Q4X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULUS8Q8X16_args, + 1, Iclass_AE_MULUS8Q8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULAUS8Q8X16_args, + 1, Iclass_AE_MULAUS8Q8X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MULUS8QW8X16_args, + 1, Iclass_AE_MULUS8QW8X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MULAUS8QW8X16_args, + 1, Iclass_AE_MULAUS8QW8X16_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULUS4O8X8_args, + 1, Iclass_AE_MULUS4O8X8_stateArgs, 0, 0 }, + { 9, Iclass_AE_MULAUS4O8X8_args, + 1, Iclass_AE_MULAUS4O8X8_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULUS4O4X16_args, + 1, Iclass_AE_MULUS4O4X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULAUS4O4X16_args, + 1, Iclass_AE_MULAUS4O4X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MULUS4O8X16_args, + 1, Iclass_AE_MULUS4O8X16_stateArgs, 0, 0 }, + { 10, Iclass_AE_MULAUS4O8X16_args, + 1, Iclass_AE_MULAUS4O8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULUS4QW8X16_args, + 1, Iclass_AE_MULUS4QW8X16_stateArgs, 0, 0 }, + { 8, Iclass_AE_MULAUS4QW8X16_args, + 1, Iclass_AE_MULAUS4QW8X16_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULUS8Q8X8CNV_L_args, + 1, Iclass_AE_MULUS8Q8X8CNV_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAUS8Q8X8CNV_L_args, + 1, Iclass_AE_MULAUS8Q8X8CNV_L_stateArgs, 0, 0 }, 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+ { 3, Iclass_MAX_S_args, + 2, Iclass_MAX_S_stateArgs, 0, 0 }, + { 4, Iclass_MULMUX_S_args, + 6, Iclass_MULMUX_S_stateArgs, 0, 0 }, + { 4, Iclass_MADDMUX_S_args, + 6, Iclass_MADDMUX_S_stateArgs, 0, 0 }, + { 3, Iclass_TRUNC_S_args, + 3, Iclass_TRUNC_S_stateArgs, 0, 0 }, + { 3, Iclass_UTRUNC_S_args, + 3, Iclass_UTRUNC_S_stateArgs, 0, 0 }, + { 3, Iclass_TRUNC_SX2_args, + 3, Iclass_TRUNC_SX2_stateArgs, 0, 0 }, + { 3, Iclass_UTRUNC_SX2_args, + 3, Iclass_UTRUNC_SX2_stateArgs, 0, 0 }, + { 2, Iclass_FICEIL_S_args, + 2, Iclass_FICEIL_S_stateArgs, 0, 0 }, + { 2, Iclass_FIFLOOR_S_args, + 2, Iclass_FIFLOOR_S_stateArgs, 0, 0 }, + { 2, Iclass_FIRINT_S_args, + 4, Iclass_FIRINT_S_stateArgs, 0, 0 }, + { 2, Iclass_FIROUND_S_args, + 2, Iclass_FIROUND_S_stateArgs, 0, 0 }, + { 2, Iclass_FITRUNC_S_args, + 2, Iclass_FITRUNC_S_stateArgs, 0, 0 }, + { 3, Iclass_FLOAT_S_args, + 3, Iclass_FLOAT_S_stateArgs, 0, 0 }, + { 3, Iclass_UFLOAT_S_args, + 3, Iclass_UFLOAT_S_stateArgs, 0, 0 }, + { 3, Iclass_FLOAT_SX2_args, + 3, Iclass_FLOAT_SX2_stateArgs, 0, 0 }, + { 3, Iclass_UFLOAT_SX2_args, + 3, Iclass_UFLOAT_SX2_stateArgs, 0, 0 }, + { 2, Iclass_ABS_S_args, + 1, Iclass_ABS_S_stateArgs, 0, 0 }, + { 2, Iclass_NEG_S_args, + 1, Iclass_NEG_S_stateArgs, 0, 0 }, + { 2, Iclass_CONJC_S_args, + 1, Iclass_CONJC_S_stateArgs, 0, 0 }, + { 2, Iclass_MULJC_S_args, + 1, Iclass_MULJC_S_stateArgs, 0, 0 }, + { 2, Iclass_CONST_S_args, + 1, Iclass_CONST_S_stateArgs, 0, 0 }, + { 2, Iclass_CLSFY_S_args, + 1, Iclass_CLSFY_S_stateArgs, 0, 0 }, + { 3, Iclass_MINNUM_S_args, + 2, Iclass_MINNUM_S_stateArgs, 0, 0 }, + { 3, Iclass_MAXNUM_S_args, + 2, Iclass_MAXNUM_S_stateArgs, 0, 0 }, + { 4, Iclass_ADDANDSUB_S_args, + 5, Iclass_ADDANDSUB_S_stateArgs, 0, 0 }, + { 4, Iclass_ADDANDSUBJC_S_args, + 5, Iclass_ADDANDSUBJC_S_stateArgs, 0, 0 }, + { 3, Iclass_ADD_HL_LH_S_args, + 5, Iclass_ADD_HL_LH_S_stateArgs, 0, 0 }, + { 4, Iclass_MADDA_S_args, + 6, Iclass_MADDA_S_stateArgs, 0, 0 }, + { 3, Iclass_FREXP_S_args, + 1, Iclass_FREXP_S_stateArgs, 0, 0 }, + { 2, Iclass_FLOATEXP_S_args, + 1, Iclass_FLOATEXP_S_stateArgs, 0, 0 }, + { 3, Iclass_MINNUMABS_S_args, + 2, Iclass_MINNUMABS_S_stateArgs, 0, 0 }, + { 3, Iclass_MAXNUMABS_S_args, + 2, Iclass_MAXNUMABS_S_stateArgs, 0, 0 }, + { 5, Iclass_MULQ_S_args, + 6, Iclass_MULQ_S_stateArgs, 0, 0 }, + { 5, Iclass_MADDQ_S_args, + 6, Iclass_MADDQ_S_stateArgs, 0, 0 }, + { 5, Iclass_MSUBQ_S_args, + 6, Iclass_MSUBQ_S_stateArgs, 0, 0 }, + { 6, Iclass_MULMUXQ_S_args, + 6, Iclass_MULMUXQ_S_stateArgs, 0, 0 }, + { 6, Iclass_MADDMUXQ_S_args, + 6, Iclass_MADDMUXQ_S_stateArgs, 0, 0 }, + { 4, Iclass_BMAXNUM_S_args, + 2, Iclass_BMAXNUM_S_stateArgs, 0, 0 }, + { 4, Iclass_BMINNUM_S_args, + 2, Iclass_BMINNUM_S_stateArgs, 0, 0 }, + { 4, Iclass_BMAXNUMABS_S_args, + 2, Iclass_BMAXNUMABS_S_stateArgs, 0, 0 }, + { 4, Iclass_BMINNUMABS_S_args, + 2, Iclass_BMINNUMABS_S_stateArgs, 0, 0 }, + { 4, Iclass_ABS_SX2X2_args, + 1, Iclass_ABS_SX2X2_stateArgs, 0, 0 }, + { 4, Iclass_NEG_SX2X2_args, + 1, Iclass_NEG_SX2X2_stateArgs, 0, 0 }, + { 4, Iclass_CONJC_SX2X2_args, + 1, Iclass_CONJC_SX2X2_stateArgs, 0, 0 }, + { 4, Iclass_MULJC_SX2X2_args, + 1, Iclass_MULJC_SX2X2_stateArgs, 0, 0 }, + { 3, Iclass_CONST_SX2X2_args, + 1, Iclass_CONST_SX2X2_stateArgs, 0, 0 }, + { 6, Iclass_ADD_SX2X2_args, + 5, Iclass_ADD_SX2X2_stateArgs, 0, 0 }, + { 6, Iclass_SUB_SX2X2_args, + 5, Iclass_SUB_SX2X2_stateArgs, 0, 0 }, + { 6, Iclass_MUL_SX2X2_args, + 6, Iclass_MUL_SX2X2_stateArgs, 0, 0 }, + { 6, Iclass_MADD_SX2X2_args, + 6, Iclass_MADD_SX2X2_stateArgs, 0, 0 }, + { 6, Iclass_MSUB_SX2X2_args, + 6, Iclass_MSUB_SX2X2_stateArgs, 0, 0 }, + { 7, Iclass_MULMUX_SX2X2_args, + 6, Iclass_MULMUX_SX2X2_stateArgs, 0, 0 }, + { 7, Iclass_MADDMUX_SX2X2_args, + 6, Iclass_MADDMUX_SX2X2_stateArgs, 0, 0 }, + { 2, Iclass_ABS_H_args, + 1, Iclass_ABS_H_stateArgs, 0, 0 }, + { 2, Iclass_ADDEXP_H_args, + 1, Iclass_ADDEXP_H_stateArgs, 0, 0 }, + { 2, Iclass_ADDEXPM_H_args, + 1, Iclass_ADDEXPM_H_stateArgs, 0, 0 }, + { 2, Iclass_CLSFY_H_args, + 1, Iclass_CLSFY_H_stateArgs, 0, 0 }, + { 2, Iclass_CONJC_H_args, + 1, Iclass_CONJC_H_stateArgs, 0, 0 }, + { 2, Iclass_CONST_H_args, + 1, Iclass_CONST_H_stateArgs, 0, 0 }, + { 3, Iclass_MIN_H_args, + 2, Iclass_MIN_H_stateArgs, 0, 0 }, + { 3, Iclass_MAX_H_args, + 2, Iclass_MAX_H_stateArgs, 0, 0 }, + { 3, Iclass_MINNUM_H_args, + 2, Iclass_MINNUM_H_stateArgs, 0, 0 }, + { 3, Iclass_MAXNUM_H_args, + 2, Iclass_MAXNUM_H_stateArgs, 0, 0 }, + { 2, Iclass_MULJC_H_args, + 1, Iclass_MULJC_H_stateArgs, 0, 0 }, + { 2, Iclass_NEG_H_args, + 1, Iclass_NEG_H_stateArgs, 0, 0 }, + { 3, Iclass_OEQ_H_args, + 2, Iclass_OEQ_H_stateArgs, 0, 0 }, + { 3, Iclass_OLE_H_args, + 2, Iclass_OLE_H_stateArgs, 0, 0 }, + { 3, Iclass_OLT_H_args, + 2, Iclass_OLT_H_stateArgs, 0, 0 }, + { 3, Iclass_UEQ_H_args, + 2, Iclass_UEQ_H_stateArgs, 0, 0 }, + { 3, Iclass_ULE_H_args, + 2, Iclass_ULE_H_stateArgs, 0, 0 }, + { 3, Iclass_ULT_H_args, + 2, Iclass_ULT_H_stateArgs, 0, 0 }, + { 3, Iclass_UN_H_args, + 2, Iclass_UN_H_stateArgs, 0, 0 }, + { 2, Iclass_DIV0_H_args, + 1, Iclass_DIV0_H_stateArgs, 0, 0 }, + { 2, Iclass_FICEIL_H_args, + 2, Iclass_FICEIL_H_stateArgs, 0, 0 }, + { 2, Iclass_FIFLOOR_H_args, + 2, Iclass_FIFLOOR_H_stateArgs, 0, 0 }, + { 2, Iclass_FIRINT_H_args, + 4, Iclass_FIRINT_H_stateArgs, 0, 0 }, + { 2, Iclass_FIROUND_H_args, + 2, Iclass_FIROUND_H_stateArgs, 0, 0 }, + { 2, Iclass_FITRUNC_H_args, + 2, Iclass_FITRUNC_H_stateArgs, 0, 0 }, + { 2, Iclass_MKDADJ_H_args, + 3, Iclass_MKDADJ_H_stateArgs, 0, 0 }, + { 2, Iclass_MKSADJ_H_args, + 2, Iclass_MKSADJ_H_stateArgs, 0, 0 }, + { 2, Iclass_NEXP0_H_args, + 1, Iclass_NEXP0_H_stateArgs, 0, 0 }, + { 2, Iclass_NEXP01_H_args, + 1, Iclass_NEXP01_H_stateArgs, 0, 0 }, + { 2, Iclass_RECIP0_H_args, + 3, Iclass_RECIP0_H_stateArgs, 0, 0 }, + { 2, Iclass_RSQRT0_H_args, + 3, Iclass_RSQRT0_H_stateArgs, 0, 0 }, + { 2, Iclass_SQRT0_H_args, + 1, Iclass_SQRT0_H_stateArgs, 0, 0 }, + { 3, Iclass_FLOAT16_H_args, + 3, Iclass_FLOAT16_H_stateArgs, 0, 0 }, + { 3, Iclass_UFLOAT16_H_args, + 4, Iclass_UFLOAT16_H_stateArgs, 0, 0 }, + { 3, Iclass_TRUNC16_H_args, + 3, Iclass_TRUNC16_H_stateArgs, 0, 0 }, + { 3, Iclass_UTRUNC16_H_args, + 3, Iclass_UTRUNC16_H_stateArgs, 0, 0 }, + { 3, Iclass_FLOAT16_HX4_args, + 3, Iclass_FLOAT16_HX4_stateArgs, 0, 0 }, + { 3, Iclass_UFLOAT16_HX4_args, + 4, Iclass_UFLOAT16_HX4_stateArgs, 0, 0 }, + { 3, Iclass_TRUNC16_HX4_args, + 3, Iclass_TRUNC16_HX4_stateArgs, 0, 0 }, + { 3, Iclass_UTRUNC16_HX4_args, + 3, Iclass_UTRUNC16_HX4_stateArgs, 0, 0 }, + { 3, Iclass_ADD_H_args, + 5, Iclass_ADD_H_stateArgs, 0, 0 }, + { 3, Iclass_SUB_H_args, + 5, Iclass_SUB_H_stateArgs, 0, 0 }, + { 3, Iclass_MUL_H_args, + 6, Iclass_MUL_H_stateArgs, 0, 0 }, + { 3, Iclass_MADD_H_args, + 6, Iclass_MADD_H_stateArgs, 0, 0 }, + { 3, Iclass_MSUB_H_args, + 6, Iclass_MSUB_H_stateArgs, 0, 0 }, + { 3, Iclass_MADDN_H_args, + 1, Iclass_MADDN_H_stateArgs, 0, 0 }, + { 3, Iclass_MSUBN_H_args, + 1, Iclass_MSUBN_H_stateArgs, 0, 0 }, + { 3, Iclass_DIVN_H_args, + 5, Iclass_DIVN_H_stateArgs, 0, 0 }, + { 2, Iclass_RMINNUM_H_args, + 2, Iclass_RMINNUM_H_stateArgs, 0, 0 }, + { 2, Iclass_RMAXNUM_H_args, + 2, Iclass_RMAXNUM_H_stateArgs, 0, 0 }, + { 4, Iclass_ABS_HX4X2_args, + 1, Iclass_ABS_HX4X2_stateArgs, 0, 0 }, + { 4, Iclass_NEG_HX4X2_args, + 1, Iclass_NEG_HX4X2_stateArgs, 0, 0 }, + { 4, Iclass_CONJC_HX4X2_args, + 1, Iclass_CONJC_HX4X2_stateArgs, 0, 0 }, + { 3, Iclass_CONST_HX4X2_args, + 1, Iclass_CONST_HX4X2_stateArgs, 0, 0 }, + { 4, Iclass_MULJC_HX4X2_args, + 1, Iclass_MULJC_HX4X2_stateArgs, 0, 0 }, + { 6, Iclass_ADD_HX4X2_args, + 5, Iclass_ADD_HX4X2_stateArgs, 0, 0 }, + { 6, Iclass_SUB_HX4X2_args, + 5, Iclass_SUB_HX4X2_stateArgs, 0, 0 }, + { 6, Iclass_MUL_HX4X2_args, + 6, Iclass_MUL_HX4X2_stateArgs, 0, 0 }, + { 6, Iclass_MADD_HX4X2_args, + 6, Iclass_MADD_HX4X2_stateArgs, 0, 0 }, + { 6, Iclass_MSUB_HX4X2_args, + 6, Iclass_MSUB_HX4X2_stateArgs, 0, 0 }, + { 5, Iclass_MULQ_H_args, + 6, Iclass_MULQ_H_stateArgs, 0, 0 }, + { 5, Iclass_MADDQ_H_args, + 6, Iclass_MADDQ_H_stateArgs, 0, 0 }, + { 5, Iclass_MULCNVH_HX4X2_args, + 6, Iclass_MULCNVH_HX4X2_stateArgs, 0, 0 }, + { 5, Iclass_MULACNVH_HX4X2_args, + 6, Iclass_MULACNVH_HX4X2_stateArgs, 0, 0 }, + { 5, Iclass_MULCNVL_HX4X2_args, + 6, Iclass_MULCNVL_HX4X2_stateArgs, 0, 0 }, + { 5, Iclass_MULACNVL_HX4X2_args, + 6, Iclass_MULACNVL_HX4X2_stateArgs, 0, 0 } +}; + +enum xtensa_iclass_id { + ICLASS_xt_iclass_excw, + ICLASS_xt_iclass_rfe, + ICLASS_xt_iclass_rfde, + ICLASS_xt_iclass_syscall, + ICLASS_xt_iclass_call12, + ICLASS_xt_iclass_call8, + ICLASS_xt_iclass_call4, + ICLASS_xt_iclass_callx12, + ICLASS_xt_iclass_callx8, + ICLASS_xt_iclass_callx4, + ICLASS_xt_iclass_entry, + ICLASS_xt_iclass_movsp, + ICLASS_xt_iclass_rotw, + ICLASS_xt_iclass_retw, + ICLASS_xt_iclass_rfwou, + ICLASS_xt_iclass_l32e, + ICLASS_xt_iclass_s32e, + ICLASS_xt_iclass_rsr_windowbase, + ICLASS_xt_iclass_wsr_windowbase, + ICLASS_xt_iclass_xsr_windowbase, + ICLASS_xt_iclass_rsr_windowstart, + ICLASS_xt_iclass_wsr_windowstart, + ICLASS_xt_iclass_xsr_windowstart, + ICLASS_xt_iclass_add_n, + ICLASS_xt_iclass_addi_n, + ICLASS_xt_iclass_bz6, + ICLASS_xt_iclass_ill_n, + ICLASS_xt_iclass_loadi4, + ICLASS_xt_iclass_mov_n, + ICLASS_xt_iclass_movi_n, + ICLASS_xt_iclass_nopn, + ICLASS_xt_iclass_retn, + ICLASS_xt_iclass_storei4, + ICLASS_rur_threadptr, + ICLASS_wur_threadptr, + ICLASS_xt_iclass_addi, + ICLASS_xt_iclass_addmi, + ICLASS_xt_iclass_addsub, + ICLASS_xt_iclass_bit, + ICLASS_xt_iclass_bsi8, + ICLASS_xt_iclass_bsi8b, + ICLASS_xt_iclass_bsi8u, + ICLASS_xt_iclass_bst8, + ICLASS_xt_iclass_bsz12, + ICLASS_xt_iclass_call0, + ICLASS_xt_iclass_callx0, + ICLASS_xt_iclass_exti, + ICLASS_xt_iclass_ill, + ICLASS_xt_iclass_jump, + ICLASS_xt_iclass_jumpx, + ICLASS_xt_iclass_l16ui, + ICLASS_xt_iclass_l16si, + ICLASS_xt_iclass_l32i, + ICLASS_xt_iclass_l32r, + ICLASS_xt_iclass_l8i, + ICLASS_xt_iclass_loop, + ICLASS_xt_iclass_loopz, + ICLASS_xt_iclass_movi, + ICLASS_xt_iclass_movz, + ICLASS_xt_iclass_neg, + ICLASS_xt_iclass_nop, + ICLASS_xt_iclass_l32ex, + ICLASS_xt_iclass_s32ex, + ICLASS_xt_iclass_getex, + ICLASS_xt_iclass_clrex, + ICLASS_xt_iclass_return, + ICLASS_xt_iclass_simcall, + ICLASS_xt_iclass_s16i, + ICLASS_xt_iclass_s32i, + ICLASS_xt_iclass_s32nb, + ICLASS_xt_iclass_s8i, + ICLASS_xt_iclass_sar, + ICLASS_xt_iclass_sari, + ICLASS_xt_iclass_shifts, + ICLASS_xt_iclass_shiftst, + ICLASS_xt_iclass_shiftt, + ICLASS_xt_iclass_slli, + ICLASS_xt_iclass_srai, + ICLASS_xt_iclass_srli, + ICLASS_xt_iclass_memw, + ICLASS_xt_iclass_extw, + ICLASS_xt_iclass_isync, + ICLASS_xt_iclass_sync, + ICLASS_xt_iclass_rsil, + ICLASS_xt_iclass_rsr_lend, + ICLASS_xt_iclass_wsr_lend, + ICLASS_xt_iclass_xsr_lend, + ICLASS_xt_iclass_rsr_lcount, + ICLASS_xt_iclass_wsr_lcount, + ICLASS_xt_iclass_xsr_lcount, + ICLASS_xt_iclass_rsr_lbeg, + ICLASS_xt_iclass_wsr_lbeg, + ICLASS_xt_iclass_xsr_lbeg, + ICLASS_xt_iclass_rsr_sar, + ICLASS_xt_iclass_wsr_sar, + ICLASS_xt_iclass_xsr_sar, + ICLASS_xt_iclass_rsr_memctl, + ICLASS_xt_iclass_wsr_memctl, + ICLASS_xt_iclass_xsr_memctl, + ICLASS_xt_iclass_rsr_configid0, + ICLASS_xt_iclass_wsr_configid0, + ICLASS_xt_iclass_rsr_configid1, + ICLASS_xt_iclass_rsr_ps, + ICLASS_xt_iclass_wsr_ps, + ICLASS_xt_iclass_xsr_ps, + ICLASS_xt_iclass_rsr_epc1, + ICLASS_xt_iclass_wsr_epc1, + ICLASS_xt_iclass_xsr_epc1, + ICLASS_xt_iclass_rsr_excsave1, + ICLASS_xt_iclass_wsr_excsave1, + ICLASS_xt_iclass_xsr_excsave1, + ICLASS_xt_iclass_rsr_epc2, + ICLASS_xt_iclass_wsr_epc2, + ICLASS_xt_iclass_xsr_epc2, + ICLASS_xt_iclass_rsr_excsave2, + ICLASS_xt_iclass_wsr_excsave2, + ICLASS_xt_iclass_xsr_excsave2, + ICLASS_xt_iclass_rsr_epc3, + ICLASS_xt_iclass_wsr_epc3, + ICLASS_xt_iclass_xsr_epc3, + ICLASS_xt_iclass_rsr_excsave3, + ICLASS_xt_iclass_wsr_excsave3, + ICLASS_xt_iclass_xsr_excsave3, + ICLASS_xt_iclass_rsr_epc4, + ICLASS_xt_iclass_wsr_epc4, + ICLASS_xt_iclass_xsr_epc4, + ICLASS_xt_iclass_rsr_excsave4, + ICLASS_xt_iclass_wsr_excsave4, + ICLASS_xt_iclass_xsr_excsave4, + ICLASS_xt_iclass_rsr_epc5, + ICLASS_xt_iclass_wsr_epc5, + ICLASS_xt_iclass_xsr_epc5, + ICLASS_xt_iclass_rsr_excsave5, + ICLASS_xt_iclass_wsr_excsave5, + ICLASS_xt_iclass_xsr_excsave5, + ICLASS_xt_iclass_rsr_epc6, + ICLASS_xt_iclass_wsr_epc6, + ICLASS_xt_iclass_xsr_epc6, + ICLASS_xt_iclass_rsr_excsave6, + ICLASS_xt_iclass_wsr_excsave6, + ICLASS_xt_iclass_xsr_excsave6, + ICLASS_xt_iclass_rsr_eps2, + ICLASS_xt_iclass_wsr_eps2, + ICLASS_xt_iclass_xsr_eps2, + ICLASS_xt_iclass_rsr_eps3, + ICLASS_xt_iclass_wsr_eps3, + ICLASS_xt_iclass_xsr_eps3, + ICLASS_xt_iclass_rsr_eps4, + ICLASS_xt_iclass_wsr_eps4, + ICLASS_xt_iclass_xsr_eps4, + ICLASS_xt_iclass_rsr_eps5, + ICLASS_xt_iclass_wsr_eps5, + ICLASS_xt_iclass_xsr_eps5, + ICLASS_xt_iclass_rsr_eps6, + ICLASS_xt_iclass_wsr_eps6, + ICLASS_xt_iclass_xsr_eps6, + ICLASS_xt_iclass_rsr_excvaddr, + ICLASS_xt_iclass_wsr_excvaddr, + ICLASS_xt_iclass_xsr_excvaddr, + ICLASS_xt_iclass_rsr_depc, + ICLASS_xt_iclass_wsr_depc, + ICLASS_xt_iclass_xsr_depc, + ICLASS_xt_iclass_rsr_exccause, + ICLASS_xt_iclass_wsr_exccause, + ICLASS_xt_iclass_xsr_exccause, + ICLASS_xt_iclass_rsr_misc0, + ICLASS_xt_iclass_wsr_misc0, + ICLASS_xt_iclass_xsr_misc0, + ICLASS_xt_iclass_rsr_misc1, + ICLASS_xt_iclass_wsr_misc1, + ICLASS_xt_iclass_xsr_misc1, + ICLASS_xt_iclass_rsr_misc2, + ICLASS_xt_iclass_wsr_misc2, + ICLASS_xt_iclass_xsr_misc2, + ICLASS_xt_iclass_rsr_misc3, + ICLASS_xt_iclass_wsr_misc3, + ICLASS_xt_iclass_xsr_misc3, + ICLASS_xt_iclass_rsr_prid, + ICLASS_xt_iclass_rsr_vecbase, + ICLASS_xt_iclass_wsr_vecbase, + ICLASS_xt_iclass_xsr_vecbase, + ICLASS_xt_iclass_rsr_mpucfg, + ICLASS_xt_iclass_wsr_mpucfg, + ICLASS_xt_iclass_salt, + ICLASS_xt_iclass_rsr_opmode, + ICLASS_xt_iclass_wsr_opmode, + ICLASS_xt_iclass_xsr_opmode, + ICLASS_xt_mul16, + ICLASS_xt_mul32, + ICLASS_xt_iclass_rfi, + ICLASS_xt_iclass_wait, + ICLASS_xt_iclass_rsr_interrupt, + ICLASS_xt_iclass_wsr_intset, + ICLASS_xt_iclass_wsr_intclear, + ICLASS_xt_iclass_rsr_intenable, + ICLASS_xt_iclass_wsr_intenable, + ICLASS_xt_iclass_xsr_intenable, + ICLASS_xt_iclass_break, + ICLASS_xt_iclass_break_n, + ICLASS_xt_iclass_rsr_dbreaka0, + ICLASS_xt_iclass_wsr_dbreaka0, + ICLASS_xt_iclass_xsr_dbreaka0, + ICLASS_xt_iclass_rsr_dbreakc0, + ICLASS_xt_iclass_wsr_dbreakc0, + ICLASS_xt_iclass_xsr_dbreakc0, + ICLASS_xt_iclass_rsr_dbreaka1, + ICLASS_xt_iclass_wsr_dbreaka1, + ICLASS_xt_iclass_xsr_dbreaka1, + ICLASS_xt_iclass_rsr_dbreakc1, + ICLASS_xt_iclass_wsr_dbreakc1, + ICLASS_xt_iclass_xsr_dbreakc1, + ICLASS_xt_iclass_rsr_ibreaka0, + ICLASS_xt_iclass_wsr_ibreaka0, + ICLASS_xt_iclass_xsr_ibreaka0, + ICLASS_xt_iclass_rsr_ibreaka1, + ICLASS_xt_iclass_wsr_ibreaka1, + ICLASS_xt_iclass_xsr_ibreaka1, + ICLASS_xt_iclass_rsr_ibreakenable, + ICLASS_xt_iclass_wsr_ibreakenable, + ICLASS_xt_iclass_xsr_ibreakenable, + ICLASS_xt_iclass_rsr_debugcause, + ICLASS_xt_iclass_wsr_debugcause, + ICLASS_xt_iclass_xsr_debugcause, + ICLASS_xt_iclass_rsr_icount, + ICLASS_xt_iclass_wsr_icount, + ICLASS_xt_iclass_xsr_icount, + ICLASS_xt_iclass_rsr_icountlevel, + ICLASS_xt_iclass_wsr_icountlevel, + ICLASS_xt_iclass_xsr_icountlevel, + ICLASS_xt_iclass_rsr_ddr, + ICLASS_xt_iclass_wsr_ddr, + ICLASS_xt_iclass_xsr_ddr, + ICLASS_xt_iclass_lddr32_p, + ICLASS_xt_iclass_sddr32_p, + ICLASS_xt_iclass_rfdo, + ICLASS_xt_iclass_rfdd, + ICLASS_xt_iclass_wsr_mmid, + ICLASS_xt_iclass_bbool1, + ICLASS_xt_iclass_bbool4, + ICLASS_xt_iclass_bbool8, + ICLASS_xt_iclass_bbranch, + ICLASS_xt_iclass_bmove, + ICLASS_xt_iclass_RSR_BR, + ICLASS_xt_iclass_WSR_BR, + ICLASS_xt_iclass_XSR_BR, + ICLASS_xt_iclass_rsr_ccount, + ICLASS_xt_iclass_wsr_ccount, + ICLASS_xt_iclass_xsr_ccount, + ICLASS_xt_iclass_rsr_ccompare0, + ICLASS_xt_iclass_wsr_ccompare0, + ICLASS_xt_iclass_xsr_ccompare0, + ICLASS_xt_iclass_rsr_ccompare1, + ICLASS_xt_iclass_wsr_ccompare1, + ICLASS_xt_iclass_xsr_ccompare1, + ICLASS_xt_iclass_rsr_ccompare2, + ICLASS_xt_iclass_wsr_ccompare2, + ICLASS_xt_iclass_xsr_ccompare2, + ICLASS_xt_iclass_icache, + ICLASS_xt_iclass_icache_lock, + ICLASS_xt_iclass_icache_inv, + ICLASS_xt_iclass_licx, + ICLASS_xt_iclass_sicx, + ICLASS_xt_iclass_dcache, + ICLASS_xt_iclass_dcache_dyn, + ICLASS_xt_iclass_dcache_ind, + ICLASS_xt_iclass_dcache_inv, + ICLASS_xt_iclass_dpf, + ICLASS_xt_iclass_dcache_lock, + ICLASS_xt_iclass_sdct, + ICLASS_xt_iclass_ldct, + ICLASS_xt_iclass_sdcw, + ICLASS_xt_iclass_ldcw, + ICLASS_xt_iclass_rsr_prefctl, + ICLASS_xt_iclass_wsr_prefctl, + ICLASS_xt_iclass_xsr_prefctl, + ICLASS_xt_iclass_wsr_cacheadrdis, + ICLASS_xt_iclass_rsr_cacheadrdis, + ICLASS_xt_iclass_xsr_cacheadrdis, + ICLASS_xt_iclass_rptlb0, + ICLASS_xt_iclass_rptlb, + ICLASS_xt_iclass_wptlb, + ICLASS_xt_iclass_rsr_mpuenb, + ICLASS_xt_iclass_wsr_mpuenb, + ICLASS_xt_iclass_xsr_mpuenb, + ICLASS_xt_iclass_rsr_cpenable, + ICLASS_xt_iclass_wsr_cpenable, + ICLASS_xt_iclass_xsr_cpenable, + ICLASS_xt_iclass_clamp, + ICLASS_xt_iclass_minmax, + ICLASS_xt_iclass_nsa, + ICLASS_xt_iclass_sx, + ICLASS_xt_iclass_l32ai, + ICLASS_xt_iclass_s32ri, + ICLASS_xt_iclass_rsr_atomctl, + ICLASS_xt_iclass_wsr_atomctl, + ICLASS_xt_iclass_xsr_atomctl, + ICLASS_xt_iclass_div, + ICLASS_xt_iclass_rsr_eraccess, + ICLASS_xt_iclass_wsr_eraccess, + ICLASS_xt_iclass_xsr_eraccess, + ICLASS_xt_iclass_rer, + ICLASS_xt_iclass_wer, + ICLASS_xt_iclass_wb15_0, + ICLASS_xt_iclass_wb15_1, + ICLASS_xt_iclass_wb15_2, + ICLASS_xt_iclass_wb15_3, + ICLASS_xt_iclass_wb15_4, + ICLASS_ic_sext16, + ICLASS_ic_zext16, + ICLASS_ic_zext8, + ICLASS_ic_clamps16, + ICLASS_rur_fcr, + ICLASS_wur_fcr, + ICLASS_rur_fsr, + ICLASS_wur_fsr, + ICLASS_iclass_READ_IMPWIRE, + ICLASS_iclass_SETB_EXPSTATE, + ICLASS_iclass_CLRB_EXPSTATE, + ICLASS_iclass_WRMSK_EXPSTATE, + ICLASS_rur_ae_ovf_sar, + ICLASS_wur_ae_ovf_sar, + ICLASS_rur_ae_bithead, + ICLASS_wur_ae_bithead, + ICLASS_rur_ae_ts_fts_bu_bp, + ICLASS_wur_ae_ts_fts_bu_bp, + ICLASS_rur_ae_cw_sd_no, + ICLASS_wur_ae_cw_sd_no, + ICLASS_rur_ae_cbegin0, + ICLASS_wur_ae_cbegin0, + ICLASS_rur_ae_cend0, + ICLASS_wur_ae_cend0, + ICLASS_rur_ae_cbegin1, + ICLASS_wur_ae_cbegin1, + ICLASS_rur_ae_cend1, + ICLASS_wur_ae_cend1, + ICLASS_rur_ae_cbegin2, + ICLASS_wur_ae_cbegin2, + ICLASS_rur_ae_cend2, + ICLASS_wur_ae_cend2, + ICLASS_rur_expstate, + ICLASS_wur_expstate, + ICLASS_RUR_AE_OVERFLOW, + ICLASS_WUR_AE_OVERFLOW, + ICLASS_RUR_AE_SAR, + ICLASS_WUR_AE_SAR, + ICLASS_RUR_AE_BITPTR, + ICLASS_WUR_AE_BITPTR, + ICLASS_RUR_AE_BITSUSED, + ICLASS_WUR_AE_BITSUSED, + ICLASS_RUR_AE_TABLESIZE, + ICLASS_WUR_AE_TABLESIZE, + ICLASS_RUR_AE_FIRST_TS, + ICLASS_WUR_AE_FIRST_TS, + ICLASS_RUR_AE_NEXTOFFSET, + ICLASS_WUR_AE_NEXTOFFSET, + ICLASS_RUR_AE_SEARCHDONE, + ICLASS_WUR_AE_SEARCHDONE, + ICLASS_RUR_AE_CWRAP, + ICLASS_WUR_AE_CWRAP, + ICLASS_AE_L8X4F_I, + ICLASS_AE_L8X4F_IP, + ICLASS_AE_L8X4F_X, + ICLASS_AE_L8X4F_XP, + ICLASS_AE_L8X4S_I, + ICLASS_AE_L8X4S_IP, + ICLASS_AE_L8X4S_X, + ICLASS_AE_L8X4S_XP, + ICLASS_AE_L8X4U_I, + ICLASS_AE_L8X4U_IP, + ICLASS_AE_L8X4U_X, + ICLASS_AE_L8X4U_XP, + ICLASS_AE_S8X4U_I, + ICLASS_AE_S8X4U_IP, + ICLASS_AE_S8X4U_X, + ICLASS_AE_S8X4U_XP, + ICLASS_AE_L16M_XC, + ICLASS_AE_L16M_XC1, + ICLASS_AE_L16M_I, + ICLASS_AE_L16M_IU, + ICLASS_AE_L16M_X, + ICLASS_AE_L16M_XU, + ICLASS_AE_L16_XC, + ICLASS_AE_L16_XC1, + ICLASS_AE_L16_I, + ICLASS_AE_L16_IP, + ICLASS_AE_L16_X, + ICLASS_AE_L16_XP, + ICLASS_AE_L8_XC, + ICLASS_AE_L8_XC1, + ICLASS_AE_L8_I, + ICLASS_AE_L8_IP, + ICLASS_AE_L8_X, + ICLASS_AE_L8_XP, + ICLASS_AE_L32F24_XC, + ICLASS_AE_L32F24_XC1, + ICLASS_AE_L32F24_I, + ICLASS_AE_L32F24_IP, + ICLASS_AE_L32F24_X, + ICLASS_AE_L32F24_XP, + ICLASS_AE_L32_XC, + ICLASS_AE_L32_XC1, + ICLASS_AE_L32_I, + ICLASS_AE_L32_IP, + ICLASS_AE_L32_X, + ICLASS_AE_L32_XP, + ICLASS_AE_L32M_XC, + ICLASS_AE_L32M_I, + ICLASS_AE_L32M_IU, + ICLASS_AE_L32M_X, + ICLASS_AE_L32M_XU, + ICLASS_AE_L16X2M_XC, + ICLASS_AE_L16X2M_XC1, + ICLASS_AE_L16X2M_I, + ICLASS_AE_L16X2M_IU, + ICLASS_AE_L16X2M_X, + ICLASS_AE_L16X2M_XU, + ICLASS_AE_L32X2F24_XC, + ICLASS_AE_L32X2F24_XC1, + ICLASS_AE_L32X2F24_I, + ICLASS_AE_L32X2F24_IP, + ICLASS_AE_L32X2F24_RIP, + ICLASS_AE_L32X2F24_RI, + ICLASS_AE_L32X2F24_RIC, + ICLASS_AE_L32X2F24_RIC1, + ICLASS_AE_L32X2F24_X, + ICLASS_AE_L32X2F24_XP, + ICLASS_AE_L32X2_XC, + ICLASS_AE_L32X2_XC1, + ICLASS_AE_L32X2_I, + ICLASS_AE_L32X2_IP, + ICLASS_AE_L32X2_RIC, + ICLASS_AE_L32X2_RIC1, + ICLASS_AE_L32X2_X, + ICLASS_AE_L32X2_XP, + ICLASS_AE_L16X4_XC, + ICLASS_AE_L16X4_XC1, + ICLASS_AE_L16X4_I, + ICLASS_AE_L16X4_IP, + ICLASS_AE_L16X4_X, + ICLASS_AE_L16X4_XP, + ICLASS_AE_L8X8_XC, + ICLASS_AE_L8X8_XC1, + ICLASS_AE_L8X8_I, + ICLASS_AE_L8X8_IP, + ICLASS_AE_L8X8_X, + ICLASS_AE_L8X8_XP, + ICLASS_AE_L64_XC, + ICLASS_AE_L64_XC1, + ICLASS_AE_L64_I, + ICLASS_AE_L64_IP, + ICLASS_AE_L64_X, + ICLASS_AE_L64_XP, + ICLASS_AE_S16X2M_XC, + ICLASS_AE_S16X2M_XC1, + ICLASS_AE_S16X2M_I, + ICLASS_AE_S16X2M_IU, + ICLASS_AE_S16X2M_X, + ICLASS_AE_S16X2M_XU, + ICLASS_AE_S32X2F24_XC, + ICLASS_AE_S32X2F24_XC1, + ICLASS_AE_S32X2F24_I, + ICLASS_AE_S32X2F24_IP, + ICLASS_AE_S32X2F24_RIP, + ICLASS_AE_S32X2F24_RIC, + ICLASS_AE_S32X2F24_RIC1, + ICLASS_AE_S32X2F24_X, + ICLASS_AE_S32X2F24_XP, + ICLASS_AE_S32X2_XC, + ICLASS_AE_S32X2_XC1, + ICLASS_AE_S32X2_I, + ICLASS_AE_S32X2_IP, + ICLASS_AE_S32X2_RIC, + ICLASS_AE_S32X2_RIC1, + ICLASS_AE_S32X2_X, + ICLASS_AE_S32X2_XP, + ICLASS_AE_S32X2RNG_I, + ICLASS_AE_S32X2RNG_IP, + ICLASS_AE_S32X2RNG_X, + ICLASS_AE_S32X2RNG_XP, + ICLASS_AE_S16X4_XC, + ICLASS_AE_S16X4_XC1, + ICLASS_AE_S16X4_I, + ICLASS_AE_S16X4_IP, + ICLASS_AE_S16X4_X, + ICLASS_AE_S16X4_XP, + ICLASS_AE_S8X8_XC, + ICLASS_AE_S8X8_XC1, + ICLASS_AE_S8X8_I, + ICLASS_AE_S8X8_IP, + ICLASS_AE_S8X8_X, + ICLASS_AE_S8X8_XP, + ICLASS_AE_S16M_L_XC, + ICLASS_AE_S16M_L_XC1, + ICLASS_AE_S16M_L_I, + ICLASS_AE_S16M_L_IU, + ICLASS_AE_S16M_L_X, + ICLASS_AE_S16M_L_XU, + ICLASS_AE_S32F24_L_XC, + ICLASS_AE_S32F24_L_XC1, + ICLASS_AE_S32F24_L_I, + ICLASS_AE_S32F24_L_IP, + ICLASS_AE_S32F24_L_X, + ICLASS_AE_S32F24_L_XP, + ICLASS_AE_S32_L_XC, + ICLASS_AE_S32_L_XC1, + ICLASS_AE_S32_L_I, + ICLASS_AE_S32_L_IP, + ICLASS_AE_S32_L_X, + ICLASS_AE_S32_L_XP, + ICLASS_AE_S32_H_XC, + ICLASS_AE_S32_H_XC1, + ICLASS_AE_S32_H_I, + ICLASS_AE_S32_H_IP, + ICLASS_AE_S32_H_X, + ICLASS_AE_S32_H_XP, + ICLASS_AE_S16_0_XC, + ICLASS_AE_S16_0_XC1, + ICLASS_AE_S16_0_I, + ICLASS_AE_S16_0_IP, + ICLASS_AE_S16_0_X, + ICLASS_AE_S16_0_XP, + ICLASS_AE_S8_0_XC, + ICLASS_AE_S8_0_XC1, + ICLASS_AE_S8_0_I, + ICLASS_AE_S8_0_IP, + ICLASS_AE_S8_0_X, + ICLASS_AE_S8_0_XP, + ICLASS_AE_S64_XC, + ICLASS_AE_S64_XC1, + ICLASS_AE_S64_I, + ICLASS_AE_S64_IP, + ICLASS_AE_S64_X, + ICLASS_AE_S64_XP, + ICLASS_AE_S32M_XC, + ICLASS_AE_S32M_I, + ICLASS_AE_S32M_IU, + ICLASS_AE_S32M_X, + ICLASS_AE_S32M_XU, + ICLASS_AE_L32X2_XC2, + ICLASS_AE_L16X4_XC2, + ICLASS_AE_L8X8_XC2, + ICLASS_AE_L64_XC2, + ICLASS_AE_S32X2_XC2, + ICLASS_AE_S16X4_XC2, + ICLASS_AE_S8X8_XC2, + ICLASS_AE_S64_XC2, + ICLASS_AE_S16X4RNG_I, + ICLASS_AE_S16X4RNG_IP, + ICLASS_AE_S16X4RNG_X, + ICLASS_AE_S16X4RNG_XP, + ICLASS_AE_L32X2X2_XC, + ICLASS_AE_L32X2X2_XC1, + ICLASS_AE_L32X2X2_I, + ICLASS_AE_L32X2X2_IP, + ICLASS_AE_L32X2X2_X, + ICLASS_AE_L32X2X2_XP, + ICLASS_AE_L16X4X2_XC, + ICLASS_AE_L16X4X2_XC1, + ICLASS_AE_L16X4X2_I, + ICLASS_AE_L16X4X2_IP, + ICLASS_AE_L16X4X2_X, + ICLASS_AE_L16X4X2_XP, + ICLASS_AE_L8X8X2_XC, + ICLASS_AE_L8X8X2_XC1, + ICLASS_AE_L8X8X2_I, + ICLASS_AE_L8X8X2_IP, + ICLASS_AE_L8X8X2_X, + ICLASS_AE_L8X8X2_XP, + ICLASS_AE_L64X2_XC, + ICLASS_AE_L64X2_XC1, + ICLASS_AE_L64X2_I, + ICLASS_AE_L64X2_IP, + ICLASS_AE_L64X2_X, + ICLASS_AE_L64X2_XP, + ICLASS_AE_S32X2X2_XC, + ICLASS_AE_S32X2X2_XC1, + ICLASS_AE_S32X2X2_I, + ICLASS_AE_S32X2X2_IP, + ICLASS_AE_S32X2X2_X, + ICLASS_AE_S32X2X2_XP, + ICLASS_AE_S32X2X2RNG_I, + ICLASS_AE_S32X2X2RNG_IP, + ICLASS_AE_S32X2X2RNG_X, + ICLASS_AE_S32X2X2RNG_XP, + ICLASS_AE_S16X4X2_XC, + ICLASS_AE_S16X4X2_XC1, + ICLASS_AE_S16X4X2_I, + ICLASS_AE_S16X4X2_IP, + ICLASS_AE_S16X4X2_X, + ICLASS_AE_S16X4X2_XP, + ICLASS_AE_S8X8X2_XC, + ICLASS_AE_S8X8X2_XC1, + ICLASS_AE_S8X8X2_I, + ICLASS_AE_S8X8X2_IP, + ICLASS_AE_S8X8X2_X, + ICLASS_AE_S8X8X2_XP, + ICLASS_AE_S8X4UX2_I, + ICLASS_AE_S8X4UX2_IP, + ICLASS_AE_S8X4UX2_X, + ICLASS_AE_S8X4UX2_XP, + ICLASS_AE_S64X2_XC, + ICLASS_AE_S64X2_XC1, + ICLASS_AE_S64X2_I, + ICLASS_AE_S64X2_IP, + ICLASS_AE_S64X2_X, + ICLASS_AE_S64X2_XP, + ICLASS_AE_L32X2X2_XC2, + ICLASS_AE_L16X4X2_XC2, + ICLASS_AE_L8X8X2_XC2, + ICLASS_AE_L64X2_XC2, + ICLASS_AE_S32X2X2_XC2, + ICLASS_AE_S16X4X2_XC2, + ICLASS_AE_S8X8X2_XC2, + ICLASS_AE_S64X2_XC2, + ICLASS_AE_S16X4X2RNG_I, + ICLASS_AE_S16X4X2RNG_IP, + ICLASS_AE_S16X4X2RNG_X, + ICLASS_AE_S16X4X2RNG_XP, + ICLASS_AE_ZALIGN64, + ICLASS_AE_LALIGN64_I, + ICLASS_AE_SALIGN64_I, + ICLASS_AE_MOVALIGN, + ICLASS_AE_LA64_PP, + ICLASS_AE_LA24POS_PC, + ICLASS_AE_LA24NEG_PC, + ICLASS_AE_LA24POS_PC1, + ICLASS_AE_LA24NEG_PC1, + ICLASS_AE_LA24X2POS_PC, + ICLASS_AE_LA24X2NEG_PC, + ICLASS_AE_LA24X2POS_PC1, + ICLASS_AE_LA24X2NEG_PC1, + ICLASS_AE_LA32X2POS_PC, + ICLASS_AE_LA32X2NEG_PC, + ICLASS_AE_LA32X2POS_PC1, + ICLASS_AE_LA32X2NEG_PC1, + ICLASS_AE_LA32X2POS_PC2, + ICLASS_AE_LA16X4POS_PC, + ICLASS_AE_LA16X4NEG_PC, + ICLASS_AE_LA16X4POS_PC1, + ICLASS_AE_LA16X4NEG_PC1, + ICLASS_AE_LA16X4POS_PC2, + ICLASS_AE_LA8X8POS_PC, + ICLASS_AE_LA8X8NEG_PC, + ICLASS_AE_LA8X8POS_PC1, + ICLASS_AE_LA8X8NEG_PC1, + ICLASS_AE_LA8X8POS_PC2, + ICLASS_AE_LA32X2X2POS_PC, + ICLASS_AE_LA32X2X2POS_PC1, + ICLASS_AE_LA32X2X2POS_PC2, + ICLASS_AE_LA16X4X2POS_PC, + ICLASS_AE_LA16X4X2POS_PC1, + ICLASS_AE_LA16X4X2POS_PC2, + ICLASS_AE_LA8X8X2POS_PC, + ICLASS_AE_LA8X8X2POS_PC1, + ICLASS_AE_LA8X8X2POS_PC2, + ICLASS_AE_SA64POS_FP, + ICLASS_AE_SA64NEG_FP, + ICLASS_AE_LA32X2_IC, + ICLASS_AE_LA32X2_IC1, + ICLASS_AE_LA32X2_IC2, + ICLASS_AE_LA32X2_IP, + ICLASS_AE_LA32X2_RIP, + ICLASS_AE_LA32X2_RIC, + ICLASS_AE_LA32X2_RIC1, + ICLASS_AE_LA16X4_IC, + ICLASS_AE_LA16X4_IC1, + ICLASS_AE_LA16X4_IC2, + ICLASS_AE_LA16X4_IP, + ICLASS_AE_LA16X4_RIP, + ICLASS_AE_LA16X4_RIC, + ICLASS_AE_LA16X4_RIC1, + ICLASS_AE_LA8X8_IC, + ICLASS_AE_LA8X8_IC1, + ICLASS_AE_LA8X8_IC2, + ICLASS_AE_LA8X8_IP, + ICLASS_AE_LA8X8_RIP, + ICLASS_AE_LA8X8_RIC, + ICLASS_AE_LA8X8_RIC1, + ICLASS_AE_LA32X2F24_IC, + ICLASS_AE_LA32X2F24_IC1, + ICLASS_AE_LA32X2F24_IP, + ICLASS_AE_LA32X2F24_RIP, + ICLASS_AE_LA32X2F24_RIC, + ICLASS_AE_LA32X2F24_RIC1, + ICLASS_AE_LA24_IC, + ICLASS_AE_LA24_IC1, + ICLASS_AE_LA24_IP, + ICLASS_AE_LA24_RIP, + ICLASS_AE_LA24_RIC, + ICLASS_AE_LA24_RIC1, + ICLASS_AE_LA24X2_IC, + ICLASS_AE_LA24X2_IC1, + ICLASS_AE_LA24X2_IP, + ICLASS_AE_LA24X2_RIP, + ICLASS_AE_LA24X2_RIC, + ICLASS_AE_LA24X2_RIC1, + ICLASS_AE_SA32X2_IC, + ICLASS_AE_SA32X2_IC1, + ICLASS_AE_SA32X2_IC2, + ICLASS_AE_SA32X2_IP, + ICLASS_AE_SA32X2_RIP, + ICLASS_AE_SA32X2_RIC, + ICLASS_AE_SA32X2_RIC1, + ICLASS_AE_SA16X4_IC, + ICLASS_AE_SA16X4_IC1, + ICLASS_AE_SA16X4_IC2, + ICLASS_AE_SA16X4_IP, + ICLASS_AE_SA16X4_RIP, + ICLASS_AE_SA16X4_RIC, + ICLASS_AE_SA16X4_RIC1, + ICLASS_AE_SA8X8_IC, + ICLASS_AE_SA8X8_IC1, + ICLASS_AE_SA8X8_IC2, + ICLASS_AE_SA8X8_IP, + ICLASS_AE_SA8X8_RIP, + ICLASS_AE_SA8X8_RIC, + ICLASS_AE_SA8X8_RIC1, + ICLASS_AE_SA32X2F24_IC, + ICLASS_AE_SA32X2F24_IC1, + ICLASS_AE_SA32X2F24_IP, + ICLASS_AE_SA32X2F24_RIP, + ICLASS_AE_SA32X2F24_RIC, + ICLASS_AE_SA32X2F24_RIC1, + ICLASS_AE_SA24_L_IC, + ICLASS_AE_SA24_L_IC1, + ICLASS_AE_SA24_L_IP, + ICLASS_AE_SA24_L_RIP, + ICLASS_AE_SA24_L_RIC, + ICLASS_AE_SA24_L_RIC1, + ICLASS_AE_SA24X2_IC, + ICLASS_AE_SA24X2_IC1, + ICLASS_AE_SA24X2_IP, + ICLASS_AE_SA24X2_RIP, + ICLASS_AE_SA24X2_RIC, + ICLASS_AE_SA24X2_RIC1, + ICLASS_AE_ADDICIRC, + ICLASS_AE_ADDCIRC_XC2, + ICLASS_AE_ADDCIRC_XC1, + ICLASS_AE_ADDCIRC_XC, + ICLASS_AE_S32RA64S_I, + ICLASS_AE_S32RA64S_IP, + ICLASS_AE_S32RA64S_X, + ICLASS_AE_S32RA64S_XP, + ICLASS_AE_S32RA64S_XC, + ICLASS_AE_S32RA64S_XC1, + ICLASS_AE_S24RA64S_I, + ICLASS_AE_S24RA64S_IP, + ICLASS_AE_S24RA64S_X, + ICLASS_AE_S24RA64S_XP, + ICLASS_AE_S24RA64S_XC, + ICLASS_AE_S24RA64S_XC1, + ICLASS_AE_S32X2RA64S_IP, + ICLASS_AE_S24X2RA64S_IP, + ICLASS_AE_S16X4RA32S_IP, + ICLASS_AE_ADDBRBA32, + ICLASS_AE_S32X2_L_IP, + ICLASS_AE_BITSWAP, + ICLASS_AE_MUL32JS, + ICLASS_AE_ADDANDSUB32S, + ICLASS_AE_ADDANDSUB32JS, + ICLASS_AE_ADDANDSUBRNG32, + ICLASS_AE_ADDANDSUBRNG32_H, + ICLASS_AE_ADDANDSUBRNG32_L, + ICLASS_AE_ADDRNG32, + ICLASS_AE_SUBRNG32, + ICLASS_AE_RNG32X2, + ICLASS_AE_SEL16I, + ICLASS_AE_SEL16I_N, + ICLASS_AE_SHORTSWAP, + ICLASS_AE_MOVAB4, + ICLASS_AE_MOVAB2, + ICLASS_AE_MOVAB, + ICLASS_AE_MOVBA, + ICLASS_AE_MOVBA1X2, + ICLASS_AE_MOVBA4, + ICLASS_AE_MOVBA2, + ICLASS_AE_MOVB2, + ICLASS_AE_MOVB4, + ICLASS_AE_MOVT16X4, + ICLASS_AE_MOVF16X4, + ICLASS_AE_MOVT32X2, + ICLASS_AE_MOVF32X2, + ICLASS_AE_MOVSARA7X2, + ICLASS_AE_MOVSARD7, + ICLASS_AE_MOVASAR, + ICLASS_AE_MOVDA32X2, + ICLASS_AE_MOVDA32, + ICLASS_AE_MOVDA16X2, + ICLASS_AE_MOVDA16, + ICLASS_AE_MOVI, + ICLASS_AE_TRUNCP24A32X2, + ICLASS_AE_SAT16X4, + ICLASS_AE_CVT32X2F16_32, + ICLASS_AE_CVT32X2F16_10, + ICLASS_AE_SEXT32X2D16_32, + ICLASS_AE_SEXT32X2D16_10, + ICLASS_AE_CVTA32F24S_L, + ICLASS_AE_CVTA32F24S_H, + ICLASS_AE_CVTP24A16X2_LL, + ICLASS_AE_CVTP24A16X2_LH, + ICLASS_AE_CVTP24A16X2_HL, + ICLASS_AE_CVTP24A16X2_HH, + ICLASS_AE_TRUNCP24Q48X2, + ICLASS_AE_TRUNCA32X2F64S, + ICLASS_AE_TRUNCI32X2F64S, + ICLASS_AE_TRUNCA32F64S_L, + ICLASS_AE_TRUNCI32F64S_L, + ICLASS_AE_TRUNCP16, + ICLASS_AE_ROUND32X2F64SSYM, + ICLASS_AE_ROUND32X2F64SASYM, + ICLASS_AE_ROUND32X2F48SSYM, + ICLASS_AE_ROUND32X2F48SASYM, + ICLASS_AE_ROUND16X4F32SSYM, + ICLASS_AE_ROUND16X4F32SASYM, + ICLASS_AE_ROUND24X2F48SSYM, + ICLASS_AE_ROUND24X2F48SASYM, + ICLASS_AE_ROUNDSP16Q48X2SYM, + ICLASS_AE_ROUNDSP16Q48X2ASYM, + ICLASS_AE_MINABS32S, + ICLASS_AE_MAXABS32S, + ICLASS_AE_ROUNDSP16F24SYM, + ICLASS_AE_ROUNDSP16F24ASYM, + ICLASS_AE_MOV, + ICLASS_AE_MOVT64, + ICLASS_AE_MOVF64, + ICLASS_AE_CVTQ56A32S, + ICLASS_AE_CVT48A32, + ICLASS_AE_CVT64A32, + ICLASS_AE_CVTQ56P32S_L, + ICLASS_AE_CVTQ56P32S_H, + ICLASS_AE_CVT64F32_H, + ICLASS_AE_CVT48F32_L, + ICLASS_AE_CVT48F32_H, + ICLASS_AE_SAT48S, + ICLASS_AE_SATQ56S, + ICLASS_AE_SAT24S, + ICLASS_AE_TRUNCQ32, + ICLASS_AE_MINABS64S, + ICLASS_AE_MAXABS64S, + ICLASS_AE_ROUNDSQ32F48SYM, + ICLASS_AE_ROUNDSQ32F48ASYM, + ICLASS_AE_TRUNCA32Q48, + ICLASS_AE_MOVAD32_L, + ICLASS_AE_MOVAD32_H, + ICLASS_AE_MOVAD16_3, + ICLASS_AE_MOVAD16_2, + ICLASS_AE_MOVAD16_1, + ICLASS_AE_MOVAD16_0, + ICLASS_AE_SRA64_32, + ICLASS_AE_PKSR32, + ICLASS_AE_PKSR24, + ICLASS_AE_PKSRF32, + ICLASS_AE_PKSR16, + ICLASS_AE_TRUNCA16P24S_L, + ICLASS_AE_TRUNCA16P24S_H, + ICLASS_AE_ADD32, + ICLASS_AE_SUB32, + ICLASS_AE_ADDSUB32, + ICLASS_AE_SUBADD32, + ICLASS_AE_ADD16, + ICLASS_AE_SUB16, + ICLASS_AE_ADD32_HL_LH, + ICLASS_AE_ADDSUB32_HL_LH, + ICLASS_AE_NEG32, + ICLASS_AE_ABS32, + ICLASS_AE_NEG32_L, + ICLASS_AE_ADD24S, + ICLASS_AE_SUB24S, + ICLASS_AE_ADD32S, + ICLASS_AE_SUB32S, + ICLASS_AE_ADDSUB32S, + ICLASS_AE_SUBADD32S, + ICLASS_AE_ADD16S, + ICLASS_AE_SUB16S, + ICLASS_AE_ADD32S_HL_LH, + ICLASS_AE_ADDSUB32S_HL_LH, + ICLASS_AE_NEG24S, + ICLASS_AE_ABS24S, + ICLASS_AE_NEG32S, + ICLASS_AE_ABS32S, + ICLASS_AE_NEG16S, + ICLASS_AE_ABS16S, + ICLASS_AE_ABS16, + ICLASS_AE_MULC16JS_H, + ICLASS_AE_MULC16JS_L, + ICLASS_AE_MULAC16JS_H, + ICLASS_AE_MULAC16JS_L, + ICLASS_AE_LT16, + ICLASS_AE_LE16, + ICLASS_AE_EQ16, + ICLASS_AE_LT32, + ICLASS_AE_LE32, + ICLASS_AE_EQ32, + ICLASS_AE_MIN32, + ICLASS_AE_MAX32, + ICLASS_AE_MINMAX32, + ICLASS_AE_MINMAX16, + ICLASS_AE_MIN16, + ICLASS_AE_MAX16, + ICLASS_AE_ADD64, + ICLASS_AE_SUB64, + ICLASS_AE_NEG64, + ICLASS_AE_ABS64, + ICLASS_AE_ADDSQ56S, + ICLASS_AE_SUBSQ56S, + ICLASS_AE_ADD64S, + ICLASS_AE_SUB64S, + ICLASS_AE_NEGSQ56S, + ICLASS_AE_ABSSQ56S, + ICLASS_AE_NEG64S, + ICLASS_AE_ABS64S, + ICLASS_AE_AND, + ICLASS_AE_NAND, + ICLASS_AE_OR, + ICLASS_AE_XOR, + ICLASS_AE_SLAI24, + ICLASS_AE_SRLI24, + ICLASS_AE_SRAI24, + ICLASS_AE_SLAS24, + ICLASS_AE_SRLS24, + ICLASS_AE_SRAS24, + ICLASS_AE_SRAI16, + ICLASS_AE_SRAI16R, + ICLASS_AE_SLAI32, + ICLASS_AE_SRLI32, + ICLASS_AE_SRAI32, + ICLASS_AE_SRAI32R, + ICLASS_AE_SLAS32, + ICLASS_AE_SRLS32, + ICLASS_AE_SRAS32, + ICLASS_AE_SLAA32, + ICLASS_AE_SRLA32, + ICLASS_AE_SRAA32, + ICLASS_AE_SLAI16S, + ICLASS_AE_SLAA16S, + ICLASS_AE_SRAA16S, + ICLASS_AE_SRAA16RS, + ICLASS_AE_SLAI24S, + ICLASS_AE_SLAS24S, + ICLASS_AE_SLAI32S, + ICLASS_AE_SLAS32S, + ICLASS_AE_SLAA32S, + ICLASS_AE_SRAA32S, + ICLASS_AE_SRAA32RS, + ICLASS_AE_SLASQ56, + ICLASS_AE_SRLSQ56, + ICLASS_AE_SRASQ56, + ICLASS_AE_SLAAQ56, + ICLASS_AE_SRLAQ56, + ICLASS_AE_SRAAQ56, + ICLASS_AE_SLAI64, + ICLASS_AE_SRLI64, + ICLASS_AE_SRAI64, + ICLASS_AE_SLAS64, + ICLASS_AE_SRLS64, + ICLASS_AE_SRAS64, + ICLASS_AE_SLAA64, + ICLASS_AE_SRLA64, + ICLASS_AE_SRAA64, + ICLASS_AE_SLAISQ56S, + ICLASS_AE_SLASSQ56S, + ICLASS_AE_SLAASQ56S, + ICLASS_AE_SLAI64S, + ICLASS_AE_SLAS64S, + ICLASS_AE_SLAA64S, + ICLASS_AE_LT64, + ICLASS_AE_LE64, + ICLASS_AE_EQ64, + ICLASS_AE_MAX64, + ICLASS_AE_MIN64, + ICLASS_AE_NSA64, + ICLASS_AE_NSAZ16_0, + ICLASS_AE_NSAZ32_L, + ICLASS_AE_MULS32F48P16S_LL, + ICLASS_AE_MULF32S_LL, + ICLASS_AE_MUL32_LL, + ICLASS_AE_MULF32R_LL, + ICLASS_AE_MULF32RA_LL, + ICLASS_AE_MULS32F48P16S_LH, + ICLASS_AE_MULF32S_LH, + ICLASS_AE_MUL32_LH, + ICLASS_AE_MULF32R_LH, + ICLASS_AE_MULF32RA_LH, + ICLASS_AE_MULS32F48P16S_HH, + ICLASS_AE_MULF32S_HH, + ICLASS_AE_MUL32_HH, + ICLASS_AE_MULF32R_HH, + ICLASS_AE_MULF32RA_HH, + ICLASS_AE_MULAS32F48P16S_LL, + ICLASS_AE_MULAF32S_LL, + ICLASS_AE_MULA32_LL, + ICLASS_AE_MULAF32R_LL, + ICLASS_AE_MULAF32RA_LL, + ICLASS_AE_MULAS32F48P16S_LH, + ICLASS_AE_MULAF32S_LH, + ICLASS_AE_MULA32_LH, + ICLASS_AE_MULAF32R_LH, + ICLASS_AE_MULAF32RA_LH, + ICLASS_AE_MULAS32F48P16S_HH, + ICLASS_AE_MULAF32S_HH, + ICLASS_AE_MULA32_HH, + ICLASS_AE_MULAF32R_HH, + ICLASS_AE_MULAF32RA_HH, + ICLASS_AE_MULSS32F48P16S_LL, + ICLASS_AE_MULSF32S_LL, + ICLASS_AE_MULS32_LL, + ICLASS_AE_MULSF32R_LL, + ICLASS_AE_MULSF32RA_LL, + ICLASS_AE_MULSS32F48P16S_LH, + ICLASS_AE_MULSF32S_LH, + ICLASS_AE_MULS32_LH, + ICLASS_AE_MULSF32R_LH, + ICLASS_AE_MULSF32RA_LH, + ICLASS_AE_MULSS32F48P16S_HH, + ICLASS_AE_MULSF32S_HH, + ICLASS_AE_MULS32_HH, + ICLASS_AE_MULSF32R_HH, + ICLASS_AE_MULSF32RA_HH, + ICLASS_AE_MUL32U_LL, + ICLASS_AE_MULA32U_LL, + ICLASS_AE_MULS32U_LL, + ICLASS_AE_MULF16SS_33, + ICLASS_AE_MULF16SS_22, + ICLASS_AE_MULF16SS_32, + ICLASS_AE_MULF16SS_21, + ICLASS_AE_MULF16SS_31, + ICLASS_AE_MULF16SS_30, + ICLASS_AE_MULF16SS_10, + ICLASS_AE_MULF16SS_20, + ICLASS_AE_MULF16SS_11, + ICLASS_AE_MULF16SS_00, + ICLASS_AE_MULSF16SS_33, + ICLASS_AE_MULSF16SS_22, + ICLASS_AE_MULSF16SS_32, + ICLASS_AE_MULSF16SS_21, + ICLASS_AE_MULSF16SS_31, + ICLASS_AE_MULSF16SS_30, + ICLASS_AE_MULSF16SS_10, + ICLASS_AE_MULSF16SS_20, + ICLASS_AE_MULSF16SS_11, + ICLASS_AE_MULSF16SS_00, + ICLASS_AE_MULAF16SS_33, + ICLASS_AE_MULAF16SS_22, + ICLASS_AE_MULAF16SS_32, + ICLASS_AE_MULAF16SS_21, + ICLASS_AE_MULAF16SS_31, + ICLASS_AE_MULAF16SS_30, + ICLASS_AE_MULAF16SS_10, + ICLASS_AE_MULAF16SS_20, + ICLASS_AE_MULAF16SS_11, + ICLASS_AE_MULAF16SS_00, + ICLASS_AE_MUL16S_00, + ICLASS_AE_MULA16S_00, + ICLASS_AE_MULS16S_00, + ICLASS_AE_MULAAFD16SS_33_22, + ICLASS_AE_MULAAFD16SS_13_02, + ICLASS_AE_MULAAFD16SS_11_00, + ICLASS_AE_MULSSFD16SS_33_22, + ICLASS_AE_MULSSFD16SS_13_02, + ICLASS_AE_MULSSFD16SS_11_00, + ICLASS_AE_MULZAAFD16SS_33_22, + ICLASS_AE_MULZAAFD16SS_13_02, + ICLASS_AE_MULZAAFD16SS_11_00, + ICLASS_AE_MULZSSFD16SS_33_22, + ICLASS_AE_MULZSSFD16SS_13_02, + ICLASS_AE_MULZSSFD16SS_11_00, + ICLASS_AE_MULF48Q32SP16S_L, + ICLASS_AE_MULF48Q32SP16U_L, + ICLASS_AE_MULQ32SP16S_L, + ICLASS_AE_MULQ32SP16U_L, + ICLASS_AE_MULAF48Q32SP16S_L, + ICLASS_AE_MULAF48Q32SP16U_L, + ICLASS_AE_MULAQ32SP16S_L, + ICLASS_AE_MULAQ32SP16U_L, + ICLASS_AE_MULSF48Q32SP16S_L, + ICLASS_AE_MULSF48Q32SP16U_L, + ICLASS_AE_MULSQ32SP16S_L, + ICLASS_AE_MULSQ32SP16U_L, + ICLASS_AE_MULFP24X2RA, + ICLASS_AE_MULFP24X2R, + ICLASS_AE_MULAFP24X2RA, + ICLASS_AE_MULAFP24X2R, + ICLASS_AE_MULSFP24X2RA, + ICLASS_AE_MULSFP24X2R, + ICLASS_AE_MULZAAFD32S_HH_LL, + ICLASS_AE_MULZAAFD32RA_HH_LL, + ICLASS_AE_MULZAAD32_HH_LL, + ICLASS_AE_MULZAAFD32S_HL_LH, + ICLASS_AE_MULZAAFD32RA_HL_LH, + ICLASS_AE_MULZAAD32_HL_LH, + ICLASS_AE_MULZASFD32S_HH_LL, + ICLASS_AE_MULZASFD32RA_HH_LL, + ICLASS_AE_MULZASD32_HH_LL, + ICLASS_AE_MULZASFD32S_HL_LH, + ICLASS_AE_MULZASFD32RA_HL_LH, + ICLASS_AE_MULZASD32_HL_LH, + ICLASS_AE_MULZSAFD32S_HH_LL, + ICLASS_AE_MULZSAFD32RA_HH_LL, + ICLASS_AE_MULZSAD32_HH_LL, + ICLASS_AE_MULZSSFD32S_HH_LL, + ICLASS_AE_MULZSSFD32RA_HH_LL, + ICLASS_AE_MULZSSD32_HH_LL, + ICLASS_AE_MULZSSFD32S_HL_LH, + ICLASS_AE_MULZSSFD32RA_HL_LH, + ICLASS_AE_MULZSSD32_HL_LH, + ICLASS_AE_MULAAFD32S_HH_LL, + ICLASS_AE_MULAAFD32RA_HH_LL, + ICLASS_AE_MULAAD32_HH_LL, + ICLASS_AE_MULAAFD32S_HL_LH, + ICLASS_AE_MULAAFD32RA_HL_LH, + ICLASS_AE_MULAAD32_HL_LH, + ICLASS_AE_MULASFD32S_HH_LL, + ICLASS_AE_MULASFD32RA_HH_LL, + ICLASS_AE_MULASD32_HH_LL, + ICLASS_AE_MULASFD32S_HL_LH, + ICLASS_AE_MULASFD32RA_HL_LH, + ICLASS_AE_MULASD32_HL_LH, + ICLASS_AE_MULSAFD32S_HH_LL, + ICLASS_AE_MULSAFD32RA_HH_LL, + ICLASS_AE_MULSAD32_HH_LL, + ICLASS_AE_MULSSFD32S_HH_LL, + ICLASS_AE_MULSSFD32RA_HH_LL, + ICLASS_AE_MULSSD32_HH_LL, + ICLASS_AE_MULSSFD32S_HL_LH, + ICLASS_AE_MULSSFD32RA_HL_LH, + ICLASS_AE_MULSSD32_HL_LH, + ICLASS_AE_MULF32X16_L0, + ICLASS_AE_MUL32X16_L0, + ICLASS_AE_MULF32X16_L1, + ICLASS_AE_MUL32X16_L1, + ICLASS_AE_MULF32X16_L2, + ICLASS_AE_MUL32X16_L2, + ICLASS_AE_MULF32X16_L3, + ICLASS_AE_MUL32X16_L3, + ICLASS_AE_MULF32X16_H0, + ICLASS_AE_MUL32X16_H0, + ICLASS_AE_MULF32X16_H1, + ICLASS_AE_MUL32X16_H1, + ICLASS_AE_MULF32X16_H2, + ICLASS_AE_MUL32X16_H2, + ICLASS_AE_MULF32X16_H3, + ICLASS_AE_MUL32X16_H3, + ICLASS_AE_MULAF32X16_L0, + ICLASS_AE_MULA32X16_L0, + ICLASS_AE_MULAF32X16_L1, + ICLASS_AE_MULA32X16_L1, + ICLASS_AE_MULAF32X16_L2, + ICLASS_AE_MULA32X16_L2, + ICLASS_AE_MULAF32X16_L3, + ICLASS_AE_MULA32X16_L3, + ICLASS_AE_MULAF32X16_H0, + ICLASS_AE_MULA32X16_H0, + ICLASS_AE_MULAF32X16_H1, + ICLASS_AE_MULA32X16_H1, + ICLASS_AE_MULAF32X16_H2, + ICLASS_AE_MULA32X16_H2, + ICLASS_AE_MULAF32X16_H3, + ICLASS_AE_MULA32X16_H3, + ICLASS_AE_MULSF32X16_L0, + ICLASS_AE_MULS32X16_L0, + ICLASS_AE_MULSF32X16_L1, + ICLASS_AE_MULS32X16_L1, + ICLASS_AE_MULSF32X16_L2, + ICLASS_AE_MULS32X16_L2, + ICLASS_AE_MULSF32X16_L3, + ICLASS_AE_MULS32X16_L3, + ICLASS_AE_MULSF32X16_H0, + ICLASS_AE_MULS32X16_H0, + ICLASS_AE_MULSF32X16_H1, + ICLASS_AE_MULS32X16_H1, + ICLASS_AE_MULSF32X16_H2, + ICLASS_AE_MULS32X16_H2, + ICLASS_AE_MULSF32X16_H3, + ICLASS_AE_MULS32X16_H3, + ICLASS_AE_MULAAFD32X16_H3_L2, + ICLASS_AE_MULAAD32X16_H3_L2, + ICLASS_AE_MULAAFD32X16_H1_L0, + ICLASS_AE_MULAAD32X16_H1_L0, + ICLASS_AE_MULASFD32X16_H3_L2, + ICLASS_AE_MULASD32X16_H3_L2, + ICLASS_AE_MULASFD32X16_H1_L0, + ICLASS_AE_MULASD32X16_H1_L0, + ICLASS_AE_MULSAFD32X16_H3_L2, + ICLASS_AE_MULSAD32X16_H3_L2, + ICLASS_AE_MULSAFD32X16_H1_L0, + ICLASS_AE_MULSAD32X16_H1_L0, + ICLASS_AE_MULSSFD32X16_H3_L2, + ICLASS_AE_MULSSD32X16_H3_L2, + ICLASS_AE_MULSSFD32X16_H1_L0, + ICLASS_AE_MULSSD32X16_H1_L0, + ICLASS_AE_MULZAAFD32X16_H3_L2, + ICLASS_AE_MULZAAD32X16_H3_L2, + ICLASS_AE_MULZAAFD32X16_H1_L0, + ICLASS_AE_MULZAAD32X16_H1_L0, + ICLASS_AE_MULZASFD32X16_H3_L2, + ICLASS_AE_MULZASD32X16_H3_L2, + ICLASS_AE_MULZASFD32X16_H1_L0, + ICLASS_AE_MULZASD32X16_H1_L0, + ICLASS_AE_MULZSAFD32X16_H3_L2, + ICLASS_AE_MULZSAD32X16_H3_L2, + ICLASS_AE_MULZSAFD32X16_H1_L0, + ICLASS_AE_MULZSAD32X16_H1_L0, + ICLASS_AE_MULZSSFD32X16_H3_L2, + ICLASS_AE_MULZSSD32X16_H3_L2, + ICLASS_AE_MULZSSFD32X16_H1_L0, + ICLASS_AE_MULZSSD32X16_H1_L0, + ICLASS_AE_MULZAAFD32X16_H2_L3, + ICLASS_AE_MULZAAFD32X16_H0_L1, + ICLASS_AE_MULAAFD32X16_H2_L3, + ICLASS_AE_MULAAFD32X16_H0_L1, + ICLASS_AE_MULZAAD32X16_H2_L3, + ICLASS_AE_MULZAAD32X16_H0_L1, + ICLASS_AE_MULAAD32X16_H2_L3, + ICLASS_AE_MULAAD32X16_H0_L1, + ICLASS_AE_MULP32X16X2_H, + ICLASS_AE_MULFP32X16X2RS_H, + ICLASS_AE_MULFP32X16X2RAS_H, + ICLASS_AE_MULFP32X16X2S_H, + ICLASS_AE_MULP32X16X2_L, + ICLASS_AE_MULFP32X16X2RS_L, + ICLASS_AE_MULFP32X16X2RAS_L, + ICLASS_AE_MULFP32X16X2S_L, + ICLASS_AE_MULAP32X16X2_H, + ICLASS_AE_MULAFP32X16X2RS_H, + ICLASS_AE_MULAFP32X16X2RAS_H, + ICLASS_AE_MULAFP32X16X2S_H, + ICLASS_AE_MULAP32X16X2_L, + ICLASS_AE_MULAFP32X16X2RS_L, + ICLASS_AE_MULAFP32X16X2RAS_L, + ICLASS_AE_MULAFP32X16X2S_L, + ICLASS_AE_MULSP32X16X2_H, + ICLASS_AE_MULSFP32X16X2RS_H, + ICLASS_AE_MULSFP32X16X2RAS_H, + ICLASS_AE_MULSFP32X16X2S_H, + ICLASS_AE_MULSP32X16X2_L, + ICLASS_AE_MULSFP32X16X2RS_L, + ICLASS_AE_MULSFP32X16X2RAS_L, + ICLASS_AE_MULSFP32X16X2S_L, + ICLASS_AE_MULP32X2, + ICLASS_AE_MULFP32X2RS, + ICLASS_AE_MULFP32X2RAS, + ICLASS_AE_MULFP32X2TS, + ICLASS_AE_MULP32X2T, + ICLASS_AE_MULAP32X2, + ICLASS_AE_MULAFP32X2RS, + ICLASS_AE_MULAFP32X2RAS, + ICLASS_AE_MULAFP32X2TS, + ICLASS_AE_MULAP32X2T, + ICLASS_AE_MULSP32X2, + ICLASS_AE_MULSFP32X2RS, + ICLASS_AE_MULSFP32X2RAS, + ICLASS_AE_MULSFP32X2TS, + ICLASS_AE_MULSP32X2T, + ICLASS_AE_MULFP16X4S, + ICLASS_AE_MULFP16X4RAS, + ICLASS_AE_MULC32, + ICLASS_AE_MULFC24RA, + ICLASS_AE_MULFC32RAS, + ICLASS_AE_MULC32X16_L, + ICLASS_AE_MULFC32X16RAS_L, + ICLASS_AE_MULC32X16_H, + ICLASS_AE_MULFC32X16RAS_H, + ICLASS_AE_MULAC32, + ICLASS_AE_MULAFC24RA, + ICLASS_AE_MULAFC32RAS, + ICLASS_AE_MULAC32X16_L, + ICLASS_AE_MULAFC32X16RAS_L, + ICLASS_AE_MULAC32X16_H, + ICLASS_AE_MULAFC32X16RAS_H, + ICLASS_AE_MULF16X4SS, + ICLASS_AE_MULAF16X4SS, + ICLASS_AE_MULSF16X4SS, + ICLASS_AE_MUL16X4S, + ICLASS_AE_MULA16X4S, + ICLASS_AE_MULS16X4S, + ICLASS_AE_MUL16X4, + ICLASS_AE_MULA16X4, + ICLASS_AE_MULS16X4, + ICLASS_AE_MULFD32X2S_FIR_H, + ICLASS_AE_MULFD32X2RA_FIR_H, + ICLASS_AE_MULFD32X2S_FIR_L, + ICLASS_AE_MULFD32X2RA_FIR_L, + ICLASS_AE_MULFD32X16X2_FIR_HH, + ICLASS_AE_MULFD32X16X2_FIR_HL, + ICLASS_AE_MULFD32X16X2_FIR_LH, + ICLASS_AE_MULFD32X16X2_FIR_LL, + ICLASS_AE_MULAFD32X2S_FIR_H, + ICLASS_AE_MULAFD32X2RA_FIR_H, + ICLASS_AE_MULAFD32X2S_FIR_L, + ICLASS_AE_MULAFD32X2RA_FIR_L, + ICLASS_AE_MULAFD32X16X2_FIR_HH, + ICLASS_AE_MULAFD32X16X2_FIR_HL, + ICLASS_AE_MULAFD32X16X2_FIR_LH, + ICLASS_AE_MULAFD32X16X2_FIR_LL, + ICLASS_AE_MULC16S_H, + ICLASS_AE_MULC16S_L, + ICLASS_AE_MULAC16S_H, + ICLASS_AE_MULAC16S_L, + ICLASS_AE_MULFC16RAS, + ICLASS_AE_MULAFC16RAS, + ICLASS_AE_MUL16JS, + ICLASS_AE_ADDANDSUBRNG16RAS_S1, + ICLASS_AE_ADDANDSUBRNG16RAS_S2, + ICLASS_AE_CONJ16S, + ICLASS_AE_MULFQ16X2_FIR_3, + ICLASS_AE_MULFQ16X2_FIR_2, + ICLASS_AE_MULFQ16X2_FIR_1, + ICLASS_AE_MULFQ16X2_FIR_0, + ICLASS_AE_MULAFQ16X2_FIR_3, + ICLASS_AE_MULAFQ16X2_FIR_2, + ICLASS_AE_MULAFQ16X2_FIR_1, + ICLASS_AE_MULAFQ16X2_FIR_0, + ICLASS_AE_MULZAAAAFQ32X16, + ICLASS_AE_MULAAAAFQ32X16, + ICLASS_AE_MULZAAAAQ32X16, + ICLASS_AE_MULAAAAQ32X16, + ICLASS_AE_MUL16_00, + ICLASS_AE_MULA16_00, + ICLASS_AE_MULZAAAAQ16, + ICLASS_AE_MULAAAAQ16, + ICLASS_AE_DIV64D32_H, + ICLASS_AE_DIV64D32_L, + ICLASS_AE_SHA32, + ICLASS_AE_VLDL32T, + ICLASS_AE_VLDL16T, + ICLASS_AE_VLDL16C, + ICLASS_AE_VLDL16C_IP, + ICLASS_AE_VLDL16C_IC, + ICLASS_AE_VLDL16C_IC1, + ICLASS_AE_VLDSHT, + ICLASS_AE_LB, + ICLASS_AE_LBI, + ICLASS_AE_LBK, + ICLASS_AE_LBKI, + ICLASS_AE_LBS, + ICLASS_AE_LBSI, + ICLASS_AE_DB, + ICLASS_AE_DBI, + ICLASS_AE_DB_IC, + ICLASS_AE_DBI_IC, + ICLASS_AE_DB_IC1, + ICLASS_AE_DBI_IC1, + ICLASS_AE_DB_IP, + ICLASS_AE_DBI_IP, + ICLASS_AE_ARDECNORM16, + ICLASS_AE_LBKI_DBI_IC, + ICLASS_AE_LBKI_DBI_IP, + ICLASS_AE_LBKI_DBI, + ICLASS_AE_LBI_DBI_IC, + ICLASS_AE_LBI_DBI_IP, + ICLASS_AE_LBI_DBI, + ICLASS_AE_LBK_DB_IC, + ICLASS_AE_LBK_DB_IP, + ICLASS_AE_LBK_DB, + ICLASS_AE_LB_DB_IC, + ICLASS_AE_LB_DB_IP, + ICLASS_AE_LB_DB, + ICLASS_AE_VLEL32T, + ICLASS_AE_VLEL16T, + ICLASS_AE_SB, + ICLASS_AE_SBI, + ICLASS_AE_VLES16C, + ICLASS_AE_SBF, + ICLASS_AE_SB_IC, + ICLASS_AE_SBI_IC, + ICLASS_AE_VLES16C_IC, + ICLASS_AE_SBF_IC, + ICLASS_AE_SB_IC1, + ICLASS_AE_SBI_IC1, + ICLASS_AE_VLES16C_IC1, + ICLASS_AE_SBF_IC1, + ICLASS_AE_SB_IP, + ICLASS_AE_SBI_IP, + ICLASS_AE_VLES16C_IP, + ICLASS_AE_SBF_IP, + ICLASS_AE_SEXT32, + ICLASS_AE_MOVAE, + ICLASS_AE_MOVEA, + ICLASS_AE_MOVEEP, + ICLASS_AE_SEXT72, + ICLASS_AE_ADD72, + ICLASS_AE_SUB72, + ICLASS_AE_ADD72X64, + ICLASS_AE_SUB72X64, + ICLASS_AE_MUL32EP_HH, + ICLASS_AE_MULA32EP_HH, + ICLASS_AE_MULS32EP_HH, + ICLASS_AE_MULZAAD32EP_HH_LL, + ICLASS_AE_MULZSSD32EP_HH_LL, + ICLASS_AE_MULAAD32EP_HH_LL, + ICLASS_AE_MULSSD32EP_HH_LL, + ICLASS_AE_MULAAD32USEP_HL_LH, + ICLASS_AE_MULZAAD32USEP_HL_LH, + ICLASS_AE_MUL32USEP_LH, + ICLASS_AE_MULA32USEP_LH, + ICLASS_AE_MUL32USEP_LL, + ICLASS_AE_MULA32USEP_LL, + ICLASS_AE_SRAI72, + ICLASS_AE_SLAI72, + ICLASS_AE_SAT64S, + ICLASS_AE_L16SI_N, + ICLASS_AE_L16UI_N, + ICLASS_AE_S16I_N, + ICLASS_AE_LALIGN128_I, + ICLASS_AE_SALIGN128_I, + ICLASS_AE_LA128_PP, + ICLASS_AE_SA128POS_FP, + ICLASS_AE_LA8X4S_IP, + ICLASS_AE_LA8X4U_IP, + ICLASS_AE_LA8X8X2_IP, + ICLASS_AE_LA16X4X2_IP, + ICLASS_AE_LA32X2X2_IP, + ICLASS_AE_LA8X8X2_IC, + ICLASS_AE_LA16X4X2_IC, + ICLASS_AE_LA32X2X2_IC, + ICLASS_AE_LA8X8X2_IC1, + ICLASS_AE_LA16X4X2_IC1, + ICLASS_AE_LA32X2X2_IC1, + ICLASS_AE_LA8X8X2_IC2, + ICLASS_AE_LA16X4X2_IC2, + ICLASS_AE_LA32X2X2_IC2, + ICLASS_AE_SA8X8X2_IP, + ICLASS_AE_SA16X4X2_IP, + ICLASS_AE_SA32X2X2_IP, + ICLASS_AE_SA8X8X2_IC, + ICLASS_AE_SA16X4X2_IC, + ICLASS_AE_SA32X2X2_IC, + ICLASS_AE_SA8X8X2_IC1, + ICLASS_AE_SA16X4X2_IC1, + ICLASS_AE_SA32X2X2_IC1, + ICLASS_AE_SA8X8X2_IC2, + ICLASS_AE_SA16X4X2_IC2, + ICLASS_AE_SA32X2X2_IC2, + ICLASS_AE_ABS8, + ICLASS_AE_ABS8S, + ICLASS_AE_NEG8S, + ICLASS_AE_ADD8, + ICLASS_AE_SUB8, + ICLASS_AE_MAX8, + ICLASS_AE_MIN8, + ICLASS_AE_ADD8S, + ICLASS_AE_SUB8S, + ICLASS_AE_LE8, + ICLASS_AE_LT8, + ICLASS_AE_EQ8, + ICLASS_AE_SATU16X4, + ICLASS_AE_SAT32X2, + ICLASS_AE_SATU32X2, + ICLASS_AE_SAT8X8X16, + ICLASS_AE_SATU8X8X16, + ICLASS_AE_SAT8X4X32_L, + ICLASS_AE_SATU8X4X32_L, + ICLASS_AE_ROUND8X8F16SSYM, + ICLASS_AE_ROUND8X8F16SASYM, + ICLASS_AE_ROUND8X4F32SSYM_L, + ICLASS_AE_ROUND8X4F32SASYM_L, + ICLASS_AE_MOVDA8, + ICLASS_AE_MOVAD8, + ICLASS_AE_MOVDX2, + ICLASS_AE_ADDANDSUB32J, + ICLASS_AE_ADDW8, + ICLASS_AE_ADDW16, + ICLASS_AE_ADDW32, + ICLASS_AE_SUBW8, + ICLASS_AE_SUBW16, + ICLASS_AE_SUBW32, + ICLASS_AE_ACCW8, + ICLASS_AE_ACCW16, + ICLASS_AE_ACCW32, + ICLASS_AE_ADDW8U, + ICLASS_AE_SUBW8U, + ICLASS_AE_ACCW8U, + ICLASS_AE_MULFP32X2S_HH_LL, + ICLASS_AE_MULAFP32X2S_HH_LL, + ICLASS_AE_MULSFP32X2S_HH_LL, + ICLASS_AE_MULFP32X2S_HL_LH, + ICLASS_AE_MULAFP32X2S_HL_LH, + ICLASS_AE_MULSFP32X2S_HL_LH, + ICLASS_AE_MULZAAF2D32S_HH_LL, + ICLASS_AE_MULZASF2D32S_HH_LL, + ICLASS_AE_MULZSAF2D32S_HH_LL, + ICLASS_AE_MULZSSF2D32S_HH_LL, + ICLASS_AE_MULAAF2D32S_HH_LL, + ICLASS_AE_MULASF2D32S_HH_LL, + ICLASS_AE_MULSAF2D32S_HH_LL, + ICLASS_AE_MULSSF2D32S_HH_LL, + ICLASS_AE_MULZAAF2D32S_HL_LH, + ICLASS_AE_MULZASF2D32S_HL_LH, + ICLASS_AE_MULZSAF2D32S_HL_LH, + ICLASS_AE_MULZSSF2D32S_HL_LH, + ICLASS_AE_MULAAF2D32S_HL_LH, + ICLASS_AE_MULASF2D32S_HL_LH, + ICLASS_AE_MULSAF2D32S_HL_LH, + ICLASS_AE_MULSSF2D32S_HL_LH, + ICLASS_AE_MUL32S_HH, + ICLASS_AE_MULA32S_HH, + ICLASS_AE_MULS32S_HH, + ICLASS_AE_MUL32S_LL, + ICLASS_AE_MULA32S_LL, + ICLASS_AE_MULS32S_LL, + ICLASS_AE_MUL32S_HL, + ICLASS_AE_MULA32S_HL, + ICLASS_AE_MULS32S_HL, + ICLASS_AE_MUL32S_LH, + ICLASS_AE_MULA32S_LH, + ICLASS_AE_MULS32S_LH, + ICLASS_AE_MUL32X2S_HH_LL, + ICLASS_AE_MULA32X2S_HH_LL, + ICLASS_AE_MULS32X2S_HH_LL, + ICLASS_AE_MUL32X2S_HL_LH, + ICLASS_AE_MULA32X2S_HL_LH, + ICLASS_AE_MULS32X2S_HL_LH, + ICLASS_AE_MULZAAD32S_HH_LL, + ICLASS_AE_MULZASD32S_HH_LL, + ICLASS_AE_MULZSAD32S_HH_LL, + ICLASS_AE_MULZSSD32S_HH_LL, + ICLASS_AE_MULAAD32S_HH_LL, + ICLASS_AE_MULASD32S_HH_LL, + ICLASS_AE_MULSAD32S_HH_LL, + ICLASS_AE_MULSSD32S_HH_LL, + ICLASS_AE_MULZAAD32S_HL_LH, + ICLASS_AE_MULZASD32S_HL_LH, + ICLASS_AE_MULZSAD32S_HL_LH, + ICLASS_AE_MULZSSD32S_HL_LH, + ICLASS_AE_MULAAD32S_HL_LH, + ICLASS_AE_MULASD32S_HL_LH, + ICLASS_AE_MULSAD32S_HL_LH, + ICLASS_AE_MULSSD32S_HL_LH, + ICLASS_AE_MULF32X2RA_HH_LL, + ICLASS_AE_MULAF32X2RA_HH_LL, + ICLASS_AE_MULSF32X2RA_HH_LL, + ICLASS_AE_MULF32X2RA_HL_LH, + ICLASS_AE_MULAF32X2RA_HL_LH, + ICLASS_AE_MULSF32X2RA_HL_LH, + ICLASS_AE_MULZAAF2D32RA_HH_LL, + ICLASS_AE_MULZASF2D32RA_HH_LL, + ICLASS_AE_MULZSAF2D32RA_HH_LL, + ICLASS_AE_MULZSSF2D32RA_HH_LL, + ICLASS_AE_MULAAF2D32RA_HH_LL, + ICLASS_AE_MULASF2D32RA_HH_LL, + ICLASS_AE_MULSAF2D32RA_HH_LL, + ICLASS_AE_MULSSF2D32RA_HH_LL, + ICLASS_AE_MULZAAF2D32RA_HL_LH, + ICLASS_AE_MULZASF2D32RA_HL_LH, + ICLASS_AE_MULZSAF2D32RA_HL_LH, + ICLASS_AE_MULZSSF2D32RA_HL_LH, + ICLASS_AE_MULAAF2D32RA_HL_LH, + ICLASS_AE_MULASF2D32RA_HL_LH, + ICLASS_AE_MULSAF2D32RA_HL_LH, + ICLASS_AE_MULSSF2D32RA_HL_LH, + ICLASS_AE_MULF32X2R_HH_LL, + ICLASS_AE_MULAF32X2R_HH_LL, + ICLASS_AE_MULSF32X2R_HH_LL, + ICLASS_AE_MULF32X2R_HL_LH, + ICLASS_AE_MULAF32X2R_HL_LH, + ICLASS_AE_MULSF32X2R_HL_LH, + ICLASS_AE_MULFC32W, + ICLASS_AE_MULAFC32W, + ICLASS_AE_MULFCJ32W, + ICLASS_AE_MULAFCJ32W, + ICLASS_AE_MULFCJ32RAS, + ICLASS_AE_MULAFCJ32RAS, + ICLASS_AE_MULF2P32X4RS, + ICLASS_AE_MULAF2P32X4RS, + ICLASS_AE_MULSF2P32X4RS, + ICLASS_AE_MULF2P32X4RAS, + ICLASS_AE_MULAF2P32X4RAS, + ICLASS_AE_MULSF2P32X4RAS, + ICLASS_AE_MULP32X2S, + ICLASS_AE_MUL2P32X4S, + ICLASS_AE_MUL2P32X4, + ICLASS_AE_MULA2P32X4, + ICLASS_AE_MULS2P32X4, + ICLASS_AE_MUL2P32X4T, + ICLASS_AE_MULA2P32X4T, + ICLASS_AE_MULS2P32X4T, + ICLASS_AE_MULZAA32X2_HH_LL, + ICLASS_AE_MULZSS32X2_HH_LL, + ICLASS_AE_MULAA32X2_HH_LL, + ICLASS_AE_MULSS32X2_HH_LL, + ICLASS_AE_MULCJ32, + ICLASS_AE_MULACJ32, + ICLASS_AE_MULADDF32RS, + ICLASS_AE_MULADDF32RAS, + ICLASS_AE_MULSUBF32RS, + ICLASS_AE_MULSUBF32RAS, + ICLASS_AE_MULFC32RA, + ICLASS_AE_MULAFC32RA, + ICLASS_AE_MULCJ32W, + ICLASS_AE_MULACJ32W, + ICLASS_AE_MULC32W, + ICLASS_AE_MULAC32W, + ICLASS_AE_MULF2D32X2WS, + ICLASS_AE_MULZAAAA2Q16, + ICLASS_AE_MULAAAA2Q16, + ICLASS_AE_MULP16S_H, + ICLASS_AE_MULAP16S_H, + ICLASS_AE_MULSP16S_H, + ICLASS_AE_MULP16S_L, + ICLASS_AE_MULAP16S_L, + ICLASS_AE_MULSP16S_L, + ICLASS_AE_MULC16W_H, + ICLASS_AE_MULAC16W_H, + ICLASS_AE_MULC16W_L, + ICLASS_AE_MULAC16W_L, + ICLASS_AE_MUL2C16S, + ICLASS_AE_MULA2C16S, + ICLASS_AE_MULFC16S, + ICLASS_AE_MULAFC16S, + ICLASS_AE_MULFCJ16S, + ICLASS_AE_MULAFCJ16S, + ICLASS_AE_MULFCJ16RAS, + ICLASS_AE_MULAFCJ16RAS, + ICLASS_AE_MULC16S, + ICLASS_AE_MULAC16S, + ICLASS_AE_MULFP16X4RS, + ICLASS_AE_MULFD16X16X4RAS, + ICLASS_AE_MULP16X16X4S, + ICLASS_AE_MULAP16X16X4S, + ICLASS_AE_MULSP16X16X4S, + ICLASS_AE_MULZAA2D16SS_HH_LL, + ICLASS_AE_MULZAA2D16SS_HL_LH, + ICLASS_AE_MULZSS2D16SS_HH_LL, + ICLASS_AE_MULZSS2D16SS_HL_LH, + ICLASS_AE_MULAA2D16SS_HH_LL, + ICLASS_AE_MULAA2D16SS_HL_LH, + ICLASS_AE_MULSS2D16SS_HH_LL, + ICLASS_AE_MULSS2D16SS_HL_LH, + ICLASS_AE_MULZAAFD16SS_HH_LL, + ICLASS_AE_MULZAAFD16SS_HL_LH, + ICLASS_AE_MULZSSFD16SS_HH_LL, + ICLASS_AE_MULZSSFD16SS_HL_LH, + ICLASS_AE_MULAAFD16SS_HH_LL, + ICLASS_AE_MULAAFD16SS_HL_LH, + ICLASS_AE_MULSSFD16SS_HH_LL, + ICLASS_AE_MULSSFD16SS_HL_LH, + ICLASS_AE_MULFD16X16X4WS, + ICLASS_AE_MULZAAAA2Q16X8, + ICLASS_AE_MULAAAA2Q16X8, + ICLASS_AE_MULZAAAA2Q8, + ICLASS_AE_MULAAAA2Q8, + ICLASS_AE_MULC32X16W_H, + ICLASS_AE_MULAC32X16W_H, + ICLASS_AE_MULC32X16W_L, + ICLASS_AE_MULAC32X16W_L, + ICLASS_AE_MULPC32X16X2, + ICLASS_AE_MULAPC32X16X2, + ICLASS_AE_MULFP32X16_H, + ICLASS_AE_MULAFP32X16_H, + ICLASS_AE_MULSFP32X16_H, + ICLASS_AE_MULFP32X16_L, + ICLASS_AE_MULAFP32X16_L, + ICLASS_AE_MULSFP32X16_L, + ICLASS_AE_MULFC32X16W_H, + ICLASS_AE_MULAFC32X16W_H, + ICLASS_AE_MULFC32X16W_L, + ICLASS_AE_MULAFC32X16W_L, + ICLASS_AE_MULFCJ32X16W_H, + ICLASS_AE_MULAFCJ32X16W_H, + ICLASS_AE_MULFCJ32X16W_L, + ICLASS_AE_MULAFCJ32X16W_L, + ICLASS_AE_MULF2P32X16X4RAS, + ICLASS_AE_MULAF2P32X16X4RAS, + ICLASS_AE_MULSF2P32X16X4RAS, + ICLASS_AE_MULF2P32X16X4RS, + ICLASS_AE_MULAF2P32X16X4RS, + ICLASS_AE_MULSF2P32X16X4RS, + ICLASS_AE_MULF2P32X16X4S, + ICLASS_AE_MULAF2P32X16X4S, + ICLASS_AE_MULSF2P32X16X4S, + ICLASS_AE_MULFPC32X16X2RAS, + ICLASS_AE_MULAFPC32X16X2RAS, + ICLASS_AE_MULFPCJ32X16X2RAS, + ICLASS_AE_MULAFPCJ32X16X2RAS, + ICLASS_AE_MULZAAAA2Q32X16, + ICLASS_AE_MULAAAA2Q32X16, + ICLASS_AE_MUL2Q32X16_FIR_H, + ICLASS_AE_MULA2Q32X16_FIR_H, + ICLASS_AE_MUL2Q32X16_FIR_L, + ICLASS_AE_MULA2Q32X16_FIR_L, + ICLASS_AE_SRAI8, + ICLASS_AE_SRAI8R, + ICLASS_AE_SRLI8, + ICLASS_AE_SLAI8, + ICLASS_AE_SLAI8S, + ICLASS_AE_SLAA8, + ICLASS_AE_SRLA8, + ICLASS_AE_SLAA8S, + ICLASS_AE_SRAA8RS, + ICLASS_AE_SRAA8S, + ICLASS_AE_SRLI16, + ICLASS_AE_SLAI16, + ICLASS_AE_SLAA16, + ICLASS_AE_SRLA16, + ICLASS_AE_SRAI16SYM, + ICLASS_AE_SRAA16SYMS, + ICLASS_AE_SRAI32SYM, + ICLASS_AE_SRAA32SYMS, + ICLASS_AE_SRAV16RS, + ICLASS_AE_SRAV32RS, + ICLASS_AE_CVTI32X4F8_H, + ICLASS_AE_CVTI32X4F8_L, + ICLASS_AE_CVTI32X4F8S_H, + ICLASS_AE_CVTI32X4F8S_L, + ICLASS_AE_CVTA32X4F8_H, + ICLASS_AE_CVTA32X4F8_L, + ICLASS_AE_CVTA32X4F8S_H, + ICLASS_AE_CVTA32X4F8S_L, + ICLASS_AE_CVTI32X4F8U_H, + ICLASS_AE_CVTI32X4F8U_L, + ICLASS_AE_CVTI32X4F8US_H, + ICLASS_AE_CVTI32X4F8US_L, + ICLASS_AE_CVTA32X4F8U_H, + ICLASS_AE_CVTA32X4F8U_L, + ICLASS_AE_CVTA32X4F8US_H, + ICLASS_AE_CVTA32X4F8US_L, + ICLASS_AE_CVTI32X4F16, + ICLASS_AE_CVTI32X4F16S, + ICLASS_AE_CVTA32X4F16, + ICLASS_AE_CVTA32X4F16S, + ICLASS_AE_CVTI32X4F16U, + ICLASS_AE_CVTI32X4F16US, + ICLASS_AE_CVTA32X4F16U, + ICLASS_AE_CVTA32X4F16US, + ICLASS_AE_CVTI16X4X2F8, + ICLASS_AE_CVTI16X4X2F8S, + ICLASS_AE_CVTA16X4X2F8, + ICLASS_AE_CVTA16X4X2F8S, + ICLASS_AE_CVTI16X4X2F8U, + ICLASS_AE_CVTI16X4X2F8US, + ICLASS_AE_CVTA16X4X2F8U, + ICLASS_AE_CVTA16X4X2F8US, + ICLASS_AE_SEL8X8, + ICLASS_AE_SHFL8X8, + ICLASS_AE_SEL16X4, + ICLASS_AE_SHFL16X4, + ICLASS_AE_DSEL8X8, + ICLASS_AE_DSEL16X4, + ICLASS_AE_SEL8X8I, + ICLASS_AE_RMAX8X8, + ICLASS_AE_RMIN8X8, + ICLASS_AE_RMAX16X4, + ICLASS_AE_RMIN16X4, + ICLASS_AE_SORT16X4, + ICLASS_AE_RADD8X8_H, + ICLASS_AE_RADDA8X8_H, + ICLASS_AE_RADD8X8_L, + ICLASS_AE_RADDA8X8_L, + ICLASS_AE_RADD16X4, + ICLASS_AE_RADDA16X4, + ICLASS_AE_BMAX8X8_H, + ICLASS_AE_BMAX8X8_L, + ICLASS_AE_BMIN8X8_H, + ICLASS_AE_BMIN8X8_L, + ICLASS_AE_BMAX16X4, + ICLASS_AE_BMIN16X4, + ICLASS_AE_BMAX32X2, + ICLASS_AE_BMIN32X2, + ICLASS_AE_ADDINV16S, + ICLASS_AE_ADDINV32S, + ICLASS_AE_MOVT16X8, + ICLASS_AE_MOVT8X16_H, + ICLASS_AE_MOVT8X16_L, + ICLASS_AE_MOVBD1X4, + ICLASS_AE_MOVBD1X2, + ICLASS_AE_MOVNEG32S_T, + ICLASS_AE_MOVDEXT, + ICLASS_AE_MOVADEXT_H, + ICLASS_AE_MOVADEXT_L, + ICLASS_AE_NSA16X4, + ICLASS_AE_NSAZ32X4, + ICLASS_AE_NSA32X4, + ICLASS_AE_TRUNCI16X4F32S, + ICLASS_AE_TRUNCI16X4F64S, + ICLASS_AE_TRUNCA16X4F32S, + ICLASS_AE_TRUNCA16X4F64S, + ICLASS_AE_ADDC32, + ICLASS_AE_SUBC32, + ICLASS_AE_ADDC32U, + ICLASS_AE_SUBC32U, + ICLASS_AE_EXPADD16_H, + ICLASS_AE_EXPSUB16_H, + ICLASS_AE_EXPADD16_L, + ICLASS_AE_EXPSUB16_L, + ICLASS_AE_ADDCEXP32_H, + ICLASS_AE_ADDCEXP32_L, + ICLASS_AE_CALCRNG16, + ICLASS_AE_CALCRNG32, + ICLASS_AE_RNG32X4, + ICLASS_AE_LAV8X8X2_XP, + ICLASS_AE_LAV16X4X2_XP, + ICLASS_AE_SAV8X8X2_XP, + ICLASS_AE_SAV16X4X2_XP, + ICLASS_AE_MOVZBVCDR, + ICLASS_AE_MOVDRZBVC, + ICLASS_AE_LAVUNSQZ8X8_XP, + ICLASS_AE_LAVUNSQZ16X4_XP, + ICLASS_AE_MUL8Q8X8, + ICLASS_AE_MULA8Q8X8, + ICLASS_AE_MUL8Q4X16, + ICLASS_AE_MULA8Q4X16, + ICLASS_AE_MUL8Q8X16, + ICLASS_AE_MULA8Q8X16, + ICLASS_AE_MUL8QW8X16, + ICLASS_AE_MULA8QW8X16, + ICLASS_AE_MUL4O8X8, + ICLASS_AE_MULA4O8X8, + ICLASS_AE_MUL4O4X16, + ICLASS_AE_MULA4O4X16, + ICLASS_AE_MUL4O8X16, + ICLASS_AE_MULA4O8X16, + ICLASS_AE_MUL4QW8X16, + ICLASS_AE_MULA4QW8X16, + ICLASS_AE_MUL8Q8X8CNV_L, + ICLASS_AE_MUL8Q8X8CNV_H, + ICLASS_AE_MULA8Q8X8CNV_L, + ICLASS_AE_MULA8Q8X8CNV_H, + ICLASS_AE_MUL8Q8X16CNV, + ICLASS_AE_MULA8Q8X16CNV, + ICLASS_AE_MUL2X4Q8X8CNV_H, + ICLASS_AE_MULA2X4Q8X8CNV_H, + ICLASS_AE_MUL2X4Q8X8CNV_L, + ICLASS_AE_MULA2X4Q8X8CNV_L, + ICLASS_AE_MUL2X4Q8X16CNV, + ICLASS_AE_MULA2X4Q8X16CNV, + ICLASS_AE_MULQQ8X16CNV, + ICLASS_AE_MULAQQ8X16CNV, + ICLASS_AE_MUL4O8X8CNV_H, + ICLASS_AE_MULA4O8X8CNV_H, + ICLASS_AE_MUL4O8X8CNV_L, + ICLASS_AE_MULA4O8X8CNV_L, + ICLASS_AE_MUL4O8X16CNV_H, + ICLASS_AE_MULA4O8X16CNV_H, + ICLASS_AE_MUL4O8X16CNV_L, + ICLASS_AE_MULA4O8X16CNV_L, + ICLASS_AE_MUL8Q4X16CNV_H, + ICLASS_AE_MULA8Q4X16CNV_H, + ICLASS_AE_MUL8Q4X16CNV_L, + ICLASS_AE_MULA8Q4X16CNV_L, + ICLASS_AE_MUL2X4Q4X16CNV_H, + ICLASS_AE_MULA2X4Q4X16CNV_H, + ICLASS_AE_MUL2X4Q4X16CNV_L, + ICLASS_AE_MULA2X4Q4X16CNV_L, + ICLASS_AE_MULQQ4X16CNV_H, + ICLASS_AE_MULAQQ4X16CNV_H, + ICLASS_AE_MULQQ4X16CNV_L, + ICLASS_AE_MULAQQ4X16CNV_L, + ICLASS_AE_MUL4O4X16CNV_HH, + ICLASS_AE_MUL4O4X16CNV_HL, + ICLASS_AE_MUL4O4X16CNV_LH, + ICLASS_AE_MUL4O4X16CNV_LL, + ICLASS_AE_MULA4O4X16CNV_HH, + ICLASS_AE_MULA4O4X16CNV_HL, + ICLASS_AE_MULA4O4X16CNV_LH, + ICLASS_AE_MULA4O4X16CNV_LL, + ICLASS_AE_MULUU8Q8X8, + ICLASS_AE_MULAUU8Q8X8, + ICLASS_AE_MULUU4O8X8, + ICLASS_AE_MULAUU4O8X8, + ICLASS_AE_MULUU8Q8X8CNV_L, + ICLASS_AE_MULAUU8Q8X8CNV_L, + ICLASS_AE_MULUU8Q8X8CNV_H, + ICLASS_AE_MULAUU8Q8X8CNV_H, + ICLASS_AE_MULUU2X4Q8X8CNV_H, + ICLASS_AE_MULAUU2X4Q8X8CNV_H, + ICLASS_AE_MULUU2X4Q8X8CNV_L, + ICLASS_AE_MULAUU2X4Q8X8CNV_L, + ICLASS_AE_MULUU4O8X8CNV_H, + ICLASS_AE_MULAUU4O8X8CNV_H, + ICLASS_AE_MULUU4O8X8CNV_L, + ICLASS_AE_MULAUU4O8X8CNV_L, + ICLASS_AE_MULUS8Q8X8, + ICLASS_AE_MULAUS8Q8X8, + ICLASS_AE_MULUS8Q4X16, + ICLASS_AE_MULAUS8Q4X16, + ICLASS_AE_MULUS8Q8X16, + ICLASS_AE_MULAUS8Q8X16, + ICLASS_AE_MULUS8QW8X16, + ICLASS_AE_MULAUS8QW8X16, + ICLASS_AE_MULUS4O8X8, + ICLASS_AE_MULAUS4O8X8, + ICLASS_AE_MULUS4O4X16, + ICLASS_AE_MULAUS4O4X16, + ICLASS_AE_MULUS4O8X16, + ICLASS_AE_MULAUS4O8X16, + ICLASS_AE_MULUS4QW8X16, + ICLASS_AE_MULAUS4QW8X16, + ICLASS_AE_MULUS8Q8X8CNV_L, + ICLASS_AE_MULAUS8Q8X8CNV_L, + ICLASS_AE_MULUS8Q8X8CNV_H, + ICLASS_AE_MULAUS8Q8X8CNV_H, + ICLASS_AE_MULUS8Q8X16CNV, + ICLASS_AE_MULAUS8Q8X16CNV, + ICLASS_AE_MULUS2X4Q8X8CNV_H, + ICLASS_AE_MULAUS2X4Q8X8CNV_H, + ICLASS_AE_MULUS2X4Q8X8CNV_L, + ICLASS_AE_MULAUS2X4Q8X8CNV_L, + ICLASS_AE_MULUS2X4Q8X16CNV, + ICLASS_AE_MULAUS2X4Q8X16CNV, + ICLASS_AE_MULUSQQ8X16CNV, + ICLASS_AE_MULAUSQQ8X16CNV, + ICLASS_AE_MULUS4O8X8CNV_H, + ICLASS_AE_MULAUS4O8X8CNV_H, + ICLASS_AE_MULUS4O8X8CNV_L, + ICLASS_AE_MULAUS4O8X8CNV_L, + ICLASS_AE_MULUS4O8X16CNV_H, + ICLASS_AE_MULAUS4O8X16CNV_H, + ICLASS_AE_MULUS4O8X16CNV_L, + ICLASS_AE_MULAUS4O8X16CNV_L, + ICLASS_AE_MULUS8Q4X16CNV_H, + ICLASS_AE_MULAUS8Q4X16CNV_H, + ICLASS_AE_MULUS8Q4X16CNV_L, + ICLASS_AE_MULAUS8Q4X16CNV_L, + ICLASS_AE_MULUS2X4Q4X16CNV_H, + ICLASS_AE_MULAUS2X4Q4X16CNV_H, + ICLASS_AE_MULUS2X4Q4X16CNV_L, + ICLASS_AE_MULAUS2X4Q4X16CNV_L, + ICLASS_AE_MULUSQQ4X16CNV_H, + ICLASS_AE_MULAUSQQ4X16CNV_H, + ICLASS_AE_MULUSQQ4X16CNV_L, + ICLASS_AE_MULAUSQQ4X16CNV_L, + ICLASS_AE_MULUS4O4X16CNV_HH, + ICLASS_AE_MULUS4O4X16CNV_HL, + ICLASS_AE_MULUS4O4X16CNV_LH, + ICLASS_AE_MULUS4O4X16CNV_LL, + ICLASS_AE_MULAUS4O4X16CNV_HH, + ICLASS_AE_MULAUS4O4X16CNV_HL, + ICLASS_AE_MULAUS4O4X16CNV_LH, + ICLASS_AE_MULAUS4O4X16CNV_LL, + ICLASS_AE_MULSU8Q8X8, + ICLASS_AE_MULASU8Q8X8, + ICLASS_AE_MULSU4O8X8, + ICLASS_AE_MULASU4O8X8, + ICLASS_AE_MULSU8Q8X8CNV_L, + ICLASS_AE_MULASU8Q8X8CNV_L, + ICLASS_AE_MULSU8Q8X8CNV_H, + ICLASS_AE_MULASU8Q8X8CNV_H, + ICLASS_AE_MULSU2X4Q8X8CNV_H, + ICLASS_AE_MULASU2X4Q8X8CNV_H, + ICLASS_AE_MULSU2X4Q8X8CNV_L, + ICLASS_AE_MULASU2X4Q8X8CNV_L, + ICLASS_AE_MULSU4O8X8CNV_H, + ICLASS_AE_MULASU4O8X8CNV_H, + ICLASS_AE_MULSU4O8X8CNV_L, + ICLASS_AE_MULASU4O8X8CNV_L, + ICLASS_AE_MULUUZB8Q8X8, + ICLASS_AE_MULAUUZB8Q8X8, + ICLASS_AE_MULUUZB4O8X8, + ICLASS_AE_MULAUUZB4O8X8, + ICLASS_AE_MULUUZB8Q8X8CNV_L, + ICLASS_AE_MULAUUZB8Q8X8CNV_L, + ICLASS_AE_MULUUZB8Q8X8CNV_H, + ICLASS_AE_MULAUUZB8Q8X8CNV_H, + ICLASS_AE_MULUUZB2X4Q8X8CNV_H, + ICLASS_AE_MULAUUZB2X4Q8X8CNV_H, + ICLASS_AE_MULUUZB2X4Q8X8CNV_L, + ICLASS_AE_MULAUUZB2X4Q8X8CNV_L, + ICLASS_AE_MULUUZB4O8X8CNV_H, + ICLASS_AE_MULAUUZB4O8X8CNV_H, + ICLASS_AE_MULUUZB4O8X8CNV_L, + ICLASS_AE_MULAUUZB4O8X8CNV_L, + ICLASS_AE_MULUUZB3X3O8X8, + ICLASS_AE_MULAUUZB3X3O8X8, + ICLASS_AE_MULZB8Q8X8, + ICLASS_AE_MULAZB8Q8X8, + ICLASS_AE_MULZB4O8X8, + ICLASS_AE_MULAZB4O8X8, + ICLASS_AE_MULZB8Q8X8CNV_L, + ICLASS_AE_MULAZB8Q8X8CNV_L, + ICLASS_AE_MULZB8Q8X8CNV_H, + ICLASS_AE_MULAZB8Q8X8CNV_H, + ICLASS_AE_MULZB2X4Q8X8CNV_H, + ICLASS_AE_MULAZB2X4Q8X8CNV_H, + ICLASS_AE_MULZB2X4Q8X8CNV_L, + ICLASS_AE_MULAZB2X4Q8X8CNV_L, + ICLASS_AE_MULZB4O8X8CNV_H, + ICLASS_AE_MULAZB4O8X8CNV_H, + ICLASS_AE_MULZB4O8X8CNV_L, + ICLASS_AE_MULAZB4O8X8CNV_L, + ICLASS_AE_MULZB3X3O8X8, + ICLASS_AE_MULAZB3X3O8X8, + ICLASS_CVTSF16_L, + ICLASS_CVTSF16_H, + ICLASS_CVTF16S_L, + ICLASS_CVTF16S_H, + ICLASS_AE_MOVFCRFSRV, + ICLASS_AE_MOVVFCRFSR, + ICLASS_MOVT_S, + ICLASS_MOVF_S, + ICLASS_MOVEQZ_S, + ICLASS_MOVNEZ_S, + ICLASS_MOVGEZ_S, + ICLASS_MOVLTZ_S, + ICLASS_RFR, + ICLASS_WFR, + ICLASS_MUL_S, + ICLASS_MADD_S, + ICLASS_MSUB_S, + ICLASS_MSUBN_S, + ICLASS_MADDN_S, + ICLASS_ADD_S, + ICLASS_SUB_S, + ICLASS_OLE_S, + ICLASS_OLT_S, + ICLASS_OEQ_S, + ICLASS_UN_S, + ICLASS_ULE_S, + ICLASS_ULT_S, + ICLASS_UEQ_S, + ICLASS_NEXP01_S, + ICLASS_MKSADJ_S, + ICLASS_MKDADJ_S, + ICLASS_DIV0_S, + ICLASS_SQRT0_S, + ICLASS_RECIP0_S, + ICLASS_RSQRT0_S, + ICLASS_DIVN_S, + ICLASS_ADDEXP_S, + ICLASS_ADDEXPM_S, + ICLASS_MIN_S, + ICLASS_MAX_S, + ICLASS_MULMUX_S, + ICLASS_MADDMUX_S, + ICLASS_TRUNC_S, + ICLASS_UTRUNC_S, + ICLASS_TRUNC_SX2, + ICLASS_UTRUNC_SX2, + ICLASS_FICEIL_S, + ICLASS_FIFLOOR_S, + ICLASS_FIRINT_S, + ICLASS_FIROUND_S, + ICLASS_FITRUNC_S, + ICLASS_FLOAT_S, + ICLASS_UFLOAT_S, + ICLASS_FLOAT_SX2, + ICLASS_UFLOAT_SX2, + ICLASS_ABS_S, + ICLASS_NEG_S, + ICLASS_CONJC_S, + ICLASS_MULJC_S, + ICLASS_CONST_S, + ICLASS_CLSFY_S, + ICLASS_MINNUM_S, + ICLASS_MAXNUM_S, + ICLASS_ADDANDSUB_S, + ICLASS_ADDANDSUBJC_S, + ICLASS_ADD_HL_LH_S, + ICLASS_MADDA_S, + ICLASS_FREXP_S, + ICLASS_FLOATEXP_S, + ICLASS_MINNUMABS_S, + ICLASS_MAXNUMABS_S, + ICLASS_MULQ_S, + ICLASS_MADDQ_S, + ICLASS_MSUBQ_S, + ICLASS_MULMUXQ_S, + ICLASS_MADDMUXQ_S, + ICLASS_BMAXNUM_S, + ICLASS_BMINNUM_S, + ICLASS_BMAXNUMABS_S, + ICLASS_BMINNUMABS_S, + ICLASS_ABS_SX2X2, + ICLASS_NEG_SX2X2, + ICLASS_CONJC_SX2X2, + ICLASS_MULJC_SX2X2, + ICLASS_CONST_SX2X2, + ICLASS_ADD_SX2X2, + ICLASS_SUB_SX2X2, + ICLASS_MUL_SX2X2, + ICLASS_MADD_SX2X2, + ICLASS_MSUB_SX2X2, + ICLASS_MULMUX_SX2X2, + ICLASS_MADDMUX_SX2X2, + ICLASS_ABS_H, + ICLASS_ADDEXP_H, + ICLASS_ADDEXPM_H, + ICLASS_CLSFY_H, + ICLASS_CONJC_H, + ICLASS_CONST_H, + ICLASS_MIN_H, + ICLASS_MAX_H, + ICLASS_MINNUM_H, + ICLASS_MAXNUM_H, + ICLASS_MULJC_H, + ICLASS_NEG_H, + ICLASS_OEQ_H, + ICLASS_OLE_H, + ICLASS_OLT_H, + ICLASS_UEQ_H, + ICLASS_ULE_H, + ICLASS_ULT_H, + ICLASS_UN_H, + ICLASS_DIV0_H, + ICLASS_FICEIL_H, + ICLASS_FIFLOOR_H, + ICLASS_FIRINT_H, + ICLASS_FIROUND_H, + ICLASS_FITRUNC_H, + ICLASS_MKDADJ_H, + ICLASS_MKSADJ_H, + ICLASS_NEXP0_H, + ICLASS_NEXP01_H, + ICLASS_RECIP0_H, + ICLASS_RSQRT0_H, + ICLASS_SQRT0_H, + ICLASS_FLOAT16_H, + ICLASS_UFLOAT16_H, + ICLASS_TRUNC16_H, + ICLASS_UTRUNC16_H, + ICLASS_FLOAT16_HX4, + ICLASS_UFLOAT16_HX4, + ICLASS_TRUNC16_HX4, + ICLASS_UTRUNC16_HX4, + ICLASS_ADD_H, + ICLASS_SUB_H, + ICLASS_MUL_H, + ICLASS_MADD_H, + ICLASS_MSUB_H, + ICLASS_MADDN_H, + ICLASS_MSUBN_H, + ICLASS_DIVN_H, + ICLASS_RMINNUM_H, + ICLASS_RMAXNUM_H, + ICLASS_ABS_HX4X2, + ICLASS_NEG_HX4X2, + ICLASS_CONJC_HX4X2, + ICLASS_CONST_HX4X2, + ICLASS_MULJC_HX4X2, + ICLASS_ADD_HX4X2, + ICLASS_SUB_HX4X2, + ICLASS_MUL_HX4X2, + ICLASS_MADD_HX4X2, + ICLASS_MSUB_HX4X2, + ICLASS_MULQ_H, + ICLASS_MADDQ_H, + ICLASS_MULCNVH_HX4X2, + ICLASS_MULACNVH_HX4X2, + ICLASS_MULCNVL_HX4X2, + ICLASS_MULACNVL_HX4X2 +}; + + +/* Opcode encodings. */ + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408000; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf01d; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3400; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3500; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34800; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134800; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614800; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34900; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134900; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614900; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf06d; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03d; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00d; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e70; +} + +static void +Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e700; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_addi_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e0000; +} + +static void +Opcode_addi_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_addi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6e0000; + slotbuf[1] = 0; +} + +static void +Opcode_addi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01000; + slotbuf[1] = 0; +} + +static void +Opcode_addi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103e0000; + slotbuf[1] = 0; +} + +static void +Opcode_addi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_addi_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000; +} + +static void +Opcode_addi_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_addi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10360000; +} + +static void +Opcode_addi_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2642000; +} + +static void +Opcode_addi_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308000; +} + +static void +Opcode_addi_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2360000; +} + +static void +Opcode_addi_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340000; +} + +static void +Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb900000; +} + +static void +Opcode_addi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340000; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002; +} + +static void +Opcode_addmi_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f0000; +} + +static void +Opcode_addmi_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1250000; +} + +static void +Opcode_addmi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6f0000; + slotbuf[1] = 0; +} + +static void +Opcode_addmi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01200; + slotbuf[1] = 0; +} + +static void +Opcode_addmi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103e2000; + slotbuf[1] = 0; +} + +static void +Opcode_addmi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_addmi_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000; +} + +static void +Opcode_addmi_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_addmi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10370000; +} + +static void +Opcode_addmi_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2643000; +} + +static void +Opcode_addmi_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130c000; +} + +static void +Opcode_addmi_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2370000; +} + +static void +Opcode_addmi_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1350000; +} + +static void +Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb901000; +} + +static void +Opcode_addmi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1350000; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_add_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc48000; +} + +static void +Opcode_add_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144c000; +} + +static void +Opcode_add_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ba000; + slotbuf[1] = 0; +} + +static void +Opcode_add_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e12000; + slotbuf[1] = 0; +} + +static void +Opcode_add_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10724000; + slotbuf[1] = 0; +} + +static void +Opcode_add_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4000; +} + +static void +Opcode_add_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c4000; +} + +static void +Opcode_add_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c000; +} + +static void +Opcode_add_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10614000; +} + +static void +Opcode_add_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a09000; +} + +static void +Opcode_add_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1588000; +} + +static void +Opcode_add_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2750000; +} + +static void +Opcode_add_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154e000; +} + +static void +Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a79004; +} + +static void +Opcode_add_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154c000; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addx2_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc49000; +} + +static void +Opcode_addx2_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144d000; +} + +static void +Opcode_addx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74bb000; + slotbuf[1] = 0; +} + +static void +Opcode_addx2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1a000; + slotbuf[1] = 0; +} + +static void +Opcode_addx2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10725000; + slotbuf[1] = 0; +} + +static void +Opcode_addx2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a5000; +} + +static void +Opcode_addx2_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c5000; +} + +static void +Opcode_addx2_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29d000; +} + +static void +Opcode_addx2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10615000; +} + +static void +Opcode_addx2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0d000; +} + +static void +Opcode_addx2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c8000; +} + +static void +Opcode_addx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2751000; +} + +static void +Opcode_addx2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f000; +} + +static void +Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b79004; +} + +static void +Opcode_addx2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154d000; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_addx4_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc88000; +} + +static void +Opcode_addx4_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148c000; +} + +static void +Opcode_addx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74bc000; + slotbuf[1] = 0; +} + +static void +Opcode_addx4_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e42000; + slotbuf[1] = 0; +} + +static void +Opcode_addx4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10726000; + slotbuf[1] = 0; +} + +static void +Opcode_addx4_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6000; +} + +static void +Opcode_addx4_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c6000; +} + +static void +Opcode_addx4_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29e000; +} + +static void +Opcode_addx4_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10616000; +} + +static void +Opcode_addx4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a11000; +} + +static void +Opcode_addx4_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1589000; +} + +static void +Opcode_addx4_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2752000; +} + +static void +Opcode_addx4_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158e000; +} + +static void +Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9928000; +} + +static void +Opcode_addx4_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158c000; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_addx8_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc89000; +} + +static void +Opcode_addx8_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148d000; +} + +static void +Opcode_addx8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74bd000; + slotbuf[1] = 0; +} + +static void +Opcode_addx8_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e4a000; + slotbuf[1] = 0; +} + +static void +Opcode_addx8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10727000; + slotbuf[1] = 0; +} + +static void +Opcode_addx8_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a7000; +} + +static void +Opcode_addx8_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c7000; +} + +static void +Opcode_addx8_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29f000; +} + +static void +Opcode_addx8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10617000; +} + +static void +Opcode_addx8_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a15000; +} + +static void +Opcode_addx8_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c9000; +} + +static void +Opcode_addx8_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2753000; +} + +static void +Opcode_addx8_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158f000; +} + +static void +Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9968000; +} + +static void +Opcode_addx8_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158d000; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_sub_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4d000; +} + +static void +Opcode_sub_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1451000; +} + +static void +Opcode_sub_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74eb000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eba000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072a000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6000; +} + +static void +Opcode_sub_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d5000; +} + +static void +Opcode_sub_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ad000; +} + +static void +Opcode_sub_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064b000; +} + +static void +Opcode_sub_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a4d000; +} + +static void +Opcode_sub_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154d000; +} + +static void +Opcode_sub_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2761000; +} + +static void +Opcode_sub_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1553000; +} + +static void +Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a7900c; +} + +static void +Opcode_sub_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1551000; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_subx2_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8c000; +} + +static void +Opcode_subx2_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1490000; +} + +static void +Opcode_subx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ec000; + slotbuf[1] = 0; +} + +static void +Opcode_subx2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec2000; + slotbuf[1] = 0; +} + +static void +Opcode_subx2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072b000; + slotbuf[1] = 0; +} + +static void +Opcode_subx2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7000; +} + +static void +Opcode_subx2_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d6000; +} + +static void +Opcode_subx2_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ae000; +} + +static void +Opcode_subx2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064d000; +} + +static void +Opcode_subx2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a51000; +} + +static void +Opcode_subx2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158d000; +} + +static void +Opcode_subx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2762000; +} + +static void +Opcode_subx2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1592000; +} + +static void +Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b7100c; +} + +static void +Opcode_subx2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1590000; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_subx4_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8d000; +} + +static void +Opcode_subx4_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1491000; +} + +static void +Opcode_subx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ed000; + slotbuf[1] = 0; +} + +static void +Opcode_subx4_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eca000; + slotbuf[1] = 0; +} + +static void +Opcode_subx4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072c000; + slotbuf[1] = 0; +} + +static void +Opcode_subx4_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8000; +} + +static void +Opcode_subx4_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d7000; +} + +static void +Opcode_subx4_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2af000; +} + +static void +Opcode_subx4_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064f000; +} + +static void +Opcode_subx4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a55000; +} + +static void +Opcode_subx4_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cd000; +} + +static void +Opcode_subx4_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2763000; +} + +static void +Opcode_subx4_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1593000; +} + +static void +Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b7900c; +} + +static void +Opcode_subx4_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1591000; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_subx8_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xccc000; +} + +static void +Opcode_subx8_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d0000; +} + +static void +Opcode_subx8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ee000; + slotbuf[1] = 0; +} + +static void +Opcode_subx8_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ed2000; + slotbuf[1] = 0; +} + +static void +Opcode_subx8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072d000; + slotbuf[1] = 0; +} + +static void +Opcode_subx8_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b9000; +} + +static void +Opcode_subx8_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d8000; +} + +static void +Opcode_subx8_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0000; +} + +static void +Opcode_subx8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10651000; +} + +static void +Opcode_subx8_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a59000; +} + +static void +Opcode_subx8_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150e000; +} + +static void +Opcode_subx8_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2764000; +} + +static void +Opcode_subx8_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d2000; +} + +static void +Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9920008; +} + +static void +Opcode_subx8_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d0000; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_and_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc8000; +} + +static void +Opcode_and_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14cc000; +} + +static void +Opcode_and_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74be000; + slotbuf[1] = 0; +} + +static void +Opcode_and_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e52000; + slotbuf[1] = 0; +} + +static void +Opcode_and_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054b000; + slotbuf[1] = 0; +} + +static void +Opcode_and_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9000; +} + +static void +Opcode_and_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c8000; +} + +static void +Opcode_and_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0000; +} + +static void +Opcode_and_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10638000; +} + +static void +Opcode_and_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a19000; +} + +static void +Opcode_and_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150a000; +} + +static void +Opcode_and_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2754000; +} + +static void +Opcode_and_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ce000; +} + +static void +Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9920004; +} + +static void +Opcode_and_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cc000; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_or_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xccb000; +} + +static void +Opcode_or_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14cf000; +} + +static void +Opcode_or_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e7000; + slotbuf[1] = 0; +} + +static void +Opcode_or_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e9a000; + slotbuf[1] = 0; +} + +static void +Opcode_or_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1075d000; + slotbuf[1] = 0; +} + +static void +Opcode_or_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2000; +} + +static void +Opcode_or_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d1000; +} + +static void +Opcode_or_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a9000; +} + +static void +Opcode_or_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10643000; +} + +static void +Opcode_or_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_or_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a3d000; +} + +static void +Opcode_or_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154c000; +} + +static void +Opcode_or_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275d000; +} + +static void +Opcode_or_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d1000; +} + +static void +Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a79008; +} + +static void +Opcode_or_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cf000; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_xor_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xccd000; +} + +static void +Opcode_xor_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d1000; +} + +static void +Opcode_xor_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ef000; + slotbuf[1] = 0; +} + +static void +Opcode_xor_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eda000; + slotbuf[1] = 0; +} + +static void +Opcode_xor_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072e000; + slotbuf[1] = 0; +} + +static void +Opcode_xor_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba000; +} + +static void +Opcode_xor_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d9000; +} + +static void +Opcode_xor_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b1000; +} + +static void +Opcode_xor_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10653000; +} + +static void +Opcode_xor_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa01000; +} + +static void +Opcode_xor_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a5d000; +} + +static void +Opcode_xor_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154e000; +} + +static void +Opcode_xor_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2765000; +} + +static void +Opcode_xor_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d3000; +} + +static void +Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9960008; +} + +static void +Opcode_xor_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d1000; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6007; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe007; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4007; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5007; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd007; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1007; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa007; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb007; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2007; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3007; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc007; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9007; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_call0_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940000; +} + +static void +Opcode_call0_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d620000; + slotbuf[1] = 0; +} + +static void +Opcode_call0_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340000; + slotbuf[1] = 0; +} + +static void +Opcode_call0_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_call0_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0000; +} + +static void +Opcode_call0_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c0000; +} + +static void +Opcode_call0_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22c0000; +} + +static void +Opcode_call0_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7300000; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_callx0_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21003; +} + +static void +Opcode_callx0_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520205; + slotbuf[1] = 0; +} + +static void +Opcode_callx0_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10587bc0; + slotbuf[1] = 0; +} + +static void +Opcode_callx0_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6402; +} + +static void +Opcode_callx0_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d230; +} + +static void +Opcode_callx0_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d001; +} + +static void +Opcode_callx0_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781003; +} + +static void +Opcode_callx0_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e10e0; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_extui_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0000; +} + +static void +Opcode_extui_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_extui_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6a0000; + slotbuf[1] = 0; +} + +static void +Opcode_extui_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00000; + slotbuf[1] = 0; +} + +static void +Opcode_extui_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103c0000; + slotbuf[1] = 0; +} + +static void +Opcode_extui_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_extui_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_extui_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_extui_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340000; +} + +static void +Opcode_extui_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2640000; +} + +static void +Opcode_extui_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_extui_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2340000; +} + +static void +Opcode_extui_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_extui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa900000; +} + +static void +Opcode_extui_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_j_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_j_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d600000; + slotbuf[1] = 0; +} + +static void +Opcode_j_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300000; + slotbuf[1] = 0; +} + +static void +Opcode_j_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_j_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280000; +} + +static void +Opcode_j_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2580000; +} + +static void +Opcode_j_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2280000; +} + +static void +Opcode_j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7200000; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; +} + +static void +Opcode_jx_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21203; +} + +static void +Opcode_jx_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520a05; + slotbuf[1] = 0; +} + +static void +Opcode_jx_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef00; + slotbuf[1] = 0; +} + +static void +Opcode_jx_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6404; +} + +static void +Opcode_jx_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d430; +} + +static void +Opcode_jx_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d201; +} + +static void +Opcode_jx_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781203; +} + +static void +Opcode_jx_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e12e0; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1002; +} + +static void +Opcode_l16ui_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa40000; +} + +static void +Opcode_l16ui_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_l16ui_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7c0000; + slotbuf[1] = 0; +} + +static void +Opcode_l16ui_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c02200; + slotbuf[1] = 0; +} + +static void +Opcode_l16ui_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10402000; + slotbuf[1] = 0; +} + +static void +Opcode_l16ui_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_l16ui_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x350000; +} + +static void +Opcode_l16ui_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250000; +} + +static void +Opcode_l16ui_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103c0000; +} + +static void +Opcode_l16ui_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c0000; +} + +static void +Opcode_l16ui_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1314000; +} + +static void +Opcode_l16ui_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2390000; +} + +static void +Opcode_l16ui_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c0000; +} + +static void +Opcode_l16ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb01000; +} + +static void +Opcode_l16ui_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c0000; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9002; +} + +static void +Opcode_l16si_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_l16si_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_l16si_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d780000; + slotbuf[1] = 0; +} + +static void +Opcode_l16si_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c02000; + slotbuf[1] = 0; +} + +static void +Opcode_l16si_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10400000; + slotbuf[1] = 0; +} + +static void +Opcode_l16si_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_l16si_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_l16si_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_l16si_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103b0000; +} + +static void +Opcode_l16si_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2680000; +} + +static void +Opcode_l16si_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1310000; +} + +static void +Opcode_l16si_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2380000; +} + +static void +Opcode_l16si_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380000; +} + +static void +Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb00000; +} + +static void +Opcode_l16si_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380000; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2002; +} + +static void +Opcode_l32i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa80000; +} + +static void +Opcode_l32i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1290000; +} + +static void +Opcode_l32i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d790000; + slotbuf[1] = 0; +} + +static void +Opcode_l32i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c03000; + slotbuf[1] = 0; +} + +static void +Opcode_l32i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10420000; + slotbuf[1] = 0; +} + +static void +Opcode_l32i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_l32i_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360000; +} + +static void +Opcode_l32i_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260000; +} + +static void +Opcode_l32i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103d0000; +} + +static void +Opcode_l32i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2681000; +} + +static void +Opcode_l32i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318000; +} + +static void +Opcode_l32i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23a0000; +} + +static void +Opcode_l32i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1390000; +} + +static void +Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7320000; +} + +static void +Opcode_l32i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1390000; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_l32r_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_l32r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7200000; + slotbuf[1] = 0; +} + +static void +Opcode_l32r_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0; +} + +static void +Opcode_l32r_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_l32r_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; +} + +static void +Opcode_l32r_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_l32r_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_l32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000000; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_l8ui_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac0000; +} + +static void +Opcode_l8ui_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12d0000; +} + +static void +Opcode_l8ui_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7d0000; + slotbuf[1] = 0; +} + +static void +Opcode_l8ui_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c03200; + slotbuf[1] = 0; +} + +static void +Opcode_l8ui_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10422000; + slotbuf[1] = 0; +} + +static void +Opcode_l8ui_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_l8ui_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370000; +} + +static void +Opcode_l8ui_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270000; +} + +static void +Opcode_l8ui_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103e0000; +} + +static void +Opcode_l8ui_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c1000; +} + +static void +Opcode_l8ui_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131c000; +} + +static void +Opcode_l8ui_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23b0000; +} + +static void +Opcode_l8ui_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d0000; +} + +static void +Opcode_l8ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7321000; +} + +static void +Opcode_l8ui_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d0000; +} + +static void +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8076; +} + +static void +Opcode_loop_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_loop_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520000; + slotbuf[1] = 0; +} + +static void +Opcode_loop_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10582000; + slotbuf[1] = 0; +} + +static void +Opcode_loop_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0000; +} + +static void +Opcode_loop_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690000; +} + +static void +Opcode_loop_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac1000; +} + +static void +Opcode_loop_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2780000; +} + +static void +Opcode_loop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b20000; +} + +static void +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa076; +} + +static void +Opcode_loopgtz_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20001; +} + +static void +Opcode_loopgtz_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520001; + slotbuf[1] = 0; +} + +static void +Opcode_loopgtz_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10582040; + slotbuf[1] = 0; +} + +static void +Opcode_loopgtz_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0001; +} + +static void +Opcode_loopgtz_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690010; +} + +static void +Opcode_loopgtz_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac1001; +} + +static void +Opcode_loopgtz_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2780001; +} + +static void +Opcode_loopgtz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b20040; +} + +static void +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9076; +} + +static void +Opcode_loopnez_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20002; +} + +static void +Opcode_loopnez_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520002; + slotbuf[1] = 0; +} + +static void +Opcode_loopnez_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10582080; + slotbuf[1] = 0; +} + +static void +Opcode_loopnez_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0002; +} + +static void +Opcode_loopnez_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690020; +} + +static void +Opcode_loopnez_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac1002; +} + +static void +Opcode_loopnez_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2780002; +} + +static void +Opcode_loopnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b20080; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa002; +} + +static void +Opcode_movi_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad0000; +} + +static void +Opcode_movi_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1220000; +} + +static void +Opcode_movi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7f0000; + slotbuf[1] = 0; +} + +static void +Opcode_movi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04000; + slotbuf[1] = 0; +} + +static void +Opcode_movi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480000; + slotbuf[1] = 0; +} + +static void +Opcode_movi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_movi_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0000; +} + +static void +Opcode_movi_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_movi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10450000; +} + +static void +Opcode_movi_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c3000; +} + +static void +Opcode_movi_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1320000; +} + +static void +Opcode_movi_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23f0000; +} + +static void +Opcode_movi_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1320000; +} + +static void +Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9820000; +} + +static void +Opcode_movi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1320000; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830000; +} + +static void +Opcode_moveqz_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4b000; +} + +static void +Opcode_moveqz_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144f000; +} + +static void +Opcode_moveqz_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e3000; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e7a000; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10755000; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae000; +} + +static void +Opcode_moveqz_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3cd000; +} + +static void +Opcode_moveqz_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a5000; +} + +static void +Opcode_moveqz_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063d000; +} + +static void +Opcode_moveqz_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a2d000; +} + +static void +Opcode_moveqz_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154b000; +} + +static void +Opcode_moveqz_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2759000; +} + +static void +Opcode_moveqz_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1551000; +} + +static void +Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9978008; +} + +static void +Opcode_moveqz_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f000; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30000; +} + +static void +Opcode_movgez_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8a000; +} + +static void +Opcode_movgez_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148e000; +} + +static void +Opcode_movgez_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e4000; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e82000; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10757000; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1af000; +} + +static void +Opcode_movgez_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ce000; +} + +static void +Opcode_movgez_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a6000; +} + +static void +Opcode_movgez_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063e000; +} + +static void +Opcode_movgez_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a31000; +} + +static void +Opcode_movgez_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158b000; +} + +static void +Opcode_movgez_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275a000; +} + +static void +Opcode_movgez_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1590000; +} + +static void +Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x997000c; +} + +static void +Opcode_movgez_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158e000; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_movltz_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8b000; +} + +static void +Opcode_movltz_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148f000; +} + +static void +Opcode_movltz_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e5000; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e8a000; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10759000; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_movltz_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3cf000; +} + +static void +Opcode_movltz_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a7000; +} + +static void +Opcode_movltz_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063f000; +} + +static void +Opcode_movltz_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a35000; +} + +static void +Opcode_movltz_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cb000; +} + +static void +Opcode_movltz_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275b000; +} + +static void +Opcode_movltz_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1591000; +} + +static void +Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x997800c; +} + +static void +Opcode_movltz_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158f000; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_movnez_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcca000; +} + +static void +Opcode_movnez_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14ce000; +} + +static void +Opcode_movnez_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e6000; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e92000; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1075b000; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1000; +} + +static void +Opcode_movnez_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d0000; +} + +static void +Opcode_movnez_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8000; +} + +static void +Opcode_movnez_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10641000; +} + +static void +Opcode_movnez_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a39000; +} + +static void +Opcode_movnez_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150c000; +} + +static void +Opcode_movnez_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275c000; +} + +static void +Opcode_movnez_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d0000; +} + +static void +Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a71008; +} + +static void +Opcode_movnez_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ce000; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600100; +} + +static void +Opcode_abs_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc12020; +} + +static void +Opcode_abs_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1453000; +} + +static void +Opcode_abs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191f6030; + slotbuf[1] = 0; +} + +static void +Opcode_abs_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e14000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a00e; + slotbuf[1] = 0; +} + +static void +Opcode_abs_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8000; +} + +static void +Opcode_abs_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e5000; +} + +static void +Opcode_abs_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6000; +} + +static void +Opcode_abs_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a200b; +} + +static void +Opcode_abs_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a89000; +} + +static void +Opcode_abs_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f000; +} + +static void +Opcode_abs_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c6010; +} + +static void +Opcode_abs_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1555000; +} + +static void +Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a3000; +} + +static void +Opcode_abs_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1521000; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_neg_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc12030; +} + +static void +Opcode_neg_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1453010; +} + +static void +Opcode_neg_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191f7030; + slotbuf[1] = 0; +} + +static void +Opcode_neg_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e14010; + slotbuf[1] = 0; +} + +static void +Opcode_neg_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071b00f; + slotbuf[1] = 0; +} + +static void +Opcode_neg_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8020; +} + +static void +Opcode_neg_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e5020; +} + +static void +Opcode_neg_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6010; +} + +static void +Opcode_neg_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a300b; +} + +static void +Opcode_neg_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a89010; +} + +static void +Opcode_neg_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f010; +} + +static void +Opcode_neg_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c7010; +} + +static void +Opcode_neg_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1555010; +} + +static void +Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a3002; +} + +static void +Opcode_neg_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1521020; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f0; +} + +static void +Opcode_nop_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21903; +} + +static void +Opcode_nop_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1496109; +} + +static void +Opcode_nop_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000065; + slotbuf[1] = 0x6; +} + +static void +Opcode_nop_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82164012; + slotbuf[1] = 0x5; +} + +static void +Opcode_nop_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b48fb5; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c702; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63f8c00; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef74; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9603; +} + +static void +Opcode_nop_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e640b; +} + +static void +Opcode_nop_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7306; +} + +static void +Opcode_nop_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x568001; +} + +static void +Opcode_nop_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40b84a0; +} + +static void +Opcode_nop_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x510040; +} + +static void +Opcode_nop_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069db31; +} + +static void +Opcode_nop_Slot_ae5_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_nop_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700212; +} + +static void +Opcode_nop_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133b800; +} + +static void +Opcode_nop_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08940; +} + +static void +Opcode_nop_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130060; +} + +static void +Opcode_nop_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000021; + slotbuf[1] = 0x2; +} + +static void +Opcode_nop_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x692180; +} + +static void +Opcode_nop_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x692180; +} + +static void +Opcode_nop_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00560; + slotbuf[1] = 0xe; +} + +static void +Opcode_nop_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000801; + slotbuf[1] = 0xe; +} + +static void +Opcode_nop_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d901; +} + +static void +Opcode_nop_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d260f; +} + +static void +Opcode_nop_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200001; + slotbuf[1] = 0x229860; +} + +static void +Opcode_nop_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781903; +} + +static void +Opcode_nop_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159690b; +} + +static void +Opcode_nop_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c10041; + slotbuf[1] = 0; +} + +static void +Opcode_nop_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d35801d; +} + +static void +Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab20055; +} + +static void +Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14b610c; +} + +static void +Opcode_nop_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00427; +} + +static void +Opcode_nop_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80426862; + slotbuf[1] = 0xe; +} + +static void +Opcode_l32ex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf14000; +} + +static void +Opcode_s32ex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf15000; +} + +static void +Opcode_getex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40a000; +} + +static void +Opcode_clrex_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3120; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_ret_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21303; +} + +static void +Opcode_ret_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520e05; + slotbuf[1] = 0; +} + +static void +Opcode_ret_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef10; + slotbuf[1] = 0; +} + +static void +Opcode_ret_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6405; +} + +static void +Opcode_ret_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d530; +} + +static void +Opcode_ret_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d301; +} + +static void +Opcode_ret_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781303; +} + +static void +Opcode_ret_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e13e0; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5002; +} + +static void +Opcode_s16i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_s16i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7a0000; + slotbuf[1] = 0; +} + +static void +Opcode_s16i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10440000; + slotbuf[1] = 0; +} + +static void +Opcode_s16i_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_s16i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103f0000; +} + +static void +Opcode_s16i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2682000; +} + +static void +Opcode_s16i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23c0000; +} + +static void +Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7330000; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002; +} + +static void +Opcode_s32i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa50000; +} + +static void +Opcode_s32i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7e0000; + slotbuf[1] = 0; +} + +static void +Opcode_s32i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10442000; + slotbuf[1] = 0; +} + +static void +Opcode_s32i_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x390000; +} + +static void +Opcode_s32i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10400000; +} + +static void +Opcode_s32i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c2000; +} + +static void +Opcode_s32i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23d0000; +} + +static void +Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7331000; +} + +static void +Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590000; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_s8i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa90000; +} + +static void +Opcode_s8i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7b0000; + slotbuf[1] = 0; +} + +static void +Opcode_s8i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10460000; + slotbuf[1] = 0; +} + +static void +Opcode_s8i_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0000; +} + +static void +Opcode_s8i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10410000; +} + +static void +Opcode_s8i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2683000; +} + +static void +Opcode_s8i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23e0000; +} + +static void +Opcode_s8i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa980000; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403000; +} + +static void +Opcode_ssa8b_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21503; +} + +static void +Opcode_ssa8b_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145420a; +} + +static void +Opcode_ssa8b_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7521605; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8b_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00c03; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8b_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef30; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8b_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9103; +} + +static void +Opcode_ssa8b_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6407; +} + +static void +Opcode_ssa8b_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7302; +} + +static void +Opcode_ssa8b_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d730; +} + +static void +Opcode_ssa8b_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d501; +} + +static void +Opcode_ssa8b_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d220f; +} + +static void +Opcode_ssa8b_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781503; +} + +static void +Opcode_ssa8b_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556a0b; +} + +static void +Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e15e0; +} + +static void +Opcode_ssa8b_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d7204; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402000; +} + +static void +Opcode_ssa8l_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21603; +} + +static void +Opcode_ssa8l_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145430a; +} + +static void +Opcode_ssa8l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7521a05; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f08c03; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef40; + slotbuf[1] = 0; +} + +static void +Opcode_ssa8l_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9503; +} + +static void +Opcode_ssa8l_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6408; +} + +static void +Opcode_ssa8l_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7303; +} + +static void +Opcode_ssa8l_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d830; +} + +static void +Opcode_ssa8l_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d601; +} + +static void +Opcode_ssa8l_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d230f; +} + +static void +Opcode_ssa8l_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781603; +} + +static void +Opcode_ssa8l_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556b0b; +} + +static void +Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e16e0; +} + +static void +Opcode_ssa8l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d7304; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401000; +} + +static void +Opcode_ssl_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21703; +} + +static void +Opcode_ssl_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416109; +} + +static void +Opcode_ssl_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7521e05; + slotbuf[1] = 0; +} + +static void +Opcode_ssl_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c402; + slotbuf[1] = 0; +} + +static void +Opcode_ssl_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef50; + slotbuf[1] = 0; +} + +static void +Opcode_ssl_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9203; +} + +static void +Opcode_ssl_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6409; +} + +static void +Opcode_ssl_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7304; +} + +static void +Opcode_ssl_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d930; +} + +static void +Opcode_ssl_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d701; +} + +static void +Opcode_ssl_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d240f; +} + +static void +Opcode_ssl_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781703; +} + +static void +Opcode_ssl_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151690b; +} + +static void +Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e17e0; +} + +static void +Opcode_ssl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143610c; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ssr_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc21803; +} + +static void +Opcode_ssr_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1456109; +} + +static void +Opcode_ssr_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a4af00; + slotbuf[1] = 0; +} + +static void +Opcode_ssr_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c502; + slotbuf[1] = 0; +} + +static void +Opcode_ssr_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef60; + slotbuf[1] = 0; +} + +static void +Opcode_ssr_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9303; +} + +static void +Opcode_ssr_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e640a; +} + +static void +Opcode_ssr_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7305; +} + +static void +Opcode_ssr_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069da30; +} + +static void +Opcode_ssr_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d801; +} + +static void +Opcode_ssr_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d250f; +} + +static void +Opcode_ssr_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2781803; +} + +static void +Opcode_ssr_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x155690b; +} + +static void +Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e18e0; +} + +static void +Opcode_ssr_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x147610c; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404000; +} + +static void +Opcode_ssai_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc92520; +} + +static void +Opcode_ssai_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145400a; +} + +static void +Opcode_ssai_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19034310; + slotbuf[1] = 0; +} + +static void +Opcode_ssai_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00c01; + slotbuf[1] = 0; +} + +static void +Opcode_ssai_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afa0a; + slotbuf[1] = 0; +} + +static void +Opcode_ssai_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9003; +} + +static void +Opcode_ssai_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6400; +} + +static void +Opcode_ssai_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7300; +} + +static void +Opcode_ssai_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687701; +} + +static void +Opcode_ssai_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a88640; +} + +static void +Opcode_ssai_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d200f; +} + +static void +Opcode_ssai_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b520; +} + +static void +Opcode_ssai_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516a0b; +} + +static void +Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa60005; +} + +static void +Opcode_ssai_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d7004; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_sll_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20003; +} + +static void +Opcode_sll_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x141400a; +} + +static void +Opcode_sll_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x752c003; + slotbuf[1] = 0; +} + +static void +Opcode_sll_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0c002; + slotbuf[1] = 0; +} + +static void +Opcode_sll_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105860c0; + slotbuf[1] = 0; +} + +static void +Opcode_sll_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9000; +} + +static void +Opcode_sll_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0003; +} + +static void +Opcode_sll_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b8000; +} + +static void +Opcode_sll_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069c030; +} + +static void +Opcode_sll_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a8d000; +} + +static void +Opcode_sll_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159200f; +} + +static void +Opcode_sll_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2780003; +} + +static void +Opcode_sll_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151600a; +} + +static void +Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e10e0; +} + +static void +Opcode_sll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1596004; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_src_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4c000; +} + +static void +Opcode_src_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1450000; +} + +static void +Opcode_src_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ea000; + slotbuf[1] = 0; +} + +static void +Opcode_src_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eb2000; + slotbuf[1] = 0; +} + +static void +Opcode_src_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10729000; + slotbuf[1] = 0; +} + +static void +Opcode_src_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b5000; +} + +static void +Opcode_src_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d4000; +} + +static void +Opcode_src_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac000; +} + +static void +Opcode_src_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10649000; +} + +static void +Opcode_src_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a49000; +} + +static void +Opcode_src_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150d000; +} + +static void +Opcode_src_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2760000; +} + +static void +Opcode_src_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1552000; +} + +static void +Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a7100c; +} + +static void +Opcode_src_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1550000; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10000; +} + +static void +Opcode_sra_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc52020; +} + +static void +Opcode_sra_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1453020; +} + +static void +Opcode_sra_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191fc030; + slotbuf[1] = 0; +} + +static void +Opcode_sra_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e14020; + slotbuf[1] = 0; +} + +static void +Opcode_sra_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af000; + slotbuf[1] = 0; +} + +static void +Opcode_sra_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8030; +} + +static void +Opcode_sra_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e5010; +} + +static void +Opcode_sra_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6020; +} + +static void +Opcode_sra_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2007; +} + +static void +Opcode_sra_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a89020; +} + +static void +Opcode_sra_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f020; +} + +static void +Opcode_sra_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b000; +} + +static void +Opcode_sra_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1555020; +} + +static void +Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a3003; +} + +static void +Opcode_sra_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1521030; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_srl_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc52030; +} + +static void +Opcode_srl_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1453030; +} + +static void +Opcode_srl_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191fe030; + slotbuf[1] = 0; +} + +static void +Opcode_srl_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e14030; + slotbuf[1] = 0; +} + +static void +Opcode_srl_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af001; + slotbuf[1] = 0; +} + +static void +Opcode_srl_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8040; +} + +static void +Opcode_srl_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e5030; +} + +static void +Opcode_srl_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b6030; +} + +static void +Opcode_srl_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a200f; +} + +static void +Opcode_srl_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a89030; +} + +static void +Opcode_srl_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154f030; +} + +static void +Opcode_srl_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b010; +} + +static void +Opcode_srl_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1555030; +} + +static void +Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a3000; +} + +static void +Opcode_srl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1521040; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_slli_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc6000; +} + +static void +Opcode_slli_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14ca000; +} + +static void +Opcode_slli_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74b6000; + slotbuf[1] = 0; +} + +static void +Opcode_slli_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e22000; + slotbuf[1] = 0; +} + +static void +Opcode_slli_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10542000; + slotbuf[1] = 0; +} + +static void +Opcode_slli_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_slli_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_slli_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290000; +} + +static void +Opcode_slli_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10610000; +} + +static void +Opcode_slli_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a01000; +} + +static void +Opcode_slli_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1508000; +} + +static void +Opcode_slli_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x274c000; +} + +static void +Opcode_slli_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cc000; +} + +static void +Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9920000; +} + +static void +Opcode_slli_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ca000; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_srai_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc08000; +} + +static void +Opcode_srai_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140c000; +} + +static void +Opcode_srai_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74b8000; + slotbuf[1] = 0; +} + +static void +Opcode_srai_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e02000; + slotbuf[1] = 0; +} + +static void +Opcode_srai_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10546000; + slotbuf[1] = 0; +} + +static void +Opcode_srai_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2000; +} + +static void +Opcode_srai_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c2000; +} + +static void +Opcode_srai_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x292000; +} + +static void +Opcode_srai_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10612000; +} + +static void +Opcode_srai_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000e0; +} + +static void +Opcode_srai_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1548000; +} + +static void +Opcode_srai_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x274e000; +} + +static void +Opcode_srai_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150e000; +} + +static void +Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9970004; +} + +static void +Opcode_srai_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150c000; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_srli_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8e000; +} + +static void +Opcode_srli_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1452000; +} + +static void +Opcode_srli_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f4000; + slotbuf[1] = 0; +} + +static void +Opcode_srli_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ef2000; + slotbuf[1] = 0; +} + +static void +Opcode_srli_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056a000; + slotbuf[1] = 0; +} + +static void +Opcode_srli_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bd000; +} + +static void +Opcode_srli_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3de000; +} + +static void +Opcode_srli_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b4000; +} + +static void +Opcode_srli_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065d000; +} + +static void +Opcode_srli_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a71000; +} + +static void +Opcode_srli_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150f000; +} + +static void +Opcode_srli_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276a000; +} + +static void +Opcode_srli_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1554000; +} + +static void +Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x992800c; +} + +static void +Opcode_srli_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1552000; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d0; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2030; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2020; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2010; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30100; +} + +static void +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610100; +} + +static void +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200; +} + +static void +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610200; +} + +static void +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30300; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610300; +} + +static void +Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36100; +} + +static void +Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136100; +} + +static void +Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616100; +} + +static void +Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b000; +} + +static void +Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e600; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e600; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e600; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b100; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b100; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b100; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d100; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d100; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d100; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b200; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b200; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b200; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d200; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d200; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d200; +} + +static void +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b300; +} + +static void +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b300; +} + +static void +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b300; +} + +static void +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d300; +} + +static void +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d300; +} + +static void +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d300; +} + +static void +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b400; +} + +static void +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b400; +} + +static void +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b400; +} + +static void +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d400; +} + +static void +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d400; +} + +static void +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d400; +} + +static void +Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b500; +} + +static void +Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b500; +} + +static void +Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b500; +} + +static void +Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d500; +} + +static void +Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d500; +} + +static void +Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d500; +} + +static void +Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b600; +} + +static void +Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b600; +} + +static void +Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b600; +} + +static void +Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d600; +} + +static void +Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d600; +} + +static void +Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d600; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c200; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c200; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c200; +} + +static void +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c300; +} + +static void +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c300; +} + +static void +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c300; +} + +static void +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400; +} + +static void +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c400; +} + +static void +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c400; +} + +static void +Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c500; +} + +static void +Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c500; +} + +static void +Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c500; +} + +static void +Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c600; +} + +static void +Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c600; +} + +static void +Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c600; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ee00; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee00; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ee00; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c000; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e800; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e800; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e800; +} + +static void +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f400; +} + +static void +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f400; +} + +static void +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f400; +} + +static void +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f500; +} + +static void +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f500; +} + +static void +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f500; +} + +static void +Opcode_rsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f600; +} + +static void +Opcode_wsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f600; +} + +static void +Opcode_xsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f600; +} + +static void +Opcode_rsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f700; +} + +static void +Opcode_wsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f700; +} + +static void +Opcode_xsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f700; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3eb00; +} + +static void +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e700; +} + +static void +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e700; +} + +static void +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e700; +} + +static void +Opcode_rsr_mpucfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35c00; +} + +static void +Opcode_wsr_mpucfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135c00; +} + +static void +Opcode_salt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720000; +} + +static void +Opcode_salt_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c000; +} + +static void +Opcode_salt_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1410000; +} + +static void +Opcode_salt_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e8000; + slotbuf[1] = 0; +} + +static void +Opcode_salt_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea2000; + slotbuf[1] = 0; +} + +static void +Opcode_salt_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1075f000; + slotbuf[1] = 0; +} + +static void +Opcode_salt_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b3000; +} + +static void +Opcode_salt_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d2000; +} + +static void +Opcode_salt_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2aa000; +} + +static void +Opcode_salt_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10645000; +} + +static void +Opcode_salt_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a41000; +} + +static void +Opcode_salt_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158c000; +} + +static void +Opcode_salt_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275e000; +} + +static void +Opcode_salt_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512000; +} + +static void +Opcode_salt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b71008; +} + +static void +Opcode_salt_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510000; +} + +static void +Opcode_saltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x620000; +} + +static void +Opcode_saltu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0d000; +} + +static void +Opcode_saltu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1411000; +} + +static void +Opcode_saltu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e9000; + slotbuf[1] = 0; +} + +static void +Opcode_saltu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eaa000; + slotbuf[1] = 0; +} + +static void +Opcode_saltu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10728000; + slotbuf[1] = 0; +} + +static void +Opcode_saltu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b4000; +} + +static void +Opcode_saltu_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d3000; +} + +static void +Opcode_saltu_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ab000; +} + +static void +Opcode_saltu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10647000; +} + +static void +Opcode_saltu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a45000; +} + +static void +Opcode_saltu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cc000; +} + +static void +Opcode_saltu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275f000; +} + +static void +Opcode_saltu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1513000; +} + +static void +Opcode_saltu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b79008; +} + +static void +Opcode_saltu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1511000; +} + +static void +Opcode_rsr_opmode_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37700; +} + +static void +Opcode_wsr_opmode_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137700; +} + +static void +Opcode_xsr_opmode_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x617700; +} + +static void +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820000; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3010; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e200; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e200; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e300; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e400; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e400; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf02d; +} + +static void +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139000; +} + +static void +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619000; +} + +static void +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a000; +} + +static void +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a000; +} + +static void +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39100; +} + +static void +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139100; +} + +static void +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619100; +} + +static void +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a100; +} + +static void +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a100; +} + +static void +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a100; +} + +static void +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618000; +} + +static void +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38100; +} + +static void +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138100; +} + +static void +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618100; +} + +static void +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000; +} + +static void +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136000; +} + +static void +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616000; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e900; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e900; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e900; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ec00; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec00; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ec00; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ed00; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ed00; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ed00; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36800; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136800; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616800; +} + +static void +Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e0; +} + +static void +Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f0; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e000; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e010; +} + +static void +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135900; +} + +static void +Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_andb_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8f000; +} + +static void +Opcode_andb_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f5000; + slotbuf[1] = 0; +} + +static void +Opcode_andb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056b000; + slotbuf[1] = 0; +} + +static void +Opcode_andb_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3df000; +} + +static void +Opcode_andb_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10661000; +} + +static void +Opcode_andb_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a75000; +} + +static void +Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996800c; +} + +static void +Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_andbc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcce000; +} + +static void +Opcode_andbc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f6000; + slotbuf[1] = 0; +} + +static void +Opcode_andbc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056e000; + slotbuf[1] = 0; +} + +static void +Opcode_andbc_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0000; +} + +static void +Opcode_andbc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10663000; +} + +static void +Opcode_andbc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a79000; +} + +static void +Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9921000; +} + +static void +Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_orb_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xccf000; +} + +static void +Opcode_orb_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f7000; + slotbuf[1] = 0; +} + +static void +Opcode_orb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056f000; + slotbuf[1] = 0; +} + +static void +Opcode_orb_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e1000; +} + +static void +Opcode_orb_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10665000; +} + +static void +Opcode_orb_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a7d000; +} + +static void +Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9961000; +} + +static void +Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000; +} + +static void +Opcode_orbc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_orbc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f8000; + slotbuf[1] = 0; +} + +static void +Opcode_orbc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10572000; + slotbuf[1] = 0; +} + +static void +Opcode_orbc_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e2000; +} + +static void +Opcode_orbc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10667000; +} + +static void +Opcode_orbc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a81000; +} + +static void +Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929000; +} + +static void +Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420000; +} + +static void +Opcode_xorb_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc11000; +} + +static void +Opcode_xorb_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f9000; + slotbuf[1] = 0; +} + +static void +Opcode_xorb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10573000; + slotbuf[1] = 0; +} + +static void +Opcode_xorb_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e3000; +} + +static void +Opcode_xorb_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10669000; +} + +static void +Opcode_xorb_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a85000; +} + +static void +Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9969000; +} + +static void +Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_all4_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc92020; +} + +static void +Opcode_all4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19034010; + slotbuf[1] = 0; +} + +static void +Opcode_all4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af00a; + slotbuf[1] = 0; +} + +static void +Opcode_all4_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6300; +} + +static void +Opcode_all4_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687602; +} + +static void +Opcode_all4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80640; +} + +static void +Opcode_all4_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b020; +} + +static void +Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a7400; +} + +static void +Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_any4_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc92030; +} + +static void +Opcode_any4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19036010; + slotbuf[1] = 0; +} + +static void +Opcode_any4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af00b; + slotbuf[1] = 0; +} + +static void +Opcode_any4_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6340; +} + +static void +Opcode_any4_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687603; +} + +static void +Opcode_any4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80650; +} + +static void +Opcode_any4_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b030; +} + +static void +Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a7401; +} + +static void +Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000; +} + +static void +Opcode_all8_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc92420; +} + +static void +Opcode_all8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19034210; + slotbuf[1] = 0; +} + +static void +Opcode_all8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af80a; + slotbuf[1] = 0; +} + +static void +Opcode_all8_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6380; +} + +static void +Opcode_all8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687700; +} + +static void +Opcode_all8_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80660; +} + +static void +Opcode_all8_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b420; +} + +static void +Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a7402; +} + +static void +Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_any8_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc92430; +} + +static void +Opcode_any8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19036210; + slotbuf[1] = 0; +} + +static void +Opcode_any8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af80b; + slotbuf[1] = 0; +} + +static void +Opcode_any8_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6390; +} + +static void +Opcode_any8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687704; +} + +static void +Opcode_any8_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80670; +} + +static void +Opcode_any8_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276b430; +} + +static void +Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a7403; +} + +static void +Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76; +} + +static void +Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1076; +} + +static void +Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc30000; +} + +static void +Opcode_movf_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0e000; +} + +static void +Opcode_movf_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f0000; + slotbuf[1] = 0; +} + +static void +Opcode_movf_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055f000; + slotbuf[1] = 0; +} + +static void +Opcode_movf_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3da000; +} + +static void +Opcode_movf_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10655000; +} + +static void +Opcode_movf_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a61000; +} + +static void +Opcode_movf_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2766000; +} + +static void +Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9928008; +} + +static void +Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30000; +} + +static void +Opcode_movt_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0f000; +} + +static void +Opcode_movt_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f1000; + slotbuf[1] = 0; +} + +static void +Opcode_movt_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10562000; + slotbuf[1] = 0; +} + +static void +Opcode_movt_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3db000; +} + +static void +Opcode_movt_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10657000; +} + +static void +Opcode_movt_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a65000; +} + +static void +Opcode_movt_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2767000; +} + +static void +Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9968008; +} + +static void +Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30400; +} + +static void +Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130400; +} + +static void +Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610400; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ea00; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea00; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ea00; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f000; +} + +static void +Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f100; +} + +static void +Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f100; +} + +static void +Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f100; +} + +static void +Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f200; +} + +static void +Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f200; +} + +static void +Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f200; +} + +static void +Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e2; +} + +static void +Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70c2; +} + +static void +Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270d2; +} + +static void +Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370d2; +} + +static void +Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70d2; +} + +static void +Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f2; +} + +static void +Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10000; +} + +static void +Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf12000; +} + +static void +Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf11000; +} + +static void +Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13000; +} + +static void +Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7042; +} + +static void +Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7052; +} + +static void +Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf7082; +} + +static void +Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x47082; +} + +static void +Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57082; +} + +static void +Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7062; +} + +static void +Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7072; +} + +static void +Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7002; +} + +static void +Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7022; +} + +static void +Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7012; +} + +static void +Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7032; +} + +static void +Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27082; +} + +static void +Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37082; +} + +static void +Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7082; +} + +static void +Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf19000; +} + +static void +Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf18000; +} + +static void +Opcode_sdcw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1b000; +} + +static void +Opcode_ldcw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1a000; +} + +static void +Opcode_rsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32800; +} + +static void +Opcode_wsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132800; +} + +static void +Opcode_xsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612800; +} + +static void +Opcode_wsr_cacheadrdis_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136200; +} + +static void +Opcode_rsr_cacheadrdis_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36200; +} + +static void +Opcode_xsr_cacheadrdis_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616200; +} + +static void +Opcode_rptlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50b000; +} + +static void +Opcode_pptlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50d000; +} + +static void +Opcode_rptlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50f000; +} + +static void +Opcode_wptlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50e000; +} + +static void +Opcode_rsr_mpuenb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35a00; +} + +static void +Opcode_wsr_mpuenb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135a00; +} + +static void +Opcode_xsr_mpuenb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615a00; +} + +static void +Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e000; +} + +static void +Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e000; +} + +static void +Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000; +} + +static void +Opcode_clamps_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4e000; +} + +static void +Opcode_clamps_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1412000; +} + +static void +Opcode_clamps_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f2000; + slotbuf[1] = 0; +} + +static void +Opcode_clamps_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee2000; + slotbuf[1] = 0; +} + +static void +Opcode_clamps_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10566000; + slotbuf[1] = 0; +} + +static void +Opcode_clamps_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb000; +} + +static void +Opcode_clamps_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3dc000; +} + +static void +Opcode_clamps_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b2000; +} + +static void +Opcode_clamps_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10659000; +} + +static void +Opcode_clamps_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a69000; +} + +static void +Opcode_clamps_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158e000; +} + +static void +Opcode_clamps_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2768000; +} + +static void +Opcode_clamps_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514000; +} + +static void +Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x992000c; +} + +static void +Opcode_clamps_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512000; +} + +static void +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_max_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc9000; +} + +static void +Opcode_max_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14cd000; +} + +static void +Opcode_max_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74bf000; + slotbuf[1] = 0; +} + +static void +Opcode_max_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e5a000; + slotbuf[1] = 0; +} + +static void +Opcode_max_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054e000; + slotbuf[1] = 0; +} + +static void +Opcode_max_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa000; +} + +static void +Opcode_max_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c9000; +} + +static void +Opcode_max_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a1000; +} + +static void +Opcode_max_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10639000; +} + +static void +Opcode_max_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a1d000; +} + +static void +Opcode_max_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154a000; +} + +static void +Opcode_max_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2755000; +} + +static void +Opcode_max_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cf000; +} + +static void +Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9960004; +} + +static void +Opcode_max_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cd000; +} + +static void +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_maxu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a000; +} + +static void +Opcode_maxu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140e000; +} + +static void +Opcode_maxu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e0000; + slotbuf[1] = 0; +} + +static void +Opcode_maxu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e62000; + slotbuf[1] = 0; +} + +static void +Opcode_maxu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054f000; + slotbuf[1] = 0; +} + +static void +Opcode_maxu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab000; +} + +static void +Opcode_maxu_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ca000; +} + +static void +Opcode_maxu_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a2000; +} + +static void +Opcode_maxu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063a000; +} + +static void +Opcode_maxu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a21000; +} + +static void +Opcode_maxu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158a000; +} + +static void +Opcode_maxu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2756000; +} + +static void +Opcode_maxu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510000; +} + +static void +Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9928004; +} + +static void +Opcode_maxu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150e000; +} + +static void +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_min_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0b000; +} + +static void +Opcode_min_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140f000; +} + +static void +Opcode_min_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e1000; + slotbuf[1] = 0; +} + +static void +Opcode_min_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6a000; + slotbuf[1] = 0; +} + +static void +Opcode_min_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10751000; + slotbuf[1] = 0; +} + +static void +Opcode_min_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac000; +} + +static void +Opcode_min_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3cb000; +} + +static void +Opcode_min_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a3000; +} + +static void +Opcode_min_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063b000; +} + +static void +Opcode_min_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a25000; +} + +static void +Opcode_min_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ca000; +} + +static void +Opcode_min_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2757000; +} + +static void +Opcode_min_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1511000; +} + +static void +Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9968004; +} + +static void +Opcode_min_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150f000; +} + +static void +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_minu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4a000; +} + +static void +Opcode_minu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144e000; +} + +static void +Opcode_minu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74e2000; + slotbuf[1] = 0; +} + +static void +Opcode_minu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e72000; + slotbuf[1] = 0; +} + +static void +Opcode_minu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10753000; + slotbuf[1] = 0; +} + +static void +Opcode_minu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ad000; +} + +static void +Opcode_minu_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3cc000; +} + +static void +Opcode_minu_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a4000; +} + +static void +Opcode_minu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063c000; +} + +static void +Opcode_minu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a29000; +} + +static void +Opcode_minu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150b000; +} + +static void +Opcode_minu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2758000; +} + +static void +Opcode_minu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1550000; +} + +static void +Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9970008; +} + +static void +Opcode_minu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154e000; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40e000; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40f000; +} + +static void +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_sext_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4f000; +} + +static void +Opcode_sext_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1413000; +} + +static void +Opcode_sext_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74f3000; + slotbuf[1] = 0; +} + +static void +Opcode_sext_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eea000; + slotbuf[1] = 0; +} + +static void +Opcode_sext_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10567000; + slotbuf[1] = 0; +} + +static void +Opcode_sext_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc000; +} + +static void +Opcode_sext_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3dd000; +} + +static void +Opcode_sext_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b3000; +} + +static void +Opcode_sext_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065b000; +} + +static void +Opcode_sext_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a6d000; +} + +static void +Opcode_sext_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ce000; +} + +static void +Opcode_sext_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2769000; +} + +static void +Opcode_sext_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1515000; +} + +static void +Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996000c; +} + +static void +Opcode_sext_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1513000; +} + +static void +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb002; +} + +static void +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002; +} + +static void +Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36300; +} + +static void +Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136300; +} + +static void +Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616300; +} + +static void +Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20000; +} + +static void +Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf20000; +} + +static void +Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe20000; +} + +static void +Opcode_rsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35f00; +} + +static void +Opcode_wsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135f00; +} + +static void +Opcode_xsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615f00; +} + +static void +Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x406000; +} + +static void +Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x407000; +} + +static void +Opcode_beqz_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000a; + slotbuf[1] = 0; +} + +static void +Opcode_beqz_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000a0; + slotbuf[1] = 0; +} + +static void +Opcode_beqz_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c0; +} + +static void +Opcode_bgez_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000e; + slotbuf[1] = 0; +} + +static void +Opcode_bgez_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000e0; + slotbuf[1] = 0; +} + +static void +Opcode_bgez_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000e0; +} + +static void +Opcode_bltz_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000040a; + slotbuf[1] = 0; +} + +static void +Opcode_bltz_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004a0; + slotbuf[1] = 0; +} + +static void +Opcode_bltz_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001c0; +} + +static void +Opcode_bnez_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000040e; + slotbuf[1] = 0; +} + +static void +Opcode_bnez_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004e0; + slotbuf[1] = 0; +} + +static void +Opcode_bnez_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001e0; +} + +static void +Opcode_beqi_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0; +} + +static void +Opcode_beqi_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0; +} + +static void +Opcode_beqi_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; +} + +static void +Opcode_bgei_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000004; + slotbuf[1] = 0; +} + +static void +Opcode_bgei_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000040; + slotbuf[1] = 0; +} + +static void +Opcode_bgei_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; +} + +static void +Opcode_blti_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000c; + slotbuf[1] = 0; +} + +static void +Opcode_blti_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c0; + slotbuf[1] = 0; +} + +static void +Opcode_blti_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000060; +} + +static void +Opcode_bnei_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000006; + slotbuf[1] = 0; +} + +static void +Opcode_bnei_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000060; + slotbuf[1] = 0; +} + +static void +Opcode_bnei_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000a0; +} + +static void +Opcode_bgeui_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000008; + slotbuf[1] = 0; +} + +static void +Opcode_bgeui_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000080; + slotbuf[1] = 0; +} + +static void +Opcode_bgeui_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000040; +} + +static void +Opcode_bltui_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000002; + slotbuf[1] = 0; +} + +static void +Opcode_bltui_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; + slotbuf[1] = 0; +} + +static void +Opcode_bltui_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000080; +} + +static void +Opcode_bbci_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0; +} + +static void +Opcode_bbci_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_bbci_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_bbsi_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000400; + slotbuf[1] = 0; +} + +static void +Opcode_bbsi_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; + slotbuf[1] = 0; +} + +static void +Opcode_bbsi_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; +} + +static void +Opcode_ball_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000800; + slotbuf[1] = 0; +} + +static void +Opcode_ball_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; + slotbuf[1] = 0; +} + +static void +Opcode_ball_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; +} + +static void +Opcode_bany_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000c00; + slotbuf[1] = 0; +} + +static void +Opcode_bany_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600; + slotbuf[1] = 0; +} + +static void +Opcode_bany_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500; +} + +static void +Opcode_bbc_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000900; + slotbuf[1] = 0; +} + +static void +Opcode_bbc_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00; + slotbuf[1] = 0; +} + +static void +Opcode_bbc_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600; +} + +static void +Opcode_bbs_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000d00; + slotbuf[1] = 0; +} + +static void +Opcode_bbs_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00; + slotbuf[1] = 0; +} + +static void +Opcode_bbs_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700; +} + +static void +Opcode_beq_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000200; + slotbuf[1] = 0; +} + +static void +Opcode_beq_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100; + slotbuf[1] = 0; +} + +static void +Opcode_beq_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; +} + +static void +Opcode_bgeu_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000600; + slotbuf[1] = 0; +} + +static void +Opcode_bgeu_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500; + slotbuf[1] = 0; +} + +static void +Opcode_bgeu_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900; +} + +static void +Opcode_bge_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000a00; + slotbuf[1] = 0; +} + +static void +Opcode_bge_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900; + slotbuf[1] = 0; +} + +static void +Opcode_bge_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00; +} + +static void +Opcode_bltu_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000e00; + slotbuf[1] = 0; +} + +static void +Opcode_bltu_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00; + slotbuf[1] = 0; +} + +static void +Opcode_bltu_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00; +} + +static void +Opcode_blt_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000300; + slotbuf[1] = 0; +} + +static void +Opcode_blt_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300; + slotbuf[1] = 0; +} + +static void +Opcode_blt_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00; +} + +static void +Opcode_bnall_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000700; + slotbuf[1] = 0; +} + +static void +Opcode_bnall_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700; + slotbuf[1] = 0; +} + +static void +Opcode_bnall_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00; +} + +static void +Opcode_bne_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000b00; + slotbuf[1] = 0; +} + +static void +Opcode_bne_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00; + slotbuf[1] = 0; +} + +static void +Opcode_bne_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00; +} + +static void +Opcode_bnone_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000f00; + slotbuf[1] = 0; +} + +static void +Opcode_bnone_w15_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00; + slotbuf[1] = 0; +} + +static void +Opcode_bnone_w15_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00; +} + +static void +Opcode_ae_sext16_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800d; +} + +static void +Opcode_ae_zext16_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900d; +} + +static void +Opcode_ae_zext8_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00d; +} + +static void +Opcode_ae_clamps16_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00d; +} + +static void +Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e80; +} + +static void +Opcode_rur_fcr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a7030; +} + +static void +Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e800; +} + +static void +Opcode_wur_fcr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa64005; +} + +static void +Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e90; +} + +static void +Opcode_rur_fsr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a7070; +} + +static void +Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e900; +} + +static void +Opcode_wur_fsr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa66005; +} + +static void +Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1200; +} + +static void +Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static void +Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f00; +} + +static void +Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f000; +} + +static void +Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f10; +} + +static void +Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f100; +} + +static void +Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f20; +} + +static void +Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f200; +} + +static void +Opcode_rur_ae_cw_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f30; +} + +static void +Opcode_wur_ae_cw_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f300; +} + +static void +Opcode_rur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f60; +} + +static void +Opcode_wur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f600; +} + +static void +Opcode_rur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f70; +} + +static void +Opcode_wur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f700; +} + +static void +Opcode_rur_ae_cbegin1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f80; +} + +static void +Opcode_wur_ae_cbegin1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f800; +} + +static void +Opcode_rur_ae_cend1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f90; +} + +static void +Opcode_wur_ae_cend1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f900; +} + +static void +Opcode_rur_ae_cbegin2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30fa0; +} + +static void +Opcode_wur_ae_cbegin2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3fa00; +} + +static void +Opcode_rur_ae_cend2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30fb0; +} + +static void +Opcode_wur_ae_cend2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3fb00; +} + +static void +Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e60; +} + +static void +Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e600; +} + +static void +Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ea04; +} + +static void +Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67eb04; +} + +static void +Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ec04; +} + +static void +Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ed04; +} + +static void +Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ee04; +} + +static void +Opcode_rur_ae_bitptr_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afe0b; + slotbuf[1] = 0; +} + +static void +Opcode_rur_ae_bitptr_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687705; +} + +static void +Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ef04; +} + +static void +Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f004; +} + +static void +Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f104; +} + +static void +Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f204; +} + +static void +Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f304; +} + +static void +Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f404; +} + +static void +Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f504; +} + +static void +Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f604; +} + +static void +Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f704; +} + +static void +Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f804; +} + +static void +Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f904; +} + +static void +Opcode_rur_ae_cwrap_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67fa04; +} + +static void +Opcode_wur_ae_cwrap_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67fb04; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3c000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7450000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10676000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168300; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054c000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901800; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133c000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2676000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c0000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb980008; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13be000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7c000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1440000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7452000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10678000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054e000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941800; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137c000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2678000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1502000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c0008; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fe000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1480000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7454000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1067a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170100; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10550000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981800; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13bc000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x267a000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1542000; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb98000c; +} + +static void +Opcode_ae_l8x4f_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xafc000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c0000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7456000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1067c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170200; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10552000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1800; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fc000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x267c000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1582000; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c000c; +} + +static void +Opcode_ae_l8x4f_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1540000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3e000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1402000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7458000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1067e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170300; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10554000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901a00; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133e000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x267e000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c2000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb981000; +} + +static void +Opcode_ae_l8x4s_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7e000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1442000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x745a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10556000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941a00; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137e000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2680000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1504000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c1000; +} + +static void +Opcode_ae_l8x4s_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c0000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabe000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1482000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x745c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10682000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178100; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10558000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981a00; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13be000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2682000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1544000; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb981004; +} + +static void +Opcode_ae_l8x4s_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1502000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xafe000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c2000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x745e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10684000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178200; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055a000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1a00; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fe000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2684000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1584000; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c1004; +} + +static void +Opcode_ae_l8x4s_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1542000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1404000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7490000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10686000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178300; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055c000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901c00; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2686000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c4000; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb981008; +} + +static void +Opcode_ae_l8x4u_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1582000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1444000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7492000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10688000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055e000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941c00; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1540000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2688000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1506000; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c1008; +} + +static void +Opcode_ae_l8x4u_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c2000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1484000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7494000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1068a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180100; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10560000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981c00; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268a000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1546000; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb98100c; +} + +static void +Opcode_ae_l8x4u_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1504000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c4000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7496000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1068c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180200; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10562000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1c00; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c0000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268c000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1586000; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c100c; +} + +static void +Opcode_ae_l8x4u_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1544000; +} + +static void +Opcode_ae_s8x4u_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7560000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x4u_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10784000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x4u_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a4000; +} + +static void +Opcode_ae_s8x4u_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2bc0000; +} + +static void +Opcode_ae_s8x4u_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2790000; +} + +static void +Opcode_ae_s8x4u_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b21000; +} + +static void +Opcode_ae_s8x4u_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7566000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x4u_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x4u_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106aa000; +} + +static void +Opcode_ae_s8x4u_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac0600; +} + +static void +Opcode_ae_s8x4u_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2796000; +} + +static void +Opcode_ae_s8x4u_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b2100c; +} + +static void +Opcode_ae_s8x4u_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7562000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x4u_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10786000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x4u_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a6000; +} + +static void +Opcode_ae_s8x4u_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2bc0200; +} + +static void +Opcode_ae_s8x4u_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2792000; +} + +static void +Opcode_ae_s8x4u_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b21004; +} + +static void +Opcode_ae_s8x4u_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7564000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x4u_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x4u_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a8000; +} + +static void +Opcode_ae_s8x4u_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2bc0400; +} + +static void +Opcode_ae_s8x4u_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2794000; +} + +static void +Opcode_ae_s8x4u_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b21008; +} + +static void +Opcode_ae_l16m_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae0000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1266000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c836000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110300; +} + +static void +Opcode_ae_l16m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10466000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e4000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2606000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1366000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a60004; +} + +static void +Opcode_ae_l16m_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1366000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa22000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1268000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c874000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10468000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900200; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1326000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2608000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1368000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1368000; +} + +static void +Opcode_ae_l16m_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa20000; +} + +static void +Opcode_ae_l16m_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1260000; +} + +static void +Opcode_ae_l16m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c832000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ec000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ae_l16m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10460000; +} + +static void +Opcode_ae_l16m_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900000; +} + +static void +Opcode_ae_l16m_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1324000; +} + +static void +Opcode_ae_l16m_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2600000; +} + +static void +Opcode_ae_l16m_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1360000; +} + +static void +Opcode_ae_l16m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9860000; +} + +static void +Opcode_ae_l16m_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1360000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa60000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1262000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c872000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_iu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ee000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_iu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110100; +} + +static void +Opcode_ae_l16m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10462000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1364000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2602000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1362000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9860004; +} + +static void +Opcode_ae_l16m_iu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1362000; +} + +static void +Opcode_ae_l16m_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa0000; +} + +static void +Opcode_ae_l16m_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1264000; +} + +static void +Opcode_ae_l16m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c834000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110200; +} + +static void +Opcode_ae_l16m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10464000; +} + +static void +Opcode_ae_l16m_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980000; +} + +static void +Opcode_ae_l16m_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a4000; +} + +static void +Opcode_ae_l16m_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2604000; +} + +static void +Opcode_ae_l16m_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1364000; +} + +static void +Opcode_ae_l16m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a60000; +} + +static void +Opcode_ae_l16m_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1364000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa62000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x126a000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c876000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16m_xu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1046a000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940200; +} + +static void +Opcode_ae_l16m_xu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1366000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260a000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136a000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e0000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136a000; +} + +static void +Opcode_ae_l16_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2a000; +} + +static void +Opcode_ae_l16_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ac000; +} + +static void +Opcode_ae_l16_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8cc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1047e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_ae_l16_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10508000; +} + +static void +Opcode_ae_l16_xc_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x920300; +} + +static void +Opcode_ae_l16_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940a00; +} + +static void +Opcode_ae_l16_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136e000; +} + +static void +Opcode_ae_l16_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262a000; +} + +static void +Opcode_ae_l16_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec000; +} + +static void +Opcode_ae_l16_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x982000c; +} + +static void +Opcode_ae_l16_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ac000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6a000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ec000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8ce000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050a000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980a00; +} + +static void +Opcode_ae_l16_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ae000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262c000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ae000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x986000c; +} + +static void +Opcode_ae_l16_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec000; +} + +static void +Opcode_ae_l16_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa68000; +} + +static void +Opcode_ae_l16_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e8000; +} + +static void +Opcode_ae_l16_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8c6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10472000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128200; +} + +static void +Opcode_ae_l16_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10502000; +} + +static void +Opcode_ae_l16_i_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x908300; +} + +static void +Opcode_ae_l16_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980800; +} + +static void +Opcode_ae_l16_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ac000; +} + +static void +Opcode_ae_l16_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2624000; +} + +static void +Opcode_ae_l16_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13aa000; +} + +static void +Opcode_ae_l16_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9c100c; +} + +static void +Opcode_ae_l16_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e8000; +} + +static void +Opcode_ae_l16_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa8000; +} + +static void +Opcode_ae_l16_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12aa000; +} + +static void +Opcode_ae_l16_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8c8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10476000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128300; +} + +static void +Opcode_ae_l16_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10504000; +} + +static void +Opcode_ae_l16_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910300; +} + +static void +Opcode_ae_l16_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0800; +} + +static void +Opcode_ae_l16_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec000; +} + +static void +Opcode_ae_l16_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2626000; +} + +static void +Opcode_ae_l16_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea000; +} + +static void +Opcode_ae_l16_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9820008; +} + +static void +Opcode_ae_l16_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13aa000; +} + +static void +Opcode_ae_l16_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae8000; +} + +static void +Opcode_ae_l16_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ea000; +} + +static void +Opcode_ae_l16_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8ca000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1047a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ae_l16_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10506000; +} + +static void +Opcode_ae_l16_x_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x918300; +} + +static void +Opcode_ae_l16_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900a00; +} + +static void +Opcode_ae_l16_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132e000; +} + +static void +Opcode_ae_l16_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2628000; +} + +static void +Opcode_ae_l16_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ac000; +} + +static void +Opcode_ae_l16_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9860008; +} + +static void +Opcode_ae_l16_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea000; +} + +static void +Opcode_ae_l16_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaaa000; +} + +static void +Opcode_ae_l16_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ae000; +} + +static void +Opcode_ae_l16_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_ae_l16_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050c000; +} + +static void +Opcode_ae_l16_xp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x928300; +} + +static void +Opcode_ae_l16_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0a00; +} + +static void +Opcode_ae_l16_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee000; +} + +static void +Opcode_ae_l16_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262e000; +} + +static void +Opcode_ae_l16_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee000; +} + +static void +Opcode_ae_l16_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a20008; +} + +static void +Opcode_ae_l16_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ae000; +} + +static void +Opcode_ae_l8_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc06000; +} + +static void +Opcode_ae_l8_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140a000; +} + +static void +Opcode_ae_l8_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74d8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190200; +} + +static void +Opcode_ae_l8_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10574000; +} + +static void +Opcode_ae_l8_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942200; +} + +static void +Opcode_ae_l8_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1546000; +} + +static void +Opcode_ae_l8_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a0000; +} + +static void +Opcode_ae_l8_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150c000; +} + +static void +Opcode_ae_l8_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab40000; +} + +static void +Opcode_ae_l8_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1588000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc46000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144a000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74da000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10576000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982200; +} + +static void +Opcode_ae_l8_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1586000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a2000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154c000; +} + +static void +Opcode_ae_l8_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab40004; +} + +static void +Opcode_ae_l8_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c8000; +} + +static void +Opcode_ae_l8_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc44000; +} + +static void +Opcode_ae_l8_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1448000; +} + +static void +Opcode_ae_l8_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74d2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10696000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188300; +} + +static void +Opcode_ae_l8_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056e000; +} + +static void +Opcode_ae_l8_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982000; +} + +static void +Opcode_ae_l8_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1584000; +} + +static void +Opcode_ae_l8_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269a000; +} + +static void +Opcode_ae_l8_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154a000; +} + +static void +Opcode_ae_l8_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa941004; +} + +static void +Opcode_ae_l8_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c6000; +} + +static void +Opcode_ae_l8_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc84000; +} + +static void +Opcode_ae_l8_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1488000; +} + +static void +Opcode_ae_l8_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74d4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10698000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_ae_l8_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10570000; +} + +static void +Opcode_ae_l8_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2000; +} + +static void +Opcode_ae_l8_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c4000; +} + +static void +Opcode_ae_l8_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269c000; +} + +static void +Opcode_ae_l8_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158a000; +} + +static void +Opcode_ae_l8_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa941008; +} + +static void +Opcode_ae_l8_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1508000; +} + +static void +Opcode_ae_l8_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc4000; +} + +static void +Opcode_ae_l8_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c8000; +} + +static void +Opcode_ae_l8_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74d6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190100; +} + +static void +Opcode_ae_l8_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10572000; +} + +static void +Opcode_ae_l8_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902200; +} + +static void +Opcode_ae_l8_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1506000; +} + +static void +Opcode_ae_l8_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269e000; +} + +static void +Opcode_ae_l8_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15ca000; +} + +static void +Opcode_ae_l8_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa94100c; +} + +static void +Opcode_ae_l8_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1548000; +} + +static void +Opcode_ae_l8_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc86000; +} + +static void +Opcode_ae_l8_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148a000; +} + +static void +Opcode_ae_l8_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74dc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190300; +} + +static void +Opcode_ae_l8_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10578000; +} + +static void +Opcode_ae_l8_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2200; +} + +static void +Opcode_ae_l8_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c6000; +} + +static void +Opcode_ae_l8_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a4000; +} + +static void +Opcode_ae_l8_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158c000; +} + +static void +Opcode_ae_l8_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab40008; +} + +static void +Opcode_ae_l8_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150a000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaac000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b0000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8d8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10648000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138200; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10514000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2636000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f0000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a0008; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b0000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaec000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f0000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8da000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10516000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2638000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1332000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e0008; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f0000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaea000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ee000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8d2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10642000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_ae_l32f24_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050e000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2630000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a60008; +} + +static void +Opcode_ae_l32f24_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2c000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1230000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8d4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10644000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10510000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2632000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1370000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a2000c; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6c000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1270000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8d6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10646000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138100; +} + +static void +Opcode_ae_l32f24_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10512000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2634000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b0000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a6000c; +} + +static void +Opcode_ae_l32f24_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1370000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2e000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1232000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8dc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138300; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10518000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263a000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1372000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a000c; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1332000; +} + +static void +Opcode_ae_l32_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf6000; +} + +static void +Opcode_ae_l32_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12fa000; +} + +static void +Opcode_ae_l32_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7410000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1066a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ae_l32_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1053c000; +} + +static void +Opcode_ae_l32_xc_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x960300; +} + +static void +Opcode_ae_l32_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981200; +} + +static void +Opcode_ae_l32_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b6000; +} + +static void +Opcode_ae_l32_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2662000; +} + +static void +Opcode_ae_l32_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137c000; +} + +static void +Opcode_ae_l32_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3a100c; +} + +static void +Opcode_ae_l32_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ba000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa38000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x123c000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7412000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1053e000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1200; +} + +static void +Opcode_ae_l32_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f6000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2664000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13bc000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3e100c; +} + +static void +Opcode_ae_l32_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fa000; +} + +static void +Opcode_ae_l32_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa36000; +} + +static void +Opcode_ae_l32_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x123a000; +} + +static void +Opcode_ae_l32_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8fa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10664000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158100; +} + +static void +Opcode_ae_l32_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10536000; +} + +static void +Opcode_ae_l32_i_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x948300; +} + +static void +Opcode_ae_l32_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1000; +} + +static void +Opcode_ae_l32_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f4000; +} + +static void +Opcode_ae_l32_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x265c000; +} + +static void +Opcode_ae_l32_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ba000; +} + +static void +Opcode_ae_l32_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3e100c; +} + +static void +Opcode_ae_l32_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f8000; +} + +static void +Opcode_ae_l32_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa76000; +} + +static void +Opcode_ae_l32_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x127a000; +} + +static void +Opcode_ae_l32_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8fc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10666000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158200; +} + +static void +Opcode_ae_l32_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10538000; +} + +static void +Opcode_ae_l32_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x950300; +} + +static void +Opcode_ae_l32_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901200; +} + +static void +Opcode_ae_l32_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1336000; +} + +static void +Opcode_ae_l32_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x265e000; +} + +static void +Opcode_ae_l32_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fa000; +} + +static void +Opcode_ae_l32_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3a100c; +} + +static void +Opcode_ae_l32_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a000; +} + +static void +Opcode_ae_l32_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab6000; +} + +static void +Opcode_ae_l32_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12ba000; +} + +static void +Opcode_ae_l32_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8fe000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10668000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158300; +} + +static void +Opcode_ae_l32_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1053a000; +} + +static void +Opcode_ae_l32_x_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x958300; +} + +static void +Opcode_ae_l32_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941200; +} + +static void +Opcode_ae_l32_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1376000; +} + +static void +Opcode_ae_l32_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2660000; +} + +static void +Opcode_ae_l32_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133c000; +} + +static void +Opcode_ae_l32_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3e100c; +} + +static void +Opcode_ae_l32_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137a000; +} + +static void +Opcode_ae_l32_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa78000; +} + +static void +Opcode_ae_l32_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x127c000; +} + +static void +Opcode_ae_l32_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7414000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1066c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160100; +} + +static void +Opcode_ae_l32_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10540000; +} + +static void +Opcode_ae_l32_xp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x968300; +} + +static void +Opcode_ae_l32_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901400; +} + +static void +Opcode_ae_l32_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338000; +} + +static void +Opcode_ae_l32_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2666000; +} + +static void +Opcode_ae_l32_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fc000; +} + +static void +Opcode_ae_l32_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3a100c; +} + +static void +Opcode_ae_l32_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133c000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1234000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8e4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10652000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140300; +} + +static void +Opcode_ae_l32m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10520000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0c00; +} + +static void +Opcode_ae_l32m_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f0000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2642000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1374000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa000c; +} + +static void +Opcode_ae_l32m_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1334000; +} + +static void +Opcode_ae_l32m_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6e000; +} + +static void +Opcode_ae_l32m_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1272000; +} + +static void +Opcode_ae_l32m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8de000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_l32m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1051a000; +} + +static void +Opcode_ae_l32m_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900c00; +} + +static void +Opcode_ae_l32m_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330000; +} + +static void +Opcode_ae_l32m_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263c000; +} + +static void +Opcode_ae_l32m_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b2000; +} + +static void +Opcode_ae_l32m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e000c; +} + +static void +Opcode_ae_l32m_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1372000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaae000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b2000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_iu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1064e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_iu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140100; +} + +static void +Opcode_ae_l32m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1051c000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940c00; +} + +static void +Opcode_ae_l32m_iu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1370000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263e000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f2000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa0008; +} + +static void +Opcode_ae_l32m_iu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b2000; +} + +static void +Opcode_ae_l32m_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaee000; +} + +static void +Opcode_ae_l32m_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f2000; +} + +static void +Opcode_ae_l32m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8e2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10650000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140200; +} + +static void +Opcode_ae_l32m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1051e000; +} + +static void +Opcode_ae_l32m_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980c00; +} + +static void +Opcode_ae_l32m_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b0000; +} + +static void +Opcode_ae_l32m_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2640000; +} + +static void +Opcode_ae_l32m_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1334000; +} + +static void +Opcode_ae_l32m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae0008; +} + +static void +Opcode_ae_l32m_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f2000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa70000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1274000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8e6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10654000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32m_xu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10522000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900e00; +} + +static void +Opcode_ae_l32m_xu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1332000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2644000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b4000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae000c; +} + +static void +Opcode_ae_l32m_xu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1374000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa64000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e0000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c83e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10472000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940400; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1368000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2612000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e0000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa981000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e0000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa4000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a2000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c878000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10474000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980400; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a8000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2614000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a2000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a2000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa2000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x126c000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c838000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118100; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1046c000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980200; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a6000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260c000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136c000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e0004; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136c000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae2000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x126e000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c83a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118200; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1046e000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0200; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e6000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260e000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136e000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae0000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136e000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa24000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a0000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c83c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118300; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10470000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900400; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1328000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2610000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a0000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae0004; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a0000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae4000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e2000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c87a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fe000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120100; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10476000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0400; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e8000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2616000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e2000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9c1000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e2000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa32000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1236000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8ea000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10658000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148300; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10526000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ca000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ca000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264a000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1376000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83e100c; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f4000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa72000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1276000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8ec000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10528000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6cc000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6cc000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264c000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b6000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x93a100c; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1336000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab0000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b4000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19002030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00202; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148100; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10618008; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680050; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680050; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2646000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f4000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9871001; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000d; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc50080; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d2000; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d86a080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10576008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198300; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c2002; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea000; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea000; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276e000; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d4000; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b70006; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d2000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd0080; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1454000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d834080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1061e004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0100; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fc003; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea080; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea080; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277e000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996100e; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1554000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1492008; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74fc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01e01; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198208; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c4002; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276c080; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1594008; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b7000a; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1592008; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd00c0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1454004; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8340c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c010e; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2001; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6080; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6080; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277e040; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556004; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0303; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516002; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd00d0; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1454005; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8360c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00402; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2009; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6090; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6090; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277e050; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556005; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a0303; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556002; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf0000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f4000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8e8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10656000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148200; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10524000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c8000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c8000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2648000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1336000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a100c; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b4000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab2000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b6000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8ee000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1052a000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ce000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ce000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264e000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f6000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x93e100c; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1376000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa74000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1278000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8f2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150300; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1052e000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d2000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d2000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0e00; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f2000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2654000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b8000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3e100c; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f6000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab4000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b8000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8f4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10530000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d4000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d4000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1334000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2656000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f8000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3a100c; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf2000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f6000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19004030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04203; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150100; +} + +static void +Opcode_ae_l32x2_i_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x298000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10618004; +} + +static void +Opcode_ae_l32x2_i_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930300; +} + +static void +Opcode_ae_l32x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680060; +} + +static void +Opcode_ae_l32x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680060; +} + +static void +Opcode_ae_l32x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940e00; +} + +static void +Opcode_ae_l32x2_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1372000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2650000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9871002; +} + +static void +Opcode_ae_l32x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000e; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90080; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d2008; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74fe000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01f01; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057a008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198308; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c6002; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x970380; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee000; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee000; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac0400; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1550000; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276e080; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d4008; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b7000e; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d2008; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd00e0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1454006; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8340d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00401; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c010f; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2005; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f60a0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f60a0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80600; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200f; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277e060; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556006; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e0303; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1596002; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd00f0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1454007; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8360d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00403; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a200d; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f60b0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f60b0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80610; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x155200f; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277e070; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556007; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e0303; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d6002; +} + +static void +Opcode_ae_l32x2_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa34000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1238000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8f0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150200; +} + +static void +Opcode_ae_l32x2_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1052c000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x938300; +} + +static void +Opcode_ae_l32x2_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980e00; +} + +static void +Opcode_ae_l32x2_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b2000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2652000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1378000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3a100c; +} + +static void +Opcode_ae_l32x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b6000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf4000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f8000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8f8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10662000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29a000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10534000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940300; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d6000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d6000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b4000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x265a000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137a000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3a100c; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b8000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa6000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a6000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c87e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10466000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1047a000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c2000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c2000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980600; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13aa000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261c000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a6000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9c1004; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e4000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae6000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e6000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1047c000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c4000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c4000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c0600; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261e000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e6000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa981008; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a6000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa26000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a4000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00203; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120200; +} + +static void +Opcode_ae_l16x4_i_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x294000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10618000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900300; +} + +static void +Opcode_ae_l16x4_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680040; +} + +static void +Opcode_ae_l16x4_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680040; +} + +static void +Opcode_ae_l16x4_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900600; +} + +static void +Opcode_ae_l16x4_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132a000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2618000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a4000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9871000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000c; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc50000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1492000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d82a080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10576000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198200; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0002; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x970300; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e8000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e8000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80400; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276c000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1594000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b70002; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1592000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa66000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e4000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c87c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10462000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120300; +} + +static void +Opcode_ae_l16x4_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10478000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940600; +} + +static void +Opcode_ae_l16x4_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136a000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261a000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e4000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa981004; +} + +static void +Opcode_ae_l16x4_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a4000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa28000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a8000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8c4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c06000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1046e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128100; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x296000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c6000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c6000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2940800; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136c000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2622000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e8000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa98100c; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a8000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc82000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1486000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x749a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188100; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10566000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e2000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e2000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981e00; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1582000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2692000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1548000; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa940004; +} + +static void +Opcode_ae_l8x8_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c4000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc2000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c6000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x749c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10568000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e4000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e4000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1e00; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c2000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2694000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1588000; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa940008; +} + +static void +Opcode_ae_l8x8_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1506000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc02000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1406000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19082030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0420b; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10708001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180300; +} + +static void +Opcode_ae_l8x8_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10620008; +} + +static void +Opcode_ae_l8x8_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0050; +} + +static void +Opcode_ae_l8x8_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0050; +} + +static void +Opcode_ae_l8x8_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901e00; +} + +static void +Opcode_ae_l8x8_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1502000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268e000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c6000; +} + +static void +Opcode_ae_l8x8_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9971001; +} + +static void +Opcode_ae_l8x8_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144000d; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd0000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1414000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74fc080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c8002; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e8080; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e8080; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80480; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1590000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2770000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516000; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9921008; +} + +static void +Opcode_ae_l8x8_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc42000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1446000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7498000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1068e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10564000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941e00; +} + +static void +Opcode_ae_l8x8_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1542000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2690000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1508000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa940000; +} + +static void +Opcode_ae_l8x8_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1584000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc04000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1408000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10694000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188200; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056c000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e6000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e6000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1544000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2698000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150a000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa941000; +} + +static void +Opcode_ae_l8x8_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1586000; +} + +static void +Opcode_ae_l64_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7a000; +} + +static void +Opcode_ae_l64_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x127e000; +} + +static void +Opcode_ae_l64_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7418000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10670000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168100; +} + +static void +Opcode_ae_l64_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10544000; +} + +static void +Opcode_ae_l64_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6da000; +} + +static void +Opcode_ae_l64_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6da000; +} + +static void +Opcode_ae_l64_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2901600; +} + +static void +Opcode_ae_l64_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a000; +} + +static void +Opcode_ae_l64_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x266e000; +} + +static void +Opcode_ae_l64_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fe000; +} + +static void +Opcode_ae_l64_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb980000; +} + +static void +Opcode_ae_l64_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13bc000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaba000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12be000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x741a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10546000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6dc000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6dc000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941600; +} + +static void +Opcode_ae_l64_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137a000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2670000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c0000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fc000; +} + +static void +Opcode_ae_l64_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab8000; +} + +static void +Opcode_ae_l64_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12bc000; +} + +static void +Opcode_ae_l64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19006030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d04202; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160200; +} + +static void +Opcode_ae_l64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1061800c; +} + +static void +Opcode_ae_l64_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680070; +} + +static void +Opcode_ae_l64_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680070; +} + +static void +Opcode_ae_l64_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941400; +} + +static void +Opcode_ae_l64_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1378000; +} + +static void +Opcode_ae_l64_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2668000; +} + +static void +Opcode_ae_l64_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133e000; +} + +static void +Opcode_ae_l64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9871003; +} + +static void +Opcode_ae_l64_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000f; +} + +static void +Opcode_ae_l64_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf8000; +} + +static void +Opcode_ae_l64_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12fc000; +} + +static void +Opcode_ae_l64_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19080030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0020b; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10708000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160300; +} + +static void +Opcode_ae_l64_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10620000; +} + +static void +Opcode_ae_l64_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0040; +} + +static void +Opcode_ae_l64_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0040; +} + +static void +Opcode_ae_l64_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981400; +} + +static void +Opcode_ae_l64_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b8000; +} + +static void +Opcode_ae_l64_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x266a000; +} + +static void +Opcode_ae_l64_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137e000; +} + +static void +Opcode_ae_l64_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9971000; +} + +static void +Opcode_ae_l64_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144000c; +} + +static void +Opcode_ae_l64_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3a000; +} + +static void +Opcode_ae_l64_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x123e000; +} + +static void +Opcode_ae_l64_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7416000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1066e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_ae_l64_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10542000; +} + +static void +Opcode_ae_l64_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d8000; +} + +static void +Opcode_ae_l64_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d8000; +} + +static void +Opcode_ae_l64_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1400; +} + +static void +Opcode_ae_l64_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f8000; +} + +static void +Opcode_ae_l64_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x266c000; +} + +static void +Opcode_ae_l64_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13be000; +} + +static void +Opcode_ae_l64_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e100c; +} + +static void +Opcode_ae_l64_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137c000; +} + +static void +Opcode_ae_l64_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xafa000; +} + +static void +Opcode_ae_l64_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12fe000; +} + +static void +Opcode_ae_l64_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x741e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10674000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168200; +} + +static void +Opcode_ae_l64_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054a000; +} + +static void +Opcode_ae_l64_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6de000; +} + +static void +Opcode_ae_l64_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6de000; +} + +static void +Opcode_ae_l64_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c1600; +} + +static void +Opcode_ae_l64_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13fa000; +} + +static void +Opcode_ae_l64_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2674000; +} + +static void +Opcode_ae_l64_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580000; +} + +static void +Opcode_ae_l64_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9c0004; +} + +static void +Opcode_ae_l64_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137e000; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7550000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058c000; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942800; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b8000; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9821008; +} + +static void +Opcode_ae_s16x2m_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7552000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058e000; +} + +static void +Opcode_ae_s16x2m_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982800; +} + +static void +Opcode_ae_s16x2m_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ba000; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x751a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106aa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10586000; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982600; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b2000; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9861000; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x751c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ac000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10588000; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2600; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b4000; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9821004; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x751e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ae000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058a000; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902800; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b6000; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9861004; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7554000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10590000; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2800; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26bc000; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9861008; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7428000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c4000; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f6000; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae100c; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c6000; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f8000; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab80000; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19100030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10710000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10628000; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318000; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f2000; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a70000; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d82e080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10730008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ce002; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380000; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2776000; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996100a; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8340f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718007; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2006; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2984010; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996110f; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8340e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718006; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2002; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2904010; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996100f; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8360e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a200a; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2944010; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996120f; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7426000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106de000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c2000; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f4000; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa100c; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c8000; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26fa000; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc0000; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7434000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ea000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d0000; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3200; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2706000; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc0008; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7436000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d2000; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903400; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2708000; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab8000c; +} + +static void +Opcode_ae_s32x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19104030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10710002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10628004; +} + +static void +Opcode_ae_s32x2_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318010; +} + +static void +Opcode_ae_s32x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943200; +} + +static void +Opcode_ae_s32x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2702000; +} + +static void +Opcode_ae_s32x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a70002; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d86e080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10732008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d2002; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380200; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00600; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277a000; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996100c; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8360f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071800a; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a200e; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80620; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c4010; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x996130f; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191a4030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2003; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80630; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2906010; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0120c; +} + +static void +Opcode_ae_s32x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7432000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ce000; +} + +static void +Opcode_ae_s32x2_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308200; +} + +static void +Opcode_ae_s32x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983200; +} + +static void +Opcode_ae_s32x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2704000; +} + +static void +Opcode_ae_s32x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab80008; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x743a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ee000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d6000; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308300; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983400; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270c000; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab81000; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19102030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10710001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10628008; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318200; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26fc000; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a70001; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d86c080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10732000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d0002; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380100; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2778000; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x992100c; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ca000; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308000; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26fe000; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab80004; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7430000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106e6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105cc000; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1308100; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700000; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc0004; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x755c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ba000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10598000; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982a00; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c8000; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a61000; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x755e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1059a000; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2a00; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ca000; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a21004; +} + +static void +Opcode_ae_s16x4_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19086030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10708003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1062000c; +} + +static void +Opcode_ae_s16x4_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1310210; +} + +static void +Opcode_ae_s16x4_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902a00; +} + +static void +Opcode_ae_s16x4_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c4000; +} + +static void +Opcode_ae_s16x4_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9971003; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d82c080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10730000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104cc002; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318310; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac0480; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2774000; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x992100a; +} + +static void +Opcode_ae_s16x4_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x755a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10596000; +} + +static void +Opcode_ae_s16x4_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330200; +} + +static void +Opcode_ae_s16x4_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942a00; +} + +static void +Opcode_ae_s16x4_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c6000; +} + +static void +Opcode_ae_s16x4_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a21000; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7592000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106be000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1059e000; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330300; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942c00; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ce000; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a21008; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1051e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105fc000; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00000; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2738000; +} + +static void +Opcode_ae_s8x8_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc1004; +} + +static void +Opcode_ae_s8x8_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74a2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105fe000; +} + +static void +Opcode_ae_s8x8_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a40000; +} + +static void +Opcode_ae_s8x8_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x273a000; +} + +static void +Opcode_ae_s8x8_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb81008; +} + +static void +Opcode_ae_s8x8_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19182030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10630008; +} + +static void +Opcode_ae_s8x8_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983e00; +} + +static void +Opcode_ae_s8x8_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2734000; +} + +static void +Opcode_ae_s8x8_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b70001; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d830080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10734000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d4002; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a40600; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277c000; +} + +static void +Opcode_ae_s8x8_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x992100e; +} + +static void +Opcode_ae_s8x8_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x747e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1051a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105fa000; +} + +static void +Opcode_ae_s8x8_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3e00; +} + +static void +Opcode_ae_s8x8_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2736000; +} + +static void +Opcode_ae_s8x8_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb81004; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74a6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10526000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10602000; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac0000; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x273e000; +} + +static void +Opcode_ae_s8x8_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb8100c; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7514000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10580000; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2400; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ac000; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab41008; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7516000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10582000; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902600; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ae000; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab4100c; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74de000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057a000; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902400; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a6000; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab4000c; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7510000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057c000; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942400; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a8000; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab41000; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7512000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057e000; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982400; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26aa000; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab41004; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7518000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10584000; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942600; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b0000; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9821000; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75d6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b2000; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e2000; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a100c; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75d8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b4000; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e4000; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e100c; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ca000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ac000; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26dc000; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e1004; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75d2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106cc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae000; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26de000; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a1008; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75d4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ce000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b0000; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e0000; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e1008; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75da000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b6000; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e6000; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa1000; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x746e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10502000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ea000; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903a00; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2720000; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb80004; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7470000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ec000; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943a00; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2722000; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc0004; +} + +static void +Opcode_ae_s32_l_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7468000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106fa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e4000; +} + +static void +Opcode_ae_s32_l_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943800; +} + +static void +Opcode_ae_s32_l_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x271a000; +} + +static void +Opcode_ae_s32_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc100c; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x746a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106fc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e6000; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983800; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x271c000; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb80000; +} + +static void +Opcode_ae_s32_l_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x746c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106fe000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e8000; +} + +static void +Opcode_ae_s32_l_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3800; +} + +static void +Opcode_ae_s32_l_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x271e000; +} + +static void +Opcode_ae_s32_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc0000; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7472000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10506000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ee000; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983a00; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2724000; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb80008; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7462000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105de000; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983600; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2714000; +} + +static void +Opcode_ae_s32_h_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab81008; +} + +static void +Opcode_ae_s32_h_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7464000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e0000; +} + +static void +Opcode_ae_s32_h_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3600; +} + +static void +Opcode_ae_s32_h_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2716000; +} + +static void +Opcode_ae_s32_h_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc1008; +} + +static void +Opcode_ae_s32_h_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x743c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d8000; +} + +static void +Opcode_ae_s32_h_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3400; +} + +static void +Opcode_ae_s32_h_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270e000; +} + +static void +Opcode_ae_s32_h_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc1000; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x743e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105da000; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903600; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2710000; +} + +static void +Opcode_ae_s32_h_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab81004; +} + +static void +Opcode_ae_s32_h_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7460000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105dc000; +} + +static void +Opcode_ae_s32_h_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943600; +} + +static void +Opcode_ae_s32_h_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2712000; +} + +static void +Opcode_ae_s32_h_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc1004; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7466000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106f8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105e2000; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903800; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2718000; +} + +static void +Opcode_ae_s32_h_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab8100c; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x759a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a6000; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2942e00; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d6000; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a1000; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x759c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a8000; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982e00; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d8000; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98e1000; +} + +static void +Opcode_ae_s16_0_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7594000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a0000; +} + +static void +Opcode_ae_s16_0_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2982c00; +} + +static void +Opcode_ae_s16_0_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d0000; +} + +static void +Opcode_ae_s16_0_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a61008; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7596000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a2000; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2c00; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d2000; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a2100c; +} + +static void +Opcode_ae_s16_0_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7598000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a4000; +} + +static void +Opcode_ae_s16_0_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902e00; +} + +static void +Opcode_ae_s16_0_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d4000; +} + +static void +Opcode_ae_s16_0_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a6100c; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x759e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa000; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c2e00; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26da000; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98a1004; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ae000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10536000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060a000; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ac0200; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2746000; +} + +static void +Opcode_ae_s8_0_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9870008; +} + +static void +Opcode_ae_s8_0_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74b0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060c000; +} + +static void +Opcode_ae_s8_0_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00400; +} + +static void +Opcode_ae_s8_0_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2748000; +} + +static void +Opcode_ae_s8_0_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x987000c; +} + +static void +Opcode_ae_s8_0_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74a8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1052a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10604000; +} + +static void +Opcode_ae_s8_0_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00200; +} + +static void +Opcode_ae_s8_0_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2740000; +} + +static void +Opcode_ae_s8_0_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc100c; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74aa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1052e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10606000; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a40200; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2742000; +} + +static void +Opcode_ae_s8_0_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9870000; +} + +static void +Opcode_ae_s8_0_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74ac000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10532000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10608000; +} + +static void +Opcode_ae_s8_0_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80200; +} + +static void +Opcode_ae_s8_0_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2744000; +} + +static void +Opcode_ae_s8_0_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9870004; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74b2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1053a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060e000; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a40400; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x274a000; +} + +static void +Opcode_ae_s8_0_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9970000; +} + +static void +Opcode_ae_s64_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7476000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f2000; +} + +static void +Opcode_ae_s64_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983c00; +} + +static void +Opcode_ae_s64_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x272c000; +} + +static void +Opcode_ae_s64_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb8000c; +} + +static void +Opcode_ae_s64_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7478000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f4000; +} + +static void +Opcode_ae_s64_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3c00; +} + +static void +Opcode_ae_s64_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x272e000; +} + +static void +Opcode_ae_s64_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc000c; +} + +static void +Opcode_ae_s64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19106030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10710003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1062800c; +} + +static void +Opcode_ae_s64_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3a00; +} + +static void +Opcode_ae_s64_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2726000; +} + +static void +Opcode_ae_s64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a70003; +} + +static void +Opcode_ae_s64_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19180030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10718000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10630000; +} + +static void +Opcode_ae_s64_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903c00; +} + +static void +Opcode_ae_s64_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2728000; +} + +static void +Opcode_ae_s64_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b70000; +} + +static void +Opcode_ae_s64_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7474000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f0000; +} + +static void +Opcode_ae_s64_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943c00; +} + +static void +Opcode_ae_s64_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x272a000; +} + +static void +Opcode_ae_s64_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc0008; +} + +static void +Opcode_ae_s64_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x747c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10516000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f8000; +} + +static void +Opcode_ae_s64_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943e00; +} + +static void +Opcode_ae_s64_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2732000; +} + +static void +Opcode_ae_s64_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc1000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7422000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106da000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105be000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29c3000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ee000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa1008; +} + +static void +Opcode_ae_s32m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75dc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105b8000; +} + +static void +Opcode_ae_s32m_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903000; +} + +static void +Opcode_ae_s32m_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e8000; +} + +static void +Opcode_ae_s32m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae1000; +} + +static void +Opcode_ae_s32m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75de000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ba000; +} + +static void +Opcode_ae_s32m_iu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943000; +} + +static void +Opcode_ae_s32m_iu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ea000; +} + +static void +Opcode_ae_s32m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9aa1004; +} + +static void +Opcode_ae_s32m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7420000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106d8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105bc000; +} + +static void +Opcode_ae_s32m_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2983000; +} + +static void +Opcode_ae_s32m_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26ec000; +} + +static void +Opcode_ae_s32m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae1004; +} + +static void +Opcode_ae_s32m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7424000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106dc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105c0000; +} + +static void +Opcode_ae_s32m_xu_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903200; +} + +static void +Opcode_ae_s32m_xu_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f0000; +} + +static void +Opcode_ae_s32m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9ae1008; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8f6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c07900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10660000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10532000; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2941000; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1374000; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2658000; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a000; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3e100c; +} + +static void +Opcode_ae_l32x2_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1378000; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8c2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1046a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1047e000; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900800; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132c000; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2620000; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a8000; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9c1008; +} + +static void +Opcode_ae_l16x4_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e6000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x749e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10692000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1056a000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1504000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2696000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c8000; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa94000c; +} + +static void +Opcode_ae_l8x8_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1546000; +} + +static void +Opcode_ae_l64_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x741c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10672000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10548000; +} + +static void +Opcode_ae_l64_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2981600; +} + +static void +Opcode_ae_l64_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ba000; +} + +static void +Opcode_ae_l64_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2672000; +} + +static void +Opcode_ae_l64_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1540000; +} + +static void +Opcode_ae_l64_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb980004; +} + +static void +Opcode_ae_l64_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133e000; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7438000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106ec000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105d4000; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2943400; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270a000; +} + +static void +Opcode_ae_s32x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xabc000c; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7590000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106bc000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1059c000; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2902c00; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26cc000; +} + +static void +Opcode_ae_s16x4_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a61004; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74a4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10522000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600000; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80000; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x273c000; +} + +static void +Opcode_ae_s8x8_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbbc1008; +} + +static void +Opcode_ae_s64_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x747a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10512000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s64_xc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105f6000; +} + +static void +Opcode_ae_s64_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2903e00; +} + +static void +Opcode_ae_s64_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2730000; +} + +static void +Opcode_ae_s64_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb81000; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19084030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10708002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10620004; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1310010; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26be000; +} + +static void +Opcode_ae_s16x4rng_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9971002; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74fe080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1057e008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ca002; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1318210; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2772000; +} + +static void +Opcode_ae_s16x4rng_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9961008; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7556000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10592000; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330000; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c0000; +} + +static void +Opcode_ae_s16x4rng_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x982100c; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7558000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106b6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10594000; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1330100; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c2000; +} + +static void +Opcode_ae_s16x4rng_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x986100c; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c500000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe150000; +} + +static void +Opcode_ae_l32x2x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c540000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a40000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1540000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf150000; +} + +static void +Opcode_ae_l32x2x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1940000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1440000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb150000; +} + +static void +Opcode_ae_l32x2x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7340000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900100; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1480000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc150000; +} + +static void +Opcode_ae_l32x2x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19c0000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c0000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd150000; +} + +static void +Opcode_ae_l32x2x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c5c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c0000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7840000; +} + +static void +Opcode_ae_l32x2x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1840000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7570000; +} + +static void +Opcode_ae_l16x4x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d480000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1880000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1380000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8150000; +} + +static void +Opcode_ae_l16x4x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c380000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1780000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7430000; +} + +static void +Opcode_ae_l16x4x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c3c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c0000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7470000; +} + +static void +Opcode_ae_l16x4x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c480000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530000; +} + +static void +Opcode_ae_l16x4x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7240000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa150000; +} + +static void +Opcode_ae_l16x4x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d380000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d80000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1880000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7830000; +} + +static void +Opcode_ae_l8x8x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc0000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c0000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7870000; +} + +static void +Opcode_ae_l8x8x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc0000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c0000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7860000; +} + +static void +Opcode_ae_l8x8x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900200; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7920000; +} + +static void +Opcode_ae_l8x8x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d340000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d40000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1840000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7960000; +} + +static void +Opcode_ae_l8x8x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c640000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e40000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1940000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7970000; +} + +static void +Opcode_ae_l8x8x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d5c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c0000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7850000; +} + +static void +Opcode_ae_l64x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d200000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7910000; +} + +static void +Opcode_ae_l64x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d500000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7900000; +} + +static void +Opcode_ae_l64x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d540000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b40000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1640000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7940000; +} + +static void +Opcode_ae_l64x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d580000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_x_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b80000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1680000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7810000; +} + +static void +Opcode_ae_l64x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d280000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1780000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7820000; +} + +static void +Opcode_ae_l64x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_s32x2x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2100000; +} + +static void +Opcode_ae_s32x2x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00000; +} + +static void +Opcode_ae_s32x2x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9800000; +} + +static void +Opcode_ae_s32x2x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2140000; +} + +static void +Opcode_ae_s32x2x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e40000; +} + +static void +Opcode_ae_s32x2x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9840000; +} + +static void +Opcode_ae_s32x2x2_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180000; +} + +static void +Opcode_ae_s32x2x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2040000; +} + +static void +Opcode_ae_s32x2x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d40000; +} + +static void +Opcode_ae_s32x2x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d70000; +} + +static void +Opcode_ae_s32x2x2_ip_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_s32x2x2_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0000; +} + +static void +Opcode_ae_s32x2x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080000; +} + +static void +Opcode_ae_s32x2x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d80000; +} + +static void +Opcode_ae_s32x2x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8800000; +} + +static void +Opcode_ae_s32x2x2_x_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_s32x2x2_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_s32x2x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0000; +} + +static void +Opcode_ae_s32x2x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc0000; +} + +static void +Opcode_ae_s32x2x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8840000; +} + +static void +Opcode_ae_s32x2x2_xp_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_s32x2x2_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1240000; +} + +static void +Opcode_ae_s32x2x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21c0000; +} + +static void +Opcode_ae_s32x2x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec0000; +} + +static void +Opcode_ae_s32x2x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa840000; +} + +static void +Opcode_ae_s32x2x2rng_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c40000; +} + +static void +Opcode_ae_s32x2x2rng_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d60000; +} + +static void +Opcode_ae_s32x2x2rng_ip_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_s32x2x2rng_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80000; +} + +static void +Opcode_ae_s32x2x2rng_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c30000; +} + +static void +Opcode_ae_s32x2x2rng_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc0000; +} + +static void +Opcode_ae_s32x2x2rng_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c70000; +} + +static void +Opcode_ae_s32x2x2rng_xp_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_s32x2x2rng_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00000; +} + +static void +Opcode_ae_s32x2x2rng_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d30000; +} + +static void +Opcode_ae_s16x4x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f40000; +} + +static void +Opcode_ae_s16x4x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b40000; +} + +static void +Opcode_ae_s16x4x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d50000; +} + +static void +Opcode_ae_s16x4x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f80000; +} + +static void +Opcode_ae_s16x4x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b80000; +} + +static void +Opcode_ae_s16x4x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c20000; +} + +static void +Opcode_ae_s16x4x2_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_s16x4x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e80000; +} + +static void +Opcode_ae_s16x4x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a80000; +} + +static void +Opcode_ae_s16x4x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c10000; +} + +static void +Opcode_ae_s16x4x2_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_s16x4x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec0000; +} + +static void +Opcode_ae_s16x4x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac0000; +} + +static void +Opcode_ae_s16x4x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c50000; +} + +static void +Opcode_ae_s16x4x2_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_s16x4x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00000; +} + +static void +Opcode_ae_s16x4x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00000; +} + +static void +Opcode_ae_s16x4x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d10000; +} + +static void +Opcode_ae_s16x4x2_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140000; +} + +static void +Opcode_ae_s16x4x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ae_s16x4x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00000; +} + +static void +Opcode_ae_s16x4x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d20000; +} + +static void +Opcode_ae_s8x8x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2480000; +} + +static void +Opcode_ae_s8x8x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2180000; +} + +static void +Opcode_ae_s8x8x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8900000; +} + +static void +Opcode_ae_s8x8x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24c0000; +} + +static void +Opcode_ae_s8x8x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21c0000; +} + +static void +Opcode_ae_s8x8x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8940000; +} + +static void +Opcode_ae_s8x8x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23c0000; +} + +static void +Opcode_ae_s8x8x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0000; +} + +static void +Opcode_ae_s8x8x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe840000; +} + +static void +Opcode_ae_s8x8x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400000; +} + +static void +Opcode_ae_s8x8x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2100000; +} + +static void +Opcode_ae_s8x8x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf800000; +} + +static void +Opcode_ae_s8x8x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2440000; +} + +static void +Opcode_ae_s8x8x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2140000; +} + +static void +Opcode_ae_s8x8x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf840000; +} + +static void +Opcode_ae_s8x8x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540000; +} + +static void +Opcode_ae_s8x8x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2240000; +} + +static void +Opcode_ae_s8x8x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9940000; +} + +static void +Opcode_ae_s8x4ux2_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20e40000; +} + +static void +Opcode_ae_s8x4ux2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b80000; +} + +static void +Opcode_ae_s8x4ux2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2580080; +} + +static void +Opcode_ae_s8x4ux2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9910000; +} + +static void +Opcode_ae_s8x4ux2_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20e80000; +} + +static void +Opcode_ae_s8x4ux2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b80080; +} + +static void +Opcode_ae_s8x4ux2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c0080; +} + +static void +Opcode_ae_s8x4ux2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9910002; +} + +static void +Opcode_ae_s8x4ux2_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c0000; +} + +static void +Opcode_ae_s8x4ux2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b00000; +} + +static void +Opcode_ae_s8x4ux2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c0000; +} + +static void +Opcode_ae_s8x4ux2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8910000; +} + +static void +Opcode_ae_s8x4ux2_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20e00000; +} + +static void +Opcode_ae_s8x4ux2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b40000; +} + +static void +Opcode_ae_s8x4ux2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000000; +} + +static void +Opcode_ae_s8x4ux2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8950000; +} + +static void +Opcode_ae_s64x2_xc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22c0000; +} + +static void +Opcode_ae_s64x2_xc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fc0000; +} + +static void +Opcode_ae_s64x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc840000; +} + +static void +Opcode_ae_s64x2_xc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2300000; +} + +static void +Opcode_ae_s64x2_xc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ae_s64x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd800000; +} + +static void +Opcode_ae_s64x2_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200000; +} + +static void +Opcode_ae_s64x2_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00000; +} + +static void +Opcode_ae_s64x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb800000; +} + +static void +Opcode_ae_s64x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2240000; +} + +static void +Opcode_ae_s64x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f40000; +} + +static void +Opcode_ae_s64x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb840000; +} + +static void +Opcode_ae_s64x2_x_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2280000; +} + +static void +Opcode_ae_s64x2_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f80000; +} + +static void +Opcode_ae_s64x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc800000; +} + +static void +Opcode_ae_s64x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2380000; +} + +static void +Opcode_ae_s64x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080000; +} + +static void +Opcode_ae_s64x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe800000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c580000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a80000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7800000; +} + +static void +Opcode_ae_l32x2x2_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d4c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c0000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c0000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9150000; +} + +static void +Opcode_ae_l16x4x2_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c600000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b00200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e00000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7930000; +} + +static void +Opcode_ae_l8x8x2_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d240000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c40000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1740000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7950000; +} + +static void +Opcode_ae_l64x2_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_s32x2x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2180000; +} + +static void +Opcode_ae_s32x2x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e80000; +} + +static void +Opcode_ae_s32x2x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800000; +} + +static void +Opcode_ae_s16x4x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fc0000; +} + +static void +Opcode_ae_s16x4x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc0000; +} + +static void +Opcode_ae_s16x4x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c60000; +} + +static void +Opcode_ae_s8x8x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500000; +} + +static void +Opcode_ae_s8x8x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2200000; +} + +static void +Opcode_ae_s8x8x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9900000; +} + +static void +Opcode_ae_s64x2_xc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2340000; +} + +static void +Opcode_ae_s64x2_xc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2040000; +} + +static void +Opcode_ae_s64x2_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd840000; +} + +static void +Opcode_ae_s16x4x2rng_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1980000; +} + +static void +Opcode_ae_s16x4x2rng_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c00000; +} + +static void +Opcode_ae_s16x4x2rng_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19c0000; +} + +static void +Opcode_ae_s16x4x2rng_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c40000; +} + +static void +Opcode_ae_s16x4x2rng_x_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00000; +} + +static void +Opcode_ae_s16x4x2rng_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d00000; +} + +static void +Opcode_ae_s16x4x2rng_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a40000; +} + +static void +Opcode_ae_s16x4x2rng_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d40000; +} + +static void +Opcode_ae_zalign64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b48fb4; + slotbuf[1] = 0; +} + +static void +Opcode_ae_zalign64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef70; + slotbuf[1] = 0; +} + +static void +Opcode_ae_zalign64_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069db30; +} + +static void +Opcode_ae_zalign64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab20045; +} + +static void +Opcode_ae_lalign64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f10; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lalign64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10748300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lalign64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680600; +} + +static void +Opcode_ae_lalign64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9839c01; +} + +static void +Opcode_ae_salign64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f20; + slotbuf[1] = 0; +} + +static void +Opcode_ae_salign64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10748700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_salign64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680700; +} + +static void +Opcode_ae_salign64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70ab000; +} + +static void +Opcode_ae_movalign_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b48fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movalign_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ef80; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movalign_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687702; +} + +static void +Opcode_ae_movalign_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab20005; +} + +static void +Opcode_ae_la64_pp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b20fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la64_pp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afa0c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la64_pp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf500; +} + +static void +Opcode_ae_la64_pp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685602; +} + +static void +Opcode_ae_la64_pp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08540; +} + +static void +Opcode_ae_la64_pp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09a0e; +} + +static void +Opcode_ae_la64_pp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142e10c; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b50f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af00c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681703; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09a0d; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b40f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074cf0c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681701; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0920d; +} + +static void +Opcode_ae_la24pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b58f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683600; +} + +static void +Opcode_ae_la24pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09e0d; +} + +static void +Opcode_ae_la24neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b48f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681702; +} + +static void +Opcode_ae_la24neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0960d; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b70f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af80c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683603; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0160e; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b60f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af40c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683601; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0120e; +} + +static void +Opcode_ae_la24x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b78f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683700; +} + +static void +Opcode_ae_la24x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0160f; +} + +static void +Opcode_ae_la24x2neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b68f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683602; +} + +static void +Opcode_ae_la24x2neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0120f; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b08fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af20c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683703; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01e0e; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afc0c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683701; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01a0e; +} + +static void +Opcode_ae_la32x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b08fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685600; +} + +static void +Opcode_ae_la32x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01e0f; +} + +static void +Opcode_ae_la32x2neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10683702; +} + +static void +Opcode_ae_la32x2neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01a0f; +} + +static void +Opcode_ae_la32x2pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b10fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2pos_pc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af60c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2pos_pc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685601; +} + +static void +Opcode_ae_la32x2pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0920e; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b10f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074cf04; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681602; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09f0e; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074cf00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681600; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09f0c; +} + +static void +Opcode_ae_la16x4pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b18f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681603; +} + +static void +Opcode_ae_la16x4pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09f0f; +} + +static void +Opcode_ae_la16x4neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b08f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681601; +} + +static void +Opcode_ae_la16x4neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09f0d; +} + +static void +Opcode_ae_la16x4pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b20f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4pos_pc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074cf08; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4pos_pc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10681700; +} + +static void +Opcode_ae_la16x4pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0120d; +} + +static void +Opcode_ae_la8x8pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b28fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074eb00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685701; +} + +static void +Opcode_ae_la8x8pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09e0f; +} + +static void +Opcode_ae_la8x8neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b20fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afe0c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685603; +} + +static void +Opcode_ae_la8x8neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09a0f; +} + +static void +Opcode_ae_la8x8pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b30fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685702; +} + +static void +Opcode_ae_la8x8pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa820005; +} + +static void +Opcode_ae_la8x8neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b28fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685700; +} + +static void +Opcode_ae_la8x8neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09e0e; +} + +static void +Opcode_ae_la8x8pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b30fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8pos_pc2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074eb04; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8pos_pc2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10685703; +} + +static void +Opcode_ae_la8x8pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa860005; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14230; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416103; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b10fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0ec02; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x686180; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x686180; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f30; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514103; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002430; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151630b; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0920f; +} + +static void +Opcode_ae_la32x2x2pos_pc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142810c; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14240; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416104; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b18fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0f002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x688180; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x688180; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f40; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514104; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002440; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151640b; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0960e; +} + +static void +Opcode_ae_la32x2x2pos_pc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142a10c; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14250; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416105; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b18fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0f402; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68a180; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68a180; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f50; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514105; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002450; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151650b; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0960f; +} + +static void +Opcode_ae_la32x2x2pos_pc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142c10c; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14200; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416100; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b28f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0e002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680180; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680180; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f00; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514100; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002400; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151600b; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0160d; +} + +static void +Opcode_ae_la16x4x2pos_pc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142210c; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14210; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416101; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b30f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0e402; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x682180; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x682180; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f10; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514101; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002410; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151610b; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01a0d; +} + +static void +Opcode_ae_la16x4x2pos_pc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142410c; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14220; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416102; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b38f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0e802; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x684180; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x684180; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f20; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514102; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002420; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151620b; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01e0d; +} + +static void +Opcode_ae_la16x4x2pos_pc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142610c; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14260; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416106; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b38fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0f802; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68c180; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68c180; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f60; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514106; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002460; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151660b; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa920005; +} + +static void +Opcode_ae_la8x8x2pos_pc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143010c; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14270; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416107; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b38fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0fc02; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68e180; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68e180; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f70; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514107; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002470; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151670b; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa960005; +} + +static void +Opcode_ae_la8x8x2pos_pc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143210c; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14280; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416108; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b40fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690180; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690180; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00f80; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514108; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002480; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151680b; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa20005; +} + +static void +Opcode_ae_la8x8x2pos_pc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143410c; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b48fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074eb0c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687601; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8a4004; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b40fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074eb08; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10687600; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa26004; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193c0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060a004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ee003; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fe000; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fe000; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006f0; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000f; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c40205; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19388030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f0002; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0040; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0040; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00800; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512000; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08205; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193c8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060c004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f0003; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00810; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512001; +} + +static void +Opcode_ae_la32x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48205; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19390030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060e004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0008; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f2002; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08000; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2040; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2040; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00820; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512002; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00305; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400c; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193d8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10612004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f4003; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08040; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f8040; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f8040; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00850; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512005; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48305; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400d; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193d0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10610004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f2003; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4040; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4040; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00830; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512003; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c40305; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19398030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f4002; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6040; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6040; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00840; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512004; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08305; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d838080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10736000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d6002; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea0c0; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ea0c0; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00680; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510008; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08208; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d838090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d6003; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec080; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec080; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00690; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1510009; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48208; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10736004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d8002; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006a0; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000a; +} + +static void +Opcode_ae_la16x4_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08209; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10736008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0104; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d8003; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x978300; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee080; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee080; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006b0; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000b; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48209; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514008; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104dc002; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x978340; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0000; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0000; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006e0; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000e; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0820b; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514009; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073600c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104da002; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec0c0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ec0c0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006c0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000c; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0820a; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104da003; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee0c0; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ee0c0; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a006d0; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000d; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c4820a; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193a8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10614004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f6002; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fa040; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fa040; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00880; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512008; +} + +static void +Opcode_ae_la8x8_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c18201; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193e8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f6003; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fc040; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fc040; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00890; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512009; +} + +static void +Opcode_ae_la8x8_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c58201; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193b0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10616004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f8002; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008a0; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200a; +} + +static void +Opcode_ae_la8x8_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c10301; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193f0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10618004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0108; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f8003; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08080; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fe040; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fe040; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008b0; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200b; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c50301; +} + +static void +Opcode_ae_la8x8_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516000; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1061c004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fc002; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa080c0; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4080; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4080; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008e0; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200e; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c10205; +} + +static void +Opcode_ae_la8x8_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516001; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193b8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1061a004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fa002; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0080; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0080; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008c0; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200c; +} + +static void +Opcode_ae_la8x8_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c18301; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193f8030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fa003; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2080; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2080; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008d0; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151200d; +} + +static void +Opcode_ae_la8x8_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c58301; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10602004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e8003; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2000; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f2000; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48201; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ea002; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4000; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f4000; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00301; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10604004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ea003; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x978380; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6000; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f6000; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c40301; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400a; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19380030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10608004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ee002; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9783c0; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fc000; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fc000; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00205; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400b; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10606004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ec002; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f8000; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f8000; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08301; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ec003; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fa000; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6fa000; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48301; +} + +static void +Opcode_ae_la24_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073e004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e2003; +} + +static void +Opcode_ae_la24_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c4830a; +} + +static void +Opcode_ae_la24_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e4002; +} + +static void +Opcode_ae_la24_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0830b; +} + +static void +Opcode_ae_la24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073e008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e4003; +} + +static void +Opcode_ae_la24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c4830b; +} + +static void +Opcode_ae_la24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e8002; +} + +static void +Opcode_ae_la24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08201; +} + +static void +Opcode_ae_la24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073e00c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e6002; +} + +static void +Opcode_ae_la24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00201; +} + +static void +Opcode_ae_la24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8780c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e6003; +} + +static void +Opcode_ae_la24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c40201; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8380f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073c004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104dc003; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c4820b; +} + +static void +Opcode_ae_la24x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d870080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104de002; +} + +static void +Opcode_ae_la24x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08308; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d878080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073c008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104de003; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48308; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8700a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e2002; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0830a; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d870090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1073c00c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e0002; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c08309; +} + +static void +Opcode_ae_la24x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d878090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la24x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e0003; +} + +static void +Opcode_ae_la24x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c48309; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a2004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ee001; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a60; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000d; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f0001; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a70; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000e; +} + +static void +Opcode_ae_sa32x2_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a2008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f2001; +} + +static void +Opcode_ae_sa32x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a80; +} + +static void +Opcode_ae_sa32x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000f; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a200c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f4001; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a90; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010c; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19038010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a6004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fa001; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00ac0; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010f; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a6000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f6001; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00aa0; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010d; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104f8001; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00ab0; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010e; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10620004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fe002; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a008f0; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0000; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fe003; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a00; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0001; +} + +static void +Opcode_ae_sa16x4_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10622004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0001; +} + +static void +Opcode_ae_sa16x4_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a10; +} + +static void +Opcode_ae_sa16x4_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0002; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10624004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c2001; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a20; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0003; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10628004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c8001; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a50; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0102; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10626004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c4001; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a30; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0100; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c6001; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00a40; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0101; +} + +static void +Opcode_ae_sa8x8_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19078010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a6008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fc001; +} + +static void +Opcode_ae_sa8x8_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00ad0; +} + +static void +Opcode_ae_sa8x8_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0200; +} + +static void +Opcode_ae_sa8x8_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190b8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104fe001; +} + +static void +Opcode_ae_sa8x8_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00ae0; +} + +static void +Opcode_ae_sa8x8_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0201; +} + +static void +Opcode_ae_sa8x8_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190f8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ic2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a600c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ic2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0000; +} + +static void +Opcode_ae_sa8x8_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00af0; +} + +static void +Opcode_ae_sa8x8_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0202; +} + +static void +Opcode_ae_sa8x8_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19138010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0001; +} + +static void +Opcode_ae_sa8x8_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00c00; +} + +static void +Opcode_ae_sa8x8_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0203; +} + +static void +Opcode_ae_sa8x8_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191f8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a2000; +} + +static void +Opcode_ae_sa8x8_rip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00c30; +} + +static void +Opcode_ae_sa8x8_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0302; +} + +static void +Opcode_ae_sa8x8_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19178010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0002; +} + +static void +Opcode_ae_sa8x8_ric_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00c10; +} + +static void +Opcode_ae_sa8x8_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0300; +} + +static void +Opcode_ae_sa8x8_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191b8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa8x8_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106a0003; +} + +static void +Opcode_ae_sa8x8_ric1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00c20; +} + +static void +Opcode_ae_sa8x8_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0301; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063a004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e2001; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000b; +} + +static void +Opcode_ae_sa32x2f24_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e4001; +} + +static void +Opcode_ae_sa32x2f24_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0108; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063c004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e6001; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0109; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105a2000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ec001; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000c; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75380b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1063e004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e8001; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010a; +} + +static void +Opcode_ae_sa32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75300c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ea001; +} + +static void +Opcode_ae_sa32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a010b; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530070; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10632004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d6001; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0105; +} + +static void +Opcode_ae_sa24_l_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538070; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d8001; +} + +static void +Opcode_ae_sa24_l_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0106; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10634004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104da001; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0107; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10638004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e0001; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a000a; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10636004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104dc001; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0008; +} + +static void +Opcode_ae_sa24_l_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24_l_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104de001; +} + +static void +Opcode_ae_sa24_l_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0009; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530040; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1062a004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ca001; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0103; +} + +static void +Opcode_ae_sa24x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538040; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104cc001; +} + +static void +Opcode_ae_sa24x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0004; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530050; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1062c004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104ce001; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0005; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538060; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10630004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d4001; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0104; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7538050; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1062e004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d0001; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0006; +} + +static void +Opcode_ae_sa24x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7530060; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sa24x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d2001; +} + +static void +Opcode_ae_sa24x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a0007; +} + +static void +Opcode_ae_addicirc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a00f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addicirc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e04000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addicirc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9838c00; +} + +static void +Opcode_ae_addicirc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1520000; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a12f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6200; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7200; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a5400; +} + +static void +Opcode_ae_addcirc_xc2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1523200; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a0af00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6100; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7100; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a7000; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1523100; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a02f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e6000; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b7000; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a5000; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1523000; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18800f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481900; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983c400; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18840f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481b00; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983e400; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18880f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481c00; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9838800; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18940f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481f00; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983e800; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188c0f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481e00; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983a800; +} + +static void +Opcode_ae_s32ra64s_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18900f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32ra64s_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481d00; +} + +static void +Opcode_ae_s32ra64s_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983c800; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18780f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481400; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9838000; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18781f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481600; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983a000; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187c0b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481500; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983c000; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187c1f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481a00; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983a400; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187c0f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481700; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x983e000; +} + +static void +Opcode_ae_s24ra64s_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187c1b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24ra64s_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481800; +} + +static void +Opcode_ae_s24ra64s_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9838400; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0004; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830203; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0008; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830302; +} + +static void +Opcode_ae_s16x4ra32s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4ra32s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_s16x4ra32s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0000; +} + +static void +Opcode_ae_s16x4ra32s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830202; +} + +static void +Opcode_ae_addbrba32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74fa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addbrba32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1efa000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addbrba32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1be000; +} + +static void +Opcode_ae_addbrba32_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e4000; +} + +static void +Opcode_ae_addbrba32_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b5000; +} + +static void +Opcode_ae_addbrba32_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa02000; +} + +static void +Opcode_ae_addbrba32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9921004; +} + +static void +Opcode_ae_addbrba32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1553000; +} + +static void +Opcode_ae_s32x2_l_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340000; +} + +static void +Opcode_ae_bitswap_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191fd030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bitswap_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0d002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bitswap_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9002; +} + +static void +Opcode_ae_bitswap_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a5000; +} + +static void +Opcode_ae_bitswap_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1597004; +} + +static void +Opcode_ae_mul32js_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32js_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80211420; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32js_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x560020; +} + +static void +Opcode_ae_mul32js_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40b00a1; +} + +static void +Opcode_ae_mul32js_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x510020; +} + +static void +Opcode_ae_mul32js_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c0008; +} + +static void +Opcode_ae_mul32js_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700220; +} + +static void +Opcode_ae_mul32js_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a800; +} + +static void +Opcode_ae_mul32js_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130040; +} + +static void +Opcode_ae_mul32js_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00d0; +} + +static void +Opcode_ae_mul32js_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2c0000; +} + +static void +Opcode_ae_mul32js_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8009e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsub32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsub32s_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000020; +} + +static void +Opcode_ae_addandsub32s_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsub32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9400000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5400000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000026; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsub32js_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsub32js_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_addandsub32js_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; +} + +static void +Opcode_ae_addandsub32js_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_addandsub32js_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_addandsub32js_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsub32js_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8400800; +} + +static void +Opcode_ae_addandsub32js_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5300000; +} + +static void +Opcode_ae_addandsub32js_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000025; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000040; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9400800; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5500000; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000027; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000060; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa400000; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5600000; +} + +static void +Opcode_ae_addandsubrng32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000028; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000080; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa400800; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5700000; +} + +static void +Opcode_ae_addandsubrng32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000029; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addrng32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007860; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subrng32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rng32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40069c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel16i_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82050000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_sel16i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sel16i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_sel16i_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000a0; +} + +static void +Opcode_ae_sel16i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200000; +} + +static void +Opcode_ae_sel16i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700000; +} + +static void +Opcode_ae_sel16i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_sel16i_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c050000; +} + +static void +Opcode_ae_sel16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7420000; +} + +static void +Opcode_ae_sel16i_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40080002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel16i_n_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_sel16i_n_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_sel16i_n_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00380; +} + +static void +Opcode_ae_shortswap_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401d1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movab4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af007; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movab4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a7010; +} + +static void +Opcode_ae_movab2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af006; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movab2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a7000; +} + +static void +Opcode_ae_movab_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movab_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a3002; +} + +static void +Opcode_ae_movba_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movba_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a3001; +} + +static void +Opcode_ae_movba1x2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movba1x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa820000; +} + +static void +Opcode_ae_movba4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af009; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movba4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa862004; +} + +static void +Opcode_ae_movba2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movba2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa822004; +} + +static void +Opcode_ae_movb2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af016; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movb4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af027; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192c0033; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt16x4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt16x4_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132c400; +} + +static void +Opcode_ae_movt16x4_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x124400; +} + +static void +Opcode_ae_movt16x4_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00221; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9832021; +} + +static void +Opcode_ae_movf16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192c0031; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf16x4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf16x4_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132c000; +} + +static void +Opcode_ae_movf16x4_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x124000; +} + +static void +Opcode_ae_movf16x4_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00201; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830021; +} + +static void +Opcode_ae_movt32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800f1; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt32x2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10720010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt32x2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132a000; +} + +static void +Opcode_ae_movt32x2_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120400; +} + +static void +Opcode_ae_movt32x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00021; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7468011; +} + +static void +Opcode_ae_movf32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf32x2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10720000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf32x2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1328000; +} + +static void +Opcode_ae_movf32x2_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ae_movf32x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7468001; +} + +static void +Opcode_ae_movsara7x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9969e04; +} + +static void +Opcode_ae_movsara7x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1523300; +} + +static void +Opcode_ae_movsard7_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19140026; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movsard7_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c401; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movsard7_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1058a0c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movsard7_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069e030; +} + +static void +Opcode_ae_movsard7_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8a6004; +} + +static void +Opcode_ae_movasar_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19036310; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movasar_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c602; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movasar_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71e19e0; +} + +static void +Opcode_ae_movda32x2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198000; +} + +static void +Opcode_ae_movda32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a79000; +} + +static void +Opcode_ae_movda32x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154a000; +} + +static void +Opcode_ae_movda32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7528003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00801; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107820e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0300; +} + +static void +Opcode_ae_movda32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640650; +} + +static void +Opcode_ae_movda32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e1080; +} + +static void +Opcode_ae_movda32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516004; +} + +static void +Opcode_ae_movda16x2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640400; +} + +static void +Opcode_ae_movda16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7526003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda16_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0310e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107800e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda16_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0203; +} + +static void +Opcode_ae_movda16_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640640; +} + +static void +Opcode_ae_movda16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e1060; +} + +static void +Opcode_ae_movda16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d6003; +} + +static void +Opcode_ae_movi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d836080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aa00c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000c; +} + +static void +Opcode_ae_movi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640600; +} + +static void +Opcode_ae_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a1000; +} + +static void +Opcode_ae_movi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1554004; +} + +static void +Opcode_ae_movi_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa400024; +} + +static void +Opcode_ae_movi_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44100003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74b4000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e01d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198100; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a71004; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158a000; +} + +static void +Opcode_ae_sat16x4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000a0; +} + +static void +Opcode_ae_sat16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000026; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03904; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98320e0; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40189002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000022; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03804; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107800c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98300e0; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40181002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19080026; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00802; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9836061; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800026; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401c9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19080022; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107800a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9836021; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800025; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401c1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvta32f24s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191ac030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32f24s_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e4b400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32f24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01708; +} + +static void +Opcode_ae_cvta32f24s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191a6030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32f24s_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e43400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32f24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01308; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1053e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640300; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a71000; +} + +static void +Opcode_ae_cvtp24a16x2_lh_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640100; +} + +static void +Opcode_ae_cvtp24a16x2_hl_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640200; +} + +static void +Opcode_ae_cvtp24a16x2_hh_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640000; +} + +static void +Opcode_ae_truncp24q48x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40098c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d180000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1580000; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81a0300; +} + +static void +Opcode_ae_trunci32x2f64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c280000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunci32x2f64s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10202000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunci32x2f64s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x804000; +} + +static void +Opcode_ae_trunci32x2f64s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1680000; +} + +static void +Opcode_ae_trunca32f64s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d100000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca32f64s_l_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_trunca32f64s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81a0200; +} + +static void +Opcode_ae_trunci32f64s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c200000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunci32f64s_l_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600000; +} + +static void +Opcode_ae_truncp16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401d9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round32x2f64ssym_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80f0000; +} + +static void +Opcode_ae_round32x2f64ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round32x2f64sasym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280400; +} + +static void +Opcode_ae_round32x2f64sasym_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80e8000; +} + +static void +Opcode_ae_round32x2f64sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round32x2f48ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round32x2f48sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round16x4f32ssym_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800090; +} + +static void +Opcode_ae_round16x4f32ssym_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80e0000; +} + +static void +Opcode_ae_round16x4f32ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round16x4f32sasym_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104b0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_round16x4f32sasym_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800080; +} + +static void +Opcode_ae_round16x4f32sasym_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80d8000; +} + +static void +Opcode_ae_round16x4f32sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round24x2f48ssym_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104b8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_round24x2f48ssym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280000; +} + +static void +Opcode_ae_round24x2f48ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round24x2f48sasym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180e00; +} + +static void +Opcode_ae_round24x2f48sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsp16q48x2sym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsp16q48x2asym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_minabs32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_maxabs32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsp16f24sym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80106862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsp16f24asym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mov_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800f; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mov_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160011; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mov_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1904002e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mov_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03b06; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mov_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80f11801; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mov_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780060; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mov_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c010c; +} + +static void +Opcode_ae_mov_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x568000; +} + +static void +Opcode_ae_mov_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40b80a0; +} + +static void +Opcode_ae_mov_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106c0000; +} + +static void +Opcode_ae_mov_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020f; +} + +static void +Opcode_ae_mov_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133ac00; +} + +static void +Opcode_ae_mov_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08100; +} + +static void +Opcode_ae_mov_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x124800; +} + +static void +Opcode_ae_mov_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000020; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mov_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00540; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mov_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000800; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mov_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2880080; +} + +static void +Opcode_ae_mov_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x229860; +} + +static void +Opcode_ae_mov_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25402e0; +} + +static void +Opcode_ae_mov_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00361; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mov_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d15801d; +} + +static void +Opcode_ae_mov_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98340e1; +} + +static void +Opcode_ae_mov_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800024; +} + +static void +Opcode_ae_mov_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401b9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movt64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt64_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1324000; +} + +static void +Opcode_ae_movt64_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c000; +} + +static void +Opcode_ae_movt64_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8b00201; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742a001; +} + +static void +Opcode_ae_movf64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf64_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1320000; +} + +static void +Opcode_ae_movf64_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118000; +} + +static void +Opcode_ae_movf64_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8b00001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movf64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7428001; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7524003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0310c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0202; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e1040; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1596003; +} + +static void +Opcode_ae_cvt48a32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48a32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03108; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48a32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0200; +} + +static void +Opcode_ae_cvt48a32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e1000; +} + +static void +Opcode_ae_cvt48a32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516003; +} + +static void +Opcode_ae_cvt64a32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7522003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt64a32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0310a; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt64a32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0201; +} + +static void +Opcode_ae_cvt64a32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e1020; +} + +static void +Opcode_ae_cvt64a32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556003; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1904002a; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03a06; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98340a1; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401b1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19040026; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03906; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9834061; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401a9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19040022; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03806; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9834021; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401a1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900002e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03b04; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98360e0; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40199002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900002a; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03a04; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98340e0; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40191002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat48s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa158000; +} + +static void +Opcode_ae_sat48s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800f6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_satq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800fe462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800ee462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_truncq32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98360a1; +} + +static void +Opcode_ae_truncq32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401e1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_minabs64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_maxabs64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsq32f48sym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80306862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_roundsq32f48asym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80206862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_trunca32q48_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191f4030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca32q48_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0cc01; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929604; +} + +static void +Opcode_ae_movad32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191e4030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e7b400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a006; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_l_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf000; +} + +static void +Opcode_ae_movad32_l_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069a030; +} + +static void +Opcode_ae_movad32_l_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2986010; +} + +static void +Opcode_ae_movad32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09f08; +} + +static void +Opcode_ae_movad32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191be030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e73400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_h_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad32_h_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10698030; +} + +static void +Opcode_ae_movad32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09b08; +} + +static void +Opcode_ae_movad16_3_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191bc030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_3_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6b400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_3_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_3_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10696030; +} + +static void +Opcode_ae_movad16_3_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09708; +} + +static void +Opcode_ae_movad16_2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191b6030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e63400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071800f; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10694030; +} + +static void +Opcode_ae_movad16_2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09308; +} + +static void +Opcode_ae_movad16_1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191b4030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e5b400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071800e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10692030; +} + +static void +Opcode_ae_movad16_1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01f08; +} + +static void +Opcode_ae_movad16_0_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191ae030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_0_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e53400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_0_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071800b; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad16_0_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690030; +} + +static void +Opcode_ae_movad16_0_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2946010; +} + +static void +Opcode_ae_movad16_0_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01b08; +} + +static void +Opcode_ae_sra64_32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d818000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sra64_32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1000; +} + +static void +Opcode_ae_pksr32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19340032; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6340c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr32_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x55a000; +} + +static void +Opcode_ae_pksr32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c008c; +} + +static void +Opcode_ae_pksr32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17401e0; +} + +static void +Opcode_ae_pksr32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338000; +} + +static void +Opcode_ae_pksr32_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128008; +} + +static void +Opcode_ae_pksr32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830060; +} + +static void +Opcode_ae_pksr32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa200024; +} + +static void +Opcode_ae_pksr24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19340031; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr24_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6320c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr24_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x559000; +} + +static void +Opcode_ae_pksr24_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c001c; +} + +static void +Opcode_ae_pksr24_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17201e0; +} + +static void +Opcode_ae_pksr24_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132e400; +} + +static void +Opcode_ae_pksr24_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128004; +} + +static void +Opcode_ae_pksr24_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa100024; +} + +static void +Opcode_ae_pksrf32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19340033; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksrf32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6360c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksrf32_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x55b000; +} + +static void +Opcode_ae_pksrf32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c009c; +} + +static void +Opcode_ae_pksrf32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17601e0; +} + +static void +Opcode_ae_pksrf32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1338400; +} + +static void +Opcode_ae_pksrf32_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12800c; +} + +static void +Opcode_ae_pksrf32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98300a0; +} + +static void +Opcode_ae_pksrf32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa300024; +} + +static void +Opcode_ae_pksr16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19340030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6300c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_pksr16_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x558000; +} + +static void +Opcode_ae_pksr16_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c000c; +} + +static void +Opcode_ae_pksr16_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17001e0; +} + +static void +Opcode_ae_pksr16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132e000; +} + +static void +Opcode_ae_pksr16_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128000; +} + +static void +Opcode_ae_pksr16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830020; +} + +static void +Opcode_ae_pksr16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000024; +} + +static void +Opcode_ae_trunca16p24s_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a00b; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929204; +} + +static void +Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929c04; +} + +static void +Opcode_ae_add32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480000; +} + +static void +Opcode_ae_add32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89a0c00; +} + +static void +Opcode_ae_add32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8038000; +} + +static void +Opcode_ae_add32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005c60; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18500b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280600; +} + +static void +Opcode_ae_sub32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8110000; +} + +static void +Opcode_ae_sub32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addsub32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18100b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addsub32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080200; +} + +static void +Opcode_ae_addsub32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8070000; +} + +static void +Opcode_ae_addsub32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subadd32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18680b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subadd32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380c00; +} + +static void +Opcode_ae_subadd32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8130000; +} + +static void +Opcode_ae_subadd32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88a0800; +} + +static void +Opcode_ae_add16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8020000; +} + +static void +Opcode_ae_add16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18400f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280800; +} + +static void +Opcode_ae_sub16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80f8000; +} + +static void +Opcode_ae_sub16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ba0800; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8050000; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006860; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addsub32_hl_lh_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18180f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addsub32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8088000; +} + +static void +Opcode_ae_addsub32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f30; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0220; +} + +static void +Opcode_ae_neg32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2d8000; +} + +static void +Opcode_ae_neg32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800b6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f60; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738090; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0060; +} + +static void +Opcode_ae_abs32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3e8000; +} + +static void +Opcode_ae_abs32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8003e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg32_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2e8000; +} + +static void +Opcode_ae_neg32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800c6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89a0800; +} + +static void +Opcode_ae_add24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8030000; +} + +static void +Opcode_ae_add24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005860; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18480f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280200; +} + +static void +Opcode_ae_sub24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8108000; +} + +static void +Opcode_ae_sub24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10498000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add32s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480400; +} + +static void +Opcode_ae_add32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002400; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_add32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8aa0800; +} + +static void +Opcode_ae_add32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8040000; +} + +static void +Opcode_ae_add32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18500f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_sub32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280a00; +} + +static void +Opcode_ae_sub32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8118000; +} + +static void +Opcode_ae_sub32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addsub32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18100f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addsub32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080600; +} + +static void +Opcode_ae_addsub32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8078000; +} + +static void +Opcode_ae_addsub32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subadd32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18680f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subadd32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380200; +} + +static void +Opcode_ae_subadd32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8138000; +} + +static void +Opcode_ae_subadd32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004062; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10490000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add16s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_add16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88a0c00; +} + +static void +Opcode_ae_add16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8028000; +} + +static void +Opcode_ae_add16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005460; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18480b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104c0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub16s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002c00; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_sub16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280c00; +} + +static void +Opcode_ae_sub16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8100000; +} + +static void +Opcode_ae_sub16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002062; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8aa0c00; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8048000; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006460; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addsub32s_hl_lh_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18180b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addsub32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8080000; +} + +static void +Opcode_ae_addsub32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f20; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg24s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107380f0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0200; +} + +static void +Opcode_ae_neg24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2d0000; +} + +static void +Opcode_ae_neg24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800ae462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f50; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs24s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738050; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0040; +} + +static void +Opcode_ae_abs24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3c8000; +} + +static void +Opcode_ae_abs24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80036462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f40; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780040; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003860; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_neg32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0240; +} + +static void +Opcode_ae_neg32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2e0000; +} + +static void +Opcode_ae_neg32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800be462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f70; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107380d0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003c00; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_abs32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0080; +} + +static void +Opcode_ae_abs32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa390000; +} + +static void +Opcode_ae_abs32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80046462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f10; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107380b0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg16s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003c40; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_neg16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00f0; +} + +static void +Opcode_ae_neg16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2c8000; +} + +static void +Opcode_ae_neg16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800a6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f40; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs16s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80211400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs16s_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x560000; +} + +static void +Opcode_ae_abs16s_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40b00a0; +} + +static void +Opcode_ae_abs16s_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x510000; +} + +static void +Opcode_ae_abs16s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003800; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_abs16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0020; +} + +static void +Opcode_ae_abs16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3a8000; +} + +static void +Opcode_ae_abs16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8002e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f30; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0000; +} + +static void +Opcode_ae_abs16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa388000; +} + +static void +Opcode_ae_abs16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80026462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16js_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc16js_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b001c0; +} + +static void +Opcode_ae_mulc16js_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16js_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc16js_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b001e0; +} + +static void +Opcode_ae_mulc16js_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16js_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac16js_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f003c0; +} + +static void +Opcode_ae_mulac16js_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16js_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac16js_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f003e0; +} + +static void +Opcode_ae_mulac16js_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_lt16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880009; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10740300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340014; +} + +static void +Opcode_ae_lt16_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400e0; +} + +static void +Opcode_ae_lt16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2a00; +} + +static void +Opcode_ae_le16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880205; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10749300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1348013; +} + +static void +Opcode_ae_le16_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25403c0; +} + +static void +Opcode_ae_le16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022e00; +} + +static void +Opcode_ae_eq16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880005; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10749100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340013; +} + +static void +Opcode_ae_eq16_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25401c0; +} + +static void +Opcode_ae_eq16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022a00; +} + +static void +Opcode_ae_lt32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10749000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340012; +} + +static void +Opcode_ae_lt32_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400c0; +} + +static void +Opcode_ae_lt32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022800; +} + +static void +Opcode_ae_le32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d88010e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10741100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340011; +} + +static void +Opcode_ae_le32_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25001e0; +} + +static void +Opcode_ae_le32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022400; +} + +static void +Opcode_ae_eq32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d88000e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10741000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1340010; +} + +static void +Opcode_ae_eq32_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000e0; +} + +static void +Opcode_ae_eq32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022000; +} + +static void +Opcode_ae_min32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18300f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0110080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104a8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min32_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_ae_min32_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40a00a0; +} + +static void +Opcode_ae_min32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180c00; +} + +static void +Opcode_ae_min32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80b0000; +} + +static void +Opcode_ae_min32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_max32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18200f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0110020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104a0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max32_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x528000; +} + +static void +Opcode_ae_max32_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40880a0; +} + +static void +Opcode_ae_max32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080e00; +} + +static void +Opcode_ae_max32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8098000; +} + +static void +Opcode_ae_max32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_minmax32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80c8000; +} + +static void +Opcode_ae_minmax32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_minmax16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80c0000; +} + +static void +Opcode_ae_minmax16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_min16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18300b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0110060; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min16_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x538000; +} + +static void +Opcode_ae_min16_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40980a0; +} + +static void +Opcode_ae_min16_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x508000; +} + +static void +Opcode_ae_min16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180800; +} + +static void +Opcode_ae_min16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a8000; +} + +static void +Opcode_ae_min16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_max16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18200b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0110000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max16_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x520000; +} + +static void +Opcode_ae_max16_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40800a0; +} + +static void +Opcode_ae_max16_Slot_ae4_slot4_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_max16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080a00; +} + +static void +Opcode_ae_max16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8090000; +} + +static void +Opcode_ae_max16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ba0c00; +} + +static void +Opcode_ae_add64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8058000; +} + +static void +Opcode_ae_add64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006c60; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18580b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7280e00; +} + +static void +Opcode_ae_sub64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8120000; +} + +static void +Opcode_ae_sub64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003062; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f50; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10780080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0260; +} + +static void +Opcode_ae_neg64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2f0000; +} + +static void +Opcode_ae_neg64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800ce462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f80; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00a0; +} + +static void +Opcode_ae_abs64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa398000; +} + +static void +Opcode_ae_abs64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8004e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addsq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18080f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addsq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080c00; +} + +static void +Opcode_ae_addsq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8068000; +} + +static void +Opcode_ae_addsq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007c60; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subsq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18700b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subsq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380600; +} + +static void +Opcode_ae_subsq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8140000; +} + +static void +Opcode_ae_subsq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080000; +} + +static void +Opcode_ae_add64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8060000; +} + +static void +Opcode_ae_add64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18580f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380000; +} + +static void +Opcode_ae_sub64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8128000; +} + +static void +Opcode_ae_sub64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_negsq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f80; + slotbuf[1] = 0; +} + +static void +Opcode_ae_negsq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a02c0; +} + +static void +Opcode_ae_negsq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa058000; +} + +static void +Opcode_ae_negsq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800e6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abssq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80fc0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0030; +} + +static void +Opcode_ae_abssq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3b8000; +} + +static void +Opcode_ae_abssq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80066462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f60; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0280; +} + +static void +Opcode_ae_neg64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2f8000; +} + +static void +Opcode_ae_neg64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800d6462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_abs64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f90; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00c0; +} + +static void +Opcode_ae_abs64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3b0000; +} + +static void +Opcode_ae_abs64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80056462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_and_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880020; + slotbuf[1] = 0; +} + +static void +Opcode_ae_and_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7428000; +} + +static void +Opcode_ae_and_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40080c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_nand_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nand_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742a000; +} + +static void +Opcode_ae_nand_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40088c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_or_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880040; + slotbuf[1] = 0; +} + +static void +Opcode_ae_or_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104d8000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742c000; +} + +static void +Opcode_ae_or_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40090c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_xor_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880050; + slotbuf[1] = 0; +} + +static void +Opcode_ae_xor_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104e0000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742e000; +} + +static void +Opcode_ae_xor_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400a0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slai24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c800000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8424003; +} + +static void +Opcode_ae_slai24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40006003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srli24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c810000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srli24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842400b; +} + +static void +Opcode_ae_srli24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c808000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8424007; +} + +static void +Opcode_ae_srai24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40007403; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19238010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c18205; +} + +static void +Opcode_ae_slas24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42080c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srls24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193b8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srls24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04308; +} + +static void +Opcode_ae_srls24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420e0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sras24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19338010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sras24_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500d01; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sras24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c18305; +} + +static void +Opcode_ae_sras24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420c0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c820000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1204; +} + +static void +Opcode_ae_srai16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42080803; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai16r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c822000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai16r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1304; +} + +static void +Opcode_ae_srai16r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slai32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c804000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842c003; +} + +static void +Opcode_ae_slai32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40006803; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srli32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c812000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srli32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842600b; +} + +static void +Opcode_ae_srli32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000403; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8426007; +} + +static void +Opcode_ae_srai32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40007803; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai32r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842c007; +} + +static void +Opcode_ae_srai32r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40007c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1923c010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1c205; +} + +static void +Opcode_ae_slas32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42090c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srls32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193ba010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srls32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c06308; +} + +static void +Opcode_ae_srls32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420e8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sras32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1933a010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sras32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1a305; +} + +static void +Opcode_ae_sras32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420c8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaa32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d814000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8208; +} + +static void +Opcode_ae_srla32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c828000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1008; +} + +static void +Opcode_ae_sraa32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1200; +} + +static void +Opcode_ae_slai16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c81e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a830c; +} + +static void +Opcode_ae_slai16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000803; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaa16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c816000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8108; +} + +static void +Opcode_ae_sraa16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d81c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa16s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9000; +} + +static void +Opcode_ae_sraa16rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d81a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa16rs_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500600; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa16rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1100; +} + +static void +Opcode_ae_slai24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c802000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8426003; +} + +static void +Opcode_ae_slai24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40006403; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1923a010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas24s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1a205; +} + +static void +Opcode_ae_slas24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42088c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slai32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c806000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842e003; +} + +static void +Opcode_ae_slai32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40006c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1923e010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1e205; +} + +static void +Opcode_ae_slas32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42098c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaa32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d816000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8308; +} + +static void +Opcode_ae_sraa32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x748c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa32s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9200; +} + +static void +Opcode_ae_sraa32rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa32rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1300; +} + +static void +Opcode_ae_slasq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192bc010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c14305; +} + +static void +Opcode_ae_slasq56_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420b0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srlsq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193be010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c06309; +} + +static void +Opcode_ae_srlsq56_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420f8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srasq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1933e010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1e305; +} + +static void +Opcode_ae_srasq56_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420d8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaaq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c818000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaaq56_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a020c; +} + +static void +Opcode_ae_srlaq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c82e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9108; +} + +static void +Opcode_ae_sraaq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x758e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraaq56_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9104; +} + +static void +Opcode_ae_slai64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a0000; +} + +static void +Opcode_ae_slai64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srli64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7408000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srli64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a0008; +} + +static void +Opcode_ae_srli64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40004003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srai64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7406000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8004; +} + +static void +Opcode_ae_srai64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4001a003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192b8010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c10305; +} + +static void +Opcode_ae_slas64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420a0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_srls64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193bc010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srls64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04309; +} + +static void +Opcode_ae_srls64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420f0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sras64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1933c010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sras64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c1c305; +} + +static void +Opcode_ae_sras64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420d0c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaa64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a000c; +} + +static void +Opcode_ae_srla64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c82a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1108; +} + +static void +Opcode_ae_sraa64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1004; +} + +static void +Opcode_ae_slaisq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7404000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a0004; +} + +static void +Opcode_ae_slaisq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40012003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slassq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192be010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slassq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c16305; +} + +static void +Opcode_ae_slassq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420b8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaasq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c81a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaasq56s_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a030c; +} + +static void +Opcode_ae_slai64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7402000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8000; +} + +static void +Opcode_ae_slai64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000a003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slas64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192ba010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slas64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c12305; +} + +static void +Opcode_ae_slas64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420a8c03; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slaa64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x748a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a010c; +} + +static void +Opcode_ae_lt64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt64_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1310000; +} + +static void +Opcode_ae_lt64_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000c0; +} + +static void +Opcode_ae_lt64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6202000; +} + +static void +Opcode_ae_le64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le64_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300010; +} + +static void +Opcode_ae_le64_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000a0; +} + +static void +Opcode_ae_le64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6102000; +} + +static void +Opcode_ae_eq64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq64_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ae_eq64_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500080; +} + +static void +Opcode_ae_eq64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002000; +} + +static void +Opcode_ae_max64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18280b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180000; +} + +static void +Opcode_ae_max64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_min64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18380b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180200; +} + +static void +Opcode_ae_min64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_nsa64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191e6030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsa64_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0c001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsa64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929004; +} + +static void +Opcode_ae_nsaz16_0_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191ec030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz16_0_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0c401; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz16_0_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a007; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz16_0_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929404; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191ee030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0c801; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a00a; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929804; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca004800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200280; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d001a0; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce001c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100140; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72001a0; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002a0; +} + +static void +Opcode_ae_mul32_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00260; +} + +static void +Opcode_ae_mul32_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88d00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8001c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000e0; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71001c0; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32ra_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca001800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32ra_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70001e0; +} + +static void +Opcode_ae_mulf32ra_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8004800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200260; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d00180; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc001c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100120; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7200180; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00280; +} + +static void +Opcode_ae_mul32_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00240; +} + +static void +Opcode_ae_mul32_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ec00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce001800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000c0; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71001a0; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32ra_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8001800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32ra_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70001c0; +} + +static void +Opcode_ae_mulf32ra_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce004400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200240; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c001e0; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca001c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100100; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71001e0; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00260; +} + +static void +Opcode_ae_mul32_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00220; +} + +static void +Opcode_ae_mul32_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8cc00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc001800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000a0; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7100180; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32ra_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce001400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32ra_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70001a0; +} + +static void +Opcode_ae_mulf32ra_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000240; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68001a0; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8bf00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00160; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7900160; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f500040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6003400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000e0; +} + +static void +Opcode_ae_mula32_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f000a0; +} + +static void +Opcode_ae_mula32_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00100; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7600160; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89500040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32ra_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32ra_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7300160; +} + +static void +Opcode_ae_mulaf32ra_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000220; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800180; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89f00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00140; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7800160; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d500040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6003000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000c0; +} + +static void +Opcode_ae_mula32_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00080; +} + +static void +Opcode_ae_mula32_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000e0; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7500160; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32ra_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32ra_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7200160; +} + +static void +Opcode_ae_mulaf32ra_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000200; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67001e0; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8fe00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00120; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7700160; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b500040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6002c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000a0; +} + +static void +Opcode_ae_mula32_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00060; +} + +static void +Opcode_ae_mula32_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000c0; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400160; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32ra_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32ra_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7100160; +} + +static void +Opcode_ae_mulaf32ra_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f300040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14002a0; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400280; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc006800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300240; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200220; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca005800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300080; +} + +static void +Opcode_ae_muls32_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60002a0; +} + +static void +Opcode_ae_muls32_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce006400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13001e0; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61003c0; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32ra_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8006400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32ra_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100360; +} + +static void +Opcode_ae_mulsf32ra_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400280; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400260; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca006800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300220; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200200; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8005800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300060; +} + +static void +Opcode_ae_muls32_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000280; +} + +static void +Opcode_ae_muls32_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc006400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13001c0; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61003a0; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32ra_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32ra_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100340; +} + +static void +Opcode_ae_mulsf32ra_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400260; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400240; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8006800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300200; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61003e0; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce005400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300040; +} + +static void +Opcode_ae_muls32_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000260; +} + +static void +Opcode_ae_muls32_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca006400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13001a0; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100380; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32ra_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32ra_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100320; +} + +static void +Opcode_ae_mulsf32ra_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32u_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32u_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00140; +} + +static void +Opcode_ae_mul32u_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00100; +} + +static void +Opcode_ae_mula32u_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32u_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00380; +} + +static void +Opcode_ae_mula32u_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00340; +} + +static void +Opcode_ae_muls32u_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc004c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32u_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200320; +} + +static void +Opcode_ae_muls32u_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e001c0; +} + +static void +Opcode_ae_mulf16ss_33_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000180; +} + +static void +Opcode_ae_mulf16ss_33_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f00180; +} + +static void +Opcode_ae_mulf16ss_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f001e0; +} + +static void +Opcode_ae_mulf16ss_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_21_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e001e0; +} + +static void +Opcode_ae_mulf16ss_21_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_31_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f001c0; +} + +static void +Opcode_ae_mulf16ss_31_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_30_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f001a0; +} + +static void +Opcode_ae_mulf16ss_30_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e00180; +} + +static void +Opcode_ae_mulf16ss_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_20_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e001c0; +} + +static void +Opcode_ae_mulf16ss_20_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_11_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e001a0; +} + +static void +Opcode_ae_mulf16ss_11_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc001400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100080; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d001e0; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_33_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100300; +} + +static void +Opcode_ae_mulsf16ss_33_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100280; +} + +static void +Opcode_ae_mulsf16ss_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61002e0; +} + +static void +Opcode_ae_mulsf16ss_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_21_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100260; +} + +static void +Opcode_ae_mulsf16ss_21_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_31_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61002c0; +} + +static void +Opcode_ae_mulsf16ss_31_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_30_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61002a0; +} + +static void +Opcode_ae_mulsf16ss_30_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100200; +} + +static void +Opcode_ae_mulsf16ss_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_20_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100240; +} + +static void +Opcode_ae_mulsf16ss_20_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_11_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100220; +} + +static void +Opcode_ae_mulsf16ss_11_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300180; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60003e0; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_33_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000160; +} + +static void +Opcode_ae_mulaf16ss_33_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d300040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c00160; +} + +static void +Opcode_ae_mulaf16ss_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d200040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f00160; +} + +static void +Opcode_ae_mulaf16ss_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b300040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_21_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b00160; +} + +static void +Opcode_ae_mulaf16ss_21_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b200040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_31_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e00160; +} + +static void +Opcode_ae_mulaf16ss_31_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89300040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_30_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d00160; +} + +static void +Opcode_ae_mulaf16ss_30_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f200040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800160; +} + +static void +Opcode_ae_mulaf16ss_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d100040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_20_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a00160; +} + +static void +Opcode_ae_mulaf16ss_20_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89200040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_11_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900160; +} + +static void +Opcode_ae_mulaf16ss_11_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f100040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000a0; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700160; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b100040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul16s_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul16s_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00080; +} + +static void +Opcode_ae_mul16s_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00040; +} + +static void +Opcode_ae_mul16s_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula16s_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula16s_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002c0; +} + +static void +Opcode_ae_mula16s_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00280; +} + +static void +Opcode_ae_mula16s_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ad00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls16s_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc004400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls16s_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200220; +} + +static void +Opcode_ae_muls16s_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c001c0; +} + +static void +Opcode_ae_muls16s_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6006c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002a0; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00260; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6006800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00280; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00240; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6006400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00260; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00220; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14003c0; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64003a0; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14003a0; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400380; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400380; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400360; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500280; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600260; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500260; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600240; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500240; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600220; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600380; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68003a0; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600360; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800380; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600340; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800360; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8002800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100260; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74001c0; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca002800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100280; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74001e0; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8004400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12001e0; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c00180; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca004400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200200; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c001a0; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00280; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60001c0; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002a0; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60001e0; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10001c0; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67001a0; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8be00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10001e0; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67001c0; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8de00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce007000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300360; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200340; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8007400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300380; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200360; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14001e0; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63003c0; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400200; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63003e0; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce003000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11003c0; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77001e0; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc003000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11003a0; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77001c0; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf003a0; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300180; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8da00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00380; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62001e0; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ba00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc007400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13003c0; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62003a0; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca007400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13003a0; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200380; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500320; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600300; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15002e0; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66002c0; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500200; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65003e0; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500340; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600320; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500300; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66002e0; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500220; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600200; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000e0; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67002c0; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000a0; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700280; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600060; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700240; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600100; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67002e0; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000c0; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67002a0; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600080; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700260; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16001e0; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800200; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16001c0; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67003e0; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16001a0; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67003c0; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700020; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900240; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003e0; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900200; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600300; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800320; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700040; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900260; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700000; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900220; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600320; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800340; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00340; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00300; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6007800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00300; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f002c0; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6005c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00220; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f001e0; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00360; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00320; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6007c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00320; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f002e0; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00240; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00200; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900200; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000360; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a001c0; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000320; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12600020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a00180; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10002e0; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69001c0; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000380; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a001e0; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000340; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12700020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a001a0; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000300; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69001e0; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc005c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300120; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000380; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca005c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300100; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12600040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000360; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8005c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000e0; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000340; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500060; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500240; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500020; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x169000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12700040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500200; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400340; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400320; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500080; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500260; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500040; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x169000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12600060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500220; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400360; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400340; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8002400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11001e0; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73001c0; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd001e0; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e001a0; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8cb00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca002400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100200; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73001e0; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00200; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e001c0; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8eb00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc002400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100220; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400180; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00220; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e001e0; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88c00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce002400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100240; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74001a0; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00240; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00200; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ac00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100160; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72001c0; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00160; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00120; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100180; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72001e0; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00180; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00140; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11001a0; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7300180; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd001a0; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00160; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ca00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11001c0; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73001a0; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd001c0; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00180; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ea00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00200; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e00160; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89700040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6001c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00020; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e003e0; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ef00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00220; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f00160; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b700040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00040; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00000; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00240; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000180; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d700040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6002400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00060; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00020; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00260; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60001a0; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f700040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6002800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00080; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00040; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00180; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a00160; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89600040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd003a0; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00360; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ee00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf001a0; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b00160; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b600040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6001000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd003c0; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00380; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88f00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf001c0; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c00160; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d600040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6001400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd003e0; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e003a0; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8af00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf001e0; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d00160; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f600040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6001800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e003c0; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8cf00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce006c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13002e0; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62002c0; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce005000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12003c0; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f001e0; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8007000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300300; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62002e0; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8005400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12003e0; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000200; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca007000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300320; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200300; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca005400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000220; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc007000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300340; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200320; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b001e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc005400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300020; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000240; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce006800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300260; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200240; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce004c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200340; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e001e0; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8006c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300280; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200260; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8005000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200360; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f00180; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca006c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13002a0; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200280; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca005000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200380; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f001a0; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc006c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13002c0; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62002a0; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc005000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12003a0; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f001c0; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe003e0; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f003a0; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6005800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00200; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f001c0; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159001c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe003a0; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00360; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6005000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe001c0; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00180; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900180; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10003c0; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b001a0; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10002c0; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69001a0; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10003a0; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b00180; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10002a0; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900180; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300160; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60003c0; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000320; +} + +static void +Opcode_ae_mulsad32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce005c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300140; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60003a0; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000300; +} + +static void +Opcode_ae_mulsad32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000c0; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65002a0; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400320; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400300; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000a0; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500280; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400300; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64002e0; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15003c0; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66003a0; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15001e0; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65003c0; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500380; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600360; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15001a0; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500380; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600140; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700320; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600040; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700220; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600120; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700300; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600020; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700200; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600220; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800240; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67003a0; +} + +static void +Opcode_ae_mulzsad32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600200; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800220; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700380; +} + +static void +Opcode_ae_mulzsad32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700080; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69002a0; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002e0; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800300; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700060; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900280; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c000a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002c0; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68002e0; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15003a0; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600380; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500360; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600340; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe003c0; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00380; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00380; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00340; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15001c0; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65003a0; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500180; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500360; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6005400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe001e0; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f001a0; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159001a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6004c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe001a0; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00160; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900160; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200160; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b00180; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc003400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200020; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78001c0; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8003400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11003e0; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7800180; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8003800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200060; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7900180; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200180; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b001a0; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce003400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200040; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78001e0; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b003a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca003400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78001a0; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00380; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca003800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200080; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x79001a0; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000140; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66001a0; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8dd00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63001e0; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8bb00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf003c0; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63001a0; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8fa00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000040; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64001a0; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8fb00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000160; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66001c0; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8fd00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000020; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400180; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8db00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf003e0; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63001c0; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89b00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000060; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64001c0; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89c00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400160; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300340; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca007800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400020; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300200; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce007400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13003e0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62003c0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce007800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400060; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300240; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400180; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300360; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc007800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400040; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300220; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8007800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62003e0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900220; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8007c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400080; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300260; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulp32x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp32x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12001a0; +} + +static void +Opcode_ae_mulp32x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b001c0; +} + +static void +Opcode_ae_mulp32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce003800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000c0; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x79001e0; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc003800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000a0; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x79001c0; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a003e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x2ts_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8003c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp32x2ts_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000e0; +} + +static void +Opcode_ae_mulfp32x2ts_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a00180; +} + +static void +Opcode_ae_mulp32x2t_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp32x2t_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12001c0; +} + +static void +Opcode_ae_mulp32x2t_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b001e0; +} + +static void +Opcode_ae_mulap32x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap32x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000180; +} + +static void +Opcode_ae_mulap32x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66001e0; +} + +static void +Opcode_ae_mulap32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89e00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000a0; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500180; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8dc00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000080; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64001e0; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8bc00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x2ts_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafp32x2ts_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000c0; +} + +static void +Opcode_ae_mulafp32x2ts_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65001a0; +} + +static void +Opcode_ae_mulap32x2t_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap32x2t_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10001a0; +} + +static void +Opcode_ae_mulap32x2t_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700180; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14001a0; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300380; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc007c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000c0; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63002a0; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca007c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000a0; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300280; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00240; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x2ts_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce007c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsfp32x2ts_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000e0; +} + +static void +Opcode_ae_mulsfp32x2ts_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63002c0; +} + +static void +Opcode_ae_mulsp32x2t_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp32x2t_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14001c0; +} + +static void +Opcode_ae_mulsp32x2t_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63003a0; +} + +static void +Opcode_ae_mulfp16x4s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100380; +} + +static void +Opcode_ae_mulfp16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77001a0; +} + +static void +Opcode_ae_mulfp16x4ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76001e0; +} + +static void +Opcode_ae_mulc32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc001000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_mulc32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c001e0; +} + +static void +Opcode_ae_mulc32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce002800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11002a0; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75001a0; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8002c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x550000; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11002c0; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75001c0; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc32x16_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8001400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc32x16_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100040; +} + +static void +Opcode_ae_mulc32x16_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d001a0; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc002c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100300; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7600180; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc32x16_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce001000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc32x16_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100020; +} + +static void +Opcode_ae_mulc32x16_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d00180; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca002c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11002e0; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108000; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75001e0; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00020; +} + +static void +Opcode_ae_mulac32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300160; +} + +static void +Opcode_ae_mulac32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002c0; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61001a0; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002e0; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61001c0; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32x16_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac32x16_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00060; +} + +static void +Opcode_ae_mulac32x16_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500160; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00320; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200180; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32x16_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac32x16_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00040; +} + +static void +Opcode_ae_mulac32x16_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400160; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00300; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61001e0; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf16x4ss_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf16x4ss_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf16x4ss_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul16x4s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_mul16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4100000; +} + +static void +Opcode_ae_mul16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4300000; +} + +static void +Opcode_ae_mula16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f00000; +} + +static void +Opcode_ae_muls16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul16x4_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mul16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; +} + +static void +Opcode_ae_mul16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4200000; +} + +static void +Opcode_ae_mula16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e00000; +} + +static void +Opcode_ae_muls16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfd32x2s_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2s_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2s_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2s_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2s_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2s_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x2ra_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2s_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x2ra_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulc16s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8001000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc16s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c001a0; +} + +static void +Opcode_ae_mulc16s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca001000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c001c0; +} + +static void +Opcode_ae_mulc16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac16s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100160; +} + +static void +Opcode_ae_mulac16s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6200160; +} + +static void +Opcode_ae_mulac16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc16ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc002800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc16ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7500180; +} + +static void +Opcode_ae_mulfc16ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a002e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc16ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc16ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6100180; +} + +static void +Opcode_ae_mulafc16ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul16js_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80ff0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul16js_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80096462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1910002e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133b000; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98360e1; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa00026; +} + +static void +Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40069462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19140022; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133b400; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18008000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x746a001; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa00027; +} + +static void +Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40069862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_conj16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_3_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_3_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_2_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_1_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_1_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_0_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_0_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfq16x2_fir_0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafq16x2_fir_3_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_3_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_2_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_1_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_1_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_0_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_0_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafq16x2_fir_0_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzaaaafq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaafq32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaafq32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaafq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaafq32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaafq32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaaq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaaq32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaaq32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaaq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaaq32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaaq32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul16_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul16_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd000a0; +} + +static void +Opcode_ae_mul16_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00060; +} + +static void +Opcode_ae_mul16_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula16_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula16_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002e0; +} + +static void +Opcode_ae_mula16_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e002a0; +} + +static void +Opcode_ae_mula16_00_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8cd00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500120; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500300; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00140; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00100; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_div64d32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0090; +} + +static void +Opcode_ae_div64d32_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3f0000; +} + +static void +Opcode_ae_div64d32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80086462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_div64d32_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10738070; + slotbuf[1] = 0; +} + +static void +Opcode_ae_div64d32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00b0; +} + +static void +Opcode_ae_div64d32_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3f8000; +} + +static void +Opcode_ae_div64d32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8008e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sha32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074cb00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl32t_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl16t_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10557000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl16c_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105872c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl16c_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10587ac0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl16c_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105876c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vldl16c_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d030; +} + +static void +Opcode_ae_vldsht_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105afa0b; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071a00f; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lb_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8010; +} + +static void +Opcode_ae_lb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a3001; +} + +static void +Opcode_ae_lb_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1521010; +} + +static void +Opcode_ae_lbi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lbi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9001; +} + +static void +Opcode_ae_lbi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a3003; +} + +static void +Opcode_ae_lbi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d6004; +} + +static void +Opcode_ae_lbk_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1054a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lbk_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8000; +} + +static void +Opcode_ae_lbki_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10563000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lbs_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1071b00e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lbsi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af005; + slotbuf[1] = 0; +} + +static void +Opcode_ae_db_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_db_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929e04; +} + +static void +Opcode_ae_dbi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10748b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dbi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c09b0c; +} + +static void +Opcode_ae_db_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dbi_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10748f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_db_ic1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dbi_ic1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074ab00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_db_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aed00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dbi_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1074af00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_ardecnorm16_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1065f000; +} + +static void +Opcode_ae_lbki_dbi_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10430000; +} + +static void +Opcode_ae_lbki_dbi_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10440000; +} + +static void +Opcode_ae_lbki_dbi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10420000; +} + +static void +Opcode_ae_lbi_dbi_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680400; +} + +static void +Opcode_ae_lbi_dbi_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680500; +} + +static void +Opcode_ae_lbi_dbi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680300; +} + +static void +Opcode_ae_lbk_db_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10390000; +} + +static void +Opcode_ae_lbk_db_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103a0000; +} + +static void +Opcode_ae_lbk_db_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10380000; +} + +static void +Opcode_ae_lb_db_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680100; +} + +static void +Opcode_ae_lb_db_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680200; +} + +static void +Opcode_ae_lb_db_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680000; +} + +static void +Opcode_ae_vlel32t_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vlel16t_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1055b000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1072f000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vles16c_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10587ec0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbf_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105871c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sb_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105ae700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbi_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10552000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vles16c_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105873c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbf_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105875c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sb_ic1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aeb00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbi_ic1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10553000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vles16c_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1069d130; +} + +static void +Opcode_ae_sbf_ic1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105879c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sb_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105aef00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbi_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10556000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_vles16c_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105877c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sbf_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10587dc0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sext32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40081002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movae_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105af209; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movae_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf400; +} + +static void +Opcode_ae_movea_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105870c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movea_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf440; +} + +static void +Opcode_ae_moveep_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00426; +} + +static void +Opcode_ae_moveep_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80406862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sext72_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa480000; +} + +static void +Opcode_ae_add72_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa080000; +} + +static void +Opcode_ae_sub72_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa180000; +} + +static void +Opcode_ae_add72x64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa280000; +} + +static void +Opcode_ae_sub72x64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2a0000; +} + +static void +Opcode_ae_mul32ep_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00100; +} + +static void +Opcode_ae_mul32ep_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32ep_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00280; +} + +static void +Opcode_ae_mula32ep_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32ep_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00100; +} + +static void +Opcode_ae_muls32ep_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00200; +} + +static void +Opcode_ae_mulzaad32ep_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00300; +} + +static void +Opcode_ae_mulzssd32ep_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00000; +} + +static void +Opcode_ae_mulaad32ep_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00180; +} + +static void +Opcode_ae_mulssd32ep_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32usep_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00080; +} + +static void +Opcode_ae_mulaad32usep_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32usep_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d00280; +} + +static void +Opcode_ae_mulzaad32usep_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e400040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32usep_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00180; +} + +static void +Opcode_ae_mula32usep_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00300; +} + +static void +Opcode_ae_mul32usep_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00200; +} + +static void +Opcode_ae_mula32usep_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00380; +} + +static void +Opcode_ae_srai72_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_slai72_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40007003; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa380000; +} + +static void +Opcode_ae_sat64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_l16si_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200d; +} + +static void +Opcode_ae_l16ui_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400d; +} + +static void +Opcode_ae_s16i_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600d; +} + +static void +Opcode_ae_lalign128_i_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc14000; +} + +static void +Opcode_ae_lalign128_i_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1416000; +} + +static void +Opcode_ae_lalign128_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lalign128_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lalign128_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680080; +} + +static void +Opcode_ae_lalign128_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680080; +} + +static void +Opcode_ae_lalign128_i_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00e00; +} + +static void +Opcode_ae_lalign128_i_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1514000; +} + +static void +Opcode_ae_lalign128_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000400; +} + +static void +Opcode_ae_lalign128_i_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1518000; +} + +static void +Opcode_ae_lalign128_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9839c00; +} + +static void +Opcode_ae_lalign128_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142000c; +} + +static void +Opcode_ae_salign128_i_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000600; +} + +static void +Opcode_ae_salign128_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a9000; +} + +static void +Opcode_ae_la128_pp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa08140; +} + +static void +Opcode_ae_la128_pp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142010c; +} + +static void +Opcode_ae_sa128pos_fp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3002490; +} + +static void +Opcode_ae_sa128pos_fp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa826004; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc12000; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1414008; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193a0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00860; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512006; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2804010; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516008; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c10201; +} + +static void +Opcode_ae_la8x4s_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400e; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc12010; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1414009; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193e0030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03802; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00870; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1512007; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2806010; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1516009; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c50201; +} + +static void +Opcode_ae_la8x4u_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151400f; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00080; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300008; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19068010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000d; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000b0; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000b; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000b0; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000b; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8818101; +} + +static void +Opcode_ae_la8x8x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000b; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00020; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300002; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19048010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00007; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600080; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600080; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700030; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400003; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400030; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400003; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810101; +} + +static void +Opcode_ae_la16x4x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400003; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00050; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300005; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19058010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000f; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640040; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640040; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700070; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400007; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400070; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400007; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810103; +} + +static void +Opcode_ae_la32x2x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400007; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00060; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300006; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19020010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00001; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640080; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640080; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700080; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400008; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400080; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400008; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8818000; +} + +static void +Opcode_ae_la8x8x2_ic_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400008; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810000; +} + +static void +Opcode_ae_la16x4x2_ic_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00030; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300003; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19010010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000c0; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000c0; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700040; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400004; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400040; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400004; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810002; +} + +static void +Opcode_ae_la32x2x2_ic_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400004; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00070; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300007; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19028010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00009; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400c0; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400c0; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700090; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400009; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400090; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400009; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8818001; +} + +static void +Opcode_ae_la8x8x2_ic1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400009; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00010; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300001; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19008010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00006; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600040; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600040; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700010; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400001; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400010; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400001; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810001; +} + +static void +Opcode_ae_la16x4x2_ic1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400001; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00040; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300004; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19018010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000e; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640000; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700050; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400005; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400050; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400005; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810003; +} + +static void +Opcode_ae_la32x2x2_ic1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400005; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19060010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00005; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000a0; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000a; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000a0; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000a; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8818100; +} + +static void +Opcode_ae_la8x8x2_ic2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000a; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19040010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700020; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400002; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400020; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400002; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810100; +} + +static void +Opcode_ae_la16x4x2_ic2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400002; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19050010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000c; + slotbuf[1] = 0; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700060; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400006; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400060; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400006; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8810102; +} + +static void +Opcode_ae_la32x2x2_ic2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400006; +} + +static void +Opcode_ae_sa8x8x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800070; +} + +static void +Opcode_ae_sa8x8x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500070; +} + +static void +Opcode_ae_sa8x8x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830301; +} + +static void +Opcode_ae_sa16x4x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000f0; +} + +static void +Opcode_ae_sa16x4x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000f0; +} + +static void +Opcode_ae_sa16x4x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820301; +} + +static void +Opcode_ae_sa32x2x2_ip_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800030; +} + +static void +Opcode_ae_sa32x2x2_ip_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500030; +} + +static void +Opcode_ae_sa32x2x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820303; +} + +static void +Opcode_ae_sa8x8x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800040; +} + +static void +Opcode_ae_sa8x8x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500040; +} + +static void +Opcode_ae_sa8x8x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830200; +} + +static void +Opcode_ae_sa16x4x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000c0; +} + +static void +Opcode_ae_sa16x4x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000c0; +} + +static void +Opcode_ae_sa16x4x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820200; +} + +static void +Opcode_ae_sa32x2x2_ic_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800000; +} + +static void +Opcode_ae_sa32x2x2_ic_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500000; +} + +static void +Opcode_ae_sa32x2x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820202; +} + +static void +Opcode_ae_sa8x8x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800050; +} + +static void +Opcode_ae_sa8x8x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500050; +} + +static void +Opcode_ae_sa8x8x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830201; +} + +static void +Opcode_ae_sa16x4x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000d0; +} + +static void +Opcode_ae_sa16x4x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000d0; +} + +static void +Opcode_ae_sa16x4x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820201; +} + +static void +Opcode_ae_sa32x2x2_ic1_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800010; +} + +static void +Opcode_ae_sa32x2x2_ic1_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500010; +} + +static void +Opcode_ae_sa32x2x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820203; +} + +static void +Opcode_ae_sa8x8x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800060; +} + +static void +Opcode_ae_sa8x8x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500060; +} + +static void +Opcode_ae_sa8x8x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8830300; +} + +static void +Opcode_ae_sa16x4x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000e0; +} + +static void +Opcode_ae_sa16x4x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000e0; +} + +static void +Opcode_ae_sa16x4x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820300; +} + +static void +Opcode_ae_sa32x2x2_ic2_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800020; +} + +static void +Opcode_ae_sa32x2x2_ic2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500020; +} + +static void +Opcode_ae_sa32x2x2_ic2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820302; +} + +static void +Opcode_ae_abs8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80fa0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00e0; +} + +static void +Opcode_ae_abs8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80fb0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_abs8s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003820; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_abs8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0010; +} + +static void +Opcode_ae_abs8s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8005e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_neg8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b00f70; + slotbuf[1] = 0; +} + +static void +Opcode_ae_neg8s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003c60; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_neg8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a02a0; +} + +static void +Opcode_ae_neg8s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800de462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_add8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080400; +} + +static void +Opcode_ae_sub8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18600b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380400; +} + +static void +Opcode_ae_max8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18280f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0110040; + slotbuf[1] = 0; +} + +static void +Opcode_ae_max8_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_ae_max8_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40900a0; +} + +static void +Opcode_ae_max8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180400; +} + +static void +Opcode_ae_max8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a0000; +} + +static void +Opcode_ae_min8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18380f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc01100a0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_min8_Slot_ae4_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x548000; +} + +static void +Opcode_ae_min8_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40a80a0; +} + +static void +Opcode_ae_min8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180600; +} + +static void +Opcode_ae_min8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80b8000; +} + +static void +Opcode_ae_add8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18080b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_add8s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002800; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_add8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080800; +} + +static void +Opcode_ae_add8s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007460; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sub8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18600f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sub8s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003400; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_sub8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380800; +} + +static void +Opcode_ae_sub8s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_le8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18740f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_le8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380e00; +} + +static void +Opcode_ae_lt8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18780b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lt8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380b00; +} + +static void +Opcode_ae_eq8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18700f00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_eq8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380a00; +} + +static void +Opcode_ae_satu16x4_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000c0; +} + +static void +Opcode_ae_satu16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000062; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_satu32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001062; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat8x8x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_satu8x8x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001862; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sat8x4x32_l_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000b0; +} + +static void +Opcode_ae_sat8x4x32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_satu8x4x32_l_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000d0; +} + +static void +Opcode_ae_satu8x4x32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round8x8f16ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80007061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round8x8f16sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006c61; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round8x4f32ssym_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006861; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_round8x4f32sasym_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006461; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movda8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x752a003; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda8_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f00803; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105820c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movda8_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0301; +} + +static void +Opcode_ae_movda8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640660; +} + +static void +Opcode_ae_movda8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e10a0; +} + +static void +Opcode_ae_movda8_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1556004; +} + +static void +Opcode_ae_movad8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d832080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad8_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10734008; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movad8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10690080; +} + +static void +Opcode_ae_movad8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c01208; +} + +static void +Opcode_ae_movdx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movdx2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movdx2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10100000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movdx2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10100000; +} + +static void +Opcode_ae_movdx2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_movdx2_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_movdx2_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_movdx2_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_movdx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_movdx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; +} + +static void +Opcode_ae_movdx2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000100; +} + +static void +Opcode_ae_movdx2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000002; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addandsub32j_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addandsub32j_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_addandsub32j_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addandsub32j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8400000; +} + +static void +Opcode_ae_addandsub32j_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5200000; +} + +static void +Opcode_ae_addandsub32j_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000024; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addw8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addw8_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_addw8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc400000; +} + +static void +Opcode_ae_addw8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002e; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addw16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000a00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addw16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_addw16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb400000; +} + +static void +Opcode_ae_addw16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002c; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addw32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000e00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addw32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ae_addw32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb400800; +} + +static void +Opcode_ae_addw32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002d; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subw8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000300; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subw8_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_subw8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe400000; +} + +static void +Opcode_ae_subw8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000032; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subw16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000900; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subw16_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_ae_subw16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd400000; +} + +static void +Opcode_ae_subw16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000030; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subw32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000d00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subw32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_ae_subw32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd400800; +} + +static void +Opcode_ae_subw32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000031; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_accw8_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_accw8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000022; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_accw16_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_accw16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_accw32_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_accw32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000021; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addw8u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addw8u_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_ae_addw8u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc400800; +} + +static void +Opcode_ae_addw8u_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002f; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_subw8u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000700; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subw8u_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_subw8u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe400800; +} + +static void +Opcode_ae_subw8u_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000033; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_accw8u_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_accw8u_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000023; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x2s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c00000; +} + +static void +Opcode_ae_mulfp32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x2s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4700000; +} + +static void +Opcode_ae_mulafp32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x2s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000000; +} + +static void +Opcode_ae_mulsfp32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x2s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d00000; +} + +static void +Opcode_ae_mulfp32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x2s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4800000; +} + +static void +Opcode_ae_mulafp32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x2s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100000; +} + +static void +Opcode_ae_mulsfp32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulasf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulssf2d32s_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32s_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulasf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulasf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulasf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulssf2d32s_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulssf2d32s_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulssf2d32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mul32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd000c0; +} + +static void +Opcode_ae_mul32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00080; +} + +static void +Opcode_ae_mul32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8aa00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00300; +} + +static void +Opcode_ae_mula32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e002c0; +} + +static void +Opcode_ae_mula32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ed00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc004800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12002a0; +} + +static void +Opcode_ae_muls32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d001c0; +} + +static void +Opcode_ae_muls32s_hh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00120; +} + +static void +Opcode_ae_mul32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e000e0; +} + +static void +Opcode_ae_mul32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00360; +} + +static void +Opcode_ae_mula32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00320; +} + +static void +Opcode_ae_mula32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ce00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca004c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200300; +} + +static void +Opcode_ae_muls32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e001a0; +} + +static void +Opcode_ae_muls32s_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32s_hl_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32s_hl_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd000e0; +} + +static void +Opcode_ae_mul32s_hl_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e000a0; +} + +static void +Opcode_ae_mul32s_hl_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ab00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32s_hl_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32s_hl_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00320; +} + +static void +Opcode_ae_mula32s_hl_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e002e0; +} + +static void +Opcode_ae_mula32s_hl_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88e00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32s_hl_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce004800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32s_hl_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12002c0; +} + +static void +Opcode_ae_muls32s_hl_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d001e0; +} + +static void +Opcode_ae_muls32s_hl_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc300000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00100; +} + +static void +Opcode_ae_mul32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e000c0; +} + +static void +Opcode_ae_mul32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c800040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00340; +} + +static void +Opcode_ae_mula32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00300; +} + +static void +Opcode_ae_mula32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ae00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8004c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_muls32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12002e0; +} + +static void +Opcode_ae_muls32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e00180; +} + +static void +Opcode_ae_muls32s_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x2s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muls32x2s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500140; +} + +static void +Opcode_ae_mulzaad32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500320; +} + +static void +Opcode_ae_mulzaad32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15003e0; +} + +static void +Opcode_ae_mulzasd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66003c0; +} + +static void +Opcode_ae_mulzasd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsad32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsad32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600160; +} + +static void +Opcode_ae_mulzsad32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700340; +} + +static void +Opcode_ae_mulzsad32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600280; +} + +static void +Opcode_ae_mulzssd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68002a0; +} + +static void +Opcode_ae_mulzssd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6004400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00160; +} + +static void +Opcode_ae_mulaad32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00120; +} + +static void +Opcode_ae_mulaad32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900120; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000260; +} + +static void +Opcode_ae_mulasd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68001c0; +} + +static void +Opcode_ae_mulasd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8df00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsad32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc005800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsad32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000a0; +} + +static void +Opcode_ae_mulsad32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60002c0; +} + +static void +Opcode_ae_mulsad32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14002c0; +} + +static void +Opcode_ae_mulssd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64002a0; +} + +static void +Opcode_ae_mulssd32s_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaad32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaad32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500160; +} + +static void +Opcode_ae_mulzaad32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6500340; +} + +static void +Opcode_ae_mulzaad32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00360; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzasd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600000; +} + +static void +Opcode_ae_mulzasd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66003e0; +} + +static void +Opcode_ae_mulzasd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzsad32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzsad32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600180; +} + +static void +Opcode_ae_mulzsad32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6700360; +} + +static void +Opcode_ae_mulzsad32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16002a0; +} + +static void +Opcode_ae_mulzssd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68002c0; +} + +static void +Opcode_ae_mulzssd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaad32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6004800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaad32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00180; +} + +static void +Opcode_ae_mulaad32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00140; +} + +static void +Opcode_ae_mulaad32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900140; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulasd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulasd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000280; +} + +static void +Opcode_ae_mulasd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68001e0; +} + +static void +Opcode_ae_mulasd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8ff00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsad32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce005800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsad32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000c0; +} + +static void +Opcode_ae_mulsad32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60002e0; +} + +static void +Opcode_ae_mulsad32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14002e0; +} + +static void +Opcode_ae_mulssd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64002c0; +} + +static void +Opcode_ae_mulssd32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a002c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x2ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x2ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x2ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x2ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x2ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x2ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xa; +} + +static void +Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xb; +} + +static void +Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xc; +} + +static void +Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulf32x2r_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x2r_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x2r_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf32x2r_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaf32x2r_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf32x2r_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj32ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8003000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfcj32ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100340; +} + +static void +Opcode_ae_mulfcj32ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76001c0; +} + +static void +Opcode_ae_mulfcj32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj32ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafcj32ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00360; +} + +static void +Opcode_ae_mulafcj32ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62001c0; +} + +static void +Opcode_ae_mulafcj32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89a00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf2p32x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2p32x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2p32x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulaf2p32x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulaf2p32x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulaf2p32x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4; +} + +static void +Opcode_ae_mulsf2p32x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulsf2p32x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulsf2p32x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x8; +} + +static void +Opcode_ae_mulf2p32x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2p32x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2p32x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulaf2p32x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaf2p32x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulaf2p32x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_ae_mulsf2p32x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsf2p32x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulsf2p32x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_mulp32x2s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00020; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul2p32x4s_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4s_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula2p32x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2p32x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2p32x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_muls2p32x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_muls2p32x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_muls2p32x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mul2p32x4t_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4t_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2p32x4t_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula2p32x4t_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2p32x4t_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2p32x4t_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_muls2p32x4t_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_muls2p32x4t_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_muls2p32x4t_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulzaa32x2_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzss32x2_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaa32x2_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss32x2_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulcj32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca001400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulcj32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100060; +} + +static void +Opcode_ae_mulcj32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d001c0; +} + +static void +Opcode_ae_mulcj32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a00100; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulacj32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulacj32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00080; +} + +static void +Opcode_ae_mulacj32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600160; +} + +static void +Opcode_ae_mulacj32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89100040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_muladdf32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsubf32ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc32ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfc32ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_mulfc32ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4900000; +} + +static void +Opcode_ae_mulfc32ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc32ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafc32ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_mulafc32ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4400000; +} + +static void +Opcode_ae_mulafc32ra_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulcj32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulacj32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32w_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf2d32x2ws_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2d32x2ws_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulf2d32x2ws_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_mulzaaaa2q16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaaa2q16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaaa2q16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulaaaa2q16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaaa2q16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaaa2q16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulp16s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca003c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp16s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200100; +} + +static void +Opcode_ae_mulp16s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a001a0; +} + +static void +Opcode_ae_mulp16s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulap16s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap16s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000e0; +} + +static void +Opcode_ae_mulap16s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65001c0; +} + +static void +Opcode_ae_mulap16s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8fc00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsp16s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp16s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400100; +} + +static void +Opcode_ae_mulsp16s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63002e0; +} + +static void +Opcode_ae_mulsp16s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17800260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc003c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200120; +} + +static void +Opcode_ae_mulp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a001c0; +} + +static void +Opcode_ae_mulp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulap16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000100; +} + +static void +Opcode_ae_mulap16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65001e0; +} + +static void +Opcode_ae_mulap16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89d00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400120; +} + +static void +Opcode_ae_mulsp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300300; +} + +static void +Opcode_ae_mulsp16s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17900260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mul2c16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mula2c16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj16ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce002c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfcj16ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100320; +} + +static void +Opcode_ae_mulfcj16ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76001a0; +} + +static void +Opcode_ae_mulfcj16ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00320; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj16ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulafcj16ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00340; +} + +static void +Opcode_ae_mulafcj16ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62001a0; +} + +static void +Opcode_ae_mulafcj16ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f900040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc16s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulc16s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10003e0; +} + +static void +Opcode_ae_mulc16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c00180; +} + +static void +Opcode_ae_mulc16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac16s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0200400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulac16s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_mulac16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000160; +} + +static void +Opcode_ae_mulac16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp16x4rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca003000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulfp16x4rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100360; +} + +static void +Opcode_ae_mulfp16x4rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7700180; +} + +static void +Opcode_ae_mulfp16x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b00340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfd16x16x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfd16x16x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfd16x16x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulp16x16x4s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce003c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulp16x16x4s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200140; +} + +static void +Opcode_ae_mulp16x16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a001e0; +} + +static void +Opcode_ae_mulp16x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulap16x16x4s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee300400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulap16x16x4s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000120; +} + +static void +Opcode_ae_mulap16x16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600180; +} + +static void +Opcode_ae_mulap16x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8bd00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsp16x16x4s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulsp16x16x4s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400140; +} + +static void +Opcode_ae_mulsp16x16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6300320; +} + +static void +Opcode_ae_mulsp16x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00260; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000e0; +} + +static void +Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65002c0; +} + +static void +Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500100; +} + +static void +Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65002e0; +} + +static void +Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00340; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600240; +} + +static void +Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800260; +} + +static void +Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f00040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1600260; +} + +static void +Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800280; +} + +static void +Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c00060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6003800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00100; +} + +static void +Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f000c0; +} + +static void +Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159000c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6003c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00120; +} + +static void +Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f000e0; +} + +static void +Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159000e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss2d16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulss2d16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400220; +} + +static void +Opcode_ae_mulss2d16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400200; +} + +static void +Opcode_ae_mulss2d16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulss2d16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulss2d16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400240; +} + +static void +Opcode_ae_mulss2d16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6400220; +} + +static void +Opcode_ae_mulss2d16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15002a0; +} + +static void +Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6600280; +} + +static void +Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc200c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15002c0; +} + +static void +Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66002a0; +} + +static void +Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179003c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003a0; +} + +static void +Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68003c0; +} + +static void +Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec300800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003c0; +} + +static void +Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68003e0; +} + +static void +Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d00080; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6007000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002c0; +} + +static void +Opcode_ae_mulaafd16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f00280; +} + +static void +Opcode_ae_mulaafd16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15900280; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaafd16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6007400; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulaafd16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002e0; +} + +static void +Opcode_ae_mulaafd16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f002a0; +} + +static void +Opcode_ae_mulaafd16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159002a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd16ss_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd16ss_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14003e0; +} + +static void +Opcode_ae_mulssfd16ss_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64003c0; +} + +static void +Opcode_ae_mulssfd16ss_hh_ll_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a00300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulssfd16ss_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0200800; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mulssfd16ss_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1500000; +} + +static void +Opcode_ae_mulssfd16ss_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64003e0; +} + +static void +Opcode_ae_mulssfd16ss_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b00300; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfd16x16x4ws_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulfd16x16x4ws_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulfd16x16x4ws_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_mulzaaaa2q16x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaa2q16x8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaa2q16x8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaa2q16x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaaaa2q16x8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaaaa2q16x8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzaaaa2q8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaa2q8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulzaaaa2q8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaa2q8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaa2q8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulaaaa2q8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14500000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulc32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulac32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulpc32x16x2_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulpc32x16x2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulpc32x16x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulapc32x16x2_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulapc32x16x2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulapc32x16x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfp32x16_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14e00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14200000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfp32x16_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14f00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafp32x16_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14300000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsfp32x16_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15400000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc32x16w_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a00000; +} + +static void +Opcode_ae_mulfc32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc32x16w_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4500000; +} + +static void +Opcode_ae_mulafc32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfc32x16w_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b00000; +} + +static void +Opcode_ae_mulfc32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16900000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafc32x16w_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4600000; +} + +static void +Opcode_ae_mulafc32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj32x16w_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfcj32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulafcj32x16w_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14100000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf2p32x16x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulsf2p32x16x4ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf2p32x16x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulsf2p32x16x4rs_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4rs_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4rs_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulf2p32x16x4s_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4s_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulf2p32x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4s_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4s_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulaf2p32x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulsf2p32x16x4s_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4s_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulsf2p32x16x4s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_mulfpc32x16x2ras_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mulfpc32x16x2ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfpc32x16x2ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfpc32x16x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpc32x16x2ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpc32x16x2ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpc32x16x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfpcj32x16x2ras_Slot_ae4_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ae_mulfpcj32x16x2ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfpcj32x16x2ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulfpcj32x16x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpcj32x16x2ras_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpcj32x16x2ras_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulafpcj32x16x2ras_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000000; + slotbuf[1] = 0xd; +} + +static void +Opcode_ae_mulzaaaa2q32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaaa2q32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulzaaaa2q32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x9; +} + +static void +Opcode_ae_mulaaaa2q32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaaa2q32x16_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mulaaaa2q32x16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mul2q32x16_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2q32x16_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mul2q32x16_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula2q32x16_fir_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2q32x16_fir_h_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2q32x16_fir_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mul2q32x16_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mul2q32x16_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mul2q32x16_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x1; +} + +static void +Opcode_ae_mula2q32x16_fir_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mula2q32x16_fir_l_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_mula2q32x16_fir_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_srai8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d824080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00208; +} + +static void +Opcode_ae_srai8r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d826080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai8r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04208; +} + +static void +Opcode_ae_srli8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d828080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srli8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00308; +} + +static void +Opcode_ae_slai8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d820080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9308; +} + +static void +Opcode_ae_slai8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d822080; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83ad308; +} + +static void +Opcode_ae_slaa8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a800c; +} + +static void +Opcode_ae_srla8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c82c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9008; +} + +static void +Opcode_ae_slaa8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x758a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a810c; +} + +static void +Opcode_ae_sraa8rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa8rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1104; +} + +static void +Opcode_ae_sraa8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x758c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9004; +} + +static void +Opcode_ae_srli16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c830000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srli16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1208; +} + +static void +Opcode_ae_slai16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c81c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slai16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a820c; +} + +static void +Opcode_ae_slaa16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c814000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_slaa16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a8008; +} + +static void +Opcode_ae_srla16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c826000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10500500; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srla16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9304; +} + +static void +Opcode_ae_srai16sym_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c824000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai16sym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9204; +} + +static void +Opcode_ae_sraa16syms_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d81e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa16syms_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9100; +} + +static void +Opcode_ae_srai32sym_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c80e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srai32sym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842e007; +} + +static void +Opcode_ae_sraa32syms_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x748e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sraa32syms_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9300; +} + +static void +Opcode_ae_srav16rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srav16rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00000; +} + +static void +Opcode_ae_srav32rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880010; + slotbuf[1] = 0; +} + +static void +Opcode_ae_srav32rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c02000; +} + +static void +Opcode_ae_cvti32x4f8_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a014000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8424002; +} + +static void +Opcode_ae_cvti32x4f8_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a016000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8426002; +} + +static void +Opcode_ae_cvti32x4f8s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a008000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8420001; +} + +static void +Opcode_ae_cvti32x4f8s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8422001; +} + +static void +Opcode_ae_cvta32x4f8_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a034000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8120200; +} + +static void +Opcode_ae_cvta32x4f8_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a036000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8120300; +} + +static void +Opcode_ae_cvta32x4f8s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a028000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82a0000; +} + +static void +Opcode_ae_cvta32x4f8s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a02a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82a0100; +} + +static void +Opcode_ae_cvti32x4f8u_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a010000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8u_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8420002; +} + +static void +Opcode_ae_cvti32x4f8u_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a012000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8u_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8422002; +} + +static void +Opcode_ae_cvti32x4f8us_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8us_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8424001; +} + +static void +Opcode_ae_cvti32x4f8us_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a00e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f8us_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8426001; +} + +static void +Opcode_ae_cvta32x4f8u_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a030000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8u_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8120000; +} + +static void +Opcode_ae_cvta32x4f8u_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a032000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8u_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8120100; +} + +static void +Opcode_ae_cvta32x4f8us_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a02c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8us_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82a0200; +} + +static void +Opcode_ae_cvta32x4f8us_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a02e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f8us_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82a0300; +} + +static void +Opcode_ae_cvti32x4f16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8420000; +} + +static void +Opcode_ae_cvti32x4f16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a002000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8422000; +} + +static void +Opcode_ae_cvta32x4f16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a020000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a0000; +} + +static void +Opcode_ae_cvta32x4f16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a022000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a0100; +} + +static void +Opcode_ae_cvti32x4f16u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a004000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f16u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8424000; +} + +static void +Opcode_ae_cvti32x4f16us_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a006000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti32x4f16us_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8426000; +} + +static void +Opcode_ae_cvta32x4f16u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a024000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f16u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a0200; +} + +static void +Opcode_ae_cvta32x4f16us_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a026000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta32x4f16us_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a0300; +} + +static void +Opcode_ae_cvti16x4x2f8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a038000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti16x4x2f8_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500200; +} + +static void +Opcode_ae_cvti16x4x2f8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8320000; +} + +static void +Opcode_ae_cvti16x4x2f8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a03a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti16x4x2f8s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_cvti16x4x2f8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8320100; +} + +static void +Opcode_ae_cvta16x4x2f8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b018000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta16x4x2f8_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_cvta16x4x2f8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220000; +} + +static void +Opcode_ae_cvta16x4x2f8s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b01a000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta16x4x2f8s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400200; +} + +static void +Opcode_ae_cvta16x4x2f8s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220100; +} + +static void +Opcode_ae_cvti16x4x2f8u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a03c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti16x4x2f8u_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600200; +} + +static void +Opcode_ae_cvti16x4x2f8u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8320200; +} + +static void +Opcode_ae_cvti16x4x2f8us_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a03e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvti16x4x2f8us_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8320300; +} + +static void +Opcode_ae_cvta16x4x2f8u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b01c000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta16x4x2f8u_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_cvta16x4x2f8u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220200; +} + +static void +Opcode_ae_cvta16x4x2f8us_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b01e000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_cvta16x4x2f8us_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8220300; +} + +static void +Opcode_ae_sel8x8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0108000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sel8x8_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_ae_sel8x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16700000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel8x8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000440; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel8x8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a00000; +} + +static void +Opcode_ae_sel8x8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000036; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl8x8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc01100e0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_shfl8x8_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900400; +} + +static void +Opcode_ae_shfl8x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a08000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl8x8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000c40; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl8x8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8200400; +} + +static void +Opcode_ae_shfl8x8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000063; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel16x4_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_ae_sel16x4_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000020; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_sel16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0100000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sel16x4_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_ae_sel16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16600000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel16x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000040; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel16x4_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000002; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sel16x4_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000020; +} + +static void +Opcode_ae_sel16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5900000; +} + +static void +Opcode_ae_sel16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000035; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc01100c0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_shfl16x4_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900000; +} + +static void +Opcode_ae_shfl16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl16x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c40; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_shfl16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8200000; +} + +static void +Opcode_ae_shfl16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000063; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel8x8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80008000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dsel8x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel8x8_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000400; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel8x8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_ae_dsel8x8_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000001; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel16x4_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_ae_dsel16x4_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_ae_dsel16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dsel16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel16x4_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_dsel16x4_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_dsel16x4_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000000; +} + +static void +Opcode_ae_dsel16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_dsel16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel8x8i_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sel8x8i_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_sel8x8i_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16800000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel8x8i_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000840; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sel8x8i_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b00000; +} + +static void +Opcode_ae_sel8x8i_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000037; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rmax8x8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63d0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_rmax8x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b004e0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rmax8x8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac58000; +} + +static void +Opcode_ae_rmin8x8_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63e0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_rmin8x8_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00520; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rmin8x8_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae58000; +} + +static void +Opcode_ae_rmax16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63c8c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_rmax16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b004c0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rmax16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab58000; +} + +static void +Opcode_ae_rmin16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63d8c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_rmin16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00500; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_rmin16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad58000; +} + +static void +Opcode_ae_sort16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e048000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_sort16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00000; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_sort16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa038000; +} + +static void +Opcode_ae_radd8x8_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63a0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radd8x8_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00420; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radd8x8_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa658000; +} + +static void +Opcode_ae_radda8x8_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63b8c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radda8x8_h_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00480; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radda8x8_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa958000; +} + +static void +Opcode_ae_radd8x8_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63a8c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radd8x8_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00440; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radd8x8_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa758000; +} + +static void +Opcode_ae_radda8x8_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63c0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radda8x8_l_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b004a0; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radda8x8_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa58000; +} + +static void +Opcode_ae_radd16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6398c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radd16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00400; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radd16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa558000; +} + +static void +Opcode_ae_radda16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63b0c00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_radda16x4_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b00460; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_radda16x4_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa858000; +} + +static void +Opcode_ae_bmax8x8_h_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14004400; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmax8x8_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_bmax8x8_l_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1288000; +} + +static void +Opcode_ae_bmax8x8_l_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14006000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmax8x8_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_bmin8x8_h_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmin8x8_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_bmin8x8_l_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c8000; +} + +static void +Opcode_ae_bmin8x8_l_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000400; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmin8x8_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_bmax16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bmax16x4_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1280000; +} + +static void +Opcode_ae_bmax16x4_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14004000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmax16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820800; +} + +static void +Opcode_ae_bmin16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d700200; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bmin16x4_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c0000; +} + +static void +Opcode_ae_bmin16x4_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14006400; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmin16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820c00; +} + +static void +Opcode_ae_bmax32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c700000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bmax32x2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_ae_bmax32x2_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmax32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400a00; +} + +static void +Opcode_ae_bmin32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c700100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_bmin32x2_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0000; +} + +static void +Opcode_ae_bmin32x2_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14002000; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_bmin32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400e00; +} + +static void +Opcode_ae_addinv16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80fd0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addinv16s_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a000; +} + +static void +Opcode_ae_addinv16s_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ae_addinv16s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003c20; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addinv16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0050; +} + +static void +Opcode_ae_addinv16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3d0000; +} + +static void +Opcode_ae_addinv16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8006e462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addinv32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a80fe0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addinv32s_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133a400; +} + +static void +Opcode_ae_addinv32s_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130020; +} + +static void +Opcode_ae_addinv32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16003840; + slotbuf[1] = 0x2; +} + +static void +Opcode_ae_addinv32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a0070; +} + +static void +Opcode_ae_addinv32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3d8000; +} + +static void +Opcode_ae_addinv32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80076462; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movt16x8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt16x8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_movt8x16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt8x16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; +} + +static void +Opcode_ae_movt8x16_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movt8x16_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000000; +} + +static void +Opcode_ae_movbd1x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520005; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movbd1x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa824004; +} + +static void +Opcode_ae_movbd1x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7520004; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movbd1x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa820004; +} + +static void +Opcode_ae_movneg32s_t_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18400b00; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movneg32s_t_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7180a00; +} + +static void +Opcode_ae_movneg32s_t_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80d0000; +} + +static void +Opcode_ae_movneg32s_t_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004061; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_movdext_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movdext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8420003; +} + +static void +Opcode_ae_movadext_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c400000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movadext_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400000; +} + +static void +Opcode_ae_movadext_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c440000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_movadext_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400400; +} + +static void +Opcode_ae_nsa16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19196030; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsa16x4_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03021; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsa16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0220c; +} + +static void +Opcode_ae_nsaz32x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880070; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsaz32x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c06001; +} + +static void +Opcode_ae_nsa32x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c880060; + slotbuf[1] = 0; +} + +static void +Opcode_ae_nsa32x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04001; +} + +static void +Opcode_ae_trunci16x4f32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c080000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunci16x4f32s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_trunci16x4f32s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; +} + +static void +Opcode_ae_trunci16x4f32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8422003; +} + +static void +Opcode_ae_trunci16x4f64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunci16x4f64s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_trunci16x4f64s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_trunci16x4f64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8020000; +} + +static void +Opcode_ae_trunca16x4f32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c100000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca16x4f32s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ae_trunca16x4f32s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; +} + +static void +Opcode_ae_trunca16x4f32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81a0000; +} + +static void +Opcode_ae_trunca16x4f64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c180000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_trunca16x4f64s_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x704000; +} + +static void +Opcode_ae_trunca16x4f64s_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1480000; +} + +static void +Opcode_ae_trunca16x4f64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81a0100; +} + +static void +Opcode_ae_addc32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c680000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addc32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_addc32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400800; +} + +static void +Opcode_ae_subc32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c780000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subc32_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_subc32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820000; +} + +static void +Opcode_ae_addc32u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c680100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_addc32u_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40000; +} + +static void +Opcode_ae_addc32u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7400c00; +} + +static void +Opcode_ae_subc32u_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c780100; + slotbuf[1] = 0; +} + +static void +Opcode_ae_subc32u_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_subc32u_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8820400; +} + +static void +Opcode_ae_expadd16_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; +} + +static void +Opcode_ae_expadd16_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004060; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_expsub16_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010000; +} + +static void +Opcode_ae_expsub16_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004860; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_expadd16_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8008000; +} + +static void +Opcode_ae_expadd16_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004460; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_expsub16_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8018000; +} + +static void +Opcode_ae_expsub16_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004c60; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addcexp32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002a; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_addcexp32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000002b; + slotbuf[1] = 0xe; +} + +static void +Opcode_ae_calcrng16_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680800; +} + +static void +Opcode_ae_calcrng32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10680c00; +} + +static void +Opcode_ae_rng32x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7382f00; +} + +static void +Opcode_ae_lav8x8x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_lav8x8x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a058000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lav8x8x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_lav8x8x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_lav8x8x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8118000; +} + +static void +Opcode_ae_lav16x4x2_xp_Slot_ae10_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lav16x4x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a018000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lav16x4x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_lav16x4x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_lav16x4x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8110000; +} + +static void +Opcode_ae_sav8x8x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_sav8x8x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_sav8x8x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf410000; +} + +static void +Opcode_ae_sav16x4x2_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_sav16x4x2_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_sav16x4x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf400000; +} + +static void +Opcode_ae_movzbvcdr_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100001; + slotbuf[1] = 0x229860; +} + +static void +Opcode_ae_movzbvcdr_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00027; +} + +static void +Opcode_ae_movdrzbvc_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; + slotbuf[1] = 0x229860; +} + +static void +Opcode_ae_movdrzbvc_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00026; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6040000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010000; +} + +static void +Opcode_ae_lavunsqz8x8_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae10_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae8_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae8_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae9_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; +} + +static void +Opcode_ae_lavunsqz16x4_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mul8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002000; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mul8q4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula8q4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400; + slotbuf[1] = 0x2c0100; +} + +static void +Opcode_ae_mul8q8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula8q8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mul8qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x40000; +} + +static void +Opcode_ae_mula8qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0xc0000; +} + +static void +Opcode_ae_mul4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x240000; +} + +static void +Opcode_ae_mula4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x240000; +} + +static void +Opcode_ae_mul4o4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x280000; +} + +static void +Opcode_ae_mula4o4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x284000; +} + +static void +Opcode_ae_mul4o8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_ae_mula4o8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x80000; +} + +static void +Opcode_ae_mul4qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x282000; +} + +static void +Opcode_ae_mula4qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x286000; +} + +static void +Opcode_ae_mul8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0728; +} + +static void +Opcode_ae_mul8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0628; +} + +static void +Opcode_ae_mula8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c2628; +} + +static void +Opcode_ae_mula8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c2628; +} + +static void +Opcode_ae_mul8q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0128; +} + +static void +Opcode_ae_mula8q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0228; +} + +static void +Opcode_ae_mul2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0628; +} + +static void +Opcode_ae_mula2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0728; +} + +static void +Opcode_ae_mul2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0008; +} + +static void +Opcode_ae_mul2x4q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula2x4q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0008; +} + +static void +Opcode_ae_mulqq8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200040; +} + +static void +Opcode_ae_mulaqq8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200010; +} + +static void +Opcode_ae_mul4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201860; +} + +static void +Opcode_ae_mula4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x205860; +} + +static void +Opcode_ae_mul4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x203860; +} + +static void +Opcode_ae_mula4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x207860; +} + +static void +Opcode_ae_mul4o8x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200460; +} + +static void +Opcode_ae_mula4o8x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200a60; +} + +static void +Opcode_ae_mul4o8x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200560; +} + +static void +Opcode_ae_mula4o8x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200b60; +} + +static void +Opcode_ae_mul8q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0028; +} + +static void +Opcode_ae_mula8q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0128; +} + +static void +Opcode_ae_mul8q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0028; +} + +static void +Opcode_ae_mula8q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0228; +} + +static void +Opcode_ae_mul2x4q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula2x4q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0008; +} + +static void +Opcode_ae_mul2x4q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mula2x4q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0008; +} + +static void +Opcode_ae_mulqq4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200030; +} + +static void +Opcode_ae_mulaqq4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200000; +} + +static void +Opcode_ae_mulqq4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200038; +} + +static void +Opcode_ae_mulaqq4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200008; +} + +static void +Opcode_ae_mul4o4x16cnv_hh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200060; +} + +static void +Opcode_ae_mul4o4x16cnv_hl_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200160; +} + +static void +Opcode_ae_mul4o4x16cnv_lh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200260; +} + +static void +Opcode_ae_mul4o4x16cnv_ll_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200360; +} + +static void +Opcode_ae_mula4o4x16cnv_hh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200660; +} + +static void +Opcode_ae_mula4o4x16cnv_hl_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200760; +} + +static void +Opcode_ae_mula4o4x16cnv_lh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200860; +} + +static void +Opcode_ae_mula4o4x16cnv_ll_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200960; +} + +static void +Opcode_ae_muluu8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; + slotbuf[1] = 0x2c0002; +} + +static void +Opcode_ae_mulauu8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; + slotbuf[1] = 0x2c0001; +} + +static void +Opcode_ae_muluu4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x240002; +} + +static void +Opcode_ae_mulauu4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x240001; +} + +static void +Opcode_ae_muluu8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2cc728; +} + +static void +Opcode_ae_mulauu8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c6728; +} + +static void +Opcode_ae_muluu8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2cc628; +} + +static void +Opcode_ae_mulauu8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c6628; +} + +static void +Opcode_ae_muluu2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2cc628; +} + +static void +Opcode_ae_mulauu2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c6628; +} + +static void +Opcode_ae_muluu2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0028; +} + +static void +Opcode_ae_mulauu2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0018; +} + +static void +Opcode_ae_muluu4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x221860; +} + +static void +Opcode_ae_mulauu4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x211860; +} + +static void +Opcode_ae_muluu4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x223860; +} + +static void +Opcode_ae_mulauu4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x213860; +} + +static void +Opcode_ae_mulus8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0002000; + slotbuf[1] = 0x2c0001; +} + +static void +Opcode_ae_mulaus8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0002000; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mulus8q4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400; + slotbuf[1] = 0x2c0300; +} + +static void +Opcode_ae_mulaus8q4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400; + slotbuf[1] = 0x2c0200; +} + +static void +Opcode_ae_mulus8q8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mulaus8q8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mulus8qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x1c0000; +} + +static void +Opcode_ae_mulaus8qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x140000; +} + +static void +Opcode_ae_mulus4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x240001; +} + +static void +Opcode_ae_mulaus4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x240000; +} + +static void +Opcode_ae_mulus4o4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x28c000; +} + +static void +Opcode_ae_mulaus4o4x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x288000; +} + +static void +Opcode_ae_mulus4o8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x180000; +} + +static void +Opcode_ae_mulaus4o8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x100000; +} + +static void +Opcode_ae_mulus4qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x28e000; +} + +static void +Opcode_ae_mulaus4qw8x16_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x28a000; +} + +static void +Opcode_ae_mulus8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2ca728; +} + +static void +Opcode_ae_mulaus8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c4728; +} + +static void +Opcode_ae_mulus8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2ca728; +} + +static void +Opcode_ae_mulaus8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c4728; +} + +static void +Opcode_ae_mulus8q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0528; +} + +static void +Opcode_ae_mulaus8q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0428; +} + +static void +Opcode_ae_mulus2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2ca628; +} + +static void +Opcode_ae_mulaus2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c4628; +} + +static void +Opcode_ae_mulus2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0020; +} + +static void +Opcode_ae_mulaus2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0018; +} + +static void +Opcode_ae_mulus2x4q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0020; +} + +static void +Opcode_ae_mulaus2x4q8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0010; +} + +static void +Opcode_ae_mulusqq8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200058; +} + +static void +Opcode_ae_mulausqq8x16cnv_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200028; +} + +static void +Opcode_ae_mulus4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x21d860; +} + +static void +Opcode_ae_mulaus4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x20d860; +} + +static void +Opcode_ae_mulus4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x21f860; +} + +static void +Opcode_ae_mulaus4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x20f860; +} + +static void +Opcode_ae_mulus4o8x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201660; +} + +static void +Opcode_ae_mulaus4o8x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201060; +} + +static void +Opcode_ae_mulus4o8x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201760; +} + +static void +Opcode_ae_mulaus4o8x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201160; +} + +static void +Opcode_ae_mulus8q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0428; +} + +static void +Opcode_ae_mulaus8q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0328; +} + +static void +Opcode_ae_mulus8q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0528; +} + +static void +Opcode_ae_mulaus8q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0328; +} + +static void +Opcode_ae_mulus2x4q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0020; +} + +static void +Opcode_ae_mulaus2x4q4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0010; +} + +static void +Opcode_ae_mulus2x4q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0020; +} + +static void +Opcode_ae_mulaus2x4q4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0010; +} + +static void +Opcode_ae_mulusqq4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200048; +} + +static void +Opcode_ae_mulausqq4x16cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200018; +} + +static void +Opcode_ae_mulusqq4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200050; +} + +static void +Opcode_ae_mulausqq4x16cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200020; +} + +static void +Opcode_ae_mulus4o4x16cnv_hh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201260; +} + +static void +Opcode_ae_mulus4o4x16cnv_hl_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201360; +} + +static void +Opcode_ae_mulus4o4x16cnv_lh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201460; +} + +static void +Opcode_ae_mulus4o4x16cnv_ll_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x201560; +} + +static void +Opcode_ae_mulaus4o4x16cnv_hh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200c60; +} + +static void +Opcode_ae_mulaus4o4x16cnv_hl_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200d60; +} + +static void +Opcode_ae_mulaus4o4x16cnv_lh_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200e60; +} + +static void +Opcode_ae_mulaus4o4x16cnv_ll_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x200f60; +} + +static void +Opcode_ae_mulsu8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002000; + slotbuf[1] = 0x2c0001; +} + +static void +Opcode_ae_mulasu8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002000; + slotbuf[1] = 0x2c0000; +} + +static void +Opcode_ae_mulsu4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x240001; +} + +static void +Opcode_ae_mulasu4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x240000; +} + +static void +Opcode_ae_mulsu8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2ca628; +} + +static void +Opcode_ae_mulasu8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c4628; +} + +static void +Opcode_ae_mulsu8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c8728; +} + +static void +Opcode_ae_mulasu8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c2728; +} + +static void +Opcode_ae_mulsu2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c8728; +} + +static void +Opcode_ae_mulasu2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c2728; +} + +static void +Opcode_ae_mulsu2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c0018; +} + +static void +Opcode_ae_mulasu2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; + slotbuf[1] = 0x2c0010; +} + +static void +Opcode_ae_mulsu4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x219860; +} + +static void +Opcode_ae_mulasu4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x209860; +} + +static void +Opcode_ae_mulsu4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x21b860; +} + +static void +Opcode_ae_mulasu4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x20b860; +} + +static void +Opcode_ae_muluuzb8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002000; + slotbuf[1] = 0x2c0002; +} + +static void +Opcode_ae_mulauuzb8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002000; + slotbuf[1] = 0x2c0001; +} + +static void +Opcode_ae_muluuzb4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x240002; +} + +static void +Opcode_ae_mulauuzb4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x240001; +} + +static void +Opcode_ae_muluuzb8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2ce628; +} + +static void +Opcode_ae_mulauuzb8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c8628; +} + +static void +Opcode_ae_muluuzb8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2ce628; +} + +static void +Opcode_ae_mulauuzb8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c8628; +} + +static void +Opcode_ae_muluuzb2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2cc728; +} + +static void +Opcode_ae_mulauuzb2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2c6728; +} + +static void +Opcode_ae_muluuzb2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; + slotbuf[1] = 0x2c0028; +} + +static void +Opcode_ae_mulauuzb2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2c0018; +} + +static void +Opcode_ae_muluuzb4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x225860; +} + +static void +Opcode_ae_mulauuzb4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x215860; +} + +static void +Opcode_ae_muluuzb4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x227860; +} + +static void +Opcode_ae_mulauuzb4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x217860; +} + +static void +Opcode_ae_muluuzb3x3o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4280000; +} + +static void +Opcode_ae_mulauuzb3x3o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4180000; +} + +static void +Opcode_ae_mulzb8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002000; + slotbuf[1] = 0x2c0003; +} + +static void +Opcode_ae_mulazb8q8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002000; + slotbuf[1] = 0x2c0002; +} + +static void +Opcode_ae_mulzb4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x240003; +} + +static void +Opcode_ae_mulazb4o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x240003; +} + +static void +Opcode_ae_mulzb8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2d8628; +} + +static void +Opcode_ae_mulazb8q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2d2728; +} + +static void +Opcode_ae_mulzb8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2dc728; +} + +static void +Opcode_ae_mulazb8q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2d6728; +} + +static void +Opcode_ae_mulzb2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; + slotbuf[1] = 0x2d0628; +} + +static void +Opcode_ae_mulazb2x4q8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; + slotbuf[1] = 0x2da728; +} + +static void +Opcode_ae_mulzb2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800; + slotbuf[1] = 0x2c0018; +} + +static void +Opcode_ae_mulazb2x4q8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; + slotbuf[1] = 0x2c0018; +} + +static void +Opcode_ae_mulzb4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x233860; +} + +static void +Opcode_ae_mulazb4o8x8cnv_h_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x231860; +} + +static void +Opcode_ae_mulzb4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x237860; +} + +static void +Opcode_ae_mulazb4o8x8cnv_l_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x235860; +} + +static void +Opcode_ae_mulzb3x3o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4000000; +} + +static void +Opcode_ae_mulazb3x3o8x8_Slot_ae8_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4040000; +} + +static void +Opcode_cvtsf16_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190c0026; + slotbuf[1] = 0; +} + +static void +Opcode_cvtsf16_l_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b7; +} + +static void +Opcode_cvtsf16_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a2f00; +} + +static void +Opcode_cvtsf16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190c0022; + slotbuf[1] = 0; +} + +static void +Opcode_cvtsf16_h_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b5; +} + +static void +Opcode_cvtsf16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a2b00; +} + +static void +Opcode_cvtf16s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1908002e; + slotbuf[1] = 0; +} + +static void +Opcode_cvtf16s_l_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b3; +} + +static void +Opcode_cvtf16s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2f00; +} + +static void +Opcode_cvtf16s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1908002a; + slotbuf[1] = 0; +} + +static void +Opcode_cvtf16s_h_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b1; +} + +static void +Opcode_cvtf16s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2b00; +} + +static void +Opcode_ae_movfcrfsrv_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4a0000; +} + +static void +Opcode_ae_movvfcrfsr_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4a8000; +} + +static void +Opcode_movt_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800e0; + slotbuf[1] = 0; +} + +static void +Opcode_movt_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481200; +} + +static void +Opcode_movt_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742e001; +} + +static void +Opcode_movf_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8800d0; + slotbuf[1] = 0; +} + +static void +Opcode_movf_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480a00; +} + +static void +Opcode_movf_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x742c001; +} + +static void +Opcode_moveqz_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d88000c; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04200; + slotbuf[1] = 0; +} + +static void +Opcode_moveqz_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480800; +} + +static void +Opcode_moveqz_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830000; +} + +static void +Opcode_movnez_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d88000a; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04b00; + slotbuf[1] = 0; +} + +static void +Opcode_movnez_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10481000; +} + +static void +Opcode_movnez_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98300c0; +} + +static void +Opcode_movgez_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880002; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04300; + slotbuf[1] = 0; +} + +static void +Opcode_movgez_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480c00; +} + +static void +Opcode_movgez_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830040; +} + +static void +Opcode_movltz_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d880006; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c04a00; + slotbuf[1] = 0; +} + +static void +Opcode_movltz_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10480e00; +} + +static void +Opcode_movltz_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9830080; +} + +static void +Opcode_rfr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9929a04; +} + +static void +Opcode_wfr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e10c0; +} + +static void +Opcode_mul_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000020; + slotbuf[1] = 0x7; +} + +static void +Opcode_mul_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000020; + slotbuf[1] = 0x5; +} + +static void +Opcode_mul_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4300c00; + slotbuf[1] = 0; +} + +static void +Opcode_mul_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17001c0; +} + +static void +Opcode_mul_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae000080; + slotbuf[1] = 0; +} + +static void +Opcode_mul_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e000020; +} + +static void +Opcode_mul_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69003e0; +} + +static void +Opcode_mul_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003f; + slotbuf[1] = 0xe; +} + +static void +Opcode_madd_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; + slotbuf[1] = 0x7; +} + +static void +Opcode_madd_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000020; + slotbuf[1] = 0x5; +} + +static void +Opcode_madd_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe300800; + slotbuf[1] = 0; +} + +static void +Opcode_madd_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700160; +} + +static void +Opcode_madd_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8000080; + slotbuf[1] = 0; +} + +static void +Opcode_madd_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000020; +} + +static void +Opcode_madd_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900300; +} + +static void +Opcode_madd_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003c; + slotbuf[1] = 0xe; +} + +static void +Opcode_msub_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000020; + slotbuf[1] = 0x7; +} + +static void +Opcode_msub_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000020; + slotbuf[1] = 0x5; +} + +static void +Opcode_msub_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2300c00; + slotbuf[1] = 0; +} + +static void +Opcode_msub_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17001a0; +} + +static void +Opcode_msub_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac000080; + slotbuf[1] = 0; +} + +static void +Opcode_msub_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c000020; +} + +static void +Opcode_msub_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69003c0; +} + +static void +Opcode_msub_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003e; + slotbuf[1] = 0xe; +} + +static void +Opcode_msubn_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000020; + slotbuf[1] = 0x7; +} + +static void +Opcode_msubn_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44000020; + slotbuf[1] = 0x5; +} + +static void +Opcode_msubn_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0300c00; + slotbuf[1] = 0; +} + +static void +Opcode_msubn_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700180; +} + +static void +Opcode_msubn_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa000080; + slotbuf[1] = 0; +} + +static void +Opcode_msubn_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a000020; +} + +static void +Opcode_msubn_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69003a0; +} + +static void +Opcode_msubn_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003d; + slotbuf[1] = 0xe; +} + +static void +Opcode_maddn_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000020; + slotbuf[1] = 0x6; +} + +static void +Opcode_maddn_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000020; + slotbuf[1] = 0x4; +} + +static void +Opcode_maddn_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc300800; + slotbuf[1] = 0; +} + +static void +Opcode_maddn_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700140; +} + +static void +Opcode_maddn_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6000080; + slotbuf[1] = 0; +} + +static void +Opcode_maddn_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26000020; +} + +static void +Opcode_maddn_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69002e0; +} + +static void +Opcode_maddn_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003b; + slotbuf[1] = 0xe; +} + +static void +Opcode_add_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000022; + slotbuf[1] = 0x5; +} + +static void +Opcode_add_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000a0; + slotbuf[1] = 0x5; +} + +static void +Opcode_add_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a050000; + slotbuf[1] = 0; +} + +static void +Opcode_add_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1848000; +} + +static void +Opcode_add_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00021; + slotbuf[1] = 0; +} + +static void +Opcode_add_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000a0; +} + +static void +Opcode_add_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa048000; +} + +static void +Opcode_add_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068022; + slotbuf[1] = 0xe; +} + +static void +Opcode_sub_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000042; + slotbuf[1] = 0x5; +} + +static void +Opcode_sub_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000c0; + slotbuf[1] = 0x5; +} + +static void +Opcode_sub_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c050000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1870000; +} + +static void +Opcode_sub_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a000a1; + slotbuf[1] = 0; +} + +static void +Opcode_sub_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000c0; +} + +static void +Opcode_sub_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa050000; +} + +static void +Opcode_sub_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068042; + slotbuf[1] = 0xe; +} + +static void +Opcode_ole_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19200031; + slotbuf[1] = 0; +} + +static void +Opcode_ole_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640510; +} + +static void +Opcode_ole_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540081; +} + +static void +Opcode_ole_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022100; +} + +static void +Opcode_olt_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19240030; + slotbuf[1] = 0; +} + +static void +Opcode_olt_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640800; +} + +static void +Opcode_olt_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540090; +} + +static void +Opcode_olt_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022500; +} + +static void +Opcode_oeq_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19200030; + slotbuf[1] = 0; +} + +static void +Opcode_oeq_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640500; +} + +static void +Opcode_oeq_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540080; +} + +static void +Opcode_oeq_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022c00; +} + +static void +Opcode_un_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192c0030; + slotbuf[1] = 0; +} + +static void +Opcode_un_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640c00; +} + +static void +Opcode_un_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b0; +} + +static void +Opcode_un_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022600; +} + +static void +Opcode_ule_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19280030; + slotbuf[1] = 0; +} + +static void +Opcode_ule_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640900; +} + +static void +Opcode_ule_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400a0; +} + +static void +Opcode_ule_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022d00; +} + +static void +Opcode_ult_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19280031; + slotbuf[1] = 0; +} + +static void +Opcode_ult_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640910; +} + +static void +Opcode_ult_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400a1; +} + +static void +Opcode_ult_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022200; +} + +static void +Opcode_ueq_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19240031; + slotbuf[1] = 0; +} + +static void +Opcode_ueq_s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10640810; +} + +static void +Opcode_ueq_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540091; +} + +static void +Opcode_ueq_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022900; +} + +static void +Opcode_nexp01_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808008; + slotbuf[1] = 0x7; +} + +static void +Opcode_nexp01_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160004; + slotbuf[1] = 0x5; +} + +static void +Opcode_nexp01_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80211801; + slotbuf[1] = 0; +} + +static void +Opcode_nexp01_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700202; +} + +static void +Opcode_nexp01_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0c08001; + slotbuf[1] = 0; +} + +static void +Opcode_nexp01_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c45801d; +} + +static void +Opcode_nexp01_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa600026; +} + +static void +Opcode_nexp01_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40381002; + slotbuf[1] = 0xe; +} + +static void +Opcode_mksadj_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808004; + slotbuf[1] = 0x7; +} + +static void +Opcode_mksadj_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160003; + slotbuf[1] = 0x5; +} + +static void +Opcode_mksadj_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80111801; + slotbuf[1] = 0; +} + +static void +Opcode_mksadj_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700201; +} + +static void +Opcode_mksadj_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8c08001; + slotbuf[1] = 0; +} + +static void +Opcode_mksadj_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c35801d; +} + +static void +Opcode_mksadj_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa500026; +} + +static void +Opcode_mksadj_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40281002; + slotbuf[1] = 0xe; +} + +static void +Opcode_mkdadj_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000062; + slotbuf[1] = 0x6; +} + +static void +Opcode_mkdadj_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000e2; + slotbuf[1] = 0x5; +} + +static void +Opcode_mkdadj_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6390c00; + slotbuf[1] = 0; +} + +static void +Opcode_mkdadj_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17901e0; +} + +static void +Opcode_mkdadj_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab002c1; + slotbuf[1] = 0; +} + +static void +Opcode_mkdadj_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000e2; +} + +static void +Opcode_mkdadj_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa458000; +} + +static void +Opcode_mkdadj_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068862; + slotbuf[1] = 0xe; +} + +static void +Opcode_div0_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808003; + slotbuf[1] = 0x7; +} + +static void +Opcode_div0_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160001; + slotbuf[1] = 0x5; +} + +static void +Opcode_div0_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80011801; + slotbuf[1] = 0; +} + +static void +Opcode_div0_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700200; +} + +static void +Opcode_div0_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6c08001; + slotbuf[1] = 0; +} + +static void +Opcode_div0_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c15801d; +} + +static void +Opcode_div0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa500025; +} + +static void +Opcode_div0_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401f1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_sqrt0_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800b; + slotbuf[1] = 0x7; +} + +static void +Opcode_sqrt0_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160007; + slotbuf[1] = 0x5; +} + +static void +Opcode_sqrt0_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80511801; + slotbuf[1] = 0; +} + +static void +Opcode_sqrt0_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700205; +} + +static void +Opcode_sqrt0_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6c08001; + slotbuf[1] = 0; +} + +static void +Opcode_sqrt0_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c75801d; +} + +static void +Opcode_sqrt0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa700025; +} + +static void +Opcode_sqrt0_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40291002; + slotbuf[1] = 0xe; +} + +static void +Opcode_recip0_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808009; + slotbuf[1] = 0x7; +} + +static void +Opcode_recip0_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160005; + slotbuf[1] = 0x5; +} + +static void +Opcode_recip0_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80311801; + slotbuf[1] = 0; +} + +static void +Opcode_recip0_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700203; +} + +static void +Opcode_recip0_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2c08001; + slotbuf[1] = 0; +} + +static void +Opcode_recip0_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c55801d; +} + +static void +Opcode_recip0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa600027; +} + +static void +Opcode_recip0_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40289002; + slotbuf[1] = 0xe; +} + +static void +Opcode_rsqrt0_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800a; + slotbuf[1] = 0x7; +} + +static void +Opcode_rsqrt0_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160006; + slotbuf[1] = 0x5; +} + +static void +Opcode_rsqrt0_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80411801; + slotbuf[1] = 0; +} + +static void +Opcode_rsqrt0_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700204; +} + +static void +Opcode_rsqrt0_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4c08001; + slotbuf[1] = 0; +} + +static void +Opcode_rsqrt0_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c65801d; +} + +static void +Opcode_rsqrt0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa700024; +} + +static void +Opcode_rsqrt0_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40389002; + slotbuf[1] = 0xe; +} + +static void +Opcode_divn_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000020; + slotbuf[1] = 0x6; +} + +static void +Opcode_divn_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000020; + slotbuf[1] = 0x4; +} + +static void +Opcode_divn_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa300800; + slotbuf[1] = 0; +} + +static void +Opcode_divn_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700120; +} + +static void +Opcode_divn_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4000080; + slotbuf[1] = 0; +} + +static void +Opcode_divn_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000020; +} + +static void +Opcode_divn_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69002c0; +} + +static void +Opcode_divn_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010003a; + slotbuf[1] = 0xe; +} + +static void +Opcode_addexp_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000061; + slotbuf[1] = 0x6; +} + +static void +Opcode_addexp_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000e1; + slotbuf[1] = 0x5; +} + +static void +Opcode_addexp_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6388c00; + slotbuf[1] = 0; +} + +static void +Opcode_addexp_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17881e0; +} + +static void +Opcode_addexp_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00261; + slotbuf[1] = 0; +} + +static void +Opcode_addexp_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000e1; +} + +static void +Opcode_addexp_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa358000; +} + +static void +Opcode_addexp_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068462; + slotbuf[1] = 0xe; +} + +static void +Opcode_addexpm_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000060; + slotbuf[1] = 0x6; +} + +static void +Opcode_addexpm_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000e0; + slotbuf[1] = 0x5; +} + +static void +Opcode_addexpm_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6380c00; + slotbuf[1] = 0; +} + +static void +Opcode_addexpm_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17801e0; +} + +static void +Opcode_addexpm_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00241; + slotbuf[1] = 0; +} + +static void +Opcode_addexpm_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000e0; +} + +static void +Opcode_addexpm_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa258000; +} + +static void +Opcode_addexpm_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068062; + slotbuf[1] = 0xe; +} + +static void +Opcode_min_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000040; + slotbuf[1] = 0x6; +} + +static void +Opcode_min_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205001b; + slotbuf[1] = 0x5; +} + +static void +Opcode_min_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c048000; + slotbuf[1] = 0; +} + +static void +Opcode_min_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1830000; +} + +static void +Opcode_min_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00141; + slotbuf[1] = 0; +} + +static void +Opcode_min_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05001b; +} + +static void +Opcode_min_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa030000; +} + +static void +Opcode_min_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400d8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_max_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000060; + slotbuf[1] = 0x6; +} + +static void +Opcode_max_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82058019; + slotbuf[1] = 0x5; +} + +static void +Opcode_max_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e040000; + slotbuf[1] = 0; +} + +static void +Opcode_max_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1818000; +} + +static void +Opcode_max_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00181; + slotbuf[1] = 0; +} + +static void +Opcode_max_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c058019; +} + +static void +Opcode_max_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa018000; +} + +static void +Opcode_max_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_mulmux_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulmux_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000020; + slotbuf[1] = 0x4; +} + +static void +Opcode_mulmux_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0300000; + slotbuf[1] = 0; +} + +static void +Opcode_mulmux_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000080; + slotbuf[1] = 0; +} + +static void +Opcode_mulmux_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000020; +} + +static void +Opcode_mulmux_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e00000; +} + +static void +Opcode_mulmux_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80100038; + slotbuf[1] = 0xe; +} + +static void +Opcode_maddmux_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_maddmux_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_maddmux_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0300000; + slotbuf[1] = 0; +} + +static void +Opcode_maddmux_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000000; + slotbuf[1] = 0; +} + +static void +Opcode_maddmux_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000000; +} + +static void +Opcode_maddmux_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c00000; +} + +static void +Opcode_maddmux_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000038; + slotbuf[1] = 0xe; +} + +static void +Opcode_trunc_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19030010; + slotbuf[1] = 0; +} + +static void +Opcode_trunc_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800010; +} + +static void +Opcode_trunc_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a1308; +} + +static void +Opcode_utrunc_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19032010; + slotbuf[1] = 0; +} + +static void +Opcode_utrunc_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2802010; +} + +static void +Opcode_utrunc_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83a9208; +} + +static void +Opcode_trunc_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000024; + slotbuf[1] = 0; +} + +static void +Opcode_trunc_sx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800002; +} + +static void +Opcode_trunc_sx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c06000; +} + +static void +Opcode_utrunc_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900002c; + slotbuf[1] = 0; +} + +static void +Opcode_utrunc_sx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800006; +} + +static void +Opcode_utrunc_sx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c02001; +} + +static void +Opcode_ficeil_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190c002a; + slotbuf[1] = 0; +} + +static void +Opcode_ficeil_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400b9; +} + +static void +Opcode_ficeil_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62a2b00; +} + +static void +Opcode_fifloor_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190c002e; + slotbuf[1] = 0; +} + +static void +Opcode_fifloor_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400bb; +} + +static void +Opcode_fifloor_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62a2f00; +} + +static void +Opcode_firint_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19100022; + slotbuf[1] = 0; +} + +static void +Opcode_firint_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400bd; +} + +static void +Opcode_firint_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63a2b00; +} + +static void +Opcode_firound_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19100026; + slotbuf[1] = 0; +} + +static void +Opcode_firound_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400bf; +} + +static void +Opcode_firound_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63a2f00; +} + +static void +Opcode_fitrunc_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1910002a; + slotbuf[1] = 0; +} + +static void +Opcode_fitrunc_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800008; +} + +static void +Opcode_fitrunc_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7380f00; +} + +static void +Opcode_float_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18800b00; + slotbuf[1] = 0; +} + +static void +Opcode_float_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000000; +} + +static void +Opcode_float_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00100; +} + +static void +Opcode_ufloat_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18800b04; + slotbuf[1] = 0; +} + +static void +Opcode_ufloat_s_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000002; +} + +static void +Opcode_ufloat_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00140; +} + +static void +Opcode_float_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000020; + slotbuf[1] = 0; +} + +static void +Opcode_float_sx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800000; +} + +static void +Opcode_float_sx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04000; +} + +static void +Opcode_ufloat_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000028; + slotbuf[1] = 0; +} + +static void +Opcode_ufloat_sx2_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800004; +} + +static void +Opcode_ufloat_sx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00001; +} + +static void +Opcode_abs_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808000; + slotbuf[1] = 0x7; +} + +static void +Opcode_abs_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160008; + slotbuf[1] = 0x5; +} + +static void +Opcode_abs_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000a; + slotbuf[1] = 0; +} + +static void +Opcode_abs_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80611801; + slotbuf[1] = 0; +} + +static void +Opcode_abs_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700206; +} + +static void +Opcode_abs_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c08001; + slotbuf[1] = 0; +} + +static void +Opcode_abs_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c85801d; +} + +static void +Opcode_abs_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa400026; +} + +static void +Opcode_abs_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40391002; + slotbuf[1] = 0xe; +} + +static void +Opcode_neg_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808007; + slotbuf[1] = 0x7; +} + +static void +Opcode_neg_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000d; + slotbuf[1] = 0x5; +} + +static void +Opcode_neg_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2800a; + slotbuf[1] = 0; +} + +static void +Opcode_neg_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80b11801; + slotbuf[1] = 0; +} + +static void +Opcode_neg_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020b; +} + +static void +Opcode_neg_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcec08001; + slotbuf[1] = 0; +} + +static void +Opcode_neg_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cd5801d; +} + +static void +Opcode_neg_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa600025; +} + +static void +Opcode_neg_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402a9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_conjc_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808002; + slotbuf[1] = 0x7; +} + +static void +Opcode_conjc_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000a; + slotbuf[1] = 0x5; +} + +static void +Opcode_conjc_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d1000a; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80811801; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700208; +} + +static void +Opcode_conjc_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4c08001; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca5801d; +} + +static void +Opcode_conjc_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa500024; +} + +static void +Opcode_conjc_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40399002; + slotbuf[1] = 0xe; +} + +static void +Opcode_muljc_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808006; + slotbuf[1] = 0x7; +} + +static void +Opcode_muljc_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000c; + slotbuf[1] = 0x5; +} + +static void +Opcode_muljc_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2000a; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80a11801; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020a; +} + +static void +Opcode_muljc_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xccc08001; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc5801d; +} + +static void +Opcode_muljc_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa600024; +} + +static void +Opcode_muljc_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403a1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_const_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808011; + slotbuf[1] = 0x7; +} + +static void +Opcode_const_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160013; + slotbuf[1] = 0x5; +} + +static void +Opcode_const_s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3000b; + slotbuf[1] = 0; +} + +static void +Opcode_const_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81011a01; + slotbuf[1] = 0; +} + +static void +Opcode_const_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700211; +} + +static void +Opcode_const_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdec0c001; + slotbuf[1] = 0; +} + +static void +Opcode_const_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d25c01d; +} + +static void +Opcode_const_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00025; +} + +static void +Opcode_const_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44300003; + slotbuf[1] = 0xe; +} + +static void +Opcode_clsfy_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82810000; + slotbuf[1] = 0x7; +} + +static void +Opcode_clsfy_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160000; + slotbuf[1] = 0x5; +} + +static void +Opcode_clsfy_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e050000; + slotbuf[1] = 0; +} + +static void +Opcode_clsfy_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1878000; +} + +static void +Opcode_clsfy_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c10001; + slotbuf[1] = 0; +} + +static void +Opcode_clsfy_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05801d; +} + +static void +Opcode_clsfy_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000021; +} + +static void +Opcode_clsfy_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401e9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_minnum_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000060; + slotbuf[1] = 0x6; +} + +static void +Opcode_minnum_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205801a; + slotbuf[1] = 0x5; +} + +static void +Opcode_minnum_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a048000; + slotbuf[1] = 0; +} + +static void +Opcode_minnum_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1828000; +} + +static void +Opcode_minnum_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a000c1; + slotbuf[1] = 0; +} + +static void +Opcode_minnum_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05801a; +} + +static void +Opcode_minnum_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa028000; +} + +static void +Opcode_minnum_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400d0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_maxnum_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000040; + slotbuf[1] = 0x6; +} + +static void +Opcode_maxnum_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82050019; + slotbuf[1] = 0x5; +} + +static void +Opcode_maxnum_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c040000; + slotbuf[1] = 0; +} + +static void +Opcode_maxnum_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1810000; +} + +static void +Opcode_maxnum_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00101; + slotbuf[1] = 0; +} + +static void +Opcode_maxnum_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c050019; +} + +static void +Opcode_maxnum_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa010000; +} + +static void +Opcode_maxnum_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400b8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_addandsub_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000001; + slotbuf[1] = 0x5; +} + +static void +Opcode_addandsub_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82048000; + slotbuf[1] = 0x5; +} + +static void +Opcode_addandsub_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80019000; + slotbuf[1] = 0; +} + +static void +Opcode_addandsub_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addandsub_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0900001; + slotbuf[1] = 0; +} + +static void +Opcode_addandsub_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c048000; +} + +static void +Opcode_addandsub_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000140; +} + +static void +Opcode_addandsub_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40048002; + slotbuf[1] = 0xe; +} + +static void +Opcode_addandsubjc_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_addandsubjc_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82040000; + slotbuf[1] = 0x5; +} + +static void +Opcode_addandsubjc_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80011000; + slotbuf[1] = 0; +} + +static void +Opcode_addandsubjc_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_addandsubjc_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0800001; + slotbuf[1] = 0; +} + +static void +Opcode_addandsubjc_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c040000; +} + +static void +Opcode_addandsubjc_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000120; +} + +static void +Opcode_addandsubjc_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40060002; + slotbuf[1] = 0xe; +} + +static void +Opcode_add_hl_lh_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000002; + slotbuf[1] = 0x5; +} + +static void +Opcode_add_hl_lh_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000080; + slotbuf[1] = 0x5; +} + +static void +Opcode_add_hl_lh_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88050000; + slotbuf[1] = 0; +} + +static void +Opcode_add_hl_lh_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1840000; +} + +static void +Opcode_add_hl_lh_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a001c1; + slotbuf[1] = 0; +} + +static void +Opcode_add_hl_lh_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000080; +} + +static void +Opcode_add_hl_lh_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa040000; +} + +static void +Opcode_add_hl_lh_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068002; + slotbuf[1] = 0xe; +} + +static void +Opcode_madda_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_madda_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_madda_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000000; + slotbuf[1] = 0; +} + +static void +Opcode_madda_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000000; + slotbuf[1] = 0; +} + +static void +Opcode_madda_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000000; +} + +static void +Opcode_madda_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5800000; +} + +static void +Opcode_madda_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000034; + slotbuf[1] = 0xe; +} + +static void +Opcode_frexp_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000040; + slotbuf[1] = 0x6; +} + +static void +Opcode_frexp_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82050018; + slotbuf[1] = 0x5; +} + +static void +Opcode_frexp_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88040000; + slotbuf[1] = 0; +} + +static void +Opcode_frexp_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800000; +} + +static void +Opcode_frexp_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00001; + slotbuf[1] = 0; +} + +static void +Opcode_frexp_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c050018; +} + +static void +Opcode_frexp_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; +} + +static void +Opcode_frexp_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400a8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_floatexp_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82810020; + slotbuf[1] = 0x7; +} + +static void +Opcode_floatexp_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160002; + slotbuf[1] = 0x5; +} + +static void +Opcode_floatexp_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e050001; + slotbuf[1] = 0; +} + +static void +Opcode_floatexp_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1878001; +} + +static void +Opcode_floatexp_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c10021; + slotbuf[1] = 0; +} + +static void +Opcode_floatexp_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c25801d; +} + +static void +Opcode_floatexp_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa008021; +} + +static void +Opcode_floatexp_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401f9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_minnumabs_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000040; + slotbuf[1] = 0x6; +} + +static void +Opcode_minnumabs_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205001a; + slotbuf[1] = 0x5; +} + +static void +Opcode_minnumabs_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88048000; + slotbuf[1] = 0; +} + +static void +Opcode_minnumabs_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1820000; +} + +static void +Opcode_minnumabs_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00041; + slotbuf[1] = 0; +} + +static void +Opcode_minnumabs_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05001a; +} + +static void +Opcode_minnumabs_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa020000; +} + +static void +Opcode_minnumabs_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_maxnumabs_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000060; + slotbuf[1] = 0x6; +} + +static void +Opcode_maxnumabs_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82058018; + slotbuf[1] = 0x5; +} + +static void +Opcode_maxnumabs_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a040000; + slotbuf[1] = 0; +} + +static void +Opcode_maxnumabs_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1808000; +} + +static void +Opcode_maxnumabs_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0a00081; + slotbuf[1] = 0; +} + +static void +Opcode_maxnumabs_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c058018; +} + +static void +Opcode_maxnumabs_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa008000; +} + +static void +Opcode_maxnumabs_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400b0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_mulq_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_mulq_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulq_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98000000; + slotbuf[1] = 0; +} + +static void +Opcode_mulq_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000000; +} + +static void +Opcode_maddq_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_maddq_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_maddq_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94000000; + slotbuf[1] = 0; +} + +static void +Opcode_maddq_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000000; +} + +static void +Opcode_msubq_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_msubq_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_msubq_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96000000; + slotbuf[1] = 0; +} + +static void +Opcode_msubq_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000000; +} + +static void +Opcode_mulmuxq_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulmuxq_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_mulmuxq_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000000; + slotbuf[1] = 0; +} + +static void +Opcode_mulmuxq_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; +} + +static void +Opcode_maddmuxq_s_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x6; +} + +static void +Opcode_maddmuxq_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4; +} + +static void +Opcode_maddmuxq_s_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0; +} + +static void +Opcode_maddmuxq_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_bmaxnum_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82058008; + slotbuf[1] = 0x5; +} + +static void +Opcode_bmaxnum_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82040000; + slotbuf[1] = 0; +} + +static void +Opcode_bmaxnum_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c058008; +} + +static void +Opcode_bmaxnum_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c0402; + slotbuf[1] = 0xe; +} + +static void +Opcode_bminnum_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82058010; + slotbuf[1] = 0x5; +} + +static void +Opcode_bminnum_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86040000; + slotbuf[1] = 0; +} + +static void +Opcode_bminnum_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c058010; +} + +static void +Opcode_bminnum_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c0802; + slotbuf[1] = 0xe; +} + +static void +Opcode_bmaxnumabs_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82058000; + slotbuf[1] = 0x5; +} + +static void +Opcode_bmaxnumabs_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80040000; + slotbuf[1] = 0; +} + +static void +Opcode_bmaxnumabs_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c058000; +} + +static void +Opcode_bmaxnumabs_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40080402; + slotbuf[1] = 0xe; +} + +static void +Opcode_bminnumabs_s_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82050010; + slotbuf[1] = 0x5; +} + +static void +Opcode_bminnumabs_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84040000; + slotbuf[1] = 0; +} + +static void +Opcode_bminnumabs_s_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c050010; +} + +static void +Opcode_bminnumabs_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40080802; + slotbuf[1] = 0xe; +} + +static void +Opcode_abs_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82100000; + slotbuf[1] = 0x7; +} + +static void +Opcode_abs_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82008000; + slotbuf[1] = 0x5; +} + +static void +Opcode_abs_sx2x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80018000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_sx2x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_abs_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0100001; + slotbuf[1] = 0; +} + +static void +Opcode_abs_sx2x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c008000; +} + +static void +Opcode_abs_sx2x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000020; +} + +static void +Opcode_abs_sx2x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40008002; + slotbuf[1] = 0xe; +} + +static void +Opcode_neg_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82700000; + slotbuf[1] = 0x7; +} + +static void +Opcode_neg_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82038000; + slotbuf[1] = 0x5; +} + +static void +Opcode_neg_sx2x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400000; + slotbuf[1] = 0; +} + +static void +Opcode_neg_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80018c00; + slotbuf[1] = 0; +} + +static void +Opcode_neg_sx2x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_neg_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0700001; + slotbuf[1] = 0; +} + +static void +Opcode_neg_sx2x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c038000; +} + +static void +Opcode_neg_sx2x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000e0; +} + +static void +Opcode_neg_sx2x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40040002; + slotbuf[1] = 0xe; +} + +static void +Opcode_conjc_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82300000; + slotbuf[1] = 0x7; +} + +static void +Opcode_conjc_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82018000; + slotbuf[1] = 0x5; +} + +static void +Opcode_conjc_sx2x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80018400; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_sx2x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_conjc_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0300001; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_sx2x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c018000; +} + +static void +Opcode_conjc_sx2x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000060; +} + +static void +Opcode_conjc_sx2x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40010002; + slotbuf[1] = 0xe; +} + +static void +Opcode_muljc_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82500000; + slotbuf[1] = 0x7; +} + +static void +Opcode_muljc_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82028000; + slotbuf[1] = 0x5; +} + +static void +Opcode_muljc_sx2x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1200000; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80018800; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_sx2x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_muljc_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0500001; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_sx2x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c028000; +} + +static void +Opcode_muljc_sx2x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000a0; +} + +static void +Opcode_muljc_sx2x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40018002; + slotbuf[1] = 0xe; +} + +static void +Opcode_const_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82804000; + slotbuf[1] = 0x7; +} + +static void +Opcode_const_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82064000; + slotbuf[1] = 0x5; +} + +static void +Opcode_const_sx2x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00003; + slotbuf[1] = 0; +} + +static void +Opcode_const_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80011a00; + slotbuf[1] = 0; +} + +static void +Opcode_const_sx2x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1904001; +} + +static void +Opcode_const_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c04001; + slotbuf[1] = 0; +} + +static void +Opcode_const_sx2x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c064000; +} + +static void +Opcode_const_sx2x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa004020; +} + +static void +Opcode_const_sx2x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46000003; + slotbuf[1] = 0xe; +} + +static void +Opcode_add_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_add_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_add_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_sub_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_sub_sx2x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_sx2x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0; +} + +static void +Opcode_mul_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x3; +} + +static void +Opcode_mul_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x3; +} + +static void +Opcode_madd_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_madd_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_msub_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_msub_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x2; +} + +static void +Opcode_mulmux_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_mulmux_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x2; +} + +static void +Opcode_maddmux_sx2x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_maddmux_sx2x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0; +} + +static void +Opcode_abs_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800c; + slotbuf[1] = 0x7; +} + +static void +Opcode_abs_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000e; + slotbuf[1] = 0x5; +} + +static void +Opcode_abs_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03001; + slotbuf[1] = 0; +} + +static void +Opcode_abs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80c11801; + slotbuf[1] = 0; +} + +static void +Opcode_abs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020c; +} + +static void +Opcode_abs_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8c08001; + slotbuf[1] = 0; +} + +static void +Opcode_abs_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce5801d; +} + +static void +Opcode_abs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf58000; +} + +static void +Opcode_abs_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403a9002; + slotbuf[1] = 0xe; +} + +static void +Opcode_addexp_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000064; + slotbuf[1] = 0x6; +} + +static void +Opcode_addexp_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000e4; + slotbuf[1] = 0x5; +} + +static void +Opcode_addexp_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63f0c00; + slotbuf[1] = 0; +} + +static void +Opcode_addexp_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a01e0; +} + +static void +Opcode_addexp_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab00341; + slotbuf[1] = 0; +} + +static void +Opcode_addexp_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000e4; +} + +static void +Opcode_addexp_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa700027; +} + +static void +Opcode_addexp_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40069062; + slotbuf[1] = 0xe; +} + +static void +Opcode_addexpm_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000063; + slotbuf[1] = 0x6; +} + +static void +Opcode_addexpm_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000e3; + slotbuf[1] = 0x5; +} + +static void +Opcode_addexpm_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc63e8c00; + slotbuf[1] = 0; +} + +static void +Opcode_addexpm_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17981e0; +} + +static void +Opcode_addexpm_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcab002e1; + slotbuf[1] = 0; +} + +static void +Opcode_addexpm_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000e3; +} + +static void +Opcode_addexpm_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa700026; +} + +static void +Opcode_addexpm_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40068c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_clsfy_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800d; + slotbuf[1] = 0x7; +} + +static void +Opcode_clsfy_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000f; + slotbuf[1] = 0x5; +} + +static void +Opcode_clsfy_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80d11801; + slotbuf[1] = 0; +} + +static void +Opcode_clsfy_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020d; +} + +static void +Opcode_clsfy_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdac08001; + slotbuf[1] = 0; +} + +static void +Opcode_clsfy_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cf5801d; +} + +static void +Opcode_clsfy_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb058000; +} + +static void +Opcode_clsfy_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402b1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_conjc_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808001; + slotbuf[1] = 0x7; +} + +static void +Opcode_conjc_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160009; + slotbuf[1] = 0x5; +} + +static void +Opcode_conjc_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0800a; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80711801; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700207; +} + +static void +Opcode_conjc_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2c08001; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c95801d; +} + +static void +Opcode_conjc_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa400027; +} + +static void +Opcode_conjc_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40299002; + slotbuf[1] = 0xe; +} + +static void +Opcode_const_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808010; + slotbuf[1] = 0x7; +} + +static void +Opcode_const_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160012; + slotbuf[1] = 0x5; +} + +static void +Opcode_const_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3000a; + slotbuf[1] = 0; +} + +static void +Opcode_const_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81011801; + slotbuf[1] = 0; +} + +static void +Opcode_const_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700210; +} + +static void +Opcode_const_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdec08001; + slotbuf[1] = 0; +} + +static void +Opcode_const_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d25801d; +} + +static void +Opcode_const_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab00024; +} + +static void +Opcode_const_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44200003; + slotbuf[1] = 0xe; +} + +static void +Opcode_min_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4100003; + slotbuf[1] = 0x6; +} + +static void +Opcode_min_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205001d; + slotbuf[1] = 0x5; +} + +static void +Opcode_min_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80119400; + slotbuf[1] = 0; +} + +static void +Opcode_min_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700100; +} + +static void +Opcode_min_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6b00001; + slotbuf[1] = 0; +} + +static void +Opcode_min_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05001d; +} + +static void +Opcode_min_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900380; +} + +static void +Opcode_min_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400f8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_max_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000003; + slotbuf[1] = 0x6; +} + +static void +Opcode_max_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205001c; + slotbuf[1] = 0x5; +} + +static void +Opcode_max_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80019400; + slotbuf[1] = 0; +} + +static void +Opcode_max_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000c0; +} + +static void +Opcode_max_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2b00001; + slotbuf[1] = 0; +} + +static void +Opcode_max_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05001c; +} + +static void +Opcode_max_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900340; +} + +static void +Opcode_max_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400e8c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_minnum_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4100002; + slotbuf[1] = 0x6; +} + +static void +Opcode_minnum_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205801c; + slotbuf[1] = 0x5; +} + +static void +Opcode_minnum_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80111400; + slotbuf[1] = 0; +} + +static void +Opcode_minnum_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000e0; +} + +static void +Opcode_minnum_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4b00001; + slotbuf[1] = 0; +} + +static void +Opcode_minnum_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05801c; +} + +static void +Opcode_minnum_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900360; +} + +static void +Opcode_minnum_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400f0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_maxnum_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000002; + slotbuf[1] = 0x6; +} + +static void +Opcode_maxnum_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8205801b; + slotbuf[1] = 0x5; +} + +static void +Opcode_maxnum_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80011400; + slotbuf[1] = 0; +} + +static void +Opcode_maxnum_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000a0; +} + +static void +Opcode_maxnum_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0b00001; + slotbuf[1] = 0; +} + +static void +Opcode_maxnum_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c05801b; +} + +static void +Opcode_maxnum_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6900320; +} + +static void +Opcode_maxnum_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400e0c02; + slotbuf[1] = 0xe; +} + +static void +Opcode_muljc_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82808005; + slotbuf[1] = 0x7; +} + +static void +Opcode_muljc_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8216000b; + slotbuf[1] = 0x5; +} + +static void +Opcode_muljc_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d1800a; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80911801; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1700209; +} + +static void +Opcode_muljc_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcac08001; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cb5801d; +} + +static void +Opcode_muljc_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa500027; +} + +static void +Opcode_muljc_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402a1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_neg_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8280800e; + slotbuf[1] = 0x7; +} + +static void +Opcode_neg_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82160010; + slotbuf[1] = 0x5; +} + +static void +Opcode_neg_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e03011; + slotbuf[1] = 0; +} + +static void +Opcode_neg_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80e11801; + slotbuf[1] = 0; +} + +static void +Opcode_neg_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170020e; +} + +static void +Opcode_neg_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdcc08001; + slotbuf[1] = 0; +} + +static void +Opcode_neg_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d05801d; +} + +static void +Opcode_neg_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb158000; +} + +static void +Opcode_neg_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403b1002; + slotbuf[1] = 0xe; +} + +static void +Opcode_oeq_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2e00; +} + +static void +Opcode_ole_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022300; +} + +static void +Opcode_olt_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022700; +} + +static void +Opcode_ueq_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022b00; +} + +static void +Opcode_ule_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6022f00; +} + +static void +Opcode_ult_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2300; +} + +static void +Opcode_un_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60a2700; +} + +static void +Opcode_div0_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800027; +} + +static void +Opcode_ficeil_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19184030; + slotbuf[1] = 0; +} + +static void +Opcode_ficeil_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0430a; +} + +static void +Opcode_fifloor_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19186030; + slotbuf[1] = 0; +} + +static void +Opcode_fifloor_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0630a; +} + +static void +Opcode_firint_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1918c030; + slotbuf[1] = 0; +} + +static void +Opcode_firint_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0430b; +} + +static void +Opcode_firound_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1918e030; + slotbuf[1] = 0; +} + +static void +Opcode_firound_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0630b; +} + +static void +Opcode_fitrunc_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19194030; + slotbuf[1] = 0; +} + +static void +Opcode_fitrunc_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0020c; +} + +static void +Opcode_mkdadj_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb258000; +} + +static void +Opcode_mksadj_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa900024; +} + +static void +Opcode_nexp0_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa900026; +} + +static void +Opcode_nexp01_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa900025; +} + +static void +Opcode_recip0_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa900027; +} + +static void +Opcode_rsqrt0_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa00024; +} + +static void +Opcode_sqrt0_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa00025; +} + +static void +Opcode_float16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18980f00; + slotbuf[1] = 0; +} + +static void +Opcode_float16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c01200; +} + +static void +Opcode_ufloat16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x189a0f00; + slotbuf[1] = 0; +} + +static void +Opcode_ufloat16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c01240; +} + +static void +Opcode_trunc16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19300030; + slotbuf[1] = 0; +} + +static void +Opcode_trunc16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c01208; +} + +static void +Opcode_utrunc16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19320030; + slotbuf[1] = 0; +} + +static void +Opcode_utrunc16_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c01608; +} + +static void +Opcode_float16_hx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d820000; + slotbuf[1] = 0; +} + +static void +Opcode_float16_hx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c00200; +} + +static void +Opcode_ufloat16_hx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d820020; + slotbuf[1] = 0; +} + +static void +Opcode_ufloat16_hx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c04200; +} + +static void +Opcode_trunc16_hx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d820010; + slotbuf[1] = 0; +} + +static void +Opcode_trunc16_hx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c02200; +} + +static void +Opcode_utrunc16_hx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d820030; + slotbuf[1] = 0; +} + +static void +Opcode_utrunc16_hx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c06200; +} + +static void +Opcode_add_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000001; + slotbuf[1] = 0x6; +} + +static void +Opcode_add_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000040; + slotbuf[1] = 0x5; +} + +static void +Opcode_add_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0118000; + slotbuf[1] = 0; +} + +static void +Opcode_add_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1838000; +} + +static void +Opcode_add_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000080; + slotbuf[1] = 0; +} + +static void +Opcode_add_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000040; +} + +static void +Opcode_add_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8148000; +} + +static void +Opcode_add_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_sub_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000a1; + slotbuf[1] = 0x6; +} + +static void +Opcode_sub_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000062; + slotbuf[1] = 0x5; +} + +static void +Opcode_sub_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc118000; + slotbuf[1] = 0; +} + +static void +Opcode_sub_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1868000; +} + +static void +Opcode_sub_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000085; + slotbuf[1] = 0; +} + +static void +Opcode_sub_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000062; +} + +static void +Opcode_sub_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8178000; +} + +static void +Opcode_sub_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80006062; + slotbuf[1] = 0xe; +} + +static void +Opcode_mul_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000081; + slotbuf[1] = 0x6; +} + +static void +Opcode_mul_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000042; + slotbuf[1] = 0x5; +} + +static void +Opcode_mul_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca118000; + slotbuf[1] = 0; +} + +static void +Opcode_mul_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1860000; +} + +static void +Opcode_mul_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000084; + slotbuf[1] = 0; +} + +static void +Opcode_mul_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000042; +} + +static void +Opcode_mul_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8170000; +} + +static void +Opcode_mul_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005c62; + slotbuf[1] = 0xe; +} + +static void +Opcode_madd_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000021; + slotbuf[1] = 0x6; +} + +static void +Opcode_madd_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000060; + slotbuf[1] = 0x5; +} + +static void +Opcode_madd_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6118000; + slotbuf[1] = 0; +} + +static void +Opcode_madd_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1850000; +} + +static void +Opcode_madd_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000081; + slotbuf[1] = 0; +} + +static void +Opcode_madd_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000060; +} + +static void +Opcode_madd_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8160000; +} + +static void +Opcode_madd_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005062; + slotbuf[1] = 0xe; +} + +static void +Opcode_msub_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000061; + slotbuf[1] = 0x6; +} + +static void +Opcode_msub_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000061; + slotbuf[1] = 0x5; +} + +static void +Opcode_msub_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8118000; + slotbuf[1] = 0; +} + +static void +Opcode_msub_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1858000; +} + +static void +Opcode_msub_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000083; + slotbuf[1] = 0; +} + +static void +Opcode_msub_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000061; +} + +static void +Opcode_msub_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8168000; +} + +static void +Opcode_msub_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005862; + slotbuf[1] = 0xe; +} + +static void +Opcode_maddn_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4118000; + slotbuf[1] = 0; +} + +static void +Opcode_maddn_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8158000; +} + +static void +Opcode_msubn_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000041; + slotbuf[1] = 0x6; +} + +static void +Opcode_msubn_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000041; + slotbuf[1] = 0x5; +} + +static void +Opcode_msubn_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000082; + slotbuf[1] = 0; +} + +static void +Opcode_msubn_h_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000041; +} + +static void +Opcode_msubn_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80005462; + slotbuf[1] = 0xe; +} + +static void +Opcode_divn_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2118000; + slotbuf[1] = 0; +} + +static void +Opcode_divn_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8150000; +} + +static void +Opcode_rminnum_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1919e030; + slotbuf[1] = 0; +} + +static void +Opcode_rminnum_h_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2540ae0; +} + +static void +Opcode_rminnum_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0620c; +} + +static void +Opcode_rmaxnum_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1919c030; + slotbuf[1] = 0; +} + +static void +Opcode_rmaxnum_h_Slot_ae9_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25406e0; +} + +static void +Opcode_rmaxnum_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0420c; +} + +static void +Opcode_abs_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000000; + slotbuf[1] = 0x7; +} + +static void +Opcode_abs_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000000; + slotbuf[1] = 0x5; +} + +static void +Opcode_abs_hx4x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_hx4x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80010000; + slotbuf[1] = 0; +} + +static void +Opcode_abs_hx4x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000001; + slotbuf[1] = 0; +} + +static void +Opcode_abs_hx4x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000000; +} + +static void +Opcode_abs_hx4x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; +} + +static void +Opcode_abs_hx4x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40020002; + slotbuf[1] = 0xe; +} + +static void +Opcode_neg_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82600000; + slotbuf[1] = 0x7; +} + +static void +Opcode_neg_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82030000; + slotbuf[1] = 0x5; +} + +static void +Opcode_neg_hx4x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1300000; + slotbuf[1] = 0; +} + +static void +Opcode_neg_hx4x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80010c00; + slotbuf[1] = 0; +} + +static void +Opcode_neg_hx4x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0600001; + slotbuf[1] = 0; +} + +static void +Opcode_neg_hx4x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c030000; +} + +static void +Opcode_neg_hx4x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000c0; +} + +static void +Opcode_neg_hx4x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40038002; + slotbuf[1] = 0xe; +} + +static void +Opcode_conjc_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82200000; + slotbuf[1] = 0x7; +} + +static void +Opcode_conjc_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82010000; + slotbuf[1] = 0x5; +} + +static void +Opcode_conjc_hx4x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_hx4x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80010400; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_hx4x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0200001; + slotbuf[1] = 0; +} + +static void +Opcode_conjc_hx4x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c010000; +} + +static void +Opcode_conjc_hx4x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000040; +} + +static void +Opcode_conjc_hx4x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40028002; + slotbuf[1] = 0xe; +} + +static void +Opcode_const_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82800000; + slotbuf[1] = 0x7; +} + +static void +Opcode_const_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82060000; + slotbuf[1] = 0x5; +} + +static void +Opcode_const_hx4x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00002; + slotbuf[1] = 0; +} + +static void +Opcode_const_hx4x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80011800; + slotbuf[1] = 0; +} + +static void +Opcode_const_hx4x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1904000; +} + +static void +Opcode_const_hx4x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0c00001; + slotbuf[1] = 0; +} + +static void +Opcode_const_hx4x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c060000; +} + +static void +Opcode_const_hx4x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000020; +} + +static void +Opcode_const_hx4x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44000003; + slotbuf[1] = 0xe; +} + +static void +Opcode_muljc_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82400000; + slotbuf[1] = 0x7; +} + +static void +Opcode_muljc_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82020000; + slotbuf[1] = 0x5; +} + +static void +Opcode_muljc_hx4x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_hx4x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80010800; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_hx4x2_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0400001; + slotbuf[1] = 0; +} + +static void +Opcode_muljc_hx4x2_Slot_ae9_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c020000; +} + +static void +Opcode_muljc_hx4x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000080; +} + +static void +Opcode_muljc_hx4x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40030002; + slotbuf[1] = 0xe; +} + +static void +Opcode_add_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_sub_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x4; +} + +static void +Opcode_mul_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x4; +} + +static void +Opcode_mul_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_madd_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_madd_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_msub_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_msub_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000000; + slotbuf[1] = 0x3; +} + +static void +Opcode_mulq_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulq_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulq_h_Slot_ae9_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a000000; + slotbuf[1] = 0; +} + +static void +Opcode_maddq_h_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x5; +} + +static void +Opcode_maddq_h_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulcnvh_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulcnvh_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulacnvh_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulacnvh_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulcnvl_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulcnvl_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; + slotbuf[1] = 0x6; +} + +static void +Opcode_mulacnvl_hx4x2_Slot_ae10_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40; + slotbuf[1] = 0x5; +} + +static void +Opcode_mulacnvl_hx4x2_Slot_ae10_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40; + slotbuf[1] = 0x6; +} + +static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { + Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { + Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0, Opcode_addi_Slot_ae_slot0_encode, Opcode_addi_Slot_ae_slot1_encode, 0, 0, Opcode_addi_Slot_ae2_slot0_encode, Opcode_addi_Slot_ae2_slot1_encode, 0, Opcode_addi_Slot_ae3_slot0_encode, Opcode_addi_Slot_ae3_slot1_encode, Opcode_addi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addi_Slot_ae8_slot0_encode, Opcode_addi_Slot_ae8_slot1_encode, 0, Opcode_addi_Slot_ae9_slot0_encode, Opcode_addi_Slot_ae9_slot1_encode, 0, 0, Opcode_addi_Slot_ae10_slot0_encode, Opcode_addi_Slot_ae10_slot1_encode, 0, 0, Opcode_addi_Slot_ae4_slot0_encode, Opcode_addi_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0, Opcode_addmi_Slot_ae_slot0_encode, Opcode_addmi_Slot_ae_slot1_encode, 0, 0, Opcode_addmi_Slot_ae2_slot0_encode, Opcode_addmi_Slot_ae2_slot1_encode, 0, Opcode_addmi_Slot_ae3_slot0_encode, Opcode_addmi_Slot_ae3_slot1_encode, Opcode_addmi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addmi_Slot_ae8_slot0_encode, Opcode_addmi_Slot_ae8_slot1_encode, 0, Opcode_addmi_Slot_ae9_slot0_encode, Opcode_addmi_Slot_ae9_slot1_encode, 0, 0, Opcode_addmi_Slot_ae10_slot0_encode, Opcode_addmi_Slot_ae10_slot1_encode, 0, 0, Opcode_addmi_Slot_ae4_slot0_encode, Opcode_addmi_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0, Opcode_add_Slot_ae_slot0_encode, Opcode_add_Slot_ae_slot1_encode, 0, 0, Opcode_add_Slot_ae2_slot0_encode, Opcode_add_Slot_ae2_slot1_encode, 0, Opcode_add_Slot_ae3_slot0_encode, Opcode_add_Slot_ae3_slot1_encode, Opcode_add_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_Slot_ae8_slot0_encode, Opcode_add_Slot_ae8_slot1_encode, 0, Opcode_add_Slot_ae9_slot0_encode, Opcode_add_Slot_ae9_slot1_encode, 0, 0, Opcode_add_Slot_ae10_slot0_encode, Opcode_add_Slot_ae10_slot1_encode, 0, 0, Opcode_add_Slot_ae4_slot0_encode, Opcode_add_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0, Opcode_addx2_Slot_ae_slot0_encode, Opcode_addx2_Slot_ae_slot1_encode, 0, 0, Opcode_addx2_Slot_ae2_slot0_encode, Opcode_addx2_Slot_ae2_slot1_encode, 0, Opcode_addx2_Slot_ae3_slot0_encode, Opcode_addx2_Slot_ae3_slot1_encode, Opcode_addx2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addx2_Slot_ae8_slot0_encode, Opcode_addx2_Slot_ae8_slot1_encode, 0, Opcode_addx2_Slot_ae9_slot0_encode, Opcode_addx2_Slot_ae9_slot1_encode, 0, 0, Opcode_addx2_Slot_ae10_slot0_encode, Opcode_addx2_Slot_ae10_slot1_encode, 0, 0, Opcode_addx2_Slot_ae4_slot0_encode, Opcode_addx2_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0, Opcode_addx4_Slot_ae_slot0_encode, Opcode_addx4_Slot_ae_slot1_encode, 0, 0, Opcode_addx4_Slot_ae2_slot0_encode, Opcode_addx4_Slot_ae2_slot1_encode, 0, Opcode_addx4_Slot_ae3_slot0_encode, Opcode_addx4_Slot_ae3_slot1_encode, Opcode_addx4_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addx4_Slot_ae8_slot0_encode, Opcode_addx4_Slot_ae8_slot1_encode, 0, Opcode_addx4_Slot_ae9_slot0_encode, Opcode_addx4_Slot_ae9_slot1_encode, 0, 0, Opcode_addx4_Slot_ae10_slot0_encode, Opcode_addx4_Slot_ae10_slot1_encode, 0, 0, Opcode_addx4_Slot_ae4_slot0_encode, Opcode_addx4_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0, Opcode_addx8_Slot_ae_slot0_encode, Opcode_addx8_Slot_ae_slot1_encode, 0, 0, Opcode_addx8_Slot_ae2_slot0_encode, Opcode_addx8_Slot_ae2_slot1_encode, 0, Opcode_addx8_Slot_ae3_slot0_encode, Opcode_addx8_Slot_ae3_slot1_encode, Opcode_addx8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addx8_Slot_ae8_slot0_encode, Opcode_addx8_Slot_ae8_slot1_encode, 0, Opcode_addx8_Slot_ae9_slot0_encode, Opcode_addx8_Slot_ae9_slot1_encode, 0, 0, Opcode_addx8_Slot_ae10_slot0_encode, Opcode_addx8_Slot_ae10_slot1_encode, 0, 0, Opcode_addx8_Slot_ae4_slot0_encode, Opcode_addx8_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0, Opcode_sub_Slot_ae_slot0_encode, Opcode_sub_Slot_ae_slot1_encode, 0, 0, Opcode_sub_Slot_ae2_slot0_encode, Opcode_sub_Slot_ae2_slot1_encode, 0, Opcode_sub_Slot_ae3_slot0_encode, Opcode_sub_Slot_ae3_slot1_encode, Opcode_sub_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_Slot_ae8_slot0_encode, Opcode_sub_Slot_ae8_slot1_encode, 0, Opcode_sub_Slot_ae9_slot0_encode, Opcode_sub_Slot_ae9_slot1_encode, 0, 0, Opcode_sub_Slot_ae10_slot0_encode, Opcode_sub_Slot_ae10_slot1_encode, 0, 0, Opcode_sub_Slot_ae4_slot0_encode, Opcode_sub_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0, Opcode_subx2_Slot_ae_slot0_encode, Opcode_subx2_Slot_ae_slot1_encode, 0, 0, Opcode_subx2_Slot_ae2_slot0_encode, Opcode_subx2_Slot_ae2_slot1_encode, 0, Opcode_subx2_Slot_ae3_slot0_encode, Opcode_subx2_Slot_ae3_slot1_encode, Opcode_subx2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_subx2_Slot_ae8_slot0_encode, Opcode_subx2_Slot_ae8_slot1_encode, 0, Opcode_subx2_Slot_ae9_slot0_encode, Opcode_subx2_Slot_ae9_slot1_encode, 0, 0, Opcode_subx2_Slot_ae10_slot0_encode, Opcode_subx2_Slot_ae10_slot1_encode, 0, 0, Opcode_subx2_Slot_ae4_slot0_encode, Opcode_subx2_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0, Opcode_subx4_Slot_ae_slot0_encode, Opcode_subx4_Slot_ae_slot1_encode, 0, 0, Opcode_subx4_Slot_ae2_slot0_encode, Opcode_subx4_Slot_ae2_slot1_encode, 0, Opcode_subx4_Slot_ae3_slot0_encode, Opcode_subx4_Slot_ae3_slot1_encode, Opcode_subx4_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_subx4_Slot_ae8_slot0_encode, Opcode_subx4_Slot_ae8_slot1_encode, 0, Opcode_subx4_Slot_ae9_slot0_encode, Opcode_subx4_Slot_ae9_slot1_encode, 0, 0, Opcode_subx4_Slot_ae10_slot0_encode, Opcode_subx4_Slot_ae10_slot1_encode, 0, 0, Opcode_subx4_Slot_ae4_slot0_encode, Opcode_subx4_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0, Opcode_subx8_Slot_ae_slot0_encode, Opcode_subx8_Slot_ae_slot1_encode, 0, 0, Opcode_subx8_Slot_ae2_slot0_encode, Opcode_subx8_Slot_ae2_slot1_encode, 0, Opcode_subx8_Slot_ae3_slot0_encode, Opcode_subx8_Slot_ae3_slot1_encode, Opcode_subx8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_subx8_Slot_ae8_slot0_encode, Opcode_subx8_Slot_ae8_slot1_encode, 0, Opcode_subx8_Slot_ae9_slot0_encode, Opcode_subx8_Slot_ae9_slot1_encode, 0, 0, Opcode_subx8_Slot_ae10_slot0_encode, Opcode_subx8_Slot_ae10_slot1_encode, 0, 0, Opcode_subx8_Slot_ae4_slot0_encode, Opcode_subx8_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0, Opcode_and_Slot_ae_slot0_encode, Opcode_and_Slot_ae_slot1_encode, 0, 0, Opcode_and_Slot_ae2_slot0_encode, Opcode_and_Slot_ae2_slot1_encode, 0, Opcode_and_Slot_ae3_slot0_encode, Opcode_and_Slot_ae3_slot1_encode, Opcode_and_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_and_Slot_ae8_slot0_encode, Opcode_and_Slot_ae8_slot1_encode, 0, Opcode_and_Slot_ae9_slot0_encode, Opcode_and_Slot_ae9_slot1_encode, 0, 0, Opcode_and_Slot_ae10_slot0_encode, Opcode_and_Slot_ae10_slot1_encode, 0, 0, Opcode_and_Slot_ae4_slot0_encode, Opcode_and_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0, Opcode_or_Slot_ae_slot0_encode, Opcode_or_Slot_ae_slot1_encode, 0, 0, Opcode_or_Slot_ae2_slot0_encode, Opcode_or_Slot_ae2_slot1_encode, 0, Opcode_or_Slot_ae3_slot0_encode, Opcode_or_Slot_ae3_slot1_encode, Opcode_or_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_or_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_or_Slot_ae8_slot0_encode, Opcode_or_Slot_ae8_slot1_encode, 0, Opcode_or_Slot_ae9_slot0_encode, Opcode_or_Slot_ae9_slot1_encode, 0, 0, Opcode_or_Slot_ae10_slot0_encode, Opcode_or_Slot_ae10_slot1_encode, 0, 0, Opcode_or_Slot_ae4_slot0_encode, Opcode_or_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0, Opcode_xor_Slot_ae_slot0_encode, Opcode_xor_Slot_ae_slot1_encode, 0, 0, Opcode_xor_Slot_ae2_slot0_encode, Opcode_xor_Slot_ae2_slot1_encode, 0, Opcode_xor_Slot_ae3_slot0_encode, Opcode_xor_Slot_ae3_slot1_encode, Opcode_xor_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_xor_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_xor_Slot_ae8_slot0_encode, Opcode_xor_Slot_ae8_slot1_encode, 0, Opcode_xor_Slot_ae9_slot0_encode, Opcode_xor_Slot_ae9_slot1_encode, 0, 0, Opcode_xor_Slot_ae10_slot0_encode, Opcode_xor_Slot_ae10_slot1_encode, 0, 0, Opcode_xor_Slot_ae4_slot0_encode, Opcode_xor_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0, Opcode_call0_Slot_ae_slot0_encode, 0, 0, 0, Opcode_call0_Slot_ae2_slot0_encode, 0, 0, Opcode_call0_Slot_ae3_slot0_encode, 0, Opcode_call0_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_call0_Slot_ae8_slot0_encode, 0, 0, Opcode_call0_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_call0_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_call0_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0, Opcode_callx0_Slot_ae_slot0_encode, 0, 0, 0, Opcode_callx0_Slot_ae2_slot0_encode, 0, 0, Opcode_callx0_Slot_ae3_slot0_encode, 0, Opcode_callx0_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_callx0_Slot_ae8_slot0_encode, 0, 0, Opcode_callx0_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_callx0_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_callx0_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0, Opcode_extui_Slot_ae_slot0_encode, Opcode_extui_Slot_ae_slot1_encode, 0, 0, Opcode_extui_Slot_ae2_slot0_encode, Opcode_extui_Slot_ae2_slot1_encode, 0, Opcode_extui_Slot_ae3_slot0_encode, Opcode_extui_Slot_ae3_slot1_encode, Opcode_extui_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_extui_Slot_ae8_slot0_encode, Opcode_extui_Slot_ae8_slot1_encode, 0, Opcode_extui_Slot_ae9_slot0_encode, Opcode_extui_Slot_ae9_slot1_encode, 0, 0, Opcode_extui_Slot_ae10_slot0_encode, Opcode_extui_Slot_ae10_slot1_encode, 0, 0, Opcode_extui_Slot_ae4_slot0_encode, Opcode_extui_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0, Opcode_j_Slot_ae_slot0_encode, 0, 0, 0, Opcode_j_Slot_ae2_slot0_encode, 0, 0, Opcode_j_Slot_ae3_slot0_encode, 0, Opcode_j_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_j_Slot_ae8_slot0_encode, 0, 0, Opcode_j_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_j_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_j_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0, Opcode_jx_Slot_ae_slot0_encode, 0, 0, 0, Opcode_jx_Slot_ae2_slot0_encode, 0, 0, Opcode_jx_Slot_ae3_slot0_encode, 0, Opcode_jx_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_jx_Slot_ae8_slot0_encode, 0, 0, Opcode_jx_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_jx_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_jx_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode, Opcode_l16ui_Slot_ae_slot1_encode, 0, 0, Opcode_l16ui_Slot_ae2_slot0_encode, Opcode_l16ui_Slot_ae2_slot1_encode, 0, Opcode_l16ui_Slot_ae3_slot0_encode, Opcode_l16ui_Slot_ae3_slot1_encode, Opcode_l16ui_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l16ui_Slot_ae8_slot0_encode, Opcode_l16ui_Slot_ae8_slot1_encode, 0, Opcode_l16ui_Slot_ae9_slot0_encode, Opcode_l16ui_Slot_ae9_slot1_encode, 0, 0, Opcode_l16ui_Slot_ae10_slot0_encode, Opcode_l16ui_Slot_ae10_slot1_encode, 0, 0, Opcode_l16ui_Slot_ae4_slot0_encode, Opcode_l16ui_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0, Opcode_l16si_Slot_ae_slot0_encode, Opcode_l16si_Slot_ae_slot1_encode, 0, 0, Opcode_l16si_Slot_ae2_slot0_encode, Opcode_l16si_Slot_ae2_slot1_encode, 0, Opcode_l16si_Slot_ae3_slot0_encode, Opcode_l16si_Slot_ae3_slot1_encode, Opcode_l16si_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l16si_Slot_ae8_slot0_encode, Opcode_l16si_Slot_ae8_slot1_encode, 0, Opcode_l16si_Slot_ae9_slot0_encode, Opcode_l16si_Slot_ae9_slot1_encode, 0, 0, Opcode_l16si_Slot_ae10_slot0_encode, Opcode_l16si_Slot_ae10_slot1_encode, 0, 0, Opcode_l16si_Slot_ae4_slot0_encode, Opcode_l16si_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0, Opcode_l32i_Slot_ae_slot0_encode, Opcode_l32i_Slot_ae_slot1_encode, 0, 0, Opcode_l32i_Slot_ae2_slot0_encode, Opcode_l32i_Slot_ae2_slot1_encode, 0, Opcode_l32i_Slot_ae3_slot0_encode, Opcode_l32i_Slot_ae3_slot1_encode, Opcode_l32i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l32i_Slot_ae8_slot0_encode, Opcode_l32i_Slot_ae8_slot1_encode, 0, Opcode_l32i_Slot_ae9_slot0_encode, Opcode_l32i_Slot_ae9_slot1_encode, 0, 0, Opcode_l32i_Slot_ae10_slot0_encode, Opcode_l32i_Slot_ae10_slot1_encode, 0, 0, Opcode_l32i_Slot_ae4_slot0_encode, Opcode_l32i_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0, Opcode_l32r_Slot_ae_slot0_encode, 0, 0, 0, Opcode_l32r_Slot_ae2_slot0_encode, 0, 0, Opcode_l32r_Slot_ae3_slot0_encode, 0, Opcode_l32r_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l32r_Slot_ae8_slot0_encode, 0, 0, Opcode_l32r_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_l32r_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_l32r_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode, Opcode_l8ui_Slot_ae_slot1_encode, 0, 0, Opcode_l8ui_Slot_ae2_slot0_encode, Opcode_l8ui_Slot_ae2_slot1_encode, 0, Opcode_l8ui_Slot_ae3_slot0_encode, Opcode_l8ui_Slot_ae3_slot1_encode, Opcode_l8ui_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l8ui_Slot_ae8_slot0_encode, Opcode_l8ui_Slot_ae8_slot1_encode, 0, Opcode_l8ui_Slot_ae9_slot0_encode, Opcode_l8ui_Slot_ae9_slot1_encode, 0, 0, Opcode_l8ui_Slot_ae10_slot0_encode, Opcode_l8ui_Slot_ae10_slot1_encode, 0, 0, Opcode_l8ui_Slot_ae4_slot0_encode, Opcode_l8ui_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { + Opcode_loop_Slot_inst_encode, 0, 0, Opcode_loop_Slot_ae_slot0_encode, 0, 0, 0, Opcode_loop_Slot_ae2_slot0_encode, 0, 0, Opcode_loop_Slot_ae3_slot0_encode, 0, Opcode_loop_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_loop_Slot_ae8_slot0_encode, 0, 0, Opcode_loop_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_loop_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_loop_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { + Opcode_loopgtz_Slot_inst_encode, 0, 0, Opcode_loopgtz_Slot_ae_slot0_encode, 0, 0, 0, Opcode_loopgtz_Slot_ae2_slot0_encode, 0, 0, Opcode_loopgtz_Slot_ae3_slot0_encode, 0, Opcode_loopgtz_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_loopgtz_Slot_ae8_slot0_encode, 0, 0, Opcode_loopgtz_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_loopgtz_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_loopgtz_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { + Opcode_loopnez_Slot_inst_encode, 0, 0, Opcode_loopnez_Slot_ae_slot0_encode, 0, 0, 0, Opcode_loopnez_Slot_ae2_slot0_encode, 0, 0, Opcode_loopnez_Slot_ae3_slot0_encode, 0, Opcode_loopnez_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_loopnez_Slot_ae8_slot0_encode, 0, 0, Opcode_loopnez_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_loopnez_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_loopnez_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0, Opcode_movi_Slot_ae_slot0_encode, Opcode_movi_Slot_ae_slot1_encode, 0, 0, Opcode_movi_Slot_ae2_slot0_encode, Opcode_movi_Slot_ae2_slot1_encode, 0, Opcode_movi_Slot_ae3_slot0_encode, Opcode_movi_Slot_ae3_slot1_encode, Opcode_movi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movi_Slot_ae8_slot0_encode, Opcode_movi_Slot_ae8_slot1_encode, 0, Opcode_movi_Slot_ae9_slot0_encode, Opcode_movi_Slot_ae9_slot1_encode, 0, 0, Opcode_movi_Slot_ae10_slot0_encode, Opcode_movi_Slot_ae10_slot1_encode, 0, 0, Opcode_movi_Slot_ae4_slot0_encode, Opcode_movi_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode, Opcode_moveqz_Slot_ae_slot1_encode, 0, 0, Opcode_moveqz_Slot_ae2_slot0_encode, Opcode_moveqz_Slot_ae2_slot1_encode, 0, Opcode_moveqz_Slot_ae3_slot0_encode, Opcode_moveqz_Slot_ae3_slot1_encode, Opcode_moveqz_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_moveqz_Slot_ae8_slot0_encode, Opcode_moveqz_Slot_ae8_slot1_encode, 0, Opcode_moveqz_Slot_ae9_slot0_encode, Opcode_moveqz_Slot_ae9_slot1_encode, 0, 0, Opcode_moveqz_Slot_ae10_slot0_encode, Opcode_moveqz_Slot_ae10_slot1_encode, 0, 0, Opcode_moveqz_Slot_ae4_slot0_encode, Opcode_moveqz_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0, Opcode_movgez_Slot_ae_slot0_encode, Opcode_movgez_Slot_ae_slot1_encode, 0, 0, Opcode_movgez_Slot_ae2_slot0_encode, Opcode_movgez_Slot_ae2_slot1_encode, 0, Opcode_movgez_Slot_ae3_slot0_encode, Opcode_movgez_Slot_ae3_slot1_encode, Opcode_movgez_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movgez_Slot_ae8_slot0_encode, Opcode_movgez_Slot_ae8_slot1_encode, 0, Opcode_movgez_Slot_ae9_slot0_encode, Opcode_movgez_Slot_ae9_slot1_encode, 0, 0, Opcode_movgez_Slot_ae10_slot0_encode, Opcode_movgez_Slot_ae10_slot1_encode, 0, 0, Opcode_movgez_Slot_ae4_slot0_encode, Opcode_movgez_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0, Opcode_movltz_Slot_ae_slot0_encode, Opcode_movltz_Slot_ae_slot1_encode, 0, 0, Opcode_movltz_Slot_ae2_slot0_encode, Opcode_movltz_Slot_ae2_slot1_encode, 0, Opcode_movltz_Slot_ae3_slot0_encode, Opcode_movltz_Slot_ae3_slot1_encode, Opcode_movltz_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movltz_Slot_ae8_slot0_encode, Opcode_movltz_Slot_ae8_slot1_encode, 0, Opcode_movltz_Slot_ae9_slot0_encode, Opcode_movltz_Slot_ae9_slot1_encode, 0, 0, Opcode_movltz_Slot_ae10_slot0_encode, Opcode_movltz_Slot_ae10_slot1_encode, 0, 0, Opcode_movltz_Slot_ae4_slot0_encode, Opcode_movltz_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0, Opcode_movnez_Slot_ae_slot0_encode, Opcode_movnez_Slot_ae_slot1_encode, 0, 0, Opcode_movnez_Slot_ae2_slot0_encode, Opcode_movnez_Slot_ae2_slot1_encode, 0, Opcode_movnez_Slot_ae3_slot0_encode, Opcode_movnez_Slot_ae3_slot1_encode, Opcode_movnez_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movnez_Slot_ae8_slot0_encode, Opcode_movnez_Slot_ae8_slot1_encode, 0, Opcode_movnez_Slot_ae9_slot0_encode, Opcode_movnez_Slot_ae9_slot1_encode, 0, 0, Opcode_movnez_Slot_ae10_slot0_encode, Opcode_movnez_Slot_ae10_slot1_encode, 0, 0, Opcode_movnez_Slot_ae4_slot0_encode, Opcode_movnez_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0, Opcode_abs_Slot_ae_slot0_encode, Opcode_abs_Slot_ae_slot1_encode, 0, 0, Opcode_abs_Slot_ae2_slot0_encode, Opcode_abs_Slot_ae2_slot1_encode, 0, Opcode_abs_Slot_ae3_slot0_encode, Opcode_abs_Slot_ae3_slot1_encode, Opcode_abs_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_abs_Slot_ae8_slot0_encode, Opcode_abs_Slot_ae8_slot1_encode, 0, Opcode_abs_Slot_ae9_slot0_encode, Opcode_abs_Slot_ae9_slot1_encode, 0, 0, Opcode_abs_Slot_ae10_slot0_encode, Opcode_abs_Slot_ae10_slot1_encode, 0, 0, Opcode_abs_Slot_ae4_slot0_encode, Opcode_abs_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0, Opcode_neg_Slot_ae_slot0_encode, Opcode_neg_Slot_ae_slot1_encode, 0, 0, Opcode_neg_Slot_ae2_slot0_encode, Opcode_neg_Slot_ae2_slot1_encode, 0, Opcode_neg_Slot_ae3_slot0_encode, Opcode_neg_Slot_ae3_slot1_encode, Opcode_neg_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_neg_Slot_ae8_slot0_encode, Opcode_neg_Slot_ae8_slot1_encode, 0, Opcode_neg_Slot_ae9_slot0_encode, Opcode_neg_Slot_ae9_slot1_encode, 0, 0, Opcode_neg_Slot_ae10_slot0_encode, Opcode_neg_Slot_ae10_slot1_encode, 0, 0, Opcode_neg_Slot_ae4_slot0_encode, Opcode_neg_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot0_encode, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot2_encode, Opcode_nop_Slot_ae_slot3_encode, Opcode_nop_Slot_ae2_slot0_encode, Opcode_nop_Slot_ae2_slot1_encode, Opcode_nop_Slot_ae2_slot2_encode, Opcode_nop_Slot_ae3_slot0_encode, Opcode_nop_Slot_ae3_slot1_encode, Opcode_nop_Slot_ae5_slot0_encode, Opcode_nop_Slot_ae5_slot1_encode, Opcode_nop_Slot_ae5_slot2_encode, Opcode_nop_Slot_ae6_slot0_encode, Opcode_nop_Slot_ae6_slot1_encode, Opcode_nop_Slot_ae6_slot2_encode, Opcode_nop_Slot_ae6_slot3_encode, Opcode_nop_Slot_ae7_slot0_encode, Opcode_nop_Slot_ae7_slot1_encode, Opcode_nop_Slot_ae7_slot2_encode, Opcode_nop_Slot_ae7_slot3_encode, Opcode_nop_Slot_ae8_slot0_encode, Opcode_nop_Slot_ae8_slot1_encode, Opcode_nop_Slot_ae8_slot2_encode, Opcode_nop_Slot_ae9_slot0_encode, Opcode_nop_Slot_ae9_slot1_encode, Opcode_nop_Slot_ae9_slot2_encode, Opcode_nop_Slot_ae9_slot3_encode, Opcode_nop_Slot_ae10_slot0_encode, Opcode_nop_Slot_ae10_slot1_encode, Opcode_nop_Slot_ae10_slot2_encode, Opcode_nop_Slot_ae10_slot3_encode, Opcode_nop_Slot_ae4_slot0_encode, Opcode_nop_Slot_ae4_slot1_encode, Opcode_nop_Slot_ae4_slot2_encode, Opcode_nop_Slot_ae4_slot3_encode, Opcode_nop_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32ex_encode_fns[] = { + Opcode_l32ex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32ex_encode_fns[] = { + Opcode_s32ex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_getex_encode_fns[] = { + Opcode_getex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clrex_encode_fns[] = { + Opcode_clrex_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0, Opcode_ret_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ret_Slot_ae2_slot0_encode, 0, 0, Opcode_ret_Slot_ae3_slot0_encode, 0, Opcode_ret_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ret_Slot_ae8_slot0_encode, 0, 0, Opcode_ret_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_ret_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_ret_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0, Opcode_s16i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_s16i_Slot_ae2_slot0_encode, 0, 0, Opcode_s16i_Slot_ae3_slot0_encode, 0, Opcode_s16i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s16i_Slot_ae8_slot0_encode, 0, 0, Opcode_s16i_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_s16i_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_s16i_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0, Opcode_s32i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_s32i_Slot_ae2_slot0_encode, 0, 0, Opcode_s32i_Slot_ae3_slot0_encode, 0, Opcode_s32i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s32i_Slot_ae8_slot0_encode, 0, 0, Opcode_s32i_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_s32i_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_s32i_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = { + Opcode_s32nb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0, Opcode_s8i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_s8i_Slot_ae2_slot0_encode, 0, 0, Opcode_s8i_Slot_ae3_slot0_encode, 0, Opcode_s8i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s8i_Slot_ae8_slot0_encode, 0, 0, Opcode_s8i_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_s8i_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_s8i_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode, Opcode_ssa8b_Slot_ae_slot1_encode, 0, 0, Opcode_ssa8b_Slot_ae2_slot0_encode, Opcode_ssa8b_Slot_ae2_slot1_encode, 0, Opcode_ssa8b_Slot_ae3_slot0_encode, Opcode_ssa8b_Slot_ae3_slot1_encode, Opcode_ssa8b_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssa8b_Slot_ae8_slot0_encode, Opcode_ssa8b_Slot_ae8_slot1_encode, 0, Opcode_ssa8b_Slot_ae9_slot0_encode, Opcode_ssa8b_Slot_ae9_slot1_encode, 0, 0, Opcode_ssa8b_Slot_ae10_slot0_encode, Opcode_ssa8b_Slot_ae10_slot1_encode, 0, 0, Opcode_ssa8b_Slot_ae4_slot0_encode, Opcode_ssa8b_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode, Opcode_ssa8l_Slot_ae_slot1_encode, 0, 0, Opcode_ssa8l_Slot_ae2_slot0_encode, Opcode_ssa8l_Slot_ae2_slot1_encode, 0, Opcode_ssa8l_Slot_ae3_slot0_encode, Opcode_ssa8l_Slot_ae3_slot1_encode, Opcode_ssa8l_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssa8l_Slot_ae8_slot0_encode, Opcode_ssa8l_Slot_ae8_slot1_encode, 0, Opcode_ssa8l_Slot_ae9_slot0_encode, Opcode_ssa8l_Slot_ae9_slot1_encode, 0, 0, Opcode_ssa8l_Slot_ae10_slot0_encode, Opcode_ssa8l_Slot_ae10_slot1_encode, 0, 0, Opcode_ssa8l_Slot_ae4_slot0_encode, Opcode_ssa8l_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0, Opcode_ssl_Slot_ae_slot0_encode, Opcode_ssl_Slot_ae_slot1_encode, 0, 0, Opcode_ssl_Slot_ae2_slot0_encode, Opcode_ssl_Slot_ae2_slot1_encode, 0, Opcode_ssl_Slot_ae3_slot0_encode, Opcode_ssl_Slot_ae3_slot1_encode, Opcode_ssl_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssl_Slot_ae8_slot0_encode, Opcode_ssl_Slot_ae8_slot1_encode, 0, Opcode_ssl_Slot_ae9_slot0_encode, Opcode_ssl_Slot_ae9_slot1_encode, 0, 0, Opcode_ssl_Slot_ae10_slot0_encode, Opcode_ssl_Slot_ae10_slot1_encode, 0, 0, Opcode_ssl_Slot_ae4_slot0_encode, Opcode_ssl_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0, Opcode_ssr_Slot_ae_slot0_encode, Opcode_ssr_Slot_ae_slot1_encode, 0, 0, Opcode_ssr_Slot_ae2_slot0_encode, Opcode_ssr_Slot_ae2_slot1_encode, 0, Opcode_ssr_Slot_ae3_slot0_encode, Opcode_ssr_Slot_ae3_slot1_encode, Opcode_ssr_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssr_Slot_ae8_slot0_encode, Opcode_ssr_Slot_ae8_slot1_encode, 0, Opcode_ssr_Slot_ae9_slot0_encode, Opcode_ssr_Slot_ae9_slot1_encode, 0, 0, Opcode_ssr_Slot_ae10_slot0_encode, Opcode_ssr_Slot_ae10_slot1_encode, 0, 0, Opcode_ssr_Slot_ae4_slot0_encode, Opcode_ssr_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0, Opcode_ssai_Slot_ae_slot0_encode, Opcode_ssai_Slot_ae_slot1_encode, 0, 0, Opcode_ssai_Slot_ae2_slot0_encode, Opcode_ssai_Slot_ae2_slot1_encode, 0, Opcode_ssai_Slot_ae3_slot0_encode, Opcode_ssai_Slot_ae3_slot1_encode, Opcode_ssai_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssai_Slot_ae8_slot0_encode, Opcode_ssai_Slot_ae8_slot1_encode, 0, Opcode_ssai_Slot_ae9_slot0_encode, Opcode_ssai_Slot_ae9_slot1_encode, 0, 0, Opcode_ssai_Slot_ae10_slot0_encode, Opcode_ssai_Slot_ae10_slot1_encode, 0, 0, Opcode_ssai_Slot_ae4_slot0_encode, Opcode_ssai_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0, Opcode_sll_Slot_ae_slot0_encode, Opcode_sll_Slot_ae_slot1_encode, 0, 0, Opcode_sll_Slot_ae2_slot0_encode, Opcode_sll_Slot_ae2_slot1_encode, 0, Opcode_sll_Slot_ae3_slot0_encode, Opcode_sll_Slot_ae3_slot1_encode, Opcode_sll_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sll_Slot_ae8_slot0_encode, Opcode_sll_Slot_ae8_slot1_encode, 0, Opcode_sll_Slot_ae9_slot0_encode, Opcode_sll_Slot_ae9_slot1_encode, 0, 0, Opcode_sll_Slot_ae10_slot0_encode, Opcode_sll_Slot_ae10_slot1_encode, 0, 0, Opcode_sll_Slot_ae4_slot0_encode, Opcode_sll_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0, Opcode_src_Slot_ae_slot0_encode, Opcode_src_Slot_ae_slot1_encode, 0, 0, Opcode_src_Slot_ae2_slot0_encode, Opcode_src_Slot_ae2_slot1_encode, 0, Opcode_src_Slot_ae3_slot0_encode, Opcode_src_Slot_ae3_slot1_encode, Opcode_src_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_src_Slot_ae8_slot0_encode, Opcode_src_Slot_ae8_slot1_encode, 0, Opcode_src_Slot_ae9_slot0_encode, Opcode_src_Slot_ae9_slot1_encode, 0, 0, Opcode_src_Slot_ae10_slot0_encode, Opcode_src_Slot_ae10_slot1_encode, 0, 0, Opcode_src_Slot_ae4_slot0_encode, Opcode_src_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0, Opcode_sra_Slot_ae_slot0_encode, Opcode_sra_Slot_ae_slot1_encode, 0, 0, Opcode_sra_Slot_ae2_slot0_encode, Opcode_sra_Slot_ae2_slot1_encode, 0, Opcode_sra_Slot_ae3_slot0_encode, Opcode_sra_Slot_ae3_slot1_encode, Opcode_sra_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sra_Slot_ae8_slot0_encode, Opcode_sra_Slot_ae8_slot1_encode, 0, Opcode_sra_Slot_ae9_slot0_encode, Opcode_sra_Slot_ae9_slot1_encode, 0, 0, Opcode_sra_Slot_ae10_slot0_encode, Opcode_sra_Slot_ae10_slot1_encode, 0, 0, Opcode_sra_Slot_ae4_slot0_encode, Opcode_sra_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0, Opcode_srl_Slot_ae_slot0_encode, Opcode_srl_Slot_ae_slot1_encode, 0, 0, Opcode_srl_Slot_ae2_slot0_encode, Opcode_srl_Slot_ae2_slot1_encode, 0, Opcode_srl_Slot_ae3_slot0_encode, Opcode_srl_Slot_ae3_slot1_encode, Opcode_srl_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_srl_Slot_ae8_slot0_encode, Opcode_srl_Slot_ae8_slot1_encode, 0, Opcode_srl_Slot_ae9_slot0_encode, Opcode_srl_Slot_ae9_slot1_encode, 0, 0, Opcode_srl_Slot_ae10_slot0_encode, Opcode_srl_Slot_ae10_slot1_encode, 0, 0, Opcode_srl_Slot_ae4_slot0_encode, Opcode_srl_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0, Opcode_slli_Slot_ae_slot0_encode, Opcode_slli_Slot_ae_slot1_encode, 0, 0, Opcode_slli_Slot_ae2_slot0_encode, Opcode_slli_Slot_ae2_slot1_encode, 0, Opcode_slli_Slot_ae3_slot0_encode, Opcode_slli_Slot_ae3_slot1_encode, Opcode_slli_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_slli_Slot_ae8_slot0_encode, Opcode_slli_Slot_ae8_slot1_encode, 0, Opcode_slli_Slot_ae9_slot0_encode, Opcode_slli_Slot_ae9_slot1_encode, 0, 0, Opcode_slli_Slot_ae10_slot0_encode, Opcode_slli_Slot_ae10_slot1_encode, 0, 0, Opcode_slli_Slot_ae4_slot0_encode, Opcode_slli_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0, Opcode_srai_Slot_ae_slot0_encode, Opcode_srai_Slot_ae_slot1_encode, 0, 0, Opcode_srai_Slot_ae2_slot0_encode, Opcode_srai_Slot_ae2_slot1_encode, 0, Opcode_srai_Slot_ae3_slot0_encode, Opcode_srai_Slot_ae3_slot1_encode, Opcode_srai_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_srai_Slot_ae8_slot0_encode, Opcode_srai_Slot_ae8_slot1_encode, 0, Opcode_srai_Slot_ae9_slot0_encode, Opcode_srai_Slot_ae9_slot1_encode, 0, 0, Opcode_srai_Slot_ae10_slot0_encode, Opcode_srai_Slot_ae10_slot1_encode, 0, 0, Opcode_srai_Slot_ae4_slot0_encode, Opcode_srai_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0, Opcode_srli_Slot_ae_slot0_encode, Opcode_srli_Slot_ae_slot1_encode, 0, 0, Opcode_srli_Slot_ae2_slot0_encode, Opcode_srli_Slot_ae2_slot1_encode, 0, Opcode_srli_Slot_ae3_slot0_encode, Opcode_srli_Slot_ae3_slot1_encode, Opcode_srli_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_srli_Slot_ae8_slot0_encode, Opcode_srli_Slot_ae8_slot1_encode, 0, Opcode_srli_Slot_ae9_slot0_encode, Opcode_srli_Slot_ae9_slot1_encode, 0, 0, Opcode_srli_Slot_ae10_slot0_encode, Opcode_srli_Slot_ae10_slot1_encode, 0, 0, Opcode_srli_Slot_ae4_slot0_encode, Opcode_srli_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { + Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { + Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { + Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { + Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { + Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { + Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = { + Opcode_rsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = { + Opcode_wsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = { + Opcode_xsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { + Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { + Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { + Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { + Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { + Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { + Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { + Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { + Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { + Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { + Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { + Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { + Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { + Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { + Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { + Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { + Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { + Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { + Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { + Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { + Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { + Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { + Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { + Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { + Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { + Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { + Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { + Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { + Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { + Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { + Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { + Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { + Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { + Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { + Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { + Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { + Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { + Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { + Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { + Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc2_encode_fns[] = { + Opcode_rsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc2_encode_fns[] = { + Opcode_wsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc2_encode_fns[] = { + Opcode_xsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc3_encode_fns[] = { + Opcode_rsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc3_encode_fns[] = { + Opcode_wsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc3_encode_fns[] = { + Opcode_xsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_mpucfg_encode_fns[] = { + Opcode_rsr_mpucfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mpucfg_encode_fns[] = { + Opcode_wsr_mpucfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_salt_encode_fns[] = { + Opcode_salt_Slot_inst_encode, 0, 0, Opcode_salt_Slot_ae_slot0_encode, Opcode_salt_Slot_ae_slot1_encode, 0, 0, Opcode_salt_Slot_ae2_slot0_encode, Opcode_salt_Slot_ae2_slot1_encode, 0, Opcode_salt_Slot_ae3_slot0_encode, Opcode_salt_Slot_ae3_slot1_encode, Opcode_salt_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_salt_Slot_ae8_slot0_encode, Opcode_salt_Slot_ae8_slot1_encode, 0, Opcode_salt_Slot_ae9_slot0_encode, Opcode_salt_Slot_ae9_slot1_encode, 0, 0, Opcode_salt_Slot_ae10_slot0_encode, Opcode_salt_Slot_ae10_slot1_encode, 0, 0, Opcode_salt_Slot_ae4_slot0_encode, Opcode_salt_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_saltu_encode_fns[] = { + Opcode_saltu_Slot_inst_encode, 0, 0, Opcode_saltu_Slot_ae_slot0_encode, Opcode_saltu_Slot_ae_slot1_encode, 0, 0, Opcode_saltu_Slot_ae2_slot0_encode, Opcode_saltu_Slot_ae2_slot1_encode, 0, Opcode_saltu_Slot_ae3_slot0_encode, Opcode_saltu_Slot_ae3_slot1_encode, Opcode_saltu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_saltu_Slot_ae8_slot0_encode, Opcode_saltu_Slot_ae8_slot1_encode, 0, Opcode_saltu_Slot_ae9_slot0_encode, Opcode_saltu_Slot_ae9_slot1_encode, 0, 0, Opcode_saltu_Slot_ae10_slot0_encode, Opcode_saltu_Slot_ae10_slot1_encode, 0, 0, Opcode_saltu_Slot_ae4_slot0_encode, Opcode_saltu_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_opmode_encode_fns[] = { + Opcode_rsr_opmode_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_opmode_encode_fns[] = { + Opcode_wsr_opmode_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_opmode_encode_fns[] = { + Opcode_xsr_opmode_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { + Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { + Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { + Opcode_mull_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = { + Opcode_lddr32_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = { + Opcode_sddr32_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { + Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { + Opcode_andb_Slot_inst_encode, 0, 0, Opcode_andb_Slot_ae_slot0_encode, 0, 0, 0, Opcode_andb_Slot_ae2_slot0_encode, 0, 0, Opcode_andb_Slot_ae3_slot0_encode, 0, Opcode_andb_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_andb_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_andb_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_andb_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { + Opcode_andbc_Slot_inst_encode, 0, 0, Opcode_andbc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_andbc_Slot_ae2_slot0_encode, 0, 0, Opcode_andbc_Slot_ae3_slot0_encode, 0, Opcode_andbc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_andbc_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_andbc_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_andbc_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { + Opcode_orb_Slot_inst_encode, 0, 0, Opcode_orb_Slot_ae_slot0_encode, 0, 0, 0, Opcode_orb_Slot_ae2_slot0_encode, 0, 0, Opcode_orb_Slot_ae3_slot0_encode, 0, Opcode_orb_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_orb_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_orb_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_orb_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { + Opcode_orbc_Slot_inst_encode, 0, 0, Opcode_orbc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_orbc_Slot_ae2_slot0_encode, 0, 0, Opcode_orbc_Slot_ae3_slot0_encode, 0, Opcode_orbc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_orbc_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_orbc_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_orbc_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { + Opcode_xorb_Slot_inst_encode, 0, 0, Opcode_xorb_Slot_ae_slot0_encode, 0, 0, 0, Opcode_xorb_Slot_ae2_slot0_encode, 0, 0, Opcode_xorb_Slot_ae3_slot0_encode, 0, Opcode_xorb_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_xorb_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_xorb_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_xorb_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { + Opcode_all4_Slot_inst_encode, 0, 0, Opcode_all4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_all4_Slot_ae2_slot0_encode, 0, 0, Opcode_all4_Slot_ae3_slot0_encode, 0, Opcode_all4_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_all4_Slot_ae8_slot0_encode, 0, 0, Opcode_all4_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_all4_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_all4_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { + Opcode_any4_Slot_inst_encode, 0, 0, Opcode_any4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_any4_Slot_ae2_slot0_encode, 0, 0, Opcode_any4_Slot_ae3_slot0_encode, 0, Opcode_any4_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_any4_Slot_ae8_slot0_encode, 0, 0, Opcode_any4_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_any4_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_any4_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { + Opcode_all8_Slot_inst_encode, 0, 0, Opcode_all8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_all8_Slot_ae2_slot0_encode, 0, 0, Opcode_all8_Slot_ae3_slot0_encode, 0, Opcode_all8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_all8_Slot_ae8_slot0_encode, 0, 0, Opcode_all8_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_all8_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_all8_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { + Opcode_any8_Slot_inst_encode, 0, 0, Opcode_any8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_any8_Slot_ae2_slot0_encode, 0, 0, Opcode_any8_Slot_ae3_slot0_encode, 0, Opcode_any8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_any8_Slot_ae8_slot0_encode, 0, 0, Opcode_any8_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_any8_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_any8_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { + Opcode_bf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { + Opcode_bt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { + Opcode_movf_Slot_inst_encode, 0, 0, Opcode_movf_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movf_Slot_ae2_slot0_encode, 0, 0, Opcode_movf_Slot_ae3_slot0_encode, 0, Opcode_movf_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movf_Slot_ae8_slot0_encode, 0, 0, Opcode_movf_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_movf_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_movf_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { + Opcode_movt_Slot_inst_encode, 0, 0, Opcode_movt_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movt_Slot_ae2_slot0_encode, 0, 0, Opcode_movt_Slot_ae3_slot0_encode, 0, Opcode_movt_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movt_Slot_ae8_slot0_encode, 0, 0, Opcode_movt_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_movt_Slot_ae10_slot0_encode, 0, 0, 0, Opcode_movt_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { + Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { + Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { + Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { + Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { + Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { + Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { + Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { + Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { + Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { + Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { + Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { + Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { + Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { + Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { + Opcode_iii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { + Opcode_lict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { + Opcode_licw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { + Opcode_sict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { + Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { + Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { + Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = { + Opcode_diwbui_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { + Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { + Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { + Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { + Opcode_dii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { + Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { + Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { + Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { + Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { + Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { + Opcode_diu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { + Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { + Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { + Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdcw_encode_fns[] = { + Opcode_sdcw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldcw_encode_fns[] = { + Opcode_ldcw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prefctl_encode_fns[] = { + Opcode_rsr_prefctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_prefctl_encode_fns[] = { + Opcode_wsr_prefctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_prefctl_encode_fns[] = { + Opcode_xsr_prefctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_cacheadrdis_encode_fns[] = { + Opcode_wsr_cacheadrdis_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_cacheadrdis_encode_fns[] = { + Opcode_rsr_cacheadrdis_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_cacheadrdis_encode_fns[] = { + Opcode_xsr_cacheadrdis_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rptlb0_encode_fns[] = { + Opcode_rptlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pptlb_encode_fns[] = { + Opcode_pptlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rptlb1_encode_fns[] = { + Opcode_rptlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wptlb_encode_fns[] = { + Opcode_wptlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_mpuenb_encode_fns[] = { + Opcode_rsr_mpuenb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mpuenb_encode_fns[] = { + Opcode_wsr_mpuenb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_mpuenb_encode_fns[] = { + Opcode_xsr_mpuenb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { + Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { + Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { + Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { + Opcode_clamps_Slot_inst_encode, 0, 0, Opcode_clamps_Slot_ae_slot0_encode, Opcode_clamps_Slot_ae_slot1_encode, 0, 0, Opcode_clamps_Slot_ae2_slot0_encode, Opcode_clamps_Slot_ae2_slot1_encode, 0, Opcode_clamps_Slot_ae3_slot0_encode, Opcode_clamps_Slot_ae3_slot1_encode, Opcode_clamps_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_clamps_Slot_ae8_slot0_encode, Opcode_clamps_Slot_ae8_slot1_encode, 0, Opcode_clamps_Slot_ae9_slot0_encode, Opcode_clamps_Slot_ae9_slot1_encode, 0, 0, Opcode_clamps_Slot_ae10_slot0_encode, Opcode_clamps_Slot_ae10_slot1_encode, 0, 0, Opcode_clamps_Slot_ae4_slot0_encode, Opcode_clamps_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { + Opcode_max_Slot_inst_encode, 0, 0, Opcode_max_Slot_ae_slot0_encode, Opcode_max_Slot_ae_slot1_encode, 0, 0, Opcode_max_Slot_ae2_slot0_encode, Opcode_max_Slot_ae2_slot1_encode, 0, Opcode_max_Slot_ae3_slot0_encode, Opcode_max_Slot_ae3_slot1_encode, Opcode_max_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_max_Slot_ae8_slot0_encode, Opcode_max_Slot_ae8_slot1_encode, 0, Opcode_max_Slot_ae9_slot0_encode, Opcode_max_Slot_ae9_slot1_encode, 0, 0, Opcode_max_Slot_ae10_slot0_encode, Opcode_max_Slot_ae10_slot1_encode, 0, 0, Opcode_max_Slot_ae4_slot0_encode, Opcode_max_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { + Opcode_maxu_Slot_inst_encode, 0, 0, Opcode_maxu_Slot_ae_slot0_encode, Opcode_maxu_Slot_ae_slot1_encode, 0, 0, Opcode_maxu_Slot_ae2_slot0_encode, Opcode_maxu_Slot_ae2_slot1_encode, 0, Opcode_maxu_Slot_ae3_slot0_encode, Opcode_maxu_Slot_ae3_slot1_encode, Opcode_maxu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maxu_Slot_ae8_slot0_encode, Opcode_maxu_Slot_ae8_slot1_encode, 0, Opcode_maxu_Slot_ae9_slot0_encode, Opcode_maxu_Slot_ae9_slot1_encode, 0, 0, Opcode_maxu_Slot_ae10_slot0_encode, Opcode_maxu_Slot_ae10_slot1_encode, 0, 0, Opcode_maxu_Slot_ae4_slot0_encode, Opcode_maxu_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { + Opcode_min_Slot_inst_encode, 0, 0, Opcode_min_Slot_ae_slot0_encode, Opcode_min_Slot_ae_slot1_encode, 0, 0, Opcode_min_Slot_ae2_slot0_encode, Opcode_min_Slot_ae2_slot1_encode, 0, Opcode_min_Slot_ae3_slot0_encode, Opcode_min_Slot_ae3_slot1_encode, Opcode_min_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_min_Slot_ae8_slot0_encode, Opcode_min_Slot_ae8_slot1_encode, 0, Opcode_min_Slot_ae9_slot0_encode, Opcode_min_Slot_ae9_slot1_encode, 0, 0, Opcode_min_Slot_ae10_slot0_encode, Opcode_min_Slot_ae10_slot1_encode, 0, 0, Opcode_min_Slot_ae4_slot0_encode, Opcode_min_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { + Opcode_minu_Slot_inst_encode, 0, 0, Opcode_minu_Slot_ae_slot0_encode, Opcode_minu_Slot_ae_slot1_encode, 0, 0, Opcode_minu_Slot_ae2_slot0_encode, Opcode_minu_Slot_ae2_slot1_encode, 0, Opcode_minu_Slot_ae3_slot0_encode, Opcode_minu_Slot_ae3_slot1_encode, Opcode_minu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_minu_Slot_ae8_slot0_encode, Opcode_minu_Slot_ae8_slot1_encode, 0, Opcode_minu_Slot_ae9_slot0_encode, Opcode_minu_Slot_ae9_slot1_encode, 0, 0, Opcode_minu_Slot_ae10_slot0_encode, Opcode_minu_Slot_ae10_slot1_encode, 0, 0, Opcode_minu_Slot_ae4_slot0_encode, Opcode_minu_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { + Opcode_sext_Slot_inst_encode, 0, 0, Opcode_sext_Slot_ae_slot0_encode, Opcode_sext_Slot_ae_slot1_encode, 0, 0, Opcode_sext_Slot_ae2_slot0_encode, Opcode_sext_Slot_ae2_slot1_encode, 0, Opcode_sext_Slot_ae3_slot0_encode, Opcode_sext_Slot_ae3_slot1_encode, Opcode_sext_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sext_Slot_ae8_slot0_encode, Opcode_sext_Slot_ae8_slot1_encode, 0, Opcode_sext_Slot_ae9_slot0_encode, Opcode_sext_Slot_ae9_slot1_encode, 0, 0, Opcode_sext_Slot_ae10_slot0_encode, Opcode_sext_Slot_ae10_slot1_encode, 0, 0, Opcode_sext_Slot_ae4_slot0_encode, Opcode_sext_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { + Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { + Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { + Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { + Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { + Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { + Opcode_quos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { + Opcode_quou_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { + Opcode_rems_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { + Opcode_remu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eraccess_encode_fns[] = { + Opcode_rsr_eraccess_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eraccess_encode_fns[] = { + Opcode_wsr_eraccess_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eraccess_encode_fns[] = { + Opcode_xsr_eraccess_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { + Opcode_rer_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { + Opcode_wer_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_beqz_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_beqz_w15_Slot_ae3_slot0_encode, 0, Opcode_beqz_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bgez_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bgez_w15_Slot_ae3_slot0_encode, 0, Opcode_bgez_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bltz_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bltz_w15_Slot_ae3_slot0_encode, 0, Opcode_bltz_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bnez_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bnez_w15_Slot_ae3_slot0_encode, 0, Opcode_bnez_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_beqi_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_beqi_w15_Slot_ae3_slot0_encode, 0, Opcode_beqi_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bgei_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bgei_w15_Slot_ae3_slot0_encode, 0, Opcode_bgei_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_blti_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_blti_w15_Slot_ae3_slot0_encode, 0, Opcode_blti_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bnei_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bnei_w15_Slot_ae3_slot0_encode, 0, Opcode_bnei_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bgeui_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bgeui_w15_Slot_ae3_slot0_encode, 0, Opcode_bgeui_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bltui_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bltui_w15_Slot_ae3_slot0_encode, 0, Opcode_bltui_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bbci_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bbci_w15_Slot_ae3_slot0_encode, 0, Opcode_bbci_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bbsi_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bbsi_w15_Slot_ae3_slot0_encode, 0, Opcode_bbsi_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ball_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_ball_w15_Slot_ae3_slot0_encode, 0, Opcode_ball_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bany_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bany_w15_Slot_ae3_slot0_encode, 0, Opcode_bany_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bbc_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bbc_w15_Slot_ae3_slot0_encode, 0, Opcode_bbc_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bbs_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bbs_w15_Slot_ae3_slot0_encode, 0, Opcode_bbs_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_beq_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_beq_w15_Slot_ae3_slot0_encode, 0, Opcode_beq_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bgeu_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bgeu_w15_Slot_ae3_slot0_encode, 0, Opcode_bgeu_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bge_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bge_w15_Slot_ae3_slot0_encode, 0, Opcode_bge_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bltu_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bltu_w15_Slot_ae3_slot0_encode, 0, Opcode_bltu_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_blt_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_blt_w15_Slot_ae3_slot0_encode, 0, Opcode_blt_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bnall_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bnall_w15_Slot_ae3_slot0_encode, 0, Opcode_bnall_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bne_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bne_w15_Slot_ae3_slot0_encode, 0, Opcode_bne_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_bnone_w15_Slot_ae2_slot0_encode, 0, 0, Opcode_bnone_w15_Slot_ae3_slot0_encode, 0, Opcode_bnone_w15_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext16_encode_fns[] = { + 0, 0, Opcode_ae_sext16_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_zext16_encode_fns[] = { + 0, 0, Opcode_ae_zext16_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_zext8_encode_fns[] = { + 0, 0, Opcode_ae_zext8_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_clamps16_encode_fns[] = { + 0, 0, Opcode_ae_clamps16_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = { + Opcode_rur_fcr_Slot_inst_encode, 0, 0, Opcode_rur_fcr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = { + Opcode_wur_fcr_Slot_inst_encode, 0, 0, Opcode_wur_fcr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = { + Opcode_rur_fsr_Slot_inst_encode, 0, 0, Opcode_rur_fsr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = { + Opcode_wur_fsr_Slot_inst_encode, 0, 0, Opcode_wur_fsr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { + Opcode_read_impwire_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { + Opcode_setb_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { + Opcode_clrb_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { + Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = { + Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = { + Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = { + Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = { + Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = { + Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = { + Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cw_sd_no_encode_fns[] = { + Opcode_rur_ae_cw_sd_no_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cw_sd_no_encode_fns[] = { + Opcode_wur_ae_cw_sd_no_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cbegin0_encode_fns[] = { + Opcode_rur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cbegin0_encode_fns[] = { + Opcode_wur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cend0_encode_fns[] = { + Opcode_rur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cend0_encode_fns[] = { + Opcode_wur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cbegin1_encode_fns[] = { + Opcode_rur_ae_cbegin1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cbegin1_encode_fns[] = { + Opcode_wur_ae_cbegin1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cend1_encode_fns[] = { + Opcode_rur_ae_cend1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cend1_encode_fns[] = { + Opcode_wur_ae_cend1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cbegin2_encode_fns[] = { + Opcode_rur_ae_cbegin2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cbegin2_encode_fns[] = { + Opcode_wur_ae_cbegin2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cend2_encode_fns[] = { + Opcode_rur_ae_cend2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cend2_encode_fns[] = { + Opcode_wur_ae_cend2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { + Opcode_rur_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { + Opcode_wur_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = { + Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = { + Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = { + Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = { + Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = { + Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rur_ae_bitptr_Slot_ae3_slot0_encode, 0, Opcode_rur_ae_bitptr_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = { + Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = { + Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = { + Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = { + Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = { + Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = { + Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = { + Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = { + Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = { + Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = { + Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = { + Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cwrap_encode_fns[] = { + Opcode_rur_ae_cwrap_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cwrap_encode_fns[] = { + Opcode_wur_ae_cwrap_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4f_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4f_i_Slot_ae_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4f_i_Slot_ae2_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4f_i_Slot_ae3_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae3_slot1_encode, Opcode_ae_l8x4f_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4f_i_Slot_ae8_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4f_i_Slot_ae9_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4f_i_Slot_ae10_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4f_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4f_ip_Slot_ae_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4f_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4f_ip_Slot_ae3_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae3_slot1_encode, Opcode_ae_l8x4f_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4f_ip_Slot_ae8_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4f_ip_Slot_ae9_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4f_ip_Slot_ae10_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4f_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4f_x_Slot_ae_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4f_x_Slot_ae2_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4f_x_Slot_ae3_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae3_slot1_encode, Opcode_ae_l8x4f_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4f_x_Slot_ae8_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4f_x_Slot_ae9_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4f_x_Slot_ae10_slot0_encode, Opcode_ae_l8x4f_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4f_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4f_xp_Slot_ae_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4f_xp_Slot_ae2_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4f_xp_Slot_ae3_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae3_slot1_encode, Opcode_ae_l8x4f_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4f_xp_Slot_ae8_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4f_xp_Slot_ae9_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4f_xp_Slot_ae10_slot0_encode, Opcode_ae_l8x4f_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4s_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4s_i_Slot_ae_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4s_i_Slot_ae2_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4s_i_Slot_ae3_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae3_slot1_encode, Opcode_ae_l8x4s_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4s_i_Slot_ae8_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4s_i_Slot_ae9_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4s_i_Slot_ae10_slot0_encode, Opcode_ae_l8x4s_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4s_ip_Slot_ae_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4s_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4s_ip_Slot_ae3_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae3_slot1_encode, Opcode_ae_l8x4s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4s_ip_Slot_ae8_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4s_ip_Slot_ae9_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4s_ip_Slot_ae10_slot0_encode, Opcode_ae_l8x4s_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4s_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4s_x_Slot_ae_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4s_x_Slot_ae2_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4s_x_Slot_ae3_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae3_slot1_encode, Opcode_ae_l8x4s_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4s_x_Slot_ae8_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4s_x_Slot_ae9_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4s_x_Slot_ae10_slot0_encode, Opcode_ae_l8x4s_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4s_xp_Slot_ae_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4s_xp_Slot_ae2_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4s_xp_Slot_ae3_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae3_slot1_encode, Opcode_ae_l8x4s_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4s_xp_Slot_ae8_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4s_xp_Slot_ae9_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4s_xp_Slot_ae10_slot0_encode, Opcode_ae_l8x4s_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4u_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4u_i_Slot_ae_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4u_i_Slot_ae2_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4u_i_Slot_ae3_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae3_slot1_encode, Opcode_ae_l8x4u_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4u_i_Slot_ae8_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4u_i_Slot_ae9_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4u_i_Slot_ae10_slot0_encode, Opcode_ae_l8x4u_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4u_ip_Slot_ae_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4u_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4u_ip_Slot_ae3_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae3_slot1_encode, Opcode_ae_l8x4u_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4u_ip_Slot_ae8_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4u_ip_Slot_ae9_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4u_ip_Slot_ae10_slot0_encode, Opcode_ae_l8x4u_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4u_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4u_x_Slot_ae_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4u_x_Slot_ae2_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4u_x_Slot_ae3_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae3_slot1_encode, Opcode_ae_l8x4u_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4u_x_Slot_ae8_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4u_x_Slot_ae9_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4u_x_Slot_ae10_slot0_encode, Opcode_ae_l8x4u_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x4u_xp_Slot_ae_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x4u_xp_Slot_ae2_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x4u_xp_Slot_ae3_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae3_slot1_encode, Opcode_ae_l8x4u_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x4u_xp_Slot_ae8_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x4u_xp_Slot_ae9_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x4u_xp_Slot_ae10_slot0_encode, Opcode_ae_l8x4u_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x4u_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x4u_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x4u_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x4u_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x4u_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4u_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x4u_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x4u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x4u_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x4u_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x4u_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x4u_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4u_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x4u_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x4u_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x4u_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x4u_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x4u_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x4u_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4u_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x4u_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x4u_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x4u_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x4u_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x4u_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x4u_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4u_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x4u_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16m_xc_Slot_ae_slot0_encode, Opcode_ae_l16m_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_xc_Slot_ae2_slot0_encode, Opcode_ae_l16m_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l16m_xc_Slot_ae3_slot0_encode, Opcode_ae_l16m_xc_Slot_ae3_slot1_encode, Opcode_ae_l16m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_xc_Slot_ae8_slot0_encode, Opcode_ae_l16m_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_xc_Slot_ae9_slot0_encode, Opcode_ae_l16m_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_xc_Slot_ae10_slot0_encode, Opcode_ae_l16m_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_xc1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_l16m_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_xc1_Slot_ae2_slot0_encode, Opcode_ae_l16m_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l16m_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_xc1_Slot_ae8_slot0_encode, Opcode_ae_l16m_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_xc1_Slot_ae9_slot0_encode, Opcode_ae_l16m_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_xc1_Slot_ae10_slot0_encode, Opcode_ae_l16m_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16m_i_Slot_ae_slot0_encode, Opcode_ae_l16m_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_i_Slot_ae2_slot0_encode, Opcode_ae_l16m_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l16m_i_Slot_ae3_slot0_encode, Opcode_ae_l16m_i_Slot_ae3_slot1_encode, Opcode_ae_l16m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_i_Slot_ae8_slot0_encode, Opcode_ae_l16m_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_i_Slot_ae9_slot0_encode, Opcode_ae_l16m_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_i_Slot_ae10_slot0_encode, Opcode_ae_l16m_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16m_iu_Slot_ae_slot0_encode, Opcode_ae_l16m_iu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_iu_Slot_ae2_slot0_encode, Opcode_ae_l16m_iu_Slot_ae2_slot1_encode, 0, Opcode_ae_l16m_iu_Slot_ae3_slot0_encode, Opcode_ae_l16m_iu_Slot_ae3_slot1_encode, Opcode_ae_l16m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_iu_Slot_ae8_slot0_encode, Opcode_ae_l16m_iu_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_iu_Slot_ae9_slot0_encode, Opcode_ae_l16m_iu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_iu_Slot_ae10_slot0_encode, Opcode_ae_l16m_iu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16m_x_Slot_ae_slot0_encode, Opcode_ae_l16m_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_x_Slot_ae2_slot0_encode, Opcode_ae_l16m_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l16m_x_Slot_ae3_slot0_encode, Opcode_ae_l16m_x_Slot_ae3_slot1_encode, Opcode_ae_l16m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_x_Slot_ae8_slot0_encode, Opcode_ae_l16m_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_x_Slot_ae9_slot0_encode, Opcode_ae_l16m_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_x_Slot_ae10_slot0_encode, Opcode_ae_l16m_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16m_xu_Slot_ae_slot0_encode, Opcode_ae_l16m_xu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_xu_Slot_ae2_slot0_encode, Opcode_ae_l16m_xu_Slot_ae2_slot1_encode, 0, Opcode_ae_l16m_xu_Slot_ae3_slot0_encode, Opcode_ae_l16m_xu_Slot_ae3_slot1_encode, Opcode_ae_l16m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_xu_Slot_ae8_slot0_encode, Opcode_ae_l16m_xu_Slot_ae8_slot1_encode, 0, Opcode_ae_l16m_xu_Slot_ae9_slot0_encode, Opcode_ae_l16m_xu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16m_xu_Slot_ae10_slot0_encode, Opcode_ae_l16m_xu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_xc_Slot_ae_slot0_encode, Opcode_ae_l16_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_xc_Slot_ae2_slot0_encode, Opcode_ae_l16_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l16_xc_Slot_ae3_slot0_encode, Opcode_ae_l16_xc_Slot_ae3_slot1_encode, Opcode_ae_l16_xc_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16_xc_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_xc_Slot_ae8_slot0_encode, Opcode_ae_l16_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_xc_Slot_ae9_slot0_encode, Opcode_ae_l16_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_xc_Slot_ae10_slot0_encode, Opcode_ae_l16_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_xc1_Slot_ae_slot0_encode, Opcode_ae_l16_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_xc1_Slot_ae2_slot0_encode, Opcode_ae_l16_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l16_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_xc1_Slot_ae8_slot0_encode, Opcode_ae_l16_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_xc1_Slot_ae9_slot0_encode, Opcode_ae_l16_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_xc1_Slot_ae10_slot0_encode, Opcode_ae_l16_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_i_Slot_ae_slot0_encode, Opcode_ae_l16_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_i_Slot_ae2_slot0_encode, Opcode_ae_l16_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l16_i_Slot_ae3_slot0_encode, Opcode_ae_l16_i_Slot_ae3_slot1_encode, Opcode_ae_l16_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16_i_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_i_Slot_ae8_slot0_encode, Opcode_ae_l16_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_i_Slot_ae9_slot0_encode, Opcode_ae_l16_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_i_Slot_ae10_slot0_encode, Opcode_ae_l16_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_ip_Slot_ae_slot0_encode, Opcode_ae_l16_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_ip_Slot_ae2_slot0_encode, Opcode_ae_l16_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l16_ip_Slot_ae3_slot0_encode, Opcode_ae_l16_ip_Slot_ae3_slot1_encode, Opcode_ae_l16_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16_ip_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_ip_Slot_ae8_slot0_encode, Opcode_ae_l16_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_ip_Slot_ae9_slot0_encode, Opcode_ae_l16_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_ip_Slot_ae10_slot0_encode, Opcode_ae_l16_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_x_Slot_ae_slot0_encode, Opcode_ae_l16_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_x_Slot_ae2_slot0_encode, Opcode_ae_l16_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l16_x_Slot_ae3_slot0_encode, Opcode_ae_l16_x_Slot_ae3_slot1_encode, Opcode_ae_l16_x_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16_x_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_x_Slot_ae8_slot0_encode, Opcode_ae_l16_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_x_Slot_ae9_slot0_encode, Opcode_ae_l16_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_x_Slot_ae10_slot0_encode, Opcode_ae_l16_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16_xp_Slot_ae_slot0_encode, Opcode_ae_l16_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16_xp_Slot_ae2_slot0_encode, Opcode_ae_l16_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l16_xp_Slot_ae3_slot0_encode, Opcode_ae_l16_xp_Slot_ae3_slot1_encode, Opcode_ae_l16_xp_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16_xp_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_xp_Slot_ae8_slot0_encode, Opcode_ae_l16_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l16_xp_Slot_ae9_slot0_encode, Opcode_ae_l16_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16_xp_Slot_ae10_slot0_encode, Opcode_ae_l16_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_xc_Slot_ae_slot0_encode, Opcode_ae_l8_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_xc_Slot_ae2_slot0_encode, Opcode_ae_l8_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l8_xc_Slot_ae3_slot0_encode, Opcode_ae_l8_xc_Slot_ae3_slot1_encode, Opcode_ae_l8_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_xc_Slot_ae8_slot0_encode, Opcode_ae_l8_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_xc_Slot_ae9_slot0_encode, Opcode_ae_l8_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_xc_Slot_ae10_slot0_encode, Opcode_ae_l8_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_xc1_Slot_ae_slot0_encode, Opcode_ae_l8_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_xc1_Slot_ae2_slot0_encode, Opcode_ae_l8_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l8_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_xc1_Slot_ae8_slot0_encode, Opcode_ae_l8_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_xc1_Slot_ae9_slot0_encode, Opcode_ae_l8_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_xc1_Slot_ae10_slot0_encode, Opcode_ae_l8_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_i_Slot_ae_slot0_encode, Opcode_ae_l8_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_i_Slot_ae2_slot0_encode, Opcode_ae_l8_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l8_i_Slot_ae3_slot0_encode, Opcode_ae_l8_i_Slot_ae3_slot1_encode, Opcode_ae_l8_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_i_Slot_ae8_slot0_encode, Opcode_ae_l8_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_i_Slot_ae9_slot0_encode, Opcode_ae_l8_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_i_Slot_ae10_slot0_encode, Opcode_ae_l8_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_ip_Slot_ae_slot0_encode, Opcode_ae_l8_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_ip_Slot_ae2_slot0_encode, Opcode_ae_l8_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l8_ip_Slot_ae3_slot0_encode, Opcode_ae_l8_ip_Slot_ae3_slot1_encode, Opcode_ae_l8_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_ip_Slot_ae8_slot0_encode, Opcode_ae_l8_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_ip_Slot_ae9_slot0_encode, Opcode_ae_l8_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_ip_Slot_ae10_slot0_encode, Opcode_ae_l8_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_x_Slot_ae_slot0_encode, Opcode_ae_l8_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_x_Slot_ae2_slot0_encode, Opcode_ae_l8_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l8_x_Slot_ae3_slot0_encode, Opcode_ae_l8_x_Slot_ae3_slot1_encode, Opcode_ae_l8_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_x_Slot_ae8_slot0_encode, Opcode_ae_l8_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_x_Slot_ae9_slot0_encode, Opcode_ae_l8_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_x_Slot_ae10_slot0_encode, Opcode_ae_l8_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8_xp_Slot_ae_slot0_encode, Opcode_ae_l8_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8_xp_Slot_ae2_slot0_encode, Opcode_ae_l8_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l8_xp_Slot_ae3_slot0_encode, Opcode_ae_l8_xp_Slot_ae3_slot1_encode, Opcode_ae_l8_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8_xp_Slot_ae8_slot0_encode, Opcode_ae_l8_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8_xp_Slot_ae9_slot0_encode, Opcode_ae_l8_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8_xp_Slot_ae10_slot0_encode, Opcode_ae_l8_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_xc_Slot_ae_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_xc_Slot_ae2_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l32f24_xc_Slot_ae3_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae3_slot1_encode, Opcode_ae_l32f24_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_xc_Slot_ae9_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_xc_Slot_ae10_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae_slot0_encode, Opcode_ae_l32f24_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae2_slot0_encode, Opcode_ae_l32f24_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae9_slot0_encode, Opcode_ae_l32f24_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae10_slot0_encode, Opcode_ae_l32f24_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_i_Slot_ae_slot0_encode, Opcode_ae_l32f24_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_i_Slot_ae2_slot0_encode, Opcode_ae_l32f24_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l32f24_i_Slot_ae3_slot0_encode, Opcode_ae_l32f24_i_Slot_ae3_slot1_encode, Opcode_ae_l32f24_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_i_Slot_ae9_slot0_encode, Opcode_ae_l32f24_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_i_Slot_ae10_slot0_encode, Opcode_ae_l32f24_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_ip_Slot_ae_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_ip_Slot_ae2_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l32f24_ip_Slot_ae3_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae3_slot1_encode, Opcode_ae_l32f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_ip_Slot_ae9_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_ip_Slot_ae10_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_x_Slot_ae_slot0_encode, Opcode_ae_l32f24_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_x_Slot_ae2_slot0_encode, Opcode_ae_l32f24_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l32f24_x_Slot_ae3_slot0_encode, Opcode_ae_l32f24_x_Slot_ae3_slot1_encode, Opcode_ae_l32f24_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_x_Slot_ae9_slot0_encode, Opcode_ae_l32f24_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_x_Slot_ae10_slot0_encode, Opcode_ae_l32f24_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32f24_xp_Slot_ae_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32f24_xp_Slot_ae2_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l32f24_xp_Slot_ae3_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae3_slot1_encode, Opcode_ae_l32f24_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_xp_Slot_ae9_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32f24_xp_Slot_ae10_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_xc_Slot_ae_slot0_encode, Opcode_ae_l32_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_xc_Slot_ae2_slot0_encode, Opcode_ae_l32_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l32_xc_Slot_ae3_slot0_encode, Opcode_ae_l32_xc_Slot_ae3_slot1_encode, Opcode_ae_l32_xc_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32_xc_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_xc_Slot_ae8_slot0_encode, Opcode_ae_l32_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_xc_Slot_ae9_slot0_encode, Opcode_ae_l32_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_xc_Slot_ae10_slot0_encode, Opcode_ae_l32_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_xc1_Slot_ae_slot0_encode, Opcode_ae_l32_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_xc1_Slot_ae2_slot0_encode, Opcode_ae_l32_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_xc1_Slot_ae8_slot0_encode, Opcode_ae_l32_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_xc1_Slot_ae9_slot0_encode, Opcode_ae_l32_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_xc1_Slot_ae10_slot0_encode, Opcode_ae_l32_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_i_Slot_ae_slot0_encode, Opcode_ae_l32_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_i_Slot_ae2_slot0_encode, Opcode_ae_l32_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l32_i_Slot_ae3_slot0_encode, Opcode_ae_l32_i_Slot_ae3_slot1_encode, Opcode_ae_l32_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32_i_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_i_Slot_ae8_slot0_encode, Opcode_ae_l32_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_i_Slot_ae9_slot0_encode, Opcode_ae_l32_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_i_Slot_ae10_slot0_encode, Opcode_ae_l32_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_ip_Slot_ae_slot0_encode, Opcode_ae_l32_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_ip_Slot_ae2_slot0_encode, Opcode_ae_l32_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l32_ip_Slot_ae3_slot0_encode, Opcode_ae_l32_ip_Slot_ae3_slot1_encode, Opcode_ae_l32_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32_ip_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_ip_Slot_ae8_slot0_encode, Opcode_ae_l32_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_ip_Slot_ae9_slot0_encode, Opcode_ae_l32_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_ip_Slot_ae10_slot0_encode, Opcode_ae_l32_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_x_Slot_ae_slot0_encode, Opcode_ae_l32_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_x_Slot_ae2_slot0_encode, Opcode_ae_l32_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l32_x_Slot_ae3_slot0_encode, Opcode_ae_l32_x_Slot_ae3_slot1_encode, Opcode_ae_l32_x_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32_x_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_x_Slot_ae8_slot0_encode, Opcode_ae_l32_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_x_Slot_ae9_slot0_encode, Opcode_ae_l32_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_x_Slot_ae10_slot0_encode, Opcode_ae_l32_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32_xp_Slot_ae_slot0_encode, Opcode_ae_l32_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32_xp_Slot_ae2_slot0_encode, Opcode_ae_l32_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l32_xp_Slot_ae3_slot0_encode, Opcode_ae_l32_xp_Slot_ae3_slot1_encode, Opcode_ae_l32_xp_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32_xp_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_xp_Slot_ae8_slot0_encode, Opcode_ae_l32_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l32_xp_Slot_ae9_slot0_encode, Opcode_ae_l32_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32_xp_Slot_ae10_slot0_encode, Opcode_ae_l32_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32m_xc_Slot_ae_slot0_encode, Opcode_ae_l32m_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32m_xc_Slot_ae2_slot0_encode, Opcode_ae_l32m_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l32m_xc_Slot_ae3_slot0_encode, Opcode_ae_l32m_xc_Slot_ae3_slot1_encode, Opcode_ae_l32m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32m_xc_Slot_ae8_slot0_encode, Opcode_ae_l32m_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l32m_xc_Slot_ae9_slot0_encode, Opcode_ae_l32m_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32m_xc_Slot_ae10_slot0_encode, Opcode_ae_l32m_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32m_i_Slot_ae_slot0_encode, Opcode_ae_l32m_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32m_i_Slot_ae2_slot0_encode, Opcode_ae_l32m_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l32m_i_Slot_ae3_slot0_encode, Opcode_ae_l32m_i_Slot_ae3_slot1_encode, Opcode_ae_l32m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32m_i_Slot_ae8_slot0_encode, Opcode_ae_l32m_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l32m_i_Slot_ae9_slot0_encode, Opcode_ae_l32m_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32m_i_Slot_ae10_slot0_encode, Opcode_ae_l32m_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32m_iu_Slot_ae_slot0_encode, Opcode_ae_l32m_iu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32m_iu_Slot_ae2_slot0_encode, Opcode_ae_l32m_iu_Slot_ae2_slot1_encode, 0, Opcode_ae_l32m_iu_Slot_ae3_slot0_encode, Opcode_ae_l32m_iu_Slot_ae3_slot1_encode, Opcode_ae_l32m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32m_iu_Slot_ae8_slot0_encode, Opcode_ae_l32m_iu_Slot_ae8_slot1_encode, 0, Opcode_ae_l32m_iu_Slot_ae9_slot0_encode, Opcode_ae_l32m_iu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32m_iu_Slot_ae10_slot0_encode, Opcode_ae_l32m_iu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32m_x_Slot_ae_slot0_encode, Opcode_ae_l32m_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32m_x_Slot_ae2_slot0_encode, Opcode_ae_l32m_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l32m_x_Slot_ae3_slot0_encode, Opcode_ae_l32m_x_Slot_ae3_slot1_encode, Opcode_ae_l32m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32m_x_Slot_ae8_slot0_encode, Opcode_ae_l32m_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l32m_x_Slot_ae9_slot0_encode, Opcode_ae_l32m_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32m_x_Slot_ae10_slot0_encode, Opcode_ae_l32m_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32m_xu_Slot_ae_slot0_encode, Opcode_ae_l32m_xu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32m_xu_Slot_ae2_slot0_encode, Opcode_ae_l32m_xu_Slot_ae2_slot1_encode, 0, Opcode_ae_l32m_xu_Slot_ae3_slot0_encode, Opcode_ae_l32m_xu_Slot_ae3_slot1_encode, Opcode_ae_l32m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32m_xu_Slot_ae8_slot0_encode, Opcode_ae_l32m_xu_Slot_ae8_slot1_encode, 0, Opcode_ae_l32m_xu_Slot_ae9_slot0_encode, Opcode_ae_l32m_xu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32m_xu_Slot_ae10_slot0_encode, Opcode_ae_l32m_xu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x2m_xc_Slot_ae_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_xc_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x2m_xc_Slot_ae3_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_xc_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_xc_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_xc_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_xc1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_xc1_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x2m_i_Slot_ae_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_i_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x2m_i_Slot_ae3_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_i_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_i_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_i_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x2m_iu_Slot_ae_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_iu_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x2m_iu_Slot_ae3_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_iu_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_iu_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_iu_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x2m_x_Slot_ae_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_x_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x2m_x_Slot_ae3_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_x_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_x_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_x_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x2m_xu_Slot_ae_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_xu_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x2m_xu_Slot_ae3_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_xu_Slot_ae8_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x2m_xu_Slot_ae9_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x2m_xu_Slot_ae10_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_xc_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_xc1_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_i_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_ip_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_rip_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ri_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_ri_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_ri_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_ric_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_ric1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ric1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_ric1_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_ric1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_ric1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_x_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2f24_xp_Slot_ae3_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae7_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae9_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae10_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_xc_Slot_ae_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_xc_Slot_ae3_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae3_slot1_encode, Opcode_ae_l32x2_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_xc_Slot_ae7_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_xc_Slot_ae8_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_xc_Slot_ae9_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_xc_Slot_ae10_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae2_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae7_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae8_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_xc1_Slot_ae9_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae10_slot0_encode, Opcode_ae_l32x2_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_i_Slot_ae_slot0_encode, Opcode_ae_l32x2_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_i_Slot_ae2_slot0_encode, Opcode_ae_l32x2_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_i_Slot_ae3_slot0_encode, Opcode_ae_l32x2_i_Slot_ae3_slot1_encode, Opcode_ae_l32x2_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32x2_i_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l32x2_i_Slot_ae7_slot0_encode, Opcode_ae_l32x2_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_i_Slot_ae8_slot0_encode, Opcode_ae_l32x2_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_i_Slot_ae9_slot0_encode, Opcode_ae_l32x2_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_i_Slot_ae10_slot0_encode, Opcode_ae_l32x2_i_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2_i_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_ip_Slot_ae_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_ip_Slot_ae3_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae3_slot1_encode, Opcode_ae_l32x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32x2_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l32x2_ip_Slot_ae7_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_ip_Slot_ae8_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_ip_Slot_ae9_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_ip_Slot_ae10_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_ric_Slot_ae_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_ric_Slot_ae2_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_ric_Slot_ae3_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae3_slot1_encode, Opcode_ae_l32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_ric_Slot_ae7_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_ric_Slot_ae8_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_ric_Slot_ae9_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_ric_Slot_ae10_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae2_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae7_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae8_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_ric1_Slot_ae9_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae10_slot0_encode, Opcode_ae_l32x2_ric1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_x_Slot_ae_slot0_encode, Opcode_ae_l32x2_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_x_Slot_ae2_slot0_encode, Opcode_ae_l32x2_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_x_Slot_ae3_slot0_encode, Opcode_ae_l32x2_x_Slot_ae3_slot1_encode, Opcode_ae_l32x2_x_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32x2_x_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l32x2_x_Slot_ae7_slot0_encode, Opcode_ae_l32x2_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_x_Slot_ae8_slot0_encode, Opcode_ae_l32x2_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_x_Slot_ae9_slot0_encode, Opcode_ae_l32x2_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_x_Slot_ae10_slot0_encode, Opcode_ae_l32x2_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_xp_Slot_ae_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_xp_Slot_ae3_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae3_slot1_encode, Opcode_ae_l32x2_xp_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l32x2_xp_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l32x2_xp_Slot_ae7_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2_xp_Slot_ae8_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_xp_Slot_ae9_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2_xp_Slot_ae10_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2_xp_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_xc_Slot_ae_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_xc_Slot_ae2_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_xc_Slot_ae3_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae3_slot1_encode, Opcode_ae_l16x4_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc_Slot_ae7_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_xc_Slot_ae8_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_xc_Slot_ae9_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_xc_Slot_ae10_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae2_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae7_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae8_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_xc1_Slot_ae9_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae10_slot0_encode, Opcode_ae_l16x4_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_i_Slot_ae_slot0_encode, Opcode_ae_l16x4_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_i_Slot_ae2_slot0_encode, Opcode_ae_l16x4_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_i_Slot_ae3_slot0_encode, Opcode_ae_l16x4_i_Slot_ae3_slot1_encode, Opcode_ae_l16x4_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16x4_i_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l16x4_i_Slot_ae7_slot0_encode, Opcode_ae_l16x4_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_i_Slot_ae8_slot0_encode, Opcode_ae_l16x4_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_i_Slot_ae9_slot0_encode, Opcode_ae_l16x4_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_i_Slot_ae10_slot0_encode, Opcode_ae_l16x4_i_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4_i_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_ip_Slot_ae_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_ip_Slot_ae2_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_ip_Slot_ae3_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae3_slot1_encode, Opcode_ae_l16x4_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_l16x4_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l16x4_ip_Slot_ae7_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_ip_Slot_ae8_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_ip_Slot_ae9_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_ip_Slot_ae10_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_x_Slot_ae_slot0_encode, Opcode_ae_l16x4_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_x_Slot_ae2_slot0_encode, Opcode_ae_l16x4_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_x_Slot_ae3_slot0_encode, Opcode_ae_l16x4_x_Slot_ae3_slot1_encode, Opcode_ae_l16x4_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_x_Slot_ae7_slot0_encode, Opcode_ae_l16x4_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_x_Slot_ae8_slot0_encode, Opcode_ae_l16x4_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_x_Slot_ae9_slot0_encode, Opcode_ae_l16x4_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_x_Slot_ae10_slot0_encode, Opcode_ae_l16x4_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_xp_Slot_ae_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_xp_Slot_ae2_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_xp_Slot_ae3_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae3_slot1_encode, Opcode_ae_l16x4_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xp_Slot_ae7_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4_xp_Slot_ae8_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_xp_Slot_ae9_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4_xp_Slot_ae10_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4_xp_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_xc_Slot_ae_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_xc_Slot_ae2_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_xc_Slot_ae3_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae3_slot1_encode, Opcode_ae_l8x8_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_xc_Slot_ae7_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_xc_Slot_ae8_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_xc_Slot_ae9_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_xc_Slot_ae10_slot0_encode, Opcode_ae_l8x8_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae2_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae7_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae8_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_xc1_Slot_ae9_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_xc1_Slot_ae10_slot0_encode, Opcode_ae_l8x8_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_i_Slot_ae_slot0_encode, Opcode_ae_l8x8_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_i_Slot_ae2_slot0_encode, Opcode_ae_l8x8_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_i_Slot_ae3_slot0_encode, Opcode_ae_l8x8_i_Slot_ae3_slot1_encode, Opcode_ae_l8x8_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_i_Slot_ae7_slot0_encode, Opcode_ae_l8x8_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_i_Slot_ae8_slot0_encode, Opcode_ae_l8x8_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_i_Slot_ae9_slot0_encode, Opcode_ae_l8x8_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_i_Slot_ae10_slot0_encode, Opcode_ae_l8x8_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_ip_Slot_ae_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_ip_Slot_ae3_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae3_slot1_encode, Opcode_ae_l8x8_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_ip_Slot_ae7_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_ip_Slot_ae8_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_ip_Slot_ae9_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_ip_Slot_ae10_slot0_encode, Opcode_ae_l8x8_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_x_Slot_ae_slot0_encode, Opcode_ae_l8x8_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_x_Slot_ae2_slot0_encode, Opcode_ae_l8x8_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_x_Slot_ae3_slot0_encode, Opcode_ae_l8x8_x_Slot_ae3_slot1_encode, Opcode_ae_l8x8_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_x_Slot_ae7_slot0_encode, Opcode_ae_l8x8_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_x_Slot_ae8_slot0_encode, Opcode_ae_l8x8_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_x_Slot_ae9_slot0_encode, Opcode_ae_l8x8_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_x_Slot_ae10_slot0_encode, Opcode_ae_l8x8_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_xp_Slot_ae_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_xp_Slot_ae2_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_xp_Slot_ae3_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae3_slot1_encode, Opcode_ae_l8x8_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_xp_Slot_ae7_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8_xp_Slot_ae8_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_xp_Slot_ae9_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8_xp_Slot_ae10_slot0_encode, Opcode_ae_l8x8_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_xc_Slot_ae_slot0_encode, Opcode_ae_l64_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_xc_Slot_ae2_slot0_encode, Opcode_ae_l64_xc_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_xc_Slot_ae3_slot0_encode, Opcode_ae_l64_xc_Slot_ae3_slot1_encode, Opcode_ae_l64_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_xc_Slot_ae7_slot0_encode, Opcode_ae_l64_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_xc_Slot_ae8_slot0_encode, Opcode_ae_l64_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_xc_Slot_ae9_slot0_encode, Opcode_ae_l64_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_xc_Slot_ae10_slot0_encode, Opcode_ae_l64_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_xc1_Slot_ae_slot0_encode, Opcode_ae_l64_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_xc1_Slot_ae2_slot0_encode, Opcode_ae_l64_xc1_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_ae_l64_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_xc1_Slot_ae7_slot0_encode, Opcode_ae_l64_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_xc1_Slot_ae8_slot0_encode, Opcode_ae_l64_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_xc1_Slot_ae9_slot0_encode, Opcode_ae_l64_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_xc1_Slot_ae10_slot0_encode, Opcode_ae_l64_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_i_Slot_ae_slot0_encode, Opcode_ae_l64_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_i_Slot_ae2_slot0_encode, Opcode_ae_l64_i_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_i_Slot_ae3_slot0_encode, Opcode_ae_l64_i_Slot_ae3_slot1_encode, Opcode_ae_l64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_i_Slot_ae7_slot0_encode, Opcode_ae_l64_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_i_Slot_ae8_slot0_encode, Opcode_ae_l64_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_i_Slot_ae9_slot0_encode, Opcode_ae_l64_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_i_Slot_ae10_slot0_encode, Opcode_ae_l64_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_ip_Slot_ae_slot0_encode, Opcode_ae_l64_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_ip_Slot_ae2_slot0_encode, Opcode_ae_l64_ip_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_ip_Slot_ae3_slot0_encode, Opcode_ae_l64_ip_Slot_ae3_slot1_encode, Opcode_ae_l64_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_ip_Slot_ae7_slot0_encode, Opcode_ae_l64_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_ip_Slot_ae8_slot0_encode, Opcode_ae_l64_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_ip_Slot_ae9_slot0_encode, Opcode_ae_l64_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_ip_Slot_ae10_slot0_encode, Opcode_ae_l64_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_x_Slot_ae_slot0_encode, Opcode_ae_l64_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_x_Slot_ae2_slot0_encode, Opcode_ae_l64_x_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_x_Slot_ae3_slot0_encode, Opcode_ae_l64_x_Slot_ae3_slot1_encode, Opcode_ae_l64_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_x_Slot_ae7_slot0_encode, Opcode_ae_l64_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_x_Slot_ae8_slot0_encode, Opcode_ae_l64_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_x_Slot_ae9_slot0_encode, Opcode_ae_l64_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_x_Slot_ae10_slot0_encode, Opcode_ae_l64_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_xp_Slot_ae_slot0_encode, Opcode_ae_l64_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_xp_Slot_ae2_slot0_encode, Opcode_ae_l64_xp_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_xp_Slot_ae3_slot0_encode, Opcode_ae_l64_xp_Slot_ae3_slot1_encode, Opcode_ae_l64_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_xp_Slot_ae7_slot0_encode, Opcode_ae_l64_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64_xp_Slot_ae8_slot0_encode, Opcode_ae_l64_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_xp_Slot_ae9_slot0_encode, Opcode_ae_l64_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64_xp_Slot_ae10_slot0_encode, Opcode_ae_l64_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x2m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x2m_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x2m_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x2m_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x2m_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x2m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x2m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x2m_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x2m_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x2m_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x2m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x2m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2f24_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_ric_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_ric_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_x_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_xp_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2rng_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2rng_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2rng_x_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2rng_xp_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_x_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_xp_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s8x8_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s16m_l_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16m_l_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s16m_l_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae3_slot0_encode, 0, Opcode_ae_s16m_l_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16m_l_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s16m_l_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae3_slot0_encode, 0, Opcode_ae_s16m_l_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32f24_l_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32f24_l_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32f24_l_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32f24_l_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32f24_l_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_l_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_l_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_l_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_l_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_l_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_l_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_l_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_l_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_l_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_l_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_l_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_l_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_l_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_h_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_h_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32_h_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_h_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_h_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_h_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_h_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_h_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_h_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_h_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32_h_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32_h_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32_h_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32_h_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_h_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32_h_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16_0_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s16_0_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16_0_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s16_0_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16_0_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s16_0_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16_0_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s16_0_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16_0_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16_0_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16_0_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s16_0_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16_0_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8_0_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s8_0_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s8_0_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8_0_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s8_0_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8_0_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s8_0_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8_0_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s8_0_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8_0_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8_0_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8_0_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8_0_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s8_0_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8_0_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8_0_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s64_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32m_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32m_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32m_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32m_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32m_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32m_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32m_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32m_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_iu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32m_iu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32m_iu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32m_iu_Slot_ae3_slot0_encode, 0, Opcode_ae_s32m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_iu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32m_iu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32m_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32m_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32m_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32m_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_xu_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32m_xu_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32m_xu_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32m_xu_Slot_ae3_slot0_encode, 0, Opcode_ae_s32m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_xu_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32m_xu_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2_xc2_Slot_ae_slot0_encode, Opcode_ae_l32x2_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2_xc2_Slot_ae2_slot0_encode, Opcode_ae_l32x2_xc2_Slot_ae2_slot1_encode, 0, Opcode_ae_l32x2_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_l32x2_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_xc2_Slot_ae8_slot0_encode, Opcode_ae_l32x2_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2_xc2_Slot_ae9_slot0_encode, Opcode_ae_l32x2_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4_xc2_Slot_ae_slot0_encode, Opcode_ae_l16x4_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4_xc2_Slot_ae2_slot0_encode, Opcode_ae_l16x4_xc2_Slot_ae2_slot1_encode, 0, Opcode_ae_l16x4_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_l16x4_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc2_Slot_ae8_slot0_encode, Opcode_ae_l16x4_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4_xc2_Slot_ae9_slot0_encode, Opcode_ae_l16x4_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8_xc2_Slot_ae_slot0_encode, Opcode_ae_l8x8_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8_xc2_Slot_ae2_slot0_encode, Opcode_ae_l8x8_xc2_Slot_ae2_slot1_encode, 0, Opcode_ae_l8x8_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_l8x8_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8_xc2_Slot_ae8_slot0_encode, Opcode_ae_l8x8_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8_xc2_Slot_ae9_slot0_encode, Opcode_ae_l8x8_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64_xc2_Slot_ae_slot0_encode, Opcode_ae_l64_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64_xc2_Slot_ae2_slot0_encode, Opcode_ae_l64_xc2_Slot_ae2_slot1_encode, 0, Opcode_ae_l64_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_l64_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_xc2_Slot_ae8_slot0_encode, Opcode_ae_l64_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l64_xc2_Slot_ae9_slot0_encode, Opcode_ae_l64_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2_xc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_xc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4_xc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_xc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8_xc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s8x8_xc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s8x8_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_s8x8_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64_xc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s64_xc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s64_xc2_Slot_ae3_slot0_encode, 0, Opcode_ae_s64_xc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4rng_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4rng_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4rng_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4rng_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4rng_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4rng_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4rng_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4rng_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4rng_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4rng_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4rng_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4rng_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4rng_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4rng_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4rng_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4rng_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4rng_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4rng_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4rng_x_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4rng_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4rng_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4rng_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4rng_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4rng_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4rng_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4rng_xp_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_s16x4rng_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4rng_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_xc_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_xc_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2x2_xc_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_xc1_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_xc1_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2x2_xc1_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_i_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_i_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_i_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_i_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_i_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_i_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_ip_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2x2_ip_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_x_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_x_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_x_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_x_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_x_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_x_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae7_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_xp_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae10_slot0_encode, Opcode_ae_l32x2x2_xp_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l32x2x2_xp_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_xc_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_xc_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4x2_xc_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_xc1_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_xc1_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4x2_xc1_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_i_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_i_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_i_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_i_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_i_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_i_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_ip_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4x2_ip_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_x_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_x_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_x_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_x_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_x_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_x_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae7_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_xp_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae10_slot0_encode, Opcode_ae_l16x4x2_xp_Slot_ae10_slot1_encode, 0, 0, 0, Opcode_ae_l16x4x2_xp_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_xc_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_xc_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_xc_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_xc1_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc1_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_xc1_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc1_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_xc1_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc1_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_i_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_i_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_i_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_i_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_i_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_i_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_ip_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_ip_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_x_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_x_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_x_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_x_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_x_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_x_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_xp_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_xp_Slot_ae7_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xp_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_xp_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xp_Slot_ae10_slot0_encode, Opcode_ae_l8x8x2_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_xc_Slot_ae_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_xc_Slot_ae7_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_xc_Slot_ae8_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_xc_Slot_ae9_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_xc_Slot_ae10_slot0_encode, Opcode_ae_l64x2_xc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_xc1_Slot_ae_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_xc1_Slot_ae2_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_xc1_Slot_ae7_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_xc1_Slot_ae8_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_xc1_Slot_ae9_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_xc1_Slot_ae10_slot0_encode, Opcode_ae_l64x2_xc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_i_Slot_ae_slot0_encode, Opcode_ae_l64x2_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_i_Slot_ae2_slot0_encode, Opcode_ae_l64x2_i_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_i_Slot_ae7_slot0_encode, Opcode_ae_l64x2_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_i_Slot_ae8_slot0_encode, Opcode_ae_l64x2_i_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_i_Slot_ae9_slot0_encode, Opcode_ae_l64x2_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_i_Slot_ae10_slot0_encode, Opcode_ae_l64x2_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_ip_Slot_ae_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_ip_Slot_ae7_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_ip_Slot_ae8_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_ip_Slot_ae9_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_ip_Slot_ae10_slot0_encode, Opcode_ae_l64x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_x_Slot_ae_slot0_encode, Opcode_ae_l64x2_x_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_x_Slot_ae2_slot0_encode, Opcode_ae_l64x2_x_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_x_Slot_ae7_slot0_encode, Opcode_ae_l64x2_x_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_x_Slot_ae8_slot0_encode, Opcode_ae_l64x2_x_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_x_Slot_ae9_slot0_encode, Opcode_ae_l64x2_x_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_x_Slot_ae10_slot0_encode, Opcode_ae_l64x2_x_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_xp_Slot_ae_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_xp_Slot_ae7_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_l64x2_xp_Slot_ae8_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_xp_Slot_ae9_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_l64x2_xp_Slot_ae10_slot0_encode, Opcode_ae_l64x2_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_xc_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_xc1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_ip_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_x_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xp_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2rng_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2rng_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2rng_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2rng_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_ip_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2rng_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2rng_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2rng_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2rng_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2rng_xp_Slot_ae4_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_xc_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_xc1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_xc_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_xc1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x4ux2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x4ux2_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4ux2_i_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4ux2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x4ux2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x4ux2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x4ux2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4ux2_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4ux2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x4ux2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x4ux2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x4ux2_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4ux2_x_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4ux2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x4ux2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x4ux2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x4ux2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4ux2_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x4ux2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x4ux2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_xc_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_xc_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_xc_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_xc1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_xc1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_xc1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_x_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l32x2x2_xc2_Slot_ae_slot0_encode, Opcode_ae_l32x2x2_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l32x2x2_xc2_Slot_ae2_slot0_encode, Opcode_ae_l32x2x2_xc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2x2_xc2_Slot_ae8_slot0_encode, Opcode_ae_l32x2x2_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l32x2x2_xc2_Slot_ae9_slot0_encode, Opcode_ae_l32x2x2_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l16x4x2_xc2_Slot_ae_slot0_encode, Opcode_ae_l16x4x2_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x4x2_xc2_Slot_ae2_slot0_encode, Opcode_ae_l16x4x2_xc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4x2_xc2_Slot_ae8_slot0_encode, Opcode_ae_l16x4x2_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l16x4x2_xc2_Slot_ae9_slot0_encode, Opcode_ae_l16x4x2_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x8x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l8x8x2_xc2_Slot_ae_slot0_encode, Opcode_ae_l8x8x2_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l8x8x2_xc2_Slot_ae2_slot0_encode, Opcode_ae_l8x8x2_xc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l8x8x2_xc2_Slot_ae8_slot0_encode, Opcode_ae_l8x8x2_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l8x8x2_xc2_Slot_ae9_slot0_encode, Opcode_ae_l8x8x2_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_l64x2_xc2_Slot_ae_slot0_encode, Opcode_ae_l64x2_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l64x2_xc2_Slot_ae2_slot0_encode, Opcode_ae_l64x2_xc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_l64x2_xc2_Slot_ae8_slot0_encode, Opcode_ae_l64x2_xc2_Slot_ae8_slot1_encode, 0, Opcode_ae_l64x2_xc2_Slot_ae9_slot0_encode, Opcode_ae_l64x2_xc2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2x2_xc2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2x2_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s32x2x2_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2_xc2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s16x4x2_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s8x8x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s8x8x2_xc2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s8x8x2_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s8x8x2_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64x2_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_s64x2_xc2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s64x2_xc2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_s64x2_xc2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2rng_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2rng_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2rng_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2rng_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2rng_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2rng_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2rng_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2rng_x_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2rng_x_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4x2rng_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4x2rng_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4x2rng_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_zalign64_encode_fns[] = { + 0, 0, 0, Opcode_ae_zalign64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_zalign64_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_zalign64_Slot_ae3_slot0_encode, 0, Opcode_ae_zalign64_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lalign64_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_lalign64_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lalign64_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_lalign64_i_Slot_ae3_slot0_encode, 0, Opcode_ae_lalign64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_salign64_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_salign64_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_salign64_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_salign64_i_Slot_ae3_slot0_encode, 0, Opcode_ae_salign64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movalign_encode_fns[] = { + 0, 0, 0, Opcode_ae_movalign_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movalign_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movalign_Slot_ae3_slot0_encode, 0, Opcode_ae_movalign_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la64_pp_encode_fns[] = { + 0, 0, 0, Opcode_ae_la64_pp_Slot_ae_slot0_encode, Opcode_ae_la64_pp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la64_pp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la64_pp_Slot_ae3_slot0_encode, Opcode_ae_la64_pp_Slot_ae3_slot1_encode, Opcode_ae_la64_pp_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la64_pp_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24pos_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24pos_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24pos_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la24pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24neg_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24neg_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24neg_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24neg_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la24neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24pos_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24neg_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24neg_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2pos_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2pos_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2pos_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2neg_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2neg_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2neg_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2neg_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2pos_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2neg_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2neg_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2pos_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2pos_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2pos_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2neg_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2neg_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2neg_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2neg_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2pos_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2neg_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2neg_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2pos_pc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2pos_pc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2pos_pc2_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2pos_pc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4pos_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4pos_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4pos_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4neg_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4neg_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4neg_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4neg_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4pos_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4neg_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4neg_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4pos_pc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4pos_pc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4pos_pc2_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4pos_pc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8pos_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8pos_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8pos_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8neg_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8neg_pc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8neg_pc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8neg_pc_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8pos_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la8x8pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8neg_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8neg_pc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la8x8neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8pos_pc2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8pos_pc2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8pos_pc2_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8pos_pc2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2pos_pc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc1_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2pos_pc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2pos_pc2_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2pos_pc2_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2pos_pc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc1_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2pos_pc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2pos_pc2_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2pos_pc2_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2pos_pc_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2pos_pc_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2pos_pc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc1_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2pos_pc1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2pos_pc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2pos_pc2_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2pos_pc2_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa64pos_fp_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa64pos_fp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa64pos_fp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa64pos_fp_Slot_ae3_slot0_encode, 0, Opcode_ae_sa64pos_fp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa64neg_fp_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa64neg_fp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa64neg_fp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa64neg_fp_Slot_ae3_slot0_encode, 0, Opcode_ae_sa64neg_fp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic_Slot_ae7_slot0_encode, Opcode_ae_la32x2_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_ic_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ic_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae7_slot0_encode, Opcode_ae_la32x2_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ic1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic2_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ic2_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ip_Slot_ae_slot0_encode, Opcode_ae_la32x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2_ip_Slot_ae3_slot0_encode, Opcode_ae_la32x2_ip_Slot_ae3_slot1_encode, Opcode_ae_la32x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la32x2_ip_Slot_ae7_slot0_encode, Opcode_ae_la32x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_ip_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_rip_Slot_ae_slot0_encode, Opcode_ae_la32x2_rip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_rip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la32x2_rip_Slot_ae7_slot0_encode, Opcode_ae_la32x2_rip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_rip_Slot_ae8_slot0_encode, Opcode_ae_la32x2_rip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ric_Slot_ae7_slot0_encode, Opcode_ae_la32x2_ric_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_ric_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ric_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae7_slot0_encode, Opcode_ae_la32x2_ric1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae8_slot0_encode, Opcode_ae_la32x2_ric1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic_Slot_ae7_slot0_encode, Opcode_ae_la16x4_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_ic_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ic_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae7_slot0_encode, Opcode_ae_la16x4_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ic1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic2_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ic2_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ip_Slot_ae_slot0_encode, Opcode_ae_la16x4_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4_ip_Slot_ae3_slot0_encode, Opcode_ae_la16x4_ip_Slot_ae3_slot1_encode, Opcode_ae_la16x4_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la16x4_ip_Slot_ae7_slot0_encode, Opcode_ae_la16x4_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_ip_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_rip_Slot_ae_slot0_encode, Opcode_ae_la16x4_rip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4_rip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_rip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la16x4_rip_Slot_ae7_slot0_encode, Opcode_ae_la16x4_rip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_rip_Slot_ae8_slot0_encode, Opcode_ae_la16x4_rip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la16x4_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la16x4_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ric_Slot_ae7_slot0_encode, Opcode_ae_la16x4_ric_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_ric_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ric_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae7_slot0_encode, Opcode_ae_la16x4_ric1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae8_slot0_encode, Opcode_ae_la16x4_ric1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8_ic_Slot_ae7_slot0_encode, Opcode_ae_la8x8_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_ic_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ic_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la8x8_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8_ic1_Slot_ae7_slot0_encode, Opcode_ae_la8x8_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_ic1_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ic1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8_ic2_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ic2_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ip_Slot_ae_slot0_encode, Opcode_ae_la8x8_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8_ip_Slot_ae3_slot0_encode, Opcode_ae_la8x8_ip_Slot_ae3_slot1_encode, Opcode_ae_la8x8_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la8x8_ip_Slot_ae7_slot0_encode, Opcode_ae_la8x8_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_ip_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_rip_Slot_ae_slot0_encode, Opcode_ae_la8x8_rip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8_rip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_rip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la8x8_rip_Slot_ae7_slot0_encode, Opcode_ae_la8x8_rip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_rip_Slot_ae8_slot0_encode, Opcode_ae_la8x8_rip_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la8x8_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la8x8_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8_ric_Slot_ae7_slot0_encode, Opcode_ae_la8x8_ric_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_ric_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ric_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la8x8_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la8x8_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8_ric1_Slot_ae7_slot0_encode, Opcode_ae_la8x8_ric1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8_ric1_Slot_ae8_slot0_encode, Opcode_ae_la8x8_ric1_Slot_ae8_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2f24_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_ic_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_ic1_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae_slot0_encode, Opcode_ae_la32x2f24_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_ip_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae_slot0_encode, Opcode_ae_la32x2f24_rip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae6_slot1_encode, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_rip_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_ric_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae7_slot0_encode, Opcode_ae_la32x2f24_ric1_Slot_ae7_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la24_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_la24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_la24x2_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_la24x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la24x2_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_la24x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ic2_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa16x4_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa16x4_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_sa16x4_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ic2_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa16x4_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa16x4_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa16x4_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa8x8_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa8x8_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ic_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa8x8_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ic1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ic2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ic2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa8x8_ic2_Slot_ae3_slot0_encode, 0, Opcode_ae_sa8x8_ic2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ic2_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa8x8_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa8x8_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa8x8_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa8x8_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_rip_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa8x8_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa8x8_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ric_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa8x8_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa8x8_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8_ric1_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2f24_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2f24_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa32x2f24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24_l_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24_l_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24_l_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24_l_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24_l_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24_l_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24_l_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24_l_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24_l_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24_l_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24_l_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24_l_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_ic_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_ic_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24x2_ic_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24x2_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_rip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_rip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_rip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24x2_rip_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ric_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_ric_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_ric_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sa24x2_ric_Slot_ae3_slot0_encode, 0, Opcode_ae_sa24x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ric1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa24x2_ric1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sa24x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addicirc_encode_fns[] = { + 0, 0, 0, Opcode_ae_addicirc_Slot_ae_slot0_encode, Opcode_ae_addicirc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_addicirc_Slot_ae2_slot0_encode, Opcode_ae_addicirc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcirc_xc2_encode_fns[] = { + 0, 0, 0, Opcode_ae_addcirc_xc2_Slot_ae_slot0_encode, Opcode_ae_addcirc_xc2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_addcirc_xc2_Slot_ae2_slot0_encode, Opcode_ae_addcirc_xc2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addcirc_xc2_Slot_ae4_slot0_encode, Opcode_ae_addcirc_xc2_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcirc_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_addcirc_xc1_Slot_ae_slot0_encode, Opcode_ae_addcirc_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_addcirc_xc1_Slot_ae2_slot0_encode, Opcode_ae_addcirc_xc1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addcirc_xc1_Slot_ae4_slot0_encode, Opcode_ae_addcirc_xc1_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcirc_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_addcirc_xc_Slot_ae_slot0_encode, Opcode_ae_addcirc_xc_Slot_ae_slot1_encode, 0, 0, Opcode_ae_addcirc_xc_Slot_ae2_slot0_encode, Opcode_ae_addcirc_xc_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addcirc_xc_Slot_ae4_slot0_encode, Opcode_ae_addcirc_xc_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32ra64s_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s32ra64s_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32ra64s_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32ra64s_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s32ra64s_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32ra64s_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s32ra64s_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32ra64s_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s32ra64s_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32ra64s_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32ra64s_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32ra64s_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_i_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_i_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24ra64s_i_Slot_ae3_slot0_encode, 0, Opcode_ae_s24ra64s_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24ra64s_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s24ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_x_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_x_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_x_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24ra64s_x_Slot_ae3_slot0_encode, 0, Opcode_ae_s24ra64s_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_xp_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24ra64s_xp_Slot_ae3_slot0_encode, 0, Opcode_ae_s24ra64s_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_xc_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_xc_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_xc_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24ra64s_xc_Slot_ae3_slot0_encode, 0, Opcode_ae_s24ra64s_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_xc1_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24ra64s_xc1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24ra64s_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_s24ra64s_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2ra64s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24x2ra64s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4ra32s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_s16x4ra32s_ip_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_s16x4ra32s_ip_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_s16x4ra32s_ip_Slot_ae3_slot0_encode, 0, Opcode_ae_s16x4ra32s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addbrba32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addbrba32_Slot_ae_slot0_encode, Opcode_ae_addbrba32_Slot_ae_slot1_encode, 0, 0, Opcode_ae_addbrba32_Slot_ae2_slot0_encode, Opcode_ae_addbrba32_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_addbrba32_Slot_ae3_slot1_encode, 0, 0, 0, 0, Opcode_ae_addbrba32_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addbrba32_Slot_ae4_slot0_encode, Opcode_ae_addbrba32_Slot_ae4_slot1_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_l_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_l_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bitswap_encode_fns[] = { + 0, 0, 0, Opcode_ae_bitswap_Slot_ae_slot0_encode, Opcode_ae_bitswap_Slot_ae_slot1_encode, 0, 0, Opcode_ae_bitswap_Slot_ae2_slot0_encode, Opcode_ae_bitswap_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_bitswap_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32js_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32js_Slot_ae_slot0_encode, 0, Opcode_ae_mul32js_Slot_ae_slot2_encode, Opcode_ae_mul32js_Slot_ae_slot3_encode, Opcode_ae_mul32js_Slot_ae2_slot0_encode, 0, Opcode_ae_mul32js_Slot_ae2_slot2_encode, 0, 0, Opcode_ae_mul32js_Slot_ae5_slot0_encode, 0, Opcode_ae_mul32js_Slot_ae5_slot2_encode, Opcode_ae_mul32js_Slot_ae6_slot0_encode, 0, Opcode_ae_mul32js_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32js_Slot_ae4_slot2_encode, Opcode_ae_mul32js_Slot_ae4_slot3_encode, Opcode_ae_mul32js_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsub32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsub32s_Slot_ae_slot0_encode, 0, Opcode_ae_addandsub32s_Slot_ae_slot2_encode, Opcode_ae_addandsub32s_Slot_ae_slot3_encode, Opcode_ae_addandsub32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32s_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsub32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32s_Slot_ae4_slot2_encode, Opcode_ae_addandsub32s_Slot_ae4_slot3_encode, Opcode_ae_addandsub32s_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsub32js_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsub32js_Slot_ae_slot0_encode, 0, Opcode_ae_addandsub32js_Slot_ae_slot2_encode, Opcode_ae_addandsub32js_Slot_ae_slot3_encode, Opcode_ae_addandsub32js_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32js_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsub32js_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32js_Slot_ae4_slot2_encode, Opcode_ae_addandsub32js_Slot_ae4_slot3_encode, Opcode_ae_addandsub32js_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsubrng32_Slot_ae_slot0_encode, 0, Opcode_ae_addandsubrng32_Slot_ae_slot2_encode, Opcode_ae_addandsubrng32_Slot_ae_slot3_encode, Opcode_ae_addandsubrng32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsubrng32_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_Slot_ae4_slot2_encode, Opcode_ae_addandsubrng32_Slot_ae4_slot3_encode, Opcode_ae_addandsubrng32_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsubrng32_h_Slot_ae_slot0_encode, 0, Opcode_ae_addandsubrng32_h_Slot_ae_slot2_encode, Opcode_ae_addandsubrng32_h_Slot_ae_slot3_encode, Opcode_ae_addandsubrng32_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_h_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsubrng32_h_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_h_Slot_ae4_slot2_encode, Opcode_ae_addandsubrng32_h_Slot_ae4_slot3_encode, Opcode_ae_addandsubrng32_h_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsubrng32_l_Slot_ae_slot0_encode, 0, Opcode_ae_addandsubrng32_l_Slot_ae_slot2_encode, Opcode_ae_addandsubrng32_l_Slot_ae_slot3_encode, Opcode_ae_addandsubrng32_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_l_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsubrng32_l_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_l_Slot_ae4_slot2_encode, Opcode_ae_addandsubrng32_l_Slot_ae4_slot3_encode, Opcode_ae_addandsubrng32_l_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_addrng32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_addrng32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subrng32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_subrng32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rng32x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_rng32x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel16i_encode_fns[] = { + 0, 0, 0, Opcode_ae_sel16i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sel16i_Slot_ae_slot3_encode, Opcode_ae_sel16i_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_ae_sel16i_Slot_ae3_slot1_encode, Opcode_ae_sel16i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sel16i_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sel16i_Slot_ae9_slot0_encode, 0, 0, Opcode_ae_sel16i_Slot_ae9_slot3_encode, 0, 0, 0, Opcode_ae_sel16i_Slot_ae10_slot3_encode, 0, 0, 0, Opcode_ae_sel16i_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel16i_n_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sel16i_n_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sel16i_n_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sel16i_n_Slot_ae4_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_shortswap_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_shortswap_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movab4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movab4_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movab4_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movab2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movab2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movab2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movab_encode_fns[] = { + 0, 0, 0, Opcode_ae_movab_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movab_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba_encode_fns[] = { + 0, 0, 0, Opcode_ae_movba_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movba_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba1x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movba1x2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movba1x2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movba4_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movba4_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movba2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movba2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movb2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movb2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movb4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movb4_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt16x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt16x4_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movt16x4_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movt16x4_Slot_ae6_slot0_encode, 0, Opcode_ae_movt16x4_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movt16x4_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movf16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movf16x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movf16x4_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movf16x4_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movf16x4_Slot_ae6_slot0_encode, 0, Opcode_ae_movf16x4_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movf16x4_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt32x2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt32x2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movt32x2_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movt32x2_Slot_ae6_slot0_encode, 0, Opcode_ae_movt32x2_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movt32x2_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movf32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movf32x2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movf32x2_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movf32x2_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movf32x2_Slot_ae6_slot0_encode, 0, Opcode_ae_movf32x2_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movf32x2_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movsara7x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movsara7x2_Slot_ae_slot0_encode, Opcode_ae_movsara7x2_Slot_ae_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movsard7_encode_fns[] = { + 0, 0, 0, Opcode_ae_movsard7_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movsard7_Slot_ae2_slot0_encode, Opcode_ae_movsard7_Slot_ae2_slot1_encode, 0, Opcode_ae_movsard7_Slot_ae3_slot0_encode, 0, Opcode_ae_movsard7_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movasar_encode_fns[] = { + 0, 0, 0, Opcode_ae_movasar_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movasar_Slot_ae2_slot0_encode, Opcode_ae_movasar_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movda32x2_Slot_ae_slot0_encode, Opcode_ae_movda32x2_Slot_ae_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_movda32x2_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda32_encode_fns[] = { + 0, 0, 0, Opcode_ae_movda32_Slot_ae_slot0_encode, Opcode_ae_movda32_Slot_ae_slot1_encode, 0, 0, Opcode_ae_movda32_Slot_ae2_slot0_encode, Opcode_ae_movda32_Slot_ae2_slot1_encode, 0, Opcode_ae_movda32_Slot_ae3_slot0_encode, Opcode_ae_movda32_Slot_ae3_slot1_encode, Opcode_ae_movda32_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda16x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movda16x2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda16_encode_fns[] = { + 0, 0, 0, Opcode_ae_movda16_Slot_ae_slot0_encode, Opcode_ae_movda16_Slot_ae_slot1_encode, 0, 0, Opcode_ae_movda16_Slot_ae2_slot0_encode, Opcode_ae_movda16_Slot_ae2_slot1_encode, 0, Opcode_ae_movda16_Slot_ae3_slot0_encode, Opcode_ae_movda16_Slot_ae3_slot1_encode, Opcode_ae_movda16_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movi_encode_fns[] = { + 0, 0, 0, Opcode_ae_movi_Slot_ae_slot0_encode, Opcode_ae_movi_Slot_ae_slot1_encode, Opcode_ae_movi_Slot_ae_slot2_encode, Opcode_ae_movi_Slot_ae_slot3_encode, Opcode_ae_movi_Slot_ae2_slot0_encode, Opcode_ae_movi_Slot_ae2_slot1_encode, 0, Opcode_ae_movi_Slot_ae3_slot0_encode, Opcode_ae_movi_Slot_ae3_slot1_encode, Opcode_ae_movi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode, Opcode_ae_truncp24a32x2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae2_slot0_encode, Opcode_ae_truncp24a32x2_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat16x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sat16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sat16x4_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt32x2f16_32_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt32x2f16_32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvt32x2f16_32_Slot_ae_slot3_encode, Opcode_ae_cvt32x2f16_32_Slot_ae2_slot0_encode, Opcode_ae_cvt32x2f16_32_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt32x2f16_10_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt32x2f16_10_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvt32x2f16_10_Slot_ae_slot3_encode, Opcode_ae_cvt32x2f16_10_Slot_ae2_slot0_encode, Opcode_ae_cvt32x2f16_10_Slot_ae2_slot1_encode, 0, Opcode_ae_cvt32x2f16_10_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext32x2d16_32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sext32x2d16_32_Slot_ae_slot0_encode, 0, Opcode_ae_sext32x2d16_32_Slot_ae_slot2_encode, Opcode_ae_sext32x2d16_32_Slot_ae_slot3_encode, Opcode_ae_sext32x2d16_32_Slot_ae2_slot0_encode, Opcode_ae_sext32x2d16_32_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext32x2d16_10_encode_fns[] = { + 0, 0, 0, Opcode_ae_sext32x2d16_10_Slot_ae_slot0_encode, 0, Opcode_ae_sext32x2d16_10_Slot_ae_slot2_encode, Opcode_ae_sext32x2d16_10_Slot_ae_slot3_encode, Opcode_ae_sext32x2d16_10_Slot_ae2_slot0_encode, Opcode_ae_sext32x2d16_10_Slot_ae2_slot1_encode, 0, Opcode_ae_sext32x2d16_10_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32f24s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32f24s_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32f24s_l_Slot_ae2_slot0_encode, Opcode_ae_cvta32f24s_l_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32f24s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32f24s_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32f24s_h_Slot_ae2_slot0_encode, Opcode_ae_cvta32f24s_h_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae3_slot0_encode, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca32x2f64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunci32x2f64s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci32x2f64s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_trunci32x2f64s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, Opcode_ae_trunci32x2f64s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci32x2f64s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca32f64s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca32f64s_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunca32f64s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca32f64s_l_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunci32f64s_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci32f64s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci32f64s_l_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f64ssym_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_round32x2f64ssym_Slot_ae_slot2_encode, Opcode_ae_round32x2f64ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f64sasym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round32x2f64sasym_Slot_ae_slot0_encode, 0, Opcode_ae_round32x2f64sasym_Slot_ae_slot2_encode, Opcode_ae_round32x2f64sasym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f48ssym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round32x2f48ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f48sasym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round32x2f48sasym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round16x4f32ssym_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_round16x4f32ssym_Slot_ae_slot2_encode, Opcode_ae_round16x4f32ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_round16x4f32ssym_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round16x4f32sasym_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_round16x4f32sasym_Slot_ae_slot2_encode, Opcode_ae_round16x4f32sasym_Slot_ae_slot3_encode, 0, 0, 0, Opcode_ae_round16x4f32sasym_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_round16x4f32sasym_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round24x2f48ssym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round24x2f48ssym_Slot_ae_slot0_encode, 0, 0, Opcode_ae_round24x2f48ssym_Slot_ae_slot3_encode, 0, 0, 0, Opcode_ae_round24x2f48ssym_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round24x2f48sasym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round24x2f48sasym_Slot_ae_slot0_encode, 0, 0, Opcode_ae_round24x2f48sasym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48x2sym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsp16q48x2sym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48x2asym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsp16q48x2asym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minabs32s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_minabs32s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxabs32s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_maxabs32s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16f24sym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsp16f24sym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16f24asym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsp16f24asym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mov_encode_fns[] = { + 0, 0, 0, Opcode_ae_mov_Slot_ae_slot0_encode, 0, Opcode_ae_mov_Slot_ae_slot2_encode, Opcode_ae_mov_Slot_ae_slot3_encode, Opcode_ae_mov_Slot_ae2_slot0_encode, Opcode_ae_mov_Slot_ae2_slot1_encode, Opcode_ae_mov_Slot_ae2_slot2_encode, Opcode_ae_mov_Slot_ae3_slot0_encode, Opcode_ae_mov_Slot_ae3_slot1_encode, Opcode_ae_mov_Slot_ae5_slot0_encode, 0, Opcode_ae_mov_Slot_ae5_slot2_encode, Opcode_ae_mov_Slot_ae6_slot0_encode, Opcode_ae_mov_Slot_ae6_slot1_encode, Opcode_ae_mov_Slot_ae6_slot2_encode, Opcode_ae_mov_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mov_Slot_ae7_slot2_encode, Opcode_ae_mov_Slot_ae7_slot3_encode, Opcode_ae_mov_Slot_ae8_slot0_encode, 0, Opcode_ae_mov_Slot_ae8_slot2_encode, Opcode_ae_mov_Slot_ae9_slot0_encode, 0, Opcode_ae_mov_Slot_ae9_slot2_encode, Opcode_ae_mov_Slot_ae9_slot3_encode, 0, 0, Opcode_ae_mov_Slot_ae10_slot2_encode, Opcode_ae_mov_Slot_ae10_slot3_encode, 0, 0, Opcode_ae_mov_Slot_ae4_slot2_encode, Opcode_ae_mov_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt64_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt64_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_movt64_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movt64_Slot_ae6_slot0_encode, 0, Opcode_ae_movt64_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movt64_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movf64_encode_fns[] = { + 0, 0, 0, Opcode_ae_movf64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movf64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movf64_Slot_ae6_slot0_encode, 0, Opcode_ae_movf64_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movf64_Slot_ae9_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq56a32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvtq56a32s_Slot_ae_slot0_encode, Opcode_ae_cvtq56a32s_Slot_ae_slot1_encode, 0, 0, Opcode_ae_cvtq56a32s_Slot_ae2_slot0_encode, Opcode_ae_cvtq56a32s_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_cvtq56a32s_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt48a32_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt48a32_Slot_ae_slot0_encode, Opcode_ae_cvt48a32_Slot_ae_slot1_encode, 0, 0, Opcode_ae_cvt48a32_Slot_ae2_slot0_encode, Opcode_ae_cvt48a32_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_cvt48a32_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt64a32_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt64a32_Slot_ae_slot0_encode, Opcode_ae_cvt64a32_Slot_ae_slot1_encode, 0, 0, Opcode_ae_cvt64a32_Slot_ae2_slot0_encode, Opcode_ae_cvt64a32_Slot_ae2_slot1_encode, 0, 0, Opcode_ae_cvt64a32_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq56p32s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvtq56p32s_l_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvtq56p32s_l_Slot_ae_slot3_encode, Opcode_ae_cvtq56p32s_l_Slot_ae2_slot0_encode, Opcode_ae_cvtq56p32s_l_Slot_ae2_slot1_encode, 0, Opcode_ae_cvtq56p32s_l_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq56p32s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvtq56p32s_h_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvtq56p32s_h_Slot_ae_slot3_encode, Opcode_ae_cvtq56p32s_h_Slot_ae2_slot0_encode, Opcode_ae_cvtq56p32s_h_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt64f32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt64f32_h_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvt64f32_h_Slot_ae_slot3_encode, Opcode_ae_cvt64f32_h_Slot_ae2_slot0_encode, Opcode_ae_cvt64f32_h_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt48f32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt48f32_l_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvt48f32_l_Slot_ae_slot3_encode, Opcode_ae_cvt48f32_l_Slot_ae2_slot0_encode, Opcode_ae_cvt48f32_l_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt48f32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt48f32_h_Slot_ae_slot0_encode, 0, 0, Opcode_ae_cvt48f32_h_Slot_ae_slot3_encode, Opcode_ae_cvt48f32_h_Slot_ae2_slot0_encode, Opcode_ae_cvt48f32_h_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat48s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sat48s_Slot_ae_slot2_encode, Opcode_ae_sat48s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satq56s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_satq56s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat24s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sat24s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = { + 0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_truncq32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minabs64s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_minabs64s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxabs64s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_maxabs64s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsq32f48sym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsq32f48sym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsq32f48asym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_roundsq32f48asym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae2_slot0_encode, Opcode_ae_trunca32q48_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad32_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad32_l_Slot_ae2_slot0_encode, Opcode_ae_movad32_l_Slot_ae2_slot1_encode, 0, Opcode_ae_movad32_l_Slot_ae3_slot0_encode, Opcode_ae_movad32_l_Slot_ae3_slot1_encode, Opcode_ae_movad32_l_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movad32_l_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad32_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad32_h_Slot_ae2_slot0_encode, Opcode_ae_movad32_h_Slot_ae2_slot1_encode, 0, Opcode_ae_movad32_h_Slot_ae3_slot0_encode, 0, Opcode_ae_movad32_h_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_3_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad16_3_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad16_3_Slot_ae2_slot0_encode, Opcode_ae_movad16_3_Slot_ae2_slot1_encode, 0, Opcode_ae_movad16_3_Slot_ae3_slot0_encode, 0, Opcode_ae_movad16_3_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad16_2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad16_2_Slot_ae2_slot0_encode, Opcode_ae_movad16_2_Slot_ae2_slot1_encode, 0, Opcode_ae_movad16_2_Slot_ae3_slot0_encode, 0, Opcode_ae_movad16_2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_1_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad16_1_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad16_1_Slot_ae2_slot0_encode, Opcode_ae_movad16_1_Slot_ae2_slot1_encode, 0, Opcode_ae_movad16_1_Slot_ae3_slot0_encode, 0, Opcode_ae_movad16_1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_0_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad16_0_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad16_0_Slot_ae2_slot0_encode, Opcode_ae_movad16_0_Slot_ae2_slot1_encode, 0, Opcode_ae_movad16_0_Slot_ae3_slot0_encode, 0, Opcode_ae_movad16_0_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movad16_0_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sra64_32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sra64_32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sra64_32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksr32_encode_fns[] = { + 0, 0, 0, Opcode_ae_pksr32_Slot_ae_slot0_encode, 0, Opcode_ae_pksr32_Slot_ae_slot2_encode, 0, Opcode_ae_pksr32_Slot_ae2_slot0_encode, 0, Opcode_ae_pksr32_Slot_ae2_slot2_encode, 0, 0, Opcode_ae_pksr32_Slot_ae5_slot0_encode, 0, Opcode_ae_pksr32_Slot_ae5_slot2_encode, Opcode_ae_pksr32_Slot_ae6_slot0_encode, 0, Opcode_ae_pksr32_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_pksr32_Slot_ae4_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksr24_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_pksr24_Slot_ae_slot2_encode, 0, Opcode_ae_pksr24_Slot_ae2_slot0_encode, 0, Opcode_ae_pksr24_Slot_ae2_slot2_encode, 0, 0, Opcode_ae_pksr24_Slot_ae5_slot0_encode, 0, Opcode_ae_pksr24_Slot_ae5_slot2_encode, Opcode_ae_pksr24_Slot_ae6_slot0_encode, 0, Opcode_ae_pksr24_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_pksr24_Slot_ae4_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksrf32_encode_fns[] = { + 0, 0, 0, Opcode_ae_pksrf32_Slot_ae_slot0_encode, 0, Opcode_ae_pksrf32_Slot_ae_slot2_encode, 0, Opcode_ae_pksrf32_Slot_ae2_slot0_encode, 0, Opcode_ae_pksrf32_Slot_ae2_slot2_encode, 0, 0, Opcode_ae_pksrf32_Slot_ae5_slot0_encode, 0, Opcode_ae_pksrf32_Slot_ae5_slot2_encode, Opcode_ae_pksrf32_Slot_ae6_slot0_encode, 0, Opcode_ae_pksrf32_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_pksrf32_Slot_ae4_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksr16_encode_fns[] = { + 0, 0, 0, Opcode_ae_pksr16_Slot_ae_slot0_encode, 0, Opcode_ae_pksr16_Slot_ae_slot2_encode, 0, Opcode_ae_pksr16_Slot_ae2_slot0_encode, 0, Opcode_ae_pksr16_Slot_ae2_slot2_encode, 0, 0, Opcode_ae_pksr16_Slot_ae5_slot0_encode, 0, Opcode_ae_pksr16_Slot_ae5_slot2_encode, Opcode_ae_pksr16_Slot_ae6_slot0_encode, 0, Opcode_ae_pksr16_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_pksr16_Slot_ae4_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32_encode_fns[] = { + 0, 0, 0, Opcode_ae_add32_Slot_ae_slot0_encode, 0, Opcode_ae_add32_Slot_ae_slot2_encode, Opcode_ae_add32_Slot_ae_slot3_encode, Opcode_ae_add32_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ae_add32_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub32_Slot_ae_slot0_encode, 0, Opcode_ae_sub32_Slot_ae_slot2_encode, Opcode_ae_sub32_Slot_ae_slot3_encode, Opcode_ae_sub32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsub32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsub32_Slot_ae_slot0_encode, 0, Opcode_ae_addsub32_Slot_ae_slot2_encode, Opcode_ae_addsub32_Slot_ae_slot3_encode, Opcode_ae_addsub32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subadd32_encode_fns[] = { + 0, 0, 0, Opcode_ae_subadd32_Slot_ae_slot0_encode, 0, Opcode_ae_subadd32_Slot_ae_slot2_encode, Opcode_ae_subadd32_Slot_ae_slot3_encode, Opcode_ae_subadd32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add16_encode_fns[] = { + 0, 0, 0, Opcode_ae_add16_Slot_ae_slot0_encode, 0, Opcode_ae_add16_Slot_ae_slot2_encode, Opcode_ae_add16_Slot_ae_slot3_encode, Opcode_ae_add16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub16_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub16_Slot_ae_slot0_encode, 0, Opcode_ae_sub16_Slot_ae_slot2_encode, Opcode_ae_sub16_Slot_ae_slot3_encode, Opcode_ae_sub16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_add32_hl_lh_Slot_ae_slot0_encode, 0, Opcode_ae_add32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_add32_hl_lh_Slot_ae_slot3_encode, Opcode_ae_add32_hl_lh_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsub32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_addsub32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_addsub32_hl_lh_Slot_ae_slot3_encode, Opcode_ae_addsub32_hl_lh_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg32_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg32_Slot_ae_slot0_encode, 0, Opcode_ae_neg32_Slot_ae_slot2_encode, Opcode_ae_neg32_Slot_ae_slot3_encode, Opcode_ae_neg32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_neg32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs32_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs32_Slot_ae_slot0_encode, 0, Opcode_ae_abs32_Slot_ae_slot2_encode, Opcode_ae_abs32_Slot_ae_slot3_encode, Opcode_ae_abs32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_abs32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg32_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_neg32_l_Slot_ae_slot2_encode, Opcode_ae_neg32_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add24s_Slot_ae_slot0_encode, 0, Opcode_ae_add24s_Slot_ae_slot2_encode, Opcode_ae_add24s_Slot_ae_slot3_encode, Opcode_ae_add24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub24s_Slot_ae_slot0_encode, 0, Opcode_ae_sub24s_Slot_ae_slot2_encode, Opcode_ae_sub24s_Slot_ae_slot3_encode, Opcode_ae_sub24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add32s_Slot_ae_slot0_encode, 0, Opcode_ae_add32s_Slot_ae_slot2_encode, Opcode_ae_add32s_Slot_ae_slot3_encode, Opcode_ae_add32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_add32s_Slot_ae3_slot0_encode, 0, Opcode_ae_add32s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, Opcode_ae_add32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub32s_Slot_ae_slot0_encode, 0, Opcode_ae_sub32s_Slot_ae_slot2_encode, Opcode_ae_sub32s_Slot_ae_slot3_encode, Opcode_ae_sub32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sub32s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sub32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsub32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsub32s_Slot_ae_slot0_encode, 0, Opcode_ae_addsub32s_Slot_ae_slot2_encode, Opcode_ae_addsub32s_Slot_ae_slot3_encode, Opcode_ae_addsub32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subadd32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_subadd32s_Slot_ae_slot0_encode, 0, Opcode_ae_subadd32s_Slot_ae_slot2_encode, Opcode_ae_subadd32s_Slot_ae_slot3_encode, Opcode_ae_subadd32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add16s_Slot_ae_slot0_encode, 0, Opcode_ae_add16s_Slot_ae_slot2_encode, Opcode_ae_add16s_Slot_ae_slot3_encode, Opcode_ae_add16s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_add16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_add16s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub16s_Slot_ae_slot0_encode, 0, Opcode_ae_sub16s_Slot_ae_slot2_encode, Opcode_ae_sub16s_Slot_ae_slot3_encode, Opcode_ae_sub16s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sub16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sub16s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_add32s_hl_lh_Slot_ae_slot0_encode, 0, Opcode_ae_add32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_add32s_hl_lh_Slot_ae_slot3_encode, Opcode_ae_add32s_hl_lh_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsub32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_addsub32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_addsub32s_hl_lh_Slot_ae_slot3_encode, Opcode_ae_addsub32s_hl_lh_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg24s_Slot_ae_slot0_encode, 0, Opcode_ae_neg24s_Slot_ae_slot2_encode, Opcode_ae_neg24s_Slot_ae_slot3_encode, Opcode_ae_neg24s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_neg24s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs24s_Slot_ae_slot0_encode, 0, Opcode_ae_abs24s_Slot_ae_slot2_encode, Opcode_ae_abs24s_Slot_ae_slot3_encode, Opcode_ae_abs24s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_abs24s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg32s_Slot_ae_slot0_encode, 0, Opcode_ae_neg32s_Slot_ae_slot2_encode, Opcode_ae_neg32s_Slot_ae_slot3_encode, Opcode_ae_neg32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_neg32s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_neg32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs32s_Slot_ae_slot0_encode, 0, Opcode_ae_abs32s_Slot_ae_slot2_encode, Opcode_ae_abs32s_Slot_ae_slot3_encode, Opcode_ae_abs32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_abs32s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_abs32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg16s_Slot_ae_slot0_encode, 0, Opcode_ae_neg16s_Slot_ae_slot2_encode, Opcode_ae_neg16s_Slot_ae_slot3_encode, Opcode_ae_neg16s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_neg16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_neg16s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs16s_Slot_ae_slot0_encode, 0, Opcode_ae_abs16s_Slot_ae_slot2_encode, Opcode_ae_abs16s_Slot_ae_slot3_encode, Opcode_ae_abs16s_Slot_ae2_slot0_encode, 0, Opcode_ae_abs16s_Slot_ae2_slot2_encode, Opcode_ae_abs16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_abs16s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_abs16s_Slot_ae4_slot2_encode, Opcode_ae_abs16s_Slot_ae4_slot3_encode, Opcode_ae_abs16s_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs16_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs16_Slot_ae_slot0_encode, 0, Opcode_ae_abs16_Slot_ae_slot2_encode, Opcode_ae_abs16_Slot_ae_slot3_encode, Opcode_ae_abs16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16js_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc16js_h_Slot_ae_slot2_encode, Opcode_ae_mulc16js_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc16js_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16js_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc16js_l_Slot_ae_slot2_encode, Opcode_ae_mulc16js_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc16js_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16js_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac16js_h_Slot_ae_slot2_encode, Opcode_ae_mulac16js_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac16js_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16js_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac16js_l_Slot_ae_slot2_encode, Opcode_ae_mulac16js_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac16js_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt16_encode_fns[] = { + 0, 0, 0, Opcode_ae_lt16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lt16_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_lt16_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_lt16_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lt16_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le16_encode_fns[] = { + 0, 0, 0, Opcode_ae_le16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_le16_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_le16_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_le16_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_le16_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq16_encode_fns[] = { + 0, 0, 0, Opcode_ae_eq16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_eq16_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_eq16_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_eq16_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_eq16_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt32_encode_fns[] = { + 0, 0, 0, Opcode_ae_lt32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lt32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_lt32_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_lt32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lt32_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le32_encode_fns[] = { + 0, 0, 0, Opcode_ae_le32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_le32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_le32_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_le32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_le32_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq32_encode_fns[] = { + 0, 0, 0, Opcode_ae_eq32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_eq32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_eq32_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_eq32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_eq32_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_min32_encode_fns[] = { + 0, 0, 0, Opcode_ae_min32_Slot_ae_slot0_encode, 0, Opcode_ae_min32_Slot_ae_slot2_encode, Opcode_ae_min32_Slot_ae_slot3_encode, Opcode_ae_min32_Slot_ae2_slot0_encode, 0, Opcode_ae_min32_Slot_ae2_slot2_encode, Opcode_ae_min32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_min32_Slot_ae4_slot2_encode, Opcode_ae_min32_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_max32_encode_fns[] = { + 0, 0, 0, Opcode_ae_max32_Slot_ae_slot0_encode, 0, Opcode_ae_max32_Slot_ae_slot2_encode, Opcode_ae_max32_Slot_ae_slot3_encode, Opcode_ae_max32_Slot_ae2_slot0_encode, 0, Opcode_ae_max32_Slot_ae2_slot2_encode, Opcode_ae_max32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_max32_Slot_ae4_slot2_encode, Opcode_ae_max32_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minmax32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_minmax32_Slot_ae_slot2_encode, Opcode_ae_minmax32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minmax16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_minmax16_Slot_ae_slot2_encode, Opcode_ae_minmax16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_min16_encode_fns[] = { + 0, 0, 0, Opcode_ae_min16_Slot_ae_slot0_encode, 0, Opcode_ae_min16_Slot_ae_slot2_encode, Opcode_ae_min16_Slot_ae_slot3_encode, Opcode_ae_min16_Slot_ae2_slot0_encode, 0, Opcode_ae_min16_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_min16_Slot_ae4_slot2_encode, Opcode_ae_min16_Slot_ae4_slot3_encode, Opcode_ae_min16_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_max16_encode_fns[] = { + 0, 0, 0, Opcode_ae_max16_Slot_ae_slot0_encode, 0, Opcode_ae_max16_Slot_ae_slot2_encode, Opcode_ae_max16_Slot_ae_slot3_encode, Opcode_ae_max16_Slot_ae2_slot0_encode, 0, Opcode_ae_max16_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_max16_Slot_ae4_slot2_encode, Opcode_ae_max16_Slot_ae4_slot3_encode, Opcode_ae_max16_Slot_ae4_slot4_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_add64_encode_fns[] = { + 0, 0, 0, Opcode_ae_add64_Slot_ae_slot0_encode, 0, Opcode_ae_add64_Slot_ae_slot2_encode, Opcode_ae_add64_Slot_ae_slot3_encode, Opcode_ae_add64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub64_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub64_Slot_ae_slot0_encode, 0, Opcode_ae_sub64_Slot_ae_slot2_encode, Opcode_ae_sub64_Slot_ae_slot3_encode, Opcode_ae_sub64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg64_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg64_Slot_ae_slot0_encode, 0, Opcode_ae_neg64_Slot_ae_slot2_encode, Opcode_ae_neg64_Slot_ae_slot3_encode, Opcode_ae_neg64_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_neg64_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs64_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs64_Slot_ae_slot0_encode, 0, Opcode_ae_abs64_Slot_ae_slot2_encode, Opcode_ae_abs64_Slot_ae_slot3_encode, Opcode_ae_abs64_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_abs64_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot0_encode, 0, Opcode_ae_addsq56s_Slot_ae_slot2_encode, Opcode_ae_addsq56s_Slot_ae_slot3_encode, Opcode_ae_addsq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot0_encode, 0, Opcode_ae_subsq56s_Slot_ae_slot2_encode, Opcode_ae_subsq56s_Slot_ae_slot3_encode, Opcode_ae_subsq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add64s_Slot_ae_slot0_encode, 0, Opcode_ae_add64s_Slot_ae_slot2_encode, Opcode_ae_add64s_Slot_ae_slot3_encode, Opcode_ae_add64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub64s_Slot_ae_slot0_encode, 0, Opcode_ae_sub64s_Slot_ae_slot2_encode, Opcode_ae_sub64s_Slot_ae_slot3_encode, Opcode_ae_sub64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot0_encode, 0, Opcode_ae_negsq56s_Slot_ae_slot2_encode, Opcode_ae_negsq56s_Slot_ae_slot3_encode, Opcode_ae_negsq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot0_encode, 0, Opcode_ae_abssq56s_Slot_ae_slot2_encode, Opcode_ae_abssq56s_Slot_ae_slot3_encode, Opcode_ae_abssq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg64s_Slot_ae_slot0_encode, 0, Opcode_ae_neg64s_Slot_ae_slot2_encode, Opcode_ae_neg64s_Slot_ae_slot3_encode, Opcode_ae_neg64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs64s_Slot_ae_slot0_encode, 0, Opcode_ae_abs64s_Slot_ae_slot2_encode, Opcode_ae_abs64s_Slot_ae_slot3_encode, Opcode_ae_abs64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_and_encode_fns[] = { + 0, 0, 0, Opcode_ae_and_Slot_ae_slot0_encode, 0, 0, Opcode_ae_and_Slot_ae_slot3_encode, Opcode_ae_and_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_and_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nand_encode_fns[] = { + 0, 0, 0, Opcode_ae_nand_Slot_ae_slot0_encode, 0, 0, Opcode_ae_nand_Slot_ae_slot3_encode, Opcode_ae_nand_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_or_encode_fns[] = { + 0, 0, 0, Opcode_ae_or_Slot_ae_slot0_encode, 0, 0, Opcode_ae_or_Slot_ae_slot3_encode, Opcode_ae_or_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_or_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_xor_encode_fns[] = { + 0, 0, 0, Opcode_ae_xor_Slot_ae_slot0_encode, 0, 0, Opcode_ae_xor_Slot_ae_slot3_encode, Opcode_ae_xor_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_xor_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai24_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai24_Slot_ae_slot3_encode, Opcode_ae_slai24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srli24_Slot_ae_slot3_encode, Opcode_ae_srli24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai24_Slot_ae_slot3_encode, Opcode_ae_srai24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas24_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas24_Slot_ae_slot3_encode, Opcode_ae_slas24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srls24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srls24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srls24_Slot_ae_slot3_encode, Opcode_ae_srls24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sras24_encode_fns[] = { + 0, 0, 0, Opcode_ae_sras24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sras24_Slot_ae_slot3_encode, Opcode_ae_sras24_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sras24_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai16_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai16_Slot_ae_slot3_encode, Opcode_ae_srai16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai16r_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai16r_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai16r_Slot_ae_slot3_encode, Opcode_ae_srai16r_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai32_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai32_Slot_ae_slot3_encode, Opcode_ae_slai32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli32_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srli32_Slot_ae_slot3_encode, Opcode_ae_srli32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai32_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai32_Slot_ae_slot3_encode, Opcode_ae_srai32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai32r_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai32r_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai32r_Slot_ae_slot3_encode, Opcode_ae_srai32r_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas32_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas32_Slot_ae_slot3_encode, Opcode_ae_slas32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srls32_encode_fns[] = { + 0, 0, 0, Opcode_ae_srls32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srls32_Slot_ae_slot3_encode, Opcode_ae_srls32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sras32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sras32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sras32_Slot_ae_slot3_encode, Opcode_ae_sras32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa32_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srla32_encode_fns[] = { + 0, 0, 0, Opcode_ae_srla32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srla32_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_srla32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai16s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai16s_Slot_ae_slot3_encode, Opcode_ae_slai16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa16s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa16s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slaa16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa16s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa16s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sraa16s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa16rs_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa16rs_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa16rs_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sraa16rs_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai24s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai24s_Slot_ae_slot3_encode, Opcode_ae_slai24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas24s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas24s_Slot_ae_slot3_encode, Opcode_ae_slas24s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slas24s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai32s_Slot_ae_slot3_encode, Opcode_ae_slai32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas32s_Slot_ae_slot3_encode, Opcode_ae_slas32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa32s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slaa32s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa32s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa32s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sraa32s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32rs_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa32rs_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa32rs_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slasq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_slasq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slasq56_Slot_ae_slot3_encode, Opcode_ae_slasq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot3_encode, Opcode_ae_srlsq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srasq56_Slot_ae_slot3_encode, Opcode_ae_srasq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaaq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaaq56_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaaq56_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slaaq56_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_sraaq56_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai64_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai64_Slot_ae_slot3_encode, Opcode_ae_slai64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli64_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srli64_Slot_ae_slot3_encode, Opcode_ae_srli64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai64_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai64_Slot_ae_slot3_encode, Opcode_ae_srai64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas64_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas64_Slot_ae_slot3_encode, Opcode_ae_slas64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srls64_encode_fns[] = { + 0, 0, 0, Opcode_ae_srls64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srls64_Slot_ae_slot3_encode, Opcode_ae_srls64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sras64_encode_fns[] = { + 0, 0, 0, Opcode_ae_sras64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sras64_Slot_ae_slot3_encode, Opcode_ae_sras64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa64_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa64_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slaa64_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srla64_encode_fns[] = { + 0, 0, 0, Opcode_ae_srla64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srla64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa64_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaisq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaisq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slaisq56s_Slot_ae_slot3_encode, Opcode_ae_slaisq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slassq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slassq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slassq56s_Slot_ae_slot3_encode, Opcode_ae_slassq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaasq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaasq56s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaasq56s_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_slaasq56s_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai64s_Slot_ae_slot3_encode, Opcode_ae_slai64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas64s_Slot_ae_slot3_encode, Opcode_ae_slas64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa64s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt64_encode_fns[] = { + 0, 0, 0, Opcode_ae_lt64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lt64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lt64_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lt64_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le64_encode_fns[] = { + 0, 0, 0, Opcode_ae_le64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_le64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_le64_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_le64_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq64_encode_fns[] = { + 0, 0, 0, Opcode_ae_eq64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_eq64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_eq64_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_eq64_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_max64_encode_fns[] = { + 0, 0, 0, Opcode_ae_max64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_max64_Slot_ae_slot3_encode, Opcode_ae_max64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_min64_encode_fns[] = { + 0, 0, 0, Opcode_ae_min64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_min64_Slot_ae_slot3_encode, Opcode_ae_min64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsa64_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsa64_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsa64_Slot_ae2_slot0_encode, Opcode_ae_nsa64_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsaz16_0_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsaz16_0_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsaz16_0_Slot_ae2_slot0_encode, Opcode_ae_nsaz16_0_Slot_ae2_slot1_encode, 0, Opcode_ae_nsaz16_0_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsaz32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsaz32_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsaz32_l_Slot_ae2_slot0_encode, Opcode_ae_nsaz32_l_Slot_ae2_slot1_encode, 0, Opcode_ae_nsaz32_l_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_ll_Slot_ae_slot2_encode, Opcode_ae_muls32f48p16s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32f48p16s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32s_ll_Slot_ae_slot2_encode, Opcode_ae_mulf32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32_ll_Slot_ae_slot2_encode, Opcode_ae_mul32_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32r_ll_Slot_ae_slot2_encode, Opcode_ae_mulf32r_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32r_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32r_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32ra_ll_Slot_ae_slot2_encode, Opcode_ae_mulf32ra_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32ra_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_lh_Slot_ae_slot2_encode, Opcode_ae_muls32f48p16s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32f48p16s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32s_lh_Slot_ae_slot2_encode, Opcode_ae_mulf32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32_lh_Slot_ae_slot2_encode, Opcode_ae_mul32_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32r_lh_Slot_ae_slot2_encode, Opcode_ae_mulf32r_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32r_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32r_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32ra_lh_Slot_ae_slot2_encode, Opcode_ae_mulf32ra_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32ra_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_hh_Slot_ae_slot2_encode, Opcode_ae_muls32f48p16s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32f48p16s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32s_hh_Slot_ae_slot2_encode, Opcode_ae_mulf32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32_hh_Slot_ae_slot2_encode, Opcode_ae_mul32_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32r_hh_Slot_ae_slot2_encode, Opcode_ae_mulf32r_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32r_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32r_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32ra_hh_Slot_ae_slot2_encode, Opcode_ae_mulf32ra_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32ra_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_ll_Slot_ae_slot2_encode, Opcode_ae_mulas32f48p16s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulas32f48p16s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32s_ll_Slot_ae_slot2_encode, Opcode_ae_mulaf32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32_ll_Slot_ae_slot2_encode, Opcode_ae_mula32_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32r_ll_Slot_ae_slot2_encode, Opcode_ae_mulaf32r_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32r_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32r_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32ra_ll_Slot_ae_slot2_encode, Opcode_ae_mulaf32ra_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32ra_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_lh_Slot_ae_slot2_encode, Opcode_ae_mulas32f48p16s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulas32f48p16s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32s_lh_Slot_ae_slot2_encode, Opcode_ae_mulaf32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32_lh_Slot_ae_slot2_encode, Opcode_ae_mula32_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32r_lh_Slot_ae_slot2_encode, Opcode_ae_mulaf32r_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32r_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32r_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32ra_lh_Slot_ae_slot2_encode, Opcode_ae_mulaf32ra_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32ra_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_hh_Slot_ae_slot2_encode, Opcode_ae_mulas32f48p16s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulas32f48p16s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32s_hh_Slot_ae_slot2_encode, Opcode_ae_mulaf32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32_hh_Slot_ae_slot2_encode, Opcode_ae_mula32_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32r_hh_Slot_ae_slot2_encode, Opcode_ae_mulaf32r_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32r_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32r_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32ra_hh_Slot_ae_slot2_encode, Opcode_ae_mulaf32ra_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32ra_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_ll_Slot_ae_slot2_encode, Opcode_ae_mulss32f48p16s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulss32f48p16s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32s_ll_Slot_ae_slot2_encode, Opcode_ae_mulsf32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32_ll_Slot_ae_slot2_encode, Opcode_ae_muls32_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32r_ll_Slot_ae_slot2_encode, Opcode_ae_mulsf32r_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32r_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32r_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32ra_ll_Slot_ae_slot2_encode, Opcode_ae_mulsf32ra_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32ra_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_lh_Slot_ae_slot2_encode, Opcode_ae_mulss32f48p16s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulss32f48p16s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32s_lh_Slot_ae_slot2_encode, Opcode_ae_mulsf32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32_lh_Slot_ae_slot2_encode, Opcode_ae_muls32_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32r_lh_Slot_ae_slot2_encode, Opcode_ae_mulsf32r_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32r_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32r_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32ra_lh_Slot_ae_slot2_encode, Opcode_ae_mulsf32ra_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32ra_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_hh_Slot_ae_slot2_encode, Opcode_ae_mulss32f48p16s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulss32f48p16s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32s_hh_Slot_ae_slot2_encode, Opcode_ae_mulsf32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32_hh_Slot_ae_slot2_encode, Opcode_ae_muls32_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32r_hh_Slot_ae_slot2_encode, Opcode_ae_mulsf32r_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32r_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32r_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32ra_hh_Slot_ae_slot2_encode, Opcode_ae_mulsf32ra_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32ra_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32u_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32u_ll_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mul32u_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32u_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32u_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32u_ll_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mula32u_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32u_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32u_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32u_ll_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_muls32u_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32u_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_33_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_33_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_33_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_22_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_22_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_32_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_21_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_21_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_21_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_31_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_31_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_31_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_30_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_30_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_30_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_10_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_10_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_10_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_20_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_20_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_20_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_11_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_11_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_11_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_00_Slot_ae_slot2_encode, Opcode_ae_mulf16ss_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf16ss_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf16ss_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_33_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_33_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_33_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_22_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_22_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_32_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_21_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_21_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_21_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_31_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_31_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_31_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_30_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_30_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_30_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_10_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_10_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_10_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_20_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_20_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_20_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_11_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_11_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_11_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_00_Slot_ae_slot2_encode, Opcode_ae_mulsf16ss_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf16ss_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf16ss_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_33_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_33_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_33_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_22_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_22_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_32_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_21_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_21_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_21_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_31_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_31_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_31_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_30_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_30_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_30_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_10_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_10_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_10_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_20_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_20_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_20_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_11_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_11_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_11_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_00_Slot_ae_slot2_encode, Opcode_ae_mulaf16ss_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf16ss_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf16ss_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16s_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul16s_00_Slot_ae_slot2_encode, Opcode_ae_mul16s_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul16s_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul16s_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16s_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula16s_00_Slot_ae_slot2_encode, Opcode_ae_mula16s_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula16s_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula16s_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls16s_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls16s_00_Slot_ae_slot2_encode, Opcode_ae_muls16s_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls16s_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls16s_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_33_22_Slot_ae_slot2_encode, Opcode_ae_mulaafd16ss_33_22_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_13_02_Slot_ae_slot2_encode, Opcode_ae_mulaafd16ss_13_02_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_11_00_Slot_ae_slot2_encode, Opcode_ae_mulaafd16ss_11_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_33_22_Slot_ae_slot2_encode, Opcode_ae_mulssfd16ss_33_22_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_13_02_Slot_ae_slot2_encode, Opcode_ae_mulssfd16ss_13_02_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_11_00_Slot_ae_slot2_encode, Opcode_ae_mulssfd16ss_11_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_33_22_Slot_ae_slot2_encode, Opcode_ae_mulzaafd16ss_33_22_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_13_02_Slot_ae_slot2_encode, Opcode_ae_mulzaafd16ss_13_02_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_11_00_Slot_ae_slot2_encode, Opcode_ae_mulzaafd16ss_11_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_33_22_Slot_ae_slot2_encode, Opcode_ae_mulzssfd16ss_33_22_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_13_02_Slot_ae_slot2_encode, Opcode_ae_mulzssfd16ss_13_02_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_11_00_Slot_ae_slot2_encode, Opcode_ae_mulzssfd16ss_11_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf48q32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf48q32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulf48q32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf48q32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf48q32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf48q32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf48q32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulf48q32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf48q32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf48q32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulq32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulq32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf48q32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulaf48q32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf48q32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf48q32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulaf48q32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf48q32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf48q32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulsf48q32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf48q32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf48q32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulsf48q32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf48q32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot2_encode, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24x2ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp24x2ra_Slot_ae_slot2_encode, Opcode_ae_mulfp24x2ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp24x2ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp24x2ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24x2r_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp24x2r_Slot_ae_slot2_encode, Opcode_ae_mulfp24x2r_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp24x2r_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp24x2r_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24x2ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp24x2ra_Slot_ae_slot2_encode, Opcode_ae_mulafp24x2ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp24x2ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp24x2ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24x2r_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp24x2r_Slot_ae_slot2_encode, Opcode_ae_mulafp24x2r_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp24x2r_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp24x2r_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24x2ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp24x2ra_Slot_ae_slot2_encode, Opcode_ae_mulsfp24x2ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp24x2ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp24x2ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24x2r_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp24x2r_Slot_ae_slot2_encode, Opcode_ae_mulsfp24x2r_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp24x2r_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp24x2r_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaad32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaad32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzasd32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzasd32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsad32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzsad32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssd32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzssd32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaafd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaad32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaafd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaad32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulasfd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulasd32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulasfd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulasd32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsafd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulsafd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsad32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulsad32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssfd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssd32_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulssfd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulssd32_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l0_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l0_Slot_ae_slot2_encode, Opcode_ae_mul32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l1_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l1_Slot_ae_slot2_encode, Opcode_ae_mul32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l2_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l2_Slot_ae_slot2_encode, Opcode_ae_mul32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l3_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l3_Slot_ae_slot2_encode, Opcode_ae_mul32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h0_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h0_Slot_ae_slot2_encode, Opcode_ae_mul32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h1_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h1_Slot_ae_slot2_encode, Opcode_ae_mul32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h2_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h2_Slot_ae_slot2_encode, Opcode_ae_mul32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h3_Slot_ae_slot2_encode, Opcode_ae_mulf32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulf32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulf32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h3_Slot_ae_slot2_encode, Opcode_ae_mul32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l0_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l0_Slot_ae_slot2_encode, Opcode_ae_mula32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l1_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l1_Slot_ae_slot2_encode, Opcode_ae_mula32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l2_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l2_Slot_ae_slot2_encode, Opcode_ae_mula32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l3_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l3_Slot_ae_slot2_encode, Opcode_ae_mula32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h0_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h0_Slot_ae_slot2_encode, Opcode_ae_mula32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h1_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h1_Slot_ae_slot2_encode, Opcode_ae_mula32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h2_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h2_Slot_ae_slot2_encode, Opcode_ae_mula32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h3_Slot_ae_slot2_encode, Opcode_ae_mulaf32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaf32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h3_Slot_ae_slot2_encode, Opcode_ae_mula32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l0_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l0_Slot_ae_slot2_encode, Opcode_ae_muls32x16_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l1_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l1_Slot_ae_slot2_encode, Opcode_ae_muls32x16_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l2_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l2_Slot_ae_slot2_encode, Opcode_ae_muls32x16_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l3_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l3_Slot_ae_slot2_encode, Opcode_ae_muls32x16_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h0_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h0_Slot_ae_slot2_encode, Opcode_ae_muls32x16_h0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h1_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h1_Slot_ae_slot2_encode, Opcode_ae_muls32x16_h1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h2_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h2_Slot_ae_slot2_encode, Opcode_ae_muls32x16_h2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h3_Slot_ae_slot2_encode, Opcode_ae_mulsf32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsf32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h3_Slot_ae_slot2_encode, Opcode_ae_muls32x16_h3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulaad32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulaad32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulasd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulasd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsad32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulsad32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsad32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulsad32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulssd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulssd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsad32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzsad32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsad32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzsad32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae_slot2_encode, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae_slot2_encode, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae_slot2_encode, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae_slot2_encode, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae_slot2_encode, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae_slot2_encode, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae_slot2_encode, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h2_l3_Slot_ae_slot2_encode, Opcode_ae_mulaad32x16_h2_l3_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h0_l1_Slot_ae_slot2_encode, Opcode_ae_mulaad32x16_h0_l1_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x16x2_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp32x16x2_h_Slot_ae_slot2_encode, Opcode_ae_mulp32x16x2_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp32x16x2_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp32x16x2_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2rs_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_h_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2rs_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2rs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2ras_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_h_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2ras_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_h_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x16x2_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp32x16x2_l_Slot_ae_slot2_encode, Opcode_ae_mulp32x16x2_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp32x16x2_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp32x16x2_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2rs_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_l_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2rs_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2rs_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2ras_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_l_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2ras_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_l_Slot_ae_slot2_encode, Opcode_ae_mulfp32x16x2s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x16x2s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x16x2_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap32x16x2_h_Slot_ae_slot2_encode, Opcode_ae_mulap32x16x2_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap32x16x2_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap32x16x2_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2rs_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_h_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2rs_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2rs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2ras_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_h_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2ras_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_h_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x16x2_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap32x16x2_l_Slot_ae_slot2_encode, Opcode_ae_mulap32x16x2_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap32x16x2_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap32x16x2_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2rs_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_l_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2rs_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2rs_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2ras_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_l_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2ras_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_l_Slot_ae_slot2_encode, Opcode_ae_mulafp32x16x2s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x16x2s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x16x2_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_h_Slot_ae_slot2_encode, Opcode_ae_mulsp32x16x2_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp32x16x2_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2rs_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2ras_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_h_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x16x2_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_l_Slot_ae_slot2_encode, Opcode_ae_mulsp32x16x2_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp32x16x2_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2rs_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2ras_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_l_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x16x2s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x16x2s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp32x2_Slot_ae_slot2_encode, Opcode_ae_mulp32x2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp32x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp32x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2rs_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2rs_Slot_ae_slot2_encode, Opcode_ae_mulfp32x2rs_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x2rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x2rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2ras_Slot_ae_slot2_encode, Opcode_ae_mulfp32x2ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp32x2ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x2ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2ts_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2ts_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulfp32x2ts_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp32x2ts_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x2t_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp32x2t_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulp32x2t_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp32x2t_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap32x2_Slot_ae_slot2_encode, Opcode_ae_mulap32x2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap32x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap32x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2rs_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2rs_Slot_ae_slot2_encode, Opcode_ae_mulafp32x2rs_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x2rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x2rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2ras_Slot_ae_slot2_encode, Opcode_ae_mulafp32x2ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafp32x2ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x2ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2ts_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2ts_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulafp32x2ts_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafp32x2ts_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x2t_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap32x2t_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulap32x2t_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap32x2t_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp32x2_Slot_ae_slot2_encode, Opcode_ae_mulsp32x2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp32x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp32x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2rs_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2rs_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x2rs_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x2rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x2rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2ras_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x2ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsfp32x2ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x2ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2ts_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2ts_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulsfp32x2ts_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsfp32x2ts_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x2t_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp32x2t_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulsp32x2t_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp32x2t_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp16x4s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp16x4s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp16x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp16x4ras_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc32_Slot_ae_slot2_encode, Opcode_ae_mulc32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc32_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulc32_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc24ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc24ra_Slot_ae_slot2_encode, Opcode_ae_mulfc24ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc24ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfc24ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32ras_Slot_ae_slot2_encode, Opcode_ae_mulfc32ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc32ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfc32ras_Slot_ae5_slot2_encode, 0, 0, Opcode_ae_mulfc32ras_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfc32ras_Slot_ae4_slot2_encode, Opcode_ae_mulfc32ras_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32x16_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc32x16_l_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulc32x16_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulc32x16_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32x16ras_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae_slot2_encode, Opcode_ae_mulfc32x16ras_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae5_slot2_encode, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32x16_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc32x16_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulc32x16_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulc32x16_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32x16ras_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae_slot2_encode, Opcode_ae_mulfc32x16ras_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae5_slot2_encode, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac32_Slot_ae_slot2_encode, Opcode_ae_mulac32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac32_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulac32_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc24ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc24ra_Slot_ae_slot2_encode, Opcode_ae_mulafc24ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc24ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafc24ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32ras_Slot_ae_slot2_encode, Opcode_ae_mulafc32ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc32ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafc32ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32x16_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac32x16_l_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulac32x16_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulac32x16_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32x16ras_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_l_Slot_ae_slot2_encode, Opcode_ae_mulafc32x16ras_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc32x16ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32x16_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac32x16_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_mulac32x16_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulac32x16_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32x16ras_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_h_Slot_ae_slot2_encode, Opcode_ae_mulafc32x16ras_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc32x16ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16x4ss_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf16x4ss_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16x4ss_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf16x4ss_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16x4ss_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf16x4ss_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul16x4s_Slot_ae_slot2_encode, Opcode_ae_mul16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul16x4s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula16x4s_Slot_ae_slot2_encode, Opcode_ae_mula16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls16x4s_Slot_ae_slot2_encode, Opcode_ae_muls16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul16x4_Slot_ae_slot2_encode, Opcode_ae_mul16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul16x4_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula16x4_Slot_ae_slot2_encode, Opcode_ae_mula16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls16x4_Slot_ae_slot2_encode, Opcode_ae_muls16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2s_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2s_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2s_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x2s_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2ra_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2ra_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2ra_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x2ra_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2s_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2s_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2s_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x2s_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2ra_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2ra_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2ra_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x2ra_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae7_slot2_encode, Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2s_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2s_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2s_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x2s_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2ra_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2ra_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2ra_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x2ra_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2s_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2s_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2s_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x2s_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2ra_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2ra_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2ra_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x2ra_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae7_slot2_encode, Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc16s_h_Slot_ae_slot2_encode, Opcode_ae_mulc16s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc16s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc16s_l_Slot_ae_slot2_encode, Opcode_ae_mulc16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac16s_h_Slot_ae_slot2_encode, Opcode_ae_mulac16s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac16s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac16s_l_Slot_ae_slot2_encode, Opcode_ae_mulac16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc16ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc16ras_Slot_ae_slot2_encode, Opcode_ae_mulfc16ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc16ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc16ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc16ras_Slot_ae_slot2_encode, Opcode_ae_mulafc16ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc16ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16js_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul16js_Slot_ae_slot3_encode, Opcode_ae_mul16js_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng16ras_s1_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot0_encode, 0, Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot2_encode, Opcode_ae_addandsubrng16ras_s1_Slot_ae_slot3_encode, Opcode_ae_addandsubrng16ras_s1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng16ras_s1_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsubrng16ras_s1_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng16ras_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot0_encode, 0, Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot2_encode, Opcode_ae_addandsubrng16ras_s2_Slot_ae_slot3_encode, Opcode_ae_addandsubrng16ras_s2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng16ras_s2_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsubrng16ras_s2_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_conj16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_conj16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq16x2_fir_3_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_3_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_3_Slot_ae7_slot2_encode, Opcode_ae_mulfq16x2_fir_3_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq16x2_fir_2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_2_Slot_ae7_slot2_encode, Opcode_ae_mulfq16x2_fir_2_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq16x2_fir_1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_1_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_1_Slot_ae7_slot2_encode, Opcode_ae_mulfq16x2_fir_1_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfq16x2_fir_0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_0_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfq16x2_fir_0_Slot_ae7_slot2_encode, Opcode_ae_mulfq16x2_fir_0_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq16x2_fir_3_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_3_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_3_Slot_ae7_slot2_encode, Opcode_ae_mulafq16x2_fir_3_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq16x2_fir_2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_2_Slot_ae7_slot2_encode, Opcode_ae_mulafq16x2_fir_2_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq16x2_fir_1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_1_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_1_Slot_ae7_slot2_encode, Opcode_ae_mulafq16x2_fir_1_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafq16x2_fir_0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_0_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafq16x2_fir_0_Slot_ae7_slot2_encode, Opcode_ae_mulafq16x2_fir_0_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaafq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaafq32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaafq32x16_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaafq32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaafq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaafq32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaafq32x16_Slot_ae7_slot2_encode, Opcode_ae_mulaaaafq32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaaq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaaq32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaaq32x16_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaaq32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaaq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaaq32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaaq32x16_Slot_ae7_slot2_encode, Opcode_ae_mulaaaaq32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul16_00_Slot_ae_slot2_encode, Opcode_ae_mul16_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul16_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul16_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16_00_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula16_00_Slot_ae_slot2_encode, Opcode_ae_mula16_00_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula16_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula16_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaaq16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaaaaq16_Slot_ae_slot2_encode, Opcode_ae_mulzaaaaq16_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaaaaq16_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaaaaq16_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaaq16_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaaaaq16_Slot_ae_slot2_encode, Opcode_ae_mulaaaaq16_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaaaaq16_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaaaaq16_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_div64d32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_div64d32_h_Slot_ae_slot0_encode, 0, Opcode_ae_div64d32_h_Slot_ae_slot2_encode, Opcode_ae_div64d32_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_div64d32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_div64d32_l_Slot_ae_slot0_encode, 0, Opcode_ae_div64d32_l_Slot_ae_slot2_encode, Opcode_ae_div64d32_l_Slot_ae_slot3_encode, 0, 0, 0, Opcode_ae_div64d32_l_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sha32_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl32t_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16t_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16c_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16c_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16c_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16c_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldsht_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = { + 0, 0, 0, Opcode_ae_lb_Slot_ae_slot0_encode, Opcode_ae_lb_Slot_ae_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_lb_Slot_ae3_slot0_encode, Opcode_ae_lb_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = { + 0, 0, 0, Opcode_ae_lbi_Slot_ae_slot0_encode, Opcode_ae_lbi_Slot_ae_slot1_encode, 0, 0, 0, 0, 0, Opcode_ae_lbi_Slot_ae3_slot0_encode, Opcode_ae_lbi_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbk_Slot_ae3_slot0_encode, Opcode_ae_lbk_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbki_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbs_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbsi_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbsi_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = { + 0, 0, 0, Opcode_ae_db_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_db_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = { + 0, 0, 0, Opcode_ae_dbi_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_dbi_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_db_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_dbi_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_db_ic1_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_dbi_ic1_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_db_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_dbi_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_ardecnorm16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_ardecnorm16_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbki_dbi_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbki_dbi_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbki_dbi_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbki_dbi_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbki_dbi_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbki_dbi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbi_dbi_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbi_dbi_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbi_dbi_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbi_dbi_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbi_dbi_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbi_dbi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbk_db_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbk_db_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbk_db_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbk_db_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbk_db_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbk_db_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lb_db_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lb_db_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lb_db_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lb_db_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lb_db_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lb_db_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vlel32t_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vlel16t_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sb_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbi_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vles16c_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbf_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sb_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbi_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vles16c_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbf_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sb_ic1_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbi_ic1_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vles16c_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbf_ic1_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sb_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbi_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vles16c_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbf_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sext32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movae_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movae_Slot_ae3_slot0_encode, Opcode_ae_movae_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movea_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movea_Slot_ae3_slot0_encode, Opcode_ae_movea_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_moveep_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_moveep_Slot_ae_slot2_encode, Opcode_ae_moveep_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext72_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sext72_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add72_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_add72_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub72_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sub72_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add72x64_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_add72x64_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub72x64_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sub72x64_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32ep_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32ep_hh_Slot_ae_slot2_encode, Opcode_ae_mul32ep_hh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32ep_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32ep_hh_Slot_ae_slot2_encode, Opcode_ae_mula32ep_hh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32ep_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32ep_hh_Slot_ae_slot2_encode, Opcode_ae_muls32ep_hh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32ep_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaad32ep_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32ep_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssd32ep_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32ep_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaad32ep_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32ep_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssd32ep_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32usep_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32usep_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaad32usep_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32usep_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32usep_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaad32usep_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32usep_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32usep_lh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32usep_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32usep_lh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32usep_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32usep_ll_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32usep_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32usep_ll_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai72_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_srai72_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai72_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_slai72_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat64s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sat64s_Slot_ae_slot2_encode, Opcode_ae_sat64s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16si_n_encode_fns[] = { + 0, 0, Opcode_ae_l16si_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16ui_n_encode_fns[] = { + 0, 0, Opcode_ae_l16ui_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16i_n_encode_fns[] = { + 0, 0, Opcode_ae_s16i_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lalign128_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_lalign128_i_Slot_ae_slot0_encode, Opcode_ae_lalign128_i_Slot_ae_slot1_encode, 0, 0, Opcode_ae_lalign128_i_Slot_ae2_slot0_encode, Opcode_ae_lalign128_i_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lalign128_i_Slot_ae7_slot0_encode, Opcode_ae_lalign128_i_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_lalign128_i_Slot_ae8_slot0_encode, Opcode_ae_lalign128_i_Slot_ae8_slot1_encode, 0, Opcode_ae_lalign128_i_Slot_ae9_slot0_encode, Opcode_ae_lalign128_i_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_lalign128_i_Slot_ae10_slot0_encode, Opcode_ae_lalign128_i_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_salign128_i_encode_fns[] = { + 0, 0, 0, Opcode_ae_salign128_i_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_salign128_i_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la128_pp_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_la128_pp_Slot_ae_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la128_pp_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa128pos_fp_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa128pos_fp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa128pos_fp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x4s_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x4s_ip_Slot_ae_slot0_encode, Opcode_ae_la8x4s_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x4s_ip_Slot_ae2_slot0_encode, Opcode_ae_la8x4s_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x4s_ip_Slot_ae8_slot0_encode, Opcode_ae_la8x4s_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x4s_ip_Slot_ae9_slot0_encode, Opcode_ae_la8x4s_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x4s_ip_Slot_ae10_slot0_encode, Opcode_ae_la8x4s_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x4u_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x4u_ip_Slot_ae_slot0_encode, Opcode_ae_la8x4u_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x4u_ip_Slot_ae2_slot0_encode, Opcode_ae_la8x4u_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x4u_ip_Slot_ae8_slot0_encode, Opcode_ae_la8x4u_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x4u_ip_Slot_ae9_slot0_encode, Opcode_ae_la8x4u_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x4u_ip_Slot_ae10_slot0_encode, Opcode_ae_la8x4u_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2_ip_Slot_ae_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ip_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2_ip_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ip_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2_ip_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ip_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2_ip_Slot_ae_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ip_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2_ip_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ip_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2_ip_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ip_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2_ip_Slot_ae_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ip_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2_ip_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ip_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2_ip_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ip_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2_ip_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2_ic_Slot_ae_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2_ic_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2_ic_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2_ic_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2_ic_Slot_ae_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2_ic_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2_ic_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2_ic_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2_ic_Slot_ae_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2_ic_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2_ic_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2_ic_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2_ic1_Slot_ae_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic1_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2_ic1_Slot_ae7_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic1_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2_ic1_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic1_Slot_ae10_slot0_encode, Opcode_ae_la8x8x2_ic1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2_ic1_Slot_ae_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic1_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2_ic1_Slot_ae7_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic1_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2_ic1_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic1_Slot_ae10_slot0_encode, Opcode_ae_la16x4x2_ic1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2_ic1_Slot_ae_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic1_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2_ic1_Slot_ae7_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae7_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic1_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2_ic1_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae9_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic1_Slot_ae10_slot0_encode, Opcode_ae_la32x2x2_ic1_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la8x8x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la8x8x2_ic2_Slot_ae_slot0_encode, Opcode_ae_la8x8x2_ic2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la8x8x2_ic2_Slot_ae2_slot0_encode, Opcode_ae_la8x8x2_ic2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la8x8x2_ic2_Slot_ae8_slot0_encode, Opcode_ae_la8x8x2_ic2_Slot_ae8_slot1_encode, 0, Opcode_ae_la8x8x2_ic2_Slot_ae9_slot0_encode, Opcode_ae_la8x8x2_ic2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la16x4x2_ic2_Slot_ae_slot0_encode, Opcode_ae_la16x4x2_ic2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la16x4x2_ic2_Slot_ae2_slot0_encode, Opcode_ae_la16x4x2_ic2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4x2_ic2_Slot_ae8_slot0_encode, Opcode_ae_la16x4x2_ic2_Slot_ae8_slot1_encode, 0, Opcode_ae_la16x4x2_ic2_Slot_ae9_slot0_encode, Opcode_ae_la16x4x2_ic2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_la32x2x2_ic2_Slot_ae_slot0_encode, Opcode_ae_la32x2x2_ic2_Slot_ae_slot1_encode, 0, 0, Opcode_ae_la32x2x2_ic2_Slot_ae2_slot0_encode, Opcode_ae_la32x2x2_ic2_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2x2_ic2_Slot_ae8_slot0_encode, Opcode_ae_la32x2x2_ic2_Slot_ae8_slot1_encode, 0, Opcode_ae_la32x2x2_ic2_Slot_ae9_slot0_encode, Opcode_ae_la32x2x2_ic2_Slot_ae9_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa8x8x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa16x4x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2x2_ip_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2x2_ip_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2x2_ip_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa32x2x2_ip_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8x2_ic_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8x2_ic_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa8x8x2_ic_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4x2_ic_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4x2_ic_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa16x4x2_ic_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2x2_ic_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2x2_ic_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2x2_ic_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa32x2x2_ic_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8x2_ic1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa8x8x2_ic1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4x2_ic1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa16x4x2_ic1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2x2_ic1_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2x2_ic1_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2x2_ic1_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa32x2x2_ic1_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa8x8x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa8x8x2_ic2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa8x8x2_ic2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa8x8x2_ic2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa16x4x2_ic2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4x2_ic2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa16x4x2_ic2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2x2_ic2_encode_fns[] = { + 0, 0, 0, Opcode_ae_sa32x2x2_ic2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2x2_ic2_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sa32x2x2_ic2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs8_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_abs8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs8s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_abs8s_Slot_ae_slot3_encode, Opcode_ae_abs8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_abs8s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg8s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_neg8s_Slot_ae_slot3_encode, Opcode_ae_neg8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_neg8s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add8_encode_fns[] = { + 0, 0, 0, Opcode_ae_add8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_add8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub8_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sub8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_max8_encode_fns[] = { + 0, 0, 0, Opcode_ae_max8_Slot_ae_slot0_encode, 0, Opcode_ae_max8_Slot_ae_slot2_encode, 0, Opcode_ae_max8_Slot_ae2_slot0_encode, 0, Opcode_ae_max8_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_max8_Slot_ae4_slot2_encode, Opcode_ae_max8_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_min8_encode_fns[] = { + 0, 0, 0, Opcode_ae_min8_Slot_ae_slot0_encode, 0, Opcode_ae_min8_Slot_ae_slot2_encode, 0, Opcode_ae_min8_Slot_ae2_slot0_encode, 0, Opcode_ae_min8_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_min8_Slot_ae4_slot2_encode, Opcode_ae_min8_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add8s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add8s_Slot_ae_slot3_encode, Opcode_ae_add8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_add8s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub8s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sub8s_Slot_ae_slot3_encode, Opcode_ae_sub8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sub8s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le8_encode_fns[] = { + 0, 0, 0, Opcode_ae_le8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_le8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt8_encode_fns[] = { + 0, 0, 0, Opcode_ae_lt8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lt8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq8_encode_fns[] = { + 0, 0, 0, Opcode_ae_eq8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_eq8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satu16x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_satu16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_satu16x4_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat32x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sat32x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satu32x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_satu32x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat8x8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sat8x8x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satu8x8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_satu8x8x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat8x4x32_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sat8x4x32_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sat8x4x32_l_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satu8x4x32_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_satu8x4x32_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_satu8x4x32_l_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round8x8f16ssym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round8x8f16ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round8x8f16sasym_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round8x8f16sasym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round8x4f32ssym_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round8x4f32ssym_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round8x4f32sasym_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_round8x4f32sasym_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda8_encode_fns[] = { + 0, 0, 0, Opcode_ae_movda8_Slot_ae_slot0_encode, Opcode_ae_movda8_Slot_ae_slot1_encode, 0, 0, Opcode_ae_movda8_Slot_ae2_slot0_encode, Opcode_ae_movda8_Slot_ae2_slot1_encode, 0, Opcode_ae_movda8_Slot_ae3_slot0_encode, Opcode_ae_movda8_Slot_ae3_slot1_encode, Opcode_ae_movda8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad8_encode_fns[] = { + 0, 0, 0, Opcode_ae_movad8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movad8_Slot_ae2_slot0_encode, Opcode_ae_movad8_Slot_ae2_slot1_encode, 0, Opcode_ae_movad8_Slot_ae3_slot0_encode, 0, Opcode_ae_movad8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movdx2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movdx2_Slot_ae_slot0_encode, 0, Opcode_ae_movdx2_Slot_ae_slot2_encode, Opcode_ae_movdx2_Slot_ae_slot3_encode, Opcode_ae_movdx2_Slot_ae2_slot0_encode, Opcode_ae_movdx2_Slot_ae2_slot1_encode, 0, Opcode_ae_movdx2_Slot_ae3_slot0_encode, 0, Opcode_ae_movdx2_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_movdx2_Slot_ae6_slot0_encode, Opcode_ae_movdx2_Slot_ae6_slot1_encode, Opcode_ae_movdx2_Slot_ae6_slot2_encode, Opcode_ae_movdx2_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movdx2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsub32j_encode_fns[] = { + 0, 0, 0, Opcode_ae_addandsub32j_Slot_ae_slot0_encode, 0, Opcode_ae_addandsub32j_Slot_ae_slot2_encode, Opcode_ae_addandsub32j_Slot_ae_slot3_encode, Opcode_ae_addandsub32j_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32j_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_addandsub32j_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addw8_encode_fns[] = { + 0, 0, 0, Opcode_ae_addw8_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addw8_Slot_ae_slot3_encode, Opcode_ae_addw8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addw8_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addw16_encode_fns[] = { + 0, 0, 0, Opcode_ae_addw16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addw16_Slot_ae_slot3_encode, Opcode_ae_addw16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addw16_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addw32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addw32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addw32_Slot_ae_slot3_encode, Opcode_ae_addw32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addw32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subw8_encode_fns[] = { + 0, 0, 0, Opcode_ae_subw8_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subw8_Slot_ae_slot3_encode, Opcode_ae_subw8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subw8_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subw16_encode_fns[] = { + 0, 0, 0, Opcode_ae_subw16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subw16_Slot_ae_slot3_encode, Opcode_ae_subw16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subw16_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subw32_encode_fns[] = { + 0, 0, 0, Opcode_ae_subw32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subw32_Slot_ae_slot3_encode, Opcode_ae_subw32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subw32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_accw8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_accw8_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_accw8_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_accw16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_accw16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_accw16_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_accw32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_accw32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_accw32_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addw8u_encode_fns[] = { + 0, 0, 0, Opcode_ae_addw8u_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addw8u_Slot_ae_slot3_encode, Opcode_ae_addw8u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addw8u_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subw8u_encode_fns[] = { + 0, 0, 0, Opcode_ae_subw8u_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subw8u_Slot_ae_slot3_encode, Opcode_ae_subw8u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subw8u_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_accw8u_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_accw8u_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_accw8u_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulfp32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulafp32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulfp32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulafp32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulsfp32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzaaf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzasf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzsaf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzssf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulaaf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulasf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsaf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulsaf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssf2d32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32s_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulssf2d32s_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzaaf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzasf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzsaf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzssf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulaaf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulasf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsaf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulsaf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssf2d32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32s_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulssf2d32s_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32s_hh_Slot_ae_slot2_encode, Opcode_ae_mul32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32s_hh_Slot_ae_slot2_encode, Opcode_ae_mula32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32s_hh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32s_hh_Slot_ae_slot2_encode, Opcode_ae_muls32s_hh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32s_ll_Slot_ae_slot2_encode, Opcode_ae_mul32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32s_ll_Slot_ae_slot2_encode, Opcode_ae_mula32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32s_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32s_ll_Slot_ae_slot2_encode, Opcode_ae_muls32s_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32s_hl_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32s_hl_Slot_ae_slot2_encode, Opcode_ae_mul32s_hl_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32s_hl_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32s_hl_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32s_hl_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32s_hl_Slot_ae_slot2_encode, Opcode_ae_mula32s_hl_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32s_hl_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32s_hl_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32s_hl_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32s_hl_Slot_ae_slot2_encode, Opcode_ae_muls32s_hl_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32s_hl_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32s_hl_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mul32s_lh_Slot_ae_slot2_encode, Opcode_ae_mul32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mul32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mul32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mula32s_lh_Slot_ae_slot2_encode, Opcode_ae_mula32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mula32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mula32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32s_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_muls32s_lh_Slot_ae_slot2_encode, Opcode_ae_muls32s_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_muls32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_muls32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x2s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x2s_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x2s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x2s_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaad32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzasd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsad32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzsad32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsad32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsad32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaad32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulasd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsad32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulsad32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsad32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsad32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32s_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssd32s_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaad32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaad32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaad32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaad32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzasd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzasd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzasd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzasd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzsad32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzsad32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzsad32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzsad32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzssd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaad32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaad32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaad32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaad32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulasd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulasd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulasd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulasd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsad32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulsad32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsad32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsad32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssd32s_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulssd32s_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x2ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x2ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x2ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x2ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x2ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x2ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x2ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x2ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x2ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x2ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x2ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x2ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzaaf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzasf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzsaf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulzssf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulaaf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulasf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsaf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulsaf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssf2d32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae7_slot2_encode, Opcode_ae_mulssf2d32ra_hh_ll_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzaaf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzasf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsaf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzsaf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae6_slot3_encode, 0, 0, Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulzssf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulaaf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulasf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsaf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulsaf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssf2d32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae7_slot2_encode, Opcode_ae_mulssf2d32ra_hl_lh_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x2r_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x2r_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x2r_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x2r_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x2r_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x2r_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x2r_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x2r_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x2r_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x2r_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x2r_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x2r_hl_lh_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfc32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafc32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfcj32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafcj32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj32ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfcj32ras_Slot_ae_slot2_encode, Opcode_ae_mulfcj32ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfcj32ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfcj32ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj32ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafcj32ras_Slot_ae_slot2_encode, Opcode_ae_mulafcj32ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafcj32ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafcj32ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2p32x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulf2p32x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf2p32x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulaf2p32x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf2p32x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulsf2p32x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2p32x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulf2p32x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf2p32x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulaf2p32x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf2p32x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulsf2p32x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x2s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulp32x2s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2p32x4s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4s_Slot_ae7_slot2_encode, Opcode_ae_mul2p32x4s_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2p32x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4_Slot_ae7_slot2_encode, Opcode_ae_mul2p32x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2p32x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula2p32x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2p32x4_Slot_ae7_slot2_encode, Opcode_ae_mula2p32x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls2p32x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muls2p32x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muls2p32x4_Slot_ae7_slot2_encode, Opcode_ae_muls2p32x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2p32x4t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4t_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2p32x4t_Slot_ae7_slot2_encode, Opcode_ae_mul2p32x4t_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2p32x4t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula2p32x4t_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2p32x4t_Slot_ae7_slot2_encode, Opcode_ae_mula2p32x4t_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls2p32x4t_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muls2p32x4t_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muls2p32x4t_Slot_ae7_slot2_encode, Opcode_ae_muls2p32x4t_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaa32x2_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaa32x2_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzss32x2_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzss32x2_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaa32x2_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaa32x2_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32x2_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulss32x2_hh_ll_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulcj32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulcj32_Slot_ae_slot2_encode, Opcode_ae_mulcj32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulcj32_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulcj32_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulacj32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulacj32_Slot_ae_slot2_encode, Opcode_ae_mulacj32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulacj32_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulacj32_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muladdf32rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muladdf32rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muladdf32rs_Slot_ae7_slot2_encode, Opcode_ae_muladdf32rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muladdf32ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_muladdf32ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muladdf32ras_Slot_ae7_slot2_encode, Opcode_ae_muladdf32ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsubf32rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsubf32rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsubf32rs_Slot_ae7_slot2_encode, Opcode_ae_mulsubf32rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsubf32ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsubf32ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsubf32ras_Slot_ae7_slot2_encode, Opcode_ae_mulsubf32ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32ra_Slot_ae_slot2_encode, Opcode_ae_mulfc32ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfc32ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfc32ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32ra_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32ra_Slot_ae_slot2_encode, Opcode_ae_mulafc32ra_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafc32ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafc32ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulcj32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulcj32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulacj32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulacj32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulc32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32w_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulac32w_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2d32x2ws_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2d32x2ws_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2d32x2ws_Slot_ae7_slot2_encode, Opcode_ae_mulf2d32x2ws_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaa2q16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q16_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaa2q16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaa2q16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q16_Slot_ae7_slot2_encode, Opcode_ae_mulaaaa2q16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp16s_h_Slot_ae_slot2_encode, Opcode_ae_mulp16s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp16s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp16s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap16s_h_Slot_ae_slot2_encode, Opcode_ae_mulap16s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap16s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap16s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp16s_h_Slot_ae_slot2_encode, Opcode_ae_mulsp16s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp16s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp16s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap16s_l_Slot_ae_slot2_encode, Opcode_ae_mulap16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp16s_l_Slot_ae_slot2_encode, Opcode_ae_mulsp16s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulc16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulac16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulc16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulac16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2c16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2c16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2c16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula2c16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfc16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafc16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfcj16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafcj16s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj16ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfcj16ras_Slot_ae_slot2_encode, Opcode_ae_mulfcj16ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfcj16ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfcj16ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj16ras_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafcj16ras_Slot_ae_slot2_encode, Opcode_ae_mulafcj16ras_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulafcj16ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulafcj16ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc16s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulc16s_Slot_ae_slot2_encode, Opcode_ae_mulc16s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulc16s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulc16s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac16s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulac16s_Slot_ae_slot2_encode, Opcode_ae_mulac16s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulac16s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulac16s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp16x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfp16x4rs_Slot_ae_slot2_encode, Opcode_ae_mulfp16x4rs_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulfp16x4rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulfp16x4rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd16x16x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd16x16x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd16x16x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulfd16x16x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp16x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulp16x16x4s_Slot_ae_slot2_encode, Opcode_ae_mulp16x16x4s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulp16x16x4s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulp16x16x4s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap16x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulap16x16x4s_Slot_ae_slot2_encode, Opcode_ae_mulap16x16x4s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulap16x16x4s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulap16x16x4s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp16x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulsp16x16x4s_Slot_ae_slot2_encode, Opcode_ae_mulsp16x16x4s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulsp16x16x4s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulsp16x16x4s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaa2d16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaa2d16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaa2d16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaa2d16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzss2d16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzss2d16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzss2d16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzss2d16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaa2d16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaa2d16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaa2d16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaa2d16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss2d16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulss2d16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulss2d16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulss2d16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulss2d16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss2d16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulss2d16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulss2d16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulss2d16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulss2d16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulaafd16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulaafd16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulaafd16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_hh_ll_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_hh_ll_Slot_ae_slot2_encode, Opcode_ae_mulssfd16ss_hh_ll_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd16ss_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_hl_lh_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_hl_lh_Slot_ae_slot2_encode, Opcode_ae_mulssfd16ss_hl_lh_Slot_ae_slot3_encode, 0, 0, Opcode_ae_mulssfd16ss_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd16x16x4ws_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd16x16x4ws_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd16x16x4ws_Slot_ae7_slot2_encode, Opcode_ae_mulfd16x16x4ws_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaa2q16x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q16x8_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q16x8_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaa2q16x8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaa2q16x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q16x8_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q16x8_Slot_ae7_slot2_encode, Opcode_ae_mulaaaa2q16x8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaa2q8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q8_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q8_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaa2q8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaa2q8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q8_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q8_Slot_ae7_slot2_encode, Opcode_ae_mulaaaa2q8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulc32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulac32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulc32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulac32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulpc32x16x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulpc32x16x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulpc32x16x2_Slot_ae7_slot2_encode, Opcode_ae_mulpc32x16x2_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulapc32x16x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulapc32x16x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulapc32x16x2_Slot_ae7_slot2_encode, Opcode_ae_mulapc32x16x2_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32x16w_h_Slot_ae_slot2_encode, Opcode_ae_mulfc32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32x16w_h_Slot_ae_slot2_encode, Opcode_ae_mulafc32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulfc32x16w_l_Slot_ae_slot2_encode, Opcode_ae_mulfc32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_mulafc32x16w_l_Slot_ae_slot2_encode, Opcode_ae_mulafc32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfcj32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj32x16w_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafcj32x16w_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfcj32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfcj32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafcj32x16w_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafcj32x16w_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2p32x16x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulf2p32x16x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf2p32x16x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulaf2p32x16x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf2p32x16x4ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4ras_Slot_ae7_slot2_encode, Opcode_ae_mulsf2p32x16x4ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2p32x16x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulf2p32x16x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf2p32x16x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulaf2p32x16x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf2p32x16x4rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4rs_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4rs_Slot_ae7_slot2_encode, Opcode_ae_mulsf2p32x16x4rs_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf2p32x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf2p32x16x4s_Slot_ae7_slot2_encode, Opcode_ae_mulf2p32x16x4s_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf2p32x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf2p32x16x4s_Slot_ae7_slot2_encode, Opcode_ae_mulaf2p32x16x4s_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf2p32x16x4s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf2p32x16x4s_Slot_ae7_slot2_encode, Opcode_ae_mulsf2p32x16x4s_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfpc32x16x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpc32x16x2ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpc32x16x2ras_Slot_ae7_slot2_encode, Opcode_ae_mulfpc32x16x2ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpc32x16x2ras_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafpc32x16x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafpc32x16x2ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafpc32x16x2ras_Slot_ae7_slot2_encode, Opcode_ae_mulafpc32x16x2ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfpcj32x16x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpcj32x16x2ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpcj32x16x2ras_Slot_ae7_slot2_encode, Opcode_ae_mulfpcj32x16x2ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfpcj32x16x2ras_Slot_ae4_slot3_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafpcj32x16x2ras_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulafpcj32x16x2ras_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafpcj32x16x2ras_Slot_ae7_slot2_encode, Opcode_ae_mulafpcj32x16x2ras_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaa2q32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaa2q32x16_Slot_ae7_slot2_encode, Opcode_ae_mulzaaaa2q32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaa2q32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q32x16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaa2q32x16_Slot_ae7_slot2_encode, Opcode_ae_mulaaaa2q32x16_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2q32x16_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2q32x16_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2q32x16_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mul2q32x16_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2q32x16_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula2q32x16_fir_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2q32x16_fir_h_Slot_ae7_slot2_encode, Opcode_ae_mula2q32x16_fir_h_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2q32x16_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mul2q32x16_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2q32x16_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mul2q32x16_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2q32x16_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_mula2q32x16_fir_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2q32x16_fir_l_Slot_ae7_slot2_encode, Opcode_ae_mula2q32x16_fir_l_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai8_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srai8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai8r_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai8r_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srai8r_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli8_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srli8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai8_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slai8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai8s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slai8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa8_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srla8_encode_fns[] = { + 0, 0, 0, Opcode_ae_srla8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srla8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa8s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa8rs_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa8rs_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa8rs_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa8s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli16_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srli16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai16_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slai16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa16_encode_fns[] = { + 0, 0, 0, Opcode_ae_slaa16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_slaa16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srla16_encode_fns[] = { + 0, 0, 0, Opcode_ae_srla16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srla16_Slot_ae2_slot0_encode, 0, 0, Opcode_ae_srla16_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai16sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai16sym_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srai16sym_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa16syms_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa16syms_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa16syms_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai32sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai32sym_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srai32sym_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32syms_encode_fns[] = { + 0, 0, 0, Opcode_ae_sraa32syms_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_sraa32syms_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srav16rs_encode_fns[] = { + 0, 0, 0, Opcode_ae_srav16rs_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srav16rs_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srav32rs_encode_fns[] = { + 0, 0, 0, Opcode_ae_srav32rs_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_srav32rs_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8s_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8s_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8s_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8s_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8s_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8s_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8s_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8s_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8u_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8u_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8u_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8u_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8u_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8u_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8us_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8us_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8us_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f8us_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f8us_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f8us_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8u_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8u_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8u_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8u_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8u_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8u_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8us_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8us_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8us_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f8us_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f8us_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f8us_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f16_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f16s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f16_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f16_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f16s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f16u_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f16u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f16u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti32x4f16us_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti32x4f16us_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti32x4f16us_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f16u_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f16u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f16u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32x4f16us_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta32x4f16us_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta32x4f16us_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti16x4x2f8_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti16x4x2f8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti16x4x2f8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvti16x4x2f8_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti16x4x2f8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti16x4x2f8s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti16x4x2f8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvti16x4x2f8s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta16x4x2f8_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta16x4x2f8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta16x4x2f8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvta16x4x2f8_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta16x4x2f8s_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta16x4x2f8s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta16x4x2f8s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvta16x4x2f8s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti16x4x2f8u_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti16x4x2f8u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti16x4x2f8u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvti16x4x2f8u_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvti16x4x2f8us_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvti16x4x2f8us_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvti16x4x2f8us_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta16x4x2f8u_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta16x4x2f8u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta16x4x2f8u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_cvta16x4x2f8u_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta16x4x2f8us_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvta16x4x2f8us_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_cvta16x4x2f8us_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel8x8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sel8x8_Slot_ae_slot2_encode, Opcode_ae_sel8x8_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sel8x8_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_sel8x8_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sel8x8_Slot_ae7_slot2_encode, Opcode_ae_sel8x8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_shfl8x8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_shfl8x8_Slot_ae_slot2_encode, Opcode_ae_shfl8x8_Slot_ae_slot3_encode, 0, 0, Opcode_ae_shfl8x8_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_shfl8x8_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_shfl8x8_Slot_ae7_slot2_encode, Opcode_ae_shfl8x8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sel16x4_Slot_ae_slot2_encode, Opcode_ae_sel16x4_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sel16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_sel16x4_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sel16x4_Slot_ae7_slot2_encode, Opcode_ae_sel16x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, Opcode_ae_sel16x4_Slot_ae9_slot2_encode, Opcode_ae_sel16x4_Slot_ae9_slot3_encode, 0, 0, Opcode_ae_sel16x4_Slot_ae10_slot2_encode, Opcode_ae_sel16x4_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_shfl16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_shfl16x4_Slot_ae_slot2_encode, Opcode_ae_shfl16x4_Slot_ae_slot3_encode, 0, 0, Opcode_ae_shfl16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_shfl16x4_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_shfl16x4_Slot_ae7_slot2_encode, Opcode_ae_shfl16x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dsel8x8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_dsel8x8_Slot_ae_slot2_encode, Opcode_ae_dsel8x8_Slot_ae_slot3_encode, 0, 0, Opcode_ae_dsel8x8_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_dsel8x8_Slot_ae7_slot2_encode, Opcode_ae_dsel8x8_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dsel16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_dsel16x4_Slot_ae_slot2_encode, Opcode_ae_dsel16x4_Slot_ae_slot3_encode, 0, 0, Opcode_ae_dsel16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_dsel16x4_Slot_ae7_slot2_encode, Opcode_ae_dsel16x4_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, Opcode_ae_dsel16x4_Slot_ae9_slot2_encode, Opcode_ae_dsel16x4_Slot_ae9_slot3_encode, 0, 0, Opcode_ae_dsel16x4_Slot_ae10_slot2_encode, Opcode_ae_dsel16x4_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel8x8i_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sel8x8i_Slot_ae_slot2_encode, Opcode_ae_sel8x8i_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sel8x8i_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_ae_sel8x8i_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sel8x8i_Slot_ae7_slot2_encode, Opcode_ae_sel8x8i_Slot_ae7_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rmax8x8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_rmax8x8_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_rmax8x8_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_rmax8x8_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rmin8x8_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_rmin8x8_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_rmin8x8_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_rmin8x8_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rmax16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_rmax16x4_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_rmax16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_rmax16x4_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rmin16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_rmin16x4_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_rmin16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_rmin16x4_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sort16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_sort16x4_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_sort16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sort16x4_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radd8x8_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radd8x8_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radd8x8_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radd8x8_h_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radda8x8_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radda8x8_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radda8x8_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radda8x8_h_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radd8x8_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radd8x8_l_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radd8x8_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radd8x8_l_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radda8x8_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radda8x8_l_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radda8x8_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radda8x8_l_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radd16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radd16x4_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radd16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radd16x4_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_radda16x4_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_radda16x4_Slot_ae_slot2_encode, 0, 0, 0, Opcode_ae_radda16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_radda16x4_Slot_ae7_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmax8x8_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_bmax8x8_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmax8x8_h_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmax8x8_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_bmax8x8_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmax8x8_l_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmax8x8_l_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmin8x8_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_bmin8x8_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmin8x8_h_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmin8x8_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_bmin8x8_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmin8x8_l_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmin8x8_l_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmax16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_bmax16x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_bmax16x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmax16x4_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmax16x4_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmin16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_bmin16x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_bmin16x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmin16x4_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmin16x4_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmax32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_bmax32x2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_bmax32x2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmax32x2_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmax32x2_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bmin32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_bmin32x2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_bmin32x2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_bmin32x2_Slot_ae6_slot0_encode, 0, 0, Opcode_ae_bmin32x2_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addinv16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addinv16s_Slot_ae_slot0_encode, 0, Opcode_ae_addinv16s_Slot_ae_slot2_encode, Opcode_ae_addinv16s_Slot_ae_slot3_encode, Opcode_ae_addinv16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addinv16s_Slot_ae6_slot0_encode, 0, Opcode_ae_addinv16s_Slot_ae6_slot2_encode, Opcode_ae_addinv16s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addinv32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addinv32s_Slot_ae_slot0_encode, 0, Opcode_ae_addinv32s_Slot_ae_slot2_encode, Opcode_ae_addinv32s_Slot_ae_slot3_encode, Opcode_ae_addinv32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addinv32s_Slot_ae6_slot0_encode, 0, Opcode_ae_addinv32s_Slot_ae6_slot2_encode, Opcode_ae_addinv32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt16x8_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt16x8_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt16x8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt8x16_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt8x16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt8x16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt8x16_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt8x16_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movt8x16_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movbd1x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movbd1x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movbd1x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movbd1x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_movbd1x2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movbd1x2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movneg32s_t_encode_fns[] = { + 0, 0, 0, Opcode_ae_movneg32s_t_Slot_ae_slot0_encode, 0, Opcode_ae_movneg32s_t_Slot_ae_slot2_encode, Opcode_ae_movneg32s_t_Slot_ae_slot3_encode, Opcode_ae_movneg32s_t_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movdext_encode_fns[] = { + 0, 0, 0, Opcode_ae_movdext_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movdext_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movadext_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_movadext_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movadext_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movadext_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_movadext_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_movadext_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsa16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsa16x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsa16x4_Slot_ae2_slot0_encode, Opcode_ae_nsa16x4_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsaz32x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsaz32x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsaz32x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsa32x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_nsa32x4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_nsa32x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunci16x4f32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunci16x4f32s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunci16x4f32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci16x4f32s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci16x4f32s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunci16x4f64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunci16x4f64s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunci16x4f64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci16x4f64s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci16x4f64s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16x4f32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca16x4f32s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunca16x4f32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca16x4f32s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca16x4f32s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16x4f64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_trunca16x4f64s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_trunca16x4f64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca16x4f64s_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_trunca16x4f64s_Slot_ae8_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addc32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addc32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_addc32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addc32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subc32_encode_fns[] = { + 0, 0, 0, Opcode_ae_subc32_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_subc32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subc32_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addc32u_encode_fns[] = { + 0, 0, 0, Opcode_ae_addc32u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_addc32u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addc32u_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subc32u_encode_fns[] = { + 0, 0, 0, Opcode_ae_subc32u_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_subc32u_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_subc32u_Slot_ae6_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_expadd16_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_expadd16_h_Slot_ae_slot2_encode, Opcode_ae_expadd16_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_expsub16_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_expsub16_h_Slot_ae_slot2_encode, Opcode_ae_expsub16_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_expadd16_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_expadd16_l_Slot_ae_slot2_encode, Opcode_ae_expadd16_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_expsub16_l_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_expsub16_l_Slot_ae_slot2_encode, Opcode_ae_expsub16_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcexp32_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_addcexp32_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcexp32_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_addcexp32_l_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_calcrng16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_calcrng16_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_calcrng32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_calcrng32_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rng32x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_rng32x4_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lav8x8x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_lav8x8x2_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lav8x8x2_xp_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lav8x8x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_lav8x8x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_ae_lav8x8x2_xp_Slot_ae10_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lav16x4x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_lav16x4x2_xp_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lav16x4x2_xp_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lav16x4x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_lav16x4x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, Opcode_ae_lav16x4x2_xp_Slot_ae10_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sav8x8x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_sav8x8x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sav8x8x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sav8x8x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sav16x4x2_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_sav16x4x2_xp_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sav16x4x2_xp_Slot_ae8_slot0_encode, 0, 0, Opcode_ae_sav16x4x2_xp_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movzbvcdr_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_movzbvcdr_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movzbvcdr_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movdrzbvc_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_movdrzbvc_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movdrzbvc_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lavunsqz8x8_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_lavunsqz8x8_xp_Slot_ae_slot0_encode, Opcode_ae_lavunsqz8x8_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_lavunsqz8x8_xp_Slot_ae2_slot0_encode, Opcode_ae_lavunsqz8x8_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lavunsqz8x8_xp_Slot_ae8_slot0_encode, Opcode_ae_lavunsqz8x8_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_lavunsqz8x8_xp_Slot_ae9_slot0_encode, Opcode_ae_lavunsqz8x8_xp_Slot_ae9_slot1_encode, 0, 0, 0, Opcode_ae_lavunsqz8x8_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lavunsqz16x4_xp_encode_fns[] = { + 0, 0, 0, Opcode_ae_lavunsqz16x4_xp_Slot_ae_slot0_encode, Opcode_ae_lavunsqz16x4_xp_Slot_ae_slot1_encode, 0, 0, Opcode_ae_lavunsqz16x4_xp_Slot_ae2_slot0_encode, Opcode_ae_lavunsqz16x4_xp_Slot_ae2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lavunsqz16x4_xp_Slot_ae8_slot0_encode, Opcode_ae_lavunsqz16x4_xp_Slot_ae8_slot1_encode, 0, Opcode_ae_lavunsqz16x4_xp_Slot_ae9_slot0_encode, Opcode_ae_lavunsqz16x4_xp_Slot_ae9_slot1_encode, 0, 0, 0, Opcode_ae_lavunsqz16x4_xp_Slot_ae10_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2x4q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2x4q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2x4q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2x4q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulqq8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulqq8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaqq8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaqq8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o8x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o8x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o8x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o8x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul8q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul8q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula8q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula8q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2x4q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2x4q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2x4q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2x4q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul2x4q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul2x4q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula2x4q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula2x4q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulqq4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulqq4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaqq4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaqq4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulqq4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulqq4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaqq4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaqq4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o4x16cnv_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o4x16cnv_hh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o4x16cnv_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o4x16cnv_hl_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o4x16cnv_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o4x16cnv_lh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul4o4x16cnv_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul4o4x16cnv_ll_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o4x16cnv_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o4x16cnv_hh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o4x16cnv_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o4x16cnv_hl_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o4x16cnv_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o4x16cnv_lh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula4o4x16cnv_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula4o4x16cnv_ll_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluu4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluu4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauu4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauu4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o4x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o4x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4qw8x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4qw8x16_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus2x4q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus2x4q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus2x4q8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus2x4q8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulusqq8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulusqq8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulausqq8x16cnv_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulausqq8x16cnv_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o8x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o8x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o8x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o8x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus8q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus8q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus8q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus8q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus2x4q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus2x4q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus2x4q4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus2x4q4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus2x4q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus2x4q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus2x4q4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus2x4q4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulusqq4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulusqq4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulausqq4x16cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulausqq4x16cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulusqq4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulusqq4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulausqq4x16cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulausqq4x16cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o4x16cnv_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o4x16cnv_hh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o4x16cnv_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o4x16cnv_hl_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o4x16cnv_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o4x16cnv_lh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulus4o4x16cnv_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulus4o4x16cnv_ll_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o4x16cnv_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o4x16cnv_hh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o4x16cnv_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o4x16cnv_hl_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o4x16cnv_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o4x16cnv_lh_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaus4o4x16cnv_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaus4o4x16cnv_ll_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsu4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsu4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasu4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasu4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muluuzb3x3o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muluuzb3x3o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulauuzb3x3o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulauuzb3x3o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzb8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzb8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulazb8q8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulazb8q8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzb4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzb4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulazb4o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulazb4o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzb8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzb8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulazb8q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulazb8q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzb8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzb8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulazb8q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulazb8q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzb2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzb2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulazb2x4q8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulazb2x4q8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzb2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzb2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulazb2x4q8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulazb2x4q8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzb4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzb4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulazb4o8x8cnv_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulazb4o8x8cnv_h_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzb4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzb4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulazb4o8x8cnv_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulazb4o8x8cnv_l_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzb3x3o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzb3x3o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulazb3x3o8x8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulazb3x3o8x8_Slot_ae8_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtsf16_l_encode_fns[] = { + 0, 0, 0, Opcode_cvtsf16_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_cvtsf16_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtsf16_l_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtsf16_h_encode_fns[] = { + 0, 0, 0, Opcode_cvtsf16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_cvtsf16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtsf16_h_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtf16s_l_encode_fns[] = { + 0, 0, 0, Opcode_cvtf16s_l_Slot_ae_slot0_encode, 0, 0, 0, Opcode_cvtf16s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtf16s_l_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtf16s_h_encode_fns[] = { + 0, 0, 0, Opcode_cvtf16s_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_cvtf16s_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtf16s_h_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movfcrfsrv_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_movfcrfsrv_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movvfcrfsr_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_movvfcrfsr_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = { + 0, 0, 0, Opcode_movt_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movt_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_movt_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = { + 0, 0, 0, Opcode_movf_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movf_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_movf_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = { + 0, 0, 0, Opcode_moveqz_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_moveqz_s_Slot_ae2_slot0_encode, Opcode_moveqz_s_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_moveqz_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = { + 0, 0, 0, Opcode_movnez_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movnez_s_Slot_ae2_slot0_encode, Opcode_movnez_s_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_movnez_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = { + 0, 0, 0, Opcode_movgez_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movgez_s_Slot_ae2_slot0_encode, Opcode_movgez_s_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_movgez_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = { + 0, 0, 0, Opcode_movltz_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_movltz_s_Slot_ae2_slot0_encode, Opcode_movltz_s_Slot_ae2_slot1_encode, 0, 0, 0, Opcode_movltz_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = { + 0, 0, 0, Opcode_rfr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = { + 0, 0, 0, Opcode_wfr_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mul_s_Slot_ae_slot2_encode, Opcode_mul_s_Slot_ae_slot3_encode, 0, 0, Opcode_mul_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_mul_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mul_s_Slot_ae9_slot2_encode, Opcode_mul_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mul_s_Slot_ae10_slot2_encode, Opcode_mul_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_madd_s_Slot_ae_slot2_encode, Opcode_madd_s_Slot_ae_slot3_encode, 0, 0, Opcode_madd_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_madd_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_madd_s_Slot_ae9_slot2_encode, Opcode_madd_s_Slot_ae9_slot3_encode, 0, 0, Opcode_madd_s_Slot_ae10_slot2_encode, Opcode_madd_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_msub_s_Slot_ae_slot2_encode, Opcode_msub_s_Slot_ae_slot3_encode, 0, 0, Opcode_msub_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_msub_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msub_s_Slot_ae9_slot2_encode, Opcode_msub_s_Slot_ae9_slot3_encode, 0, 0, Opcode_msub_s_Slot_ae10_slot2_encode, Opcode_msub_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msubn_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_msubn_s_Slot_ae_slot2_encode, Opcode_msubn_s_Slot_ae_slot3_encode, 0, 0, Opcode_msubn_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_msubn_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msubn_s_Slot_ae9_slot2_encode, Opcode_msubn_s_Slot_ae9_slot3_encode, 0, 0, Opcode_msubn_s_Slot_ae10_slot2_encode, Opcode_msubn_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddn_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maddn_s_Slot_ae_slot2_encode, Opcode_maddn_s_Slot_ae_slot3_encode, 0, 0, Opcode_maddn_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_maddn_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddn_s_Slot_ae9_slot2_encode, Opcode_maddn_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maddn_s_Slot_ae10_slot2_encode, Opcode_maddn_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_add_s_Slot_ae_slot2_encode, Opcode_add_s_Slot_ae_slot3_encode, 0, 0, Opcode_add_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_add_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_s_Slot_ae9_slot2_encode, Opcode_add_s_Slot_ae9_slot3_encode, 0, 0, Opcode_add_s_Slot_ae10_slot2_encode, Opcode_add_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_sub_s_Slot_ae_slot2_encode, Opcode_sub_s_Slot_ae_slot3_encode, 0, 0, Opcode_sub_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_sub_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_s_Slot_ae9_slot2_encode, Opcode_sub_s_Slot_ae9_slot3_encode, 0, 0, Opcode_sub_s_Slot_ae10_slot2_encode, Opcode_sub_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = { + 0, 0, 0, Opcode_ole_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ole_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ole_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ole_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = { + 0, 0, 0, Opcode_olt_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_olt_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_olt_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_olt_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = { + 0, 0, 0, Opcode_oeq_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_oeq_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_oeq_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_oeq_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = { + 0, 0, 0, Opcode_un_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_un_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_un_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_un_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = { + 0, 0, 0, Opcode_ule_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ule_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ule_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ule_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = { + 0, 0, 0, Opcode_ult_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ult_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ult_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ult_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = { + 0, 0, 0, Opcode_ueq_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ueq_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, Opcode_ueq_s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ueq_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nexp01_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_nexp01_s_Slot_ae_slot2_encode, Opcode_nexp01_s_Slot_ae_slot3_encode, 0, 0, Opcode_nexp01_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_nexp01_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_nexp01_s_Slot_ae9_slot2_encode, Opcode_nexp01_s_Slot_ae9_slot3_encode, 0, 0, Opcode_nexp01_s_Slot_ae10_slot2_encode, Opcode_nexp01_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mksadj_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mksadj_s_Slot_ae_slot2_encode, Opcode_mksadj_s_Slot_ae_slot3_encode, 0, 0, Opcode_mksadj_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_mksadj_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mksadj_s_Slot_ae9_slot2_encode, Opcode_mksadj_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mksadj_s_Slot_ae10_slot2_encode, Opcode_mksadj_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mkdadj_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mkdadj_s_Slot_ae_slot2_encode, Opcode_mkdadj_s_Slot_ae_slot3_encode, 0, 0, Opcode_mkdadj_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_mkdadj_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mkdadj_s_Slot_ae9_slot2_encode, Opcode_mkdadj_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mkdadj_s_Slot_ae10_slot2_encode, Opcode_mkdadj_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_div0_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_div0_s_Slot_ae_slot2_encode, Opcode_div0_s_Slot_ae_slot3_encode, 0, 0, Opcode_div0_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_div0_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_div0_s_Slot_ae9_slot2_encode, Opcode_div0_s_Slot_ae9_slot3_encode, 0, 0, Opcode_div0_s_Slot_ae10_slot2_encode, Opcode_div0_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sqrt0_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_sqrt0_s_Slot_ae_slot2_encode, Opcode_sqrt0_s_Slot_ae_slot3_encode, 0, 0, Opcode_sqrt0_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_sqrt0_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sqrt0_s_Slot_ae9_slot2_encode, Opcode_sqrt0_s_Slot_ae9_slot3_encode, 0, 0, Opcode_sqrt0_s_Slot_ae10_slot2_encode, Opcode_sqrt0_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_recip0_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_recip0_s_Slot_ae_slot2_encode, Opcode_recip0_s_Slot_ae_slot3_encode, 0, 0, Opcode_recip0_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_recip0_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_recip0_s_Slot_ae9_slot2_encode, Opcode_recip0_s_Slot_ae9_slot3_encode, 0, 0, Opcode_recip0_s_Slot_ae10_slot2_encode, Opcode_recip0_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsqrt0_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_rsqrt0_s_Slot_ae_slot2_encode, Opcode_rsqrt0_s_Slot_ae_slot3_encode, 0, 0, Opcode_rsqrt0_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_rsqrt0_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rsqrt0_s_Slot_ae9_slot2_encode, Opcode_rsqrt0_s_Slot_ae9_slot3_encode, 0, 0, Opcode_rsqrt0_s_Slot_ae10_slot2_encode, Opcode_rsqrt0_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_divn_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_divn_s_Slot_ae_slot2_encode, Opcode_divn_s_Slot_ae_slot3_encode, 0, 0, Opcode_divn_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_divn_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_divn_s_Slot_ae9_slot2_encode, Opcode_divn_s_Slot_ae9_slot3_encode, 0, 0, Opcode_divn_s_Slot_ae10_slot2_encode, Opcode_divn_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexp_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addexp_s_Slot_ae_slot2_encode, Opcode_addexp_s_Slot_ae_slot3_encode, 0, 0, Opcode_addexp_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addexp_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addexp_s_Slot_ae9_slot2_encode, Opcode_addexp_s_Slot_ae9_slot3_encode, 0, 0, Opcode_addexp_s_Slot_ae10_slot2_encode, Opcode_addexp_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexpm_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addexpm_s_Slot_ae_slot2_encode, Opcode_addexpm_s_Slot_ae_slot3_encode, 0, 0, Opcode_addexpm_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addexpm_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addexpm_s_Slot_ae9_slot2_encode, Opcode_addexpm_s_Slot_ae9_slot3_encode, 0, 0, Opcode_addexpm_s_Slot_ae10_slot2_encode, Opcode_addexpm_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_min_s_Slot_ae_slot2_encode, Opcode_min_s_Slot_ae_slot3_encode, 0, 0, Opcode_min_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_min_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_min_s_Slot_ae9_slot2_encode, Opcode_min_s_Slot_ae9_slot3_encode, 0, 0, Opcode_min_s_Slot_ae10_slot2_encode, Opcode_min_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_max_s_Slot_ae_slot2_encode, Opcode_max_s_Slot_ae_slot3_encode, 0, 0, Opcode_max_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_max_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_max_s_Slot_ae9_slot2_encode, Opcode_max_s_Slot_ae9_slot3_encode, 0, 0, Opcode_max_s_Slot_ae10_slot2_encode, Opcode_max_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulmux_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mulmux_s_Slot_ae_slot2_encode, Opcode_mulmux_s_Slot_ae_slot3_encode, 0, 0, Opcode_mulmux_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulmux_s_Slot_ae9_slot2_encode, Opcode_mulmux_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mulmux_s_Slot_ae10_slot2_encode, Opcode_mulmux_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddmux_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maddmux_s_Slot_ae_slot2_encode, Opcode_maddmux_s_Slot_ae_slot3_encode, 0, 0, Opcode_maddmux_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddmux_s_Slot_ae9_slot2_encode, Opcode_maddmux_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maddmux_s_Slot_ae10_slot2_encode, Opcode_maddmux_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = { + 0, 0, 0, Opcode_trunc_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_trunc_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_trunc_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = { + 0, 0, 0, Opcode_utrunc_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_utrunc_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_utrunc_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc_sx2_encode_fns[] = { + 0, 0, 0, Opcode_trunc_sx2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_trunc_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_trunc_sx2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc_sx2_encode_fns[] = { + 0, 0, 0, Opcode_utrunc_sx2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_utrunc_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_utrunc_sx2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ficeil_s_encode_fns[] = { + 0, 0, 0, Opcode_ficeil_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ficeil_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ficeil_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_fifloor_s_encode_fns[] = { + 0, 0, 0, Opcode_fifloor_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_fifloor_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_fifloor_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_firint_s_encode_fns[] = { + 0, 0, 0, Opcode_firint_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_firint_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_firint_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_firound_s_encode_fns[] = { + 0, 0, 0, Opcode_firound_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_firound_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_firound_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_fitrunc_s_encode_fns[] = { + 0, 0, 0, Opcode_fitrunc_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_fitrunc_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_fitrunc_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = { + 0, 0, 0, Opcode_float_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_float_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_float_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = { + 0, 0, 0, Opcode_ufloat_s_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ufloat_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ufloat_s_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float_sx2_encode_fns[] = { + 0, 0, 0, Opcode_float_sx2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_float_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_float_sx2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat_sx2_encode_fns[] = { + 0, 0, 0, Opcode_ufloat_sx2_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ufloat_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ufloat_sx2_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_abs_s_Slot_ae_slot2_encode, Opcode_abs_s_Slot_ae_slot3_encode, 0, Opcode_abs_s_Slot_ae2_slot1_encode, Opcode_abs_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_abs_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_abs_s_Slot_ae9_slot2_encode, Opcode_abs_s_Slot_ae9_slot3_encode, 0, 0, Opcode_abs_s_Slot_ae10_slot2_encode, Opcode_abs_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_neg_s_Slot_ae_slot2_encode, Opcode_neg_s_Slot_ae_slot3_encode, 0, Opcode_neg_s_Slot_ae2_slot1_encode, Opcode_neg_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_neg_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_neg_s_Slot_ae9_slot2_encode, Opcode_neg_s_Slot_ae9_slot3_encode, 0, 0, Opcode_neg_s_Slot_ae10_slot2_encode, Opcode_neg_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_conjc_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_conjc_s_Slot_ae_slot2_encode, Opcode_conjc_s_Slot_ae_slot3_encode, 0, Opcode_conjc_s_Slot_ae2_slot1_encode, Opcode_conjc_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_conjc_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_conjc_s_Slot_ae9_slot2_encode, Opcode_conjc_s_Slot_ae9_slot3_encode, 0, 0, Opcode_conjc_s_Slot_ae10_slot2_encode, Opcode_conjc_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muljc_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_muljc_s_Slot_ae_slot2_encode, Opcode_muljc_s_Slot_ae_slot3_encode, 0, Opcode_muljc_s_Slot_ae2_slot1_encode, Opcode_muljc_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_muljc_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_muljc_s_Slot_ae9_slot2_encode, Opcode_muljc_s_Slot_ae9_slot3_encode, 0, 0, Opcode_muljc_s_Slot_ae10_slot2_encode, Opcode_muljc_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_const_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_const_s_Slot_ae_slot2_encode, Opcode_const_s_Slot_ae_slot3_encode, 0, Opcode_const_s_Slot_ae2_slot1_encode, Opcode_const_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_const_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_const_s_Slot_ae9_slot2_encode, Opcode_const_s_Slot_ae9_slot3_encode, 0, 0, Opcode_const_s_Slot_ae10_slot2_encode, Opcode_const_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clsfy_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_clsfy_s_Slot_ae_slot2_encode, Opcode_clsfy_s_Slot_ae_slot3_encode, 0, 0, Opcode_clsfy_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_clsfy_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_clsfy_s_Slot_ae9_slot2_encode, Opcode_clsfy_s_Slot_ae9_slot3_encode, 0, 0, Opcode_clsfy_s_Slot_ae10_slot2_encode, Opcode_clsfy_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minnum_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_minnum_s_Slot_ae_slot2_encode, Opcode_minnum_s_Slot_ae_slot3_encode, 0, 0, Opcode_minnum_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_minnum_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_minnum_s_Slot_ae9_slot2_encode, Opcode_minnum_s_Slot_ae9_slot3_encode, 0, 0, Opcode_minnum_s_Slot_ae10_slot2_encode, Opcode_minnum_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxnum_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maxnum_s_Slot_ae_slot2_encode, Opcode_maxnum_s_Slot_ae_slot3_encode, 0, 0, Opcode_maxnum_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_maxnum_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maxnum_s_Slot_ae9_slot2_encode, Opcode_maxnum_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maxnum_s_Slot_ae10_slot2_encode, Opcode_maxnum_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addandsub_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addandsub_s_Slot_ae_slot2_encode, Opcode_addandsub_s_Slot_ae_slot3_encode, 0, 0, Opcode_addandsub_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addandsub_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addandsub_s_Slot_ae9_slot2_encode, Opcode_addandsub_s_Slot_ae9_slot3_encode, 0, 0, Opcode_addandsub_s_Slot_ae10_slot2_encode, Opcode_addandsub_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addandsubjc_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addandsubjc_s_Slot_ae_slot2_encode, Opcode_addandsubjc_s_Slot_ae_slot3_encode, 0, 0, Opcode_addandsubjc_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addandsubjc_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addandsubjc_s_Slot_ae9_slot2_encode, Opcode_addandsubjc_s_Slot_ae9_slot3_encode, 0, 0, Opcode_addandsubjc_s_Slot_ae10_slot2_encode, Opcode_addandsubjc_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_hl_lh_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_add_hl_lh_s_Slot_ae_slot2_encode, Opcode_add_hl_lh_s_Slot_ae_slot3_encode, 0, 0, Opcode_add_hl_lh_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_add_hl_lh_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_hl_lh_s_Slot_ae9_slot2_encode, Opcode_add_hl_lh_s_Slot_ae9_slot3_encode, 0, 0, Opcode_add_hl_lh_s_Slot_ae10_slot2_encode, Opcode_add_hl_lh_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madda_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_madda_s_Slot_ae_slot2_encode, Opcode_madda_s_Slot_ae_slot3_encode, 0, 0, Opcode_madda_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_madda_s_Slot_ae9_slot2_encode, Opcode_madda_s_Slot_ae9_slot3_encode, 0, 0, Opcode_madda_s_Slot_ae10_slot2_encode, Opcode_madda_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_frexp_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_frexp_s_Slot_ae_slot2_encode, Opcode_frexp_s_Slot_ae_slot3_encode, 0, 0, Opcode_frexp_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_frexp_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_frexp_s_Slot_ae9_slot2_encode, Opcode_frexp_s_Slot_ae9_slot3_encode, 0, 0, Opcode_frexp_s_Slot_ae10_slot2_encode, Opcode_frexp_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_floatexp_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_floatexp_s_Slot_ae_slot2_encode, Opcode_floatexp_s_Slot_ae_slot3_encode, 0, 0, Opcode_floatexp_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_floatexp_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_floatexp_s_Slot_ae9_slot2_encode, Opcode_floatexp_s_Slot_ae9_slot3_encode, 0, 0, Opcode_floatexp_s_Slot_ae10_slot2_encode, Opcode_floatexp_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minnumabs_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_minnumabs_s_Slot_ae_slot2_encode, Opcode_minnumabs_s_Slot_ae_slot3_encode, 0, 0, Opcode_minnumabs_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_minnumabs_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_minnumabs_s_Slot_ae9_slot2_encode, Opcode_minnumabs_s_Slot_ae9_slot3_encode, 0, 0, Opcode_minnumabs_s_Slot_ae10_slot2_encode, Opcode_minnumabs_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxnumabs_s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maxnumabs_s_Slot_ae_slot2_encode, Opcode_maxnumabs_s_Slot_ae_slot3_encode, 0, 0, Opcode_maxnumabs_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_maxnumabs_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maxnumabs_s_Slot_ae9_slot2_encode, Opcode_maxnumabs_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maxnumabs_s_Slot_ae10_slot2_encode, Opcode_maxnumabs_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulq_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulq_s_Slot_ae9_slot2_encode, Opcode_mulq_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mulq_s_Slot_ae10_slot2_encode, Opcode_mulq_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddq_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddq_s_Slot_ae9_slot2_encode, Opcode_maddq_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maddq_s_Slot_ae10_slot2_encode, Opcode_maddq_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msubq_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msubq_s_Slot_ae9_slot2_encode, Opcode_msubq_s_Slot_ae9_slot3_encode, 0, 0, Opcode_msubq_s_Slot_ae10_slot2_encode, Opcode_msubq_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulmuxq_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulmuxq_s_Slot_ae9_slot2_encode, Opcode_mulmuxq_s_Slot_ae9_slot3_encode, 0, 0, Opcode_mulmuxq_s_Slot_ae10_slot2_encode, Opcode_mulmuxq_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddmuxq_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddmuxq_s_Slot_ae9_slot2_encode, Opcode_maddmuxq_s_Slot_ae9_slot3_encode, 0, 0, Opcode_maddmuxq_s_Slot_ae10_slot2_encode, Opcode_maddmuxq_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bmaxnum_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_bmaxnum_s_Slot_ae_slot3_encode, 0, 0, Opcode_bmaxnum_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bmaxnum_s_Slot_ae9_slot3_encode, 0, 0, 0, Opcode_bmaxnum_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bminnum_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_bminnum_s_Slot_ae_slot3_encode, 0, 0, Opcode_bminnum_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bminnum_s_Slot_ae9_slot3_encode, 0, 0, 0, Opcode_bminnum_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bmaxnumabs_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_bmaxnumabs_s_Slot_ae_slot3_encode, 0, 0, Opcode_bmaxnumabs_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bmaxnumabs_s_Slot_ae9_slot3_encode, 0, 0, 0, Opcode_bmaxnumabs_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bminnumabs_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_bminnumabs_s_Slot_ae_slot3_encode, 0, 0, Opcode_bminnumabs_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bminnumabs_s_Slot_ae9_slot3_encode, 0, 0, 0, Opcode_bminnumabs_s_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_abs_sx2x2_Slot_ae_slot2_encode, Opcode_abs_sx2x2_Slot_ae_slot3_encode, 0, Opcode_abs_sx2x2_Slot_ae2_slot1_encode, Opcode_abs_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_abs_sx2x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_abs_sx2x2_Slot_ae9_slot2_encode, Opcode_abs_sx2x2_Slot_ae9_slot3_encode, 0, 0, Opcode_abs_sx2x2_Slot_ae10_slot2_encode, Opcode_abs_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_neg_sx2x2_Slot_ae_slot2_encode, Opcode_neg_sx2x2_Slot_ae_slot3_encode, 0, Opcode_neg_sx2x2_Slot_ae2_slot1_encode, Opcode_neg_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_neg_sx2x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_neg_sx2x2_Slot_ae9_slot2_encode, Opcode_neg_sx2x2_Slot_ae9_slot3_encode, 0, 0, Opcode_neg_sx2x2_Slot_ae10_slot2_encode, Opcode_neg_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_conjc_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_conjc_sx2x2_Slot_ae_slot2_encode, Opcode_conjc_sx2x2_Slot_ae_slot3_encode, 0, Opcode_conjc_sx2x2_Slot_ae2_slot1_encode, Opcode_conjc_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_conjc_sx2x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_conjc_sx2x2_Slot_ae9_slot2_encode, Opcode_conjc_sx2x2_Slot_ae9_slot3_encode, 0, 0, Opcode_conjc_sx2x2_Slot_ae10_slot2_encode, Opcode_conjc_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muljc_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_muljc_sx2x2_Slot_ae_slot2_encode, Opcode_muljc_sx2x2_Slot_ae_slot3_encode, 0, Opcode_muljc_sx2x2_Slot_ae2_slot1_encode, Opcode_muljc_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_muljc_sx2x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_muljc_sx2x2_Slot_ae9_slot2_encode, Opcode_muljc_sx2x2_Slot_ae9_slot3_encode, 0, 0, Opcode_muljc_sx2x2_Slot_ae10_slot2_encode, Opcode_muljc_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_const_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_const_sx2x2_Slot_ae_slot2_encode, Opcode_const_sx2x2_Slot_ae_slot3_encode, 0, Opcode_const_sx2x2_Slot_ae2_slot1_encode, Opcode_const_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_const_sx2x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_const_sx2x2_Slot_ae9_slot2_encode, Opcode_const_sx2x2_Slot_ae9_slot3_encode, 0, 0, Opcode_const_sx2x2_Slot_ae10_slot2_encode, Opcode_const_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_sx2x2_Slot_ae9_slot2_encode, 0, 0, 0, Opcode_add_sx2x2_Slot_ae10_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_sx2x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_sx2x2_Slot_ae9_slot2_encode, 0, 0, 0, Opcode_sub_sx2x2_Slot_ae10_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mul_sx2x2_Slot_ae10_slot2_encode, Opcode_mul_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madd_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_madd_sx2x2_Slot_ae10_slot2_encode, Opcode_madd_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msub_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msub_sx2x2_Slot_ae10_slot2_encode, Opcode_msub_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulmux_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulmux_sx2x2_Slot_ae10_slot2_encode, Opcode_mulmux_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddmux_sx2x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddmux_sx2x2_Slot_ae10_slot2_encode, Opcode_maddmux_sx2x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_abs_h_Slot_ae_slot2_encode, Opcode_abs_h_Slot_ae_slot3_encode, 0, Opcode_abs_h_Slot_ae2_slot1_encode, Opcode_abs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_abs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_abs_h_Slot_ae9_slot2_encode, Opcode_abs_h_Slot_ae9_slot3_encode, 0, 0, Opcode_abs_h_Slot_ae10_slot2_encode, Opcode_abs_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexp_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addexp_h_Slot_ae_slot2_encode, Opcode_addexp_h_Slot_ae_slot3_encode, 0, 0, Opcode_addexp_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addexp_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addexp_h_Slot_ae9_slot2_encode, Opcode_addexp_h_Slot_ae9_slot3_encode, 0, 0, Opcode_addexp_h_Slot_ae10_slot2_encode, Opcode_addexp_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexpm_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_addexpm_h_Slot_ae_slot2_encode, Opcode_addexpm_h_Slot_ae_slot3_encode, 0, 0, Opcode_addexpm_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_addexpm_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addexpm_h_Slot_ae9_slot2_encode, Opcode_addexpm_h_Slot_ae9_slot3_encode, 0, 0, Opcode_addexpm_h_Slot_ae10_slot2_encode, Opcode_addexpm_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clsfy_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_clsfy_h_Slot_ae_slot2_encode, Opcode_clsfy_h_Slot_ae_slot3_encode, 0, 0, Opcode_clsfy_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_clsfy_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_clsfy_h_Slot_ae9_slot2_encode, Opcode_clsfy_h_Slot_ae9_slot3_encode, 0, 0, Opcode_clsfy_h_Slot_ae10_slot2_encode, Opcode_clsfy_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_conjc_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_conjc_h_Slot_ae_slot2_encode, Opcode_conjc_h_Slot_ae_slot3_encode, 0, Opcode_conjc_h_Slot_ae2_slot1_encode, Opcode_conjc_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_conjc_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_conjc_h_Slot_ae9_slot2_encode, Opcode_conjc_h_Slot_ae9_slot3_encode, 0, 0, Opcode_conjc_h_Slot_ae10_slot2_encode, Opcode_conjc_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_const_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_const_h_Slot_ae_slot2_encode, Opcode_const_h_Slot_ae_slot3_encode, 0, Opcode_const_h_Slot_ae2_slot1_encode, Opcode_const_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_const_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_const_h_Slot_ae9_slot2_encode, Opcode_const_h_Slot_ae9_slot3_encode, 0, 0, Opcode_const_h_Slot_ae10_slot2_encode, Opcode_const_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_min_h_Slot_ae_slot2_encode, Opcode_min_h_Slot_ae_slot3_encode, 0, 0, Opcode_min_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_min_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_min_h_Slot_ae9_slot2_encode, Opcode_min_h_Slot_ae9_slot3_encode, 0, 0, Opcode_min_h_Slot_ae10_slot2_encode, Opcode_min_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_max_h_Slot_ae_slot2_encode, Opcode_max_h_Slot_ae_slot3_encode, 0, 0, Opcode_max_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_max_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_max_h_Slot_ae9_slot2_encode, Opcode_max_h_Slot_ae9_slot3_encode, 0, 0, Opcode_max_h_Slot_ae10_slot2_encode, Opcode_max_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minnum_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_minnum_h_Slot_ae_slot2_encode, Opcode_minnum_h_Slot_ae_slot3_encode, 0, 0, Opcode_minnum_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_minnum_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_minnum_h_Slot_ae9_slot2_encode, Opcode_minnum_h_Slot_ae9_slot3_encode, 0, 0, Opcode_minnum_h_Slot_ae10_slot2_encode, Opcode_minnum_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxnum_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maxnum_h_Slot_ae_slot2_encode, Opcode_maxnum_h_Slot_ae_slot3_encode, 0, 0, Opcode_maxnum_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_maxnum_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maxnum_h_Slot_ae9_slot2_encode, Opcode_maxnum_h_Slot_ae9_slot3_encode, 0, 0, Opcode_maxnum_h_Slot_ae10_slot2_encode, Opcode_maxnum_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muljc_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_muljc_h_Slot_ae_slot2_encode, Opcode_muljc_h_Slot_ae_slot3_encode, 0, Opcode_muljc_h_Slot_ae2_slot1_encode, Opcode_muljc_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_muljc_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_muljc_h_Slot_ae9_slot2_encode, Opcode_muljc_h_Slot_ae9_slot3_encode, 0, 0, Opcode_muljc_h_Slot_ae10_slot2_encode, Opcode_muljc_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_neg_h_Slot_ae_slot2_encode, Opcode_neg_h_Slot_ae_slot3_encode, 0, Opcode_neg_h_Slot_ae2_slot1_encode, Opcode_neg_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_neg_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_neg_h_Slot_ae9_slot2_encode, Opcode_neg_h_Slot_ae9_slot3_encode, 0, 0, Opcode_neg_h_Slot_ae10_slot2_encode, Opcode_neg_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_oeq_h_encode_fns[] = { + 0, 0, 0, Opcode_oeq_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ole_h_encode_fns[] = { + 0, 0, 0, Opcode_ole_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_olt_h_encode_fns[] = { + 0, 0, 0, Opcode_olt_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ueq_h_encode_fns[] = { + 0, 0, 0, Opcode_ueq_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ule_h_encode_fns[] = { + 0, 0, 0, Opcode_ule_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ult_h_encode_fns[] = { + 0, 0, 0, Opcode_ult_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_un_h_encode_fns[] = { + 0, 0, 0, Opcode_un_h_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_div0_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_div0_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ficeil_h_encode_fns[] = { + 0, 0, 0, Opcode_ficeil_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ficeil_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_fifloor_h_encode_fns[] = { + 0, 0, 0, Opcode_fifloor_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_fifloor_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_firint_h_encode_fns[] = { + 0, 0, 0, Opcode_firint_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_firint_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_firound_h_encode_fns[] = { + 0, 0, 0, Opcode_firound_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_firound_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_fitrunc_h_encode_fns[] = { + 0, 0, 0, Opcode_fitrunc_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_fitrunc_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mkdadj_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mkdadj_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mksadj_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mksadj_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nexp0_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_nexp0_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nexp01_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_nexp01_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_recip0_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_recip0_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsqrt0_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_rsqrt0_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sqrt0_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_sqrt0_h_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float16_h_encode_fns[] = { + 0, 0, 0, Opcode_float16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_float16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat16_h_encode_fns[] = { + 0, 0, 0, Opcode_ufloat16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ufloat16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc16_h_encode_fns[] = { + 0, 0, 0, Opcode_trunc16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_trunc16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc16_h_encode_fns[] = { + 0, 0, 0, Opcode_utrunc16_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_utrunc16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float16_hx4_encode_fns[] = { + 0, 0, 0, Opcode_float16_hx4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_float16_hx4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat16_hx4_encode_fns[] = { + 0, 0, 0, Opcode_ufloat16_hx4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ufloat16_hx4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc16_hx4_encode_fns[] = { + 0, 0, 0, Opcode_trunc16_hx4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_trunc16_hx4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc16_hx4_encode_fns[] = { + 0, 0, 0, Opcode_utrunc16_hx4_Slot_ae_slot0_encode, 0, 0, 0, Opcode_utrunc16_hx4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_add_h_Slot_ae_slot2_encode, Opcode_add_h_Slot_ae_slot3_encode, 0, 0, Opcode_add_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_add_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_h_Slot_ae9_slot2_encode, Opcode_add_h_Slot_ae9_slot3_encode, 0, 0, Opcode_add_h_Slot_ae10_slot2_encode, Opcode_add_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_sub_h_Slot_ae_slot2_encode, Opcode_sub_h_Slot_ae_slot3_encode, 0, 0, Opcode_sub_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_sub_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_h_Slot_ae9_slot2_encode, Opcode_sub_h_Slot_ae9_slot3_encode, 0, 0, Opcode_sub_h_Slot_ae10_slot2_encode, Opcode_sub_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_mul_h_Slot_ae_slot2_encode, Opcode_mul_h_Slot_ae_slot3_encode, 0, 0, Opcode_mul_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_mul_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mul_h_Slot_ae9_slot2_encode, Opcode_mul_h_Slot_ae9_slot3_encode, 0, 0, Opcode_mul_h_Slot_ae10_slot2_encode, Opcode_mul_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madd_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_madd_h_Slot_ae_slot2_encode, Opcode_madd_h_Slot_ae_slot3_encode, 0, 0, Opcode_madd_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_madd_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_madd_h_Slot_ae9_slot2_encode, Opcode_madd_h_Slot_ae9_slot3_encode, 0, 0, Opcode_madd_h_Slot_ae10_slot2_encode, Opcode_madd_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msub_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_msub_h_Slot_ae_slot2_encode, Opcode_msub_h_Slot_ae_slot3_encode, 0, 0, Opcode_msub_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_msub_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msub_h_Slot_ae9_slot2_encode, Opcode_msub_h_Slot_ae9_slot3_encode, 0, 0, Opcode_msub_h_Slot_ae10_slot2_encode, Opcode_msub_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddn_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_maddn_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_maddn_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msubn_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_msubn_h_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msubn_h_Slot_ae9_slot2_encode, Opcode_msubn_h_Slot_ae9_slot3_encode, 0, 0, Opcode_msubn_h_Slot_ae10_slot2_encode, Opcode_msubn_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_divn_h_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_divn_h_Slot_ae_slot2_encode, 0, 0, 0, Opcode_divn_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rminnum_h_encode_fns[] = { + 0, 0, 0, Opcode_rminnum_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_rminnum_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rminnum_h_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rmaxnum_h_encode_fns[] = { + 0, 0, 0, Opcode_rmaxnum_h_Slot_ae_slot0_encode, 0, 0, 0, Opcode_rmaxnum_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rmaxnum_h_Slot_ae9_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_abs_hx4x2_Slot_ae_slot2_encode, Opcode_abs_hx4x2_Slot_ae_slot3_encode, 0, Opcode_abs_hx4x2_Slot_ae2_slot1_encode, Opcode_abs_hx4x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_abs_hx4x2_Slot_ae9_slot2_encode, Opcode_abs_hx4x2_Slot_ae9_slot3_encode, 0, 0, Opcode_abs_hx4x2_Slot_ae10_slot2_encode, Opcode_abs_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_neg_hx4x2_Slot_ae_slot2_encode, Opcode_neg_hx4x2_Slot_ae_slot3_encode, 0, Opcode_neg_hx4x2_Slot_ae2_slot1_encode, Opcode_neg_hx4x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_neg_hx4x2_Slot_ae9_slot2_encode, Opcode_neg_hx4x2_Slot_ae9_slot3_encode, 0, 0, Opcode_neg_hx4x2_Slot_ae10_slot2_encode, Opcode_neg_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_conjc_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_conjc_hx4x2_Slot_ae_slot2_encode, Opcode_conjc_hx4x2_Slot_ae_slot3_encode, 0, Opcode_conjc_hx4x2_Slot_ae2_slot1_encode, Opcode_conjc_hx4x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_conjc_hx4x2_Slot_ae9_slot2_encode, Opcode_conjc_hx4x2_Slot_ae9_slot3_encode, 0, 0, Opcode_conjc_hx4x2_Slot_ae10_slot2_encode, Opcode_conjc_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_const_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_const_hx4x2_Slot_ae_slot2_encode, Opcode_const_hx4x2_Slot_ae_slot3_encode, 0, Opcode_const_hx4x2_Slot_ae2_slot1_encode, Opcode_const_hx4x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, Opcode_const_hx4x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_const_hx4x2_Slot_ae9_slot2_encode, Opcode_const_hx4x2_Slot_ae9_slot3_encode, 0, 0, Opcode_const_hx4x2_Slot_ae10_slot2_encode, Opcode_const_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muljc_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_muljc_hx4x2_Slot_ae_slot2_encode, Opcode_muljc_hx4x2_Slot_ae_slot3_encode, 0, Opcode_muljc_hx4x2_Slot_ae2_slot1_encode, Opcode_muljc_hx4x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_muljc_hx4x2_Slot_ae9_slot2_encode, Opcode_muljc_hx4x2_Slot_ae9_slot3_encode, 0, 0, Opcode_muljc_hx4x2_Slot_ae10_slot2_encode, Opcode_muljc_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_hx4x2_Slot_ae10_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_hx4x2_Slot_ae10_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mul_hx4x2_Slot_ae10_slot2_encode, Opcode_mul_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madd_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_madd_hx4x2_Slot_ae10_slot2_encode, Opcode_madd_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msub_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msub_hx4x2_Slot_ae10_slot2_encode, Opcode_msub_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulq_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulq_h_Slot_ae9_slot2_encode, 0, 0, 0, Opcode_mulq_h_Slot_ae10_slot2_encode, Opcode_mulq_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddq_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_maddq_h_Slot_ae10_slot2_encode, Opcode_maddq_h_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulcnvh_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulcnvh_hx4x2_Slot_ae10_slot2_encode, Opcode_mulcnvh_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulacnvh_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulacnvh_hx4x2_Slot_ae10_slot2_encode, Opcode_mulacnvh_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulcnvl_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulcnvl_hx4x2_Slot_ae10_slot2_encode, Opcode_mulcnvl_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulacnvl_hx4x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mulacnvl_hx4x2_Slot_ae10_slot2_encode, Opcode_mulacnvl_hx4x2_Slot_ae10_slot3_encode, 0, 0, 0, 0, 0 +}; + +int num_bypass_groups() { + return 0; +} + +int num_bypass_group_chunks() { + return 0; +} + +uint32 *bypass_entry(int i) { + return 0; +} + + +/* Opcode table. */ + +static xtensa_funcUnit_use Opcode_l32e_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32e_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32i_n_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32i_n_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l16ui_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l16si_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32r_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l8ui_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32ex_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32ex_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s16i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32nb_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s8i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_lddr32_p_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sddr32_p_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_lict_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_licw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sict_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sicw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sdct_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ldct_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sdcw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ldcw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32ai_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32ri_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4f_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4f_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4f_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4f_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4s_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4s_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4s_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4u_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4u_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4u_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4u_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x4u_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x4u_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x4u_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x4u_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ri_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_h_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8_0_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4rng_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4rng_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4rng_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4rng_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2rng_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2rng_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2rng_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2rng_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x4ux2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x4ux2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x4ux2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x4ux2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x8x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s8x8x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64x2_xc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2rng_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2rng_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2rng_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4x2rng_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lalign64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_salign64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la64_pp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2pos_pc2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa64pos_fp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa64neg_fp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24x2ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4ra32s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 } +}; + +static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbs_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbsi_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbki_dbi_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbki_dbi_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbki_dbi_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbi_dbi_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbi_dbi_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbi_dbi_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbk_db_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbk_db_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbk_db_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lb_db_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lb_db_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lb_db_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16si_n_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16ui_n_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16i_n_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lalign128_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_salign128_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la128_pp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa128pos_fp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x4s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x4u_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la8x8x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa8x8x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2x2_ic2_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lav8x8x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lav16x4x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sav8x8x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sav16x4x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lavunsqz8x8_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lavunsqz16x4_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_opcode_internal opcodes[] = { + { "excw", ICLASS_xt_iclass_excw, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", ICLASS_xt_iclass_rfe, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", ICLASS_xt_iclass_rfde, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", ICLASS_xt_iclass_syscall, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "call12", ICLASS_xt_iclass_call12, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", ICLASS_xt_iclass_call8, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", ICLASS_xt_iclass_call4, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", ICLASS_xt_iclass_callx12, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", ICLASS_xt_iclass_callx8, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", ICLASS_xt_iclass_callx4, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", ICLASS_xt_iclass_entry, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", ICLASS_xt_iclass_movsp, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", ICLASS_xt_iclass_rotw, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", ICLASS_xt_iclass_l32e, + 0, + Opcode_l32e_encode_fns, 1, Opcode_l32e_funcUnit_uses }, + { "s32e", ICLASS_xt_iclass_s32e, + 0, + Opcode_s32e_encode_fns, 1, Opcode_s32e_funcUnit_uses }, + { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", ICLASS_xt_iclass_add_n, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", ICLASS_xt_iclass_addi_n, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", ICLASS_xt_iclass_ill_n, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", ICLASS_xt_iclass_loadi4, + 0, + Opcode_l32i_n_encode_fns, 1, Opcode_l32i_n_funcUnit_uses }, + { "mov.n", ICLASS_xt_iclass_mov_n, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", ICLASS_xt_iclass_movi_n, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", ICLASS_xt_iclass_nopn, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", ICLASS_xt_iclass_retn, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", ICLASS_xt_iclass_storei4, + 0, + Opcode_s32i_n_encode_fns, 1, Opcode_s32i_n_funcUnit_uses }, + { "rur.threadptr", ICLASS_rur_threadptr, + 0, + Opcode_rur_threadptr_encode_fns, 0, 0 }, + { "wur.threadptr", ICLASS_wur_threadptr, + 0, + Opcode_wur_threadptr_encode_fns, 0, 0 }, + { "addi", ICLASS_xt_iclass_addi, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", ICLASS_xt_iclass_addmi, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", ICLASS_xt_iclass_addsub, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "addx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "sub", ICLASS_xt_iclass_addsub, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "subx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", ICLASS_xt_iclass_bit, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", ICLASS_xt_iclass_bit, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", ICLASS_xt_iclass_bit, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bgei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bnei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bbci", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "ball", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bany", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bbc", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beq", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bge", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "bgeu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "blt", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bltu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bnall", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bne", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bnone", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "beqz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bgez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "bnez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "call0", ICLASS_xt_iclass_call0, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", ICLASS_xt_iclass_callx0, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "extui", ICLASS_xt_iclass_exti, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", ICLASS_xt_iclass_ill, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", ICLASS_xt_iclass_jump, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", ICLASS_xt_iclass_jumpx, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", ICLASS_xt_iclass_l16ui, + 0, + Opcode_l16ui_encode_fns, 1, Opcode_l16ui_funcUnit_uses }, + { "l16si", ICLASS_xt_iclass_l16si, + 0, + Opcode_l16si_encode_fns, 1, Opcode_l16si_funcUnit_uses }, + { "l32i", ICLASS_xt_iclass_l32i, + 0, + Opcode_l32i_encode_fns, 1, Opcode_l32i_funcUnit_uses }, + { "l32r", ICLASS_xt_iclass_l32r, + 0, + Opcode_l32r_encode_fns, 1, Opcode_l32r_funcUnit_uses }, + { "l8ui", ICLASS_xt_iclass_l8i, + 0, + Opcode_l8ui_encode_fns, 1, Opcode_l8ui_funcUnit_uses }, + { "loop", ICLASS_xt_iclass_loop, + XTENSA_OPCODE_IS_LOOP, + Opcode_loop_encode_fns, 0, 0 }, + { "loopgtz", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopgtz_encode_fns, 0, 0 }, + { "loopnez", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopnez_encode_fns, 0, 0 }, + { "movi", ICLASS_xt_iclass_movi, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", ICLASS_xt_iclass_movz, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movgez", ICLASS_xt_iclass_movz, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "movltz", ICLASS_xt_iclass_movz, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movnez", ICLASS_xt_iclass_movz, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "abs", ICLASS_xt_iclass_neg, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "neg", ICLASS_xt_iclass_neg, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "nop", ICLASS_xt_iclass_nop, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "l32ex", ICLASS_xt_iclass_l32ex, + 0, + Opcode_l32ex_encode_fns, 1, Opcode_l32ex_funcUnit_uses }, + { "s32ex", ICLASS_xt_iclass_s32ex, + 0, + Opcode_s32ex_encode_fns, 1, Opcode_s32ex_funcUnit_uses }, + { "getex", ICLASS_xt_iclass_getex, + 0, + Opcode_getex_encode_fns, 0, 0 }, + { "clrex", ICLASS_xt_iclass_clrex, + 0, + Opcode_clrex_encode_fns, 0, 0 }, + { "ret", ICLASS_xt_iclass_return, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "simcall", ICLASS_xt_iclass_simcall, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "s16i", ICLASS_xt_iclass_s16i, + 0, + Opcode_s16i_encode_fns, 1, Opcode_s16i_funcUnit_uses }, + { "s32i", ICLASS_xt_iclass_s32i, + 0, + Opcode_s32i_encode_fns, 1, Opcode_s32i_funcUnit_uses }, + { "s32nb", ICLASS_xt_iclass_s32nb, + 0, + Opcode_s32nb_encode_fns, 1, Opcode_s32nb_funcUnit_uses }, + { "s8i", ICLASS_xt_iclass_s8i, + 0, + Opcode_s8i_encode_fns, 1, Opcode_s8i_funcUnit_uses }, + { "ssa8b", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssa8l", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssl", ICLASS_xt_iclass_sar, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssr", ICLASS_xt_iclass_sar, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssai", ICLASS_xt_iclass_sari, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", ICLASS_xt_iclass_shifts, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", ICLASS_xt_iclass_shiftst, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "sra", ICLASS_xt_iclass_shiftt, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "srl", ICLASS_xt_iclass_shiftt, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "slli", ICLASS_xt_iclass_slli, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", ICLASS_xt_iclass_srai, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", ICLASS_xt_iclass_srli, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", ICLASS_xt_iclass_memw, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", ICLASS_xt_iclass_extw, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", ICLASS_xt_iclass_isync, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "dsync", ICLASS_xt_iclass_sync, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "esync", ICLASS_xt_iclass_sync, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "rsync", ICLASS_xt_iclass_sync, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "rsil", ICLASS_xt_iclass_rsil, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.lend", ICLASS_xt_iclass_rsr_lend, + 0, + Opcode_rsr_lend_encode_fns, 0, 0 }, + { "wsr.lend", ICLASS_xt_iclass_wsr_lend, + 0, + Opcode_wsr_lend_encode_fns, 0, 0 }, + { "xsr.lend", ICLASS_xt_iclass_xsr_lend, + 0, + Opcode_xsr_lend_encode_fns, 0, 0 }, + { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, + 0, + Opcode_rsr_lcount_encode_fns, 0, 0 }, + { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, + 0, + Opcode_wsr_lcount_encode_fns, 0, 0 }, + { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, + 0, + Opcode_xsr_lcount_encode_fns, 0, 0 }, + { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, + 0, + Opcode_rsr_lbeg_encode_fns, 0, 0 }, + { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, + 0, + Opcode_wsr_lbeg_encode_fns, 0, 0 }, + { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, + 0, + Opcode_xsr_lbeg_encode_fns, 0, 0 }, + { "rsr.sar", ICLASS_xt_iclass_rsr_sar, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", ICLASS_xt_iclass_wsr_sar, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", ICLASS_xt_iclass_xsr_sar, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl, + 0, + Opcode_rsr_memctl_encode_fns, 0, 0 }, + { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl, + 0, + Opcode_wsr_memctl_encode_fns, 0, 0 }, + { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl, + 0, + Opcode_xsr_memctl_encode_fns, 0, 0 }, + { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, + 0, + Opcode_rsr_configid0_encode_fns, 0, 0 }, + { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, + 0, + Opcode_wsr_configid0_encode_fns, 0, 0 }, + { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, + 0, + Opcode_rsr_configid1_encode_fns, 0, 0 }, + { "rsr.ps", ICLASS_xt_iclass_rsr_ps, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", ICLASS_xt_iclass_wsr_ps, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", ICLASS_xt_iclass_xsr_ps, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, + 0, + Opcode_rsr_epc3_encode_fns, 0, 0 }, + { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, + 0, + Opcode_wsr_epc3_encode_fns, 0, 0 }, + { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, + 0, + Opcode_xsr_epc3_encode_fns, 0, 0 }, + { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, + 0, + Opcode_rsr_excsave3_encode_fns, 0, 0 }, + { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, + 0, + Opcode_wsr_excsave3_encode_fns, 0, 0 }, + { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, + 0, + Opcode_xsr_excsave3_encode_fns, 0, 0 }, + { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, + 0, + Opcode_rsr_epc4_encode_fns, 0, 0 }, + { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, + 0, + Opcode_wsr_epc4_encode_fns, 0, 0 }, + { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, + 0, + Opcode_xsr_epc4_encode_fns, 0, 0 }, + { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, + 0, + Opcode_rsr_excsave4_encode_fns, 0, 0 }, + { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, + 0, + Opcode_wsr_excsave4_encode_fns, 0, 0 }, + { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, + 0, + Opcode_xsr_excsave4_encode_fns, 0, 0 }, + { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, + 0, + Opcode_rsr_epc5_encode_fns, 0, 0 }, + { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, + 0, + Opcode_wsr_epc5_encode_fns, 0, 0 }, + { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, + 0, + Opcode_xsr_epc5_encode_fns, 0, 0 }, + { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, + 0, + Opcode_rsr_excsave5_encode_fns, 0, 0 }, + { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, + 0, + Opcode_wsr_excsave5_encode_fns, 0, 0 }, + { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, + 0, + Opcode_xsr_excsave5_encode_fns, 0, 0 }, + { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, + 0, + Opcode_rsr_epc6_encode_fns, 0, 0 }, + { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, + 0, + Opcode_wsr_epc6_encode_fns, 0, 0 }, + { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, + 0, + Opcode_xsr_epc6_encode_fns, 0, 0 }, + { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, + 0, + Opcode_rsr_excsave6_encode_fns, 0, 0 }, + { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, + 0, + Opcode_wsr_excsave6_encode_fns, 0, 0 }, + { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, + 0, + Opcode_xsr_excsave6_encode_fns, 0, 0 }, + { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, + 0, + Opcode_rsr_eps3_encode_fns, 0, 0 }, + { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, + 0, + Opcode_wsr_eps3_encode_fns, 0, 0 }, + { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, + 0, + Opcode_xsr_eps3_encode_fns, 0, 0 }, + { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, + 0, + Opcode_rsr_eps4_encode_fns, 0, 0 }, + { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, + 0, + Opcode_wsr_eps4_encode_fns, 0, 0 }, + { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, + 0, + Opcode_xsr_eps4_encode_fns, 0, 0 }, + { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, + 0, + Opcode_rsr_eps5_encode_fns, 0, 0 }, + { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, + 0, + Opcode_wsr_eps5_encode_fns, 0, 0 }, + { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, + 0, + Opcode_xsr_eps5_encode_fns, 0, 0 }, + { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, + 0, + Opcode_rsr_eps6_encode_fns, 0, 0 }, + { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, + 0, + Opcode_wsr_eps6_encode_fns, 0, 0 }, + { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, + 0, + Opcode_xsr_eps6_encode_fns, 0, 0 }, + { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", ICLASS_xt_iclass_rsr_depc, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", ICLASS_xt_iclass_wsr_depc, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", ICLASS_xt_iclass_xsr_depc, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, + 0, + Opcode_rsr_misc0_encode_fns, 0, 0 }, + { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, + 0, + Opcode_wsr_misc0_encode_fns, 0, 0 }, + { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, + 0, + Opcode_xsr_misc0_encode_fns, 0, 0 }, + { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, + 0, + Opcode_rsr_misc1_encode_fns, 0, 0 }, + { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, + 0, + Opcode_wsr_misc1_encode_fns, 0, 0 }, + { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, + 0, + Opcode_xsr_misc1_encode_fns, 0, 0 }, + { "rsr.misc2", ICLASS_xt_iclass_rsr_misc2, + 0, + Opcode_rsr_misc2_encode_fns, 0, 0 }, + { "wsr.misc2", ICLASS_xt_iclass_wsr_misc2, + 0, + Opcode_wsr_misc2_encode_fns, 0, 0 }, + { "xsr.misc2", ICLASS_xt_iclass_xsr_misc2, + 0, + Opcode_xsr_misc2_encode_fns, 0, 0 }, + { "rsr.misc3", ICLASS_xt_iclass_rsr_misc3, + 0, + Opcode_rsr_misc3_encode_fns, 0, 0 }, + { "wsr.misc3", ICLASS_xt_iclass_wsr_misc3, + 0, + Opcode_wsr_misc3_encode_fns, 0, 0 }, + { "xsr.misc3", ICLASS_xt_iclass_xsr_misc3, + 0, + Opcode_xsr_misc3_encode_fns, 0, 0 }, + { "rsr.prid", ICLASS_xt_iclass_rsr_prid, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, + 0, + Opcode_rsr_vecbase_encode_fns, 0, 0 }, + { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, + 0, + Opcode_wsr_vecbase_encode_fns, 0, 0 }, + { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, + 0, + Opcode_xsr_vecbase_encode_fns, 0, 0 }, + { "rsr.mpucfg", ICLASS_xt_iclass_rsr_mpucfg, + 0, + Opcode_rsr_mpucfg_encode_fns, 0, 0 }, + { "wsr.mpucfg", ICLASS_xt_iclass_wsr_mpucfg, + 0, + Opcode_wsr_mpucfg_encode_fns, 0, 0 }, + { "salt", ICLASS_xt_iclass_salt, + 0, + Opcode_salt_encode_fns, 0, 0 }, + { "saltu", ICLASS_xt_iclass_salt, + 0, + Opcode_saltu_encode_fns, 0, 0 }, + { "rsr.opmode", ICLASS_xt_iclass_rsr_opmode, + 0, + Opcode_rsr_opmode_encode_fns, 0, 0 }, + { "wsr.opmode", ICLASS_xt_iclass_wsr_opmode, + 0, + Opcode_wsr_opmode_encode_fns, 0, 0 }, + { "xsr.opmode", ICLASS_xt_iclass_xsr_opmode, + 0, + Opcode_xsr_opmode_encode_fns, 0, 0 }, + { "mul16s", ICLASS_xt_mul16, + 0, + Opcode_mul16s_encode_fns, 0, 0 }, + { "mul16u", ICLASS_xt_mul16, + 0, + Opcode_mul16u_encode_fns, 0, 0 }, + { "mull", ICLASS_xt_mul32, + 0, + Opcode_mull_encode_fns, 0, 0 }, + { "rfi", ICLASS_xt_iclass_rfi, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", ICLASS_xt_iclass_wait, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", ICLASS_xt_iclass_wsr_intset, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", ICLASS_xt_iclass_break, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", ICLASS_xt_iclass_break_n, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, + 0, + Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, + { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, + 0, + Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, + { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, + 0, + Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, + { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, + 0, + Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, + { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, + 0, + Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, + { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, + 0, + Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, + { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, + 0, + Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, + { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, + 0, + Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, + { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, + 0, + Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, + { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, + 0, + Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, + { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, + 0, + Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, + { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, + 0, + Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, + { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, + 0, + Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, + { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, + 0, + Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, + { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, + 0, + Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, + { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, + 0, + Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, + { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, + 0, + Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, + { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, + 0, + Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, + { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, + 0, + Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, + { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, + 0, + Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, + { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, + 0, + Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, + { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", ICLASS_xt_iclass_rsr_icount, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", ICLASS_xt_iclass_wsr_icount, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", ICLASS_xt_iclass_xsr_icount, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "lddr32.p", ICLASS_xt_iclass_lddr32_p, + 0, + Opcode_lddr32_p_encode_fns, 1, Opcode_lddr32_p_funcUnit_uses }, + { "sddr32.p", ICLASS_xt_iclass_sddr32_p, + 0, + Opcode_sddr32_p_encode_fns, 1, Opcode_sddr32_p_funcUnit_uses }, + { "rfdo", ICLASS_xt_iclass_rfdo, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", ICLASS_xt_iclass_rfdd, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, + 0, + Opcode_wsr_mmid_encode_fns, 0, 0 }, + { "andb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andb_encode_fns, 0, 0 }, + { "andbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andbc_encode_fns, 0, 0 }, + { "orb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orb_encode_fns, 0, 0 }, + { "orbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orbc_encode_fns, 0, 0 }, + { "xorb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_xorb_encode_fns, 0, 0 }, + { "all4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_all4_encode_fns, 0, 0 }, + { "any4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_any4_encode_fns, 0, 0 }, + { "all8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_all8_encode_fns, 0, 0 }, + { "any8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_any8_encode_fns, 0, 0 }, + { "bf", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bf_encode_fns, 0, 0 }, + { "bt", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bt_encode_fns, 0, 0 }, + { "movf", ICLASS_xt_iclass_bmove, + 0, + Opcode_movf_encode_fns, 0, 0 }, + { "movt", ICLASS_xt_iclass_bmove, + 0, + Opcode_movt_encode_fns, 0, 0 }, + { "rsr.br", ICLASS_xt_iclass_RSR_BR, + 0, + Opcode_rsr_br_encode_fns, 0, 0 }, + { "wsr.br", ICLASS_xt_iclass_WSR_BR, + 0, + Opcode_wsr_br_encode_fns, 0, 0 }, + { "xsr.br", ICLASS_xt_iclass_XSR_BR, + 0, + Opcode_xsr_br_encode_fns, 0, 0 }, + { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, + 0, + Opcode_rsr_ccompare1_encode_fns, 0, 0 }, + { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, + 0, + Opcode_wsr_ccompare1_encode_fns, 0, 0 }, + { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, + 0, + Opcode_xsr_ccompare1_encode_fns, 0, 0 }, + { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, + 0, + Opcode_rsr_ccompare2_encode_fns, 0, 0 }, + { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, + 0, + Opcode_wsr_ccompare2_encode_fns, 0, 0 }, + { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, + 0, + Opcode_xsr_ccompare2_encode_fns, 0, 0 }, + { "ihi", ICLASS_xt_iclass_icache, + 0, + Opcode_ihi_encode_fns, 0, 0 }, + { "ipf", ICLASS_xt_iclass_icache, + 0, + Opcode_ipf_encode_fns, 0, 0 }, + { "ihu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ihu_encode_fns, 0, 0 }, + { "iiu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_iiu_encode_fns, 0, 0 }, + { "ipfl", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ipfl_encode_fns, 0, 0 }, + { "iii", ICLASS_xt_iclass_icache_inv, + 0, + Opcode_iii_encode_fns, 0, 0 }, + { "lict", ICLASS_xt_iclass_licx, + 0, + Opcode_lict_encode_fns, 1, Opcode_lict_funcUnit_uses }, + { "licw", ICLASS_xt_iclass_licx, + 0, + Opcode_licw_encode_fns, 1, Opcode_licw_funcUnit_uses }, + { "sict", ICLASS_xt_iclass_sicx, + 0, + Opcode_sict_encode_fns, 1, Opcode_sict_funcUnit_uses }, + { "sicw", ICLASS_xt_iclass_sicx, + 0, + Opcode_sicw_encode_fns, 1, Opcode_sicw_funcUnit_uses }, + { "dhwb", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwb_encode_fns, 0, 0 }, + { "dhwbi", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwbi_encode_fns, 0, 0 }, + { "diwbui.p", ICLASS_xt_iclass_dcache_dyn, + 0, + Opcode_diwbui_p_encode_fns, 0, 0 }, + { "diwb", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwb_encode_fns, 0, 0 }, + { "diwbi", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwbi_encode_fns, 0, 0 }, + { "dhi", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dhi_encode_fns, 0, 0 }, + { "dii", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dii_encode_fns, 0, 0 }, + { "dpfr", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfr_encode_fns, 0, 0 }, + { "dpfro", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfro_encode_fns, 0, 0 }, + { "dpfw", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfw_encode_fns, 0, 0 }, + { "dpfwo", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfwo_encode_fns, 0, 0 }, + { "dhu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dhu_encode_fns, 0, 0 }, + { "diu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_diu_encode_fns, 0, 0 }, + { "dpfl", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dpfl_encode_fns, 0, 0 }, + { "sdct", ICLASS_xt_iclass_sdct, + 0, + Opcode_sdct_encode_fns, 1, Opcode_sdct_funcUnit_uses }, + { "ldct", ICLASS_xt_iclass_ldct, + 0, + Opcode_ldct_encode_fns, 1, Opcode_ldct_funcUnit_uses }, + { "sdcw", ICLASS_xt_iclass_sdcw, + 0, + Opcode_sdcw_encode_fns, 1, Opcode_sdcw_funcUnit_uses }, + { "ldcw", ICLASS_xt_iclass_ldcw, + 0, + Opcode_ldcw_encode_fns, 1, Opcode_ldcw_funcUnit_uses }, + { "rsr.prefctl", ICLASS_xt_iclass_rsr_prefctl, + 0, + Opcode_rsr_prefctl_encode_fns, 0, 0 }, + { "wsr.prefctl", ICLASS_xt_iclass_wsr_prefctl, + 0, + Opcode_wsr_prefctl_encode_fns, 0, 0 }, + { "xsr.prefctl", ICLASS_xt_iclass_xsr_prefctl, + 0, + Opcode_xsr_prefctl_encode_fns, 0, 0 }, + { "wsr.cacheadrdis", ICLASS_xt_iclass_wsr_cacheadrdis, + 0, + Opcode_wsr_cacheadrdis_encode_fns, 0, 0 }, + { "rsr.cacheadrdis", ICLASS_xt_iclass_rsr_cacheadrdis, + 0, + Opcode_rsr_cacheadrdis_encode_fns, 0, 0 }, + { "xsr.cacheadrdis", ICLASS_xt_iclass_xsr_cacheadrdis, + 0, + Opcode_xsr_cacheadrdis_encode_fns, 0, 0 }, + { "rptlb0", ICLASS_xt_iclass_rptlb0, + 0, + Opcode_rptlb0_encode_fns, 0, 0 }, + { "pptlb", ICLASS_xt_iclass_rptlb, + 0, + Opcode_pptlb_encode_fns, 0, 0 }, + { "rptlb1", ICLASS_xt_iclass_rptlb, + 0, + Opcode_rptlb1_encode_fns, 0, 0 }, + { "wptlb", ICLASS_xt_iclass_wptlb, + 0, + Opcode_wptlb_encode_fns, 0, 0 }, + { "rsr.mpuenb", ICLASS_xt_iclass_rsr_mpuenb, + 0, + Opcode_rsr_mpuenb_encode_fns, 0, 0 }, + { "wsr.mpuenb", ICLASS_xt_iclass_wsr_mpuenb, + 0, + Opcode_wsr_mpuenb_encode_fns, 0, 0 }, + { "xsr.mpuenb", ICLASS_xt_iclass_xsr_mpuenb, + 0, + Opcode_xsr_mpuenb_encode_fns, 0, 0 }, + { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, + 0, + Opcode_rsr_cpenable_encode_fns, 0, 0 }, + { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, + 0, + Opcode_wsr_cpenable_encode_fns, 0, 0 }, + { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, + 0, + Opcode_xsr_cpenable_encode_fns, 0, 0 }, + { "clamps", ICLASS_xt_iclass_clamp, + 0, + Opcode_clamps_encode_fns, 0, 0 }, + { "max", ICLASS_xt_iclass_minmax, + 0, + Opcode_max_encode_fns, 0, 0 }, + { "maxu", ICLASS_xt_iclass_minmax, + 0, + Opcode_maxu_encode_fns, 0, 0 }, + { "min", ICLASS_xt_iclass_minmax, + 0, + Opcode_min_encode_fns, 0, 0 }, + { "minu", ICLASS_xt_iclass_minmax, + 0, + Opcode_minu_encode_fns, 0, 0 }, + { "nsa", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsau_encode_fns, 0, 0 }, + { "sext", ICLASS_xt_iclass_sx, + 0, + Opcode_sext_encode_fns, 0, 0 }, + { "l32ai", ICLASS_xt_iclass_l32ai, + 0, + Opcode_l32ai_encode_fns, 1, Opcode_l32ai_funcUnit_uses }, + { "s32ri", ICLASS_xt_iclass_s32ri, + 0, + Opcode_s32ri_encode_fns, 1, Opcode_s32ri_funcUnit_uses }, + { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, + 0, + Opcode_rsr_atomctl_encode_fns, 0, 0 }, + { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, + 0, + Opcode_wsr_atomctl_encode_fns, 0, 0 }, + { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, + 0, + Opcode_xsr_atomctl_encode_fns, 0, 0 }, + { "quos", ICLASS_xt_iclass_div, + 0, + Opcode_quos_encode_fns, 0, 0 }, + { "quou", ICLASS_xt_iclass_div, + 0, + Opcode_quou_encode_fns, 0, 0 }, + { "rems", ICLASS_xt_iclass_div, + 0, + Opcode_rems_encode_fns, 0, 0 }, + { "remu", ICLASS_xt_iclass_div, + 0, + Opcode_remu_encode_fns, 0, 0 }, + { "rsr.eraccess", ICLASS_xt_iclass_rsr_eraccess, + 0, + Opcode_rsr_eraccess_encode_fns, 0, 0 }, + { "wsr.eraccess", ICLASS_xt_iclass_wsr_eraccess, + 0, + Opcode_wsr_eraccess_encode_fns, 0, 0 }, + { "xsr.eraccess", ICLASS_xt_iclass_xsr_eraccess, + 0, + Opcode_xsr_eraccess_encode_fns, 0, 0 }, + { "rer", ICLASS_xt_iclass_rer, + 0, + Opcode_rer_encode_fns, 0, 0 }, + { "wer", ICLASS_xt_iclass_wer, + 0, + Opcode_wer_encode_fns, 0, 0 }, + { "beqz.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_w15_encode_fns, 0, 0 }, + { "bgez.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_w15_encode_fns, 0, 0 }, + { "bltz.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_w15_encode_fns, 0, 0 }, + { "bnez.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_w15_encode_fns, 0, 0 }, + { "beqi.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_w15_encode_fns, 0, 0 }, + { "bgei.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_w15_encode_fns, 0, 0 }, + { "blti.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_w15_encode_fns, 0, 0 }, + { "bnei.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_w15_encode_fns, 0, 0 }, + { "bgeui.w15", ICLASS_xt_iclass_wb15_2, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_w15_encode_fns, 0, 0 }, + { "bltui.w15", ICLASS_xt_iclass_wb15_2, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_w15_encode_fns, 0, 0 }, + { "bbci.w15", ICLASS_xt_iclass_wb15_3, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_w15_encode_fns, 0, 0 }, + { "bbsi.w15", ICLASS_xt_iclass_wb15_3, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_w15_encode_fns, 0, 0 }, + { "ball.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_w15_encode_fns, 0, 0 }, + { "bany.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_w15_encode_fns, 0, 0 }, + { "bbc.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_w15_encode_fns, 0, 0 }, + { "bbs.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_w15_encode_fns, 0, 0 }, + { "beq.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_w15_encode_fns, 0, 0 }, + { "bgeu.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_w15_encode_fns, 0, 0 }, + { "bge.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_w15_encode_fns, 0, 0 }, + { "bltu.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_w15_encode_fns, 0, 0 }, + { "blt.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_w15_encode_fns, 0, 0 }, + { "bnall.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_w15_encode_fns, 0, 0 }, + { "bne.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_w15_encode_fns, 0, 0 }, + { "bnone.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_w15_encode_fns, 0, 0 }, + { "ae_sext16", ICLASS_ic_sext16, + 0, + Opcode_ae_sext16_encode_fns, 0, 0 }, + { "ae_zext16", ICLASS_ic_zext16, + 0, + Opcode_ae_zext16_encode_fns, 0, 0 }, + { "ae_zext8", ICLASS_ic_zext8, + 0, + Opcode_ae_zext8_encode_fns, 0, 0 }, + { "ae_clamps16", ICLASS_ic_clamps16, + 0, + Opcode_ae_clamps16_encode_fns, 0, 0 }, + { "rur.fcr", ICLASS_rur_fcr, + 0, + Opcode_rur_fcr_encode_fns, 0, 0 }, + { "wur.fcr", ICLASS_wur_fcr, + 0, + Opcode_wur_fcr_encode_fns, 0, 0 }, + { "rur.fsr", ICLASS_rur_fsr, + 0, + Opcode_rur_fsr_encode_fns, 0, 0 }, + { "wur.fsr", ICLASS_wur_fsr, + 0, + Opcode_wur_fsr_encode_fns, 0, 0 }, + { "read_impwire", ICLASS_iclass_READ_IMPWIRE, + 0, + Opcode_read_impwire_encode_fns, 0, 0 }, + { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, + 0, + Opcode_setb_expstate_encode_fns, 0, 0 }, + { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, + 0, + Opcode_clrb_expstate_encode_fns, 0, 0 }, + { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, + 0, + Opcode_wrmsk_expstate_encode_fns, 0, 0 }, + { "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar, + 0, + Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 }, + { "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar, + 0, + Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 }, + { "rur.ae_bithead", ICLASS_rur_ae_bithead, + 0, + Opcode_rur_ae_bithead_encode_fns, 0, 0 }, + { "wur.ae_bithead", ICLASS_wur_ae_bithead, + 0, + Opcode_wur_ae_bithead_encode_fns, 0, 0 }, + { "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp, + 0, + Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, + { "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp, + 0, + Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, + { "rur.ae_cw_sd_no", ICLASS_rur_ae_cw_sd_no, + 0, + Opcode_rur_ae_cw_sd_no_encode_fns, 0, 0 }, + { "wur.ae_cw_sd_no", ICLASS_wur_ae_cw_sd_no, + 0, + Opcode_wur_ae_cw_sd_no_encode_fns, 0, 0 }, + { "rur.ae_cbegin0", ICLASS_rur_ae_cbegin0, + 0, + Opcode_rur_ae_cbegin0_encode_fns, 0, 0 }, + { "wur.ae_cbegin0", ICLASS_wur_ae_cbegin0, + 0, + Opcode_wur_ae_cbegin0_encode_fns, 0, 0 }, + { "rur.ae_cend0", ICLASS_rur_ae_cend0, + 0, + Opcode_rur_ae_cend0_encode_fns, 0, 0 }, + { "wur.ae_cend0", ICLASS_wur_ae_cend0, + 0, + Opcode_wur_ae_cend0_encode_fns, 0, 0 }, + { "rur.ae_cbegin1", ICLASS_rur_ae_cbegin1, + 0, + Opcode_rur_ae_cbegin1_encode_fns, 0, 0 }, + { "wur.ae_cbegin1", ICLASS_wur_ae_cbegin1, + 0, + Opcode_wur_ae_cbegin1_encode_fns, 0, 0 }, + { "rur.ae_cend1", ICLASS_rur_ae_cend1, + 0, + Opcode_rur_ae_cend1_encode_fns, 0, 0 }, + { "wur.ae_cend1", ICLASS_wur_ae_cend1, + 0, + Opcode_wur_ae_cend1_encode_fns, 0, 0 }, + { "rur.ae_cbegin2", ICLASS_rur_ae_cbegin2, + 0, + Opcode_rur_ae_cbegin2_encode_fns, 0, 0 }, + { "wur.ae_cbegin2", ICLASS_wur_ae_cbegin2, + 0, + Opcode_wur_ae_cbegin2_encode_fns, 0, 0 }, + { "rur.ae_cend2", ICLASS_rur_ae_cend2, + 0, + Opcode_rur_ae_cend2_encode_fns, 0, 0 }, + { "wur.ae_cend2", ICLASS_wur_ae_cend2, + 0, + Opcode_wur_ae_cend2_encode_fns, 0, 0 }, + { "rur.expstate", ICLASS_rur_expstate, + 0, + Opcode_rur_expstate_encode_fns, 0, 0 }, + { "wur.expstate", ICLASS_wur_expstate, + 0, + Opcode_wur_expstate_encode_fns, 0, 0 }, + { "rur.ae_overflow", ICLASS_RUR_AE_OVERFLOW, + 0, + Opcode_rur_ae_overflow_encode_fns, 0, 0 }, + { "wur.ae_overflow", ICLASS_WUR_AE_OVERFLOW, + 0, + Opcode_wur_ae_overflow_encode_fns, 0, 0 }, + { "rur.ae_sar", ICLASS_RUR_AE_SAR, + 0, + Opcode_rur_ae_sar_encode_fns, 0, 0 }, + { "wur.ae_sar", ICLASS_WUR_AE_SAR, + 0, + Opcode_wur_ae_sar_encode_fns, 0, 0 }, + { "rur.ae_bitptr", ICLASS_RUR_AE_BITPTR, + 0, + Opcode_rur_ae_bitptr_encode_fns, 0, 0 }, + { "wur.ae_bitptr", ICLASS_WUR_AE_BITPTR, + 0, + Opcode_wur_ae_bitptr_encode_fns, 0, 0 }, + { "rur.ae_bitsused", ICLASS_RUR_AE_BITSUSED, + 0, + Opcode_rur_ae_bitsused_encode_fns, 0, 0 }, + { "wur.ae_bitsused", ICLASS_WUR_AE_BITSUSED, + 0, + Opcode_wur_ae_bitsused_encode_fns, 0, 0 }, + { "rur.ae_tablesize", ICLASS_RUR_AE_TABLESIZE, + 0, + Opcode_rur_ae_tablesize_encode_fns, 0, 0 }, + { "wur.ae_tablesize", ICLASS_WUR_AE_TABLESIZE, + 0, + Opcode_wur_ae_tablesize_encode_fns, 0, 0 }, + { "rur.ae_first_ts", ICLASS_RUR_AE_FIRST_TS, + 0, + Opcode_rur_ae_first_ts_encode_fns, 0, 0 }, + { "wur.ae_first_ts", ICLASS_WUR_AE_FIRST_TS, + 0, + Opcode_wur_ae_first_ts_encode_fns, 0, 0 }, + { "rur.ae_nextoffset", ICLASS_RUR_AE_NEXTOFFSET, + 0, + Opcode_rur_ae_nextoffset_encode_fns, 0, 0 }, + { "wur.ae_nextoffset", ICLASS_WUR_AE_NEXTOFFSET, + 0, + Opcode_wur_ae_nextoffset_encode_fns, 0, 0 }, + { "rur.ae_searchdone", ICLASS_RUR_AE_SEARCHDONE, + 0, + Opcode_rur_ae_searchdone_encode_fns, 0, 0 }, + { "wur.ae_searchdone", ICLASS_WUR_AE_SEARCHDONE, + 0, + Opcode_wur_ae_searchdone_encode_fns, 0, 0 }, + { "rur.ae_cwrap", ICLASS_RUR_AE_CWRAP, + 0, + Opcode_rur_ae_cwrap_encode_fns, 0, 0 }, + { "wur.ae_cwrap", ICLASS_WUR_AE_CWRAP, + 0, + Opcode_wur_ae_cwrap_encode_fns, 0, 0 }, + { "ae_l8x4f.i", ICLASS_AE_L8X4F_I, + 0, + Opcode_ae_l8x4f_i_encode_fns, 1, Opcode_ae_l8x4f_i_funcUnit_uses }, + { "ae_l8x4f.ip", ICLASS_AE_L8X4F_IP, + 0, + Opcode_ae_l8x4f_ip_encode_fns, 1, Opcode_ae_l8x4f_ip_funcUnit_uses }, + { "ae_l8x4f.x", ICLASS_AE_L8X4F_X, + 0, + Opcode_ae_l8x4f_x_encode_fns, 1, Opcode_ae_l8x4f_x_funcUnit_uses }, + { "ae_l8x4f.xp", ICLASS_AE_L8X4F_XP, + 0, + Opcode_ae_l8x4f_xp_encode_fns, 1, Opcode_ae_l8x4f_xp_funcUnit_uses }, + { "ae_l8x4s.i", ICLASS_AE_L8X4S_I, + 0, + Opcode_ae_l8x4s_i_encode_fns, 1, Opcode_ae_l8x4s_i_funcUnit_uses }, + { "ae_l8x4s.ip", ICLASS_AE_L8X4S_IP, + 0, + Opcode_ae_l8x4s_ip_encode_fns, 1, Opcode_ae_l8x4s_ip_funcUnit_uses }, + { "ae_l8x4s.x", ICLASS_AE_L8X4S_X, + 0, + Opcode_ae_l8x4s_x_encode_fns, 1, Opcode_ae_l8x4s_x_funcUnit_uses }, + { "ae_l8x4s.xp", ICLASS_AE_L8X4S_XP, + 0, + Opcode_ae_l8x4s_xp_encode_fns, 1, Opcode_ae_l8x4s_xp_funcUnit_uses }, + { "ae_l8x4u.i", ICLASS_AE_L8X4U_I, + 0, + Opcode_ae_l8x4u_i_encode_fns, 1, Opcode_ae_l8x4u_i_funcUnit_uses }, + { "ae_l8x4u.ip", ICLASS_AE_L8X4U_IP, + 0, + Opcode_ae_l8x4u_ip_encode_fns, 1, Opcode_ae_l8x4u_ip_funcUnit_uses }, + { "ae_l8x4u.x", ICLASS_AE_L8X4U_X, + 0, + Opcode_ae_l8x4u_x_encode_fns, 1, Opcode_ae_l8x4u_x_funcUnit_uses }, + { "ae_l8x4u.xp", ICLASS_AE_L8X4U_XP, + 0, + Opcode_ae_l8x4u_xp_encode_fns, 1, Opcode_ae_l8x4u_xp_funcUnit_uses }, + { "ae_s8x4u.i", ICLASS_AE_S8X4U_I, + 0, + Opcode_ae_s8x4u_i_encode_fns, 1, Opcode_ae_s8x4u_i_funcUnit_uses }, + { "ae_s8x4u.ip", ICLASS_AE_S8X4U_IP, + 0, + Opcode_ae_s8x4u_ip_encode_fns, 1, Opcode_ae_s8x4u_ip_funcUnit_uses }, + { "ae_s8x4u.x", ICLASS_AE_S8X4U_X, + 0, + Opcode_ae_s8x4u_x_encode_fns, 1, Opcode_ae_s8x4u_x_funcUnit_uses }, + { "ae_s8x4u.xp", ICLASS_AE_S8X4U_XP, + 0, + Opcode_ae_s8x4u_xp_encode_fns, 1, Opcode_ae_s8x4u_xp_funcUnit_uses }, + { "ae_l16m.xc", ICLASS_AE_L16M_XC, + 0, + Opcode_ae_l16m_xc_encode_fns, 1, Opcode_ae_l16m_xc_funcUnit_uses }, + { "ae_l16m.xc1", ICLASS_AE_L16M_XC1, + 0, + Opcode_ae_l16m_xc1_encode_fns, 1, Opcode_ae_l16m_xc1_funcUnit_uses }, + { "ae_l16m.i", ICLASS_AE_L16M_I, + 0, + Opcode_ae_l16m_i_encode_fns, 1, Opcode_ae_l16m_i_funcUnit_uses }, + { "ae_l16m.iu", ICLASS_AE_L16M_IU, + 0, + Opcode_ae_l16m_iu_encode_fns, 1, Opcode_ae_l16m_iu_funcUnit_uses }, + { "ae_l16m.x", ICLASS_AE_L16M_X, + 0, + Opcode_ae_l16m_x_encode_fns, 1, Opcode_ae_l16m_x_funcUnit_uses }, + { "ae_l16m.xu", ICLASS_AE_L16M_XU, + 0, + Opcode_ae_l16m_xu_encode_fns, 1, Opcode_ae_l16m_xu_funcUnit_uses }, + { "ae_l16.xc", ICLASS_AE_L16_XC, + 0, + Opcode_ae_l16_xc_encode_fns, 1, Opcode_ae_l16_xc_funcUnit_uses }, + { "ae_l16.xc1", ICLASS_AE_L16_XC1, + 0, + Opcode_ae_l16_xc1_encode_fns, 1, Opcode_ae_l16_xc1_funcUnit_uses }, + { "ae_l16.i", ICLASS_AE_L16_I, + 0, + Opcode_ae_l16_i_encode_fns, 1, Opcode_ae_l16_i_funcUnit_uses }, + { "ae_l16.ip", ICLASS_AE_L16_IP, + 0, + Opcode_ae_l16_ip_encode_fns, 1, Opcode_ae_l16_ip_funcUnit_uses }, + { "ae_l16.x", ICLASS_AE_L16_X, + 0, + Opcode_ae_l16_x_encode_fns, 1, Opcode_ae_l16_x_funcUnit_uses }, + { "ae_l16.xp", ICLASS_AE_L16_XP, + 0, + Opcode_ae_l16_xp_encode_fns, 1, Opcode_ae_l16_xp_funcUnit_uses }, + { "ae_l8.xc", ICLASS_AE_L8_XC, + 0, + Opcode_ae_l8_xc_encode_fns, 1, Opcode_ae_l8_xc_funcUnit_uses }, + { "ae_l8.xc1", ICLASS_AE_L8_XC1, + 0, + Opcode_ae_l8_xc1_encode_fns, 1, Opcode_ae_l8_xc1_funcUnit_uses }, + { "ae_l8.i", ICLASS_AE_L8_I, + 0, + Opcode_ae_l8_i_encode_fns, 1, Opcode_ae_l8_i_funcUnit_uses }, + { "ae_l8.ip", ICLASS_AE_L8_IP, + 0, + Opcode_ae_l8_ip_encode_fns, 1, Opcode_ae_l8_ip_funcUnit_uses }, + { "ae_l8.x", ICLASS_AE_L8_X, + 0, + Opcode_ae_l8_x_encode_fns, 1, Opcode_ae_l8_x_funcUnit_uses }, + { "ae_l8.xp", ICLASS_AE_L8_XP, + 0, + Opcode_ae_l8_xp_encode_fns, 1, Opcode_ae_l8_xp_funcUnit_uses }, + { "ae_l32f24.xc", ICLASS_AE_L32F24_XC, + 0, + Opcode_ae_l32f24_xc_encode_fns, 1, Opcode_ae_l32f24_xc_funcUnit_uses }, + { "ae_l32f24.xc1", ICLASS_AE_L32F24_XC1, + 0, + Opcode_ae_l32f24_xc1_encode_fns, 1, Opcode_ae_l32f24_xc1_funcUnit_uses }, + { "ae_l32f24.i", ICLASS_AE_L32F24_I, + 0, + Opcode_ae_l32f24_i_encode_fns, 1, Opcode_ae_l32f24_i_funcUnit_uses }, + { "ae_l32f24.ip", ICLASS_AE_L32F24_IP, + 0, + Opcode_ae_l32f24_ip_encode_fns, 1, Opcode_ae_l32f24_ip_funcUnit_uses }, + { "ae_l32f24.x", ICLASS_AE_L32F24_X, + 0, + Opcode_ae_l32f24_x_encode_fns, 1, Opcode_ae_l32f24_x_funcUnit_uses }, + { "ae_l32f24.xp", ICLASS_AE_L32F24_XP, + 0, + Opcode_ae_l32f24_xp_encode_fns, 1, Opcode_ae_l32f24_xp_funcUnit_uses }, + { "ae_l32.xc", ICLASS_AE_L32_XC, + 0, + Opcode_ae_l32_xc_encode_fns, 1, Opcode_ae_l32_xc_funcUnit_uses }, + { "ae_l32.xc1", ICLASS_AE_L32_XC1, + 0, + Opcode_ae_l32_xc1_encode_fns, 1, Opcode_ae_l32_xc1_funcUnit_uses }, + { "ae_l32.i", ICLASS_AE_L32_I, + 0, + Opcode_ae_l32_i_encode_fns, 1, Opcode_ae_l32_i_funcUnit_uses }, + { "ae_l32.ip", ICLASS_AE_L32_IP, + 0, + Opcode_ae_l32_ip_encode_fns, 1, Opcode_ae_l32_ip_funcUnit_uses }, + { "ae_l32.x", ICLASS_AE_L32_X, + 0, + Opcode_ae_l32_x_encode_fns, 1, Opcode_ae_l32_x_funcUnit_uses }, + { "ae_l32.xp", ICLASS_AE_L32_XP, + 0, + Opcode_ae_l32_xp_encode_fns, 1, Opcode_ae_l32_xp_funcUnit_uses }, + { "ae_l32m.xc", ICLASS_AE_L32M_XC, + 0, + Opcode_ae_l32m_xc_encode_fns, 1, Opcode_ae_l32m_xc_funcUnit_uses }, + { "ae_l32m.i", ICLASS_AE_L32M_I, + 0, + Opcode_ae_l32m_i_encode_fns, 1, Opcode_ae_l32m_i_funcUnit_uses }, + { "ae_l32m.iu", ICLASS_AE_L32M_IU, + 0, + Opcode_ae_l32m_iu_encode_fns, 1, Opcode_ae_l32m_iu_funcUnit_uses }, + { "ae_l32m.x", ICLASS_AE_L32M_X, + 0, + Opcode_ae_l32m_x_encode_fns, 1, Opcode_ae_l32m_x_funcUnit_uses }, + { "ae_l32m.xu", ICLASS_AE_L32M_XU, + 0, + Opcode_ae_l32m_xu_encode_fns, 1, Opcode_ae_l32m_xu_funcUnit_uses }, + { "ae_l16x2m.xc", ICLASS_AE_L16X2M_XC, + 0, + Opcode_ae_l16x2m_xc_encode_fns, 1, Opcode_ae_l16x2m_xc_funcUnit_uses }, + { "ae_l16x2m.xc1", ICLASS_AE_L16X2M_XC1, + 0, + Opcode_ae_l16x2m_xc1_encode_fns, 1, Opcode_ae_l16x2m_xc1_funcUnit_uses }, + { "ae_l16x2m.i", ICLASS_AE_L16X2M_I, + 0, + Opcode_ae_l16x2m_i_encode_fns, 1, Opcode_ae_l16x2m_i_funcUnit_uses }, + { "ae_l16x2m.iu", ICLASS_AE_L16X2M_IU, + 0, + Opcode_ae_l16x2m_iu_encode_fns, 1, Opcode_ae_l16x2m_iu_funcUnit_uses }, + { "ae_l16x2m.x", ICLASS_AE_L16X2M_X, + 0, + Opcode_ae_l16x2m_x_encode_fns, 1, Opcode_ae_l16x2m_x_funcUnit_uses }, + { "ae_l16x2m.xu", ICLASS_AE_L16X2M_XU, + 0, + Opcode_ae_l16x2m_xu_encode_fns, 1, Opcode_ae_l16x2m_xu_funcUnit_uses }, + { "ae_l32x2f24.xc", ICLASS_AE_L32X2F24_XC, + 0, + Opcode_ae_l32x2f24_xc_encode_fns, 1, Opcode_ae_l32x2f24_xc_funcUnit_uses }, + { "ae_l32x2f24.xc1", ICLASS_AE_L32X2F24_XC1, + 0, + Opcode_ae_l32x2f24_xc1_encode_fns, 1, Opcode_ae_l32x2f24_xc1_funcUnit_uses }, + { "ae_l32x2f24.i", ICLASS_AE_L32X2F24_I, + 0, + Opcode_ae_l32x2f24_i_encode_fns, 1, Opcode_ae_l32x2f24_i_funcUnit_uses }, + { "ae_l32x2f24.ip", ICLASS_AE_L32X2F24_IP, + 0, + Opcode_ae_l32x2f24_ip_encode_fns, 1, Opcode_ae_l32x2f24_ip_funcUnit_uses }, + { "ae_l32x2f24.rip", ICLASS_AE_L32X2F24_RIP, + 0, + Opcode_ae_l32x2f24_rip_encode_fns, 1, Opcode_ae_l32x2f24_rip_funcUnit_uses }, + { "ae_l32x2f24.ri", ICLASS_AE_L32X2F24_RI, + 0, + Opcode_ae_l32x2f24_ri_encode_fns, 1, Opcode_ae_l32x2f24_ri_funcUnit_uses }, + { "ae_l32x2f24.ric", ICLASS_AE_L32X2F24_RIC, + 0, + Opcode_ae_l32x2f24_ric_encode_fns, 1, Opcode_ae_l32x2f24_ric_funcUnit_uses }, + { "ae_l32x2f24.ric1", ICLASS_AE_L32X2F24_RIC1, + 0, + Opcode_ae_l32x2f24_ric1_encode_fns, 1, Opcode_ae_l32x2f24_ric1_funcUnit_uses }, + { "ae_l32x2f24.x", ICLASS_AE_L32X2F24_X, + 0, + Opcode_ae_l32x2f24_x_encode_fns, 1, Opcode_ae_l32x2f24_x_funcUnit_uses }, + { "ae_l32x2f24.xp", ICLASS_AE_L32X2F24_XP, + 0, + Opcode_ae_l32x2f24_xp_encode_fns, 1, Opcode_ae_l32x2f24_xp_funcUnit_uses }, + { "ae_l32x2.xc", ICLASS_AE_L32X2_XC, + 0, + Opcode_ae_l32x2_xc_encode_fns, 1, Opcode_ae_l32x2_xc_funcUnit_uses }, + { "ae_l32x2.xc1", ICLASS_AE_L32X2_XC1, + 0, + Opcode_ae_l32x2_xc1_encode_fns, 1, Opcode_ae_l32x2_xc1_funcUnit_uses }, + { "ae_l32x2.i", ICLASS_AE_L32X2_I, + 0, + Opcode_ae_l32x2_i_encode_fns, 1, Opcode_ae_l32x2_i_funcUnit_uses }, + { "ae_l32x2.ip", ICLASS_AE_L32X2_IP, + 0, + Opcode_ae_l32x2_ip_encode_fns, 1, Opcode_ae_l32x2_ip_funcUnit_uses }, + { "ae_l32x2.ric", ICLASS_AE_L32X2_RIC, + 0, + Opcode_ae_l32x2_ric_encode_fns, 1, Opcode_ae_l32x2_ric_funcUnit_uses }, + { "ae_l32x2.ric1", ICLASS_AE_L32X2_RIC1, + 0, + Opcode_ae_l32x2_ric1_encode_fns, 1, Opcode_ae_l32x2_ric1_funcUnit_uses }, + { "ae_l32x2.x", ICLASS_AE_L32X2_X, + 0, + Opcode_ae_l32x2_x_encode_fns, 1, Opcode_ae_l32x2_x_funcUnit_uses }, + { "ae_l32x2.xp", ICLASS_AE_L32X2_XP, + 0, + Opcode_ae_l32x2_xp_encode_fns, 1, Opcode_ae_l32x2_xp_funcUnit_uses }, + { "ae_l16x4.xc", ICLASS_AE_L16X4_XC, + 0, + Opcode_ae_l16x4_xc_encode_fns, 1, Opcode_ae_l16x4_xc_funcUnit_uses }, + { "ae_l16x4.xc1", ICLASS_AE_L16X4_XC1, + 0, + Opcode_ae_l16x4_xc1_encode_fns, 1, Opcode_ae_l16x4_xc1_funcUnit_uses }, + { "ae_l16x4.i", ICLASS_AE_L16X4_I, + 0, + Opcode_ae_l16x4_i_encode_fns, 1, Opcode_ae_l16x4_i_funcUnit_uses }, + { "ae_l16x4.ip", ICLASS_AE_L16X4_IP, + 0, + Opcode_ae_l16x4_ip_encode_fns, 1, Opcode_ae_l16x4_ip_funcUnit_uses }, + { "ae_l16x4.x", ICLASS_AE_L16X4_X, + 0, + Opcode_ae_l16x4_x_encode_fns, 1, Opcode_ae_l16x4_x_funcUnit_uses }, + { "ae_l16x4.xp", ICLASS_AE_L16X4_XP, + 0, + Opcode_ae_l16x4_xp_encode_fns, 1, Opcode_ae_l16x4_xp_funcUnit_uses }, + { "ae_l8x8.xc", ICLASS_AE_L8X8_XC, + 0, + Opcode_ae_l8x8_xc_encode_fns, 1, Opcode_ae_l8x8_xc_funcUnit_uses }, + { "ae_l8x8.xc1", ICLASS_AE_L8X8_XC1, + 0, + Opcode_ae_l8x8_xc1_encode_fns, 1, Opcode_ae_l8x8_xc1_funcUnit_uses }, + { "ae_l8x8.i", ICLASS_AE_L8X8_I, + 0, + Opcode_ae_l8x8_i_encode_fns, 1, Opcode_ae_l8x8_i_funcUnit_uses }, + { "ae_l8x8.ip", ICLASS_AE_L8X8_IP, + 0, + Opcode_ae_l8x8_ip_encode_fns, 1, Opcode_ae_l8x8_ip_funcUnit_uses }, + { "ae_l8x8.x", ICLASS_AE_L8X8_X, + 0, + Opcode_ae_l8x8_x_encode_fns, 1, Opcode_ae_l8x8_x_funcUnit_uses }, + { "ae_l8x8.xp", ICLASS_AE_L8X8_XP, + 0, + Opcode_ae_l8x8_xp_encode_fns, 1, Opcode_ae_l8x8_xp_funcUnit_uses }, + { "ae_l64.xc", ICLASS_AE_L64_XC, + 0, + Opcode_ae_l64_xc_encode_fns, 1, Opcode_ae_l64_xc_funcUnit_uses }, + { "ae_l64.xc1", ICLASS_AE_L64_XC1, + 0, + Opcode_ae_l64_xc1_encode_fns, 1, Opcode_ae_l64_xc1_funcUnit_uses }, + { "ae_l64.i", ICLASS_AE_L64_I, + 0, + Opcode_ae_l64_i_encode_fns, 1, Opcode_ae_l64_i_funcUnit_uses }, + { "ae_l64.ip", ICLASS_AE_L64_IP, + 0, + Opcode_ae_l64_ip_encode_fns, 1, Opcode_ae_l64_ip_funcUnit_uses }, + { "ae_l64.x", ICLASS_AE_L64_X, + 0, + Opcode_ae_l64_x_encode_fns, 1, Opcode_ae_l64_x_funcUnit_uses }, + { "ae_l64.xp", ICLASS_AE_L64_XP, + 0, + Opcode_ae_l64_xp_encode_fns, 1, Opcode_ae_l64_xp_funcUnit_uses }, + { "ae_s16x2m.xc", ICLASS_AE_S16X2M_XC, + 0, + Opcode_ae_s16x2m_xc_encode_fns, 1, Opcode_ae_s16x2m_xc_funcUnit_uses }, + { "ae_s16x2m.xc1", ICLASS_AE_S16X2M_XC1, + 0, + Opcode_ae_s16x2m_xc1_encode_fns, 1, Opcode_ae_s16x2m_xc1_funcUnit_uses }, + { "ae_s16x2m.i", ICLASS_AE_S16X2M_I, + 0, + Opcode_ae_s16x2m_i_encode_fns, 1, Opcode_ae_s16x2m_i_funcUnit_uses }, + { "ae_s16x2m.iu", ICLASS_AE_S16X2M_IU, + 0, + Opcode_ae_s16x2m_iu_encode_fns, 1, Opcode_ae_s16x2m_iu_funcUnit_uses }, + { "ae_s16x2m.x", ICLASS_AE_S16X2M_X, + 0, + Opcode_ae_s16x2m_x_encode_fns, 1, Opcode_ae_s16x2m_x_funcUnit_uses }, + { "ae_s16x2m.xu", ICLASS_AE_S16X2M_XU, + 0, + Opcode_ae_s16x2m_xu_encode_fns, 1, Opcode_ae_s16x2m_xu_funcUnit_uses }, + { "ae_s32x2f24.xc", ICLASS_AE_S32X2F24_XC, + 0, + Opcode_ae_s32x2f24_xc_encode_fns, 1, Opcode_ae_s32x2f24_xc_funcUnit_uses }, + { "ae_s32x2f24.xc1", ICLASS_AE_S32X2F24_XC1, + 0, + Opcode_ae_s32x2f24_xc1_encode_fns, 1, Opcode_ae_s32x2f24_xc1_funcUnit_uses }, + { "ae_s32x2f24.i", ICLASS_AE_S32X2F24_I, + 0, + Opcode_ae_s32x2f24_i_encode_fns, 1, Opcode_ae_s32x2f24_i_funcUnit_uses }, + { "ae_s32x2f24.ip", ICLASS_AE_S32X2F24_IP, + 0, + Opcode_ae_s32x2f24_ip_encode_fns, 1, Opcode_ae_s32x2f24_ip_funcUnit_uses }, + { "ae_s32x2f24.rip", ICLASS_AE_S32X2F24_RIP, + 0, + Opcode_ae_s32x2f24_rip_encode_fns, 1, Opcode_ae_s32x2f24_rip_funcUnit_uses }, + { "ae_s32x2f24.ric", ICLASS_AE_S32X2F24_RIC, + 0, + Opcode_ae_s32x2f24_ric_encode_fns, 1, Opcode_ae_s32x2f24_ric_funcUnit_uses }, + { "ae_s32x2f24.ric1", ICLASS_AE_S32X2F24_RIC1, + 0, + Opcode_ae_s32x2f24_ric1_encode_fns, 1, Opcode_ae_s32x2f24_ric1_funcUnit_uses }, + { "ae_s32x2f24.x", ICLASS_AE_S32X2F24_X, + 0, + Opcode_ae_s32x2f24_x_encode_fns, 1, Opcode_ae_s32x2f24_x_funcUnit_uses }, + { "ae_s32x2f24.xp", ICLASS_AE_S32X2F24_XP, + 0, + Opcode_ae_s32x2f24_xp_encode_fns, 1, Opcode_ae_s32x2f24_xp_funcUnit_uses }, + { "ae_s32x2.xc", ICLASS_AE_S32X2_XC, + 0, + Opcode_ae_s32x2_xc_encode_fns, 1, Opcode_ae_s32x2_xc_funcUnit_uses }, + { "ae_s32x2.xc1", ICLASS_AE_S32X2_XC1, + 0, + Opcode_ae_s32x2_xc1_encode_fns, 1, Opcode_ae_s32x2_xc1_funcUnit_uses }, + { "ae_s32x2.i", ICLASS_AE_S32X2_I, + 0, + Opcode_ae_s32x2_i_encode_fns, 1, Opcode_ae_s32x2_i_funcUnit_uses }, + { "ae_s32x2.ip", ICLASS_AE_S32X2_IP, + 0, + Opcode_ae_s32x2_ip_encode_fns, 1, Opcode_ae_s32x2_ip_funcUnit_uses }, + { "ae_s32x2.ric", ICLASS_AE_S32X2_RIC, + 0, + Opcode_ae_s32x2_ric_encode_fns, 1, Opcode_ae_s32x2_ric_funcUnit_uses }, + { "ae_s32x2.ric1", ICLASS_AE_S32X2_RIC1, + 0, + Opcode_ae_s32x2_ric1_encode_fns, 1, Opcode_ae_s32x2_ric1_funcUnit_uses }, + { "ae_s32x2.x", ICLASS_AE_S32X2_X, + 0, + Opcode_ae_s32x2_x_encode_fns, 1, Opcode_ae_s32x2_x_funcUnit_uses }, + { "ae_s32x2.xp", ICLASS_AE_S32X2_XP, + 0, + Opcode_ae_s32x2_xp_encode_fns, 1, Opcode_ae_s32x2_xp_funcUnit_uses }, + { "ae_s32x2rng.i", ICLASS_AE_S32X2RNG_I, + 0, + Opcode_ae_s32x2rng_i_encode_fns, 1, Opcode_ae_s32x2rng_i_funcUnit_uses }, + { "ae_s32x2rng.ip", ICLASS_AE_S32X2RNG_IP, + 0, + Opcode_ae_s32x2rng_ip_encode_fns, 1, Opcode_ae_s32x2rng_ip_funcUnit_uses }, + { "ae_s32x2rng.x", ICLASS_AE_S32X2RNG_X, + 0, + Opcode_ae_s32x2rng_x_encode_fns, 1, Opcode_ae_s32x2rng_x_funcUnit_uses }, + { "ae_s32x2rng.xp", ICLASS_AE_S32X2RNG_XP, + 0, + Opcode_ae_s32x2rng_xp_encode_fns, 1, Opcode_ae_s32x2rng_xp_funcUnit_uses }, + { "ae_s16x4.xc", ICLASS_AE_S16X4_XC, + 0, + Opcode_ae_s16x4_xc_encode_fns, 1, Opcode_ae_s16x4_xc_funcUnit_uses }, + { "ae_s16x4.xc1", ICLASS_AE_S16X4_XC1, + 0, + Opcode_ae_s16x4_xc1_encode_fns, 1, Opcode_ae_s16x4_xc1_funcUnit_uses }, + { "ae_s16x4.i", ICLASS_AE_S16X4_I, + 0, + Opcode_ae_s16x4_i_encode_fns, 1, Opcode_ae_s16x4_i_funcUnit_uses }, + { "ae_s16x4.ip", ICLASS_AE_S16X4_IP, + 0, + Opcode_ae_s16x4_ip_encode_fns, 1, Opcode_ae_s16x4_ip_funcUnit_uses }, + { "ae_s16x4.x", ICLASS_AE_S16X4_X, + 0, + Opcode_ae_s16x4_x_encode_fns, 1, Opcode_ae_s16x4_x_funcUnit_uses }, + { "ae_s16x4.xp", ICLASS_AE_S16X4_XP, + 0, + Opcode_ae_s16x4_xp_encode_fns, 1, Opcode_ae_s16x4_xp_funcUnit_uses }, + { "ae_s8x8.xc", ICLASS_AE_S8X8_XC, + 0, + Opcode_ae_s8x8_xc_encode_fns, 1, Opcode_ae_s8x8_xc_funcUnit_uses }, + { "ae_s8x8.xc1", ICLASS_AE_S8X8_XC1, + 0, + Opcode_ae_s8x8_xc1_encode_fns, 1, Opcode_ae_s8x8_xc1_funcUnit_uses }, + { "ae_s8x8.i", ICLASS_AE_S8X8_I, + 0, + Opcode_ae_s8x8_i_encode_fns, 1, Opcode_ae_s8x8_i_funcUnit_uses }, + { "ae_s8x8.ip", ICLASS_AE_S8X8_IP, + 0, + Opcode_ae_s8x8_ip_encode_fns, 1, Opcode_ae_s8x8_ip_funcUnit_uses }, + { "ae_s8x8.x", ICLASS_AE_S8X8_X, + 0, + Opcode_ae_s8x8_x_encode_fns, 1, Opcode_ae_s8x8_x_funcUnit_uses }, + { "ae_s8x8.xp", ICLASS_AE_S8X8_XP, + 0, + Opcode_ae_s8x8_xp_encode_fns, 1, Opcode_ae_s8x8_xp_funcUnit_uses }, + { "ae_s16m.l.xc", ICLASS_AE_S16M_L_XC, + 0, + Opcode_ae_s16m_l_xc_encode_fns, 1, Opcode_ae_s16m_l_xc_funcUnit_uses }, + { "ae_s16m.l.xc1", ICLASS_AE_S16M_L_XC1, + 0, + Opcode_ae_s16m_l_xc1_encode_fns, 1, Opcode_ae_s16m_l_xc1_funcUnit_uses }, + { "ae_s16m.l.i", ICLASS_AE_S16M_L_I, + 0, + Opcode_ae_s16m_l_i_encode_fns, 1, Opcode_ae_s16m_l_i_funcUnit_uses }, + { "ae_s16m.l.iu", ICLASS_AE_S16M_L_IU, + 0, + Opcode_ae_s16m_l_iu_encode_fns, 1, Opcode_ae_s16m_l_iu_funcUnit_uses }, + { "ae_s16m.l.x", ICLASS_AE_S16M_L_X, + 0, + Opcode_ae_s16m_l_x_encode_fns, 1, Opcode_ae_s16m_l_x_funcUnit_uses }, + { "ae_s16m.l.xu", ICLASS_AE_S16M_L_XU, + 0, + Opcode_ae_s16m_l_xu_encode_fns, 1, Opcode_ae_s16m_l_xu_funcUnit_uses }, + { "ae_s32f24.l.xc", ICLASS_AE_S32F24_L_XC, + 0, + Opcode_ae_s32f24_l_xc_encode_fns, 1, Opcode_ae_s32f24_l_xc_funcUnit_uses }, + { "ae_s32f24.l.xc1", ICLASS_AE_S32F24_L_XC1, + 0, + Opcode_ae_s32f24_l_xc1_encode_fns, 1, Opcode_ae_s32f24_l_xc1_funcUnit_uses }, + { "ae_s32f24.l.i", ICLASS_AE_S32F24_L_I, + 0, + Opcode_ae_s32f24_l_i_encode_fns, 1, Opcode_ae_s32f24_l_i_funcUnit_uses }, + { "ae_s32f24.l.ip", ICLASS_AE_S32F24_L_IP, + 0, + Opcode_ae_s32f24_l_ip_encode_fns, 1, Opcode_ae_s32f24_l_ip_funcUnit_uses }, + { "ae_s32f24.l.x", ICLASS_AE_S32F24_L_X, + 0, + Opcode_ae_s32f24_l_x_encode_fns, 1, Opcode_ae_s32f24_l_x_funcUnit_uses }, + { "ae_s32f24.l.xp", ICLASS_AE_S32F24_L_XP, + 0, + Opcode_ae_s32f24_l_xp_encode_fns, 1, Opcode_ae_s32f24_l_xp_funcUnit_uses }, + { "ae_s32.l.xc", ICLASS_AE_S32_L_XC, + 0, + Opcode_ae_s32_l_xc_encode_fns, 1, Opcode_ae_s32_l_xc_funcUnit_uses }, + { "ae_s32.l.xc1", ICLASS_AE_S32_L_XC1, + 0, + Opcode_ae_s32_l_xc1_encode_fns, 1, Opcode_ae_s32_l_xc1_funcUnit_uses }, + { "ae_s32.l.i", ICLASS_AE_S32_L_I, + 0, + Opcode_ae_s32_l_i_encode_fns, 1, Opcode_ae_s32_l_i_funcUnit_uses }, + { "ae_s32.l.ip", ICLASS_AE_S32_L_IP, + 0, + Opcode_ae_s32_l_ip_encode_fns, 1, Opcode_ae_s32_l_ip_funcUnit_uses }, + { "ae_s32.l.x", ICLASS_AE_S32_L_X, + 0, + Opcode_ae_s32_l_x_encode_fns, 1, Opcode_ae_s32_l_x_funcUnit_uses }, + { "ae_s32.l.xp", ICLASS_AE_S32_L_XP, + 0, + Opcode_ae_s32_l_xp_encode_fns, 1, Opcode_ae_s32_l_xp_funcUnit_uses }, + { "ae_s32.h.xc", ICLASS_AE_S32_H_XC, + 0, + Opcode_ae_s32_h_xc_encode_fns, 1, Opcode_ae_s32_h_xc_funcUnit_uses }, + { "ae_s32.h.xc1", ICLASS_AE_S32_H_XC1, + 0, + Opcode_ae_s32_h_xc1_encode_fns, 1, Opcode_ae_s32_h_xc1_funcUnit_uses }, + { "ae_s32.h.i", ICLASS_AE_S32_H_I, + 0, + Opcode_ae_s32_h_i_encode_fns, 1, Opcode_ae_s32_h_i_funcUnit_uses }, + { "ae_s32.h.ip", ICLASS_AE_S32_H_IP, + 0, + Opcode_ae_s32_h_ip_encode_fns, 1, Opcode_ae_s32_h_ip_funcUnit_uses }, + { "ae_s32.h.x", ICLASS_AE_S32_H_X, + 0, + Opcode_ae_s32_h_x_encode_fns, 1, Opcode_ae_s32_h_x_funcUnit_uses }, + { "ae_s32.h.xp", ICLASS_AE_S32_H_XP, + 0, + Opcode_ae_s32_h_xp_encode_fns, 1, Opcode_ae_s32_h_xp_funcUnit_uses }, + { "ae_s16.0.xc", ICLASS_AE_S16_0_XC, + 0, + Opcode_ae_s16_0_xc_encode_fns, 1, Opcode_ae_s16_0_xc_funcUnit_uses }, + { "ae_s16.0.xc1", ICLASS_AE_S16_0_XC1, + 0, + Opcode_ae_s16_0_xc1_encode_fns, 1, Opcode_ae_s16_0_xc1_funcUnit_uses }, + { "ae_s16.0.i", ICLASS_AE_S16_0_I, + 0, + Opcode_ae_s16_0_i_encode_fns, 1, Opcode_ae_s16_0_i_funcUnit_uses }, + { "ae_s16.0.ip", ICLASS_AE_S16_0_IP, + 0, + Opcode_ae_s16_0_ip_encode_fns, 1, Opcode_ae_s16_0_ip_funcUnit_uses }, + { "ae_s16.0.x", ICLASS_AE_S16_0_X, + 0, + Opcode_ae_s16_0_x_encode_fns, 1, Opcode_ae_s16_0_x_funcUnit_uses }, + { "ae_s16.0.xp", ICLASS_AE_S16_0_XP, + 0, + Opcode_ae_s16_0_xp_encode_fns, 1, Opcode_ae_s16_0_xp_funcUnit_uses }, + { "ae_s8.0.xc", ICLASS_AE_S8_0_XC, + 0, + Opcode_ae_s8_0_xc_encode_fns, 1, Opcode_ae_s8_0_xc_funcUnit_uses }, + { "ae_s8.0.xc1", ICLASS_AE_S8_0_XC1, + 0, + Opcode_ae_s8_0_xc1_encode_fns, 1, Opcode_ae_s8_0_xc1_funcUnit_uses }, + { "ae_s8.0.i", ICLASS_AE_S8_0_I, + 0, + Opcode_ae_s8_0_i_encode_fns, 1, Opcode_ae_s8_0_i_funcUnit_uses }, + { "ae_s8.0.ip", ICLASS_AE_S8_0_IP, + 0, + Opcode_ae_s8_0_ip_encode_fns, 1, Opcode_ae_s8_0_ip_funcUnit_uses }, + { "ae_s8.0.x", ICLASS_AE_S8_0_X, + 0, + Opcode_ae_s8_0_x_encode_fns, 1, Opcode_ae_s8_0_x_funcUnit_uses }, + { "ae_s8.0.xp", ICLASS_AE_S8_0_XP, + 0, + Opcode_ae_s8_0_xp_encode_fns, 1, Opcode_ae_s8_0_xp_funcUnit_uses }, + { "ae_s64.xc", ICLASS_AE_S64_XC, + 0, + Opcode_ae_s64_xc_encode_fns, 1, Opcode_ae_s64_xc_funcUnit_uses }, + { "ae_s64.xc1", ICLASS_AE_S64_XC1, + 0, + Opcode_ae_s64_xc1_encode_fns, 1, Opcode_ae_s64_xc1_funcUnit_uses }, + { "ae_s64.i", ICLASS_AE_S64_I, + 0, + Opcode_ae_s64_i_encode_fns, 1, Opcode_ae_s64_i_funcUnit_uses }, + { "ae_s64.ip", ICLASS_AE_S64_IP, + 0, + Opcode_ae_s64_ip_encode_fns, 1, Opcode_ae_s64_ip_funcUnit_uses }, + { "ae_s64.x", ICLASS_AE_S64_X, + 0, + Opcode_ae_s64_x_encode_fns, 1, Opcode_ae_s64_x_funcUnit_uses }, + { "ae_s64.xp", ICLASS_AE_S64_XP, + 0, + Opcode_ae_s64_xp_encode_fns, 1, Opcode_ae_s64_xp_funcUnit_uses }, + { "ae_s32m.xc", ICLASS_AE_S32M_XC, + 0, + Opcode_ae_s32m_xc_encode_fns, 1, Opcode_ae_s32m_xc_funcUnit_uses }, + { "ae_s32m.i", ICLASS_AE_S32M_I, + 0, + Opcode_ae_s32m_i_encode_fns, 1, Opcode_ae_s32m_i_funcUnit_uses }, + { "ae_s32m.iu", ICLASS_AE_S32M_IU, + 0, + Opcode_ae_s32m_iu_encode_fns, 1, Opcode_ae_s32m_iu_funcUnit_uses }, + { "ae_s32m.x", ICLASS_AE_S32M_X, + 0, + Opcode_ae_s32m_x_encode_fns, 1, Opcode_ae_s32m_x_funcUnit_uses }, + { "ae_s32m.xu", ICLASS_AE_S32M_XU, + 0, + Opcode_ae_s32m_xu_encode_fns, 1, Opcode_ae_s32m_xu_funcUnit_uses }, + { "ae_l32x2.xc2", ICLASS_AE_L32X2_XC2, + 0, + Opcode_ae_l32x2_xc2_encode_fns, 1, Opcode_ae_l32x2_xc2_funcUnit_uses }, + { "ae_l16x4.xc2", ICLASS_AE_L16X4_XC2, + 0, + Opcode_ae_l16x4_xc2_encode_fns, 1, Opcode_ae_l16x4_xc2_funcUnit_uses }, + { "ae_l8x8.xc2", ICLASS_AE_L8X8_XC2, + 0, + Opcode_ae_l8x8_xc2_encode_fns, 1, Opcode_ae_l8x8_xc2_funcUnit_uses }, + { "ae_l64.xc2", ICLASS_AE_L64_XC2, + 0, + Opcode_ae_l64_xc2_encode_fns, 1, Opcode_ae_l64_xc2_funcUnit_uses }, + { "ae_s32x2.xc2", ICLASS_AE_S32X2_XC2, + 0, + Opcode_ae_s32x2_xc2_encode_fns, 1, Opcode_ae_s32x2_xc2_funcUnit_uses }, + { "ae_s16x4.xc2", ICLASS_AE_S16X4_XC2, + 0, + Opcode_ae_s16x4_xc2_encode_fns, 1, Opcode_ae_s16x4_xc2_funcUnit_uses }, + { "ae_s8x8.xc2", ICLASS_AE_S8X8_XC2, + 0, + Opcode_ae_s8x8_xc2_encode_fns, 1, Opcode_ae_s8x8_xc2_funcUnit_uses }, + { "ae_s64.xc2", ICLASS_AE_S64_XC2, + 0, + Opcode_ae_s64_xc2_encode_fns, 1, Opcode_ae_s64_xc2_funcUnit_uses }, + { "ae_s16x4rng.i", ICLASS_AE_S16X4RNG_I, + 0, + Opcode_ae_s16x4rng_i_encode_fns, 1, Opcode_ae_s16x4rng_i_funcUnit_uses }, + { "ae_s16x4rng.ip", ICLASS_AE_S16X4RNG_IP, + 0, + Opcode_ae_s16x4rng_ip_encode_fns, 1, Opcode_ae_s16x4rng_ip_funcUnit_uses }, + { "ae_s16x4rng.x", ICLASS_AE_S16X4RNG_X, + 0, + Opcode_ae_s16x4rng_x_encode_fns, 1, Opcode_ae_s16x4rng_x_funcUnit_uses }, + { "ae_s16x4rng.xp", ICLASS_AE_S16X4RNG_XP, + 0, + Opcode_ae_s16x4rng_xp_encode_fns, 1, Opcode_ae_s16x4rng_xp_funcUnit_uses }, + { "ae_l32x2x2.xc", ICLASS_AE_L32X2X2_XC, + 0, + Opcode_ae_l32x2x2_xc_encode_fns, 1, Opcode_ae_l32x2x2_xc_funcUnit_uses }, + { "ae_l32x2x2.xc1", ICLASS_AE_L32X2X2_XC1, + 0, + Opcode_ae_l32x2x2_xc1_encode_fns, 1, Opcode_ae_l32x2x2_xc1_funcUnit_uses }, + { "ae_l32x2x2.i", ICLASS_AE_L32X2X2_I, + 0, + Opcode_ae_l32x2x2_i_encode_fns, 1, Opcode_ae_l32x2x2_i_funcUnit_uses }, + { "ae_l32x2x2.ip", ICLASS_AE_L32X2X2_IP, + 0, + Opcode_ae_l32x2x2_ip_encode_fns, 1, Opcode_ae_l32x2x2_ip_funcUnit_uses }, + { "ae_l32x2x2.x", ICLASS_AE_L32X2X2_X, + 0, + Opcode_ae_l32x2x2_x_encode_fns, 1, Opcode_ae_l32x2x2_x_funcUnit_uses }, + { "ae_l32x2x2.xp", ICLASS_AE_L32X2X2_XP, + 0, + Opcode_ae_l32x2x2_xp_encode_fns, 1, Opcode_ae_l32x2x2_xp_funcUnit_uses }, + { "ae_l16x4x2.xc", ICLASS_AE_L16X4X2_XC, + 0, + Opcode_ae_l16x4x2_xc_encode_fns, 1, Opcode_ae_l16x4x2_xc_funcUnit_uses }, + { "ae_l16x4x2.xc1", ICLASS_AE_L16X4X2_XC1, + 0, + Opcode_ae_l16x4x2_xc1_encode_fns, 1, Opcode_ae_l16x4x2_xc1_funcUnit_uses }, + { "ae_l16x4x2.i", ICLASS_AE_L16X4X2_I, + 0, + Opcode_ae_l16x4x2_i_encode_fns, 1, Opcode_ae_l16x4x2_i_funcUnit_uses }, + { "ae_l16x4x2.ip", ICLASS_AE_L16X4X2_IP, + 0, + Opcode_ae_l16x4x2_ip_encode_fns, 1, Opcode_ae_l16x4x2_ip_funcUnit_uses }, + { "ae_l16x4x2.x", ICLASS_AE_L16X4X2_X, + 0, + Opcode_ae_l16x4x2_x_encode_fns, 1, Opcode_ae_l16x4x2_x_funcUnit_uses }, + { "ae_l16x4x2.xp", ICLASS_AE_L16X4X2_XP, + 0, + Opcode_ae_l16x4x2_xp_encode_fns, 1, Opcode_ae_l16x4x2_xp_funcUnit_uses }, + { "ae_l8x8x2.xc", ICLASS_AE_L8X8X2_XC, + 0, + Opcode_ae_l8x8x2_xc_encode_fns, 1, Opcode_ae_l8x8x2_xc_funcUnit_uses }, + { "ae_l8x8x2.xc1", ICLASS_AE_L8X8X2_XC1, + 0, + Opcode_ae_l8x8x2_xc1_encode_fns, 1, Opcode_ae_l8x8x2_xc1_funcUnit_uses }, + { "ae_l8x8x2.i", ICLASS_AE_L8X8X2_I, + 0, + Opcode_ae_l8x8x2_i_encode_fns, 1, Opcode_ae_l8x8x2_i_funcUnit_uses }, + { "ae_l8x8x2.ip", ICLASS_AE_L8X8X2_IP, + 0, + Opcode_ae_l8x8x2_ip_encode_fns, 1, Opcode_ae_l8x8x2_ip_funcUnit_uses }, + { "ae_l8x8x2.x", ICLASS_AE_L8X8X2_X, + 0, + Opcode_ae_l8x8x2_x_encode_fns, 1, Opcode_ae_l8x8x2_x_funcUnit_uses }, + { "ae_l8x8x2.xp", ICLASS_AE_L8X8X2_XP, + 0, + Opcode_ae_l8x8x2_xp_encode_fns, 1, Opcode_ae_l8x8x2_xp_funcUnit_uses }, + { "ae_l64x2.xc", ICLASS_AE_L64X2_XC, + 0, + Opcode_ae_l64x2_xc_encode_fns, 1, Opcode_ae_l64x2_xc_funcUnit_uses }, + { "ae_l64x2.xc1", ICLASS_AE_L64X2_XC1, + 0, + Opcode_ae_l64x2_xc1_encode_fns, 1, Opcode_ae_l64x2_xc1_funcUnit_uses }, + { "ae_l64x2.i", ICLASS_AE_L64X2_I, + 0, + Opcode_ae_l64x2_i_encode_fns, 1, Opcode_ae_l64x2_i_funcUnit_uses }, + { "ae_l64x2.ip", ICLASS_AE_L64X2_IP, + 0, + Opcode_ae_l64x2_ip_encode_fns, 1, Opcode_ae_l64x2_ip_funcUnit_uses }, + { "ae_l64x2.x", ICLASS_AE_L64X2_X, + 0, + Opcode_ae_l64x2_x_encode_fns, 1, Opcode_ae_l64x2_x_funcUnit_uses }, + { "ae_l64x2.xp", ICLASS_AE_L64X2_XP, + 0, + Opcode_ae_l64x2_xp_encode_fns, 1, Opcode_ae_l64x2_xp_funcUnit_uses }, + { "ae_s32x2x2.xc", ICLASS_AE_S32X2X2_XC, + 0, + Opcode_ae_s32x2x2_xc_encode_fns, 1, Opcode_ae_s32x2x2_xc_funcUnit_uses }, + { "ae_s32x2x2.xc1", ICLASS_AE_S32X2X2_XC1, + 0, + Opcode_ae_s32x2x2_xc1_encode_fns, 1, Opcode_ae_s32x2x2_xc1_funcUnit_uses }, + { "ae_s32x2x2.i", ICLASS_AE_S32X2X2_I, + 0, + Opcode_ae_s32x2x2_i_encode_fns, 1, Opcode_ae_s32x2x2_i_funcUnit_uses }, + { "ae_s32x2x2.ip", ICLASS_AE_S32X2X2_IP, + 0, + Opcode_ae_s32x2x2_ip_encode_fns, 1, Opcode_ae_s32x2x2_ip_funcUnit_uses }, + { "ae_s32x2x2.x", ICLASS_AE_S32X2X2_X, + 0, + Opcode_ae_s32x2x2_x_encode_fns, 1, Opcode_ae_s32x2x2_x_funcUnit_uses }, + { "ae_s32x2x2.xp", ICLASS_AE_S32X2X2_XP, + 0, + Opcode_ae_s32x2x2_xp_encode_fns, 1, Opcode_ae_s32x2x2_xp_funcUnit_uses }, + { "ae_s32x2x2rng.i", ICLASS_AE_S32X2X2RNG_I, + 0, + Opcode_ae_s32x2x2rng_i_encode_fns, 1, Opcode_ae_s32x2x2rng_i_funcUnit_uses }, + { "ae_s32x2x2rng.ip", ICLASS_AE_S32X2X2RNG_IP, + 0, + Opcode_ae_s32x2x2rng_ip_encode_fns, 1, Opcode_ae_s32x2x2rng_ip_funcUnit_uses }, + { "ae_s32x2x2rng.x", ICLASS_AE_S32X2X2RNG_X, + 0, + Opcode_ae_s32x2x2rng_x_encode_fns, 1, Opcode_ae_s32x2x2rng_x_funcUnit_uses }, + { "ae_s32x2x2rng.xp", ICLASS_AE_S32X2X2RNG_XP, + 0, + Opcode_ae_s32x2x2rng_xp_encode_fns, 1, Opcode_ae_s32x2x2rng_xp_funcUnit_uses }, + { "ae_s16x4x2.xc", ICLASS_AE_S16X4X2_XC, + 0, + Opcode_ae_s16x4x2_xc_encode_fns, 1, Opcode_ae_s16x4x2_xc_funcUnit_uses }, + { "ae_s16x4x2.xc1", ICLASS_AE_S16X4X2_XC1, + 0, + Opcode_ae_s16x4x2_xc1_encode_fns, 1, Opcode_ae_s16x4x2_xc1_funcUnit_uses }, + { "ae_s16x4x2.i", ICLASS_AE_S16X4X2_I, + 0, + Opcode_ae_s16x4x2_i_encode_fns, 1, Opcode_ae_s16x4x2_i_funcUnit_uses }, + { "ae_s16x4x2.ip", ICLASS_AE_S16X4X2_IP, + 0, + Opcode_ae_s16x4x2_ip_encode_fns, 1, Opcode_ae_s16x4x2_ip_funcUnit_uses }, + { "ae_s16x4x2.x", ICLASS_AE_S16X4X2_X, + 0, + Opcode_ae_s16x4x2_x_encode_fns, 1, Opcode_ae_s16x4x2_x_funcUnit_uses }, + { "ae_s16x4x2.xp", ICLASS_AE_S16X4X2_XP, + 0, + Opcode_ae_s16x4x2_xp_encode_fns, 1, Opcode_ae_s16x4x2_xp_funcUnit_uses }, + { "ae_s8x8x2.xc", ICLASS_AE_S8X8X2_XC, + 0, + Opcode_ae_s8x8x2_xc_encode_fns, 1, Opcode_ae_s8x8x2_xc_funcUnit_uses }, + { "ae_s8x8x2.xc1", ICLASS_AE_S8X8X2_XC1, + 0, + Opcode_ae_s8x8x2_xc1_encode_fns, 1, Opcode_ae_s8x8x2_xc1_funcUnit_uses }, + { "ae_s8x8x2.i", ICLASS_AE_S8X8X2_I, + 0, + Opcode_ae_s8x8x2_i_encode_fns, 1, Opcode_ae_s8x8x2_i_funcUnit_uses }, + { "ae_s8x8x2.ip", ICLASS_AE_S8X8X2_IP, + 0, + Opcode_ae_s8x8x2_ip_encode_fns, 1, Opcode_ae_s8x8x2_ip_funcUnit_uses }, + { "ae_s8x8x2.x", ICLASS_AE_S8X8X2_X, + 0, + Opcode_ae_s8x8x2_x_encode_fns, 1, Opcode_ae_s8x8x2_x_funcUnit_uses }, + { "ae_s8x8x2.xp", ICLASS_AE_S8X8X2_XP, + 0, + Opcode_ae_s8x8x2_xp_encode_fns, 1, Opcode_ae_s8x8x2_xp_funcUnit_uses }, + { "ae_s8x4ux2.i", ICLASS_AE_S8X4UX2_I, + 0, + Opcode_ae_s8x4ux2_i_encode_fns, 1, Opcode_ae_s8x4ux2_i_funcUnit_uses }, + { "ae_s8x4ux2.ip", ICLASS_AE_S8X4UX2_IP, + 0, + Opcode_ae_s8x4ux2_ip_encode_fns, 1, Opcode_ae_s8x4ux2_ip_funcUnit_uses }, + { "ae_s8x4ux2.x", ICLASS_AE_S8X4UX2_X, + 0, + Opcode_ae_s8x4ux2_x_encode_fns, 1, Opcode_ae_s8x4ux2_x_funcUnit_uses }, + { "ae_s8x4ux2.xp", ICLASS_AE_S8X4UX2_XP, + 0, + Opcode_ae_s8x4ux2_xp_encode_fns, 1, Opcode_ae_s8x4ux2_xp_funcUnit_uses }, + { "ae_s64x2.xc", ICLASS_AE_S64X2_XC, + 0, + Opcode_ae_s64x2_xc_encode_fns, 1, Opcode_ae_s64x2_xc_funcUnit_uses }, + { "ae_s64x2.xc1", ICLASS_AE_S64X2_XC1, + 0, + Opcode_ae_s64x2_xc1_encode_fns, 1, Opcode_ae_s64x2_xc1_funcUnit_uses }, + { "ae_s64x2.i", ICLASS_AE_S64X2_I, + 0, + Opcode_ae_s64x2_i_encode_fns, 1, Opcode_ae_s64x2_i_funcUnit_uses }, + { "ae_s64x2.ip", ICLASS_AE_S64X2_IP, + 0, + Opcode_ae_s64x2_ip_encode_fns, 1, Opcode_ae_s64x2_ip_funcUnit_uses }, + { "ae_s64x2.x", ICLASS_AE_S64X2_X, + 0, + Opcode_ae_s64x2_x_encode_fns, 1, Opcode_ae_s64x2_x_funcUnit_uses }, + { "ae_s64x2.xp", ICLASS_AE_S64X2_XP, + 0, + Opcode_ae_s64x2_xp_encode_fns, 1, Opcode_ae_s64x2_xp_funcUnit_uses }, + { "ae_l32x2x2.xc2", ICLASS_AE_L32X2X2_XC2, + 0, + Opcode_ae_l32x2x2_xc2_encode_fns, 1, Opcode_ae_l32x2x2_xc2_funcUnit_uses }, + { "ae_l16x4x2.xc2", ICLASS_AE_L16X4X2_XC2, + 0, + Opcode_ae_l16x4x2_xc2_encode_fns, 1, Opcode_ae_l16x4x2_xc2_funcUnit_uses }, + { "ae_l8x8x2.xc2", ICLASS_AE_L8X8X2_XC2, + 0, + Opcode_ae_l8x8x2_xc2_encode_fns, 1, Opcode_ae_l8x8x2_xc2_funcUnit_uses }, + { "ae_l64x2.xc2", ICLASS_AE_L64X2_XC2, + 0, + Opcode_ae_l64x2_xc2_encode_fns, 1, Opcode_ae_l64x2_xc2_funcUnit_uses }, + { "ae_s32x2x2.xc2", ICLASS_AE_S32X2X2_XC2, + 0, + Opcode_ae_s32x2x2_xc2_encode_fns, 1, Opcode_ae_s32x2x2_xc2_funcUnit_uses }, + { "ae_s16x4x2.xc2", ICLASS_AE_S16X4X2_XC2, + 0, + Opcode_ae_s16x4x2_xc2_encode_fns, 1, Opcode_ae_s16x4x2_xc2_funcUnit_uses }, + { "ae_s8x8x2.xc2", ICLASS_AE_S8X8X2_XC2, + 0, + Opcode_ae_s8x8x2_xc2_encode_fns, 1, Opcode_ae_s8x8x2_xc2_funcUnit_uses }, + { "ae_s64x2.xc2", ICLASS_AE_S64X2_XC2, + 0, + Opcode_ae_s64x2_xc2_encode_fns, 1, Opcode_ae_s64x2_xc2_funcUnit_uses }, + { "ae_s16x4x2rng.i", ICLASS_AE_S16X4X2RNG_I, + 0, + Opcode_ae_s16x4x2rng_i_encode_fns, 1, Opcode_ae_s16x4x2rng_i_funcUnit_uses }, + { "ae_s16x4x2rng.ip", ICLASS_AE_S16X4X2RNG_IP, + 0, + Opcode_ae_s16x4x2rng_ip_encode_fns, 1, Opcode_ae_s16x4x2rng_ip_funcUnit_uses }, + { "ae_s16x4x2rng.x", ICLASS_AE_S16X4X2RNG_X, + 0, + Opcode_ae_s16x4x2rng_x_encode_fns, 1, Opcode_ae_s16x4x2rng_x_funcUnit_uses }, + { "ae_s16x4x2rng.xp", ICLASS_AE_S16X4X2RNG_XP, + 0, + Opcode_ae_s16x4x2rng_xp_encode_fns, 1, Opcode_ae_s16x4x2rng_xp_funcUnit_uses }, + { "ae_zalign64", ICLASS_AE_ZALIGN64, + 0, + Opcode_ae_zalign64_encode_fns, 0, 0 }, + { "ae_lalign64.i", ICLASS_AE_LALIGN64_I, + 0, + Opcode_ae_lalign64_i_encode_fns, 1, Opcode_ae_lalign64_i_funcUnit_uses }, + { "ae_salign64.i", ICLASS_AE_SALIGN64_I, + 0, + Opcode_ae_salign64_i_encode_fns, 1, Opcode_ae_salign64_i_funcUnit_uses }, + { "ae_movalign", ICLASS_AE_MOVALIGN, + 0, + Opcode_ae_movalign_encode_fns, 0, 0 }, + { "ae_la64.pp", ICLASS_AE_LA64_PP, + 0, + Opcode_ae_la64_pp_encode_fns, 1, Opcode_ae_la64_pp_funcUnit_uses }, + { "ae_la24pos.pc", ICLASS_AE_LA24POS_PC, + 0, + Opcode_ae_la24pos_pc_encode_fns, 1, Opcode_ae_la24pos_pc_funcUnit_uses }, + { "ae_la24neg.pc", ICLASS_AE_LA24NEG_PC, + 0, + Opcode_ae_la24neg_pc_encode_fns, 1, Opcode_ae_la24neg_pc_funcUnit_uses }, + { "ae_la24pos.pc1", ICLASS_AE_LA24POS_PC1, + 0, + Opcode_ae_la24pos_pc1_encode_fns, 1, Opcode_ae_la24pos_pc1_funcUnit_uses }, + { "ae_la24neg.pc1", ICLASS_AE_LA24NEG_PC1, + 0, + Opcode_ae_la24neg_pc1_encode_fns, 1, Opcode_ae_la24neg_pc1_funcUnit_uses }, + { "ae_la24x2pos.pc", ICLASS_AE_LA24X2POS_PC, + 0, + Opcode_ae_la24x2pos_pc_encode_fns, 1, Opcode_ae_la24x2pos_pc_funcUnit_uses }, + { "ae_la24x2neg.pc", ICLASS_AE_LA24X2NEG_PC, + 0, + Opcode_ae_la24x2neg_pc_encode_fns, 1, Opcode_ae_la24x2neg_pc_funcUnit_uses }, + { "ae_la24x2pos.pc1", ICLASS_AE_LA24X2POS_PC1, + 0, + Opcode_ae_la24x2pos_pc1_encode_fns, 1, Opcode_ae_la24x2pos_pc1_funcUnit_uses }, + { "ae_la24x2neg.pc1", ICLASS_AE_LA24X2NEG_PC1, + 0, + Opcode_ae_la24x2neg_pc1_encode_fns, 1, Opcode_ae_la24x2neg_pc1_funcUnit_uses }, + { "ae_la32x2pos.pc", ICLASS_AE_LA32X2POS_PC, + 0, + Opcode_ae_la32x2pos_pc_encode_fns, 1, Opcode_ae_la32x2pos_pc_funcUnit_uses }, + { "ae_la32x2neg.pc", ICLASS_AE_LA32X2NEG_PC, + 0, + Opcode_ae_la32x2neg_pc_encode_fns, 1, Opcode_ae_la32x2neg_pc_funcUnit_uses }, + { "ae_la32x2pos.pc1", ICLASS_AE_LA32X2POS_PC1, + 0, + Opcode_ae_la32x2pos_pc1_encode_fns, 1, Opcode_ae_la32x2pos_pc1_funcUnit_uses }, + { "ae_la32x2neg.pc1", ICLASS_AE_LA32X2NEG_PC1, + 0, + Opcode_ae_la32x2neg_pc1_encode_fns, 1, Opcode_ae_la32x2neg_pc1_funcUnit_uses }, + { "ae_la32x2pos.pc2", ICLASS_AE_LA32X2POS_PC2, + 0, + Opcode_ae_la32x2pos_pc2_encode_fns, 1, Opcode_ae_la32x2pos_pc2_funcUnit_uses }, + { "ae_la16x4pos.pc", ICLASS_AE_LA16X4POS_PC, + 0, + Opcode_ae_la16x4pos_pc_encode_fns, 1, Opcode_ae_la16x4pos_pc_funcUnit_uses }, + { "ae_la16x4neg.pc", ICLASS_AE_LA16X4NEG_PC, + 0, + Opcode_ae_la16x4neg_pc_encode_fns, 1, Opcode_ae_la16x4neg_pc_funcUnit_uses }, + { "ae_la16x4pos.pc1", ICLASS_AE_LA16X4POS_PC1, + 0, + Opcode_ae_la16x4pos_pc1_encode_fns, 1, Opcode_ae_la16x4pos_pc1_funcUnit_uses }, + { "ae_la16x4neg.pc1", ICLASS_AE_LA16X4NEG_PC1, + 0, + Opcode_ae_la16x4neg_pc1_encode_fns, 1, Opcode_ae_la16x4neg_pc1_funcUnit_uses }, + { "ae_la16x4pos.pc2", ICLASS_AE_LA16X4POS_PC2, + 0, + Opcode_ae_la16x4pos_pc2_encode_fns, 1, Opcode_ae_la16x4pos_pc2_funcUnit_uses }, + { "ae_la8x8pos.pc", ICLASS_AE_LA8X8POS_PC, + 0, + Opcode_ae_la8x8pos_pc_encode_fns, 1, Opcode_ae_la8x8pos_pc_funcUnit_uses }, + { "ae_la8x8neg.pc", ICLASS_AE_LA8X8NEG_PC, + 0, + Opcode_ae_la8x8neg_pc_encode_fns, 1, Opcode_ae_la8x8neg_pc_funcUnit_uses }, + { "ae_la8x8pos.pc1", ICLASS_AE_LA8X8POS_PC1, + 0, + Opcode_ae_la8x8pos_pc1_encode_fns, 1, Opcode_ae_la8x8pos_pc1_funcUnit_uses }, + { "ae_la8x8neg.pc1", ICLASS_AE_LA8X8NEG_PC1, + 0, + Opcode_ae_la8x8neg_pc1_encode_fns, 1, Opcode_ae_la8x8neg_pc1_funcUnit_uses }, + { "ae_la8x8pos.pc2", ICLASS_AE_LA8X8POS_PC2, + 0, + Opcode_ae_la8x8pos_pc2_encode_fns, 1, Opcode_ae_la8x8pos_pc2_funcUnit_uses }, + { "ae_la32x2x2pos.pc", ICLASS_AE_LA32X2X2POS_PC, + 0, + Opcode_ae_la32x2x2pos_pc_encode_fns, 1, Opcode_ae_la32x2x2pos_pc_funcUnit_uses }, + { "ae_la32x2x2pos.pc1", ICLASS_AE_LA32X2X2POS_PC1, + 0, + Opcode_ae_la32x2x2pos_pc1_encode_fns, 1, Opcode_ae_la32x2x2pos_pc1_funcUnit_uses }, + { "ae_la32x2x2pos.pc2", ICLASS_AE_LA32X2X2POS_PC2, + 0, + Opcode_ae_la32x2x2pos_pc2_encode_fns, 1, Opcode_ae_la32x2x2pos_pc2_funcUnit_uses }, + { "ae_la16x4x2pos.pc", ICLASS_AE_LA16X4X2POS_PC, + 0, + Opcode_ae_la16x4x2pos_pc_encode_fns, 1, Opcode_ae_la16x4x2pos_pc_funcUnit_uses }, + { "ae_la16x4x2pos.pc1", ICLASS_AE_LA16X4X2POS_PC1, + 0, + Opcode_ae_la16x4x2pos_pc1_encode_fns, 1, Opcode_ae_la16x4x2pos_pc1_funcUnit_uses }, + { "ae_la16x4x2pos.pc2", ICLASS_AE_LA16X4X2POS_PC2, + 0, + Opcode_ae_la16x4x2pos_pc2_encode_fns, 1, Opcode_ae_la16x4x2pos_pc2_funcUnit_uses }, + { "ae_la8x8x2pos.pc", ICLASS_AE_LA8X8X2POS_PC, + 0, + Opcode_ae_la8x8x2pos_pc_encode_fns, 1, Opcode_ae_la8x8x2pos_pc_funcUnit_uses }, + { "ae_la8x8x2pos.pc1", ICLASS_AE_LA8X8X2POS_PC1, + 0, + Opcode_ae_la8x8x2pos_pc1_encode_fns, 1, Opcode_ae_la8x8x2pos_pc1_funcUnit_uses }, + { "ae_la8x8x2pos.pc2", ICLASS_AE_LA8X8X2POS_PC2, + 0, + Opcode_ae_la8x8x2pos_pc2_encode_fns, 1, Opcode_ae_la8x8x2pos_pc2_funcUnit_uses }, + { "ae_sa64pos.fp", ICLASS_AE_SA64POS_FP, + 0, + Opcode_ae_sa64pos_fp_encode_fns, 1, Opcode_ae_sa64pos_fp_funcUnit_uses }, + { "ae_sa64neg.fp", ICLASS_AE_SA64NEG_FP, + 0, + Opcode_ae_sa64neg_fp_encode_fns, 1, Opcode_ae_sa64neg_fp_funcUnit_uses }, + { "ae_la32x2.ic", ICLASS_AE_LA32X2_IC, + 0, + Opcode_ae_la32x2_ic_encode_fns, 1, Opcode_ae_la32x2_ic_funcUnit_uses }, + { "ae_la32x2.ic1", ICLASS_AE_LA32X2_IC1, + 0, + Opcode_ae_la32x2_ic1_encode_fns, 1, Opcode_ae_la32x2_ic1_funcUnit_uses }, + { "ae_la32x2.ic2", ICLASS_AE_LA32X2_IC2, + 0, + Opcode_ae_la32x2_ic2_encode_fns, 1, Opcode_ae_la32x2_ic2_funcUnit_uses }, + { "ae_la32x2.ip", ICLASS_AE_LA32X2_IP, + 0, + Opcode_ae_la32x2_ip_encode_fns, 1, Opcode_ae_la32x2_ip_funcUnit_uses }, + { "ae_la32x2.rip", ICLASS_AE_LA32X2_RIP, + 0, + Opcode_ae_la32x2_rip_encode_fns, 1, Opcode_ae_la32x2_rip_funcUnit_uses }, + { "ae_la32x2.ric", ICLASS_AE_LA32X2_RIC, + 0, + Opcode_ae_la32x2_ric_encode_fns, 1, Opcode_ae_la32x2_ric_funcUnit_uses }, + { "ae_la32x2.ric1", ICLASS_AE_LA32X2_RIC1, + 0, + Opcode_ae_la32x2_ric1_encode_fns, 1, Opcode_ae_la32x2_ric1_funcUnit_uses }, + { "ae_la16x4.ic", ICLASS_AE_LA16X4_IC, + 0, + Opcode_ae_la16x4_ic_encode_fns, 1, Opcode_ae_la16x4_ic_funcUnit_uses }, + { "ae_la16x4.ic1", ICLASS_AE_LA16X4_IC1, + 0, + Opcode_ae_la16x4_ic1_encode_fns, 1, Opcode_ae_la16x4_ic1_funcUnit_uses }, + { "ae_la16x4.ic2", ICLASS_AE_LA16X4_IC2, + 0, + Opcode_ae_la16x4_ic2_encode_fns, 1, Opcode_ae_la16x4_ic2_funcUnit_uses }, + { "ae_la16x4.ip", ICLASS_AE_LA16X4_IP, + 0, + Opcode_ae_la16x4_ip_encode_fns, 1, Opcode_ae_la16x4_ip_funcUnit_uses }, + { "ae_la16x4.rip", ICLASS_AE_LA16X4_RIP, + 0, + Opcode_ae_la16x4_rip_encode_fns, 1, Opcode_ae_la16x4_rip_funcUnit_uses }, + { "ae_la16x4.ric", ICLASS_AE_LA16X4_RIC, + 0, + Opcode_ae_la16x4_ric_encode_fns, 1, Opcode_ae_la16x4_ric_funcUnit_uses }, + { "ae_la16x4.ric1", ICLASS_AE_LA16X4_RIC1, + 0, + Opcode_ae_la16x4_ric1_encode_fns, 1, Opcode_ae_la16x4_ric1_funcUnit_uses }, + { "ae_la8x8.ic", ICLASS_AE_LA8X8_IC, + 0, + Opcode_ae_la8x8_ic_encode_fns, 1, Opcode_ae_la8x8_ic_funcUnit_uses }, + { "ae_la8x8.ic1", ICLASS_AE_LA8X8_IC1, + 0, + Opcode_ae_la8x8_ic1_encode_fns, 1, Opcode_ae_la8x8_ic1_funcUnit_uses }, + { "ae_la8x8.ic2", ICLASS_AE_LA8X8_IC2, + 0, + Opcode_ae_la8x8_ic2_encode_fns, 1, Opcode_ae_la8x8_ic2_funcUnit_uses }, + { "ae_la8x8.ip", ICLASS_AE_LA8X8_IP, + 0, + Opcode_ae_la8x8_ip_encode_fns, 1, Opcode_ae_la8x8_ip_funcUnit_uses }, + { "ae_la8x8.rip", ICLASS_AE_LA8X8_RIP, + 0, + Opcode_ae_la8x8_rip_encode_fns, 1, Opcode_ae_la8x8_rip_funcUnit_uses }, + { "ae_la8x8.ric", ICLASS_AE_LA8X8_RIC, + 0, + Opcode_ae_la8x8_ric_encode_fns, 1, Opcode_ae_la8x8_ric_funcUnit_uses }, + { "ae_la8x8.ric1", ICLASS_AE_LA8X8_RIC1, + 0, + Opcode_ae_la8x8_ric1_encode_fns, 1, Opcode_ae_la8x8_ric1_funcUnit_uses }, + { "ae_la32x2f24.ic", ICLASS_AE_LA32X2F24_IC, + 0, + Opcode_ae_la32x2f24_ic_encode_fns, 1, Opcode_ae_la32x2f24_ic_funcUnit_uses }, + { "ae_la32x2f24.ic1", ICLASS_AE_LA32X2F24_IC1, + 0, + Opcode_ae_la32x2f24_ic1_encode_fns, 1, Opcode_ae_la32x2f24_ic1_funcUnit_uses }, + { "ae_la32x2f24.ip", ICLASS_AE_LA32X2F24_IP, + 0, + Opcode_ae_la32x2f24_ip_encode_fns, 1, Opcode_ae_la32x2f24_ip_funcUnit_uses }, + { "ae_la32x2f24.rip", ICLASS_AE_LA32X2F24_RIP, + 0, + Opcode_ae_la32x2f24_rip_encode_fns, 1, Opcode_ae_la32x2f24_rip_funcUnit_uses }, + { "ae_la32x2f24.ric", ICLASS_AE_LA32X2F24_RIC, + 0, + Opcode_ae_la32x2f24_ric_encode_fns, 1, Opcode_ae_la32x2f24_ric_funcUnit_uses }, + { "ae_la32x2f24.ric1", ICLASS_AE_LA32X2F24_RIC1, + 0, + Opcode_ae_la32x2f24_ric1_encode_fns, 1, Opcode_ae_la32x2f24_ric1_funcUnit_uses }, + { "ae_la24.ic", ICLASS_AE_LA24_IC, + 0, + Opcode_ae_la24_ic_encode_fns, 1, Opcode_ae_la24_ic_funcUnit_uses }, + { "ae_la24.ic1", ICLASS_AE_LA24_IC1, + 0, + Opcode_ae_la24_ic1_encode_fns, 1, Opcode_ae_la24_ic1_funcUnit_uses }, + { "ae_la24.ip", ICLASS_AE_LA24_IP, + 0, + Opcode_ae_la24_ip_encode_fns, 1, Opcode_ae_la24_ip_funcUnit_uses }, + { "ae_la24.rip", ICLASS_AE_LA24_RIP, + 0, + Opcode_ae_la24_rip_encode_fns, 1, Opcode_ae_la24_rip_funcUnit_uses }, + { "ae_la24.ric", ICLASS_AE_LA24_RIC, + 0, + Opcode_ae_la24_ric_encode_fns, 1, Opcode_ae_la24_ric_funcUnit_uses }, + { "ae_la24.ric1", ICLASS_AE_LA24_RIC1, + 0, + Opcode_ae_la24_ric1_encode_fns, 1, Opcode_ae_la24_ric1_funcUnit_uses }, + { "ae_la24x2.ic", ICLASS_AE_LA24X2_IC, + 0, + Opcode_ae_la24x2_ic_encode_fns, 1, Opcode_ae_la24x2_ic_funcUnit_uses }, + { "ae_la24x2.ic1", ICLASS_AE_LA24X2_IC1, + 0, + Opcode_ae_la24x2_ic1_encode_fns, 1, Opcode_ae_la24x2_ic1_funcUnit_uses }, + { "ae_la24x2.ip", ICLASS_AE_LA24X2_IP, + 0, + Opcode_ae_la24x2_ip_encode_fns, 1, Opcode_ae_la24x2_ip_funcUnit_uses }, + { "ae_la24x2.rip", ICLASS_AE_LA24X2_RIP, + 0, + Opcode_ae_la24x2_rip_encode_fns, 1, Opcode_ae_la24x2_rip_funcUnit_uses }, + { "ae_la24x2.ric", ICLASS_AE_LA24X2_RIC, + 0, + Opcode_ae_la24x2_ric_encode_fns, 1, Opcode_ae_la24x2_ric_funcUnit_uses }, + { "ae_la24x2.ric1", ICLASS_AE_LA24X2_RIC1, + 0, + Opcode_ae_la24x2_ric1_encode_fns, 1, Opcode_ae_la24x2_ric1_funcUnit_uses }, + { "ae_sa32x2.ic", ICLASS_AE_SA32X2_IC, + 0, + Opcode_ae_sa32x2_ic_encode_fns, 1, Opcode_ae_sa32x2_ic_funcUnit_uses }, + { "ae_sa32x2.ic1", ICLASS_AE_SA32X2_IC1, + 0, + Opcode_ae_sa32x2_ic1_encode_fns, 1, Opcode_ae_sa32x2_ic1_funcUnit_uses }, + { "ae_sa32x2.ic2", ICLASS_AE_SA32X2_IC2, + 0, + Opcode_ae_sa32x2_ic2_encode_fns, 1, Opcode_ae_sa32x2_ic2_funcUnit_uses }, + { "ae_sa32x2.ip", ICLASS_AE_SA32X2_IP, + 0, + Opcode_ae_sa32x2_ip_encode_fns, 1, Opcode_ae_sa32x2_ip_funcUnit_uses }, + { "ae_sa32x2.rip", ICLASS_AE_SA32X2_RIP, + 0, + Opcode_ae_sa32x2_rip_encode_fns, 1, Opcode_ae_sa32x2_rip_funcUnit_uses }, + { "ae_sa32x2.ric", ICLASS_AE_SA32X2_RIC, + 0, + Opcode_ae_sa32x2_ric_encode_fns, 1, Opcode_ae_sa32x2_ric_funcUnit_uses }, + { "ae_sa32x2.ric1", ICLASS_AE_SA32X2_RIC1, + 0, + Opcode_ae_sa32x2_ric1_encode_fns, 1, Opcode_ae_sa32x2_ric1_funcUnit_uses }, + { "ae_sa16x4.ic", ICLASS_AE_SA16X4_IC, + 0, + Opcode_ae_sa16x4_ic_encode_fns, 1, Opcode_ae_sa16x4_ic_funcUnit_uses }, + { "ae_sa16x4.ic1", ICLASS_AE_SA16X4_IC1, + 0, + Opcode_ae_sa16x4_ic1_encode_fns, 1, Opcode_ae_sa16x4_ic1_funcUnit_uses }, + { "ae_sa16x4.ic2", ICLASS_AE_SA16X4_IC2, + 0, + Opcode_ae_sa16x4_ic2_encode_fns, 1, Opcode_ae_sa16x4_ic2_funcUnit_uses }, + { "ae_sa16x4.ip", ICLASS_AE_SA16X4_IP, + 0, + Opcode_ae_sa16x4_ip_encode_fns, 1, Opcode_ae_sa16x4_ip_funcUnit_uses }, + { "ae_sa16x4.rip", ICLASS_AE_SA16X4_RIP, + 0, + Opcode_ae_sa16x4_rip_encode_fns, 1, Opcode_ae_sa16x4_rip_funcUnit_uses }, + { "ae_sa16x4.ric", ICLASS_AE_SA16X4_RIC, + 0, + Opcode_ae_sa16x4_ric_encode_fns, 1, Opcode_ae_sa16x4_ric_funcUnit_uses }, + { "ae_sa16x4.ric1", ICLASS_AE_SA16X4_RIC1, + 0, + Opcode_ae_sa16x4_ric1_encode_fns, 1, Opcode_ae_sa16x4_ric1_funcUnit_uses }, + { "ae_sa8x8.ic", ICLASS_AE_SA8X8_IC, + 0, + Opcode_ae_sa8x8_ic_encode_fns, 1, Opcode_ae_sa8x8_ic_funcUnit_uses }, + { "ae_sa8x8.ic1", ICLASS_AE_SA8X8_IC1, + 0, + Opcode_ae_sa8x8_ic1_encode_fns, 1, Opcode_ae_sa8x8_ic1_funcUnit_uses }, + { "ae_sa8x8.ic2", ICLASS_AE_SA8X8_IC2, + 0, + Opcode_ae_sa8x8_ic2_encode_fns, 1, Opcode_ae_sa8x8_ic2_funcUnit_uses }, + { "ae_sa8x8.ip", ICLASS_AE_SA8X8_IP, + 0, + Opcode_ae_sa8x8_ip_encode_fns, 1, Opcode_ae_sa8x8_ip_funcUnit_uses }, + { "ae_sa8x8.rip", ICLASS_AE_SA8X8_RIP, + 0, + Opcode_ae_sa8x8_rip_encode_fns, 1, Opcode_ae_sa8x8_rip_funcUnit_uses }, + { "ae_sa8x8.ric", ICLASS_AE_SA8X8_RIC, + 0, + Opcode_ae_sa8x8_ric_encode_fns, 1, Opcode_ae_sa8x8_ric_funcUnit_uses }, + { "ae_sa8x8.ric1", ICLASS_AE_SA8X8_RIC1, + 0, + Opcode_ae_sa8x8_ric1_encode_fns, 1, Opcode_ae_sa8x8_ric1_funcUnit_uses }, + { "ae_sa32x2f24.ic", ICLASS_AE_SA32X2F24_IC, + 0, + Opcode_ae_sa32x2f24_ic_encode_fns, 1, Opcode_ae_sa32x2f24_ic_funcUnit_uses }, + { "ae_sa32x2f24.ic1", ICLASS_AE_SA32X2F24_IC1, + 0, + Opcode_ae_sa32x2f24_ic1_encode_fns, 1, Opcode_ae_sa32x2f24_ic1_funcUnit_uses }, + { "ae_sa32x2f24.ip", ICLASS_AE_SA32X2F24_IP, + 0, + Opcode_ae_sa32x2f24_ip_encode_fns, 1, Opcode_ae_sa32x2f24_ip_funcUnit_uses }, + { "ae_sa32x2f24.rip", ICLASS_AE_SA32X2F24_RIP, + 0, + Opcode_ae_sa32x2f24_rip_encode_fns, 1, Opcode_ae_sa32x2f24_rip_funcUnit_uses }, + { "ae_sa32x2f24.ric", ICLASS_AE_SA32X2F24_RIC, + 0, + Opcode_ae_sa32x2f24_ric_encode_fns, 1, Opcode_ae_sa32x2f24_ric_funcUnit_uses }, + { "ae_sa32x2f24.ric1", ICLASS_AE_SA32X2F24_RIC1, + 0, + Opcode_ae_sa32x2f24_ric1_encode_fns, 1, Opcode_ae_sa32x2f24_ric1_funcUnit_uses }, + { "ae_sa24.l.ic", ICLASS_AE_SA24_L_IC, + 0, + Opcode_ae_sa24_l_ic_encode_fns, 1, Opcode_ae_sa24_l_ic_funcUnit_uses }, + { "ae_sa24.l.ic1", ICLASS_AE_SA24_L_IC1, + 0, + Opcode_ae_sa24_l_ic1_encode_fns, 1, Opcode_ae_sa24_l_ic1_funcUnit_uses }, + { "ae_sa24.l.ip", ICLASS_AE_SA24_L_IP, + 0, + Opcode_ae_sa24_l_ip_encode_fns, 1, Opcode_ae_sa24_l_ip_funcUnit_uses }, + { "ae_sa24.l.rip", ICLASS_AE_SA24_L_RIP, + 0, + Opcode_ae_sa24_l_rip_encode_fns, 1, Opcode_ae_sa24_l_rip_funcUnit_uses }, + { "ae_sa24.l.ric", ICLASS_AE_SA24_L_RIC, + 0, + Opcode_ae_sa24_l_ric_encode_fns, 1, Opcode_ae_sa24_l_ric_funcUnit_uses }, + { "ae_sa24.l.ric1", ICLASS_AE_SA24_L_RIC1, + 0, + Opcode_ae_sa24_l_ric1_encode_fns, 1, Opcode_ae_sa24_l_ric1_funcUnit_uses }, + { "ae_sa24x2.ic", ICLASS_AE_SA24X2_IC, + 0, + Opcode_ae_sa24x2_ic_encode_fns, 1, Opcode_ae_sa24x2_ic_funcUnit_uses }, + { "ae_sa24x2.ic1", ICLASS_AE_SA24X2_IC1, + 0, + Opcode_ae_sa24x2_ic1_encode_fns, 1, Opcode_ae_sa24x2_ic1_funcUnit_uses }, + { "ae_sa24x2.ip", ICLASS_AE_SA24X2_IP, + 0, + Opcode_ae_sa24x2_ip_encode_fns, 1, Opcode_ae_sa24x2_ip_funcUnit_uses }, + { "ae_sa24x2.rip", ICLASS_AE_SA24X2_RIP, + 0, + Opcode_ae_sa24x2_rip_encode_fns, 1, Opcode_ae_sa24x2_rip_funcUnit_uses }, + { "ae_sa24x2.ric", ICLASS_AE_SA24X2_RIC, + 0, + Opcode_ae_sa24x2_ric_encode_fns, 1, Opcode_ae_sa24x2_ric_funcUnit_uses }, + { "ae_sa24x2.ric1", ICLASS_AE_SA24X2_RIC1, + 0, + Opcode_ae_sa24x2_ric1_encode_fns, 1, Opcode_ae_sa24x2_ric1_funcUnit_uses }, + { "ae_addicirc", ICLASS_AE_ADDICIRC, + 0, + Opcode_ae_addicirc_encode_fns, 0, 0 }, + { "ae_addcirc.xc2", ICLASS_AE_ADDCIRC_XC2, + 0, + Opcode_ae_addcirc_xc2_encode_fns, 0, 0 }, + { "ae_addcirc.xc1", ICLASS_AE_ADDCIRC_XC1, + 0, + Opcode_ae_addcirc_xc1_encode_fns, 0, 0 }, + { "ae_addcirc.xc", ICLASS_AE_ADDCIRC_XC, + 0, + Opcode_ae_addcirc_xc_encode_fns, 0, 0 }, + { "ae_s32ra64s.i", ICLASS_AE_S32RA64S_I, + 0, + Opcode_ae_s32ra64s_i_encode_fns, 1, Opcode_ae_s32ra64s_i_funcUnit_uses }, + { "ae_s32ra64s.ip", ICLASS_AE_S32RA64S_IP, + 0, + Opcode_ae_s32ra64s_ip_encode_fns, 1, Opcode_ae_s32ra64s_ip_funcUnit_uses }, + { "ae_s32ra64s.x", ICLASS_AE_S32RA64S_X, + 0, + Opcode_ae_s32ra64s_x_encode_fns, 1, Opcode_ae_s32ra64s_x_funcUnit_uses }, + { "ae_s32ra64s.xp", ICLASS_AE_S32RA64S_XP, + 0, + Opcode_ae_s32ra64s_xp_encode_fns, 1, Opcode_ae_s32ra64s_xp_funcUnit_uses }, + { "ae_s32ra64s.xc", ICLASS_AE_S32RA64S_XC, + 0, + Opcode_ae_s32ra64s_xc_encode_fns, 1, Opcode_ae_s32ra64s_xc_funcUnit_uses }, + { "ae_s32ra64s.xc1", ICLASS_AE_S32RA64S_XC1, + 0, + Opcode_ae_s32ra64s_xc1_encode_fns, 1, Opcode_ae_s32ra64s_xc1_funcUnit_uses }, + { "ae_s24ra64s.i", ICLASS_AE_S24RA64S_I, + 0, + Opcode_ae_s24ra64s_i_encode_fns, 1, Opcode_ae_s24ra64s_i_funcUnit_uses }, + { "ae_s24ra64s.ip", ICLASS_AE_S24RA64S_IP, + 0, + Opcode_ae_s24ra64s_ip_encode_fns, 1, Opcode_ae_s24ra64s_ip_funcUnit_uses }, + { "ae_s24ra64s.x", ICLASS_AE_S24RA64S_X, + 0, + Opcode_ae_s24ra64s_x_encode_fns, 1, Opcode_ae_s24ra64s_x_funcUnit_uses }, + { "ae_s24ra64s.xp", ICLASS_AE_S24RA64S_XP, + 0, + Opcode_ae_s24ra64s_xp_encode_fns, 1, Opcode_ae_s24ra64s_xp_funcUnit_uses }, + { "ae_s24ra64s.xc", ICLASS_AE_S24RA64S_XC, + 0, + Opcode_ae_s24ra64s_xc_encode_fns, 1, Opcode_ae_s24ra64s_xc_funcUnit_uses }, + { "ae_s24ra64s.xc1", ICLASS_AE_S24RA64S_XC1, + 0, + Opcode_ae_s24ra64s_xc1_encode_fns, 1, Opcode_ae_s24ra64s_xc1_funcUnit_uses }, + { "ae_s32x2ra64s.ip", ICLASS_AE_S32X2RA64S_IP, + 0, + Opcode_ae_s32x2ra64s_ip_encode_fns, 1, Opcode_ae_s32x2ra64s_ip_funcUnit_uses }, + { "ae_s24x2ra64s.ip", ICLASS_AE_S24X2RA64S_IP, + 0, + Opcode_ae_s24x2ra64s_ip_encode_fns, 1, Opcode_ae_s24x2ra64s_ip_funcUnit_uses }, + { "ae_s16x4ra32s.ip", ICLASS_AE_S16X4RA32S_IP, + 0, + Opcode_ae_s16x4ra32s_ip_encode_fns, 1, Opcode_ae_s16x4ra32s_ip_funcUnit_uses }, + { "ae_addbrba32", ICLASS_AE_ADDBRBA32, + 0, + Opcode_ae_addbrba32_encode_fns, 0, 0 }, + { "ae_s32x2.l.ip", ICLASS_AE_S32X2_L_IP, + 0, + Opcode_ae_s32x2_l_ip_encode_fns, 1, Opcode_ae_s32x2_l_ip_funcUnit_uses }, + { "ae_bitswap", ICLASS_AE_BITSWAP, + 0, + Opcode_ae_bitswap_encode_fns, 0, 0 }, + { "ae_mul32js", ICLASS_AE_MUL32JS, + 0, + Opcode_ae_mul32js_encode_fns, 0, 0 }, + { "ae_addandsub32s", ICLASS_AE_ADDANDSUB32S, + 0, + Opcode_ae_addandsub32s_encode_fns, 0, 0 }, + { "ae_addandsub32js", ICLASS_AE_ADDANDSUB32JS, + 0, + Opcode_ae_addandsub32js_encode_fns, 0, 0 }, + { "ae_addandsubrng32", ICLASS_AE_ADDANDSUBRNG32, + 0, + Opcode_ae_addandsubrng32_encode_fns, 0, 0 }, + { "ae_addandsubrng32.h", ICLASS_AE_ADDANDSUBRNG32_H, + 0, + Opcode_ae_addandsubrng32_h_encode_fns, 0, 0 }, + { "ae_addandsubrng32.l", ICLASS_AE_ADDANDSUBRNG32_L, + 0, + Opcode_ae_addandsubrng32_l_encode_fns, 0, 0 }, + { "ae_addrng32", ICLASS_AE_ADDRNG32, + 0, + Opcode_ae_addrng32_encode_fns, 0, 0 }, + { "ae_subrng32", ICLASS_AE_SUBRNG32, + 0, + Opcode_ae_subrng32_encode_fns, 0, 0 }, + { "ae_rng32x2", ICLASS_AE_RNG32X2, + 0, + Opcode_ae_rng32x2_encode_fns, 0, 0 }, + { "ae_sel16i", ICLASS_AE_SEL16I, + 0, + Opcode_ae_sel16i_encode_fns, 0, 0 }, + { "ae_sel16i.n", ICLASS_AE_SEL16I_N, + 0, + Opcode_ae_sel16i_n_encode_fns, 0, 0 }, + { "ae_shortswap", ICLASS_AE_SHORTSWAP, + 0, + Opcode_ae_shortswap_encode_fns, 0, 0 }, + { "ae_movab4", ICLASS_AE_MOVAB4, + 0, + Opcode_ae_movab4_encode_fns, 0, 0 }, + { "ae_movab2", ICLASS_AE_MOVAB2, + 0, + Opcode_ae_movab2_encode_fns, 0, 0 }, + { "ae_movab", ICLASS_AE_MOVAB, + 0, + Opcode_ae_movab_encode_fns, 0, 0 }, + { "ae_movba", ICLASS_AE_MOVBA, + 0, + Opcode_ae_movba_encode_fns, 0, 0 }, + { "ae_movba1x2", ICLASS_AE_MOVBA1X2, + 0, + Opcode_ae_movba1x2_encode_fns, 0, 0 }, + { "ae_movba4", ICLASS_AE_MOVBA4, + 0, + Opcode_ae_movba4_encode_fns, 0, 0 }, + { "ae_movba2", ICLASS_AE_MOVBA2, + 0, + Opcode_ae_movba2_encode_fns, 0, 0 }, + { "ae_movb2", ICLASS_AE_MOVB2, + 0, + Opcode_ae_movb2_encode_fns, 0, 0 }, + { "ae_movb4", ICLASS_AE_MOVB4, + 0, + Opcode_ae_movb4_encode_fns, 0, 0 }, + { "ae_movt16x4", ICLASS_AE_MOVT16X4, + 0, + Opcode_ae_movt16x4_encode_fns, 0, 0 }, + { "ae_movf16x4", ICLASS_AE_MOVF16X4, + 0, + Opcode_ae_movf16x4_encode_fns, 0, 0 }, + { "ae_movt32x2", ICLASS_AE_MOVT32X2, + 0, + Opcode_ae_movt32x2_encode_fns, 0, 0 }, + { "ae_movf32x2", ICLASS_AE_MOVF32X2, + 0, + Opcode_ae_movf32x2_encode_fns, 0, 0 }, + { "ae_movsara7x2", ICLASS_AE_MOVSARA7X2, + 0, + Opcode_ae_movsara7x2_encode_fns, 0, 0 }, + { "ae_movsard7", ICLASS_AE_MOVSARD7, + 0, + Opcode_ae_movsard7_encode_fns, 0, 0 }, + { "ae_movasar", ICLASS_AE_MOVASAR, + 0, + Opcode_ae_movasar_encode_fns, 0, 0 }, + { "ae_movda32x2", ICLASS_AE_MOVDA32X2, + 0, + Opcode_ae_movda32x2_encode_fns, 0, 0 }, + { "ae_movda32", ICLASS_AE_MOVDA32, + 0, + Opcode_ae_movda32_encode_fns, 0, 0 }, + { "ae_movda16x2", ICLASS_AE_MOVDA16X2, + 0, + Opcode_ae_movda16x2_encode_fns, 0, 0 }, + { "ae_movda16", ICLASS_AE_MOVDA16, + 0, + Opcode_ae_movda16_encode_fns, 0, 0 }, + { "ae_movi", ICLASS_AE_MOVI, + 0, + Opcode_ae_movi_encode_fns, 0, 0 }, + { "ae_truncp24a32x2", ICLASS_AE_TRUNCP24A32X2, + 0, + Opcode_ae_truncp24a32x2_encode_fns, 0, 0 }, + { "ae_sat16x4", ICLASS_AE_SAT16X4, + 0, + Opcode_ae_sat16x4_encode_fns, 0, 0 }, + { "ae_cvt32x2f16.32", ICLASS_AE_CVT32X2F16_32, + 0, + Opcode_ae_cvt32x2f16_32_encode_fns, 0, 0 }, + { "ae_cvt32x2f16.10", ICLASS_AE_CVT32X2F16_10, + 0, + Opcode_ae_cvt32x2f16_10_encode_fns, 0, 0 }, + { "ae_sext32x2d16.32", ICLASS_AE_SEXT32X2D16_32, + 0, + Opcode_ae_sext32x2d16_32_encode_fns, 0, 0 }, + { "ae_sext32x2d16.10", ICLASS_AE_SEXT32X2D16_10, + 0, + Opcode_ae_sext32x2d16_10_encode_fns, 0, 0 }, + { "ae_cvta32f24s.l", ICLASS_AE_CVTA32F24S_L, + 0, + Opcode_ae_cvta32f24s_l_encode_fns, 0, 0 }, + { "ae_cvta32f24s.h", ICLASS_AE_CVTA32F24S_H, + 0, + Opcode_ae_cvta32f24s_h_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.ll", ICLASS_AE_CVTP24A16X2_LL, + 0, + Opcode_ae_cvtp24a16x2_ll_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.lh", ICLASS_AE_CVTP24A16X2_LH, + 0, + Opcode_ae_cvtp24a16x2_lh_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.hl", ICLASS_AE_CVTP24A16X2_HL, + 0, + Opcode_ae_cvtp24a16x2_hl_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.hh", ICLASS_AE_CVTP24A16X2_HH, + 0, + Opcode_ae_cvtp24a16x2_hh_encode_fns, 0, 0 }, + { "ae_truncp24q48x2", ICLASS_AE_TRUNCP24Q48X2, + 0, + Opcode_ae_truncp24q48x2_encode_fns, 0, 0 }, + { "ae_trunca32x2f64s", ICLASS_AE_TRUNCA32X2F64S, + 0, + Opcode_ae_trunca32x2f64s_encode_fns, 0, 0 }, + { "ae_trunci32x2f64s", ICLASS_AE_TRUNCI32X2F64S, + 0, + Opcode_ae_trunci32x2f64s_encode_fns, 0, 0 }, + { "ae_trunca32f64s.l", ICLASS_AE_TRUNCA32F64S_L, + 0, + Opcode_ae_trunca32f64s_l_encode_fns, 0, 0 }, + { "ae_trunci32f64s.l", ICLASS_AE_TRUNCI32F64S_L, + 0, + Opcode_ae_trunci32f64s_l_encode_fns, 0, 0 }, + { "ae_truncp16", ICLASS_AE_TRUNCP16, + 0, + Opcode_ae_truncp16_encode_fns, 0, 0 }, + { "ae_round32x2f64ssym", ICLASS_AE_ROUND32X2F64SSYM, + 0, + Opcode_ae_round32x2f64ssym_encode_fns, 0, 0 }, + { "ae_round32x2f64sasym", ICLASS_AE_ROUND32X2F64SASYM, + 0, + Opcode_ae_round32x2f64sasym_encode_fns, 0, 0 }, + { "ae_round32x2f48ssym", ICLASS_AE_ROUND32X2F48SSYM, + 0, + Opcode_ae_round32x2f48ssym_encode_fns, 0, 0 }, + { "ae_round32x2f48sasym", ICLASS_AE_ROUND32X2F48SASYM, + 0, + Opcode_ae_round32x2f48sasym_encode_fns, 0, 0 }, + { "ae_round16x4f32ssym", ICLASS_AE_ROUND16X4F32SSYM, + 0, + Opcode_ae_round16x4f32ssym_encode_fns, 0, 0 }, + { "ae_round16x4f32sasym", ICLASS_AE_ROUND16X4F32SASYM, + 0, + Opcode_ae_round16x4f32sasym_encode_fns, 0, 0 }, + { "ae_round24x2f48ssym", ICLASS_AE_ROUND24X2F48SSYM, + 0, + Opcode_ae_round24x2f48ssym_encode_fns, 0, 0 }, + { "ae_round24x2f48sasym", ICLASS_AE_ROUND24X2F48SASYM, + 0, + Opcode_ae_round24x2f48sasym_encode_fns, 0, 0 }, + { "ae_roundsp16q48x2sym", ICLASS_AE_ROUNDSP16Q48X2SYM, + 0, + Opcode_ae_roundsp16q48x2sym_encode_fns, 0, 0 }, + { "ae_roundsp16q48x2asym", ICLASS_AE_ROUNDSP16Q48X2ASYM, + 0, + Opcode_ae_roundsp16q48x2asym_encode_fns, 0, 0 }, + { "ae_minabs32s", ICLASS_AE_MINABS32S, + 0, + Opcode_ae_minabs32s_encode_fns, 0, 0 }, + { "ae_maxabs32s", ICLASS_AE_MAXABS32S, + 0, + Opcode_ae_maxabs32s_encode_fns, 0, 0 }, + { "ae_roundsp16f24sym", ICLASS_AE_ROUNDSP16F24SYM, + 0, + Opcode_ae_roundsp16f24sym_encode_fns, 0, 0 }, + { "ae_roundsp16f24asym", ICLASS_AE_ROUNDSP16F24ASYM, + 0, + Opcode_ae_roundsp16f24asym_encode_fns, 0, 0 }, + { "ae_mov", ICLASS_AE_MOV, + 0, + Opcode_ae_mov_encode_fns, 0, 0 }, + { "ae_movt64", ICLASS_AE_MOVT64, + 0, + Opcode_ae_movt64_encode_fns, 0, 0 }, + { "ae_movf64", ICLASS_AE_MOVF64, + 0, + Opcode_ae_movf64_encode_fns, 0, 0 }, + { "ae_cvtq56a32s", ICLASS_AE_CVTQ56A32S, + 0, + Opcode_ae_cvtq56a32s_encode_fns, 0, 0 }, + { "ae_cvt48a32", ICLASS_AE_CVT48A32, + 0, + Opcode_ae_cvt48a32_encode_fns, 0, 0 }, + { "ae_cvt64a32", ICLASS_AE_CVT64A32, + 0, + Opcode_ae_cvt64a32_encode_fns, 0, 0 }, + { "ae_cvtq56p32s.l", ICLASS_AE_CVTQ56P32S_L, + 0, + Opcode_ae_cvtq56p32s_l_encode_fns, 0, 0 }, + { "ae_cvtq56p32s.h", ICLASS_AE_CVTQ56P32S_H, + 0, + Opcode_ae_cvtq56p32s_h_encode_fns, 0, 0 }, + { "ae_cvt64f32.h", ICLASS_AE_CVT64F32_H, + 0, + Opcode_ae_cvt64f32_h_encode_fns, 0, 0 }, + { "ae_cvt48f32.l", ICLASS_AE_CVT48F32_L, + 0, + Opcode_ae_cvt48f32_l_encode_fns, 0, 0 }, + { "ae_cvt48f32.h", ICLASS_AE_CVT48F32_H, + 0, + Opcode_ae_cvt48f32_h_encode_fns, 0, 0 }, + { "ae_sat48s", ICLASS_AE_SAT48S, + 0, + Opcode_ae_sat48s_encode_fns, 0, 0 }, + { "ae_satq56s", ICLASS_AE_SATQ56S, + 0, + Opcode_ae_satq56s_encode_fns, 0, 0 }, + { "ae_sat24s", ICLASS_AE_SAT24S, + 0, + Opcode_ae_sat24s_encode_fns, 0, 0 }, + { "ae_truncq32", ICLASS_AE_TRUNCQ32, + 0, + Opcode_ae_truncq32_encode_fns, 0, 0 }, + { "ae_minabs64s", ICLASS_AE_MINABS64S, + 0, + Opcode_ae_minabs64s_encode_fns, 0, 0 }, + { "ae_maxabs64s", ICLASS_AE_MAXABS64S, + 0, + Opcode_ae_maxabs64s_encode_fns, 0, 0 }, + { "ae_roundsq32f48sym", ICLASS_AE_ROUNDSQ32F48SYM, + 0, + Opcode_ae_roundsq32f48sym_encode_fns, 0, 0 }, + { "ae_roundsq32f48asym", ICLASS_AE_ROUNDSQ32F48ASYM, + 0, + Opcode_ae_roundsq32f48asym_encode_fns, 0, 0 }, + { "ae_trunca32q48", ICLASS_AE_TRUNCA32Q48, + 0, + Opcode_ae_trunca32q48_encode_fns, 0, 0 }, + { "ae_movad32.l", ICLASS_AE_MOVAD32_L, + 0, + Opcode_ae_movad32_l_encode_fns, 0, 0 }, + { "ae_movad32.h", ICLASS_AE_MOVAD32_H, + 0, + Opcode_ae_movad32_h_encode_fns, 0, 0 }, + { "ae_movad16.3", ICLASS_AE_MOVAD16_3, + 0, + Opcode_ae_movad16_3_encode_fns, 0, 0 }, + { "ae_movad16.2", ICLASS_AE_MOVAD16_2, + 0, + Opcode_ae_movad16_2_encode_fns, 0, 0 }, + { "ae_movad16.1", ICLASS_AE_MOVAD16_1, + 0, + Opcode_ae_movad16_1_encode_fns, 0, 0 }, + { "ae_movad16.0", ICLASS_AE_MOVAD16_0, + 0, + Opcode_ae_movad16_0_encode_fns, 0, 0 }, + { "ae_sra64_32", ICLASS_AE_SRA64_32, + 0, + Opcode_ae_sra64_32_encode_fns, 0, 0 }, + { "ae_pksr32", ICLASS_AE_PKSR32, + 0, + Opcode_ae_pksr32_encode_fns, 0, 0 }, + { "ae_pksr24", ICLASS_AE_PKSR24, + 0, + Opcode_ae_pksr24_encode_fns, 0, 0 }, + { "ae_pksrf32", ICLASS_AE_PKSRF32, + 0, + Opcode_ae_pksrf32_encode_fns, 0, 0 }, + { "ae_pksr16", ICLASS_AE_PKSR16, + 0, + Opcode_ae_pksr16_encode_fns, 0, 0 }, + { "ae_trunca16p24s.l", ICLASS_AE_TRUNCA16P24S_L, + 0, + Opcode_ae_trunca16p24s_l_encode_fns, 0, 0 }, + { "ae_trunca16p24s.h", ICLASS_AE_TRUNCA16P24S_H, + 0, + Opcode_ae_trunca16p24s_h_encode_fns, 0, 0 }, + { "ae_add32", ICLASS_AE_ADD32, + 0, + Opcode_ae_add32_encode_fns, 0, 0 }, + { "ae_sub32", ICLASS_AE_SUB32, + 0, + Opcode_ae_sub32_encode_fns, 0, 0 }, + { "ae_addsub32", ICLASS_AE_ADDSUB32, + 0, + Opcode_ae_addsub32_encode_fns, 0, 0 }, + { "ae_subadd32", ICLASS_AE_SUBADD32, + 0, + Opcode_ae_subadd32_encode_fns, 0, 0 }, + { "ae_add16", ICLASS_AE_ADD16, + 0, + Opcode_ae_add16_encode_fns, 0, 0 }, + { "ae_sub16", ICLASS_AE_SUB16, + 0, + Opcode_ae_sub16_encode_fns, 0, 0 }, + { "ae_add32_hl_lh", ICLASS_AE_ADD32_HL_LH, + 0, + Opcode_ae_add32_hl_lh_encode_fns, 0, 0 }, + { "ae_addsub32_hl_lh", ICLASS_AE_ADDSUB32_HL_LH, + 0, + Opcode_ae_addsub32_hl_lh_encode_fns, 0, 0 }, + { "ae_neg32", ICLASS_AE_NEG32, + 0, + Opcode_ae_neg32_encode_fns, 0, 0 }, + { "ae_abs32", ICLASS_AE_ABS32, + 0, + Opcode_ae_abs32_encode_fns, 0, 0 }, + { "ae_neg32_l", ICLASS_AE_NEG32_L, + 0, + Opcode_ae_neg32_l_encode_fns, 0, 0 }, + { "ae_add24s", ICLASS_AE_ADD24S, + 0, + Opcode_ae_add24s_encode_fns, 0, 0 }, + { "ae_sub24s", ICLASS_AE_SUB24S, + 0, + Opcode_ae_sub24s_encode_fns, 0, 0 }, + { "ae_add32s", ICLASS_AE_ADD32S, + 0, + Opcode_ae_add32s_encode_fns, 0, 0 }, + { "ae_sub32s", ICLASS_AE_SUB32S, + 0, + Opcode_ae_sub32s_encode_fns, 0, 0 }, + { "ae_addsub32s", ICLASS_AE_ADDSUB32S, + 0, + Opcode_ae_addsub32s_encode_fns, 0, 0 }, + { "ae_subadd32s", ICLASS_AE_SUBADD32S, + 0, + Opcode_ae_subadd32s_encode_fns, 0, 0 }, + { "ae_add16s", ICLASS_AE_ADD16S, + 0, + Opcode_ae_add16s_encode_fns, 0, 0 }, + { "ae_sub16s", ICLASS_AE_SUB16S, + 0, + Opcode_ae_sub16s_encode_fns, 0, 0 }, + { "ae_add32s_hl_lh", ICLASS_AE_ADD32S_HL_LH, + 0, + Opcode_ae_add32s_hl_lh_encode_fns, 0, 0 }, + { "ae_addsub32s_hl_lh", ICLASS_AE_ADDSUB32S_HL_LH, + 0, + Opcode_ae_addsub32s_hl_lh_encode_fns, 0, 0 }, + { "ae_neg24s", ICLASS_AE_NEG24S, + 0, + Opcode_ae_neg24s_encode_fns, 0, 0 }, + { "ae_abs24s", ICLASS_AE_ABS24S, + 0, + Opcode_ae_abs24s_encode_fns, 0, 0 }, + { "ae_neg32s", ICLASS_AE_NEG32S, + 0, + Opcode_ae_neg32s_encode_fns, 0, 0 }, + { "ae_abs32s", ICLASS_AE_ABS32S, + 0, + Opcode_ae_abs32s_encode_fns, 0, 0 }, + { "ae_neg16s", ICLASS_AE_NEG16S, + 0, + Opcode_ae_neg16s_encode_fns, 0, 0 }, + { "ae_abs16s", ICLASS_AE_ABS16S, + 0, + Opcode_ae_abs16s_encode_fns, 0, 0 }, + { "ae_abs16", ICLASS_AE_ABS16, + 0, + Opcode_ae_abs16_encode_fns, 0, 0 }, + { "ae_mulc16js.h", ICLASS_AE_MULC16JS_H, + 0, + Opcode_ae_mulc16js_h_encode_fns, 0, 0 }, + { "ae_mulc16js.l", ICLASS_AE_MULC16JS_L, + 0, + Opcode_ae_mulc16js_l_encode_fns, 0, 0 }, + { "ae_mulac16js.h", ICLASS_AE_MULAC16JS_H, + 0, + Opcode_ae_mulac16js_h_encode_fns, 0, 0 }, + { "ae_mulac16js.l", ICLASS_AE_MULAC16JS_L, + 0, + Opcode_ae_mulac16js_l_encode_fns, 0, 0 }, + { "ae_lt16", ICLASS_AE_LT16, + 0, + Opcode_ae_lt16_encode_fns, 0, 0 }, + { "ae_le16", ICLASS_AE_LE16, + 0, + Opcode_ae_le16_encode_fns, 0, 0 }, + { "ae_eq16", ICLASS_AE_EQ16, + 0, + Opcode_ae_eq16_encode_fns, 0, 0 }, + { "ae_lt32", ICLASS_AE_LT32, + 0, + Opcode_ae_lt32_encode_fns, 0, 0 }, + { "ae_le32", ICLASS_AE_LE32, + 0, + Opcode_ae_le32_encode_fns, 0, 0 }, + { "ae_eq32", ICLASS_AE_EQ32, + 0, + Opcode_ae_eq32_encode_fns, 0, 0 }, + { "ae_min32", ICLASS_AE_MIN32, + 0, + Opcode_ae_min32_encode_fns, 0, 0 }, + { "ae_max32", ICLASS_AE_MAX32, + 0, + Opcode_ae_max32_encode_fns, 0, 0 }, + { "ae_minmax32", ICLASS_AE_MINMAX32, + 0, + Opcode_ae_minmax32_encode_fns, 0, 0 }, + { "ae_minmax16", ICLASS_AE_MINMAX16, + 0, + Opcode_ae_minmax16_encode_fns, 0, 0 }, + { "ae_min16", ICLASS_AE_MIN16, + 0, + Opcode_ae_min16_encode_fns, 0, 0 }, + { "ae_max16", ICLASS_AE_MAX16, + 0, + Opcode_ae_max16_encode_fns, 0, 0 }, + { "ae_add64", ICLASS_AE_ADD64, + 0, + Opcode_ae_add64_encode_fns, 0, 0 }, + { "ae_sub64", ICLASS_AE_SUB64, + 0, + Opcode_ae_sub64_encode_fns, 0, 0 }, + { "ae_neg64", ICLASS_AE_NEG64, + 0, + Opcode_ae_neg64_encode_fns, 0, 0 }, + { "ae_abs64", ICLASS_AE_ABS64, + 0, + Opcode_ae_abs64_encode_fns, 0, 0 }, + { "ae_addsq56s", ICLASS_AE_ADDSQ56S, + 0, + Opcode_ae_addsq56s_encode_fns, 0, 0 }, + { "ae_subsq56s", ICLASS_AE_SUBSQ56S, + 0, + Opcode_ae_subsq56s_encode_fns, 0, 0 }, + { "ae_add64s", ICLASS_AE_ADD64S, + 0, + Opcode_ae_add64s_encode_fns, 0, 0 }, + { "ae_sub64s", ICLASS_AE_SUB64S, + 0, + Opcode_ae_sub64s_encode_fns, 0, 0 }, + { "ae_negsq56s", ICLASS_AE_NEGSQ56S, + 0, + Opcode_ae_negsq56s_encode_fns, 0, 0 }, + { "ae_abssq56s", ICLASS_AE_ABSSQ56S, + 0, + Opcode_ae_abssq56s_encode_fns, 0, 0 }, + { "ae_neg64s", ICLASS_AE_NEG64S, + 0, + Opcode_ae_neg64s_encode_fns, 0, 0 }, + { "ae_abs64s", ICLASS_AE_ABS64S, + 0, + Opcode_ae_abs64s_encode_fns, 0, 0 }, + { "ae_and", ICLASS_AE_AND, + 0, + Opcode_ae_and_encode_fns, 0, 0 }, + { "ae_nand", ICLASS_AE_NAND, + 0, + Opcode_ae_nand_encode_fns, 0, 0 }, + { "ae_or", ICLASS_AE_OR, + 0, + Opcode_ae_or_encode_fns, 0, 0 }, + { "ae_xor", ICLASS_AE_XOR, + 0, + Opcode_ae_xor_encode_fns, 0, 0 }, + { "ae_slai24", ICLASS_AE_SLAI24, + 0, + Opcode_ae_slai24_encode_fns, 0, 0 }, + { "ae_srli24", ICLASS_AE_SRLI24, + 0, + Opcode_ae_srli24_encode_fns, 0, 0 }, + { "ae_srai24", ICLASS_AE_SRAI24, + 0, + Opcode_ae_srai24_encode_fns, 0, 0 }, + { "ae_slas24", ICLASS_AE_SLAS24, + 0, + Opcode_ae_slas24_encode_fns, 0, 0 }, + { "ae_srls24", ICLASS_AE_SRLS24, + 0, + Opcode_ae_srls24_encode_fns, 0, 0 }, + { "ae_sras24", ICLASS_AE_SRAS24, + 0, + Opcode_ae_sras24_encode_fns, 0, 0 }, + { "ae_srai16", ICLASS_AE_SRAI16, + 0, + Opcode_ae_srai16_encode_fns, 0, 0 }, + { "ae_srai16r", ICLASS_AE_SRAI16R, + 0, + Opcode_ae_srai16r_encode_fns, 0, 0 }, + { "ae_slai32", ICLASS_AE_SLAI32, + 0, + Opcode_ae_slai32_encode_fns, 0, 0 }, + { "ae_srli32", ICLASS_AE_SRLI32, + 0, + Opcode_ae_srli32_encode_fns, 0, 0 }, + { "ae_srai32", ICLASS_AE_SRAI32, + 0, + Opcode_ae_srai32_encode_fns, 0, 0 }, + { "ae_srai32r", ICLASS_AE_SRAI32R, + 0, + Opcode_ae_srai32r_encode_fns, 0, 0 }, + { "ae_slas32", ICLASS_AE_SLAS32, + 0, + Opcode_ae_slas32_encode_fns, 0, 0 }, + { "ae_srls32", ICLASS_AE_SRLS32, + 0, + Opcode_ae_srls32_encode_fns, 0, 0 }, + { "ae_sras32", ICLASS_AE_SRAS32, + 0, + Opcode_ae_sras32_encode_fns, 0, 0 }, + { "ae_slaa32", ICLASS_AE_SLAA32, + 0, + Opcode_ae_slaa32_encode_fns, 0, 0 }, + { "ae_srla32", ICLASS_AE_SRLA32, + 0, + Opcode_ae_srla32_encode_fns, 0, 0 }, + { "ae_sraa32", ICLASS_AE_SRAA32, + 0, + Opcode_ae_sraa32_encode_fns, 0, 0 }, + { "ae_slai16s", ICLASS_AE_SLAI16S, + 0, + Opcode_ae_slai16s_encode_fns, 0, 0 }, + { "ae_slaa16s", ICLASS_AE_SLAA16S, + 0, + Opcode_ae_slaa16s_encode_fns, 0, 0 }, + { "ae_sraa16s", ICLASS_AE_SRAA16S, + 0, + Opcode_ae_sraa16s_encode_fns, 0, 0 }, + { "ae_sraa16rs", ICLASS_AE_SRAA16RS, + 0, + Opcode_ae_sraa16rs_encode_fns, 0, 0 }, + { "ae_slai24s", ICLASS_AE_SLAI24S, + 0, + Opcode_ae_slai24s_encode_fns, 0, 0 }, + { "ae_slas24s", ICLASS_AE_SLAS24S, + 0, + Opcode_ae_slas24s_encode_fns, 0, 0 }, + { "ae_slai32s", ICLASS_AE_SLAI32S, + 0, + Opcode_ae_slai32s_encode_fns, 0, 0 }, + { "ae_slas32s", ICLASS_AE_SLAS32S, + 0, + Opcode_ae_slas32s_encode_fns, 0, 0 }, + { "ae_slaa32s", ICLASS_AE_SLAA32S, + 0, + Opcode_ae_slaa32s_encode_fns, 0, 0 }, + { "ae_sraa32s", ICLASS_AE_SRAA32S, + 0, + Opcode_ae_sraa32s_encode_fns, 0, 0 }, + { "ae_sraa32rs", ICLASS_AE_SRAA32RS, + 0, + Opcode_ae_sraa32rs_encode_fns, 0, 0 }, + { "ae_slasq56", ICLASS_AE_SLASQ56, + 0, + Opcode_ae_slasq56_encode_fns, 0, 0 }, + { "ae_srlsq56", ICLASS_AE_SRLSQ56, + 0, + Opcode_ae_srlsq56_encode_fns, 0, 0 }, + { "ae_srasq56", ICLASS_AE_SRASQ56, + 0, + Opcode_ae_srasq56_encode_fns, 0, 0 }, + { "ae_slaaq56", ICLASS_AE_SLAAQ56, + 0, + Opcode_ae_slaaq56_encode_fns, 0, 0 }, + { "ae_srlaq56", ICLASS_AE_SRLAQ56, + 0, + Opcode_ae_srlaq56_encode_fns, 0, 0 }, + { "ae_sraaq56", ICLASS_AE_SRAAQ56, + 0, + Opcode_ae_sraaq56_encode_fns, 0, 0 }, + { "ae_slai64", ICLASS_AE_SLAI64, + 0, + Opcode_ae_slai64_encode_fns, 0, 0 }, + { "ae_srli64", ICLASS_AE_SRLI64, + 0, + Opcode_ae_srli64_encode_fns, 0, 0 }, + { "ae_srai64", ICLASS_AE_SRAI64, + 0, + Opcode_ae_srai64_encode_fns, 0, 0 }, + { "ae_slas64", ICLASS_AE_SLAS64, + 0, + Opcode_ae_slas64_encode_fns, 0, 0 }, + { "ae_srls64", ICLASS_AE_SRLS64, + 0, + Opcode_ae_srls64_encode_fns, 0, 0 }, + { "ae_sras64", ICLASS_AE_SRAS64, + 0, + Opcode_ae_sras64_encode_fns, 0, 0 }, + { "ae_slaa64", ICLASS_AE_SLAA64, + 0, + Opcode_ae_slaa64_encode_fns, 0, 0 }, + { "ae_srla64", ICLASS_AE_SRLA64, + 0, + Opcode_ae_srla64_encode_fns, 0, 0 }, + { "ae_sraa64", ICLASS_AE_SRAA64, + 0, + Opcode_ae_sraa64_encode_fns, 0, 0 }, + { "ae_slaisq56s", ICLASS_AE_SLAISQ56S, + 0, + Opcode_ae_slaisq56s_encode_fns, 0, 0 }, + { "ae_slassq56s", ICLASS_AE_SLASSQ56S, + 0, + Opcode_ae_slassq56s_encode_fns, 0, 0 }, + { "ae_slaasq56s", ICLASS_AE_SLAASQ56S, + 0, + Opcode_ae_slaasq56s_encode_fns, 0, 0 }, + { "ae_slai64s", ICLASS_AE_SLAI64S, + 0, + Opcode_ae_slai64s_encode_fns, 0, 0 }, + { "ae_slas64s", ICLASS_AE_SLAS64S, + 0, + Opcode_ae_slas64s_encode_fns, 0, 0 }, + { "ae_slaa64s", ICLASS_AE_SLAA64S, + 0, + Opcode_ae_slaa64s_encode_fns, 0, 0 }, + { "ae_lt64", ICLASS_AE_LT64, + 0, + Opcode_ae_lt64_encode_fns, 0, 0 }, + { "ae_le64", ICLASS_AE_LE64, + 0, + Opcode_ae_le64_encode_fns, 0, 0 }, + { "ae_eq64", ICLASS_AE_EQ64, + 0, + Opcode_ae_eq64_encode_fns, 0, 0 }, + { "ae_max64", ICLASS_AE_MAX64, + 0, + Opcode_ae_max64_encode_fns, 0, 0 }, + { "ae_min64", ICLASS_AE_MIN64, + 0, + Opcode_ae_min64_encode_fns, 0, 0 }, + { "ae_nsa64", ICLASS_AE_NSA64, + 0, + Opcode_ae_nsa64_encode_fns, 0, 0 }, + { "ae_nsaz16.0", ICLASS_AE_NSAZ16_0, + 0, + Opcode_ae_nsaz16_0_encode_fns, 0, 0 }, + { "ae_nsaz32.l", ICLASS_AE_NSAZ32_L, + 0, + Opcode_ae_nsaz32_l_encode_fns, 0, 0 }, + { "ae_muls32f48p16s.ll", ICLASS_AE_MULS32F48P16S_LL, + 0, + Opcode_ae_muls32f48p16s_ll_encode_fns, 0, 0 }, + { "ae_mulf32s.ll", ICLASS_AE_MULF32S_LL, + 0, + Opcode_ae_mulf32s_ll_encode_fns, 0, 0 }, + { "ae_mul32.ll", ICLASS_AE_MUL32_LL, + 0, + Opcode_ae_mul32_ll_encode_fns, 0, 0 }, + { "ae_mulf32r.ll", ICLASS_AE_MULF32R_LL, + 0, + Opcode_ae_mulf32r_ll_encode_fns, 0, 0 }, + { "ae_mulf32ra.ll", ICLASS_AE_MULF32RA_LL, + 0, + Opcode_ae_mulf32ra_ll_encode_fns, 0, 0 }, + { "ae_muls32f48p16s.lh", ICLASS_AE_MULS32F48P16S_LH, + 0, + Opcode_ae_muls32f48p16s_lh_encode_fns, 0, 0 }, + { "ae_mulf32s.lh", ICLASS_AE_MULF32S_LH, + 0, + Opcode_ae_mulf32s_lh_encode_fns, 0, 0 }, + { "ae_mul32.lh", ICLASS_AE_MUL32_LH, + 0, + Opcode_ae_mul32_lh_encode_fns, 0, 0 }, + { "ae_mulf32r.lh", ICLASS_AE_MULF32R_LH, + 0, + Opcode_ae_mulf32r_lh_encode_fns, 0, 0 }, + { "ae_mulf32ra.lh", ICLASS_AE_MULF32RA_LH, + 0, + Opcode_ae_mulf32ra_lh_encode_fns, 0, 0 }, + { "ae_muls32f48p16s.hh", ICLASS_AE_MULS32F48P16S_HH, + 0, + Opcode_ae_muls32f48p16s_hh_encode_fns, 0, 0 }, + { "ae_mulf32s.hh", ICLASS_AE_MULF32S_HH, + 0, + Opcode_ae_mulf32s_hh_encode_fns, 0, 0 }, + { "ae_mul32.hh", ICLASS_AE_MUL32_HH, + 0, + Opcode_ae_mul32_hh_encode_fns, 0, 0 }, + { "ae_mulf32r.hh", ICLASS_AE_MULF32R_HH, + 0, + Opcode_ae_mulf32r_hh_encode_fns, 0, 0 }, + { "ae_mulf32ra.hh", ICLASS_AE_MULF32RA_HH, + 0, + Opcode_ae_mulf32ra_hh_encode_fns, 0, 0 }, + { "ae_mulas32f48p16s.ll", ICLASS_AE_MULAS32F48P16S_LL, + 0, + Opcode_ae_mulas32f48p16s_ll_encode_fns, 0, 0 }, + { "ae_mulaf32s.ll", ICLASS_AE_MULAF32S_LL, + 0, + Opcode_ae_mulaf32s_ll_encode_fns, 0, 0 }, + { "ae_mula32.ll", ICLASS_AE_MULA32_LL, + 0, + Opcode_ae_mula32_ll_encode_fns, 0, 0 }, + { "ae_mulaf32r.ll", ICLASS_AE_MULAF32R_LL, + 0, + Opcode_ae_mulaf32r_ll_encode_fns, 0, 0 }, + { "ae_mulaf32ra.ll", ICLASS_AE_MULAF32RA_LL, + 0, + Opcode_ae_mulaf32ra_ll_encode_fns, 0, 0 }, + { "ae_mulas32f48p16s.lh", ICLASS_AE_MULAS32F48P16S_LH, + 0, + Opcode_ae_mulas32f48p16s_lh_encode_fns, 0, 0 }, + { "ae_mulaf32s.lh", ICLASS_AE_MULAF32S_LH, + 0, + Opcode_ae_mulaf32s_lh_encode_fns, 0, 0 }, + { "ae_mula32.lh", ICLASS_AE_MULA32_LH, + 0, + Opcode_ae_mula32_lh_encode_fns, 0, 0 }, + { "ae_mulaf32r.lh", ICLASS_AE_MULAF32R_LH, + 0, + Opcode_ae_mulaf32r_lh_encode_fns, 0, 0 }, + { "ae_mulaf32ra.lh", ICLASS_AE_MULAF32RA_LH, + 0, + Opcode_ae_mulaf32ra_lh_encode_fns, 0, 0 }, + { "ae_mulas32f48p16s.hh", ICLASS_AE_MULAS32F48P16S_HH, + 0, + Opcode_ae_mulas32f48p16s_hh_encode_fns, 0, 0 }, + { "ae_mulaf32s.hh", ICLASS_AE_MULAF32S_HH, + 0, + Opcode_ae_mulaf32s_hh_encode_fns, 0, 0 }, + { "ae_mula32.hh", ICLASS_AE_MULA32_HH, + 0, + Opcode_ae_mula32_hh_encode_fns, 0, 0 }, + { "ae_mulaf32r.hh", ICLASS_AE_MULAF32R_HH, + 0, + Opcode_ae_mulaf32r_hh_encode_fns, 0, 0 }, + { "ae_mulaf32ra.hh", ICLASS_AE_MULAF32RA_HH, + 0, + Opcode_ae_mulaf32ra_hh_encode_fns, 0, 0 }, + { "ae_mulss32f48p16s.ll", ICLASS_AE_MULSS32F48P16S_LL, + 0, + Opcode_ae_mulss32f48p16s_ll_encode_fns, 0, 0 }, + { "ae_mulsf32s.ll", ICLASS_AE_MULSF32S_LL, + 0, + Opcode_ae_mulsf32s_ll_encode_fns, 0, 0 }, + { "ae_muls32.ll", ICLASS_AE_MULS32_LL, + 0, + Opcode_ae_muls32_ll_encode_fns, 0, 0 }, + { "ae_mulsf32r.ll", ICLASS_AE_MULSF32R_LL, + 0, + Opcode_ae_mulsf32r_ll_encode_fns, 0, 0 }, + { "ae_mulsf32ra.ll", ICLASS_AE_MULSF32RA_LL, + 0, + Opcode_ae_mulsf32ra_ll_encode_fns, 0, 0 }, + { "ae_mulss32f48p16s.lh", ICLASS_AE_MULSS32F48P16S_LH, + 0, + Opcode_ae_mulss32f48p16s_lh_encode_fns, 0, 0 }, + { "ae_mulsf32s.lh", ICLASS_AE_MULSF32S_LH, + 0, + Opcode_ae_mulsf32s_lh_encode_fns, 0, 0 }, + { "ae_muls32.lh", ICLASS_AE_MULS32_LH, + 0, + Opcode_ae_muls32_lh_encode_fns, 0, 0 }, + { "ae_mulsf32r.lh", ICLASS_AE_MULSF32R_LH, + 0, + Opcode_ae_mulsf32r_lh_encode_fns, 0, 0 }, + { "ae_mulsf32ra.lh", ICLASS_AE_MULSF32RA_LH, + 0, + Opcode_ae_mulsf32ra_lh_encode_fns, 0, 0 }, + { "ae_mulss32f48p16s.hh", ICLASS_AE_MULSS32F48P16S_HH, + 0, + Opcode_ae_mulss32f48p16s_hh_encode_fns, 0, 0 }, + { "ae_mulsf32s.hh", ICLASS_AE_MULSF32S_HH, + 0, + Opcode_ae_mulsf32s_hh_encode_fns, 0, 0 }, + { "ae_muls32.hh", ICLASS_AE_MULS32_HH, + 0, + Opcode_ae_muls32_hh_encode_fns, 0, 0 }, + { "ae_mulsf32r.hh", ICLASS_AE_MULSF32R_HH, + 0, + Opcode_ae_mulsf32r_hh_encode_fns, 0, 0 }, + { "ae_mulsf32ra.hh", ICLASS_AE_MULSF32RA_HH, + 0, + Opcode_ae_mulsf32ra_hh_encode_fns, 0, 0 }, + { "ae_mul32u.ll", ICLASS_AE_MUL32U_LL, + 0, + Opcode_ae_mul32u_ll_encode_fns, 0, 0 }, + { "ae_mula32u.ll", ICLASS_AE_MULA32U_LL, + 0, + Opcode_ae_mula32u_ll_encode_fns, 0, 0 }, + { "ae_muls32u.ll", ICLASS_AE_MULS32U_LL, + 0, + Opcode_ae_muls32u_ll_encode_fns, 0, 0 }, + { "ae_mulf16ss.33", ICLASS_AE_MULF16SS_33, + 0, + Opcode_ae_mulf16ss_33_encode_fns, 0, 0 }, + { "ae_mulf16ss.22", ICLASS_AE_MULF16SS_22, + 0, + Opcode_ae_mulf16ss_22_encode_fns, 0, 0 }, + { "ae_mulf16ss.32", ICLASS_AE_MULF16SS_32, + 0, + Opcode_ae_mulf16ss_32_encode_fns, 0, 0 }, + { "ae_mulf16ss.21", ICLASS_AE_MULF16SS_21, + 0, + Opcode_ae_mulf16ss_21_encode_fns, 0, 0 }, + { "ae_mulf16ss.31", ICLASS_AE_MULF16SS_31, + 0, + Opcode_ae_mulf16ss_31_encode_fns, 0, 0 }, + { "ae_mulf16ss.30", ICLASS_AE_MULF16SS_30, + 0, + Opcode_ae_mulf16ss_30_encode_fns, 0, 0 }, + { "ae_mulf16ss.10", ICLASS_AE_MULF16SS_10, + 0, + Opcode_ae_mulf16ss_10_encode_fns, 0, 0 }, + { "ae_mulf16ss.20", ICLASS_AE_MULF16SS_20, + 0, + Opcode_ae_mulf16ss_20_encode_fns, 0, 0 }, + { "ae_mulf16ss.11", ICLASS_AE_MULF16SS_11, + 0, + Opcode_ae_mulf16ss_11_encode_fns, 0, 0 }, + { "ae_mulf16ss.00", ICLASS_AE_MULF16SS_00, + 0, + Opcode_ae_mulf16ss_00_encode_fns, 0, 0 }, + { "ae_mulsf16ss.33", ICLASS_AE_MULSF16SS_33, + 0, + Opcode_ae_mulsf16ss_33_encode_fns, 0, 0 }, + { "ae_mulsf16ss.22", ICLASS_AE_MULSF16SS_22, + 0, + Opcode_ae_mulsf16ss_22_encode_fns, 0, 0 }, + { "ae_mulsf16ss.32", ICLASS_AE_MULSF16SS_32, + 0, + Opcode_ae_mulsf16ss_32_encode_fns, 0, 0 }, + { "ae_mulsf16ss.21", ICLASS_AE_MULSF16SS_21, + 0, + Opcode_ae_mulsf16ss_21_encode_fns, 0, 0 }, + { "ae_mulsf16ss.31", ICLASS_AE_MULSF16SS_31, + 0, + Opcode_ae_mulsf16ss_31_encode_fns, 0, 0 }, + { "ae_mulsf16ss.30", ICLASS_AE_MULSF16SS_30, + 0, + Opcode_ae_mulsf16ss_30_encode_fns, 0, 0 }, + { "ae_mulsf16ss.10", ICLASS_AE_MULSF16SS_10, + 0, + Opcode_ae_mulsf16ss_10_encode_fns, 0, 0 }, + { "ae_mulsf16ss.20", ICLASS_AE_MULSF16SS_20, + 0, + Opcode_ae_mulsf16ss_20_encode_fns, 0, 0 }, + { "ae_mulsf16ss.11", ICLASS_AE_MULSF16SS_11, + 0, + Opcode_ae_mulsf16ss_11_encode_fns, 0, 0 }, + { "ae_mulsf16ss.00", ICLASS_AE_MULSF16SS_00, + 0, + Opcode_ae_mulsf16ss_00_encode_fns, 0, 0 }, + { "ae_mulaf16ss.33", ICLASS_AE_MULAF16SS_33, + 0, + Opcode_ae_mulaf16ss_33_encode_fns, 0, 0 }, + { "ae_mulaf16ss.22", ICLASS_AE_MULAF16SS_22, + 0, + Opcode_ae_mulaf16ss_22_encode_fns, 0, 0 }, + { "ae_mulaf16ss.32", ICLASS_AE_MULAF16SS_32, + 0, + Opcode_ae_mulaf16ss_32_encode_fns, 0, 0 }, + { "ae_mulaf16ss.21", ICLASS_AE_MULAF16SS_21, + 0, + Opcode_ae_mulaf16ss_21_encode_fns, 0, 0 }, + { "ae_mulaf16ss.31", ICLASS_AE_MULAF16SS_31, + 0, + Opcode_ae_mulaf16ss_31_encode_fns, 0, 0 }, + { "ae_mulaf16ss.30", ICLASS_AE_MULAF16SS_30, + 0, + Opcode_ae_mulaf16ss_30_encode_fns, 0, 0 }, + { "ae_mulaf16ss.10", ICLASS_AE_MULAF16SS_10, + 0, + Opcode_ae_mulaf16ss_10_encode_fns, 0, 0 }, + { "ae_mulaf16ss.20", ICLASS_AE_MULAF16SS_20, + 0, + Opcode_ae_mulaf16ss_20_encode_fns, 0, 0 }, + { "ae_mulaf16ss.11", ICLASS_AE_MULAF16SS_11, + 0, + Opcode_ae_mulaf16ss_11_encode_fns, 0, 0 }, + { "ae_mulaf16ss.00", ICLASS_AE_MULAF16SS_00, + 0, + Opcode_ae_mulaf16ss_00_encode_fns, 0, 0 }, + { "ae_mul16s.00", ICLASS_AE_MUL16S_00, + 0, + Opcode_ae_mul16s_00_encode_fns, 0, 0 }, + { "ae_mula16s.00", ICLASS_AE_MULA16S_00, + 0, + Opcode_ae_mula16s_00_encode_fns, 0, 0 }, + { "ae_muls16s.00", ICLASS_AE_MULS16S_00, + 0, + Opcode_ae_muls16s_00_encode_fns, 0, 0 }, + { "ae_mulaafd16ss.33_22", ICLASS_AE_MULAAFD16SS_33_22, + 0, + Opcode_ae_mulaafd16ss_33_22_encode_fns, 0, 0 }, + { "ae_mulaafd16ss.13_02", ICLASS_AE_MULAAFD16SS_13_02, + 0, + Opcode_ae_mulaafd16ss_13_02_encode_fns, 0, 0 }, + { "ae_mulaafd16ss.11_00", ICLASS_AE_MULAAFD16SS_11_00, + 0, + Opcode_ae_mulaafd16ss_11_00_encode_fns, 0, 0 }, + { "ae_mulssfd16ss.33_22", ICLASS_AE_MULSSFD16SS_33_22, + 0, + Opcode_ae_mulssfd16ss_33_22_encode_fns, 0, 0 }, + { "ae_mulssfd16ss.13_02", ICLASS_AE_MULSSFD16SS_13_02, + 0, + Opcode_ae_mulssfd16ss_13_02_encode_fns, 0, 0 }, + { "ae_mulssfd16ss.11_00", ICLASS_AE_MULSSFD16SS_11_00, + 0, + Opcode_ae_mulssfd16ss_11_00_encode_fns, 0, 0 }, + { "ae_mulzaafd16ss.33_22", ICLASS_AE_MULZAAFD16SS_33_22, + 0, + Opcode_ae_mulzaafd16ss_33_22_encode_fns, 0, 0 }, + { "ae_mulzaafd16ss.13_02", ICLASS_AE_MULZAAFD16SS_13_02, + 0, + Opcode_ae_mulzaafd16ss_13_02_encode_fns, 0, 0 }, + { "ae_mulzaafd16ss.11_00", ICLASS_AE_MULZAAFD16SS_11_00, + 0, + Opcode_ae_mulzaafd16ss_11_00_encode_fns, 0, 0 }, + { "ae_mulzssfd16ss.33_22", ICLASS_AE_MULZSSFD16SS_33_22, + 0, + Opcode_ae_mulzssfd16ss_33_22_encode_fns, 0, 0 }, + { "ae_mulzssfd16ss.13_02", ICLASS_AE_MULZSSFD16SS_13_02, + 0, + Opcode_ae_mulzssfd16ss_13_02_encode_fns, 0, 0 }, + { "ae_mulzssfd16ss.11_00", ICLASS_AE_MULZSSFD16SS_11_00, + 0, + Opcode_ae_mulzssfd16ss_11_00_encode_fns, 0, 0 }, + { "ae_mulf48q32sp16s.l", ICLASS_AE_MULF48Q32SP16S_L, + 0, + Opcode_ae_mulf48q32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulf48q32sp16u.l", ICLASS_AE_MULF48Q32SP16U_L, + 0, + Opcode_ae_mulf48q32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulq32sp16s.l", ICLASS_AE_MULQ32SP16S_L, + 0, + Opcode_ae_mulq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulq32sp16u.l", ICLASS_AE_MULQ32SP16U_L, + 0, + Opcode_ae_mulq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulaf48q32sp16s.l", ICLASS_AE_MULAF48Q32SP16S_L, + 0, + Opcode_ae_mulaf48q32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulaf48q32sp16u.l", ICLASS_AE_MULAF48Q32SP16U_L, + 0, + Opcode_ae_mulaf48q32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulaq32sp16s.l", ICLASS_AE_MULAQ32SP16S_L, + 0, + Opcode_ae_mulaq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulaq32sp16u.l", ICLASS_AE_MULAQ32SP16U_L, + 0, + Opcode_ae_mulaq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulsf48q32sp16s.l", ICLASS_AE_MULSF48Q32SP16S_L, + 0, + Opcode_ae_mulsf48q32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulsf48q32sp16u.l", ICLASS_AE_MULSF48Q32SP16U_L, + 0, + Opcode_ae_mulsf48q32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulsq32sp16s.l", ICLASS_AE_MULSQ32SP16S_L, + 0, + Opcode_ae_mulsq32sp16s_l_encode_fns, 0, 0 }, + { "ae_mulsq32sp16u.l", ICLASS_AE_MULSQ32SP16U_L, + 0, + Opcode_ae_mulsq32sp16u_l_encode_fns, 0, 0 }, + { "ae_mulfp24x2ra", ICLASS_AE_MULFP24X2RA, + 0, + Opcode_ae_mulfp24x2ra_encode_fns, 0, 0 }, + { "ae_mulfp24x2r", ICLASS_AE_MULFP24X2R, + 0, + Opcode_ae_mulfp24x2r_encode_fns, 0, 0 }, + { "ae_mulafp24x2ra", ICLASS_AE_MULAFP24X2RA, + 0, + Opcode_ae_mulafp24x2ra_encode_fns, 0, 0 }, + { "ae_mulafp24x2r", ICLASS_AE_MULAFP24X2R, + 0, + Opcode_ae_mulafp24x2r_encode_fns, 0, 0 }, + { "ae_mulsfp24x2ra", ICLASS_AE_MULSFP24X2RA, + 0, + Opcode_ae_mulsfp24x2ra_encode_fns, 0, 0 }, + { "ae_mulsfp24x2r", ICLASS_AE_MULSFP24X2R, + 0, + Opcode_ae_mulsfp24x2r_encode_fns, 0, 0 }, + { "ae_mulzaafd32s.hh.ll", ICLASS_AE_MULZAAFD32S_HH_LL, + 0, + Opcode_ae_mulzaafd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaafd32ra.hh.ll", ICLASS_AE_MULZAAFD32RA_HH_LL, + 0, + Opcode_ae_mulzaafd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaad32.hh.ll", ICLASS_AE_MULZAAD32_HH_LL, + 0, + Opcode_ae_mulzaad32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaafd32s.hl.lh", ICLASS_AE_MULZAAFD32S_HL_LH, + 0, + Opcode_ae_mulzaafd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaafd32ra.hl.lh", ICLASS_AE_MULZAAFD32RA_HL_LH, + 0, + Opcode_ae_mulzaafd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaad32.hl.lh", ICLASS_AE_MULZAAD32_HL_LH, + 0, + Opcode_ae_mulzaad32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasfd32s.hh.ll", ICLASS_AE_MULZASFD32S_HH_LL, + 0, + Opcode_ae_mulzasfd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasfd32ra.hh.ll", ICLASS_AE_MULZASFD32RA_HH_LL, + 0, + Opcode_ae_mulzasfd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasd32.hh.ll", ICLASS_AE_MULZASD32_HH_LL, + 0, + Opcode_ae_mulzasd32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasfd32s.hl.lh", ICLASS_AE_MULZASFD32S_HL_LH, + 0, + Opcode_ae_mulzasfd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasfd32ra.hl.lh", ICLASS_AE_MULZASFD32RA_HL_LH, + 0, + Opcode_ae_mulzasfd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasd32.hl.lh", ICLASS_AE_MULZASD32_HL_LH, + 0, + Opcode_ae_mulzasd32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzsafd32s.hh.ll", ICLASS_AE_MULZSAFD32S_HH_LL, + 0, + Opcode_ae_mulzsafd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsafd32ra.hh.ll", ICLASS_AE_MULZSAFD32RA_HH_LL, + 0, + Opcode_ae_mulzsafd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsad32.hh.ll", ICLASS_AE_MULZSAD32_HH_LL, + 0, + Opcode_ae_mulzsad32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssfd32s.hh.ll", ICLASS_AE_MULZSSFD32S_HH_LL, + 0, + Opcode_ae_mulzssfd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssfd32ra.hh.ll", ICLASS_AE_MULZSSFD32RA_HH_LL, + 0, + Opcode_ae_mulzssfd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssd32.hh.ll", ICLASS_AE_MULZSSD32_HH_LL, + 0, + Opcode_ae_mulzssd32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssfd32s.hl.lh", ICLASS_AE_MULZSSFD32S_HL_LH, + 0, + Opcode_ae_mulzssfd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssfd32ra.hl.lh", ICLASS_AE_MULZSSFD32RA_HL_LH, + 0, + Opcode_ae_mulzssfd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssd32.hl.lh", ICLASS_AE_MULZSSD32_HL_LH, + 0, + Opcode_ae_mulzssd32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaafd32s.hh.ll", ICLASS_AE_MULAAFD32S_HH_LL, + 0, + Opcode_ae_mulaafd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaafd32ra.hh.ll", ICLASS_AE_MULAAFD32RA_HH_LL, + 0, + Opcode_ae_mulaafd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaad32.hh.ll", ICLASS_AE_MULAAD32_HH_LL, + 0, + Opcode_ae_mulaad32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaafd32s.hl.lh", ICLASS_AE_MULAAFD32S_HL_LH, + 0, + Opcode_ae_mulaafd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaafd32ra.hl.lh", ICLASS_AE_MULAAFD32RA_HL_LH, + 0, + Opcode_ae_mulaafd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaad32.hl.lh", ICLASS_AE_MULAAD32_HL_LH, + 0, + Opcode_ae_mulaad32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasfd32s.hh.ll", ICLASS_AE_MULASFD32S_HH_LL, + 0, + Opcode_ae_mulasfd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasfd32ra.hh.ll", ICLASS_AE_MULASFD32RA_HH_LL, + 0, + Opcode_ae_mulasfd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasd32.hh.ll", ICLASS_AE_MULASD32_HH_LL, + 0, + Opcode_ae_mulasd32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasfd32s.hl.lh", ICLASS_AE_MULASFD32S_HL_LH, + 0, + Opcode_ae_mulasfd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasfd32ra.hl.lh", ICLASS_AE_MULASFD32RA_HL_LH, + 0, + Opcode_ae_mulasfd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasd32.hl.lh", ICLASS_AE_MULASD32_HL_LH, + 0, + Opcode_ae_mulasd32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsafd32s.hh.ll", ICLASS_AE_MULSAFD32S_HH_LL, + 0, + Opcode_ae_mulsafd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsafd32ra.hh.ll", ICLASS_AE_MULSAFD32RA_HH_LL, + 0, + Opcode_ae_mulsafd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsad32.hh.ll", ICLASS_AE_MULSAD32_HH_LL, + 0, + Opcode_ae_mulsad32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssfd32s.hh.ll", ICLASS_AE_MULSSFD32S_HH_LL, + 0, + Opcode_ae_mulssfd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssfd32ra.hh.ll", ICLASS_AE_MULSSFD32RA_HH_LL, + 0, + Opcode_ae_mulssfd32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssd32.hh.ll", ICLASS_AE_MULSSD32_HH_LL, + 0, + Opcode_ae_mulssd32_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssfd32s.hl.lh", ICLASS_AE_MULSSFD32S_HL_LH, + 0, + Opcode_ae_mulssfd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssfd32ra.hl.lh", ICLASS_AE_MULSSFD32RA_HL_LH, + 0, + Opcode_ae_mulssfd32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssd32.hl.lh", ICLASS_AE_MULSSD32_HL_LH, + 0, + Opcode_ae_mulssd32_hl_lh_encode_fns, 0, 0 }, + { "ae_mulf32x16.l0", ICLASS_AE_MULF32X16_L0, + 0, + Opcode_ae_mulf32x16_l0_encode_fns, 0, 0 }, + { "ae_mul32x16.l0", ICLASS_AE_MUL32X16_L0, + 0, + Opcode_ae_mul32x16_l0_encode_fns, 0, 0 }, + { "ae_mulf32x16.l1", ICLASS_AE_MULF32X16_L1, + 0, + Opcode_ae_mulf32x16_l1_encode_fns, 0, 0 }, + { "ae_mul32x16.l1", ICLASS_AE_MUL32X16_L1, + 0, + Opcode_ae_mul32x16_l1_encode_fns, 0, 0 }, + { "ae_mulf32x16.l2", ICLASS_AE_MULF32X16_L2, + 0, + Opcode_ae_mulf32x16_l2_encode_fns, 0, 0 }, + { "ae_mul32x16.l2", ICLASS_AE_MUL32X16_L2, + 0, + Opcode_ae_mul32x16_l2_encode_fns, 0, 0 }, + { "ae_mulf32x16.l3", ICLASS_AE_MULF32X16_L3, + 0, + Opcode_ae_mulf32x16_l3_encode_fns, 0, 0 }, + { "ae_mul32x16.l3", ICLASS_AE_MUL32X16_L3, + 0, + Opcode_ae_mul32x16_l3_encode_fns, 0, 0 }, + { "ae_mulf32x16.h0", ICLASS_AE_MULF32X16_H0, + 0, + Opcode_ae_mulf32x16_h0_encode_fns, 0, 0 }, + { "ae_mul32x16.h0", ICLASS_AE_MUL32X16_H0, + 0, + Opcode_ae_mul32x16_h0_encode_fns, 0, 0 }, + { "ae_mulf32x16.h1", ICLASS_AE_MULF32X16_H1, + 0, + Opcode_ae_mulf32x16_h1_encode_fns, 0, 0 }, + { "ae_mul32x16.h1", ICLASS_AE_MUL32X16_H1, + 0, + Opcode_ae_mul32x16_h1_encode_fns, 0, 0 }, + { "ae_mulf32x16.h2", ICLASS_AE_MULF32X16_H2, + 0, + Opcode_ae_mulf32x16_h2_encode_fns, 0, 0 }, + { "ae_mul32x16.h2", ICLASS_AE_MUL32X16_H2, + 0, + Opcode_ae_mul32x16_h2_encode_fns, 0, 0 }, + { "ae_mulf32x16.h3", ICLASS_AE_MULF32X16_H3, + 0, + Opcode_ae_mulf32x16_h3_encode_fns, 0, 0 }, + { "ae_mul32x16.h3", ICLASS_AE_MUL32X16_H3, + 0, + Opcode_ae_mul32x16_h3_encode_fns, 0, 0 }, + { "ae_mulaf32x16.l0", ICLASS_AE_MULAF32X16_L0, + 0, + Opcode_ae_mulaf32x16_l0_encode_fns, 0, 0 }, + { "ae_mula32x16.l0", ICLASS_AE_MULA32X16_L0, + 0, + Opcode_ae_mula32x16_l0_encode_fns, 0, 0 }, + { "ae_mulaf32x16.l1", ICLASS_AE_MULAF32X16_L1, + 0, + Opcode_ae_mulaf32x16_l1_encode_fns, 0, 0 }, + { "ae_mula32x16.l1", ICLASS_AE_MULA32X16_L1, + 0, + Opcode_ae_mula32x16_l1_encode_fns, 0, 0 }, + { "ae_mulaf32x16.l2", ICLASS_AE_MULAF32X16_L2, + 0, + Opcode_ae_mulaf32x16_l2_encode_fns, 0, 0 }, + { "ae_mula32x16.l2", ICLASS_AE_MULA32X16_L2, + 0, + Opcode_ae_mula32x16_l2_encode_fns, 0, 0 }, + { "ae_mulaf32x16.l3", ICLASS_AE_MULAF32X16_L3, + 0, + Opcode_ae_mulaf32x16_l3_encode_fns, 0, 0 }, + { "ae_mula32x16.l3", ICLASS_AE_MULA32X16_L3, + 0, + Opcode_ae_mula32x16_l3_encode_fns, 0, 0 }, + { "ae_mulaf32x16.h0", ICLASS_AE_MULAF32X16_H0, + 0, + Opcode_ae_mulaf32x16_h0_encode_fns, 0, 0 }, + { "ae_mula32x16.h0", ICLASS_AE_MULA32X16_H0, + 0, + Opcode_ae_mula32x16_h0_encode_fns, 0, 0 }, + { "ae_mulaf32x16.h1", ICLASS_AE_MULAF32X16_H1, + 0, + Opcode_ae_mulaf32x16_h1_encode_fns, 0, 0 }, + { "ae_mula32x16.h1", ICLASS_AE_MULA32X16_H1, + 0, + Opcode_ae_mula32x16_h1_encode_fns, 0, 0 }, + { "ae_mulaf32x16.h2", ICLASS_AE_MULAF32X16_H2, + 0, + Opcode_ae_mulaf32x16_h2_encode_fns, 0, 0 }, + { "ae_mula32x16.h2", ICLASS_AE_MULA32X16_H2, + 0, + Opcode_ae_mula32x16_h2_encode_fns, 0, 0 }, + { "ae_mulaf32x16.h3", ICLASS_AE_MULAF32X16_H3, + 0, + Opcode_ae_mulaf32x16_h3_encode_fns, 0, 0 }, + { "ae_mula32x16.h3", ICLASS_AE_MULA32X16_H3, + 0, + Opcode_ae_mula32x16_h3_encode_fns, 0, 0 }, + { "ae_mulsf32x16.l0", ICLASS_AE_MULSF32X16_L0, + 0, + Opcode_ae_mulsf32x16_l0_encode_fns, 0, 0 }, + { "ae_muls32x16.l0", ICLASS_AE_MULS32X16_L0, + 0, + Opcode_ae_muls32x16_l0_encode_fns, 0, 0 }, + { "ae_mulsf32x16.l1", ICLASS_AE_MULSF32X16_L1, + 0, + Opcode_ae_mulsf32x16_l1_encode_fns, 0, 0 }, + { "ae_muls32x16.l1", ICLASS_AE_MULS32X16_L1, + 0, + Opcode_ae_muls32x16_l1_encode_fns, 0, 0 }, + { "ae_mulsf32x16.l2", ICLASS_AE_MULSF32X16_L2, + 0, + Opcode_ae_mulsf32x16_l2_encode_fns, 0, 0 }, + { "ae_muls32x16.l2", ICLASS_AE_MULS32X16_L2, + 0, + Opcode_ae_muls32x16_l2_encode_fns, 0, 0 }, + { "ae_mulsf32x16.l3", ICLASS_AE_MULSF32X16_L3, + 0, + Opcode_ae_mulsf32x16_l3_encode_fns, 0, 0 }, + { "ae_muls32x16.l3", ICLASS_AE_MULS32X16_L3, + 0, + Opcode_ae_muls32x16_l3_encode_fns, 0, 0 }, + { "ae_mulsf32x16.h0", ICLASS_AE_MULSF32X16_H0, + 0, + Opcode_ae_mulsf32x16_h0_encode_fns, 0, 0 }, + { "ae_muls32x16.h0", ICLASS_AE_MULS32X16_H0, + 0, + Opcode_ae_muls32x16_h0_encode_fns, 0, 0 }, + { "ae_mulsf32x16.h1", ICLASS_AE_MULSF32X16_H1, + 0, + Opcode_ae_mulsf32x16_h1_encode_fns, 0, 0 }, + { "ae_muls32x16.h1", ICLASS_AE_MULS32X16_H1, + 0, + Opcode_ae_muls32x16_h1_encode_fns, 0, 0 }, + { "ae_mulsf32x16.h2", ICLASS_AE_MULSF32X16_H2, + 0, + Opcode_ae_mulsf32x16_h2_encode_fns, 0, 0 }, + { "ae_muls32x16.h2", ICLASS_AE_MULS32X16_H2, + 0, + Opcode_ae_muls32x16_h2_encode_fns, 0, 0 }, + { "ae_mulsf32x16.h3", ICLASS_AE_MULSF32X16_H3, + 0, + Opcode_ae_mulsf32x16_h3_encode_fns, 0, 0 }, + { "ae_muls32x16.h3", ICLASS_AE_MULS32X16_H3, + 0, + Opcode_ae_muls32x16_h3_encode_fns, 0, 0 }, + { "ae_mulaafd32x16.h3.l2", ICLASS_AE_MULAAFD32X16_H3_L2, + 0, + Opcode_ae_mulaafd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulaad32x16.h3.l2", ICLASS_AE_MULAAD32X16_H3_L2, + 0, + Opcode_ae_mulaad32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulaafd32x16.h1.l0", ICLASS_AE_MULAAFD32X16_H1_L0, + 0, + Opcode_ae_mulaafd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulaad32x16.h1.l0", ICLASS_AE_MULAAD32X16_H1_L0, + 0, + Opcode_ae_mulaad32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulasfd32x16.h3.l2", ICLASS_AE_MULASFD32X16_H3_L2, + 0, + Opcode_ae_mulasfd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulasd32x16.h3.l2", ICLASS_AE_MULASD32X16_H3_L2, + 0, + Opcode_ae_mulasd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulasfd32x16.h1.l0", ICLASS_AE_MULASFD32X16_H1_L0, + 0, + Opcode_ae_mulasfd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulasd32x16.h1.l0", ICLASS_AE_MULASD32X16_H1_L0, + 0, + Opcode_ae_mulasd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulsafd32x16.h3.l2", ICLASS_AE_MULSAFD32X16_H3_L2, + 0, + Opcode_ae_mulsafd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulsad32x16.h3.l2", ICLASS_AE_MULSAD32X16_H3_L2, + 0, + Opcode_ae_mulsad32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulsafd32x16.h1.l0", ICLASS_AE_MULSAFD32X16_H1_L0, + 0, + Opcode_ae_mulsafd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulsad32x16.h1.l0", ICLASS_AE_MULSAD32X16_H1_L0, + 0, + Opcode_ae_mulsad32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulssfd32x16.h3.l2", ICLASS_AE_MULSSFD32X16_H3_L2, + 0, + Opcode_ae_mulssfd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulssd32x16.h3.l2", ICLASS_AE_MULSSD32X16_H3_L2, + 0, + Opcode_ae_mulssd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulssfd32x16.h1.l0", ICLASS_AE_MULSSFD32X16_H1_L0, + 0, + Opcode_ae_mulssfd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulssd32x16.h1.l0", ICLASS_AE_MULSSD32X16_H1_L0, + 0, + Opcode_ae_mulssd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzaafd32x16.h3.l2", ICLASS_AE_MULZAAFD32X16_H3_L2, + 0, + Opcode_ae_mulzaafd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzaad32x16.h3.l2", ICLASS_AE_MULZAAD32X16_H3_L2, + 0, + Opcode_ae_mulzaad32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzaafd32x16.h1.l0", ICLASS_AE_MULZAAFD32X16_H1_L0, + 0, + Opcode_ae_mulzaafd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzaad32x16.h1.l0", ICLASS_AE_MULZAAD32X16_H1_L0, + 0, + Opcode_ae_mulzaad32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzasfd32x16.h3.l2", ICLASS_AE_MULZASFD32X16_H3_L2, + 0, + Opcode_ae_mulzasfd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzasd32x16.h3.l2", ICLASS_AE_MULZASD32X16_H3_L2, + 0, + Opcode_ae_mulzasd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzasfd32x16.h1.l0", ICLASS_AE_MULZASFD32X16_H1_L0, + 0, + Opcode_ae_mulzasfd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzasd32x16.h1.l0", ICLASS_AE_MULZASD32X16_H1_L0, + 0, + Opcode_ae_mulzasd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzsafd32x16.h3.l2", ICLASS_AE_MULZSAFD32X16_H3_L2, + 0, + Opcode_ae_mulzsafd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzsad32x16.h3.l2", ICLASS_AE_MULZSAD32X16_H3_L2, + 0, + Opcode_ae_mulzsad32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzsafd32x16.h1.l0", ICLASS_AE_MULZSAFD32X16_H1_L0, + 0, + Opcode_ae_mulzsafd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzsad32x16.h1.l0", ICLASS_AE_MULZSAD32X16_H1_L0, + 0, + Opcode_ae_mulzsad32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzssfd32x16.h3.l2", ICLASS_AE_MULZSSFD32X16_H3_L2, + 0, + Opcode_ae_mulzssfd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzssd32x16.h3.l2", ICLASS_AE_MULZSSD32X16_H3_L2, + 0, + Opcode_ae_mulzssd32x16_h3_l2_encode_fns, 0, 0 }, + { "ae_mulzssfd32x16.h1.l0", ICLASS_AE_MULZSSFD32X16_H1_L0, + 0, + Opcode_ae_mulzssfd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzssd32x16.h1.l0", ICLASS_AE_MULZSSD32X16_H1_L0, + 0, + Opcode_ae_mulzssd32x16_h1_l0_encode_fns, 0, 0 }, + { "ae_mulzaafd32x16.h2.l3", ICLASS_AE_MULZAAFD32X16_H2_L3, + 0, + Opcode_ae_mulzaafd32x16_h2_l3_encode_fns, 0, 0 }, + { "ae_mulzaafd32x16.h0.l1", ICLASS_AE_MULZAAFD32X16_H0_L1, + 0, + Opcode_ae_mulzaafd32x16_h0_l1_encode_fns, 0, 0 }, + { "ae_mulaafd32x16.h2.l3", ICLASS_AE_MULAAFD32X16_H2_L3, + 0, + Opcode_ae_mulaafd32x16_h2_l3_encode_fns, 0, 0 }, + { "ae_mulaafd32x16.h0.l1", ICLASS_AE_MULAAFD32X16_H0_L1, + 0, + Opcode_ae_mulaafd32x16_h0_l1_encode_fns, 0, 0 }, + { "ae_mulzaad32x16.h2.l3", ICLASS_AE_MULZAAD32X16_H2_L3, + 0, + Opcode_ae_mulzaad32x16_h2_l3_encode_fns, 0, 0 }, + { "ae_mulzaad32x16.h0.l1", ICLASS_AE_MULZAAD32X16_H0_L1, + 0, + Opcode_ae_mulzaad32x16_h0_l1_encode_fns, 0, 0 }, + { "ae_mulaad32x16.h2.l3", ICLASS_AE_MULAAD32X16_H2_L3, + 0, + Opcode_ae_mulaad32x16_h2_l3_encode_fns, 0, 0 }, + { "ae_mulaad32x16.h0.l1", ICLASS_AE_MULAAD32X16_H0_L1, + 0, + Opcode_ae_mulaad32x16_h0_l1_encode_fns, 0, 0 }, + { "ae_mulp32x16x2.h", ICLASS_AE_MULP32X16X2_H, + 0, + Opcode_ae_mulp32x16x2_h_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2rs.h", ICLASS_AE_MULFP32X16X2RS_H, + 0, + Opcode_ae_mulfp32x16x2rs_h_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2ras.h", ICLASS_AE_MULFP32X16X2RAS_H, + 0, + Opcode_ae_mulfp32x16x2ras_h_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2s.h", ICLASS_AE_MULFP32X16X2S_H, + 0, + Opcode_ae_mulfp32x16x2s_h_encode_fns, 0, 0 }, + { "ae_mulp32x16x2.l", ICLASS_AE_MULP32X16X2_L, + 0, + Opcode_ae_mulp32x16x2_l_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2rs.l", ICLASS_AE_MULFP32X16X2RS_L, + 0, + Opcode_ae_mulfp32x16x2rs_l_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2ras.l", ICLASS_AE_MULFP32X16X2RAS_L, + 0, + Opcode_ae_mulfp32x16x2ras_l_encode_fns, 0, 0 }, + { "ae_mulfp32x16x2s.l", ICLASS_AE_MULFP32X16X2S_L, + 0, + Opcode_ae_mulfp32x16x2s_l_encode_fns, 0, 0 }, + { "ae_mulap32x16x2.h", ICLASS_AE_MULAP32X16X2_H, + 0, + Opcode_ae_mulap32x16x2_h_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2rs.h", ICLASS_AE_MULAFP32X16X2RS_H, + 0, + Opcode_ae_mulafp32x16x2rs_h_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2ras.h", ICLASS_AE_MULAFP32X16X2RAS_H, + 0, + Opcode_ae_mulafp32x16x2ras_h_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2s.h", ICLASS_AE_MULAFP32X16X2S_H, + 0, + Opcode_ae_mulafp32x16x2s_h_encode_fns, 0, 0 }, + { "ae_mulap32x16x2.l", ICLASS_AE_MULAP32X16X2_L, + 0, + Opcode_ae_mulap32x16x2_l_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2rs.l", ICLASS_AE_MULAFP32X16X2RS_L, + 0, + Opcode_ae_mulafp32x16x2rs_l_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2ras.l", ICLASS_AE_MULAFP32X16X2RAS_L, + 0, + Opcode_ae_mulafp32x16x2ras_l_encode_fns, 0, 0 }, + { "ae_mulafp32x16x2s.l", ICLASS_AE_MULAFP32X16X2S_L, + 0, + Opcode_ae_mulafp32x16x2s_l_encode_fns, 0, 0 }, + { "ae_mulsp32x16x2.h", ICLASS_AE_MULSP32X16X2_H, + 0, + Opcode_ae_mulsp32x16x2_h_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2rs.h", ICLASS_AE_MULSFP32X16X2RS_H, + 0, + Opcode_ae_mulsfp32x16x2rs_h_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2ras.h", ICLASS_AE_MULSFP32X16X2RAS_H, + 0, + Opcode_ae_mulsfp32x16x2ras_h_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2s.h", ICLASS_AE_MULSFP32X16X2S_H, + 0, + Opcode_ae_mulsfp32x16x2s_h_encode_fns, 0, 0 }, + { "ae_mulsp32x16x2.l", ICLASS_AE_MULSP32X16X2_L, + 0, + Opcode_ae_mulsp32x16x2_l_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2rs.l", ICLASS_AE_MULSFP32X16X2RS_L, + 0, + Opcode_ae_mulsfp32x16x2rs_l_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2ras.l", ICLASS_AE_MULSFP32X16X2RAS_L, + 0, + Opcode_ae_mulsfp32x16x2ras_l_encode_fns, 0, 0 }, + { "ae_mulsfp32x16x2s.l", ICLASS_AE_MULSFP32X16X2S_L, + 0, + Opcode_ae_mulsfp32x16x2s_l_encode_fns, 0, 0 }, + { "ae_mulp32x2", ICLASS_AE_MULP32X2, + 0, + Opcode_ae_mulp32x2_encode_fns, 0, 0 }, + { "ae_mulfp32x2rs", ICLASS_AE_MULFP32X2RS, + 0, + Opcode_ae_mulfp32x2rs_encode_fns, 0, 0 }, + { "ae_mulfp32x2ras", ICLASS_AE_MULFP32X2RAS, + 0, + Opcode_ae_mulfp32x2ras_encode_fns, 0, 0 }, + { "ae_mulfp32x2ts", ICLASS_AE_MULFP32X2TS, + 0, + Opcode_ae_mulfp32x2ts_encode_fns, 0, 0 }, + { "ae_mulp32x2t", ICLASS_AE_MULP32X2T, + 0, + Opcode_ae_mulp32x2t_encode_fns, 0, 0 }, + { "ae_mulap32x2", ICLASS_AE_MULAP32X2, + 0, + Opcode_ae_mulap32x2_encode_fns, 0, 0 }, + { "ae_mulafp32x2rs", ICLASS_AE_MULAFP32X2RS, + 0, + Opcode_ae_mulafp32x2rs_encode_fns, 0, 0 }, + { "ae_mulafp32x2ras", ICLASS_AE_MULAFP32X2RAS, + 0, + Opcode_ae_mulafp32x2ras_encode_fns, 0, 0 }, + { "ae_mulafp32x2ts", ICLASS_AE_MULAFP32X2TS, + 0, + Opcode_ae_mulafp32x2ts_encode_fns, 0, 0 }, + { "ae_mulap32x2t", ICLASS_AE_MULAP32X2T, + 0, + Opcode_ae_mulap32x2t_encode_fns, 0, 0 }, + { "ae_mulsp32x2", ICLASS_AE_MULSP32X2, + 0, + Opcode_ae_mulsp32x2_encode_fns, 0, 0 }, + { "ae_mulsfp32x2rs", ICLASS_AE_MULSFP32X2RS, + 0, + Opcode_ae_mulsfp32x2rs_encode_fns, 0, 0 }, + { "ae_mulsfp32x2ras", ICLASS_AE_MULSFP32X2RAS, + 0, + Opcode_ae_mulsfp32x2ras_encode_fns, 0, 0 }, + { "ae_mulsfp32x2ts", ICLASS_AE_MULSFP32X2TS, + 0, + Opcode_ae_mulsfp32x2ts_encode_fns, 0, 0 }, + { "ae_mulsp32x2t", ICLASS_AE_MULSP32X2T, + 0, + Opcode_ae_mulsp32x2t_encode_fns, 0, 0 }, + { "ae_mulfp16x4s", ICLASS_AE_MULFP16X4S, + 0, + Opcode_ae_mulfp16x4s_encode_fns, 0, 0 }, + { "ae_mulfp16x4ras", ICLASS_AE_MULFP16X4RAS, + 0, + Opcode_ae_mulfp16x4ras_encode_fns, 0, 0 }, + { "ae_mulc32", ICLASS_AE_MULC32, + 0, + Opcode_ae_mulc32_encode_fns, 0, 0 }, + { "ae_mulfc24ra", ICLASS_AE_MULFC24RA, + 0, + Opcode_ae_mulfc24ra_encode_fns, 0, 0 }, + { "ae_mulfc32ras", ICLASS_AE_MULFC32RAS, + 0, + Opcode_ae_mulfc32ras_encode_fns, 0, 0 }, + { "ae_mulc32x16.l", ICLASS_AE_MULC32X16_L, + 0, + Opcode_ae_mulc32x16_l_encode_fns, 0, 0 }, + { "ae_mulfc32x16ras.l", ICLASS_AE_MULFC32X16RAS_L, + 0, + Opcode_ae_mulfc32x16ras_l_encode_fns, 0, 0 }, + { "ae_mulc32x16.h", ICLASS_AE_MULC32X16_H, + 0, + Opcode_ae_mulc32x16_h_encode_fns, 0, 0 }, + { "ae_mulfc32x16ras.h", ICLASS_AE_MULFC32X16RAS_H, + 0, + Opcode_ae_mulfc32x16ras_h_encode_fns, 0, 0 }, + { "ae_mulac32", ICLASS_AE_MULAC32, + 0, + Opcode_ae_mulac32_encode_fns, 0, 0 }, + { "ae_mulafc24ra", ICLASS_AE_MULAFC24RA, + 0, + Opcode_ae_mulafc24ra_encode_fns, 0, 0 }, + { "ae_mulafc32ras", ICLASS_AE_MULAFC32RAS, + 0, + Opcode_ae_mulafc32ras_encode_fns, 0, 0 }, + { "ae_mulac32x16.l", ICLASS_AE_MULAC32X16_L, + 0, + Opcode_ae_mulac32x16_l_encode_fns, 0, 0 }, + { "ae_mulafc32x16ras.l", ICLASS_AE_MULAFC32X16RAS_L, + 0, + Opcode_ae_mulafc32x16ras_l_encode_fns, 0, 0 }, + { "ae_mulac32x16.h", ICLASS_AE_MULAC32X16_H, + 0, + Opcode_ae_mulac32x16_h_encode_fns, 0, 0 }, + { "ae_mulafc32x16ras.h", ICLASS_AE_MULAFC32X16RAS_H, + 0, + Opcode_ae_mulafc32x16ras_h_encode_fns, 0, 0 }, + { "ae_mulf16x4ss", ICLASS_AE_MULF16X4SS, + 0, + Opcode_ae_mulf16x4ss_encode_fns, 0, 0 }, + { "ae_mulaf16x4ss", ICLASS_AE_MULAF16X4SS, + 0, + Opcode_ae_mulaf16x4ss_encode_fns, 0, 0 }, + { "ae_mulsf16x4ss", ICLASS_AE_MULSF16X4SS, + 0, + Opcode_ae_mulsf16x4ss_encode_fns, 0, 0 }, + { "ae_mul16x4s", ICLASS_AE_MUL16X4S, + 0, + Opcode_ae_mul16x4s_encode_fns, 0, 0 }, + { "ae_mula16x4s", ICLASS_AE_MULA16X4S, + 0, + Opcode_ae_mula16x4s_encode_fns, 0, 0 }, + { "ae_muls16x4s", ICLASS_AE_MULS16X4S, + 0, + Opcode_ae_muls16x4s_encode_fns, 0, 0 }, + { "ae_mul16x4", ICLASS_AE_MUL16X4, + 0, + Opcode_ae_mul16x4_encode_fns, 0, 0 }, + { "ae_mula16x4", ICLASS_AE_MULA16X4, + 0, + Opcode_ae_mula16x4_encode_fns, 0, 0 }, + { "ae_muls16x4", ICLASS_AE_MULS16X4, + 0, + Opcode_ae_muls16x4_encode_fns, 0, 0 }, + { "ae_mulfd32x2s.fir.h", ICLASS_AE_MULFD32X2S_FIR_H, + 0, + Opcode_ae_mulfd32x2s_fir_h_encode_fns, 0, 0 }, + { "ae_mulfd32x2ra.fir.h", ICLASS_AE_MULFD32X2RA_FIR_H, + 0, + Opcode_ae_mulfd32x2ra_fir_h_encode_fns, 0, 0 }, + { "ae_mulfd32x2s.fir.l", ICLASS_AE_MULFD32X2S_FIR_L, + 0, + Opcode_ae_mulfd32x2s_fir_l_encode_fns, 0, 0 }, + { "ae_mulfd32x2ra.fir.l", ICLASS_AE_MULFD32X2RA_FIR_L, + 0, + Opcode_ae_mulfd32x2ra_fir_l_encode_fns, 0, 0 }, + { "ae_mulfd32x16x2.fir.hh", ICLASS_AE_MULFD32X16X2_FIR_HH, + 0, + Opcode_ae_mulfd32x16x2_fir_hh_encode_fns, 0, 0 }, + { "ae_mulfd32x16x2.fir.hl", ICLASS_AE_MULFD32X16X2_FIR_HL, + 0, + Opcode_ae_mulfd32x16x2_fir_hl_encode_fns, 0, 0 }, + { "ae_mulfd32x16x2.fir.lh", ICLASS_AE_MULFD32X16X2_FIR_LH, + 0, + Opcode_ae_mulfd32x16x2_fir_lh_encode_fns, 0, 0 }, + { "ae_mulfd32x16x2.fir.ll", ICLASS_AE_MULFD32X16X2_FIR_LL, + 0, + Opcode_ae_mulfd32x16x2_fir_ll_encode_fns, 0, 0 }, + { "ae_mulafd32x2s.fir.h", ICLASS_AE_MULAFD32X2S_FIR_H, + 0, + Opcode_ae_mulafd32x2s_fir_h_encode_fns, 0, 0 }, + { "ae_mulafd32x2ra.fir.h", ICLASS_AE_MULAFD32X2RA_FIR_H, + 0, + Opcode_ae_mulafd32x2ra_fir_h_encode_fns, 0, 0 }, + { "ae_mulafd32x2s.fir.l", ICLASS_AE_MULAFD32X2S_FIR_L, + 0, + Opcode_ae_mulafd32x2s_fir_l_encode_fns, 0, 0 }, + { "ae_mulafd32x2ra.fir.l", ICLASS_AE_MULAFD32X2RA_FIR_L, + 0, + Opcode_ae_mulafd32x2ra_fir_l_encode_fns, 0, 0 }, + { "ae_mulafd32x16x2.fir.hh", ICLASS_AE_MULAFD32X16X2_FIR_HH, + 0, + Opcode_ae_mulafd32x16x2_fir_hh_encode_fns, 0, 0 }, + { "ae_mulafd32x16x2.fir.hl", ICLASS_AE_MULAFD32X16X2_FIR_HL, + 0, + Opcode_ae_mulafd32x16x2_fir_hl_encode_fns, 0, 0 }, + { "ae_mulafd32x16x2.fir.lh", ICLASS_AE_MULAFD32X16X2_FIR_LH, + 0, + Opcode_ae_mulafd32x16x2_fir_lh_encode_fns, 0, 0 }, + { "ae_mulafd32x16x2.fir.ll", ICLASS_AE_MULAFD32X16X2_FIR_LL, + 0, + Opcode_ae_mulafd32x16x2_fir_ll_encode_fns, 0, 0 }, + { "ae_mulc16s.h", ICLASS_AE_MULC16S_H, + 0, + Opcode_ae_mulc16s_h_encode_fns, 0, 0 }, + { "ae_mulc16s.l", ICLASS_AE_MULC16S_L, + 0, + Opcode_ae_mulc16s_l_encode_fns, 0, 0 }, + { "ae_mulac16s.h", ICLASS_AE_MULAC16S_H, + 0, + Opcode_ae_mulac16s_h_encode_fns, 0, 0 }, + { "ae_mulac16s.l", ICLASS_AE_MULAC16S_L, + 0, + Opcode_ae_mulac16s_l_encode_fns, 0, 0 }, + { "ae_mulfc16ras", ICLASS_AE_MULFC16RAS, + 0, + Opcode_ae_mulfc16ras_encode_fns, 0, 0 }, + { "ae_mulafc16ras", ICLASS_AE_MULAFC16RAS, + 0, + Opcode_ae_mulafc16ras_encode_fns, 0, 0 }, + { "ae_mul16js", ICLASS_AE_MUL16JS, + 0, + Opcode_ae_mul16js_encode_fns, 0, 0 }, + { "ae_addandsubrng16ras_s1", ICLASS_AE_ADDANDSUBRNG16RAS_S1, + 0, + Opcode_ae_addandsubrng16ras_s1_encode_fns, 0, 0 }, + { "ae_addandsubrng16ras_s2", ICLASS_AE_ADDANDSUBRNG16RAS_S2, + 0, + Opcode_ae_addandsubrng16ras_s2_encode_fns, 0, 0 }, + { "ae_conj16s", ICLASS_AE_CONJ16S, + 0, + Opcode_ae_conj16s_encode_fns, 0, 0 }, + { "ae_mulfq16x2.fir.3", ICLASS_AE_MULFQ16X2_FIR_3, + 0, + Opcode_ae_mulfq16x2_fir_3_encode_fns, 0, 0 }, + { "ae_mulfq16x2.fir.2", ICLASS_AE_MULFQ16X2_FIR_2, + 0, + Opcode_ae_mulfq16x2_fir_2_encode_fns, 0, 0 }, + { "ae_mulfq16x2.fir.1", ICLASS_AE_MULFQ16X2_FIR_1, + 0, + Opcode_ae_mulfq16x2_fir_1_encode_fns, 0, 0 }, + { "ae_mulfq16x2.fir.0", ICLASS_AE_MULFQ16X2_FIR_0, + 0, + Opcode_ae_mulfq16x2_fir_0_encode_fns, 0, 0 }, + { "ae_mulafq16x2.fir.3", ICLASS_AE_MULAFQ16X2_FIR_3, + 0, + Opcode_ae_mulafq16x2_fir_3_encode_fns, 0, 0 }, + { "ae_mulafq16x2.fir.2", ICLASS_AE_MULAFQ16X2_FIR_2, + 0, + Opcode_ae_mulafq16x2_fir_2_encode_fns, 0, 0 }, + { "ae_mulafq16x2.fir.1", ICLASS_AE_MULAFQ16X2_FIR_1, + 0, + Opcode_ae_mulafq16x2_fir_1_encode_fns, 0, 0 }, + { "ae_mulafq16x2.fir.0", ICLASS_AE_MULAFQ16X2_FIR_0, + 0, + Opcode_ae_mulafq16x2_fir_0_encode_fns, 0, 0 }, + { "ae_mulzaaaafq32x16", ICLASS_AE_MULZAAAAFQ32X16, + 0, + Opcode_ae_mulzaaaafq32x16_encode_fns, 0, 0 }, + { "ae_mulaaaafq32x16", ICLASS_AE_MULAAAAFQ32X16, + 0, + Opcode_ae_mulaaaafq32x16_encode_fns, 0, 0 }, + { "ae_mulzaaaaq32x16", ICLASS_AE_MULZAAAAQ32X16, + 0, + Opcode_ae_mulzaaaaq32x16_encode_fns, 0, 0 }, + { "ae_mulaaaaq32x16", ICLASS_AE_MULAAAAQ32X16, + 0, + Opcode_ae_mulaaaaq32x16_encode_fns, 0, 0 }, + { "ae_mul16.00", ICLASS_AE_MUL16_00, + 0, + Opcode_ae_mul16_00_encode_fns, 0, 0 }, + { "ae_mula16.00", ICLASS_AE_MULA16_00, + 0, + Opcode_ae_mula16_00_encode_fns, 0, 0 }, + { "ae_mulzaaaaq16", ICLASS_AE_MULZAAAAQ16, + 0, + Opcode_ae_mulzaaaaq16_encode_fns, 0, 0 }, + { "ae_mulaaaaq16", ICLASS_AE_MULAAAAQ16, + 0, + Opcode_ae_mulaaaaq16_encode_fns, 0, 0 }, + { "ae_div64d32.h", ICLASS_AE_DIV64D32_H, + 0, + Opcode_ae_div64d32_h_encode_fns, 0, 0 }, + { "ae_div64d32.l", ICLASS_AE_DIV64D32_L, + 0, + Opcode_ae_div64d32_l_encode_fns, 0, 0 }, + { "ae_sha32", ICLASS_AE_SHA32, + 0, + Opcode_ae_sha32_encode_fns, 0, 0 }, + { "ae_vldl32t", ICLASS_AE_VLDL32T, + 0, + Opcode_ae_vldl32t_encode_fns, 2, Opcode_ae_vldl32t_funcUnit_uses }, + { "ae_vldl16t", ICLASS_AE_VLDL16T, + 0, + Opcode_ae_vldl16t_encode_fns, 2, Opcode_ae_vldl16t_funcUnit_uses }, + { "ae_vldl16c", ICLASS_AE_VLDL16C, + 0, + Opcode_ae_vldl16c_encode_fns, 4, Opcode_ae_vldl16c_funcUnit_uses }, + { "ae_vldl16c.ip", ICLASS_AE_VLDL16C_IP, + 0, + Opcode_ae_vldl16c_ip_encode_fns, 4, Opcode_ae_vldl16c_ip_funcUnit_uses }, + { "ae_vldl16c.ic", ICLASS_AE_VLDL16C_IC, + 0, + Opcode_ae_vldl16c_ic_encode_fns, 4, Opcode_ae_vldl16c_ic_funcUnit_uses }, + { "ae_vldl16c.ic1", ICLASS_AE_VLDL16C_IC1, + 0, + Opcode_ae_vldl16c_ic1_encode_fns, 4, Opcode_ae_vldl16c_ic1_funcUnit_uses }, + { "ae_vldsht", ICLASS_AE_VLDSHT, + 0, + Opcode_ae_vldsht_encode_fns, 3, Opcode_ae_vldsht_funcUnit_uses }, + { "ae_lb", ICLASS_AE_LB, + 0, + Opcode_ae_lb_encode_fns, 1, Opcode_ae_lb_funcUnit_uses }, + { "ae_lbi", ICLASS_AE_LBI, + 0, + Opcode_ae_lbi_encode_fns, 1, Opcode_ae_lbi_funcUnit_uses }, + { "ae_lbk", ICLASS_AE_LBK, + 0, + Opcode_ae_lbk_encode_fns, 1, Opcode_ae_lbk_funcUnit_uses }, + { "ae_lbki", ICLASS_AE_LBKI, + 0, + Opcode_ae_lbki_encode_fns, 1, Opcode_ae_lbki_funcUnit_uses }, + { "ae_lbs", ICLASS_AE_LBS, + 0, + Opcode_ae_lbs_encode_fns, 1, Opcode_ae_lbs_funcUnit_uses }, + { "ae_lbsi", ICLASS_AE_LBSI, + 0, + Opcode_ae_lbsi_encode_fns, 1, Opcode_ae_lbsi_funcUnit_uses }, + { "ae_db", ICLASS_AE_DB, + 0, + Opcode_ae_db_encode_fns, 3, Opcode_ae_db_funcUnit_uses }, + { "ae_dbi", ICLASS_AE_DBI, + 0, + Opcode_ae_dbi_encode_fns, 3, Opcode_ae_dbi_funcUnit_uses }, + { "ae_db.ic", ICLASS_AE_DB_IC, + 0, + Opcode_ae_db_ic_encode_fns, 3, Opcode_ae_db_ic_funcUnit_uses }, + { "ae_dbi.ic", ICLASS_AE_DBI_IC, + 0, + Opcode_ae_dbi_ic_encode_fns, 3, Opcode_ae_dbi_ic_funcUnit_uses }, + { "ae_db.ic1", ICLASS_AE_DB_IC1, + 0, + Opcode_ae_db_ic1_encode_fns, 3, Opcode_ae_db_ic1_funcUnit_uses }, + { "ae_dbi.ic1", ICLASS_AE_DBI_IC1, + 0, + Opcode_ae_dbi_ic1_encode_fns, 3, Opcode_ae_dbi_ic1_funcUnit_uses }, + { "ae_db.ip", ICLASS_AE_DB_IP, + 0, + Opcode_ae_db_ip_encode_fns, 3, Opcode_ae_db_ip_funcUnit_uses }, + { "ae_dbi.ip", ICLASS_AE_DBI_IP, + 0, + Opcode_ae_dbi_ip_encode_fns, 3, Opcode_ae_dbi_ip_funcUnit_uses }, + { "ae_ardecnorm16", ICLASS_AE_ARDECNORM16, + 0, + Opcode_ae_ardecnorm16_encode_fns, 0, 0 }, + { "ae_lbki_dbi.ic", ICLASS_AE_LBKI_DBI_IC, + 0, + Opcode_ae_lbki_dbi_ic_encode_fns, 1, Opcode_ae_lbki_dbi_ic_funcUnit_uses }, + { "ae_lbki_dbi.ip", ICLASS_AE_LBKI_DBI_IP, + 0, + Opcode_ae_lbki_dbi_ip_encode_fns, 1, Opcode_ae_lbki_dbi_ip_funcUnit_uses }, + { "ae_lbki_dbi", ICLASS_AE_LBKI_DBI, + 0, + Opcode_ae_lbki_dbi_encode_fns, 1, Opcode_ae_lbki_dbi_funcUnit_uses }, + { "ae_lbi_dbi.ic", ICLASS_AE_LBI_DBI_IC, + 0, + Opcode_ae_lbi_dbi_ic_encode_fns, 1, Opcode_ae_lbi_dbi_ic_funcUnit_uses }, + { "ae_lbi_dbi.ip", ICLASS_AE_LBI_DBI_IP, + 0, + Opcode_ae_lbi_dbi_ip_encode_fns, 1, Opcode_ae_lbi_dbi_ip_funcUnit_uses }, + { "ae_lbi_dbi", ICLASS_AE_LBI_DBI, + 0, + Opcode_ae_lbi_dbi_encode_fns, 1, Opcode_ae_lbi_dbi_funcUnit_uses }, + { "ae_lbk_db.ic", ICLASS_AE_LBK_DB_IC, + 0, + Opcode_ae_lbk_db_ic_encode_fns, 1, Opcode_ae_lbk_db_ic_funcUnit_uses }, + { "ae_lbk_db.ip", ICLASS_AE_LBK_DB_IP, + 0, + Opcode_ae_lbk_db_ip_encode_fns, 1, Opcode_ae_lbk_db_ip_funcUnit_uses }, + { "ae_lbk_db", ICLASS_AE_LBK_DB, + 0, + Opcode_ae_lbk_db_encode_fns, 1, Opcode_ae_lbk_db_funcUnit_uses }, + { "ae_lb_db.ic", ICLASS_AE_LB_DB_IC, + 0, + Opcode_ae_lb_db_ic_encode_fns, 1, Opcode_ae_lb_db_ic_funcUnit_uses }, + { "ae_lb_db.ip", ICLASS_AE_LB_DB_IP, + 0, + Opcode_ae_lb_db_ip_encode_fns, 1, Opcode_ae_lb_db_ip_funcUnit_uses }, + { "ae_lb_db", ICLASS_AE_LB_DB, + 0, + Opcode_ae_lb_db_encode_fns, 1, Opcode_ae_lb_db_funcUnit_uses }, + { "ae_vlel32t", ICLASS_AE_VLEL32T, + 0, + Opcode_ae_vlel32t_encode_fns, 2, Opcode_ae_vlel32t_funcUnit_uses }, + { "ae_vlel16t", ICLASS_AE_VLEL16T, + 0, + Opcode_ae_vlel16t_encode_fns, 2, Opcode_ae_vlel16t_funcUnit_uses }, + { "ae_sb", ICLASS_AE_SB, + 0, + Opcode_ae_sb_encode_fns, 3, Opcode_ae_sb_funcUnit_uses }, + { "ae_sbi", ICLASS_AE_SBI, + 0, + Opcode_ae_sbi_encode_fns, 3, Opcode_ae_sbi_funcUnit_uses }, + { "ae_vles16c", ICLASS_AE_VLES16C, + 0, + Opcode_ae_vles16c_encode_fns, 3, Opcode_ae_vles16c_funcUnit_uses }, + { "ae_sbf", ICLASS_AE_SBF, + 0, + Opcode_ae_sbf_encode_fns, 3, Opcode_ae_sbf_funcUnit_uses }, + { "ae_sb.ic", ICLASS_AE_SB_IC, + 0, + Opcode_ae_sb_ic_encode_fns, 3, Opcode_ae_sb_ic_funcUnit_uses }, + { "ae_sbi.ic", ICLASS_AE_SBI_IC, + 0, + Opcode_ae_sbi_ic_encode_fns, 3, Opcode_ae_sbi_ic_funcUnit_uses }, + { "ae_vles16c.ic", ICLASS_AE_VLES16C_IC, + 0, + Opcode_ae_vles16c_ic_encode_fns, 3, Opcode_ae_vles16c_ic_funcUnit_uses }, + { "ae_sbf.ic", ICLASS_AE_SBF_IC, + 0, + Opcode_ae_sbf_ic_encode_fns, 3, Opcode_ae_sbf_ic_funcUnit_uses }, + { "ae_sb.ic1", ICLASS_AE_SB_IC1, + 0, + Opcode_ae_sb_ic1_encode_fns, 3, Opcode_ae_sb_ic1_funcUnit_uses }, + { "ae_sbi.ic1", ICLASS_AE_SBI_IC1, + 0, + Opcode_ae_sbi_ic1_encode_fns, 3, Opcode_ae_sbi_ic1_funcUnit_uses }, + { "ae_vles16c.ic1", ICLASS_AE_VLES16C_IC1, + 0, + Opcode_ae_vles16c_ic1_encode_fns, 3, Opcode_ae_vles16c_ic1_funcUnit_uses }, + { "ae_sbf.ic1", ICLASS_AE_SBF_IC1, + 0, + Opcode_ae_sbf_ic1_encode_fns, 3, Opcode_ae_sbf_ic1_funcUnit_uses }, + { "ae_sb.ip", ICLASS_AE_SB_IP, + 0, + Opcode_ae_sb_ip_encode_fns, 3, Opcode_ae_sb_ip_funcUnit_uses }, + { "ae_sbi.ip", ICLASS_AE_SBI_IP, + 0, + Opcode_ae_sbi_ip_encode_fns, 3, Opcode_ae_sbi_ip_funcUnit_uses }, + { "ae_vles16c.ip", ICLASS_AE_VLES16C_IP, + 0, + Opcode_ae_vles16c_ip_encode_fns, 3, Opcode_ae_vles16c_ip_funcUnit_uses }, + { "ae_sbf.ip", ICLASS_AE_SBF_IP, + 0, + Opcode_ae_sbf_ip_encode_fns, 3, Opcode_ae_sbf_ip_funcUnit_uses }, + { "ae_sext32", ICLASS_AE_SEXT32, + 0, + Opcode_ae_sext32_encode_fns, 0, 0 }, + { "ae_movae", ICLASS_AE_MOVAE, + 0, + Opcode_ae_movae_encode_fns, 0, 0 }, + { "ae_movea", ICLASS_AE_MOVEA, + 0, + Opcode_ae_movea_encode_fns, 0, 0 }, + { "ae_moveep", ICLASS_AE_MOVEEP, + 0, + Opcode_ae_moveep_encode_fns, 0, 0 }, + { "ae_sext72", ICLASS_AE_SEXT72, + 0, + Opcode_ae_sext72_encode_fns, 0, 0 }, + { "ae_add72", ICLASS_AE_ADD72, + 0, + Opcode_ae_add72_encode_fns, 0, 0 }, + { "ae_sub72", ICLASS_AE_SUB72, + 0, + Opcode_ae_sub72_encode_fns, 0, 0 }, + { "ae_add72x64", ICLASS_AE_ADD72X64, + 0, + Opcode_ae_add72x64_encode_fns, 0, 0 }, + { "ae_sub72x64", ICLASS_AE_SUB72X64, + 0, + Opcode_ae_sub72x64_encode_fns, 0, 0 }, + { "ae_mul32ep.hh", ICLASS_AE_MUL32EP_HH, + 0, + Opcode_ae_mul32ep_hh_encode_fns, 0, 0 }, + { "ae_mula32ep.hh", ICLASS_AE_MULA32EP_HH, + 0, + Opcode_ae_mula32ep_hh_encode_fns, 0, 0 }, + { "ae_muls32ep.hh", ICLASS_AE_MULS32EP_HH, + 0, + Opcode_ae_muls32ep_hh_encode_fns, 0, 0 }, + { "ae_mulzaad32ep.hh.ll", ICLASS_AE_MULZAAD32EP_HH_LL, + 0, + Opcode_ae_mulzaad32ep_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssd32ep.hh.ll", ICLASS_AE_MULZSSD32EP_HH_LL, + 0, + Opcode_ae_mulzssd32ep_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaad32ep.hh.ll", ICLASS_AE_MULAAD32EP_HH_LL, + 0, + Opcode_ae_mulaad32ep_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssd32ep.hh.ll", ICLASS_AE_MULSSD32EP_HH_LL, + 0, + Opcode_ae_mulssd32ep_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaad32usep.hl.lh", ICLASS_AE_MULAAD32USEP_HL_LH, + 0, + Opcode_ae_mulaad32usep_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaad32usep.hl.lh", ICLASS_AE_MULZAAD32USEP_HL_LH, + 0, + Opcode_ae_mulzaad32usep_hl_lh_encode_fns, 0, 0 }, + { "ae_mul32usep.lh", ICLASS_AE_MUL32USEP_LH, + 0, + Opcode_ae_mul32usep_lh_encode_fns, 0, 0 }, + { "ae_mula32usep.lh", ICLASS_AE_MULA32USEP_LH, + 0, + Opcode_ae_mula32usep_lh_encode_fns, 0, 0 }, + { "ae_mul32usep.ll", ICLASS_AE_MUL32USEP_LL, + 0, + Opcode_ae_mul32usep_ll_encode_fns, 0, 0 }, + { "ae_mula32usep.ll", ICLASS_AE_MULA32USEP_LL, + 0, + Opcode_ae_mula32usep_ll_encode_fns, 0, 0 }, + { "ae_srai72", ICLASS_AE_SRAI72, + 0, + Opcode_ae_srai72_encode_fns, 0, 0 }, + { "ae_slai72", ICLASS_AE_SLAI72, + 0, + Opcode_ae_slai72_encode_fns, 0, 0 }, + { "ae_sat64s", ICLASS_AE_SAT64S, + 0, + Opcode_ae_sat64s_encode_fns, 0, 0 }, + { "ae_l16si.n", ICLASS_AE_L16SI_N, + 0, + Opcode_ae_l16si_n_encode_fns, 2, Opcode_ae_l16si_n_funcUnit_uses }, + { "ae_l16ui.n", ICLASS_AE_L16UI_N, + 0, + Opcode_ae_l16ui_n_encode_fns, 2, Opcode_ae_l16ui_n_funcUnit_uses }, + { "ae_s16i.n", ICLASS_AE_S16I_N, + 0, + Opcode_ae_s16i_n_encode_fns, 2, Opcode_ae_s16i_n_funcUnit_uses }, + { "ae_lalign128.i", ICLASS_AE_LALIGN128_I, + 0, + Opcode_ae_lalign128_i_encode_fns, 1, Opcode_ae_lalign128_i_funcUnit_uses }, + { "ae_salign128.i", ICLASS_AE_SALIGN128_I, + 0, + Opcode_ae_salign128_i_encode_fns, 1, Opcode_ae_salign128_i_funcUnit_uses }, + { "ae_la128.pp", ICLASS_AE_LA128_PP, + 0, + Opcode_ae_la128_pp_encode_fns, 1, Opcode_ae_la128_pp_funcUnit_uses }, + { "ae_sa128pos.fp", ICLASS_AE_SA128POS_FP, + 0, + Opcode_ae_sa128pos_fp_encode_fns, 1, Opcode_ae_sa128pos_fp_funcUnit_uses }, + { "ae_la8x4s_ip", ICLASS_AE_LA8X4S_IP, + 0, + Opcode_ae_la8x4s_ip_encode_fns, 1, Opcode_ae_la8x4s_ip_funcUnit_uses }, + { "ae_la8x4u_ip", ICLASS_AE_LA8X4U_IP, + 0, + Opcode_ae_la8x4u_ip_encode_fns, 1, Opcode_ae_la8x4u_ip_funcUnit_uses }, + { "ae_la8x8x2_ip", ICLASS_AE_LA8X8X2_IP, + 0, + Opcode_ae_la8x8x2_ip_encode_fns, 1, Opcode_ae_la8x8x2_ip_funcUnit_uses }, + { "ae_la16x4x2_ip", ICLASS_AE_LA16X4X2_IP, + 0, + Opcode_ae_la16x4x2_ip_encode_fns, 1, Opcode_ae_la16x4x2_ip_funcUnit_uses }, + { "ae_la32x2x2_ip", ICLASS_AE_LA32X2X2_IP, + 0, + Opcode_ae_la32x2x2_ip_encode_fns, 1, Opcode_ae_la32x2x2_ip_funcUnit_uses }, + { "ae_la8x8x2_ic", ICLASS_AE_LA8X8X2_IC, + 0, + Opcode_ae_la8x8x2_ic_encode_fns, 1, Opcode_ae_la8x8x2_ic_funcUnit_uses }, + { "ae_la16x4x2_ic", ICLASS_AE_LA16X4X2_IC, + 0, + Opcode_ae_la16x4x2_ic_encode_fns, 1, Opcode_ae_la16x4x2_ic_funcUnit_uses }, + { "ae_la32x2x2_ic", ICLASS_AE_LA32X2X2_IC, + 0, + Opcode_ae_la32x2x2_ic_encode_fns, 1, Opcode_ae_la32x2x2_ic_funcUnit_uses }, + { "ae_la8x8x2_ic1", ICLASS_AE_LA8X8X2_IC1, + 0, + Opcode_ae_la8x8x2_ic1_encode_fns, 1, Opcode_ae_la8x8x2_ic1_funcUnit_uses }, + { "ae_la16x4x2_ic1", ICLASS_AE_LA16X4X2_IC1, + 0, + Opcode_ae_la16x4x2_ic1_encode_fns, 1, Opcode_ae_la16x4x2_ic1_funcUnit_uses }, + { "ae_la32x2x2_ic1", ICLASS_AE_LA32X2X2_IC1, + 0, + Opcode_ae_la32x2x2_ic1_encode_fns, 1, Opcode_ae_la32x2x2_ic1_funcUnit_uses }, + { "ae_la8x8x2_ic2", ICLASS_AE_LA8X8X2_IC2, + 0, + Opcode_ae_la8x8x2_ic2_encode_fns, 1, Opcode_ae_la8x8x2_ic2_funcUnit_uses }, + { "ae_la16x4x2_ic2", ICLASS_AE_LA16X4X2_IC2, + 0, + Opcode_ae_la16x4x2_ic2_encode_fns, 1, Opcode_ae_la16x4x2_ic2_funcUnit_uses }, + { "ae_la32x2x2_ic2", ICLASS_AE_LA32X2X2_IC2, + 0, + Opcode_ae_la32x2x2_ic2_encode_fns, 1, Opcode_ae_la32x2x2_ic2_funcUnit_uses }, + { "ae_sa8x8x2_ip", ICLASS_AE_SA8X8X2_IP, + 0, + Opcode_ae_sa8x8x2_ip_encode_fns, 1, Opcode_ae_sa8x8x2_ip_funcUnit_uses }, + { "ae_sa16x4x2_ip", ICLASS_AE_SA16X4X2_IP, + 0, + Opcode_ae_sa16x4x2_ip_encode_fns, 1, Opcode_ae_sa16x4x2_ip_funcUnit_uses }, + { "ae_sa32x2x2_ip", ICLASS_AE_SA32X2X2_IP, + 0, + Opcode_ae_sa32x2x2_ip_encode_fns, 1, Opcode_ae_sa32x2x2_ip_funcUnit_uses }, + { "ae_sa8x8x2_ic", ICLASS_AE_SA8X8X2_IC, + 0, + Opcode_ae_sa8x8x2_ic_encode_fns, 1, Opcode_ae_sa8x8x2_ic_funcUnit_uses }, + { "ae_sa16x4x2_ic", ICLASS_AE_SA16X4X2_IC, + 0, + Opcode_ae_sa16x4x2_ic_encode_fns, 1, Opcode_ae_sa16x4x2_ic_funcUnit_uses }, + { "ae_sa32x2x2_ic", ICLASS_AE_SA32X2X2_IC, + 0, + Opcode_ae_sa32x2x2_ic_encode_fns, 1, Opcode_ae_sa32x2x2_ic_funcUnit_uses }, + { "ae_sa8x8x2_ic1", ICLASS_AE_SA8X8X2_IC1, + 0, + Opcode_ae_sa8x8x2_ic1_encode_fns, 1, Opcode_ae_sa8x8x2_ic1_funcUnit_uses }, + { "ae_sa16x4x2_ic1", ICLASS_AE_SA16X4X2_IC1, + 0, + Opcode_ae_sa16x4x2_ic1_encode_fns, 1, Opcode_ae_sa16x4x2_ic1_funcUnit_uses }, + { "ae_sa32x2x2_ic1", ICLASS_AE_SA32X2X2_IC1, + 0, + Opcode_ae_sa32x2x2_ic1_encode_fns, 1, Opcode_ae_sa32x2x2_ic1_funcUnit_uses }, + { "ae_sa8x8x2_ic2", ICLASS_AE_SA8X8X2_IC2, + 0, + Opcode_ae_sa8x8x2_ic2_encode_fns, 1, Opcode_ae_sa8x8x2_ic2_funcUnit_uses }, + { "ae_sa16x4x2_ic2", ICLASS_AE_SA16X4X2_IC2, + 0, + Opcode_ae_sa16x4x2_ic2_encode_fns, 1, Opcode_ae_sa16x4x2_ic2_funcUnit_uses }, + { "ae_sa32x2x2_ic2", ICLASS_AE_SA32X2X2_IC2, + 0, + Opcode_ae_sa32x2x2_ic2_encode_fns, 1, Opcode_ae_sa32x2x2_ic2_funcUnit_uses }, + { "ae_abs8", ICLASS_AE_ABS8, + 0, + Opcode_ae_abs8_encode_fns, 0, 0 }, + { "ae_abs8s", ICLASS_AE_ABS8S, + 0, + Opcode_ae_abs8s_encode_fns, 0, 0 }, + { "ae_neg8s", ICLASS_AE_NEG8S, + 0, + Opcode_ae_neg8s_encode_fns, 0, 0 }, + { "ae_add8", ICLASS_AE_ADD8, + 0, + Opcode_ae_add8_encode_fns, 0, 0 }, + { "ae_sub8", ICLASS_AE_SUB8, + 0, + Opcode_ae_sub8_encode_fns, 0, 0 }, + { "ae_max8", ICLASS_AE_MAX8, + 0, + Opcode_ae_max8_encode_fns, 0, 0 }, + { "ae_min8", ICLASS_AE_MIN8, + 0, + Opcode_ae_min8_encode_fns, 0, 0 }, + { "ae_add8s", ICLASS_AE_ADD8S, + 0, + Opcode_ae_add8s_encode_fns, 0, 0 }, + { "ae_sub8s", ICLASS_AE_SUB8S, + 0, + Opcode_ae_sub8s_encode_fns, 0, 0 }, + { "ae_le8", ICLASS_AE_LE8, + 0, + Opcode_ae_le8_encode_fns, 0, 0 }, + { "ae_lt8", ICLASS_AE_LT8, + 0, + Opcode_ae_lt8_encode_fns, 0, 0 }, + { "ae_eq8", ICLASS_AE_EQ8, + 0, + Opcode_ae_eq8_encode_fns, 0, 0 }, + { "ae_satu16x4", ICLASS_AE_SATU16X4, + 0, + Opcode_ae_satu16x4_encode_fns, 0, 0 }, + { "ae_sat32x2", ICLASS_AE_SAT32X2, + 0, + Opcode_ae_sat32x2_encode_fns, 0, 0 }, + { "ae_satu32x2", ICLASS_AE_SATU32X2, + 0, + Opcode_ae_satu32x2_encode_fns, 0, 0 }, + { "ae_sat8x8x16", ICLASS_AE_SAT8X8X16, + 0, + Opcode_ae_sat8x8x16_encode_fns, 0, 0 }, + { "ae_satu8x8x16", ICLASS_AE_SATU8X8X16, + 0, + Opcode_ae_satu8x8x16_encode_fns, 0, 0 }, + { "ae_sat8x4x32_l", ICLASS_AE_SAT8X4X32_L, + 0, + Opcode_ae_sat8x4x32_l_encode_fns, 0, 0 }, + { "ae_satu8x4x32_l", ICLASS_AE_SATU8X4X32_L, + 0, + Opcode_ae_satu8x4x32_l_encode_fns, 0, 0 }, + { "ae_round8x8f16ssym", ICLASS_AE_ROUND8X8F16SSYM, + 0, + Opcode_ae_round8x8f16ssym_encode_fns, 0, 0 }, + { "ae_round8x8f16sasym", ICLASS_AE_ROUND8X8F16SASYM, + 0, + Opcode_ae_round8x8f16sasym_encode_fns, 0, 0 }, + { "ae_round8x4f32ssym_l", ICLASS_AE_ROUND8X4F32SSYM_L, + 0, + Opcode_ae_round8x4f32ssym_l_encode_fns, 0, 0 }, + { "ae_round8x4f32sasym_l", ICLASS_AE_ROUND8X4F32SASYM_L, + 0, + Opcode_ae_round8x4f32sasym_l_encode_fns, 0, 0 }, + { "ae_movda8", ICLASS_AE_MOVDA8, + 0, + Opcode_ae_movda8_encode_fns, 0, 0 }, + { "ae_movad8", ICLASS_AE_MOVAD8, + 0, + Opcode_ae_movad8_encode_fns, 0, 0 }, + { "ae_movdx2", ICLASS_AE_MOVDX2, + 0, + Opcode_ae_movdx2_encode_fns, 0, 0 }, + { "ae_addandsub32j", ICLASS_AE_ADDANDSUB32J, + 0, + Opcode_ae_addandsub32j_encode_fns, 0, 0 }, + { "ae_addw8", ICLASS_AE_ADDW8, + 0, + Opcode_ae_addw8_encode_fns, 0, 0 }, + { "ae_addw16", ICLASS_AE_ADDW16, + 0, + Opcode_ae_addw16_encode_fns, 0, 0 }, + { "ae_addw32", ICLASS_AE_ADDW32, + 0, + Opcode_ae_addw32_encode_fns, 0, 0 }, + { "ae_subw8", ICLASS_AE_SUBW8, + 0, + Opcode_ae_subw8_encode_fns, 0, 0 }, + { "ae_subw16", ICLASS_AE_SUBW16, + 0, + Opcode_ae_subw16_encode_fns, 0, 0 }, + { "ae_subw32", ICLASS_AE_SUBW32, + 0, + Opcode_ae_subw32_encode_fns, 0, 0 }, + { "ae_accw8", ICLASS_AE_ACCW8, + 0, + Opcode_ae_accw8_encode_fns, 0, 0 }, + { "ae_accw16", ICLASS_AE_ACCW16, + 0, + Opcode_ae_accw16_encode_fns, 0, 0 }, + { "ae_accw32", ICLASS_AE_ACCW32, + 0, + Opcode_ae_accw32_encode_fns, 0, 0 }, + { "ae_addw8u", ICLASS_AE_ADDW8U, + 0, + Opcode_ae_addw8u_encode_fns, 0, 0 }, + { "ae_subw8u", ICLASS_AE_SUBW8U, + 0, + Opcode_ae_subw8u_encode_fns, 0, 0 }, + { "ae_accw8u", ICLASS_AE_ACCW8U, + 0, + Opcode_ae_accw8u_encode_fns, 0, 0 }, + { "ae_mulfp32x2s.hh.ll", ICLASS_AE_MULFP32X2S_HH_LL, + 0, + Opcode_ae_mulfp32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulafp32x2s.hh.ll", ICLASS_AE_MULAFP32X2S_HH_LL, + 0, + Opcode_ae_mulafp32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsfp32x2s.hh.ll", ICLASS_AE_MULSFP32X2S_HH_LL, + 0, + Opcode_ae_mulsfp32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulfp32x2s.hl.lh", ICLASS_AE_MULFP32X2S_HL_LH, + 0, + Opcode_ae_mulfp32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulafp32x2s.hl.lh", ICLASS_AE_MULAFP32X2S_HL_LH, + 0, + Opcode_ae_mulafp32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsfp32x2s.hl.lh", ICLASS_AE_MULSFP32X2S_HL_LH, + 0, + Opcode_ae_mulsfp32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaaf2d32s.hh.ll", ICLASS_AE_MULZAAF2D32S_HH_LL, + 0, + Opcode_ae_mulzaaf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasf2d32s.hh.ll", ICLASS_AE_MULZASF2D32S_HH_LL, + 0, + Opcode_ae_mulzasf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsaf2d32s.hh.ll", ICLASS_AE_MULZSAF2D32S_HH_LL, + 0, + Opcode_ae_mulzsaf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssf2d32s.hh.ll", ICLASS_AE_MULZSSF2D32S_HH_LL, + 0, + Opcode_ae_mulzssf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaaf2d32s.hh.ll", ICLASS_AE_MULAAF2D32S_HH_LL, + 0, + Opcode_ae_mulaaf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasf2d32s.hh.ll", ICLASS_AE_MULASF2D32S_HH_LL, + 0, + Opcode_ae_mulasf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsaf2d32s.hh.ll", ICLASS_AE_MULSAF2D32S_HH_LL, + 0, + Opcode_ae_mulsaf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssf2d32s.hh.ll", ICLASS_AE_MULSSF2D32S_HH_LL, + 0, + Opcode_ae_mulssf2d32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaaf2d32s.hl.lh", ICLASS_AE_MULZAAF2D32S_HL_LH, + 0, + Opcode_ae_mulzaaf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasf2d32s.hl.lh", ICLASS_AE_MULZASF2D32S_HL_LH, + 0, + Opcode_ae_mulzasf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzsaf2d32s.hl.lh", ICLASS_AE_MULZSAF2D32S_HL_LH, + 0, + Opcode_ae_mulzsaf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssf2d32s.hl.lh", ICLASS_AE_MULZSSF2D32S_HL_LH, + 0, + Opcode_ae_mulzssf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaaf2d32s.hl.lh", ICLASS_AE_MULAAF2D32S_HL_LH, + 0, + Opcode_ae_mulaaf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasf2d32s.hl.lh", ICLASS_AE_MULASF2D32S_HL_LH, + 0, + Opcode_ae_mulasf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsaf2d32s.hl.lh", ICLASS_AE_MULSAF2D32S_HL_LH, + 0, + Opcode_ae_mulsaf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssf2d32s.hl.lh", ICLASS_AE_MULSSF2D32S_HL_LH, + 0, + Opcode_ae_mulssf2d32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mul32s.hh", ICLASS_AE_MUL32S_HH, + 0, + Opcode_ae_mul32s_hh_encode_fns, 0, 0 }, + { "ae_mula32s.hh", ICLASS_AE_MULA32S_HH, + 0, + Opcode_ae_mula32s_hh_encode_fns, 0, 0 }, + { "ae_muls32s.hh", ICLASS_AE_MULS32S_HH, + 0, + Opcode_ae_muls32s_hh_encode_fns, 0, 0 }, + { "ae_mul32s.ll", ICLASS_AE_MUL32S_LL, + 0, + Opcode_ae_mul32s_ll_encode_fns, 0, 0 }, + { "ae_mula32s.ll", ICLASS_AE_MULA32S_LL, + 0, + Opcode_ae_mula32s_ll_encode_fns, 0, 0 }, + { "ae_muls32s.ll", ICLASS_AE_MULS32S_LL, + 0, + Opcode_ae_muls32s_ll_encode_fns, 0, 0 }, + { "ae_mul32s.hl", ICLASS_AE_MUL32S_HL, + 0, + Opcode_ae_mul32s_hl_encode_fns, 0, 0 }, + { "ae_mula32s.hl", ICLASS_AE_MULA32S_HL, + 0, + Opcode_ae_mula32s_hl_encode_fns, 0, 0 }, + { "ae_muls32s.hl", ICLASS_AE_MULS32S_HL, + 0, + Opcode_ae_muls32s_hl_encode_fns, 0, 0 }, + { "ae_mul32s.lh", ICLASS_AE_MUL32S_LH, + 0, + Opcode_ae_mul32s_lh_encode_fns, 0, 0 }, + { "ae_mula32s.lh", ICLASS_AE_MULA32S_LH, + 0, + Opcode_ae_mula32s_lh_encode_fns, 0, 0 }, + { "ae_muls32s.lh", ICLASS_AE_MULS32S_LH, + 0, + Opcode_ae_muls32s_lh_encode_fns, 0, 0 }, + { "ae_mul32x2s.hh.ll", ICLASS_AE_MUL32X2S_HH_LL, + 0, + Opcode_ae_mul32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_mula32x2s.hh.ll", ICLASS_AE_MULA32X2S_HH_LL, + 0, + Opcode_ae_mula32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_muls32x2s.hh.ll", ICLASS_AE_MULS32X2S_HH_LL, + 0, + Opcode_ae_muls32x2s_hh_ll_encode_fns, 0, 0 }, + { "ae_mul32x2s.hl.lh", ICLASS_AE_MUL32X2S_HL_LH, + 0, + Opcode_ae_mul32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_mula32x2s.hl.lh", ICLASS_AE_MULA32X2S_HL_LH, + 0, + Opcode_ae_mula32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_muls32x2s.hl.lh", ICLASS_AE_MULS32X2S_HL_LH, + 0, + Opcode_ae_muls32x2s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaad32s.hh.ll", ICLASS_AE_MULZAAD32S_HH_LL, + 0, + Opcode_ae_mulzaad32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasd32s.hh.ll", ICLASS_AE_MULZASD32S_HH_LL, + 0, + Opcode_ae_mulzasd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsad32s.hh.ll", ICLASS_AE_MULZSAD32S_HH_LL, + 0, + Opcode_ae_mulzsad32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssd32s.hh.ll", ICLASS_AE_MULZSSD32S_HH_LL, + 0, + Opcode_ae_mulzssd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaad32s.hh.ll", ICLASS_AE_MULAAD32S_HH_LL, + 0, + Opcode_ae_mulaad32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasd32s.hh.ll", ICLASS_AE_MULASD32S_HH_LL, + 0, + Opcode_ae_mulasd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsad32s.hh.ll", ICLASS_AE_MULSAD32S_HH_LL, + 0, + Opcode_ae_mulsad32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssd32s.hh.ll", ICLASS_AE_MULSSD32S_HH_LL, + 0, + Opcode_ae_mulssd32s_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaad32s.hl.lh", ICLASS_AE_MULZAAD32S_HL_LH, + 0, + Opcode_ae_mulzaad32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasd32s.hl.lh", ICLASS_AE_MULZASD32S_HL_LH, + 0, + Opcode_ae_mulzasd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzsad32s.hl.lh", ICLASS_AE_MULZSAD32S_HL_LH, + 0, + Opcode_ae_mulzsad32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssd32s.hl.lh", ICLASS_AE_MULZSSD32S_HL_LH, + 0, + Opcode_ae_mulzssd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaad32s.hl.lh", ICLASS_AE_MULAAD32S_HL_LH, + 0, + Opcode_ae_mulaad32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasd32s.hl.lh", ICLASS_AE_MULASD32S_HL_LH, + 0, + Opcode_ae_mulasd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsad32s.hl.lh", ICLASS_AE_MULSAD32S_HL_LH, + 0, + Opcode_ae_mulsad32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssd32s.hl.lh", ICLASS_AE_MULSSD32S_HL_LH, + 0, + Opcode_ae_mulssd32s_hl_lh_encode_fns, 0, 0 }, + { "ae_mulf32x2ra.hh.ll", ICLASS_AE_MULF32X2RA_HH_LL, + 0, + Opcode_ae_mulf32x2ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaf32x2ra.hh.ll", ICLASS_AE_MULAF32X2RA_HH_LL, + 0, + Opcode_ae_mulaf32x2ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsf32x2ra.hh.ll", ICLASS_AE_MULSF32X2RA_HH_LL, + 0, + Opcode_ae_mulsf32x2ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulf32x2ra.hl.lh", ICLASS_AE_MULF32X2RA_HL_LH, + 0, + Opcode_ae_mulf32x2ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaf32x2ra.hl.lh", ICLASS_AE_MULAF32X2RA_HL_LH, + 0, + Opcode_ae_mulaf32x2ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsf32x2ra.hl.lh", ICLASS_AE_MULSF32X2RA_HL_LH, + 0, + Opcode_ae_mulsf32x2ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaaf2d32ra.hh.ll", ICLASS_AE_MULZAAF2D32RA_HH_LL, + 0, + Opcode_ae_mulzaaf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzasf2d32ra.hh.ll", ICLASS_AE_MULZASF2D32RA_HH_LL, + 0, + Opcode_ae_mulzasf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzsaf2d32ra.hh.ll", ICLASS_AE_MULZSAF2D32RA_HH_LL, + 0, + Opcode_ae_mulzsaf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssf2d32ra.hh.ll", ICLASS_AE_MULZSSF2D32RA_HH_LL, + 0, + Opcode_ae_mulzssf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaaf2d32ra.hh.ll", ICLASS_AE_MULAAF2D32RA_HH_LL, + 0, + Opcode_ae_mulaaf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulasf2d32ra.hh.ll", ICLASS_AE_MULASF2D32RA_HH_LL, + 0, + Opcode_ae_mulasf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsaf2d32ra.hh.ll", ICLASS_AE_MULSAF2D32RA_HH_LL, + 0, + Opcode_ae_mulsaf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssf2d32ra.hh.ll", ICLASS_AE_MULSSF2D32RA_HH_LL, + 0, + Opcode_ae_mulssf2d32ra_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaaf2d32ra.hl.lh", ICLASS_AE_MULZAAF2D32RA_HL_LH, + 0, + Opcode_ae_mulzaaf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzasf2d32ra.hl.lh", ICLASS_AE_MULZASF2D32RA_HL_LH, + 0, + Opcode_ae_mulzasf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzsaf2d32ra.hl.lh", ICLASS_AE_MULZSAF2D32RA_HL_LH, + 0, + Opcode_ae_mulzsaf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssf2d32ra.hl.lh", ICLASS_AE_MULZSSF2D32RA_HL_LH, + 0, + Opcode_ae_mulzssf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaaf2d32ra.hl.lh", ICLASS_AE_MULAAF2D32RA_HL_LH, + 0, + Opcode_ae_mulaaf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulasf2d32ra.hl.lh", ICLASS_AE_MULASF2D32RA_HL_LH, + 0, + Opcode_ae_mulasf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsaf2d32ra.hl.lh", ICLASS_AE_MULSAF2D32RA_HL_LH, + 0, + Opcode_ae_mulsaf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssf2d32ra.hl.lh", ICLASS_AE_MULSSF2D32RA_HL_LH, + 0, + Opcode_ae_mulssf2d32ra_hl_lh_encode_fns, 0, 0 }, + { "ae_mulf32x2r.hh.ll", ICLASS_AE_MULF32X2R_HH_LL, + 0, + Opcode_ae_mulf32x2r_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaf32x2r.hh.ll", ICLASS_AE_MULAF32X2R_HH_LL, + 0, + Opcode_ae_mulaf32x2r_hh_ll_encode_fns, 0, 0 }, + { "ae_mulsf32x2r.hh.ll", ICLASS_AE_MULSF32X2R_HH_LL, + 0, + Opcode_ae_mulsf32x2r_hh_ll_encode_fns, 0, 0 }, + { "ae_mulf32x2r.hl.lh", ICLASS_AE_MULF32X2R_HL_LH, + 0, + Opcode_ae_mulf32x2r_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaf32x2r.hl.lh", ICLASS_AE_MULAF32X2R_HL_LH, + 0, + Opcode_ae_mulaf32x2r_hl_lh_encode_fns, 0, 0 }, + { "ae_mulsf32x2r.hl.lh", ICLASS_AE_MULSF32X2R_HL_LH, + 0, + Opcode_ae_mulsf32x2r_hl_lh_encode_fns, 0, 0 }, + { "ae_mulfc32w", ICLASS_AE_MULFC32W, + 0, + Opcode_ae_mulfc32w_encode_fns, 0, 0 }, + { "ae_mulafc32w", ICLASS_AE_MULAFC32W, + 0, + Opcode_ae_mulafc32w_encode_fns, 0, 0 }, + { "ae_mulfcj32w", ICLASS_AE_MULFCJ32W, + 0, + Opcode_ae_mulfcj32w_encode_fns, 0, 0 }, + { "ae_mulafcj32w", ICLASS_AE_MULAFCJ32W, + 0, + Opcode_ae_mulafcj32w_encode_fns, 0, 0 }, + { "ae_mulfcj32ras", ICLASS_AE_MULFCJ32RAS, + 0, + Opcode_ae_mulfcj32ras_encode_fns, 0, 0 }, + { "ae_mulafcj32ras", ICLASS_AE_MULAFCJ32RAS, + 0, + Opcode_ae_mulafcj32ras_encode_fns, 0, 0 }, + { "ae_mulf2p32x4rs", ICLASS_AE_MULF2P32X4RS, + 0, + Opcode_ae_mulf2p32x4rs_encode_fns, 0, 0 }, + { "ae_mulaf2p32x4rs", ICLASS_AE_MULAF2P32X4RS, + 0, + Opcode_ae_mulaf2p32x4rs_encode_fns, 0, 0 }, + { "ae_mulsf2p32x4rs", ICLASS_AE_MULSF2P32X4RS, + 0, + Opcode_ae_mulsf2p32x4rs_encode_fns, 0, 0 }, + { "ae_mulf2p32x4ras", ICLASS_AE_MULF2P32X4RAS, + 0, + Opcode_ae_mulf2p32x4ras_encode_fns, 0, 0 }, + { "ae_mulaf2p32x4ras", ICLASS_AE_MULAF2P32X4RAS, + 0, + Opcode_ae_mulaf2p32x4ras_encode_fns, 0, 0 }, + { "ae_mulsf2p32x4ras", ICLASS_AE_MULSF2P32X4RAS, + 0, + Opcode_ae_mulsf2p32x4ras_encode_fns, 0, 0 }, + { "ae_mulp32x2s", ICLASS_AE_MULP32X2S, + 0, + Opcode_ae_mulp32x2s_encode_fns, 0, 0 }, + { "ae_mul2p32x4s", ICLASS_AE_MUL2P32X4S, + 0, + Opcode_ae_mul2p32x4s_encode_fns, 0, 0 }, + { "ae_mul2p32x4", ICLASS_AE_MUL2P32X4, + 0, + Opcode_ae_mul2p32x4_encode_fns, 0, 0 }, + { "ae_mula2p32x4", ICLASS_AE_MULA2P32X4, + 0, + Opcode_ae_mula2p32x4_encode_fns, 0, 0 }, + { "ae_muls2p32x4", ICLASS_AE_MULS2P32X4, + 0, + Opcode_ae_muls2p32x4_encode_fns, 0, 0 }, + { "ae_mul2p32x4t", ICLASS_AE_MUL2P32X4T, + 0, + Opcode_ae_mul2p32x4t_encode_fns, 0, 0 }, + { "ae_mula2p32x4t", ICLASS_AE_MULA2P32X4T, + 0, + Opcode_ae_mula2p32x4t_encode_fns, 0, 0 }, + { "ae_muls2p32x4t", ICLASS_AE_MULS2P32X4T, + 0, + Opcode_ae_muls2p32x4t_encode_fns, 0, 0 }, + { "ae_mulzaa32x2.hh.ll", ICLASS_AE_MULZAA32X2_HH_LL, + 0, + Opcode_ae_mulzaa32x2_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzss32x2.hh.ll", ICLASS_AE_MULZSS32X2_HH_LL, + 0, + Opcode_ae_mulzss32x2_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaa32x2.hh.ll", ICLASS_AE_MULAA32X2_HH_LL, + 0, + Opcode_ae_mulaa32x2_hh_ll_encode_fns, 0, 0 }, + { "ae_mulss32x2.hh.ll", ICLASS_AE_MULSS32X2_HH_LL, + 0, + Opcode_ae_mulss32x2_hh_ll_encode_fns, 0, 0 }, + { "ae_mulcj32", ICLASS_AE_MULCJ32, + 0, + Opcode_ae_mulcj32_encode_fns, 0, 0 }, + { "ae_mulacj32", ICLASS_AE_MULACJ32, + 0, + Opcode_ae_mulacj32_encode_fns, 0, 0 }, + { "ae_muladdf32rs", ICLASS_AE_MULADDF32RS, + 0, + Opcode_ae_muladdf32rs_encode_fns, 0, 0 }, + { "ae_muladdf32ras", ICLASS_AE_MULADDF32RAS, + 0, + Opcode_ae_muladdf32ras_encode_fns, 0, 0 }, + { "ae_mulsubf32rs", ICLASS_AE_MULSUBF32RS, + 0, + Opcode_ae_mulsubf32rs_encode_fns, 0, 0 }, + { "ae_mulsubf32ras", ICLASS_AE_MULSUBF32RAS, + 0, + Opcode_ae_mulsubf32ras_encode_fns, 0, 0 }, + { "ae_mulfc32ra", ICLASS_AE_MULFC32RA, + 0, + Opcode_ae_mulfc32ra_encode_fns, 0, 0 }, + { "ae_mulafc32ra", ICLASS_AE_MULAFC32RA, + 0, + Opcode_ae_mulafc32ra_encode_fns, 0, 0 }, + { "ae_mulcj32w", ICLASS_AE_MULCJ32W, + 0, + Opcode_ae_mulcj32w_encode_fns, 0, 0 }, + { "ae_mulacj32w", ICLASS_AE_MULACJ32W, + 0, + Opcode_ae_mulacj32w_encode_fns, 0, 0 }, + { "ae_mulc32w", ICLASS_AE_MULC32W, + 0, + Opcode_ae_mulc32w_encode_fns, 0, 0 }, + { "ae_mulac32w", ICLASS_AE_MULAC32W, + 0, + Opcode_ae_mulac32w_encode_fns, 0, 0 }, + { "ae_mulf2d32x2ws", ICLASS_AE_MULF2D32X2WS, + 0, + Opcode_ae_mulf2d32x2ws_encode_fns, 0, 0 }, + { "ae_mulzaaaa2q16", ICLASS_AE_MULZAAAA2Q16, + 0, + Opcode_ae_mulzaaaa2q16_encode_fns, 0, 0 }, + { "ae_mulaaaa2q16", ICLASS_AE_MULAAAA2Q16, + 0, + Opcode_ae_mulaaaa2q16_encode_fns, 0, 0 }, + { "ae_mulp16s.h", ICLASS_AE_MULP16S_H, + 0, + Opcode_ae_mulp16s_h_encode_fns, 0, 0 }, + { "ae_mulap16s.h", ICLASS_AE_MULAP16S_H, + 0, + Opcode_ae_mulap16s_h_encode_fns, 0, 0 }, + { "ae_mulsp16s.h", ICLASS_AE_MULSP16S_H, + 0, + Opcode_ae_mulsp16s_h_encode_fns, 0, 0 }, + { "ae_mulp16s.l", ICLASS_AE_MULP16S_L, + 0, + Opcode_ae_mulp16s_l_encode_fns, 0, 0 }, + { "ae_mulap16s.l", ICLASS_AE_MULAP16S_L, + 0, + Opcode_ae_mulap16s_l_encode_fns, 0, 0 }, + { "ae_mulsp16s.l", ICLASS_AE_MULSP16S_L, + 0, + Opcode_ae_mulsp16s_l_encode_fns, 0, 0 }, + { "ae_mulc16w.h", ICLASS_AE_MULC16W_H, + 0, + Opcode_ae_mulc16w_h_encode_fns, 0, 0 }, + { "ae_mulac16w.h", ICLASS_AE_MULAC16W_H, + 0, + Opcode_ae_mulac16w_h_encode_fns, 0, 0 }, + { "ae_mulc16w.l", ICLASS_AE_MULC16W_L, + 0, + Opcode_ae_mulc16w_l_encode_fns, 0, 0 }, + { "ae_mulac16w.l", ICLASS_AE_MULAC16W_L, + 0, + Opcode_ae_mulac16w_l_encode_fns, 0, 0 }, + { "ae_mul2c16s", ICLASS_AE_MUL2C16S, + 0, + Opcode_ae_mul2c16s_encode_fns, 0, 0 }, + { "ae_mula2c16s", ICLASS_AE_MULA2C16S, + 0, + Opcode_ae_mula2c16s_encode_fns, 0, 0 }, + { "ae_mulfc16s", ICLASS_AE_MULFC16S, + 0, + Opcode_ae_mulfc16s_encode_fns, 0, 0 }, + { "ae_mulafc16s", ICLASS_AE_MULAFC16S, + 0, + Opcode_ae_mulafc16s_encode_fns, 0, 0 }, + { "ae_mulfcj16s", ICLASS_AE_MULFCJ16S, + 0, + Opcode_ae_mulfcj16s_encode_fns, 0, 0 }, + { "ae_mulafcj16s", ICLASS_AE_MULAFCJ16S, + 0, + Opcode_ae_mulafcj16s_encode_fns, 0, 0 }, + { "ae_mulfcj16ras", ICLASS_AE_MULFCJ16RAS, + 0, + Opcode_ae_mulfcj16ras_encode_fns, 0, 0 }, + { "ae_mulafcj16ras", ICLASS_AE_MULAFCJ16RAS, + 0, + Opcode_ae_mulafcj16ras_encode_fns, 0, 0 }, + { "ae_mulc16s", ICLASS_AE_MULC16S, + 0, + Opcode_ae_mulc16s_encode_fns, 0, 0 }, + { "ae_mulac16s", ICLASS_AE_MULAC16S, + 0, + Opcode_ae_mulac16s_encode_fns, 0, 0 }, + { "ae_mulfp16x4rs", ICLASS_AE_MULFP16X4RS, + 0, + Opcode_ae_mulfp16x4rs_encode_fns, 0, 0 }, + { "ae_mulfd16x16x4ras", ICLASS_AE_MULFD16X16X4RAS, + 0, + Opcode_ae_mulfd16x16x4ras_encode_fns, 0, 0 }, + { "ae_mulp16x16x4s", ICLASS_AE_MULP16X16X4S, + 0, + Opcode_ae_mulp16x16x4s_encode_fns, 0, 0 }, + { "ae_mulap16x16x4s", ICLASS_AE_MULAP16X16X4S, + 0, + Opcode_ae_mulap16x16x4s_encode_fns, 0, 0 }, + { "ae_mulsp16x16x4s", ICLASS_AE_MULSP16X16X4S, + 0, + Opcode_ae_mulsp16x16x4s_encode_fns, 0, 0 }, + { "ae_mulzaa2d16ss.hh_ll", ICLASS_AE_MULZAA2D16SS_HH_LL, + 0, + Opcode_ae_mulzaa2d16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaa2d16ss.hl_lh", ICLASS_AE_MULZAA2D16SS_HL_LH, + 0, + Opcode_ae_mulzaa2d16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzss2d16ss.hh_ll", ICLASS_AE_MULZSS2D16SS_HH_LL, + 0, + Opcode_ae_mulzss2d16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzss2d16ss.hl_lh", ICLASS_AE_MULZSS2D16SS_HL_LH, + 0, + Opcode_ae_mulzss2d16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaa2d16ss.hh_ll", ICLASS_AE_MULAA2D16SS_HH_LL, + 0, + Opcode_ae_mulaa2d16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaa2d16ss.hl_lh", ICLASS_AE_MULAA2D16SS_HL_LH, + 0, + Opcode_ae_mulaa2d16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulss2d16ss.hh_ll", ICLASS_AE_MULSS2D16SS_HH_LL, + 0, + Opcode_ae_mulss2d16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulss2d16ss.hl_lh", ICLASS_AE_MULSS2D16SS_HL_LH, + 0, + Opcode_ae_mulss2d16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzaafd16ss.hh_ll", ICLASS_AE_MULZAAFD16SS_HH_LL, + 0, + Opcode_ae_mulzaafd16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzaafd16ss.hl_lh", ICLASS_AE_MULZAAFD16SS_HL_LH, + 0, + Opcode_ae_mulzaafd16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulzssfd16ss.hh_ll", ICLASS_AE_MULZSSFD16SS_HH_LL, + 0, + Opcode_ae_mulzssfd16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulzssfd16ss.hl_lh", ICLASS_AE_MULZSSFD16SS_HL_LH, + 0, + Opcode_ae_mulzssfd16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulaafd16ss.hh_ll", ICLASS_AE_MULAAFD16SS_HH_LL, + 0, + Opcode_ae_mulaafd16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulaafd16ss.hl_lh", ICLASS_AE_MULAAFD16SS_HL_LH, + 0, + Opcode_ae_mulaafd16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulssfd16ss.hh_ll", ICLASS_AE_MULSSFD16SS_HH_LL, + 0, + Opcode_ae_mulssfd16ss_hh_ll_encode_fns, 0, 0 }, + { "ae_mulssfd16ss.hl_lh", ICLASS_AE_MULSSFD16SS_HL_LH, + 0, + Opcode_ae_mulssfd16ss_hl_lh_encode_fns, 0, 0 }, + { "ae_mulfd16x16x4ws", ICLASS_AE_MULFD16X16X4WS, + 0, + Opcode_ae_mulfd16x16x4ws_encode_fns, 0, 0 }, + { "ae_mulzaaaa2q16x8", ICLASS_AE_MULZAAAA2Q16X8, + 0, + Opcode_ae_mulzaaaa2q16x8_encode_fns, 0, 0 }, + { "ae_mulaaaa2q16x8", ICLASS_AE_MULAAAA2Q16X8, + 0, + Opcode_ae_mulaaaa2q16x8_encode_fns, 0, 0 }, + { "ae_mulzaaaa2q8", ICLASS_AE_MULZAAAA2Q8, + 0, + Opcode_ae_mulzaaaa2q8_encode_fns, 0, 0 }, + { "ae_mulaaaa2q8", ICLASS_AE_MULAAAA2Q8, + 0, + Opcode_ae_mulaaaa2q8_encode_fns, 0, 0 }, + { "ae_mulc32x16w.h", ICLASS_AE_MULC32X16W_H, + 0, + Opcode_ae_mulc32x16w_h_encode_fns, 0, 0 }, + { "ae_mulac32x16w.h", ICLASS_AE_MULAC32X16W_H, + 0, + Opcode_ae_mulac32x16w_h_encode_fns, 0, 0 }, + { "ae_mulc32x16w.l", ICLASS_AE_MULC32X16W_L, + 0, + Opcode_ae_mulc32x16w_l_encode_fns, 0, 0 }, + { "ae_mulac32x16w.l", ICLASS_AE_MULAC32X16W_L, + 0, + Opcode_ae_mulac32x16w_l_encode_fns, 0, 0 }, + { "ae_mulpc32x16x2", ICLASS_AE_MULPC32X16X2, + 0, + Opcode_ae_mulpc32x16x2_encode_fns, 0, 0 }, + { "ae_mulapc32x16x2", ICLASS_AE_MULAPC32X16X2, + 0, + Opcode_ae_mulapc32x16x2_encode_fns, 0, 0 }, + { "ae_mulfp32x16.h", ICLASS_AE_MULFP32X16_H, + 0, + Opcode_ae_mulfp32x16_h_encode_fns, 0, 0 }, + { "ae_mulafp32x16.h", ICLASS_AE_MULAFP32X16_H, + 0, + Opcode_ae_mulafp32x16_h_encode_fns, 0, 0 }, + { "ae_mulsfp32x16.h", ICLASS_AE_MULSFP32X16_H, + 0, + Opcode_ae_mulsfp32x16_h_encode_fns, 0, 0 }, + { "ae_mulfp32x16.l", ICLASS_AE_MULFP32X16_L, + 0, + Opcode_ae_mulfp32x16_l_encode_fns, 0, 0 }, + { "ae_mulafp32x16.l", ICLASS_AE_MULAFP32X16_L, + 0, + Opcode_ae_mulafp32x16_l_encode_fns, 0, 0 }, + { "ae_mulsfp32x16.l", ICLASS_AE_MULSFP32X16_L, + 0, + Opcode_ae_mulsfp32x16_l_encode_fns, 0, 0 }, + { "ae_mulfc32x16w.h", ICLASS_AE_MULFC32X16W_H, + 0, + Opcode_ae_mulfc32x16w_h_encode_fns, 0, 0 }, + { "ae_mulafc32x16w.h", ICLASS_AE_MULAFC32X16W_H, + 0, + Opcode_ae_mulafc32x16w_h_encode_fns, 0, 0 }, + { "ae_mulfc32x16w.l", ICLASS_AE_MULFC32X16W_L, + 0, + Opcode_ae_mulfc32x16w_l_encode_fns, 0, 0 }, + { "ae_mulafc32x16w.l", ICLASS_AE_MULAFC32X16W_L, + 0, + Opcode_ae_mulafc32x16w_l_encode_fns, 0, 0 }, + { "ae_mulfcj32x16w.h", ICLASS_AE_MULFCJ32X16W_H, + 0, + Opcode_ae_mulfcj32x16w_h_encode_fns, 0, 0 }, + { "ae_mulafcj32x16w.h", ICLASS_AE_MULAFCJ32X16W_H, + 0, + Opcode_ae_mulafcj32x16w_h_encode_fns, 0, 0 }, + { "ae_mulfcj32x16w.l", ICLASS_AE_MULFCJ32X16W_L, + 0, + Opcode_ae_mulfcj32x16w_l_encode_fns, 0, 0 }, + { "ae_mulafcj32x16w.l", ICLASS_AE_MULAFCJ32X16W_L, + 0, + Opcode_ae_mulafcj32x16w_l_encode_fns, 0, 0 }, + { "ae_mulf2p32x16x4ras", ICLASS_AE_MULF2P32X16X4RAS, + 0, + Opcode_ae_mulf2p32x16x4ras_encode_fns, 0, 0 }, + { "ae_mulaf2p32x16x4ras", ICLASS_AE_MULAF2P32X16X4RAS, + 0, + Opcode_ae_mulaf2p32x16x4ras_encode_fns, 0, 0 }, + { "ae_mulsf2p32x16x4ras", ICLASS_AE_MULSF2P32X16X4RAS, + 0, + Opcode_ae_mulsf2p32x16x4ras_encode_fns, 0, 0 }, + { "ae_mulf2p32x16x4rs", ICLASS_AE_MULF2P32X16X4RS, + 0, + Opcode_ae_mulf2p32x16x4rs_encode_fns, 0, 0 }, + { "ae_mulaf2p32x16x4rs", ICLASS_AE_MULAF2P32X16X4RS, + 0, + Opcode_ae_mulaf2p32x16x4rs_encode_fns, 0, 0 }, + { "ae_mulsf2p32x16x4rs", ICLASS_AE_MULSF2P32X16X4RS, + 0, + Opcode_ae_mulsf2p32x16x4rs_encode_fns, 0, 0 }, + { "ae_mulf2p32x16x4s", ICLASS_AE_MULF2P32X16X4S, + 0, + Opcode_ae_mulf2p32x16x4s_encode_fns, 0, 0 }, + { "ae_mulaf2p32x16x4s", ICLASS_AE_MULAF2P32X16X4S, + 0, + Opcode_ae_mulaf2p32x16x4s_encode_fns, 0, 0 }, + { "ae_mulsf2p32x16x4s", ICLASS_AE_MULSF2P32X16X4S, + 0, + Opcode_ae_mulsf2p32x16x4s_encode_fns, 0, 0 }, + { "ae_mulfpc32x16x2ras", ICLASS_AE_MULFPC32X16X2RAS, + 0, + Opcode_ae_mulfpc32x16x2ras_encode_fns, 0, 0 }, + { "ae_mulafpc32x16x2ras", ICLASS_AE_MULAFPC32X16X2RAS, + 0, + Opcode_ae_mulafpc32x16x2ras_encode_fns, 0, 0 }, + { "ae_mulfpcj32x16x2ras", ICLASS_AE_MULFPCJ32X16X2RAS, + 0, + Opcode_ae_mulfpcj32x16x2ras_encode_fns, 0, 0 }, + { "ae_mulafpcj32x16x2ras", ICLASS_AE_MULAFPCJ32X16X2RAS, + 0, + Opcode_ae_mulafpcj32x16x2ras_encode_fns, 0, 0 }, + { "ae_mulzaaaa2q32x16", ICLASS_AE_MULZAAAA2Q32X16, + 0, + Opcode_ae_mulzaaaa2q32x16_encode_fns, 0, 0 }, + { "ae_mulaaaa2q32x16", ICLASS_AE_MULAAAA2Q32X16, + 0, + Opcode_ae_mulaaaa2q32x16_encode_fns, 0, 0 }, + { "ae_mul2q32x16.fir.h", ICLASS_AE_MUL2Q32X16_FIR_H, + 0, + Opcode_ae_mul2q32x16_fir_h_encode_fns, 0, 0 }, + { "ae_mula2q32x16.fir.h", ICLASS_AE_MULA2Q32X16_FIR_H, + 0, + Opcode_ae_mula2q32x16_fir_h_encode_fns, 0, 0 }, + { "ae_mul2q32x16.fir.l", ICLASS_AE_MUL2Q32X16_FIR_L, + 0, + Opcode_ae_mul2q32x16_fir_l_encode_fns, 0, 0 }, + { "ae_mula2q32x16.fir.l", ICLASS_AE_MULA2Q32X16_FIR_L, + 0, + Opcode_ae_mula2q32x16_fir_l_encode_fns, 0, 0 }, + { "ae_srai8", ICLASS_AE_SRAI8, + 0, + Opcode_ae_srai8_encode_fns, 0, 0 }, + { "ae_srai8r", ICLASS_AE_SRAI8R, + 0, + Opcode_ae_srai8r_encode_fns, 0, 0 }, + { "ae_srli8", ICLASS_AE_SRLI8, + 0, + Opcode_ae_srli8_encode_fns, 0, 0 }, + { "ae_slai8", ICLASS_AE_SLAI8, + 0, + Opcode_ae_slai8_encode_fns, 0, 0 }, + { "ae_slai8s", ICLASS_AE_SLAI8S, + 0, + Opcode_ae_slai8s_encode_fns, 0, 0 }, + { "ae_slaa8", ICLASS_AE_SLAA8, + 0, + Opcode_ae_slaa8_encode_fns, 0, 0 }, + { "ae_srla8", ICLASS_AE_SRLA8, + 0, + Opcode_ae_srla8_encode_fns, 0, 0 }, + { "ae_slaa8s", ICLASS_AE_SLAA8S, + 0, + Opcode_ae_slaa8s_encode_fns, 0, 0 }, + { "ae_sraa8rs", ICLASS_AE_SRAA8RS, + 0, + Opcode_ae_sraa8rs_encode_fns, 0, 0 }, + { "ae_sraa8s", ICLASS_AE_SRAA8S, + 0, + Opcode_ae_sraa8s_encode_fns, 0, 0 }, + { "ae_srli16", ICLASS_AE_SRLI16, + 0, + Opcode_ae_srli16_encode_fns, 0, 0 }, + { "ae_slai16", ICLASS_AE_SLAI16, + 0, + Opcode_ae_slai16_encode_fns, 0, 0 }, + { "ae_slaa16", ICLASS_AE_SLAA16, + 0, + Opcode_ae_slaa16_encode_fns, 0, 0 }, + { "ae_srla16", ICLASS_AE_SRLA16, + 0, + Opcode_ae_srla16_encode_fns, 0, 0 }, + { "ae_srai16sym", ICLASS_AE_SRAI16SYM, + 0, + Opcode_ae_srai16sym_encode_fns, 0, 0 }, + { "ae_sraa16syms", ICLASS_AE_SRAA16SYMS, + 0, + Opcode_ae_sraa16syms_encode_fns, 0, 0 }, + { "ae_srai32sym", ICLASS_AE_SRAI32SYM, + 0, + Opcode_ae_srai32sym_encode_fns, 0, 0 }, + { "ae_sraa32syms", ICLASS_AE_SRAA32SYMS, + 0, + Opcode_ae_sraa32syms_encode_fns, 0, 0 }, + { "ae_srav16rs", ICLASS_AE_SRAV16RS, + 0, + Opcode_ae_srav16rs_encode_fns, 0, 0 }, + { "ae_srav32rs", ICLASS_AE_SRAV32RS, + 0, + Opcode_ae_srav32rs_encode_fns, 0, 0 }, + { "ae_cvti32x4f8.h", ICLASS_AE_CVTI32X4F8_H, + 0, + Opcode_ae_cvti32x4f8_h_encode_fns, 0, 0 }, + { "ae_cvti32x4f8.l", ICLASS_AE_CVTI32X4F8_L, + 0, + Opcode_ae_cvti32x4f8_l_encode_fns, 0, 0 }, + { "ae_cvti32x4f8s.h", ICLASS_AE_CVTI32X4F8S_H, + 0, + Opcode_ae_cvti32x4f8s_h_encode_fns, 0, 0 }, + { "ae_cvti32x4f8s.l", ICLASS_AE_CVTI32X4F8S_L, + 0, + Opcode_ae_cvti32x4f8s_l_encode_fns, 0, 0 }, + { "ae_cvta32x4f8.h", ICLASS_AE_CVTA32X4F8_H, + 0, + Opcode_ae_cvta32x4f8_h_encode_fns, 0, 0 }, + { "ae_cvta32x4f8.l", ICLASS_AE_CVTA32X4F8_L, + 0, + Opcode_ae_cvta32x4f8_l_encode_fns, 0, 0 }, + { "ae_cvta32x4f8s.h", ICLASS_AE_CVTA32X4F8S_H, + 0, + Opcode_ae_cvta32x4f8s_h_encode_fns, 0, 0 }, + { "ae_cvta32x4f8s.l", ICLASS_AE_CVTA32X4F8S_L, + 0, + Opcode_ae_cvta32x4f8s_l_encode_fns, 0, 0 }, + { "ae_cvti32x4f8u.h", ICLASS_AE_CVTI32X4F8U_H, + 0, + Opcode_ae_cvti32x4f8u_h_encode_fns, 0, 0 }, + { "ae_cvti32x4f8u.l", ICLASS_AE_CVTI32X4F8U_L, + 0, + Opcode_ae_cvti32x4f8u_l_encode_fns, 0, 0 }, + { "ae_cvti32x4f8us.h", ICLASS_AE_CVTI32X4F8US_H, + 0, + Opcode_ae_cvti32x4f8us_h_encode_fns, 0, 0 }, + { "ae_cvti32x4f8us.l", ICLASS_AE_CVTI32X4F8US_L, + 0, + Opcode_ae_cvti32x4f8us_l_encode_fns, 0, 0 }, + { "ae_cvta32x4f8u.h", ICLASS_AE_CVTA32X4F8U_H, + 0, + Opcode_ae_cvta32x4f8u_h_encode_fns, 0, 0 }, + { "ae_cvta32x4f8u.l", ICLASS_AE_CVTA32X4F8U_L, + 0, + Opcode_ae_cvta32x4f8u_l_encode_fns, 0, 0 }, + { "ae_cvta32x4f8us.h", ICLASS_AE_CVTA32X4F8US_H, + 0, + Opcode_ae_cvta32x4f8us_h_encode_fns, 0, 0 }, + { "ae_cvta32x4f8us.l", ICLASS_AE_CVTA32X4F8US_L, + 0, + Opcode_ae_cvta32x4f8us_l_encode_fns, 0, 0 }, + { "ae_cvti32x4f16", ICLASS_AE_CVTI32X4F16, + 0, + Opcode_ae_cvti32x4f16_encode_fns, 0, 0 }, + { "ae_cvti32x4f16s", ICLASS_AE_CVTI32X4F16S, + 0, + Opcode_ae_cvti32x4f16s_encode_fns, 0, 0 }, + { "ae_cvta32x4f16", ICLASS_AE_CVTA32X4F16, + 0, + Opcode_ae_cvta32x4f16_encode_fns, 0, 0 }, + { "ae_cvta32x4f16s", ICLASS_AE_CVTA32X4F16S, + 0, + Opcode_ae_cvta32x4f16s_encode_fns, 0, 0 }, + { "ae_cvti32x4f16u", ICLASS_AE_CVTI32X4F16U, + 0, + Opcode_ae_cvti32x4f16u_encode_fns, 0, 0 }, + { "ae_cvti32x4f16us", ICLASS_AE_CVTI32X4F16US, + 0, + Opcode_ae_cvti32x4f16us_encode_fns, 0, 0 }, + { "ae_cvta32x4f16u", ICLASS_AE_CVTA32X4F16U, + 0, + Opcode_ae_cvta32x4f16u_encode_fns, 0, 0 }, + { "ae_cvta32x4f16us", ICLASS_AE_CVTA32X4F16US, + 0, + Opcode_ae_cvta32x4f16us_encode_fns, 0, 0 }, + { "ae_cvti16x4x2f8", ICLASS_AE_CVTI16X4X2F8, + 0, + Opcode_ae_cvti16x4x2f8_encode_fns, 0, 0 }, + { "ae_cvti16x4x2f8s", ICLASS_AE_CVTI16X4X2F8S, + 0, + Opcode_ae_cvti16x4x2f8s_encode_fns, 0, 0 }, + { "ae_cvta16x4x2f8", ICLASS_AE_CVTA16X4X2F8, + 0, + Opcode_ae_cvta16x4x2f8_encode_fns, 0, 0 }, + { "ae_cvta16x4x2f8s", ICLASS_AE_CVTA16X4X2F8S, + 0, + Opcode_ae_cvta16x4x2f8s_encode_fns, 0, 0 }, + { "ae_cvti16x4x2f8u", ICLASS_AE_CVTI16X4X2F8U, + 0, + Opcode_ae_cvti16x4x2f8u_encode_fns, 0, 0 }, + { "ae_cvti16x4x2f8us", ICLASS_AE_CVTI16X4X2F8US, + 0, + Opcode_ae_cvti16x4x2f8us_encode_fns, 0, 0 }, + { "ae_cvta16x4x2f8u", ICLASS_AE_CVTA16X4X2F8U, + 0, + Opcode_ae_cvta16x4x2f8u_encode_fns, 0, 0 }, + { "ae_cvta16x4x2f8us", ICLASS_AE_CVTA16X4X2F8US, + 0, + Opcode_ae_cvta16x4x2f8us_encode_fns, 0, 0 }, + { "ae_sel8x8", ICLASS_AE_SEL8X8, + 0, + Opcode_ae_sel8x8_encode_fns, 0, 0 }, + { "ae_shfl8x8", ICLASS_AE_SHFL8X8, + 0, + Opcode_ae_shfl8x8_encode_fns, 0, 0 }, + { "ae_sel16x4", ICLASS_AE_SEL16X4, + 0, + Opcode_ae_sel16x4_encode_fns, 0, 0 }, + { "ae_shfl16x4", ICLASS_AE_SHFL16X4, + 0, + Opcode_ae_shfl16x4_encode_fns, 0, 0 }, + { "ae_dsel8x8", ICLASS_AE_DSEL8X8, + 0, + Opcode_ae_dsel8x8_encode_fns, 0, 0 }, + { "ae_dsel16x4", ICLASS_AE_DSEL16X4, + 0, + Opcode_ae_dsel16x4_encode_fns, 0, 0 }, + { "ae_sel8x8i", ICLASS_AE_SEL8X8I, + 0, + Opcode_ae_sel8x8i_encode_fns, 0, 0 }, + { "ae_rmax8x8", ICLASS_AE_RMAX8X8, + 0, + Opcode_ae_rmax8x8_encode_fns, 0, 0 }, + { "ae_rmin8x8", ICLASS_AE_RMIN8X8, + 0, + Opcode_ae_rmin8x8_encode_fns, 0, 0 }, + { "ae_rmax16x4", ICLASS_AE_RMAX16X4, + 0, + Opcode_ae_rmax16x4_encode_fns, 0, 0 }, + { "ae_rmin16x4", ICLASS_AE_RMIN16X4, + 0, + Opcode_ae_rmin16x4_encode_fns, 0, 0 }, + { "ae_sort16x4", ICLASS_AE_SORT16X4, + 0, + Opcode_ae_sort16x4_encode_fns, 0, 0 }, + { "ae_radd8x8.h", ICLASS_AE_RADD8X8_H, + 0, + Opcode_ae_radd8x8_h_encode_fns, 0, 0 }, + { "ae_radda8x8.h", ICLASS_AE_RADDA8X8_H, + 0, + Opcode_ae_radda8x8_h_encode_fns, 0, 0 }, + { "ae_radd8x8.l", ICLASS_AE_RADD8X8_L, + 0, + Opcode_ae_radd8x8_l_encode_fns, 0, 0 }, + { "ae_radda8x8.l", ICLASS_AE_RADDA8X8_L, + 0, + Opcode_ae_radda8x8_l_encode_fns, 0, 0 }, + { "ae_radd16x4", ICLASS_AE_RADD16X4, + 0, + Opcode_ae_radd16x4_encode_fns, 0, 0 }, + { "ae_radda16x4", ICLASS_AE_RADDA16X4, + 0, + Opcode_ae_radda16x4_encode_fns, 0, 0 }, + { "ae_bmax8x8.h", ICLASS_AE_BMAX8X8_H, + 0, + Opcode_ae_bmax8x8_h_encode_fns, 0, 0 }, + { "ae_bmax8x8.l", ICLASS_AE_BMAX8X8_L, + 0, + Opcode_ae_bmax8x8_l_encode_fns, 0, 0 }, + { "ae_bmin8x8.h", ICLASS_AE_BMIN8X8_H, + 0, + Opcode_ae_bmin8x8_h_encode_fns, 0, 0 }, + { "ae_bmin8x8.l", ICLASS_AE_BMIN8X8_L, + 0, + Opcode_ae_bmin8x8_l_encode_fns, 0, 0 }, + { "ae_bmax16x4", ICLASS_AE_BMAX16X4, + 0, + Opcode_ae_bmax16x4_encode_fns, 0, 0 }, + { "ae_bmin16x4", ICLASS_AE_BMIN16X4, + 0, + Opcode_ae_bmin16x4_encode_fns, 0, 0 }, + { "ae_bmax32x2", ICLASS_AE_BMAX32X2, + 0, + Opcode_ae_bmax32x2_encode_fns, 0, 0 }, + { "ae_bmin32x2", ICLASS_AE_BMIN32X2, + 0, + Opcode_ae_bmin32x2_encode_fns, 0, 0 }, + { "ae_addinv16s", ICLASS_AE_ADDINV16S, + 0, + Opcode_ae_addinv16s_encode_fns, 0, 0 }, + { "ae_addinv32s", ICLASS_AE_ADDINV32S, + 0, + Opcode_ae_addinv32s_encode_fns, 0, 0 }, + { "ae_movt16x8", ICLASS_AE_MOVT16X8, + 0, + Opcode_ae_movt16x8_encode_fns, 0, 0 }, + { "ae_movt8x16.h", ICLASS_AE_MOVT8X16_H, + 0, + Opcode_ae_movt8x16_h_encode_fns, 0, 0 }, + { "ae_movt8x16.l", ICLASS_AE_MOVT8X16_L, + 0, + Opcode_ae_movt8x16_l_encode_fns, 0, 0 }, + { "ae_movbd1x4", ICLASS_AE_MOVBD1X4, + 0, + Opcode_ae_movbd1x4_encode_fns, 0, 0 }, + { "ae_movbd1x2", ICLASS_AE_MOVBD1X2, + 0, + Opcode_ae_movbd1x2_encode_fns, 0, 0 }, + { "ae_movneg32s_t", ICLASS_AE_MOVNEG32S_T, + 0, + Opcode_ae_movneg32s_t_encode_fns, 0, 0 }, + { "ae_movdext", ICLASS_AE_MOVDEXT, + 0, + Opcode_ae_movdext_encode_fns, 0, 0 }, + { "ae_movadext.h", ICLASS_AE_MOVADEXT_H, + 0, + Opcode_ae_movadext_h_encode_fns, 0, 0 }, + { "ae_movadext.l", ICLASS_AE_MOVADEXT_L, + 0, + Opcode_ae_movadext_l_encode_fns, 0, 0 }, + { "ae_nsa16x4", ICLASS_AE_NSA16X4, + 0, + Opcode_ae_nsa16x4_encode_fns, 0, 0 }, + { "ae_nsaz32x4", ICLASS_AE_NSAZ32X4, + 0, + Opcode_ae_nsaz32x4_encode_fns, 0, 0 }, + { "ae_nsa32x4", ICLASS_AE_NSA32X4, + 0, + Opcode_ae_nsa32x4_encode_fns, 0, 0 }, + { "ae_trunci16x4f32s", ICLASS_AE_TRUNCI16X4F32S, + 0, + Opcode_ae_trunci16x4f32s_encode_fns, 0, 0 }, + { "ae_trunci16x4f64s", ICLASS_AE_TRUNCI16X4F64S, + 0, + Opcode_ae_trunci16x4f64s_encode_fns, 0, 0 }, + { "ae_trunca16x4f32s", ICLASS_AE_TRUNCA16X4F32S, + 0, + Opcode_ae_trunca16x4f32s_encode_fns, 0, 0 }, + { "ae_trunca16x4f64s", ICLASS_AE_TRUNCA16X4F64S, + 0, + Opcode_ae_trunca16x4f64s_encode_fns, 0, 0 }, + { "ae_addc32", ICLASS_AE_ADDC32, + 0, + Opcode_ae_addc32_encode_fns, 0, 0 }, + { "ae_subc32", ICLASS_AE_SUBC32, + 0, + Opcode_ae_subc32_encode_fns, 0, 0 }, + { "ae_addc32u", ICLASS_AE_ADDC32U, + 0, + Opcode_ae_addc32u_encode_fns, 0, 0 }, + { "ae_subc32u", ICLASS_AE_SUBC32U, + 0, + Opcode_ae_subc32u_encode_fns, 0, 0 }, + { "ae_expadd16.h", ICLASS_AE_EXPADD16_H, + 0, + Opcode_ae_expadd16_h_encode_fns, 0, 0 }, + { "ae_expsub16.h", ICLASS_AE_EXPSUB16_H, + 0, + Opcode_ae_expsub16_h_encode_fns, 0, 0 }, + { "ae_expadd16.l", ICLASS_AE_EXPADD16_L, + 0, + Opcode_ae_expadd16_l_encode_fns, 0, 0 }, + { "ae_expsub16.l", ICLASS_AE_EXPSUB16_L, + 0, + Opcode_ae_expsub16_l_encode_fns, 0, 0 }, + { "ae_addcexp32.h", ICLASS_AE_ADDCEXP32_H, + 0, + Opcode_ae_addcexp32_h_encode_fns, 0, 0 }, + { "ae_addcexp32.l", ICLASS_AE_ADDCEXP32_L, + 0, + Opcode_ae_addcexp32_l_encode_fns, 0, 0 }, + { "ae_calcrng16", ICLASS_AE_CALCRNG16, + 0, + Opcode_ae_calcrng16_encode_fns, 0, 0 }, + { "ae_calcrng32", ICLASS_AE_CALCRNG32, + 0, + Opcode_ae_calcrng32_encode_fns, 0, 0 }, + { "ae_rng32x4", ICLASS_AE_RNG32X4, + 0, + Opcode_ae_rng32x4_encode_fns, 0, 0 }, + { "ae_lav8x8x2_xp", ICLASS_AE_LAV8X8X2_XP, + 0, + Opcode_ae_lav8x8x2_xp_encode_fns, 1, Opcode_ae_lav8x8x2_xp_funcUnit_uses }, + { "ae_lav16x4x2_xp", ICLASS_AE_LAV16X4X2_XP, + 0, + Opcode_ae_lav16x4x2_xp_encode_fns, 1, Opcode_ae_lav16x4x2_xp_funcUnit_uses }, + { "ae_sav8x8x2_xp", ICLASS_AE_SAV8X8X2_XP, + 0, + Opcode_ae_sav8x8x2_xp_encode_fns, 1, Opcode_ae_sav8x8x2_xp_funcUnit_uses }, + { "ae_sav16x4x2_xp", ICLASS_AE_SAV16X4X2_XP, + 0, + Opcode_ae_sav16x4x2_xp_encode_fns, 1, Opcode_ae_sav16x4x2_xp_funcUnit_uses }, + { "ae_movzbvcdr", ICLASS_AE_MOVZBVCDR, + 0, + Opcode_ae_movzbvcdr_encode_fns, 0, 0 }, + { "ae_movdrzbvc", ICLASS_AE_MOVDRZBVC, + 0, + Opcode_ae_movdrzbvc_encode_fns, 0, 0 }, + { "ae_lavunsqz8x8_xp", ICLASS_AE_LAVUNSQZ8X8_XP, + 0, + Opcode_ae_lavunsqz8x8_xp_encode_fns, 1, Opcode_ae_lavunsqz8x8_xp_funcUnit_uses }, + { "ae_lavunsqz16x4_xp", ICLASS_AE_LAVUNSQZ16X4_XP, + 0, + Opcode_ae_lavunsqz16x4_xp_encode_fns, 1, Opcode_ae_lavunsqz16x4_xp_funcUnit_uses }, + { "ae_mul8q8x8", ICLASS_AE_MUL8Q8X8, + 0, + Opcode_ae_mul8q8x8_encode_fns, 0, 0 }, + { "ae_mula8q8x8", ICLASS_AE_MULA8Q8X8, + 0, + Opcode_ae_mula8q8x8_encode_fns, 0, 0 }, + { "ae_mul8q4x16", ICLASS_AE_MUL8Q4X16, + 0, + Opcode_ae_mul8q4x16_encode_fns, 0, 0 }, + { "ae_mula8q4x16", ICLASS_AE_MULA8Q4X16, + 0, + Opcode_ae_mula8q4x16_encode_fns, 0, 0 }, + { "ae_mul8q8x16", ICLASS_AE_MUL8Q8X16, + 0, + Opcode_ae_mul8q8x16_encode_fns, 0, 0 }, + { "ae_mula8q8x16", ICLASS_AE_MULA8Q8X16, + 0, + Opcode_ae_mula8q8x16_encode_fns, 0, 0 }, + { "ae_mul8qw8x16", ICLASS_AE_MUL8QW8X16, + 0, + Opcode_ae_mul8qw8x16_encode_fns, 0, 0 }, + { "ae_mula8qw8x16", ICLASS_AE_MULA8QW8X16, + 0, + Opcode_ae_mula8qw8x16_encode_fns, 0, 0 }, + { "ae_mul4o8x8", ICLASS_AE_MUL4O8X8, + 0, + Opcode_ae_mul4o8x8_encode_fns, 0, 0 }, + { "ae_mula4o8x8", ICLASS_AE_MULA4O8X8, + 0, + Opcode_ae_mula4o8x8_encode_fns, 0, 0 }, + { "ae_mul4o4x16", ICLASS_AE_MUL4O4X16, + 0, + Opcode_ae_mul4o4x16_encode_fns, 0, 0 }, + { "ae_mula4o4x16", ICLASS_AE_MULA4O4X16, + 0, + Opcode_ae_mula4o4x16_encode_fns, 0, 0 }, + { "ae_mul4o8x16", ICLASS_AE_MUL4O8X16, + 0, + Opcode_ae_mul4o8x16_encode_fns, 0, 0 }, + { "ae_mula4o8x16", ICLASS_AE_MULA4O8X16, + 0, + Opcode_ae_mula4o8x16_encode_fns, 0, 0 }, + { "ae_mul4qw8x16", ICLASS_AE_MUL4QW8X16, + 0, + Opcode_ae_mul4qw8x16_encode_fns, 0, 0 }, + { "ae_mula4qw8x16", ICLASS_AE_MULA4QW8X16, + 0, + Opcode_ae_mula4qw8x16_encode_fns, 0, 0 }, + { "ae_mul8q8x8cnv_l", ICLASS_AE_MUL8Q8X8CNV_L, + 0, + Opcode_ae_mul8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mul8q8x8cnv_h", ICLASS_AE_MUL8Q8X8CNV_H, + 0, + Opcode_ae_mul8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mula8q8x8cnv_l", ICLASS_AE_MULA8Q8X8CNV_L, + 0, + Opcode_ae_mula8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mula8q8x8cnv_h", ICLASS_AE_MULA8Q8X8CNV_H, + 0, + Opcode_ae_mula8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mul8q8x16cnv", ICLASS_AE_MUL8Q8X16CNV, + 0, + Opcode_ae_mul8q8x16cnv_encode_fns, 0, 0 }, + { "ae_mula8q8x16cnv", ICLASS_AE_MULA8Q8X16CNV, + 0, + Opcode_ae_mula8q8x16cnv_encode_fns, 0, 0 }, + { "ae_mul2x4q8x8cnv_h", ICLASS_AE_MUL2X4Q8X8CNV_H, + 0, + Opcode_ae_mul2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mula2x4q8x8cnv_h", ICLASS_AE_MULA2X4Q8X8CNV_H, + 0, + Opcode_ae_mula2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mul2x4q8x8cnv_l", ICLASS_AE_MUL2X4Q8X8CNV_L, + 0, + Opcode_ae_mul2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mula2x4q8x8cnv_l", ICLASS_AE_MULA2X4Q8X8CNV_L, + 0, + Opcode_ae_mula2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mul2x4q8x16cnv", ICLASS_AE_MUL2X4Q8X16CNV, + 0, + Opcode_ae_mul2x4q8x16cnv_encode_fns, 0, 0 }, + { "ae_mula2x4q8x16cnv", ICLASS_AE_MULA2X4Q8X16CNV, + 0, + Opcode_ae_mula2x4q8x16cnv_encode_fns, 0, 0 }, + { "ae_mulqq8x16cnv", ICLASS_AE_MULQQ8X16CNV, + 0, + Opcode_ae_mulqq8x16cnv_encode_fns, 0, 0 }, + { "ae_mulaqq8x16cnv", ICLASS_AE_MULAQQ8X16CNV, + 0, + Opcode_ae_mulaqq8x16cnv_encode_fns, 0, 0 }, + { "ae_mul4o8x8cnv_h", ICLASS_AE_MUL4O8X8CNV_H, + 0, + Opcode_ae_mul4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mula4o8x8cnv_h", ICLASS_AE_MULA4O8X8CNV_H, + 0, + Opcode_ae_mula4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mul4o8x8cnv_l", ICLASS_AE_MUL4O8X8CNV_L, + 0, + Opcode_ae_mul4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mula4o8x8cnv_l", ICLASS_AE_MULA4O8X8CNV_L, + 0, + Opcode_ae_mula4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mul4o8x16cnv_h", ICLASS_AE_MUL4O8X16CNV_H, + 0, + Opcode_ae_mul4o8x16cnv_h_encode_fns, 0, 0 }, + { "ae_mula4o8x16cnv_h", ICLASS_AE_MULA4O8X16CNV_H, + 0, + Opcode_ae_mula4o8x16cnv_h_encode_fns, 0, 0 }, + { "ae_mul4o8x16cnv_l", ICLASS_AE_MUL4O8X16CNV_L, + 0, + Opcode_ae_mul4o8x16cnv_l_encode_fns, 0, 0 }, + { "ae_mula4o8x16cnv_l", ICLASS_AE_MULA4O8X16CNV_L, + 0, + Opcode_ae_mula4o8x16cnv_l_encode_fns, 0, 0 }, + { "ae_mul8q4x16cnv_h", ICLASS_AE_MUL8Q4X16CNV_H, + 0, + Opcode_ae_mul8q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mula8q4x16cnv_h", ICLASS_AE_MULA8Q4X16CNV_H, + 0, + Opcode_ae_mula8q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mul8q4x16cnv_l", ICLASS_AE_MUL8Q4X16CNV_L, + 0, + Opcode_ae_mul8q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mula8q4x16cnv_l", ICLASS_AE_MULA8Q4X16CNV_L, + 0, + Opcode_ae_mula8q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mul2x4q4x16cnv_h", ICLASS_AE_MUL2X4Q4X16CNV_H, + 0, + Opcode_ae_mul2x4q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mula2x4q4x16cnv_h", ICLASS_AE_MULA2X4Q4X16CNV_H, + 0, + Opcode_ae_mula2x4q4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mul2x4q4x16cnv_l", ICLASS_AE_MUL2X4Q4X16CNV_L, + 0, + Opcode_ae_mul2x4q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mula2x4q4x16cnv_l", ICLASS_AE_MULA2X4Q4X16CNV_L, + 0, + Opcode_ae_mula2x4q4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulqq4x16cnv_h", ICLASS_AE_MULQQ4X16CNV_H, + 0, + Opcode_ae_mulqq4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulaqq4x16cnv_h", ICLASS_AE_MULAQQ4X16CNV_H, + 0, + Opcode_ae_mulaqq4x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulqq4x16cnv_l", ICLASS_AE_MULQQ4X16CNV_L, + 0, + Opcode_ae_mulqq4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulaqq4x16cnv_l", ICLASS_AE_MULAQQ4X16CNV_L, + 0, + Opcode_ae_mulaqq4x16cnv_l_encode_fns, 0, 0 }, + { "ae_mul4o4x16cnv_hh", ICLASS_AE_MUL4O4X16CNV_HH, + 0, + Opcode_ae_mul4o4x16cnv_hh_encode_fns, 0, 0 }, + { "ae_mul4o4x16cnv_hl", ICLASS_AE_MUL4O4X16CNV_HL, + 0, + Opcode_ae_mul4o4x16cnv_hl_encode_fns, 0, 0 }, + { "ae_mul4o4x16cnv_lh", ICLASS_AE_MUL4O4X16CNV_LH, + 0, + Opcode_ae_mul4o4x16cnv_lh_encode_fns, 0, 0 }, + { "ae_mul4o4x16cnv_ll", ICLASS_AE_MUL4O4X16CNV_LL, + 0, + Opcode_ae_mul4o4x16cnv_ll_encode_fns, 0, 0 }, + { "ae_mula4o4x16cnv_hh", ICLASS_AE_MULA4O4X16CNV_HH, + 0, + Opcode_ae_mula4o4x16cnv_hh_encode_fns, 0, 0 }, + { "ae_mula4o4x16cnv_hl", ICLASS_AE_MULA4O4X16CNV_HL, + 0, + Opcode_ae_mula4o4x16cnv_hl_encode_fns, 0, 0 }, + { "ae_mula4o4x16cnv_lh", ICLASS_AE_MULA4O4X16CNV_LH, + 0, + Opcode_ae_mula4o4x16cnv_lh_encode_fns, 0, 0 }, + { "ae_mula4o4x16cnv_ll", ICLASS_AE_MULA4O4X16CNV_LL, + 0, + Opcode_ae_mula4o4x16cnv_ll_encode_fns, 0, 0 }, + { "ae_muluu8q8x8", ICLASS_AE_MULUU8Q8X8, + 0, + Opcode_ae_muluu8q8x8_encode_fns, 0, 0 }, + { "ae_mulauu8q8x8", ICLASS_AE_MULAUU8Q8X8, + 0, + Opcode_ae_mulauu8q8x8_encode_fns, 0, 0 }, + { "ae_muluu4o8x8", ICLASS_AE_MULUU4O8X8, + 0, + Opcode_ae_muluu4o8x8_encode_fns, 0, 0 }, + { "ae_mulauu4o8x8", ICLASS_AE_MULAUU4O8X8, + 0, + Opcode_ae_mulauu4o8x8_encode_fns, 0, 0 }, + { "ae_muluu8q8x8cnv_l", ICLASS_AE_MULUU8Q8X8CNV_L, + 0, + Opcode_ae_muluu8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauu8q8x8cnv_l", ICLASS_AE_MULAUU8Q8X8CNV_L, + 0, + Opcode_ae_mulauu8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluu8q8x8cnv_h", ICLASS_AE_MULUU8Q8X8CNV_H, + 0, + Opcode_ae_muluu8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauu8q8x8cnv_h", ICLASS_AE_MULAUU8Q8X8CNV_H, + 0, + Opcode_ae_mulauu8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluu2x4q8x8cnv_h", ICLASS_AE_MULUU2X4Q8X8CNV_H, + 0, + Opcode_ae_muluu2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauu2x4q8x8cnv_h", ICLASS_AE_MULAUU2X4Q8X8CNV_H, + 0, + Opcode_ae_mulauu2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluu2x4q8x8cnv_l", ICLASS_AE_MULUU2X4Q8X8CNV_L, + 0, + Opcode_ae_muluu2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauu2x4q8x8cnv_l", ICLASS_AE_MULAUU2X4Q8X8CNV_L, + 0, + Opcode_ae_mulauu2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluu4o8x8cnv_h", ICLASS_AE_MULUU4O8X8CNV_H, + 0, + Opcode_ae_muluu4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauu4o8x8cnv_h", ICLASS_AE_MULAUU4O8X8CNV_H, + 0, + Opcode_ae_mulauu4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluu4o8x8cnv_l", ICLASS_AE_MULUU4O8X8CNV_L, + 0, + Opcode_ae_muluu4o8x8cnv_l_encode_fns, 0, 0 }, + { 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ICLASS_AE_MULAUS4O8X8, + 0, + Opcode_ae_mulaus4o8x8_encode_fns, 0, 0 }, + { "ae_mulus4o4x16", ICLASS_AE_MULUS4O4X16, + 0, + Opcode_ae_mulus4o4x16_encode_fns, 0, 0 }, + { "ae_mulaus4o4x16", ICLASS_AE_MULAUS4O4X16, + 0, + Opcode_ae_mulaus4o4x16_encode_fns, 0, 0 }, + { "ae_mulus4o8x16", ICLASS_AE_MULUS4O8X16, + 0, + Opcode_ae_mulus4o8x16_encode_fns, 0, 0 }, + { "ae_mulaus4o8x16", ICLASS_AE_MULAUS4O8X16, + 0, + Opcode_ae_mulaus4o8x16_encode_fns, 0, 0 }, + { "ae_mulus4qw8x16", ICLASS_AE_MULUS4QW8X16, + 0, + Opcode_ae_mulus4qw8x16_encode_fns, 0, 0 }, + { "ae_mulaus4qw8x16", ICLASS_AE_MULAUS4QW8X16, + 0, + Opcode_ae_mulaus4qw8x16_encode_fns, 0, 0 }, + { "ae_mulus8q8x8cnv_l", ICLASS_AE_MULUS8Q8X8CNV_L, + 0, + Opcode_ae_mulus8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulaus8q8x8cnv_l", ICLASS_AE_MULAUS8Q8X8CNV_L, + 0, + Opcode_ae_mulaus8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulus8q8x8cnv_h", ICLASS_AE_MULUS8Q8X8CNV_H, + 0, + Opcode_ae_mulus8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulaus8q8x8cnv_h", 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ICLASS_AE_MULUSQQ8X16CNV, + 0, + Opcode_ae_mulusqq8x16cnv_encode_fns, 0, 0 }, + { "ae_mulausqq8x16cnv", ICLASS_AE_MULAUSQQ8X16CNV, + 0, + Opcode_ae_mulausqq8x16cnv_encode_fns, 0, 0 }, + { "ae_mulus4o8x8cnv_h", ICLASS_AE_MULUS4O8X8CNV_H, + 0, + Opcode_ae_mulus4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulaus4o8x8cnv_h", ICLASS_AE_MULAUS4O8X8CNV_H, + 0, + Opcode_ae_mulaus4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulus4o8x8cnv_l", ICLASS_AE_MULUS4O8X8CNV_L, + 0, + Opcode_ae_mulus4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulaus4o8x8cnv_l", ICLASS_AE_MULAUS4O8X8CNV_L, + 0, + Opcode_ae_mulaus4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulus4o8x16cnv_h", ICLASS_AE_MULUS4O8X16CNV_H, + 0, + Opcode_ae_mulus4o8x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulaus4o8x16cnv_h", ICLASS_AE_MULAUS4O8X16CNV_H, + 0, + Opcode_ae_mulaus4o8x16cnv_h_encode_fns, 0, 0 }, + { "ae_mulus4o8x16cnv_l", ICLASS_AE_MULUS4O8X16CNV_L, + 0, + Opcode_ae_mulus4o8x16cnv_l_encode_fns, 0, 0 }, + { "ae_mulaus4o8x16cnv_l", ICLASS_AE_MULAUS4O8X16CNV_L, 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Opcode_ae_mulasu4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluuzb8q8x8", ICLASS_AE_MULUUZB8Q8X8, + 0, + Opcode_ae_muluuzb8q8x8_encode_fns, 0, 0 }, + { "ae_mulauuzb8q8x8", ICLASS_AE_MULAUUZB8Q8X8, + 0, + Opcode_ae_mulauuzb8q8x8_encode_fns, 0, 0 }, + { "ae_muluuzb4o8x8", ICLASS_AE_MULUUZB4O8X8, + 0, + Opcode_ae_muluuzb4o8x8_encode_fns, 0, 0 }, + { "ae_mulauuzb4o8x8", ICLASS_AE_MULAUUZB4O8X8, + 0, + Opcode_ae_mulauuzb4o8x8_encode_fns, 0, 0 }, + { "ae_muluuzb8q8x8cnv_l", ICLASS_AE_MULUUZB8Q8X8CNV_L, + 0, + Opcode_ae_muluuzb8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauuzb8q8x8cnv_l", ICLASS_AE_MULAUUZB8Q8X8CNV_L, + 0, + Opcode_ae_mulauuzb8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluuzb8q8x8cnv_h", ICLASS_AE_MULUUZB8Q8X8CNV_H, + 0, + Opcode_ae_muluuzb8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauuzb8q8x8cnv_h", ICLASS_AE_MULAUUZB8Q8X8CNV_H, + 0, + Opcode_ae_mulauuzb8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluuzb2x4q8x8cnv_h", ICLASS_AE_MULUUZB2X4Q8X8CNV_H, + 0, + Opcode_ae_muluuzb2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauuzb2x4q8x8cnv_h", ICLASS_AE_MULAUUZB2X4Q8X8CNV_H, + 0, + Opcode_ae_mulauuzb2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluuzb2x4q8x8cnv_l", ICLASS_AE_MULUUZB2X4Q8X8CNV_L, + 0, + Opcode_ae_muluuzb2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauuzb2x4q8x8cnv_l", ICLASS_AE_MULAUUZB2X4Q8X8CNV_L, + 0, + Opcode_ae_mulauuzb2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluuzb4o8x8cnv_h", ICLASS_AE_MULUUZB4O8X8CNV_H, + 0, + Opcode_ae_muluuzb4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulauuzb4o8x8cnv_h", ICLASS_AE_MULAUUZB4O8X8CNV_H, + 0, + Opcode_ae_mulauuzb4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_muluuzb4o8x8cnv_l", ICLASS_AE_MULUUZB4O8X8CNV_L, + 0, + Opcode_ae_muluuzb4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulauuzb4o8x8cnv_l", ICLASS_AE_MULAUUZB4O8X8CNV_L, + 0, + Opcode_ae_mulauuzb4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_muluuzb3x3o8x8", ICLASS_AE_MULUUZB3X3O8X8, + 0, + Opcode_ae_muluuzb3x3o8x8_encode_fns, 0, 0 }, + { "ae_mulauuzb3x3o8x8", ICLASS_AE_MULAUUZB3X3O8X8, + 0, + Opcode_ae_mulauuzb3x3o8x8_encode_fns, 0, 0 }, + { "ae_mulzb8q8x8", ICLASS_AE_MULZB8Q8X8, + 0, + Opcode_ae_mulzb8q8x8_encode_fns, 0, 0 }, + { "ae_mulazb8q8x8", ICLASS_AE_MULAZB8Q8X8, + 0, + Opcode_ae_mulazb8q8x8_encode_fns, 0, 0 }, + { "ae_mulzb4o8x8", ICLASS_AE_MULZB4O8X8, + 0, + Opcode_ae_mulzb4o8x8_encode_fns, 0, 0 }, + { "ae_mulazb4o8x8", ICLASS_AE_MULAZB4O8X8, + 0, + Opcode_ae_mulazb4o8x8_encode_fns, 0, 0 }, + { "ae_mulzb8q8x8cnv_l", ICLASS_AE_MULZB8Q8X8CNV_L, + 0, + Opcode_ae_mulzb8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulazb8q8x8cnv_l", ICLASS_AE_MULAZB8Q8X8CNV_L, + 0, + Opcode_ae_mulazb8q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulzb8q8x8cnv_h", ICLASS_AE_MULZB8Q8X8CNV_H, + 0, + Opcode_ae_mulzb8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulazb8q8x8cnv_h", ICLASS_AE_MULAZB8Q8X8CNV_H, + 0, + Opcode_ae_mulazb8q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulzb2x4q8x8cnv_h", ICLASS_AE_MULZB2X4Q8X8CNV_H, + 0, + Opcode_ae_mulzb2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulazb2x4q8x8cnv_h", ICLASS_AE_MULAZB2X4Q8X8CNV_H, + 0, + Opcode_ae_mulazb2x4q8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulzb2x4q8x8cnv_l", ICLASS_AE_MULZB2X4Q8X8CNV_L, + 0, + Opcode_ae_mulzb2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulazb2x4q8x8cnv_l", ICLASS_AE_MULAZB2X4Q8X8CNV_L, + 0, + Opcode_ae_mulazb2x4q8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulzb4o8x8cnv_h", ICLASS_AE_MULZB4O8X8CNV_H, + 0, + Opcode_ae_mulzb4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulazb4o8x8cnv_h", ICLASS_AE_MULAZB4O8X8CNV_H, + 0, + Opcode_ae_mulazb4o8x8cnv_h_encode_fns, 0, 0 }, + { "ae_mulzb4o8x8cnv_l", ICLASS_AE_MULZB4O8X8CNV_L, + 0, + Opcode_ae_mulzb4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulazb4o8x8cnv_l", ICLASS_AE_MULAZB4O8X8CNV_L, + 0, + Opcode_ae_mulazb4o8x8cnv_l_encode_fns, 0, 0 }, + { "ae_mulzb3x3o8x8", ICLASS_AE_MULZB3X3O8X8, + 0, + Opcode_ae_mulzb3x3o8x8_encode_fns, 0, 0 }, + { "ae_mulazb3x3o8x8", ICLASS_AE_MULAZB3X3O8X8, + 0, + Opcode_ae_mulazb3x3o8x8_encode_fns, 0, 0 }, + { "cvtsf16.l", ICLASS_CVTSF16_L, + 0, + Opcode_cvtsf16_l_encode_fns, 0, 0 }, + { "cvtsf16.h", ICLASS_CVTSF16_H, + 0, + Opcode_cvtsf16_h_encode_fns, 0, 0 }, + { "cvtf16s.l", ICLASS_CVTF16S_L, + 0, + Opcode_cvtf16s_l_encode_fns, 0, 0 }, + { "cvtf16s.h", ICLASS_CVTF16S_H, + 0, + Opcode_cvtf16s_h_encode_fns, 0, 0 }, + { "ae_movfcrfsrv", ICLASS_AE_MOVFCRFSRV, + 0, + Opcode_ae_movfcrfsrv_encode_fns, 0, 0 }, + { "ae_movvfcrfsr", ICLASS_AE_MOVVFCRFSR, + 0, + Opcode_ae_movvfcrfsr_encode_fns, 0, 0 }, + { "movt.s", ICLASS_MOVT_S, + 0, + Opcode_movt_s_encode_fns, 0, 0 }, + { "movf.s", ICLASS_MOVF_S, + 0, + Opcode_movf_s_encode_fns, 0, 0 }, + { "moveqz.s", ICLASS_MOVEQZ_S, + 0, + Opcode_moveqz_s_encode_fns, 0, 0 }, + { "movnez.s", ICLASS_MOVNEZ_S, + 0, + Opcode_movnez_s_encode_fns, 0, 0 }, + { "movgez.s", ICLASS_MOVGEZ_S, + 0, + Opcode_movgez_s_encode_fns, 0, 0 }, + { "movltz.s", ICLASS_MOVLTZ_S, + 0, + Opcode_movltz_s_encode_fns, 0, 0 }, + { "rfr", ICLASS_RFR, + 0, + Opcode_rfr_encode_fns, 0, 0 }, + { "wfr", ICLASS_WFR, + 0, + Opcode_wfr_encode_fns, 0, 0 }, + { "mul.s", ICLASS_MUL_S, + 0, + Opcode_mul_s_encode_fns, 0, 0 }, + { "madd.s", ICLASS_MADD_S, + 0, + Opcode_madd_s_encode_fns, 0, 0 }, + { "msub.s", ICLASS_MSUB_S, + 0, + Opcode_msub_s_encode_fns, 0, 0 }, + { "msubn.s", ICLASS_MSUBN_S, + 0, + Opcode_msubn_s_encode_fns, 0, 0 }, + { "maddn.s", ICLASS_MADDN_S, + 0, + Opcode_maddn_s_encode_fns, 0, 0 }, + { "add.s", ICLASS_ADD_S, + 0, + Opcode_add_s_encode_fns, 0, 0 }, + { "sub.s", ICLASS_SUB_S, + 0, + Opcode_sub_s_encode_fns, 0, 0 }, + { "ole.s", ICLASS_OLE_S, + 0, + Opcode_ole_s_encode_fns, 0, 0 }, + { "olt.s", ICLASS_OLT_S, + 0, + Opcode_olt_s_encode_fns, 0, 0 }, + { "oeq.s", ICLASS_OEQ_S, + 0, + Opcode_oeq_s_encode_fns, 0, 0 }, + { "un.s", ICLASS_UN_S, + 0, + Opcode_un_s_encode_fns, 0, 0 }, + { "ule.s", ICLASS_ULE_S, + 0, + Opcode_ule_s_encode_fns, 0, 0 }, + { "ult.s", ICLASS_ULT_S, + 0, + Opcode_ult_s_encode_fns, 0, 0 }, + { "ueq.s", ICLASS_UEQ_S, + 0, + Opcode_ueq_s_encode_fns, 0, 0 }, + { "nexp01.s", ICLASS_NEXP01_S, + 0, + Opcode_nexp01_s_encode_fns, 0, 0 }, + { "mksadj.s", ICLASS_MKSADJ_S, + 0, + Opcode_mksadj_s_encode_fns, 0, 0 }, + { "mkdadj.s", ICLASS_MKDADJ_S, + 0, + Opcode_mkdadj_s_encode_fns, 0, 0 }, + { "div0.s", ICLASS_DIV0_S, + 0, + Opcode_div0_s_encode_fns, 0, 0 }, + { "sqrt0.s", ICLASS_SQRT0_S, + 0, + Opcode_sqrt0_s_encode_fns, 0, 0 }, + { "recip0.s", ICLASS_RECIP0_S, + 0, + Opcode_recip0_s_encode_fns, 0, 0 }, + { "rsqrt0.s", ICLASS_RSQRT0_S, + 0, + Opcode_rsqrt0_s_encode_fns, 0, 0 }, + { "divn.s", ICLASS_DIVN_S, + 0, + Opcode_divn_s_encode_fns, 0, 0 }, + { "addexp.s", ICLASS_ADDEXP_S, + 0, + Opcode_addexp_s_encode_fns, 0, 0 }, + { "addexpm.s", ICLASS_ADDEXPM_S, + 0, + Opcode_addexpm_s_encode_fns, 0, 0 }, + { "min.s", ICLASS_MIN_S, + 0, + Opcode_min_s_encode_fns, 0, 0 }, + { "max.s", ICLASS_MAX_S, + 0, + Opcode_max_s_encode_fns, 0, 0 }, + { "mulmux.s", ICLASS_MULMUX_S, + 0, + Opcode_mulmux_s_encode_fns, 0, 0 }, + { "maddmux.s", ICLASS_MADDMUX_S, + 0, + Opcode_maddmux_s_encode_fns, 0, 0 }, + { "trunc.s", ICLASS_TRUNC_S, + 0, + Opcode_trunc_s_encode_fns, 0, 0 }, + { "utrunc.s", ICLASS_UTRUNC_S, + 0, + Opcode_utrunc_s_encode_fns, 0, 0 }, + { "trunc.sx2", ICLASS_TRUNC_SX2, + 0, + Opcode_trunc_sx2_encode_fns, 0, 0 }, + { "utrunc.sx2", ICLASS_UTRUNC_SX2, + 0, + Opcode_utrunc_sx2_encode_fns, 0, 0 }, + { "ficeil.s", ICLASS_FICEIL_S, + 0, + Opcode_ficeil_s_encode_fns, 0, 0 }, + { "fifloor.s", ICLASS_FIFLOOR_S, + 0, + Opcode_fifloor_s_encode_fns, 0, 0 }, + { "firint.s", ICLASS_FIRINT_S, + 0, + Opcode_firint_s_encode_fns, 0, 0 }, + { "firound.s", ICLASS_FIROUND_S, + 0, + Opcode_firound_s_encode_fns, 0, 0 }, + { "fitrunc.s", ICLASS_FITRUNC_S, + 0, + Opcode_fitrunc_s_encode_fns, 0, 0 }, + { "float.s", ICLASS_FLOAT_S, + 0, + Opcode_float_s_encode_fns, 0, 0 }, + { "ufloat.s", ICLASS_UFLOAT_S, + 0, + Opcode_ufloat_s_encode_fns, 0, 0 }, + { "float.sx2", ICLASS_FLOAT_SX2, + 0, + Opcode_float_sx2_encode_fns, 0, 0 }, + { "ufloat.sx2", ICLASS_UFLOAT_SX2, + 0, + Opcode_ufloat_sx2_encode_fns, 0, 0 }, + { "abs.s", ICLASS_ABS_S, + 0, + Opcode_abs_s_encode_fns, 0, 0 }, + { "neg.s", ICLASS_NEG_S, + 0, + Opcode_neg_s_encode_fns, 0, 0 }, + { "conjc.s", ICLASS_CONJC_S, + 0, + Opcode_conjc_s_encode_fns, 0, 0 }, + { "muljc.s", ICLASS_MULJC_S, + 0, + Opcode_muljc_s_encode_fns, 0, 0 }, + { "const.s", ICLASS_CONST_S, + 0, + Opcode_const_s_encode_fns, 0, 0 }, + { "clsfy.s", ICLASS_CLSFY_S, + 0, + Opcode_clsfy_s_encode_fns, 0, 0 }, + { "minnum.s", ICLASS_MINNUM_S, + 0, + Opcode_minnum_s_encode_fns, 0, 0 }, + { "maxnum.s", ICLASS_MAXNUM_S, + 0, + Opcode_maxnum_s_encode_fns, 0, 0 }, + { "addandsub.s", ICLASS_ADDANDSUB_S, + 0, + Opcode_addandsub_s_encode_fns, 0, 0 }, + { "addandsubjc.s", ICLASS_ADDANDSUBJC_S, + 0, + Opcode_addandsubjc_s_encode_fns, 0, 0 }, + { "add_hl_lh.s", ICLASS_ADD_HL_LH_S, + 0, + Opcode_add_hl_lh_s_encode_fns, 0, 0 }, + { "madda.s", ICLASS_MADDA_S, + 0, + Opcode_madda_s_encode_fns, 0, 0 }, + { "frexp.s", ICLASS_FREXP_S, + 0, + Opcode_frexp_s_encode_fns, 0, 0 }, + { "floatexp.s", ICLASS_FLOATEXP_S, + 0, + Opcode_floatexp_s_encode_fns, 0, 0 }, + { "minnumabs.s", ICLASS_MINNUMABS_S, + 0, + Opcode_minnumabs_s_encode_fns, 0, 0 }, + { "maxnumabs.s", ICLASS_MAXNUMABS_S, + 0, + Opcode_maxnumabs_s_encode_fns, 0, 0 }, + { "mulq.s", ICLASS_MULQ_S, + 0, + Opcode_mulq_s_encode_fns, 0, 0 }, + { "maddq.s", ICLASS_MADDQ_S, + 0, + Opcode_maddq_s_encode_fns, 0, 0 }, + { "msubq.s", ICLASS_MSUBQ_S, + 0, + Opcode_msubq_s_encode_fns, 0, 0 }, + { "mulmuxq.s", ICLASS_MULMUXQ_S, + 0, + Opcode_mulmuxq_s_encode_fns, 0, 0 }, + { "maddmuxq.s", ICLASS_MADDMUXQ_S, + 0, + Opcode_maddmuxq_s_encode_fns, 0, 0 }, + { "bmaxnum.s", ICLASS_BMAXNUM_S, + 0, + Opcode_bmaxnum_s_encode_fns, 0, 0 }, + { "bminnum.s", ICLASS_BMINNUM_S, + 0, + Opcode_bminnum_s_encode_fns, 0, 0 }, + { "bmaxnumabs.s", ICLASS_BMAXNUMABS_S, + 0, + Opcode_bmaxnumabs_s_encode_fns, 0, 0 }, + { "bminnumabs.s", ICLASS_BMINNUMABS_S, + 0, + Opcode_bminnumabs_s_encode_fns, 0, 0 }, + { "abs.sx2x2", ICLASS_ABS_SX2X2, + 0, + Opcode_abs_sx2x2_encode_fns, 0, 0 }, + { "neg.sx2x2", ICLASS_NEG_SX2X2, + 0, + Opcode_neg_sx2x2_encode_fns, 0, 0 }, + { "conjc.sx2x2", ICLASS_CONJC_SX2X2, + 0, + Opcode_conjc_sx2x2_encode_fns, 0, 0 }, + { "muljc.sx2x2", ICLASS_MULJC_SX2X2, + 0, + Opcode_muljc_sx2x2_encode_fns, 0, 0 }, + { "const.sx2x2", ICLASS_CONST_SX2X2, + 0, + Opcode_const_sx2x2_encode_fns, 0, 0 }, + { "add.sx2x2", ICLASS_ADD_SX2X2, + 0, + Opcode_add_sx2x2_encode_fns, 0, 0 }, + { "sub.sx2x2", ICLASS_SUB_SX2X2, + 0, + Opcode_sub_sx2x2_encode_fns, 0, 0 }, + { "mul.sx2x2", ICLASS_MUL_SX2X2, + 0, + Opcode_mul_sx2x2_encode_fns, 0, 0 }, + { "madd.sx2x2", ICLASS_MADD_SX2X2, + 0, + Opcode_madd_sx2x2_encode_fns, 0, 0 }, + { "msub.sx2x2", ICLASS_MSUB_SX2X2, + 0, + Opcode_msub_sx2x2_encode_fns, 0, 0 }, + { "mulmux.sx2x2", ICLASS_MULMUX_SX2X2, + 0, + Opcode_mulmux_sx2x2_encode_fns, 0, 0 }, + { "maddmux.sx2x2", ICLASS_MADDMUX_SX2X2, + 0, + Opcode_maddmux_sx2x2_encode_fns, 0, 0 }, + { "abs.h", ICLASS_ABS_H, + 0, + Opcode_abs_h_encode_fns, 0, 0 }, + { "addexp.h", ICLASS_ADDEXP_H, + 0, + Opcode_addexp_h_encode_fns, 0, 0 }, + { "addexpm.h", ICLASS_ADDEXPM_H, + 0, + Opcode_addexpm_h_encode_fns, 0, 0 }, + { "clsfy.h", ICLASS_CLSFY_H, + 0, + Opcode_clsfy_h_encode_fns, 0, 0 }, + { "conjc.h", ICLASS_CONJC_H, + 0, + Opcode_conjc_h_encode_fns, 0, 0 }, + { "const.h", ICLASS_CONST_H, + 0, + Opcode_const_h_encode_fns, 0, 0 }, + { "min.h", ICLASS_MIN_H, + 0, + Opcode_min_h_encode_fns, 0, 0 }, + { "max.h", ICLASS_MAX_H, + 0, + Opcode_max_h_encode_fns, 0, 0 }, + { "minnum.h", ICLASS_MINNUM_H, + 0, + Opcode_minnum_h_encode_fns, 0, 0 }, + { "maxnum.h", ICLASS_MAXNUM_H, + 0, + Opcode_maxnum_h_encode_fns, 0, 0 }, + { "muljc.h", ICLASS_MULJC_H, + 0, + Opcode_muljc_h_encode_fns, 0, 0 }, + { "neg.h", ICLASS_NEG_H, + 0, + Opcode_neg_h_encode_fns, 0, 0 }, + { "oeq.h", ICLASS_OEQ_H, + 0, + Opcode_oeq_h_encode_fns, 0, 0 }, + { "ole.h", ICLASS_OLE_H, + 0, + Opcode_ole_h_encode_fns, 0, 0 }, + { "olt.h", ICLASS_OLT_H, + 0, + Opcode_olt_h_encode_fns, 0, 0 }, + { "ueq.h", ICLASS_UEQ_H, + 0, + Opcode_ueq_h_encode_fns, 0, 0 }, + { "ule.h", ICLASS_ULE_H, + 0, + Opcode_ule_h_encode_fns, 0, 0 }, + { "ult.h", ICLASS_ULT_H, + 0, + Opcode_ult_h_encode_fns, 0, 0 }, + { "un.h", ICLASS_UN_H, + 0, + Opcode_un_h_encode_fns, 0, 0 }, + { "div0.h", ICLASS_DIV0_H, + 0, + Opcode_div0_h_encode_fns, 0, 0 }, + { "ficeil.h", ICLASS_FICEIL_H, + 0, + Opcode_ficeil_h_encode_fns, 0, 0 }, + { "fifloor.h", ICLASS_FIFLOOR_H, + 0, + Opcode_fifloor_h_encode_fns, 0, 0 }, + { "firint.h", ICLASS_FIRINT_H, + 0, + Opcode_firint_h_encode_fns, 0, 0 }, + { "firound.h", ICLASS_FIROUND_H, + 0, + Opcode_firound_h_encode_fns, 0, 0 }, + { "fitrunc.h", ICLASS_FITRUNC_H, + 0, + Opcode_fitrunc_h_encode_fns, 0, 0 }, + { "mkdadj.h", ICLASS_MKDADJ_H, + 0, + Opcode_mkdadj_h_encode_fns, 0, 0 }, + { "mksadj.h", ICLASS_MKSADJ_H, + 0, + Opcode_mksadj_h_encode_fns, 0, 0 }, + { "nexp0.h", ICLASS_NEXP0_H, + 0, + Opcode_nexp0_h_encode_fns, 0, 0 }, + { "nexp01.h", ICLASS_NEXP01_H, + 0, + Opcode_nexp01_h_encode_fns, 0, 0 }, + { "recip0.h", ICLASS_RECIP0_H, + 0, + Opcode_recip0_h_encode_fns, 0, 0 }, + { "rsqrt0.h", ICLASS_RSQRT0_H, + 0, + Opcode_rsqrt0_h_encode_fns, 0, 0 }, + { "sqrt0.h", ICLASS_SQRT0_H, + 0, + Opcode_sqrt0_h_encode_fns, 0, 0 }, + { "float16.h", ICLASS_FLOAT16_H, + 0, + Opcode_float16_h_encode_fns, 0, 0 }, + { "ufloat16.h", ICLASS_UFLOAT16_H, + 0, + Opcode_ufloat16_h_encode_fns, 0, 0 }, + { "trunc16.h", ICLASS_TRUNC16_H, + 0, + Opcode_trunc16_h_encode_fns, 0, 0 }, + { "utrunc16.h", ICLASS_UTRUNC16_H, + 0, + Opcode_utrunc16_h_encode_fns, 0, 0 }, + { "float16.hx4", ICLASS_FLOAT16_HX4, + 0, + Opcode_float16_hx4_encode_fns, 0, 0 }, + { "ufloat16.hx4", ICLASS_UFLOAT16_HX4, + 0, + Opcode_ufloat16_hx4_encode_fns, 0, 0 }, + { "trunc16.hx4", ICLASS_TRUNC16_HX4, + 0, + Opcode_trunc16_hx4_encode_fns, 0, 0 }, + { "utrunc16.hx4", ICLASS_UTRUNC16_HX4, + 0, + Opcode_utrunc16_hx4_encode_fns, 0, 0 }, + { "add.h", ICLASS_ADD_H, + 0, + Opcode_add_h_encode_fns, 0, 0 }, + { "sub.h", ICLASS_SUB_H, + 0, + Opcode_sub_h_encode_fns, 0, 0 }, + { "mul.h", ICLASS_MUL_H, + 0, + Opcode_mul_h_encode_fns, 0, 0 }, + { "madd.h", ICLASS_MADD_H, + 0, + Opcode_madd_h_encode_fns, 0, 0 }, + { "msub.h", ICLASS_MSUB_H, + 0, + Opcode_msub_h_encode_fns, 0, 0 }, + { "maddn.h", ICLASS_MADDN_H, + 0, + Opcode_maddn_h_encode_fns, 0, 0 }, + { "msubn.h", ICLASS_MSUBN_H, + 0, + Opcode_msubn_h_encode_fns, 0, 0 }, + { "divn.h", ICLASS_DIVN_H, + 0, + Opcode_divn_h_encode_fns, 0, 0 }, + { "rminnum.h", ICLASS_RMINNUM_H, + 0, + Opcode_rminnum_h_encode_fns, 0, 0 }, + { "rmaxnum.h", ICLASS_RMAXNUM_H, + 0, + Opcode_rmaxnum_h_encode_fns, 0, 0 }, + { "abs.hx4x2", ICLASS_ABS_HX4X2, + 0, + Opcode_abs_hx4x2_encode_fns, 0, 0 }, + { "neg.hx4x2", ICLASS_NEG_HX4X2, + 0, + Opcode_neg_hx4x2_encode_fns, 0, 0 }, + { "conjc.hx4x2", ICLASS_CONJC_HX4X2, + 0, + Opcode_conjc_hx4x2_encode_fns, 0, 0 }, + { "const.hx4x2", ICLASS_CONST_HX4X2, + 0, + Opcode_const_hx4x2_encode_fns, 0, 0 }, + { "muljc.hx4x2", ICLASS_MULJC_HX4X2, + 0, + Opcode_muljc_hx4x2_encode_fns, 0, 0 }, + { "add.hx4x2", ICLASS_ADD_HX4X2, + 0, + Opcode_add_hx4x2_encode_fns, 0, 0 }, + { "sub.hx4x2", ICLASS_SUB_HX4X2, + 0, + Opcode_sub_hx4x2_encode_fns, 0, 0 }, + { "mul.hx4x2", ICLASS_MUL_HX4X2, + 0, + Opcode_mul_hx4x2_encode_fns, 0, 0 }, + { "madd.hx4x2", ICLASS_MADD_HX4X2, + 0, + Opcode_madd_hx4x2_encode_fns, 0, 0 }, + { "msub.hx4x2", ICLASS_MSUB_HX4X2, + 0, + Opcode_msub_hx4x2_encode_fns, 0, 0 }, + { "mulq.h", ICLASS_MULQ_H, + 0, + Opcode_mulq_h_encode_fns, 0, 0 }, + { "maddq.h", ICLASS_MADDQ_H, + 0, + Opcode_maddq_h_encode_fns, 0, 0 }, + { "mulcnvh.hx4x2", ICLASS_MULCNVH_HX4X2, + 0, + Opcode_mulcnvh_hx4x2_encode_fns, 0, 0 }, + { "mulacnvh.hx4x2", ICLASS_MULACNVH_HX4X2, + 0, + Opcode_mulacnvh_hx4x2_encode_fns, 0, 0 }, + { "mulcnvl.hx4x2", ICLASS_MULCNVL_HX4X2, + 0, + Opcode_mulcnvl_hx4x2_encode_fns, 0, 0 }, + { "mulacnvl.hx4x2", ICLASS_MULACNVL_HX4X2, + 0, + Opcode_mulacnvl_hx4x2_encode_fns, 0, 0 } +}; + +enum xtensa_opcode_id { + OPCODE_EXCW, + OPCODE_RFE, + OPCODE_RFDE, + OPCODE_SYSCALL, + OPCODE_CALL12, + OPCODE_CALL8, + OPCODE_CALL4, + OPCODE_CALLX12, + OPCODE_CALLX8, + OPCODE_CALLX4, + OPCODE_ENTRY, + OPCODE_MOVSP, + OPCODE_ROTW, + OPCODE_RETW, + OPCODE_RETW_N, + OPCODE_RFWO, + OPCODE_RFWU, + OPCODE_L32E, + OPCODE_S32E, + OPCODE_RSR_WINDOWBASE, + OPCODE_WSR_WINDOWBASE, + OPCODE_XSR_WINDOWBASE, + OPCODE_RSR_WINDOWSTART, + OPCODE_WSR_WINDOWSTART, + OPCODE_XSR_WINDOWSTART, + OPCODE_ADD_N, + OPCODE_ADDI_N, + OPCODE_BEQZ_N, + OPCODE_BNEZ_N, + OPCODE_ILL_N, + OPCODE_L32I_N, + OPCODE_MOV_N, + OPCODE_MOVI_N, + OPCODE_NOP_N, + OPCODE_RET_N, + OPCODE_S32I_N, + OPCODE_RUR_THREADPTR, + OPCODE_WUR_THREADPTR, + OPCODE_ADDI, + OPCODE_ADDMI, + OPCODE_ADD, + OPCODE_ADDX2, + OPCODE_ADDX4, + OPCODE_ADDX8, + OPCODE_SUB, + OPCODE_SUBX2, + OPCODE_SUBX4, + OPCODE_SUBX8, + OPCODE_AND, + OPCODE_OR, + OPCODE_XOR, + OPCODE_BEQI, + OPCODE_BGEI, + OPCODE_BLTI, + OPCODE_BNEI, + OPCODE_BBCI, + OPCODE_BBSI, + OPCODE_BGEUI, + OPCODE_BLTUI, + OPCODE_BALL, + OPCODE_BANY, + OPCODE_BBC, + OPCODE_BBS, + OPCODE_BEQ, + OPCODE_BGE, + OPCODE_BGEU, + OPCODE_BLT, + OPCODE_BLTU, + OPCODE_BNALL, + OPCODE_BNE, + OPCODE_BNONE, + OPCODE_BEQZ, + OPCODE_BGEZ, + OPCODE_BLTZ, + OPCODE_BNEZ, + OPCODE_CALL0, + OPCODE_CALLX0, + OPCODE_EXTUI, + OPCODE_ILL, + OPCODE_J, + OPCODE_JX, + OPCODE_L16UI, + OPCODE_L16SI, + OPCODE_L32I, + OPCODE_L32R, + OPCODE_L8UI, + OPCODE_LOOP, + OPCODE_LOOPGTZ, + OPCODE_LOOPNEZ, + OPCODE_MOVI, + OPCODE_MOVEQZ, + OPCODE_MOVGEZ, + OPCODE_MOVLTZ, + OPCODE_MOVNEZ, + OPCODE_ABS, + OPCODE_NEG, + OPCODE_NOP, + OPCODE_L32EX, + OPCODE_S32EX, + OPCODE_GETEX, + OPCODE_CLREX, + OPCODE_RET, + OPCODE_SIMCALL, + OPCODE_S16I, + OPCODE_S32I, + OPCODE_S32NB, + OPCODE_S8I, + OPCODE_SSA8B, + OPCODE_SSA8L, + OPCODE_SSL, + OPCODE_SSR, + OPCODE_SSAI, + OPCODE_SLL, + OPCODE_SRC, + OPCODE_SRA, + OPCODE_SRL, + OPCODE_SLLI, + OPCODE_SRAI, + OPCODE_SRLI, + OPCODE_MEMW, + OPCODE_EXTW, + OPCODE_ISYNC, + OPCODE_DSYNC, + OPCODE_ESYNC, + OPCODE_RSYNC, + OPCODE_RSIL, + OPCODE_RSR_LEND, + OPCODE_WSR_LEND, + OPCODE_XSR_LEND, + OPCODE_RSR_LCOUNT, + OPCODE_WSR_LCOUNT, + OPCODE_XSR_LCOUNT, + OPCODE_RSR_LBEG, + OPCODE_WSR_LBEG, + OPCODE_XSR_LBEG, + OPCODE_RSR_SAR, + OPCODE_WSR_SAR, + OPCODE_XSR_SAR, + OPCODE_RSR_MEMCTL, + OPCODE_WSR_MEMCTL, + OPCODE_XSR_MEMCTL, + OPCODE_RSR_CONFIGID0, + OPCODE_WSR_CONFIGID0, + OPCODE_RSR_CONFIGID1, + OPCODE_RSR_PS, + OPCODE_WSR_PS, + OPCODE_XSR_PS, + OPCODE_RSR_EPC1, + OPCODE_WSR_EPC1, + OPCODE_XSR_EPC1, + OPCODE_RSR_EXCSAVE1, + OPCODE_WSR_EXCSAVE1, + OPCODE_XSR_EXCSAVE1, + OPCODE_RSR_EPC2, + OPCODE_WSR_EPC2, + OPCODE_XSR_EPC2, + OPCODE_RSR_EXCSAVE2, + OPCODE_WSR_EXCSAVE2, + OPCODE_XSR_EXCSAVE2, + OPCODE_RSR_EPC3, + OPCODE_WSR_EPC3, + OPCODE_XSR_EPC3, + OPCODE_RSR_EXCSAVE3, + OPCODE_WSR_EXCSAVE3, + OPCODE_XSR_EXCSAVE3, + OPCODE_RSR_EPC4, + OPCODE_WSR_EPC4, + OPCODE_XSR_EPC4, + OPCODE_RSR_EXCSAVE4, + OPCODE_WSR_EXCSAVE4, + OPCODE_XSR_EXCSAVE4, + OPCODE_RSR_EPC5, + OPCODE_WSR_EPC5, + OPCODE_XSR_EPC5, + OPCODE_RSR_EXCSAVE5, + OPCODE_WSR_EXCSAVE5, + OPCODE_XSR_EXCSAVE5, + OPCODE_RSR_EPC6, + OPCODE_WSR_EPC6, + OPCODE_XSR_EPC6, + OPCODE_RSR_EXCSAVE6, + OPCODE_WSR_EXCSAVE6, + OPCODE_XSR_EXCSAVE6, + OPCODE_RSR_EPS2, + OPCODE_WSR_EPS2, + OPCODE_XSR_EPS2, + OPCODE_RSR_EPS3, + OPCODE_WSR_EPS3, + OPCODE_XSR_EPS3, + OPCODE_RSR_EPS4, + OPCODE_WSR_EPS4, + OPCODE_XSR_EPS4, + OPCODE_RSR_EPS5, + OPCODE_WSR_EPS5, + OPCODE_XSR_EPS5, + OPCODE_RSR_EPS6, + OPCODE_WSR_EPS6, + OPCODE_XSR_EPS6, + OPCODE_RSR_EXCVADDR, + OPCODE_WSR_EXCVADDR, + OPCODE_XSR_EXCVADDR, + OPCODE_RSR_DEPC, + OPCODE_WSR_DEPC, + OPCODE_XSR_DEPC, + OPCODE_RSR_EXCCAUSE, + OPCODE_WSR_EXCCAUSE, + OPCODE_XSR_EXCCAUSE, + OPCODE_RSR_MISC0, + OPCODE_WSR_MISC0, + OPCODE_XSR_MISC0, + OPCODE_RSR_MISC1, + OPCODE_WSR_MISC1, + OPCODE_XSR_MISC1, + OPCODE_RSR_MISC2, + OPCODE_WSR_MISC2, + OPCODE_XSR_MISC2, + OPCODE_RSR_MISC3, + OPCODE_WSR_MISC3, + OPCODE_XSR_MISC3, + OPCODE_RSR_PRID, + OPCODE_RSR_VECBASE, + OPCODE_WSR_VECBASE, + OPCODE_XSR_VECBASE, + OPCODE_RSR_MPUCFG, + OPCODE_WSR_MPUCFG, + OPCODE_SALT, + OPCODE_SALTU, + OPCODE_RSR_OPMODE, + OPCODE_WSR_OPMODE, + OPCODE_XSR_OPMODE, + OPCODE_MUL16S, + OPCODE_MUL16U, + OPCODE_MULL, + OPCODE_RFI, + OPCODE_WAITI, + OPCODE_RSR_INTERRUPT, + OPCODE_WSR_INTSET, + OPCODE_WSR_INTCLEAR, + OPCODE_RSR_INTENABLE, + OPCODE_WSR_INTENABLE, + OPCODE_XSR_INTENABLE, + OPCODE_BREAK, + OPCODE_BREAK_N, + OPCODE_RSR_DBREAKA0, + OPCODE_WSR_DBREAKA0, + OPCODE_XSR_DBREAKA0, + OPCODE_RSR_DBREAKC0, + OPCODE_WSR_DBREAKC0, + OPCODE_XSR_DBREAKC0, + OPCODE_RSR_DBREAKA1, + OPCODE_WSR_DBREAKA1, + OPCODE_XSR_DBREAKA1, + OPCODE_RSR_DBREAKC1, + OPCODE_WSR_DBREAKC1, + OPCODE_XSR_DBREAKC1, + OPCODE_RSR_IBREAKA0, + OPCODE_WSR_IBREAKA0, + OPCODE_XSR_IBREAKA0, + OPCODE_RSR_IBREAKA1, + OPCODE_WSR_IBREAKA1, + OPCODE_XSR_IBREAKA1, + OPCODE_RSR_IBREAKENABLE, + OPCODE_WSR_IBREAKENABLE, + OPCODE_XSR_IBREAKENABLE, + OPCODE_RSR_DEBUGCAUSE, + OPCODE_WSR_DEBUGCAUSE, + OPCODE_XSR_DEBUGCAUSE, + OPCODE_RSR_ICOUNT, + OPCODE_WSR_ICOUNT, + OPCODE_XSR_ICOUNT, + OPCODE_RSR_ICOUNTLEVEL, + OPCODE_WSR_ICOUNTLEVEL, + OPCODE_XSR_ICOUNTLEVEL, + OPCODE_RSR_DDR, + OPCODE_WSR_DDR, + OPCODE_XSR_DDR, + OPCODE_LDDR32_P, + OPCODE_SDDR32_P, + OPCODE_RFDO, + OPCODE_RFDD, + OPCODE_WSR_MMID, + OPCODE_ANDB, + OPCODE_ANDBC, + OPCODE_ORB, + OPCODE_ORBC, + OPCODE_XORB, + OPCODE_ALL4, + OPCODE_ANY4, + OPCODE_ALL8, + OPCODE_ANY8, + OPCODE_BF, + OPCODE_BT, + OPCODE_MOVF, + OPCODE_MOVT, + OPCODE_RSR_BR, + OPCODE_WSR_BR, + OPCODE_XSR_BR, + OPCODE_RSR_CCOUNT, + OPCODE_WSR_CCOUNT, + OPCODE_XSR_CCOUNT, + OPCODE_RSR_CCOMPARE0, + OPCODE_WSR_CCOMPARE0, + OPCODE_XSR_CCOMPARE0, + OPCODE_RSR_CCOMPARE1, + OPCODE_WSR_CCOMPARE1, + OPCODE_XSR_CCOMPARE1, + OPCODE_RSR_CCOMPARE2, + OPCODE_WSR_CCOMPARE2, + OPCODE_XSR_CCOMPARE2, + OPCODE_IHI, + OPCODE_IPF, + OPCODE_IHU, + OPCODE_IIU, + OPCODE_IPFL, + OPCODE_III, + OPCODE_LICT, + OPCODE_LICW, + OPCODE_SICT, + OPCODE_SICW, + OPCODE_DHWB, + OPCODE_DHWBI, + OPCODE_DIWBUI_P, + OPCODE_DIWB, + OPCODE_DIWBI, + OPCODE_DHI, + OPCODE_DII, + OPCODE_DPFR, + OPCODE_DPFRO, + OPCODE_DPFW, + OPCODE_DPFWO, + OPCODE_DHU, + OPCODE_DIU, + OPCODE_DPFL, + OPCODE_SDCT, + OPCODE_LDCT, + OPCODE_SDCW, + OPCODE_LDCW, + OPCODE_RSR_PREFCTL, + OPCODE_WSR_PREFCTL, + OPCODE_XSR_PREFCTL, + OPCODE_WSR_CACHEADRDIS, + OPCODE_RSR_CACHEADRDIS, + OPCODE_XSR_CACHEADRDIS, + OPCODE_RPTLB0, + OPCODE_PPTLB, + OPCODE_RPTLB1, + OPCODE_WPTLB, + OPCODE_RSR_MPUENB, + OPCODE_WSR_MPUENB, + OPCODE_XSR_MPUENB, + OPCODE_RSR_CPENABLE, + OPCODE_WSR_CPENABLE, + OPCODE_XSR_CPENABLE, + OPCODE_CLAMPS, + OPCODE_MAX, + OPCODE_MAXU, + OPCODE_MIN, + OPCODE_MINU, + OPCODE_NSA, + OPCODE_NSAU, + OPCODE_SEXT, + OPCODE_L32AI, + OPCODE_S32RI, + OPCODE_RSR_ATOMCTL, + OPCODE_WSR_ATOMCTL, + OPCODE_XSR_ATOMCTL, + OPCODE_QUOS, + OPCODE_QUOU, + OPCODE_REMS, + OPCODE_REMU, + OPCODE_RSR_ERACCESS, + OPCODE_WSR_ERACCESS, + OPCODE_XSR_ERACCESS, + OPCODE_RER, + OPCODE_WER, + OPCODE_BEQZ_W15, + OPCODE_BGEZ_W15, + OPCODE_BLTZ_W15, + OPCODE_BNEZ_W15, + OPCODE_BEQI_W15, + OPCODE_BGEI_W15, + OPCODE_BLTI_W15, + OPCODE_BNEI_W15, + OPCODE_BGEUI_W15, + OPCODE_BLTUI_W15, + OPCODE_BBCI_W15, + OPCODE_BBSI_W15, + OPCODE_BALL_W15, + OPCODE_BANY_W15, + OPCODE_BBC_W15, + OPCODE_BBS_W15, + OPCODE_BEQ_W15, + OPCODE_BGEU_W15, + OPCODE_BGE_W15, + OPCODE_BLTU_W15, + OPCODE_BLT_W15, + OPCODE_BNALL_W15, + OPCODE_BNE_W15, + OPCODE_BNONE_W15, + OPCODE_AE_SEXT16, + OPCODE_AE_ZEXT16, + OPCODE_AE_ZEXT8, + OPCODE_AE_CLAMPS16, + OPCODE_RUR_FCR, + OPCODE_WUR_FCR, + OPCODE_RUR_FSR, + OPCODE_WUR_FSR, + OPCODE_READ_IMPWIRE, + OPCODE_SETB_EXPSTATE, + OPCODE_CLRB_EXPSTATE, + OPCODE_WRMSK_EXPSTATE, + OPCODE_RUR_AE_OVF_SAR, + OPCODE_WUR_AE_OVF_SAR, + OPCODE_RUR_AE_BITHEAD, + OPCODE_WUR_AE_BITHEAD, + OPCODE_RUR_AE_TS_FTS_BU_BP, + OPCODE_WUR_AE_TS_FTS_BU_BP, + OPCODE_RUR_AE_CW_SD_NO, + OPCODE_WUR_AE_CW_SD_NO, + OPCODE_RUR_AE_CBEGIN0, + OPCODE_WUR_AE_CBEGIN0, + OPCODE_RUR_AE_CEND0, + OPCODE_WUR_AE_CEND0, + OPCODE_RUR_AE_CBEGIN1, + OPCODE_WUR_AE_CBEGIN1, + OPCODE_RUR_AE_CEND1, + OPCODE_WUR_AE_CEND1, + OPCODE_RUR_AE_CBEGIN2, + OPCODE_WUR_AE_CBEGIN2, + OPCODE_RUR_AE_CEND2, + OPCODE_WUR_AE_CEND2, + OPCODE_RUR_EXPSTATE, + OPCODE_WUR_EXPSTATE, + OPCODE_RUR_AE_OVERFLOW, + OPCODE_WUR_AE_OVERFLOW, + OPCODE_RUR_AE_SAR, + OPCODE_WUR_AE_SAR, + OPCODE_RUR_AE_BITPTR, + OPCODE_WUR_AE_BITPTR, + OPCODE_RUR_AE_BITSUSED, + OPCODE_WUR_AE_BITSUSED, + OPCODE_RUR_AE_TABLESIZE, + OPCODE_WUR_AE_TABLESIZE, + OPCODE_RUR_AE_FIRST_TS, + OPCODE_WUR_AE_FIRST_TS, + OPCODE_RUR_AE_NEXTOFFSET, + OPCODE_WUR_AE_NEXTOFFSET, + OPCODE_RUR_AE_SEARCHDONE, + OPCODE_WUR_AE_SEARCHDONE, + OPCODE_RUR_AE_CWRAP, + OPCODE_WUR_AE_CWRAP, + OPCODE_AE_L8X4F_I, + OPCODE_AE_L8X4F_IP, + OPCODE_AE_L8X4F_X, + OPCODE_AE_L8X4F_XP, + OPCODE_AE_L8X4S_I, + OPCODE_AE_L8X4S_IP, + OPCODE_AE_L8X4S_X, + OPCODE_AE_L8X4S_XP, + OPCODE_AE_L8X4U_I, + OPCODE_AE_L8X4U_IP, + OPCODE_AE_L8X4U_X, + OPCODE_AE_L8X4U_XP, + OPCODE_AE_S8X4U_I, + OPCODE_AE_S8X4U_IP, + OPCODE_AE_S8X4U_X, + OPCODE_AE_S8X4U_XP, + OPCODE_AE_L16M_XC, + OPCODE_AE_L16M_XC1, + OPCODE_AE_L16M_I, + OPCODE_AE_L16M_IU, + OPCODE_AE_L16M_X, + OPCODE_AE_L16M_XU, + OPCODE_AE_L16_XC, + OPCODE_AE_L16_XC1, + OPCODE_AE_L16_I, + OPCODE_AE_L16_IP, + OPCODE_AE_L16_X, + OPCODE_AE_L16_XP, + OPCODE_AE_L8_XC, + OPCODE_AE_L8_XC1, + OPCODE_AE_L8_I, + OPCODE_AE_L8_IP, + OPCODE_AE_L8_X, + OPCODE_AE_L8_XP, + OPCODE_AE_L32F24_XC, + OPCODE_AE_L32F24_XC1, + OPCODE_AE_L32F24_I, + OPCODE_AE_L32F24_IP, + OPCODE_AE_L32F24_X, + OPCODE_AE_L32F24_XP, + OPCODE_AE_L32_XC, + OPCODE_AE_L32_XC1, + OPCODE_AE_L32_I, + OPCODE_AE_L32_IP, + OPCODE_AE_L32_X, + OPCODE_AE_L32_XP, + OPCODE_AE_L32M_XC, + OPCODE_AE_L32M_I, + OPCODE_AE_L32M_IU, + OPCODE_AE_L32M_X, + OPCODE_AE_L32M_XU, + OPCODE_AE_L16X2M_XC, + OPCODE_AE_L16X2M_XC1, + OPCODE_AE_L16X2M_I, + OPCODE_AE_L16X2M_IU, + OPCODE_AE_L16X2M_X, + OPCODE_AE_L16X2M_XU, + OPCODE_AE_L32X2F24_XC, + OPCODE_AE_L32X2F24_XC1, + OPCODE_AE_L32X2F24_I, + OPCODE_AE_L32X2F24_IP, + OPCODE_AE_L32X2F24_RIP, + OPCODE_AE_L32X2F24_RI, + OPCODE_AE_L32X2F24_RIC, + OPCODE_AE_L32X2F24_RIC1, + OPCODE_AE_L32X2F24_X, + OPCODE_AE_L32X2F24_XP, + OPCODE_AE_L32X2_XC, + OPCODE_AE_L32X2_XC1, + OPCODE_AE_L32X2_I, + OPCODE_AE_L32X2_IP, + OPCODE_AE_L32X2_RIC, + OPCODE_AE_L32X2_RIC1, + OPCODE_AE_L32X2_X, + OPCODE_AE_L32X2_XP, + OPCODE_AE_L16X4_XC, + OPCODE_AE_L16X4_XC1, + OPCODE_AE_L16X4_I, + OPCODE_AE_L16X4_IP, + OPCODE_AE_L16X4_X, + OPCODE_AE_L16X4_XP, + OPCODE_AE_L8X8_XC, + OPCODE_AE_L8X8_XC1, + OPCODE_AE_L8X8_I, + OPCODE_AE_L8X8_IP, + OPCODE_AE_L8X8_X, + OPCODE_AE_L8X8_XP, + OPCODE_AE_L64_XC, + OPCODE_AE_L64_XC1, + OPCODE_AE_L64_I, + OPCODE_AE_L64_IP, + OPCODE_AE_L64_X, + OPCODE_AE_L64_XP, + OPCODE_AE_S16X2M_XC, + OPCODE_AE_S16X2M_XC1, + OPCODE_AE_S16X2M_I, + OPCODE_AE_S16X2M_IU, + OPCODE_AE_S16X2M_X, + OPCODE_AE_S16X2M_XU, + OPCODE_AE_S32X2F24_XC, + OPCODE_AE_S32X2F24_XC1, + OPCODE_AE_S32X2F24_I, + OPCODE_AE_S32X2F24_IP, + OPCODE_AE_S32X2F24_RIP, + OPCODE_AE_S32X2F24_RIC, + OPCODE_AE_S32X2F24_RIC1, + OPCODE_AE_S32X2F24_X, + OPCODE_AE_S32X2F24_XP, + OPCODE_AE_S32X2_XC, + OPCODE_AE_S32X2_XC1, + OPCODE_AE_S32X2_I, + OPCODE_AE_S32X2_IP, + OPCODE_AE_S32X2_RIC, + OPCODE_AE_S32X2_RIC1, + OPCODE_AE_S32X2_X, + OPCODE_AE_S32X2_XP, + OPCODE_AE_S32X2RNG_I, + OPCODE_AE_S32X2RNG_IP, + OPCODE_AE_S32X2RNG_X, + OPCODE_AE_S32X2RNG_XP, + OPCODE_AE_S16X4_XC, + OPCODE_AE_S16X4_XC1, + OPCODE_AE_S16X4_I, + OPCODE_AE_S16X4_IP, + OPCODE_AE_S16X4_X, + OPCODE_AE_S16X4_XP, + OPCODE_AE_S8X8_XC, + OPCODE_AE_S8X8_XC1, + OPCODE_AE_S8X8_I, + OPCODE_AE_S8X8_IP, + OPCODE_AE_S8X8_X, + OPCODE_AE_S8X8_XP, + OPCODE_AE_S16M_L_XC, + OPCODE_AE_S16M_L_XC1, + OPCODE_AE_S16M_L_I, + OPCODE_AE_S16M_L_IU, + OPCODE_AE_S16M_L_X, + OPCODE_AE_S16M_L_XU, + OPCODE_AE_S32F24_L_XC, + OPCODE_AE_S32F24_L_XC1, + OPCODE_AE_S32F24_L_I, + OPCODE_AE_S32F24_L_IP, + OPCODE_AE_S32F24_L_X, + OPCODE_AE_S32F24_L_XP, + OPCODE_AE_S32_L_XC, + OPCODE_AE_S32_L_XC1, + OPCODE_AE_S32_L_I, + OPCODE_AE_S32_L_IP, + OPCODE_AE_S32_L_X, + OPCODE_AE_S32_L_XP, + OPCODE_AE_S32_H_XC, + OPCODE_AE_S32_H_XC1, + OPCODE_AE_S32_H_I, + OPCODE_AE_S32_H_IP, + OPCODE_AE_S32_H_X, + OPCODE_AE_S32_H_XP, + OPCODE_AE_S16_0_XC, + OPCODE_AE_S16_0_XC1, + OPCODE_AE_S16_0_I, + OPCODE_AE_S16_0_IP, + OPCODE_AE_S16_0_X, + OPCODE_AE_S16_0_XP, + OPCODE_AE_S8_0_XC, + OPCODE_AE_S8_0_XC1, + OPCODE_AE_S8_0_I, + OPCODE_AE_S8_0_IP, + OPCODE_AE_S8_0_X, + OPCODE_AE_S8_0_XP, + OPCODE_AE_S64_XC, + OPCODE_AE_S64_XC1, + OPCODE_AE_S64_I, + OPCODE_AE_S64_IP, + OPCODE_AE_S64_X, + OPCODE_AE_S64_XP, + OPCODE_AE_S32M_XC, + OPCODE_AE_S32M_I, + OPCODE_AE_S32M_IU, + OPCODE_AE_S32M_X, + OPCODE_AE_S32M_XU, + OPCODE_AE_L32X2_XC2, + OPCODE_AE_L16X4_XC2, + OPCODE_AE_L8X8_XC2, + OPCODE_AE_L64_XC2, + OPCODE_AE_S32X2_XC2, + OPCODE_AE_S16X4_XC2, + OPCODE_AE_S8X8_XC2, + OPCODE_AE_S64_XC2, + OPCODE_AE_S16X4RNG_I, + OPCODE_AE_S16X4RNG_IP, + OPCODE_AE_S16X4RNG_X, + OPCODE_AE_S16X4RNG_XP, + OPCODE_AE_L32X2X2_XC, + OPCODE_AE_L32X2X2_XC1, + OPCODE_AE_L32X2X2_I, + OPCODE_AE_L32X2X2_IP, + OPCODE_AE_L32X2X2_X, + OPCODE_AE_L32X2X2_XP, + OPCODE_AE_L16X4X2_XC, + OPCODE_AE_L16X4X2_XC1, + OPCODE_AE_L16X4X2_I, + OPCODE_AE_L16X4X2_IP, + OPCODE_AE_L16X4X2_X, + OPCODE_AE_L16X4X2_XP, + OPCODE_AE_L8X8X2_XC, + OPCODE_AE_L8X8X2_XC1, + OPCODE_AE_L8X8X2_I, + OPCODE_AE_L8X8X2_IP, + OPCODE_AE_L8X8X2_X, + OPCODE_AE_L8X8X2_XP, + OPCODE_AE_L64X2_XC, + OPCODE_AE_L64X2_XC1, + OPCODE_AE_L64X2_I, + OPCODE_AE_L64X2_IP, + OPCODE_AE_L64X2_X, + OPCODE_AE_L64X2_XP, + OPCODE_AE_S32X2X2_XC, + OPCODE_AE_S32X2X2_XC1, + OPCODE_AE_S32X2X2_I, + OPCODE_AE_S32X2X2_IP, + OPCODE_AE_S32X2X2_X, + OPCODE_AE_S32X2X2_XP, + OPCODE_AE_S32X2X2RNG_I, + OPCODE_AE_S32X2X2RNG_IP, + OPCODE_AE_S32X2X2RNG_X, + OPCODE_AE_S32X2X2RNG_XP, + OPCODE_AE_S16X4X2_XC, + OPCODE_AE_S16X4X2_XC1, + OPCODE_AE_S16X4X2_I, + OPCODE_AE_S16X4X2_IP, + OPCODE_AE_S16X4X2_X, + OPCODE_AE_S16X4X2_XP, + OPCODE_AE_S8X8X2_XC, + OPCODE_AE_S8X8X2_XC1, + OPCODE_AE_S8X8X2_I, + OPCODE_AE_S8X8X2_IP, + OPCODE_AE_S8X8X2_X, + OPCODE_AE_S8X8X2_XP, + OPCODE_AE_S8X4UX2_I, + OPCODE_AE_S8X4UX2_IP, + OPCODE_AE_S8X4UX2_X, + OPCODE_AE_S8X4UX2_XP, + OPCODE_AE_S64X2_XC, + OPCODE_AE_S64X2_XC1, + OPCODE_AE_S64X2_I, + OPCODE_AE_S64X2_IP, + OPCODE_AE_S64X2_X, + OPCODE_AE_S64X2_XP, + OPCODE_AE_L32X2X2_XC2, + OPCODE_AE_L16X4X2_XC2, + OPCODE_AE_L8X8X2_XC2, + OPCODE_AE_L64X2_XC2, + OPCODE_AE_S32X2X2_XC2, + OPCODE_AE_S16X4X2_XC2, + OPCODE_AE_S8X8X2_XC2, + OPCODE_AE_S64X2_XC2, + OPCODE_AE_S16X4X2RNG_I, + OPCODE_AE_S16X4X2RNG_IP, + OPCODE_AE_S16X4X2RNG_X, + OPCODE_AE_S16X4X2RNG_XP, + OPCODE_AE_ZALIGN64, + OPCODE_AE_LALIGN64_I, + OPCODE_AE_SALIGN64_I, + OPCODE_AE_MOVALIGN, + OPCODE_AE_LA64_PP, + OPCODE_AE_LA24POS_PC, + OPCODE_AE_LA24NEG_PC, + OPCODE_AE_LA24POS_PC1, + OPCODE_AE_LA24NEG_PC1, + OPCODE_AE_LA24X2POS_PC, + OPCODE_AE_LA24X2NEG_PC, + OPCODE_AE_LA24X2POS_PC1, + OPCODE_AE_LA24X2NEG_PC1, + OPCODE_AE_LA32X2POS_PC, + OPCODE_AE_LA32X2NEG_PC, + OPCODE_AE_LA32X2POS_PC1, + OPCODE_AE_LA32X2NEG_PC1, + OPCODE_AE_LA32X2POS_PC2, + OPCODE_AE_LA16X4POS_PC, + OPCODE_AE_LA16X4NEG_PC, + OPCODE_AE_LA16X4POS_PC1, + OPCODE_AE_LA16X4NEG_PC1, + OPCODE_AE_LA16X4POS_PC2, + OPCODE_AE_LA8X8POS_PC, + OPCODE_AE_LA8X8NEG_PC, + OPCODE_AE_LA8X8POS_PC1, + OPCODE_AE_LA8X8NEG_PC1, + OPCODE_AE_LA8X8POS_PC2, + OPCODE_AE_LA32X2X2POS_PC, + OPCODE_AE_LA32X2X2POS_PC1, + OPCODE_AE_LA32X2X2POS_PC2, + OPCODE_AE_LA16X4X2POS_PC, + OPCODE_AE_LA16X4X2POS_PC1, + OPCODE_AE_LA16X4X2POS_PC2, + OPCODE_AE_LA8X8X2POS_PC, + OPCODE_AE_LA8X8X2POS_PC1, + OPCODE_AE_LA8X8X2POS_PC2, + OPCODE_AE_SA64POS_FP, + OPCODE_AE_SA64NEG_FP, + OPCODE_AE_LA32X2_IC, + OPCODE_AE_LA32X2_IC1, + OPCODE_AE_LA32X2_IC2, + OPCODE_AE_LA32X2_IP, + OPCODE_AE_LA32X2_RIP, + OPCODE_AE_LA32X2_RIC, + OPCODE_AE_LA32X2_RIC1, + OPCODE_AE_LA16X4_IC, + OPCODE_AE_LA16X4_IC1, + OPCODE_AE_LA16X4_IC2, + OPCODE_AE_LA16X4_IP, + OPCODE_AE_LA16X4_RIP, + OPCODE_AE_LA16X4_RIC, + OPCODE_AE_LA16X4_RIC1, + OPCODE_AE_LA8X8_IC, + OPCODE_AE_LA8X8_IC1, + OPCODE_AE_LA8X8_IC2, + OPCODE_AE_LA8X8_IP, + OPCODE_AE_LA8X8_RIP, + OPCODE_AE_LA8X8_RIC, + OPCODE_AE_LA8X8_RIC1, + OPCODE_AE_LA32X2F24_IC, + OPCODE_AE_LA32X2F24_IC1, + OPCODE_AE_LA32X2F24_IP, + OPCODE_AE_LA32X2F24_RIP, + OPCODE_AE_LA32X2F24_RIC, + OPCODE_AE_LA32X2F24_RIC1, + OPCODE_AE_LA24_IC, + OPCODE_AE_LA24_IC1, + OPCODE_AE_LA24_IP, + OPCODE_AE_LA24_RIP, + OPCODE_AE_LA24_RIC, + OPCODE_AE_LA24_RIC1, + OPCODE_AE_LA24X2_IC, + OPCODE_AE_LA24X2_IC1, + OPCODE_AE_LA24X2_IP, + OPCODE_AE_LA24X2_RIP, + OPCODE_AE_LA24X2_RIC, + OPCODE_AE_LA24X2_RIC1, + OPCODE_AE_SA32X2_IC, + OPCODE_AE_SA32X2_IC1, + OPCODE_AE_SA32X2_IC2, + OPCODE_AE_SA32X2_IP, + OPCODE_AE_SA32X2_RIP, + OPCODE_AE_SA32X2_RIC, + OPCODE_AE_SA32X2_RIC1, + OPCODE_AE_SA16X4_IC, + OPCODE_AE_SA16X4_IC1, + OPCODE_AE_SA16X4_IC2, + OPCODE_AE_SA16X4_IP, + OPCODE_AE_SA16X4_RIP, + OPCODE_AE_SA16X4_RIC, + OPCODE_AE_SA16X4_RIC1, + OPCODE_AE_SA8X8_IC, + OPCODE_AE_SA8X8_IC1, + OPCODE_AE_SA8X8_IC2, + OPCODE_AE_SA8X8_IP, + OPCODE_AE_SA8X8_RIP, + OPCODE_AE_SA8X8_RIC, + OPCODE_AE_SA8X8_RIC1, + OPCODE_AE_SA32X2F24_IC, + OPCODE_AE_SA32X2F24_IC1, + OPCODE_AE_SA32X2F24_IP, + OPCODE_AE_SA32X2F24_RIP, + OPCODE_AE_SA32X2F24_RIC, + OPCODE_AE_SA32X2F24_RIC1, + OPCODE_AE_SA24_L_IC, + OPCODE_AE_SA24_L_IC1, + OPCODE_AE_SA24_L_IP, + OPCODE_AE_SA24_L_RIP, + OPCODE_AE_SA24_L_RIC, + OPCODE_AE_SA24_L_RIC1, + OPCODE_AE_SA24X2_IC, + OPCODE_AE_SA24X2_IC1, + OPCODE_AE_SA24X2_IP, + OPCODE_AE_SA24X2_RIP, + OPCODE_AE_SA24X2_RIC, + OPCODE_AE_SA24X2_RIC1, + OPCODE_AE_ADDICIRC, + OPCODE_AE_ADDCIRC_XC2, + OPCODE_AE_ADDCIRC_XC1, + OPCODE_AE_ADDCIRC_XC, + OPCODE_AE_S32RA64S_I, + OPCODE_AE_S32RA64S_IP, + OPCODE_AE_S32RA64S_X, + OPCODE_AE_S32RA64S_XP, + OPCODE_AE_S32RA64S_XC, + OPCODE_AE_S32RA64S_XC1, + OPCODE_AE_S24RA64S_I, + OPCODE_AE_S24RA64S_IP, + OPCODE_AE_S24RA64S_X, + OPCODE_AE_S24RA64S_XP, + OPCODE_AE_S24RA64S_XC, + OPCODE_AE_S24RA64S_XC1, + OPCODE_AE_S32X2RA64S_IP, + OPCODE_AE_S24X2RA64S_IP, + OPCODE_AE_S16X4RA32S_IP, + OPCODE_AE_ADDBRBA32, + OPCODE_AE_S32X2_L_IP, + OPCODE_AE_BITSWAP, + OPCODE_AE_MUL32JS, + OPCODE_AE_ADDANDSUB32S, + OPCODE_AE_ADDANDSUB32JS, + OPCODE_AE_ADDANDSUBRNG32, + OPCODE_AE_ADDANDSUBRNG32_H, + OPCODE_AE_ADDANDSUBRNG32_L, + OPCODE_AE_ADDRNG32, + OPCODE_AE_SUBRNG32, + OPCODE_AE_RNG32X2, + OPCODE_AE_SEL16I, + OPCODE_AE_SEL16I_N, + OPCODE_AE_SHORTSWAP, + OPCODE_AE_MOVAB4, + OPCODE_AE_MOVAB2, + OPCODE_AE_MOVAB, + OPCODE_AE_MOVBA, + OPCODE_AE_MOVBA1X2, + OPCODE_AE_MOVBA4, + OPCODE_AE_MOVBA2, + OPCODE_AE_MOVB2, + OPCODE_AE_MOVB4, + OPCODE_AE_MOVT16X4, + OPCODE_AE_MOVF16X4, + OPCODE_AE_MOVT32X2, + OPCODE_AE_MOVF32X2, + OPCODE_AE_MOVSARA7X2, + OPCODE_AE_MOVSARD7, + OPCODE_AE_MOVASAR, + OPCODE_AE_MOVDA32X2, + OPCODE_AE_MOVDA32, + OPCODE_AE_MOVDA16X2, + OPCODE_AE_MOVDA16, + OPCODE_AE_MOVI, + OPCODE_AE_TRUNCP24A32X2, + OPCODE_AE_SAT16X4, + OPCODE_AE_CVT32X2F16_32, + OPCODE_AE_CVT32X2F16_10, + OPCODE_AE_SEXT32X2D16_32, + OPCODE_AE_SEXT32X2D16_10, + OPCODE_AE_CVTA32F24S_L, + OPCODE_AE_CVTA32F24S_H, + OPCODE_AE_CVTP24A16X2_LL, + OPCODE_AE_CVTP24A16X2_LH, + OPCODE_AE_CVTP24A16X2_HL, + OPCODE_AE_CVTP24A16X2_HH, + OPCODE_AE_TRUNCP24Q48X2, + OPCODE_AE_TRUNCA32X2F64S, + OPCODE_AE_TRUNCI32X2F64S, + OPCODE_AE_TRUNCA32F64S_L, + OPCODE_AE_TRUNCI32F64S_L, + OPCODE_AE_TRUNCP16, + OPCODE_AE_ROUND32X2F64SSYM, + OPCODE_AE_ROUND32X2F64SASYM, + OPCODE_AE_ROUND32X2F48SSYM, + OPCODE_AE_ROUND32X2F48SASYM, + OPCODE_AE_ROUND16X4F32SSYM, + OPCODE_AE_ROUND16X4F32SASYM, + OPCODE_AE_ROUND24X2F48SSYM, + OPCODE_AE_ROUND24X2F48SASYM, + OPCODE_AE_ROUNDSP16Q48X2SYM, + OPCODE_AE_ROUNDSP16Q48X2ASYM, + OPCODE_AE_MINABS32S, + OPCODE_AE_MAXABS32S, + OPCODE_AE_ROUNDSP16F24SYM, + OPCODE_AE_ROUNDSP16F24ASYM, + OPCODE_AE_MOV, + OPCODE_AE_MOVT64, + OPCODE_AE_MOVF64, + OPCODE_AE_CVTQ56A32S, + OPCODE_AE_CVT48A32, + OPCODE_AE_CVT64A32, + OPCODE_AE_CVTQ56P32S_L, + OPCODE_AE_CVTQ56P32S_H, + OPCODE_AE_CVT64F32_H, + OPCODE_AE_CVT48F32_L, + OPCODE_AE_CVT48F32_H, + OPCODE_AE_SAT48S, + OPCODE_AE_SATQ56S, + OPCODE_AE_SAT24S, + OPCODE_AE_TRUNCQ32, + OPCODE_AE_MINABS64S, + OPCODE_AE_MAXABS64S, + OPCODE_AE_ROUNDSQ32F48SYM, + OPCODE_AE_ROUNDSQ32F48ASYM, + OPCODE_AE_TRUNCA32Q48, + OPCODE_AE_MOVAD32_L, + OPCODE_AE_MOVAD32_H, + OPCODE_AE_MOVAD16_3, + OPCODE_AE_MOVAD16_2, + OPCODE_AE_MOVAD16_1, + OPCODE_AE_MOVAD16_0, + OPCODE_AE_SRA64_32, + OPCODE_AE_PKSR32, + OPCODE_AE_PKSR24, + OPCODE_AE_PKSRF32, + OPCODE_AE_PKSR16, + OPCODE_AE_TRUNCA16P24S_L, + OPCODE_AE_TRUNCA16P24S_H, + OPCODE_AE_ADD32, + OPCODE_AE_SUB32, + OPCODE_AE_ADDSUB32, + OPCODE_AE_SUBADD32, + OPCODE_AE_ADD16, + OPCODE_AE_SUB16, + OPCODE_AE_ADD32_HL_LH, + OPCODE_AE_ADDSUB32_HL_LH, + OPCODE_AE_NEG32, + OPCODE_AE_ABS32, + OPCODE_AE_NEG32_L, + OPCODE_AE_ADD24S, + OPCODE_AE_SUB24S, + OPCODE_AE_ADD32S, + OPCODE_AE_SUB32S, + OPCODE_AE_ADDSUB32S, + OPCODE_AE_SUBADD32S, + OPCODE_AE_ADD16S, + OPCODE_AE_SUB16S, + OPCODE_AE_ADD32S_HL_LH, + OPCODE_AE_ADDSUB32S_HL_LH, + OPCODE_AE_NEG24S, + OPCODE_AE_ABS24S, + OPCODE_AE_NEG32S, + OPCODE_AE_ABS32S, + OPCODE_AE_NEG16S, + OPCODE_AE_ABS16S, + OPCODE_AE_ABS16, + OPCODE_AE_MULC16JS_H, + OPCODE_AE_MULC16JS_L, + OPCODE_AE_MULAC16JS_H, + OPCODE_AE_MULAC16JS_L, + OPCODE_AE_LT16, + OPCODE_AE_LE16, + OPCODE_AE_EQ16, + OPCODE_AE_LT32, + OPCODE_AE_LE32, + OPCODE_AE_EQ32, + OPCODE_AE_MIN32, + OPCODE_AE_MAX32, + OPCODE_AE_MINMAX32, + OPCODE_AE_MINMAX16, + OPCODE_AE_MIN16, + OPCODE_AE_MAX16, + OPCODE_AE_ADD64, + OPCODE_AE_SUB64, + OPCODE_AE_NEG64, + OPCODE_AE_ABS64, + OPCODE_AE_ADDSQ56S, + OPCODE_AE_SUBSQ56S, + OPCODE_AE_ADD64S, + OPCODE_AE_SUB64S, + OPCODE_AE_NEGSQ56S, + OPCODE_AE_ABSSQ56S, + OPCODE_AE_NEG64S, + OPCODE_AE_ABS64S, + OPCODE_AE_AND, + OPCODE_AE_NAND, + OPCODE_AE_OR, + OPCODE_AE_XOR, + OPCODE_AE_SLAI24, + OPCODE_AE_SRLI24, + OPCODE_AE_SRAI24, + OPCODE_AE_SLAS24, + OPCODE_AE_SRLS24, + OPCODE_AE_SRAS24, + OPCODE_AE_SRAI16, + OPCODE_AE_SRAI16R, + OPCODE_AE_SLAI32, + OPCODE_AE_SRLI32, + OPCODE_AE_SRAI32, + OPCODE_AE_SRAI32R, + OPCODE_AE_SLAS32, + OPCODE_AE_SRLS32, + OPCODE_AE_SRAS32, + OPCODE_AE_SLAA32, + OPCODE_AE_SRLA32, + OPCODE_AE_SRAA32, + OPCODE_AE_SLAI16S, + OPCODE_AE_SLAA16S, + OPCODE_AE_SRAA16S, + OPCODE_AE_SRAA16RS, + OPCODE_AE_SLAI24S, + OPCODE_AE_SLAS24S, + OPCODE_AE_SLAI32S, + OPCODE_AE_SLAS32S, + OPCODE_AE_SLAA32S, + OPCODE_AE_SRAA32S, + OPCODE_AE_SRAA32RS, + OPCODE_AE_SLASQ56, + OPCODE_AE_SRLSQ56, + OPCODE_AE_SRASQ56, + OPCODE_AE_SLAAQ56, + OPCODE_AE_SRLAQ56, + OPCODE_AE_SRAAQ56, + OPCODE_AE_SLAI64, + OPCODE_AE_SRLI64, + OPCODE_AE_SRAI64, + OPCODE_AE_SLAS64, + OPCODE_AE_SRLS64, + OPCODE_AE_SRAS64, + OPCODE_AE_SLAA64, + OPCODE_AE_SRLA64, + OPCODE_AE_SRAA64, + OPCODE_AE_SLAISQ56S, + OPCODE_AE_SLASSQ56S, + OPCODE_AE_SLAASQ56S, + OPCODE_AE_SLAI64S, + OPCODE_AE_SLAS64S, + OPCODE_AE_SLAA64S, + OPCODE_AE_LT64, + OPCODE_AE_LE64, + OPCODE_AE_EQ64, + OPCODE_AE_MAX64, + OPCODE_AE_MIN64, + OPCODE_AE_NSA64, + OPCODE_AE_NSAZ16_0, + OPCODE_AE_NSAZ32_L, + OPCODE_AE_MULS32F48P16S_LL, + OPCODE_AE_MULF32S_LL, + OPCODE_AE_MUL32_LL, + OPCODE_AE_MULF32R_LL, + OPCODE_AE_MULF32RA_LL, + OPCODE_AE_MULS32F48P16S_LH, + OPCODE_AE_MULF32S_LH, + OPCODE_AE_MUL32_LH, + OPCODE_AE_MULF32R_LH, + OPCODE_AE_MULF32RA_LH, + OPCODE_AE_MULS32F48P16S_HH, + OPCODE_AE_MULF32S_HH, + OPCODE_AE_MUL32_HH, + OPCODE_AE_MULF32R_HH, + OPCODE_AE_MULF32RA_HH, + OPCODE_AE_MULAS32F48P16S_LL, + OPCODE_AE_MULAF32S_LL, + OPCODE_AE_MULA32_LL, + OPCODE_AE_MULAF32R_LL, + OPCODE_AE_MULAF32RA_LL, + OPCODE_AE_MULAS32F48P16S_LH, + OPCODE_AE_MULAF32S_LH, + OPCODE_AE_MULA32_LH, + OPCODE_AE_MULAF32R_LH, + OPCODE_AE_MULAF32RA_LH, + OPCODE_AE_MULAS32F48P16S_HH, + OPCODE_AE_MULAF32S_HH, + OPCODE_AE_MULA32_HH, + OPCODE_AE_MULAF32R_HH, + OPCODE_AE_MULAF32RA_HH, + OPCODE_AE_MULSS32F48P16S_LL, + OPCODE_AE_MULSF32S_LL, + OPCODE_AE_MULS32_LL, + OPCODE_AE_MULSF32R_LL, + OPCODE_AE_MULSF32RA_LL, + OPCODE_AE_MULSS32F48P16S_LH, + OPCODE_AE_MULSF32S_LH, + OPCODE_AE_MULS32_LH, + OPCODE_AE_MULSF32R_LH, + OPCODE_AE_MULSF32RA_LH, + OPCODE_AE_MULSS32F48P16S_HH, + OPCODE_AE_MULSF32S_HH, + OPCODE_AE_MULS32_HH, + OPCODE_AE_MULSF32R_HH, + OPCODE_AE_MULSF32RA_HH, + OPCODE_AE_MUL32U_LL, + OPCODE_AE_MULA32U_LL, + OPCODE_AE_MULS32U_LL, + OPCODE_AE_MULF16SS_33, + OPCODE_AE_MULF16SS_22, + OPCODE_AE_MULF16SS_32, + OPCODE_AE_MULF16SS_21, + OPCODE_AE_MULF16SS_31, + OPCODE_AE_MULF16SS_30, + OPCODE_AE_MULF16SS_10, + OPCODE_AE_MULF16SS_20, + OPCODE_AE_MULF16SS_11, + OPCODE_AE_MULF16SS_00, + OPCODE_AE_MULSF16SS_33, + OPCODE_AE_MULSF16SS_22, + OPCODE_AE_MULSF16SS_32, + OPCODE_AE_MULSF16SS_21, + OPCODE_AE_MULSF16SS_31, + OPCODE_AE_MULSF16SS_30, + OPCODE_AE_MULSF16SS_10, + OPCODE_AE_MULSF16SS_20, + OPCODE_AE_MULSF16SS_11, + OPCODE_AE_MULSF16SS_00, + OPCODE_AE_MULAF16SS_33, + OPCODE_AE_MULAF16SS_22, + OPCODE_AE_MULAF16SS_32, + OPCODE_AE_MULAF16SS_21, + OPCODE_AE_MULAF16SS_31, + OPCODE_AE_MULAF16SS_30, + OPCODE_AE_MULAF16SS_10, + OPCODE_AE_MULAF16SS_20, + OPCODE_AE_MULAF16SS_11, + OPCODE_AE_MULAF16SS_00, + OPCODE_AE_MUL16S_00, + OPCODE_AE_MULA16S_00, + OPCODE_AE_MULS16S_00, + OPCODE_AE_MULAAFD16SS_33_22, + OPCODE_AE_MULAAFD16SS_13_02, + OPCODE_AE_MULAAFD16SS_11_00, + OPCODE_AE_MULSSFD16SS_33_22, + OPCODE_AE_MULSSFD16SS_13_02, + OPCODE_AE_MULSSFD16SS_11_00, + OPCODE_AE_MULZAAFD16SS_33_22, + OPCODE_AE_MULZAAFD16SS_13_02, + OPCODE_AE_MULZAAFD16SS_11_00, + OPCODE_AE_MULZSSFD16SS_33_22, + OPCODE_AE_MULZSSFD16SS_13_02, + OPCODE_AE_MULZSSFD16SS_11_00, + OPCODE_AE_MULF48Q32SP16S_L, + OPCODE_AE_MULF48Q32SP16U_L, + OPCODE_AE_MULQ32SP16S_L, + OPCODE_AE_MULQ32SP16U_L, + OPCODE_AE_MULAF48Q32SP16S_L, + OPCODE_AE_MULAF48Q32SP16U_L, + OPCODE_AE_MULAQ32SP16S_L, + OPCODE_AE_MULAQ32SP16U_L, + OPCODE_AE_MULSF48Q32SP16S_L, + OPCODE_AE_MULSF48Q32SP16U_L, + OPCODE_AE_MULSQ32SP16S_L, + OPCODE_AE_MULSQ32SP16U_L, + OPCODE_AE_MULFP24X2RA, + OPCODE_AE_MULFP24X2R, + OPCODE_AE_MULAFP24X2RA, + OPCODE_AE_MULAFP24X2R, + OPCODE_AE_MULSFP24X2RA, + OPCODE_AE_MULSFP24X2R, + OPCODE_AE_MULZAAFD32S_HH_LL, + OPCODE_AE_MULZAAFD32RA_HH_LL, + OPCODE_AE_MULZAAD32_HH_LL, + OPCODE_AE_MULZAAFD32S_HL_LH, + OPCODE_AE_MULZAAFD32RA_HL_LH, + OPCODE_AE_MULZAAD32_HL_LH, + OPCODE_AE_MULZASFD32S_HH_LL, + OPCODE_AE_MULZASFD32RA_HH_LL, + OPCODE_AE_MULZASD32_HH_LL, + OPCODE_AE_MULZASFD32S_HL_LH, + OPCODE_AE_MULZASFD32RA_HL_LH, + OPCODE_AE_MULZASD32_HL_LH, + OPCODE_AE_MULZSAFD32S_HH_LL, + OPCODE_AE_MULZSAFD32RA_HH_LL, + OPCODE_AE_MULZSAD32_HH_LL, + OPCODE_AE_MULZSSFD32S_HH_LL, + OPCODE_AE_MULZSSFD32RA_HH_LL, + OPCODE_AE_MULZSSD32_HH_LL, + OPCODE_AE_MULZSSFD32S_HL_LH, + OPCODE_AE_MULZSSFD32RA_HL_LH, + OPCODE_AE_MULZSSD32_HL_LH, + OPCODE_AE_MULAAFD32S_HH_LL, + OPCODE_AE_MULAAFD32RA_HH_LL, + OPCODE_AE_MULAAD32_HH_LL, + OPCODE_AE_MULAAFD32S_HL_LH, + OPCODE_AE_MULAAFD32RA_HL_LH, + OPCODE_AE_MULAAD32_HL_LH, + OPCODE_AE_MULASFD32S_HH_LL, + OPCODE_AE_MULASFD32RA_HH_LL, + OPCODE_AE_MULASD32_HH_LL, + OPCODE_AE_MULASFD32S_HL_LH, + OPCODE_AE_MULASFD32RA_HL_LH, + OPCODE_AE_MULASD32_HL_LH, + OPCODE_AE_MULSAFD32S_HH_LL, + OPCODE_AE_MULSAFD32RA_HH_LL, + OPCODE_AE_MULSAD32_HH_LL, + OPCODE_AE_MULSSFD32S_HH_LL, + OPCODE_AE_MULSSFD32RA_HH_LL, + OPCODE_AE_MULSSD32_HH_LL, + OPCODE_AE_MULSSFD32S_HL_LH, + OPCODE_AE_MULSSFD32RA_HL_LH, + OPCODE_AE_MULSSD32_HL_LH, + OPCODE_AE_MULF32X16_L0, + OPCODE_AE_MUL32X16_L0, + OPCODE_AE_MULF32X16_L1, + OPCODE_AE_MUL32X16_L1, + OPCODE_AE_MULF32X16_L2, + OPCODE_AE_MUL32X16_L2, + OPCODE_AE_MULF32X16_L3, + OPCODE_AE_MUL32X16_L3, + OPCODE_AE_MULF32X16_H0, + OPCODE_AE_MUL32X16_H0, + OPCODE_AE_MULF32X16_H1, + OPCODE_AE_MUL32X16_H1, + OPCODE_AE_MULF32X16_H2, + OPCODE_AE_MUL32X16_H2, + OPCODE_AE_MULF32X16_H3, + OPCODE_AE_MUL32X16_H3, + OPCODE_AE_MULAF32X16_L0, + OPCODE_AE_MULA32X16_L0, + OPCODE_AE_MULAF32X16_L1, + OPCODE_AE_MULA32X16_L1, + OPCODE_AE_MULAF32X16_L2, + OPCODE_AE_MULA32X16_L2, + OPCODE_AE_MULAF32X16_L3, + OPCODE_AE_MULA32X16_L3, + OPCODE_AE_MULAF32X16_H0, + OPCODE_AE_MULA32X16_H0, + OPCODE_AE_MULAF32X16_H1, + OPCODE_AE_MULA32X16_H1, + OPCODE_AE_MULAF32X16_H2, + OPCODE_AE_MULA32X16_H2, + OPCODE_AE_MULAF32X16_H3, + OPCODE_AE_MULA32X16_H3, + OPCODE_AE_MULSF32X16_L0, + OPCODE_AE_MULS32X16_L0, + OPCODE_AE_MULSF32X16_L1, + OPCODE_AE_MULS32X16_L1, + OPCODE_AE_MULSF32X16_L2, + OPCODE_AE_MULS32X16_L2, + OPCODE_AE_MULSF32X16_L3, + OPCODE_AE_MULS32X16_L3, + OPCODE_AE_MULSF32X16_H0, + OPCODE_AE_MULS32X16_H0, + OPCODE_AE_MULSF32X16_H1, + OPCODE_AE_MULS32X16_H1, + OPCODE_AE_MULSF32X16_H2, + OPCODE_AE_MULS32X16_H2, + OPCODE_AE_MULSF32X16_H3, + OPCODE_AE_MULS32X16_H3, + OPCODE_AE_MULAAFD32X16_H3_L2, + OPCODE_AE_MULAAD32X16_H3_L2, + OPCODE_AE_MULAAFD32X16_H1_L0, + OPCODE_AE_MULAAD32X16_H1_L0, + OPCODE_AE_MULASFD32X16_H3_L2, + OPCODE_AE_MULASD32X16_H3_L2, + OPCODE_AE_MULASFD32X16_H1_L0, + OPCODE_AE_MULASD32X16_H1_L0, + OPCODE_AE_MULSAFD32X16_H3_L2, + OPCODE_AE_MULSAD32X16_H3_L2, + OPCODE_AE_MULSAFD32X16_H1_L0, + OPCODE_AE_MULSAD32X16_H1_L0, + OPCODE_AE_MULSSFD32X16_H3_L2, + OPCODE_AE_MULSSD32X16_H3_L2, + OPCODE_AE_MULSSFD32X16_H1_L0, + OPCODE_AE_MULSSD32X16_H1_L0, + OPCODE_AE_MULZAAFD32X16_H3_L2, + OPCODE_AE_MULZAAD32X16_H3_L2, + OPCODE_AE_MULZAAFD32X16_H1_L0, + OPCODE_AE_MULZAAD32X16_H1_L0, + OPCODE_AE_MULZASFD32X16_H3_L2, + OPCODE_AE_MULZASD32X16_H3_L2, + OPCODE_AE_MULZASFD32X16_H1_L0, + OPCODE_AE_MULZASD32X16_H1_L0, + OPCODE_AE_MULZSAFD32X16_H3_L2, + OPCODE_AE_MULZSAD32X16_H3_L2, + OPCODE_AE_MULZSAFD32X16_H1_L0, + OPCODE_AE_MULZSAD32X16_H1_L0, + OPCODE_AE_MULZSSFD32X16_H3_L2, + OPCODE_AE_MULZSSD32X16_H3_L2, + OPCODE_AE_MULZSSFD32X16_H1_L0, + OPCODE_AE_MULZSSD32X16_H1_L0, + OPCODE_AE_MULZAAFD32X16_H2_L3, + OPCODE_AE_MULZAAFD32X16_H0_L1, + OPCODE_AE_MULAAFD32X16_H2_L3, + OPCODE_AE_MULAAFD32X16_H0_L1, + OPCODE_AE_MULZAAD32X16_H2_L3, + OPCODE_AE_MULZAAD32X16_H0_L1, + OPCODE_AE_MULAAD32X16_H2_L3, + OPCODE_AE_MULAAD32X16_H0_L1, + OPCODE_AE_MULP32X16X2_H, + OPCODE_AE_MULFP32X16X2RS_H, + OPCODE_AE_MULFP32X16X2RAS_H, + OPCODE_AE_MULFP32X16X2S_H, + OPCODE_AE_MULP32X16X2_L, + OPCODE_AE_MULFP32X16X2RS_L, + OPCODE_AE_MULFP32X16X2RAS_L, + OPCODE_AE_MULFP32X16X2S_L, + OPCODE_AE_MULAP32X16X2_H, + OPCODE_AE_MULAFP32X16X2RS_H, + OPCODE_AE_MULAFP32X16X2RAS_H, + OPCODE_AE_MULAFP32X16X2S_H, + OPCODE_AE_MULAP32X16X2_L, + OPCODE_AE_MULAFP32X16X2RS_L, + OPCODE_AE_MULAFP32X16X2RAS_L, + OPCODE_AE_MULAFP32X16X2S_L, + OPCODE_AE_MULSP32X16X2_H, + OPCODE_AE_MULSFP32X16X2RS_H, + OPCODE_AE_MULSFP32X16X2RAS_H, + OPCODE_AE_MULSFP32X16X2S_H, + OPCODE_AE_MULSP32X16X2_L, + OPCODE_AE_MULSFP32X16X2RS_L, + OPCODE_AE_MULSFP32X16X2RAS_L, + OPCODE_AE_MULSFP32X16X2S_L, + OPCODE_AE_MULP32X2, + OPCODE_AE_MULFP32X2RS, + OPCODE_AE_MULFP32X2RAS, + OPCODE_AE_MULFP32X2TS, + OPCODE_AE_MULP32X2T, + OPCODE_AE_MULAP32X2, + OPCODE_AE_MULAFP32X2RS, + OPCODE_AE_MULAFP32X2RAS, + OPCODE_AE_MULAFP32X2TS, + OPCODE_AE_MULAP32X2T, + OPCODE_AE_MULSP32X2, + OPCODE_AE_MULSFP32X2RS, + OPCODE_AE_MULSFP32X2RAS, + OPCODE_AE_MULSFP32X2TS, + OPCODE_AE_MULSP32X2T, + OPCODE_AE_MULFP16X4S, + OPCODE_AE_MULFP16X4RAS, + OPCODE_AE_MULC32, + OPCODE_AE_MULFC24RA, + OPCODE_AE_MULFC32RAS, + OPCODE_AE_MULC32X16_L, + OPCODE_AE_MULFC32X16RAS_L, + OPCODE_AE_MULC32X16_H, + OPCODE_AE_MULFC32X16RAS_H, + OPCODE_AE_MULAC32, + OPCODE_AE_MULAFC24RA, + OPCODE_AE_MULAFC32RAS, + OPCODE_AE_MULAC32X16_L, + OPCODE_AE_MULAFC32X16RAS_L, + OPCODE_AE_MULAC32X16_H, + OPCODE_AE_MULAFC32X16RAS_H, + OPCODE_AE_MULF16X4SS, + OPCODE_AE_MULAF16X4SS, + OPCODE_AE_MULSF16X4SS, + OPCODE_AE_MUL16X4S, + OPCODE_AE_MULA16X4S, + OPCODE_AE_MULS16X4S, + OPCODE_AE_MUL16X4, + OPCODE_AE_MULA16X4, + OPCODE_AE_MULS16X4, + OPCODE_AE_MULFD32X2S_FIR_H, + OPCODE_AE_MULFD32X2RA_FIR_H, + OPCODE_AE_MULFD32X2S_FIR_L, + OPCODE_AE_MULFD32X2RA_FIR_L, + OPCODE_AE_MULFD32X16X2_FIR_HH, + OPCODE_AE_MULFD32X16X2_FIR_HL, + OPCODE_AE_MULFD32X16X2_FIR_LH, + OPCODE_AE_MULFD32X16X2_FIR_LL, + OPCODE_AE_MULAFD32X2S_FIR_H, + OPCODE_AE_MULAFD32X2RA_FIR_H, + OPCODE_AE_MULAFD32X2S_FIR_L, + OPCODE_AE_MULAFD32X2RA_FIR_L, + OPCODE_AE_MULAFD32X16X2_FIR_HH, + OPCODE_AE_MULAFD32X16X2_FIR_HL, + OPCODE_AE_MULAFD32X16X2_FIR_LH, + OPCODE_AE_MULAFD32X16X2_FIR_LL, + OPCODE_AE_MULC16S_H, + OPCODE_AE_MULC16S_L, + OPCODE_AE_MULAC16S_H, + OPCODE_AE_MULAC16S_L, + OPCODE_AE_MULFC16RAS, + OPCODE_AE_MULAFC16RAS, + OPCODE_AE_MUL16JS, + OPCODE_AE_ADDANDSUBRNG16RAS_S1, + OPCODE_AE_ADDANDSUBRNG16RAS_S2, + OPCODE_AE_CONJ16S, + OPCODE_AE_MULFQ16X2_FIR_3, + OPCODE_AE_MULFQ16X2_FIR_2, + OPCODE_AE_MULFQ16X2_FIR_1, + OPCODE_AE_MULFQ16X2_FIR_0, + OPCODE_AE_MULAFQ16X2_FIR_3, + OPCODE_AE_MULAFQ16X2_FIR_2, + OPCODE_AE_MULAFQ16X2_FIR_1, + OPCODE_AE_MULAFQ16X2_FIR_0, + OPCODE_AE_MULZAAAAFQ32X16, + OPCODE_AE_MULAAAAFQ32X16, + OPCODE_AE_MULZAAAAQ32X16, + OPCODE_AE_MULAAAAQ32X16, + OPCODE_AE_MUL16_00, + OPCODE_AE_MULA16_00, + OPCODE_AE_MULZAAAAQ16, + OPCODE_AE_MULAAAAQ16, + OPCODE_AE_DIV64D32_H, + OPCODE_AE_DIV64D32_L, + OPCODE_AE_SHA32, + OPCODE_AE_VLDL32T, + OPCODE_AE_VLDL16T, + OPCODE_AE_VLDL16C, + OPCODE_AE_VLDL16C_IP, + OPCODE_AE_VLDL16C_IC, + OPCODE_AE_VLDL16C_IC1, + OPCODE_AE_VLDSHT, + OPCODE_AE_LB, + OPCODE_AE_LBI, + OPCODE_AE_LBK, + OPCODE_AE_LBKI, + OPCODE_AE_LBS, + OPCODE_AE_LBSI, + OPCODE_AE_DB, + OPCODE_AE_DBI, + OPCODE_AE_DB_IC, + OPCODE_AE_DBI_IC, + OPCODE_AE_DB_IC1, + OPCODE_AE_DBI_IC1, + OPCODE_AE_DB_IP, + OPCODE_AE_DBI_IP, + OPCODE_AE_ARDECNORM16, + OPCODE_AE_LBKI_DBI_IC, + OPCODE_AE_LBKI_DBI_IP, + OPCODE_AE_LBKI_DBI, + OPCODE_AE_LBI_DBI_IC, + OPCODE_AE_LBI_DBI_IP, + OPCODE_AE_LBI_DBI, + OPCODE_AE_LBK_DB_IC, + OPCODE_AE_LBK_DB_IP, + OPCODE_AE_LBK_DB, + OPCODE_AE_LB_DB_IC, + OPCODE_AE_LB_DB_IP, + OPCODE_AE_LB_DB, + OPCODE_AE_VLEL32T, + OPCODE_AE_VLEL16T, + OPCODE_AE_SB, + OPCODE_AE_SBI, + OPCODE_AE_VLES16C, + OPCODE_AE_SBF, + OPCODE_AE_SB_IC, + OPCODE_AE_SBI_IC, + OPCODE_AE_VLES16C_IC, + OPCODE_AE_SBF_IC, + OPCODE_AE_SB_IC1, + OPCODE_AE_SBI_IC1, + OPCODE_AE_VLES16C_IC1, + OPCODE_AE_SBF_IC1, + OPCODE_AE_SB_IP, + OPCODE_AE_SBI_IP, + OPCODE_AE_VLES16C_IP, + OPCODE_AE_SBF_IP, + OPCODE_AE_SEXT32, + OPCODE_AE_MOVAE, + OPCODE_AE_MOVEA, + OPCODE_AE_MOVEEP, + OPCODE_AE_SEXT72, + OPCODE_AE_ADD72, + OPCODE_AE_SUB72, + OPCODE_AE_ADD72X64, + OPCODE_AE_SUB72X64, + OPCODE_AE_MUL32EP_HH, + OPCODE_AE_MULA32EP_HH, + OPCODE_AE_MULS32EP_HH, + OPCODE_AE_MULZAAD32EP_HH_LL, + OPCODE_AE_MULZSSD32EP_HH_LL, + OPCODE_AE_MULAAD32EP_HH_LL, + OPCODE_AE_MULSSD32EP_HH_LL, + OPCODE_AE_MULAAD32USEP_HL_LH, + OPCODE_AE_MULZAAD32USEP_HL_LH, + OPCODE_AE_MUL32USEP_LH, + OPCODE_AE_MULA32USEP_LH, + OPCODE_AE_MUL32USEP_LL, + OPCODE_AE_MULA32USEP_LL, + OPCODE_AE_SRAI72, + OPCODE_AE_SLAI72, + OPCODE_AE_SAT64S, + OPCODE_AE_L16SI_N, + OPCODE_AE_L16UI_N, + OPCODE_AE_S16I_N, + OPCODE_AE_LALIGN128_I, + OPCODE_AE_SALIGN128_I, + OPCODE_AE_LA128_PP, + OPCODE_AE_SA128POS_FP, + OPCODE_AE_LA8X4S_IP, + OPCODE_AE_LA8X4U_IP, + OPCODE_AE_LA8X8X2_IP, + OPCODE_AE_LA16X4X2_IP, + OPCODE_AE_LA32X2X2_IP, + OPCODE_AE_LA8X8X2_IC, + OPCODE_AE_LA16X4X2_IC, + OPCODE_AE_LA32X2X2_IC, + OPCODE_AE_LA8X8X2_IC1, + OPCODE_AE_LA16X4X2_IC1, + OPCODE_AE_LA32X2X2_IC1, + OPCODE_AE_LA8X8X2_IC2, + OPCODE_AE_LA16X4X2_IC2, + OPCODE_AE_LA32X2X2_IC2, + OPCODE_AE_SA8X8X2_IP, + OPCODE_AE_SA16X4X2_IP, + OPCODE_AE_SA32X2X2_IP, + OPCODE_AE_SA8X8X2_IC, + OPCODE_AE_SA16X4X2_IC, + OPCODE_AE_SA32X2X2_IC, + OPCODE_AE_SA8X8X2_IC1, + OPCODE_AE_SA16X4X2_IC1, + OPCODE_AE_SA32X2X2_IC1, + OPCODE_AE_SA8X8X2_IC2, + OPCODE_AE_SA16X4X2_IC2, + OPCODE_AE_SA32X2X2_IC2, + OPCODE_AE_ABS8, + OPCODE_AE_ABS8S, + OPCODE_AE_NEG8S, + OPCODE_AE_ADD8, + OPCODE_AE_SUB8, + OPCODE_AE_MAX8, + OPCODE_AE_MIN8, + OPCODE_AE_ADD8S, + OPCODE_AE_SUB8S, + OPCODE_AE_LE8, + OPCODE_AE_LT8, + OPCODE_AE_EQ8, + OPCODE_AE_SATU16X4, + OPCODE_AE_SAT32X2, + OPCODE_AE_SATU32X2, + OPCODE_AE_SAT8X8X16, + OPCODE_AE_SATU8X8X16, + OPCODE_AE_SAT8X4X32_L, + OPCODE_AE_SATU8X4X32_L, + OPCODE_AE_ROUND8X8F16SSYM, + OPCODE_AE_ROUND8X8F16SASYM, + OPCODE_AE_ROUND8X4F32SSYM_L, + OPCODE_AE_ROUND8X4F32SASYM_L, + OPCODE_AE_MOVDA8, + OPCODE_AE_MOVAD8, + OPCODE_AE_MOVDX2, + OPCODE_AE_ADDANDSUB32J, + OPCODE_AE_ADDW8, + OPCODE_AE_ADDW16, + OPCODE_AE_ADDW32, + OPCODE_AE_SUBW8, + OPCODE_AE_SUBW16, + OPCODE_AE_SUBW32, + OPCODE_AE_ACCW8, + OPCODE_AE_ACCW16, + OPCODE_AE_ACCW32, + OPCODE_AE_ADDW8U, + OPCODE_AE_SUBW8U, + OPCODE_AE_ACCW8U, + OPCODE_AE_MULFP32X2S_HH_LL, + OPCODE_AE_MULAFP32X2S_HH_LL, + OPCODE_AE_MULSFP32X2S_HH_LL, + OPCODE_AE_MULFP32X2S_HL_LH, + OPCODE_AE_MULAFP32X2S_HL_LH, + OPCODE_AE_MULSFP32X2S_HL_LH, + OPCODE_AE_MULZAAF2D32S_HH_LL, + OPCODE_AE_MULZASF2D32S_HH_LL, + OPCODE_AE_MULZSAF2D32S_HH_LL, + OPCODE_AE_MULZSSF2D32S_HH_LL, + OPCODE_AE_MULAAF2D32S_HH_LL, + OPCODE_AE_MULASF2D32S_HH_LL, + OPCODE_AE_MULSAF2D32S_HH_LL, + OPCODE_AE_MULSSF2D32S_HH_LL, + OPCODE_AE_MULZAAF2D32S_HL_LH, + OPCODE_AE_MULZASF2D32S_HL_LH, + OPCODE_AE_MULZSAF2D32S_HL_LH, + OPCODE_AE_MULZSSF2D32S_HL_LH, + OPCODE_AE_MULAAF2D32S_HL_LH, + OPCODE_AE_MULASF2D32S_HL_LH, + OPCODE_AE_MULSAF2D32S_HL_LH, + OPCODE_AE_MULSSF2D32S_HL_LH, + OPCODE_AE_MUL32S_HH, + OPCODE_AE_MULA32S_HH, + OPCODE_AE_MULS32S_HH, + OPCODE_AE_MUL32S_LL, + OPCODE_AE_MULA32S_LL, + OPCODE_AE_MULS32S_LL, + OPCODE_AE_MUL32S_HL, + OPCODE_AE_MULA32S_HL, + OPCODE_AE_MULS32S_HL, + OPCODE_AE_MUL32S_LH, + OPCODE_AE_MULA32S_LH, + OPCODE_AE_MULS32S_LH, + OPCODE_AE_MUL32X2S_HH_LL, + OPCODE_AE_MULA32X2S_HH_LL, + OPCODE_AE_MULS32X2S_HH_LL, + OPCODE_AE_MUL32X2S_HL_LH, + OPCODE_AE_MULA32X2S_HL_LH, + OPCODE_AE_MULS32X2S_HL_LH, + OPCODE_AE_MULZAAD32S_HH_LL, + OPCODE_AE_MULZASD32S_HH_LL, + OPCODE_AE_MULZSAD32S_HH_LL, + OPCODE_AE_MULZSSD32S_HH_LL, + OPCODE_AE_MULAAD32S_HH_LL, + OPCODE_AE_MULASD32S_HH_LL, + OPCODE_AE_MULSAD32S_HH_LL, + OPCODE_AE_MULSSD32S_HH_LL, + OPCODE_AE_MULZAAD32S_HL_LH, + OPCODE_AE_MULZASD32S_HL_LH, + OPCODE_AE_MULZSAD32S_HL_LH, + OPCODE_AE_MULZSSD32S_HL_LH, + OPCODE_AE_MULAAD32S_HL_LH, + OPCODE_AE_MULASD32S_HL_LH, + OPCODE_AE_MULSAD32S_HL_LH, + OPCODE_AE_MULSSD32S_HL_LH, + OPCODE_AE_MULF32X2RA_HH_LL, + OPCODE_AE_MULAF32X2RA_HH_LL, + OPCODE_AE_MULSF32X2RA_HH_LL, + OPCODE_AE_MULF32X2RA_HL_LH, + OPCODE_AE_MULAF32X2RA_HL_LH, + OPCODE_AE_MULSF32X2RA_HL_LH, + OPCODE_AE_MULZAAF2D32RA_HH_LL, + OPCODE_AE_MULZASF2D32RA_HH_LL, + OPCODE_AE_MULZSAF2D32RA_HH_LL, + OPCODE_AE_MULZSSF2D32RA_HH_LL, + OPCODE_AE_MULAAF2D32RA_HH_LL, + OPCODE_AE_MULASF2D32RA_HH_LL, + OPCODE_AE_MULSAF2D32RA_HH_LL, + OPCODE_AE_MULSSF2D32RA_HH_LL, + OPCODE_AE_MULZAAF2D32RA_HL_LH, + OPCODE_AE_MULZASF2D32RA_HL_LH, + OPCODE_AE_MULZSAF2D32RA_HL_LH, + OPCODE_AE_MULZSSF2D32RA_HL_LH, + OPCODE_AE_MULAAF2D32RA_HL_LH, + OPCODE_AE_MULASF2D32RA_HL_LH, + OPCODE_AE_MULSAF2D32RA_HL_LH, + OPCODE_AE_MULSSF2D32RA_HL_LH, + OPCODE_AE_MULF32X2R_HH_LL, + OPCODE_AE_MULAF32X2R_HH_LL, + OPCODE_AE_MULSF32X2R_HH_LL, + OPCODE_AE_MULF32X2R_HL_LH, + OPCODE_AE_MULAF32X2R_HL_LH, + OPCODE_AE_MULSF32X2R_HL_LH, + OPCODE_AE_MULFC32W, + OPCODE_AE_MULAFC32W, + OPCODE_AE_MULFCJ32W, + OPCODE_AE_MULAFCJ32W, + OPCODE_AE_MULFCJ32RAS, + OPCODE_AE_MULAFCJ32RAS, + OPCODE_AE_MULF2P32X4RS, + OPCODE_AE_MULAF2P32X4RS, + OPCODE_AE_MULSF2P32X4RS, + OPCODE_AE_MULF2P32X4RAS, + OPCODE_AE_MULAF2P32X4RAS, + OPCODE_AE_MULSF2P32X4RAS, + OPCODE_AE_MULP32X2S, + OPCODE_AE_MUL2P32X4S, + OPCODE_AE_MUL2P32X4, + OPCODE_AE_MULA2P32X4, + OPCODE_AE_MULS2P32X4, + OPCODE_AE_MUL2P32X4T, + OPCODE_AE_MULA2P32X4T, + OPCODE_AE_MULS2P32X4T, + OPCODE_AE_MULZAA32X2_HH_LL, + OPCODE_AE_MULZSS32X2_HH_LL, + OPCODE_AE_MULAA32X2_HH_LL, + OPCODE_AE_MULSS32X2_HH_LL, + OPCODE_AE_MULCJ32, + OPCODE_AE_MULACJ32, + OPCODE_AE_MULADDF32RS, + OPCODE_AE_MULADDF32RAS, + OPCODE_AE_MULSUBF32RS, + OPCODE_AE_MULSUBF32RAS, + OPCODE_AE_MULFC32RA, + OPCODE_AE_MULAFC32RA, + OPCODE_AE_MULCJ32W, + OPCODE_AE_MULACJ32W, + OPCODE_AE_MULC32W, + OPCODE_AE_MULAC32W, + OPCODE_AE_MULF2D32X2WS, + OPCODE_AE_MULZAAAA2Q16, + OPCODE_AE_MULAAAA2Q16, + OPCODE_AE_MULP16S_H, + OPCODE_AE_MULAP16S_H, + OPCODE_AE_MULSP16S_H, + OPCODE_AE_MULP16S_L, + OPCODE_AE_MULAP16S_L, + OPCODE_AE_MULSP16S_L, + OPCODE_AE_MULC16W_H, + OPCODE_AE_MULAC16W_H, + OPCODE_AE_MULC16W_L, + OPCODE_AE_MULAC16W_L, + OPCODE_AE_MUL2C16S, + OPCODE_AE_MULA2C16S, + OPCODE_AE_MULFC16S, + OPCODE_AE_MULAFC16S, + OPCODE_AE_MULFCJ16S, + OPCODE_AE_MULAFCJ16S, + OPCODE_AE_MULFCJ16RAS, + OPCODE_AE_MULAFCJ16RAS, + OPCODE_AE_MULC16S, + OPCODE_AE_MULAC16S, + OPCODE_AE_MULFP16X4RS, + OPCODE_AE_MULFD16X16X4RAS, + OPCODE_AE_MULP16X16X4S, + OPCODE_AE_MULAP16X16X4S, + OPCODE_AE_MULSP16X16X4S, + OPCODE_AE_MULZAA2D16SS_HH_LL, + OPCODE_AE_MULZAA2D16SS_HL_LH, + OPCODE_AE_MULZSS2D16SS_HH_LL, + OPCODE_AE_MULZSS2D16SS_HL_LH, + OPCODE_AE_MULAA2D16SS_HH_LL, + OPCODE_AE_MULAA2D16SS_HL_LH, + OPCODE_AE_MULSS2D16SS_HH_LL, + OPCODE_AE_MULSS2D16SS_HL_LH, + OPCODE_AE_MULZAAFD16SS_HH_LL, + OPCODE_AE_MULZAAFD16SS_HL_LH, + OPCODE_AE_MULZSSFD16SS_HH_LL, + OPCODE_AE_MULZSSFD16SS_HL_LH, + OPCODE_AE_MULAAFD16SS_HH_LL, + OPCODE_AE_MULAAFD16SS_HL_LH, + OPCODE_AE_MULSSFD16SS_HH_LL, + OPCODE_AE_MULSSFD16SS_HL_LH, + OPCODE_AE_MULFD16X16X4WS, + OPCODE_AE_MULZAAAA2Q16X8, + OPCODE_AE_MULAAAA2Q16X8, + OPCODE_AE_MULZAAAA2Q8, + OPCODE_AE_MULAAAA2Q8, + OPCODE_AE_MULC32X16W_H, + OPCODE_AE_MULAC32X16W_H, + OPCODE_AE_MULC32X16W_L, + OPCODE_AE_MULAC32X16W_L, + OPCODE_AE_MULPC32X16X2, + OPCODE_AE_MULAPC32X16X2, + OPCODE_AE_MULFP32X16_H, + OPCODE_AE_MULAFP32X16_H, + OPCODE_AE_MULSFP32X16_H, + OPCODE_AE_MULFP32X16_L, + OPCODE_AE_MULAFP32X16_L, + OPCODE_AE_MULSFP32X16_L, + OPCODE_AE_MULFC32X16W_H, + OPCODE_AE_MULAFC32X16W_H, + OPCODE_AE_MULFC32X16W_L, + OPCODE_AE_MULAFC32X16W_L, + OPCODE_AE_MULFCJ32X16W_H, + OPCODE_AE_MULAFCJ32X16W_H, + OPCODE_AE_MULFCJ32X16W_L, + OPCODE_AE_MULAFCJ32X16W_L, + OPCODE_AE_MULF2P32X16X4RAS, + OPCODE_AE_MULAF2P32X16X4RAS, + OPCODE_AE_MULSF2P32X16X4RAS, + OPCODE_AE_MULF2P32X16X4RS, + OPCODE_AE_MULAF2P32X16X4RS, + OPCODE_AE_MULSF2P32X16X4RS, + OPCODE_AE_MULF2P32X16X4S, + OPCODE_AE_MULAF2P32X16X4S, + OPCODE_AE_MULSF2P32X16X4S, + OPCODE_AE_MULFPC32X16X2RAS, + OPCODE_AE_MULAFPC32X16X2RAS, + OPCODE_AE_MULFPCJ32X16X2RAS, + OPCODE_AE_MULAFPCJ32X16X2RAS, + OPCODE_AE_MULZAAAA2Q32X16, + OPCODE_AE_MULAAAA2Q32X16, + OPCODE_AE_MUL2Q32X16_FIR_H, + OPCODE_AE_MULA2Q32X16_FIR_H, + OPCODE_AE_MUL2Q32X16_FIR_L, + OPCODE_AE_MULA2Q32X16_FIR_L, + OPCODE_AE_SRAI8, + OPCODE_AE_SRAI8R, + OPCODE_AE_SRLI8, + OPCODE_AE_SLAI8, + OPCODE_AE_SLAI8S, + OPCODE_AE_SLAA8, + OPCODE_AE_SRLA8, + OPCODE_AE_SLAA8S, + OPCODE_AE_SRAA8RS, + OPCODE_AE_SRAA8S, + OPCODE_AE_SRLI16, + OPCODE_AE_SLAI16, + OPCODE_AE_SLAA16, + OPCODE_AE_SRLA16, + OPCODE_AE_SRAI16SYM, + OPCODE_AE_SRAA16SYMS, + OPCODE_AE_SRAI32SYM, + OPCODE_AE_SRAA32SYMS, + OPCODE_AE_SRAV16RS, + OPCODE_AE_SRAV32RS, + OPCODE_AE_CVTI32X4F8_H, + OPCODE_AE_CVTI32X4F8_L, + OPCODE_AE_CVTI32X4F8S_H, + OPCODE_AE_CVTI32X4F8S_L, + OPCODE_AE_CVTA32X4F8_H, + OPCODE_AE_CVTA32X4F8_L, + OPCODE_AE_CVTA32X4F8S_H, + OPCODE_AE_CVTA32X4F8S_L, + OPCODE_AE_CVTI32X4F8U_H, + OPCODE_AE_CVTI32X4F8U_L, + OPCODE_AE_CVTI32X4F8US_H, + OPCODE_AE_CVTI32X4F8US_L, + OPCODE_AE_CVTA32X4F8U_H, + OPCODE_AE_CVTA32X4F8U_L, + OPCODE_AE_CVTA32X4F8US_H, + OPCODE_AE_CVTA32X4F8US_L, + OPCODE_AE_CVTI32X4F16, + OPCODE_AE_CVTI32X4F16S, + OPCODE_AE_CVTA32X4F16, + OPCODE_AE_CVTA32X4F16S, + OPCODE_AE_CVTI32X4F16U, + OPCODE_AE_CVTI32X4F16US, + OPCODE_AE_CVTA32X4F16U, + OPCODE_AE_CVTA32X4F16US, + OPCODE_AE_CVTI16X4X2F8, + OPCODE_AE_CVTI16X4X2F8S, + OPCODE_AE_CVTA16X4X2F8, + OPCODE_AE_CVTA16X4X2F8S, + OPCODE_AE_CVTI16X4X2F8U, + OPCODE_AE_CVTI16X4X2F8US, + OPCODE_AE_CVTA16X4X2F8U, + OPCODE_AE_CVTA16X4X2F8US, + OPCODE_AE_SEL8X8, + OPCODE_AE_SHFL8X8, + OPCODE_AE_SEL16X4, + OPCODE_AE_SHFL16X4, + OPCODE_AE_DSEL8X8, + OPCODE_AE_DSEL16X4, + OPCODE_AE_SEL8X8I, + OPCODE_AE_RMAX8X8, + OPCODE_AE_RMIN8X8, + OPCODE_AE_RMAX16X4, + OPCODE_AE_RMIN16X4, + OPCODE_AE_SORT16X4, + OPCODE_AE_RADD8X8_H, + OPCODE_AE_RADDA8X8_H, + OPCODE_AE_RADD8X8_L, + OPCODE_AE_RADDA8X8_L, + OPCODE_AE_RADD16X4, + OPCODE_AE_RADDA16X4, + OPCODE_AE_BMAX8X8_H, + OPCODE_AE_BMAX8X8_L, + OPCODE_AE_BMIN8X8_H, + OPCODE_AE_BMIN8X8_L, + OPCODE_AE_BMAX16X4, + OPCODE_AE_BMIN16X4, + OPCODE_AE_BMAX32X2, + OPCODE_AE_BMIN32X2, + OPCODE_AE_ADDINV16S, + OPCODE_AE_ADDINV32S, + OPCODE_AE_MOVT16X8, + OPCODE_AE_MOVT8X16_H, + OPCODE_AE_MOVT8X16_L, + OPCODE_AE_MOVBD1X4, + OPCODE_AE_MOVBD1X2, + OPCODE_AE_MOVNEG32S_T, + OPCODE_AE_MOVDEXT, + OPCODE_AE_MOVADEXT_H, + OPCODE_AE_MOVADEXT_L, + OPCODE_AE_NSA16X4, + OPCODE_AE_NSAZ32X4, + OPCODE_AE_NSA32X4, + OPCODE_AE_TRUNCI16X4F32S, + OPCODE_AE_TRUNCI16X4F64S, + OPCODE_AE_TRUNCA16X4F32S, + OPCODE_AE_TRUNCA16X4F64S, + OPCODE_AE_ADDC32, + OPCODE_AE_SUBC32, + OPCODE_AE_ADDC32U, + OPCODE_AE_SUBC32U, + OPCODE_AE_EXPADD16_H, + OPCODE_AE_EXPSUB16_H, + OPCODE_AE_EXPADD16_L, + OPCODE_AE_EXPSUB16_L, + OPCODE_AE_ADDCEXP32_H, + OPCODE_AE_ADDCEXP32_L, + OPCODE_AE_CALCRNG16, + OPCODE_AE_CALCRNG32, + OPCODE_AE_RNG32X4, + OPCODE_AE_LAV8X8X2_XP, + OPCODE_AE_LAV16X4X2_XP, + OPCODE_AE_SAV8X8X2_XP, + OPCODE_AE_SAV16X4X2_XP, + OPCODE_AE_MOVZBVCDR, + OPCODE_AE_MOVDRZBVC, + OPCODE_AE_LAVUNSQZ8X8_XP, + OPCODE_AE_LAVUNSQZ16X4_XP, + OPCODE_AE_MUL8Q8X8, + OPCODE_AE_MULA8Q8X8, + OPCODE_AE_MUL8Q4X16, + OPCODE_AE_MULA8Q4X16, + OPCODE_AE_MUL8Q8X16, + OPCODE_AE_MULA8Q8X16, + OPCODE_AE_MUL8QW8X16, + OPCODE_AE_MULA8QW8X16, + OPCODE_AE_MUL4O8X8, + OPCODE_AE_MULA4O8X8, + OPCODE_AE_MUL4O4X16, + OPCODE_AE_MULA4O4X16, + OPCODE_AE_MUL4O8X16, + OPCODE_AE_MULA4O8X16, + OPCODE_AE_MUL4QW8X16, + OPCODE_AE_MULA4QW8X16, + OPCODE_AE_MUL8Q8X8CNV_L, + OPCODE_AE_MUL8Q8X8CNV_H, + OPCODE_AE_MULA8Q8X8CNV_L, + OPCODE_AE_MULA8Q8X8CNV_H, + OPCODE_AE_MUL8Q8X16CNV, + OPCODE_AE_MULA8Q8X16CNV, + OPCODE_AE_MUL2X4Q8X8CNV_H, + OPCODE_AE_MULA2X4Q8X8CNV_H, + OPCODE_AE_MUL2X4Q8X8CNV_L, + OPCODE_AE_MULA2X4Q8X8CNV_L, + OPCODE_AE_MUL2X4Q8X16CNV, + OPCODE_AE_MULA2X4Q8X16CNV, + OPCODE_AE_MULQQ8X16CNV, + OPCODE_AE_MULAQQ8X16CNV, + OPCODE_AE_MUL4O8X8CNV_H, + OPCODE_AE_MULA4O8X8CNV_H, + OPCODE_AE_MUL4O8X8CNV_L, + OPCODE_AE_MULA4O8X8CNV_L, + OPCODE_AE_MUL4O8X16CNV_H, + OPCODE_AE_MULA4O8X16CNV_H, + OPCODE_AE_MUL4O8X16CNV_L, + OPCODE_AE_MULA4O8X16CNV_L, + OPCODE_AE_MUL8Q4X16CNV_H, + OPCODE_AE_MULA8Q4X16CNV_H, + OPCODE_AE_MUL8Q4X16CNV_L, + OPCODE_AE_MULA8Q4X16CNV_L, + OPCODE_AE_MUL2X4Q4X16CNV_H, + OPCODE_AE_MULA2X4Q4X16CNV_H, + OPCODE_AE_MUL2X4Q4X16CNV_L, + OPCODE_AE_MULA2X4Q4X16CNV_L, + OPCODE_AE_MULQQ4X16CNV_H, + OPCODE_AE_MULAQQ4X16CNV_H, + OPCODE_AE_MULQQ4X16CNV_L, + OPCODE_AE_MULAQQ4X16CNV_L, + OPCODE_AE_MUL4O4X16CNV_HH, + OPCODE_AE_MUL4O4X16CNV_HL, + OPCODE_AE_MUL4O4X16CNV_LH, + OPCODE_AE_MUL4O4X16CNV_LL, + OPCODE_AE_MULA4O4X16CNV_HH, + OPCODE_AE_MULA4O4X16CNV_HL, + OPCODE_AE_MULA4O4X16CNV_LH, + OPCODE_AE_MULA4O4X16CNV_LL, + OPCODE_AE_MULUU8Q8X8, + OPCODE_AE_MULAUU8Q8X8, + OPCODE_AE_MULUU4O8X8, + OPCODE_AE_MULAUU4O8X8, + OPCODE_AE_MULUU8Q8X8CNV_L, + OPCODE_AE_MULAUU8Q8X8CNV_L, + OPCODE_AE_MULUU8Q8X8CNV_H, + OPCODE_AE_MULAUU8Q8X8CNV_H, + OPCODE_AE_MULUU2X4Q8X8CNV_H, + OPCODE_AE_MULAUU2X4Q8X8CNV_H, + OPCODE_AE_MULUU2X4Q8X8CNV_L, + OPCODE_AE_MULAUU2X4Q8X8CNV_L, + OPCODE_AE_MULUU4O8X8CNV_H, + OPCODE_AE_MULAUU4O8X8CNV_H, + OPCODE_AE_MULUU4O8X8CNV_L, + OPCODE_AE_MULAUU4O8X8CNV_L, + OPCODE_AE_MULUS8Q8X8, + OPCODE_AE_MULAUS8Q8X8, + OPCODE_AE_MULUS8Q4X16, + OPCODE_AE_MULAUS8Q4X16, + OPCODE_AE_MULUS8Q8X16, + OPCODE_AE_MULAUS8Q8X16, + OPCODE_AE_MULUS8QW8X16, + OPCODE_AE_MULAUS8QW8X16, + OPCODE_AE_MULUS4O8X8, + OPCODE_AE_MULAUS4O8X8, + OPCODE_AE_MULUS4O4X16, + OPCODE_AE_MULAUS4O4X16, + OPCODE_AE_MULUS4O8X16, + OPCODE_AE_MULAUS4O8X16, + OPCODE_AE_MULUS4QW8X16, + OPCODE_AE_MULAUS4QW8X16, + OPCODE_AE_MULUS8Q8X8CNV_L, + OPCODE_AE_MULAUS8Q8X8CNV_L, + OPCODE_AE_MULUS8Q8X8CNV_H, + OPCODE_AE_MULAUS8Q8X8CNV_H, + OPCODE_AE_MULUS8Q8X16CNV, + OPCODE_AE_MULAUS8Q8X16CNV, + OPCODE_AE_MULUS2X4Q8X8CNV_H, + OPCODE_AE_MULAUS2X4Q8X8CNV_H, + OPCODE_AE_MULUS2X4Q8X8CNV_L, + OPCODE_AE_MULAUS2X4Q8X8CNV_L, + OPCODE_AE_MULUS2X4Q8X16CNV, + OPCODE_AE_MULAUS2X4Q8X16CNV, + OPCODE_AE_MULUSQQ8X16CNV, + OPCODE_AE_MULAUSQQ8X16CNV, + OPCODE_AE_MULUS4O8X8CNV_H, + OPCODE_AE_MULAUS4O8X8CNV_H, + OPCODE_AE_MULUS4O8X8CNV_L, + OPCODE_AE_MULAUS4O8X8CNV_L, + OPCODE_AE_MULUS4O8X16CNV_H, + OPCODE_AE_MULAUS4O8X16CNV_H, + OPCODE_AE_MULUS4O8X16CNV_L, + OPCODE_AE_MULAUS4O8X16CNV_L, + OPCODE_AE_MULUS8Q4X16CNV_H, + OPCODE_AE_MULAUS8Q4X16CNV_H, + OPCODE_AE_MULUS8Q4X16CNV_L, + OPCODE_AE_MULAUS8Q4X16CNV_L, + OPCODE_AE_MULUS2X4Q4X16CNV_H, + OPCODE_AE_MULAUS2X4Q4X16CNV_H, + OPCODE_AE_MULUS2X4Q4X16CNV_L, + OPCODE_AE_MULAUS2X4Q4X16CNV_L, + OPCODE_AE_MULUSQQ4X16CNV_H, + OPCODE_AE_MULAUSQQ4X16CNV_H, + OPCODE_AE_MULUSQQ4X16CNV_L, + OPCODE_AE_MULAUSQQ4X16CNV_L, + OPCODE_AE_MULUS4O4X16CNV_HH, + OPCODE_AE_MULUS4O4X16CNV_HL, + OPCODE_AE_MULUS4O4X16CNV_LH, + OPCODE_AE_MULUS4O4X16CNV_LL, + OPCODE_AE_MULAUS4O4X16CNV_HH, + OPCODE_AE_MULAUS4O4X16CNV_HL, + OPCODE_AE_MULAUS4O4X16CNV_LH, + OPCODE_AE_MULAUS4O4X16CNV_LL, + OPCODE_AE_MULSU8Q8X8, + OPCODE_AE_MULASU8Q8X8, + OPCODE_AE_MULSU4O8X8, + OPCODE_AE_MULASU4O8X8, + OPCODE_AE_MULSU8Q8X8CNV_L, + OPCODE_AE_MULASU8Q8X8CNV_L, + OPCODE_AE_MULSU8Q8X8CNV_H, + OPCODE_AE_MULASU8Q8X8CNV_H, + OPCODE_AE_MULSU2X4Q8X8CNV_H, + OPCODE_AE_MULASU2X4Q8X8CNV_H, + OPCODE_AE_MULSU2X4Q8X8CNV_L, + OPCODE_AE_MULASU2X4Q8X8CNV_L, + OPCODE_AE_MULSU4O8X8CNV_H, + OPCODE_AE_MULASU4O8X8CNV_H, + OPCODE_AE_MULSU4O8X8CNV_L, + OPCODE_AE_MULASU4O8X8CNV_L, + OPCODE_AE_MULUUZB8Q8X8, + OPCODE_AE_MULAUUZB8Q8X8, + OPCODE_AE_MULUUZB4O8X8, + OPCODE_AE_MULAUUZB4O8X8, + OPCODE_AE_MULUUZB8Q8X8CNV_L, + OPCODE_AE_MULAUUZB8Q8X8CNV_L, + OPCODE_AE_MULUUZB8Q8X8CNV_H, + OPCODE_AE_MULAUUZB8Q8X8CNV_H, + OPCODE_AE_MULUUZB2X4Q8X8CNV_H, + OPCODE_AE_MULAUUZB2X4Q8X8CNV_H, + OPCODE_AE_MULUUZB2X4Q8X8CNV_L, + OPCODE_AE_MULAUUZB2X4Q8X8CNV_L, + OPCODE_AE_MULUUZB4O8X8CNV_H, + OPCODE_AE_MULAUUZB4O8X8CNV_H, + OPCODE_AE_MULUUZB4O8X8CNV_L, + OPCODE_AE_MULAUUZB4O8X8CNV_L, + OPCODE_AE_MULUUZB3X3O8X8, + OPCODE_AE_MULAUUZB3X3O8X8, + OPCODE_AE_MULZB8Q8X8, + OPCODE_AE_MULAZB8Q8X8, + OPCODE_AE_MULZB4O8X8, + OPCODE_AE_MULAZB4O8X8, + OPCODE_AE_MULZB8Q8X8CNV_L, + OPCODE_AE_MULAZB8Q8X8CNV_L, + OPCODE_AE_MULZB8Q8X8CNV_H, + OPCODE_AE_MULAZB8Q8X8CNV_H, + OPCODE_AE_MULZB2X4Q8X8CNV_H, + OPCODE_AE_MULAZB2X4Q8X8CNV_H, + OPCODE_AE_MULZB2X4Q8X8CNV_L, + OPCODE_AE_MULAZB2X4Q8X8CNV_L, + OPCODE_AE_MULZB4O8X8CNV_H, + OPCODE_AE_MULAZB4O8X8CNV_H, + OPCODE_AE_MULZB4O8X8CNV_L, + OPCODE_AE_MULAZB4O8X8CNV_L, + OPCODE_AE_MULZB3X3O8X8, + OPCODE_AE_MULAZB3X3O8X8, + OPCODE_CVTSF16_L, + OPCODE_CVTSF16_H, + OPCODE_CVTF16S_L, + OPCODE_CVTF16S_H, + OPCODE_AE_MOVFCRFSRV, + OPCODE_AE_MOVVFCRFSR, + OPCODE_MOVT_S, + OPCODE_MOVF_S, + OPCODE_MOVEQZ_S, + OPCODE_MOVNEZ_S, + OPCODE_MOVGEZ_S, + OPCODE_MOVLTZ_S, + OPCODE_RFR, + OPCODE_WFR, + OPCODE_MUL_S, + OPCODE_MADD_S, + OPCODE_MSUB_S, + OPCODE_MSUBN_S, + OPCODE_MADDN_S, + OPCODE_ADD_S, + OPCODE_SUB_S, + OPCODE_OLE_S, + OPCODE_OLT_S, + OPCODE_OEQ_S, + OPCODE_UN_S, + OPCODE_ULE_S, + OPCODE_ULT_S, + OPCODE_UEQ_S, + OPCODE_NEXP01_S, + OPCODE_MKSADJ_S, + OPCODE_MKDADJ_S, + OPCODE_DIV0_S, + OPCODE_SQRT0_S, + OPCODE_RECIP0_S, + OPCODE_RSQRT0_S, + OPCODE_DIVN_S, + OPCODE_ADDEXP_S, + OPCODE_ADDEXPM_S, + OPCODE_MIN_S, + OPCODE_MAX_S, + OPCODE_MULMUX_S, + OPCODE_MADDMUX_S, + OPCODE_TRUNC_S, + OPCODE_UTRUNC_S, + OPCODE_TRUNC_SX2, + OPCODE_UTRUNC_SX2, + OPCODE_FICEIL_S, + OPCODE_FIFLOOR_S, + OPCODE_FIRINT_S, + OPCODE_FIROUND_S, + OPCODE_FITRUNC_S, + OPCODE_FLOAT_S, + OPCODE_UFLOAT_S, + OPCODE_FLOAT_SX2, + OPCODE_UFLOAT_SX2, + OPCODE_ABS_S, + OPCODE_NEG_S, + OPCODE_CONJC_S, + OPCODE_MULJC_S, + OPCODE_CONST_S, + OPCODE_CLSFY_S, + OPCODE_MINNUM_S, + OPCODE_MAXNUM_S, + OPCODE_ADDANDSUB_S, + OPCODE_ADDANDSUBJC_S, + OPCODE_ADD_HL_LH_S, + OPCODE_MADDA_S, + OPCODE_FREXP_S, + OPCODE_FLOATEXP_S, + OPCODE_MINNUMABS_S, + OPCODE_MAXNUMABS_S, + OPCODE_MULQ_S, + OPCODE_MADDQ_S, + OPCODE_MSUBQ_S, + OPCODE_MULMUXQ_S, + OPCODE_MADDMUXQ_S, + OPCODE_BMAXNUM_S, + OPCODE_BMINNUM_S, + OPCODE_BMAXNUMABS_S, + OPCODE_BMINNUMABS_S, + OPCODE_ABS_SX2X2, + OPCODE_NEG_SX2X2, + OPCODE_CONJC_SX2X2, + OPCODE_MULJC_SX2X2, + OPCODE_CONST_SX2X2, + OPCODE_ADD_SX2X2, + OPCODE_SUB_SX2X2, + OPCODE_MUL_SX2X2, + OPCODE_MADD_SX2X2, + OPCODE_MSUB_SX2X2, + OPCODE_MULMUX_SX2X2, + OPCODE_MADDMUX_SX2X2, + OPCODE_ABS_H, + OPCODE_ADDEXP_H, + OPCODE_ADDEXPM_H, + OPCODE_CLSFY_H, + OPCODE_CONJC_H, + OPCODE_CONST_H, + OPCODE_MIN_H, + OPCODE_MAX_H, + OPCODE_MINNUM_H, + OPCODE_MAXNUM_H, + OPCODE_MULJC_H, + OPCODE_NEG_H, + OPCODE_OEQ_H, + OPCODE_OLE_H, + OPCODE_OLT_H, + OPCODE_UEQ_H, + OPCODE_ULE_H, + OPCODE_ULT_H, + OPCODE_UN_H, + OPCODE_DIV0_H, + OPCODE_FICEIL_H, + OPCODE_FIFLOOR_H, + OPCODE_FIRINT_H, + OPCODE_FIROUND_H, + OPCODE_FITRUNC_H, + OPCODE_MKDADJ_H, + OPCODE_MKSADJ_H, + OPCODE_NEXP0_H, + OPCODE_NEXP01_H, + OPCODE_RECIP0_H, + OPCODE_RSQRT0_H, + OPCODE_SQRT0_H, + OPCODE_FLOAT16_H, + OPCODE_UFLOAT16_H, + OPCODE_TRUNC16_H, + OPCODE_UTRUNC16_H, + OPCODE_FLOAT16_HX4, + OPCODE_UFLOAT16_HX4, + OPCODE_TRUNC16_HX4, + OPCODE_UTRUNC16_HX4, + OPCODE_ADD_H, + OPCODE_SUB_H, + OPCODE_MUL_H, + OPCODE_MADD_H, + OPCODE_MSUB_H, + OPCODE_MADDN_H, + OPCODE_MSUBN_H, + OPCODE_DIVN_H, + OPCODE_RMINNUM_H, + OPCODE_RMAXNUM_H, + OPCODE_ABS_HX4X2, + OPCODE_NEG_HX4X2, + OPCODE_CONJC_HX4X2, + OPCODE_CONST_HX4X2, + OPCODE_MULJC_HX4X2, + OPCODE_ADD_HX4X2, + OPCODE_SUB_HX4X2, + OPCODE_MUL_HX4X2, + OPCODE_MADD_HX4X2, + OPCODE_MSUB_HX4X2, + OPCODE_MULQ_H, + OPCODE_MADDQ_H, + OPCODE_MULCNVH_HX4X2, + OPCODE_MULACNVH_HX4X2, + OPCODE_MULCNVL_HX4X2, + OPCODE_MULACNVL_HX4X2 +}; + + +/* Slot-specific opcode decode functions. */ + +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst_get (insn) == 0) + { + if (Field_op1_Slot_inst_get (insn) == 0) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_r_Slot_inst_get (insn) == 0) + { + if (Field_m_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return OPCODE_ILL; + if (Field_m_Slot_inst_get (insn) == 2) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_RET; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_RETW; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_JX; + } + if (Field_m_Slot_inst_get (insn) == 3) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALLX0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALLX4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALLX8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALLX12; + } + } + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_MOVSP; + if (Field_r_Slot_inst_get (insn) == 2) + { + if (Field_s_Slot_inst_get (insn) == 0) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_ISYNC; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RSYNC; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_ESYNC; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DSYNC; + if (Field_t_Slot_inst_get (insn) == 8) + return OPCODE_EXCW; + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_MEMW; + if (Field_t_Slot_inst_get (insn) == 13) + return OPCODE_EXTW; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_NOP; + } + } + if (Field_r_Slot_inst_get (insn) == 3) + { + if (Field_t_Slot_inst_get (insn) == 0) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_RFE; + if (Field_s_Slot_inst_get (insn) == 2) + return OPCODE_RFDE; + if (Field_s_Slot_inst_get (insn) == 4) + return OPCODE_RFWO; + if (Field_s_Slot_inst_get (insn) == 5) + return OPCODE_RFWU; + } + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFI; + if (Field_t_Slot_inst_get (insn) == 2 && + Field_s_Slot_inst_get (insn) == 1) + return OPCODE_CLREX; + } + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BREAK; + if (Field_r_Slot_inst_get (insn) == 5) + { + if (Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SYSCALL; + if (Field_s_Slot_inst_get (insn) == 1) + return OPCODE_SIMCALL; + } + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RSIL; + if (Field_r_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_WAITI; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_LDDR32_P; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_SDDR32_P; + } + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_ANY4; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_ALL4; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_ANY8; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_ALL8; + } + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_AND; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_OR; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_XOR; + if (Field_op2_Slot_inst_get (insn) == 4) + { + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSR; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSL; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8L; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8B; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_thi3_Slot_inst_get (insn) == 0) + return OPCODE_SSAI; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RER; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_WER; + if (Field_r_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_ROTW; + if (Field_r_Slot_inst_get (insn) == 10 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_GETEX; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_NSA; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_NSAU; + } + if (Field_op2_Slot_inst_get (insn) == 5) + { + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_RPTLB0; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_PPTLB; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_WPTLB; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_RPTLB1; + } + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_NEG; + if (Field_s_Slot_inst_get (insn) == 1) + return OPCODE_ABS; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_ADD; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_ADDX2; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_ADDX4; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_ADDX8; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_SUB; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_SUBX2; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_SUBX4; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_SUBX8; + } + if (Field_op1_Slot_inst_get (insn) == 1) + { + if ((Field_op2_Slot_inst_get (insn) == 0 || + Field_op2_Slot_inst_get (insn) == 1)) + return OPCODE_SLLI; + if ((Field_op2_Slot_inst_get (insn) == 2 || + Field_op2_Slot_inst_get (insn) == 3)) + return OPCODE_SRAI; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_SRLI; + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_XSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_XSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_XSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_XSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_XSR_BR; + if (Field_sr_Slot_inst_get (insn) == 40) + return OPCODE_XSR_PREFCTL; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_XSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_XSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_XSR_MPUENB; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_XSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_XSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_XSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 98) + return OPCODE_XSR_CACHEADRDIS; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_XSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_XSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 119) + return OPCODE_XSR_OPMODE; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_XSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_XSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_XSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_XSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_XSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_XSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_XSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_XSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_XSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_XSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_XSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_XSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_XSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_XSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_XSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_XSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_XSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_XSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_XSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_XSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_XSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_XSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_XSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_XSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_XSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_XSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_XSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_XSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_XSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_XSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_XSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_XSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_XSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_XSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_XSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_XSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_XSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_XSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_XSR_MISC1; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_XSR_MISC2; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_XSR_MISC3; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_SRC; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRL; + if (Field_op2_Slot_inst_get (insn) == 10 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SLL; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRA; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MUL16U; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MUL16S; + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_LICT; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_SICT; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_LICW; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_SICW; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_L32EX; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_S32EX; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LDCT; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_SDCT; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_LDCW; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_SDCW; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_RFDO; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFDD; + } + } + if (Field_op1_Slot_inst_get (insn) == 2) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_ANDB; + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_ANDBC; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_ORB; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_ORBC; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_XORB; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_SALTU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_SALT; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MULL; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_QUOU; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_QUOS; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_REMU; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_REMS; + } + if (Field_op1_Slot_inst_get (insn) == 3) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_RSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_RSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_RSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_RSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_RSR_BR; + if (Field_sr_Slot_inst_get (insn) == 40) + return OPCODE_RSR_PREFCTL; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_RSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_RSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_RSR_MPUENB; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_RSR_MPUCFG; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_RSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_RSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_RSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 98) + return OPCODE_RSR_CACHEADRDIS; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_RSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_RSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 119) + return OPCODE_RSR_OPMODE; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_RSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_RSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_RSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_RSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_RSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_RSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_RSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_RSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_RSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_RSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_RSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_RSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_RSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_RSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_RSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_RSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_RSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_RSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_RSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 208) + return OPCODE_RSR_CONFIGID1; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_RSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_RSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_RSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_RSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_RSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_RSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_RSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_RSR_INTERRUPT; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_RSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_RSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_RSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_RSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_RSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_RSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 235) + return OPCODE_RSR_PRID; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_RSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_RSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_RSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_RSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_RSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_RSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_RSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_RSR_MISC1; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_RSR_MISC2; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_RSR_MISC3; + } + if (Field_op2_Slot_inst_get (insn) == 1) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_WSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_WSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_WSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_WSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_WSR_BR; + if (Field_sr_Slot_inst_get (insn) == 40) + return OPCODE_WSR_PREFCTL; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_WSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_WSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 89) + return OPCODE_WSR_MMID; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_WSR_MPUENB; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_WSR_MPUCFG; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_WSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_WSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_WSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 98) + return OPCODE_WSR_CACHEADRDIS; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_WSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_WSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 119) + return OPCODE_WSR_OPMODE; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_WSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_WSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_WSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_WSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_WSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_WSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_WSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_WSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_WSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_WSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_WSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_WSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_WSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_WSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_WSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_WSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_WSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_WSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_WSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_WSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_WSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_WSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_WSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_WSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_WSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_WSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_WSR_INTSET; + if (Field_sr_Slot_inst_get (insn) == 227) + return OPCODE_WSR_INTCLEAR; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_WSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_WSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_WSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_WSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_WSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_WSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_WSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_WSR_MISC1; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_WSR_MISC2; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_WSR_MISC3; + } + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_SEXT; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_CLAMPS; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_MIN; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_MAX; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_MINU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_MAXU; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MOVEQZ; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_MOVNEZ; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MOVLTZ; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MOVGEZ; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MOVF; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MOVT; + if (Field_op2_Slot_inst_get (insn) == 14) + { + if (Field_st_Slot_inst_get (insn) == 230) + return OPCODE_RUR_EXPSTATE; + if (Field_st_Slot_inst_get (insn) == 231) + return OPCODE_RUR_THREADPTR; + if (Field_st_Slot_inst_get (insn) == 232) + return OPCODE_RUR_FCR; + if (Field_st_Slot_inst_get (insn) == 233) + return OPCODE_RUR_FSR; + if (Field_st_Slot_inst_get (insn) == 240) + return OPCODE_RUR_AE_OVF_SAR; + if (Field_st_Slot_inst_get (insn) == 241) + return OPCODE_RUR_AE_BITHEAD; + if (Field_st_Slot_inst_get (insn) == 242) + return OPCODE_RUR_AE_TS_FTS_BU_BP; + if (Field_st_Slot_inst_get (insn) == 243) + return OPCODE_RUR_AE_CW_SD_NO; + if (Field_st_Slot_inst_get (insn) == 246) + return OPCODE_RUR_AE_CBEGIN0; + if (Field_st_Slot_inst_get (insn) == 247) + return OPCODE_RUR_AE_CEND0; + if (Field_st_Slot_inst_get (insn) == 248) + return OPCODE_RUR_AE_CBEGIN1; + if (Field_st_Slot_inst_get (insn) == 249) + return OPCODE_RUR_AE_CEND1; + if (Field_st_Slot_inst_get (insn) == 250) + return OPCODE_RUR_AE_CBEGIN2; + if (Field_st_Slot_inst_get (insn) == 251) + return OPCODE_RUR_AE_CEND2; + } + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WUR_EXPSTATE; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WUR_THREADPTR; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WUR_FCR; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WUR_FSR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WUR_AE_OVF_SAR; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WUR_AE_BITHEAD; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_WUR_AE_TS_FTS_BU_BP; + if (Field_sr_Slot_inst_get (insn) == 243) + return OPCODE_WUR_AE_CW_SD_NO; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_WUR_AE_CBEGIN0; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_WUR_AE_CEND0; + if (Field_sr_Slot_inst_get (insn) == 248) + return OPCODE_WUR_AE_CBEGIN1; + if (Field_sr_Slot_inst_get (insn) == 249) + return OPCODE_WUR_AE_CEND1; + if (Field_sr_Slot_inst_get (insn) == 250) + return OPCODE_WUR_AE_CBEGIN2; + if (Field_sr_Slot_inst_get (insn) == 251) + return OPCODE_WUR_AE_CEND2; + } + } + if ((Field_op1_Slot_inst_get (insn) == 4 || + Field_op1_Slot_inst_get (insn) == 5)) + return OPCODE_EXTUI; + if (Field_op1_Slot_inst_get (insn) == 9) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_L32E; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_S32E; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_S32NB; + } + if (Field_r_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_READ_IMPWIRE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_SETB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_CLRB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_WRMSK_EXPSTATE; + } + if (Field_op0_Slot_inst_get (insn) == 1) + return OPCODE_L32R; + if (Field_op0_Slot_inst_get (insn) == 2) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_L8UI; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_L16UI; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_L32I; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_S8I; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_S16I; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_S32I; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_DPFR; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_DPFW; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_DPFRO; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DPFWO; + if (Field_t_Slot_inst_get (insn) == 4) + return OPCODE_DHWB; + if (Field_t_Slot_inst_get (insn) == 5) + return OPCODE_DHWBI; + if (Field_t_Slot_inst_get (insn) == 6) + return OPCODE_DHI; + if (Field_t_Slot_inst_get (insn) == 7) + return OPCODE_DII; + if (Field_t_Slot_inst_get (insn) == 8) + { + if (Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_DPFL; + if (Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_DHU; + if (Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_DIU; + if (Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_DIWB; + if (Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_DIWBI; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_DIWBUI_P; + } + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_IPF; + if (Field_t_Slot_inst_get (insn) == 13) + { + if (Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_IPFL; + if (Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_IHU; + if (Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_IIU; + } + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_IHI; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_III; + } + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_L16SI; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_MOVI; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_L32AI; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_ADDI; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_ADDMI; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_S32RI; + } + if (Field_op0_Slot_inst_get (insn) == 4) + { + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 10) + return OPCODE_RUR_AE_OVERFLOW; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 11) + return OPCODE_WUR_AE_OVERFLOW; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_SAR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 13) + return OPCODE_WUR_AE_SAR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 14) + return OPCODE_RUR_AE_BITPTR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 14 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 15) + return OPCODE_WUR_AE_BITPTR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 0) + return OPCODE_RUR_AE_BITSUSED; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 1) + return OPCODE_WUR_AE_BITSUSED; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 2) + return OPCODE_RUR_AE_TABLESIZE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 3) + return OPCODE_WUR_AE_TABLESIZE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 4) + return OPCODE_RUR_AE_FIRST_TS; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 5) + return OPCODE_WUR_AE_FIRST_TS; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 6) + return OPCODE_RUR_AE_NEXTOFFSET; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 7) + return OPCODE_WUR_AE_NEXTOFFSET; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 8) + return OPCODE_RUR_AE_SEARCHDONE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 9) + return OPCODE_WUR_AE_SEARCHDONE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 10) + return OPCODE_RUR_AE_CWRAP; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_fld_inst_15_12_Slot_inst_get (insn) == 15 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 11) + return OPCODE_WUR_AE_CWRAP; + } + if (Field_op0_Slot_inst_get (insn) == 5) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALL0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALL4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALL8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALL12; + } + if (Field_op0_Slot_inst_get (insn) == 6) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_J; + if (Field_n_Slot_inst_get (insn) == 1) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQZ; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEZ; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTZ; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEZ; + } + if (Field_n_Slot_inst_get (insn) == 2) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQI; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEI; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEI; + } + if (Field_n_Slot_inst_get (insn) == 3) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_ENTRY; + if (Field_m_Slot_inst_get (insn) == 1) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BF; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BT; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LOOP; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_LOOPNEZ; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_LOOPGTZ; + } + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTUI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEUI; + } + } + if (Field_op0_Slot_inst_get (insn) == 7) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BNONE; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BEQ; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_BLT; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_BLTU; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BALL; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_BBC; + if ((Field_r_Slot_inst_get (insn) == 6 || + Field_r_Slot_inst_get (insn) == 7)) + return OPCODE_BBCI; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_BANY; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_BNE; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_BGE; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_BGEU; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_BNALL; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_BBS; + if ((Field_r_Slot_inst_get (insn) == 14 || + Field_r_Slot_inst_get (insn) == 15)) + return OPCODE_BBSI; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16b_get (insn) == 12) + { + if (Field_i_Slot_inst16b_get (insn) == 0) + return OPCODE_MOVI_N; + if (Field_i_Slot_inst16b_get (insn) == 1) + { + if (Field_z_Slot_inst16b_get (insn) == 0) + return OPCODE_BEQZ_N; + if (Field_z_Slot_inst16b_get (insn) == 1) + return OPCODE_BNEZ_N; + } + } + if (Field_op0_Slot_inst16b_get (insn) == 13) + { + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 1) + return OPCODE_AE_L16SI_N; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 2) + return OPCODE_AE_L16UI_N; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 3) + return OPCODE_AE_S16I_N; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 4 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 0) + return OPCODE_AE_SEXT16; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 4 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 1) + return OPCODE_AE_ZEXT16; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 5 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 1) + return OPCODE_AE_ZEXT8; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 5 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 0) + return OPCODE_AE_CLAMPS16; + if (Field_r_Slot_inst16b_get (insn) == 0) + return OPCODE_MOV_N; + if (Field_r_Slot_inst16b_get (insn) == 15) + { + if (Field_t_Slot_inst16b_get (insn) == 0) + return OPCODE_RET_N; + if (Field_t_Slot_inst16b_get (insn) == 1) + return OPCODE_RETW_N; + if (Field_t_Slot_inst16b_get (insn) == 2) + return OPCODE_BREAK_N; + if (Field_t_Slot_inst16b_get (insn) == 3 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_NOP_N; + if (Field_t_Slot_inst16b_get (insn) == 6 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_ILL_N; + } + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16a_get (insn) == 8) + return OPCODE_L32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 9) + return OPCODE_S32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 10) + return OPCODE_ADD_N; + if (Field_op0_Slot_inst16a_get (insn) == 11) + return OPCODE_ADDI_N; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae10_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae10_slot0_24_0_Slot_ae10_slot0_get (insn) == 12720387) + return OPCODE_NOP; + if (Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (insn) == 12872 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_ALL4; + if (Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (insn) == 12872 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_ANY4; + if (Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (insn) == 12873 && + Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_get (insn) == 18) + return OPCODE_SSAI; + if (Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (insn) == 12873 && + Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_ALL8; + if (Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get (insn) == 12873 && + Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_ANY8; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3082) + return OPCODE_MAXU; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3083) + return OPCODE_MIN; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3084) + return OPCODE_SALT; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3085) + return OPCODE_SALTU; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3086) + return OPCODE_MOVF; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3087) + return OPCODE_MOVT; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3088) + return OPCODE_ORBC; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3089) + return OPCODE_XORB; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3090 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_ABS; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3090 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_NEG; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3104 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3144) + return OPCODE_ADD; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3145) + return OPCODE_ADDX2; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3146) + return OPCODE_MINU; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3147) + return OPCODE_MOVEQZ; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3148) + return OPCODE_SRC; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3149) + return OPCODE_SUB; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3150) + return OPCODE_CLAMPS; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3151) + return OPCODE_SEXT; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3154 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3154 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3208) + return OPCODE_ADDX4; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3209) + return OPCODE_ADDX8; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3210) + return OPCODE_MOVGEZ; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3211) + return OPCODE_MOVLTZ; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3212) + return OPCODE_SUBX2; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3213) + return OPCODE_SUBX4; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3214) + return OPCODE_SRLI; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3215) + return OPCODE_ANDB; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3272) + return OPCODE_AND; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3273) + return OPCODE_MAX; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3274) + return OPCODE_MOVNEZ; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3275) + return OPCODE_OR; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3276) + return OPCODE_SUBX8; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3277) + return OPCODE_XOR; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3278) + return OPCODE_ANDBC; + if (Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get (insn) == 3279) + return OPCODE_ORB; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1296) + return OPCODE_AE_L16M_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1297) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1298) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1299) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1300) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1301) + return OPCODE_AE_L16_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1302) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1303) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1304) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1305) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1306) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1307) + return OPCODE_AE_L32_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1308) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1309) + return OPCODE_AE_L64_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1310) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1311) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1328) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1329) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1330) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1331) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1332) + return OPCODE_AE_L16_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1333) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1334) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1335) + return OPCODE_AE_L32M_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1336) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1337) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1338) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1339) + return OPCODE_AE_L32_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1340) + return OPCODE_AE_L32_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1341) + return OPCODE_AE_L64_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1342) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1343) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1360) + return OPCODE_AE_L16M_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1361) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1362) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1363) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1364) + return OPCODE_AE_L16_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1365) + return OPCODE_AE_L16_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1366) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1367) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1368) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1369) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1370) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1371) + return OPCODE_AE_L32_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1372) + return OPCODE_AE_L64_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1373) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1374) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1375) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1392) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1393) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1394) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1395) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1396) + return OPCODE_AE_L16_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1397) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1398) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1399) + return OPCODE_AE_L32M_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1400) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1401) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1402) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1403) + return OPCODE_AE_L32_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1404) + return OPCODE_AE_L64_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1405) + return OPCODE_AE_L64_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1406) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1407) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1536) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1537) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1538) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1539) + return OPCODE_AE_L8_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1540) + return OPCODE_SRAI; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1568) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1569) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1570) + return OPCODE_AE_L8_I; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1571) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1576 && + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1576 && + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1600) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1601) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1602) + return OPCODE_AE_L8_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1603) + return OPCODE_AE_L8_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1608 && + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1608 && + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1632) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1633) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1634) + return OPCODE_AE_L8_X; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1635) + return OPCODE_SLLI; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_6_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 12) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 13) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 14) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 15) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get (insn) == 1640 && + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 158) + return OPCODE_ADDI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 159) + return OPCODE_ADDMI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 160) + return OPCODE_L16SI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 161) + return OPCODE_S16I; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 164) + return OPCODE_L16UI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 165) + return OPCODE_S32I; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 168) + return OPCODE_L32I; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 169) + return OPCODE_S8I; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 172) + return OPCODE_L8UI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 173) + return OPCODE_MOVI; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 194 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 194 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get (insn) == 194 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae10_slot0_24_17_Slot_ae10_slot0_get (insn) == 78) + return OPCODE_EXTUI; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 12) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 13) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 14) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 15) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 16) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 17) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 18) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 19) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 20) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 21) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 22) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 23) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 24) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 25) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 26) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 27) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 28) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 29) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 30) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 31) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 32) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 33) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 34) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 35) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 36) + return OPCODE_J; + if (Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get (insn) == 37) + return OPCODE_CALL0; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_LAV16X4X2_XP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_AE_LAV8X8X2_XP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_L32R; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 6) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 7) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 11 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5155) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5156) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5157) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5152) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5153) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5154) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5158) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5159) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get (insn) == 5160) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_8_Slot_ae10_slot0_get (insn) == 320) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_get (insn) == 9 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 0) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get (insn) == 12 && + Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_get (insn) == 9 && + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get (insn) == 1) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49680 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_CALLX0; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49682 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_JX; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49683 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_RET; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49685 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SSA8B; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49686 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SSA8L; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49687 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SSL; + if (Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get (insn) == 49688 && + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get (insn) == 3) + return OPCODE_SSR; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae10_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae10_slot1_25_1_Slot_ae10_slot1_get (insn) == 10793092 && + Field_fld_ae10_slot1_0_0_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5134) + return OPCODE_MAXU; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5135) + return OPCODE_MIN; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5136) + return OPCODE_SALT; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5137) + return OPCODE_SALTU; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5138) + return OPCODE_CLAMPS; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5139) + return OPCODE_SEXT; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5140 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 10) + return OPCODE_SLL; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5196) + return OPCODE_ADD; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5197) + return OPCODE_ADDX2; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5198) + return OPCODE_MINU; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5199) + return OPCODE_MOVEQZ; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5200) + return OPCODE_SRC; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5201) + return OPCODE_SUB; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5202) + return OPCODE_SRLI; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5203 && + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5203 && + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5203 && + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5203 && + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5260) + return OPCODE_ADDX4; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5261) + return OPCODE_ADDX8; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5262) + return OPCODE_MOVGEZ; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5263) + return OPCODE_MOVLTZ; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5264) + return OPCODE_SUBX2; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5265) + return OPCODE_SUBX4; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5324) + return OPCODE_AND; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5325) + return OPCODE_MAX; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5326) + return OPCODE_MOVNEZ; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5327) + return OPCODE_OR; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5328) + return OPCODE_SUBX8; + if (Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get (insn) == 5329) + return OPCODE_XOR; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2328) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2329) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2330) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2331) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2332) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2333) + return OPCODE_AE_L32_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2334) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2335) + return OPCODE_AE_L64_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2352) + return OPCODE_AE_L16M_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2353) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2354) + return OPCODE_AE_L16M_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2355) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2356) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2357) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2358) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2359) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2360) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2361) + return OPCODE_AE_L32M_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2362) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2363) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2364) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2365) + return OPCODE_AE_L32_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2366) + return OPCODE_AE_L32_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2367) + return OPCODE_AE_L64_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2384) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2385) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2386) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2387) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2388) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2389) + return OPCODE_AE_L16_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2390) + return OPCODE_AE_L16_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2391) + return OPCODE_AE_L16_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2392) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2393) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2394) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2395) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2396) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2397) + return OPCODE_AE_L32_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2398) + return OPCODE_AE_L64_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2399) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2416) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2417) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2418) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2419) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2420) + return OPCODE_AE_L16_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2421) + return OPCODE_AE_L16_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2422) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2423) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2424) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2425) + return OPCODE_AE_L32M_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2426) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2427) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2428) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2429) + return OPCODE_AE_L32_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2430) + return OPCODE_AE_L64_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2431) + return OPCODE_AE_L64_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2560) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2561) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2562) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2563) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2564) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2565) + return OPCODE_AE_L8_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2566) + return OPCODE_SRAI; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2570 && + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2592) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2593) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2594) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2595) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2596) + return OPCODE_AE_L8_I; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2597) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2602 && + Field_fld_ae10_slot1_3_2_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2602 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 4) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2602 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 5) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2602 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 6) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2602 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 7) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2624) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2625) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2626) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2627) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2628) + return OPCODE_AE_L8_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2629) + return OPCODE_AE_L8_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2633 && + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2633 && + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2656) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2657) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2658) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2659) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2660) + return OPCODE_AE_L8_X; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2661) + return OPCODE_SLLI; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2665 && + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get (insn) == 2665 && + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 290) + return OPCODE_MOVI; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 292) + return OPCODE_ADDI; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 293) + return OPCODE_ADDMI; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 296) + return OPCODE_L16SI; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 297) + return OPCODE_L32I; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 300) + return OPCODE_L16UI; + if (Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get (insn) == 301) + return OPCODE_L8UI; + if (Field_fld_ae10_slot1_25_17_Slot_ae10_slot1_get (insn) == 144) + return OPCODE_EXTUI; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 48) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 49) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 50) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 51) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 52) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 53) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 54) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 55) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 56) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 57) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 58) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 59) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 60) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 61) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 62) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 63) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 64) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 65) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 66) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 67) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 68) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 69) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 70) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get (insn) == 71) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 6) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 7) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 19 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 6) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 7) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 353 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get (insn) == 352) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_get (insn) == 10 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 8) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get (insn) == 20 && + Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_get (insn) == 10 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 9) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae10_slot1_25_22_Slot_ae10_slot1_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae10_slot1_25_23_Slot_ae10_slot1_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get (insn) == 82273 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 9) + return OPCODE_SSL; + if (Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get (insn) == 83266 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 10) + return OPCODE_SSA8B; + if (Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get (insn) == 83267 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 10) + return OPCODE_SSA8L; + if (Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get (insn) == 83297 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 9) + return OPCODE_SSR; + if (Field_fld_ae10_slot1_25_9_Slot_ae10_slot1_get (insn) == 41632 && + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get (insn) == 10) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae2_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L64_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L64_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L64_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1857 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32M_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1858 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1859 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1861 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S32_H_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1862 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S64_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S64_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S64_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1863 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1865 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1866 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_ADD; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_ADDX2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_ADDX4; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_ADDX8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AND; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SLLI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_SRAI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_MAX; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S8_0_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1867 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L8_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L8_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L8_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L8_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L8_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1869 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_SUB; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_SUBX2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_SUBX4; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_SUBX8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_OR; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_XOR; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_MOVEQZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_MOVGEZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_MOVLTZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_MOVNEZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_SRC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_SALT; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_SALTU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_MAXU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_MIN; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1870 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_MINU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_SRLI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_ANDB; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_ANDBC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_ORB; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_ORBC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_XORB; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_MOVF; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_MOVT; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_CLAMPS; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SEXT; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1871 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1873 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_CALLX0; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 10 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_JX; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_RET; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 22 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_SSA8B; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_SSA8L; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 30 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_SSL; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 12 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_MOVBD1X4; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1874 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_MOVBD1X2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_SA32X2_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_SA32X2F24_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_SA32X2F24_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SA24_L_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SA24_L_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_SA24X2_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1875 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SA24X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16X2M_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1877 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1878 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S8X4U_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1878 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S8X4U_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1878 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S8X4U_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1878 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S8X4U_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1881 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S32M_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 1885 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6304 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 175) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6304 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 47) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6305 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 47) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6308 && + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get (insn) == 175 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_SSR; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA32X2POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA32X2NEG_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6320 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4NEG_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA32X2POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6321 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA8X8POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA8X8NEG_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA8X8NEG_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6322 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA8X8POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA8X8POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6323 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_0_Slot_ae2_slot0_get (insn) == 36789) + return OPCODE_NOP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_0_Slot_ae2_slot0_get (insn) == 4020) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_2_Slot_ae2_slot0_get (insn) == 1004) + return OPCODE_AE_MOVALIGN; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24NEG_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6324 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6325 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6325 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6326 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6326 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24X2NEG_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6327 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6327 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_LA24X2POS_PC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 49) + return OPCODE_SSAI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_ALL4; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_ANY4; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 33) + return OPCODE_ALL8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 33) + return OPCODE_ANY8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6403 && + Field_fld_ae2_slot0_15_4_Slot_ae2_slot0_get (insn) == 1585) + return OPCODE_AE_MOVASAR; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6407 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6411 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6415 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6419 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6420 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6423 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6426 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6426 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVTA32F24S_L; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6426 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVTA32F24S_H; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6426 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6427 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6427 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6427 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6427 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6427 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6430 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6430 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_NSA64; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6430 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_NSAZ16_0; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6430 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_ABS; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_NEG; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 12 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6431 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_TRUNCA32Q48; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6456 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6456 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6457 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6457 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6458 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6458 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6459 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6459 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6460 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6460 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6461 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6461 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6462 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6462 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6463 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 6463 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16M_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L16M_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7299 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7303 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7534) + return OPCODE_ADDI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7535) + return OPCODE_ADDMI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7544) + return OPCODE_L16SI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7545) + return OPCODE_L32I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7546) + return OPCODE_S16I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7547) + return OPCODE_S8I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7548) + return OPCODE_L16UI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7549) + return OPCODE_L8UI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7550) + return OPCODE_S32I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7551) + return OPCODE_MOVI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7554 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7554 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7554 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_MOVI; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7555 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_MOVAD8; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7558 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7558 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7558 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_LA24_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_LA24_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_LA24X2_IC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7559 && + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_LA24X2_RIC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L16_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L16_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L16_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L16_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7564 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L16_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7565 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L32M_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32M_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7566 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L32_I; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L32_IP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L32_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get (insn) == 7567 && + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_get (insn) == 3224 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_TRUNC16_H; + if (Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_get (insn) == 3225 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_UTRUNC16_H; + if (Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_get (insn) == 3765) + return OPCODE_EXTUI; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 457) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 459) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 461) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 463) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1564 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_EQ8; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1565 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_LE8; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1566 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1566 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 31) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1566 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_LT8; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1567 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1567 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 31) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1567 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1567 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 27) + return OPCODE_AE_S24RA64S_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1568 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1569 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1570 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1571 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1572 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1573 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1600 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1600 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1600 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1600 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1601 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_AE_MOV; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1601 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1601 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1601 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1602 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1602 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1602 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_CVTF16S_L; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1602 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_CVTF16S_H; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1603 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_CVTSF16_L; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1603 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_CVTSF16_H; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1603 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_FICEIL_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1603 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_FIFLOOR_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1604 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1604 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_FIRINT_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1604 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_FIROUND_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1604 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_FITRUNC_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1605 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1608 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_OLE_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1608 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_OEQ_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1609 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_OLT_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1609 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_UEQ_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1610 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_ULE_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1610 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_ULT_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1611 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1611 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1611 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_UN_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1613 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_PKSR32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1613 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_PKSR24; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1613 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1613 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_PKSR16; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1806) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1807) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1810) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1811) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1812) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1813) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1814) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1815) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1816) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1817) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_S16X4RA32S_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_MOVT64; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MOVF64; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_MOVT_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1826 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_MOVF_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1864) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1865) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1866) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1867) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1868) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1869) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1870) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1871) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1874) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1875) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1876) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1877) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1878) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1879) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_LT16; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_LE16; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_EQ16; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LT32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_LE32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_EQ32; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_LT64; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_LE64; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_EQ64; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_MOVEQZ_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_MOVNEZ_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_MOVGEZ_S; + if (Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get (insn) == 1890 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_MOVLTZ_S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 232 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRAA32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 232 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRAA32RS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 232 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SLAA64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 233 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRAA32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 233 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SLAA64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 233 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRAA32SYMS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 234 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRAA64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 234 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SLAA8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 234 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRAA8RS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 235 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRAAQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 235 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SLAA8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 235 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRAA8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 768 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADD64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 768 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADD8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 769 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 769 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADD8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 770 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 770 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 771 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADDSUB32_HL_LH; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 771 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADDSUB32S_HL_LH; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 772 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_MAX32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 772 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MAX16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 773 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MAX64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 773 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_MAX8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 774 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_MIN32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 774 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MIN16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 775 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MIN64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 775 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_MIN8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 776 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUB16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 776 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_MOVNEG32S_T; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 777 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUB24S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 777 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUB16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 778 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUB32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 778 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUB32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 779 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUB64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 779 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUB64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 780 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUB8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 780 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUB8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 781 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 781 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 782 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 787 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_FLOAT16_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 787 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_UFLOAT16_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 788 && + Field_fld_ae2_slot0_14_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 241) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 242) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 246) + return OPCODE_AE_ABS32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 245) + return OPCODE_AE_ABS24S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 247) + return OPCODE_AE_ABS32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 244) + return OPCODE_AE_ABS16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 243) + return OPCODE_AE_ABS16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 248) + return OPCODE_AE_ABS64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 252) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 249) + return OPCODE_AE_ABS64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 255) + return OPCODE_AE_MUL16JS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 240) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 250) + return OPCODE_AE_ABS8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 251) + return OPCODE_AE_ABS8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 253) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 789 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 254) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 240) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 243) + return OPCODE_AE_NEG32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 242) + return OPCODE_AE_NEG24S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 244) + return OPCODE_AE_NEG32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 241) + return OPCODE_AE_NEG16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 245) + return OPCODE_AE_NEG64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 248) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 246) + return OPCODE_AE_NEG64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 790 && + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get (insn) == 247) + return OPCODE_AE_NEG8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 800 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 800 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 800 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 800 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 801 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 801 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L64_IP; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 801 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 801 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 802 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 802 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 802 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 802 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S64_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S64_IP; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_NSA16X4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FICEIL_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FIFLOOR_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FIRINT_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FIROUND_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 10 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FITRUNC_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 15 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_RMINNUM_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 803 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_RMAXNUM_H; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 804 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 28 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS24; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 804 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 30 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 804 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 29 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 804 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 31 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 805 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 30 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLASQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 805 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 28 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 805 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 31 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLASSQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 805 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 29 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAS64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 806 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 28 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAS24; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 806 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 29 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAS32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 806 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 31 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRASQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 806 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 30 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAS64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 807 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 28 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRLS24; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 807 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 29 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRLS32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 807 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 31 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRLSQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 807 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 30 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRLS64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 898) + return OPCODE_AE_TRUNCA16X4F32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 899) + return OPCODE_AE_TRUNCA16X4F64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 900) + return OPCODE_AE_TRUNCI32F64S_L; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 901) + return OPCODE_AE_TRUNCI32X2F64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 902) + return OPCODE_AE_SEL16I; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 909 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_ADDC32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 909 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_ADDC32U; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 910 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_BMAX32X2; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 910 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_BMIN32X2; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 911 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SUBC32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 911 && + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SUBC32U; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 16) + return OPCODE_AE_SRAI16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 17) + return OPCODE_AE_SRAI16R; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 20) + return OPCODE_AE_SRLA32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SLAI16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SLAA16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_SLAAQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 23) + return OPCODE_AE_SRLAQ56; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 21) + return OPCODE_AE_SRLA64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SLAASQ56S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 22) + return OPCODE_AE_SRLA8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 24) + return OPCODE_AE_SRLI16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_SLAI16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_SLAA16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 19) + return OPCODE_AE_SRLA16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 912 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 18) + return OPCODE_AE_SRAI16SYM; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_AND; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_NAND; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_OR; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_XOR; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SRAV16RS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAV32RS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_NSAZ32X4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 913 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_NSA32X4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 930) + return OPCODE_AE_TRUNCA32F64S_L; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 931) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 940 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_CALL0; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 940 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_J; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_ADD32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_ADD16; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_ADD24S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_ADD32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_ADD16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADD64; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_BMAX16X4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 942 && + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_BMIN16X4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_SRA64_32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_SLAA32; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_SRAA16S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SRAA16RS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SLAA32S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 18 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAI8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 19 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRAI8R; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 20 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SRLI8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAI8; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 17 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAI8S; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SRAA16SYMS; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_FLOAT16_HX4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_UFLOAT16_HX4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_TRUNC16_HX4; + if (Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get (insn) == 944 && + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_UTRUNC16_HX4; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 56) + return OPCODE_AE_TRUNCI16X4F64S; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 57 && + Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_L32R; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 58 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SLAI64; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 58 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_SRLI64; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 58 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SRAI64; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 58 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SLAISQ56S; + if (Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get (insn) == 58 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAI64S; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 49 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_FLOAT_S; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 49 && + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_UFLOAT_S; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_TRUNC_S; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_UTRUNC_S; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 36) + return OPCODE_TRUNC_SX2; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 44) + return OPCODE_UTRUNC_SX2; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 32) + return OPCODE_FLOAT_SX2; + if (Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get (insn) == 50 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 40) + return OPCODE_UFLOAT_SX2; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_MOVT8X16_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_MOVT8X16_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_18_17_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_ADDW8; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_ADDW16; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_ADDW32; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SUBW8; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SUBW16; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SUBW32; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_ADDW8U; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 24 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SUBW8U; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 9 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 4 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 12 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 8 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 10 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 25 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 26) + return OPCODE_AE_CVTA32X4F8_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 27) + return OPCODE_AE_CVTA32X4F8_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 20) + return OPCODE_AE_CVTA32X4F8S_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 21) + return OPCODE_AE_CVTA32X4F8S_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 24) + return OPCODE_AE_CVTA32X4F8U_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 25) + return OPCODE_AE_CVTA32X4F8U_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 22) + return OPCODE_AE_CVTA32X4F8US_H; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 23) + return OPCODE_AE_CVTA32X4F8US_L; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 16) + return OPCODE_AE_CVTA32X4F16; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 17) + return OPCODE_AE_CVTA32X4F16S; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 18) + return OPCODE_AE_CVTA32X4F16U; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 19) + return OPCODE_AE_CVTA32X4F16US; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 28) + return OPCODE_AE_CVTI16X4X2F8; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 29) + return OPCODE_AE_CVTI16X4X2F8S; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 30) + return OPCODE_AE_CVTI16X4X2F8U; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 31) + return OPCODE_AE_CVTI16X4X2F8US; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_LAV8X8X2_XP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 26 && + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LAV16X4X2_XP; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 27 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_CVTA16X4X2F8; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 27 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_CVTA16X4X2F8S; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 27 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_CVTA16X4X2F8U; + if (Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get (insn) == 27 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_CVTA16X4X2F8US; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_CVTI32X4F8_H; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_CVTI32X4F8_L; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_CVTI32X4F8S_H; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_CVTI32X4F8S_L; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_CVTI32X4F8U_H; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_CVTI32X4F8U_L; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_CVTI32X4F8US_H; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_CVTI32X4F8US_L; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_CVTI32X4F16; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_CVTI32X4F16S; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_CVTI32X4F16U; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_CVTI32X4F16US; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SLAI24; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_SRLI24; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_SRAI24; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SLAI32; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SRLI32; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SRAI32; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRAI32R; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAI24S; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SLAI32S; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 16 && + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRAI32SYM; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVDEXT; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_get (insn) == 16) + return OPCODE_AE_MOVADEXT_H; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_get (insn) == 17) + return OPCODE_AE_MOVADEXT_L; + if (Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCI16X4F32S; + if (Field_fld_ae2_slot0_40_26_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVT16X8; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_BBSI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_BALL_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_BANY_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_BBC_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_BBS_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_BEQ_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_BGEU_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_BGE_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_BLTU_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_BLT_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_BNALL_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_BNE_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_BNONE_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_BEQZ_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_BGEZ_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_BLTZ_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_BNEZ_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_BEQI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_BGEI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_BLTI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_BNEI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_BGEUI_W15; + if (Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_BLTUI_W15; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae2_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7692 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_SLL; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7692 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_TRUNCA32Q48; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7692 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_NSA64; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7692 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_NSAZ16_0; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7692 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7693 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7694 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7694 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7694 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7694 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7695 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7695 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7695 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7695 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7698) + return OPCODE_ADD; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7700 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7700 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7700 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7700 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7706) + return OPCODE_ADDX2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_0_Slot_ae2_slot1_get (insn) == 1794) + return OPCODE_NOP; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_SSL; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 5 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_SSR; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7708 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 6 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_MOVASAR; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7746) + return OPCODE_ADDX4; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7747 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_CVTA32F24S_H; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7754) + return OPCODE_ADDX8; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7755 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_CVTA32F24S_L; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7762) + return OPCODE_AND; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7763 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7770) + return OPCODE_MAX; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7771 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7778) + return OPCODE_MAXU; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7779 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7786) + return OPCODE_MIN; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7787 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7794) + return OPCODE_MINU; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7795 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7802) + return OPCODE_MOVEQZ; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7803 && + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7810) + return OPCODE_MOVGEZ; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7818) + return OPCODE_MOVLTZ; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7826) + return OPCODE_MOVNEZ; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7834) + return OPCODE_OR; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7842) + return OPCODE_SALT; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7850) + return OPCODE_SALTU; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7858) + return OPCODE_SRC; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7866) + return OPCODE_SUB; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7874) + return OPCODE_SUBX2; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7882) + return OPCODE_SUBX4; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7890) + return OPCODE_SUBX8; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7898) + return OPCODE_XOR; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7906) + return OPCODE_CLAMPS; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7914) + return OPCODE_SEXT; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7922) + return OPCODE_SRLI; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7930) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7936 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_SSA8B; + if (Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get (insn) == 7944 && + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_SSA8L; + if (Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_get (insn) == 1921 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_get (insn) == 1923 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 928 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_ABS_S; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 929 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_CONJC_H; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 930 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_CONJC_S; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 931 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_MULJC_H; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 932 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_MULJC_S; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 933 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_NEG_S; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 934 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 11) + return OPCODE_CONST_S; + if (Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get (insn) == 934 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 10) + return OPCODE_CONST_H; + if (Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_get (insn) == 480 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_SRAI; + if (Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_get (insn) == 496 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_SSAI; + if (Field_fld_ae2_slot1_36_17_Slot_ae2_slot1_get (insn) == 241 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_SLLI; + if (Field_fld_ae2_slot1_36_18_Slot_ae2_slot1_get (insn) == 120 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 13 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVAD8; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 12) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 13) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 14) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 15) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 16) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 17) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 18) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 19) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 20) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 21 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 21 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 21 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 21 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 22 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 22 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 22 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 22 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 23 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 23 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 23 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 23 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 24 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 24 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 24 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 24 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 25 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 25 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 25 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 25 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 26 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 26 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 26 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 26 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 27 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 27 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 27 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 27 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_ADDI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_ADDMI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_L16UI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_L16SI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_L32I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_L8UI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_MOVI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 83) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 84) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 80) + return OPCODE_AE_L16M_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 81) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 82) + return OPCODE_AE_L16M_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 85) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 100) + return OPCODE_AE_L16_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 101) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 97) + return OPCODE_AE_L16_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 98) + return OPCODE_AE_L16_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 99) + return OPCODE_AE_L16_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 102) + return OPCODE_AE_L16_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 106) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 107) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 103) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 104) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 105) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 108) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 126) + return OPCODE_AE_L32_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 127) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 123) + return OPCODE_AE_L32_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 124) + return OPCODE_AE_L32_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 125) + return OPCODE_AE_L32_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 112) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 109) + return OPCODE_AE_L32M_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 110) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 111) + return OPCODE_AE_L32M_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 113) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 89) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 90) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 86) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 87) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 88) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 91) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 115) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 116) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 114) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 117) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 119) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 120) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 118) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 122) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 93) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 94) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 92) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 96) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 121) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 95) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 8 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_MOVEQZ_S; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 9 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_MOVNEZ_S; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 8 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_MOVGEZ_S; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 28 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 9 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_MOVLTZ_S; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 11) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L64_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 11) + return OPCODE_AE_L64_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 13) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 7) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 15) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 8) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 14) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 12) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 29 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 7) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 8) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 9) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 10) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 11) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 12) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 13) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 14) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 15) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 16) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 17) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 26) + return OPCODE_AE_L8_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 27) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 23) + return OPCODE_AE_L8_I; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 24) + return OPCODE_AE_L8_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 25) + return OPCODE_AE_L8_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 28) + return OPCODE_AE_L8_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 49 && + Field_fld_ae2_slot1_3_3_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 19) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 20) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 48 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 18) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 22) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L64_XC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L64_X; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_AE_L64_XP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 21) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 49 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 14) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 29) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_MOV; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 49 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 12) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 49 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 8) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 49 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 10) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 3 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 7 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 14 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 14 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 2 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_NSA16X4; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_ABS_H; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 30 && + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get (insn) == 12 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_NEG_H; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 4 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 8 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_2_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_MOVI; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get (insn) == 1 && + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get (insn) == 0 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get (insn) == 31 && + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get (insn) == 8 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae2_slot1_36_22_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae2_slot1_36_23_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae3_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (insn) == 133982 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_ALL4; + if (Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (insn) == 133982 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_ANY4; + if (Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (insn) == 133983 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 2 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_SSAI; + if (Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (insn) == 133983 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_ALL8; + if (Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get (insn) == 133983 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_ANY8; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66890) + return OPCODE_AE_LBK; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66891) + return OPCODE_AND; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66894) + return OPCODE_MAX; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66895) + return OPCODE_MAXU; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66898) + return OPCODE_AE_SBI_IC; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66899) + return OPCODE_AE_SBI_IC1; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66902) + return OPCODE_AE_SBI_IP; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66903) + return OPCODE_AE_VLDL16T; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66906) + return OPCODE_AE_VLDL32T; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66907) + return OPCODE_AE_VLEL16T; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66910) + return OPCODE_AE_VLEL32T; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66911) + return OPCODE_MOVF; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66914) + return OPCODE_MOVT; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66915) + return OPCODE_AE_LBKI; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66918) + return OPCODE_CLAMPS; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66919) + return OPCODE_SEXT; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66922) + return OPCODE_SRLI; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66923) + return OPCODE_ANDB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66926) + return OPCODE_ANDBC; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66927) + return OPCODE_ORB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66930) + return OPCODE_ORBC; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66931) + return OPCODE_XORB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66950 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_SLL; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66951 && + Field_fld_ae3_slot0_9_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_MOVEA; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66990 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVBA1X2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_SRA; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_SRL; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_MOVAB4; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_MOVAB2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_MOVAB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_MOVBA; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_MOVBA4; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_AE_MOVBA2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get (insn) == 22) + return OPCODE_AE_MOVB2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get (insn) == 39) + return OPCODE_AE_MOVB4; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_AE_LBI; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_LBSI; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 66991 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 2 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_MOVAE; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67354 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_ABS; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67354 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_AE_LB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67355 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_NEG; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67355 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_LBS; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67364) + return OPCODE_ADD; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67365) + return OPCODE_ADDX2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67366) + return OPCODE_ADDX4; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67367) + return OPCODE_ADDX8; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67368) + return OPCODE_SALTU; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67369) + return OPCODE_SRC; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67370) + return OPCODE_SUB; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67371) + return OPCODE_SUBX2; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67372) + return OPCODE_SUBX4; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67373) + return OPCODE_SUBX8; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67374) + return OPCODE_XOR; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67375) + return OPCODE_AE_SBI; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67409) + return OPCODE_MIN; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67411) + return OPCODE_MINU; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67413) + return OPCODE_MOVEQZ; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67415) + return OPCODE_MOVGEZ; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67417) + return OPCODE_MOVLTZ; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67419) + return OPCODE_MOVNEZ; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67421) + return OPCODE_OR; + if (Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get (insn) == 67423) + return OPCODE_SALT; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33329) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33331) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33333) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33335) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33337) + return OPCODE_AE_L16_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33339) + return OPCODE_AE_L16_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33341) + return OPCODE_AE_L16_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33343) + return OPCODE_AE_L16_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33398) + return OPCODE_AE_L16M_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33399) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33400) + return OPCODE_AE_L16M_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33401) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33402) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33403) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33404) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33405) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33406) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33407) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33409) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33411) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33413) + return OPCODE_AE_S64_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33415) + return OPCODE_AE_S64_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33417) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33419) + return OPCODE_AE_S64_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33421) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33423) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33425) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33427) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33429) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33431) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33433) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33435) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33437) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33439) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33441) + return OPCODE_SLLI; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33443) + return OPCODE_SRAI; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33467 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33467 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33469 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33469 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33471 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33471 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33473 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33477 && + Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_get (insn) == 192) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33489 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33489 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33489 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33489 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33491 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33491 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33491 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33491 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA8X8_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33493 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33493 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33493 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33493 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_MOVI; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33497) + return OPCODE_AE_S8X4U_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33499 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S8X4U_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33536 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33537 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33538 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33539 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33540 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33541 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33542 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33543 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33544 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33545 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33546 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33547 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33548 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33549 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33550 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33551 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33552 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33553 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33554 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33555 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33556 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33557 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33558 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33559 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33560 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33561 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33562 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33563 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33564 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33565 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33566 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33567 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33568) + return OPCODE_AE_L16_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33569) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33570) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33571) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33572) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33573) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33574) + return OPCODE_AE_L32M_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33575) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33576) + return OPCODE_AE_L32M_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33577) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33578) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33579) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33580) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33581) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33582) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33583) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33584) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33585) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33586) + return OPCODE_AE_L32_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33587) + return OPCODE_AE_L32_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33588) + return OPCODE_AE_L32_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33589) + return OPCODE_AE_L32_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33590) + return OPCODE_AE_L32_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33591) + return OPCODE_AE_L64_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33592) + return OPCODE_AE_L64_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33593) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33594) + return OPCODE_AE_L64_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33595) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33596) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33597) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33598) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33599) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33600) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33601) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33602) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33603) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33604) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33605) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33606) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33607) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33608) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33609) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33610) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33611) + return OPCODE_AE_L8_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33612) + return OPCODE_AE_L8_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33613) + return OPCODE_AE_L8_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33614) + return OPCODE_AE_L8_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33615) + return OPCODE_AE_L8_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33616) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33617) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33618) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33619) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33620) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33621) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33622) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33623) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33624) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33625) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33626) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33627) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33628) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33629) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33630) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33631) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33632) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33633) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33634) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33635) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33636) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33637) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33638) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33639) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33640) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33641) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33642) + return OPCODE_AE_S32M_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33643) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33644) + return OPCODE_AE_S32M_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33645) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33646) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33647) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33648) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33649) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33650) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33651) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33652) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33653) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33654) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33655) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33656) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33657) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33658) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33659) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33660) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33661) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33662) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33663) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33676 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_AE_TRUNCA16P24S_L; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_NSAZ16_0; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33677 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33688 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33688 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33689 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33689 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33690 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33690 && + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_MOVAD8; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33691 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33691 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33691 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33691 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33694 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33694 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33694 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33694 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33695 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33695 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33695 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33695 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33728 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33729 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33730) + return OPCODE_AE_S8X4U_I; + if (Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get (insn) == 33731) + return OPCODE_AE_S8X4U_X; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16698) + return OPCODE_AE_MOVT64; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16840 && + Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16840 && + Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_ABS32; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_AE_NEG24S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_ABS24S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 13) + return OPCODE_AE_ABS32S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_AE_NEG16S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_ABS16S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_ABS64; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16846 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_MOV; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_NEG32; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_AE_NEG32S; + if (Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get (insn) == 16864 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_AE_NEG64; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8338) + return OPCODE_AE_ADD16S; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8339) + return OPCODE_AE_ADD32S; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8340) + return OPCODE_AE_MAX32; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8341) + return OPCODE_AE_MIN32; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8342) + return OPCODE_AE_ROUND16X4F32SASYM; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8343) + return OPCODE_AE_ROUND24X2F48SSYM; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8344) + return OPCODE_AE_SUB16S; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8345) + return OPCODE_AE_SUB32S; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8346) + return OPCODE_AE_AND; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8347) + return OPCODE_AE_OR; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8348) + return OPCODE_AE_XOR; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8416 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8416 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8416 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8416 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8417 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8417 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L64_IP; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8417 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8417 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8418 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8418 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8418 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8418 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_S64_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8419 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8419 && + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S64_IP; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8424 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LT16; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8424 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LE32; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8424 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_EQ32; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8425 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8425 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8425 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LE16; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8425 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_EQ16; + if (Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get (insn) == 8425 && + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LT32; + if (Field_fld_ae3_slot0_32_16_Slot_ae3_slot0_get (insn) == 4168) + return OPCODE_MOVI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2078) + return OPCODE_EXTUI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2079 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_ADDI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2079 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_ADDMI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2080 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_L16UI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2080 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_L16SI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2081 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_L32I; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2081 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_L8UI; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2082 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_S16I; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2082 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_S32I; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2083 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_S8I; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2092 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2092 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_LOOPGTZ; + if (Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get (insn) == 2092 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_LOOPNEZ; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1036) + return OPCODE_J; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1037) + return OPCODE_CALL0; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1048 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1048 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1048 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S16X4RA32S_IP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get (insn) == 1053 && + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 256) + return OPCODE_L32R; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 257) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 258 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 258 && + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCI32X2F64S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 13 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SRAS24; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_SRLA32; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_SLAA16S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_SRAA16S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_SRAA16RS; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 13 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_AE_SLAA32S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_SRAA32S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_SLAAQ56; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SRAAQ56; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_AE_SLAA64; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SLAASQ56S; + if (Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get (insn) == 261 && + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_SRLA16; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_BBSI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_BALL_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_BANY_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_BBC_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_BBS_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_BEQ_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_BGEU_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_BGE_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 13) + return OPCODE_BLTU_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_BLT_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_BNALL_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_BNE_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_BNONE_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_BEQZ_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_BGEZ_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get (insn) == 74) + return OPCODE_BLTZ_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get (insn) == 78) + return OPCODE_BNEZ_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_BEQI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_BGEI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_BLTI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_BNEI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_BGEUI_W15; + if (Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_BLTUI_W15; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071217 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_SBF; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071218 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLDL16C; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071219 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLES16C_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071221 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_SBF_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071222 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLDL16C_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071223 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLES16C_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071225 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_SBF_IC1; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071226 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLDL16C_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071227 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_CALLX0; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071229 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_SBF_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071230 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_VLES16C; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071841) + return OPCODE_AE_DB; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071843) + return OPCODE_AE_SB; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071845) + return OPCODE_AE_DB_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071847) + return OPCODE_AE_SB_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071849) + return OPCODE_AE_DB_IC1; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071851) + return OPCODE_AE_SB_IC1; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071853) + return OPCODE_AE_DB_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071855) + return OPCODE_AE_SB_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071856 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071858 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071860 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071862 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2POS_PC2; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071864 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071866 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071866 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_AE_VLDSHT; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071868 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071870 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_RUR_AE_BITPTR; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1071870 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8NEG_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078411) + return OPCODE_AE_DBI; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078415) + return OPCODE_AE_DBI_IC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078443) + return OPCODE_AE_DBI_IC1; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078447) + return OPCODE_AE_DBI_IP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078475) + return OPCODE_AE_SHA32; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078479 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078479 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078479 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078479 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4POS_PC2; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078507 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8POS_PC; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078507 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8POS_PC2; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078507 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078507 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_JX; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_get (insn) == 116) + return OPCODE_NOP; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_RET; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_SSA8B; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_SSA8L; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_SSL; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_SSR; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_2_Slot_ae3_slot0_get (insn) == 28) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get (insn) == 1078511 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 2 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVALIGN; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae3_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae3_slot1_23_0_Slot_ae3_slot1_get (insn) == 1873411) + return OPCODE_NOP; + if (Field_fld_ae3_slot1_23_11_Slot_ae3_slot1_get (insn) == 914 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSAI; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 420) + return OPCODE_ADD; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 421) + return OPCODE_ADDX2; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 422) + return OPCODE_ADDX4; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 423) + return OPCODE_ADDX8; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 424) + return OPCODE_AE_LBK; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 425) + return OPCODE_AND; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 426) + return OPCODE_MAX; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 427) + return OPCODE_MAXU; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 428) + return OPCODE_MIN; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 429) + return OPCODE_MINU; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 430) + return OPCODE_MOVEQZ; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 431) + return OPCODE_MOVGEZ; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 432) + return OPCODE_MOVLTZ; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 433) + return OPCODE_MOVNEZ; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 434) + return OPCODE_OR; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 435) + return OPCODE_SALT; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 436) + return OPCODE_SALTU; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 437) + return OPCODE_SRC; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 438) + return OPCODE_SUB; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 439) + return OPCODE_SUBX2; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 440) + return OPCODE_SUBX4; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 441) + return OPCODE_SUBX8; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 442) + return OPCODE_XOR; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 443) + return OPCODE_CLAMPS; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 444) + return OPCODE_SEXT; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 445) + return OPCODE_SRLI; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 446) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 456 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 456 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 456 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 456 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 4) + return OPCODE_SRL; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 456 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_LB; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 457 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 457 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get (insn) == 457 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_LBI; + if (Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_get (insn) == 208) + return OPCODE_SLLI; + if (Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_get (insn) == 209) + return OPCODE_SRAI; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 34 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 34 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16M_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 34 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 34 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L16M_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 35 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 35 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 35 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 35 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 36 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 36 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 36 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 36 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 37 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L16_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 37 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L16_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 37 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 37 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 38 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L16_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 38 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 38 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L16_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 38 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 39 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 39 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 39 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 39 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 40 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 40 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32M_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 40 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 40 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L32M_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 41 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 41 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 41 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 41 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 42 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 42 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 42 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 42 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 43 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 43 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L32_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 43 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L32_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 43 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 44 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 44 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 44 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L64_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 44 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L64_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 45 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 45 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L64_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 45 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L64_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 45 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L64_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 46 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 46 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 46 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 46 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 47 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 47 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 47 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 47 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 48 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 48 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 48 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 48 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 49 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8_I; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 49 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 49 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 49 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 50 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_L8_XC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 50 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 50 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L8_X; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 50 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_L8_XP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3 && + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3 && + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_MOVDA32X2; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 51 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 14) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 15) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0 && + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 0 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_AE_MOVI; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 1 && + Field_fld_ae3_slot1_3_1_Slot_ae3_slot1_get (insn) == 6) + return OPCODE_AE_MOV; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 2 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get (insn) == 56 && + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get (insn) == 3 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 10) + return OPCODE_ADDI; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 11) + return OPCODE_ADDMI; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 12) + return OPCODE_L16SI; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 13) + return OPCODE_L16UI; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 14) + return OPCODE_L32I; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 15) + return OPCODE_L8UI; + if (Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get (insn) == 16) + return OPCODE_MOVI; + if (Field_fld_ae3_slot1_23_17_Slot_ae3_slot1_get (insn) == 4) + return OPCODE_EXTUI; + if (Field_fld_ae3_slot1_23_19_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_SEL16I; + if (Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_get (insn) == 28624) + return OPCODE_AE_MOVAE; + if (Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_get (insn) == 28625) + return OPCODE_AE_MOVEA; + if (Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (insn) == 7157 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (insn) == 7313 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSA8B; + if (Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (insn) == 7314 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSL; + if (Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (insn) == 7315 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSR; + if (Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get (insn) == 7317 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSA8L; + if (Field_fld_ae3_slot1_23_9_Slot_ae3_slot1_get (insn) == 3576) + return OPCODE_AE_MOVAD32_L; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot0_22_0_Slot_ae4_slot0_get (insn) == 4088843) + return OPCODE_NOP; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 964) + return OPCODE_ADD; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 965) + return OPCODE_ADDX2; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 966) + return OPCODE_ADDX4; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 967) + return OPCODE_ADDX8; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 968) + return OPCODE_AND; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 969) + return OPCODE_MAX; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 970) + return OPCODE_MAXU; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 971) + return OPCODE_MIN; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 972) + return OPCODE_MINU; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 973) + return OPCODE_MOVEQZ; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 974) + return OPCODE_MOVGEZ; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 975) + return OPCODE_MOVLTZ; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 976) + return OPCODE_MOVNEZ; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 977) + return OPCODE_OR; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 978) + return OPCODE_SALT; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 979) + return OPCODE_SALTU; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 980) + return OPCODE_SRC; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 981) + return OPCODE_SUB; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 982) + return OPCODE_SUBX2; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 983) + return OPCODE_SUBX4; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 984) + return OPCODE_SUBX8; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 985) + return OPCODE_XOR; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 986) + return OPCODE_MOVF; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 987) + return OPCODE_MOVT; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 988) + return OPCODE_CLAMPS; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 989) + return OPCODE_SEXT; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 990) + return OPCODE_SRLI; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 991) + return OPCODE_ANDB; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 992) + return OPCODE_ANDBC; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 993) + return OPCODE_ORB; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 994) + return OPCODE_ORBC; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 995) + return OPCODE_XORB; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 996) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 997 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 997 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 997 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 1) + return OPCODE_SRA; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 997 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get (insn) == 1008 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_get (insn) == 480) + return OPCODE_SLLI; + if (Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_get (insn) == 481) + return OPCODE_SRAI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 50) + return OPCODE_ADDI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 51) + return OPCODE_ADDMI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 52) + return OPCODE_L16SI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 53) + return OPCODE_L16UI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 54) + return OPCODE_L32I; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 55) + return OPCODE_L8UI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 56) + return OPCODE_S16I; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 57) + return OPCODE_S32I; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 58) + return OPCODE_S8I; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 59) + return OPCODE_MOVI; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 63 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 63 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get (insn) == 63 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae4_slot0_22_17_Slot_ae4_slot0_get (insn) == 24) + return OPCODE_EXTUI; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 4) + return OPCODE_AE_S32X2X2RNG_IP; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 5) + return OPCODE_AE_S32X2X2RNG_XP; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 6) + return OPCODE_AE_S32X2X2_IP; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 7) + return OPCODE_AE_S32X2X2_X; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 8) + return OPCODE_AE_S32X2X2_XP; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 9) + return OPCODE_J; + if (Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get (insn) == 10) + return OPCODE_CALL0; + if (Field_fld_ae4_slot0_22_20_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_L32R; + if (Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get (insn) == 63884) + return OPCODE_ALL4; + if (Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get (insn) == 63885) + return OPCODE_ANY4; + if (Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get (insn) == 63886 && + Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_ALL8; + if (Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get (insn) == 63886 && + Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_get (insn) == 1) + return OPCODE_ANY8; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15968) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15969) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15970) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 2) + return OPCODE_CALLX0; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 4) + return OPCODE_JX; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 5) + return OPCODE_RET; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 7) + return OPCODE_SSA8B; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 8) + return OPCODE_SSA8L; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 9) + return OPCODE_SSL; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get (insn) == 10) + return OPCODE_SSR; + if (Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get (insn) == 15972 && + Field_fld_ae4_slot0_3_1_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot1_22_0_Slot_ae4_slot1_get (insn) == 2847494) + return OPCODE_NOP; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 668) + return OPCODE_ADD; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 669) + return OPCODE_ADDX2; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 670) + return OPCODE_ADDX4; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 671) + return OPCODE_ADDX8; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 672) + return OPCODE_AND; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 673) + return OPCODE_MAX; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 674) + return OPCODE_MAXU; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 675) + return OPCODE_MIN; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 676) + return OPCODE_MINU; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 677) + return OPCODE_MOVEQZ; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 678) + return OPCODE_MOVGEZ; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 679) + return OPCODE_MOVLTZ; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 680) + return OPCODE_MOVNEZ; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 681) + return OPCODE_OR; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 682) + return OPCODE_SALT; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 683) + return OPCODE_SALTU; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 684) + return OPCODE_SRC; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 685) + return OPCODE_SUB; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 686) + return OPCODE_SUBX2; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 687) + return OPCODE_SUBX4; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 688) + return OPCODE_SUBX8; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 689) + return OPCODE_XOR; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 690) + return OPCODE_CLAMPS; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 691) + return OPCODE_SEXT; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 692) + return OPCODE_SRLI; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 693) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 694 && + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 694 && + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 694 && + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 694 && + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get (insn) == 696 && + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 328) + return OPCODE_SLLI; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 329) + return OPCODE_SRAI; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 330) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 331) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 332) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get (insn) == 333) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 34) + return OPCODE_ADDI; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 35) + return OPCODE_ADDMI; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 36) + return OPCODE_L16SI; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 37) + return OPCODE_L16UI; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 38) + return OPCODE_L32I; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 39) + return OPCODE_L8UI; + if (Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get (insn) == 40) + return OPCODE_MOVI; + if (Field_fld_ae4_slot1_22_17_Slot_ae4_slot1_get (insn) == 16) + return OPCODE_EXTUI; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 0) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 1) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 2) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 3) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 4) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 5) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 6) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get (insn) == 7) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11120) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11121) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11122) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11123 && + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (insn) == 2) + return OPCODE_SSA8B; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11123 && + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (insn) == 3) + return OPCODE_SSA8L; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11123 && + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (insn) == 4) + return OPCODE_SSL; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11123 && + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get (insn) == 5) + return OPCODE_SSR; + if (Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get (insn) == 11123 && + Field_fld_ae4_slot1_3_1_Slot_ae4_slot1_get (insn) == 0) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae5_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67092) + return OPCODE_ADD; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67093) + return OPCODE_ADDX2; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67094) + return OPCODE_ADDX4; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67095) + return OPCODE_ADDX8; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67128) + return OPCODE_AND; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67129) + return OPCODE_MAX; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67130) + return OPCODE_MAXU; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67131) + return OPCODE_MIN; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67132) + return OPCODE_MINU; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67133) + return OPCODE_MOVEQZ; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67134) + return OPCODE_MOVGEZ; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67135) + return OPCODE_MOVLTZ; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67137) + return OPCODE_MOVNEZ; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67139) + return OPCODE_OR; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67141) + return OPCODE_SALT; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67143) + return OPCODE_SALTU; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67145) + return OPCODE_SRC; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67147) + return OPCODE_SUB; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67149) + return OPCODE_SUBX2; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67151) + return OPCODE_SUBX4; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67153) + return OPCODE_SUBX8; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67155) + return OPCODE_XOR; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67157) + return OPCODE_MOVF; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67159) + return OPCODE_MOVT; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67161) + return OPCODE_CLAMPS; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67163) + return OPCODE_SEXT; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67165) + return OPCODE_SRLI; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67167) + return OPCODE_AE_ARDECNORM16; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67169) + return OPCODE_ANDB; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67171) + return OPCODE_ANDBC; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67173) + return OPCODE_ORB; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67175) + return OPCODE_ORBC; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67177) + return OPCODE_XORB; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67228 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67234 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 11) + return OPCODE_ABS; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67234 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 7) + return OPCODE_SRA; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67234 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 15) + return OPCODE_SRL; + if (Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get (insn) == 67235 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 11) + return OPCODE_NEG; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33328) + return OPCODE_AE_L16M_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33329) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33330) + return OPCODE_AE_L16M_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33331) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33332) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33333) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33334) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33335) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33336) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33337) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33338) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33339) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33340) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33341) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33342) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33343) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33376 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33376 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33377 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33377 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33378 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33378 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33379 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33379 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33380 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33380 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33381 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33381 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33382 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33382 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33383 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33383 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33384 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33384 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33385 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33385 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33386 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33386 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33387 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33387 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33387 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33388 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33388 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33388 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33389 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33389 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33389 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33390 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33390 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33390 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33391 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33391 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33391 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33392 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33392 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33392 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33393 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33393 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33393 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33394 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33394 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33394 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33395 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33395 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33395 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33396 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33396 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33396 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33397 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33397 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33397 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33398 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33398 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33398 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33399 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33399 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33399 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33400 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33400 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33400 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33401 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33401 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33401 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33402 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33402 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33402 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33403 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33403 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33403 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33404 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33404 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33404 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33405 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33405 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33405 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33406 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33406 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33406 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33407 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33407 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33407 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33408) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33409) + return OPCODE_AE_L16_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33410) + return OPCODE_AE_L16_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33411) + return OPCODE_AE_L16_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33412) + return OPCODE_AE_L16_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33413) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33414) + return OPCODE_AE_L16_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33415) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33416) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33417) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33418) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33419) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33420) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33421) + return OPCODE_AE_L32M_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33422) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33423) + return OPCODE_AE_L32M_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33424) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33425) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33426) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33427) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33428) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33429) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33430) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33431) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33432) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33433) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33434) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33435) + return OPCODE_AE_L32_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33436) + return OPCODE_AE_L32_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33437) + return OPCODE_AE_L32_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33438) + return OPCODE_AE_L32_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33439) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33440) + return OPCODE_AE_L32_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33441) + return OPCODE_AE_L64_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33442) + return OPCODE_AE_L64_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33443) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33444) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33445) + return OPCODE_AE_L64_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33446) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33447) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33448) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33449) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33450) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33451) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33452) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33453) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33454) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33455) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33456) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33457) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33458) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33459) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33460) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33461) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33462) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33463) + return OPCODE_AE_L8_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33464) + return OPCODE_AE_L8_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33465) + return OPCODE_AE_L8_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33466) + return OPCODE_AE_L8_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33467) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33468) + return OPCODE_AE_L8_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33469) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33470) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33471) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33472) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33473) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33474) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33475) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33476) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33477) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33478) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33479) + return OPCODE_AE_S16X2M_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33480) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33481) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33482) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33483) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33484) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33485) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33486) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33487) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33488) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33489) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33490) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33491) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33492) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33493) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33494) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33495) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33496) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33497) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33498) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33499) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33500) + return OPCODE_AE_S32M_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33501) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33502) + return OPCODE_AE_S32M_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33503) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33504) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33505) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33506) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33507) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33508) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33509) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33510) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33511) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33512) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33513) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33514) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33515) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33516) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33517) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33518) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33519) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33520) + return OPCODE_AE_S32_H_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33521) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33522) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33523) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33524) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33525) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33526) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33527) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33528) + return OPCODE_AE_S64_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33529) + return OPCODE_AE_S64_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33530) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33531) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33532) + return OPCODE_AE_S64_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33533) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33534) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33535) + return OPCODE_AE_S8X8_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33536) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33537) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33538) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33539) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33540) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33541) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33542) + return OPCODE_AE_S8_0_XC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33543) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33544) + return OPCODE_SLLI; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33545) + return OPCODE_SRAI; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33608 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33608 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_MOVAD8; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33609 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33610 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33611 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33612 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33613 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33615 && + Field_fld_ae5_slot0_7_0_Slot_ae5_slot0_get (insn) == 48) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33616 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_IC2; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33616 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33616 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33616 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA8X8_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 9) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 13) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 10) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 14) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33617 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_RIP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33618) + return OPCODE_AE_S8X4U_I; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33619) + return OPCODE_AE_S8X4U_X; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33620) + return OPCODE_AE_S8X4U_XP; + if (Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get (insn) == 33621 && + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_S8X4U_IP; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8387 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8387 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8387 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8387 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8388 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8388 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_L64_IP; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8388 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8388 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8389 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8389 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8389 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8389 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_S64_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8390 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8390 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_S64_IP; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8400 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get (insn) == 8400 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 7) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4150) + return OPCODE_ADDI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4151) + return OPCODE_ADDMI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4152) + return OPCODE_AE_LBK_DB; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4153) + return OPCODE_AE_LBK_DB_IC; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4154) + return OPCODE_AE_LBK_DB_IP; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4155) + return OPCODE_L16SI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4156) + return OPCODE_L16UI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4157) + return OPCODE_L32I; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4158) + return OPCODE_L8UI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4159) + return OPCODE_S16I; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4160) + return OPCODE_S32I; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4161) + return OPCODE_S8I; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4162) + return OPCODE_AE_LBKI_DBI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4163) + return OPCODE_AE_LBKI_DBI_IC; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4164) + return OPCODE_AE_LBKI_DBI_IP; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4165) + return OPCODE_MOVI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_AE_LBI_DBI_IC; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_AE_LBI_DBI_IP; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LBI_DBI; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LB_DB_IC; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LB_DB_IP; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LB_DB; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_get (insn) == 2 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_CALCRNG16; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4200 && + Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_get (insn) == 3 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_CALCRNG32; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4201 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4201 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get (insn) == 4201 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae5_slot0_29_17_Slot_ae5_slot0_get (insn) == 2074) + return OPCODE_EXTUI; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1034) + return OPCODE_J; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1035) + return OPCODE_CALL0; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 25) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 27) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 28) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 31) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 30) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 29) + return OPCODE_AE_S32RA64S_XC1; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 20) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 22) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 21) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 26) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 23) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 24) + return OPCODE_AE_S24RA64S_XC1; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_ADD32; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_ADD32S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 9) + return OPCODE_MOVT_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_MOVF_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_MOVEQZ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_MOVNEZ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_MOVGEZ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1042 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 7) + return OPCODE_MOVLTZ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_S16X4RA32S_IP; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (insn) == 12) + return OPCODE_AE_PKSR32; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (insn) == 28) + return OPCODE_AE_PKSR24; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (insn) == 28) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1043 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (insn) == 12) + return OPCODE_AE_PKSR16; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_get (insn) == 101) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_AE_MOVDA16X2; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_get (insn) == 100) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_6_Slot_ae5_slot0_get (insn) == 24) + return OPCODE_AE_MOVI; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_CVTP24A16X2_LH; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_CVTP24A16X2_HL; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_CVTP24A16X2_HH; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_get (insn) == 102) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_OLE_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 2 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_OLT_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_OEQ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 3 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_UN_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 2 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_ULE_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 2 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_ULT_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1049 && + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get (insn) == 2 && + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_UEQ_S; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1051 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get (insn) == 1051 && + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_MOV; + if (Field_fld_ae5_slot0_29_19_Slot_ae5_slot0_get (insn) == 516) + return OPCODE_AE_SEL16I; + if (Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_get (insn) == 256) + return OPCODE_L32R; + if (Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_get (insn) == 257) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_BBSI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_BALL_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_BANY_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_BBC_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 7) + return OPCODE_BBS_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_BEQ_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 9) + return OPCODE_BGEU_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 10) + return OPCODE_BGE_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 11) + return OPCODE_BLTU_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 12) + return OPCODE_BLT_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 13) + return OPCODE_BNALL_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 14) + return OPCODE_BNE_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 0 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 15) + return OPCODE_BNONE_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get (insn) == 12) + return OPCODE_BEQZ_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get (insn) == 14) + return OPCODE_BGEZ_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get (insn) == 28) + return OPCODE_BLTZ_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get (insn) == 30) + return OPCODE_BNEZ_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_BEQI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_BGEI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_BLTI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 10) + return OPCODE_BNEI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_BGEUI_W15; + if (Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_BLTUI_W15; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605313 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_VLDL16C_IC1; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605321 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_VLES16C_IC1; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605329 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_CALLX0; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605345 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_JX; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605353 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_RET; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605369 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_SSA8B; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605377 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_SSA8L; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605385 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_SSL; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605393 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_SSR; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605401 && + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get (insn) == 17) + return OPCODE_NOP; + if (Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get (insn) == 8605401 && + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get (insn) == 1 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae5_slot0_29_6_Slot_ae5_slot0_get (insn) == 4301276 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_MOVALIGN; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075222 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075222 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075222 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4POS_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075222 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4NEG_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075223 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075223 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075223 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24NEG_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075223 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4POS_PC2; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075254 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA24POS_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075254 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075254 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075254 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2NEG_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075255 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA24X2POS_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075255 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075255 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075255 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2NEG_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075286 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075286 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2POS_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075286 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2POS_PC2; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075286 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8NEG_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075287 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8POS_PC; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075287 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8POS_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075287 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8NEG_PC1; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075287 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8POS_PC2; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075318 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_ALL4; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075318 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_ANY4; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075318 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075318 && + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075319 && + Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_SSAI; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075319 && + Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_ALL8; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075319 && + Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_ANY8; + if (Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get (insn) == 1075319 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_RUR_AE_BITPTR; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae8_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10761) + return OPCODE_ADD; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10765) + return OPCODE_ADDX2; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10769) + return OPCODE_ADDX4; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10773) + return OPCODE_ADDX8; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10777) + return OPCODE_AND; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10781) + return OPCODE_MAX; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10785) + return OPCODE_MAXU; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10789) + return OPCODE_MIN; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10793) + return OPCODE_MINU; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10797) + return OPCODE_MOVEQZ; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10801) + return OPCODE_MOVGEZ; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10805) + return OPCODE_MOVLTZ; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10809) + return OPCODE_MOVNEZ; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10813) + return OPCODE_OR; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10817) + return OPCODE_SALT; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10821) + return OPCODE_SALTU; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10825) + return OPCODE_SRC; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10829) + return OPCODE_SUB; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10833) + return OPCODE_SUBX2; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10837) + return OPCODE_SUBX4; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10841) + return OPCODE_SUBX8; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10845) + return OPCODE_XOR; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10849) + return OPCODE_MOVF; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10853) + return OPCODE_MOVT; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10857) + return OPCODE_CLAMPS; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10861) + return OPCODE_SEXT; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10865) + return OPCODE_SRLI; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10869) + return OPCODE_ANDB; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10873) + return OPCODE_ANDBC; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10877) + return OPCODE_ORB; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10881) + return OPCODE_ORBC; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10885) + return OPCODE_XORB; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10889 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10889 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10889 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10889 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get (insn) == 10893 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_SLL; + if (Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (insn) == 1344 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_SLLI; + if (Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (insn) == 1360 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_ALL4; + if (Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (insn) == 1360 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_ANY4; + if (Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (insn) == 1360 && + Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_get (insn) == 102) + return OPCODE_ALL8; + if (Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get (insn) == 1360 && + Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_get (insn) == 103) + return OPCODE_ANY8; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 94) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 95) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 96) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 97) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 98) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 99) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 100) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 101) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 102) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 103) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 104) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 105) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 106) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 107) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 108) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 109) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 110) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 111) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 112) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 113) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 114) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 115) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 116) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 117) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 118) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 119) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 120) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 121) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 122) + return OPCODE_AE_S16X4X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 123) + return OPCODE_AE_S16X4X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 124) + return OPCODE_AE_S16X4X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 125) + return OPCODE_AE_S16X4X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 126) + return OPCODE_AE_S16X4X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 127) + return OPCODE_AE_S16X4X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 128) + return OPCODE_AE_S16X4X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 129) + return OPCODE_AE_S32X2X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 130) + return OPCODE_AE_S32X2X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 131) + return OPCODE_AE_S32X2X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 132) + return OPCODE_AE_S32X2X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 133) + return OPCODE_AE_S32X2X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 134) + return OPCODE_AE_S32X2X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 135) + return OPCODE_AE_S32X2X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 136) + return OPCODE_AE_S64X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 137) + return OPCODE_AE_S64X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 138) + return OPCODE_AE_S64X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 139) + return OPCODE_AE_S64X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 140) + return OPCODE_AE_S64X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 141) + return OPCODE_AE_S64X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 142) + return OPCODE_AE_S64X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 143) + return OPCODE_AE_S8X8X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 144) + return OPCODE_AE_S8X8X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 145) + return OPCODE_AE_S8X8X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 146) + return OPCODE_AE_S8X8X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 147) + return OPCODE_AE_S8X8X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 148) + return OPCODE_AE_S8X8X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 149) + return OPCODE_AE_S8X8X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 150) + return OPCODE_J; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 151) + return OPCODE_CALL0; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 153 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 153 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 153 && + Field_fld_ae8_slot0_13_13_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 154 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_L16SI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 154 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_L32I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 154 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_S16I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 154 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_S8I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 155 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_L16UI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 155 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_L8UI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 155 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_MOVI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 155 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_S32I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 160 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 0 && + Field_fld_ae8_slot0_7_5_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_SRAI; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L16M_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_L16_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 17) + return OPCODE_AE_L8_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_L32_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_L32_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_L32M_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_L64_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 20) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 26) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 21) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 19) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 18) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 29) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 27) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 28) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 23) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 30) + return OPCODE_AE_S64_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 24) + return OPCODE_AE_S32M_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 25) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 16) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 22) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 164 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 31) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_L16_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 17) + return OPCODE_AE_L8_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_L32_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 16) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_L64_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 20) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 25) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 21) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 22) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 18) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 19) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 29) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 28) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 27) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 23) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 30) + return OPCODE_AE_S64_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 31) + return OPCODE_AE_S64_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 24) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 165 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 26) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L16M_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_L16_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 17) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 16) + return OPCODE_AE_L8_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_L32_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_L32M_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_L64_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 20) + return OPCODE_AE_S16X2M_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 19) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 25) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 26) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 21) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 31) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 18) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 28) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 29) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 27) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 23) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 22) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 30) + return OPCODE_AE_S64_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 24) + return OPCODE_AE_S32M_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 166 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_L16_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_L16_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 16) + return OPCODE_AE_L8_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 17) + return OPCODE_AE_L8_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_L32_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_L64_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_L64_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 19) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 20) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 25) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 21) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 31) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 18) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 28) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 27) + return OPCODE_AE_S32_H_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 26) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 22) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 23) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 30) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 29) + return OPCODE_AE_S64_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 167 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 24) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 168 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 168 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 168 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_S8_0_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 168 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 169 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_XC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 169 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 169 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 169 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 170 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get (insn) == 1 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X4U_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 171 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 172) + return OPCODE_AE_S8X4UX2_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 173) + return OPCODE_AE_S8X4UX2_XP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 174 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X4UX2_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 174 && + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S8X4UX2_IP; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 175 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_S8X4U_I; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 175 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_S8X4U_X; + if (Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get (insn) == 175 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_S8X4U_XP; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 40) + return OPCODE_AE_TRUNCA16X4F32S; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 41) + return OPCODE_AE_TRUNCA16X4F64S; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 42) + return OPCODE_AE_TRUNCA32F64S_L; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 43) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 44) + return OPCODE_AE_TRUNCI32F64S_L; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 45) + return OPCODE_AE_TRUNCI32X2F64S; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 46) + return OPCODE_AE_SEL16I; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_SAT16X4; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_ROUND16X4F32SSYM; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_ROUND16X4F32SASYM; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_SATU16X4; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_SAT8X4X32_L; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 80 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_SATU8X4X32_L; + if (Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get (insn) == 81 && + Field_fld_ae8_slot0_8_0_Slot_ae8_slot0_get (insn) == 128) + return OPCODE_AE_MOV; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_LAV16X4X2_XP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_LAV8X8X2_XP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 16) + return OPCODE_AE_SAV16X4X2_XP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 17) + return OPCODE_AE_SAV8X8X2_XP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 18) + return OPCODE_L32R; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 19) + return OPCODE_AE_TRUNCI16X4F32S; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_SA16X4X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_SA16X4X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_SA16X4X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 39 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_SA16X4X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_SA8X8X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_SA8X8X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_SA8X8X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_SA8X8X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 40 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 243) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 244) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 245) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 240) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 241) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 242) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 246) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 247) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get (insn) == 248) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 3 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 8) + return OPCODE_AE_SA32X2_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 9) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 12) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 10) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 11) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 5) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 13) + return OPCODE_AE_SA8X8_IC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_SA8X8_IC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 5 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 15) + return OPCODE_AE_SA8X8_IC2; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 3) + return OPCODE_AE_SA8X8_RIP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIC; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 6 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_RIC1; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_17_8_Slot_ae8_slot0_get (insn) == 14) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get (insn) == 42 && + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get (insn) == 4 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 7) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae8_slot0_31_21_Slot_ae8_slot0_get (insn) == 6) + return OPCODE_AE_TRUNCI16X4F64S; + if (Field_fld_ae8_slot0_31_22_Slot_ae8_slot0_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae8_slot0_31_23_Slot_ae8_slot0_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae8_slot0_31_7_Slot_ae8_slot0_get (insn) == 348594 && + Field_fld_ae8_slot0_6_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174288 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_CALLX0; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174290 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_JX; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174291 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_RET; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174293 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_SSA8B; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174294 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_SSA8L; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174295 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_SSL; + if (Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get (insn) == 174296 && + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get (insn) == 1) + return OPCODE_SSR; + if (Field_fld_ae8_slot0_31_9_Slot_ae8_slot0_get (insn) == 87107 && + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get (insn) == 4) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae8_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5386) + return OPCODE_AND; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5387) + return OPCODE_MINU; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5388) + return OPCODE_MOVNEZ; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5389) + return OPCODE_SRC; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5390) + return OPCODE_SUBX8; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5391) + return OPCODE_SRLI; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5450) + return OPCODE_MAX; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5451) + return OPCODE_MOVEQZ; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5452) + return OPCODE_OR; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5453) + return OPCODE_SUB; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5454) + return OPCODE_XOR; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5455 && + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5455 && + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5455 && + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5455 && + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5512) + return OPCODE_ADD; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5513) + return OPCODE_ADDX4; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5514) + return OPCODE_MAXU; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5515) + return OPCODE_MOVGEZ; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5516) + return OPCODE_SALT; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5517) + return OPCODE_SUBX2; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5518) + return OPCODE_CLAMPS; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5522 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SLL; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5576) + return OPCODE_ADDX2; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5577) + return OPCODE_ADDX8; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5578) + return OPCODE_MIN; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5579) + return OPCODE_MOVLTZ; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5580) + return OPCODE_SALTU; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5581) + return OPCODE_SUBX4; + if (Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get (insn) == 5582) + return OPCODE_SEXT; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2450) + return OPCODE_AE_L16M_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2451) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2452) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2453) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2454) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2455) + return OPCODE_AE_L16_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2456) + return OPCODE_AE_L32M_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2457) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2458) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2459) + return OPCODE_AE_L32_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2460) + return OPCODE_AE_L32_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2461) + return OPCODE_AE_L64_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2462) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2463) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2482) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2483) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2484) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2485) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2486) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2487) + return OPCODE_AE_L16_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2488) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2489) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2490) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2491) + return OPCODE_AE_L32_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2492) + return OPCODE_AE_L64_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2493) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2494) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2495) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2514) + return OPCODE_AE_L16M_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2515) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2516) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2517) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2518) + return OPCODE_AE_L16_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2519) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2520) + return OPCODE_AE_L32M_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2521) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2522) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2523) + return OPCODE_AE_L32_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2524) + return OPCODE_AE_L64_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2525) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2526) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2527) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2546) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2547) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2548) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2549) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2550) + return OPCODE_AE_L16_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2551) + return OPCODE_AE_L16_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2552) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2553) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2554) + return OPCODE_AE_L32_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2555) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2556) + return OPCODE_AE_L64_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2557) + return OPCODE_AE_L64_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2558) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2559) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2688) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2689) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2690) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2691) + return OPCODE_AE_L8_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2692) + return OPCODE_SLLI; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2696 && + Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2697 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2720) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2721) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2722) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2723) + return OPCODE_AE_L8_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2724) + return OPCODE_SRAI; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2728 && + Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2729 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2752) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2753) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2754) + return OPCODE_AE_L8_I; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2755) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2760 && + Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2784) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2785) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2786) + return OPCODE_AE_L8_IP; + if (Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get (insn) == 2787) + return OPCODE_AE_L8_XP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 48) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 49) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 50) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 51) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 52) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 53) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 54) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 55) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 56) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 57) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 58) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 59) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 60) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 61) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 62) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 63) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 64) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 65) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 66) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 67) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 68) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 69) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 70) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 71) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 72) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 73) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 74) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get (insn) == 75) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_15_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 5) + return OPCODE_L16UI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 4) + return OPCODE_L16SI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 6) + return OPCODE_L32I; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 7) + return OPCODE_L8UI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 19 && + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get (insn) == 8) + return OPCODE_MOVI; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 7) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 10) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 20 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 6) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 6) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 7) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 321 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 8) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 9) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 10) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 11) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 14) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 12) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 8 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 13) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 9) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 10) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 14) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 12) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 13) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get (insn) == 320) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 6) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get (insn) == 21 && + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get (insn) == 9 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 7) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae8_slot1_29_22_Slot_ae8_slot1_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae8_slot1_29_23_Slot_ae8_slot1_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae8_slot1_29_5_Slot_ae8_slot1_get (insn) == 715056 && + Field_fld_ae8_slot1_4_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_NOP; + if (Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get (insn) == 89378 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SSA8B; + if (Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get (insn) == 89379 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SSA8L; + if (Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get (insn) == 89380 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SSL; + if (Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get (insn) == 89381 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SSR; + if (Field_fld_ae8_slot1_29_9_Slot_ae8_slot1_get (insn) == 44688 && + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get (insn) == 15) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae9_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (insn) == 40364 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_ALL4; + if (Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (insn) == 40364 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_ANY4; + if (Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (insn) == 40365 && + Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_get (insn) == 18) + return OPCODE_SSAI; + if (Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (insn) == 40365 && + Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_ALL8; + if (Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get (insn) == 40365 && + Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_ANY8; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10064) + return OPCODE_ADD; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10065) + return OPCODE_ADDX2; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10066) + return OPCODE_ADDX4; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10067) + return OPCODE_ADDX8; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10068) + return OPCODE_AND; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10069) + return OPCODE_MAX; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10070) + return OPCODE_MAXU; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10071) + return OPCODE_MIN; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10072) + return OPCODE_MINU; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10073) + return OPCODE_MOVEQZ; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10074) + return OPCODE_MOVGEZ; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10075) + return OPCODE_MOVLTZ; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10076) + return OPCODE_MOVNEZ; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10077) + return OPCODE_OR; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10078) + return OPCODE_SALT; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10079) + return OPCODE_SALTU; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10080) + return OPCODE_SRC; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10081) + return OPCODE_SUB; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10082) + return OPCODE_SUBX2; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10083) + return OPCODE_SUBX4; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10084) + return OPCODE_SUBX8; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10085) + return OPCODE_XOR; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10086) + return OPCODE_MOVF; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10087) + return OPCODE_MOVT; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10088) + return OPCODE_CLAMPS; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10089) + return OPCODE_SEXT; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10090) + return OPCODE_SRLI; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10091 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_SRA; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10091 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_SRL; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10112 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_SLL; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10694 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_ABS; + if (Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get (insn) == 10695 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4864) + return OPCODE_AE_L16M_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4865) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4866) + return OPCODE_AE_L16M_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4867) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4868) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4869) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4870) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4871) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4872) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4873) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4874) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4875) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4876) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4877) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4878) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4879) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4880) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4881) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4882) + return OPCODE_AE_L16_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4883) + return OPCODE_AE_L16_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4884) + return OPCODE_AE_L16_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4885) + return OPCODE_AE_L16_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4886) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4887) + return OPCODE_AE_L16_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4888) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4889) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4890) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4891) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4892) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4893) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4894) + return OPCODE_AE_L32M_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4895) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4896) + return OPCODE_AE_L32M_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4897) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4898) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4899) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4900) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4901) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4902) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4903) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4904) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4905) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4906) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4907) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4908) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4909) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4910) + return OPCODE_AE_L32_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4911) + return OPCODE_AE_L32_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4912) + return OPCODE_AE_L32_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4913) + return OPCODE_AE_L32_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4914) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4915) + return OPCODE_AE_L32_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4916) + return OPCODE_AE_L64_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4917) + return OPCODE_AE_L64_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4918) + return OPCODE_AE_L64_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4919) + return OPCODE_AE_L64_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4920) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4921) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4922) + return OPCODE_AE_L64_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4923) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4924) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4925) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4926) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4927) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4928) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4929) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4930) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4931) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4932) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4933) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4934) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4935) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4936) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4937) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4938) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4939) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4940) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4941) + return OPCODE_AE_L8_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4942) + return OPCODE_AE_L8_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4943) + return OPCODE_AE_L8_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4944) + return OPCODE_AE_L8_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4945) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4946) + return OPCODE_AE_L8_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4947) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4948) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4949) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4950) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4951) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4952) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4953) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4954) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4955) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4956) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4957) + return OPCODE_AE_S16X2M_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4958) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4959) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4960) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4961) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4962) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4963) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4964) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4965) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4966) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4967) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4968) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4969) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4970) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4971) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4972) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4973) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4974) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4975) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4976) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4977) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4978) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4979) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4980) + return OPCODE_AE_S32M_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4981) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4982) + return OPCODE_AE_S32M_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4983) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4984) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4985) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4986) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4987) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4988) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4989) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4990) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4991) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4992) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4993) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4994) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4995) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4996) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4997) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4998) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 4999) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5000) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5001) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5002) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5003) + return OPCODE_AE_S32_H_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5004) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5005) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5006) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5007) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5008) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5009) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5010) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5011) + return OPCODE_AE_S64_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5012) + return OPCODE_AE_S64_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5013) + return OPCODE_AE_S64_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5014) + return OPCODE_AE_S64_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5015) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5016) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5017) + return OPCODE_AE_S64_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5018) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5019) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5020) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5021) + return OPCODE_AE_S8X8_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5022) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5023) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5024) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5025) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5026) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5027) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5028) + return OPCODE_AE_S8_0_XC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5029) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5030) + return OPCODE_SLLI; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5031) + return OPCODE_SRAI; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5046 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5046 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5047 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5047 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5048 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5049 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5050 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5051 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5052 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5053 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5054 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5055 && + Field_fld_ae9_slot0_7_6_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5055 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5055 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5055 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5055 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5064) + return OPCODE_AE_S8X4U_I; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5065) + return OPCODE_AE_S8X4U_X; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5066) + return OPCODE_AE_S8X4U_XP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5067 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_S8X4U_IP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5250 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5251 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5282 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5283 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5314 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5315 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get (insn) == 5346 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 566) + return OPCODE_ADDI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 567) + return OPCODE_ADDMI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 568) + return OPCODE_L16SI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 569) + return OPCODE_L16UI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 570) + return OPCODE_L32I; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 571) + return OPCODE_L8UI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 572) + return OPCODE_S16I; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 573) + return OPCODE_S32I; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 574) + return OPCODE_S8I; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 575) + return OPCODE_MOVI; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 632 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 632 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get (insn) == 632 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae9_slot0_27_17_Slot_ae9_slot0_get (insn) == 282) + return OPCODE_EXTUI; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 74) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 75) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 76) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 77) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 78) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 79) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 80) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 81) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 82) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 83) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 84) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 85) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 86) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 87) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 88) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 89) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 90) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 91) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 92) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 93) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 94) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 95) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 96) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 97) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 98) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 99) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 100) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 101) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 102) + return OPCODE_AE_S16X4X2RNG_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 103) + return OPCODE_AE_S16X4X2RNG_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 104) + return OPCODE_AE_S16X4X2RNG_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 105) + return OPCODE_AE_S16X4X2RNG_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 106) + return OPCODE_AE_S16X4X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 107) + return OPCODE_AE_S16X4X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 108) + return OPCODE_AE_S16X4X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 109) + return OPCODE_AE_S16X4X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 110) + return OPCODE_AE_S16X4X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 111) + return OPCODE_AE_S16X4X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 112) + return OPCODE_AE_S16X4X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 113) + return OPCODE_AE_S32X2X2RNG_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 114) + return OPCODE_AE_S32X2X2RNG_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 115) + return OPCODE_AE_S32X2X2RNG_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 116) + return OPCODE_AE_S32X2X2RNG_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 117) + return OPCODE_AE_S32X2X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 118) + return OPCODE_AE_S32X2X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 119) + return OPCODE_AE_S32X2X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 120) + return OPCODE_AE_S32X2X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 121) + return OPCODE_AE_S32X2X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 122) + return OPCODE_AE_S32X2X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 123) + return OPCODE_AE_S32X2X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 124) + return OPCODE_AE_S64X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 125) + return OPCODE_AE_S64X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 126) + return OPCODE_AE_S64X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 127) + return OPCODE_AE_S64X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 128) + return OPCODE_AE_S64X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 129) + return OPCODE_AE_S64X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 130) + return OPCODE_AE_S64X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 131) + return OPCODE_AE_S8X8X2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 132) + return OPCODE_AE_S8X8X2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 133) + return OPCODE_AE_S8X8X2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 134) + return OPCODE_AE_S8X8X2_XC; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 135) + return OPCODE_AE_S8X8X2_XC1; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 136) + return OPCODE_AE_S8X8X2_XC2; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 137) + return OPCODE_AE_S8X8X2_XP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 138) + return OPCODE_J; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 139) + return OPCODE_CALL0; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 148 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_get (insn) == 15) + return OPCODE_AE_LE32; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 148 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_get (insn) == 7) + return OPCODE_AE_EQ32; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 148 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_LT64; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 148 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_get (insn) == 5) + return OPCODE_AE_LE64; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 148 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_AE_EQ64; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_get (insn) == 23) + return OPCODE_AE_MOV; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_get (insn) == 7) + return OPCODE_AE_LT16; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_get (insn) == 30) + return OPCODE_AE_LE16; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_get (insn) == 14) + return OPCODE_AE_EQ16; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_LT32; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 183) + return OPCODE_CVTSF16_L; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 181) + return OPCODE_CVTSF16_H; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 179) + return OPCODE_CVTF16S_L; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 177) + return OPCODE_CVTF16S_H; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 8 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_OLE_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 9 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_OLT_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 8 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_OEQ_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 11 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_UN_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 10 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_ULE_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 10 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_ULT_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 9 && + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_UEQ_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 185) + return OPCODE_FICEIL_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 187) + return OPCODE_FIFLOOR_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 189) + return OPCODE_FIRINT_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 191) + return OPCODE_FIROUND_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_get (insn) == 87) + return OPCODE_RMINNUM_H; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 149 && + Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_get (insn) == 55) + return OPCODE_RMAXNUM_H; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 150 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S8X4UX2_I; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 151 && + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_S8X4UX2_IP; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 159) + return OPCODE_AE_S8X4UX2_X; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 160 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 8) + return OPCODE_FITRUNC_S; + if (Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get (insn) == 704) + return OPCODE_AE_S8X4UX2_XP; + if (Field_fld_ae9_slot0_27_19_Slot_ae9_slot0_get (insn) == 36) + return OPCODE_AE_SEL16I; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 12) + return OPCODE_AE_LAV16X4X2_XP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 13) + return OPCODE_AE_LAV8X8X2_XP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 14) + return OPCODE_AE_SAV16X4X2_XP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 15) + return OPCODE_AE_SAV8X8X2_XP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 16) + return OPCODE_L32R; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 17) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 11) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 7) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 10) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 15) + return OPCODE_AE_SA16X4X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 12) + return OPCODE_AE_SA16X4X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 13) + return OPCODE_AE_SA16X4X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 36 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 14) + return OPCODE_AE_SA16X4X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 7) + return OPCODE_AE_SA8X8X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2X2_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_AE_SA8X8X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2X2_IC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 5) + return OPCODE_AE_SA8X8X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2X2_IC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_SA8X8X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 37 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2X2_IC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 40 && + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get (insn) == 2 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 40 && + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get (insn) == 3 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 579) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 580) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 581) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 576) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 577) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 578) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 582) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 583) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 584) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_AE_SALIGN128_I; + if (Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get (insn) == 48 && + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get (insn) == 585) + return OPCODE_AE_SA128POS_FP; + if (Field_fld_ae9_slot0_27_22_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_TRUNC_S; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get (insn) == 1 && + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get (insn) == 1) + return OPCODE_UTRUNC_S; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_TRUNC_SX2; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 6) + return OPCODE_UTRUNC_SX2; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_FLOAT_SX2; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 5 && + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get (insn) == 4) + return OPCODE_UFLOAT_SX2; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 6 && + Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 0) + return OPCODE_FLOAT_S; + if (Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get (insn) == 6 && + Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_get (insn) == 0 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 2) + return OPCODE_UFLOAT_S; + if (Field_fld_ae9_slot0_27_3_Slot_ae9_slot0_get (insn) == 5178144 && + Field_fld_ae9_slot0_2_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_NOP; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161808 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_CALLX0; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161810 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_JX; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161811 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_RET; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161813 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_SSA8B; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161814 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_SSA8L; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161815 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_SSL; + if (Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get (insn) == 161816 && + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get (insn) == 3) + return OPCODE_SSR; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae9_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5392) + return OPCODE_MAXU; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5393) + return OPCODE_MIN; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5394) + return OPCODE_SALT; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5395) + return OPCODE_SALTU; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5396) + return OPCODE_CLAMPS; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5397) + return OPCODE_SEXT; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5398 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 10) + return OPCODE_SLL; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5454) + return OPCODE_ADD; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5455) + return OPCODE_ADDX2; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5456) + return OPCODE_MINU; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5457) + return OPCODE_MOVEQZ; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5458) + return OPCODE_SRC; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5459) + return OPCODE_SUB; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5460) + return OPCODE_SRLI; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5461 && + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5461 && + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5461 && + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5461 && + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5518) + return OPCODE_ADDX4; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5519) + return OPCODE_ADDX8; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5520) + return OPCODE_MOVGEZ; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5521) + return OPCODE_MOVLTZ; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5522) + return OPCODE_SUBX2; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5523) + return OPCODE_SUBX4; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5582) + return OPCODE_AND; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5583) + return OPCODE_MAX; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5584) + return OPCODE_MOVNEZ; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5585) + return OPCODE_OR; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5586) + return OPCODE_SUBX8; + if (Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get (insn) == 5587) + return OPCODE_XOR; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2456) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2457) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2458) + return OPCODE_AE_L32M_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2459) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2460) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2461) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2462) + return OPCODE_AE_L32_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2463) + return OPCODE_AE_L64_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2480) + return OPCODE_AE_L16M_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2481) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2482) + return OPCODE_AE_L16M_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2483) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2484) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2485) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2486) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2487) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2488) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2489) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2490) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2491) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2492) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2493) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2494) + return OPCODE_AE_L32_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2495) + return OPCODE_AE_L64_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2512) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2513) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2514) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2515) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2516) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2517) + return OPCODE_AE_L16_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2518) + return OPCODE_AE_L16_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2519) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2520) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2521) + return OPCODE_AE_L32M_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2522) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2523) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2524) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2525) + return OPCODE_AE_L32_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2526) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2527) + return OPCODE_AE_L64_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2544) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2545) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2546) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2547) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2548) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2549) + return OPCODE_AE_L16_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2550) + return OPCODE_AE_L16_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2551) + return OPCODE_AE_L16_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2552) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2553) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2554) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2555) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2556) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2557) + return OPCODE_AE_L32_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2558) + return OPCODE_AE_L32_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2559) + return OPCODE_AE_L64_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2688) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2689) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2690) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2691) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2692) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2693) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2694) + return OPCODE_AE_L8_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2695) + return OPCODE_SRAI; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2699 && + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2720) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2721) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2722) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2723) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2724) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2725) + return OPCODE_AE_L8_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2726) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2731 && + Field_fld_ae9_slot1_3_2_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2731 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 4) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2731 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 5) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2731 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 6) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2731 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 7) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2752) + return OPCODE_AE_L64_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2753) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2754) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2755) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2756) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2757) + return OPCODE_AE_L8_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2758) + return OPCODE_AE_L8_XP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2762 && + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2762 && + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2784) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2785) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2786) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2787) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2788) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2789) + return OPCODE_AE_L8_X; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2790) + return OPCODE_SLLI; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2794 && + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get (insn) == 2794 && + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 306) + return OPCODE_MOVI; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 308) + return OPCODE_ADDI; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 309) + return OPCODE_ADDMI; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 312) + return OPCODE_L16SI; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 313) + return OPCODE_L32I; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 316) + return OPCODE_L16UI; + if (Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get (insn) == 317) + return OPCODE_L8UI; + if (Field_fld_ae9_slot1_26_17_Slot_ae9_slot1_get (insn) == 152) + return OPCODE_EXTUI; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 48) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 49) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 50) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 51) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 52) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 53) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 54) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 55) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 56) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 57) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 58) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 59) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 60) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 61) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 62) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 63) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 64) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 65) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 66) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 67) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 68) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 69) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 70) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 71) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 72) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 73) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 74) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get (insn) == 75) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae9_slot1_26_2_Slot_ae9_slot1_get (insn) == 5659202 && + Field_fld_ae9_slot1_1_0_Slot_ae9_slot1_get (insn) == 3) + return OPCODE_NOP; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 7) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 10) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 20 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 6) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 355 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 356 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 357 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 352 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 353 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 354 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 358 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 359 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 360 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get (insn) == 384) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_get (insn) == 11 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 8) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get (insn) == 21 && + Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_get (insn) == 11 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 9) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae9_slot1_26_22_Slot_ae9_slot1_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae9_slot1_26_23_Slot_ae9_slot1_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get (insn) == 86377 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_SSL; + if (Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get (insn) == 87401 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_SSR; + if (Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get (insn) == 87402 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_SSA8B; + if (Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get (insn) == 87403 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_SSA8L; + if (Field_fld_ae9_slot1_26_9_Slot_ae9_slot1_get (insn) == 43189 && + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get (insn) == 11) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116372 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116373 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116380 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116381 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ALL4; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116381 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ANY4; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116381 && + Field_fld_ae_slot0_8_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_ALL8; + if (Field_fld_ae_slot0_28_10_Slot_ae_slot0_get (insn) == 116381 && + Field_fld_ae_slot0_8_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_ANY8; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28835 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28835 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28835 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28835 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LB; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28837 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28839 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 48) + return OPCODE_RUR_FCR; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28839 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 112) + return OPCODE_RUR_FSR; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28839 && + Field_fld_ae_slot0_5_0_Slot_ae_slot0_get (insn) == 16) + return OPCODE_AE_MOVAB4; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 28839 && + Field_fld_ae_slot0_4_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVAB2; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 29091 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_SRL; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 29091 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAB; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 29091 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVBA; + if (Field_fld_ae_slot0_28_12_Slot_ae_slot0_get (insn) == 29091 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LBI; + if (Field_fld_ae_slot0_28_14_Slot_ae_slot0_get (insn) == 10904 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_SSAI; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3612 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 56) + return OPCODE_SLL; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1080) + return OPCODE_CALLX0; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1208) + return OPCODE_JX; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1272) + return OPCODE_RET; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1400) + return OPCODE_SSA8B; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1464) + return OPCODE_SSA8L; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1528) + return OPCODE_SSL; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1592) + return OPCODE_SSR; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 3644 && + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get (insn) == 1656) + return OPCODE_AE_MOVASAR; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4871 && + Field_fld_ae_slot0_12_10_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4871 && + Field_fld_ae_slot0_12_10_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4871 && + Field_fld_ae_slot0_12_10_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4900 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_SUBX8; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4900 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AND; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4900 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ANDBC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4900 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_CLAMPS; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4900 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ADDX4; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SRLI; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ORBC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_MOVF; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MAXU; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4901 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_DB; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4908 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_XOR; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4908 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ORB; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4908 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MAX; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4908 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SEXT; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ADDX8; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_ANDB; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_XORB; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_MOVT; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MIN; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4909 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVSARA7X2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4910 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_MOVGEZ; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4910 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_MINU; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4911 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_MOVEQZ; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4911 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_MOVLTZ; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4942 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_MOVNEZ; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4942 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SRC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4943 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADD; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4943 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SUB; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4943 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_OR; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4974 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SUBX2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4974 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_SALT; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4975 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADDX2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4975 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_SUBX4; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4975 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_SALTU; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA24X2POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA24X2NEG_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2NEG_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4992 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA24POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA24NEG_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA16X4POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_LA16X4NEG_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA8X8POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA8X8NEG_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA8X8NEG_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 4993 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_DBI; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5380 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5388 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5412 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5420 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5444 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5476 && + Field_fld_ae_slot0_12_0_Slot_ae_slot0_get (insn) == 69) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae_slot0_28_15_Slot_ae_slot0_get (insn) == 5476 && + Field_fld_ae_slot0_12_6_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_MOVALIGN; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 1802 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 1806 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 1818 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 1822 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2106 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2110 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2362 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2366 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2434 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16M_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2438 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S8_0_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S8_0_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8_0_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2439 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8_0_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2442 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32M_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2446 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2450 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2450 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2450 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2450 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S8X8_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2454 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SRAI; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L64_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8_0_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2455 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2466 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16M_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2470 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2471 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2471 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2471 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2471 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S64_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2474 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32M_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32M_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32M_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2478 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2482 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8X4U_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2482 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S8X4U_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2482 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8X4U_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2482 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S8X4U_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2487 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2496 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2618 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2622 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2708 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2712 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2712 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2712 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2712 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2716 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2716 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2716 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2716 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L8_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2740 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32_H_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32_H_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2744 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32_H_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32_H_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32_H_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32_H_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2748 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2874 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2878 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L64_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2968 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 2972 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L64_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S8X8_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S8X8_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S64_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3000 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8X8_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S8_0_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S64_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3004 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S8X8_XC2; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3130 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3134 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_I; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3386 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_IP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3390 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_X; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3642 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_XC; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3646 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3898 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32_XP; + if (Field_fld_ae_slot0_28_16_Slot_ae_slot0_get (insn) == 3902 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L64_X; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_NEG32; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ABS32; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_NEG24S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ABS24S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_NEG32S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_ABS32S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_NEG16S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_ABS16S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ABS16; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_NEG64; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_ABS64; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_NEG64S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_ABS64S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_DIV64D32_H; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_ABS8; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ABS8S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_NEG8S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae_slot0_28_17_Slot_ae_slot0_get (insn) == 917 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 192 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_EQ64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 193 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_CVTF16S_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 193 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_CVTF16S_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 194 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LE64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 195 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_CVTSF16_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 195 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_CVTSF16_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 196 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LT64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 197 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FICEIL_S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 197 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FIFLOOR_S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 199 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FIRINT_S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 199 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FIROUND_S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_MAX32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_MAX16; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADD64S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_ADD8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 225 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADD8S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_ROUND24X2F48SASYM; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_MIN32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MIN16; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MAX64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MIN64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MAX8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_MIN8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 227 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_MOVNEG32S_T; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 228 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0) + return OPCODE_J; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_ROUND32X2F64SASYM; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ROUND24X2F48SSYM; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SUB32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SUB16; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SUB24S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SUB32S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_SUB16S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 229 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SUB64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 230 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0) + return OPCODE_CALL0; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 230 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0) + return OPCODE_L32I; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 230 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1) + return OPCODE_L8UI; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 230 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0) + return OPCODE_S16I; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 230 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1) + return OPCODE_S32I; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SUB64S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SUB8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SUB8S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_LE8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LT8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_EQ8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_RNG32X4; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 231 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FITRUNC_S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 273 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADD16; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 273 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADD16S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 275 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADD32; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 275 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADD24S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 277 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADD32S; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 277 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 279 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 279 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADD64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 280 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_9_Slot_ae_slot0_get (insn) == 9 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 1) + return OPCODE_TRUNC16_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 280 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_9_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 1) + return OPCODE_UTRUNC16_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_SLLI; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCA32Q48; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCA16P24S_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCA16P24S_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSA64; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSAZ16_0; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 306 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_RFR; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 310 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 310 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_LOOPGTZ; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 310 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 8) + return OPCODE_LOOPNEZ; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32F24S_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32F24S_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 312 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVAD8; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 337 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 608 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 339 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0) + return OPCODE_S8I; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 370 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ADDI; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 370 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADDMI; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 374 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1) + return OPCODE_L16UI; + if (Field_fld_ae_slot0_28_19_Slot_ae_slot0_get (insn) == 374 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0) + return OPCODE_L16SI; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0) + return OPCODE_L32R; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_10_Slot_ae_slot0_get (insn) == 172 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_SA32X2_IC2; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IC2; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_IC2; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SA8X8_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA8X8_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_SA32X2F24_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_SA32X2F24_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_SA24_L_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_SA24_L_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SA24X2_IC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SA24X2_RIC1; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 32) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 24) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_12_Slot_ae_slot0_get (insn) == 161 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 16) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_10_Slot_ae_slot0_get (insn) == 164 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SALIGN128_I; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 40) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get (insn) == 48) + return OPCODE_WFR; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 77 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVDA32X2; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 77 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 77 && + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 84 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 576 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 84 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 608 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SA128POS_FP; + if (Field_fld_ae_slot0_28_21_Slot_ae_slot0_get (insn) == 85 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 608 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LT16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LE16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_EQ16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LT32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LE32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_EQ32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OLE_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OLT_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OEQ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UN_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ULE_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ULT_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UEQ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OEQ_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OLE_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OLT_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UEQ_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ULE_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ULT_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UN_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SEL16I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 52 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 52 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVT64; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVF64; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_13_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_AND; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_13_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_NAND; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_13_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_OR; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_13_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_XOR; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 53 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_BMAX32X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_BMIN32X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVADEXT_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVADEXT_L; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADDC32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_ADDC32U; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVT_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVF_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S32X2X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S32X2X2RNG_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2X2RNG_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S32X2X2RNG_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2X2RNG_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S16X4X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X4X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X4X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S16X4X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X4X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X4X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S16X4X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X4X2RNG_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S16X4X2RNG_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X4X2RNG_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S16X4X2RNG_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 32 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 33 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 33 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S32X2X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8X8X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S8X8X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8X4UX2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S8X4UX2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16X4RA32S_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8X2_IC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4X2_IC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2X2_IC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA8X8X2_IC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4X2_IC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2X2_IC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA8X8X2_IC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4X2_IC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2X2_IC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_BMAX16X4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_BMIN16X4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SUBC32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 34 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SUBC32U; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 36 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 37 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 37 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 0) + return OPCODE_MOVI; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S32X2X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S8X8X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_1_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8X4UX2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_1_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S8X4UX2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8X8X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S24RA64S_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOV; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCQ32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_PKSR32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_PKSR16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_MOVEQZ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 12) + return OPCODE_MOVNEZ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_MOVGEZ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 8) + return OPCODE_MOVLTZ_S; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 40 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 41 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 41 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16) + return OPCODE_EXTUI; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S32X2X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVBA1X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_19_8_Slot_ae_slot0_get (insn) == 1568 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVBA4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_18_8_Slot_ae_slot0_get (insn) == 544 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVBA2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 576 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVBD1X4; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 42 && + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get (insn) == 512 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVBD1X2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 44 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 45 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDW16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 45 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDW32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 46 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 46 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S64X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 48 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 49 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADDW8; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 49 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADDW8U; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 50 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S64X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 50 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 52 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 53 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SUBW16; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 53 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SUBW32; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 54 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 54 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S64X2_XC2; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 56 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 57 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SUBW8; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 57 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SUBW8U; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 58 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S8X8X2_I; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 58 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S64X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 60 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 61 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SAV8X8X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 61 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SAV16X4X2_XP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 62 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S8X8X2_IP; + if (Field_fld_ae_slot0_28_22_Slot_ae_slot0_get (insn) == 62 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S8X8X2_X; + if (Field_fld_ae_slot0_28_24_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVT8X16_H; + if (Field_fld_ae_slot0_28_24_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_MOVT8X16_L; + if (Field_fld_ae_slot0_28_24_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae_slot0_28_26_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVT16X8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 392 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 384 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 392 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_LA16X4_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 387 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 395 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 386 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 394 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 386 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 387 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 395 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 384 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 392 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 384 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LA24_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 384 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 392 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA24_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_LA24X2_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 385 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 393 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_LA24X2_RIC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_TRUNCA32F64S_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRA64_32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 36 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 36 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_SRLI24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 36 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SRAI24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_SRLS24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SRAS24; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAI16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAI16R; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 44 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_SRLI32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SRAI32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 44 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SRAI32R; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_SRLS32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SRAS32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAA32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLA32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA32; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI16S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAA16S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA16S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA16RS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 38 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI24S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 26 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 46 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAA32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA32RS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLASQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_SRLSQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 30 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SRASQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAAQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLAQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAAQ56; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SLAI64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLI64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAI64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_SRLS64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SRAS64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAA64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLA64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAA64; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLAISQ56S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLASSQ56S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAASQ56S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SLAI64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAS64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAA64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 386 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get (insn) == 394 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRAI8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRAI8R; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLI8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAI8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAI8S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAA8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLA8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAA8S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAA8RS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAA8S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLI16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAI16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAA16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRLA16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAI16SYM; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA16SYMS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 46 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SRAI32SYM; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA32SYMS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAV16RS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAV32RS; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTI32X4F8_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTI32X4F8_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTI32X4F8S_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTI32X4F8S_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32X4F8_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_CVTA32X4F8_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTA32X4F8S_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTA32X4F8S_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTI32X4F8U_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTI32X4F8U_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTI32X4F8US_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTI32X4F8US_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTA32X4F8U_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTA32X4F8U_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32X4F8US_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_CVTA32X4F8US_L; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTI32X4F16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTI32X4F16S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTA32X4F16; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTA32X4F16S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTI32X4F16U; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTI32X4F16US; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32X4F16U; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_CVTA32X4F16US; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTI16X4X2F8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTI16X4X2F8S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTA16X4X2F8; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_CVTA16X4X2F8S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTI16X4X2F8U; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_CVTI16X4X2F8US; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA16X4X2F8U; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_CVTA16X4X2F8US; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_MOVDEXT; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_NSA16X4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSAZ32X4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSA32X4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_TRUNCI16X4F32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCI16X4F64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_TRUNCA16X4F32S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCA16X4F64S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LAV8X8X2_XP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LAV16X4X2_XP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_TRUNC_S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 2) + return OPCODE_UTRUNC_S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_TRUNC_SX2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_UTRUNC_SX2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_17_Slot_ae_slot0_get (insn) == 96 && + Field_fld_ae_slot0_9_4_Slot_ae_slot0_get (insn) == 16) + return OPCODE_FLOAT_S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_17_Slot_ae_slot0_get (insn) == 96 && + Field_fld_ae_slot0_9_4_Slot_ae_slot0_get (insn) == 20) + return OPCODE_UFLOAT_S; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FLOAT_SX2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_UFLOAT_SX2; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_FICEIL_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_FIFLOOR_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_FIRINT_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 11) + return OPCODE_FIROUND_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_FITRUNC_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_17_Slot_ae_slot0_get (insn) == 96 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_3_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FLOAT16_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_17_Slot_ae_slot0_get (insn) == 96 && + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_7_3_Slot_ae_slot0_get (insn) == 8) + return OPCODE_UFLOAT16_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_12_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FLOAT16_HX4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UFLOAT16_HX4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_12_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_TRUNC16_HX4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_14_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_UTRUNC16_HX4; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_RMINNUM_H; + if (Field_fld_ae_slot0_28_27_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 12) + return OPCODE_RMAXNUM_H; + if (Field_fld_ae_slot0_28_4_Slot_ae_slot0_get (insn) == 11214853 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_NOP; + if (Field_fld_ae_slot0_28_8_Slot_ae_slot0_get (insn) == 697920 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_WUR_FCR; + if (Field_fld_ae_slot0_28_8_Slot_ae_slot0_get (insn) == 697952 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_WUR_FSR; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot1_25_1_Slot_ae_slot1_get (insn) == 10858630 && + Field_fld_ae_slot1_0_0_Slot_ae_slot1_get (insn) == 0) + return OPCODE_NOP; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5390) + return OPCODE_MAXU; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5391) + return OPCODE_MIN; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5392) + return OPCODE_SALT; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5393) + return OPCODE_SALTU; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5394) + return OPCODE_CLAMPS; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5395) + return OPCODE_SEXT; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5409 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5409 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5409 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5409 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SRL; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5409 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_LB; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5452) + return OPCODE_ADD; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5453) + return OPCODE_ADDX2; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5454) + return OPCODE_MINU; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5455) + return OPCODE_MOVEQZ; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5456) + return OPCODE_SRC; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5457) + return OPCODE_SUB; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5458) + return OPCODE_SRLI; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5459) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5516) + return OPCODE_ADDX4; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5517) + return OPCODE_ADDX8; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5518) + return OPCODE_MOVGEZ; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5519) + return OPCODE_MOVLTZ; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5520) + return OPCODE_SUBX2; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5521) + return OPCODE_SUBX4; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5526 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SLL; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5527 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5580) + return OPCODE_AND; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5581) + return OPCODE_MAX; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5582) + return OPCODE_MOVNEZ; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5583) + return OPCODE_OR; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5584) + return OPCODE_SUBX8; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5585) + return OPCODE_XOR; + if (Field_fld_ae_slot1_25_12_Slot_ae_slot1_get (insn) == 5590 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_LBI; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2456) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2457) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2458) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2459) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2460) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2461) + return OPCODE_AE_L32_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2462) + return OPCODE_AE_L32_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2463) + return OPCODE_AE_L64_XC2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2480) + return OPCODE_AE_L16M_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2481) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2482) + return OPCODE_AE_L16M_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2483) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2484) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2485) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2486) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2487) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2488) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2489) + return OPCODE_AE_L32M_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2490) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2491) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2492) + return OPCODE_AE_L32X2_XC2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2493) + return OPCODE_AE_L32_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2494) + return OPCODE_AE_L64_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2495) + return OPCODE_AE_L64_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2512) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2513) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2514) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2515) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2516) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2517) + return OPCODE_AE_L16_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2518) + return OPCODE_AE_L16_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2519) + return OPCODE_AE_L16_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2520) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2521) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2522) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2523) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2524) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2525) + return OPCODE_AE_L32_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2526) + return OPCODE_AE_L64_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2527) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2544) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2545) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2546) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2547) + return OPCODE_AE_L16X4_XC2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2548) + return OPCODE_AE_L16_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2549) + return OPCODE_AE_L16_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2550) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2551) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2552) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2553) + return OPCODE_AE_L32M_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2554) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2555) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2556) + return OPCODE_AE_L32_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2557) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2558) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2559) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2688) + return OPCODE_AE_L8X4F_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2689) + return OPCODE_AE_L8X4S_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2690) + return OPCODE_AE_L8X4U_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2691) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2692) + return OPCODE_AE_L8_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2693) + return OPCODE_AE_L8_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2694) + return OPCODE_SRAI; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2698 && + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2699 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2699 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2699 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2720) + return OPCODE_AE_L8X4F_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2721) + return OPCODE_AE_L8X4S_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2722) + return OPCODE_AE_L8X4U_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2723) + return OPCODE_AE_L8X8_XC2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2724) + return OPCODE_AE_L8_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2725) + return OPCODE_AE_MOVDA32X2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2730 && + Field_fld_ae_slot1_3_2_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2730 && + Field_fld_ae_slot1_3_2_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2731 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2731 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2731 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MOVDA8; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2752) + return OPCODE_AE_L8X4S_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2753) + return OPCODE_AE_L8X4U_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2754) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2755) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2756) + return OPCODE_AE_L8_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2757) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2761 && + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2761 && + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2763 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2763 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2784) + return OPCODE_AE_L8X4S_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2785) + return OPCODE_AE_L8X4U_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2786) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2787) + return OPCODE_AE_L8_I; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2788) + return OPCODE_AE_L8_XC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2789) + return OPCODE_SLLI; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2793 && + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2793 && + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2795 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae_slot1_25_13_Slot_ae_slot1_get (insn) == 2795 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 306) + return OPCODE_MOVI; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 308) + return OPCODE_ADDI; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 309) + return OPCODE_ADDMI; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 312) + return OPCODE_L16SI; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 313) + return OPCODE_L32I; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 316) + return OPCODE_L16UI; + if (Field_fld_ae_slot1_25_16_Slot_ae_slot1_get (insn) == 317) + return OPCODE_L8UI; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 152) + return OPCODE_EXTUI; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 160 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 13) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 160 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 14) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 160 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 160 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 15) + return OPCODE_AE_L64_I; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 162 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 13) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 162 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_L64_IP; + if (Field_fld_ae_slot1_25_17_Slot_ae_slot1_get (insn) == 169 && + Field_fld_ae_slot1_12_8_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 48) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 49) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 50) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 51) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 52) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 53) + return OPCODE_AE_L16X4X2_XC2; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 54) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 55) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 56) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 57) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 58) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 59) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 60) + return OPCODE_AE_L32X2X2_XC2; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 61) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 62) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 63) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 64) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 65) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 66) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 67) + return OPCODE_AE_L64X2_XC2; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 68) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 69) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 70) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 71) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 72) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 73) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 74) + return OPCODE_AE_L8X8X2_XC2; + if (Field_fld_ae_slot1_25_18_Slot_ae_slot1_get (insn) == 75) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 737 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 641 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 673 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 705 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 545 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 577 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 609 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 769 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 801 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 833 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA8X8X2POS_PC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_17_Slot_ae_slot1_get (insn) == 1 && + Field_fld_ae_slot1_12_8_Slot_ae_slot1_get (insn) == 0 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get (insn) == 513 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA128_PP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 11) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 7) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 8) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 9) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 10) + return OPCODE_AE_LA8X8X2_IC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 20 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_LA32X2X2_IC2; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 13) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 8) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 9) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 11 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 11 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 10) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 11) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 14) + return OPCODE_AE_LA8X4S_IP; + if (Field_fld_ae_slot1_25_20_Slot_ae_slot1_get (insn) == 21 && + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get (insn) == 10 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 15) + return OPCODE_AE_LA8X4U_IP; + if (Field_fld_ae_slot1_25_22_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_LAVUNSQZ8X8_XP; + if (Field_fld_ae_slot1_25_23_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_LAVUNSQZ16X4_XP; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 82785 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_SSL; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 83809 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 12) + return OPCODE_SSR; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 86576) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 86577) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 86578) + return OPCODE_AE_ADDCIRC_XC2; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 86579) + return OPCODE_AE_MOVSARA7X2; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 89458 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SSA8B; + if (Field_fld_ae_slot1_25_8_Slot_ae_slot1_get (insn) == 89459 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SSA8L; + if (Field_fld_ae_slot1_25_9_Slot_ae_slot1_get (insn) == 44728 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_get (insn) == 2560) + return OPCODE_OR; + if (Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_get (insn) == 2561) + return OPCODE_XOR; + if (Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_get (insn) == 2562) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 288 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 289 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16_I; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 290 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 291 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16_X; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 292 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16_XC; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 293 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L16_XP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 294 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 295 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 296 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 297 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32_I; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 298 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 299 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32_X; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 300 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32_XC; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 301 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32_XP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 302 && + Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_get (insn) == 7) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 302 && + Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_get (insn) == 6) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 303 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 12) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 303 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 13) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 303 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 14) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 303 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 15) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 321 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 321 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 321 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 321 && + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get (insn) == 321 && + Field_fld_ae6_slot1_9_5_Slot_ae6_slot1_get (insn) == 8) + return OPCODE_AE_MOV; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 2) + return OPCODE_AE_TRUNCI16X4F32S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 4 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_CVTA16X4X2F8; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 4 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_CVTA16X4X2F8S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 5 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_CVTI16X4X2F8; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 5 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_CVTA16X4X2F8U; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 6 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_CVTI16X4X2F8S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 6 && + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_CVTI16X4X2F8U; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 7 && + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_TRUNCA16X4F32S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 7 && + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_TRUNCA16X4F64S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 8 && + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 8 && + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_TRUNCI32X2F64S; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 9 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 9 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get (insn) == 9 && + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get (insn) == 2) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae6_slot1_27_21_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_TRUNCI16X4F64S; + if (Field_fld_ae6_slot1_27_3_Slot_ae6_slot1_get (insn) == 1315112 && + Field_fld_ae6_slot1_2_0_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_NOP; + if (Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_get (insn) == 164357) + return OPCODE_AE_LA128_PP; + if (Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_get (insn) == 164373) + return OPCODE_AE_LA64_PP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae10_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae10_slot2_34_10_Slot_ae10_slot2_get (insn) == 28442624 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 101) + return OPCODE_NOP; + if (Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get (insn) == 1968640) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get (insn) == 1968641) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get (insn) == 1968642 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 17) + return OPCODE_CONST_S; + if (Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get (insn) == 1968642 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 16) + return OPCODE_CONST_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 15) + return OPCODE_AE_MOV; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 8) + return OPCODE_NEXP01_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 4) + return OPCODE_MKSADJ_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_DIV0_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 11) + return OPCODE_SQRT0_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 9) + return OPCODE_RECIP0_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 10) + return OPCODE_RSQRT0_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_ABS_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 7) + return OPCODE_NEG_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_CONJC_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 6) + return OPCODE_MULJC_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 12) + return OPCODE_ABS_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 13) + return OPCODE_CLSFY_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_CONJC_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 5) + return OPCODE_MULJC_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984321 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 14) + return OPCODE_NEG_H; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984322 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_CLSFY_S; + if (Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get (insn) == 984322 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24640 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MAX_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24640 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MAXNUM_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24641 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MIN_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24641 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MINNUM_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24704 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_FREXP_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 24704 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 25728 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MAX_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 25728 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MAXNUM_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 26752 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_DIVN_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 26752 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MINNUM_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 26752 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MADDN_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 98) + return OPCODE_MKDADJ_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 97) + return OPCODE_ADDEXP_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 96) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MIN_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 100) + return OPCODE_ADDEXP_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 27776 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 99) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 28800 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MADD_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 29824 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MSUBN_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30752) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30753) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30754) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30755) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30756) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30757) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30758) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30759) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 30848 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MSUB_S; + if (Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get (insn) == 31872 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MUL_S; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_ADD_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 161) + return OPCODE_SUB_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 129) + return OPCODE_MUL_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 33) + return OPCODE_MADD_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 97) + return OPCODE_MSUB_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 770 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 65) + return OPCODE_MSUBN_H; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 833) + return OPCODE_MADDQ_S; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 865) + return OPCODE_MSUBQ_S; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 897) + return OPCODE_MULQ_S; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 929) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get (insn) == 993 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_MADDA_S; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 10) + return OPCODE_MADD_SX2X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 11) + return OPCODE_MSUB_SX2X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 12) + return OPCODE_MUL_SX2X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 13) + return OPCODE_ADD_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 14) + return OPCODE_MADD_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 15) + return OPCODE_MSUB_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 16) + return OPCODE_MUL_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 17) + return OPCODE_SUB_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 18) + return OPCODE_ADD_SX2X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 19) + return OPCODE_SUB_SX2X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 5) + return OPCODE_MULQ_H; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_MADDQ_H; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 3) + return OPCODE_MULCNVH_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MULACNVH_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 4) + return OPCODE_MULCNVL_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 20 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_MULACNVL_HX4X2; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 21 && + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (insn) == 0 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 34) + return OPCODE_ADD_S; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 21 && + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (insn) == 0 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 66) + return OPCODE_SUB_S; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 21 && + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (insn) == 0 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 21 && + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (insn) == 0 && + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get (insn) == 21 && + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get (insn) == 0 && + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get (insn) == 2) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_get (insn) == 4) + return OPCODE_MULMUX_SX2X2; + if (Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_get (insn) == 12 && + Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_get (insn) == 128 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MULMUX_S; + if (Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_get (insn) == 12 && + Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_get (insn) == 1) + return OPCODE_MULMUXQ_S; + if (Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_MADDMUX_SX2X2; + if (Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_get (insn) == 3 && + Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_get (insn) == 128 && + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_get (insn) == 3 && + Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_get (insn) == 0) + return OPCODE_MADDMUXQ_S; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae10_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae10_slot3_34_10_Slot_ae10_slot3_get (insn) == 23102864 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 18) + return OPCODE_NOP; + if (Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get (insn) == 1443864) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get (insn) == 1443865) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get (insn) == 1443928 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 19) + return OPCODE_CONST_S; + if (Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get (insn) == 1443928 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 18) + return OPCODE_CONST_H; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 17) + return OPCODE_AE_MOV; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 4) + return OPCODE_NEXP01_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 3) + return OPCODE_MKSADJ_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_DIV0_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 7) + return OPCODE_SQRT0_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 5) + return OPCODE_RECIP0_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 6) + return OPCODE_RSQRT0_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 8) + return OPCODE_ABS_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 13) + return OPCODE_NEG_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 10) + return OPCODE_CONJC_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 12) + return OPCODE_MULJC_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_CLSFY_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 2) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 14) + return OPCODE_ABS_H; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 15) + return OPCODE_CLSFY_H; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 9) + return OPCODE_CONJC_H; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 11) + return OPCODE_MULJC_H; + if (Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get (insn) == 721964 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 16) + return OPCODE_NEG_H; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 18496 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_DIVN_S; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 19520 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MADDN_S; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 20544 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MADD_S; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 21568 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MSUBN_S; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 22592 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MSUB_S; + if (Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get (insn) == 23616 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MUL_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 577) + return OPCODE_MADDQ_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 609) + return OPCODE_MSUBQ_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 641) + return OPCODE_MULQ_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 673) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_4_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_AE_SEL16I; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 27) + return OPCODE_MIN_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 25) + return OPCODE_MAX_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 26) + return OPCODE_MINNUM_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 25) + return OPCODE_MAXNUM_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 9) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 8) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 24) + return OPCODE_FREXP_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 26) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 24) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_BMAXNUM_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get (insn) == 2) + return OPCODE_BMINNUM_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_BMAXNUMABS_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get (insn) == 2) + return OPCODE_BMINNUMABS_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 7) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 3) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 5) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 29) + return OPCODE_MIN_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 10 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 28) + return OPCODE_MAX_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 28) + return OPCODE_MINNUM_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 11 && + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get (insn) == 27) + return OPCODE_MAXNUM_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 6) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 2) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 705 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 4) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 5) + return OPCODE_ADD_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 6) + return OPCODE_SUB_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 226) + return OPCODE_MKDADJ_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 225) + return OPCODE_ADDEXP_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 224) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 4) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_MADDA_S; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 228) + return OPCODE_ADDEXP_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get (insn) == 0 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 227) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 64) + return OPCODE_ADD_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 98) + return OPCODE_SUB_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 66) + return OPCODE_MUL_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 96) + return OPCODE_MADD_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 97) + return OPCODE_MSUB_H; + if (Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get (insn) == 737 && + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get (insn) == 65) + return OPCODE_MSUBN_H; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 10) + return OPCODE_MADD_SX2X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 11) + return OPCODE_MSUB_SX2X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 12) + return OPCODE_MUL_SX2X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 13) + return OPCODE_MADD_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 14) + return OPCODE_MSUB_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 15) + return OPCODE_MUL_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 5) + return OPCODE_MULQ_H; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_MADDQ_H; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 3) + return OPCODE_MULCNVH_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MULACNVH_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 4) + return OPCODE_MULCNVL_HX4X2; + if (Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get (insn) == 24 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 2) + return OPCODE_MULACNVL_HX4X2; + if (Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_get (insn) == 4) + return OPCODE_MULMUX_SX2X2; + if (Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_get (insn) == 8 && + Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_get (insn) == 64 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MULMUX_S; + if (Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_get (insn) == 8 && + Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_get (insn) == 1) + return OPCODE_MULMUXQ_S; + if (Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_MADDMUX_SX2X2; + if (Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_get (insn) == 2 && + Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_get (insn) == 64 && + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_get (insn) == 2 && + Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_get (insn) == 0) + return OPCODE_MADDMUXQ_S; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae2_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12292 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_ADD_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12420 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_DIVN_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12548 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MADDN_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12676 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MADD_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12684 && + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_PKSR24; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12684 && + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get (insn) == 0 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_PKSR16; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12685 && + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get (insn) == 0 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_PKSR32; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12685 && + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 131) + return OPCODE_AE_RADD8X8_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 227) + return OPCODE_AE_RADDA8X8_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 163) + return OPCODE_AE_RADD8X8_L; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 99) + return OPCODE_AE_RADD16X4; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 195) + return OPCODE_AE_RADDA16X4; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 67) + return OPCODE_MKDADJ_S; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 35) + return OPCODE_ADDEXP_S; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12686 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_0_Slot_ae2_slot2_get (insn) == 232448) + return OPCODE_NOP; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 67) + return OPCODE_AE_RMAX8X8; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 131) + return OPCODE_AE_RMIN8X8; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 35) + return OPCODE_AE_RMAX16X4; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 99) + return OPCODE_AE_RMIN16X4; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_RADDA8X8_L; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 195) + return OPCODE_ADDEXP_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12687 && + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get (insn) == 163) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12804 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MSUB_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 12932 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MUL_H; + if (Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get (insn) == 13060 && + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_SUB_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3072) + return OPCODE_AE_MULAFC32RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3074 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3074 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP16S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3074 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAA2D16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3075 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3075 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3075 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MSUBN_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3104) + return OPCODE_AE_MULFC32RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3106 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3106 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3106 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3107 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3107 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3107 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MSUB_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3136) + return OPCODE_MADDA_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3138 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3138 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3138 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP16X16X4S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3139 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3139 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3139 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_MUL_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULA32U_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 27) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 26) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 25) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 30) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 23) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 31) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 24) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 22) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 20) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 21) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 19) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 16) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULA32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 17) + return OPCODE_AE_MULAAD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 18) + return OPCODE_AE_MULAAD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULAA2D16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULAA2D16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 28) + return OPCODE_AE_MULAAFD16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3168 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 29) + return OPCODE_AE_MULAAFD16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3170 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3170 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3170 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3171 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFC16RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3171 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 18) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULF32RA_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32RA_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 22) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 17) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 29) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 23) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 28) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 21) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 27) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 20) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 24) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 16) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULFP32X2TS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULC32X16_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULC16S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 19) + return OPCODE_AE_MULS32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3200 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULFCJ32RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3202 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3202 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3202 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3203 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3203 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULC16JS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 18) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULF32RA_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 22) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 24) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 17) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 29) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 23) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 28) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 21) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 27) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 20) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 16) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULC16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 19) + return OPCODE_AE_MULS32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULASD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULCJ32; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULP16S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3232 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULFP16X4RS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3234 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3234 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3234 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3235 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3235 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULC16JS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 24) + return OPCODE_AE_MULSF32RA_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 19) + return OPCODE_AE_MULS32U_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 17) + return OPCODE_AE_MULS16S_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 29) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 23) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 28) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 21) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 27) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 20) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 16) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULC32; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULFC16RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 18) + return OPCODE_AE_MULS32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 22) + return OPCODE_AE_MULSAD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULASD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3264 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3266 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC16JS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3266 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3266 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP32X2T; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3267 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3267 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 17) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULF32RA_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 24) + return OPCODE_AE_MULSF32RA_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 21) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 28) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 27) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 20) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 19) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 23) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 29) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 16) + return OPCODE_AE_MULP32X2T; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X2TS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULC32X16_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 18) + return OPCODE_AE_MULS32S_HL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 22) + return OPCODE_AE_MULSAD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULFCJ16RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULC16S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3296 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULP16X16X4S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3298 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC16JS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3298 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3298 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3299 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3299 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3330 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3330 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3330 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC16S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3331 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3331 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFCJ16RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3362 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3362 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC16S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3362 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSS2D16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3363 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3363 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFCJ32RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3394 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3394 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3394 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSS2D16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3395 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL16S_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3395 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3395 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSS2D16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3426 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3426 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3426 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC32; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3427 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3427 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3427 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSS2D16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3458 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3458 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3458 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC32X16_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3459 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3459 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3459 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3490 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3490 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAC32X16_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3490 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3491 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3491 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32S_HL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3491 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3522 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3522 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULACJ32; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3522 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3523 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3523 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3523 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3554 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3554 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3554 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3555 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3555 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3555 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3586 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32RA_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3586 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3586 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3587 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32U_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3587 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3587 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3618 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32RA_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3618 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3618 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3619 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3619 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3619 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3650 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32RA_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3650 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3650 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3651 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3651 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3651 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3682 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3682 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3682 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3683 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3683 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3683 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3714 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3714 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3714 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3715 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3715 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3715 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X2TS; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3746 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3746 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3746 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3747 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3747 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP16S_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3747 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3778 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3778 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3778 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3779 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3779 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3779 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3810 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3810 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3810 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3811 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3811 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3811 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP16X16X4S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3842 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3842 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3842 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD16SS_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3843 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3843 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3843 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3874 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3874 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3874 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3875 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3875 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3875 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3906 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3906 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3906 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3907 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3907 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3907 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3938 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3938 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3938 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3939 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3939 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3939 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAP32X2T; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3970 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3970 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3970 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3971 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA16S_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3971 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 3971 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4002 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4002 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4002 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4003 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4003 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4003 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_DIVN_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4034 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4034 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4034 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4035 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4035 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA32S_HH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4035 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_MADDN_S; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4066 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4066 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4066 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZAA2D16SS_HH_LL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4067 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4067 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA32S_HL; + if (Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get (insn) == 4067 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_MADD_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 64 && + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_BMAXNUMABS_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 65 && + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_BMAXNUM_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 66 && + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_BMINNUMABS_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 67 && + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get (insn) == 1 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_BMINNUM_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 68 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 320) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 68 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 256) + return OPCODE_FREXP_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 68 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 288) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 69 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 320) + return OPCODE_ADD_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 69 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 288) + return OPCODE_MINNUM_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 69 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 256) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 70 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 320) + return OPCODE_SUB_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 70 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 288) + return OPCODE_MIN_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 70 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 256) + return OPCODE_MAXNUM_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 71 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 288) + return OPCODE_AE_SORT16X4; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 71 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 256) + return OPCODE_MAX_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 71 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 320 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_CLSFY_S; + if (Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get (insn) == 71 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 320 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae2_slot2_42_26_Slot_ae2_slot2_get (insn) == 52 && + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_MULMUX_S; + if (Field_fld_ae2_slot2_42_28_Slot_ae2_slot2_get (insn) == 12 && + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_ADD_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_SUB_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_get (insn) == 67745) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 15430 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MOV; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_get (insn) == 67744) + return OPCODE_AE_ABS16S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_DSEL8X8; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 2118 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_NEXP01_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 1094 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_MKSADJ_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 70 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_DIV0_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 5190 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_SQRT0_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 3142 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_RECIP0_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 4166 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_RSQRT0_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 6214 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_ABS_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 11334 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_NEG_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 8262 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_CONJC_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 10310 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_MULJC_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_get (insn) == 32909 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_CONST_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 100) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 68) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 96) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 99) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 97) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 98) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_get (insn) == 141 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 12358 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_ABS_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 13382 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_CLSFY_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 7238 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_CONJC_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_get (insn) == 32908 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_CONST_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 1125) + return OPCODE_MIN_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 101) + return OPCODE_MAX_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 1093) + return OPCODE_MINNUM_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 69) + return OPCODE_MAXNUM_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 9286 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_MULJC_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get (insn) == 14406 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_NEG_H; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 64) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 67) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 65) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_get (insn) == 140 && + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get (insn) == 66) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MIN32; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MAX32; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MIN16; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MAX16; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MAX8; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MIN8; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 33) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 32) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get (insn) == 34 && + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get (insn) == 3 && + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 2 && + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_SEL8X8I; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot2_23_0_Slot_ae4_slot2_get (insn) == 5668865) + return OPCODE_NOP; + if (Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get (insn) == 1368) + return OPCODE_AE_PKSR16; + if (Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get (insn) == 1369) + return OPCODE_AE_PKSR24; + if (Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get (insn) == 1370) + return OPCODE_AE_PKSR32; + if (Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get (insn) == 1371) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 164) + return OPCODE_AE_MAX16; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 165) + return OPCODE_AE_MAX32; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 166) + return OPCODE_AE_MAX8; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 167) + return OPCODE_AE_MIN16; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 168) + return OPCODE_AE_MIN32; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 169) + return OPCODE_AE_MIN8; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 170) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 172 && + Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_get (insn) == 1) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 172 && + Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_get (insn) == 0) + return OPCODE_AE_ABS16S; + if (Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get (insn) == 173 && + Field_fld_ae4_slot2_4_0_Slot_ae4_slot2_get (insn) == 0) + return OPCODE_AE_MOV; + if (Field_fld_ae4_slot2_23_17_Slot_ae4_slot2_get (insn) == 40) + return OPCODE_AE_SEL16I_N; + if (Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (insn) == 1) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (insn) == 2) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (insn) == 3) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get (insn) == 4) + return OPCODE_AE_ADDANDSUBRNG32_L; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot3_27_20_Slot_ae4_slot3_get (insn) == 96 && + Field_fld_ae4_slot3_14_10_Slot_ae4_slot3_get (insn) == 0) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 0) + return OPCODE_AE_MULFPC32X16X2RAS; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 1) + return OPCODE_AE_MULFPCJ32X16X2RAS; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 22 && + Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_get (insn) == 161) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 1) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 2) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 3) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 4) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_19_Slot_ae4_slot3_get (insn) == 0 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_SEL16I; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_5_Slot_ae4_slot3_get (insn) == 23557) + return OPCODE_AE_MOV; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 22 && + Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_get (insn) == 160) + return OPCODE_AE_ABS16S; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 20 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MIN32; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 17 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MAX32; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 19 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MIN16; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 16 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MAX16; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 18 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MAX8; + if (Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get (insn) == 2 && + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get (insn) == 21 && + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get (insn) == 5) + return OPCODE_AE_MIN8; + if (Field_fld_ae4_slot3_27_3_Slot_ae4_slot3_get (insn) == 8482964 && + Field_fld_ae4_slot3_2_0_Slot_ae4_slot3_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot4_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot4_22_0_Slot_ae4_slot4_get (insn) == 5308480) + return OPCODE_NOP; + if (Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get (insn) == 160) + return OPCODE_AE_MAX16; + if (Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get (insn) == 161) + return OPCODE_AE_MIN16; + if (Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get (insn) == 162 && + Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_get (insn) == 1) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get (insn) == 162 && + Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_get (insn) == 0) + return OPCODE_AE_ABS16S; + if (Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (insn) == 1) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (insn) == 2) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (insn) == 3) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get (insn) == 4) + return OPCODE_AE_ADDANDSUBRNG32_L; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae5_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae5_slot1_1_0_Slot_ae5_slot1_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae5_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae5_slot2_24_0_Slot_ae5_slot2_get (insn) == 24117778) + return OPCODE_NOP; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 752 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 753 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_ADDEXP_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 754 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_MKDADJ_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 755 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 756 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_ADDEXP_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 768) + return OPCODE_FREXP_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 769) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 770) + return OPCODE_MAXNUM_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 771) + return OPCODE_MAX_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 772) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 773) + return OPCODE_MINNUM_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 774) + return OPCODE_MIN_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 775) + return OPCODE_ADD_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 776) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 777) + return OPCODE_ADD_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 778) + return OPCODE_MADD_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 779) + return OPCODE_MSUB_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 780) + return OPCODE_MUL_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 781) + return OPCODE_SUB_H; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 782) + return OPCODE_SUB_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 783 && + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_CLSFY_S; + if (Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get (insn) == 783 && + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get (insn) == 184 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_PKSR16; + if (Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get (insn) == 185 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_PKSR24; + if (Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get (insn) == 186 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_PKSR32; + if (Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get (insn) == 187 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MUL16X4; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MUL16X4S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULAFC32RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULFC32RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_SEL8X8I; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_7_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_SEL16I_N; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MUL32U_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULA32U_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MUL16S_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULA16S_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MUL32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULA32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MUL32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULA32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MUL32S_HL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULA32S_HL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MUL32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 13 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULA32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULAAD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULAAD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULAA2D16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULAA2D16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULAAFD16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 14 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULAAFD16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULAC32; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULAC32X16_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULAC32X16_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULAFCJ32RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULACJ32; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULAFCJ16RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 15 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULAC16S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULAFP32X2TS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULAP32X2T; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULASD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULASD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULAP16S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULAP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULC16S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 16 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULAP16X16X4S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULFP16X4S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULC32; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULC32X16_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULC32X16_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULFCJ32RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULCJ32; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULFCJ16RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 17 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULFP16X4RS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULS32U_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULS16S_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULFP32X2TS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULP32X2T; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULS32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULS32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULS32S_HL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULS32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULP16S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 18 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULP16X16X4S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULSAD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 19 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULSAD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULSFP32X2TS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULSP32X2T; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULSSD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULSSD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULSP16S_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULSP16S_L; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULSP16X16X4S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULSS2D16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULSS2D16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 20 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULSSFD16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULZAAD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULZASD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULZAAD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULZAA2D16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULZAA2D16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULZAAFD16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULZAAFD16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 21 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULSSFD16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MULZSAD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULZSSD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULZASD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MULZSAD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULZSSD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULZSS2D16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULZSS2D16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULZSSFD16SS_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 22 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULZSSFD16SS_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_14_5_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 527) + return OPCODE_AE_MOV; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_MUL_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_MADD_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_MSUB_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_MSUBN_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_MADDN_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 514) + return OPCODE_NEXP01_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 513) + return OPCODE_MKSADJ_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 512) + return OPCODE_DIV0_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 517) + return OPCODE_SQRT0_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 515) + return OPCODE_RECIP0_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 516) + return OPCODE_RSQRT0_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_DIVN_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 518) + return OPCODE_ABS_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 523) + return OPCODE_NEG_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 520) + return OPCODE_CONJC_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 522) + return OPCODE_MULJC_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get (insn) == 0 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 529) + return OPCODE_CONST_S; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 524) + return OPCODE_ABS_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 525) + return OPCODE_CLSFY_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 519) + return OPCODE_CONJC_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get (insn) == 0 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 528) + return OPCODE_CONST_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_MIN_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_MAX_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_MINNUM_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_MAXNUM_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 521) + return OPCODE_MULJC_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 23 && + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get (insn) == 526) + return OPCODE_NEG_H; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 25 && + Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 25 && + Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 25 && + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get (insn) == 1 && + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get (insn) == 25 && + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get (insn) == 1 && + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_CONST_HX4X2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19688) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19689) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19690) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19691) + return OPCODE_AE_MOV; + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19692) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get (insn) == 19693) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2452) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2453) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2454 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2454 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2455 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_PKSR24; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2455 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_PKSR16; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2460 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_PKSR32; + if (Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get (insn) == 2460 && + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_get (insn) == 1224) + return OPCODE_AE_MOVF64; + if (Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_get (insn) == 1225) + return OPCODE_AE_MOVT64; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 608 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_LE64; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 608 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_EQ64; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 609 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 2) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 609 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 609 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 609 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 610 && + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (insn) == 1 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 610 && + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_I; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 610 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_LT64; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 611 && + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 611 && + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 611 && + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get (insn) == 1 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 611 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 3 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 611 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 2 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_IP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 614 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 2) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 614 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 3) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 614 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S16X4RNG_X; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 614 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S16X4RNG_XP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 624 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 624 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 2 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get (insn) == 624 && + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get (insn) == 1 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 60) + return OPCODE_AE_ADDC32; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 61) + return OPCODE_AE_ADDC32U; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 62) + return OPCODE_AE_BMAX32X2; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 63) + return OPCODE_AE_BMIN32X2; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 64) + return OPCODE_AE_SUBC32; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 65) + return OPCODE_AE_SUBC32U; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 66) + return OPCODE_AE_S16X4X2_I; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 67) + return OPCODE_AE_S16X4X2_IP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 68) + return OPCODE_AE_S16X4X2_X; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 69) + return OPCODE_AE_S16X4X2_XP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 70) + return OPCODE_AE_S32X2X2_I; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 71) + return OPCODE_AE_S32X2X2_IP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 72) + return OPCODE_AE_S32X2X2_X; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 73) + return OPCODE_AE_S32X2X2_XP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 74 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_BMAX8X8_L; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 74 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_BMAX16X4; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 75 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_BMIN8X8_L; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 75 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_BMIN16X4; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_7_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_L_IP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 20) + return OPCODE_AE_LT16; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 1 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 19) + return OPCODE_AE_LE16; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get (insn) == 0 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 19) + return OPCODE_AE_EQ16; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 18) + return OPCODE_AE_LT32; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 17) + return OPCODE_AE_LE32; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 77 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 16) + return OPCODE_AE_EQ32; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 79) + return OPCODE_AE_S8X4UX2_X; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 2104) + return OPCODE_AE_S8X4UX2_XP; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 2105 && + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S8X4UX2_I; + if (Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get (insn) == 2106 && + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S8X4UX2_IP; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 2) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 3) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 4) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 5) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 6) + return OPCODE_AE_ADDW16; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 7) + return OPCODE_AE_ADDW32; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 8) + return OPCODE_AE_ADDW8; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 9) + return OPCODE_AE_ADDW8U; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 10) + return OPCODE_AE_SUBW16; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 11) + return OPCODE_AE_SUBW32; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 12) + return OPCODE_AE_SUBW8; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 13) + return OPCODE_AE_SUBW8U; + if (Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get (insn) == 14) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae6_slot0_29_5_Slot_ae6_slot0_get (insn) == 630208 && + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot2_24_0_Slot_ae6_slot2_get (insn) == 1245280) + return OPCODE_NOP; + if (Field_fld_ae6_slot2_24_10_Slot_ae6_slot2_get (insn) == 1170) + return OPCODE_AE_MOV; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 70) + return OPCODE_AE_MOVF64; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 71) + return OPCODE_AE_MOVT64; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 72 && + Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_get (insn) == 1) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 72 && + Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 73 && + Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_get (insn) == 1) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get (insn) == 73 && + Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 32) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 33) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 34) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 37 && + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get (insn) == 2) + return OPCODE_AE_PKSR32; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 37 && + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get (insn) == 1) + return OPCODE_AE_PKSR24; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 37 && + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get (insn) == 3) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 37 && + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_PKSR16; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 38 && + Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_get (insn) == 2) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 38 && + Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get (insn) == 38 && + Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_get (insn) == 1) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae6_slot2_24_20_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_MOVDX2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot3_37_13_Slot_ae6_slot3_get (insn) == 1179648 && + Field_fld_ae6_slot3_12_0_Slot_ae6_slot3_get (insn) == 33) + return OPCODE_NOP; + if (Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_get (insn) == 274432 && + Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_get (insn) == 274433 && + Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8192) + return OPCODE_AE_ACCW16; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8224) + return OPCODE_AE_ACCW32; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8256) + return OPCODE_AE_ACCW8; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8288) + return OPCODE_AE_ACCW8U; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8320) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8352) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8384) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8416) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8448) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8480) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 2 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_BMAX8X8_H; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 3 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_BMAX8X8_L; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 2 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_BMAX16X4; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 3 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_BMIN16X4; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_BMAX32X2; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8512 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_BMIN32X2; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 9) + return OPCODE_AE_ADD32S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 12) + return OPCODE_AE_SUB32S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 8) + return OPCODE_AE_ADD16S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 11) + return OPCODE_AE_SUB16S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 451) + return OPCODE_AE_NEG32S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 480) + return OPCODE_AE_ABS32S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 482) + return OPCODE_AE_NEG16S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 448) + return OPCODE_AE_ABS16S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 449) + return OPCODE_AE_ABS8S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 483) + return OPCODE_AE_NEG8S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 10) + return OPCODE_AE_ADD8S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get (insn) == 13) + return OPCODE_AE_SUB8S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 0 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_BMIN8X8_H; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get (insn) == 0 && + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_BMIN8X8_L; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 481) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get (insn) == 8544 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 450) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_MULZAAF2D32RA_HH_LL; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_MULZAAF2D32RA_HL_LH; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 2) + return OPCODE_AE_MULZASF2D32RA_HH_LL; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 3) + return OPCODE_AE_MULZASF2D32RA_HL_LH; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 4) + return OPCODE_AE_MULZSAF2D32RA_HH_LL; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 5) + return OPCODE_AE_MULZSAF2D32RA_HL_LH; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 6) + return OPCODE_AE_MULZSSF2D32RA_HH_LL; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 7) + return OPCODE_AE_MULZSSF2D32RA_HL_LH; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 9 && + Field_fld_ae6_slot3_24_20_Slot_ae6_slot3_get (insn) == 0 && + Field_fld_ae6_slot3_14_0_Slot_ae6_slot3_get (insn) == 32) + return OPCODE_AE_MOV; + if (Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get (insn) == 9 && + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_MOVDX2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot0_23_0_Slot_ae7_slot0_get (insn) == 6889856) + return OPCODE_NOP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 864) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 865) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 866) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 867) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 868) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 869) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 870) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 871) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 872) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 873) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 874) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 875) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 876) + return OPCODE_AE_L64_X; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 877) + return OPCODE_AE_L64_XC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 878) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 879) + return OPCODE_AE_L64_XP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 880) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 881) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 882) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 883) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 884 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 884 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 885 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 885 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 885 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 886 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 886 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 886 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 887 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 887 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 887 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 888 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 888 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 888 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 889 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 889 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 889 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 890 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 890 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 890 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 8) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 9) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 10) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 11) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 891 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 892 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 892 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 893 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 893 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 894 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 894 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 895 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get (insn) == 895 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 52 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 52 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 6) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 52 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 4) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 52 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 7) + return OPCODE_AE_L64_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 52 && + Field_fld_ae7_slot0_12_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 53 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 5) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get (insn) == 53 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 4) + return OPCODE_AE_L64_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 4) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 5) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 6) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 7) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 8) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 9) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 10) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 11) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 12) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 13) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 14) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 15) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 16) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 17) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 18) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 19) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 20) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 21) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 22) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 23) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 24 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 24 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 24 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 24 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 25 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 25 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 25 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 25 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get (insn) == 26 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 106502) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 106630) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 106758) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 106886) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 107014) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 107142) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 107270) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 107398) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get (insn) == 107526) + return OPCODE_AE_LA8X8X2POS_PC2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot1_23_0_Slot_ae7_slot1_get (insn) == 6889856) + return OPCODE_NOP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 864) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 865) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 866) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 867) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 868) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 869) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 870) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 871) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 872) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 873) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 874) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 875) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 876) + return OPCODE_AE_L64_X; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 877) + return OPCODE_AE_L64_XC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 878) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 879) + return OPCODE_AE_L64_XP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 880) + return OPCODE_AE_L8X8_X; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 881) + return OPCODE_AE_L8X8_XC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 882) + return OPCODE_AE_L8X8_XC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 883) + return OPCODE_AE_L8X8_XP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 884 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 884 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_L8X8_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 885 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 885 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 885 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 886 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 886 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 886 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 887 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 887 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 887 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 888 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 888 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 888 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 889 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 889 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 889 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 890 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 890 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8_RIP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 890 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 8) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 9) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 10) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 11) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 891 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 892 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 892 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 893 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA8X8_IC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 893 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 894 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA8X8_IC1; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 894 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 895 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get (insn) == 895 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA8X8_IP; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 52 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 5) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 52 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 6) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 52 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 4) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 52 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 7) + return OPCODE_AE_L64_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 52 && + Field_fld_ae7_slot1_12_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LALIGN128_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 53 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 5) + return OPCODE_AE_L8X8_I; + if (Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get (insn) == 53 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 4) + return OPCODE_AE_L64_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L16X4X2_I; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_L16X4X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_L16X4X2_X; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_L16X4X2_XC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 4) + return OPCODE_AE_L16X4X2_XC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 5) + return OPCODE_AE_L16X4X2_XP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 6) + return OPCODE_AE_L32X2X2_I; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 7) + return OPCODE_AE_L32X2X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 8) + return OPCODE_AE_L32X2X2_X; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 9) + return OPCODE_AE_L32X2X2_XC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 10) + return OPCODE_AE_L32X2X2_XC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 11) + return OPCODE_AE_L32X2X2_XP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 12) + return OPCODE_AE_L64X2_I; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 13) + return OPCODE_AE_L64X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 14) + return OPCODE_AE_L64X2_X; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 15) + return OPCODE_AE_L64X2_XC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 16) + return OPCODE_AE_L64X2_XC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 17) + return OPCODE_AE_L64X2_XP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 18) + return OPCODE_AE_L8X8X2_I; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 19) + return OPCODE_AE_L8X8X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 20) + return OPCODE_AE_L8X8X2_X; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 21) + return OPCODE_AE_L8X8X2_XC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 22) + return OPCODE_AE_L8X8X2_XC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 23) + return OPCODE_AE_L8X8X2_XP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 24 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA16X4X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 24 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4X2_IC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 24 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2X2_IC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 24 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4X2_IC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 25 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2X2_IP; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 25 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_LA8X8X2_IC; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 25 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_LA8X8X2_IC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 25 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2X2_IC1; + if (Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get (insn) == 26 && + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_LA8X8X2_IP; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 106502) + return OPCODE_AE_LA16X4X2POS_PC; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 106630) + return OPCODE_AE_LA16X4X2POS_PC1; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 106758) + return OPCODE_AE_LA16X4X2POS_PC2; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 106886) + return OPCODE_AE_LA32X2X2POS_PC; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 107014) + return OPCODE_AE_LA32X2X2POS_PC1; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 107142) + return OPCODE_AE_LA32X2X2POS_PC2; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 107270) + return OPCODE_AE_LA8X8X2POS_PC; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 107398) + return OPCODE_AE_LA8X8X2POS_PC1; + if (Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get (insn) == 107526) + return OPCODE_AE_LA8X8X2POS_PC2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot2_36_12_Slot_ae7_slot2_get (insn) == 14772992 && + Field_fld_ae7_slot2_11_0_Slot_ae7_slot2_get (insn) == 1376) + return OPCODE_NOP; + if (Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_get (insn) == 1846592) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_get (insn) == 1846593) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57696) + return OPCODE_AE_MULAAAA2Q8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57697) + return OPCODE_AE_MULADDF32RAS; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57698) + return OPCODE_AE_MULADDF32RS; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57699) + return OPCODE_AE_MULSUBF32RAS; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57700) + return OPCODE_AE_MULSUBF32RS; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57701) + return OPCODE_AE_MULZAAAA2Q8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57702) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57703) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57704) + return OPCODE_AE_SEL8X8I; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 0) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 2) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 3) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 4) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 5) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57705 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 6) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 42) + return OPCODE_AE_MOV; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 39) + return OPCODE_AE_RMAX8X8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 41) + return OPCODE_AE_RMIN8X8; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 38) + return OPCODE_AE_RMAX16X4; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 40) + return OPCODE_AE_RMIN16X4; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_10_Slot_ae7_slot2_get (insn) == 0) + return OPCODE_AE_SORT16X4; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 33) + return OPCODE_AE_RADD8X8_H; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 36) + return OPCODE_AE_RADDA8X8_H; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 34) + return OPCODE_AE_RADD8X8_L; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 37) + return OPCODE_AE_RADDA8X8_L; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 32) + return OPCODE_AE_RADD16X4; + if (Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get (insn) == 57707 && + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get (insn) == 35) + return OPCODE_AE_RADDA16X4; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1760) + return OPCODE_AE_MULAAAA2Q16X8; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1761) + return OPCODE_AE_MULAF2P32X16X4RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1762) + return OPCODE_AE_MULAF2P32X16X4RS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1763) + return OPCODE_AE_MULAF2P32X16X4S; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1764) + return OPCODE_AE_MULAFD32X16X2_FIR_HH; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1765) + return OPCODE_AE_MULAFD32X16X2_FIR_HL; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1766) + return OPCODE_AE_MULAFD32X16X2_FIR_LH; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1767) + return OPCODE_AE_MULAFD32X16X2_FIR_LL; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1768) + return OPCODE_AE_MULAFD32X2RA_FIR_H; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1769) + return OPCODE_AE_MULAFD32X2RA_FIR_L; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1770) + return OPCODE_AE_MULAFD32X2S_FIR_H; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1771) + return OPCODE_AE_MULAFD32X2S_FIR_L; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1772) + return OPCODE_AE_MULAFPC32X16X2RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1773) + return OPCODE_AE_MULAFPCJ32X16X2RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1774) + return OPCODE_AE_MULAFQ16X2_FIR_0; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1775) + return OPCODE_AE_MULAFQ16X2_FIR_1; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1776) + return OPCODE_AE_MULAFQ16X2_FIR_2; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1777) + return OPCODE_AE_MULAFQ16X2_FIR_3; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1778) + return OPCODE_AE_MULAPC32X16X2; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1779) + return OPCODE_AE_MULF2P32X16X4RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1780) + return OPCODE_AE_MULF2P32X16X4RS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1781) + return OPCODE_AE_MULF2P32X16X4S; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1782) + return OPCODE_AE_MULFD32X16X2_FIR_HH; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1783) + return OPCODE_AE_MULFD32X16X2_FIR_HL; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1784) + return OPCODE_AE_MULFD32X16X2_FIR_LH; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1785) + return OPCODE_AE_MULFD32X16X2_FIR_LL; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1786) + return OPCODE_AE_MULFD32X2RA_FIR_H; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1787) + return OPCODE_AE_MULFD32X2RA_FIR_L; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1788) + return OPCODE_AE_MULFD32X2S_FIR_H; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1789) + return OPCODE_AE_MULFD32X2S_FIR_L; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1790) + return OPCODE_AE_MULFPC32X16X2RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1791) + return OPCODE_AE_MULFPCJ32X16X2RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1792) + return OPCODE_AE_MULFQ16X2_FIR_0; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1793) + return OPCODE_AE_MULFQ16X2_FIR_1; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1794) + return OPCODE_AE_MULFQ16X2_FIR_2; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1795) + return OPCODE_AE_MULFQ16X2_FIR_3; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1796) + return OPCODE_AE_MULPC32X16X2; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1797) + return OPCODE_AE_MULSF2P32X16X4RAS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1798) + return OPCODE_AE_MULSF2P32X16X4RS; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1799) + return OPCODE_AE_MULSF2P32X16X4S; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1800) + return OPCODE_AE_MULZAAAA2Q16X8; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1801) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1802) + return OPCODE_AE_DSEL8X8; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1824 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULAAAAFQ32X16; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1825 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULAAAAQ32X16; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1826 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULZAAAAFQ32X16; + if (Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get (insn) == 1827 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULZAAAAQ32X16; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 0) + return OPCODE_AE_MUL2P32X4; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MUL2P32X4S; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 2) + return OPCODE_AE_MUL2P32X4T; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 3) + return OPCODE_AE_MUL2Q32X16_FIR_H; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 4) + return OPCODE_AE_MUL2Q32X16_FIR_L; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 5) + return OPCODE_AE_MULA2P32X4; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 6) + return OPCODE_AE_MULA2P32X4T; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 7) + return OPCODE_AE_MULA2Q32X16_FIR_H; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 8) + return OPCODE_AE_MULA2Q32X16_FIR_L; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 9) + return OPCODE_AE_MULAAAA2Q16; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 10) + return OPCODE_AE_MULAAAA2Q32X16; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 11) + return OPCODE_AE_MULAAF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 12) + return OPCODE_AE_MULAAF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 13) + return OPCODE_AE_MULAAF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 14) + return OPCODE_AE_MULAAF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 15) + return OPCODE_AE_MULAF2P32X4RAS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 16) + return OPCODE_AE_MULAF2P32X4RS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 17) + return OPCODE_AE_MULASF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 18) + return OPCODE_AE_MULASF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 19) + return OPCODE_AE_MULASF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 20) + return OPCODE_AE_MULASF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 21) + return OPCODE_AE_MULF2D32X2WS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 22) + return OPCODE_AE_MULF2P32X4RAS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 23) + return OPCODE_AE_MULF2P32X4RS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 24) + return OPCODE_AE_MULFD16X16X4WS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 25) + return OPCODE_AE_MULS2P32X4; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 26) + return OPCODE_AE_MULS2P32X4T; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 27) + return OPCODE_AE_MULSAF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 28) + return OPCODE_AE_MULSAF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 29) + return OPCODE_AE_MULSAF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 30) + return OPCODE_AE_MULSAF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 31) + return OPCODE_AE_MULSF2P32X4RAS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 32) + return OPCODE_AE_MULSF2P32X4RS; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 33) + return OPCODE_AE_MULSSF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 34) + return OPCODE_AE_MULSSF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 35) + return OPCODE_AE_MULSSF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 36) + return OPCODE_AE_MULSSF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 37) + return OPCODE_AE_MULZAAAA2Q16; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 38) + return OPCODE_AE_MULZAAAA2Q32X16; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 39) + return OPCODE_AE_MULZAAF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 40) + return OPCODE_AE_MULZAAF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 41) + return OPCODE_AE_MULZAAF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 42) + return OPCODE_AE_MULZAAF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 43) + return OPCODE_AE_MULZASF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 44) + return OPCODE_AE_MULZASF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 45) + return OPCODE_AE_MULZASF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 46) + return OPCODE_AE_MULZASF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 47) + return OPCODE_AE_MULZSAF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 48) + return OPCODE_AE_MULZSAF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 49) + return OPCODE_AE_MULZSAF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 50) + return OPCODE_AE_MULZSAF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 51) + return OPCODE_AE_MULZSSF2D32RA_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 52) + return OPCODE_AE_MULZSSF2D32RA_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 53) + return OPCODE_AE_MULZSSF2D32S_HH_LL; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 54) + return OPCODE_AE_MULZSSF2D32S_HL_LH; + if (Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get (insn) == 57 && + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get (insn) == 0) + return OPCODE_AE_MULFD16X16X4RAS; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot3_35_11_Slot_ae7_slot3_get (insn) == 29884417 && + Field_fld_ae7_slot3_10_0_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57632) + return OPCODE_AE_MULAAAA2Q8; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57633) + return OPCODE_AE_MULADDF32RAS; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57634) + return OPCODE_AE_MULADDF32RS; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57635) + return OPCODE_AE_MULSUBF32RAS; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57636) + return OPCODE_AE_MULSUBF32RS; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57637) + return OPCODE_AE_MULZAAAA2Q8; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57638 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57638 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57638 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 2) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57638 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 3) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57639 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57639 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get (insn) == 57639 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 2) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1760) + return OPCODE_AE_MULAAAA2Q16X8; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1761) + return OPCODE_AE_MULAF2P32X16X4RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1762) + return OPCODE_AE_MULAF2P32X16X4RS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1763) + return OPCODE_AE_MULAF2P32X16X4S; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1764) + return OPCODE_AE_MULAFD32X16X2_FIR_HH; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1765) + return OPCODE_AE_MULAFD32X16X2_FIR_HL; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1766) + return OPCODE_AE_MULAFD32X16X2_FIR_LH; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1767) + return OPCODE_AE_MULAFD32X16X2_FIR_LL; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1768) + return OPCODE_AE_MULAFD32X2RA_FIR_H; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1769) + return OPCODE_AE_MULAFD32X2RA_FIR_L; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1770) + return OPCODE_AE_MULAFD32X2S_FIR_H; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1771) + return OPCODE_AE_MULAFD32X2S_FIR_L; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1772) + return OPCODE_AE_MULAFPC32X16X2RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1773) + return OPCODE_AE_MULAFPCJ32X16X2RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1774) + return OPCODE_AE_MULAFQ16X2_FIR_0; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1775) + return OPCODE_AE_MULAFQ16X2_FIR_1; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1776) + return OPCODE_AE_MULAFQ16X2_FIR_2; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1777) + return OPCODE_AE_MULAFQ16X2_FIR_3; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1778) + return OPCODE_AE_MULAPC32X16X2; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1779) + return OPCODE_AE_MULF2P32X16X4RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1780) + return OPCODE_AE_MULF2P32X16X4RS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1781) + return OPCODE_AE_MULF2P32X16X4S; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1782) + return OPCODE_AE_MULFD32X16X2_FIR_HH; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1783) + return OPCODE_AE_MULFD32X16X2_FIR_HL; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1784) + return OPCODE_AE_MULFD32X16X2_FIR_LH; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1785) + return OPCODE_AE_MULFD32X16X2_FIR_LL; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1786) + return OPCODE_AE_MULFD32X2RA_FIR_H; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1787) + return OPCODE_AE_MULFD32X2RA_FIR_L; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1788) + return OPCODE_AE_MULFD32X2S_FIR_H; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1789) + return OPCODE_AE_MULFD32X2S_FIR_L; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1790) + return OPCODE_AE_MULFPC32X16X2RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1791) + return OPCODE_AE_MULFPCJ32X16X2RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1792) + return OPCODE_AE_MULFQ16X2_FIR_0; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1793) + return OPCODE_AE_MULFQ16X2_FIR_1; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1794) + return OPCODE_AE_MULFQ16X2_FIR_2; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1795) + return OPCODE_AE_MULFQ16X2_FIR_3; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1796) + return OPCODE_AE_MULPC32X16X2; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1797) + return OPCODE_AE_MULSF2P32X16X4RAS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1798) + return OPCODE_AE_MULSF2P32X16X4RS; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1799) + return OPCODE_AE_MULSF2P32X16X4S; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1800) + return OPCODE_AE_MULZAAAA2Q16X8; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1856 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULAAAAFQ32X16; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1856 && + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (insn) == 98) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1857 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULAAAAQ32X16; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1857 && + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (insn) == 98) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1858 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULZAAAAFQ32X16; + if (Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get (insn) == 1859 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULZAAAAQ32X16; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MUL2P32X4; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MUL2P32X4S; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 2) + return OPCODE_AE_MUL2P32X4T; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 3) + return OPCODE_AE_MUL2Q32X16_FIR_H; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 4) + return OPCODE_AE_MUL2Q32X16_FIR_L; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 5) + return OPCODE_AE_MULA2P32X4; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 6) + return OPCODE_AE_MULA2P32X4T; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 7) + return OPCODE_AE_MULA2Q32X16_FIR_H; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 8) + return OPCODE_AE_MULA2Q32X16_FIR_L; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 9) + return OPCODE_AE_MULAAAA2Q16; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 10) + return OPCODE_AE_MULAAAA2Q32X16; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 11) + return OPCODE_AE_MULAAF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 12) + return OPCODE_AE_MULAAF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 13) + return OPCODE_AE_MULAAF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 14) + return OPCODE_AE_MULAAF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 15) + return OPCODE_AE_MULAF2P32X4RAS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 16) + return OPCODE_AE_MULAF2P32X4RS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 17) + return OPCODE_AE_MULASF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 18) + return OPCODE_AE_MULASF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 19) + return OPCODE_AE_MULASF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 20) + return OPCODE_AE_MULASF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 21) + return OPCODE_AE_MULF2D32X2WS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 22) + return OPCODE_AE_MULF2P32X4RAS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 23) + return OPCODE_AE_MULF2P32X4RS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 24) + return OPCODE_AE_MULFD16X16X4WS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 25) + return OPCODE_AE_MULS2P32X4; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 26) + return OPCODE_AE_MULS2P32X4T; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 27) + return OPCODE_AE_MULSAF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 28) + return OPCODE_AE_MULSAF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 29) + return OPCODE_AE_MULSAF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 30) + return OPCODE_AE_MULSAF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 31) + return OPCODE_AE_MULSF2P32X4RAS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 32) + return OPCODE_AE_MULSF2P32X4RS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 33) + return OPCODE_AE_MULSSF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 34) + return OPCODE_AE_MULSSF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 35) + return OPCODE_AE_MULSSF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 36) + return OPCODE_AE_MULSSF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 37) + return OPCODE_AE_MULZAAAA2Q16; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 38) + return OPCODE_AE_MULZAAAA2Q32X16; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 39) + return OPCODE_AE_MULZAAF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 40) + return OPCODE_AE_MULZAAF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 41) + return OPCODE_AE_MULZAAF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 42) + return OPCODE_AE_MULZAAF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 43) + return OPCODE_AE_MULZASF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 44) + return OPCODE_AE_MULZASF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 45) + return OPCODE_AE_MULZASF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 46) + return OPCODE_AE_MULZASF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 47) + return OPCODE_AE_MULZSAF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 48) + return OPCODE_AE_MULZSAF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 49) + return OPCODE_AE_MULZSAF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 50) + return OPCODE_AE_MULZSAF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 51) + return OPCODE_AE_MULZSSF2D32RA_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 52) + return OPCODE_AE_MULZSSF2D32RA_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 53) + return OPCODE_AE_MULZSSF2D32S_HH_LL; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 54) + return OPCODE_AE_MULZSSF2D32S_HL_LH; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 57 && + Field_fld_ae7_slot3_24_10_Slot_ae7_slot3_get (insn) == 2 && + Field_fld_ae7_slot3_4_0_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MOV; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 57 && + Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_DSEL8X8; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 57 && + Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 58 && + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MULFD16X16X4RAS; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 58 && + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (insn) == 34) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 58 && + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (insn) == 2) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get (insn) == 58 && + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get (insn) == 66) + return OPCODE_AE_SEL8X8I; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae8_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get (insn) == 566808 && + Field_fld_ae8_slot2_33_9_Slot_ae8_slot2_get (insn) == 4096 && + Field_fld_ae8_slot2_8_0_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_NOP; + if (Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get (insn) == 566808 && + Field_fld_ae8_slot2_33_25_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_15_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_get (insn) == 0) + return OPCODE_AE_MOV; + if (Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get (insn) == 566808 && + Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_get (insn) == 32 && + Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MOVZBVCDR; + if (Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get (insn) == 566808 && + Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MOVDRZBVC; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 262924) + return OPCODE_AE_MUL4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 263948) + return OPCODE_AE_MUL4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 264972) + return OPCODE_AE_MULA4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 265996) + return OPCODE_AE_MULA4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 267020) + return OPCODE_AE_MULASU4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 268044) + return OPCODE_AE_MULASU4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 269068) + return OPCODE_AE_MULAUS4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 270092) + return OPCODE_AE_MULAUS4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 271116) + return OPCODE_AE_MULAUU4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 272140) + return OPCODE_AE_MULAUU4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 273164) + return OPCODE_AE_MULAUUZB4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 274188) + return OPCODE_AE_MULAUUZB4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 275212) + return OPCODE_AE_MULSU4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 276236) + return OPCODE_AE_MULSU4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 277260) + return OPCODE_AE_MULUS4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 278284) + return OPCODE_AE_MULUS4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 279308) + return OPCODE_AE_MULUU4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 280332) + return OPCODE_AE_MULUU4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 281356) + return OPCODE_AE_MULUUZB4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 282380) + return OPCODE_AE_MULUUZB4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 287500) + return OPCODE_AE_MULAZB4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 288524) + return OPCODE_AE_MULZB4O8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 289548) + return OPCODE_AE_MULAZB4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 290572) + return OPCODE_AE_MULZB4O8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 360645 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MUL8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 360645 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MUL2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 360677 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MUL8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 360677 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULA2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 361669 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULA8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 361669 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULA8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 361701 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULASU8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 361701 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULASU2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 362693 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUS2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 362693 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULASU8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 362725 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUS8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 362725 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUS8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 363717 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUU8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 363717 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUU2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 363749 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUU8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 363749 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUUZB2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 364741 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUUZB8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 364741 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUUZB8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 364773 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULSU8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 364773 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULSU2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 365765 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 365765 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULSU8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 365797 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 365797 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUS8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 366789 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUU8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 366789 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUU2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 366821 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUU8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 366821 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUUZB2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 367813 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUUZB8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 367813 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUUZB8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 368837 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULZB2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 369893 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAZB8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 371941 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAZB8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 372933 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULZB8Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 373989 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAZB2X4Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get (insn) == 375013 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULZB8Q8X8CNV_H; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10240) + return OPCODE_AE_MUL4O4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10272) + return OPCODE_AE_MUL4QW8X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10304) + return OPCODE_AE_MULA4O4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10336) + return OPCODE_AE_MULA4QW8X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10368) + return OPCODE_AE_MULAUS4O4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10400) + return OPCODE_AE_MULAUS4QW8X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10432) + return OPCODE_AE_MULUS4O4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 10464) + return OPCODE_AE_MULUS4QW8X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 11264 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MUL8Q4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 11265 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MULA8Q4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 11266 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MULAUS8Q4X16; + if (Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get (insn) == 11267 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MULUS8Q4X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 0) + return OPCODE_AE_MUL4O8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MUL8QW8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 2) + return OPCODE_AE_MULA4O8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 3) + return OPCODE_AE_MULA8QW8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULAUS4O8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULAUS8QW8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUS4O8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS8QW8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULQQ8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 2) + return OPCODE_AE_MULAQQ8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 140) + return OPCODE_AE_MUL4O8X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 332) + return OPCODE_AE_MULA4O8X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 172) + return OPCODE_AE_MUL4O8X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 364) + return OPCODE_AE_MULA4O8X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULQQ4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 0) + return OPCODE_AE_MULAQQ4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULQQ4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MULAQQ4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 12) + return OPCODE_AE_MUL4O4X16CNV_HH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 44) + return OPCODE_AE_MUL4O4X16CNV_HL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 76) + return OPCODE_AE_MUL4O4X16CNV_LH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 108) + return OPCODE_AE_MUL4O4X16CNV_LL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 204) + return OPCODE_AE_MULA4O4X16CNV_HH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 236) + return OPCODE_AE_MULA4O4X16CNV_HL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 268) + return OPCODE_AE_MULA4O4X16CNV_LH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 300) + return OPCODE_AE_MULA4O4X16CNV_LL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 11) + return OPCODE_AE_MULUSQQ8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULAUSQQ8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 716) + return OPCODE_AE_MULUS4O8X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 524) + return OPCODE_AE_MULAUS4O8X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 748) + return OPCODE_AE_MULUS4O8X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 556) + return OPCODE_AE_MULAUS4O8X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MULUSQQ4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3) + return OPCODE_AE_MULAUSQQ4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 10) + return OPCODE_AE_MULUSQQ4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULAUSQQ4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 588) + return OPCODE_AE_MULUS4O4X16CNV_HH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 620) + return OPCODE_AE_MULUS4O4X16CNV_HL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 652) + return OPCODE_AE_MULUS4O4X16CNV_LH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 684) + return OPCODE_AE_MULUS4O4X16CNV_LL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 396) + return OPCODE_AE_MULAUS4O4X16CNV_HH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 428) + return OPCODE_AE_MULAUS4O4X16CNV_HL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 460) + return OPCODE_AE_MULAUS4O4X16CNV_LH; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 492) + return OPCODE_AE_MULAUS4O4X16CNV_LL; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 0) + return OPCODE_AE_MUL4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MULA4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULUU4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULAUU4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 3) + return OPCODE_AE_MULAUS4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULSU4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 2) + return OPCODE_AE_MULASU4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 9) + return OPCODE_AE_MULUUZB4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULAUUZB4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 13) + return OPCODE_AE_MULZB4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 12) + return OPCODE_AE_MULAZB4O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MUL8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 1 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULA8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 0) + return OPCODE_AE_MUL8Q8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 1) + return OPCODE_AE_MULA8Q8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 37 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MUL8Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 69 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULA8Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MUL2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 1 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULA2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MUL2X4Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 1 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULA2X4Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 5 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MUL8Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 37 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULA8Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 5 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MUL8Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 69 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULA8Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MUL2X4Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 1 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULA2X4Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 0 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MUL2X4Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 1 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULA2X4Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 8 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULUU8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 4 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULAUU8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 5 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULUU2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULAUU2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 7 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULUS8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULAUS8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 3) + return OPCODE_AE_MULUS8Q8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 2) + return OPCODE_AE_MULAUS8Q8X16; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 165 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS8Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 133 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUS8Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 4 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULAUS2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 4 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUS2X4Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 2 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUS2X4Q8X16CNV; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 133 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULUS8Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 101 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUS8Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 165 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULUS8Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get (insn) == 101 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULAUS8Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 4 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULUS2X4Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 2 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULAUS2X4Q4X16CNV_H; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 4 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULUS2X4Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 2 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUS2X4Q4X16CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 6 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULSU8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 2 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULASU8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 7) + return OPCODE_AE_MULSU2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 2 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 4) + return OPCODE_AE_MULASU2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 9 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULUUZB8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 5 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULAUUZB8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 5 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 5) + return OPCODE_AE_MULUUZB2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 6) + return OPCODE_AE_MULAUUZB2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 14 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULZB8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get (insn) == 10 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 8) + return OPCODE_AE_MULAZB8Q8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 14) + return OPCODE_AE_MULZB2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 11 && + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get (insn) == 3 && + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get (insn) == 12) + return OPCODE_AE_MULAZB2X4Q8X8CNV_L; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 256) + return OPCODE_AE_MULZB3X3O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 257) + return OPCODE_AE_MULAZB3X3O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 262) + return OPCODE_AE_MULAUUZB3X3O8X8; + if (Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get (insn) == 266) + return OPCODE_AE_MULUUZB3X3O8X8; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae9_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_get (insn) == 228098 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONST_H; + if (Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_get (insn) == 228099 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONST_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 98689 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ABS_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 99713 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONJC_H; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 100737 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONJC_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 101761 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_DIV0_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 102785 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MKSADJ_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 103809 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MULJC_H; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 104833 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MULJC_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 105857 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_NEG_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 106881 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_NEXP01_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 107905 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_RECIP0_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 108929 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_RSQRT0_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 109953 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_SQRT0_S; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 110977 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ABS_H; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 112001 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CLSFY_H; + if (Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get (insn) == 113025 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_NEG_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2624 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_DIVN_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2656 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MADDN_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2688 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MADD_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2720 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MSUBN_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2752 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MSUB_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 2784 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MUL_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3083 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MAXNUM_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3115 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MAX_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3147 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MINNUM_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3179 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MIN_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3211 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 1 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_AE_MOVT64; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3211 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_AE_MOVF64; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 1 && + Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_get (insn) == 33) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 1 && + Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_get (insn) == 33) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 865) + return OPCODE_AE_MOV; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 705) + return OPCODE_MKDADJ_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 609) + return OPCODE_ADDEXP_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 577) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 833) + return OPCODE_ADDEXP_H; + if (Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get (insn) == 3243 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 737) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 74) + return OPCODE_MADDQ_S; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 75) + return OPCODE_MSUBQ_S; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 76) + return OPCODE_MULQ_S; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 77) + return OPCODE_MULQ_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 0) + return OPCODE_MADDA_S; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 128) + return OPCODE_ADD_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 133) + return OPCODE_SUB_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 132) + return OPCODE_MUL_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 129) + return OPCODE_MADD_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 131) + return OPCODE_MSUB_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 78 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 130) + return OPCODE_MSUBN_H; + if (Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get (insn) == 96 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 2) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_get (insn) == 36) + return OPCODE_MULMUXQ_S; + if (Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_get (insn) == 40 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 4) + return OPCODE_MULMUX_S; + if (Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_get (insn) == 8) + return OPCODE_MADDMUXQ_S; + if (Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 0) + return OPCODE_ADD_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_SUB_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 0) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 33) + return OPCODE_ADD_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 161) + return OPCODE_SUB_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 321) + return OPCODE_MIN_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 385) + return OPCODE_MAX_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_get (insn) == 386 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CLSFY_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 193) + return OPCODE_MINNUM_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 257) + return OPCODE_MAXNUM_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 9 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 8 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 449) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_FREXP_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_get (insn) == 386 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 33) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 65) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 10 && + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get (insn) == 129) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 1 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 7 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 5 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_get (insn) == 769 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 0 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 6 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 2 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_get (insn) == 768 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get (insn) == 3 && + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get (insn) == 4 && + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get (insn) == 1) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae9_slot2_33_9_Slot_ae9_slot2_get (insn) == 6316160 && + Field_fld_ae9_slot2_8_0_Slot_ae9_slot2_get (insn) == 65) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae9_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get (insn) == 28696) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get (insn) == 28697) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get (insn) == 29846 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CONST_H; + if (Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get (insn) == 29847 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CONST_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14347 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CLSFY_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14379 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_DIV0_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14411 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14443 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_MKSADJ_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14475 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_NEXP01_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14507 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_RECIP0_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14539 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_RSQRT0_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14571 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_SQRT0_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14603 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_ABS_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14635 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CONJC_H; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14667 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CONJC_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14699 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_MULJC_H; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14731 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_MULJC_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14763 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_NEG_S; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14795 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_ABS_H; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14827 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_CLSFY_H; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14859 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_NEG_H; + if (Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get (insn) == 14891 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_AE_MOV; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 576 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_DIVN_S; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 608 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MADDN_S; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 640 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MADD_S; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 672 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MSUBN_S; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 704 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MSUB_S; + if (Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get (insn) == 736 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MUL_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 10) + return OPCODE_MADDQ_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 11) + return OPCODE_MSUBQ_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 12) + return OPCODE_MULQ_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 13) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_4_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_AE_SEL16I; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 27) + return OPCODE_MIN_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 25) + return OPCODE_MAX_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 26) + return OPCODE_MINNUM_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 25) + return OPCODE_MAXNUM_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 9) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 8) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 24) + return OPCODE_FREXP_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 26) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 24) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_BMAXNUM_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get (insn) == 2) + return OPCODE_BMINNUM_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_BMAXNUMABS_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get (insn) == 2) + return OPCODE_BMINNUMABS_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 7) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 3) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 5) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_MIN_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 10 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 28) + return OPCODE_MAX_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 28) + return OPCODE_MINNUM_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 11 && + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get (insn) == 27) + return OPCODE_MAXNUM_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 6) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 2) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 14 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 4) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 5) + return OPCODE_ADD_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 6) + return OPCODE_SUB_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 226) + return OPCODE_MKDADJ_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 225) + return OPCODE_ADDEXP_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 224) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 4) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_MADDA_S; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 228) + return OPCODE_ADDEXP_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 227) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 64) + return OPCODE_ADD_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 98) + return OPCODE_SUB_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 66) + return OPCODE_MUL_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 96) + return OPCODE_MADD_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 97) + return OPCODE_MSUB_H; + if (Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get (insn) == 15 && + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get (insn) == 65) + return OPCODE_MSUBN_H; + if (Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_get (insn) == 4) + return OPCODE_MULMUXQ_S; + if (Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_get (insn) == 8 && + Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 1) + return OPCODE_MULMUX_S; + if (Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_MADDMUXQ_S; + if (Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_get (insn) == 2 && + Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_get (insn) == 0 && + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae9_slot3_31_7_Slot_ae9_slot3_get (insn) == 3828480 && + Field_fld_ae9_slot3_6_0_Slot_ae9_slot3_get (insn) == 29) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4096) + return OPCODE_AE_EXPADD16_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4097) + return OPCODE_AE_EXPADD16_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4098) + return OPCODE_AE_EXPSUB16_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4099) + return OPCODE_AE_EXPSUB16_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4100) + return OPCODE_AE_ADD16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4101) + return OPCODE_AE_ADD16S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4102) + return OPCODE_AE_ADD24S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4103) + return OPCODE_AE_ADD32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4104) + return OPCODE_AE_ADD32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4105) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4106) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4107) + return OPCODE_AE_ADD64; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4108) + return OPCODE_AE_ADD64S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4109) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4110) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4111) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4112) + return OPCODE_AE_ADDSUB32S_HL_LH; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4113) + return OPCODE_AE_ADDSUB32_HL_LH; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4114) + return OPCODE_AE_MAX16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4115) + return OPCODE_AE_MAX32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4116) + return OPCODE_AE_MAX8; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4117) + return OPCODE_AE_MIN16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4118) + return OPCODE_AE_MIN32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4119) + return OPCODE_AE_MIN8; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4120) + return OPCODE_AE_MINMAX16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4121) + return OPCODE_AE_MINMAX32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4122) + return OPCODE_AE_MOVNEG32S_T; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4123) + return OPCODE_AE_ROUND16X4F32SASYM; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4124) + return OPCODE_AE_ROUND16X4F32SSYM; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4125) + return OPCODE_AE_ROUND32X2F64SASYM; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4126) + return OPCODE_AE_ROUND32X2F64SSYM; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4127) + return OPCODE_AE_SUB16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4128) + return OPCODE_AE_SUB16S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4129) + return OPCODE_AE_SUB24S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4130) + return OPCODE_AE_SUB32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4131) + return OPCODE_AE_SUB32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4132) + return OPCODE_AE_SUB64; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4133) + return OPCODE_AE_SUB64S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4134) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4135) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4136) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4137) + return OPCODE_ADD_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4138) + return OPCODE_DIVN_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4139) + return OPCODE_MADDN_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4140) + return OPCODE_MADD_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4141) + return OPCODE_MSUB_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4142) + return OPCODE_MUL_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 4143) + return OPCODE_SUB_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5131 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5163 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SAT48S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5195 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5208 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5209 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG16S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5210 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG24S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5211 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5212 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5213 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG32_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5214 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG64; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5215 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_NEG64S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5227 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ADDEXP_S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5233 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS16; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5234 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5235 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS64; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5237 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS16S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5238 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS64S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5239 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5241 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS24S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5242 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5243 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5245 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ABS32; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5246 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_DIV64D32_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5247 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5259 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MKDADJ_S; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5291 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADD16X4; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5323 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADD8X8_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5355 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADD8X8_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5387 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADDA16X4; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5419 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADDA8X8_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5451 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RADDA8X8_L; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5483 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RMAX16X4; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5515 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RMAX8X8; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5547 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RMIN16X4; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5579 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_RMIN8X8; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5611 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ABS_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5643 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_CLSFY_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5675 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_NEG_H; + if (Field_fld_ae_slot2_28_15_Slot_ae_slot2_get (insn) == 5707 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MKDADJ_H; + if (Field_fld_ae_slot2_28_17_Slot_ae_slot2_get (insn) == 1300 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ADD72X64; + if (Field_fld_ae_slot2_28_17_Slot_ae_slot2_get (insn) == 1301 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SUB72X64; + if (Field_fld_ae_slot2_28_17_Slot_ae_slot2_get (insn) == 1316 && + Field_fld_ae_slot2_14_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SEXT72; + if (Field_fld_ae_slot2_28_19_Slot_ae_slot2_get (insn) == 321 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_ADD72; + if (Field_fld_ae_slot2_28_19_Slot_ae_slot2_get (insn) == 323 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SUB72; + if (Field_fld_ae_slot2_28_19_Slot_ae_slot2_get (insn) == 327 && + Field_fld_ae_slot2_16_15_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SAT64S; + if (Field_fld_ae_slot2_28_19_Slot_ae_slot2_get (insn) == 342 && + Field_fld_ae_slot2_14_0_Slot_ae_slot2_get (insn) == 1062) + return OPCODE_AE_MOVEEP; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 64) + return OPCODE_AE_MUL16X4; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 65) + return OPCODE_AE_MUL16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 66) + return OPCODE_AE_MULA16X4; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 67) + return OPCODE_AE_MULA16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 68) + return OPCODE_AE_MULAFC32RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 69) + return OPCODE_AE_MULAFC32X16W_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 70) + return OPCODE_AE_MULAFC32X16W_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 71) + return OPCODE_AE_MULAFP32X2S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 72) + return OPCODE_AE_MULAFP32X2S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 73) + return OPCODE_AE_MULFC32RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 74) + return OPCODE_AE_MULFC32X16W_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 75) + return OPCODE_AE_MULFC32X16W_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 76) + return OPCODE_AE_MULFP32X2S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 77) + return OPCODE_AE_MULFP32X2S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 78) + return OPCODE_AE_MULS16X4; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 79) + return OPCODE_AE_MULS16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 80) + return OPCODE_AE_MULSFP32X2S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 81) + return OPCODE_AE_MULSFP32X2S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 82) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 83) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 84) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 85) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 86) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 87) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 88) + return OPCODE_MADDA_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 89) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 90) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 91) + return OPCODE_AE_SEL8X8I; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 2) + return OPCODE_AE_MUL32EP_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 5) + return OPCODE_AE_MULA32EP_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 3) + return OPCODE_AE_MUL32USEP_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 6) + return OPCODE_AE_MULA32USEP_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 4) + return OPCODE_AE_MUL32USEP_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 7) + return OPCODE_AE_MULA32USEP_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 92 && + Field_fld_ae_slot2_9_8_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MADDMUX_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 7) + return OPCODE_AE_SEL16I_N; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 2) + return OPCODE_AE_MULS32EP_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 4) + return OPCODE_AE_MULZAAD32EP_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 6) + return OPCODE_AE_MULZSSD32EP_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_MULAAD32EP_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 3) + return OPCODE_AE_MULSSD32EP_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 1) + return OPCODE_AE_MULAAD32USEP_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 93 && + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get (insn) == 5) + return OPCODE_AE_MULZAAD32USEP_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 8) + return OPCODE_AE_MUL32U_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULA32U_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 2) + return OPCODE_AE_MUL16S_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULA16S_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 10) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 3) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 4) + return OPCODE_AE_MUL32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULA32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 7) + return OPCODE_AE_MUL32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULA32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 5) + return OPCODE_AE_MUL32S_HL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULA32S_HL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 6) + return OPCODE_AE_MUL32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULA32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 94 && + Field_fld_ae_slot2_9_6_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MULMUX_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULAC16JS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULAC16JS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 5) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 4) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 3) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 1) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 2) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 8) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_MULAAD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 10) + return OPCODE_AE_MULAAD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 6) + return OPCODE_AE_MULAA2D16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 7) + return OPCODE_AE_MULAA2D16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULAAFD16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 95 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULAAFD16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULSAD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULSAD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULSAD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULSAD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 96 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC16S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULSF32RA_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULSF32RA_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32RA_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULSF16SS_33; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULSF16SS_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULSF16SS_32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULSF16SS_21; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULSF16SS_31; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULSF16SS_30; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULSF16SS_10; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULSF16SS_20; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULSF16SS_11; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC16S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 97 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAFC16RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAFCJ32RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 98 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAFCJ16RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULSFP32X2TS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULSP32X2T; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULSP16S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULSP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 99 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULSP16X16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC32X16_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULSSD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULSSD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULSS2D16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULSS2D16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULSSFD16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 100 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULSSFD16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAFP32X2TS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAC32X16_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULZAAD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULZAAD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAP16S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULZAA2D16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 101 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULZAA2D16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULZASD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULZASD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULACJ32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAP16X16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULZAAFD16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 102 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULZAAFD16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULZSAD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULZSAD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAP32X2T; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULZSAD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 103 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULZSAD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_10; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULZSSD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULASD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_AE_MULZSSD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULASD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULZSS2D16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULZSS2D16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_AE_MULZSSFD16SS_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 104 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_AE_MULZSSFD16SS_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_11; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 19) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 17) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 21) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 20) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 31) + return OPCODE_MUL_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 24) + return OPCODE_MADD_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 30) + return OPCODE_MSUB_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 29) + return OPCODE_MSUBN_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 23) + return OPCODE_MADDN_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 22) + return OPCODE_DIVN_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 28) + return OPCODE_MIN_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 26) + return OPCODE_MAX_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 27) + return OPCODE_MINNUM_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 105 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 25) + return OPCODE_MAXNUM_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 106 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_20; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 106 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 106 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 106 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 106 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 107 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULC16JS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 107 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULC16JS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 107 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_21; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 107 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 107 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 108 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 108 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULC32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 108 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULC16S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 108 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULC16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 108 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULC16S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 109 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 109 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_30; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 109 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULC32X16_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 109 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULC32X16_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 109 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULCJ32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 110 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF16SS_21; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 110 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF16SS_10; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 110 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF16SS_20; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 110 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF16SS_11; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 110 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_31; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 111 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF16SS_22; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 111 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF16SS_32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 111 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF16SS_31; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 111 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF16SS_30; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 111 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 112 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF32RA_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 112 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF32RA_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 112 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF32RA_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 112 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF16SS_33; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 112 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF16SS_33; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 113 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 113 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 113 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 113 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 113 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32RA_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 114 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 114 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 114 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32RA_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 114 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 114 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 115 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32RA_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 115 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 115 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 115 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 115 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 116 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 116 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 116 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 116 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 116 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 117 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 117 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 117 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 117 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 117 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFC16RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 118 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 118 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULFP16X4RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 118 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 118 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULFCJ32RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 118 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULFCJ16RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 119 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 119 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 119 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 119 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULFP16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 119 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFP16X4RS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 120 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 120 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 120 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 120 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 120 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 121 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 121 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 121 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 121 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 121 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 122 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 122 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULFP32X2TS; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 122 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULP16S_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 122 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 122 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULP16X16X4S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 123 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 123 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 123 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 123 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 123 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULP32X2T; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 124 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 124 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULS16S_00; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 124 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 124 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 124 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 125 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 125 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 125 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 125 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULS32S_HH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 125 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULS32S_HL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 126 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULS32U_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 126 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 126 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 126 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULS32S_LL; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 126 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULS32S_LH; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 127 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 127 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 15) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 127 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 127 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 127 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 14) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 130 && + Field_fld_ae_slot2_14_10_Slot_ae_slot2_get (insn) == 1) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 130 && + Field_fld_ae_slot2_14_10_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 160 && + Field_fld_ae_slot2_9_2_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_PKSR16; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 161 && + Field_fld_ae_slot2_9_2_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_PKSR24; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 162 && + Field_fld_ae_slot2_9_2_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_PKSR32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 163 && + Field_fld_ae_slot2_9_2_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 164 && + Field_fld_ae_slot2_9_1_Slot_ae_slot2_get (insn) == 18) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 164 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_ABS_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 164 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_CONJC_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 165 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_MKSADJ_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 165 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_DIV0_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 165 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_CONJC_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 165 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_MULJC_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 166 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_NEXP01_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 166 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_RECIP0_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 166 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_NEG_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 166 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_MULJC_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 167 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_SQRT0_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 167 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_RSQRT0_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 167 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_ADDEXP_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 167 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 168 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 168 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 168 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_AE_MOV; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 168 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_DIV0_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 169 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_MKSADJ_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 169 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_NEXP0_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 169 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_NEXP01_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 169 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_RECIP0_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 170 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 170 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 170 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_RSQRT0_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 170 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_SQRT0_H; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 171 && + Field_fld_ae_slot2_14_0_Slot_ae_slot2_get (insn) == 39) + return OPCODE_AE_MOVZBVCDR; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 171 && + Field_fld_ae_slot2_14_0_Slot_ae_slot2_get (insn) == 38) + return OPCODE_AE_MOVDRZBVC; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 171 && + Field_fld_ae_slot2_14_14_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 37) + return OPCODE_CONST_S; + if (Field_fld_ae_slot2_28_20_Slot_ae_slot2_get (insn) == 171 && + Field_fld_ae_slot2_14_14_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 36) + return OPCODE_CONST_H; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 1) + return OPCODE_AE_DSEL8X8; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 8) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 10) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 9) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 1) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 7) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 3) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 5) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 6) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 2) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 4) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 7 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SORT16X4; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 9 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ADD_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 10 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_SUB_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 6 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MIN_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 3 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MAX_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 33) + return OPCODE_CLSFY_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MINNUM_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 2 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MAXNUM_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 8 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_FREXP_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 1 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 33) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 4 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get (insn) == 1 && + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get (insn) == 0) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_14_14_Slot_ae_slot2_get (insn) == 1 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 32) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae_slot2_28_25_Slot_ae_slot2_get (insn) == 5 && + Field_fld_ae_slot2_14_14_Slot_ae_slot2_get (insn) == 0 && + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get (insn) == 32) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae_slot2_28_4_Slot_ae_slot2_get (insn) == 11206722 && + Field_fld_ae_slot2_3_0_Slot_ae_slot2_get (insn) == 7) + return OPCODE_NOP; + if (Field_fld_ae_slot2_28_5_Slot_ae_slot2_get (insn) == 5394432) + return OPCODE_AE_MOVFCRFSRV; + if (Field_fld_ae_slot2_28_5_Slot_ae_slot2_get (insn) == 5395456) + return OPCODE_AE_MOVVFCRFSR; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot3_36_12_Slot_ae_slot3_get (insn) == 15205414 && + Field_fld_ae_slot3_11_0_Slot_ae_slot3_get (insn) == 2146) + return OPCODE_NOP; + if (Field_fld_ae_slot3_36_16_Slot_ae_slot3_get (insn) == 934928 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot3_36_19_Slot_ae_slot3_get (insn) == 116864 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_CONST_HX4X2; + if (Field_fld_ae_slot3_36_19_Slot_ae_slot3_get (insn) == 116868 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_CONST_H; + if (Field_fld_ae_slot3_36_19_Slot_ae_slot3_get (insn) == 116870 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_CONST_S; + if (Field_fld_ae_slot3_36_19_Slot_ae_slot3_get (insn) == 116928 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_CONST_SX2X2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57632) + return OPCODE_AE_MUL16X4; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57633) + return OPCODE_AE_MUL16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57634) + return OPCODE_AE_MUL2C16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57635) + return OPCODE_AE_MUL32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57636) + return OPCODE_AE_MUL32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57637) + return OPCODE_AE_MULA16X4; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57638) + return OPCODE_AE_MULA16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57639) + return OPCODE_AE_MULA2C16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57640) + return OPCODE_AE_MULA32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57641) + return OPCODE_AE_MULA32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57642) + return OPCODE_AE_MULAA32X2_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57643) + return OPCODE_AE_MULAAAA2Q8; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57644) + return OPCODE_AE_MULAC16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57645) + return OPCODE_AE_MULAC16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57646) + return OPCODE_AE_MULAC32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57647) + return OPCODE_AE_MULAC32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57648) + return OPCODE_AE_MULAC32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57649) + return OPCODE_AE_MULACJ32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57650) + return OPCODE_AE_MULADDF32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57651) + return OPCODE_AE_MULADDF32RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57652) + return OPCODE_AE_MULAF16X4SS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57653) + return OPCODE_AE_MULAF32X2RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57654) + return OPCODE_AE_MULAF32X2RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57655) + return OPCODE_AE_MULAF32X2R_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57656) + return OPCODE_AE_MULAF32X2R_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57657) + return OPCODE_AE_MULAFC16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57658) + return OPCODE_AE_MULAFC32RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57659) + return OPCODE_AE_MULAFC32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57660) + return OPCODE_AE_MULAFC32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57661) + return OPCODE_AE_MULAFC32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57662) + return OPCODE_AE_MULAFCJ16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57663) + return OPCODE_AE_MULAFCJ32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57664) + return OPCODE_AE_MULAFCJ32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57665) + return OPCODE_AE_MULAFCJ32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57666) + return OPCODE_AE_MULAFP32X16_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57667) + return OPCODE_AE_MULAFP32X16_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57668) + return OPCODE_AE_MULC32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57669) + return OPCODE_AE_MULC32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57670) + return OPCODE_AE_MULC32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57671) + return OPCODE_AE_MULCJ32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57672) + return OPCODE_AE_MULF32X2R_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57673) + return OPCODE_AE_MULFC16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57674) + return OPCODE_AE_MULFC32RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57675) + return OPCODE_AE_MULFC32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57676) + return OPCODE_AE_MULFCJ32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57677) + return OPCODE_AE_MULFCJ32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57678) + return OPCODE_AE_MULFP32X16_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57679) + return OPCODE_AE_MULFP32X16_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57680) + return OPCODE_AE_MULS32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57681) + return OPCODE_AE_MULS32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57682) + return OPCODE_AE_MULSF16X4SS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57683) + return OPCODE_AE_MULSF32X2RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57684) + return OPCODE_AE_MULSFP32X16_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57685) + return OPCODE_AE_MULSFP32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57686) + return OPCODE_AE_MULSFP32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57687) + return OPCODE_AE_MULSS32X2_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57688) + return OPCODE_AE_MULZSS32X2_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULAC16JS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULAC16JS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULAAD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULAAD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULAA2D16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULAA2D16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULAAFD16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57689 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULAAFD16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULC16JS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULF32RA_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULF16SS_33; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULF16SS_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULF16SS_31; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULF16SS_10; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULF16SS_20; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULC16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULFC16RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULFCJ32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULCJ32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57690 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULC16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULC16JS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULF32RA_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULF32RA_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULF16SS_32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULF16SS_21; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULF16SS_30; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULF16SS_11; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULC32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULC16S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULFCJ16RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57691 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULFP16X4RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57692 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSS2D16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57693 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57693 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57693 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57693 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57693 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57694 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57694 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57694 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57694 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57694 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57695 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57695 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57695 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57695 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57695 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZSAD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57696) + return OPCODE_AE_MULAFP32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57697) + return OPCODE_AE_MULAFP32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57698) + return OPCODE_AE_MULC16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57699) + return OPCODE_AE_MULC16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57700) + return OPCODE_AE_MULF16X4SS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57701) + return OPCODE_AE_MULF32X2RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57702) + return OPCODE_AE_MULF32X2RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57703) + return OPCODE_AE_MULF32X2R_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57704) + return OPCODE_AE_MULFC32X16W_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57705) + return OPCODE_AE_MULFC32X16W_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57706) + return OPCODE_AE_MULFCJ16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57707) + return OPCODE_AE_MULFCJ32W; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57708) + return OPCODE_AE_MULFP32X2S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57709) + return OPCODE_AE_MULFP32X2S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57710) + return OPCODE_AE_MULS16X4; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57711) + return OPCODE_AE_MULS16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57712) + return OPCODE_AE_MULSF32X2RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57713) + return OPCODE_AE_MULSF32X2R_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57714) + return OPCODE_AE_MULSF32X2R_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57715) + return OPCODE_AE_MULSFP32X16_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57716) + return OPCODE_AE_MULSUBF32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57717) + return OPCODE_AE_MULSUBF32RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57718) + return OPCODE_AE_MULZAA32X2_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57719) + return OPCODE_AE_MULZAAAA2Q8; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULSF32RA_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULSF16SS_31; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULSF16SS_20; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULS32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULSAD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULP16S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULSP16S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULSS2D16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57720 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULZAAFD16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULSF32RA_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULSF16SS_32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULSF16SS_21; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULS16S_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULS32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULZAAD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULSSD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULSAD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULSP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULSS2D16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57721 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULZAAFD16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULSF16SS_33; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULSF16SS_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULSF16SS_10; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULSAD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULS32S_HL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULZAAD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULSSD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULP32X2S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULP16X16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULSP16X16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULZAA2D16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57722 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULSSFD16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULSF32RA_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULSF16SS_30; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULSF16SS_11; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULSAD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULS32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULZAA2D16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57723 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULSSFD16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57724 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57725 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57725 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57725 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57725 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57725 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD16SS_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57726 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57726 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57726 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57726 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57726 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57727 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57727 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57727 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57727 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MULZSAD32S_HL_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 57727 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSS2D16SS_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59532 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59533 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59534 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32S_HL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59535 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59536 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAC16S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59537 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULACJ32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59538 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_20; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59539 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_31; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59540 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32RA_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59541 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59542 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59543 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59544 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59545 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59546 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFCJ32RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59547 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59548 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59549 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59550 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59551 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59560 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL16S_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59561 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59562 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59563 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32S_HL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59564 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59565 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA16S_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59566 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59567 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59568 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAC16S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59569 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59570 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_21; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59571 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59572 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32RA_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59573 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59574 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59575 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59576 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59577 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59578 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59579 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59580 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59581 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP16X16X4S; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59582 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59583 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59592 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59593 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59594 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59595 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59596 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59597 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59598 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59599 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59600 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAC16S_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59601 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_10; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59602 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_22; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59603 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_33; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59604 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59605 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59606 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59607 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59608 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFC16RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59609 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59610 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59611 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59612 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59613 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59614 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59615 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULASD32S_HH_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59624 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59625 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59626 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59627 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59628 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59629 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59630 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59631 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59632 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAC32; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59633 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_11; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59634 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF16SS_30; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59635 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32RA_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59636 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59637 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59638 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59639 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59640 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59641 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFCJ16RAS; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59642 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59643 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59644 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP16S_H; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59645 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59646 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae_slot3_36_20_Slot_ae_slot3_get (insn) == 59647 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULASD32S_HL_LH; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14849 && + Field_fld_ae_slot3_19_17_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26722) + return OPCODE_AE_MOVEEP; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14880 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL32EP_HH; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14881 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULS32EP_HH; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14882 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZSSD32EP_HH_LL; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14888 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULA32EP_HH; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14889 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULSSD32EP_HH_LL; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14896 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAAD32EP_HH_LL; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14897 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZAAD32EP_HH_LL; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14904 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAAD32USEP_HL_LH; + if (Field_fld_ae_slot3_36_22_Slot_ae_slot3_get (insn) == 14905 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZAAD32USEP_HL_LH; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1760) + return OPCODE_AE_MULAAAA2Q16X8; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1761) + return OPCODE_AE_MULAF2P32X16X4RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1762) + return OPCODE_AE_MULAF2P32X16X4RS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1763) + return OPCODE_AE_MULAF2P32X16X4S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1764) + return OPCODE_AE_MULAFD32X16X2_FIR_HH; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1765) + return OPCODE_AE_MULAFD32X16X2_FIR_HL; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1766) + return OPCODE_AE_MULAFD32X16X2_FIR_LH; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1767) + return OPCODE_AE_MULAFD32X16X2_FIR_LL; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1768) + return OPCODE_AE_MULAFD32X2RA_FIR_H; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1769) + return OPCODE_AE_MULAFD32X2RA_FIR_L; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1770) + return OPCODE_AE_MULAFD32X2S_FIR_H; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1771) + return OPCODE_AE_MULAFD32X2S_FIR_L; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1772) + return OPCODE_AE_MULAFPC32X16X2RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1773) + return OPCODE_AE_MULAFPCJ32X16X2RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1774) + return OPCODE_AE_MULAFQ16X2_FIR_0; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1775) + return OPCODE_AE_MULAFQ16X2_FIR_1; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1776) + return OPCODE_AE_MULAFQ16X2_FIR_2; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1777) + return OPCODE_AE_MULAFQ16X2_FIR_3; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1778) + return OPCODE_AE_MULAPC32X16X2; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1779) + return OPCODE_AE_MULF2P32X16X4RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1780) + return OPCODE_AE_MULF2P32X16X4RS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1781) + return OPCODE_AE_MULF2P32X16X4S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1782) + return OPCODE_AE_MULFD32X16X2_FIR_HH; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1783) + return OPCODE_AE_MULFD32X16X2_FIR_HL; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1784) + return OPCODE_AE_MULFD32X16X2_FIR_LH; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1785) + return OPCODE_AE_MULFD32X16X2_FIR_LL; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1786) + return OPCODE_AE_MULFD32X2RA_FIR_H; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1787) + return OPCODE_AE_MULFD32X2RA_FIR_L; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1788) + return OPCODE_AE_MULFD32X2S_FIR_H; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1789) + return OPCODE_AE_MULFD32X2S_FIR_L; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1790) + return OPCODE_AE_MULFPC32X16X2RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1791) + return OPCODE_AE_MULFPCJ32X16X2RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1792) + return OPCODE_AE_MULFQ16X2_FIR_0; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1793) + return OPCODE_AE_MULFQ16X2_FIR_1; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1794) + return OPCODE_AE_MULFQ16X2_FIR_2; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1795) + return OPCODE_AE_MULFQ16X2_FIR_3; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1796) + return OPCODE_AE_MULPC32X16X2; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1797) + return OPCODE_AE_MULSF2P32X16X4RAS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1798) + return OPCODE_AE_MULSF2P32X16X4RS; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1799) + return OPCODE_AE_MULSF2P32X16X4S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1800) + return OPCODE_AE_MULZAAAA2Q16X8; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 433250) + return OPCODE_AE_RNG32X2; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 24 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 29 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 26 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 30 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 31 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI32R; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 25 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI24S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 27 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI32S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLI64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (insn) == 13 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (insn) == 9 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAISQ56S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get (insn) == 5 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI64S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_13_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI72; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1824 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 28 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI72; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLI24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 515 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 899 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLS24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 771 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAS24; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_19_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI16; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_19_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI16R; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLI32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 579 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 931 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLS32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 803 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAS32; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_19_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAI16S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 547 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 611 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS32S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 707 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLASQ56; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 995 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLSQ56; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 867 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRASQ56; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 643 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 963 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRLS64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 835 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAS64; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 739 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLASSQ56S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1825 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 675 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SLAS64S; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1856 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAAAAFQ32X16; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1856 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 99) + return OPCODE_AE_SHFL16X4; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1857 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULAAAAQ32X16; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1857 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 99) + return OPCODE_AE_SHFL8X8; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1858 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZAAAAFQ32X16; + if (Field_fld_ae_slot3_36_25_Slot_ae_slot3_get (insn) == 1859 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MULZAAAAQ32X16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MUL2P32X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MUL2P32X4S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MUL2P32X4T; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_MUL2Q32X16_FIR_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_MUL2Q32X16_FIR_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_MULA2P32X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_MULA2P32X4T; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_MULA2Q32X16_FIR_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MULA2Q32X16_FIR_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULAAAA2Q16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULAAAA2Q32X16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULAAF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULAAF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULAAF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULAAF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULAF2P32X4RAS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULAF2P32X4RS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 17) + return OPCODE_AE_MULASF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 18) + return OPCODE_AE_MULASF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 19) + return OPCODE_AE_MULASF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 20) + return OPCODE_AE_MULASF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 21) + return OPCODE_AE_MULF2D32X2WS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 22) + return OPCODE_AE_MULF2P32X4RAS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 23) + return OPCODE_AE_MULF2P32X4RS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 24) + return OPCODE_AE_MULFD16X16X4WS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 25) + return OPCODE_AE_MULS2P32X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 26) + return OPCODE_AE_MULS2P32X4T; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 27) + return OPCODE_AE_MULSAF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 28) + return OPCODE_AE_MULSAF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 29) + return OPCODE_AE_MULSAF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 30) + return OPCODE_AE_MULSAF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 31) + return OPCODE_AE_MULSF2P32X4RAS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 32) + return OPCODE_AE_MULSF2P32X4RS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 33) + return OPCODE_AE_MULSSF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 34) + return OPCODE_AE_MULSSF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 35) + return OPCODE_AE_MULSSF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 36) + return OPCODE_AE_MULSSF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 37) + return OPCODE_AE_MULZAAAA2Q16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 38) + return OPCODE_AE_MULZAAAA2Q32X16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 39) + return OPCODE_AE_MULZAAF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 40) + return OPCODE_AE_MULZAAF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 41) + return OPCODE_AE_MULZAAF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 42) + return OPCODE_AE_MULZAAF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 43) + return OPCODE_AE_MULZASF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 44) + return OPCODE_AE_MULZASF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 45) + return OPCODE_AE_MULZASF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 46) + return OPCODE_AE_MULZASF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 47) + return OPCODE_AE_MULZSAF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 48) + return OPCODE_AE_MULZSAF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 49) + return OPCODE_AE_MULZSAF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 50) + return OPCODE_AE_MULZSAF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 51) + return OPCODE_AE_MULZSSF2D32RA_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 52) + return OPCODE_AE_MULZSSF2D32RA_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 53) + return OPCODE_AE_MULZSSF2D32S_HH_LL; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 54) + return OPCODE_AE_MULZSSF2D32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_19_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SEL16I; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1860 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SHORTSWAP; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1572 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1540 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1828 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1796 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 611 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_TRUNCP24Q48X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1892 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_TRUNCP16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1764 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MOV; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1732 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1700 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1668 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1636 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1604 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1924 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_TRUNCQ32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 515 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_AND; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 547 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_NAND; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 579 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_OR; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 643 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_XOR; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 431202) + return OPCODE_AE_ADDANDSUBRNG16RAS_S1; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 432226) + return OPCODE_AE_ADDANDSUBRNG16RAS_S2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_19_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 4 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SEXT32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_MOVDX2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_DSEL8X8; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_DSEL16X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 13 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 34) + return OPCODE_ADD_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 13 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 66) + return OPCODE_SUB_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3588 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_NEXP01_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2564 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MKSADJ_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 428130) + return OPCODE_MKDADJ_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1988 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_DIV0_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2628 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_SQRT0_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2596 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_RECIP0_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3620 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_RSQRT0_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 427106) + return OPCODE_ADDEXP_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 426082) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 867 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MIN_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 771 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MAX_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3652 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ABS_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2724 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_NEG_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3684 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CONJC_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3716 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MULJC_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 1956 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CLSFY_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 835 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MINNUM_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 739 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MAXNUM_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 9 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ADDANDSUB_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 12 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ADDANDSUBJC_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 13 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ADD_HL_LH_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 675 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_FREXP_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2020 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_FLOATEXP_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 803 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MINNUMABS_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 707 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MAXNUMABS_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_18_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_BMAXNUM_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_18_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_BMINNUM_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_18_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_BMAXNUMABS_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_18_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_BMINNUMABS_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ABS_SX2X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 8 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_NEG_SX2X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CONJC_SX2X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MULJC_SX2X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3748 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ABS_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 430178) + return OPCODE_ADDEXP_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 429154) + return OPCODE_ADDEXPM_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2756 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CLSFY_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2660 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CONJC_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 995 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MIN_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 931 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MAX_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 963 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MINNUM_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get (insn) == 899 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MAXNUM_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 2692 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MULJC_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get (insn) == 3780 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_NEG_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 4 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_ABS_HX4X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 7 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_NEG_HX4X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 5 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_CONJC_HX4X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 57 && + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get (insn) == 6 && + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get (insn) == 2) + return OPCODE_MULJC_HX4X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 648290) + return OPCODE_AE_MUL32JS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 38) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 37) + return OPCODE_AE_ADDANDSUB32JS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 39) + return OPCODE_AE_ADDANDSUBRNG32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 40) + return OPCODE_AE_ADDANDSUBRNG32_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 41) + return OPCODE_AE_ADDANDSUBRNG32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 30816) + return OPCODE_AE_ADDRNG32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 17506) + return OPCODE_AE_SUBRNG32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 31841) + return OPCODE_AE_SAT16X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 24673) + return OPCODE_AE_ROUND32X2F64SSYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 23649) + return OPCODE_AE_ROUND32X2F64SASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 22625) + return OPCODE_AE_ROUND32X2F48SSYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 21601) + return OPCODE_AE_ROUND32X2F48SASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 18529) + return OPCODE_AE_ROUND16X4F32SSYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 17505) + return OPCODE_AE_ROUND16X4F32SASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 20577) + return OPCODE_AE_ROUND24X2F48SSYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 19553) + return OPCODE_AE_ROUND24X2F48SASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 30817) + return OPCODE_AE_ROUNDSP16Q48X2SYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 29793) + return OPCODE_AE_ROUNDSP16Q48X2ASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 12385) + return OPCODE_AE_MINABS32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 7265) + return OPCODE_AE_MAXABS32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26722) + return OPCODE_AE_ROUNDSP16F24SYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26722) + return OPCODE_AE_ROUNDSP16F24ASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 1008738) + return OPCODE_AE_SAT48S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 1041506) + return OPCODE_AE_SATQ56S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 975970) + return OPCODE_AE_SAT24S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 13409) + return OPCODE_AE_MINABS64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 8289) + return OPCODE_AE_MAXABS64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26722) + return OPCODE_AE_ROUNDSQ32F48SYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26722) + return OPCODE_AE_ROUNDSQ32F48ASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 23648) + return OPCODE_AE_ADD32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 10338) + return OPCODE_AE_SUB32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 97) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 15458) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 20576) + return OPCODE_AE_ADD16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 7266) + return OPCODE_AE_SUB16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26720) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 3169) + return OPCODE_AE_ADDSUB32_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 746594) + return OPCODE_AE_NEG32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 255074) + return OPCODE_AE_ABS32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 812130) + return OPCODE_AE_NEG32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 22624) + return OPCODE_AE_ADD24S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 9314) + return OPCODE_AE_SUB24S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 24672) + return OPCODE_AE_ADD32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 11362) + return OPCODE_AE_SUB32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 1121) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 16482) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 21600) + return OPCODE_AE_ADD16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 8290) + return OPCODE_AE_SUB16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 25696) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 2145) + return OPCODE_AE_ADDSUB32S_HL_LH; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 713826) + return OPCODE_AE_NEG24S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 222306) + return OPCODE_AE_ABS24S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 779362) + return OPCODE_AE_NEG32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 287842) + return OPCODE_AE_ABS32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 681058) + return OPCODE_AE_NEG16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 189538) + return OPCODE_AE_ABS16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 156770) + return OPCODE_AE_ABS16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 10337) + return OPCODE_AE_MIN32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 5217) + return OPCODE_AE_MAX32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 15457) + return OPCODE_AE_MINMAX32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 14433) + return OPCODE_AE_MINMAX16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 9313) + return OPCODE_AE_MIN16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 4193) + return OPCODE_AE_MAX16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 27744) + return OPCODE_AE_ADD64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 12386) + return OPCODE_AE_SUB64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 844898) + return OPCODE_AE_NEG64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 320610) + return OPCODE_AE_ABS64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 31840) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 18530) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 28768) + return OPCODE_AE_ADD64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 13410) + return OPCODE_AE_SUB64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 943202) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 418914) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 877666) + return OPCODE_AE_NEG64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 353378) + return OPCODE_AE_ABS64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 6241) + return OPCODE_AE_MAX64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 11361) + return OPCODE_AE_MIN64; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 615522) + return OPCODE_AE_MUL16JS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 517218) + return OPCODE_AE_CONJ16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 549986) + return OPCODE_AE_DIV64D32_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 582754) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_17_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 25698) + return OPCODE_AE_SAT64S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 386146) + return OPCODE_AE_ABS8S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 910434) + return OPCODE_AE_NEG8S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 29792) + return OPCODE_AE_ADD8S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 14434) + return OPCODE_AE_SUB8S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 3170) + return OPCODE_AE_SATU16X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 98) + return OPCODE_AE_SAT32X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 4194) + return OPCODE_AE_SATU32X2; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 2146) + return OPCODE_AE_SAT8X8X16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 6242) + return OPCODE_AE_SATU8X8X16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 1122) + return OPCODE_AE_SAT8X4X32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 5218) + return OPCODE_AE_SATU8X4X32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 28769) + return OPCODE_AE_ROUND8X8F16SSYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 27745) + return OPCODE_AE_ROUND8X8F16SASYM; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 26721) + return OPCODE_AE_ROUND8X4F32SSYM_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 25697) + return OPCODE_AE_ROUND8X4F32SASYM_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 36) + return OPCODE_AE_ADDANDSUB32J; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 46) + return OPCODE_AE_ADDW8; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 44) + return OPCODE_AE_ADDW16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 45) + return OPCODE_AE_ADDW32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 50) + return OPCODE_AE_SUBW8; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 48) + return OPCODE_AE_SUBW16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 49) + return OPCODE_AE_SUBW32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 34) + return OPCODE_AE_ACCW8; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 32) + return OPCODE_AE_ACCW16; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 33) + return OPCODE_AE_ACCW32; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 47) + return OPCODE_AE_ADDW8U; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 51) + return OPCODE_AE_SUBW8U; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 35) + return OPCODE_AE_ACCW8U; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MULFD16X16X4RAS; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 54) + return OPCODE_AE_SEL8X8; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 53) + return OPCODE_AE_SEL16X4; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 55) + return OPCODE_AE_SEL8X8I; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_12_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 96) + return OPCODE_AE_BMAX8X8_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_12_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 96) + return OPCODE_AE_BMAX8X8_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_12_Slot_ae_slot3_get (insn) == 2 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 96) + return OPCODE_AE_BMIN8X8_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_12_Slot_ae_slot3_get (insn) == 3 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 96) + return OPCODE_AE_BMIN8X8_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 451682) + return OPCODE_AE_ADDINV16S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get (insn) == 484450) + return OPCODE_AE_ADDINV32S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 16481) + return OPCODE_AE_MOVNEG32S_T; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 16480) + return OPCODE_AE_EXPADD16_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 18528) + return OPCODE_AE_EXPSUB16_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 17504) + return OPCODE_AE_EXPADD16_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 19552) + return OPCODE_AE_EXPSUB16_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 42) + return OPCODE_AE_ADDCEXP32_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 43) + return OPCODE_AE_ADDCEXP32_L; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 63) + return OPCODE_MUL_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 60) + return OPCODE_MADD_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 62) + return OPCODE_MSUB_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 61) + return OPCODE_MSUBN_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 59) + return OPCODE_MADDN_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 58) + return OPCODE_DIVN_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 1 && + Field_fld_ae_slot3_9_1_Slot_ae_slot3_get (insn) == 28) + return OPCODE_MULMUX_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get (insn) == 0 && + Field_fld_ae_slot3_9_3_Slot_ae_slot3_get (insn) == 7) + return OPCODE_MADDMUX_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get (insn) == 52) + return OPCODE_MADDA_S; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 19554) + return OPCODE_ADD_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 24674) + return OPCODE_SUB_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 23650) + return OPCODE_MUL_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 20578) + return OPCODE_MADD_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 22626) + return OPCODE_MSUB_H; + if (Field_fld_ae_slot3_36_30_Slot_ae_slot3_get (insn) == 58 && + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get (insn) == 21602) + return OPCODE_MSUBN_H; + return XTENSA_UNDEFINED; +} + + +/* Instruction slots. */ + +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = (insn[0] & 0xffffff); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_ae_format_Format_ae_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x300) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xc) | (((insn[0] & 0x18000000) >> 27) << 2); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf0) >> 4) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf000) >> 12) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | ((insn[1] & 0x1) << 12); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[0] & 0xc00) >> 10) << 13); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[1] & 0x6) >> 1) << 15); + slotbuf[0] = (slotbuf[0] & ~0x20000) | (((insn[2] & 0x1000000) >> 24) << 17); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x10000) >> 16) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[1] & 0x800000) >> 23) << 19); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[0] & 0x4000000) >> 26) << 20); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[1] & 0x1000000) >> 24) << 21); + slotbuf[0] = (slotbuf[0] & ~0xc00000) | (((insn[2] & 0x6000000) >> 25) << 22); + slotbuf[0] = (slotbuf[0] & ~0x7000000) | (((insn[2] & 0xe00000) >> 21) << 24); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x2000) >> 13) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x10000000) >> 28) << 28); +} + +static void +Slot_ae_format_Format_ae_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x300) | ((slotbuf[0] & 0x3) << 8); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0xc) >> 2) << 27); + insn[0] = (insn[0] & ~0xf0) | (((slotbuf[0] & 0xf0) >> 4) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0xf00) >> 8) << 12); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x1000) >> 12); + insn[0] = (insn[0] & ~0xc00) | (((slotbuf[0] & 0x6000) >> 13) << 10); + insn[1] = (insn[1] & ~0x6) | (((slotbuf[0] & 0x18000) >> 15) << 1); + insn[2] = (insn[2] & ~0x1000000) | (((slotbuf[0] & 0x20000) >> 17) << 24); + insn[2] = (insn[2] & ~0x10000) | (((slotbuf[0] & 0x40000) >> 18) << 16); + insn[1] = (insn[1] & ~0x800000) | (((slotbuf[0] & 0x80000) >> 19) << 23); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x100000) >> 20) << 26); + insn[1] = (insn[1] & ~0x1000000) | (((slotbuf[0] & 0x200000) >> 21) << 24); + insn[2] = (insn[2] & ~0x6000000) | (((slotbuf[0] & 0xc00000) >> 22) << 25); + insn[2] = (insn[2] & ~0xe00000) | (((slotbuf[0] & 0x7000000) >> 24) << 21); + insn[3] = (insn[3] & ~0x2000) | (((slotbuf[0] & 0x8000000) >> 27) << 13); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[0] & 0x10000000) >> 28) << 28); +} + +static void +Slot_ae_format_Format_ae_slot1_72_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[2] & 0xf8000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[2] & 0x60000) >> 17) << 18); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[3] & 0x7c000) >> 14) << 20); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x20000000) >> 29) << 25); +} + +static void +Slot_ae_format_Format_ae_slot1_72_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x1f00) >> 8) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[2] = (insn[2] & ~0x60000) | (((slotbuf[0] & 0xc0000) >> 18) << 17); + insn[3] = (insn[3] & ~0x7c000) | (((slotbuf[0] & 0x1f00000) >> 20) << 14); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x2000000) >> 25) << 29); +} + +static void +Slot_ae_format_Format_ae_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x1ff8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0xffc00) | (((insn[0] & 0x3ff0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[3] & 0x3e0) >> 5) << 20); + slotbuf[0] = (slotbuf[0] & ~0xe000000) | (((insn[3] & 0x380000) >> 19) << 25); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x40000000) >> 30) << 28); +} + +static void +Slot_ae_format_Format_ae_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x1ff8) | ((slotbuf[0] & 0x3ff) << 3); + insn[0] = (insn[0] & ~0x3ff0000) | (((slotbuf[0] & 0xffc00) >> 10) << 16); + insn[3] = (insn[3] & ~0x3e0) | (((slotbuf[0] & 0x1f00000) >> 20) << 5); + insn[3] = (insn[3] & ~0x380000) | (((slotbuf[0] & 0xe000000) >> 25) << 19); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x10000000) >> 28) << 30); +} + +static void +Slot_ae_format_Format_ae_slot3_45_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xfe000000) >> 25); + slotbuf[0] = (slotbuf[0] & ~0x7f80) | ((insn[2] & 0xff) << 7); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x180000) >> 19) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[3] & 0x1c00) >> 10) << 17); + slotbuf[0] = (slotbuf[0] & ~0x3ff00000) | (((insn[1] & 0x7fe000) >> 13) << 20); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0xc00000) >> 22) << 30); + slotbuf[1] = ((insn[3] & 0xf000000) >> 24); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x80000000) >> 31) << 4); +} + +static void +Slot_ae_format_Format_ae_slot3_45_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xfe000000) | ((slotbuf[0] & 0x7f) << 25); + insn[2] = (insn[2] & ~0xff) | ((slotbuf[0] & 0x7f80) >> 7); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x18000) >> 15) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0xe0000) >> 17) << 10); + insn[1] = (insn[1] & ~0x7fe000) | (((slotbuf[0] & 0x3ff00000) >> 20) << 13); + insn[3] = (insn[3] & ~0xc00000) | (((slotbuf[0] & 0xc0000000) >> 30) << 22); + insn[3] = (insn[3] & ~0xf000000) | ((slotbuf[1] & 0xf) << 24); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x10) >> 4) << 31); +} + +static void +Slot_ae_format_2_Format_ae2_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xff0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[0] & 0x18000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1c00) | ((insn[1] & 0x7) << 10); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x1000000) >> 24) << 13); + slotbuf[0] = (slotbuf[0] & ~0x1c000) | (((insn[0] & 0xe000) >> 13) << 14); + slotbuf[0] = (slotbuf[0] & ~0x20000) | (((insn[0] & 0x4000000) >> 26) << 17); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x800000) >> 23) << 18); + slotbuf[0] = (slotbuf[0] & ~0x180000) | (((insn[2] & 0x30000) >> 16) << 19); + slotbuf[0] = (slotbuf[0] & ~0xe00000) | (((insn[2] & 0x7000000) >> 24) << 21); + slotbuf[0] = (slotbuf[0] & ~0x7000000) | (((insn[1] & 0xe00000) >> 21) << 24); + slotbuf[0] = (slotbuf[0] & ~0x18000000) | (((insn[1] & 0x6000000) >> 25) << 27); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[2] & 0x100) >> 8) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[2] & 0x200) >> 9) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[2] & 0x400) >> 10) << 31); + slotbuf[1] = ((insn[2] & 0x800) >> 11); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[2] & 0x1000) >> 12) << 1); + slotbuf[1] = (slotbuf[1] & ~0x4) | (((insn[2] & 0x2000) >> 13) << 2); + slotbuf[1] = (slotbuf[1] & ~0x8) | (((insn[2] & 0x4000) >> 14) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[2] & 0x8000) >> 15) << 4); + slotbuf[1] = (slotbuf[1] & ~0x20) | (((insn[2] & 0x40000) >> 18) << 5); + slotbuf[1] = (slotbuf[1] & ~0x40) | (((insn[2] & 0x80000) >> 19) << 6); + slotbuf[1] = (slotbuf[1] & ~0x80) | (((insn[2] & 0x100000) >> 20) << 7); + slotbuf[1] = (slotbuf[1] & ~0x100) | (((insn[2] & 0x200000) >> 21) << 8); +} + +static void +Slot_ae_format_2_Format_ae2_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff0) | ((slotbuf[0] & 0xff) << 4); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x300) >> 8) << 27); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x1c00) >> 10); + insn[1] = (insn[1] & ~0x1000000) | (((slotbuf[0] & 0x2000) >> 13) << 24); + insn[0] = (insn[0] & ~0xe000) | (((slotbuf[0] & 0x1c000) >> 14) << 13); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x20000) >> 17) << 26); + insn[2] = (insn[2] & ~0x800000) | (((slotbuf[0] & 0x40000) >> 18) << 23); + insn[2] = (insn[2] & ~0x30000) | (((slotbuf[0] & 0x180000) >> 19) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0xe00000) >> 21) << 24); + insn[1] = (insn[1] & ~0xe00000) | (((slotbuf[0] & 0x7000000) >> 24) << 21); + insn[1] = (insn[1] & ~0x6000000) | (((slotbuf[0] & 0x18000000) >> 27) << 25); + insn[2] = (insn[2] & ~0x100) | (((slotbuf[0] & 0x20000000) >> 29) << 8); + insn[2] = (insn[2] & ~0x200) | (((slotbuf[0] & 0x40000000) >> 30) << 9); + insn[2] = (insn[2] & ~0x400) | (((slotbuf[0] & 0x80000000) >> 31) << 10); + insn[2] = (insn[2] & ~0x800) | ((slotbuf[1] & 0x1) << 11); + insn[2] = (insn[2] & ~0x1000) | (((slotbuf[1] & 0x2) >> 1) << 12); + insn[2] = (insn[2] & ~0x2000) | (((slotbuf[1] & 0x4) >> 2) << 13); + insn[2] = (insn[2] & ~0x4000) | (((slotbuf[1] & 0x8) >> 3) << 14); + insn[2] = (insn[2] & ~0x8000) | (((slotbuf[1] & 0x10) >> 4) << 15); + insn[2] = (insn[2] & ~0x40000) | (((slotbuf[1] & 0x20) >> 5) << 18); + insn[2] = (insn[2] & ~0x80000) | (((slotbuf[1] & 0x40) >> 6) << 19); + insn[2] = (insn[2] & ~0x100000) | (((slotbuf[1] & 0x80) >> 7) << 20); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[1] & 0x100) >> 8) << 21); +} + +static void +Slot_ae_format_2_Format_ae2_slot1_12_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x40000000) >> 30); + slotbuf[0] = (slotbuf[0] & ~0x2) | (((insn[1] & 0x20000000) >> 29) << 1); + slotbuf[0] = (slotbuf[0] & ~0xc) | (((insn[2] & 0x18000000) >> 27) << 2); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[1] & 0x80000000) >> 31) << 4); + slotbuf[0] = (slotbuf[0] & ~0xe0) | ((insn[2] & 0x7) << 5); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[2] & 0x60000000) >> 29) << 8); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | ((insn[3] & 0x1f) << 10); + slotbuf[0] = (slotbuf[0] & ~0x8000) | (((insn[0] & 0x1000) >> 12) << 15); + slotbuf[0] = (slotbuf[0] & ~0x70000) | (((insn[1] & 0xe000) >> 13) << 16); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[2] & 0x80000000) >> 31) << 19); + slotbuf[0] = (slotbuf[0] & ~0x300000) | (((insn[1] & 0x18000000) >> 27) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1c00000) | (((insn[2] & 0x38) >> 3) << 22); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[2] & 0x400000) >> 22) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x400) >> 10) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x800) >> 11) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x1000) >> 12) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x2000) >> 13) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x4000) >> 14) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x8000) >> 15) << 31); + slotbuf[1] = ((insn[3] & 0x10000) >> 16); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[3] & 0x20000) >> 17) << 1); + slotbuf[1] = (slotbuf[1] & ~0x4) | (((insn[3] & 0x40000) >> 18) << 2); + slotbuf[1] = (slotbuf[1] & ~0x8) | (((insn[3] & 0x80000) >> 19) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x100000) >> 20) << 4); +} + +static void +Slot_ae_format_2_Format_ae2_slot1_12_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x40000000) | ((slotbuf[0] & 0x1) << 30); + insn[1] = (insn[1] & ~0x20000000) | (((slotbuf[0] & 0x2) >> 1) << 29); + insn[2] = (insn[2] & ~0x18000000) | (((slotbuf[0] & 0xc) >> 2) << 27); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x10) >> 4) << 31); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0xe0) >> 5); + insn[2] = (insn[2] & ~0x60000000) | (((slotbuf[0] & 0x300) >> 8) << 29); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x7c00) >> 10); + insn[0] = (insn[0] & ~0x1000) | (((slotbuf[0] & 0x8000) >> 15) << 12); + insn[1] = (insn[1] & ~0xe000) | (((slotbuf[0] & 0x70000) >> 16) << 13); + insn[2] = (insn[2] & ~0x80000000) | (((slotbuf[0] & 0x80000) >> 19) << 31); + insn[1] = (insn[1] & ~0x18000000) | (((slotbuf[0] & 0x300000) >> 20) << 27); + insn[2] = (insn[2] & ~0x38) | (((slotbuf[0] & 0x1c00000) >> 22) << 3); + insn[2] = (insn[2] & ~0x400000) | (((slotbuf[0] & 0x2000000) >> 25) << 22); + insn[3] = (insn[3] & ~0x400) | (((slotbuf[0] & 0x4000000) >> 26) << 10); + insn[3] = (insn[3] & ~0x800) | (((slotbuf[0] & 0x8000000) >> 27) << 11); + insn[3] = (insn[3] & ~0x1000) | (((slotbuf[0] & 0x10000000) >> 28) << 12); + insn[3] = (insn[3] & ~0x2000) | (((slotbuf[0] & 0x20000000) >> 29) << 13); + insn[3] = (insn[3] & ~0x4000) | (((slotbuf[0] & 0x40000000) >> 30) << 14); + insn[3] = (insn[3] & ~0x8000) | (((slotbuf[0] & 0x80000000) >> 31) << 15); + insn[3] = (insn[3] & ~0x10000) | ((slotbuf[1] & 0x1) << 16); + insn[3] = (insn[3] & ~0x20000) | (((slotbuf[1] & 0x2) >> 1) << 17); + insn[3] = (insn[3] & ~0x40000) | (((slotbuf[1] & 0x4) >> 2) << 18); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[1] & 0x8) >> 3) << 19); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[1] & 0x10) >> 4) << 20); +} + +static void +Slot_ae_format_2_Format_ae2_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xf8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0x3e0) | (((insn[0] & 0x1f0000) >> 16) << 5); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[1] & 0x1f00) >> 8) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[3] & 0x3e0) >> 5) << 15); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[0] & 0x3e00000) >> 21) << 20); + slotbuf[0] = (slotbuf[0] & ~0x3e000000) | (((insn[1] & 0x1f0000) >> 16) << 25); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[2] & 0xc0) >> 6) << 30); + slotbuf[1] = ((insn[3] & 0x200000) >> 21); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[3] & 0x400000) >> 22) << 1); + slotbuf[1] = (slotbuf[1] & ~0x4) | (((insn[3] & 0x800000) >> 23) << 2); + slotbuf[1] = (slotbuf[1] & ~0x8) | (((insn[3] & 0x1000000) >> 24) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x2000000) >> 25) << 4); + slotbuf[1] = (slotbuf[1] & ~0x20) | (((insn[3] & 0x4000000) >> 26) << 5); + slotbuf[1] = (slotbuf[1] & ~0x40) | (((insn[3] & 0x8000000) >> 27) << 6); + slotbuf[1] = (slotbuf[1] & ~0x80) | (((insn[3] & 0x10000000) >> 28) << 7); + slotbuf[1] = (slotbuf[1] & ~0x100) | (((insn[3] & 0x20000000) >> 29) << 8); + slotbuf[1] = (slotbuf[1] & ~0x200) | (((insn[3] & 0x40000000) >> 30) << 9); + slotbuf[1] = (slotbuf[1] & ~0x400) | (((insn[3] & 0x80000000) >> 31) << 10); +} + +static void +Slot_ae_format_2_Format_ae2_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xf8) | ((slotbuf[0] & 0x1f) << 3); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0x3e0) >> 5) << 16); + insn[1] = (insn[1] & ~0x1f00) | (((slotbuf[0] & 0x7c00) >> 10) << 8); + insn[3] = (insn[3] & ~0x3e0) | (((slotbuf[0] & 0xf8000) >> 15) << 5); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x1f00000) >> 20) << 21); + insn[1] = (insn[1] & ~0x1f0000) | (((slotbuf[0] & 0x3e000000) >> 25) << 16); + insn[2] = (insn[2] & ~0xc0) | (((slotbuf[0] & 0xc0000000) >> 30) << 6); + insn[3] = (insn[3] & ~0x200000) | ((slotbuf[1] & 0x1) << 21); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[1] & 0x2) >> 1) << 22); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[1] & 0x4) >> 2) << 23); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[1] & 0x8) >> 3) << 24); + insn[3] = (insn[3] & ~0x2000000) | (((slotbuf[1] & 0x10) >> 4) << 25); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[1] & 0x20) >> 5) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[1] & 0x40) >> 6) << 27); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[1] & 0x80) >> 7) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[1] & 0x100) >> 8) << 29); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[1] & 0x200) >> 9) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x400) >> 10) << 31); +} + +static void +Slot_ae_format_3_Format_ae3_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xf00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf0) >> 4) << 4); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[0] & 0x18000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1c00) | ((insn[1] & 0x7) << 10); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x1000000) >> 24) << 13); + slotbuf[0] = (slotbuf[0] & ~0x1c000) | (((insn[0] & 0xe000) >> 13) << 14); + slotbuf[0] = (slotbuf[0] & ~0x20000) | (((insn[0] & 0x4000000) >> 26) << 17); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[1] & 0x6000) >> 13) << 18); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[0] & 0x3e00000) >> 21) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1e000000) | (((insn[1] & 0x78) >> 3) << 25); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[1] & 0x80000) >> 19) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[1] & 0x100000) >> 20) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[1] & 0x200000) >> 21) << 31); + slotbuf[1] = ((insn[1] & 0x400000) >> 22); +} + +static void +Slot_ae_format_3_Format_ae3_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf00) | ((slotbuf[0] & 0xf) << 8); + insn[0] = (insn[0] & ~0xf0) | (((slotbuf[0] & 0xf0) >> 4) << 4); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x300) >> 8) << 27); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x1c00) >> 10); + insn[1] = (insn[1] & ~0x1000000) | (((slotbuf[0] & 0x2000) >> 13) << 24); + insn[0] = (insn[0] & ~0xe000) | (((slotbuf[0] & 0x1c000) >> 14) << 13); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x20000) >> 17) << 26); + insn[1] = (insn[1] & ~0x6000) | (((slotbuf[0] & 0xc0000) >> 18) << 13); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x1f00000) >> 20) << 21); + insn[1] = (insn[1] & ~0x78) | (((slotbuf[0] & 0x1e000000) >> 25) << 3); + insn[1] = (insn[1] & ~0x80000) | (((slotbuf[0] & 0x20000000) >> 29) << 19); + insn[1] = (insn[1] & ~0x100000) | (((slotbuf[0] & 0x40000000) >> 30) << 20); + insn[1] = (insn[1] & ~0x200000) | (((slotbuf[0] & 0x80000000) >> 31) << 21); + insn[1] = (insn[1] & ~0x400000) | ((slotbuf[1] & 0x1) << 22); +} + +static void +Slot_ae_format_3_Format_ae3_slot1_12_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x1000) >> 12); + slotbuf[0] = (slotbuf[0] & ~0xe) | (((insn[1] & 0xe000000) >> 25) << 1); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[1] & 0xf00) >> 8) << 4); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[1] & 0x30000000) >> 28) << 8); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x1f0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x8000) | (((insn[1] & 0x80) >> 7) << 15); + slotbuf[0] = (slotbuf[0] & ~0x10000) | (((insn[1] & 0x1000) >> 12) << 16); + slotbuf[0] = (slotbuf[0] & ~0x1e0000) | (((insn[1] & 0x78000) >> 15) << 17); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[1] & 0x800000) >> 23) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[1] & 0x40000000) >> 30) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[1] & 0x80000000) >> 31) << 23); +} + +static void +Slot_ae_format_3_Format_ae3_slot1_12_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x1000) | ((slotbuf[0] & 0x1) << 12); + insn[1] = (insn[1] & ~0xe000000) | (((slotbuf[0] & 0xe) >> 1) << 25); + insn[1] = (insn[1] & ~0xf00) | (((slotbuf[0] & 0xf0) >> 4) << 8); + insn[1] = (insn[1] & ~0x30000000) | (((slotbuf[0] & 0x300) >> 8) << 28); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0x7c00) >> 10) << 16); + insn[1] = (insn[1] & ~0x80) | (((slotbuf[0] & 0x8000) >> 15) << 7); + insn[1] = (insn[1] & ~0x1000) | (((slotbuf[0] & 0x10000) >> 16) << 12); + insn[1] = (insn[1] & ~0x78000) | (((slotbuf[0] & 0x1e0000) >> 17) << 15); + insn[1] = (insn[1] & ~0x800000) | (((slotbuf[0] & 0x200000) >> 21) << 23); + insn[1] = (insn[1] & ~0x40000000) | (((slotbuf[0] & 0x400000) >> 22) << 30); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x800000) >> 23) << 31); +} + +static void +Slot_ae_format_5_Format_ae5_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xf00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf0) >> 4) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf000) >> 12) << 8); + slotbuf[0] = (slotbuf[0] & ~0x7000) | (((insn[0] & 0x1c000000) >> 26) << 12); + slotbuf[0] = (slotbuf[0] & ~0x38000) | ((insn[1] & 0x7) << 15); + slotbuf[0] = (slotbuf[0] & ~0x1ffc0000) | (((insn[1] & 0xffe000) >> 13) << 18); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[1] & 0x40000000) >> 30) << 29); +} + +static void +Slot_ae_format_5_Format_ae5_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf00) | ((slotbuf[0] & 0xf) << 8); + insn[0] = (insn[0] & ~0xf0) | (((slotbuf[0] & 0xf0) >> 4) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0xf00) >> 8) << 12); + insn[0] = (insn[0] & ~0x1c000000) | (((slotbuf[0] & 0x7000) >> 12) << 26); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x38000) >> 15); + insn[1] = (insn[1] & ~0xffe000) | (((slotbuf[0] & 0x1ffc0000) >> 18) << 13); + insn[1] = (insn[1] & ~0x40000000) | (((slotbuf[0] & 0x20000000) >> 29) << 30); +} + +static void +Slot_ae_format_5_Format_ae5_slot1_56_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x1000000) >> 24); + slotbuf[0] = (slotbuf[0] & ~0x2) | (((insn[1] & 0x80000000) >> 31) << 1); +} + +static void +Slot_ae_format_5_Format_ae5_slot1_56_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x1000000) | ((slotbuf[0] & 0x1) << 24); + insn[1] = (insn[1] & ~0x80000000) | (((slotbuf[0] & 0x2) >> 1) << 31); +} + +static void +Slot_ae_format_5_Format_ae5_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x1ff8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0xffc00) | (((insn[0] & 0x3ff0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[1] & 0x3e000000) >> 25) << 20); +} + +static void +Slot_ae_format_5_Format_ae5_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x1ff8) | ((slotbuf[0] & 0x3ff) << 3); + insn[0] = (insn[0] & ~0x3ff0000) | (((slotbuf[0] & 0xffc00) >> 10) << 16); + insn[1] = (insn[1] & ~0x3e000000) | (((slotbuf[0] & 0x1f00000) >> 20) << 25); +} + +static void +Slot_ae_format_6_Format_ae6_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xf0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[2] & 0x800000) >> 23) << 4); + slotbuf[0] = (slotbuf[0] & ~0x60) | (((insn[0] & 0x18000000) >> 27) << 5); + slotbuf[0] = (slotbuf[0] & ~0x380) | ((insn[1] & 0x7) << 7); + slotbuf[0] = (slotbuf[0] & ~0x3c00) | (((insn[0] & 0xf000) >> 12) << 10); + slotbuf[0] = (slotbuf[0] & ~0x4000) | (((insn[0] & 0x4000000) >> 26) << 14); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x30000) >> 16) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[2] & 0x7000000) >> 24) << 17); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[1] & 0x1000) >> 12) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1e00000) | (((insn[2] & 0xf00) >> 8) << 21); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x8000) >> 15) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x10000) >> 16) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x20000) >> 17) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x40000) >> 18) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x80000) >> 19) << 29); +} + +static void +Slot_ae_format_6_Format_ae6_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0) | ((slotbuf[0] & 0xf) << 4); + insn[2] = (insn[2] & ~0x800000) | (((slotbuf[0] & 0x10) >> 4) << 23); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x60) >> 5) << 27); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x380) >> 7); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0x3c00) >> 10) << 12); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x4000) >> 14) << 26); + insn[2] = (insn[2] & ~0x30000) | (((slotbuf[0] & 0x18000) >> 15) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0xe0000) >> 17) << 24); + insn[1] = (insn[1] & ~0x1000) | (((slotbuf[0] & 0x100000) >> 20) << 12); + insn[2] = (insn[2] & ~0xf00) | (((slotbuf[0] & 0x1e00000) >> 21) << 8); + insn[3] = (insn[3] & ~0x8000) | (((slotbuf[0] & 0x2000000) >> 25) << 15); + insn[3] = (insn[3] & ~0x10000) | (((slotbuf[0] & 0x4000000) >> 26) << 16); + insn[3] = (insn[3] & ~0x20000) | (((slotbuf[0] & 0x8000000) >> 27) << 17); + insn[3] = (insn[3] & ~0x40000) | (((slotbuf[0] & 0x10000000) >> 28) << 18); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[0] & 0x20000000) >> 29) << 19); +} + +static void +Slot_ae_format_6_Format_ae6_slot1_57_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xc0000000) >> 30); + slotbuf[0] = (slotbuf[0] & ~0x1c) | ((insn[2] & 0x7) << 2); + slotbuf[0] = (slotbuf[0] & ~0x3e0) | (((insn[1] & 0x3e000000) >> 25) << 5); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[2] & 0xf8000000) >> 27) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | ((insn[3] & 0x1f) << 15); + slotbuf[0] = (slotbuf[0] & ~0xf00000) | (((insn[2] & 0xf000) >> 12) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x100000) >> 20) << 24); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x200000) >> 21) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x400000) >> 22) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x800000) >> 23) << 27); +} + +static void +Slot_ae_format_6_Format_ae6_slot1_57_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xc0000000) | ((slotbuf[0] & 0x3) << 30); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0x1c) >> 2); + insn[1] = (insn[1] & ~0x3e000000) | (((slotbuf[0] & 0x3e0) >> 5) << 25); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x7c00) >> 10) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0xf8000) >> 15); + insn[2] = (insn[2] & ~0xf000) | (((slotbuf[0] & 0xf00000) >> 20) << 12); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[0] & 0x1000000) >> 24) << 20); + insn[3] = (insn[3] & ~0x200000) | (((slotbuf[0] & 0x2000000) >> 25) << 21); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[0] & 0x4000000) >> 26) << 22); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[0] & 0x8000000) >> 27) << 23); +} + +static void +Slot_ae_format_6_Format_ae6_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xf8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0x7fe0) | (((insn[0] & 0x3ff0000) >> 16) << 5); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[3] & 0x3e0) >> 5) << 15); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[2] & 0x40000) >> 18) << 20); + slotbuf[0] = (slotbuf[0] & ~0x200000) | (((insn[3] & 0x1000000) >> 24) << 21); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x2000000) >> 25) << 22); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x4000000) >> 26) << 23); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x8000000) >> 27) << 24); +} + +static void +Slot_ae_format_6_Format_ae6_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xf8) | ((slotbuf[0] & 0x1f) << 3); + insn[0] = (insn[0] & ~0x3ff0000) | (((slotbuf[0] & 0x7fe0) >> 5) << 16); + insn[3] = (insn[3] & ~0x3e0) | (((slotbuf[0] & 0xf8000) >> 15) << 5); + insn[2] = (insn[2] & ~0x40000) | (((slotbuf[0] & 0x100000) >> 20) << 18); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x200000) >> 21) << 24); + insn[3] = (insn[3] & ~0x2000000) | (((slotbuf[0] & 0x400000) >> 22) << 25); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x800000) >> 23) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x1000000) >> 24) << 27); +} + +static void +Slot_ae_format_6_Format_ae6_slot3_8_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x3e000) >> 13); + slotbuf[0] = (slotbuf[0] & ~0x60) | (((insn[2] & 0x180000) >> 19) << 5); + slotbuf[0] = (slotbuf[0] & ~0x380) | (((insn[3] & 0x1c00) >> 10) << 7); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[2] & 0xf8) >> 3) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[1] & 0x7c0000) >> 18) << 15); + slotbuf[0] = (slotbuf[0] & ~0x700000) | (((insn[0] & 0x700) >> 8) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1800000) | (((insn[1] & 0x1800000) >> 23) << 23); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[0] & 0x800) >> 11) << 25); + slotbuf[0] = (slotbuf[0] & ~0x3c000000) | (((insn[1] & 0xf00) >> 8) << 26); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[2] & 0x600000) >> 21) << 30); + slotbuf[1] = ((insn[3] & 0x6000) >> 13); + slotbuf[1] = (slotbuf[1] & ~0x4) | (((insn[3] & 0x10000000) >> 28) << 2); + slotbuf[1] = (slotbuf[1] & ~0x8) | (((insn[3] & 0x20000000) >> 29) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x40000000) >> 30) << 4); + slotbuf[1] = (slotbuf[1] & ~0x20) | (((insn[3] & 0x80000000) >> 31) << 5); +} + +static void +Slot_ae_format_6_Format_ae6_slot3_8_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x3e000) | ((slotbuf[0] & 0x1f) << 13); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x60) >> 5) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0x380) >> 7) << 10); + insn[2] = (insn[2] & ~0xf8) | (((slotbuf[0] & 0x7c00) >> 10) << 3); + insn[1] = (insn[1] & ~0x7c0000) | (((slotbuf[0] & 0xf8000) >> 15) << 18); + insn[0] = (insn[0] & ~0x700) | (((slotbuf[0] & 0x700000) >> 20) << 8); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x1800000) >> 23) << 23); + insn[0] = (insn[0] & ~0x800) | (((slotbuf[0] & 0x2000000) >> 25) << 11); + insn[1] = (insn[1] & ~0xf00) | (((slotbuf[0] & 0x3c000000) >> 26) << 8); + insn[2] = (insn[2] & ~0x600000) | (((slotbuf[0] & 0xc0000000) >> 30) << 21); + insn[3] = (insn[3] & ~0x6000) | ((slotbuf[1] & 0x3) << 13); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[1] & 0x4) >> 2) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[1] & 0x8) >> 3) << 29); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[1] & 0x10) >> 4) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x20) >> 5) << 31); +} + +static void +Slot_ae_format_7_Format_ae7_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x3f0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x3c0) | (((insn[0] & 0xf000) >> 12) << 6); + slotbuf[0] = (slotbuf[0] & ~0x1c00) | (((insn[2] & 0xe00000) >> 21) << 10); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[2] & 0x30000) >> 16) << 13); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[2] & 0x7000000) >> 24) << 15); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[0] & 0xc00) >> 10) << 18); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[0] & 0x4000000) >> 26) << 20); + slotbuf[0] = (slotbuf[0] & ~0x600000) | (((insn[1] & 0x1800000) >> 23) << 21); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x20000000) >> 29) << 23); +} + +static void +Slot_ae_format_7_Format_ae7_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3f0) | ((slotbuf[0] & 0x3f) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0x3c0) >> 6) << 12); + insn[2] = (insn[2] & ~0xe00000) | (((slotbuf[0] & 0x1c00) >> 10) << 21); + insn[2] = (insn[2] & ~0x30000) | (((slotbuf[0] & 0x6000) >> 13) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0x38000) >> 15) << 24); + insn[0] = (insn[0] & ~0xc00) | (((slotbuf[0] & 0xc0000) >> 18) << 10); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x100000) >> 20) << 26); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x600000) >> 21) << 23); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x800000) >> 23) << 29); +} + +static void +Slot_ae_format_7_Format_ae7_slot1_72_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xf000) >> 12); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[2] & 0xf00) >> 8) << 4); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[2] & 0xf8000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x40000) >> 18) << 18); + slotbuf[0] = (slotbuf[0] & ~0x780000) | (((insn[3] & 0x1e000) >> 13) << 19); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x40000000) >> 30) << 23); +} + +static void +Slot_ae_format_7_Format_ae7_slot1_72_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xf000) | ((slotbuf[0] & 0xf) << 12); + insn[2] = (insn[2] & ~0xf00) | (((slotbuf[0] & 0xf0) >> 4) << 8); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x1f00) >> 8) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[2] = (insn[2] & ~0x40000) | (((slotbuf[0] & 0x40000) >> 18) << 18); + insn[3] = (insn[3] & ~0x1e000) | (((slotbuf[0] & 0x780000) >> 19) << 13); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x800000) >> 23) << 30); +} + +static void +Slot_ae_format_7_Format_ae7_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0x1ff8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x3e00000) >> 21) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[0] & 0x1f0000) >> 16) << 15); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[3] & 0x3e0) >> 5) << 20); + slotbuf[0] = (slotbuf[0] & ~0x6000000) | (((insn[0] & 0x18000000) >> 27) << 25); + slotbuf[0] = (slotbuf[0] & ~0x38000000) | ((insn[1] & 0x7) << 27); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0x60000) >> 17) << 30); + slotbuf[1] = ((insn[3] & 0x780000) >> 19); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[3] & 0x80000000) >> 31) << 4); +} + +static void +Slot_ae_format_7_Format_ae7_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x1ff8) | ((slotbuf[0] & 0x3ff) << 3); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x7c00) >> 10) << 21); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0xf8000) >> 15) << 16); + insn[3] = (insn[3] & ~0x3e0) | (((slotbuf[0] & 0x1f00000) >> 20) << 5); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x6000000) >> 25) << 27); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x38000000) >> 27); + insn[3] = (insn[3] & ~0x60000) | (((slotbuf[0] & 0xc0000000) >> 30) << 17); + insn[3] = (insn[3] & ~0x780000) | ((slotbuf[1] & 0xf) << 19); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x10) >> 4) << 31); +} + +static void +Slot_ae_format_7_Format_ae7_slot3_45_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xfe000000) >> 25); + slotbuf[0] = (slotbuf[0] & ~0x7f80) | ((insn[2] & 0xff) << 7); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x180000) >> 19) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[3] & 0x1c00) >> 10) << 17); + slotbuf[0] = (slotbuf[0] & ~0x3ff00000) | (((insn[1] & 0x7fe000) >> 13) << 20); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0x1800000) >> 23) << 30); + slotbuf[1] = ((insn[3] & 0x1e000000) >> 25); +} + +static void +Slot_ae_format_7_Format_ae7_slot3_45_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xfe000000) | ((slotbuf[0] & 0x7f) << 25); + insn[2] = (insn[2] & ~0xff) | ((slotbuf[0] & 0x7f80) >> 7); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x18000) >> 15) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0xe0000) >> 17) << 10); + insn[1] = (insn[1] & ~0x7fe000) | (((slotbuf[0] & 0x3ff00000) >> 20) << 13); + insn[3] = (insn[3] & ~0x1800000) | (((slotbuf[0] & 0xc0000000) >> 30) << 23); + insn[3] = (insn[3] & ~0x1e000000) | ((slotbuf[1] & 0xf) << 25); +} + +static void +Slot_ae_format_8_Format_ae8_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xf0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x70) | (((insn[2] & 0x3800000) >> 23) << 4); + slotbuf[0] = (slotbuf[0] & ~0x80) | (((insn[0] & 0x2000) >> 13) << 7); + slotbuf[0] = (slotbuf[0] & ~0x100) | (((insn[0] & 0x100) >> 8) << 8); + slotbuf[0] = (slotbuf[0] & ~0x600) | (((insn[0] & 0x18000000) >> 27) << 9); + slotbuf[0] = (slotbuf[0] & ~0x800) | ((insn[1] & 0x1) << 11); + slotbuf[0] = (slotbuf[0] & ~0x3000) | (((insn[1] & 0x1800000) >> 23) << 12); + slotbuf[0] = (slotbuf[0] & ~0x4000) | (((insn[0] & 0x200) >> 9) << 14); + slotbuf[0] = (slotbuf[0] & ~0x8000) | (((insn[0] & 0x1000) >> 12) << 15); + slotbuf[0] = (slotbuf[0] & ~0x30000) | (((insn[0] & 0xc00) >> 10) << 16); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x10000) >> 16) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[2] & 0x200000) >> 21) << 19); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[1] & 0x1000) >> 12) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1e00000) | (((insn[1] & 0x1e000000) >> 25) << 21); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[2] & 0x400000) >> 22) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x10000) >> 16) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x20000) >> 17) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x40000) >> 18) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x80000) >> 19) << 29); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x100000) >> 20) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x200000) >> 21) << 31); +} + +static void +Slot_ae_format_8_Format_ae8_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0) | ((slotbuf[0] & 0xf) << 4); + insn[2] = (insn[2] & ~0x3800000) | (((slotbuf[0] & 0x70) >> 4) << 23); + insn[0] = (insn[0] & ~0x2000) | (((slotbuf[0] & 0x80) >> 7) << 13); + insn[0] = (insn[0] & ~0x100) | (((slotbuf[0] & 0x100) >> 8) << 8); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x600) >> 9) << 27); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x800) >> 11); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x3000) >> 12) << 23); + insn[0] = (insn[0] & ~0x200) | (((slotbuf[0] & 0x4000) >> 14) << 9); + insn[0] = (insn[0] & ~0x1000) | (((slotbuf[0] & 0x8000) >> 15) << 12); + insn[0] = (insn[0] & ~0xc00) | (((slotbuf[0] & 0x30000) >> 16) << 10); + insn[2] = (insn[2] & ~0x10000) | (((slotbuf[0] & 0x40000) >> 18) << 16); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[0] & 0x80000) >> 19) << 21); + insn[1] = (insn[1] & ~0x1000) | (((slotbuf[0] & 0x100000) >> 20) << 12); + insn[1] = (insn[1] & ~0x1e000000) | (((slotbuf[0] & 0x1e00000) >> 21) << 25); + insn[2] = (insn[2] & ~0x400000) | (((slotbuf[0] & 0x2000000) >> 25) << 22); + insn[3] = (insn[3] & ~0x10000) | (((slotbuf[0] & 0x4000000) >> 26) << 16); + insn[3] = (insn[3] & ~0x20000) | (((slotbuf[0] & 0x8000000) >> 27) << 17); + insn[3] = (insn[3] & ~0x40000) | (((slotbuf[0] & 0x10000000) >> 28) << 18); + insn[3] = (insn[3] & ~0x80000) | (((slotbuf[0] & 0x20000000) >> 29) << 19); + insn[3] = (insn[3] & ~0x100000) | (((slotbuf[0] & 0x40000000) >> 30) << 20); + insn[3] = (insn[3] & ~0x200000) | (((slotbuf[0] & 0x80000000) >> 31) << 21); +} + +static void +Slot_ae_format_8_Format_ae8_slot1_14_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x300) | (((insn[0] & 0xc000) >> 14) << 8); + slotbuf[0] = (slotbuf[0] & ~0x400) | (((insn[1] & 0x2) >> 1) << 10); + slotbuf[0] = (slotbuf[0] & ~0x800) | (((insn[1] & 0x8) >> 3) << 11); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[2] & 0x80000000) >> 31) << 12); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[2] & 0x60000) >> 17) << 18); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[2] & 0x4000000) >> 26) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1e00000) | (((insn[3] & 0x1e0) >> 5) << 21); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x400000) >> 22) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x800000) >> 23) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x1000000) >> 24) << 27); + slotbuf[0] = (slotbuf[0] & ~0x10000000) | (((insn[3] & 0x2000000) >> 25) << 28); + slotbuf[0] = (slotbuf[0] & ~0x20000000) | (((insn[3] & 0x4000000) >> 26) << 29); +} + +static void +Slot_ae_format_8_Format_ae8_slot1_14_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[0] = (insn[0] & ~0xc000) | (((slotbuf[0] & 0x300) >> 8) << 14); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x400) >> 10) << 1); + insn[1] = (insn[1] & ~0x8) | (((slotbuf[0] & 0x800) >> 11) << 3); + insn[2] = (insn[2] & ~0x80000000) | (((slotbuf[0] & 0x1000) >> 12) << 31); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[2] = (insn[2] & ~0x60000) | (((slotbuf[0] & 0xc0000) >> 18) << 17); + insn[2] = (insn[2] & ~0x4000000) | (((slotbuf[0] & 0x100000) >> 20) << 26); + insn[3] = (insn[3] & ~0x1e0) | (((slotbuf[0] & 0x1e00000) >> 21) << 5); + insn[3] = (insn[3] & ~0x400000) | (((slotbuf[0] & 0x2000000) >> 25) << 22); + insn[3] = (insn[3] & ~0x800000) | (((slotbuf[0] & 0x4000000) >> 26) << 23); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x8000000) >> 27) << 24); + insn[3] = (insn[3] & ~0x2000000) | (((slotbuf[0] & 0x10000000) >> 28) << 25); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x20000000) >> 29) << 26); +} + +static void +Slot_ae_format_8_Format_ae8_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xc0000000) >> 30); + slotbuf[0] = (slotbuf[0] & ~0x3fc) | ((insn[2] & 0xff) << 2); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x3e00000) >> 21) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[0] & 0x1f0000) >> 16) << 15); + slotbuf[0] = (slotbuf[0] & ~0xf00000) | (((insn[1] & 0xf0) >> 4) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[1] & 0x800) >> 11) << 24); + slotbuf[0] = (slotbuf[0] & ~0x6000000) | (((insn[2] & 0x180000) >> 19) << 25); + slotbuf[0] = (slotbuf[0] & ~0x38000000) | (((insn[3] & 0x1c00) >> 10) << 27); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[1] & 0xc0000) >> 18) << 30); + slotbuf[1] = ((insn[1] & 0x700000) >> 20); + slotbuf[1] = (slotbuf[1] & ~0x8) | (((insn[0] & 0x4000000) >> 26) << 3); + slotbuf[1] = (slotbuf[1] & ~0x10) | (((insn[1] & 0x4) >> 2) << 4); + slotbuf[1] = (slotbuf[1] & ~0xe0) | (((insn[1] & 0x700) >> 8) << 5); + slotbuf[1] = (slotbuf[1] & ~0x1f00) | (((insn[1] & 0x3e000) >> 13) << 8); + slotbuf[1] = (slotbuf[1] & ~0x2000) | (((insn[1] & 0x20000000) >> 29) << 13); + slotbuf[1] = (slotbuf[1] & ~0x3c000) | (((insn[2] & 0x78000000) >> 27) << 14); + slotbuf[1] = (slotbuf[1] & ~0x40000) | (((insn[3] & 0x200) >> 9) << 18); + slotbuf[1] = (slotbuf[1] & ~0x380000) | (((insn[3] & 0xe000) >> 13) << 19); + slotbuf[1] = (slotbuf[1] & ~0x400000) | (((insn[3] & 0x8000000) >> 27) << 22); + slotbuf[1] = (slotbuf[1] & ~0x800000) | (((insn[3] & 0x10000000) >> 28) << 23); + slotbuf[1] = (slotbuf[1] & ~0x1000000) | (((insn[3] & 0x20000000) >> 29) << 24); + slotbuf[1] = (slotbuf[1] & ~0x2000000) | (((insn[3] & 0x40000000) >> 30) << 25); + slotbuf[1] = (slotbuf[1] & ~0x4000000) | (((insn[3] & 0x80000000) >> 31) << 26); +} + +static void +Slot_ae_format_8_Format_ae8_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xc0000000) | ((slotbuf[0] & 0x3) << 30); + insn[2] = (insn[2] & ~0xff) | ((slotbuf[0] & 0x3fc) >> 2); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x7c00) >> 10) << 21); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0xf8000) >> 15) << 16); + insn[1] = (insn[1] & ~0xf0) | (((slotbuf[0] & 0xf00000) >> 20) << 4); + insn[1] = (insn[1] & ~0x800) | (((slotbuf[0] & 0x1000000) >> 24) << 11); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x6000000) >> 25) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0x38000000) >> 27) << 10); + insn[1] = (insn[1] & ~0xc0000) | (((slotbuf[0] & 0xc0000000) >> 30) << 18); + insn[1] = (insn[1] & ~0x700000) | ((slotbuf[1] & 0x7) << 20); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[1] & 0x8) >> 3) << 26); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[1] & 0x10) >> 4) << 2); + insn[1] = (insn[1] & ~0x700) | (((slotbuf[1] & 0xe0) >> 5) << 8); + insn[1] = (insn[1] & ~0x3e000) | (((slotbuf[1] & 0x1f00) >> 8) << 13); + insn[1] = (insn[1] & ~0x20000000) | (((slotbuf[1] & 0x2000) >> 13) << 29); + insn[2] = (insn[2] & ~0x78000000) | (((slotbuf[1] & 0x3c000) >> 14) << 27); + insn[3] = (insn[3] & ~0x200) | (((slotbuf[1] & 0x40000) >> 18) << 9); + insn[3] = (insn[3] & ~0xe000) | (((slotbuf[1] & 0x380000) >> 19) << 13); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[1] & 0x400000) >> 22) << 27); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[1] & 0x800000) >> 23) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[1] & 0x1000000) >> 24) << 29); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[1] & 0x2000000) >> 25) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[1] & 0x4000000) >> 26) << 31); +} + +static void +Slot_ae_format_9_Format_ae9_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0xfff0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x7000) | (((insn[0] & 0x1c000000) >> 26) << 12); + slotbuf[0] = (slotbuf[0] & ~0x38000) | ((insn[1] & 0x7) << 15); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x10000) >> 16) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[2] & 0x200000) >> 21) << 19); + slotbuf[0] = (slotbuf[0] & ~0x300000) | (((insn[1] & 0x1800000) >> 23) << 20); + slotbuf[0] = (slotbuf[0] & ~0x3c00000) | (((insn[2] & 0x3c00000) >> 22) << 22); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x1000000) >> 24) << 26); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x2000000) >> 25) << 27); +} + +static void +Slot_ae_format_9_Format_ae9_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xfff0) | ((slotbuf[0] & 0xfff) << 4); + insn[0] = (insn[0] & ~0x1c000000) | (((slotbuf[0] & 0x7000) >> 12) << 26); + insn[1] = (insn[1] & ~0x7) | ((slotbuf[0] & 0x38000) >> 15); + insn[2] = (insn[2] & ~0x10000) | (((slotbuf[0] & 0x40000) >> 18) << 16); + insn[2] = (insn[2] & ~0x200000) | (((slotbuf[0] & 0x80000) >> 19) << 21); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x300000) >> 20) << 23); + insn[2] = (insn[2] & ~0x3c00000) | (((slotbuf[0] & 0x3c00000) >> 22) << 22); + insn[3] = (insn[3] & ~0x1000000) | (((slotbuf[0] & 0x4000000) >> 26) << 24); + insn[3] = (insn[3] & ~0x2000000) | (((slotbuf[0] & 0x8000000) >> 27) << 25); +} + +static void +Slot_ae_format_9_Format_ae9_slot1_72_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[2] & 0xf8000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc0000) | (((insn[2] & 0x60000) >> 17) << 18); + slotbuf[0] = (slotbuf[0] & ~0x100000) | (((insn[2] & 0x4000000) >> 26) << 20); + slotbuf[0] = (slotbuf[0] & ~0x1e00000) | (((insn[3] & 0x1e000) >> 13) << 21); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x4000000) >> 26) << 25); + slotbuf[0] = (slotbuf[0] & ~0x4000000) | (((insn[3] & 0x8000000) >> 27) << 26); +} + +static void +Slot_ae_format_9_Format_ae9_slot1_72_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x1f00) >> 8) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[2] = (insn[2] & ~0x60000) | (((slotbuf[0] & 0xc0000) >> 18) << 17); + insn[2] = (insn[2] & ~0x4000000) | (((slotbuf[0] & 0x100000) >> 20) << 26); + insn[3] = (insn[3] & ~0x1e000) | (((slotbuf[0] & 0x1e00000) >> 21) << 13); + insn[3] = (insn[3] & ~0x4000000) | (((slotbuf[0] & 0x2000000) >> 25) << 26); + insn[3] = (insn[3] & ~0x8000000) | (((slotbuf[0] & 0x4000000) >> 26) << 27); +} + +static void +Slot_ae_format_9_Format_ae9_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[3] & 0x3e0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x60) | (((insn[1] & 0xc0000000) >> 30) << 5); + slotbuf[0] = (slotbuf[0] & ~0x380) | ((insn[2] & 0x7) << 7); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x1f0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1ff8000) | (((insn[1] & 0x1ff8) >> 3) << 15); + slotbuf[0] = (slotbuf[0] & ~0x3e000000) | (((insn[0] & 0x3e00000) >> 21) << 25); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0x60000) >> 17) << 30); + slotbuf[1] = ((insn[3] & 0x10000000) >> 28); + slotbuf[1] = (slotbuf[1] & ~0x2) | (((insn[3] & 0x20000000) >> 29) << 1); +} + +static void +Slot_ae_format_9_Format_ae9_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[3] = (insn[3] & ~0x3e0) | ((slotbuf[0] & 0x1f) << 5); + insn[1] = (insn[1] & ~0xc0000000) | (((slotbuf[0] & 0x60) >> 5) << 30); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0x380) >> 7); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0x7c00) >> 10) << 16); + insn[1] = (insn[1] & ~0x1ff8) | (((slotbuf[0] & 0x1ff8000) >> 15) << 3); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x3e000000) >> 25) << 21); + insn[3] = (insn[3] & ~0x60000) | (((slotbuf[0] & 0xc0000000) >> 30) << 17); + insn[3] = (insn[3] & ~0x10000000) | ((slotbuf[1] & 0x1) << 28); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[1] & 0x2) >> 1) << 29); +} + +static void +Slot_ae_format_9_Format_ae9_slot3_45_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xf8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0x3e0) | (((insn[1] & 0x3e000000) >> 25) << 5); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[1] & 0x7c0000) >> 18) << 10); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x180000) >> 19) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[3] & 0x1c00) >> 10) << 17); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[1] & 0x3e000) >> 13) << 20); + slotbuf[0] = (slotbuf[0] & ~0x3e000000) | (((insn[3] & 0xf80000) >> 19) << 25); + slotbuf[0] = (slotbuf[0] & ~0x40000000) | (((insn[3] & 0x40000000) >> 30) << 30); + slotbuf[0] = (slotbuf[0] & ~0x80000000) | (((insn[3] & 0x80000000) >> 31) << 31); +} + +static void +Slot_ae_format_9_Format_ae9_slot3_45_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xf8) | ((slotbuf[0] & 0x1f) << 3); + insn[1] = (insn[1] & ~0x3e000000) | (((slotbuf[0] & 0x3e0) >> 5) << 25); + insn[1] = (insn[1] & ~0x7c0000) | (((slotbuf[0] & 0x7c00) >> 10) << 18); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x18000) >> 15) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0xe0000) >> 17) << 10); + insn[1] = (insn[1] & ~0x3e000) | (((slotbuf[0] & 0x1f00000) >> 20) << 13); + insn[3] = (insn[3] & ~0xf80000) | (((slotbuf[0] & 0x3e000000) >> 25) << 19); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x40000000) >> 30) << 30); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x80000000) >> 31) << 31); +} + +static void +Slot_ae_format_10_Format_ae10_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x3f0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x3c0) | (((insn[0] & 0xf000) >> 12) << 6); + slotbuf[0] = (slotbuf[0] & ~0xc00) | (((insn[0] & 0xc00) >> 10) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[2] & 0x800000) >> 23) << 12); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[2] & 0x30000) >> 16) << 13); + slotbuf[0] = (slotbuf[0] & ~0x38000) | (((insn[2] & 0x7000000) >> 24) << 15); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[1] & 0x2) >> 1) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[0] & 0x4000000) >> 26) << 19); + slotbuf[0] = (slotbuf[0] & ~0x300000) | (((insn[2] & 0x600000) >> 21) << 20); + slotbuf[0] = (slotbuf[0] & ~0xc00000) | (((insn[3] & 0x6000) >> 13) << 22); + slotbuf[0] = (slotbuf[0] & ~0x1000000) | (((insn[3] & 0x40000000) >> 30) << 24); +} + +static void +Slot_ae_format_10_Format_ae10_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3f0) | ((slotbuf[0] & 0x3f) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0x3c0) >> 6) << 12); + insn[0] = (insn[0] & ~0xc00) | (((slotbuf[0] & 0xc00) >> 10) << 10); + insn[2] = (insn[2] & ~0x800000) | (((slotbuf[0] & 0x1000) >> 12) << 23); + insn[2] = (insn[2] & ~0x30000) | (((slotbuf[0] & 0x6000) >> 13) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0x38000) >> 15) << 24); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x40000) >> 18) << 1); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x80000) >> 19) << 26); + insn[2] = (insn[2] & ~0x600000) | (((slotbuf[0] & 0x300000) >> 20) << 21); + insn[3] = (insn[3] & ~0x6000) | (((slotbuf[0] & 0xc00000) >> 22) << 13); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x1000000) >> 24) << 30); +} + +static void +Slot_ae_format_10_Format_ae10_slot1_34_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[2] & 0xf8000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[1] & 0x4) >> 2) << 18); + slotbuf[0] = (slotbuf[0] & ~0x80000) | (((insn[2] & 0x40000) >> 18) << 19); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[3] & 0xf8000) >> 15) << 20); + slotbuf[0] = (slotbuf[0] & ~0x2000000) | (((insn[3] & 0x80000000) >> 31) << 25); +} + +static void +Slot_ae_format_10_Format_ae10_slot1_34_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x1f00) >> 8) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[0] & 0x40000) >> 18) << 2); + insn[2] = (insn[2] & ~0x40000) | (((slotbuf[0] & 0x80000) >> 19) << 18); + insn[3] = (insn[3] & ~0xf8000) | (((slotbuf[0] & 0x1f00000) >> 20) << 15); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x2000000) >> 25) << 31); +} + +static void +Slot_ae_format_10_Format_ae10_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[3] & 0x3e0) >> 5); + slotbuf[0] = (slotbuf[0] & ~0x60) | (((insn[1] & 0xc0000000) >> 30) << 5); + slotbuf[0] = (slotbuf[0] & ~0x380) | ((insn[2] & 0x7) << 7); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[0] & 0x1f0000) >> 16) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1ff8000) | (((insn[1] & 0x1ff8) >> 3) << 15); + slotbuf[0] = (slotbuf[0] & ~0x3e000000) | (((insn[0] & 0x3e00000) >> 21) << 25); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0x300000) >> 20) << 30); + slotbuf[1] = ((insn[3] & 0x1c00000) >> 22); +} + +static void +Slot_ae_format_10_Format_ae10_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[3] = (insn[3] & ~0x3e0) | ((slotbuf[0] & 0x1f) << 5); + insn[1] = (insn[1] & ~0xc0000000) | (((slotbuf[0] & 0x60) >> 5) << 30); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0x380) >> 7); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0x7c00) >> 10) << 16); + insn[1] = (insn[1] & ~0x1ff8) | (((slotbuf[0] & 0x1ff8000) >> 15) << 3); + insn[0] = (insn[0] & ~0x3e00000) | (((slotbuf[0] & 0x3e000000) >> 25) << 21); + insn[3] = (insn[3] & ~0x300000) | (((slotbuf[0] & 0xc0000000) >> 30) << 20); + insn[3] = (insn[3] & ~0x1c00000) | ((slotbuf[1] & 0x7) << 22); +} + +static void +Slot_ae_format_10_Format_ae10_slot3_27_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xf8) >> 3); + slotbuf[0] = (slotbuf[0] & ~0x3e0) | (((insn[1] & 0x3e000000) >> 25) << 5); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[1] & 0x7c0000) >> 18) << 10); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x180000) >> 19) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[3] & 0x1c00) >> 10) << 17); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[1] & 0x3e000) >> 13) << 20); + slotbuf[0] = (slotbuf[0] & ~0x6000000) | (((insn[0] & 0x18000000) >> 27) << 25); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | ((insn[1] & 0x1) << 27); + slotbuf[0] = (slotbuf[0] & ~0x30000000) | (((insn[1] & 0x1800000) >> 23) << 28); + slotbuf[0] = (slotbuf[0] & ~0xc0000000) | (((insn[3] & 0x6000000) >> 25) << 30); + slotbuf[1] = ((insn[3] & 0x38000000) >> 27); +} + +static void +Slot_ae_format_10_Format_ae10_slot3_27_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xf8) | ((slotbuf[0] & 0x1f) << 3); + insn[1] = (insn[1] & ~0x3e000000) | (((slotbuf[0] & 0x3e0) >> 5) << 25); + insn[1] = (insn[1] & ~0x7c0000) | (((slotbuf[0] & 0x7c00) >> 10) << 18); + insn[2] = (insn[2] & ~0x180000) | (((slotbuf[0] & 0x18000) >> 15) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0xe0000) >> 17) << 10); + insn[1] = (insn[1] & ~0x3e000) | (((slotbuf[0] & 0x1f00000) >> 20) << 13); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x6000000) >> 25) << 27); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x8000000) >> 27); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x30000000) >> 28) << 23); + insn[3] = (insn[3] & ~0x6000000) | (((slotbuf[0] & 0xc0000000) >> 30) << 25); + insn[3] = (insn[3] & ~0x38000000) | ((slotbuf[1] & 0x7) << 27); +} + +static void +Slot_ae_format_4_Format_ae4_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x3f0) >> 4); + slotbuf[0] = (slotbuf[0] & ~0x3c0) | (((insn[0] & 0xf000) >> 12) << 6); + slotbuf[0] = (slotbuf[0] & ~0xc00) | (((insn[0] & 0xc00) >> 10) << 10); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x2) >> 1) << 12); + slotbuf[0] = (slotbuf[0] & ~0x6000) | (((insn[0] & 0x18000000) >> 27) << 13); + slotbuf[0] = (slotbuf[0] & ~0x8000) | ((insn[1] & 0x1) << 15); + slotbuf[0] = (slotbuf[0] & ~0x30000) | (((insn[1] & 0x1800000) >> 23) << 16); + slotbuf[0] = (slotbuf[0] & ~0x40000) | (((insn[2] & 0x40000) >> 18) << 18); + slotbuf[0] = (slotbuf[0] & ~0x380000) | (((insn[3] & 0xe000) >> 13) << 19); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x10000000) >> 28) << 22); +} + +static void +Slot_ae_format_4_Format_ae4_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3f0) | ((slotbuf[0] & 0x3f) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0x3c0) >> 6) << 12); + insn[0] = (insn[0] & ~0xc00) | (((slotbuf[0] & 0xc00) >> 10) << 10); + insn[1] = (insn[1] & ~0x2) | (((slotbuf[0] & 0x1000) >> 12) << 1); + insn[0] = (insn[0] & ~0x18000000) | (((slotbuf[0] & 0x6000) >> 13) << 27); + insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x8000) >> 15); + insn[1] = (insn[1] & ~0x1800000) | (((slotbuf[0] & 0x30000) >> 16) << 23); + insn[2] = (insn[2] & ~0x40000) | (((slotbuf[0] & 0x40000) >> 18) << 18); + insn[3] = (insn[3] & ~0xe000) | (((slotbuf[0] & 0x380000) >> 19) << 13); + insn[3] = (insn[3] & ~0x10000000) | (((slotbuf[0] & 0x400000) >> 22) << 28); +} + +static void +Slot_ae_format_4_Format_ae4_slot1_72_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x1f00) | (((insn[2] & 0xf8000000) >> 27) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3e000) | ((insn[3] & 0x1f) << 13); + slotbuf[0] = (slotbuf[0] & ~0x3c0000) | (((insn[3] & 0xf0000) >> 16) << 18); + slotbuf[0] = (slotbuf[0] & ~0x400000) | (((insn[3] & 0x20000000) >> 29) << 22); +} + +static void +Slot_ae_format_4_Format_ae4_slot1_72_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[2] = (insn[2] & ~0xf8000000) | (((slotbuf[0] & 0x1f00) >> 8) << 27); + insn[3] = (insn[3] & ~0x1f) | ((slotbuf[0] & 0x3e000) >> 13); + insn[3] = (insn[3] & ~0xf0000) | (((slotbuf[0] & 0x3c0000) >> 18) << 16); + insn[3] = (insn[3] & ~0x20000000) | (((slotbuf[0] & 0x400000) >> 22) << 29); +} + +static void +Slot_ae_format_4_Format_ae4_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[0] & 0x3e00000) >> 21); + slotbuf[0] = (slotbuf[0] & ~0x3e0) | (((insn[0] & 0x1f0000) >> 16) << 5); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[1] & 0xf8) >> 3) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[3] & 0x3e0) >> 5) << 15); + slotbuf[0] = (slotbuf[0] & ~0x700000) | (((insn[3] & 0x700000) >> 20) << 20); + slotbuf[0] = (slotbuf[0] & ~0x800000) | (((insn[3] & 0x40000000) >> 30) << 23); +} + +static void +Slot_ae_format_4_Format_ae4_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3e00000) | ((slotbuf[0] & 0x1f) << 21); + insn[0] = (insn[0] & ~0x1f0000) | (((slotbuf[0] & 0x3e0) >> 5) << 16); + insn[1] = (insn[1] & ~0xf8) | (((slotbuf[0] & 0x7c00) >> 10) << 3); + insn[3] = (insn[3] & ~0x3e0) | (((slotbuf[0] & 0xf8000) >> 15) << 5); + insn[3] = (insn[3] & ~0x700000) | (((slotbuf[0] & 0x700000) >> 20) << 20); + insn[3] = (insn[3] & ~0x40000000) | (((slotbuf[0] & 0x800000) >> 23) << 30); +} + +static void +Slot_ae_format_4_Format_ae4_slot3_26_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[2] & 0x180000) >> 19); + slotbuf[0] = (slotbuf[0] & ~0x1c) | (((insn[3] & 0x1c00) >> 10) << 2); + slotbuf[0] = (slotbuf[0] & ~0x20) | (((insn[0] & 0x4000000) >> 26) << 5); + slotbuf[0] = (slotbuf[0] & ~0x40) | (((insn[1] & 0x4) >> 2) << 6); + slotbuf[0] = (slotbuf[0] & ~0x380) | (((insn[1] & 0x700) >> 8) << 7); + slotbuf[0] = (slotbuf[0] & ~0x7c00) | (((insn[1] & 0x3e000) >> 13) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf8000) | (((insn[2] & 0xf8) >> 3) << 15); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[1] & 0x7c0000) >> 18) << 20); + slotbuf[0] = (slotbuf[0] & ~0x6000000) | (((insn[3] & 0x1800000) >> 23) << 25); + slotbuf[0] = (slotbuf[0] & ~0x8000000) | (((insn[3] & 0x80000000) >> 31) << 27); +} + +static void +Slot_ae_format_4_Format_ae4_slot3_26_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[2] = (insn[2] & ~0x180000) | ((slotbuf[0] & 0x3) << 19); + insn[3] = (insn[3] & ~0x1c00) | (((slotbuf[0] & 0x1c) >> 2) << 10); + insn[0] = (insn[0] & ~0x4000000) | (((slotbuf[0] & 0x20) >> 5) << 26); + insn[1] = (insn[1] & ~0x4) | (((slotbuf[0] & 0x40) >> 6) << 2); + insn[1] = (insn[1] & ~0x700) | (((slotbuf[0] & 0x380) >> 7) << 8); + insn[1] = (insn[1] & ~0x3e000) | (((slotbuf[0] & 0x7c00) >> 10) << 13); + insn[2] = (insn[2] & ~0xf8) | (((slotbuf[0] & 0xf8000) >> 15) << 3); + insn[1] = (insn[1] & ~0x7c0000) | (((slotbuf[0] & 0x1f00000) >> 20) << 18); + insn[3] = (insn[3] & ~0x1800000) | (((slotbuf[0] & 0x6000000) >> 25) << 23); + insn[3] = (insn[3] & ~0x80000000) | (((slotbuf[0] & 0x8000000) >> 27) << 31); +} + +static void +Slot_ae_format_4_Format_ae4_slot4_43_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[3] = 0; + slotbuf[0] = ((insn[1] & 0xfe000000) >> 25); + slotbuf[0] = (slotbuf[0] & ~0x380) | ((insn[2] & 0x7) << 7); + slotbuf[0] = (slotbuf[0] & ~0xc00) | (((insn[1] & 0x1800) >> 11) << 10); + slotbuf[0] = (slotbuf[0] & ~0x7000) | (((insn[2] & 0xe00000) >> 21) << 12); + slotbuf[0] = (slotbuf[0] & ~0x18000) | (((insn[2] & 0x30000) >> 16) << 15); + slotbuf[0] = (slotbuf[0] & ~0xe0000) | (((insn[2] & 0x7000000) >> 24) << 17); + slotbuf[0] = (slotbuf[0] & ~0x700000) | (((insn[3] & 0xe000000) >> 25) << 20); +} + +static void +Slot_ae_format_4_Format_ae4_slot4_43_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xfe000000) | ((slotbuf[0] & 0x7f) << 25); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0x380) >> 7); + insn[1] = (insn[1] & ~0x1800) | (((slotbuf[0] & 0xc00) >> 10) << 11); + insn[2] = (insn[2] & ~0xe00000) | (((slotbuf[0] & 0x7000) >> 12) << 21); + insn[2] = (insn[2] & ~0x30000) | (((slotbuf[0] & 0x18000) >> 15) << 16); + insn[2] = (insn[2] & ~0x7000000) | (((slotbuf[0] & 0xe0000) >> 17) << 24); + insn[3] = (insn[3] & ~0xe000000) | (((slotbuf[0] & 0x700000) >> 20) << 25); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_s8_Slot_inst_get, + Field_imms8_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_r_disp_Slot_inst_get, + Field_r_3_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst_get, + Field_s2_Slot_inst_get, + Field_r2_Slot_inst_get, + Field_t4_Slot_inst_get, + Field_s4_Slot_inst_get, + Field_r4_Slot_inst_get, + Field_t8_Slot_inst_get, + Field_r8_Slot_inst_get, + Field_xt_wbr15_imm_Slot_inst_get, + Field_xt_wloop_imm_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_inst_11_8_Slot_inst_get, + Field_fld_inst_12_12_Slot_inst_get, + Field_fld_inst_12_8_Slot_inst_get, + Field_fld_inst_13_8_Slot_inst_get, + Field_fld_inst_15_12_Slot_inst_get, + Field_fld_inst_19_17_Slot_inst_get, + Field_fld_inst_19_18_Slot_inst_get, + Field_fld_inst_23_12_Slot_inst_get, + Field_fld_inst_23_16_Slot_inst_get, + Field_fld_inst_4_4_Slot_inst_get, + Field_fld_inst_5_4_Slot_inst_get, + Field_fld_inst_7_4_Slot_inst_get, + Field_fld_inst_7_6_Slot_inst_get, + Field_fld_inst_7_7_Slot_inst_get, + Field_fld_inst_9_8_Slot_inst_get, + Field_bitindex_Slot_inst_get, + Field_s3to1_Slot_inst_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_s8_Slot_inst_set, + Field_imms8_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_r_disp_Slot_inst_set, + Field_r_3_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst_set, + Field_s2_Slot_inst_set, + Field_r2_Slot_inst_set, + Field_t4_Slot_inst_set, + Field_s4_Slot_inst_set, + Field_r4_Slot_inst_set, + Field_t8_Slot_inst_set, + Field_r8_Slot_inst_set, + Field_xt_wbr15_imm_Slot_inst_set, + Field_xt_wloop_imm_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_inst_11_8_Slot_inst_set, + Field_fld_inst_12_12_Slot_inst_set, + Field_fld_inst_12_8_Slot_inst_set, + Field_fld_inst_13_8_Slot_inst_set, + Field_fld_inst_15_12_Slot_inst_set, + Field_fld_inst_19_17_Slot_inst_set, + Field_fld_inst_19_18_Slot_inst_set, + Field_fld_inst_23_12_Slot_inst_set, + Field_fld_inst_23_16_Slot_inst_set, + Field_fld_inst_4_4_Slot_inst_set, + Field_fld_inst_5_4_Slot_inst_set, + Field_fld_inst_7_4_Slot_inst_set, + Field_fld_inst_7_6_Slot_inst_set, + Field_fld_inst_7_7_Slot_inst_set, + Field_fld_inst_9_8_Slot_inst_set, + Field_bitindex_Slot_inst_set, + Field_s3to1_Slot_inst_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_get, + 0, + 0, + Field_r_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_set, + 0, + 0, + Field_r_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, 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+ 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_get, + 0, + 0, + Field_r_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_inst16b_12_Slot_inst16b_get, + Field_ae_fld_inst16b_15_13_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_set, + 0, + 0, + Field_r_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_inst16b_12_Slot_inst16b_set, + Field_ae_fld_inst16b_15_13_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot0_get_field_fns[] = { + Field_t_Slot_ae_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot0_get, + Field_s_Slot_ae_slot0_get, + Field_s8_Slot_ae_slot0_get, + 0, + Field_imm12b_Slot_ae_slot0_get, + Field_imm16_Slot_ae_slot0_get, + 0, + 0, + Field_offset_Slot_ae_slot0_get, + 0, + 0, + Field_op2_Slot_ae_slot0_get, + Field_r_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae_slot0_get, + Field_sal_Slot_ae_slot0_get, + Field_sargt_Slot_ae_slot0_get, + 0, + Field_sas_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae_slot0_get, + 0, + Field_r2_Slot_ae_slot0_get, + Field_t4_Slot_ae_slot0_get, + Field_s4_Slot_ae_slot0_get, + Field_r4_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_art_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot0_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_d1_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_ar_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcmp_br4t_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcnv_arr_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcnv_art_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot0_get, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae_slot0_get, + Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_a_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_su_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_vu_Slot_ae_slot0_get, + Field_fld_ae_sem_loads_stores_x_Slot_ae_slot0_get, + Field_fld_ae_sem_pks_d_Slot_ae_slot0_get, + Field_fld_ae_sem_pks_pos_Slot_ae_slot0_get, + Field_fld_ae_sem_pks_s_Slot_ae_slot0_get, + Field_fld_ae_sem_rng_v0_Slot_ae_slot0_get, + Field_fld_ae_sem_rng_v1_Slot_ae_slot0_get, + Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_a_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_a0_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_d_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_d0_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_d1_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_da_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_i16_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_i32_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_i64_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_imm32_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_imm8_Slot_ae_slot0_get, + Field_fld_ae_sem_shift_sd_Slot_ae_slot0_get, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae_slot0_get, + Field_fld_ae_sem_sp32cvt_art_Slot_ae_slot0_get, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae_slot0_get, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae_slot0_get, + Field_fld_ae_sem_spmisc_brt_Slot_ae_slot0_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot0_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot0_get, + Field_fld_ae_slot0_11_10_Slot_ae_slot0_get, + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get, + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_11_9_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_10_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_12_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_2_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_6_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_12_9_Slot_ae_slot0_get, + Field_fld_ae_slot0_14_12_Slot_ae_slot0_get, + Field_fld_ae_slot0_14_13_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_10_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_12_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_13_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_14_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_15_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_16_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_17_Slot_ae_slot0_get, + Field_fld_ae_slot0_17_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_18_13_Slot_ae_slot0_get, + Field_fld_ae_slot0_18_15_Slot_ae_slot0_get, + Field_fld_ae_slot0_18_16_Slot_ae_slot0_get, + Field_fld_ae_slot0_18_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_19_12_Slot_ae_slot0_get, + Field_fld_ae_slot0_19_15_Slot_ae_slot0_get, + Field_fld_ae_slot0_19_19_Slot_ae_slot0_get, + Field_fld_ae_slot0_19_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_1_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_1_1_Slot_ae_slot0_get, + Field_fld_ae_slot0_20_16_Slot_ae_slot0_get, + Field_fld_ae_slot0_20_20_Slot_ae_slot0_get, + Field_fld_ae_slot0_23_15_Slot_ae_slot0_get, + Field_fld_ae_slot0_23_17_Slot_ae_slot0_get, + Field_fld_ae_slot0_23_19_Slot_ae_slot0_get, + Field_fld_ae_slot0_23_22_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_10_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_12_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_14_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_15_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_16_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_17_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_19_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_21_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_22_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_24_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_26_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_27_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_4_Slot_ae_slot0_get, + Field_fld_ae_slot0_28_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_3_1_Slot_ae_slot0_get, + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get, + Field_fld_ae_slot0_3_3_Slot_ae_slot0_get, + Field_fld_ae_slot0_4_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get, + Field_fld_ae_slot0_5_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get, + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get, + Field_fld_ae_slot0_7_2_Slot_ae_slot0_get, + Field_fld_ae_slot0_7_3_Slot_ae_slot0_get, + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get, + Field_fld_ae_slot0_8_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_9_4_Slot_ae_slot0_get, + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_9_9_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot0_set_field_fns[] = { + Field_t_Slot_ae_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot0_set, + Field_s_Slot_ae_slot0_set, + Field_s8_Slot_ae_slot0_set, + 0, + Field_imm12b_Slot_ae_slot0_set, + Field_imm16_Slot_ae_slot0_set, + 0, + 0, + Field_offset_Slot_ae_slot0_set, + 0, + 0, + Field_op2_Slot_ae_slot0_set, + Field_r_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae_slot0_set, + Field_sal_Slot_ae_slot0_set, + Field_sargt_Slot_ae_slot0_set, + 0, + Field_sas_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae_slot0_set, + 0, + Field_r2_Slot_ae_slot0_set, + Field_t4_Slot_ae_slot0_set, + Field_s4_Slot_ae_slot0_set, + Field_r4_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_art_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot0_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_d1_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_ar_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcmp_br4t_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcnv_arr_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcnv_art_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot0_set, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae_slot0_set, + Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_a_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_su_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_vu_Slot_ae_slot0_set, + Field_fld_ae_sem_loads_stores_x_Slot_ae_slot0_set, + Field_fld_ae_sem_pks_d_Slot_ae_slot0_set, + Field_fld_ae_sem_pks_pos_Slot_ae_slot0_set, + Field_fld_ae_sem_pks_s_Slot_ae_slot0_set, + Field_fld_ae_sem_rng_v0_Slot_ae_slot0_set, + Field_fld_ae_sem_rng_v1_Slot_ae_slot0_set, + Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_a_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_a0_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_d_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_d0_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_d1_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_da_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_i16_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_i32_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_i64_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_imm32_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_imm8_Slot_ae_slot0_set, + Field_fld_ae_sem_shift_sd_Slot_ae_slot0_set, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae_slot0_set, + Field_fld_ae_sem_sp32cvt_art_Slot_ae_slot0_set, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae_slot0_set, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae_slot0_set, + Field_fld_ae_sem_spmisc_brt_Slot_ae_slot0_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot0_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot0_set, + Field_fld_ae_slot0_11_10_Slot_ae_slot0_set, + Field_fld_ae_slot0_11_11_Slot_ae_slot0_set, + Field_fld_ae_slot0_11_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_11_9_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_10_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_12_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_2_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_6_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_12_9_Slot_ae_slot0_set, + Field_fld_ae_slot0_14_12_Slot_ae_slot0_set, + Field_fld_ae_slot0_14_13_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_10_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_12_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_13_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_14_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_15_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_16_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_17_Slot_ae_slot0_set, + Field_fld_ae_slot0_17_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_18_13_Slot_ae_slot0_set, + Field_fld_ae_slot0_18_15_Slot_ae_slot0_set, + Field_fld_ae_slot0_18_16_Slot_ae_slot0_set, + Field_fld_ae_slot0_18_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_19_12_Slot_ae_slot0_set, + Field_fld_ae_slot0_19_15_Slot_ae_slot0_set, + Field_fld_ae_slot0_19_19_Slot_ae_slot0_set, + Field_fld_ae_slot0_19_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_1_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_1_1_Slot_ae_slot0_set, + Field_fld_ae_slot0_20_16_Slot_ae_slot0_set, + Field_fld_ae_slot0_20_20_Slot_ae_slot0_set, + Field_fld_ae_slot0_23_15_Slot_ae_slot0_set, + Field_fld_ae_slot0_23_17_Slot_ae_slot0_set, + Field_fld_ae_slot0_23_19_Slot_ae_slot0_set, + Field_fld_ae_slot0_23_22_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_10_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_12_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_14_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_15_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_16_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_17_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_19_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_21_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_22_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_24_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_26_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_27_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_4_Slot_ae_slot0_set, + Field_fld_ae_slot0_28_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_3_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_3_1_Slot_ae_slot0_set, + Field_fld_ae_slot0_3_2_Slot_ae_slot0_set, + Field_fld_ae_slot0_3_3_Slot_ae_slot0_set, + Field_fld_ae_slot0_4_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_4_4_Slot_ae_slot0_set, + Field_fld_ae_slot0_5_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_5_4_Slot_ae_slot0_set, + Field_fld_ae_slot0_7_0_Slot_ae_slot0_set, + Field_fld_ae_slot0_7_2_Slot_ae_slot0_set, + Field_fld_ae_slot0_7_3_Slot_ae_slot0_set, + Field_fld_ae_slot0_7_4_Slot_ae_slot0_set, + Field_fld_ae_slot0_8_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_9_4_Slot_ae_slot0_set, + Field_fld_ae_slot0_9_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_9_9_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot1_get_field_fns[] = { + Field_t_Slot_ae_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot1_get, + Field_s_Slot_ae_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae_slot1_get, + Field_r_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae_slot1_get, + Field_sal_Slot_ae_slot1_get, + Field_sargt_Slot_ae_slot1_get, + 0, + Field_sas_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot1_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot1_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot1_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_a_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_0_0_Slot_ae_slot1_get, + Field_fld_ae_slot1_12_8_Slot_ae_slot1_get, + Field_fld_ae_slot1_17_13_Slot_ae_slot1_get, + Field_fld_ae_slot1_17_17_Slot_ae_slot1_get, + Field_fld_ae_slot1_17_8_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_1_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_12_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_13_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_16_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_17_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_18_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_20_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_22_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_23_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_8_Slot_ae_slot1_get, + Field_fld_ae_slot1_25_9_Slot_ae_slot1_get, + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get, + Field_fld_ae_slot1_3_2_Slot_ae_slot1_get, + Field_fld_ae_slot1_3_3_Slot_ae_slot1_get, + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot1_set_field_fns[] = { + Field_t_Slot_ae_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot1_set, + Field_s_Slot_ae_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae_slot1_set, + Field_r_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae_slot1_set, + Field_sal_Slot_ae_slot1_set, + Field_sargt_Slot_ae_slot1_set, + 0, + Field_sas_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae_slot1_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae_slot1_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot1_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_a_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i128_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_0_0_Slot_ae_slot1_set, + Field_fld_ae_slot1_12_8_Slot_ae_slot1_set, + Field_fld_ae_slot1_17_13_Slot_ae_slot1_set, + Field_fld_ae_slot1_17_17_Slot_ae_slot1_set, + Field_fld_ae_slot1_17_8_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_1_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_12_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_13_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_16_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_17_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_18_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_20_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_22_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_23_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_8_Slot_ae_slot1_set, + Field_fld_ae_slot1_25_9_Slot_ae_slot1_set, + Field_fld_ae_slot1_3_0_Slot_ae_slot1_set, + Field_fld_ae_slot1_3_2_Slot_ae_slot1_set, + Field_fld_ae_slot1_3_3_Slot_ae_slot1_set, + Field_fld_ae_slot1_7_4_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot2_get, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot2_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae_slot2_get, + Field_fld_ae_sem_pks_pos_Slot_ae_slot2_get, + Field_fld_ae_sem_pks_s_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot2_get, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae_slot2_get, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot2_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae_slot2_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_hpcnv_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_hpfma_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_get, + Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot2_get, + Field_fld_ae_sem_multiply_d0_Slot_ae_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae_slot2_get, + Field_fld_ae_sem_multiply_q1_Slot_ae_slot2_get, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae_slot2_get, + Field_fld_ae_sem_reduction_sort_v_Slot_ae_slot2_get, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae_slot2_get, + Field_fld_ae_sem_select_isel_Slot_ae_slot2_get, + Field_fld_ae_sem_select_ss_Slot_ae_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_select_vu_Slot_ae_slot2_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_vp_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_vr_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_vs_Slot_ae_slot2_get, + Field_fld_ae_sem_spfma_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot2_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae_slot2_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot2_get, + Field_fld_ae_slot2_14_0_Slot_ae_slot2_get, + Field_fld_ae_slot2_14_10_Slot_ae_slot2_get, + Field_fld_ae_slot2_14_14_Slot_ae_slot2_get, + Field_fld_ae_slot2_14_5_Slot_ae_slot2_get, + Field_fld_ae_slot2_16_15_Slot_ae_slot2_get, + Field_fld_ae_slot2_19_15_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_15_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_17_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_19_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_20_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_25_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_4_Slot_ae_slot2_get, + Field_fld_ae_slot2_28_5_Slot_ae_slot2_get, + Field_fld_ae_slot2_3_0_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_0_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_1_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_2_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_5_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_6_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_7_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_8_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot2_set, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot2_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_hpcnv_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_hpcnv_vt_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae_slot2_set, + Field_fld_ae_sem_pks_pos_Slot_ae_slot2_set, + Field_fld_ae_sem_pks_s_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot2_set, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae_slot2_set, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot2_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae_slot2_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_hpcnv_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_hpfma_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_set, + Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot2_set, + Field_fld_ae_sem_multiply_d0_Slot_ae_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae_slot2_set, + Field_fld_ae_sem_multiply_q1_Slot_ae_slot2_set, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae_slot2_set, + Field_fld_ae_sem_reduction_sort_v_Slot_ae_slot2_set, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae_slot2_set, + Field_fld_ae_sem_select_isel_Slot_ae_slot2_set, + Field_fld_ae_sem_select_ss_Slot_ae_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_select_vu_Slot_ae_slot2_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_vp_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_vr_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_vs_Slot_ae_slot2_set, + Field_fld_ae_sem_spfma_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot2_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae_slot2_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot2_set, + Field_fld_ae_slot2_14_0_Slot_ae_slot2_set, + Field_fld_ae_slot2_14_10_Slot_ae_slot2_set, + Field_fld_ae_slot2_14_14_Slot_ae_slot2_set, + Field_fld_ae_slot2_14_5_Slot_ae_slot2_set, + Field_fld_ae_slot2_16_15_Slot_ae_slot2_set, + Field_fld_ae_slot2_19_15_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_15_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_17_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_19_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_20_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_25_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_4_Slot_ae_slot2_set, + Field_fld_ae_slot2_28_5_Slot_ae_slot2_set, + Field_fld_ae_slot2_3_0_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_0_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_1_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_2_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_5_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_6_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_7_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_8_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r4_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot3_get, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot3_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot3_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_d_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_d0_Slot_ae_slot3_get, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_i32_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_i64_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae_slot3_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_get, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot3_get, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot3_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae_slot3_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae_slot3_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae_slot3_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae_slot3_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_d0_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_d2_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_q0_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_q1_Slot_ae_slot3_get, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae_slot3_get, + Field_fld_ae_sem_select_ss_Slot_ae_slot3_get, + Field_fld_ae_sem_select_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_select_vs_Slot_ae_slot3_get, + Field_fld_ae_sem_select_vt_Slot_ae_slot3_get, + Field_fld_ae_sem_select_vu_Slot_ae_slot3_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot3_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot3_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_vp_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_vr_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_vs_Slot_ae_slot3_get, + Field_fld_ae_sem_spfma_vt_Slot_ae_slot3_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot3_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae_slot3_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_imm_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_d1_Slot_ae_slot3_get, + Field_fld_ae_sem_multiply_d3_Slot_ae_slot3_get, + Field_fld_ae_sem_rng_d_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_e_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_i8_Slot_ae_slot3_get, + Field_fld_ae_slot3_11_0_Slot_ae_slot3_get, + Field_fld_ae_slot3_14_0_Slot_ae_slot3_get, + Field_fld_ae_slot3_14_10_Slot_ae_slot3_get, + Field_fld_ae_slot3_14_12_Slot_ae_slot3_get, + Field_fld_ae_slot3_14_13_Slot_ae_slot3_get, + Field_fld_ae_slot3_16_13_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_0_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_10_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_15_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_17_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_18_Slot_ae_slot3_get, + Field_fld_ae_slot3_19_19_Slot_ae_slot3_get, + Field_fld_ae_slot3_24_10_Slot_ae_slot3_get, + Field_fld_ae_slot3_24_19_Slot_ae_slot3_get, + Field_fld_ae_slot3_24_20_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_12_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_16_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_19_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_20_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_22_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_25_Slot_ae_slot3_get, + Field_fld_ae_slot3_36_30_Slot_ae_slot3_get, + Field_fld_ae_slot3_4_0_Slot_ae_slot3_get, + Field_fld_ae_slot3_9_0_Slot_ae_slot3_get, + Field_fld_ae_slot3_9_1_Slot_ae_slot3_get, + Field_fld_ae_slot3_9_3_Slot_ae_slot3_get, + Field_fld_ae_slot3_9_5_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r4_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae_slot3_set, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae_slot3_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae_slot3_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_d_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_d0_Slot_ae_slot3_set, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_i32_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_i64_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae_slot3_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_set, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae_slot3_set, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae_slot3_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae_slot3_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae_slot3_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae_slot3_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae_slot3_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_multiply_acc_ep_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_d0_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_d2_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_q0_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_q1_Slot_ae_slot3_set, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae_slot3_set, + Field_fld_ae_sem_select_ss_Slot_ae_slot3_set, + Field_fld_ae_sem_select_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_select_vs_Slot_ae_slot3_set, + Field_fld_ae_sem_select_vt_Slot_ae_slot3_set, + Field_fld_ae_sem_select_vu_Slot_ae_slot3_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae_slot3_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae_slot3_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_vp_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_vr_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_vs_Slot_ae_slot3_set, + Field_fld_ae_sem_spfma_vt_Slot_ae_slot3_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae_slot3_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae_slot3_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_imm_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_d1_Slot_ae_slot3_set, + Field_fld_ae_sem_multiply_d3_Slot_ae_slot3_set, + Field_fld_ae_sem_rng_d_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_e_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_i8_Slot_ae_slot3_set, + Field_fld_ae_slot3_11_0_Slot_ae_slot3_set, + Field_fld_ae_slot3_14_0_Slot_ae_slot3_set, + Field_fld_ae_slot3_14_10_Slot_ae_slot3_set, + Field_fld_ae_slot3_14_12_Slot_ae_slot3_set, + Field_fld_ae_slot3_14_13_Slot_ae_slot3_set, + Field_fld_ae_slot3_16_13_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_0_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_10_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_15_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_17_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_18_Slot_ae_slot3_set, + Field_fld_ae_slot3_19_19_Slot_ae_slot3_set, + Field_fld_ae_slot3_24_10_Slot_ae_slot3_set, + Field_fld_ae_slot3_24_19_Slot_ae_slot3_set, + Field_fld_ae_slot3_24_20_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_12_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_16_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_19_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_20_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_22_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_25_Slot_ae_slot3_set, + Field_fld_ae_slot3_36_30_Slot_ae_slot3_set, + Field_fld_ae_slot3_4_0_Slot_ae_slot3_set, + Field_fld_ae_slot3_9_0_Slot_ae_slot3_set, + Field_fld_ae_slot3_9_1_Slot_ae_slot3_set, + Field_fld_ae_slot3_9_3_Slot_ae_slot3_set, + Field_fld_ae_slot3_9_5_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae2_slot0_get_field_fns[] = { + Field_t_Slot_ae2_slot0_get, + 0, + Field_bbi_Slot_ae2_slot0_get, + 0, + Field_imm8_Slot_ae2_slot0_get, + Field_s_Slot_ae2_slot0_get, + Field_s8_Slot_ae2_slot0_get, + 0, + Field_imm12b_Slot_ae2_slot0_get, + Field_imm16_Slot_ae2_slot0_get, + 0, + 0, + Field_offset_Slot_ae2_slot0_get, + 0, + 0, + Field_op2_Slot_ae2_slot0_get, + Field_r_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot0_get, + Field_sal_Slot_ae2_slot0_get, + Field_sargt_Slot_ae2_slot0_get, + 0, + Field_sas_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae2_slot0_get, + 0, + Field_r2_Slot_ae2_slot0_get, + Field_t4_Slot_ae2_slot0_get, + Field_s4_Slot_ae2_slot0_get, + Field_r4_Slot_ae2_slot0_get, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae2_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_art_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_ds_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae2_slot0_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_d1_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_hpcnv_arr_Slot_ae2_slot0_get, + Field_fld_ae_sem_hpcnv_art_Slot_ae2_slot0_get, + Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae2_slot0_get, + Field_fld_ae_sem_hpcnv_vr_Slot_ae2_slot0_get, + Field_fld_ae_sem_hpcnv_vt_Slot_ae2_slot0_get, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae2_slot0_get, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae2_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_su_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_vu_Slot_ae2_slot0_get, + Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot0_get, + Field_fld_ae_sem_pks_d_Slot_ae2_slot0_get, + Field_fld_ae_sem_pks_pos_Slot_ae2_slot0_get, + Field_fld_ae_sem_pks_s_Slot_ae2_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_a0_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_d_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_d0_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_d1_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_da_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_i16_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_i32_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_i64_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_imm32_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_imm8_Slot_ae2_slot0_get, + Field_fld_ae_sem_shift_sd_Slot_ae2_slot0_get, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae2_slot0_get, + Field_fld_ae_sem_sp32cvt_art_Slot_ae2_slot0_get, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae2_slot0_get, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae2_slot0_get, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae2_slot0_get, + Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot0_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot0_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_12_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_12_2_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_14_8_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_4_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_18_17_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_26_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae2_slot0_set_field_fns[] = { + Field_t_Slot_ae2_slot0_set, + 0, + Field_bbi_Slot_ae2_slot0_set, + 0, + Field_imm8_Slot_ae2_slot0_set, + Field_s_Slot_ae2_slot0_set, + Field_s8_Slot_ae2_slot0_set, + 0, + Field_imm12b_Slot_ae2_slot0_set, + Field_imm16_Slot_ae2_slot0_set, + 0, + 0, + Field_offset_Slot_ae2_slot0_set, + 0, + 0, + Field_op2_Slot_ae2_slot0_set, + Field_r_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot0_set, + Field_sal_Slot_ae2_slot0_set, + Field_sargt_Slot_ae2_slot0_set, + 0, + Field_sas_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae2_slot0_set, + 0, + Field_r2_Slot_ae2_slot0_set, + Field_t4_Slot_ae2_slot0_set, + Field_s4_Slot_ae2_slot0_set, + Field_r4_Slot_ae2_slot0_set, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae2_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_art_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_ds_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae2_slot0_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_d1_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_imm2_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_hpcnv_arr_Slot_ae2_slot0_set, + Field_fld_ae_sem_hpcnv_art_Slot_ae2_slot0_set, + Field_fld_ae_sem_hpcnv_i_imm4_Slot_ae2_slot0_set, + Field_fld_ae_sem_hpcnv_vr_Slot_ae2_slot0_set, + Field_fld_ae_sem_hpcnv_vt_Slot_ae2_slot0_set, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae2_slot0_set, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae2_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_su_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_vu_Slot_ae2_slot0_set, + Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot0_set, + Field_fld_ae_sem_pks_d_Slot_ae2_slot0_set, + Field_fld_ae_sem_pks_pos_Slot_ae2_slot0_set, + Field_fld_ae_sem_pks_s_Slot_ae2_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_a0_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_d_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_d0_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_d1_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_da_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_i16_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_i32_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_i64_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_imm32_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_imm8_Slot_ae2_slot0_set, + Field_fld_ae_sem_shift_sd_Slot_ae2_slot0_set, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae2_slot0_set, + Field_fld_ae_sem_sp32cvt_art_Slot_ae2_slot0_set, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae2_slot0_set, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae2_slot0_set, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae2_slot0_set, + Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot0_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot0_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_12_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_12_2_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_12_4_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_12_8_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_14_13_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_14_8_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_12_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_13_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_15_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_4_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_15_8_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_17_13_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_17_17_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_18_15_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_18_17_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_18_18_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_1_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_23_18_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_23_19_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_16_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_17_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_18_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_19_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_21_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_23_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_24_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_25_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_26_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_40_27_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_7_6_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_8_8_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_9_8_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae2_slot1_get_field_fns[] = { + Field_t_Slot_ae2_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae2_slot1_get, + Field_s_Slot_ae2_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae2_slot1_get, + Field_r_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot1_get, + Field_sal_Slot_ae2_slot1_get, + Field_sargt_Slot_ae2_slot1_get, + 0, + Field_sas_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot1_get, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot1_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot1_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot1_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot1_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot1_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot1_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_11_0_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_17_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_18_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_22_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_36_23_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_3_2_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_3_3_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae2_slot1_set_field_fns[] = { + Field_t_Slot_ae2_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae2_slot1_set, + Field_s_Slot_ae2_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae2_slot1_set, + Field_r_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot1_set, + Field_sal_Slot_ae2_slot1_set, + Field_sargt_Slot_ae2_slot1_set, + 0, + Field_sas_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_d_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_d0_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae2_slot1_set, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot1_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i128_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae2_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae2_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot1_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot1_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot1_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot1_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot1_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_0_0_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_11_0_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_11_10_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_11_8_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_14_10_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_14_11_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_14_12_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_14_14_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_14_8_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_12_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_14_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_15_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_16_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_17_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_18_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_20_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_22_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_36_23_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_3_1_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_3_2_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_3_3_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_9_8_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_9_9_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae2_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot2_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot2_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot2_get, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae2_slot2_get, + Field_fld_ae_sem_pks_pos_Slot_ae2_slot2_get, + Field_fld_ae_sem_pks_s_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot2_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot2_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot2_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot2_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot2_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot2_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae2_slot2_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae2_slot2_get, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae2_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae2_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae2_slot2_get, + Field_fld_ae_sem_multiply_q1_Slot_ae2_slot2_get, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae2_slot2_get, + Field_fld_ae_sem_reduction_sort_v_Slot_ae2_slot2_get, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_isel_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_ss_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae2_slot2_get, + Field_fld_ae_sem_select_vu_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_vp_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_vr_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_vs_Slot_ae2_slot2_get, + Field_fld_ae_sem_spfma_vt_Slot_ae2_slot2_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae2_slot2_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae2_slot2_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_17_0_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_26_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_28_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vp_Slot_ae2_slot2_get, + Field_fld_ae_sem_spaddsub_vq_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae2_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae2_slot2_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae2_slot2_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae2_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae2_slot2_set, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae2_slot2_set, + Field_fld_ae_sem_pks_pos_Slot_ae2_slot2_set, + Field_fld_ae_sem_pks_s_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae2_slot2_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae2_slot2_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae2_slot2_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae2_slot2_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae2_slot2_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae2_slot2_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae2_slot2_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae2_slot2_set, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae2_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae2_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae2_slot2_set, + Field_fld_ae_sem_multiply_q1_Slot_ae2_slot2_set, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae2_slot2_set, + Field_fld_ae_sem_reduction_sort_v_Slot_ae2_slot2_set, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_isel_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_ss_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae2_slot2_set, + Field_fld_ae_sem_select_vu_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_vp_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_vr_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_vs_Slot_ae2_slot2_set, + Field_fld_ae_sem_spfma_vt_Slot_ae2_slot2_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae2_slot2_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae2_slot2_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot2_14_10_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_17_0_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_17_10_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_17_15_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_17_17_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_19_10_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_19_15_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_19_18_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_19_9_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_10_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_15_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_5_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_9_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_18_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_20_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_25_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_26_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_28_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_42_30_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_4_0_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_9_5_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vp_Slot_ae2_slot2_set, + Field_fld_ae_sem_spaddsub_vq_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae3_slot0_get_field_fns[] = { + Field_t_Slot_ae3_slot0_get, + 0, + Field_bbi_Slot_ae3_slot0_get, + 0, + Field_imm8_Slot_ae3_slot0_get, + Field_s_Slot_ae3_slot0_get, + Field_s8_Slot_ae3_slot0_get, + 0, + Field_imm12b_Slot_ae3_slot0_get, + Field_imm16_Slot_ae3_slot0_get, + 0, + 0, + Field_offset_Slot_ae3_slot0_get, + 0, + 0, + Field_op2_Slot_ae3_slot0_get, + Field_r_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot0_get, + Field_sal_Slot_ae3_slot0_get, + Field_sargt_Slot_ae3_slot0_get, + 0, + Field_sas_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae3_slot0_get, + 0, + Field_r2_Slot_ae3_slot0_get, + Field_t4_Slot_ae3_slot0_get, + Field_s4_Slot_ae3_slot0_get, + Field_r4_Slot_ae3_slot0_get, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae3_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae3_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae3_slot0_get, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae3_slot0_get, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_su_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_vu_Slot_ae3_slot0_get, + Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae3_slot0_get, + Field_fld_ae_sem_shift_d_Slot_ae3_slot0_get, + Field_fld_ae_sem_shift_d0_Slot_ae3_slot0_get, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_16_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_7_2_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_9_4_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get, + Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot0_get, + Field_fld_ae_sem_sb_loads_stores_iba2_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae3_slot0_set_field_fns[] = { + Field_t_Slot_ae3_slot0_set, + 0, + Field_bbi_Slot_ae3_slot0_set, + 0, + Field_imm8_Slot_ae3_slot0_set, + Field_s_Slot_ae3_slot0_set, + Field_s8_Slot_ae3_slot0_set, + 0, + Field_imm12b_Slot_ae3_slot0_set, + Field_imm16_Slot_ae3_slot0_set, + 0, + 0, + Field_offset_Slot_ae3_slot0_set, + 0, + 0, + Field_op2_Slot_ae3_slot0_set, + Field_r_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot0_set, + Field_sal_Slot_ae3_slot0_set, + Field_sargt_Slot_ae3_slot0_set, + 0, + Field_sas_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae3_slot0_set, + 0, + Field_r2_Slot_ae3_slot0_set, + Field_t4_Slot_ae3_slot0_set, + Field_s4_Slot_ae3_slot0_set, + Field_r4_Slot_ae3_slot0_set, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae3_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae3_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae3_slot0_set, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae3_slot0_set, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_su_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_vu_Slot_ae3_slot0_set, + Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_sb_loads_stores_iba_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae3_slot0_set, + Field_fld_ae_sem_shift_d_Slot_ae3_slot0_set, + Field_fld_ae_sem_shift_d0_Slot_ae3_slot0_set, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_11_11_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_11_4_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_12_12_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_12_8_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_13_13_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_13_8_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_1_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_11_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_12_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_13_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_14_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_15_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_16_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_17_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_18_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_20_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_27_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_32_8_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_3_3_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_4_4_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_7_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_7_2_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_9_4_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_set, + Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot0_set, + Field_fld_ae_sem_sb_loads_stores_iba2_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae3_slot1_get_field_fns[] = { + Field_t_Slot_ae3_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae3_slot1_get, + Field_s_Slot_ae3_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae3_slot1_get, + Field_r_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot1_get, + Field_sal_Slot_ae3_slot1_get, + Field_sargt_Slot_ae3_slot1_get, + 0, + Field_sas_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot1_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot1_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot1_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot1_get, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot1_get, + 0, + Field_fld_ae3_slot1_23_0_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_11_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_17_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_19_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_23_9_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_3_1_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get, + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae3_slot1_set_field_fns[] = { + Field_t_Slot_ae3_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae3_slot1_set, + Field_s_Slot_ae3_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae3_slot1_set, + Field_r_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot1_set, + Field_sal_Slot_ae3_slot1_set, + Field_sargt_Slot_ae3_slot1_set, + 0, + Field_sas_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_lb_ops_iba_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_a_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae3_slot1_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae3_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae3_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae3_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae3_slot1_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae3_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae3_slot1_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ei_Slot_ae3_slot1_set, + Field_fld_ae_sem_dr_to_ar_eo_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ar_s_Slot_ae3_slot1_set, + 0, + Field_fld_ae3_slot1_23_0_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_11_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_12_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_13_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_15_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_16_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_17_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_19_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_6_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_8_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_23_9_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_3_1_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_3_3_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_set, + Field_fld_ae3_slot1_9_8_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae5_slot0_get_field_fns[] = { + Field_t_Slot_ae5_slot0_get, + 0, + Field_bbi_Slot_ae5_slot0_get, + 0, + Field_imm8_Slot_ae5_slot0_get, + Field_s_Slot_ae5_slot0_get, + Field_s8_Slot_ae5_slot0_get, + 0, + Field_imm12b_Slot_ae5_slot0_get, + Field_imm16_Slot_ae5_slot0_get, + 0, + 0, + Field_offset_Slot_ae5_slot0_get, + 0, + 0, + Field_op2_Slot_ae5_slot0_get, + Field_r_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae5_slot0_get, + Field_sal_Slot_ae5_slot0_get, + Field_sargt_Slot_ae5_slot0_get, + 0, + Field_sas_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae5_slot0_get, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae5_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot0_get, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae5_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae5_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae5_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae5_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae5_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae5_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_su_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_vu_Slot_ae5_slot0_get, + Field_fld_ae_sem_loads_stores_x_Slot_ae5_slot0_get, + Field_fld_ae_sem_pks_d_Slot_ae5_slot0_get, + Field_fld_ae_sem_pks_pos_Slot_ae5_slot0_get, + Field_fld_ae_sem_pks_s_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae5_slot0_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot0_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_ardecnorm16_ar_u_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_12_6_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_17_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_19_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_6_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_7_0_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_get, + Field_fld_ae_sem_lb_db_ops_ar_u_Slot_ae5_slot0_get, + Field_fld_ae_sem_lb_db_ops_iba_Slot_ae5_slot0_get, + Field_fld_ae_sem_rng_a_Slot_ae5_slot0_get, + Field_fld_ae_sem_rng_art_Slot_ae5_slot0_get, + Field_fld_ae_sem_rng_i2_Slot_ae5_slot0_get, + Field_fld_ae_sem_rng_imm2_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae5_slot0_set_field_fns[] = { + Field_t_Slot_ae5_slot0_set, + 0, + Field_bbi_Slot_ae5_slot0_set, + 0, + Field_imm8_Slot_ae5_slot0_set, + Field_s_Slot_ae5_slot0_set, + Field_s8_Slot_ae5_slot0_set, + 0, + Field_imm12b_Slot_ae5_slot0_set, + Field_imm16_Slot_ae5_slot0_set, + 0, + 0, + Field_offset_Slot_ae5_slot0_set, + 0, + 0, + Field_op2_Slot_ae5_slot0_set, + Field_r_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae5_slot0_set, + Field_sal_Slot_ae5_slot0_set, + Field_sargt_Slot_ae5_slot0_set, + 0, + Field_sas_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae5_slot0_set, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae5_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot0_set, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_imm8_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae5_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_arr_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_bt_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae5_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_movi_imm_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae5_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i16_Slot_ae5_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae5_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae5_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_su_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_vu_Slot_ae5_slot0_set, + Field_fld_ae_sem_loads_stores_x_Slot_ae5_slot0_set, + Field_fld_ae_sem_pks_d_Slot_ae5_slot0_set, + Field_fld_ae_sem_pks_pos_Slot_ae5_slot0_set, + Field_fld_ae_sem_pks_s_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae5_slot0_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot0_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_ardecnorm16_ar_u_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_11_10_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_11_4_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_11_9_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_12_10_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_12_4_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_12_6_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_12_8_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_12_9_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_1_0_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_1_1_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_12_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_13_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_15_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_16_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_17_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_18_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_19_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_20_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_27_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_5_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_6_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_29_8_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_2_0_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_4_0_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_4_4_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_7_0_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_8_8_Slot_ae5_slot0_set, + Field_fld_ae_sem_lb_db_ops_ar_u_Slot_ae5_slot0_set, + Field_fld_ae_sem_lb_db_ops_iba_Slot_ae5_slot0_set, + Field_fld_ae_sem_rng_a_Slot_ae5_slot0_set, + Field_fld_ae_sem_rng_art_Slot_ae5_slot0_set, + Field_fld_ae_sem_rng_i2_Slot_ae5_slot0_set, + Field_fld_ae_sem_rng_imm2_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae5_slot1_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot1_1_0_Slot_ae5_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae5_slot1_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot1_1_0_Slot_ae5_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae5_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot2_get, + 0, + Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot2_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot2_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae5_slot2_get, + Field_fld_ae_sem_pks_pos_Slot_ae5_slot2_get, + Field_fld_ae_sem_pks_s_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae5_slot2_get, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae5_slot2_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae5_slot2_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae5_slot2_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae5_slot2_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae5_slot2_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae5_slot2_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae5_slot2_get, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae5_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae5_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae5_slot2_get, + Field_fld_ae_sem_multiply_q1_Slot_ae5_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae5_slot2_get, + Field_fld_ae_sem_select_ss_Slot_ae5_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae5_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae5_slot2_get, + 0, + Field_fld_ae_sem_spaddsub_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae5_slot2_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae5_slot2_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae5_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_spfma_vr_Slot_ae5_slot2_get, + Field_fld_ae_sem_spfma_vs_Slot_ae5_slot2_get, + Field_fld_ae_sem_spfma_vt_Slot_ae5_slot2_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae5_slot2_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae5_slot2_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_14_5_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_24_0_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_get, + Field_fld_ae5_slot2_9_7_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae5_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae5_slot2_set, + 0, + Field_fld_ae_sem_arithmetic_v1_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae5_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae5_slot2_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae5_slot2_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae5_slot2_set, + Field_fld_ae_sem_pks_pos_Slot_ae5_slot2_set, + Field_fld_ae_sem_pks_s_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae5_slot2_set, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae5_slot2_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae5_slot2_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae5_slot2_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae5_slot2_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae5_slot2_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae5_slot2_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae5_slot2_set, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae5_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae5_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae5_slot2_set, + Field_fld_ae_sem_multiply_q1_Slot_ae5_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae5_slot2_set, + Field_fld_ae_sem_select_ss_Slot_ae5_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae5_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae5_slot2_set, + 0, + Field_fld_ae_sem_spaddsub_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae5_slot2_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae5_slot2_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae5_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_spfma_vr_Slot_ae5_slot2_set, + Field_fld_ae_sem_spfma_vs_Slot_ae5_slot2_set, + Field_fld_ae_sem_spfma_vt_Slot_ae5_slot2_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae5_slot2_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae5_slot2_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot2_14_10_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_14_14_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_14_5_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_24_0_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_24_15_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_24_17_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_24_20_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_4_0_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_9_0_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_9_5_Slot_ae5_slot2_set, + Field_fld_ae5_slot2_9_7_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot0_get_field_fns[] = { + Field_t_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae6_slot0_get, + 0, + Field_r2_Slot_ae6_slot0_get, + Field_t4_Slot_ae6_slot0_get, + 0, + Field_r4_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot0_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot0_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot0_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot0_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot0_get, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot0_get, + Field_fld_ae_sem_pks_d_Slot_ae6_slot0_get, + Field_fld_ae_sem_pks_pos_Slot_ae6_slot0_get, + Field_fld_ae_sem_pks_s_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_29_5_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_7_4_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot0_set_field_fns[] = { + Field_t_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae6_slot0_set, + 0, + Field_r2_Slot_ae6_slot0_set, + Field_t4_Slot_ae6_slot0_set, + 0, + Field_r4_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot0_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot0_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot0_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot0_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot0_set, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot0_set, + Field_fld_ae_sem_pks_d_Slot_ae6_slot0_set, + Field_fld_ae_sem_pks_pos_Slot_ae6_slot0_set, + Field_fld_ae_sem_pks_s_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot0_10_10_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_15_15_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_10_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_13_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_14_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_15_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_18_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_20_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_29_5_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_4_0_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_4_4_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_7_4_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_9_8_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_9_9_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot1_get_field_fns[] = { + Field_t_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + Field_s_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae6_slot1_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae6_slot1_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot1_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot1_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot1_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae6_slot1_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae6_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae6_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot1_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae6_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae6_slot1_get, + Field_fld_ae_sem_shift_d_Slot_ae6_slot1_get, + Field_fld_ae_sem_shift_d0_Slot_ae6_slot1_get, + 0, + Field_fld_ae_sem_shift_da_Slot_ae6_slot1_get, + Field_fld_ae_sem_shift_i16_Slot_ae6_slot1_get, + Field_fld_ae_sem_shift_i32_Slot_ae6_slot1_get, + Field_fld_ae_sem_shift_i64_Slot_ae6_slot1_get, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_21_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_3_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_2_0_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_9_5_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot1_set_field_fns[] = { + Field_t_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + Field_s_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae6_slot1_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae6_slot1_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot1_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot1_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot1_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae6_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae6_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae6_slot1_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae6_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae6_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae6_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae6_slot1_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae6_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae6_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae6_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae6_slot1_set, + Field_fld_ae_sem_shift_d_Slot_ae6_slot1_set, + Field_fld_ae_sem_shift_d0_Slot_ae6_slot1_set, + 0, + Field_fld_ae_sem_shift_da_Slot_ae6_slot1_set, + Field_fld_ae_sem_shift_i16_Slot_ae6_slot1_set, + Field_fld_ae_sem_shift_i32_Slot_ae6_slot1_set, + Field_fld_ae_sem_shift_i64_Slot_ae6_slot1_set, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_14_14_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_12_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_15_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_20_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_21_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_3_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_27_6_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_2_0_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_9_5_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_9_6_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_9_7_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_9_8_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_9_9_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot2_get_field_fns[] = { + Field_t_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae6_slot2_get, + 0, + 0, + Field_t4_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot2_get, + 0, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot2_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae6_slot2_get, + Field_fld_ae_sem_pks_pos_Slot_ae6_slot2_get, + Field_fld_ae_sem_pks_s_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae6_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae6_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_24_0_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_24_10_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_24_20_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot2_set_field_fns[] = { + Field_t_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae6_slot2_set, + 0, + 0, + Field_t4_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot2_set, + 0, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot2_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae6_slot2_set, + Field_fld_ae_sem_pks_pos_Slot_ae6_slot2_set, + Field_fld_ae_sem_pks_s_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae6_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae6_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot2_10_10_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_11_10_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_24_0_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_24_10_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_24_14_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_24_15_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_24_20_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_4_2_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_9_5_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r2_Slot_ae6_slot3_get, + 0, + 0, + Field_r4_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot3_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot3_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot3_get, + Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot3_get, + Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot3_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot3_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae6_slot3_get, + Field_fld_ae_sem_multiply_d2_Slot_ae6_slot3_get, + Field_fld_ae_sem_multiply_q0_Slot_ae6_slot3_get, + Field_fld_ae_sem_multiply_q1_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae6_slot3_get, + Field_fld_ae_sem_multiply_d3_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_12_0_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_14_0_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_24_20_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_37_13_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r2_Slot_ae6_slot3_set, + 0, + 0, + Field_r4_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae6_slot3_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae6_slot3_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae6_slot3_set, + Field_fld_ae_sem_arithmetic_va_Slot_ae6_slot3_set, + Field_fld_ae_sem_arithmetic_vs_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae6_slot3_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae6_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae6_slot3_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae6_slot3_set, + Field_fld_ae_sem_multiply_d2_Slot_ae6_slot3_set, + Field_fld_ae_sem_multiply_q0_Slot_ae6_slot3_set, + Field_fld_ae_sem_multiply_q1_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae6_slot3_set, + Field_fld_ae_sem_multiply_d3_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot3_10_10_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_12_0_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_14_0_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_14_10_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_14_13_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_14_5_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_24_20_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_37_13_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_37_15_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_37_20_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_37_30_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_9_5_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot0_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_12_6_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_23_0_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get, + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot0_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_12_6_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_23_0_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_23_13_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_23_17_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_23_18_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_23_6_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_set, + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot1_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_12_6_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_23_0_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_get, + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot1_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae7_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae7_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae7_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_12_6_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_23_0_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_23_13_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_23_17_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_23_18_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_23_6_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_7_6_Slot_ae7_slot1_set, + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae7_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae7_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae7_slot2_get, + Field_fld_ae_sem_multiply_q1_Slot_ae7_slot2_get, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae7_slot2_get, + Field_fld_ae_sem_reduction_sort_v_Slot_ae7_slot2_get, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_isel_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_ss_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae7_slot2_get, + Field_fld_ae_sem_select_vu_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae7_slot2_get, + Field_fld_ae_sem_multiply_d3_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot2_11_0_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_14_10_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_36_12_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_get, + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae7_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae7_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae7_slot2_set, + Field_fld_ae_sem_multiply_q1_Slot_ae7_slot2_set, + Field_fld_ae_sem_reduction_sort_ds_Slot_ae7_slot2_set, + Field_fld_ae_sem_reduction_sort_v_Slot_ae7_slot2_set, + Field_fld_ae_sem_reduction_sort_v0_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_isel_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_ss_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae7_slot2_set, + Field_fld_ae_sem_select_vu_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae7_slot2_set, + Field_fld_ae_sem_multiply_d3_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot2_11_0_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_14_10_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_14_5_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_36_12_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_36_15_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_36_20_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_36_25_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_36_30_Slot_ae7_slot2_set, + Field_fld_ae7_slot2_9_5_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae7_slot3_get, + Field_fld_ae_sem_multiply_d2_Slot_ae7_slot3_get, + Field_fld_ae_sem_multiply_q0_Slot_ae7_slot3_get, + Field_fld_ae_sem_multiply_q1_Slot_ae7_slot3_get, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae7_slot3_get, + Field_fld_ae_sem_select_ss_Slot_ae7_slot3_get, + Field_fld_ae_sem_select_vr_Slot_ae7_slot3_get, + Field_fld_ae_sem_select_vs_Slot_ae7_slot3_get, + Field_fld_ae_sem_select_vt_Slot_ae7_slot3_get, + Field_fld_ae_sem_select_vu_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae7_slot3_get, + Field_fld_ae_sem_multiply_d3_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot3_10_0_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_24_10_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_35_11_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_4_0_Slot_ae7_slot3_get, + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae7_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae7_slot3_set, + Field_fld_ae_sem_multiply_d2_Slot_ae7_slot3_set, + Field_fld_ae_sem_multiply_q0_Slot_ae7_slot3_set, + Field_fld_ae_sem_multiply_q1_Slot_ae7_slot3_set, + 0, + 0, + 0, + Field_fld_ae_sem_select_isel_Slot_ae7_slot3_set, + Field_fld_ae_sem_select_ss_Slot_ae7_slot3_set, + Field_fld_ae_sem_select_vr_Slot_ae7_slot3_set, + Field_fld_ae_sem_select_vs_Slot_ae7_slot3_set, + Field_fld_ae_sem_select_vt_Slot_ae7_slot3_set, + Field_fld_ae_sem_select_vu_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae7_slot3_set, + Field_fld_ae_sem_multiply_d3_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot3_10_0_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_14_10_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_14_5_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_24_10_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_35_11_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_35_20_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_35_25_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_35_30_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_4_0_Slot_ae7_slot3_set, + Field_fld_ae7_slot3_9_5_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae8_slot0_get_field_fns[] = { + Field_t_Slot_ae8_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae8_slot0_get, + Field_s_Slot_ae8_slot0_get, + Field_s8_Slot_ae8_slot0_get, + 0, + Field_imm12b_Slot_ae8_slot0_get, + Field_imm16_Slot_ae8_slot0_get, + 0, + 0, + Field_offset_Slot_ae8_slot0_get, + 0, + 0, + Field_op2_Slot_ae8_slot0_get, + Field_r_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae8_slot0_get, + Field_sal_Slot_ae8_slot0_get, + Field_sargt_Slot_ae8_slot0_get, + 0, + Field_sas_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae8_slot0_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae8_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae8_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot0_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_su_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae8_slot0_get, + Field_fld_ae_sem_shift_d_Slot_ae8_slot0_get, + Field_fld_ae_sem_shift_d0_Slot_ae8_slot0_get, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae8_slot0_get, + Field_fld_ae_sem_shift_i32_Slot_ae8_slot0_get, + Field_fld_ae_sem_shift_i64_Slot_ae8_slot0_get, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_13_13_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_17_8_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_21_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_22_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_23_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_7_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_31_9_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_6_0_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_7_5_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_get, + Field_fld_ae8_slot0_8_0_Slot_ae8_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae8_slot0_set_field_fns[] = { + Field_t_Slot_ae8_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae8_slot0_set, + Field_s_Slot_ae8_slot0_set, + Field_s8_Slot_ae8_slot0_set, + 0, + Field_imm12b_Slot_ae8_slot0_set, + Field_imm16_Slot_ae8_slot0_set, + 0, + 0, + Field_offset_Slot_ae8_slot0_set, + 0, + 0, + Field_op2_Slot_ae8_slot0_set, + Field_r_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae8_slot0_set, + Field_sal_Slot_ae8_slot0_set, + Field_sargt_Slot_ae8_slot0_set, + 0, + Field_sas_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v_Slot_ae8_slot0_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae8_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae8_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot0_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_su_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_shift_a0_Slot_ae8_slot0_set, + Field_fld_ae_sem_shift_d_Slot_ae8_slot0_set, + Field_fld_ae_sem_shift_d0_Slot_ae8_slot0_set, + 0, + 0, + Field_fld_ae_sem_shift_i16_Slot_ae8_slot0_set, + Field_fld_ae_sem_shift_i32_Slot_ae8_slot0_set, + Field_fld_ae_sem_shift_i64_Slot_ae8_slot0_set, + 0, + 0, + Field_fld_ae_sem_shift_sd_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot0_13_12_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_13_13_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_13_4_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_13_9_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_17_4_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_17_8_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_12_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_15_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_18_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_19_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_20_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_21_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_22_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_23_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_7_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_8_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_31_9_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_3_0_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_6_0_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_7_4_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_7_5_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_7_7_Slot_ae8_slot0_set, + Field_fld_ae8_slot0_8_0_Slot_ae8_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae8_slot1_get_field_fns[] = { + Field_t_Slot_ae8_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae8_slot1_get, + Field_s_Slot_ae8_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae8_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae8_slot1_get, + Field_r_Slot_ae8_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae8_slot1_get, + Field_sal_Slot_ae8_slot1_get, + Field_sargt_Slot_ae8_slot1_get, + 0, + Field_sas_Slot_ae8_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot1_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_17_15_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_22_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_23_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_5_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_29_9_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_4_0_Slot_ae8_slot1_get, + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae8_slot1_set_field_fns[] = { + Field_t_Slot_ae8_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae8_slot1_set, + Field_s_Slot_ae8_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae8_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae8_slot1_set, + Field_r_Slot_ae8_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae8_slot1_set, + Field_sal_Slot_ae8_slot1_set, + Field_sargt_Slot_ae8_slot1_set, + 0, + Field_sas_Slot_ae8_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae8_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae8_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae8_slot1_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae8_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae8_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae8_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae8_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae8_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot1_17_13_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_17_14_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_17_15_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_17_8_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_12_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_13_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_18_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_20_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_22_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_23_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_5_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_8_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_29_9_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_3_0_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_3_3_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_4_0_Slot_ae8_slot1_set, + Field_fld_ae8_slot1_7_4_Slot_ae8_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae8_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_19_15_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_33_25_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_33_9_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_8_0_Slot_ae8_slot2_get, + Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_c0_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_c1_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_c2_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_c3_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_q0_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_q1_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_q2_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_q3_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_v0_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_v1_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_v2_Slot_ae8_slot2_get, + Field_fld_ae_sem_mul_nn_v3_Slot_ae8_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae8_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae8_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae8_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae8_slot2_19_10_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_19_15_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_33_15_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_33_25_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_33_9_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_34_30_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_39_35_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_44_35_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_58_34_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_58_35_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_58_40_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_58_50_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_8_0_Slot_ae8_slot2_set, + Field_fld_ae8_slot2_9_0_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_c0_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_c1_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_c2_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_c3_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_q0_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_q1_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_q2_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_q3_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_v0_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_v1_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_v2_Slot_ae8_slot2_set, + Field_fld_ae_sem_mul_nn_v3_Slot_ae8_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae9_slot0_get_field_fns[] = { + Field_t_Slot_ae9_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae9_slot0_get, + Field_s_Slot_ae9_slot0_get, + Field_s8_Slot_ae9_slot0_get, + 0, + Field_imm12b_Slot_ae9_slot0_get, + Field_imm16_Slot_ae9_slot0_get, + 0, + 0, + Field_offset_Slot_ae9_slot0_get, + 0, + 0, + Field_op2_Slot_ae9_slot0_get, + Field_r_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae9_slot0_get, + Field_sal_Slot_ae9_slot0_get, + Field_sargt_Slot_ae9_slot0_get, + 0, + Field_sas_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r2_Slot_ae9_slot0_get, + 0, + Field_s4_Slot_ae9_slot0_get, + Field_r4_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v0_Slot_ae9_slot0_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae9_slot0_get, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae9_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae9_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot0_get, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot0_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot0_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae9_slot0_get, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae9_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_su_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae9_slot0_get, + Field_fld_ae_sem_sp32cvt_art_Slot_ae9_slot0_get, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae9_slot0_get, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae9_slot0_get, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae9_slot0_get, + Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot0_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot0_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_17_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_19_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_22_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_3_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_2_0_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_7_6_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_get, + Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae9_slot0_set_field_fns[] = { + Field_t_Slot_ae9_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae9_slot0_set, + Field_s_Slot_ae9_slot0_set, + Field_s8_Slot_ae9_slot0_set, + 0, + Field_imm12b_Slot_ae9_slot0_set, + Field_imm16_Slot_ae9_slot0_set, + 0, + 0, + Field_offset_Slot_ae9_slot0_set, + 0, + 0, + Field_op2_Slot_ae9_slot0_set, + Field_r_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae9_slot0_set, + Field_sal_Slot_ae9_slot0_set, + Field_sargt_Slot_ae9_slot0_set, + 0, + Field_sas_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r2_Slot_ae9_slot0_set, + 0, + Field_s4_Slot_ae9_slot0_set, + Field_r4_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_v0_Slot_ae9_slot0_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae9_slot0_set, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_a_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_v0_Slot_ae9_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_ds_Slot_ae9_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot0_set, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot0_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot0_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hprminmaxnum_vr_Slot_ae9_slot0_set, + Field_fld_ae_sem_hprminmaxnum_vt_Slot_ae9_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i32pos_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i64x2_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_su_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_sp32cvt_arr_Slot_ae9_slot0_set, + Field_fld_ae_sem_sp32cvt_art_Slot_ae9_slot0_set, + Field_fld_ae_sem_sp32cvt_i_imm5_Slot_ae9_slot0_set, + Field_fld_ae_sem_sp32cvt_vr_Slot_ae9_slot0_set, + Field_fld_ae_sem_sp32cvt_vt_Slot_ae9_slot0_set, + Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot0_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot0_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot0_0_0_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_12_12_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_12_5_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_12_8_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_17_13_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_17_4_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_17_8_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_10_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_12_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_13_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_16_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_17_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_18_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_19_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_20_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_22_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_23_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_3_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_27_8_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_2_0_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_3_0_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_7_0_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_7_4_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_7_5_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_7_6_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_7_7_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_8_4_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_8_5_Slot_ae9_slot0_set, + Field_fld_ae9_slot0_9_5_Slot_ae9_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae9_slot1_get_field_fns[] = { + Field_t_Slot_ae9_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae9_slot1_get, + Field_s_Slot_ae9_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae9_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae9_slot1_get, + Field_r_Slot_ae9_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae9_slot1_get, + Field_sal_Slot_ae9_slot1_get, + Field_sargt_Slot_ae9_slot1_get, + 0, + Field_sas_Slot_ae9_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_1_0_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_17_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_2_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_22_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_23_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_26_9_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_3_2_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_get, + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae9_slot1_set_field_fns[] = { + Field_t_Slot_ae9_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae9_slot1_set, + Field_s_Slot_ae9_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae9_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae9_slot1_set, + Field_r_Slot_ae9_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae9_slot1_set, + Field_sal_Slot_ae9_slot1_set, + Field_sargt_Slot_ae9_slot1_set, + 0, + Field_sas_Slot_ae9_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae9_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae9_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae9_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae9_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae9_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae9_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae9_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot1_17_13_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_17_8_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_1_0_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_12_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_13_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_16_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_17_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_18_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_2_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_20_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_22_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_23_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_8_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_26_9_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_3_0_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_3_2_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_3_3_Slot_ae9_slot1_set, + Field_fld_ae9_slot1_7_4_Slot_ae9_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae9_slot2_get_field_fns[] = { + Field_t_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae9_slot2_get, + 0, + 0, + Field_t4_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot2_get, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot2_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot2_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot2_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot2_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae9_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae9_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae9_slot2_get, + Field_fld_ae_sem_select_vu_Slot_ae9_slot2_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot2_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot2_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_vp_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_vr_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_vs_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_vt_Slot_ae9_slot2_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot2_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot2_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spaddsub_vp_Slot_ae9_slot2_get, + Field_fld_ae_sem_spaddsub_vq_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_33_9_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_8_0_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_get, + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpfma_vp_Slot_ae9_slot2_get, + Field_fld_ae_sem_hpfma_vu_Slot_ae9_slot2_get, + Field_fld_ae_sem_spfma_vu_Slot_ae9_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae9_slot2_set_field_fns[] = { + Field_t_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae9_slot2_set, + 0, + 0, + Field_t4_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot2_set, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot2_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot2_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot2_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot2_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae9_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae9_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae9_slot2_set, + Field_fld_ae_sem_select_vu_Slot_ae9_slot2_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot2_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot2_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_vp_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_vr_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_vs_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_vt_Slot_ae9_slot2_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot2_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot2_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spaddsub_vp_Slot_ae9_slot2_set, + Field_fld_ae_sem_spaddsub_vq_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae9_slot2_24_14_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_24_15_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_24_20_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_14_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_15_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_20_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_25_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_26_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_28_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_30_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_33_9_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_4_0_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_5_0_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_6_0_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_8_0_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_9_0_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_9_5_Slot_ae9_slot2_set, + Field_fld_ae9_slot2_9_9_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpfma_vp_Slot_ae9_slot2_set, + Field_fld_ae_sem_hpfma_vu_Slot_ae9_slot2_set, + Field_fld_ae_sem_spfma_vu_Slot_ae9_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae9_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot3_get, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot3_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot3_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot3_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot3_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot3_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot3_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot3_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot3_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot3_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae9_slot3_get, + Field_fld_ae_sem_select_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_select_vs_Slot_ae9_slot3_get, + Field_fld_ae_sem_select_vt_Slot_ae9_slot3_get, + Field_fld_ae_sem_select_vu_Slot_ae9_slot3_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot3_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot3_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_vp_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_vr_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_vs_Slot_ae9_slot3_get, + Field_fld_ae_sem_spfma_vt_Slot_ae9_slot3_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot3_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot3_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spfma_vu_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_31_7_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_4_4_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_6_0_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_get, + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae9_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae9_slot3_set, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae9_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae9_slot3_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae9_slot3_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae9_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae9_slot3_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae9_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae9_slot3_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae9_slot3_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae9_slot3_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae9_slot3_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae9_slot3_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae9_slot3_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae9_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae9_slot3_set, + Field_fld_ae_sem_select_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_select_vs_Slot_ae9_slot3_set, + Field_fld_ae_sem_select_vt_Slot_ae9_slot3_set, + Field_fld_ae_sem_select_vu_Slot_ae9_slot3_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae9_slot3_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae9_slot3_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_vp_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_vr_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_vs_Slot_ae9_slot3_set, + Field_fld_ae_sem_spfma_vt_Slot_ae9_slot3_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae9_slot3_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae9_slot3_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae9_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spfma_vu_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_19_15_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_24_20_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_14_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_15_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_20_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_25_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_26_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_28_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_31_7_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_4_0_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_4_3_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_4_4_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_6_0_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_9_0_Slot_ae9_slot3_set, + Field_fld_ae9_slot3_9_5_Slot_ae9_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae10_slot0_get_field_fns[] = { + Field_t_Slot_ae10_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae10_slot0_get, + Field_s_Slot_ae10_slot0_get, + Field_s8_Slot_ae10_slot0_get, + 0, + Field_imm12b_Slot_ae10_slot0_get, + Field_imm16_Slot_ae10_slot0_get, + 0, + 0, + Field_offset_Slot_ae10_slot0_get, + 0, + 0, + Field_op2_Slot_ae10_slot0_get, + Field_r_Slot_ae10_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae10_slot0_get, + Field_sal_Slot_ae10_slot0_get, + Field_sargt_Slot_ae10_slot0_get, + 0, + Field_sas_Slot_ae10_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae10_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot0_get, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_17_8_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_0_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_17_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_7_6_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_get, + Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae10_slot0_set_field_fns[] = { + Field_t_Slot_ae10_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae10_slot0_set, + Field_s_Slot_ae10_slot0_set, + Field_s8_Slot_ae10_slot0_set, + 0, + Field_imm12b_Slot_ae10_slot0_set, + Field_imm16_Slot_ae10_slot0_set, + 0, + 0, + Field_offset_Slot_ae10_slot0_set, + 0, + 0, + Field_op2_Slot_ae10_slot0_set, + Field_r_Slot_ae10_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae10_slot0_set, + Field_sal_Slot_ae10_slot0_set, + Field_sargt_Slot_ae10_slot0_set, + 0, + Field_sas_Slot_ae10_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae10_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot0_set, + 0, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot0_17_13_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_17_4_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_17_8_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_0_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_10_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_12_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_13_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_16_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_17_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_18_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_20_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_24_8_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_3_0_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_7_4_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_7_6_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_7_7_Slot_ae10_slot0_set, + Field_fld_ae10_slot0_8_4_Slot_ae10_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae10_slot1_get_field_fns[] = { + Field_t_Slot_ae10_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae10_slot1_get, + Field_s_Slot_ae10_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae10_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae10_slot1_get, + Field_r_Slot_ae10_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae10_slot1_get, + Field_sal_Slot_ae10_slot1_get, + Field_sargt_Slot_ae10_slot1_get, + 0, + Field_sas_Slot_ae10_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i3_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae10_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot1_0_0_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_1_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_17_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_22_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_23_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_25_9_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_3_2_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_get, + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae10_slot1_set_field_fns[] = { + Field_t_Slot_ae10_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae10_slot1_set, + Field_s_Slot_ae10_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae10_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae10_slot1_set, + Field_r_Slot_ae10_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae10_slot1_set, + Field_sal_Slot_ae10_slot1_set, + Field_sargt_Slot_ae10_slot1_set, + 0, + Field_sas_Slot_ae10_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_av_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_av1_Slot_ae10_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i16_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i3_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i32_Slot_ae10_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i64half_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i64neg_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_i64pos_Slot_ae10_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_i8_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_imm2_Slot_ae10_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_uu_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_v_Slot_ae10_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae10_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae10_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot1_0_0_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_17_13_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_17_8_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_1_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_12_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_13_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_16_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_17_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_18_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_20_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_22_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_23_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_8_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_25_9_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_3_0_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_3_2_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_3_3_Slot_ae10_slot1_set, + Field_fld_ae10_slot1_7_4_Slot_ae10_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae10_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot2_get, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot2_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot2_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot2_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot2_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae10_slot2_get, + Field_fld_ae_sem_select_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_select_vs_Slot_ae10_slot2_get, + Field_fld_ae_sem_select_vt_Slot_ae10_slot2_get, + Field_fld_ae_sem_select_vu_Slot_ae10_slot2_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot2_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot2_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vp_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vr_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vs_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vt_Slot_ae10_slot2_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot2_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot2_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spaddsub_vp_Slot_ae10_slot2_get, + Field_fld_ae_sem_spaddsub_vq_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vu_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_10_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_get, + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_get, + Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot2_get, + Field_fld_ae_sem_spfma_vq_Slot_ae10_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae10_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot2_set, + 0, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot2_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot2_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot2_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot2_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae10_slot2_set, + Field_fld_ae_sem_select_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_select_vs_Slot_ae10_slot2_set, + Field_fld_ae_sem_select_vt_Slot_ae10_slot2_set, + Field_fld_ae_sem_select_vu_Slot_ae10_slot2_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot2_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot2_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vp_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vr_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vs_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vt_Slot_ae10_slot2_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot2_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot2_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spaddsub_vp_Slot_ae10_slot2_set, + Field_fld_ae_sem_spaddsub_vq_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vu_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae10_slot2_24_20_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_29_20_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_29_25_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_10_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_14_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_15_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_20_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_25_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_30_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_31_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_34_33_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_4_0_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_9_0_Slot_ae10_slot2_set, + Field_fld_ae10_slot2_9_5_Slot_ae10_slot2_set, + Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot2_set, + Field_fld_ae_sem_spfma_vq_Slot_ae10_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae10_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae10_slot3_get, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot3_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae10_slot3_get, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae10_slot3_get, + Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot3_get, + Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot3_get, + Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot3_get, + Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot3_get, + Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot3_get, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot3_get, + Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae10_slot3_get, + Field_fld_ae_sem_select_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_select_vs_Slot_ae10_slot3_get, + Field_fld_ae_sem_select_vt_Slot_ae10_slot3_get, + Field_fld_ae_sem_select_vu_Slot_ae10_slot3_get, + Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot3_get, + Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot3_get, + Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vp_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vr_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vs_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vt_Slot_ae10_slot3_get, + Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot3_get, + Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot3_get, + Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot3_get, + Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vu_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot3_get, + Field_fld_ae_sem_spfma_vq_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_10_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_4_4_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_get, + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae10_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae10_slot3_set, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae10_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae10_slot3_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae10_slot3_set, + 0, + Field_fld_ae_sem_hpcmp_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_hpcmp_vs_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_spmisc_brt_Slot_ae10_slot3_set, + Field_fld_ae_sem_spmisc_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_spmisc_vs_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_fpmov_i_imm4_Slot_ae10_slot3_set, + Field_fld_ae_sem_fpmov_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_fpmov_vs_Slot_ae10_slot3_set, + Field_fld_ae_sem_fpmov_vt_Slot_ae10_slot3_set, + Field_fld_ae_sem_fpmov_vu_Slot_ae10_slot3_set, + Field_fld_ae_sem_hpcmp_vt_Slot_ae10_slot3_set, + 0, + Field_fld_ae_sem_hpfma_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_hpfma_vs_Slot_ae10_slot3_set, + Field_fld_ae_sem_hpfma_vt_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_select_ss_Slot_ae10_slot3_set, + Field_fld_ae_sem_select_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_select_vs_Slot_ae10_slot3_set, + Field_fld_ae_sem_select_vt_Slot_ae10_slot3_set, + Field_fld_ae_sem_select_vu_Slot_ae10_slot3_set, + Field_fld_ae_sem_spaddsub_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_spaddsub_vs_Slot_ae10_slot3_set, + Field_fld_ae_sem_spaddsub_vt_Slot_ae10_slot3_set, + Field_fld_ae_sem_spaddsub_vu_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_i_imm1_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_i_imm3_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vp_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vr_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vs_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vt_Slot_ae10_slot3_set, + Field_fld_ae_sem_spmisc_vsm_Slot_ae10_slot3_set, + Field_fld_ae_sem_spmisc_vt_Slot_ae10_slot3_set, + Field_fld_ae_sem_spmisc_vtm_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vp_Slot_ae10_slot3_set, + Field_fld_ae_sem_hpfma_vu_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vu_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_hpfma_vq_Slot_ae10_slot3_set, + Field_fld_ae_sem_spfma_vq_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_19_15_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_29_20_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_29_25_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_10_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_14_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_15_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_20_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_25_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_30_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_31_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_34_33_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_4_0_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_4_3_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_4_4_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_9_0_Slot_ae10_slot3_set, + Field_fld_ae10_slot3_9_5_Slot_ae10_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot0_get_field_fns[] = { + Field_t_Slot_ae4_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae4_slot0_get, + Field_s_Slot_ae4_slot0_get, + Field_s8_Slot_ae4_slot0_get, + 0, + Field_imm12b_Slot_ae4_slot0_get, + Field_imm16_Slot_ae4_slot0_get, + 0, + 0, + Field_offset_Slot_ae4_slot0_get, + 0, + 0, + Field_op2_Slot_ae4_slot0_get, + Field_r_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae4_slot0_get, + Field_sal_Slot_ae4_slot0_get, + Field_sargt_Slot_ae4_slot0_get, + 0, + Field_sas_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot0_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot0_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot0_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot0_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot0_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot0_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot0_22_0_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_17_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_20_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_3_1_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot0_set_field_fns[] = { + Field_t_Slot_ae4_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae4_slot0_set, + Field_s_Slot_ae4_slot0_set, + Field_s8_Slot_ae4_slot0_set, + 0, + Field_imm12b_Slot_ae4_slot0_set, + Field_imm16_Slot_ae4_slot0_set, + 0, + 0, + Field_offset_Slot_ae4_slot0_set, + 0, + 0, + Field_op2_Slot_ae4_slot0_set, + Field_r_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae4_slot0_set, + Field_sal_Slot_ae4_slot0_set, + Field_sargt_Slot_ae4_slot0_set, + 0, + Field_sas_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_s4_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot0_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot0_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot0_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot0_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot0_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot0_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot0_22_0_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_12_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_13_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_16_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_17_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_18_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_20_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_6_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_22_8_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_3_0_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_3_1_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_4_4_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot1_get_field_fns[] = { + Field_t_Slot_ae4_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae4_slot1_get, + Field_s_Slot_ae4_slot1_get, + 0, + 0, + Field_imm12b_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae4_slot1_get, + Field_r_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae4_slot1_get, + Field_sal_Slot_ae4_slot1_get, + Field_sargt_Slot_ae4_slot1_get, + 0, + Field_sas_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot1_get, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot1_get, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot1_get, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot1_get, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot1_get, + Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot1_get, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot1_22_0_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_17_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_3_1_Slot_ae4_slot1_get, + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot1_set_field_fns[] = { + Field_t_Slot_ae4_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae4_slot1_set, + Field_s_Slot_ae4_slot1_set, + 0, + 0, + Field_imm12b_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae4_slot1_set, + Field_r_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae4_slot1_set, + Field_sal_Slot_ae4_slot1_set, + Field_sargt_Slot_ae4_slot1_set, + 0, + Field_sas_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_ab_Slot_ae4_slot1_set, + Field_fld_ae_sem_dr_to_ar_ai_Slot_ae4_slot1_set, + Field_fld_ae_sem_dr_to_ar_aoe_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_a_Slot_ae4_slot1_set, + Field_fld_ae_sem_loads_stores_a_0_Slot_ae4_slot1_set, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i128_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_i64_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_v_Slot_ae4_slot1_set, + Field_fld_ae_sem_loads_stores_v1_Slot_ae4_slot1_set, + 0, + Field_fld_ae_sem_loads_stores_x_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot1_22_0_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_12_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_13_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_16_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_17_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_18_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_22_8_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_3_0_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_3_1_Slot_ae4_slot1_set, + Field_fld_ae4_slot1_7_4_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot2_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot2_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot2_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot2_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot2_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae4_slot2_get, + Field_fld_ae_sem_pks_pos_Slot_ae4_slot2_get, + Field_fld_ae_sem_pks_s_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae4_slot2_get, + Field_fld_ae_sem_multiply_d2_Slot_ae4_slot2_get, + Field_fld_ae_sem_multiply_q0_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot2_23_0_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_23_17_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_4_0_Slot_ae4_slot2_get, + Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot2_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot2_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot2_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot2_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot2_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_pks_d_Slot_ae4_slot2_set, + Field_fld_ae_sem_pks_pos_Slot_ae4_slot2_set, + Field_fld_ae_sem_pks_s_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_n_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae4_slot2_set, + Field_fld_ae_sem_multiply_d2_Slot_ae4_slot2_set, + Field_fld_ae_sem_multiply_q0_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot2_23_0_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_23_12_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_23_15_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_23_17_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_23_20_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_4_0_Slot_ae4_slot2_set, + Field_fld_ae4_slot2_9_5_Slot_ae4_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot3_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot3_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot3_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae4_slot3_get, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot3_get, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot3_get, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae4_slot3_get, + Field_fld_ae_sem_multiply_d2_Slot_ae4_slot3_get, + Field_fld_ae_sem_multiply_q0_Slot_ae4_slot3_get, + Field_fld_ae_sem_multiply_q1_Slot_ae4_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae4_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot3_14_10_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_19_19_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_19_5_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_27_20_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_27_3_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_2_0_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_get, + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot3_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot3_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot3_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_dr_immed_Slot_ae4_slot3_set, + 0, + Field_fld_ae_sem_dr_to_dr_v_Slot_ae4_slot3_set, + Field_fld_ae_sem_dr_to_dr_v0_Slot_ae4_slot3_set, + Field_fld_ae_sem_dr_to_dr_v1_Slot_ae4_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d0_Slot_ae4_slot3_set, + Field_fld_ae_sem_multiply_d2_Slot_ae4_slot3_set, + Field_fld_ae_sem_multiply_q0_Slot_ae4_slot3_set, + Field_fld_ae_sem_multiply_q1_Slot_ae4_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_multiply_d1_Slot_ae4_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot3_14_10_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_19_15_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_19_19_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_19_5_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_27_20_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_27_25_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_27_3_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_2_0_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_9_0_Slot_ae4_slot3_set, + Field_fld_ae4_slot3_9_5_Slot_ae4_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot4_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot4_get, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot4_get, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot4_get, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot4_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot4_22_0_Slot_ae4_slot4_get, + Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_get, + Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_get, + Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot4_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae4_slot4_set, + Field_fld_ae_sem_arithmetic_v_Slot_ae4_slot4_set, + Field_fld_ae_sem_arithmetic_v0_Slot_ae4_slot4_set, + Field_fld_ae_sem_arithmetic_v1_Slot_ae4_slot4_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 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0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot4_22_0_Slot_ae4_slot4_set, + Field_fld_ae4_slot4_22_15_Slot_ae4_slot4_set, + Field_fld_ae4_slot4_22_20_Slot_ae4_slot4_set, + Field_fld_ae4_slot4_9_5_Slot_ae4_slot4_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_slot_internal slots[] = { + { "Inst", "x24", 0, + Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, + Slot_inst_get_field_fns, Slot_inst_set_field_fns, + Slot_inst_decode, "nop" }, + { "Inst16a", "x16a", 0, + Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, + Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, + Slot_inst16a_decode, "" }, + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, + Slot_inst16b_decode, "nop.n" }, + { "ae_slot0", "ae_format", 0, + Slot_ae_format_Format_ae_slot0_4_get, Slot_ae_format_Format_ae_slot0_4_set, + Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns, + Slot_ae_slot0_decode, "nop" }, + { "ae_slot1", "ae_format", 1, + Slot_ae_format_Format_ae_slot1_72_get, Slot_ae_format_Format_ae_slot1_72_set, + Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns, + Slot_ae_slot1_decode, "nop" }, + { "ae_slot2", "ae_format", 2, + Slot_ae_format_Format_ae_slot2_16_get, Slot_ae_format_Format_ae_slot2_16_set, + Slot_ae_slot2_get_field_fns, Slot_ae_slot2_set_field_fns, + Slot_ae_slot2_decode, "nop" }, + { "ae_slot3", "ae_format", 3, + Slot_ae_format_Format_ae_slot3_45_get, Slot_ae_format_Format_ae_slot3_45_set, + Slot_ae_slot3_get_field_fns, Slot_ae_slot3_set_field_fns, + Slot_ae_slot3_decode, "nop" }, + { "ae2_slot0", "ae_format_2", 0, + Slot_ae_format_2_Format_ae2_slot0_4_get, Slot_ae_format_2_Format_ae2_slot0_4_set, + Slot_ae2_slot0_get_field_fns, Slot_ae2_slot0_set_field_fns, + Slot_ae2_slot0_decode, "nop" }, + { "ae2_slot1", "ae_format_2", 1, + Slot_ae_format_2_Format_ae2_slot1_12_get, Slot_ae_format_2_Format_ae2_slot1_12_set, + Slot_ae2_slot1_get_field_fns, Slot_ae2_slot1_set_field_fns, + Slot_ae2_slot1_decode, "nop" }, + { "ae2_slot2", "ae_format_2", 2, + Slot_ae_format_2_Format_ae2_slot2_16_get, Slot_ae_format_2_Format_ae2_slot2_16_set, + Slot_ae2_slot2_get_field_fns, Slot_ae2_slot2_set_field_fns, + Slot_ae2_slot2_decode, "nop" }, + { "ae3_slot0", "ae_format_3", 0, + Slot_ae_format_3_Format_ae3_slot0_4_get, Slot_ae_format_3_Format_ae3_slot0_4_set, + Slot_ae3_slot0_get_field_fns, Slot_ae3_slot0_set_field_fns, + Slot_ae3_slot0_decode, "nop" }, + { "ae3_slot1", "ae_format_3", 1, + Slot_ae_format_3_Format_ae3_slot1_12_get, Slot_ae_format_3_Format_ae3_slot1_12_set, + Slot_ae3_slot1_get_field_fns, Slot_ae3_slot1_set_field_fns, + Slot_ae3_slot1_decode, "nop" }, + { "ae5_slot0", "ae_format_5", 0, + Slot_ae_format_5_Format_ae5_slot0_4_get, Slot_ae_format_5_Format_ae5_slot0_4_set, + Slot_ae5_slot0_get_field_fns, Slot_ae5_slot0_set_field_fns, + Slot_ae5_slot0_decode, "nop" }, + { "ae5_slot1", "ae_format_5", 1, + Slot_ae_format_5_Format_ae5_slot1_56_get, Slot_ae_format_5_Format_ae5_slot1_56_set, + Slot_ae5_slot1_get_field_fns, Slot_ae5_slot1_set_field_fns, + Slot_ae5_slot1_decode, "nop" }, + { "ae5_slot2", "ae_format_5", 2, + Slot_ae_format_5_Format_ae5_slot2_16_get, Slot_ae_format_5_Format_ae5_slot2_16_set, + Slot_ae5_slot2_get_field_fns, Slot_ae5_slot2_set_field_fns, + Slot_ae5_slot2_decode, "nop" }, + { "ae6_slot0", "ae_format_6", 0, + Slot_ae_format_6_Format_ae6_slot0_4_get, Slot_ae_format_6_Format_ae6_slot0_4_set, + Slot_ae6_slot0_get_field_fns, Slot_ae6_slot0_set_field_fns, + Slot_ae6_slot0_decode, "nop" }, + { "ae6_slot1", "ae_format_6", 1, + Slot_ae_format_6_Format_ae6_slot1_57_get, Slot_ae_format_6_Format_ae6_slot1_57_set, + Slot_ae6_slot1_get_field_fns, Slot_ae6_slot1_set_field_fns, + Slot_ae6_slot1_decode, "nop" }, + { "ae6_slot2", "ae_format_6", 2, + Slot_ae_format_6_Format_ae6_slot2_16_get, Slot_ae_format_6_Format_ae6_slot2_16_set, + Slot_ae6_slot2_get_field_fns, Slot_ae6_slot2_set_field_fns, + Slot_ae6_slot2_decode, "nop" }, + { "ae6_slot3", "ae_format_6", 3, + Slot_ae_format_6_Format_ae6_slot3_8_get, Slot_ae_format_6_Format_ae6_slot3_8_set, + Slot_ae6_slot3_get_field_fns, Slot_ae6_slot3_set_field_fns, + Slot_ae6_slot3_decode, "nop" }, + { "ae7_slot0", "ae_format_7", 0, + Slot_ae_format_7_Format_ae7_slot0_4_get, Slot_ae_format_7_Format_ae7_slot0_4_set, + Slot_ae7_slot0_get_field_fns, Slot_ae7_slot0_set_field_fns, + Slot_ae7_slot0_decode, "nop" }, + { "ae7_slot1", "ae_format_7", 1, + Slot_ae_format_7_Format_ae7_slot1_72_get, Slot_ae_format_7_Format_ae7_slot1_72_set, + Slot_ae7_slot1_get_field_fns, Slot_ae7_slot1_set_field_fns, + Slot_ae7_slot1_decode, "nop" }, + { "ae7_slot2", "ae_format_7", 2, + Slot_ae_format_7_Format_ae7_slot2_16_get, Slot_ae_format_7_Format_ae7_slot2_16_set, + Slot_ae7_slot2_get_field_fns, Slot_ae7_slot2_set_field_fns, + Slot_ae7_slot2_decode, "nop" }, + { "ae7_slot3", "ae_format_7", 3, + Slot_ae_format_7_Format_ae7_slot3_45_get, Slot_ae_format_7_Format_ae7_slot3_45_set, + Slot_ae7_slot3_get_field_fns, Slot_ae7_slot3_set_field_fns, + Slot_ae7_slot3_decode, "nop" }, + { "ae8_slot0", "ae_format_8", 0, + Slot_ae_format_8_Format_ae8_slot0_4_get, Slot_ae_format_8_Format_ae8_slot0_4_set, + Slot_ae8_slot0_get_field_fns, Slot_ae8_slot0_set_field_fns, + Slot_ae8_slot0_decode, "nop" }, + { "ae8_slot1", "ae_format_8", 1, + Slot_ae_format_8_Format_ae8_slot1_14_get, Slot_ae_format_8_Format_ae8_slot1_14_set, + Slot_ae8_slot1_get_field_fns, Slot_ae8_slot1_set_field_fns, + Slot_ae8_slot1_decode, "nop" }, + { "ae8_slot2", "ae_format_8", 2, + Slot_ae_format_8_Format_ae8_slot2_16_get, Slot_ae_format_8_Format_ae8_slot2_16_set, + Slot_ae8_slot2_get_field_fns, Slot_ae8_slot2_set_field_fns, + Slot_ae8_slot2_decode, "nop" }, + { "ae9_slot0", "ae_format_9", 0, + Slot_ae_format_9_Format_ae9_slot0_4_get, Slot_ae_format_9_Format_ae9_slot0_4_set, + Slot_ae9_slot0_get_field_fns, Slot_ae9_slot0_set_field_fns, + Slot_ae9_slot0_decode, "nop" }, + { "ae9_slot1", "ae_format_9", 1, + Slot_ae_format_9_Format_ae9_slot1_72_get, Slot_ae_format_9_Format_ae9_slot1_72_set, + Slot_ae9_slot1_get_field_fns, Slot_ae9_slot1_set_field_fns, + Slot_ae9_slot1_decode, "nop" }, + { "ae9_slot2", "ae_format_9", 2, + Slot_ae_format_9_Format_ae9_slot2_16_get, Slot_ae_format_9_Format_ae9_slot2_16_set, + Slot_ae9_slot2_get_field_fns, Slot_ae9_slot2_set_field_fns, + Slot_ae9_slot2_decode, "nop" }, + { "ae9_slot3", "ae_format_9", 3, + Slot_ae_format_9_Format_ae9_slot3_45_get, Slot_ae_format_9_Format_ae9_slot3_45_set, + Slot_ae9_slot3_get_field_fns, Slot_ae9_slot3_set_field_fns, + Slot_ae9_slot3_decode, "nop" }, + { "ae10_slot0", "ae_format_10", 0, + Slot_ae_format_10_Format_ae10_slot0_4_get, Slot_ae_format_10_Format_ae10_slot0_4_set, + Slot_ae10_slot0_get_field_fns, Slot_ae10_slot0_set_field_fns, + Slot_ae10_slot0_decode, "nop" }, + { "ae10_slot1", "ae_format_10", 1, + Slot_ae_format_10_Format_ae10_slot1_34_get, Slot_ae_format_10_Format_ae10_slot1_34_set, + Slot_ae10_slot1_get_field_fns, Slot_ae10_slot1_set_field_fns, + Slot_ae10_slot1_decode, "nop" }, + { "ae10_slot2", "ae_format_10", 2, + Slot_ae_format_10_Format_ae10_slot2_16_get, Slot_ae_format_10_Format_ae10_slot2_16_set, + Slot_ae10_slot2_get_field_fns, Slot_ae10_slot2_set_field_fns, + Slot_ae10_slot2_decode, "nop" }, + { "ae10_slot3", "ae_format_10", 3, + Slot_ae_format_10_Format_ae10_slot3_27_get, Slot_ae_format_10_Format_ae10_slot3_27_set, + Slot_ae10_slot3_get_field_fns, Slot_ae10_slot3_set_field_fns, + Slot_ae10_slot3_decode, "nop" }, + { "ae4_slot0", "ae_format_4", 0, + Slot_ae_format_4_Format_ae4_slot0_4_get, Slot_ae_format_4_Format_ae4_slot0_4_set, + Slot_ae4_slot0_get_field_fns, Slot_ae4_slot0_set_field_fns, + Slot_ae4_slot0_decode, "nop" }, + { "ae4_slot1", "ae_format_4", 1, + Slot_ae_format_4_Format_ae4_slot1_72_get, Slot_ae_format_4_Format_ae4_slot1_72_set, + Slot_ae4_slot1_get_field_fns, Slot_ae4_slot1_set_field_fns, + Slot_ae4_slot1_decode, "nop" }, + { "ae4_slot2", "ae_format_4", 2, + Slot_ae_format_4_Format_ae4_slot2_16_get, Slot_ae_format_4_Format_ae4_slot2_16_set, + Slot_ae4_slot2_get_field_fns, Slot_ae4_slot2_set_field_fns, + Slot_ae4_slot2_decode, "nop" }, + { "ae4_slot3", "ae_format_4", 3, + Slot_ae_format_4_Format_ae4_slot3_26_get, Slot_ae_format_4_Format_ae4_slot3_26_set, + Slot_ae4_slot3_get_field_fns, Slot_ae4_slot3_set_field_fns, + Slot_ae4_slot3_decode, "nop" }, + { "ae4_slot4", "ae_format_4", 4, + Slot_ae_format_4_Format_ae4_slot4_43_get, Slot_ae_format_4_Format_ae4_slot4_43_set, + Slot_ae4_slot4_get_field_fns, Slot_ae4_slot4_set_field_fns, + Slot_ae4_slot4_decode, "nop" } +}; + + +/* Instruction formats. */ + +static void +Format_x24_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_x16a_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_x16b_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xf; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_2_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x2000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_3_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_5_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x2000000e; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_6_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x6000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_7_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_8_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xa000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_9_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_10_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static void +Format_ae_format_4_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x4000000f; + insn[1] = 0; + insn[2] = 0; + insn[3] = 0; +} + +static int Format_x24_slots[] = { 0 }; + +static int Format_x16a_slots[] = { 1 }; + +static int Format_x16b_slots[] = { 2 }; + +static int Format_ae_format_slots[] = { 3, 5, 6, 4 }; + +static int Format_ae_format_2_slots[] = { 7, 8, 9 }; + +static int Format_ae_format_3_slots[] = { 10, 11 }; + +static int Format_ae_format_5_slots[] = { 12, 14, 13 }; + +static int Format_ae_format_6_slots[] = { 15, 18, 17, 16 }; + +static int Format_ae_format_7_slots[] = { 19, 21, 22, 20 }; + +static int Format_ae_format_8_slots[] = { 23, 24, 25 }; + +static int Format_ae_format_9_slots[] = { 26, 28, 29, 27 }; + +static int Format_ae_format_10_slots[] = { 30, 32, 33, 31 }; + +static int Format_ae_format_4_slots[] = { 34, 36, 37, 38, 35 }; + +static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }, + { "ae_format", 16, Format_ae_format_encode, 4, Format_ae_format_slots }, + { "ae_format_2", 16, Format_ae_format_2_encode, 3, Format_ae_format_2_slots }, + { "ae_format_3", 8, Format_ae_format_3_encode, 2, Format_ae_format_3_slots }, + { "ae_format_5", 8, Format_ae_format_5_encode, 3, Format_ae_format_5_slots }, + { "ae_format_6", 16, Format_ae_format_6_encode, 4, Format_ae_format_6_slots }, + { "ae_format_7", 16, Format_ae_format_7_encode, 4, Format_ae_format_7_slots }, + { "ae_format_8", 16, Format_ae_format_8_encode, 3, Format_ae_format_8_slots }, + { "ae_format_9", 16, Format_ae_format_9_encode, 4, Format_ae_format_9_slots }, + { "ae_format_10", 16, Format_ae_format_10_encode, 4, Format_ae_format_10_slots }, + { "ae_format_4", 16, Format_ae_format_4_encode, 5, Format_ae_format_4_slots } +}; + + +static int +format_decoder (const xtensa_insnbuf insn) +{ + if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 0; /* x24 */ + if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 1; /* x16a */ + if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 2; /* x16b */ + if ((insn[0] & 0xe000000f) == 0xf && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 3; /* ae_format */ + if ((insn[0] & 0xe000000f) == 0x2000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 4; /* ae_format_2 */ + if ((insn[0] & 0xe000000f) == 0xe && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 5; /* ae_format_3 */ + if ((insn[0] & 0xe000000f) == 0x2000000e && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 6; /* ae_format_5 */ + if ((insn[0] & 0xe000000f) == 0x6000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 7; /* ae_format_6 */ + if ((insn[0] & 0xe000000f) == 0x8000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 8; /* ae_format_7 */ + if ((insn[0] & 0xe000000f) == 0xa000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 9; /* ae_format_8 */ + if ((insn[0] & 0xe000000f) == 0xc000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 10; /* ae_format_9 */ + if ((insn[0] & 0xe000000f) == 0xe000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 11; /* ae_format_10 */ + if ((insn[0] & 0xe000000f) == 0x4000000f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0 && (insn[3] & 0) == 0) + return 12; /* ae_format_4 */ + return -1; +} + +static int length_table[256] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 8, + 16 +}; + +static int +length_decoder (const unsigned char *insn) +{ + int l = insn[0]; + return length_table[l]; +} + + +/* Top-level ISA structure. */ + +xtensa_isa_internal xtensa_modules = { + 0 /* little-endian */, + 16 /* insn_size */, 0, + 13, formats, format_decoder, length_decoder, + 39, slots, + 886 /* num_fields */, + 1100, operands, + 2139, iclasses, + 2231, opcodes, 0, + 9, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, + 6, interfaces, 0, + 7, funcUnits, 0 +}; diff --git a/overlays/xtensa_mtk_mt8196_adsp/gdb/xtensa-regmap.c b/overlays/xtensa_mtk_mt8196_adsp/gdb/xtensa-regmap.c new file mode 100644 index 00000000..a1086beb --- /dev/null +++ b/overlays/xtensa_mtk_mt8196_adsp/gdb/xtensa-regmap.c @@ -0,0 +1,95 @@ +/* Customized table mapping between kernel xtregset and GDB register cache. + + Copyright (c) 2007-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +typedef struct { + int gdb_regnum; + int gdb_offset; + int ptrace_cp_offset; + int ptrace_offset; + int size; + int coproc; + int dbnum; + char* name +;} xtensa_regtable_t; + +#define XTENSA_ELF_XTREG_SIZE 404 + +const xtensa_regtable_t xtensa_regmap_table[] = { + /* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */ + { 76, 304, 0, 0, 4, -1, 0x0204, "br" }, + { 78, 312, 16, 32, 4, 1, 0x03f0, "ae_ovf_sar" }, + { 79, 316, 20, 36, 4, 1, 0x03f1, "ae_bithead" }, + { 80, 320, 24, 40, 4, 1, 0x03f2, "ae_ts_fts_bu_bp" }, + { 81, 324, 28, 44, 4, 1, 0x03f3, "ae_cw_sd_no" }, + { 82, 328, 32, 48, 4, 1, 0x03f6, "ae_cbegin0" }, + { 83, 332, 36, 52, 4, 1, 0x03f7, "ae_cend0" }, + { 84, 336, 40, 56, 4, 1, 0x03f8, "ae_cbegin1" }, + { 85, 340, 44, 60, 4, 1, 0x03f9, "ae_cend1" }, + { 86, 344, 48, 64, 4, 1, 0x03fa, "ae_cbegin2" }, + { 87, 348, 52, 68, 4, 1, 0x03fb, "ae_cend2" }, + { 88, 352, 128, 144, 8, 1, 0x1000, "aed0" }, + { 89, 360, 136, 152, 8, 1, 0x1001, "aed1" }, + { 90, 368, 144, 160, 8, 1, 0x1002, "aed2" }, + { 91, 376, 152, 168, 8, 1, 0x1003, "aed3" }, + { 92, 384, 160, 176, 8, 1, 0x1004, "aed4" }, + { 93, 392, 168, 184, 8, 1, 0x1005, "aed5" }, + { 94, 400, 176, 192, 8, 1, 0x1006, "aed6" }, + { 95, 408, 184, 200, 8, 1, 0x1007, "aed7" }, + { 96, 416, 192, 208, 8, 1, 0x1008, "aed8" }, + { 97, 424, 200, 216, 8, 1, 0x1009, "aed9" }, + { 98, 432, 208, 224, 8, 1, 0x100a, "aed10" }, + { 99, 440, 216, 232, 8, 1, 0x100b, "aed11" }, + { 100, 448, 224, 240, 8, 1, 0x100c, "aed12" }, + { 101, 456, 232, 248, 8, 1, 0x100d, "aed13" }, + { 102, 464, 240, 256, 8, 1, 0x100e, "aed14" }, + { 103, 472, 248, 264, 8, 1, 0x100f, "aed15" }, + { 104, 480, 256, 272, 8, 1, 0x1010, "aed16" }, + { 105, 488, 264, 280, 8, 1, 0x1011, "aed17" }, + { 106, 496, 272, 288, 8, 1, 0x1012, "aed18" }, + { 107, 504, 280, 296, 8, 1, 0x1013, "aed19" }, + { 108, 512, 288, 304, 8, 1, 0x1014, "aed20" }, + { 109, 520, 296, 312, 8, 1, 0x1015, "aed21" }, + { 110, 528, 304, 320, 8, 1, 0x1016, "aed22" }, + { 111, 536, 312, 328, 8, 1, 0x1017, "aed23" }, + { 112, 544, 320, 336, 8, 1, 0x1018, "aed24" }, + { 113, 552, 328, 344, 8, 1, 0x1019, "aed25" }, + { 114, 560, 336, 352, 8, 1, 0x101a, "aed26" }, + { 115, 568, 344, 360, 8, 1, 0x101b, "aed27" }, + { 116, 576, 352, 368, 8, 1, 0x101c, "aed28" }, + { 117, 584, 360, 376, 8, 1, 0x101d, "aed29" }, + { 118, 592, 368, 384, 8, 1, 0x101e, "aed30" }, + { 119, 600, 376, 392, 8, 1, 0x101f, "aed31" }, + { 120, 608, 64, 80, 16, 1, 0x1020, "u0" }, + { 121, 624, 80, 96, 16, 1, 0x1021, "u1" }, + { 122, 640, 96, 112, 16, 1, 0x1022, "u2" }, + { 123, 656, 112, 128, 16, 1, 0x1023, "u3" }, + { 124, 672, 384, 400, 1, 1, 0x1024, "aep0" }, + { 125, 673, 385, 401, 1, 1, 0x1025, "aep1" }, + { 126, 674, 386, 402, 1, 1, 0x1026, "aep2" }, + { 127, 675, 387, 403, 1, 1, 0x1027, "aep3" }, + { 128, 676, 0, 16, 4, 1, 0x1029, "ae_zbiasv8c" }, + { 129, 680, 8, 24, 4, 1, 0x102a, "fcr_fsr" }, + { 0 } +}; + diff --git a/overlays/xtensa_mtk_mt8196_adsp/gdb/xtensa-xtregs.c b/overlays/xtensa_mtk_mt8196_adsp/gdb/xtensa-xtregs.c new file mode 100644 index 00000000..a1086beb --- /dev/null +++ b/overlays/xtensa_mtk_mt8196_adsp/gdb/xtensa-xtregs.c @@ -0,0 +1,95 @@ +/* Customized table mapping between kernel xtregset and GDB register cache. + + Copyright (c) 2007-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +typedef struct { + int gdb_regnum; + int gdb_offset; + int ptrace_cp_offset; + int ptrace_offset; + int size; + int coproc; + int dbnum; + char* name +;} xtensa_regtable_t; + +#define XTENSA_ELF_XTREG_SIZE 404 + +const xtensa_regtable_t xtensa_regmap_table[] = { + /* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */ + { 76, 304, 0, 0, 4, -1, 0x0204, "br" }, + { 78, 312, 16, 32, 4, 1, 0x03f0, "ae_ovf_sar" }, + { 79, 316, 20, 36, 4, 1, 0x03f1, "ae_bithead" }, + { 80, 320, 24, 40, 4, 1, 0x03f2, "ae_ts_fts_bu_bp" }, + { 81, 324, 28, 44, 4, 1, 0x03f3, "ae_cw_sd_no" }, + { 82, 328, 32, 48, 4, 1, 0x03f6, "ae_cbegin0" }, + { 83, 332, 36, 52, 4, 1, 0x03f7, "ae_cend0" }, + { 84, 336, 40, 56, 4, 1, 0x03f8, "ae_cbegin1" }, + { 85, 340, 44, 60, 4, 1, 0x03f9, "ae_cend1" }, + { 86, 344, 48, 64, 4, 1, 0x03fa, "ae_cbegin2" }, + { 87, 348, 52, 68, 4, 1, 0x03fb, "ae_cend2" }, + { 88, 352, 128, 144, 8, 1, 0x1000, "aed0" }, + { 89, 360, 136, 152, 8, 1, 0x1001, "aed1" }, + { 90, 368, 144, 160, 8, 1, 0x1002, "aed2" }, + { 91, 376, 152, 168, 8, 1, 0x1003, "aed3" }, + { 92, 384, 160, 176, 8, 1, 0x1004, "aed4" }, + { 93, 392, 168, 184, 8, 1, 0x1005, "aed5" }, + { 94, 400, 176, 192, 8, 1, 0x1006, "aed6" }, + { 95, 408, 184, 200, 8, 1, 0x1007, "aed7" }, + { 96, 416, 192, 208, 8, 1, 0x1008, "aed8" }, + { 97, 424, 200, 216, 8, 1, 0x1009, "aed9" }, + { 98, 432, 208, 224, 8, 1, 0x100a, "aed10" }, + { 99, 440, 216, 232, 8, 1, 0x100b, "aed11" }, + { 100, 448, 224, 240, 8, 1, 0x100c, "aed12" }, + { 101, 456, 232, 248, 8, 1, 0x100d, "aed13" }, + { 102, 464, 240, 256, 8, 1, 0x100e, "aed14" }, + { 103, 472, 248, 264, 8, 1, 0x100f, "aed15" }, + { 104, 480, 256, 272, 8, 1, 0x1010, "aed16" }, + { 105, 488, 264, 280, 8, 1, 0x1011, "aed17" }, + { 106, 496, 272, 288, 8, 1, 0x1012, "aed18" }, + { 107, 504, 280, 296, 8, 1, 0x1013, "aed19" }, + { 108, 512, 288, 304, 8, 1, 0x1014, "aed20" }, + { 109, 520, 296, 312, 8, 1, 0x1015, "aed21" }, + { 110, 528, 304, 320, 8, 1, 0x1016, "aed22" }, + { 111, 536, 312, 328, 8, 1, 0x1017, "aed23" }, + { 112, 544, 320, 336, 8, 1, 0x1018, "aed24" }, + { 113, 552, 328, 344, 8, 1, 0x1019, "aed25" }, + { 114, 560, 336, 352, 8, 1, 0x101a, "aed26" }, + { 115, 568, 344, 360, 8, 1, 0x101b, "aed27" }, + { 116, 576, 352, 368, 8, 1, 0x101c, "aed28" }, + { 117, 584, 360, 376, 8, 1, 0x101d, "aed29" }, + { 118, 592, 368, 384, 8, 1, 0x101e, "aed30" }, + { 119, 600, 376, 392, 8, 1, 0x101f, "aed31" }, + { 120, 608, 64, 80, 16, 1, 0x1020, "u0" }, + { 121, 624, 80, 96, 16, 1, 0x1021, "u1" }, + { 122, 640, 96, 112, 16, 1, 0x1022, "u2" }, + { 123, 656, 112, 128, 16, 1, 0x1023, "u3" }, + { 124, 672, 384, 400, 1, 1, 0x1024, "aep0" }, + { 125, 673, 385, 401, 1, 1, 0x1025, "aep1" }, + { 126, 674, 386, 402, 1, 1, 0x1026, "aep2" }, + { 127, 675, 387, 403, 1, 1, 0x1027, "aep3" }, + { 128, 676, 0, 16, 4, 1, 0x1029, "ae_zbiasv8c" }, + { 129, 680, 8, 24, 4, 1, 0x102a, "fcr_fsr" }, + { 0 } +}; + diff --git a/overlays/xtensa_mtk_mt8196_adsp/xtensa/config/core-isa.h b/overlays/xtensa_mtk_mt8196_adsp/xtensa/config/core-isa.h new file mode 100644 index 00000000..78c4fba3 --- /dev/null +++ b/overlays/xtensa_mtk_mt8196_adsp/xtensa/config/core-isa.h @@ -0,0 +1,844 @@ +/* + * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa + * processor CORE configuration + * + * See , which includes this file, for more details. + */ + +/* Xtensa processor core configuration information. + + Copyright (c) 1999-2024 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef XTENSA_CORE_CONFIGURATION_H_ +#define XTENSA_CORE_CONFIGURATION_H_ + + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 16 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_EXCLUSIVE 1 /* L32EX/S32EX instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ +#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ +#define XCHAL_HAVE_LX 1 /* LX core */ +#define XCHAL_HAVE_NX 0 /* NX core (starting RH) */ +#define XCHAL_HAVE_RNX 0 /* RNX core (starting RJ) */ + +#define XCHAL_HAVE_SUPERGATHER 0 /* SuperGather */ + +#define XCHAL_HAVE_FUSION 0 /* Fusion */ +#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ +#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ +#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ +#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ +#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ +#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ +#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ +#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ +#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ +#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI5S 0 /* HiFi5s Audio Engine pkg */ +#define XCHAL_HAVE_HIFI5S_NN_MAC 0 /* HiFi5s Audio Engine NN-MAC option */ +#define XCHAL_HAVE_HIFI5S_VFPU 0 /* HiFi5s Audio Engine Single-Precision VFPU option */ +#define XCHAL_HAVE_HIFI5S_HP_VFPU 0 /* HiFi5s Audio Engine Half-Precision VFPU option */ +#define XCHAL_HAVE_HIFI5S_DP_FPU 0 /* HiFi5s Audio Engine Double-Precision FPU option */ +#define XCHAL_HAVE_HIFI5 1 /* HiFi5 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI5_NN_MAC 1 /* HiFi5 Audio Engine NN-MAC option */ +#define XCHAL_HAVE_HIFI5_VFPU 1 /* HiFi5 Audio Engine Single-Precision VFPU option */ +#define XCHAL_HAVE_HIFI5_HP_VFPU 1 /* HiFi5 Audio Engine Half-Precision VFPU option */ +#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4_VFPU 1 /* HiFi4 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3 1 /* HiFi3 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3_VFPU 1 /* HiFi3 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI1S 0 /* HiFi1s */ +#define XCHAL_HAVE_HIFI1S_VFPU 0 /* HiFi1s SP-VFPU option */ +#define XCHAL_HAVE_HIFI1S_DP_FPU 0 /* HiFi1s DP-FPU option */ +#define XCHAL_HAVE_HIFI1S_LOW_LATENCY_MAC_FMA 0 /* HiFi1s Low-latency MAC/FMA option */ +#define XCHAL_HAVE_HIFI1 0 /* HiFi1 */ +#define XCHAL_HAVE_HIFI1_VFPU 0 /* HiFi1 VFPU option */ +#define XCHAL_HAVE_HIFI1_LOW_LATENCY_MAC_FMA 0 /* HiFi1 Low-latency MAC/FMA option */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ +#define XCHAL_HAVE_HIFI_MINI 0 + + + +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ +#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_USER_SPFPU 1 /* user SP floating-point pkg */ +#define XCHAL_HAVE_FP 1 /* single prec floating point */ +#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */ +#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */ +#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ +#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */ +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ +#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ +#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ +#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ +#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ + +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ + +#define XCHAL_HAVE_FUSIONG 0 /* FusionG */ +#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */ +#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */ +#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */ +#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */ +#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ + +#define XCHAL_HAVE_FUSIONJ 0 /* FusionJ */ +#define XCHAL_HAVE_FUSIONJ6 0 /* FusionJ6 */ +#define XCHAL_HAVE_FUSIONJ_SP_VFPU 0 /* sp_vfpu option on FusionJ */ +#define XCHAL_HAVE_FUSIONJ_DP_VFPU 0 /* dp_vfpu option on FusionJ */ +#define XCHAL_FUSIONJ_SIMD32 0 /* simd32 for FusionJ */ + +#define XCHAL_HAVE_PDX 0 /* PDX-LX */ +#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */ +#define XCHAL_HAVE_PDX4 0 /* PDX4-LX */ +#define XCHAL_HAVE_PDX8 0 /* PDX8-LX */ +#define XCHAL_HAVE_PDX16 0 /* PDX16-LX */ +#define XCHAL_HAVE_PDXNX 0 /* PDX-NX */ + +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ +#define XCHAL_HAVE_BALL 0 +#define XCHAL_HAVE_BALLAP 0 +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_CONNX_B10 0 /* ConnX B10 pkg*/ +#define XCHAL_HAVE_CONNX_B20 0 /* ConnX B20 pkg*/ +#define XCHAL_HAVE_CONNX_B_DP_VFPU 0 /* Double-precision Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_DPX_VFPU 0 /* Double-precision Vector Floating-point option on FP Machine*/ +#define XCHAL_HAVE_CONNX_B_SP_VFPU 0 /* Single-precision Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_SPX_VFPU 0 /* Single-precision Extended Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_HP_VFPU 0 /* Half-precision Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_HPX_VFPU 0 /* Half-precision Extended Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_32B_MAC 0 /* 32-bit vector MAC (real and complex), FIR & FFT option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_VITERBI 0 /* Viterbi option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_TURBO 0 /* Turbo option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_LDPC 0 /* LDPC option on ConnX B10 & B20 */ +#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */ +#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ + +#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */ +#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ +#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, Q6, Q7, Q8 or v331/v341 */ +#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */ +#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */ +#define XCHAL_HAVE_VISION_DP_VFPU 0 /* dp_vfpu option on Vision Q7/Q8 */ +#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6/Q6/Q7 */ +#define XCHAL_HAVE_VISION_SP_VFPU_2XFMAC 0 /* sp_vfpu_2xfma option on Vision Q7 */ +#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6/Q6 */ +#define XCHAL_HAVE_VISION_HP_VFPU_2XFMAC 0 /* hp_vfpu_2xfma option on Vision Q7 */ + +#define XCHAL_HAVE_VISIONC 0 /* Vision C */ + +#define XCHAL_HAVE_XNNE 0 /* XNNE */ + +/* Radar FFT */ +#define XCHAL_HAVE_RADAR_FFT 0 /* Radar FFT eTIE module */ + + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_LOADSTORE_UNITS 2 /* load/store units */ +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 32 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 16 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 16 /* data width in bytes */ +#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay + (1 = 5-stage, 2 = 7-stage) */ +#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ +#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ +#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ + +#define XCHAL_UNIFIED_LOADSTORE 0 + +#define XCHAL_SW_VERSION 1503000 /* sw version of this header */ +#define XCHAL_SW_VERSION_MAJOR 15000 /* major ver# of sw */ +#define XCHAL_SW_VERSION_MINOR 3 /* minor ver# of sw */ +#define XCHAL_SW_VERSION_MICRO 0 /* micro ver# of sw */ +#define XCHAL_SW_MINOR_VERSION 1503000 /* with zeroed micro */ +#define XCHAL_SW_MICRO_VERSION 1503000 + +#define XCHAL_CORE_ID "HiFi5_MPU_lock_2023_11" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_BUILD_UNIQUE_ID 0x000B68B4 /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC003B286 /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x2A09D04B /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX7.1.8" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2810 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 8 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION_MICRO 0 /* subdot ver# of targeted hw */ +#define XCHAL_HW_VERSION 281080 /* major*100+(major<2810 ? minor : minor*10+micro) */ +#define XCHAL_HW_REL_LX7 1 +#define XCHAL_HW_REL_LX7_1 1 +#define XCHAL_HW_REL_LX7_1_8 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2810 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 8 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MICRO 0 /* micro v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 281080 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2810 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 8 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MICRO 0 /* micro v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 281080 /* latest targeted hw */ + +/* Config is enabled for functional safety: */ +#define XCHAL_HAVE_FUNC_SAFETY 0 + +/* Config is enabled for secure operation: */ +#define XCHAL_HAVE_SECURE 0 + +#define XCHAL_HAVE_APB 0 + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 7 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 7 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 65536 /* I-cache size in bytes or 0 */ +#define XCHAL_ICACHE_SIZE_LOG2 16 +#define XCHAL_DCACHE_SIZE 131072 /* D-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE_LOG2 17 + +#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + + +#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ + +#define XCHAL_HAVE_PREFETCH_L1 1 /* prefetch to L1 cache */ +#define XCHAL_PREFETCH_CASTOUT_LINES 2 /* dcache pref. castout bufsz */ +#define XCHAL_PREFETCH_ENTRIES 16 /* cache prefetch entries */ + + +#define XCHAL_HAVE_DCACHE_PREFETCH 1 +#define XCHAL_HAVE_DCACHE_PREFETCH_L1 1 /* prefetch to L1 cache */ +#define XCHAL_DCACHE_PREFETCH_ENTRIES 16 /* cache prefetch entries */ + +#define XCHAL_HAVE_ICACHE_PREFETCH 0 +#define XCHAL_HAVE_ICACHE_PREFETCH_L1 0 /* prefetch to L1 cache */ +#define XCHAL_ICACHE_PREFETCH_ENTRIES 0 /* cache prefetch entries */ + +#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ +#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ +#define XCHAL_HAVE_CME_DOWNGRADES 0 +#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ +#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ +#define XCHAL_HAVE_ICACHE_DYN_WAYS 1 /* Icache dynamic way support */ +#define XCHAL_HAVE_DCACHE_DYN_WAYS 1 /* Dcache dynamic way support */ +#define XCHAL_HAVE_ICACHE_DYN_ENABLE 1 /* Icache enabled via MEMCTL */ +#define XCHAL_HAVE_DCACHE_DYN_ENABLE 1 /* Dcache enabled via MEMCTL */ + +#define XCHAL_L1SCACHE_SIZE 0 +#define XCHAL_L1SCACHE_SIZE_LOG2 0 +#define XCHAL_L1SCACHE_WAYS 1 +#define XCHAL_L1SCACHE_WAYS_LOG2 0 +#define XCHAL_L1SCACHE_ACCESS_SIZE 0 +#define XCHAL_L1SCACHE_BANKS 1 + +#define XCHAL_L1VCACHE_SIZE 0 + +#define XCHAL_HAVE_L2 0 /* L2 memory controller */ +#define XCHAL_HAVE_L2_CACHE 0 /* L2 cache configured */ +#define XCHAL_HAVE_L2_RAM 0 /* L2 cache configured */ +#define XCHAL_NUM_CORES_IN_CLUSTER 0 + +/* PRID_ID macros are for internal use only ... subject to removal */ +#define PRID_ID_SHIFT 0 +#define PRID_ID_BITS 4 +#define PRID_ID_MASK 0x0000000F + +/* This one is a form of caching, though not architecturally visible: */ +#define XCHAL_HAVE_BRANCH_PREDICTION 0 /* branch [target] prediction */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound bus present */ + +#define XCHAL_HAVE_AXI 1 /* AXI bus */ +#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */ +#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ + +#define XCHAL_HAVE_PIF_WR_RESP 1 /* pif write response */ +#define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 7 +#define XCHAL_DCACHE_SETWIDTH 8 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 4 +#define XCHAL_ICACHE_WAYS_LOG2 2 +#define XCHAL_DCACHE_WAYS 4 +#define XCHAL_DCACHE_WAYS_LOG2 2 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 1 +#define XCHAL_DCACHE_LINE_LOCKABLE 1 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 +#define XCHAL_ICACHE_ECC_WIDTH 4 +#define XCHAL_DCACHE_ECC_WIDTH 1 + +/* Cache access size in bytes (affects operation of SICW instruction): */ +#define XCHAL_ICACHE_ACCESS_SIZE 16 +#define XCHAL_DCACHE_ACCESS_SIZE 16 + +#define XCHAL_DCACHE_BANKS 2 /* number of banks */ + +/* The number of Cache lines associated with a single cache tag */ +#define XCHAL_DCACHE_LINES_PER_TAG_LOG2 0 + +/* Number of encoded cache attr bits (see for decoded bits): */ + +/* Extended memory attributes supported. */ +#define XCHAL_HAVE_EXT_CA 0 + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ +#define XCHAL_HAVE_IRAMCFG 0 /* IRAMxCFG register present */ +#define XCHAL_HAVE_DRAMCFG 0 /* DRAMxCFG register present */ + +/* Instruction RAM 0: */ +#define XCHAL_INSTRAM0_VADDR 0x4FFC0000 /* virtual address */ +#define XCHAL_INSTRAM0_PADDR 0x4FFC0000 /* physical address */ +#define XCHAL_INSTRAM0_SIZE 262144 /* size in bytes */ +#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_HAVE_INSTRAM0 1 +#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* Data RAM 0: */ +#define XCHAL_DATARAM0_VADDR 0x4FF90000 /* virtual address */ +#define XCHAL_DATARAM0_PADDR 0x4FF90000 /* physical address */ +#define XCHAL_DATARAM0_SIZE 65536 /* size in bytes */ +#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM0_BANKS 2 /* number of banks */ +#define XCHAL_HAVE_DATARAM0 1 +#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* Data RAM 1: */ +#define XCHAL_DATARAM1_VADDR 0x4FFA0000 /* virtual address */ +#define XCHAL_DATARAM1_PADDR 0x4FFA0000 /* physical address */ +#define XCHAL_DATARAM1_SIZE 131072 /* size in bytes */ +#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM1_BANKS 2 /* number of banks */ +#define XCHAL_HAVE_DATARAM1 1 +#define XCHAL_DATARAM1_HAVE_IDMA 0 /* idma supported by this local memory */ + +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ + + +/*---------------------------------------------------------------------- + IDMA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_IDMA 0 + + + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 5 /* number of interrupt levels + (not including level zero) */ +#define XCHAL_INTERRUPT_RANGE 32 /* range of interrupt numbers */ + + +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x040000FF +#define XCHAL_INTLEVEL2_MASK 0xA800FF00 +#define XCHAL_INTLEVEL3_MASK 0x518F0000 +#define XCHAL_INTLEVEL4_MASK 0x00700000 +#define XCHAL_INTLEVEL5_MASK 0x00000000 +#define XCHAL_INTLEVEL6_MASK 0x02000000 +#define XCHAL_INTLEVEL7_MASK 0x00000000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x040000FF +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0xAC00FFFF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0xFD8FFFFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0xFDFFFFFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFDFFFFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFFFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 1 +#define XCHAL_INT2_LEVEL 1 +#define XCHAL_INT3_LEVEL 1 +#define XCHAL_INT4_LEVEL 1 +#define XCHAL_INT5_LEVEL 1 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 1 +#define XCHAL_INT8_LEVEL 2 +#define XCHAL_INT9_LEVEL 2 +#define XCHAL_INT10_LEVEL 2 +#define XCHAL_INT11_LEVEL 2 +#define XCHAL_INT12_LEVEL 2 +#define XCHAL_INT13_LEVEL 2 +#define XCHAL_INT14_LEVEL 2 +#define XCHAL_INT15_LEVEL 2 +#define XCHAL_INT16_LEVEL 3 +#define XCHAL_INT17_LEVEL 3 +#define XCHAL_INT18_LEVEL 3 +#define XCHAL_INT19_LEVEL 3 +#define XCHAL_INT20_LEVEL 4 +#define XCHAL_INT21_LEVEL 4 +#define XCHAL_INT22_LEVEL 4 +#define XCHAL_INT23_LEVEL 3 +#define XCHAL_INT24_LEVEL 3 +#define XCHAL_INT25_LEVEL 6 +#define XCHAL_INT26_LEVEL 1 +#define XCHAL_INT27_LEVEL 2 +#define XCHAL_INT28_LEVEL 3 +#define XCHAL_INT29_LEVEL 2 +#define XCHAL_INT30_LEVEL 3 +#define XCHAL_INT31_LEVEL 2 +#define XCHAL_DEBUGLEVEL 5 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 6 /* NMI "level" (for use with + EXCSAVE/EPS/EPC_n, RFI n) */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT25_TYPE XTHAL_INTTYPE_NMI +#define XCHAL_INT26_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT27_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT28_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT29_TYPE XTHAL_INTTYPE_PROFILING +#define XCHAL_INT30_TYPE XTHAL_INTTYPE_WRITE_ERROR +#define XCHAL_INT31_TYPE XTHAL_INTTYPE_SOFTWARE + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x007FFFFF +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x01800000 +#define XCHAL_INTTYPE_MASK_NMI 0x02000000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x80000000 +#define XCHAL_INTTYPE_MASK_TIMER 0x1C000000 +#define XCHAL_INTTYPE_MASK_ETIE 0x00000000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x40000000 +#define XCHAL_INTTYPE_MASK_DBG_REQUEST 0x00000000 +#define XCHAL_INTTYPE_MASK_BREAKIN 0x00000000 +#define XCHAL_INTTYPE_MASK_TRAX 0x00000000 +#define XCHAL_INTTYPE_MASK_PROFILING 0x20000000 +#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000 +#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_L2_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_L2_STATUS 0x00000000 +#define XCHAL_INTTYPE_MASK_COR_ECC_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_WWDT 0x00000000 +#define XCHAL_INTTYPE_MASK_FXLK 0x00000000 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 26 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 27 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT 28 /* CCOMPARE2 */ +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 25 +#define XCHAL_WRITE_ERROR_INTERRUPT 30 +#define XCHAL_PROFILING_INTERRUPT 29 + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +#define XCHAL_INTLEVEL6_NUM 25 +/* (There are many interrupts each at level(s) 1, 2, 3, 4.) */ + + +/* + * External interrupt mapping. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ +#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ +#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ +#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ +#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 6 /* (intlevel 1) */ +#define XCHAL_EXTINT7_NUM 7 /* (intlevel 1) */ +#define XCHAL_EXTINT8_NUM 8 /* (intlevel 2) */ +#define XCHAL_EXTINT9_NUM 9 /* (intlevel 2) */ +#define XCHAL_EXTINT10_NUM 10 /* (intlevel 2) */ +#define XCHAL_EXTINT11_NUM 11 /* (intlevel 2) */ +#define XCHAL_EXTINT12_NUM 12 /* (intlevel 2) */ +#define XCHAL_EXTINT13_NUM 13 /* (intlevel 2) */ +#define XCHAL_EXTINT14_NUM 14 /* (intlevel 2) */ +#define XCHAL_EXTINT15_NUM 15 /* (intlevel 2) */ +#define XCHAL_EXTINT16_NUM 16 /* (intlevel 3) */ +#define XCHAL_EXTINT17_NUM 17 /* (intlevel 3) */ +#define XCHAL_EXTINT18_NUM 18 /* (intlevel 3) */ +#define XCHAL_EXTINT19_NUM 19 /* (intlevel 3) */ +#define XCHAL_EXTINT20_NUM 20 /* (intlevel 4) */ +#define XCHAL_EXTINT21_NUM 21 /* (intlevel 4) */ +#define XCHAL_EXTINT22_NUM 22 /* (intlevel 4) */ +#define XCHAL_EXTINT23_NUM 23 /* (intlevel 3) */ +#define XCHAL_EXTINT24_NUM 24 /* (intlevel 3) */ +#define XCHAL_EXTINT25_NUM 25 /* (intlevel 6) */ +/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ +#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ +#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ +#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ +#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ +#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ +#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ +#define XCHAL_INT6_EXTNUM 6 /* (intlevel 1) */ +#define XCHAL_INT7_EXTNUM 7 /* (intlevel 1) */ +#define XCHAL_INT8_EXTNUM 8 /* (intlevel 2) */ +#define XCHAL_INT9_EXTNUM 9 /* (intlevel 2) */ +#define XCHAL_INT10_EXTNUM 10 /* (intlevel 2) */ +#define XCHAL_INT11_EXTNUM 11 /* (intlevel 2) */ +#define XCHAL_INT12_EXTNUM 12 /* (intlevel 2) */ +#define XCHAL_INT13_EXTNUM 13 /* (intlevel 2) */ +#define XCHAL_INT14_EXTNUM 14 /* (intlevel 2) */ +#define XCHAL_INT15_EXTNUM 15 /* (intlevel 2) */ +#define XCHAL_INT16_EXTNUM 16 /* (intlevel 3) */ +#define XCHAL_INT17_EXTNUM 17 /* (intlevel 3) */ +#define XCHAL_INT18_EXTNUM 18 /* (intlevel 3) */ +#define XCHAL_INT19_EXTNUM 19 /* (intlevel 3) */ +#define XCHAL_INT20_EXTNUM 20 /* (intlevel 4) */ +#define XCHAL_INT21_EXTNUM 21 /* (intlevel 4) */ +#define XCHAL_INT22_EXTNUM 22 /* (intlevel 4) */ +#define XCHAL_INT23_EXTNUM 23 /* (intlevel 3) */ +#define XCHAL_INT24_EXTNUM 24 /* (intlevel 3) */ +#define XCHAL_INT25_EXTNUM 25 /* (intlevel 6) */ + +#define XCHAL_HAVE_ISB 0 /* No ISB */ +#define XCHAL_ISB_VADDR 0 /* N/A */ +#define XCHAL_HAVE_ITB 0 /* No ITB */ +#define XCHAL_ITB_VADDR 0 /* N/A */ + +#define XCHAL_HAVE_KSL 0 /* Kernel Stack Limit */ +#define XCHAL_HAVE_ISL 0 /* Interrupt Stack Limit */ +#define XCHAL_HAVE_PSL 0 /* Pageable Stack Limit */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (until T1050) + 2 == XEA2 (LX) + 3 == XEA3 (NX) + 0 == XEA5 (RNX) */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEA3 0 /* Exception Architecture 3 */ +#define XCHAL_HAVE_XEA5 0 /* Exception Architecture 5 */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_IMPRECISE_EXCEPTIONS 0 /* imprecise exception option */ +#define XCHAL_EXCCAUSE_NUM 64 /* Number of exceptions */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0x4FFC0400 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x4FFC0400 +#define XCHAL_RESET_VECBASE_OVERLAP 0 /* UNUSED */ + +#define XCHAL_RESET_VECTOR0_VADDR 0x4FFC0000 +#define XCHAL_RESET_VECTOR0_PADDR 0x4FFC0000 +#define XCHAL_RESET_VECTOR1_VADDR 0x4FFC0680 +#define XCHAL_RESET_VECTOR1_PADDR 0x4FFC0680 +#define XCHAL_RESET_VECTOR_VADDR XCHAL_RESET_VECTOR1_VADDR +#define XCHAL_RESET_VECTOR_PADDR XCHAL_RESET_VECTOR1_PADDR +#define XCHAL_USER_VECOFS 0x0000023C +#define XCHAL_USER_VECTOR_VADDR 0x4FFC063C +#define XCHAL_USER_VECTOR_PADDR 0x4FFC063C +#define XCHAL_KERNEL_VECOFS 0x0000021C +#define XCHAL_KERNEL_VECTOR_VADDR 0x4FFC061C +#define XCHAL_KERNEL_VECTOR_PADDR 0x4FFC061C +#define XCHAL_DOUBLEEXC_VECOFS 0x0000025C +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x4FFC065C +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x4FFC065C +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x4FFC0400 +#define XCHAL_WINDOW_VECTORS_PADDR 0x4FFC0400 +#define XCHAL_INTLEVEL2_VECOFS 0x0000017C +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x4FFC057C +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x4FFC057C +#define XCHAL_INTLEVEL3_VECOFS 0x0000019C +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x4FFC059C +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x4FFC059C +#define XCHAL_INTLEVEL4_VECOFS 0x000001BC +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x4FFC05BC +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x4FFC05BC +#define XCHAL_INTLEVEL5_VECOFS 0x000001DC +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x4FFC05DC +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x4FFC05DC +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL5_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL5_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL5_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x000001FC +#define XCHAL_NMI_VECTOR_VADDR 0x4FFC05FC +#define XCHAL_NMI_VECTOR_PADDR 0x4FFC05FC +#define XCHAL_INTLEVEL6_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL6_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL6_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG MODULE + ----------------------------------------------------------------------*/ + +/* Misc */ +#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ +#define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */ +#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ + +/* On-Chip Debug (OCD) */ +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ +#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ + +/* TRAX (in core) */ +#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ +#define XCHAL_TRAX_MEM_SIZE 4096 /* TRAX memory size in bytes */ +#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ +#define XCHAL_TRAX_ATB_WIDTH 32 /* ATB width (bits), 0=no ATB */ +#define XCHAL_TRAX_TIME_WIDTH 64 /* timestamp bitwidth, 0=none */ + +/* Perf counters */ +#define XCHAL_NUM_PERF_COUNTERS 8 /* performance counters */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 0 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */ +#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ + +/* If none of the above last 5 are set, it's a custom TLB configuration. */ + +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ + +/*---------------------------------------------------------------------- + MPU + ----------------------------------------------------------------------*/ +#define XCHAL_HAVE_MPU 1 +#define XCHAL_MPU_ENTRIES 32 +#define XCHAL_MPU_LOCK 1 + +#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ +#define XCHAL_MPU_BACKGROUND_ENTRIES 2 /* number of entries in bg map*/ +#define XCHAL_MPU_BG_CACHEADRDIS 0xFF /* default CACHEADRDIS for bg */ + +#define XCHAL_MPU_ALIGN_BITS 7 +#define XCHAL_MPU_ALIGN 128 + +/*----------------------------------------------------------------------- + CSR Parity +------------------------------------------------------------------------*/ +#define XCHAL_HAVE_CSR_PARITY 0 + + +/*---------------------------------------------------------------------- + FLEX-LOCK +------------------------------------------------------------------------*/ + +#define XCHAL_HAVE_FXLK 0 + +/*---------------------------------------------------------------------- + WWDT (Windowed Watchdog Timer) +------------------------------------------------------------------------*/ +#define XCHAL_HAVE_WWDT 0 +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* XTENSA_CORE_CONFIGURATION_H_ */ +